Commit | Line | Data |
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8b9bc460 | 1 | /** |
dfbc6fa3 AT |
2 | * Copyright (c) 2011 Samsung Electronics Co., Ltd. |
3 | * http://www.samsung.com | |
5b7d70c6 BD |
4 | * |
5 | * Copyright 2008 Openmoko, Inc. | |
6 | * Copyright 2008 Simtec Electronics | |
7 | * Ben Dooks <ben@simtec.co.uk> | |
8 | * http://armlinux.simtec.co.uk/ | |
9 | * | |
10 | * S3C USB2.0 High-speed / OtG driver | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License version 2 as | |
14 | * published by the Free Software Foundation. | |
8b9bc460 | 15 | */ |
5b7d70c6 BD |
16 | |
17 | #include <linux/kernel.h> | |
18 | #include <linux/module.h> | |
19 | #include <linux/spinlock.h> | |
20 | #include <linux/interrupt.h> | |
21 | #include <linux/platform_device.h> | |
22 | #include <linux/dma-mapping.h> | |
23 | #include <linux/debugfs.h> | |
7ad8096e | 24 | #include <linux/mutex.h> |
5b7d70c6 BD |
25 | #include <linux/seq_file.h> |
26 | #include <linux/delay.h> | |
27 | #include <linux/io.h> | |
5a0e3ad6 | 28 | #include <linux/slab.h> |
e50bf385 | 29 | #include <linux/clk.h> |
fc9a731e | 30 | #include <linux/regulator/consumer.h> |
c50f056c | 31 | #include <linux/of_platform.h> |
74084844 | 32 | #include <linux/phy/phy.h> |
5b7d70c6 BD |
33 | |
34 | #include <linux/usb/ch9.h> | |
35 | #include <linux/usb/gadget.h> | |
b2e587db | 36 | #include <linux/usb/phy.h> |
126625e1 | 37 | #include <linux/platform_data/s3c-hsotg.h> |
5b7d70c6 | 38 | |
f7c0b143 | 39 | #include "core.h" |
941fcce4 | 40 | #include "hw.h" |
5b7d70c6 BD |
41 | |
42 | /* conversion functions */ | |
43 | static inline struct s3c_hsotg_req *our_req(struct usb_request *req) | |
44 | { | |
45 | return container_of(req, struct s3c_hsotg_req, req); | |
46 | } | |
47 | ||
48 | static inline struct s3c_hsotg_ep *our_ep(struct usb_ep *ep) | |
49 | { | |
50 | return container_of(ep, struct s3c_hsotg_ep, ep); | |
51 | } | |
52 | ||
941fcce4 | 53 | static inline struct dwc2_hsotg *to_hsotg(struct usb_gadget *gadget) |
5b7d70c6 | 54 | { |
941fcce4 | 55 | return container_of(gadget, struct dwc2_hsotg, gadget); |
5b7d70c6 BD |
56 | } |
57 | ||
58 | static inline void __orr32(void __iomem *ptr, u32 val) | |
59 | { | |
60 | writel(readl(ptr) | val, ptr); | |
61 | } | |
62 | ||
63 | static inline void __bic32(void __iomem *ptr, u32 val) | |
64 | { | |
65 | writel(readl(ptr) & ~val, ptr); | |
66 | } | |
67 | ||
c6f5c050 MYK |
68 | static inline struct s3c_hsotg_ep *index_to_ep(struct dwc2_hsotg *hsotg, |
69 | u32 ep_index, u32 dir_in) | |
70 | { | |
71 | if (dir_in) | |
72 | return hsotg->eps_in[ep_index]; | |
73 | else | |
74 | return hsotg->eps_out[ep_index]; | |
75 | } | |
76 | ||
997f4f81 | 77 | /* forward declaration of functions */ |
941fcce4 | 78 | static void s3c_hsotg_dump(struct dwc2_hsotg *hsotg); |
5b7d70c6 BD |
79 | |
80 | /** | |
81 | * using_dma - return the DMA status of the driver. | |
82 | * @hsotg: The driver state. | |
83 | * | |
84 | * Return true if we're using DMA. | |
85 | * | |
86 | * Currently, we have the DMA support code worked into everywhere | |
87 | * that needs it, but the AMBA DMA implementation in the hardware can | |
88 | * only DMA from 32bit aligned addresses. This means that gadgets such | |
89 | * as the CDC Ethernet cannot work as they often pass packets which are | |
90 | * not 32bit aligned. | |
91 | * | |
92 | * Unfortunately the choice to use DMA or not is global to the controller | |
93 | * and seems to be only settable when the controller is being put through | |
94 | * a core reset. This means we either need to fix the gadgets to take | |
95 | * account of DMA alignment, or add bounce buffers (yuerk). | |
96 | * | |
edd74be8 | 97 | * g_using_dma is set depending on dts flag. |
5b7d70c6 | 98 | */ |
941fcce4 | 99 | static inline bool using_dma(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 100 | { |
edd74be8 | 101 | return hsotg->g_using_dma; |
5b7d70c6 BD |
102 | } |
103 | ||
104 | /** | |
105 | * s3c_hsotg_en_gsint - enable one or more of the general interrupt | |
106 | * @hsotg: The device state | |
107 | * @ints: A bitmask of the interrupts to enable | |
108 | */ | |
941fcce4 | 109 | static void s3c_hsotg_en_gsint(struct dwc2_hsotg *hsotg, u32 ints) |
5b7d70c6 | 110 | { |
94cb8fd6 | 111 | u32 gsintmsk = readl(hsotg->regs + GINTMSK); |
5b7d70c6 BD |
112 | u32 new_gsintmsk; |
113 | ||
114 | new_gsintmsk = gsintmsk | ints; | |
115 | ||
116 | if (new_gsintmsk != gsintmsk) { | |
117 | dev_dbg(hsotg->dev, "gsintmsk now 0x%08x\n", new_gsintmsk); | |
94cb8fd6 | 118 | writel(new_gsintmsk, hsotg->regs + GINTMSK); |
5b7d70c6 BD |
119 | } |
120 | } | |
121 | ||
122 | /** | |
123 | * s3c_hsotg_disable_gsint - disable one or more of the general interrupt | |
124 | * @hsotg: The device state | |
125 | * @ints: A bitmask of the interrupts to enable | |
126 | */ | |
941fcce4 | 127 | static void s3c_hsotg_disable_gsint(struct dwc2_hsotg *hsotg, u32 ints) |
5b7d70c6 | 128 | { |
94cb8fd6 | 129 | u32 gsintmsk = readl(hsotg->regs + GINTMSK); |
5b7d70c6 BD |
130 | u32 new_gsintmsk; |
131 | ||
132 | new_gsintmsk = gsintmsk & ~ints; | |
133 | ||
134 | if (new_gsintmsk != gsintmsk) | |
94cb8fd6 | 135 | writel(new_gsintmsk, hsotg->regs + GINTMSK); |
5b7d70c6 BD |
136 | } |
137 | ||
138 | /** | |
139 | * s3c_hsotg_ctrl_epint - enable/disable an endpoint irq | |
140 | * @hsotg: The device state | |
141 | * @ep: The endpoint index | |
142 | * @dir_in: True if direction is in. | |
143 | * @en: The enable value, true to enable | |
144 | * | |
145 | * Set or clear the mask for an individual endpoint's interrupt | |
146 | * request. | |
147 | */ | |
941fcce4 | 148 | static void s3c_hsotg_ctrl_epint(struct dwc2_hsotg *hsotg, |
5b7d70c6 BD |
149 | unsigned int ep, unsigned int dir_in, |
150 | unsigned int en) | |
151 | { | |
152 | unsigned long flags; | |
153 | u32 bit = 1 << ep; | |
154 | u32 daint; | |
155 | ||
156 | if (!dir_in) | |
157 | bit <<= 16; | |
158 | ||
159 | local_irq_save(flags); | |
94cb8fd6 | 160 | daint = readl(hsotg->regs + DAINTMSK); |
5b7d70c6 BD |
161 | if (en) |
162 | daint |= bit; | |
163 | else | |
164 | daint &= ~bit; | |
94cb8fd6 | 165 | writel(daint, hsotg->regs + DAINTMSK); |
5b7d70c6 BD |
166 | local_irq_restore(flags); |
167 | } | |
168 | ||
169 | /** | |
170 | * s3c_hsotg_init_fifo - initialise non-periodic FIFOs | |
171 | * @hsotg: The device instance. | |
172 | */ | |
941fcce4 | 173 | static void s3c_hsotg_init_fifo(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 174 | { |
0f002d20 BD |
175 | unsigned int ep; |
176 | unsigned int addr; | |
1703a6d3 | 177 | int timeout; |
0f002d20 BD |
178 | u32 val; |
179 | ||
0a176279 GH |
180 | /* set RX/NPTX FIFO sizes */ |
181 | writel(hsotg->g_rx_fifo_sz, hsotg->regs + GRXFSIZ); | |
182 | writel((hsotg->g_rx_fifo_sz << FIFOSIZE_STARTADDR_SHIFT) | | |
183 | (hsotg->g_np_g_tx_fifo_sz << FIFOSIZE_DEPTH_SHIFT), | |
184 | hsotg->regs + GNPTXFSIZ); | |
0f002d20 | 185 | |
8b9bc460 LM |
186 | /* |
187 | * arange all the rest of the TX FIFOs, as some versions of this | |
0f002d20 BD |
188 | * block have overlapping default addresses. This also ensures |
189 | * that if the settings have been changed, then they are set to | |
8b9bc460 LM |
190 | * known values. |
191 | */ | |
0f002d20 BD |
192 | |
193 | /* start at the end of the GNPTXFSIZ, rounded up */ | |
0a176279 | 194 | addr = hsotg->g_rx_fifo_sz + hsotg->g_np_g_tx_fifo_sz; |
0f002d20 | 195 | |
8b9bc460 | 196 | /* |
0a176279 | 197 | * Configure fifos sizes from provided configuration and assign |
b203d0a2 RB |
198 | * them to endpoints dynamically according to maxpacket size value of |
199 | * given endpoint. | |
8b9bc460 | 200 | */ |
0a176279 GH |
201 | for (ep = 1; ep < MAX_EPS_CHANNELS; ep++) { |
202 | if (!hsotg->g_tx_fifo_sz[ep]) | |
203 | continue; | |
0f002d20 | 204 | val = addr; |
0a176279 GH |
205 | val |= hsotg->g_tx_fifo_sz[ep] << FIFOSIZE_DEPTH_SHIFT; |
206 | WARN_ONCE(addr + hsotg->g_tx_fifo_sz[ep] > hsotg->fifo_mem, | |
cff9eb75 | 207 | "insufficient fifo memory"); |
0a176279 | 208 | addr += hsotg->g_tx_fifo_sz[ep]; |
0f002d20 | 209 | |
47a1685f | 210 | writel(val, hsotg->regs + DPTXFSIZN(ep)); |
0f002d20 | 211 | } |
1703a6d3 | 212 | |
8b9bc460 LM |
213 | /* |
214 | * according to p428 of the design guide, we need to ensure that | |
215 | * all fifos are flushed before continuing | |
216 | */ | |
1703a6d3 | 217 | |
47a1685f DN |
218 | writel(GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH | |
219 | GRSTCTL_RXFFLSH, hsotg->regs + GRSTCTL); | |
1703a6d3 BD |
220 | |
221 | /* wait until the fifos are both flushed */ | |
222 | timeout = 100; | |
223 | while (1) { | |
94cb8fd6 | 224 | val = readl(hsotg->regs + GRSTCTL); |
1703a6d3 | 225 | |
47a1685f | 226 | if ((val & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH)) == 0) |
1703a6d3 BD |
227 | break; |
228 | ||
229 | if (--timeout == 0) { | |
230 | dev_err(hsotg->dev, | |
231 | "%s: timeout flushing fifos (GRSTCTL=%08x)\n", | |
232 | __func__, val); | |
233 | } | |
234 | ||
235 | udelay(1); | |
236 | } | |
237 | ||
238 | dev_dbg(hsotg->dev, "FIFOs reset, timeout at %d\n", timeout); | |
5b7d70c6 BD |
239 | } |
240 | ||
241 | /** | |
242 | * @ep: USB endpoint to allocate request for. | |
243 | * @flags: Allocation flags | |
244 | * | |
245 | * Allocate a new USB request structure appropriate for the specified endpoint | |
246 | */ | |
0978f8c5 MB |
247 | static struct usb_request *s3c_hsotg_ep_alloc_request(struct usb_ep *ep, |
248 | gfp_t flags) | |
5b7d70c6 BD |
249 | { |
250 | struct s3c_hsotg_req *req; | |
251 | ||
252 | req = kzalloc(sizeof(struct s3c_hsotg_req), flags); | |
253 | if (!req) | |
254 | return NULL; | |
255 | ||
256 | INIT_LIST_HEAD(&req->queue); | |
257 | ||
5b7d70c6 BD |
258 | return &req->req; |
259 | } | |
260 | ||
261 | /** | |
262 | * is_ep_periodic - return true if the endpoint is in periodic mode. | |
263 | * @hs_ep: The endpoint to query. | |
264 | * | |
265 | * Returns true if the endpoint is in periodic mode, meaning it is being | |
266 | * used for an Interrupt or ISO transfer. | |
267 | */ | |
268 | static inline int is_ep_periodic(struct s3c_hsotg_ep *hs_ep) | |
269 | { | |
270 | return hs_ep->periodic; | |
271 | } | |
272 | ||
273 | /** | |
274 | * s3c_hsotg_unmap_dma - unmap the DMA memory being used for the request | |
275 | * @hsotg: The device state. | |
276 | * @hs_ep: The endpoint for the request | |
277 | * @hs_req: The request being processed. | |
278 | * | |
279 | * This is the reverse of s3c_hsotg_map_dma(), called for the completion | |
280 | * of a request to ensure the buffer is ready for access by the caller. | |
8b9bc460 | 281 | */ |
941fcce4 | 282 | static void s3c_hsotg_unmap_dma(struct dwc2_hsotg *hsotg, |
5b7d70c6 BD |
283 | struct s3c_hsotg_ep *hs_ep, |
284 | struct s3c_hsotg_req *hs_req) | |
285 | { | |
286 | struct usb_request *req = &hs_req->req; | |
5b7d70c6 BD |
287 | |
288 | /* ignore this if we're not moving any data */ | |
289 | if (hs_req->req.length == 0) | |
290 | return; | |
291 | ||
17d966a3 | 292 | usb_gadget_unmap_request(&hsotg->gadget, req, hs_ep->dir_in); |
5b7d70c6 BD |
293 | } |
294 | ||
295 | /** | |
296 | * s3c_hsotg_write_fifo - write packet Data to the TxFIFO | |
297 | * @hsotg: The controller state. | |
298 | * @hs_ep: The endpoint we're going to write for. | |
299 | * @hs_req: The request to write data for. | |
300 | * | |
301 | * This is called when the TxFIFO has some space in it to hold a new | |
302 | * transmission and we have something to give it. The actual setup of | |
303 | * the data size is done elsewhere, so all we have to do is to actually | |
304 | * write the data. | |
305 | * | |
306 | * The return value is zero if there is more space (or nothing was done) | |
307 | * otherwise -ENOSPC is returned if the FIFO space was used up. | |
308 | * | |
309 | * This routine is only needed for PIO | |
8b9bc460 | 310 | */ |
941fcce4 | 311 | static int s3c_hsotg_write_fifo(struct dwc2_hsotg *hsotg, |
5b7d70c6 BD |
312 | struct s3c_hsotg_ep *hs_ep, |
313 | struct s3c_hsotg_req *hs_req) | |
314 | { | |
315 | bool periodic = is_ep_periodic(hs_ep); | |
94cb8fd6 | 316 | u32 gnptxsts = readl(hsotg->regs + GNPTXSTS); |
5b7d70c6 BD |
317 | int buf_pos = hs_req->req.actual; |
318 | int to_write = hs_ep->size_loaded; | |
319 | void *data; | |
320 | int can_write; | |
321 | int pkt_round; | |
4fca54aa | 322 | int max_transfer; |
5b7d70c6 BD |
323 | |
324 | to_write -= (buf_pos - hs_ep->last_load); | |
325 | ||
326 | /* if there's nothing to write, get out early */ | |
327 | if (to_write == 0) | |
328 | return 0; | |
329 | ||
10aebc77 | 330 | if (periodic && !hsotg->dedicated_fifos) { |
94cb8fd6 | 331 | u32 epsize = readl(hsotg->regs + DIEPTSIZ(hs_ep->index)); |
5b7d70c6 BD |
332 | int size_left; |
333 | int size_done; | |
334 | ||
8b9bc460 LM |
335 | /* |
336 | * work out how much data was loaded so we can calculate | |
337 | * how much data is left in the fifo. | |
338 | */ | |
5b7d70c6 | 339 | |
47a1685f | 340 | size_left = DXEPTSIZ_XFERSIZE_GET(epsize); |
5b7d70c6 | 341 | |
8b9bc460 LM |
342 | /* |
343 | * if shared fifo, we cannot write anything until the | |
e7a9ff54 BD |
344 | * previous data has been completely sent. |
345 | */ | |
346 | if (hs_ep->fifo_load != 0) { | |
47a1685f | 347 | s3c_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP); |
e7a9ff54 BD |
348 | return -ENOSPC; |
349 | } | |
350 | ||
5b7d70c6 BD |
351 | dev_dbg(hsotg->dev, "%s: left=%d, load=%d, fifo=%d, size %d\n", |
352 | __func__, size_left, | |
353 | hs_ep->size_loaded, hs_ep->fifo_load, hs_ep->fifo_size); | |
354 | ||
355 | /* how much of the data has moved */ | |
356 | size_done = hs_ep->size_loaded - size_left; | |
357 | ||
358 | /* how much data is left in the fifo */ | |
359 | can_write = hs_ep->fifo_load - size_done; | |
360 | dev_dbg(hsotg->dev, "%s: => can_write1=%d\n", | |
361 | __func__, can_write); | |
362 | ||
363 | can_write = hs_ep->fifo_size - can_write; | |
364 | dev_dbg(hsotg->dev, "%s: => can_write2=%d\n", | |
365 | __func__, can_write); | |
366 | ||
367 | if (can_write <= 0) { | |
47a1685f | 368 | s3c_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP); |
5b7d70c6 BD |
369 | return -ENOSPC; |
370 | } | |
10aebc77 | 371 | } else if (hsotg->dedicated_fifos && hs_ep->index != 0) { |
94cb8fd6 | 372 | can_write = readl(hsotg->regs + DTXFSTS(hs_ep->index)); |
10aebc77 BD |
373 | |
374 | can_write &= 0xffff; | |
375 | can_write *= 4; | |
5b7d70c6 | 376 | } else { |
47a1685f | 377 | if (GNPTXSTS_NP_TXQ_SPC_AVAIL_GET(gnptxsts) == 0) { |
5b7d70c6 BD |
378 | dev_dbg(hsotg->dev, |
379 | "%s: no queue slots available (0x%08x)\n", | |
380 | __func__, gnptxsts); | |
381 | ||
47a1685f | 382 | s3c_hsotg_en_gsint(hsotg, GINTSTS_NPTXFEMP); |
5b7d70c6 BD |
383 | return -ENOSPC; |
384 | } | |
385 | ||
47a1685f | 386 | can_write = GNPTXSTS_NP_TXF_SPC_AVAIL_GET(gnptxsts); |
679f9b7c | 387 | can_write *= 4; /* fifo size is in 32bit quantities. */ |
5b7d70c6 BD |
388 | } |
389 | ||
4fca54aa RB |
390 | max_transfer = hs_ep->ep.maxpacket * hs_ep->mc; |
391 | ||
392 | dev_dbg(hsotg->dev, "%s: GNPTXSTS=%08x, can=%d, to=%d, max_transfer %d\n", | |
393 | __func__, gnptxsts, can_write, to_write, max_transfer); | |
5b7d70c6 | 394 | |
8b9bc460 LM |
395 | /* |
396 | * limit to 512 bytes of data, it seems at least on the non-periodic | |
5b7d70c6 BD |
397 | * FIFO, requests of >512 cause the endpoint to get stuck with a |
398 | * fragment of the end of the transfer in it. | |
399 | */ | |
811f3303 | 400 | if (can_write > 512 && !periodic) |
5b7d70c6 BD |
401 | can_write = 512; |
402 | ||
8b9bc460 LM |
403 | /* |
404 | * limit the write to one max-packet size worth of data, but allow | |
03e10e5a | 405 | * the transfer to return that it did not run out of fifo space |
8b9bc460 LM |
406 | * doing it. |
407 | */ | |
4fca54aa RB |
408 | if (to_write > max_transfer) { |
409 | to_write = max_transfer; | |
03e10e5a | 410 | |
5cb2ff0c RB |
411 | /* it's needed only when we do not use dedicated fifos */ |
412 | if (!hsotg->dedicated_fifos) | |
413 | s3c_hsotg_en_gsint(hsotg, | |
47a1685f DN |
414 | periodic ? GINTSTS_PTXFEMP : |
415 | GINTSTS_NPTXFEMP); | |
03e10e5a BD |
416 | } |
417 | ||
5b7d70c6 BD |
418 | /* see if we can write data */ |
419 | ||
420 | if (to_write > can_write) { | |
421 | to_write = can_write; | |
4fca54aa | 422 | pkt_round = to_write % max_transfer; |
5b7d70c6 | 423 | |
8b9bc460 LM |
424 | /* |
425 | * Round the write down to an | |
5b7d70c6 BD |
426 | * exact number of packets. |
427 | * | |
428 | * Note, we do not currently check to see if we can ever | |
429 | * write a full packet or not to the FIFO. | |
430 | */ | |
431 | ||
432 | if (pkt_round) | |
433 | to_write -= pkt_round; | |
434 | ||
8b9bc460 LM |
435 | /* |
436 | * enable correct FIFO interrupt to alert us when there | |
437 | * is more room left. | |
438 | */ | |
5b7d70c6 | 439 | |
5cb2ff0c RB |
440 | /* it's needed only when we do not use dedicated fifos */ |
441 | if (!hsotg->dedicated_fifos) | |
442 | s3c_hsotg_en_gsint(hsotg, | |
47a1685f DN |
443 | periodic ? GINTSTS_PTXFEMP : |
444 | GINTSTS_NPTXFEMP); | |
5b7d70c6 BD |
445 | } |
446 | ||
447 | dev_dbg(hsotg->dev, "write %d/%d, can_write %d, done %d\n", | |
448 | to_write, hs_req->req.length, can_write, buf_pos); | |
449 | ||
450 | if (to_write <= 0) | |
451 | return -ENOSPC; | |
452 | ||
453 | hs_req->req.actual = buf_pos + to_write; | |
454 | hs_ep->total_data += to_write; | |
455 | ||
456 | if (periodic) | |
457 | hs_ep->fifo_load += to_write; | |
458 | ||
459 | to_write = DIV_ROUND_UP(to_write, 4); | |
460 | data = hs_req->req.buf + buf_pos; | |
461 | ||
1a7ed5be | 462 | iowrite32_rep(hsotg->regs + EPFIFO(hs_ep->index), data, to_write); |
5b7d70c6 BD |
463 | |
464 | return (to_write >= can_write) ? -ENOSPC : 0; | |
465 | } | |
466 | ||
467 | /** | |
468 | * get_ep_limit - get the maximum data legnth for this endpoint | |
469 | * @hs_ep: The endpoint | |
470 | * | |
471 | * Return the maximum data that can be queued in one go on a given endpoint | |
472 | * so that transfers that are too long can be split. | |
473 | */ | |
474 | static unsigned get_ep_limit(struct s3c_hsotg_ep *hs_ep) | |
475 | { | |
476 | int index = hs_ep->index; | |
477 | unsigned maxsize; | |
478 | unsigned maxpkt; | |
479 | ||
480 | if (index != 0) { | |
47a1685f DN |
481 | maxsize = DXEPTSIZ_XFERSIZE_LIMIT + 1; |
482 | maxpkt = DXEPTSIZ_PKTCNT_LIMIT + 1; | |
5b7d70c6 | 483 | } else { |
b05ca580 | 484 | maxsize = 64+64; |
66e5c643 | 485 | if (hs_ep->dir_in) |
47a1685f | 486 | maxpkt = DIEPTSIZ0_PKTCNT_LIMIT + 1; |
66e5c643 | 487 | else |
5b7d70c6 | 488 | maxpkt = 2; |
5b7d70c6 BD |
489 | } |
490 | ||
491 | /* we made the constant loading easier above by using +1 */ | |
492 | maxpkt--; | |
493 | maxsize--; | |
494 | ||
8b9bc460 LM |
495 | /* |
496 | * constrain by packet count if maxpkts*pktsize is greater | |
497 | * than the length register size. | |
498 | */ | |
5b7d70c6 BD |
499 | |
500 | if ((maxpkt * hs_ep->ep.maxpacket) < maxsize) | |
501 | maxsize = maxpkt * hs_ep->ep.maxpacket; | |
502 | ||
503 | return maxsize; | |
504 | } | |
505 | ||
506 | /** | |
507 | * s3c_hsotg_start_req - start a USB request from an endpoint's queue | |
508 | * @hsotg: The controller state. | |
509 | * @hs_ep: The endpoint to process a request for | |
510 | * @hs_req: The request to start. | |
511 | * @continuing: True if we are doing more for the current request. | |
512 | * | |
513 | * Start the given request running by setting the endpoint registers | |
514 | * appropriately, and writing any data to the FIFOs. | |
515 | */ | |
941fcce4 | 516 | static void s3c_hsotg_start_req(struct dwc2_hsotg *hsotg, |
5b7d70c6 BD |
517 | struct s3c_hsotg_ep *hs_ep, |
518 | struct s3c_hsotg_req *hs_req, | |
519 | bool continuing) | |
520 | { | |
521 | struct usb_request *ureq = &hs_req->req; | |
522 | int index = hs_ep->index; | |
523 | int dir_in = hs_ep->dir_in; | |
524 | u32 epctrl_reg; | |
525 | u32 epsize_reg; | |
526 | u32 epsize; | |
527 | u32 ctrl; | |
528 | unsigned length; | |
529 | unsigned packets; | |
530 | unsigned maxreq; | |
531 | ||
532 | if (index != 0) { | |
533 | if (hs_ep->req && !continuing) { | |
534 | dev_err(hsotg->dev, "%s: active request\n", __func__); | |
535 | WARN_ON(1); | |
536 | return; | |
537 | } else if (hs_ep->req != hs_req && continuing) { | |
538 | dev_err(hsotg->dev, | |
539 | "%s: continue different req\n", __func__); | |
540 | WARN_ON(1); | |
541 | return; | |
542 | } | |
543 | } | |
544 | ||
94cb8fd6 LM |
545 | epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index); |
546 | epsize_reg = dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index); | |
5b7d70c6 BD |
547 | |
548 | dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n", | |
549 | __func__, readl(hsotg->regs + epctrl_reg), index, | |
550 | hs_ep->dir_in ? "in" : "out"); | |
551 | ||
9c39ddc6 AT |
552 | /* If endpoint is stalled, we will restart request later */ |
553 | ctrl = readl(hsotg->regs + epctrl_reg); | |
554 | ||
47a1685f | 555 | if (ctrl & DXEPCTL_STALL) { |
9c39ddc6 AT |
556 | dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index); |
557 | return; | |
558 | } | |
559 | ||
5b7d70c6 | 560 | length = ureq->length - ureq->actual; |
71225bee LM |
561 | dev_dbg(hsotg->dev, "ureq->length:%d ureq->actual:%d\n", |
562 | ureq->length, ureq->actual); | |
5b7d70c6 BD |
563 | if (0) |
564 | dev_dbg(hsotg->dev, | |
0cc4cf6f | 565 | "REQ buf %p len %d dma %pad noi=%d zp=%d snok=%d\n", |
8b3bc14f | 566 | ureq->buf, length, &ureq->dma, |
5b7d70c6 BD |
567 | ureq->no_interrupt, ureq->zero, ureq->short_not_ok); |
568 | ||
569 | maxreq = get_ep_limit(hs_ep); | |
570 | if (length > maxreq) { | |
571 | int round = maxreq % hs_ep->ep.maxpacket; | |
572 | ||
573 | dev_dbg(hsotg->dev, "%s: length %d, max-req %d, r %d\n", | |
574 | __func__, length, maxreq, round); | |
575 | ||
576 | /* round down to multiple of packets */ | |
577 | if (round) | |
578 | maxreq -= round; | |
579 | ||
580 | length = maxreq; | |
581 | } | |
582 | ||
583 | if (length) | |
584 | packets = DIV_ROUND_UP(length, hs_ep->ep.maxpacket); | |
585 | else | |
586 | packets = 1; /* send one packet if length is zero. */ | |
587 | ||
4fca54aa RB |
588 | if (hs_ep->isochronous && length > (hs_ep->mc * hs_ep->ep.maxpacket)) { |
589 | dev_err(hsotg->dev, "req length > maxpacket*mc\n"); | |
590 | return; | |
591 | } | |
592 | ||
5b7d70c6 | 593 | if (dir_in && index != 0) |
4fca54aa | 594 | if (hs_ep->isochronous) |
47a1685f | 595 | epsize = DXEPTSIZ_MC(packets); |
4fca54aa | 596 | else |
47a1685f | 597 | epsize = DXEPTSIZ_MC(1); |
5b7d70c6 BD |
598 | else |
599 | epsize = 0; | |
600 | ||
601 | if (index != 0 && ureq->zero) { | |
8b9bc460 LM |
602 | /* |
603 | * test for the packets being exactly right for the | |
604 | * transfer | |
605 | */ | |
5b7d70c6 BD |
606 | |
607 | if (length == (packets * hs_ep->ep.maxpacket)) | |
608 | packets++; | |
609 | } | |
610 | ||
47a1685f DN |
611 | epsize |= DXEPTSIZ_PKTCNT(packets); |
612 | epsize |= DXEPTSIZ_XFERSIZE(length); | |
5b7d70c6 BD |
613 | |
614 | dev_dbg(hsotg->dev, "%s: %d@%d/%d, 0x%08x => 0x%08x\n", | |
615 | __func__, packets, length, ureq->length, epsize, epsize_reg); | |
616 | ||
617 | /* store the request as the current one we're doing */ | |
618 | hs_ep->req = hs_req; | |
619 | ||
620 | /* write size / packets */ | |
621 | writel(epsize, hsotg->regs + epsize_reg); | |
622 | ||
db1d8ba3 | 623 | if (using_dma(hsotg) && !continuing) { |
5b7d70c6 BD |
624 | unsigned int dma_reg; |
625 | ||
8b9bc460 LM |
626 | /* |
627 | * write DMA address to control register, buffer already | |
628 | * synced by s3c_hsotg_ep_queue(). | |
629 | */ | |
5b7d70c6 | 630 | |
94cb8fd6 | 631 | dma_reg = dir_in ? DIEPDMA(index) : DOEPDMA(index); |
5b7d70c6 BD |
632 | writel(ureq->dma, hsotg->regs + dma_reg); |
633 | ||
0cc4cf6f | 634 | dev_dbg(hsotg->dev, "%s: %pad => 0x%08x\n", |
8b3bc14f | 635 | __func__, &ureq->dma, dma_reg); |
5b7d70c6 BD |
636 | } |
637 | ||
47a1685f DN |
638 | ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */ |
639 | ctrl |= DXEPCTL_USBACTEP; | |
71225bee | 640 | |
fe0b94ab | 641 | dev_dbg(hsotg->dev, "ep0 state:%d\n", hsotg->ep0_state); |
71225bee LM |
642 | |
643 | /* For Setup request do not clear NAK */ | |
fe0b94ab | 644 | if (!(index == 0 && hsotg->ep0_state == DWC2_EP0_SETUP)) |
47a1685f | 645 | ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */ |
71225bee | 646 | |
5b7d70c6 BD |
647 | dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl); |
648 | writel(ctrl, hsotg->regs + epctrl_reg); | |
649 | ||
8b9bc460 LM |
650 | /* |
651 | * set these, it seems that DMA support increments past the end | |
5b7d70c6 | 652 | * of the packet buffer so we need to calculate the length from |
8b9bc460 LM |
653 | * this information. |
654 | */ | |
5b7d70c6 BD |
655 | hs_ep->size_loaded = length; |
656 | hs_ep->last_load = ureq->actual; | |
657 | ||
658 | if (dir_in && !using_dma(hsotg)) { | |
659 | /* set these anyway, we may need them for non-periodic in */ | |
660 | hs_ep->fifo_load = 0; | |
661 | ||
662 | s3c_hsotg_write_fifo(hsotg, hs_ep, hs_req); | |
663 | } | |
664 | ||
8b9bc460 LM |
665 | /* |
666 | * clear the INTknTXFEmpMsk when we start request, more as a aide | |
667 | * to debugging to see what is going on. | |
668 | */ | |
5b7d70c6 | 669 | if (dir_in) |
47a1685f | 670 | writel(DIEPMSK_INTKNTXFEMPMSK, |
94cb8fd6 | 671 | hsotg->regs + DIEPINT(index)); |
5b7d70c6 | 672 | |
8b9bc460 LM |
673 | /* |
674 | * Note, trying to clear the NAK here causes problems with transmit | |
675 | * on the S3C6400 ending up with the TXFIFO becoming full. | |
676 | */ | |
5b7d70c6 BD |
677 | |
678 | /* check ep is enabled */ | |
47a1685f | 679 | if (!(readl(hsotg->regs + epctrl_reg) & DXEPCTL_EPENA)) |
5b7d70c6 | 680 | dev_warn(hsotg->dev, |
47a1685f | 681 | "ep%d: failed to become enabled (DXEPCTL=0x%08x)?\n", |
5b7d70c6 BD |
682 | index, readl(hsotg->regs + epctrl_reg)); |
683 | ||
47a1685f | 684 | dev_dbg(hsotg->dev, "%s: DXEPCTL=0x%08x\n", |
5b7d70c6 | 685 | __func__, readl(hsotg->regs + epctrl_reg)); |
afcf4169 RB |
686 | |
687 | /* enable ep interrupts */ | |
688 | s3c_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 1); | |
5b7d70c6 BD |
689 | } |
690 | ||
691 | /** | |
692 | * s3c_hsotg_map_dma - map the DMA memory being used for the request | |
693 | * @hsotg: The device state. | |
694 | * @hs_ep: The endpoint the request is on. | |
695 | * @req: The request being processed. | |
696 | * | |
697 | * We've been asked to queue a request, so ensure that the memory buffer | |
698 | * is correctly setup for DMA. If we've been passed an extant DMA address | |
699 | * then ensure the buffer has been synced to memory. If our buffer has no | |
700 | * DMA memory, then we map the memory and mark our request to allow us to | |
701 | * cleanup on completion. | |
8b9bc460 | 702 | */ |
941fcce4 | 703 | static int s3c_hsotg_map_dma(struct dwc2_hsotg *hsotg, |
5b7d70c6 BD |
704 | struct s3c_hsotg_ep *hs_ep, |
705 | struct usb_request *req) | |
706 | { | |
5b7d70c6 | 707 | struct s3c_hsotg_req *hs_req = our_req(req); |
e58ebcd1 | 708 | int ret; |
5b7d70c6 BD |
709 | |
710 | /* if the length is zero, ignore the DMA data */ | |
711 | if (hs_req->req.length == 0) | |
712 | return 0; | |
713 | ||
e58ebcd1 FB |
714 | ret = usb_gadget_map_request(&hsotg->gadget, req, hs_ep->dir_in); |
715 | if (ret) | |
716 | goto dma_error; | |
5b7d70c6 BD |
717 | |
718 | return 0; | |
719 | ||
720 | dma_error: | |
721 | dev_err(hsotg->dev, "%s: failed to map buffer %p, %d bytes\n", | |
722 | __func__, req->buf, req->length); | |
723 | ||
724 | return -EIO; | |
725 | } | |
726 | ||
727 | static int s3c_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req, | |
728 | gfp_t gfp_flags) | |
729 | { | |
730 | struct s3c_hsotg_req *hs_req = our_req(req); | |
731 | struct s3c_hsotg_ep *hs_ep = our_ep(ep); | |
941fcce4 | 732 | struct dwc2_hsotg *hs = hs_ep->parent; |
5b7d70c6 BD |
733 | bool first; |
734 | ||
735 | dev_dbg(hs->dev, "%s: req %p: %d@%p, noi=%d, zero=%d, snok=%d\n", | |
736 | ep->name, req, req->length, req->buf, req->no_interrupt, | |
737 | req->zero, req->short_not_ok); | |
738 | ||
739 | /* initialise status of the request */ | |
740 | INIT_LIST_HEAD(&hs_req->queue); | |
741 | req->actual = 0; | |
742 | req->status = -EINPROGRESS; | |
743 | ||
744 | /* if we're using DMA, sync the buffers as necessary */ | |
745 | if (using_dma(hs)) { | |
746 | int ret = s3c_hsotg_map_dma(hs, hs_ep, req); | |
747 | if (ret) | |
748 | return ret; | |
749 | } | |
750 | ||
5b7d70c6 BD |
751 | first = list_empty(&hs_ep->queue); |
752 | list_add_tail(&hs_req->queue, &hs_ep->queue); | |
753 | ||
754 | if (first) | |
755 | s3c_hsotg_start_req(hs, hs_ep, hs_req, false); | |
756 | ||
5b7d70c6 BD |
757 | return 0; |
758 | } | |
759 | ||
5ad1d316 LM |
760 | static int s3c_hsotg_ep_queue_lock(struct usb_ep *ep, struct usb_request *req, |
761 | gfp_t gfp_flags) | |
762 | { | |
763 | struct s3c_hsotg_ep *hs_ep = our_ep(ep); | |
941fcce4 | 764 | struct dwc2_hsotg *hs = hs_ep->parent; |
5ad1d316 LM |
765 | unsigned long flags = 0; |
766 | int ret = 0; | |
767 | ||
768 | spin_lock_irqsave(&hs->lock, flags); | |
769 | ret = s3c_hsotg_ep_queue(ep, req, gfp_flags); | |
770 | spin_unlock_irqrestore(&hs->lock, flags); | |
771 | ||
772 | return ret; | |
773 | } | |
774 | ||
5b7d70c6 BD |
775 | static void s3c_hsotg_ep_free_request(struct usb_ep *ep, |
776 | struct usb_request *req) | |
777 | { | |
778 | struct s3c_hsotg_req *hs_req = our_req(req); | |
779 | ||
780 | kfree(hs_req); | |
781 | } | |
782 | ||
783 | /** | |
784 | * s3c_hsotg_complete_oursetup - setup completion callback | |
785 | * @ep: The endpoint the request was on. | |
786 | * @req: The request completed. | |
787 | * | |
788 | * Called on completion of any requests the driver itself | |
789 | * submitted that need cleaning up. | |
790 | */ | |
791 | static void s3c_hsotg_complete_oursetup(struct usb_ep *ep, | |
792 | struct usb_request *req) | |
793 | { | |
794 | struct s3c_hsotg_ep *hs_ep = our_ep(ep); | |
941fcce4 | 795 | struct dwc2_hsotg *hsotg = hs_ep->parent; |
5b7d70c6 BD |
796 | |
797 | dev_dbg(hsotg->dev, "%s: ep %p, req %p\n", __func__, ep, req); | |
798 | ||
799 | s3c_hsotg_ep_free_request(ep, req); | |
800 | } | |
801 | ||
802 | /** | |
803 | * ep_from_windex - convert control wIndex value to endpoint | |
804 | * @hsotg: The driver state. | |
805 | * @windex: The control request wIndex field (in host order). | |
806 | * | |
807 | * Convert the given wIndex into a pointer to an driver endpoint | |
808 | * structure, or return NULL if it is not a valid endpoint. | |
8b9bc460 | 809 | */ |
941fcce4 | 810 | static struct s3c_hsotg_ep *ep_from_windex(struct dwc2_hsotg *hsotg, |
5b7d70c6 BD |
811 | u32 windex) |
812 | { | |
c6f5c050 | 813 | struct s3c_hsotg_ep *ep; |
5b7d70c6 BD |
814 | int dir = (windex & USB_DIR_IN) ? 1 : 0; |
815 | int idx = windex & 0x7F; | |
816 | ||
817 | if (windex >= 0x100) | |
818 | return NULL; | |
819 | ||
b3f489b2 | 820 | if (idx > hsotg->num_of_eps) |
5b7d70c6 BD |
821 | return NULL; |
822 | ||
c6f5c050 MYK |
823 | ep = index_to_ep(hsotg, idx, dir); |
824 | ||
5b7d70c6 BD |
825 | if (idx && ep->dir_in != dir) |
826 | return NULL; | |
827 | ||
828 | return ep; | |
829 | } | |
830 | ||
831 | /** | |
832 | * s3c_hsotg_send_reply - send reply to control request | |
833 | * @hsotg: The device state | |
834 | * @ep: Endpoint 0 | |
835 | * @buff: Buffer for request | |
836 | * @length: Length of reply. | |
837 | * | |
838 | * Create a request and queue it on the given endpoint. This is useful as | |
839 | * an internal method of sending replies to certain control requests, etc. | |
840 | */ | |
941fcce4 | 841 | static int s3c_hsotg_send_reply(struct dwc2_hsotg *hsotg, |
5b7d70c6 BD |
842 | struct s3c_hsotg_ep *ep, |
843 | void *buff, | |
844 | int length) | |
845 | { | |
846 | struct usb_request *req; | |
847 | int ret; | |
848 | ||
849 | dev_dbg(hsotg->dev, "%s: buff %p, len %d\n", __func__, buff, length); | |
850 | ||
851 | req = s3c_hsotg_ep_alloc_request(&ep->ep, GFP_ATOMIC); | |
852 | hsotg->ep0_reply = req; | |
853 | if (!req) { | |
854 | dev_warn(hsotg->dev, "%s: cannot alloc req\n", __func__); | |
855 | return -ENOMEM; | |
856 | } | |
857 | ||
858 | req->buf = hsotg->ep0_buff; | |
859 | req->length = length; | |
860 | req->zero = 1; /* always do zero-length final transfer */ | |
861 | req->complete = s3c_hsotg_complete_oursetup; | |
862 | ||
863 | if (length) | |
864 | memcpy(req->buf, buff, length); | |
5b7d70c6 BD |
865 | |
866 | ret = s3c_hsotg_ep_queue(&ep->ep, req, GFP_ATOMIC); | |
867 | if (ret) { | |
868 | dev_warn(hsotg->dev, "%s: cannot queue req\n", __func__); | |
869 | return ret; | |
870 | } | |
871 | ||
872 | return 0; | |
873 | } | |
874 | ||
875 | /** | |
876 | * s3c_hsotg_process_req_status - process request GET_STATUS | |
877 | * @hsotg: The device state | |
878 | * @ctrl: USB control request | |
879 | */ | |
941fcce4 | 880 | static int s3c_hsotg_process_req_status(struct dwc2_hsotg *hsotg, |
5b7d70c6 BD |
881 | struct usb_ctrlrequest *ctrl) |
882 | { | |
c6f5c050 | 883 | struct s3c_hsotg_ep *ep0 = hsotg->eps_out[0]; |
5b7d70c6 BD |
884 | struct s3c_hsotg_ep *ep; |
885 | __le16 reply; | |
886 | int ret; | |
887 | ||
888 | dev_dbg(hsotg->dev, "%s: USB_REQ_GET_STATUS\n", __func__); | |
889 | ||
890 | if (!ep0->dir_in) { | |
891 | dev_warn(hsotg->dev, "%s: direction out?\n", __func__); | |
892 | return -EINVAL; | |
893 | } | |
894 | ||
895 | switch (ctrl->bRequestType & USB_RECIP_MASK) { | |
896 | case USB_RECIP_DEVICE: | |
897 | reply = cpu_to_le16(0); /* bit 0 => self powered, | |
898 | * bit 1 => remote wakeup */ | |
899 | break; | |
900 | ||
901 | case USB_RECIP_INTERFACE: | |
902 | /* currently, the data result should be zero */ | |
903 | reply = cpu_to_le16(0); | |
904 | break; | |
905 | ||
906 | case USB_RECIP_ENDPOINT: | |
907 | ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex)); | |
908 | if (!ep) | |
909 | return -ENOENT; | |
910 | ||
911 | reply = cpu_to_le16(ep->halted ? 1 : 0); | |
912 | break; | |
913 | ||
914 | default: | |
915 | return 0; | |
916 | } | |
917 | ||
918 | if (le16_to_cpu(ctrl->wLength) != 2) | |
919 | return -EINVAL; | |
920 | ||
921 | ret = s3c_hsotg_send_reply(hsotg, ep0, &reply, 2); | |
922 | if (ret) { | |
923 | dev_err(hsotg->dev, "%s: failed to send reply\n", __func__); | |
924 | return ret; | |
925 | } | |
926 | ||
927 | return 1; | |
928 | } | |
929 | ||
930 | static int s3c_hsotg_ep_sethalt(struct usb_ep *ep, int value); | |
931 | ||
9c39ddc6 AT |
932 | /** |
933 | * get_ep_head - return the first request on the endpoint | |
934 | * @hs_ep: The controller endpoint to get | |
935 | * | |
936 | * Get the first request on the endpoint. | |
937 | */ | |
938 | static struct s3c_hsotg_req *get_ep_head(struct s3c_hsotg_ep *hs_ep) | |
939 | { | |
940 | if (list_empty(&hs_ep->queue)) | |
941 | return NULL; | |
942 | ||
943 | return list_first_entry(&hs_ep->queue, struct s3c_hsotg_req, queue); | |
944 | } | |
945 | ||
5b7d70c6 BD |
946 | /** |
947 | * s3c_hsotg_process_req_featire - process request {SET,CLEAR}_FEATURE | |
948 | * @hsotg: The device state | |
949 | * @ctrl: USB control request | |
950 | */ | |
941fcce4 | 951 | static int s3c_hsotg_process_req_feature(struct dwc2_hsotg *hsotg, |
5b7d70c6 BD |
952 | struct usb_ctrlrequest *ctrl) |
953 | { | |
c6f5c050 | 954 | struct s3c_hsotg_ep *ep0 = hsotg->eps_out[0]; |
9c39ddc6 AT |
955 | struct s3c_hsotg_req *hs_req; |
956 | bool restart; | |
5b7d70c6 BD |
957 | bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE); |
958 | struct s3c_hsotg_ep *ep; | |
26ab3d0c | 959 | int ret; |
bd9ef7bf | 960 | bool halted; |
5b7d70c6 BD |
961 | |
962 | dev_dbg(hsotg->dev, "%s: %s_FEATURE\n", | |
963 | __func__, set ? "SET" : "CLEAR"); | |
964 | ||
965 | if (ctrl->bRequestType == USB_RECIP_ENDPOINT) { | |
966 | ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex)); | |
967 | if (!ep) { | |
968 | dev_dbg(hsotg->dev, "%s: no endpoint for 0x%04x\n", | |
969 | __func__, le16_to_cpu(ctrl->wIndex)); | |
970 | return -ENOENT; | |
971 | } | |
972 | ||
973 | switch (le16_to_cpu(ctrl->wValue)) { | |
974 | case USB_ENDPOINT_HALT: | |
bd9ef7bf RB |
975 | halted = ep->halted; |
976 | ||
5b7d70c6 | 977 | s3c_hsotg_ep_sethalt(&ep->ep, set); |
26ab3d0c AT |
978 | |
979 | ret = s3c_hsotg_send_reply(hsotg, ep0, NULL, 0); | |
980 | if (ret) { | |
981 | dev_err(hsotg->dev, | |
982 | "%s: failed to send reply\n", __func__); | |
983 | return ret; | |
984 | } | |
9c39ddc6 | 985 | |
bd9ef7bf RB |
986 | /* |
987 | * we have to complete all requests for ep if it was | |
988 | * halted, and the halt was cleared by CLEAR_FEATURE | |
989 | */ | |
990 | ||
991 | if (!set && halted) { | |
9c39ddc6 AT |
992 | /* |
993 | * If we have request in progress, | |
994 | * then complete it | |
995 | */ | |
996 | if (ep->req) { | |
997 | hs_req = ep->req; | |
998 | ep->req = NULL; | |
999 | list_del_init(&hs_req->queue); | |
304f7e5e MS |
1000 | usb_gadget_giveback_request(&ep->ep, |
1001 | &hs_req->req); | |
9c39ddc6 AT |
1002 | } |
1003 | ||
1004 | /* If we have pending request, then start it */ | |
1005 | restart = !list_empty(&ep->queue); | |
1006 | if (restart) { | |
1007 | hs_req = get_ep_head(ep); | |
1008 | s3c_hsotg_start_req(hsotg, ep, | |
1009 | hs_req, false); | |
1010 | } | |
1011 | } | |
1012 | ||
5b7d70c6 BD |
1013 | break; |
1014 | ||
1015 | default: | |
1016 | return -ENOENT; | |
1017 | } | |
1018 | } else | |
1019 | return -ENOENT; /* currently only deal with endpoint */ | |
1020 | ||
1021 | return 1; | |
1022 | } | |
1023 | ||
941fcce4 | 1024 | static void s3c_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg); |
ab93e014 | 1025 | |
c9f721b2 RB |
1026 | /** |
1027 | * s3c_hsotg_stall_ep0 - stall ep0 | |
1028 | * @hsotg: The device state | |
1029 | * | |
1030 | * Set stall for ep0 as response for setup request. | |
1031 | */ | |
941fcce4 | 1032 | static void s3c_hsotg_stall_ep0(struct dwc2_hsotg *hsotg) |
e9ebe7c3 | 1033 | { |
c6f5c050 | 1034 | struct s3c_hsotg_ep *ep0 = hsotg->eps_out[0]; |
c9f721b2 RB |
1035 | u32 reg; |
1036 | u32 ctrl; | |
1037 | ||
1038 | dev_dbg(hsotg->dev, "ep0 stall (dir=%d)\n", ep0->dir_in); | |
1039 | reg = (ep0->dir_in) ? DIEPCTL0 : DOEPCTL0; | |
1040 | ||
1041 | /* | |
1042 | * DxEPCTL_Stall will be cleared by EP once it has | |
1043 | * taken effect, so no need to clear later. | |
1044 | */ | |
1045 | ||
1046 | ctrl = readl(hsotg->regs + reg); | |
47a1685f DN |
1047 | ctrl |= DXEPCTL_STALL; |
1048 | ctrl |= DXEPCTL_CNAK; | |
c9f721b2 RB |
1049 | writel(ctrl, hsotg->regs + reg); |
1050 | ||
1051 | dev_dbg(hsotg->dev, | |
47a1685f | 1052 | "written DXEPCTL=0x%08x to %08x (DXEPCTL=0x%08x)\n", |
c9f721b2 RB |
1053 | ctrl, reg, readl(hsotg->regs + reg)); |
1054 | ||
1055 | /* | |
1056 | * complete won't be called, so we enqueue | |
1057 | * setup request here | |
1058 | */ | |
1059 | s3c_hsotg_enqueue_setup(hsotg); | |
1060 | } | |
1061 | ||
5b7d70c6 BD |
1062 | /** |
1063 | * s3c_hsotg_process_control - process a control request | |
1064 | * @hsotg: The device state | |
1065 | * @ctrl: The control request received | |
1066 | * | |
1067 | * The controller has received the SETUP phase of a control request, and | |
1068 | * needs to work out what to do next (and whether to pass it on to the | |
1069 | * gadget driver). | |
1070 | */ | |
941fcce4 | 1071 | static void s3c_hsotg_process_control(struct dwc2_hsotg *hsotg, |
5b7d70c6 BD |
1072 | struct usb_ctrlrequest *ctrl) |
1073 | { | |
c6f5c050 | 1074 | struct s3c_hsotg_ep *ep0 = hsotg->eps_out[0]; |
5b7d70c6 BD |
1075 | int ret = 0; |
1076 | u32 dcfg; | |
1077 | ||
5b7d70c6 BD |
1078 | dev_dbg(hsotg->dev, "ctrl Req=%02x, Type=%02x, V=%04x, L=%04x\n", |
1079 | ctrl->bRequest, ctrl->bRequestType, | |
1080 | ctrl->wValue, ctrl->wLength); | |
1081 | ||
fe0b94ab MYK |
1082 | if (ctrl->wLength == 0) { |
1083 | ep0->dir_in = 1; | |
1084 | hsotg->ep0_state = DWC2_EP0_STATUS_IN; | |
1085 | } else if (ctrl->bRequestType & USB_DIR_IN) { | |
5b7d70c6 | 1086 | ep0->dir_in = 1; |
fe0b94ab MYK |
1087 | hsotg->ep0_state = DWC2_EP0_DATA_IN; |
1088 | } else { | |
1089 | ep0->dir_in = 0; | |
1090 | hsotg->ep0_state = DWC2_EP0_DATA_OUT; | |
1091 | } | |
5b7d70c6 BD |
1092 | |
1093 | if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) { | |
1094 | switch (ctrl->bRequest) { | |
1095 | case USB_REQ_SET_ADDRESS: | |
94cb8fd6 | 1096 | dcfg = readl(hsotg->regs + DCFG); |
47a1685f | 1097 | dcfg &= ~DCFG_DEVADDR_MASK; |
d5dbd3f7 PZ |
1098 | dcfg |= (le16_to_cpu(ctrl->wValue) << |
1099 | DCFG_DEVADDR_SHIFT) & DCFG_DEVADDR_MASK; | |
94cb8fd6 | 1100 | writel(dcfg, hsotg->regs + DCFG); |
5b7d70c6 BD |
1101 | |
1102 | dev_info(hsotg->dev, "new address %d\n", ctrl->wValue); | |
1103 | ||
1104 | ret = s3c_hsotg_send_reply(hsotg, ep0, NULL, 0); | |
1105 | return; | |
1106 | ||
1107 | case USB_REQ_GET_STATUS: | |
1108 | ret = s3c_hsotg_process_req_status(hsotg, ctrl); | |
1109 | break; | |
1110 | ||
1111 | case USB_REQ_CLEAR_FEATURE: | |
1112 | case USB_REQ_SET_FEATURE: | |
1113 | ret = s3c_hsotg_process_req_feature(hsotg, ctrl); | |
1114 | break; | |
1115 | } | |
1116 | } | |
1117 | ||
1118 | /* as a fallback, try delivering it to the driver to deal with */ | |
1119 | ||
1120 | if (ret == 0 && hsotg->driver) { | |
93f599f2 | 1121 | spin_unlock(&hsotg->lock); |
5b7d70c6 | 1122 | ret = hsotg->driver->setup(&hsotg->gadget, ctrl); |
93f599f2 | 1123 | spin_lock(&hsotg->lock); |
5b7d70c6 BD |
1124 | if (ret < 0) |
1125 | dev_dbg(hsotg->dev, "driver->setup() ret %d\n", ret); | |
1126 | } | |
1127 | ||
8b9bc460 LM |
1128 | /* |
1129 | * the request is either unhandlable, or is not formatted correctly | |
5b7d70c6 BD |
1130 | * so respond with a STALL for the status stage to indicate failure. |
1131 | */ | |
1132 | ||
c9f721b2 RB |
1133 | if (ret < 0) |
1134 | s3c_hsotg_stall_ep0(hsotg); | |
5b7d70c6 BD |
1135 | } |
1136 | ||
5b7d70c6 BD |
1137 | /** |
1138 | * s3c_hsotg_complete_setup - completion of a setup transfer | |
1139 | * @ep: The endpoint the request was on. | |
1140 | * @req: The request completed. | |
1141 | * | |
1142 | * Called on completion of any requests the driver itself submitted for | |
1143 | * EP0 setup packets | |
1144 | */ | |
1145 | static void s3c_hsotg_complete_setup(struct usb_ep *ep, | |
1146 | struct usb_request *req) | |
1147 | { | |
1148 | struct s3c_hsotg_ep *hs_ep = our_ep(ep); | |
941fcce4 | 1149 | struct dwc2_hsotg *hsotg = hs_ep->parent; |
5b7d70c6 BD |
1150 | |
1151 | if (req->status < 0) { | |
1152 | dev_dbg(hsotg->dev, "%s: failed %d\n", __func__, req->status); | |
1153 | return; | |
1154 | } | |
1155 | ||
93f599f2 | 1156 | spin_lock(&hsotg->lock); |
5b7d70c6 BD |
1157 | if (req->actual == 0) |
1158 | s3c_hsotg_enqueue_setup(hsotg); | |
1159 | else | |
1160 | s3c_hsotg_process_control(hsotg, req->buf); | |
93f599f2 | 1161 | spin_unlock(&hsotg->lock); |
5b7d70c6 BD |
1162 | } |
1163 | ||
1164 | /** | |
1165 | * s3c_hsotg_enqueue_setup - start a request for EP0 packets | |
1166 | * @hsotg: The device state. | |
1167 | * | |
1168 | * Enqueue a request on EP0 if necessary to received any SETUP packets | |
1169 | * received from the host. | |
1170 | */ | |
941fcce4 | 1171 | static void s3c_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg) |
5b7d70c6 BD |
1172 | { |
1173 | struct usb_request *req = hsotg->ctrl_req; | |
1174 | struct s3c_hsotg_req *hs_req = our_req(req); | |
1175 | int ret; | |
1176 | ||
1177 | dev_dbg(hsotg->dev, "%s: queueing setup request\n", __func__); | |
1178 | ||
1179 | req->zero = 0; | |
1180 | req->length = 8; | |
1181 | req->buf = hsotg->ctrl_buff; | |
1182 | req->complete = s3c_hsotg_complete_setup; | |
1183 | ||
1184 | if (!list_empty(&hs_req->queue)) { | |
1185 | dev_dbg(hsotg->dev, "%s already queued???\n", __func__); | |
1186 | return; | |
1187 | } | |
1188 | ||
c6f5c050 | 1189 | hsotg->eps_out[0]->dir_in = 0; |
fe0b94ab MYK |
1190 | hsotg->eps_out[0]->sent_zlp = 0; |
1191 | hsotg->ep0_state = DWC2_EP0_SETUP; | |
5b7d70c6 | 1192 | |
c6f5c050 | 1193 | ret = s3c_hsotg_ep_queue(&hsotg->eps_out[0]->ep, req, GFP_ATOMIC); |
5b7d70c6 BD |
1194 | if (ret < 0) { |
1195 | dev_err(hsotg->dev, "%s: failed queue (%d)\n", __func__, ret); | |
8b9bc460 LM |
1196 | /* |
1197 | * Don't think there's much we can do other than watch the | |
1198 | * driver fail. | |
1199 | */ | |
5b7d70c6 BD |
1200 | } |
1201 | } | |
1202 | ||
fe0b94ab MYK |
1203 | static void s3c_hsotg_program_zlp(struct dwc2_hsotg *hsotg, |
1204 | struct s3c_hsotg_ep *hs_ep) | |
1205 | { | |
1206 | u32 ctrl; | |
1207 | u8 index = hs_ep->index; | |
1208 | u32 epctl_reg = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index); | |
1209 | u32 epsiz_reg = hs_ep->dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index); | |
1210 | ||
1211 | dev_dbg(hsotg->dev, "Sending zero-length packet on ep%d\n", index); | |
1212 | ||
1213 | writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) | | |
1214 | DXEPTSIZ_XFERSIZE(0), hsotg->regs + | |
1215 | epsiz_reg); | |
1216 | ||
1217 | ctrl = readl(hsotg->regs + epctl_reg); | |
1218 | ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */ | |
1219 | ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */ | |
1220 | ctrl |= DXEPCTL_USBACTEP; | |
1221 | writel(ctrl, hsotg->regs + epctl_reg); | |
1222 | } | |
1223 | ||
5b7d70c6 BD |
1224 | /** |
1225 | * s3c_hsotg_complete_request - complete a request given to us | |
1226 | * @hsotg: The device state. | |
1227 | * @hs_ep: The endpoint the request was on. | |
1228 | * @hs_req: The request to complete. | |
1229 | * @result: The result code (0 => Ok, otherwise errno) | |
1230 | * | |
1231 | * The given request has finished, so call the necessary completion | |
1232 | * if it has one and then look to see if we can start a new request | |
1233 | * on the endpoint. | |
1234 | * | |
1235 | * Note, expects the ep to already be locked as appropriate. | |
8b9bc460 | 1236 | */ |
941fcce4 | 1237 | static void s3c_hsotg_complete_request(struct dwc2_hsotg *hsotg, |
5b7d70c6 BD |
1238 | struct s3c_hsotg_ep *hs_ep, |
1239 | struct s3c_hsotg_req *hs_req, | |
1240 | int result) | |
1241 | { | |
1242 | bool restart; | |
1243 | ||
1244 | if (!hs_req) { | |
1245 | dev_dbg(hsotg->dev, "%s: nothing to complete?\n", __func__); | |
1246 | return; | |
1247 | } | |
1248 | ||
1249 | dev_dbg(hsotg->dev, "complete: ep %p %s, req %p, %d => %p\n", | |
1250 | hs_ep, hs_ep->ep.name, hs_req, result, hs_req->req.complete); | |
1251 | ||
8b9bc460 LM |
1252 | /* |
1253 | * only replace the status if we've not already set an error | |
1254 | * from a previous transaction | |
1255 | */ | |
5b7d70c6 BD |
1256 | |
1257 | if (hs_req->req.status == -EINPROGRESS) | |
1258 | hs_req->req.status = result; | |
1259 | ||
1260 | hs_ep->req = NULL; | |
1261 | list_del_init(&hs_req->queue); | |
1262 | ||
1263 | if (using_dma(hsotg)) | |
1264 | s3c_hsotg_unmap_dma(hsotg, hs_ep, hs_req); | |
1265 | ||
8b9bc460 LM |
1266 | /* |
1267 | * call the complete request with the locks off, just in case the | |
1268 | * request tries to queue more work for this endpoint. | |
1269 | */ | |
5b7d70c6 BD |
1270 | |
1271 | if (hs_req->req.complete) { | |
22258f49 | 1272 | spin_unlock(&hsotg->lock); |
304f7e5e | 1273 | usb_gadget_giveback_request(&hs_ep->ep, &hs_req->req); |
22258f49 | 1274 | spin_lock(&hsotg->lock); |
5b7d70c6 BD |
1275 | } |
1276 | ||
8b9bc460 LM |
1277 | /* |
1278 | * Look to see if there is anything else to do. Note, the completion | |
5b7d70c6 | 1279 | * of the previous request may have caused a new request to be started |
8b9bc460 LM |
1280 | * so be careful when doing this. |
1281 | */ | |
5b7d70c6 BD |
1282 | |
1283 | if (!hs_ep->req && result >= 0) { | |
1284 | restart = !list_empty(&hs_ep->queue); | |
1285 | if (restart) { | |
1286 | hs_req = get_ep_head(hs_ep); | |
1287 | s3c_hsotg_start_req(hsotg, hs_ep, hs_req, false); | |
1288 | } | |
1289 | } | |
1290 | } | |
1291 | ||
5b7d70c6 BD |
1292 | /** |
1293 | * s3c_hsotg_rx_data - receive data from the FIFO for an endpoint | |
1294 | * @hsotg: The device state. | |
1295 | * @ep_idx: The endpoint index for the data | |
1296 | * @size: The size of data in the fifo, in bytes | |
1297 | * | |
1298 | * The FIFO status shows there is data to read from the FIFO for a given | |
1299 | * endpoint, so sort out whether we need to read the data into a request | |
1300 | * that has been made for that endpoint. | |
1301 | */ | |
941fcce4 | 1302 | static void s3c_hsotg_rx_data(struct dwc2_hsotg *hsotg, int ep_idx, int size) |
5b7d70c6 | 1303 | { |
c6f5c050 | 1304 | struct s3c_hsotg_ep *hs_ep = hsotg->eps_out[ep_idx]; |
5b7d70c6 | 1305 | struct s3c_hsotg_req *hs_req = hs_ep->req; |
94cb8fd6 | 1306 | void __iomem *fifo = hsotg->regs + EPFIFO(ep_idx); |
5b7d70c6 BD |
1307 | int to_read; |
1308 | int max_req; | |
1309 | int read_ptr; | |
1310 | ||
22258f49 | 1311 | |
5b7d70c6 | 1312 | if (!hs_req) { |
94cb8fd6 | 1313 | u32 epctl = readl(hsotg->regs + DOEPCTL(ep_idx)); |
5b7d70c6 BD |
1314 | int ptr; |
1315 | ||
6b448af4 | 1316 | dev_dbg(hsotg->dev, |
47a1685f | 1317 | "%s: FIFO %d bytes on ep%d but no req (DXEPCTl=0x%08x)\n", |
5b7d70c6 BD |
1318 | __func__, size, ep_idx, epctl); |
1319 | ||
1320 | /* dump the data from the FIFO, we've nothing we can do */ | |
1321 | for (ptr = 0; ptr < size; ptr += 4) | |
1322 | (void)readl(fifo); | |
1323 | ||
1324 | return; | |
1325 | } | |
1326 | ||
5b7d70c6 BD |
1327 | to_read = size; |
1328 | read_ptr = hs_req->req.actual; | |
1329 | max_req = hs_req->req.length - read_ptr; | |
1330 | ||
a33e7136 BD |
1331 | dev_dbg(hsotg->dev, "%s: read %d/%d, done %d/%d\n", |
1332 | __func__, to_read, max_req, read_ptr, hs_req->req.length); | |
1333 | ||
5b7d70c6 | 1334 | if (to_read > max_req) { |
8b9bc460 LM |
1335 | /* |
1336 | * more data appeared than we where willing | |
5b7d70c6 BD |
1337 | * to deal with in this request. |
1338 | */ | |
1339 | ||
1340 | /* currently we don't deal this */ | |
1341 | WARN_ON_ONCE(1); | |
1342 | } | |
1343 | ||
5b7d70c6 BD |
1344 | hs_ep->total_data += to_read; |
1345 | hs_req->req.actual += to_read; | |
1346 | to_read = DIV_ROUND_UP(to_read, 4); | |
1347 | ||
8b9bc460 LM |
1348 | /* |
1349 | * note, we might over-write the buffer end by 3 bytes depending on | |
1350 | * alignment of the data. | |
1351 | */ | |
1a7ed5be | 1352 | ioread32_rep(fifo, hs_req->req.buf + read_ptr, to_read); |
5b7d70c6 BD |
1353 | } |
1354 | ||
1355 | /** | |
fe0b94ab | 1356 | * s3c_hsotg_ep0_zlp - send/receive zero-length packet on control endpoint |
5b7d70c6 | 1357 | * @hsotg: The device instance |
fe0b94ab | 1358 | * @dir_in: If IN zlp |
5b7d70c6 BD |
1359 | * |
1360 | * Generate a zero-length IN packet request for terminating a SETUP | |
1361 | * transaction. | |
1362 | * | |
1363 | * Note, since we don't write any data to the TxFIFO, then it is | |
25985edc | 1364 | * currently believed that we do not need to wait for any space in |
5b7d70c6 BD |
1365 | * the TxFIFO. |
1366 | */ | |
fe0b94ab | 1367 | static void s3c_hsotg_ep0_zlp(struct dwc2_hsotg *hsotg, bool dir_in) |
5b7d70c6 | 1368 | { |
c6f5c050 | 1369 | /* eps_out[0] is used in both directions */ |
fe0b94ab MYK |
1370 | hsotg->eps_out[0]->dir_in = dir_in; |
1371 | hsotg->ep0_state = dir_in ? DWC2_EP0_STATUS_IN : DWC2_EP0_STATUS_OUT; | |
5b7d70c6 | 1372 | |
fe0b94ab | 1373 | s3c_hsotg_program_zlp(hsotg, hsotg->eps_out[0]); |
5b7d70c6 BD |
1374 | } |
1375 | ||
1376 | /** | |
1377 | * s3c_hsotg_handle_outdone - handle receiving OutDone/SetupDone from RXFIFO | |
1378 | * @hsotg: The device instance | |
1379 | * @epnum: The endpoint received from | |
5b7d70c6 BD |
1380 | * |
1381 | * The RXFIFO has delivered an OutDone event, which means that the data | |
1382 | * transfer for an OUT endpoint has been completed, either by a short | |
1383 | * packet or by the finish of a transfer. | |
8b9bc460 | 1384 | */ |
fe0b94ab | 1385 | static void s3c_hsotg_handle_outdone(struct dwc2_hsotg *hsotg, int epnum) |
5b7d70c6 | 1386 | { |
94cb8fd6 | 1387 | u32 epsize = readl(hsotg->regs + DOEPTSIZ(epnum)); |
c6f5c050 | 1388 | struct s3c_hsotg_ep *hs_ep = hsotg->eps_out[epnum]; |
5b7d70c6 BD |
1389 | struct s3c_hsotg_req *hs_req = hs_ep->req; |
1390 | struct usb_request *req = &hs_req->req; | |
47a1685f | 1391 | unsigned size_left = DXEPTSIZ_XFERSIZE_GET(epsize); |
5b7d70c6 BD |
1392 | int result = 0; |
1393 | ||
1394 | if (!hs_req) { | |
1395 | dev_dbg(hsotg->dev, "%s: no request active\n", __func__); | |
1396 | return; | |
1397 | } | |
1398 | ||
fe0b94ab MYK |
1399 | if (epnum == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_OUT) { |
1400 | dev_dbg(hsotg->dev, "zlp packet received\n"); | |
1401 | s3c_hsotg_complete_request(hsotg, hs_ep, hs_req, 0); | |
1402 | s3c_hsotg_enqueue_setup(hsotg); | |
1403 | return; | |
1404 | } | |
1405 | ||
5b7d70c6 | 1406 | if (using_dma(hsotg)) { |
5b7d70c6 | 1407 | unsigned size_done; |
5b7d70c6 | 1408 | |
8b9bc460 LM |
1409 | /* |
1410 | * Calculate the size of the transfer by checking how much | |
5b7d70c6 BD |
1411 | * is left in the endpoint size register and then working it |
1412 | * out from the amount we loaded for the transfer. | |
1413 | * | |
1414 | * We need to do this as DMA pointers are always 32bit aligned | |
1415 | * so may overshoot/undershoot the transfer. | |
1416 | */ | |
1417 | ||
5b7d70c6 BD |
1418 | size_done = hs_ep->size_loaded - size_left; |
1419 | size_done += hs_ep->last_load; | |
1420 | ||
1421 | req->actual = size_done; | |
1422 | } | |
1423 | ||
a33e7136 BD |
1424 | /* if there is more request to do, schedule new transfer */ |
1425 | if (req->actual < req->length && size_left == 0) { | |
1426 | s3c_hsotg_start_req(hsotg, hs_ep, hs_req, true); | |
1427 | return; | |
1428 | } | |
1429 | ||
5b7d70c6 BD |
1430 | if (req->actual < req->length && req->short_not_ok) { |
1431 | dev_dbg(hsotg->dev, "%s: got %d/%d (short not ok) => error\n", | |
1432 | __func__, req->actual, req->length); | |
1433 | ||
8b9bc460 LM |
1434 | /* |
1435 | * todo - what should we return here? there's no one else | |
1436 | * even bothering to check the status. | |
1437 | */ | |
5b7d70c6 BD |
1438 | } |
1439 | ||
fe0b94ab MYK |
1440 | if (epnum == 0 && hsotg->ep0_state == DWC2_EP0_DATA_OUT) { |
1441 | /* Move to STATUS IN */ | |
1442 | s3c_hsotg_ep0_zlp(hsotg, true); | |
1443 | return; | |
5b7d70c6 BD |
1444 | } |
1445 | ||
5ad1d316 | 1446 | s3c_hsotg_complete_request(hsotg, hs_ep, hs_req, result); |
5b7d70c6 BD |
1447 | } |
1448 | ||
1449 | /** | |
1450 | * s3c_hsotg_read_frameno - read current frame number | |
1451 | * @hsotg: The device instance | |
1452 | * | |
1453 | * Return the current frame number | |
8b9bc460 | 1454 | */ |
941fcce4 | 1455 | static u32 s3c_hsotg_read_frameno(struct dwc2_hsotg *hsotg) |
5b7d70c6 BD |
1456 | { |
1457 | u32 dsts; | |
1458 | ||
94cb8fd6 LM |
1459 | dsts = readl(hsotg->regs + DSTS); |
1460 | dsts &= DSTS_SOFFN_MASK; | |
1461 | dsts >>= DSTS_SOFFN_SHIFT; | |
5b7d70c6 BD |
1462 | |
1463 | return dsts; | |
1464 | } | |
1465 | ||
1466 | /** | |
1467 | * s3c_hsotg_handle_rx - RX FIFO has data | |
1468 | * @hsotg: The device instance | |
1469 | * | |
1470 | * The IRQ handler has detected that the RX FIFO has some data in it | |
1471 | * that requires processing, so find out what is in there and do the | |
1472 | * appropriate read. | |
1473 | * | |
25985edc | 1474 | * The RXFIFO is a true FIFO, the packets coming out are still in packet |
5b7d70c6 BD |
1475 | * chunks, so if you have x packets received on an endpoint you'll get x |
1476 | * FIFO events delivered, each with a packet's worth of data in it. | |
1477 | * | |
1478 | * When using DMA, we should not be processing events from the RXFIFO | |
1479 | * as the actual data should be sent to the memory directly and we turn | |
1480 | * on the completion interrupts to get notifications of transfer completion. | |
1481 | */ | |
941fcce4 | 1482 | static void s3c_hsotg_handle_rx(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 1483 | { |
94cb8fd6 | 1484 | u32 grxstsr = readl(hsotg->regs + GRXSTSP); |
5b7d70c6 BD |
1485 | u32 epnum, status, size; |
1486 | ||
1487 | WARN_ON(using_dma(hsotg)); | |
1488 | ||
47a1685f DN |
1489 | epnum = grxstsr & GRXSTS_EPNUM_MASK; |
1490 | status = grxstsr & GRXSTS_PKTSTS_MASK; | |
5b7d70c6 | 1491 | |
47a1685f DN |
1492 | size = grxstsr & GRXSTS_BYTECNT_MASK; |
1493 | size >>= GRXSTS_BYTECNT_SHIFT; | |
5b7d70c6 BD |
1494 | |
1495 | if (1) | |
1496 | dev_dbg(hsotg->dev, "%s: GRXSTSP=0x%08x (%d@%d)\n", | |
1497 | __func__, grxstsr, size, epnum); | |
1498 | ||
47a1685f DN |
1499 | switch ((status & GRXSTS_PKTSTS_MASK) >> GRXSTS_PKTSTS_SHIFT) { |
1500 | case GRXSTS_PKTSTS_GLOBALOUTNAK: | |
1501 | dev_dbg(hsotg->dev, "GLOBALOUTNAK\n"); | |
5b7d70c6 BD |
1502 | break; |
1503 | ||
47a1685f | 1504 | case GRXSTS_PKTSTS_OUTDONE: |
5b7d70c6 BD |
1505 | dev_dbg(hsotg->dev, "OutDone (Frame=0x%08x)\n", |
1506 | s3c_hsotg_read_frameno(hsotg)); | |
1507 | ||
1508 | if (!using_dma(hsotg)) | |
fe0b94ab | 1509 | s3c_hsotg_handle_outdone(hsotg, epnum); |
5b7d70c6 BD |
1510 | break; |
1511 | ||
47a1685f | 1512 | case GRXSTS_PKTSTS_SETUPDONE: |
5b7d70c6 BD |
1513 | dev_dbg(hsotg->dev, |
1514 | "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n", | |
1515 | s3c_hsotg_read_frameno(hsotg), | |
94cb8fd6 | 1516 | readl(hsotg->regs + DOEPCTL(0))); |
fe0b94ab MYK |
1517 | /* |
1518 | * Call s3c_hsotg_handle_outdone here if it was not called from | |
1519 | * GRXSTS_PKTSTS_OUTDONE. That is, if the core didn't | |
1520 | * generate GRXSTS_PKTSTS_OUTDONE for setup packet. | |
1521 | */ | |
1522 | if (hsotg->ep0_state == DWC2_EP0_SETUP) | |
1523 | s3c_hsotg_handle_outdone(hsotg, epnum); | |
5b7d70c6 BD |
1524 | break; |
1525 | ||
47a1685f | 1526 | case GRXSTS_PKTSTS_OUTRX: |
5b7d70c6 BD |
1527 | s3c_hsotg_rx_data(hsotg, epnum, size); |
1528 | break; | |
1529 | ||
47a1685f | 1530 | case GRXSTS_PKTSTS_SETUPRX: |
5b7d70c6 BD |
1531 | dev_dbg(hsotg->dev, |
1532 | "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n", | |
1533 | s3c_hsotg_read_frameno(hsotg), | |
94cb8fd6 | 1534 | readl(hsotg->regs + DOEPCTL(0))); |
5b7d70c6 | 1535 | |
fe0b94ab MYK |
1536 | WARN_ON(hsotg->ep0_state != DWC2_EP0_SETUP); |
1537 | ||
5b7d70c6 BD |
1538 | s3c_hsotg_rx_data(hsotg, epnum, size); |
1539 | break; | |
1540 | ||
1541 | default: | |
1542 | dev_warn(hsotg->dev, "%s: unknown status %08x\n", | |
1543 | __func__, grxstsr); | |
1544 | ||
1545 | s3c_hsotg_dump(hsotg); | |
1546 | break; | |
1547 | } | |
1548 | } | |
1549 | ||
1550 | /** | |
1551 | * s3c_hsotg_ep0_mps - turn max packet size into register setting | |
1552 | * @mps: The maximum packet size in bytes. | |
8b9bc460 | 1553 | */ |
5b7d70c6 BD |
1554 | static u32 s3c_hsotg_ep0_mps(unsigned int mps) |
1555 | { | |
1556 | switch (mps) { | |
1557 | case 64: | |
94cb8fd6 | 1558 | return D0EPCTL_MPS_64; |
5b7d70c6 | 1559 | case 32: |
94cb8fd6 | 1560 | return D0EPCTL_MPS_32; |
5b7d70c6 | 1561 | case 16: |
94cb8fd6 | 1562 | return D0EPCTL_MPS_16; |
5b7d70c6 | 1563 | case 8: |
94cb8fd6 | 1564 | return D0EPCTL_MPS_8; |
5b7d70c6 BD |
1565 | } |
1566 | ||
1567 | /* bad max packet size, warn and return invalid result */ | |
1568 | WARN_ON(1); | |
1569 | return (u32)-1; | |
1570 | } | |
1571 | ||
1572 | /** | |
1573 | * s3c_hsotg_set_ep_maxpacket - set endpoint's max-packet field | |
1574 | * @hsotg: The driver state. | |
1575 | * @ep: The index number of the endpoint | |
1576 | * @mps: The maximum packet size in bytes | |
1577 | * | |
1578 | * Configure the maximum packet size for the given endpoint, updating | |
1579 | * the hardware control registers to reflect this. | |
1580 | */ | |
941fcce4 | 1581 | static void s3c_hsotg_set_ep_maxpacket(struct dwc2_hsotg *hsotg, |
c6f5c050 | 1582 | unsigned int ep, unsigned int mps, unsigned int dir_in) |
5b7d70c6 | 1583 | { |
c6f5c050 | 1584 | struct s3c_hsotg_ep *hs_ep; |
5b7d70c6 BD |
1585 | void __iomem *regs = hsotg->regs; |
1586 | u32 mpsval; | |
4fca54aa | 1587 | u32 mcval; |
5b7d70c6 BD |
1588 | u32 reg; |
1589 | ||
c6f5c050 MYK |
1590 | hs_ep = index_to_ep(hsotg, ep, dir_in); |
1591 | if (!hs_ep) | |
1592 | return; | |
1593 | ||
5b7d70c6 BD |
1594 | if (ep == 0) { |
1595 | /* EP0 is a special case */ | |
1596 | mpsval = s3c_hsotg_ep0_mps(mps); | |
1597 | if (mpsval > 3) | |
1598 | goto bad_mps; | |
e9edd199 | 1599 | hs_ep->ep.maxpacket = mps; |
4fca54aa | 1600 | hs_ep->mc = 1; |
5b7d70c6 | 1601 | } else { |
47a1685f | 1602 | mpsval = mps & DXEPCTL_MPS_MASK; |
e9edd199 | 1603 | if (mpsval > 1024) |
5b7d70c6 | 1604 | goto bad_mps; |
4fca54aa RB |
1605 | mcval = ((mps >> 11) & 0x3) + 1; |
1606 | hs_ep->mc = mcval; | |
1607 | if (mcval > 3) | |
1608 | goto bad_mps; | |
e9edd199 | 1609 | hs_ep->ep.maxpacket = mpsval; |
5b7d70c6 BD |
1610 | } |
1611 | ||
c6f5c050 MYK |
1612 | if (dir_in) { |
1613 | reg = readl(regs + DIEPCTL(ep)); | |
1614 | reg &= ~DXEPCTL_MPS_MASK; | |
1615 | reg |= mpsval; | |
1616 | writel(reg, regs + DIEPCTL(ep)); | |
1617 | } else { | |
94cb8fd6 | 1618 | reg = readl(regs + DOEPCTL(ep)); |
47a1685f | 1619 | reg &= ~DXEPCTL_MPS_MASK; |
659ad60c | 1620 | reg |= mpsval; |
94cb8fd6 | 1621 | writel(reg, regs + DOEPCTL(ep)); |
659ad60c | 1622 | } |
5b7d70c6 BD |
1623 | |
1624 | return; | |
1625 | ||
1626 | bad_mps: | |
1627 | dev_err(hsotg->dev, "ep%d: bad mps of %d\n", ep, mps); | |
1628 | } | |
1629 | ||
9c39ddc6 AT |
1630 | /** |
1631 | * s3c_hsotg_txfifo_flush - flush Tx FIFO | |
1632 | * @hsotg: The driver state | |
1633 | * @idx: The index for the endpoint (0..15) | |
1634 | */ | |
941fcce4 | 1635 | static void s3c_hsotg_txfifo_flush(struct dwc2_hsotg *hsotg, unsigned int idx) |
9c39ddc6 AT |
1636 | { |
1637 | int timeout; | |
1638 | int val; | |
1639 | ||
47a1685f | 1640 | writel(GRSTCTL_TXFNUM(idx) | GRSTCTL_TXFFLSH, |
94cb8fd6 | 1641 | hsotg->regs + GRSTCTL); |
9c39ddc6 AT |
1642 | |
1643 | /* wait until the fifo is flushed */ | |
1644 | timeout = 100; | |
1645 | ||
1646 | while (1) { | |
94cb8fd6 | 1647 | val = readl(hsotg->regs + GRSTCTL); |
9c39ddc6 | 1648 | |
47a1685f | 1649 | if ((val & (GRSTCTL_TXFFLSH)) == 0) |
9c39ddc6 AT |
1650 | break; |
1651 | ||
1652 | if (--timeout == 0) { | |
1653 | dev_err(hsotg->dev, | |
1654 | "%s: timeout flushing fifo (GRSTCTL=%08x)\n", | |
1655 | __func__, val); | |
e0cbe595 | 1656 | break; |
9c39ddc6 AT |
1657 | } |
1658 | ||
1659 | udelay(1); | |
1660 | } | |
1661 | } | |
5b7d70c6 BD |
1662 | |
1663 | /** | |
1664 | * s3c_hsotg_trytx - check to see if anything needs transmitting | |
1665 | * @hsotg: The driver state | |
1666 | * @hs_ep: The driver endpoint to check. | |
1667 | * | |
1668 | * Check to see if there is a request that has data to send, and if so | |
1669 | * make an attempt to write data into the FIFO. | |
1670 | */ | |
941fcce4 | 1671 | static int s3c_hsotg_trytx(struct dwc2_hsotg *hsotg, |
5b7d70c6 BD |
1672 | struct s3c_hsotg_ep *hs_ep) |
1673 | { | |
1674 | struct s3c_hsotg_req *hs_req = hs_ep->req; | |
1675 | ||
afcf4169 RB |
1676 | if (!hs_ep->dir_in || !hs_req) { |
1677 | /** | |
1678 | * if request is not enqueued, we disable interrupts | |
1679 | * for endpoints, excepting ep0 | |
1680 | */ | |
1681 | if (hs_ep->index != 0) | |
1682 | s3c_hsotg_ctrl_epint(hsotg, hs_ep->index, | |
1683 | hs_ep->dir_in, 0); | |
5b7d70c6 | 1684 | return 0; |
afcf4169 | 1685 | } |
5b7d70c6 BD |
1686 | |
1687 | if (hs_req->req.actual < hs_req->req.length) { | |
1688 | dev_dbg(hsotg->dev, "trying to write more for ep%d\n", | |
1689 | hs_ep->index); | |
1690 | return s3c_hsotg_write_fifo(hsotg, hs_ep, hs_req); | |
1691 | } | |
1692 | ||
1693 | return 0; | |
1694 | } | |
1695 | ||
1696 | /** | |
1697 | * s3c_hsotg_complete_in - complete IN transfer | |
1698 | * @hsotg: The device state. | |
1699 | * @hs_ep: The endpoint that has just completed. | |
1700 | * | |
1701 | * An IN transfer has been completed, update the transfer's state and then | |
1702 | * call the relevant completion routines. | |
1703 | */ | |
941fcce4 | 1704 | static void s3c_hsotg_complete_in(struct dwc2_hsotg *hsotg, |
5b7d70c6 BD |
1705 | struct s3c_hsotg_ep *hs_ep) |
1706 | { | |
1707 | struct s3c_hsotg_req *hs_req = hs_ep->req; | |
94cb8fd6 | 1708 | u32 epsize = readl(hsotg->regs + DIEPTSIZ(hs_ep->index)); |
5b7d70c6 BD |
1709 | int size_left, size_done; |
1710 | ||
1711 | if (!hs_req) { | |
1712 | dev_dbg(hsotg->dev, "XferCompl but no req\n"); | |
1713 | return; | |
1714 | } | |
1715 | ||
d3ca0259 | 1716 | /* Finish ZLP handling for IN EP0 transactions */ |
fe0b94ab MYK |
1717 | if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_IN) { |
1718 | dev_dbg(hsotg->dev, "zlp packet sent\n"); | |
5ad1d316 | 1719 | s3c_hsotg_complete_request(hsotg, hs_ep, hs_req, 0); |
fe0b94ab | 1720 | s3c_hsotg_enqueue_setup(hsotg); |
d3ca0259 LM |
1721 | return; |
1722 | } | |
1723 | ||
8b9bc460 LM |
1724 | /* |
1725 | * Calculate the size of the transfer by checking how much is left | |
5b7d70c6 BD |
1726 | * in the endpoint size register and then working it out from |
1727 | * the amount we loaded for the transfer. | |
1728 | * | |
1729 | * We do this even for DMA, as the transfer may have incremented | |
1730 | * past the end of the buffer (DMA transfers are always 32bit | |
1731 | * aligned). | |
1732 | */ | |
1733 | ||
47a1685f | 1734 | size_left = DXEPTSIZ_XFERSIZE_GET(epsize); |
5b7d70c6 BD |
1735 | |
1736 | size_done = hs_ep->size_loaded - size_left; | |
1737 | size_done += hs_ep->last_load; | |
1738 | ||
1739 | if (hs_req->req.actual != size_done) | |
1740 | dev_dbg(hsotg->dev, "%s: adjusting size done %d => %d\n", | |
1741 | __func__, hs_req->req.actual, size_done); | |
1742 | ||
1743 | hs_req->req.actual = size_done; | |
d3ca0259 LM |
1744 | dev_dbg(hsotg->dev, "req->length:%d req->actual:%d req->zero:%d\n", |
1745 | hs_req->req.length, hs_req->req.actual, hs_req->req.zero); | |
1746 | ||
1747 | /* | |
1748 | * Check if dealing with Maximum Packet Size(MPS) IN transfer at EP0 | |
1749 | * When sent data is a multiple MPS size (e.g. 64B ,128B ,192B | |
1750 | * ,256B ... ), after last MPS sized packet send IN ZLP packet to | |
1751 | * inform the host that no more data is available. | |
1752 | * The state of req.zero member is checked to be sure that the value to | |
1753 | * send is smaller than wValue expected from host. | |
1754 | * Check req.length to NOT send another ZLP when the current one is | |
1755 | * under completion (the one for which this completion has been called). | |
1756 | */ | |
1757 | if (hs_req->req.length && hs_ep->index == 0 && hs_req->req.zero && | |
1758 | hs_req->req.length == hs_req->req.actual && | |
1759 | !(hs_req->req.length % hs_ep->ep.maxpacket)) { | |
1760 | ||
1761 | dev_dbg(hsotg->dev, "ep0 zlp IN packet sent\n"); | |
fe0b94ab | 1762 | s3c_hsotg_program_zlp(hsotg, hs_ep); |
5b7d70c6 | 1763 | |
d3ca0259 LM |
1764 | return; |
1765 | } | |
5b7d70c6 BD |
1766 | |
1767 | if (!size_left && hs_req->req.actual < hs_req->req.length) { | |
1768 | dev_dbg(hsotg->dev, "%s trying more for req...\n", __func__); | |
1769 | s3c_hsotg_start_req(hsotg, hs_ep, hs_req, true); | |
fe0b94ab MYK |
1770 | return; |
1771 | } | |
1772 | ||
1773 | if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_DATA_IN) { | |
1774 | /* Move to STATUS OUT */ | |
1775 | s3c_hsotg_ep0_zlp(hsotg, false); | |
1776 | return; | |
1777 | } | |
1778 | ||
1779 | s3c_hsotg_complete_request(hsotg, hs_ep, hs_req, 0); | |
5b7d70c6 BD |
1780 | } |
1781 | ||
1782 | /** | |
1783 | * s3c_hsotg_epint - handle an in/out endpoint interrupt | |
1784 | * @hsotg: The driver state | |
1785 | * @idx: The index for the endpoint (0..15) | |
1786 | * @dir_in: Set if this is an IN endpoint | |
1787 | * | |
1788 | * Process and clear any interrupt pending for an individual endpoint | |
8b9bc460 | 1789 | */ |
941fcce4 | 1790 | static void s3c_hsotg_epint(struct dwc2_hsotg *hsotg, unsigned int idx, |
5b7d70c6 BD |
1791 | int dir_in) |
1792 | { | |
c6f5c050 | 1793 | struct s3c_hsotg_ep *hs_ep = index_to_ep(hsotg, idx, dir_in); |
94cb8fd6 LM |
1794 | u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx); |
1795 | u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx); | |
1796 | u32 epsiz_reg = dir_in ? DIEPTSIZ(idx) : DOEPTSIZ(idx); | |
5b7d70c6 | 1797 | u32 ints; |
1479e841 | 1798 | u32 ctrl; |
5b7d70c6 BD |
1799 | |
1800 | ints = readl(hsotg->regs + epint_reg); | |
1479e841 | 1801 | ctrl = readl(hsotg->regs + epctl_reg); |
5b7d70c6 | 1802 | |
a3395f0d AT |
1803 | /* Clear endpoint interrupts */ |
1804 | writel(ints, hsotg->regs + epint_reg); | |
1805 | ||
c6f5c050 MYK |
1806 | if (!hs_ep) { |
1807 | dev_err(hsotg->dev, "%s:Interrupt for unconfigured ep%d(%s)\n", | |
1808 | __func__, idx, dir_in ? "in" : "out"); | |
1809 | return; | |
1810 | } | |
1811 | ||
5b7d70c6 BD |
1812 | dev_dbg(hsotg->dev, "%s: ep%d(%s) DxEPINT=0x%08x\n", |
1813 | __func__, idx, dir_in ? "in" : "out", ints); | |
1814 | ||
b787d755 MYK |
1815 | /* Don't process XferCompl interrupt if it is a setup packet */ |
1816 | if (idx == 0 && (ints & (DXEPINT_SETUP | DXEPINT_SETUP_RCVD))) | |
1817 | ints &= ~DXEPINT_XFERCOMPL; | |
1818 | ||
47a1685f | 1819 | if (ints & DXEPINT_XFERCOMPL) { |
1479e841 | 1820 | if (hs_ep->isochronous && hs_ep->interval == 1) { |
47a1685f DN |
1821 | if (ctrl & DXEPCTL_EOFRNUM) |
1822 | ctrl |= DXEPCTL_SETEVENFR; | |
1479e841 | 1823 | else |
47a1685f | 1824 | ctrl |= DXEPCTL_SETODDFR; |
1479e841 RB |
1825 | writel(ctrl, hsotg->regs + epctl_reg); |
1826 | } | |
1827 | ||
5b7d70c6 | 1828 | dev_dbg(hsotg->dev, |
47a1685f | 1829 | "%s: XferCompl: DxEPCTL=0x%08x, DXEPTSIZ=%08x\n", |
5b7d70c6 BD |
1830 | __func__, readl(hsotg->regs + epctl_reg), |
1831 | readl(hsotg->regs + epsiz_reg)); | |
1832 | ||
8b9bc460 LM |
1833 | /* |
1834 | * we get OutDone from the FIFO, so we only need to look | |
1835 | * at completing IN requests here | |
1836 | */ | |
5b7d70c6 BD |
1837 | if (dir_in) { |
1838 | s3c_hsotg_complete_in(hsotg, hs_ep); | |
1839 | ||
c9a64ea8 | 1840 | if (idx == 0 && !hs_ep->req) |
5b7d70c6 BD |
1841 | s3c_hsotg_enqueue_setup(hsotg); |
1842 | } else if (using_dma(hsotg)) { | |
8b9bc460 LM |
1843 | /* |
1844 | * We're using DMA, we need to fire an OutDone here | |
1845 | * as we ignore the RXFIFO. | |
1846 | */ | |
5b7d70c6 | 1847 | |
fe0b94ab | 1848 | s3c_hsotg_handle_outdone(hsotg, idx); |
5b7d70c6 | 1849 | } |
5b7d70c6 BD |
1850 | } |
1851 | ||
47a1685f | 1852 | if (ints & DXEPINT_EPDISBLD) { |
5b7d70c6 | 1853 | dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__); |
5b7d70c6 | 1854 | |
9c39ddc6 AT |
1855 | if (dir_in) { |
1856 | int epctl = readl(hsotg->regs + epctl_reg); | |
1857 | ||
b203d0a2 | 1858 | s3c_hsotg_txfifo_flush(hsotg, hs_ep->fifo_index); |
9c39ddc6 | 1859 | |
47a1685f DN |
1860 | if ((epctl & DXEPCTL_STALL) && |
1861 | (epctl & DXEPCTL_EPTYPE_BULK)) { | |
94cb8fd6 | 1862 | int dctl = readl(hsotg->regs + DCTL); |
9c39ddc6 | 1863 | |
47a1685f | 1864 | dctl |= DCTL_CGNPINNAK; |
94cb8fd6 | 1865 | writel(dctl, hsotg->regs + DCTL); |
9c39ddc6 AT |
1866 | } |
1867 | } | |
1868 | } | |
1869 | ||
47a1685f | 1870 | if (ints & DXEPINT_AHBERR) |
5b7d70c6 | 1871 | dev_dbg(hsotg->dev, "%s: AHBErr\n", __func__); |
5b7d70c6 | 1872 | |
47a1685f | 1873 | if (ints & DXEPINT_SETUP) { /* Setup or Timeout */ |
5b7d70c6 BD |
1874 | dev_dbg(hsotg->dev, "%s: Setup/Timeout\n", __func__); |
1875 | ||
1876 | if (using_dma(hsotg) && idx == 0) { | |
8b9bc460 LM |
1877 | /* |
1878 | * this is the notification we've received a | |
5b7d70c6 BD |
1879 | * setup packet. In non-DMA mode we'd get this |
1880 | * from the RXFIFO, instead we need to process | |
8b9bc460 LM |
1881 | * the setup here. |
1882 | */ | |
5b7d70c6 BD |
1883 | |
1884 | if (dir_in) | |
1885 | WARN_ON_ONCE(1); | |
1886 | else | |
fe0b94ab | 1887 | s3c_hsotg_handle_outdone(hsotg, 0); |
5b7d70c6 | 1888 | } |
5b7d70c6 BD |
1889 | } |
1890 | ||
47a1685f | 1891 | if (ints & DXEPINT_BACK2BACKSETUP) |
5b7d70c6 | 1892 | dev_dbg(hsotg->dev, "%s: B2BSetup/INEPNakEff\n", __func__); |
5b7d70c6 | 1893 | |
1479e841 | 1894 | if (dir_in && !hs_ep->isochronous) { |
8b9bc460 | 1895 | /* not sure if this is important, but we'll clear it anyway */ |
47a1685f | 1896 | if (ints & DIEPMSK_INTKNTXFEMPMSK) { |
5b7d70c6 BD |
1897 | dev_dbg(hsotg->dev, "%s: ep%d: INTknTXFEmpMsk\n", |
1898 | __func__, idx); | |
5b7d70c6 BD |
1899 | } |
1900 | ||
1901 | /* this probably means something bad is happening */ | |
47a1685f | 1902 | if (ints & DIEPMSK_INTKNEPMISMSK) { |
5b7d70c6 BD |
1903 | dev_warn(hsotg->dev, "%s: ep%d: INTknEP\n", |
1904 | __func__, idx); | |
5b7d70c6 | 1905 | } |
10aebc77 BD |
1906 | |
1907 | /* FIFO has space or is empty (see GAHBCFG) */ | |
1908 | if (hsotg->dedicated_fifos && | |
47a1685f | 1909 | ints & DIEPMSK_TXFIFOEMPTY) { |
10aebc77 BD |
1910 | dev_dbg(hsotg->dev, "%s: ep%d: TxFIFOEmpty\n", |
1911 | __func__, idx); | |
70fa030f AT |
1912 | if (!using_dma(hsotg)) |
1913 | s3c_hsotg_trytx(hsotg, hs_ep); | |
10aebc77 | 1914 | } |
5b7d70c6 | 1915 | } |
5b7d70c6 BD |
1916 | } |
1917 | ||
1918 | /** | |
1919 | * s3c_hsotg_irq_enumdone - Handle EnumDone interrupt (enumeration done) | |
1920 | * @hsotg: The device state. | |
1921 | * | |
1922 | * Handle updating the device settings after the enumeration phase has | |
1923 | * been completed. | |
8b9bc460 | 1924 | */ |
941fcce4 | 1925 | static void s3c_hsotg_irq_enumdone(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 1926 | { |
94cb8fd6 | 1927 | u32 dsts = readl(hsotg->regs + DSTS); |
9b2667f1 | 1928 | int ep0_mps = 0, ep_mps = 8; |
5b7d70c6 | 1929 | |
8b9bc460 LM |
1930 | /* |
1931 | * This should signal the finish of the enumeration phase | |
5b7d70c6 | 1932 | * of the USB handshaking, so we should now know what rate |
8b9bc460 LM |
1933 | * we connected at. |
1934 | */ | |
5b7d70c6 BD |
1935 | |
1936 | dev_dbg(hsotg->dev, "EnumDone (DSTS=0x%08x)\n", dsts); | |
1937 | ||
8b9bc460 LM |
1938 | /* |
1939 | * note, since we're limited by the size of transfer on EP0, and | |
5b7d70c6 | 1940 | * it seems IN transfers must be a even number of packets we do |
8b9bc460 LM |
1941 | * not advertise a 64byte MPS on EP0. |
1942 | */ | |
5b7d70c6 BD |
1943 | |
1944 | /* catch both EnumSpd_FS and EnumSpd_FS48 */ | |
47a1685f DN |
1945 | switch (dsts & DSTS_ENUMSPD_MASK) { |
1946 | case DSTS_ENUMSPD_FS: | |
1947 | case DSTS_ENUMSPD_FS48: | |
5b7d70c6 | 1948 | hsotg->gadget.speed = USB_SPEED_FULL; |
5b7d70c6 | 1949 | ep0_mps = EP0_MPS_LIMIT; |
295538ff | 1950 | ep_mps = 1023; |
5b7d70c6 BD |
1951 | break; |
1952 | ||
47a1685f | 1953 | case DSTS_ENUMSPD_HS: |
5b7d70c6 | 1954 | hsotg->gadget.speed = USB_SPEED_HIGH; |
5b7d70c6 | 1955 | ep0_mps = EP0_MPS_LIMIT; |
295538ff | 1956 | ep_mps = 1024; |
5b7d70c6 BD |
1957 | break; |
1958 | ||
47a1685f | 1959 | case DSTS_ENUMSPD_LS: |
5b7d70c6 | 1960 | hsotg->gadget.speed = USB_SPEED_LOW; |
8b9bc460 LM |
1961 | /* |
1962 | * note, we don't actually support LS in this driver at the | |
5b7d70c6 BD |
1963 | * moment, and the documentation seems to imply that it isn't |
1964 | * supported by the PHYs on some of the devices. | |
1965 | */ | |
1966 | break; | |
1967 | } | |
e538dfda MN |
1968 | dev_info(hsotg->dev, "new device is %s\n", |
1969 | usb_speed_string(hsotg->gadget.speed)); | |
5b7d70c6 | 1970 | |
8b9bc460 LM |
1971 | /* |
1972 | * we should now know the maximum packet size for an | |
1973 | * endpoint, so set the endpoints to a default value. | |
1974 | */ | |
5b7d70c6 BD |
1975 | |
1976 | if (ep0_mps) { | |
1977 | int i; | |
c6f5c050 MYK |
1978 | /* Initialize ep0 for both in and out directions */ |
1979 | s3c_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 1); | |
1980 | s3c_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 0); | |
1981 | for (i = 1; i < hsotg->num_of_eps; i++) { | |
1982 | if (hsotg->eps_in[i]) | |
1983 | s3c_hsotg_set_ep_maxpacket(hsotg, i, ep_mps, 1); | |
1984 | if (hsotg->eps_out[i]) | |
1985 | s3c_hsotg_set_ep_maxpacket(hsotg, i, ep_mps, 0); | |
1986 | } | |
5b7d70c6 BD |
1987 | } |
1988 | ||
1989 | /* ensure after enumeration our EP0 is active */ | |
1990 | ||
1991 | s3c_hsotg_enqueue_setup(hsotg); | |
1992 | ||
1993 | dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n", | |
94cb8fd6 LM |
1994 | readl(hsotg->regs + DIEPCTL0), |
1995 | readl(hsotg->regs + DOEPCTL0)); | |
5b7d70c6 BD |
1996 | } |
1997 | ||
1998 | /** | |
1999 | * kill_all_requests - remove all requests from the endpoint's queue | |
2000 | * @hsotg: The device state. | |
2001 | * @ep: The endpoint the requests may be on. | |
2002 | * @result: The result code to use. | |
5b7d70c6 BD |
2003 | * |
2004 | * Go through the requests on the given endpoint and mark them | |
2005 | * completed with the given result code. | |
2006 | */ | |
941fcce4 | 2007 | static void kill_all_requests(struct dwc2_hsotg *hsotg, |
5b7d70c6 | 2008 | struct s3c_hsotg_ep *ep, |
6b448af4 | 2009 | int result) |
5b7d70c6 BD |
2010 | { |
2011 | struct s3c_hsotg_req *req, *treq; | |
b203d0a2 | 2012 | unsigned size; |
5b7d70c6 | 2013 | |
6b448af4 | 2014 | ep->req = NULL; |
5b7d70c6 | 2015 | |
6b448af4 | 2016 | list_for_each_entry_safe(req, treq, &ep->queue, queue) |
5b7d70c6 BD |
2017 | s3c_hsotg_complete_request(hsotg, ep, req, |
2018 | result); | |
6b448af4 | 2019 | |
b203d0a2 RB |
2020 | if (!hsotg->dedicated_fifos) |
2021 | return; | |
2022 | size = (readl(hsotg->regs + DTXFSTS(ep->index)) & 0xffff) * 4; | |
2023 | if (size < ep->fifo_size) | |
2024 | s3c_hsotg_txfifo_flush(hsotg, ep->fifo_index); | |
5b7d70c6 BD |
2025 | } |
2026 | ||
5b7d70c6 | 2027 | /** |
5e891342 | 2028 | * s3c_hsotg_disconnect - disconnect service |
5b7d70c6 BD |
2029 | * @hsotg: The device state. |
2030 | * | |
5e891342 LM |
2031 | * The device has been disconnected. Remove all current |
2032 | * transactions and signal the gadget driver that this | |
2033 | * has happened. | |
8b9bc460 | 2034 | */ |
4ace06e8 | 2035 | void s3c_hsotg_disconnect(struct dwc2_hsotg *hsotg) |
5b7d70c6 BD |
2036 | { |
2037 | unsigned ep; | |
2038 | ||
4ace06e8 MS |
2039 | if (!hsotg->connected) |
2040 | return; | |
2041 | ||
2042 | hsotg->connected = 0; | |
c6f5c050 MYK |
2043 | |
2044 | for (ep = 0; ep < hsotg->num_of_eps; ep++) { | |
2045 | if (hsotg->eps_in[ep]) | |
2046 | kill_all_requests(hsotg, hsotg->eps_in[ep], | |
2047 | -ESHUTDOWN); | |
2048 | if (hsotg->eps_out[ep]) | |
2049 | kill_all_requests(hsotg, hsotg->eps_out[ep], | |
2050 | -ESHUTDOWN); | |
2051 | } | |
5b7d70c6 BD |
2052 | |
2053 | call_gadget(hsotg, disconnect); | |
2054 | } | |
4ace06e8 | 2055 | EXPORT_SYMBOL_GPL(s3c_hsotg_disconnect); |
5b7d70c6 BD |
2056 | |
2057 | /** | |
2058 | * s3c_hsotg_irq_fifoempty - TX FIFO empty interrupt handler | |
2059 | * @hsotg: The device state: | |
2060 | * @periodic: True if this is a periodic FIFO interrupt | |
2061 | */ | |
941fcce4 | 2062 | static void s3c_hsotg_irq_fifoempty(struct dwc2_hsotg *hsotg, bool periodic) |
5b7d70c6 BD |
2063 | { |
2064 | struct s3c_hsotg_ep *ep; | |
2065 | int epno, ret; | |
2066 | ||
2067 | /* look through for any more data to transmit */ | |
b3f489b2 | 2068 | for (epno = 0; epno < hsotg->num_of_eps; epno++) { |
c6f5c050 MYK |
2069 | ep = index_to_ep(hsotg, epno, 1); |
2070 | ||
2071 | if (!ep) | |
2072 | continue; | |
5b7d70c6 BD |
2073 | |
2074 | if (!ep->dir_in) | |
2075 | continue; | |
2076 | ||
2077 | if ((periodic && !ep->periodic) || | |
2078 | (!periodic && ep->periodic)) | |
2079 | continue; | |
2080 | ||
2081 | ret = s3c_hsotg_trytx(hsotg, ep); | |
2082 | if (ret < 0) | |
2083 | break; | |
2084 | } | |
2085 | } | |
2086 | ||
5b7d70c6 | 2087 | /* IRQ flags which will trigger a retry around the IRQ loop */ |
47a1685f DN |
2088 | #define IRQ_RETRY_MASK (GINTSTS_NPTXFEMP | \ |
2089 | GINTSTS_PTXFEMP | \ | |
2090 | GINTSTS_RXFLVL) | |
5b7d70c6 | 2091 | |
308d734e LM |
2092 | /** |
2093 | * s3c_hsotg_corereset - issue softreset to the core | |
2094 | * @hsotg: The device state | |
2095 | * | |
2096 | * Issue a soft reset to the core, and await the core finishing it. | |
8b9bc460 | 2097 | */ |
941fcce4 | 2098 | static int s3c_hsotg_corereset(struct dwc2_hsotg *hsotg) |
308d734e LM |
2099 | { |
2100 | int timeout; | |
2101 | u32 grstctl; | |
2102 | ||
2103 | dev_dbg(hsotg->dev, "resetting core\n"); | |
2104 | ||
2105 | /* issue soft reset */ | |
47a1685f | 2106 | writel(GRSTCTL_CSFTRST, hsotg->regs + GRSTCTL); |
308d734e | 2107 | |
2868fea2 | 2108 | timeout = 10000; |
308d734e | 2109 | do { |
94cb8fd6 | 2110 | grstctl = readl(hsotg->regs + GRSTCTL); |
47a1685f | 2111 | } while ((grstctl & GRSTCTL_CSFTRST) && timeout-- > 0); |
308d734e | 2112 | |
47a1685f | 2113 | if (grstctl & GRSTCTL_CSFTRST) { |
308d734e LM |
2114 | dev_err(hsotg->dev, "Failed to get CSftRst asserted\n"); |
2115 | return -EINVAL; | |
2116 | } | |
2117 | ||
2868fea2 | 2118 | timeout = 10000; |
308d734e LM |
2119 | |
2120 | while (1) { | |
94cb8fd6 | 2121 | u32 grstctl = readl(hsotg->regs + GRSTCTL); |
308d734e LM |
2122 | |
2123 | if (timeout-- < 0) { | |
2124 | dev_info(hsotg->dev, | |
2125 | "%s: reset failed, GRSTCTL=%08x\n", | |
2126 | __func__, grstctl); | |
2127 | return -ETIMEDOUT; | |
2128 | } | |
2129 | ||
47a1685f | 2130 | if (!(grstctl & GRSTCTL_AHBIDLE)) |
308d734e LM |
2131 | continue; |
2132 | ||
2133 | break; /* reset done */ | |
2134 | } | |
2135 | ||
2136 | dev_dbg(hsotg->dev, "reset successful\n"); | |
2137 | return 0; | |
2138 | } | |
2139 | ||
8b9bc460 LM |
2140 | /** |
2141 | * s3c_hsotg_core_init - issue softreset to the core | |
2142 | * @hsotg: The device state | |
2143 | * | |
2144 | * Issue a soft reset to the core, and await the core finishing it. | |
2145 | */ | |
510ffaa4 | 2146 | void s3c_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg) |
308d734e LM |
2147 | { |
2148 | s3c_hsotg_corereset(hsotg); | |
2149 | ||
2150 | /* | |
2151 | * we must now enable ep0 ready for host detection and then | |
2152 | * set configuration. | |
2153 | */ | |
2154 | ||
2155 | /* set the PLL on, remove the HNP/SRP and set the PHY */ | |
47a1685f | 2156 | writel(hsotg->phyif | GUSBCFG_TOUTCAL(7) | |
94cb8fd6 | 2157 | (0x5 << 10), hsotg->regs + GUSBCFG); |
308d734e LM |
2158 | |
2159 | s3c_hsotg_init_fifo(hsotg); | |
2160 | ||
47a1685f | 2161 | __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON); |
308d734e | 2162 | |
47a1685f | 2163 | writel(1 << 18 | DCFG_DEVSPD_HS, hsotg->regs + DCFG); |
308d734e LM |
2164 | |
2165 | /* Clear any pending OTG interrupts */ | |
94cb8fd6 | 2166 | writel(0xffffffff, hsotg->regs + GOTGINT); |
308d734e LM |
2167 | |
2168 | /* Clear any pending interrupts */ | |
94cb8fd6 | 2169 | writel(0xffffffff, hsotg->regs + GINTSTS); |
308d734e | 2170 | |
47a1685f DN |
2171 | writel(GINTSTS_ERLYSUSP | GINTSTS_SESSREQINT | |
2172 | GINTSTS_GOUTNAKEFF | GINTSTS_GINNAKEFF | | |
2173 | GINTSTS_CONIDSTSCHNG | GINTSTS_USBRST | | |
2174 | GINTSTS_ENUMDONE | GINTSTS_OTGINT | | |
2175 | GINTSTS_USBSUSP | GINTSTS_WKUPINT, | |
2176 | hsotg->regs + GINTMSK); | |
308d734e LM |
2177 | |
2178 | if (using_dma(hsotg)) | |
47a1685f | 2179 | writel(GAHBCFG_GLBL_INTR_EN | GAHBCFG_DMA_EN | |
5f05048e | 2180 | (GAHBCFG_HBSTLEN_INCR4 << GAHBCFG_HBSTLEN_SHIFT), |
94cb8fd6 | 2181 | hsotg->regs + GAHBCFG); |
308d734e | 2182 | else |
47a1685f DN |
2183 | writel(((hsotg->dedicated_fifos) ? (GAHBCFG_NP_TXF_EMP_LVL | |
2184 | GAHBCFG_P_TXF_EMP_LVL) : 0) | | |
2185 | GAHBCFG_GLBL_INTR_EN, | |
8acc8296 | 2186 | hsotg->regs + GAHBCFG); |
308d734e LM |
2187 | |
2188 | /* | |
8acc8296 RB |
2189 | * If INTknTXFEmpMsk is enabled, it's important to disable ep interrupts |
2190 | * when we have no data to transfer. Otherwise we get being flooded by | |
2191 | * interrupts. | |
308d734e LM |
2192 | */ |
2193 | ||
6ff2e832 MYK |
2194 | writel(((hsotg->dedicated_fifos && !using_dma(hsotg)) ? |
2195 | DIEPMSK_TXFIFOEMPTY | DIEPMSK_INTKNTXFEMPMSK : 0) | | |
47a1685f DN |
2196 | DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK | |
2197 | DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK | | |
2198 | DIEPMSK_INTKNEPMISMSK, | |
2199 | hsotg->regs + DIEPMSK); | |
308d734e LM |
2200 | |
2201 | /* | |
2202 | * don't need XferCompl, we get that from RXFIFO in slave mode. In | |
2203 | * DMA mode we may need this. | |
2204 | */ | |
47a1685f DN |
2205 | writel((using_dma(hsotg) ? (DIEPMSK_XFERCOMPLMSK | |
2206 | DIEPMSK_TIMEOUTMSK) : 0) | | |
2207 | DOEPMSK_EPDISBLDMSK | DOEPMSK_AHBERRMSK | | |
2208 | DOEPMSK_SETUPMSK, | |
2209 | hsotg->regs + DOEPMSK); | |
308d734e | 2210 | |
94cb8fd6 | 2211 | writel(0, hsotg->regs + DAINTMSK); |
308d734e LM |
2212 | |
2213 | dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n", | |
94cb8fd6 LM |
2214 | readl(hsotg->regs + DIEPCTL0), |
2215 | readl(hsotg->regs + DOEPCTL0)); | |
308d734e LM |
2216 | |
2217 | /* enable in and out endpoint interrupts */ | |
47a1685f | 2218 | s3c_hsotg_en_gsint(hsotg, GINTSTS_OEPINT | GINTSTS_IEPINT); |
308d734e LM |
2219 | |
2220 | /* | |
2221 | * Enable the RXFIFO when in slave mode, as this is how we collect | |
2222 | * the data. In DMA mode, we get events from the FIFO but also | |
2223 | * things we cannot process, so do not use it. | |
2224 | */ | |
2225 | if (!using_dma(hsotg)) | |
47a1685f | 2226 | s3c_hsotg_en_gsint(hsotg, GINTSTS_RXFLVL); |
308d734e LM |
2227 | |
2228 | /* Enable interrupts for EP0 in and out */ | |
2229 | s3c_hsotg_ctrl_epint(hsotg, 0, 0, 1); | |
2230 | s3c_hsotg_ctrl_epint(hsotg, 0, 1, 1); | |
2231 | ||
47a1685f | 2232 | __orr32(hsotg->regs + DCTL, DCTL_PWRONPRGDONE); |
308d734e | 2233 | udelay(10); /* see openiboot */ |
47a1685f | 2234 | __bic32(hsotg->regs + DCTL, DCTL_PWRONPRGDONE); |
308d734e | 2235 | |
94cb8fd6 | 2236 | dev_dbg(hsotg->dev, "DCTL=0x%08x\n", readl(hsotg->regs + DCTL)); |
308d734e LM |
2237 | |
2238 | /* | |
94cb8fd6 | 2239 | * DxEPCTL_USBActEp says RO in manual, but seems to be set by |
308d734e LM |
2240 | * writing to the EPCTL register.. |
2241 | */ | |
2242 | ||
2243 | /* set to read 1 8byte packet */ | |
47a1685f DN |
2244 | writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) | |
2245 | DXEPTSIZ_XFERSIZE(8), hsotg->regs + DOEPTSIZ0); | |
308d734e | 2246 | |
c6f5c050 | 2247 | writel(s3c_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) | |
47a1685f DN |
2248 | DXEPCTL_CNAK | DXEPCTL_EPENA | |
2249 | DXEPCTL_USBACTEP, | |
94cb8fd6 | 2250 | hsotg->regs + DOEPCTL0); |
308d734e LM |
2251 | |
2252 | /* enable, but don't activate EP0in */ | |
c6f5c050 | 2253 | writel(s3c_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) | |
47a1685f | 2254 | DXEPCTL_USBACTEP, hsotg->regs + DIEPCTL0); |
308d734e LM |
2255 | |
2256 | s3c_hsotg_enqueue_setup(hsotg); | |
2257 | ||
2258 | dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n", | |
94cb8fd6 LM |
2259 | readl(hsotg->regs + DIEPCTL0), |
2260 | readl(hsotg->regs + DOEPCTL0)); | |
308d734e LM |
2261 | |
2262 | /* clear global NAKs */ | |
ad38dc5d | 2263 | writel(DCTL_CGOUTNAK | DCTL_CGNPINNAK | DCTL_SFTDISCON, |
94cb8fd6 | 2264 | hsotg->regs + DCTL); |
308d734e LM |
2265 | |
2266 | /* must be at-least 3ms to allow bus to see disconnect */ | |
2267 | mdelay(3); | |
2268 | ||
ac3c81f3 | 2269 | hsotg->last_rst = jiffies; |
ad38dc5d MS |
2270 | } |
2271 | ||
941fcce4 | 2272 | static void s3c_hsotg_core_disconnect(struct dwc2_hsotg *hsotg) |
ad38dc5d MS |
2273 | { |
2274 | /* set the soft-disconnect bit */ | |
2275 | __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON); | |
2276 | } | |
ac3c81f3 | 2277 | |
510ffaa4 | 2278 | void s3c_hsotg_core_connect(struct dwc2_hsotg *hsotg) |
ad38dc5d | 2279 | { |
308d734e | 2280 | /* remove the soft-disconnect and let's go */ |
47a1685f | 2281 | __bic32(hsotg->regs + DCTL, DCTL_SFTDISCON); |
308d734e LM |
2282 | } |
2283 | ||
5b7d70c6 BD |
2284 | /** |
2285 | * s3c_hsotg_irq - handle device interrupt | |
2286 | * @irq: The IRQ number triggered | |
2287 | * @pw: The pw value when registered the handler. | |
2288 | */ | |
2289 | static irqreturn_t s3c_hsotg_irq(int irq, void *pw) | |
2290 | { | |
941fcce4 | 2291 | struct dwc2_hsotg *hsotg = pw; |
5b7d70c6 BD |
2292 | int retry_count = 8; |
2293 | u32 gintsts; | |
2294 | u32 gintmsk; | |
2295 | ||
5ad1d316 | 2296 | spin_lock(&hsotg->lock); |
5b7d70c6 | 2297 | irq_retry: |
94cb8fd6 LM |
2298 | gintsts = readl(hsotg->regs + GINTSTS); |
2299 | gintmsk = readl(hsotg->regs + GINTMSK); | |
5b7d70c6 BD |
2300 | |
2301 | dev_dbg(hsotg->dev, "%s: %08x %08x (%08x) retry %d\n", | |
2302 | __func__, gintsts, gintsts & gintmsk, gintmsk, retry_count); | |
2303 | ||
2304 | gintsts &= gintmsk; | |
2305 | ||
47a1685f DN |
2306 | if (gintsts & GINTSTS_ENUMDONE) { |
2307 | writel(GINTSTS_ENUMDONE, hsotg->regs + GINTSTS); | |
a3395f0d AT |
2308 | |
2309 | s3c_hsotg_irq_enumdone(hsotg); | |
4ace06e8 | 2310 | hsotg->connected = 1; |
5b7d70c6 BD |
2311 | } |
2312 | ||
47a1685f | 2313 | if (gintsts & (GINTSTS_OEPINT | GINTSTS_IEPINT)) { |
94cb8fd6 | 2314 | u32 daint = readl(hsotg->regs + DAINT); |
7e804650 RB |
2315 | u32 daintmsk = readl(hsotg->regs + DAINTMSK); |
2316 | u32 daint_out, daint_in; | |
5b7d70c6 BD |
2317 | int ep; |
2318 | ||
7e804650 | 2319 | daint &= daintmsk; |
47a1685f DN |
2320 | daint_out = daint >> DAINT_OUTEP_SHIFT; |
2321 | daint_in = daint & ~(daint_out << DAINT_OUTEP_SHIFT); | |
7e804650 | 2322 | |
5b7d70c6 BD |
2323 | dev_dbg(hsotg->dev, "%s: daint=%08x\n", __func__, daint); |
2324 | ||
cec87f1d MYK |
2325 | for (ep = 0; ep < hsotg->num_of_eps && daint_out; |
2326 | ep++, daint_out >>= 1) { | |
5b7d70c6 BD |
2327 | if (daint_out & 1) |
2328 | s3c_hsotg_epint(hsotg, ep, 0); | |
2329 | } | |
2330 | ||
cec87f1d MYK |
2331 | for (ep = 0; ep < hsotg->num_of_eps && daint_in; |
2332 | ep++, daint_in >>= 1) { | |
5b7d70c6 BD |
2333 | if (daint_in & 1) |
2334 | s3c_hsotg_epint(hsotg, ep, 1); | |
2335 | } | |
5b7d70c6 BD |
2336 | } |
2337 | ||
47a1685f | 2338 | if (gintsts & GINTSTS_USBRST) { |
12a1f4dc | 2339 | |
94cb8fd6 | 2340 | u32 usb_status = readl(hsotg->regs + GOTGCTL); |
12a1f4dc | 2341 | |
9599815d | 2342 | dev_dbg(hsotg->dev, "%s: USBRst\n", __func__); |
5b7d70c6 | 2343 | dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n", |
94cb8fd6 | 2344 | readl(hsotg->regs + GNPTXSTS)); |
5b7d70c6 | 2345 | |
47a1685f | 2346 | writel(GINTSTS_USBRST, hsotg->regs + GINTSTS); |
a3395f0d | 2347 | |
94cb8fd6 | 2348 | if (usb_status & GOTGCTL_BSESVLD) { |
12a1f4dc LM |
2349 | if (time_after(jiffies, hsotg->last_rst + |
2350 | msecs_to_jiffies(200))) { | |
5b7d70c6 | 2351 | |
c6f5c050 | 2352 | kill_all_requests(hsotg, hsotg->eps_out[0], |
6b448af4 | 2353 | -ECONNRESET); |
5b7d70c6 | 2354 | |
ad38dc5d MS |
2355 | s3c_hsotg_core_init_disconnected(hsotg); |
2356 | s3c_hsotg_core_connect(hsotg); | |
12a1f4dc LM |
2357 | } |
2358 | } | |
5b7d70c6 BD |
2359 | } |
2360 | ||
2361 | /* check both FIFOs */ | |
2362 | ||
47a1685f | 2363 | if (gintsts & GINTSTS_NPTXFEMP) { |
5b7d70c6 BD |
2364 | dev_dbg(hsotg->dev, "NPTxFEmp\n"); |
2365 | ||
8b9bc460 LM |
2366 | /* |
2367 | * Disable the interrupt to stop it happening again | |
5b7d70c6 | 2368 | * unless one of these endpoint routines decides that |
8b9bc460 LM |
2369 | * it needs re-enabling |
2370 | */ | |
5b7d70c6 | 2371 | |
47a1685f | 2372 | s3c_hsotg_disable_gsint(hsotg, GINTSTS_NPTXFEMP); |
5b7d70c6 | 2373 | s3c_hsotg_irq_fifoempty(hsotg, false); |
5b7d70c6 BD |
2374 | } |
2375 | ||
47a1685f | 2376 | if (gintsts & GINTSTS_PTXFEMP) { |
5b7d70c6 BD |
2377 | dev_dbg(hsotg->dev, "PTxFEmp\n"); |
2378 | ||
94cb8fd6 | 2379 | /* See note in GINTSTS_NPTxFEmp */ |
5b7d70c6 | 2380 | |
47a1685f | 2381 | s3c_hsotg_disable_gsint(hsotg, GINTSTS_PTXFEMP); |
5b7d70c6 | 2382 | s3c_hsotg_irq_fifoempty(hsotg, true); |
5b7d70c6 BD |
2383 | } |
2384 | ||
47a1685f | 2385 | if (gintsts & GINTSTS_RXFLVL) { |
8b9bc460 LM |
2386 | /* |
2387 | * note, since GINTSTS_RxFLvl doubles as FIFO-not-empty, | |
5b7d70c6 | 2388 | * we need to retry s3c_hsotg_handle_rx if this is still |
8b9bc460 LM |
2389 | * set. |
2390 | */ | |
5b7d70c6 BD |
2391 | |
2392 | s3c_hsotg_handle_rx(hsotg); | |
5b7d70c6 BD |
2393 | } |
2394 | ||
47a1685f | 2395 | if (gintsts & GINTSTS_ERLYSUSP) { |
94cb8fd6 | 2396 | dev_dbg(hsotg->dev, "GINTSTS_ErlySusp\n"); |
47a1685f | 2397 | writel(GINTSTS_ERLYSUSP, hsotg->regs + GINTSTS); |
5b7d70c6 BD |
2398 | } |
2399 | ||
8b9bc460 LM |
2400 | /* |
2401 | * these next two seem to crop-up occasionally causing the core | |
5b7d70c6 | 2402 | * to shutdown the USB transfer, so try clearing them and logging |
8b9bc460 LM |
2403 | * the occurrence. |
2404 | */ | |
5b7d70c6 | 2405 | |
47a1685f | 2406 | if (gintsts & GINTSTS_GOUTNAKEFF) { |
5b7d70c6 BD |
2407 | dev_info(hsotg->dev, "GOUTNakEff triggered\n"); |
2408 | ||
47a1685f | 2409 | writel(DCTL_CGOUTNAK, hsotg->regs + DCTL); |
a3395f0d AT |
2410 | |
2411 | s3c_hsotg_dump(hsotg); | |
5b7d70c6 BD |
2412 | } |
2413 | ||
47a1685f | 2414 | if (gintsts & GINTSTS_GINNAKEFF) { |
5b7d70c6 BD |
2415 | dev_info(hsotg->dev, "GINNakEff triggered\n"); |
2416 | ||
47a1685f | 2417 | writel(DCTL_CGNPINNAK, hsotg->regs + DCTL); |
a3395f0d AT |
2418 | |
2419 | s3c_hsotg_dump(hsotg); | |
5b7d70c6 BD |
2420 | } |
2421 | ||
8b9bc460 LM |
2422 | /* |
2423 | * if we've had fifo events, we should try and go around the | |
2424 | * loop again to see if there's any point in returning yet. | |
2425 | */ | |
5b7d70c6 BD |
2426 | |
2427 | if (gintsts & IRQ_RETRY_MASK && --retry_count > 0) | |
2428 | goto irq_retry; | |
2429 | ||
5ad1d316 LM |
2430 | spin_unlock(&hsotg->lock); |
2431 | ||
5b7d70c6 BD |
2432 | return IRQ_HANDLED; |
2433 | } | |
2434 | ||
2435 | /** | |
2436 | * s3c_hsotg_ep_enable - enable the given endpoint | |
2437 | * @ep: The USB endpint to configure | |
2438 | * @desc: The USB endpoint descriptor to configure with. | |
2439 | * | |
2440 | * This is called from the USB gadget code's usb_ep_enable(). | |
8b9bc460 | 2441 | */ |
5b7d70c6 BD |
2442 | static int s3c_hsotg_ep_enable(struct usb_ep *ep, |
2443 | const struct usb_endpoint_descriptor *desc) | |
2444 | { | |
2445 | struct s3c_hsotg_ep *hs_ep = our_ep(ep); | |
941fcce4 | 2446 | struct dwc2_hsotg *hsotg = hs_ep->parent; |
5b7d70c6 BD |
2447 | unsigned long flags; |
2448 | int index = hs_ep->index; | |
2449 | u32 epctrl_reg; | |
2450 | u32 epctrl; | |
2451 | u32 mps; | |
2452 | int dir_in; | |
b203d0a2 | 2453 | int i, val, size; |
19c190f9 | 2454 | int ret = 0; |
5b7d70c6 BD |
2455 | |
2456 | dev_dbg(hsotg->dev, | |
2457 | "%s: ep %s: a 0x%02x, attr 0x%02x, mps 0x%04x, intr %d\n", | |
2458 | __func__, ep->name, desc->bEndpointAddress, desc->bmAttributes, | |
2459 | desc->wMaxPacketSize, desc->bInterval); | |
2460 | ||
2461 | /* not to be called for EP0 */ | |
2462 | WARN_ON(index == 0); | |
2463 | ||
2464 | dir_in = (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) ? 1 : 0; | |
2465 | if (dir_in != hs_ep->dir_in) { | |
2466 | dev_err(hsotg->dev, "%s: direction mismatch!\n", __func__); | |
2467 | return -EINVAL; | |
2468 | } | |
2469 | ||
29cc8897 | 2470 | mps = usb_endpoint_maxp(desc); |
5b7d70c6 BD |
2471 | |
2472 | /* note, we handle this here instead of s3c_hsotg_set_ep_maxpacket */ | |
2473 | ||
94cb8fd6 | 2474 | epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index); |
5b7d70c6 BD |
2475 | epctrl = readl(hsotg->regs + epctrl_reg); |
2476 | ||
2477 | dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x from 0x%08x\n", | |
2478 | __func__, epctrl, epctrl_reg); | |
2479 | ||
22258f49 | 2480 | spin_lock_irqsave(&hsotg->lock, flags); |
5b7d70c6 | 2481 | |
47a1685f DN |
2482 | epctrl &= ~(DXEPCTL_EPTYPE_MASK | DXEPCTL_MPS_MASK); |
2483 | epctrl |= DXEPCTL_MPS(mps); | |
5b7d70c6 | 2484 | |
8b9bc460 LM |
2485 | /* |
2486 | * mark the endpoint as active, otherwise the core may ignore | |
2487 | * transactions entirely for this endpoint | |
2488 | */ | |
47a1685f | 2489 | epctrl |= DXEPCTL_USBACTEP; |
5b7d70c6 | 2490 | |
8b9bc460 LM |
2491 | /* |
2492 | * set the NAK status on the endpoint, otherwise we might try and | |
5b7d70c6 BD |
2493 | * do something with data that we've yet got a request to process |
2494 | * since the RXFIFO will take data for an endpoint even if the | |
2495 | * size register hasn't been set. | |
2496 | */ | |
2497 | ||
47a1685f | 2498 | epctrl |= DXEPCTL_SNAK; |
5b7d70c6 BD |
2499 | |
2500 | /* update the endpoint state */ | |
c6f5c050 | 2501 | s3c_hsotg_set_ep_maxpacket(hsotg, hs_ep->index, mps, dir_in); |
5b7d70c6 BD |
2502 | |
2503 | /* default, set to non-periodic */ | |
1479e841 | 2504 | hs_ep->isochronous = 0; |
5b7d70c6 | 2505 | hs_ep->periodic = 0; |
a18ed7b0 | 2506 | hs_ep->halted = 0; |
1479e841 | 2507 | hs_ep->interval = desc->bInterval; |
5b7d70c6 | 2508 | |
4fca54aa RB |
2509 | if (hs_ep->interval > 1 && hs_ep->mc > 1) |
2510 | dev_err(hsotg->dev, "MC > 1 when interval is not 1\n"); | |
2511 | ||
5b7d70c6 BD |
2512 | switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) { |
2513 | case USB_ENDPOINT_XFER_ISOC: | |
47a1685f DN |
2514 | epctrl |= DXEPCTL_EPTYPE_ISO; |
2515 | epctrl |= DXEPCTL_SETEVENFR; | |
1479e841 RB |
2516 | hs_ep->isochronous = 1; |
2517 | if (dir_in) | |
2518 | hs_ep->periodic = 1; | |
2519 | break; | |
5b7d70c6 BD |
2520 | |
2521 | case USB_ENDPOINT_XFER_BULK: | |
47a1685f | 2522 | epctrl |= DXEPCTL_EPTYPE_BULK; |
5b7d70c6 BD |
2523 | break; |
2524 | ||
2525 | case USB_ENDPOINT_XFER_INT: | |
b203d0a2 | 2526 | if (dir_in) |
5b7d70c6 | 2527 | hs_ep->periodic = 1; |
5b7d70c6 | 2528 | |
47a1685f | 2529 | epctrl |= DXEPCTL_EPTYPE_INTERRUPT; |
5b7d70c6 BD |
2530 | break; |
2531 | ||
2532 | case USB_ENDPOINT_XFER_CONTROL: | |
47a1685f | 2533 | epctrl |= DXEPCTL_EPTYPE_CONTROL; |
5b7d70c6 BD |
2534 | break; |
2535 | } | |
2536 | ||
8b9bc460 LM |
2537 | /* |
2538 | * if the hardware has dedicated fifos, we must give each IN EP | |
10aebc77 BD |
2539 | * a unique tx-fifo even if it is non-periodic. |
2540 | */ | |
b203d0a2 RB |
2541 | if (dir_in && hsotg->dedicated_fifos) { |
2542 | size = hs_ep->ep.maxpacket*hs_ep->mc; | |
5f2196bd | 2543 | for (i = 1; i < hsotg->num_of_eps; ++i) { |
b203d0a2 RB |
2544 | if (hsotg->fifo_map & (1<<i)) |
2545 | continue; | |
2546 | val = readl(hsotg->regs + DPTXFSIZN(i)); | |
2547 | val = (val >> FIFOSIZE_DEPTH_SHIFT)*4; | |
2548 | if (val < size) | |
2549 | continue; | |
2550 | hsotg->fifo_map |= 1<<i; | |
2551 | ||
2552 | epctrl |= DXEPCTL_TXFNUM(i); | |
2553 | hs_ep->fifo_index = i; | |
2554 | hs_ep->fifo_size = val; | |
2555 | break; | |
2556 | } | |
5f2196bd MYK |
2557 | if (i == hsotg->num_of_eps) { |
2558 | dev_err(hsotg->dev, | |
2559 | "%s: No suitable fifo found\n", __func__); | |
b585a48b SM |
2560 | ret = -ENOMEM; |
2561 | goto error; | |
2562 | } | |
b203d0a2 | 2563 | } |
10aebc77 | 2564 | |
5b7d70c6 BD |
2565 | /* for non control endpoints, set PID to D0 */ |
2566 | if (index) | |
47a1685f | 2567 | epctrl |= DXEPCTL_SETD0PID; |
5b7d70c6 BD |
2568 | |
2569 | dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n", | |
2570 | __func__, epctrl); | |
2571 | ||
2572 | writel(epctrl, hsotg->regs + epctrl_reg); | |
2573 | dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x\n", | |
2574 | __func__, readl(hsotg->regs + epctrl_reg)); | |
2575 | ||
2576 | /* enable the endpoint interrupt */ | |
2577 | s3c_hsotg_ctrl_epint(hsotg, index, dir_in, 1); | |
2578 | ||
b585a48b | 2579 | error: |
22258f49 | 2580 | spin_unlock_irqrestore(&hsotg->lock, flags); |
19c190f9 | 2581 | return ret; |
5b7d70c6 BD |
2582 | } |
2583 | ||
8b9bc460 LM |
2584 | /** |
2585 | * s3c_hsotg_ep_disable - disable given endpoint | |
2586 | * @ep: The endpoint to disable. | |
2587 | */ | |
5b7d70c6 BD |
2588 | static int s3c_hsotg_ep_disable(struct usb_ep *ep) |
2589 | { | |
2590 | struct s3c_hsotg_ep *hs_ep = our_ep(ep); | |
941fcce4 | 2591 | struct dwc2_hsotg *hsotg = hs_ep->parent; |
5b7d70c6 BD |
2592 | int dir_in = hs_ep->dir_in; |
2593 | int index = hs_ep->index; | |
2594 | unsigned long flags; | |
2595 | u32 epctrl_reg; | |
2596 | u32 ctrl; | |
2597 | ||
1e011293 | 2598 | dev_dbg(hsotg->dev, "%s(ep %p)\n", __func__, ep); |
5b7d70c6 | 2599 | |
c6f5c050 | 2600 | if (ep == &hsotg->eps_out[0]->ep) { |
5b7d70c6 BD |
2601 | dev_err(hsotg->dev, "%s: called for ep0\n", __func__); |
2602 | return -EINVAL; | |
2603 | } | |
2604 | ||
94cb8fd6 | 2605 | epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index); |
5b7d70c6 | 2606 | |
5ad1d316 | 2607 | spin_lock_irqsave(&hsotg->lock, flags); |
5b7d70c6 | 2608 | |
b203d0a2 RB |
2609 | hsotg->fifo_map &= ~(1<<hs_ep->fifo_index); |
2610 | hs_ep->fifo_index = 0; | |
2611 | hs_ep->fifo_size = 0; | |
5b7d70c6 BD |
2612 | |
2613 | ctrl = readl(hsotg->regs + epctrl_reg); | |
47a1685f DN |
2614 | ctrl &= ~DXEPCTL_EPENA; |
2615 | ctrl &= ~DXEPCTL_USBACTEP; | |
2616 | ctrl |= DXEPCTL_SNAK; | |
5b7d70c6 BD |
2617 | |
2618 | dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl); | |
2619 | writel(ctrl, hsotg->regs + epctrl_reg); | |
2620 | ||
2621 | /* disable endpoint interrupts */ | |
2622 | s3c_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 0); | |
2623 | ||
1141ea01 MYK |
2624 | /* terminate all requests with shutdown */ |
2625 | kill_all_requests(hsotg, hs_ep, -ESHUTDOWN); | |
2626 | ||
22258f49 | 2627 | spin_unlock_irqrestore(&hsotg->lock, flags); |
5b7d70c6 BD |
2628 | return 0; |
2629 | } | |
2630 | ||
2631 | /** | |
2632 | * on_list - check request is on the given endpoint | |
2633 | * @ep: The endpoint to check. | |
2634 | * @test: The request to test if it is on the endpoint. | |
8b9bc460 | 2635 | */ |
5b7d70c6 BD |
2636 | static bool on_list(struct s3c_hsotg_ep *ep, struct s3c_hsotg_req *test) |
2637 | { | |
2638 | struct s3c_hsotg_req *req, *treq; | |
2639 | ||
2640 | list_for_each_entry_safe(req, treq, &ep->queue, queue) { | |
2641 | if (req == test) | |
2642 | return true; | |
2643 | } | |
2644 | ||
2645 | return false; | |
2646 | } | |
2647 | ||
8b9bc460 LM |
2648 | /** |
2649 | * s3c_hsotg_ep_dequeue - dequeue given endpoint | |
2650 | * @ep: The endpoint to dequeue. | |
2651 | * @req: The request to be removed from a queue. | |
2652 | */ | |
5b7d70c6 BD |
2653 | static int s3c_hsotg_ep_dequeue(struct usb_ep *ep, struct usb_request *req) |
2654 | { | |
2655 | struct s3c_hsotg_req *hs_req = our_req(req); | |
2656 | struct s3c_hsotg_ep *hs_ep = our_ep(ep); | |
941fcce4 | 2657 | struct dwc2_hsotg *hs = hs_ep->parent; |
5b7d70c6 BD |
2658 | unsigned long flags; |
2659 | ||
1e011293 | 2660 | dev_dbg(hs->dev, "ep_dequeue(%p,%p)\n", ep, req); |
5b7d70c6 | 2661 | |
22258f49 | 2662 | spin_lock_irqsave(&hs->lock, flags); |
5b7d70c6 BD |
2663 | |
2664 | if (!on_list(hs_ep, hs_req)) { | |
22258f49 | 2665 | spin_unlock_irqrestore(&hs->lock, flags); |
5b7d70c6 BD |
2666 | return -EINVAL; |
2667 | } | |
2668 | ||
2669 | s3c_hsotg_complete_request(hs, hs_ep, hs_req, -ECONNRESET); | |
22258f49 | 2670 | spin_unlock_irqrestore(&hs->lock, flags); |
5b7d70c6 BD |
2671 | |
2672 | return 0; | |
2673 | } | |
2674 | ||
8b9bc460 LM |
2675 | /** |
2676 | * s3c_hsotg_ep_sethalt - set halt on a given endpoint | |
2677 | * @ep: The endpoint to set halt. | |
2678 | * @value: Set or unset the halt. | |
2679 | */ | |
5b7d70c6 BD |
2680 | static int s3c_hsotg_ep_sethalt(struct usb_ep *ep, int value) |
2681 | { | |
2682 | struct s3c_hsotg_ep *hs_ep = our_ep(ep); | |
941fcce4 | 2683 | struct dwc2_hsotg *hs = hs_ep->parent; |
5b7d70c6 | 2684 | int index = hs_ep->index; |
5b7d70c6 BD |
2685 | u32 epreg; |
2686 | u32 epctl; | |
9c39ddc6 | 2687 | u32 xfertype; |
5b7d70c6 BD |
2688 | |
2689 | dev_info(hs->dev, "%s(ep %p %s, %d)\n", __func__, ep, ep->name, value); | |
2690 | ||
c9f721b2 RB |
2691 | if (index == 0) { |
2692 | if (value) | |
2693 | s3c_hsotg_stall_ep0(hs); | |
2694 | else | |
2695 | dev_warn(hs->dev, | |
2696 | "%s: can't clear halt on ep0\n", __func__); | |
2697 | return 0; | |
2698 | } | |
2699 | ||
c6f5c050 MYK |
2700 | if (hs_ep->dir_in) { |
2701 | epreg = DIEPCTL(index); | |
2702 | epctl = readl(hs->regs + epreg); | |
2703 | ||
2704 | if (value) { | |
2705 | epctl |= DXEPCTL_STALL + DXEPCTL_SNAK; | |
2706 | if (epctl & DXEPCTL_EPENA) | |
2707 | epctl |= DXEPCTL_EPDIS; | |
2708 | } else { | |
2709 | epctl &= ~DXEPCTL_STALL; | |
2710 | xfertype = epctl & DXEPCTL_EPTYPE_MASK; | |
2711 | if (xfertype == DXEPCTL_EPTYPE_BULK || | |
2712 | xfertype == DXEPCTL_EPTYPE_INTERRUPT) | |
2713 | epctl |= DXEPCTL_SETD0PID; | |
2714 | } | |
2715 | writel(epctl, hs->regs + epreg); | |
9c39ddc6 | 2716 | } else { |
5b7d70c6 | 2717 | |
c6f5c050 MYK |
2718 | epreg = DOEPCTL(index); |
2719 | epctl = readl(hs->regs + epreg); | |
5b7d70c6 | 2720 | |
c6f5c050 MYK |
2721 | if (value) |
2722 | epctl |= DXEPCTL_STALL; | |
2723 | else { | |
2724 | epctl &= ~DXEPCTL_STALL; | |
2725 | xfertype = epctl & DXEPCTL_EPTYPE_MASK; | |
2726 | if (xfertype == DXEPCTL_EPTYPE_BULK || | |
2727 | xfertype == DXEPCTL_EPTYPE_INTERRUPT) | |
2728 | epctl |= DXEPCTL_SETD0PID; | |
2729 | } | |
2730 | writel(epctl, hs->regs + epreg); | |
9c39ddc6 | 2731 | } |
5b7d70c6 | 2732 | |
a18ed7b0 RB |
2733 | hs_ep->halted = value; |
2734 | ||
5b7d70c6 BD |
2735 | return 0; |
2736 | } | |
2737 | ||
5ad1d316 LM |
2738 | /** |
2739 | * s3c_hsotg_ep_sethalt_lock - set halt on a given endpoint with lock held | |
2740 | * @ep: The endpoint to set halt. | |
2741 | * @value: Set or unset the halt. | |
2742 | */ | |
2743 | static int s3c_hsotg_ep_sethalt_lock(struct usb_ep *ep, int value) | |
2744 | { | |
2745 | struct s3c_hsotg_ep *hs_ep = our_ep(ep); | |
941fcce4 | 2746 | struct dwc2_hsotg *hs = hs_ep->parent; |
5ad1d316 LM |
2747 | unsigned long flags = 0; |
2748 | int ret = 0; | |
2749 | ||
2750 | spin_lock_irqsave(&hs->lock, flags); | |
2751 | ret = s3c_hsotg_ep_sethalt(ep, value); | |
2752 | spin_unlock_irqrestore(&hs->lock, flags); | |
2753 | ||
2754 | return ret; | |
2755 | } | |
2756 | ||
5b7d70c6 BD |
2757 | static struct usb_ep_ops s3c_hsotg_ep_ops = { |
2758 | .enable = s3c_hsotg_ep_enable, | |
2759 | .disable = s3c_hsotg_ep_disable, | |
2760 | .alloc_request = s3c_hsotg_ep_alloc_request, | |
2761 | .free_request = s3c_hsotg_ep_free_request, | |
5ad1d316 | 2762 | .queue = s3c_hsotg_ep_queue_lock, |
5b7d70c6 | 2763 | .dequeue = s3c_hsotg_ep_dequeue, |
5ad1d316 | 2764 | .set_halt = s3c_hsotg_ep_sethalt_lock, |
25985edc | 2765 | /* note, don't believe we have any call for the fifo routines */ |
5b7d70c6 BD |
2766 | }; |
2767 | ||
41188786 LM |
2768 | /** |
2769 | * s3c_hsotg_phy_enable - enable platform phy dev | |
8b9bc460 | 2770 | * @hsotg: The driver state |
41188786 LM |
2771 | * |
2772 | * A wrapper for platform code responsible for controlling | |
2773 | * low-level USB code | |
2774 | */ | |
941fcce4 | 2775 | static void s3c_hsotg_phy_enable(struct dwc2_hsotg *hsotg) |
41188786 LM |
2776 | { |
2777 | struct platform_device *pdev = to_platform_device(hsotg->dev); | |
2778 | ||
2779 | dev_dbg(hsotg->dev, "pdev 0x%p\n", pdev); | |
b2e587db | 2780 | |
ca2c5ba8 | 2781 | if (hsotg->uphy) |
74084844 | 2782 | usb_phy_init(hsotg->uphy); |
ca2c5ba8 | 2783 | else if (hsotg->plat && hsotg->plat->phy_init) |
41188786 | 2784 | hsotg->plat->phy_init(pdev, hsotg->plat->phy_type); |
ca2c5ba8 KD |
2785 | else { |
2786 | phy_init(hsotg->phy); | |
2787 | phy_power_on(hsotg->phy); | |
2788 | } | |
41188786 LM |
2789 | } |
2790 | ||
2791 | /** | |
2792 | * s3c_hsotg_phy_disable - disable platform phy dev | |
8b9bc460 | 2793 | * @hsotg: The driver state |
41188786 LM |
2794 | * |
2795 | * A wrapper for platform code responsible for controlling | |
2796 | * low-level USB code | |
2797 | */ | |
941fcce4 | 2798 | static void s3c_hsotg_phy_disable(struct dwc2_hsotg *hsotg) |
41188786 LM |
2799 | { |
2800 | struct platform_device *pdev = to_platform_device(hsotg->dev); | |
2801 | ||
ca2c5ba8 | 2802 | if (hsotg->uphy) |
74084844 | 2803 | usb_phy_shutdown(hsotg->uphy); |
ca2c5ba8 | 2804 | else if (hsotg->plat && hsotg->plat->phy_exit) |
41188786 | 2805 | hsotg->plat->phy_exit(pdev, hsotg->plat->phy_type); |
ca2c5ba8 KD |
2806 | else { |
2807 | phy_power_off(hsotg->phy); | |
2808 | phy_exit(hsotg->phy); | |
2809 | } | |
41188786 LM |
2810 | } |
2811 | ||
8b9bc460 LM |
2812 | /** |
2813 | * s3c_hsotg_init - initalize the usb core | |
2814 | * @hsotg: The driver state | |
2815 | */ | |
941fcce4 | 2816 | static void s3c_hsotg_init(struct dwc2_hsotg *hsotg) |
b3f489b2 LM |
2817 | { |
2818 | /* unmask subset of endpoint interrupts */ | |
2819 | ||
47a1685f DN |
2820 | writel(DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK | |
2821 | DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK, | |
2822 | hsotg->regs + DIEPMSK); | |
b3f489b2 | 2823 | |
47a1685f DN |
2824 | writel(DOEPMSK_SETUPMSK | DOEPMSK_AHBERRMSK | |
2825 | DOEPMSK_EPDISBLDMSK | DOEPMSK_XFERCOMPLMSK, | |
2826 | hsotg->regs + DOEPMSK); | |
b3f489b2 | 2827 | |
94cb8fd6 | 2828 | writel(0, hsotg->regs + DAINTMSK); |
b3f489b2 LM |
2829 | |
2830 | /* Be in disconnected state until gadget is registered */ | |
47a1685f | 2831 | __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON); |
b3f489b2 LM |
2832 | |
2833 | if (0) { | |
2834 | /* post global nak until we're ready */ | |
47a1685f | 2835 | writel(DCTL_SGNPINNAK | DCTL_SGOUTNAK, |
94cb8fd6 | 2836 | hsotg->regs + DCTL); |
b3f489b2 LM |
2837 | } |
2838 | ||
2839 | /* setup fifos */ | |
2840 | ||
2841 | dev_dbg(hsotg->dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n", | |
94cb8fd6 LM |
2842 | readl(hsotg->regs + GRXFSIZ), |
2843 | readl(hsotg->regs + GNPTXFSIZ)); | |
b3f489b2 LM |
2844 | |
2845 | s3c_hsotg_init_fifo(hsotg); | |
2846 | ||
2847 | /* set the PLL on, remove the HNP/SRP and set the PHY */ | |
47a1685f | 2848 | writel(GUSBCFG_PHYIF16 | GUSBCFG_TOUTCAL(7) | (0x5 << 10), |
94cb8fd6 | 2849 | hsotg->regs + GUSBCFG); |
b3f489b2 | 2850 | |
f5090044 GH |
2851 | if (using_dma(hsotg)) |
2852 | __orr32(hsotg->regs + GAHBCFG, GAHBCFG_DMA_EN); | |
b3f489b2 LM |
2853 | } |
2854 | ||
8b9bc460 LM |
2855 | /** |
2856 | * s3c_hsotg_udc_start - prepare the udc for work | |
2857 | * @gadget: The usb gadget state | |
2858 | * @driver: The usb gadget driver | |
2859 | * | |
2860 | * Perform initialization to prepare udc device and driver | |
2861 | * to work. | |
2862 | */ | |
f65f0f10 LM |
2863 | static int s3c_hsotg_udc_start(struct usb_gadget *gadget, |
2864 | struct usb_gadget_driver *driver) | |
5b7d70c6 | 2865 | { |
941fcce4 | 2866 | struct dwc2_hsotg *hsotg = to_hsotg(gadget); |
5b9451f8 | 2867 | unsigned long flags; |
5b7d70c6 BD |
2868 | int ret; |
2869 | ||
2870 | if (!hsotg) { | |
a023da33 | 2871 | pr_err("%s: called with no device\n", __func__); |
5b7d70c6 BD |
2872 | return -ENODEV; |
2873 | } | |
2874 | ||
2875 | if (!driver) { | |
2876 | dev_err(hsotg->dev, "%s: no driver\n", __func__); | |
2877 | return -EINVAL; | |
2878 | } | |
2879 | ||
7177aed4 | 2880 | if (driver->max_speed < USB_SPEED_FULL) |
5b7d70c6 | 2881 | dev_err(hsotg->dev, "%s: bad speed\n", __func__); |
5b7d70c6 | 2882 | |
f65f0f10 | 2883 | if (!driver->setup) { |
5b7d70c6 BD |
2884 | dev_err(hsotg->dev, "%s: missing entry points\n", __func__); |
2885 | return -EINVAL; | |
2886 | } | |
2887 | ||
7ad8096e | 2888 | mutex_lock(&hsotg->init_mutex); |
5b7d70c6 BD |
2889 | WARN_ON(hsotg->driver); |
2890 | ||
2891 | driver->driver.bus = NULL; | |
2892 | hsotg->driver = driver; | |
7d7b2292 | 2893 | hsotg->gadget.dev.of_node = hsotg->dev->of_node; |
5b7d70c6 BD |
2894 | hsotg->gadget.speed = USB_SPEED_UNKNOWN; |
2895 | ||
d00b4142 RB |
2896 | clk_enable(hsotg->clk); |
2897 | ||
f65f0f10 LM |
2898 | ret = regulator_bulk_enable(ARRAY_SIZE(hsotg->supplies), |
2899 | hsotg->supplies); | |
5b7d70c6 | 2900 | if (ret) { |
f65f0f10 | 2901 | dev_err(hsotg->dev, "failed to enable supplies: %d\n", ret); |
5b7d70c6 BD |
2902 | goto err; |
2903 | } | |
2904 | ||
c816c47f | 2905 | s3c_hsotg_phy_enable(hsotg); |
f6c01592 GH |
2906 | if (!IS_ERR_OR_NULL(hsotg->uphy)) |
2907 | otg_set_peripheral(hsotg->uphy->otg, &hsotg->gadget); | |
c816c47f | 2908 | |
5b9451f8 MS |
2909 | spin_lock_irqsave(&hsotg->lock, flags); |
2910 | s3c_hsotg_init(hsotg); | |
2911 | s3c_hsotg_core_init_disconnected(hsotg); | |
dc6e69e6 | 2912 | hsotg->enabled = 0; |
5b9451f8 MS |
2913 | spin_unlock_irqrestore(&hsotg->lock, flags); |
2914 | ||
5b7d70c6 | 2915 | dev_info(hsotg->dev, "bound driver %s\n", driver->driver.name); |
5b9451f8 | 2916 | |
7ad8096e MS |
2917 | mutex_unlock(&hsotg->init_mutex); |
2918 | ||
5b7d70c6 BD |
2919 | return 0; |
2920 | ||
2921 | err: | |
7ad8096e | 2922 | mutex_unlock(&hsotg->init_mutex); |
5b7d70c6 | 2923 | hsotg->driver = NULL; |
5b7d70c6 BD |
2924 | return ret; |
2925 | } | |
2926 | ||
8b9bc460 LM |
2927 | /** |
2928 | * s3c_hsotg_udc_stop - stop the udc | |
2929 | * @gadget: The usb gadget state | |
2930 | * @driver: The usb gadget driver | |
2931 | * | |
2932 | * Stop udc hw block and stay tunned for future transmissions | |
2933 | */ | |
22835b80 | 2934 | static int s3c_hsotg_udc_stop(struct usb_gadget *gadget) |
5b7d70c6 | 2935 | { |
941fcce4 | 2936 | struct dwc2_hsotg *hsotg = to_hsotg(gadget); |
2b19a52c | 2937 | unsigned long flags = 0; |
5b7d70c6 BD |
2938 | int ep; |
2939 | ||
2940 | if (!hsotg) | |
2941 | return -ENODEV; | |
2942 | ||
7ad8096e MS |
2943 | mutex_lock(&hsotg->init_mutex); |
2944 | ||
5b7d70c6 | 2945 | /* all endpoints should be shutdown */ |
c6f5c050 MYK |
2946 | for (ep = 1; ep < hsotg->num_of_eps; ep++) { |
2947 | if (hsotg->eps_in[ep]) | |
2948 | s3c_hsotg_ep_disable(&hsotg->eps_in[ep]->ep); | |
2949 | if (hsotg->eps_out[ep]) | |
2950 | s3c_hsotg_ep_disable(&hsotg->eps_out[ep]->ep); | |
2951 | } | |
5b7d70c6 | 2952 | |
2b19a52c LM |
2953 | spin_lock_irqsave(&hsotg->lock, flags); |
2954 | ||
32805c35 | 2955 | hsotg->driver = NULL; |
5b7d70c6 | 2956 | hsotg->gadget.speed = USB_SPEED_UNKNOWN; |
dc6e69e6 | 2957 | hsotg->enabled = 0; |
5b7d70c6 | 2958 | |
2b19a52c LM |
2959 | spin_unlock_irqrestore(&hsotg->lock, flags); |
2960 | ||
f6c01592 GH |
2961 | if (!IS_ERR_OR_NULL(hsotg->uphy)) |
2962 | otg_set_peripheral(hsotg->uphy->otg, NULL); | |
c816c47f MS |
2963 | s3c_hsotg_phy_disable(hsotg); |
2964 | ||
c8c10253 | 2965 | regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies), hsotg->supplies); |
5b7d70c6 | 2966 | |
d00b4142 RB |
2967 | clk_disable(hsotg->clk); |
2968 | ||
7ad8096e MS |
2969 | mutex_unlock(&hsotg->init_mutex); |
2970 | ||
5b7d70c6 BD |
2971 | return 0; |
2972 | } | |
5b7d70c6 | 2973 | |
8b9bc460 LM |
2974 | /** |
2975 | * s3c_hsotg_gadget_getframe - read the frame number | |
2976 | * @gadget: The usb gadget state | |
2977 | * | |
2978 | * Read the {micro} frame number | |
2979 | */ | |
5b7d70c6 BD |
2980 | static int s3c_hsotg_gadget_getframe(struct usb_gadget *gadget) |
2981 | { | |
2982 | return s3c_hsotg_read_frameno(to_hsotg(gadget)); | |
2983 | } | |
2984 | ||
a188b689 LM |
2985 | /** |
2986 | * s3c_hsotg_pullup - connect/disconnect the USB PHY | |
2987 | * @gadget: The usb gadget state | |
2988 | * @is_on: Current state of the USB PHY | |
2989 | * | |
2990 | * Connect/Disconnect the USB PHY pullup | |
2991 | */ | |
2992 | static int s3c_hsotg_pullup(struct usb_gadget *gadget, int is_on) | |
2993 | { | |
941fcce4 | 2994 | struct dwc2_hsotg *hsotg = to_hsotg(gadget); |
a188b689 LM |
2995 | unsigned long flags = 0; |
2996 | ||
d784f1e5 | 2997 | dev_dbg(hsotg->dev, "%s: is_on: %d\n", __func__, is_on); |
a188b689 | 2998 | |
7ad8096e | 2999 | mutex_lock(&hsotg->init_mutex); |
a188b689 LM |
3000 | spin_lock_irqsave(&hsotg->lock, flags); |
3001 | if (is_on) { | |
d00b4142 | 3002 | clk_enable(hsotg->clk); |
dc6e69e6 | 3003 | hsotg->enabled = 1; |
ad38dc5d | 3004 | s3c_hsotg_core_connect(hsotg); |
a188b689 | 3005 | } else { |
5b9451f8 | 3006 | s3c_hsotg_core_disconnect(hsotg); |
dc6e69e6 | 3007 | hsotg->enabled = 0; |
d00b4142 | 3008 | clk_disable(hsotg->clk); |
a188b689 LM |
3009 | } |
3010 | ||
3011 | hsotg->gadget.speed = USB_SPEED_UNKNOWN; | |
3012 | spin_unlock_irqrestore(&hsotg->lock, flags); | |
7ad8096e | 3013 | mutex_unlock(&hsotg->init_mutex); |
a188b689 LM |
3014 | |
3015 | return 0; | |
3016 | } | |
3017 | ||
eeef4587 | 3018 | static const struct usb_gadget_ops s3c_hsotg_gadget_ops = { |
5b7d70c6 | 3019 | .get_frame = s3c_hsotg_gadget_getframe, |
f65f0f10 LM |
3020 | .udc_start = s3c_hsotg_udc_start, |
3021 | .udc_stop = s3c_hsotg_udc_stop, | |
a188b689 | 3022 | .pullup = s3c_hsotg_pullup, |
5b7d70c6 BD |
3023 | }; |
3024 | ||
3025 | /** | |
3026 | * s3c_hsotg_initep - initialise a single endpoint | |
3027 | * @hsotg: The device state. | |
3028 | * @hs_ep: The endpoint to be initialised. | |
3029 | * @epnum: The endpoint number | |
3030 | * | |
3031 | * Initialise the given endpoint (as part of the probe and device state | |
3032 | * creation) to give to the gadget driver. Setup the endpoint name, any | |
3033 | * direction information and other state that may be required. | |
3034 | */ | |
941fcce4 | 3035 | static void s3c_hsotg_initep(struct dwc2_hsotg *hsotg, |
5b7d70c6 | 3036 | struct s3c_hsotg_ep *hs_ep, |
c6f5c050 MYK |
3037 | int epnum, |
3038 | bool dir_in) | |
5b7d70c6 | 3039 | { |
5b7d70c6 BD |
3040 | char *dir; |
3041 | ||
3042 | if (epnum == 0) | |
3043 | dir = ""; | |
c6f5c050 | 3044 | else if (dir_in) |
5b7d70c6 | 3045 | dir = "in"; |
c6f5c050 MYK |
3046 | else |
3047 | dir = "out"; | |
5b7d70c6 | 3048 | |
c6f5c050 | 3049 | hs_ep->dir_in = dir_in; |
5b7d70c6 BD |
3050 | hs_ep->index = epnum; |
3051 | ||
3052 | snprintf(hs_ep->name, sizeof(hs_ep->name), "ep%d%s", epnum, dir); | |
3053 | ||
3054 | INIT_LIST_HEAD(&hs_ep->queue); | |
3055 | INIT_LIST_HEAD(&hs_ep->ep.ep_list); | |
3056 | ||
5b7d70c6 BD |
3057 | /* add to the list of endpoints known by the gadget driver */ |
3058 | if (epnum) | |
3059 | list_add_tail(&hs_ep->ep.ep_list, &hsotg->gadget.ep_list); | |
3060 | ||
3061 | hs_ep->parent = hsotg; | |
3062 | hs_ep->ep.name = hs_ep->name; | |
e117e742 | 3063 | usb_ep_set_maxpacket_limit(&hs_ep->ep, epnum ? 1024 : EP0_MPS_LIMIT); |
5b7d70c6 BD |
3064 | hs_ep->ep.ops = &s3c_hsotg_ep_ops; |
3065 | ||
8b9bc460 LM |
3066 | /* |
3067 | * if we're using dma, we need to set the next-endpoint pointer | |
5b7d70c6 BD |
3068 | * to be something valid. |
3069 | */ | |
3070 | ||
3071 | if (using_dma(hsotg)) { | |
47a1685f | 3072 | u32 next = DXEPCTL_NEXTEP((epnum + 1) % 15); |
c6f5c050 MYK |
3073 | if (dir_in) |
3074 | writel(next, hsotg->regs + DIEPCTL(epnum)); | |
3075 | else | |
3076 | writel(next, hsotg->regs + DOEPCTL(epnum)); | |
5b7d70c6 BD |
3077 | } |
3078 | } | |
3079 | ||
b3f489b2 LM |
3080 | /** |
3081 | * s3c_hsotg_hw_cfg - read HW configuration registers | |
3082 | * @param: The device state | |
3083 | * | |
3084 | * Read the USB core HW configuration registers | |
3085 | */ | |
c6f5c050 | 3086 | static int s3c_hsotg_hw_cfg(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 3087 | { |
c6f5c050 MYK |
3088 | u32 cfg; |
3089 | u32 ep_type; | |
3090 | u32 i; | |
3091 | ||
b3f489b2 | 3092 | /* check hardware configuration */ |
5b7d70c6 | 3093 | |
c6f5c050 MYK |
3094 | cfg = readl(hsotg->regs + GHWCFG2); |
3095 | hsotg->num_of_eps = (cfg >> 10) & 0xF; | |
3096 | /* Add ep0 */ | |
3097 | hsotg->num_of_eps++; | |
10aebc77 | 3098 | |
c6f5c050 MYK |
3099 | hsotg->eps_in[0] = devm_kzalloc(hsotg->dev, sizeof(struct s3c_hsotg_ep), |
3100 | GFP_KERNEL); | |
3101 | if (!hsotg->eps_in[0]) | |
3102 | return -ENOMEM; | |
3103 | /* Same s3c_hsotg_ep is used in both directions for ep0 */ | |
3104 | hsotg->eps_out[0] = hsotg->eps_in[0]; | |
3105 | ||
3106 | cfg = readl(hsotg->regs + GHWCFG1); | |
3107 | for (i = 1; i < hsotg->num_of_eps; i++, cfg >>= 2) { | |
3108 | ep_type = cfg & 3; | |
3109 | /* Direction in or both */ | |
3110 | if (!(ep_type & 2)) { | |
3111 | hsotg->eps_in[i] = devm_kzalloc(hsotg->dev, | |
3112 | sizeof(struct s3c_hsotg_ep), GFP_KERNEL); | |
3113 | if (!hsotg->eps_in[i]) | |
3114 | return -ENOMEM; | |
3115 | } | |
3116 | /* Direction out or both */ | |
3117 | if (!(ep_type & 1)) { | |
3118 | hsotg->eps_out[i] = devm_kzalloc(hsotg->dev, | |
3119 | sizeof(struct s3c_hsotg_ep), GFP_KERNEL); | |
3120 | if (!hsotg->eps_out[i]) | |
3121 | return -ENOMEM; | |
3122 | } | |
3123 | } | |
3124 | ||
3125 | cfg = readl(hsotg->regs + GHWCFG3); | |
3126 | hsotg->fifo_mem = (cfg >> 16); | |
10aebc77 | 3127 | |
c6f5c050 MYK |
3128 | cfg = readl(hsotg->regs + GHWCFG4); |
3129 | hsotg->dedicated_fifos = (cfg >> 25) & 1; | |
10aebc77 | 3130 | |
cff9eb75 MS |
3131 | dev_info(hsotg->dev, "EPs: %d, %s fifos, %d entries in SPRAM\n", |
3132 | hsotg->num_of_eps, | |
3133 | hsotg->dedicated_fifos ? "dedicated" : "shared", | |
3134 | hsotg->fifo_mem); | |
c6f5c050 | 3135 | return 0; |
5b7d70c6 BD |
3136 | } |
3137 | ||
8b9bc460 LM |
3138 | /** |
3139 | * s3c_hsotg_dump - dump state of the udc | |
3140 | * @param: The device state | |
3141 | */ | |
941fcce4 | 3142 | static void s3c_hsotg_dump(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 3143 | { |
83a01804 | 3144 | #ifdef DEBUG |
5b7d70c6 BD |
3145 | struct device *dev = hsotg->dev; |
3146 | void __iomem *regs = hsotg->regs; | |
3147 | u32 val; | |
3148 | int idx; | |
3149 | ||
3150 | dev_info(dev, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n", | |
94cb8fd6 LM |
3151 | readl(regs + DCFG), readl(regs + DCTL), |
3152 | readl(regs + DIEPMSK)); | |
5b7d70c6 BD |
3153 | |
3154 | dev_info(dev, "GAHBCFG=0x%08x, 0x44=0x%08x\n", | |
94cb8fd6 | 3155 | readl(regs + GAHBCFG), readl(regs + 0x44)); |
5b7d70c6 BD |
3156 | |
3157 | dev_info(dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n", | |
94cb8fd6 | 3158 | readl(regs + GRXFSIZ), readl(regs + GNPTXFSIZ)); |
5b7d70c6 BD |
3159 | |
3160 | /* show periodic fifo settings */ | |
3161 | ||
364f8e93 | 3162 | for (idx = 1; idx < hsotg->num_of_eps; idx++) { |
47a1685f | 3163 | val = readl(regs + DPTXFSIZN(idx)); |
5b7d70c6 | 3164 | dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx, |
47a1685f DN |
3165 | val >> FIFOSIZE_DEPTH_SHIFT, |
3166 | val & FIFOSIZE_STARTADDR_MASK); | |
5b7d70c6 BD |
3167 | } |
3168 | ||
364f8e93 | 3169 | for (idx = 0; idx < hsotg->num_of_eps; idx++) { |
5b7d70c6 BD |
3170 | dev_info(dev, |
3171 | "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx, | |
94cb8fd6 LM |
3172 | readl(regs + DIEPCTL(idx)), |
3173 | readl(regs + DIEPTSIZ(idx)), | |
3174 | readl(regs + DIEPDMA(idx))); | |
5b7d70c6 | 3175 | |
94cb8fd6 | 3176 | val = readl(regs + DOEPCTL(idx)); |
5b7d70c6 BD |
3177 | dev_info(dev, |
3178 | "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", | |
94cb8fd6 LM |
3179 | idx, readl(regs + DOEPCTL(idx)), |
3180 | readl(regs + DOEPTSIZ(idx)), | |
3181 | readl(regs + DOEPDMA(idx))); | |
5b7d70c6 BD |
3182 | |
3183 | } | |
3184 | ||
3185 | dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n", | |
94cb8fd6 | 3186 | readl(regs + DVBUSDIS), readl(regs + DVBUSPULSE)); |
83a01804 | 3187 | #endif |
5b7d70c6 BD |
3188 | } |
3189 | ||
5b7d70c6 BD |
3190 | /** |
3191 | * state_show - debugfs: show overall driver and device state. | |
3192 | * @seq: The seq file to write to. | |
3193 | * @v: Unused parameter. | |
3194 | * | |
3195 | * This debugfs entry shows the overall state of the hardware and | |
3196 | * some general information about each of the endpoints available | |
3197 | * to the system. | |
3198 | */ | |
3199 | static int state_show(struct seq_file *seq, void *v) | |
3200 | { | |
941fcce4 | 3201 | struct dwc2_hsotg *hsotg = seq->private; |
5b7d70c6 BD |
3202 | void __iomem *regs = hsotg->regs; |
3203 | int idx; | |
3204 | ||
3205 | seq_printf(seq, "DCFG=0x%08x, DCTL=0x%08x, DSTS=0x%08x\n", | |
94cb8fd6 LM |
3206 | readl(regs + DCFG), |
3207 | readl(regs + DCTL), | |
3208 | readl(regs + DSTS)); | |
5b7d70c6 BD |
3209 | |
3210 | seq_printf(seq, "DIEPMSK=0x%08x, DOEPMASK=0x%08x\n", | |
94cb8fd6 | 3211 | readl(regs + DIEPMSK), readl(regs + DOEPMSK)); |
5b7d70c6 BD |
3212 | |
3213 | seq_printf(seq, "GINTMSK=0x%08x, GINTSTS=0x%08x\n", | |
94cb8fd6 LM |
3214 | readl(regs + GINTMSK), |
3215 | readl(regs + GINTSTS)); | |
5b7d70c6 BD |
3216 | |
3217 | seq_printf(seq, "DAINTMSK=0x%08x, DAINT=0x%08x\n", | |
94cb8fd6 LM |
3218 | readl(regs + DAINTMSK), |
3219 | readl(regs + DAINT)); | |
5b7d70c6 BD |
3220 | |
3221 | seq_printf(seq, "GNPTXSTS=0x%08x, GRXSTSR=%08x\n", | |
94cb8fd6 LM |
3222 | readl(regs + GNPTXSTS), |
3223 | readl(regs + GRXSTSR)); | |
5b7d70c6 | 3224 | |
a023da33 | 3225 | seq_puts(seq, "\nEndpoint status:\n"); |
5b7d70c6 | 3226 | |
364f8e93 | 3227 | for (idx = 0; idx < hsotg->num_of_eps; idx++) { |
5b7d70c6 BD |
3228 | u32 in, out; |
3229 | ||
94cb8fd6 LM |
3230 | in = readl(regs + DIEPCTL(idx)); |
3231 | out = readl(regs + DOEPCTL(idx)); | |
5b7d70c6 BD |
3232 | |
3233 | seq_printf(seq, "ep%d: DIEPCTL=0x%08x, DOEPCTL=0x%08x", | |
3234 | idx, in, out); | |
3235 | ||
94cb8fd6 LM |
3236 | in = readl(regs + DIEPTSIZ(idx)); |
3237 | out = readl(regs + DOEPTSIZ(idx)); | |
5b7d70c6 BD |
3238 | |
3239 | seq_printf(seq, ", DIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x", | |
3240 | in, out); | |
3241 | ||
a023da33 | 3242 | seq_puts(seq, "\n"); |
5b7d70c6 BD |
3243 | } |
3244 | ||
3245 | return 0; | |
3246 | } | |
3247 | ||
3248 | static int state_open(struct inode *inode, struct file *file) | |
3249 | { | |
3250 | return single_open(file, state_show, inode->i_private); | |
3251 | } | |
3252 | ||
3253 | static const struct file_operations state_fops = { | |
3254 | .owner = THIS_MODULE, | |
3255 | .open = state_open, | |
3256 | .read = seq_read, | |
3257 | .llseek = seq_lseek, | |
3258 | .release = single_release, | |
3259 | }; | |
3260 | ||
3261 | /** | |
3262 | * fifo_show - debugfs: show the fifo information | |
3263 | * @seq: The seq_file to write data to. | |
3264 | * @v: Unused parameter. | |
3265 | * | |
3266 | * Show the FIFO information for the overall fifo and all the | |
3267 | * periodic transmission FIFOs. | |
8b9bc460 | 3268 | */ |
5b7d70c6 BD |
3269 | static int fifo_show(struct seq_file *seq, void *v) |
3270 | { | |
941fcce4 | 3271 | struct dwc2_hsotg *hsotg = seq->private; |
5b7d70c6 BD |
3272 | void __iomem *regs = hsotg->regs; |
3273 | u32 val; | |
3274 | int idx; | |
3275 | ||
a023da33 | 3276 | seq_puts(seq, "Non-periodic FIFOs:\n"); |
94cb8fd6 | 3277 | seq_printf(seq, "RXFIFO: Size %d\n", readl(regs + GRXFSIZ)); |
5b7d70c6 | 3278 | |
94cb8fd6 | 3279 | val = readl(regs + GNPTXFSIZ); |
5b7d70c6 | 3280 | seq_printf(seq, "NPTXFIFO: Size %d, Start 0x%08x\n", |
47a1685f DN |
3281 | val >> FIFOSIZE_DEPTH_SHIFT, |
3282 | val & FIFOSIZE_DEPTH_MASK); | |
5b7d70c6 | 3283 | |
a023da33 | 3284 | seq_puts(seq, "\nPeriodic TXFIFOs:\n"); |
5b7d70c6 | 3285 | |
364f8e93 | 3286 | for (idx = 1; idx < hsotg->num_of_eps; idx++) { |
47a1685f | 3287 | val = readl(regs + DPTXFSIZN(idx)); |
5b7d70c6 BD |
3288 | |
3289 | seq_printf(seq, "\tDPTXFIFO%2d: Size %d, Start 0x%08x\n", idx, | |
47a1685f DN |
3290 | val >> FIFOSIZE_DEPTH_SHIFT, |
3291 | val & FIFOSIZE_STARTADDR_MASK); | |
5b7d70c6 BD |
3292 | } |
3293 | ||
3294 | return 0; | |
3295 | } | |
3296 | ||
3297 | static int fifo_open(struct inode *inode, struct file *file) | |
3298 | { | |
3299 | return single_open(file, fifo_show, inode->i_private); | |
3300 | } | |
3301 | ||
3302 | static const struct file_operations fifo_fops = { | |
3303 | .owner = THIS_MODULE, | |
3304 | .open = fifo_open, | |
3305 | .read = seq_read, | |
3306 | .llseek = seq_lseek, | |
3307 | .release = single_release, | |
3308 | }; | |
3309 | ||
3310 | ||
3311 | static const char *decode_direction(int is_in) | |
3312 | { | |
3313 | return is_in ? "in" : "out"; | |
3314 | } | |
3315 | ||
3316 | /** | |
3317 | * ep_show - debugfs: show the state of an endpoint. | |
3318 | * @seq: The seq_file to write data to. | |
3319 | * @v: Unused parameter. | |
3320 | * | |
3321 | * This debugfs entry shows the state of the given endpoint (one is | |
3322 | * registered for each available). | |
8b9bc460 | 3323 | */ |
5b7d70c6 BD |
3324 | static int ep_show(struct seq_file *seq, void *v) |
3325 | { | |
3326 | struct s3c_hsotg_ep *ep = seq->private; | |
941fcce4 | 3327 | struct dwc2_hsotg *hsotg = ep->parent; |
5b7d70c6 BD |
3328 | struct s3c_hsotg_req *req; |
3329 | void __iomem *regs = hsotg->regs; | |
3330 | int index = ep->index; | |
3331 | int show_limit = 15; | |
3332 | unsigned long flags; | |
3333 | ||
3334 | seq_printf(seq, "Endpoint index %d, named %s, dir %s:\n", | |
3335 | ep->index, ep->ep.name, decode_direction(ep->dir_in)); | |
3336 | ||
3337 | /* first show the register state */ | |
3338 | ||
3339 | seq_printf(seq, "\tDIEPCTL=0x%08x, DOEPCTL=0x%08x\n", | |
94cb8fd6 LM |
3340 | readl(regs + DIEPCTL(index)), |
3341 | readl(regs + DOEPCTL(index))); | |
5b7d70c6 BD |
3342 | |
3343 | seq_printf(seq, "\tDIEPDMA=0x%08x, DOEPDMA=0x%08x\n", | |
94cb8fd6 LM |
3344 | readl(regs + DIEPDMA(index)), |
3345 | readl(regs + DOEPDMA(index))); | |
5b7d70c6 BD |
3346 | |
3347 | seq_printf(seq, "\tDIEPINT=0x%08x, DOEPINT=0x%08x\n", | |
94cb8fd6 LM |
3348 | readl(regs + DIEPINT(index)), |
3349 | readl(regs + DOEPINT(index))); | |
5b7d70c6 BD |
3350 | |
3351 | seq_printf(seq, "\tDIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x\n", | |
94cb8fd6 LM |
3352 | readl(regs + DIEPTSIZ(index)), |
3353 | readl(regs + DOEPTSIZ(index))); | |
5b7d70c6 | 3354 | |
a023da33 | 3355 | seq_puts(seq, "\n"); |
5b7d70c6 BD |
3356 | seq_printf(seq, "mps %d\n", ep->ep.maxpacket); |
3357 | seq_printf(seq, "total_data=%ld\n", ep->total_data); | |
3358 | ||
3359 | seq_printf(seq, "request list (%p,%p):\n", | |
3360 | ep->queue.next, ep->queue.prev); | |
3361 | ||
22258f49 | 3362 | spin_lock_irqsave(&hsotg->lock, flags); |
5b7d70c6 BD |
3363 | |
3364 | list_for_each_entry(req, &ep->queue, queue) { | |
3365 | if (--show_limit < 0) { | |
a023da33 | 3366 | seq_puts(seq, "not showing more requests...\n"); |
5b7d70c6 BD |
3367 | break; |
3368 | } | |
3369 | ||
3370 | seq_printf(seq, "%c req %p: %d bytes @%p, ", | |
3371 | req == ep->req ? '*' : ' ', | |
3372 | req, req->req.length, req->req.buf); | |
3373 | seq_printf(seq, "%d done, res %d\n", | |
3374 | req->req.actual, req->req.status); | |
3375 | } | |
3376 | ||
22258f49 | 3377 | spin_unlock_irqrestore(&hsotg->lock, flags); |
5b7d70c6 BD |
3378 | |
3379 | return 0; | |
3380 | } | |
3381 | ||
3382 | static int ep_open(struct inode *inode, struct file *file) | |
3383 | { | |
3384 | return single_open(file, ep_show, inode->i_private); | |
3385 | } | |
3386 | ||
3387 | static const struct file_operations ep_fops = { | |
3388 | .owner = THIS_MODULE, | |
3389 | .open = ep_open, | |
3390 | .read = seq_read, | |
3391 | .llseek = seq_lseek, | |
3392 | .release = single_release, | |
3393 | }; | |
3394 | ||
3395 | /** | |
3396 | * s3c_hsotg_create_debug - create debugfs directory and files | |
3397 | * @hsotg: The driver state | |
3398 | * | |
3399 | * Create the debugfs files to allow the user to get information | |
3400 | * about the state of the system. The directory name is created | |
3401 | * with the same name as the device itself, in case we end up | |
3402 | * with multiple blocks in future systems. | |
8b9bc460 | 3403 | */ |
941fcce4 | 3404 | static void s3c_hsotg_create_debug(struct dwc2_hsotg *hsotg) |
5b7d70c6 BD |
3405 | { |
3406 | struct dentry *root; | |
3407 | unsigned epidx; | |
3408 | ||
3409 | root = debugfs_create_dir(dev_name(hsotg->dev), NULL); | |
3410 | hsotg->debug_root = root; | |
3411 | if (IS_ERR(root)) { | |
3412 | dev_err(hsotg->dev, "cannot create debug root\n"); | |
3413 | return; | |
3414 | } | |
3415 | ||
3416 | /* create general state file */ | |
3417 | ||
3418 | hsotg->debug_file = debugfs_create_file("state", 0444, root, | |
3419 | hsotg, &state_fops); | |
3420 | ||
3421 | if (IS_ERR(hsotg->debug_file)) | |
3422 | dev_err(hsotg->dev, "%s: failed to create state\n", __func__); | |
3423 | ||
3424 | hsotg->debug_fifo = debugfs_create_file("fifo", 0444, root, | |
3425 | hsotg, &fifo_fops); | |
3426 | ||
3427 | if (IS_ERR(hsotg->debug_fifo)) | |
3428 | dev_err(hsotg->dev, "%s: failed to create fifo\n", __func__); | |
3429 | ||
c6f5c050 | 3430 | /* Create one file for each out endpoint */ |
b3f489b2 | 3431 | for (epidx = 0; epidx < hsotg->num_of_eps; epidx++) { |
c6f5c050 | 3432 | struct s3c_hsotg_ep *ep; |
5b7d70c6 | 3433 | |
c6f5c050 MYK |
3434 | ep = hsotg->eps_out[epidx]; |
3435 | if (ep) { | |
3436 | ep->debugfs = debugfs_create_file(ep->name, 0444, | |
3437 | root, ep, &ep_fops); | |
5b7d70c6 | 3438 | |
c6f5c050 MYK |
3439 | if (IS_ERR(ep->debugfs)) |
3440 | dev_err(hsotg->dev, "failed to create %s debug file\n", | |
3441 | ep->name); | |
3442 | } | |
3443 | } | |
3444 | /* Create one file for each in endpoint. EP0 is handled with out eps */ | |
3445 | for (epidx = 1; epidx < hsotg->num_of_eps; epidx++) { | |
3446 | struct s3c_hsotg_ep *ep; | |
3447 | ||
3448 | ep = hsotg->eps_in[epidx]; | |
3449 | if (ep) { | |
3450 | ep->debugfs = debugfs_create_file(ep->name, 0444, | |
3451 | root, ep, &ep_fops); | |
3452 | ||
3453 | if (IS_ERR(ep->debugfs)) | |
3454 | dev_err(hsotg->dev, "failed to create %s debug file\n", | |
3455 | ep->name); | |
3456 | } | |
5b7d70c6 BD |
3457 | } |
3458 | } | |
3459 | ||
3460 | /** | |
3461 | * s3c_hsotg_delete_debug - cleanup debugfs entries | |
3462 | * @hsotg: The driver state | |
3463 | * | |
3464 | * Cleanup (remove) the debugfs files for use on module exit. | |
8b9bc460 | 3465 | */ |
941fcce4 | 3466 | static void s3c_hsotg_delete_debug(struct dwc2_hsotg *hsotg) |
5b7d70c6 BD |
3467 | { |
3468 | unsigned epidx; | |
3469 | ||
b3f489b2 | 3470 | for (epidx = 0; epidx < hsotg->num_of_eps; epidx++) { |
c6f5c050 MYK |
3471 | if (hsotg->eps_in[epidx]) |
3472 | debugfs_remove(hsotg->eps_in[epidx]->debugfs); | |
3473 | if (hsotg->eps_out[epidx]) | |
3474 | debugfs_remove(hsotg->eps_out[epidx]->debugfs); | |
5b7d70c6 BD |
3475 | } |
3476 | ||
3477 | debugfs_remove(hsotg->debug_file); | |
3478 | debugfs_remove(hsotg->debug_fifo); | |
3479 | debugfs_remove(hsotg->debug_root); | |
3480 | } | |
3481 | ||
edd74be8 GH |
3482 | #ifdef CONFIG_OF |
3483 | static void s3c_hsotg_of_probe(struct dwc2_hsotg *hsotg) | |
3484 | { | |
3485 | struct device_node *np = hsotg->dev->of_node; | |
0a176279 GH |
3486 | u32 len = 0; |
3487 | u32 i = 0; | |
edd74be8 GH |
3488 | |
3489 | /* Enable dma if requested in device tree */ | |
3490 | hsotg->g_using_dma = of_property_read_bool(np, "g-use-dma"); | |
0a176279 GH |
3491 | |
3492 | /* | |
3493 | * Register TX periodic fifo size per endpoint. | |
3494 | * EP0 is excluded since it has no fifo configuration. | |
3495 | */ | |
3496 | if (!of_find_property(np, "g-tx-fifo-size", &len)) | |
3497 | goto rx_fifo; | |
3498 | ||
3499 | len /= sizeof(u32); | |
3500 | ||
3501 | /* Read tx fifo sizes other than ep0 */ | |
3502 | if (of_property_read_u32_array(np, "g-tx-fifo-size", | |
3503 | &hsotg->g_tx_fifo_sz[1], len)) | |
3504 | goto rx_fifo; | |
3505 | ||
3506 | /* Add ep0 */ | |
3507 | len++; | |
3508 | ||
3509 | /* Make remaining TX fifos unavailable */ | |
3510 | if (len < MAX_EPS_CHANNELS) { | |
3511 | for (i = len; i < MAX_EPS_CHANNELS; i++) | |
3512 | hsotg->g_tx_fifo_sz[i] = 0; | |
3513 | } | |
3514 | ||
3515 | rx_fifo: | |
3516 | /* Register RX fifo size */ | |
3517 | of_property_read_u32(np, "g-rx-fifo-size", &hsotg->g_rx_fifo_sz); | |
3518 | ||
3519 | /* Register NPTX fifo size */ | |
3520 | of_property_read_u32(np, "g-np-tx-fifo-size", | |
3521 | &hsotg->g_np_g_tx_fifo_sz); | |
edd74be8 GH |
3522 | } |
3523 | #else | |
3524 | static inline void s3c_hsotg_of_probe(struct dwc2_hsotg *hsotg) { } | |
3525 | #endif | |
3526 | ||
8b9bc460 | 3527 | /** |
117777b2 DN |
3528 | * dwc2_gadget_init - init function for gadget |
3529 | * @dwc2: The data structure for the DWC2 driver. | |
3530 | * @irq: The IRQ number for the controller. | |
8b9bc460 | 3531 | */ |
117777b2 | 3532 | int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq) |
5b7d70c6 | 3533 | { |
117777b2 DN |
3534 | struct device *dev = hsotg->dev; |
3535 | struct s3c_hsotg_plat *plat = dev->platform_data; | |
5b7d70c6 BD |
3536 | int epnum; |
3537 | int ret; | |
fc9a731e | 3538 | int i; |
0a176279 | 3539 | u32 p_tx_fifo[] = DWC2_G_P_LEGACY_TX_FIFO_SIZE; |
5b7d70c6 | 3540 | |
1b59fc7e KD |
3541 | /* Set default UTMI width */ |
3542 | hsotg->phyif = GUSBCFG_PHYIF16; | |
3543 | ||
edd74be8 GH |
3544 | s3c_hsotg_of_probe(hsotg); |
3545 | ||
0a176279 GH |
3546 | /* Initialize to legacy fifo configuration values */ |
3547 | hsotg->g_rx_fifo_sz = 2048; | |
3548 | hsotg->g_np_g_tx_fifo_sz = 1024; | |
3549 | memcpy(&hsotg->g_tx_fifo_sz[1], p_tx_fifo, sizeof(p_tx_fifo)); | |
3550 | /* Device tree specific probe */ | |
3551 | s3c_hsotg_of_probe(hsotg); | |
3552 | /* Dump fifo information */ | |
3553 | dev_dbg(dev, "NonPeriodic TXFIFO size: %d\n", | |
3554 | hsotg->g_np_g_tx_fifo_sz); | |
3555 | dev_dbg(dev, "RXFIFO size: %d\n", hsotg->g_rx_fifo_sz); | |
3556 | for (i = 0; i < MAX_EPS_CHANNELS; i++) | |
3557 | dev_dbg(dev, "Periodic TXFIFO%2d size: %d\n", i, | |
3558 | hsotg->g_tx_fifo_sz[i]); | |
74084844 | 3559 | /* |
135b3c43 YL |
3560 | * If platform probe couldn't find a generic PHY or an old style |
3561 | * USB PHY, fall back to pdata | |
74084844 | 3562 | */ |
135b3c43 YL |
3563 | if (IS_ERR_OR_NULL(hsotg->phy) && IS_ERR_OR_NULL(hsotg->uphy)) { |
3564 | plat = dev_get_platdata(dev); | |
3565 | if (!plat) { | |
3566 | dev_err(dev, | |
3567 | "no platform data or transceiver defined\n"); | |
3568 | return -EPROBE_DEFER; | |
3569 | } | |
3570 | hsotg->plat = plat; | |
3571 | } else if (hsotg->phy) { | |
1b59fc7e KD |
3572 | /* |
3573 | * If using the generic PHY framework, check if the PHY bus | |
3574 | * width is 8-bit and set the phyif appropriately. | |
3575 | */ | |
135b3c43 | 3576 | if (phy_get_bus_width(hsotg->phy) == 8) |
1b59fc7e KD |
3577 | hsotg->phyif = GUSBCFG_PHYIF8; |
3578 | } | |
b2e587db | 3579 | |
117777b2 | 3580 | hsotg->clk = devm_clk_get(dev, "otg"); |
31ee04de | 3581 | if (IS_ERR(hsotg->clk)) { |
8d736d8a | 3582 | hsotg->clk = NULL; |
f415fbd1 | 3583 | dev_dbg(dev, "cannot get otg clock\n"); |
5b7d70c6 BD |
3584 | } |
3585 | ||
d327ab5b | 3586 | hsotg->gadget.max_speed = USB_SPEED_HIGH; |
5b7d70c6 BD |
3587 | hsotg->gadget.ops = &s3c_hsotg_gadget_ops; |
3588 | hsotg->gadget.name = dev_name(dev); | |
5b7d70c6 | 3589 | |
5b7d70c6 BD |
3590 | /* reset the system */ |
3591 | ||
f415fbd1 DN |
3592 | ret = clk_prepare_enable(hsotg->clk); |
3593 | if (ret) { | |
3594 | dev_err(dev, "failed to enable otg clk\n"); | |
3595 | goto err_clk; | |
3596 | } | |
3597 | ||
31ee04de | 3598 | |
fc9a731e LM |
3599 | /* regulators */ |
3600 | ||
3601 | for (i = 0; i < ARRAY_SIZE(hsotg->supplies); i++) | |
3602 | hsotg->supplies[i].supply = s3c_hsotg_supply_names[i]; | |
3603 | ||
cd76213e | 3604 | ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(hsotg->supplies), |
fc9a731e LM |
3605 | hsotg->supplies); |
3606 | if (ret) { | |
3607 | dev_err(dev, "failed to request supplies: %d\n", ret); | |
338edabc | 3608 | goto err_clk; |
fc9a731e LM |
3609 | } |
3610 | ||
3611 | ret = regulator_bulk_enable(ARRAY_SIZE(hsotg->supplies), | |
3612 | hsotg->supplies); | |
3613 | ||
3614 | if (ret) { | |
941fcce4 | 3615 | dev_err(dev, "failed to enable supplies: %d\n", ret); |
c139ec27 | 3616 | goto err_clk; |
fc9a731e LM |
3617 | } |
3618 | ||
41188786 LM |
3619 | /* usb phy enable */ |
3620 | s3c_hsotg_phy_enable(hsotg); | |
5b7d70c6 | 3621 | |
5b7d70c6 | 3622 | s3c_hsotg_corereset(hsotg); |
c6f5c050 MYK |
3623 | ret = s3c_hsotg_hw_cfg(hsotg); |
3624 | if (ret) { | |
3625 | dev_err(hsotg->dev, "Hardware configuration failed: %d\n", ret); | |
3626 | goto err_clk; | |
3627 | } | |
3628 | ||
cff9eb75 | 3629 | s3c_hsotg_init(hsotg); |
b3f489b2 | 3630 | |
3f95001d MYK |
3631 | hsotg->ctrl_buff = devm_kzalloc(hsotg->dev, |
3632 | DWC2_CTRL_BUFF_SIZE, GFP_KERNEL); | |
3633 | if (!hsotg->ctrl_buff) { | |
3634 | dev_err(dev, "failed to allocate ctrl request buff\n"); | |
3635 | ret = -ENOMEM; | |
3636 | goto err_supplies; | |
3637 | } | |
3638 | ||
3639 | hsotg->ep0_buff = devm_kzalloc(hsotg->dev, | |
3640 | DWC2_CTRL_BUFF_SIZE, GFP_KERNEL); | |
3641 | if (!hsotg->ep0_buff) { | |
3642 | dev_err(dev, "failed to allocate ctrl reply buff\n"); | |
3643 | ret = -ENOMEM; | |
3644 | goto err_supplies; | |
3645 | } | |
3646 | ||
db8178c3 DN |
3647 | ret = devm_request_irq(hsotg->dev, irq, s3c_hsotg_irq, IRQF_SHARED, |
3648 | dev_name(hsotg->dev), hsotg); | |
eb3c56c5 MS |
3649 | if (ret < 0) { |
3650 | s3c_hsotg_phy_disable(hsotg); | |
3651 | clk_disable_unprepare(hsotg->clk); | |
3652 | regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies), | |
3653 | hsotg->supplies); | |
db8178c3 | 3654 | dev_err(dev, "cannot claim IRQ for gadget\n"); |
c139ec27 | 3655 | goto err_supplies; |
eb3c56c5 MS |
3656 | } |
3657 | ||
b3f489b2 LM |
3658 | /* hsotg->num_of_eps holds number of EPs other than ep0 */ |
3659 | ||
3660 | if (hsotg->num_of_eps == 0) { | |
3661 | dev_err(dev, "wrong number of EPs (zero)\n"); | |
dfdda5a0 | 3662 | ret = -EINVAL; |
b3f489b2 LM |
3663 | goto err_supplies; |
3664 | } | |
3665 | ||
b3f489b2 LM |
3666 | /* setup endpoint information */ |
3667 | ||
3668 | INIT_LIST_HEAD(&hsotg->gadget.ep_list); | |
c6f5c050 | 3669 | hsotg->gadget.ep0 = &hsotg->eps_out[0]->ep; |
b3f489b2 LM |
3670 | |
3671 | /* allocate EP0 request */ | |
3672 | ||
c6f5c050 | 3673 | hsotg->ctrl_req = s3c_hsotg_ep_alloc_request(&hsotg->eps_out[0]->ep, |
b3f489b2 LM |
3674 | GFP_KERNEL); |
3675 | if (!hsotg->ctrl_req) { | |
3676 | dev_err(dev, "failed to allocate ctrl req\n"); | |
dfdda5a0 | 3677 | ret = -ENOMEM; |
c6f5c050 | 3678 | goto err_supplies; |
b3f489b2 | 3679 | } |
5b7d70c6 BD |
3680 | |
3681 | /* initialise the endpoints now the core has been initialised */ | |
c6f5c050 MYK |
3682 | for (epnum = 0; epnum < hsotg->num_of_eps; epnum++) { |
3683 | if (hsotg->eps_in[epnum]) | |
3684 | s3c_hsotg_initep(hsotg, hsotg->eps_in[epnum], | |
3685 | epnum, 1); | |
3686 | if (hsotg->eps_out[epnum]) | |
3687 | s3c_hsotg_initep(hsotg, hsotg->eps_out[epnum], | |
3688 | epnum, 0); | |
3689 | } | |
5b7d70c6 | 3690 | |
f65f0f10 | 3691 | /* disable power and clock */ |
3a8146aa | 3692 | s3c_hsotg_phy_disable(hsotg); |
f65f0f10 LM |
3693 | |
3694 | ret = regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies), | |
3695 | hsotg->supplies); | |
3696 | if (ret) { | |
117777b2 | 3697 | dev_err(dev, "failed to disable supplies: %d\n", ret); |
c6f5c050 | 3698 | goto err_supplies; |
f65f0f10 LM |
3699 | } |
3700 | ||
117777b2 | 3701 | ret = usb_add_gadget_udc(dev, &hsotg->gadget); |
0f91349b | 3702 | if (ret) |
c6f5c050 | 3703 | goto err_supplies; |
0f91349b | 3704 | |
5b7d70c6 BD |
3705 | s3c_hsotg_create_debug(hsotg); |
3706 | ||
3707 | s3c_hsotg_dump(hsotg); | |
3708 | ||
5b7d70c6 BD |
3709 | return 0; |
3710 | ||
fc9a731e | 3711 | err_supplies: |
41188786 | 3712 | s3c_hsotg_phy_disable(hsotg); |
31ee04de | 3713 | err_clk: |
1d144c67 | 3714 | clk_disable_unprepare(hsotg->clk); |
338edabc | 3715 | |
5b7d70c6 BD |
3716 | return ret; |
3717 | } | |
117777b2 | 3718 | EXPORT_SYMBOL_GPL(dwc2_gadget_init); |
5b7d70c6 | 3719 | |
8b9bc460 LM |
3720 | /** |
3721 | * s3c_hsotg_remove - remove function for hsotg driver | |
3722 | * @pdev: The platform information for the driver | |
3723 | */ | |
117777b2 | 3724 | int s3c_hsotg_remove(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 3725 | { |
0f91349b | 3726 | usb_del_gadget_udc(&hsotg->gadget); |
5b7d70c6 | 3727 | s3c_hsotg_delete_debug(hsotg); |
04b4a0fc | 3728 | clk_disable_unprepare(hsotg->clk); |
31ee04de | 3729 | |
5b7d70c6 BD |
3730 | return 0; |
3731 | } | |
117777b2 | 3732 | EXPORT_SYMBOL_GPL(s3c_hsotg_remove); |
5b7d70c6 | 3733 | |
117777b2 | 3734 | int s3c_hsotg_suspend(struct dwc2_hsotg *hsotg) |
b83e333a | 3735 | { |
b83e333a MS |
3736 | unsigned long flags; |
3737 | int ret = 0; | |
3738 | ||
7ad8096e MS |
3739 | mutex_lock(&hsotg->init_mutex); |
3740 | ||
dc6e69e6 MS |
3741 | if (hsotg->driver) { |
3742 | int ep; | |
3743 | ||
b83e333a MS |
3744 | dev_info(hsotg->dev, "suspending usb gadget %s\n", |
3745 | hsotg->driver->driver.name); | |
3746 | ||
dc6e69e6 MS |
3747 | spin_lock_irqsave(&hsotg->lock, flags); |
3748 | if (hsotg->enabled) | |
3749 | s3c_hsotg_core_disconnect(hsotg); | |
3750 | s3c_hsotg_disconnect(hsotg); | |
3751 | hsotg->gadget.speed = USB_SPEED_UNKNOWN; | |
3752 | spin_unlock_irqrestore(&hsotg->lock, flags); | |
b83e333a | 3753 | |
dc6e69e6 | 3754 | s3c_hsotg_phy_disable(hsotg); |
b83e333a | 3755 | |
c6f5c050 MYK |
3756 | for (ep = 0; ep < hsotg->num_of_eps; ep++) { |
3757 | if (hsotg->eps_in[ep]) | |
3758 | s3c_hsotg_ep_disable(&hsotg->eps_in[ep]->ep); | |
3759 | if (hsotg->eps_out[ep]) | |
3760 | s3c_hsotg_ep_disable(&hsotg->eps_out[ep]->ep); | |
3761 | } | |
b83e333a MS |
3762 | |
3763 | ret = regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies), | |
3764 | hsotg->supplies); | |
d00b4142 | 3765 | clk_disable(hsotg->clk); |
b83e333a MS |
3766 | } |
3767 | ||
7ad8096e MS |
3768 | mutex_unlock(&hsotg->init_mutex); |
3769 | ||
b83e333a MS |
3770 | return ret; |
3771 | } | |
117777b2 | 3772 | EXPORT_SYMBOL_GPL(s3c_hsotg_suspend); |
b83e333a | 3773 | |
117777b2 | 3774 | int s3c_hsotg_resume(struct dwc2_hsotg *hsotg) |
b83e333a | 3775 | { |
b83e333a MS |
3776 | unsigned long flags; |
3777 | int ret = 0; | |
3778 | ||
7ad8096e MS |
3779 | mutex_lock(&hsotg->init_mutex); |
3780 | ||
b83e333a MS |
3781 | if (hsotg->driver) { |
3782 | dev_info(hsotg->dev, "resuming usb gadget %s\n", | |
3783 | hsotg->driver->driver.name); | |
d00b4142 RB |
3784 | |
3785 | clk_enable(hsotg->clk); | |
b83e333a | 3786 | ret = regulator_bulk_enable(ARRAY_SIZE(hsotg->supplies), |
dc6e69e6 | 3787 | hsotg->supplies); |
b83e333a | 3788 | |
dc6e69e6 | 3789 | s3c_hsotg_phy_enable(hsotg); |
b83e333a | 3790 | |
dc6e69e6 MS |
3791 | spin_lock_irqsave(&hsotg->lock, flags); |
3792 | s3c_hsotg_core_init_disconnected(hsotg); | |
3793 | if (hsotg->enabled) | |
3794 | s3c_hsotg_core_connect(hsotg); | |
3795 | spin_unlock_irqrestore(&hsotg->lock, flags); | |
3796 | } | |
7ad8096e | 3797 | mutex_unlock(&hsotg->init_mutex); |
b83e333a MS |
3798 | |
3799 | return ret; | |
3800 | } | |
117777b2 | 3801 | EXPORT_SYMBOL_GPL(s3c_hsotg_resume); |