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usb: mtu3: make USB_MTU3_DUAL_ROLE depend on EXTCON but not USB_MTU3
[linux-block.git] / drivers / usb / dwc2 / gadget.c
CommitLineData
5fd54ace 1// SPDX-License-Identifier: GPL-2.0
8b9bc460 2/**
dfbc6fa3
AT		 3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5b7d70c6
BD		 5 *
6 * Copyright 2008 Openmoko, Inc.
7 * Copyright 2008 Simtec Electronics
8 * Ben Dooks <ben@simtec.co.uk>
9 * http://armlinux.simtec.co.uk/
10 *
11 * S3C USB2.0 High-speed / OtG driver
8b9bc460 12 */
5b7d70c6
BD		 13
14#include <linux/kernel.h>
15#include <linux/module.h>
16#include <linux/spinlock.h>
17#include <linux/interrupt.h>
18#include <linux/platform_device.h>
19#include <linux/dma-mapping.h>
7ad8096e 20#include <linux/mutex.h>
5b7d70c6
BD		 21#include <linux/seq_file.h>
22#include <linux/delay.h>
23#include <linux/io.h>
5a0e3ad6 24#include <linux/slab.h>
c50f056c 25#include <linux/of_platform.h>
5b7d70c6
BD		 26
27#include <linux/usb/ch9.h>
28#include <linux/usb/gadget.h>
b2e587db 29#include <linux/usb/phy.h>
5b7d70c6 30
f7c0b143 31#include "core.h"
941fcce4 32#include "hw.h"
5b7d70c6
BD		 33
34/* conversion functions */
1f91b4cc 35static inline struct dwc2_hsotg_req *our_req(struct usb_request *req)
5b7d70c6 36{
1f91b4cc 37 return container_of(req, struct dwc2_hsotg_req, req);
5b7d70c6
BD		 38}
39
1f91b4cc 40static inline struct dwc2_hsotg_ep *our_ep(struct usb_ep *ep)
5b7d70c6 41{
1f91b4cc 42 return container_of(ep, struct dwc2_hsotg_ep, ep);
5b7d70c6
BD		 43}
44
941fcce4 45static inline struct dwc2_hsotg *to_hsotg(struct usb_gadget *gadget)
5b7d70c6 46{
941fcce4 47 return container_of(gadget, struct dwc2_hsotg, gadget);
5b7d70c6
BD		 48}
49
abd064a1 50static inline void dwc2_set_bit(void __iomem *ptr, u32 val)
5b7d70c6 51{
95c8bc36 52 dwc2_writel(dwc2_readl(ptr) | val, ptr);
5b7d70c6
BD		 53}
54
abd064a1 55static inline void dwc2_clear_bit(void __iomem *ptr, u32 val)
5b7d70c6 56{
95c8bc36 57 dwc2_writel(dwc2_readl(ptr) & ~val, ptr);
5b7d70c6
BD		 58}
59
1f91b4cc 60static inline struct dwc2_hsotg_ep *index_to_ep(struct dwc2_hsotg *hsotg,
c6f5c050
MYK		 61 u32 ep_index, u32 dir_in)
62{
63 if (dir_in)
64 return hsotg->eps_in[ep_index];
65 else
66 return hsotg->eps_out[ep_index];
67}
68
997f4f81 69/* forward declaration of functions */
1f91b4cc 70static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg);
5b7d70c6
BD		 71
72/**
73 * using_dma - return the DMA status of the driver.
74 * @hsotg: The driver state.
75 *
76 * Return true if we're using DMA.
77 *
78 * Currently, we have the DMA support code worked into everywhere
79 * that needs it, but the AMBA DMA implementation in the hardware can
80 * only DMA from 32bit aligned addresses. This means that gadgets such
81 * as the CDC Ethernet cannot work as they often pass packets which are
82 * not 32bit aligned.
83 *
84 * Unfortunately the choice to use DMA or not is global to the controller
85 * and seems to be only settable when the controller is being put through
86 * a core reset. This means we either need to fix the gadgets to take
87 * account of DMA alignment, or add bounce buffers (yuerk).
88 *
edd74be8 89 * g_using_dma is set depending on dts flag.
5b7d70c6 90 */
941fcce4 91static inline bool using_dma(struct dwc2_hsotg *hsotg)
5b7d70c6 92{
05ee799f 93 return hsotg->params.g_dma;
5b7d70c6
BD		 94}
95
dec4b556
VA		 96/*
97 * using_desc_dma - return the descriptor DMA status of the driver.
98 * @hsotg: The driver state.
99 *
100 * Return true if we're using descriptor DMA.
101 */
102static inline bool using_desc_dma(struct dwc2_hsotg *hsotg)
103{
104 return hsotg->params.g_dma_desc;
105}
106
92d1635d
VM		 107/**
108 * dwc2_gadget_incr_frame_num - Increments the targeted frame number.
109 * @hs_ep: The endpoint
110 * @increment: The value to increment by
111 *
112 * This function will also check if the frame number overruns DSTS_SOFFN_LIMIT.
113 * If an overrun occurs it will wrap the value and set the frame_overrun flag.
114 */
115static inline void dwc2_gadget_incr_frame_num(struct dwc2_hsotg_ep *hs_ep)
116{
117 hs_ep->target_frame += hs_ep->interval;
118 if (hs_ep->target_frame > DSTS_SOFFN_LIMIT) {
c1d5df69 119 hs_ep->frame_overrun = true;
92d1635d
VM		 120 hs_ep->target_frame &= DSTS_SOFFN_LIMIT;
121 } else {
c1d5df69 122 hs_ep->frame_overrun = false;
92d1635d
VM		 123 }
124}
125
5b7d70c6 126/**
1f91b4cc 127 * dwc2_hsotg_en_gsint - enable one or more of the general interrupt
5b7d70c6
BD		 128 * @hsotg: The device state
129 * @ints: A bitmask of the interrupts to enable
130 */
1f91b4cc 131static void dwc2_hsotg_en_gsint(struct dwc2_hsotg *hsotg, u32 ints)
5b7d70c6 132{
95c8bc36 133 u32 gsintmsk = dwc2_readl(hsotg->regs + GINTMSK);
5b7d70c6
BD		 134 u32 new_gsintmsk;
135
136 new_gsintmsk = gsintmsk | ints;
137
138 if (new_gsintmsk != gsintmsk) {
139 dev_dbg(hsotg->dev, "gsintmsk now 0x%08x\n", new_gsintmsk);
95c8bc36 140 dwc2_writel(new_gsintmsk, hsotg->regs + GINTMSK);
5b7d70c6
BD		 141 }
142}
143
144/**
1f91b4cc 145 * dwc2_hsotg_disable_gsint - disable one or more of the general interrupt
5b7d70c6
BD		 146 * @hsotg: The device state
147 * @ints: A bitmask of the interrupts to enable
148 */
1f91b4cc 149static void dwc2_hsotg_disable_gsint(struct dwc2_hsotg *hsotg, u32 ints)
5b7d70c6 150{
95c8bc36 151 u32 gsintmsk = dwc2_readl(hsotg->regs + GINTMSK);
5b7d70c6
BD		 152 u32 new_gsintmsk;
153
154 new_gsintmsk = gsintmsk & ~ints;
155
156 if (new_gsintmsk != gsintmsk)
95c8bc36 157 dwc2_writel(new_gsintmsk, hsotg->regs + GINTMSK);
5b7d70c6
BD		 158}
159
160/**
1f91b4cc 161 * dwc2_hsotg_ctrl_epint - enable/disable an endpoint irq
5b7d70c6
BD		 162 * @hsotg: The device state
163 * @ep: The endpoint index
164 * @dir_in: True if direction is in.
165 * @en: The enable value, true to enable
166 *
167 * Set or clear the mask for an individual endpoint's interrupt
168 * request.
169 */
1f91b4cc 170static void dwc2_hsotg_ctrl_epint(struct dwc2_hsotg *hsotg,
9da51974 171 unsigned int ep, unsigned int dir_in,
5b7d70c6
BD		 172 unsigned int en)
173{
174 unsigned long flags;
175 u32 bit = 1 << ep;
176 u32 daint;
177
178 if (!dir_in)
179 bit <<= 16;
180
181 local_irq_save(flags);
95c8bc36 182 daint = dwc2_readl(hsotg->regs + DAINTMSK);
5b7d70c6
BD		 183 if (en)
184 daint |= bit;
185 else
186 daint &= ~bit;
95c8bc36 187 dwc2_writel(daint, hsotg->regs + DAINTMSK);
5b7d70c6
BD		 188 local_irq_restore(flags);
189}
190
c138ecfa
SA		 191/**
192 * dwc2_hsotg_tx_fifo_count - return count of TX FIFOs in device mode
193 */
194int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg *hsotg)
195{
196 if (hsotg->hw_params.en_multiple_tx_fifo)
197 /* In dedicated FIFO mode we need count of IN EPs */
9273083a 198 return hsotg->hw_params.num_dev_in_eps;
c138ecfa
SA		 199 else
200 /* In shared FIFO mode we need count of Periodic IN EPs */
201 return hsotg->hw_params.num_dev_perio_in_ep;
202}
203
c138ecfa
SA		 204/**
205 * dwc2_hsotg_tx_fifo_total_depth - return total FIFO depth available for
206 * device mode TX FIFOs
207 */
208int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg)
209{
c138ecfa
SA		 210 int addr;
211 int tx_addr_max;
212 u32 np_tx_fifo_size;
213
214 np_tx_fifo_size = min_t(u32, hsotg->hw_params.dev_nperio_tx_fifo_size,
215 hsotg->params.g_np_tx_fifo_size);
216
217 /* Get Endpoint Info Control block size in DWORDs. */
9273083a 218 tx_addr_max = hsotg->hw_params.total_fifo_size;
c138ecfa
SA		 219
220 addr = hsotg->params.g_rx_fifo_size + np_tx_fifo_size;
221 if (tx_addr_max <= addr)
222 return 0;
223
224 return tx_addr_max - addr;
225}
226
227/**
228 * dwc2_hsotg_tx_fifo_average_depth - returns average depth of device mode
229 * TX FIFOs
230 */
231int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg *hsotg)
232{
233 int tx_fifo_count;
234 int tx_fifo_depth;
235
236 tx_fifo_depth = dwc2_hsotg_tx_fifo_total_depth(hsotg);
237
238 tx_fifo_count = dwc2_hsotg_tx_fifo_count(hsotg);
239
240 if (!tx_fifo_count)
241 return tx_fifo_depth;
242 else
243 return tx_fifo_depth / tx_fifo_count;
244}
245
5b7d70c6 246/**
1f91b4cc 247 * dwc2_hsotg_init_fifo - initialise non-periodic FIFOs
5b7d70c6
BD		 248 * @hsotg: The device instance.
249 */
1f91b4cc 250static void dwc2_hsotg_init_fifo(struct dwc2_hsotg *hsotg)
5b7d70c6 251{
2317eacd 252 unsigned int ep;
0f002d20 253 unsigned int addr;
1703a6d3 254 int timeout;
79d6b8c5 255
0f002d20 256 u32 val;
05ee799f 257 u32 *txfsz = hsotg->params.g_tx_fifo_size;
0f002d20 258
7fcbc95c
GH		 259 /* Reset fifo map if not correctly cleared during previous session */
260 WARN_ON(hsotg->fifo_map);
261 hsotg->fifo_map = 0;
262
0a176279 263 /* set RX/NPTX FIFO sizes */
05ee799f
JY		 264 dwc2_writel(hsotg->params.g_rx_fifo_size, hsotg->regs + GRXFSIZ);
265 dwc2_writel((hsotg->params.g_rx_fifo_size << FIFOSIZE_STARTADDR_SHIFT) |
266 (hsotg->params.g_np_tx_fifo_size << FIFOSIZE_DEPTH_SHIFT),
267 hsotg->regs + GNPTXFSIZ);
0f002d20 268
8b9bc460
LM		 269 /*
270 * arange all the rest of the TX FIFOs, as some versions of this
0f002d20
BD		 271 * block have overlapping default addresses. This also ensures
272 * that if the settings have been changed, then they are set to
8b9bc460
LM		 273 * known values.
274 */
0f002d20
BD		 275
276 /* start at the end of the GNPTXFSIZ, rounded up */
05ee799f 277 addr = hsotg->params.g_rx_fifo_size + hsotg->params.g_np_tx_fifo_size;
0f002d20 278
8b9bc460 279 /*
0a176279 280 * Configure fifos sizes from provided configuration and assign
b203d0a2
RB		 281 * them to endpoints dynamically according to maxpacket size value of
282 * given endpoint.
8b9bc460 283 */
2317eacd 284 for (ep = 1; ep < MAX_EPS_CHANNELS; ep++) {
05ee799f 285 if (!txfsz[ep])
3fa95385
JY		 286 continue;
287 val = addr;
05ee799f
JY		 288 val |= txfsz[ep] << FIFOSIZE_DEPTH_SHIFT;
289 WARN_ONCE(addr + txfsz[ep] > hsotg->fifo_mem,
3fa95385 290 "insufficient fifo memory");
05ee799f 291 addr += txfsz[ep];
0f002d20 292
2317eacd 293 dwc2_writel(val, hsotg->regs + DPTXFSIZN(ep));
05ee799f 294 val = dwc2_readl(hsotg->regs + DPTXFSIZN(ep));
0f002d20 295 }
1703a6d3 296
f87c842f
SA		 297 dwc2_writel(hsotg->hw_params.total_fifo_size |
298 addr << GDFIFOCFG_EPINFOBASE_SHIFT,
299 hsotg->regs + GDFIFOCFG);
8b9bc460
LM		 300 /*
301 * according to p428 of the design guide, we need to ensure that
302 * all fifos are flushed before continuing
303 */
1703a6d3 304
95c8bc36 305 dwc2_writel(GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH |
47a1685f 306 GRSTCTL_RXFFLSH, hsotg->regs + GRSTCTL);
1703a6d3
BD		 307
308 /* wait until the fifos are both flushed */
309 timeout = 100;
310 while (1) {
95c8bc36 311 val = dwc2_readl(hsotg->regs + GRSTCTL);
1703a6d3 312
47a1685f 313 if ((val & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH)) == 0)
1703a6d3
BD		 314 break;
315
316 if (--timeout == 0) {
317 dev_err(hsotg->dev,
318 "%s: timeout flushing fifos (GRSTCTL=%08x)\n",
319 __func__, val);
48b20bcb 320 break;
1703a6d3
BD		 321 }
322
323 udelay(1);
324 }
325
326 dev_dbg(hsotg->dev, "FIFOs reset, timeout at %d\n", timeout);
5b7d70c6
BD		 327}
328
329/**
330 * @ep: USB endpoint to allocate request for.
331 * @flags: Allocation flags
332 *
333 * Allocate a new USB request structure appropriate for the specified endpoint
334 */
1f91b4cc 335static struct usb_request *dwc2_hsotg_ep_alloc_request(struct usb_ep *ep,
9da51974 336 gfp_t flags)
5b7d70c6 337{
1f91b4cc 338 struct dwc2_hsotg_req *req;
5b7d70c6 339
ec33efe2 340 req = kzalloc(sizeof(*req), flags);
5b7d70c6
BD		 341 if (!req)
342 return NULL;
343
344 INIT_LIST_HEAD(&req->queue);
345
5b7d70c6
BD		 346 return &req->req;
347}
348
349/**
350 * is_ep_periodic - return true if the endpoint is in periodic mode.
351 * @hs_ep: The endpoint to query.
352 *
353 * Returns true if the endpoint is in periodic mode, meaning it is being
354 * used for an Interrupt or ISO transfer.
355 */
1f91b4cc 356static inline int is_ep_periodic(struct dwc2_hsotg_ep *hs_ep)
5b7d70c6
BD		 357{
358 return hs_ep->periodic;
359}
360
361/**
1f91b4cc 362 * dwc2_hsotg_unmap_dma - unmap the DMA memory being used for the request
5b7d70c6
BD		 363 * @hsotg: The device state.
364 * @hs_ep: The endpoint for the request
365 * @hs_req: The request being processed.
366 *
1f91b4cc 367 * This is the reverse of dwc2_hsotg_map_dma(), called for the completion
5b7d70c6 368 * of a request to ensure the buffer is ready for access by the caller.
8b9bc460 369 */
1f91b4cc 370static void dwc2_hsotg_unmap_dma(struct dwc2_hsotg *hsotg,
9da51974 371 struct dwc2_hsotg_ep *hs_ep,
1f91b4cc 372 struct dwc2_hsotg_req *hs_req)
5b7d70c6
BD		 373{
374 struct usb_request *req = &hs_req->req;
9da51974 375
17d966a3 376 usb_gadget_unmap_request(&hsotg->gadget, req, hs_ep->dir_in);
5b7d70c6
BD		 377}
378
0f6b80c0
VA		 379/*
380 * dwc2_gadget_alloc_ctrl_desc_chains - allocate DMA descriptor chains
381 * for Control endpoint
382 * @hsotg: The device state.
383 *
384 * This function will allocate 4 descriptor chains for EP 0: 2 for
385 * Setup stage, per one for IN and OUT data/status transactions.
386 */
387static int dwc2_gadget_alloc_ctrl_desc_chains(struct dwc2_hsotg *hsotg)
388{
389 hsotg->setup_desc[0] =
390 dmam_alloc_coherent(hsotg->dev,
391 sizeof(struct dwc2_dma_desc),
392 &hsotg->setup_desc_dma[0],
393 GFP_KERNEL);
394 if (!hsotg->setup_desc[0])
395 goto fail;
396
397 hsotg->setup_desc[1] =
398 dmam_alloc_coherent(hsotg->dev,
399 sizeof(struct dwc2_dma_desc),
400 &hsotg->setup_desc_dma[1],
401 GFP_KERNEL);
402 if (!hsotg->setup_desc[1])
403 goto fail;
404
405 hsotg->ctrl_in_desc =
406 dmam_alloc_coherent(hsotg->dev,
407 sizeof(struct dwc2_dma_desc),
408 &hsotg->ctrl_in_desc_dma,
409 GFP_KERNEL);
410 if (!hsotg->ctrl_in_desc)
411 goto fail;
412
413 hsotg->ctrl_out_desc =
414 dmam_alloc_coherent(hsotg->dev,
415 sizeof(struct dwc2_dma_desc),
416 &hsotg->ctrl_out_desc_dma,
417 GFP_KERNEL);
418 if (!hsotg->ctrl_out_desc)
419 goto fail;
420
421 return 0;
422
423fail:
424 return -ENOMEM;
425}
426
5b7d70c6 427/**
1f91b4cc 428 * dwc2_hsotg_write_fifo - write packet Data to the TxFIFO
5b7d70c6
BD		 429 * @hsotg: The controller state.
430 * @hs_ep: The endpoint we're going to write for.
431 * @hs_req: The request to write data for.
432 *
433 * This is called when the TxFIFO has some space in it to hold a new
434 * transmission and we have something to give it. The actual setup of
435 * the data size is done elsewhere, so all we have to do is to actually
436 * write the data.
437 *
438 * The return value is zero if there is more space (or nothing was done)
439 * otherwise -ENOSPC is returned if the FIFO space was used up.
440 *
441 * This routine is only needed for PIO
8b9bc460 442 */
1f91b4cc 443static int dwc2_hsotg_write_fifo(struct dwc2_hsotg *hsotg,
9da51974 444 struct dwc2_hsotg_ep *hs_ep,
1f91b4cc 445 struct dwc2_hsotg_req *hs_req)
5b7d70c6
BD		 446{
447 bool periodic = is_ep_periodic(hs_ep);
95c8bc36 448 u32 gnptxsts = dwc2_readl(hsotg->regs + GNPTXSTS);
5b7d70c6
BD		 449 int buf_pos = hs_req->req.actual;
450 int to_write = hs_ep->size_loaded;
451 void *data;
452 int can_write;
453 int pkt_round;
4fca54aa 454 int max_transfer;
5b7d70c6
BD		 455
456 to_write -= (buf_pos - hs_ep->last_load);
457
458 /* if there's nothing to write, get out early */
459 if (to_write == 0)
460 return 0;
461
10aebc77 462 if (periodic && !hsotg->dedicated_fifos) {
95c8bc36 463 u32 epsize = dwc2_readl(hsotg->regs + DIEPTSIZ(hs_ep->index));
5b7d70c6
BD		 464 int size_left;
465 int size_done;
466
8b9bc460
LM		 467 /*
468 * work out how much data was loaded so we can calculate
469 * how much data is left in the fifo.
470 */
5b7d70c6 471
47a1685f 472 size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
5b7d70c6 473
8b9bc460
LM		 474 /*
475 * if shared fifo, we cannot write anything until the
e7a9ff54
BD		 476 * previous data has been completely sent.
477 */
478 if (hs_ep->fifo_load != 0) {
1f91b4cc 479 dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP);
e7a9ff54
BD		 480 return -ENOSPC;
481 }
482
5b7d70c6
BD		 483 dev_dbg(hsotg->dev, "%s: left=%d, load=%d, fifo=%d, size %d\n",
484 __func__, size_left,
485 hs_ep->size_loaded, hs_ep->fifo_load, hs_ep->fifo_size);
486
487 /* how much of the data has moved */
488 size_done = hs_ep->size_loaded - size_left;
489
490 /* how much data is left in the fifo */
491 can_write = hs_ep->fifo_load - size_done;
492 dev_dbg(hsotg->dev, "%s: => can_write1=%d\n",
493 __func__, can_write);
494
495 can_write = hs_ep->fifo_size - can_write;
496 dev_dbg(hsotg->dev, "%s: => can_write2=%d\n",
497 __func__, can_write);
498
499 if (can_write <= 0) {
1f91b4cc 500 dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP);
5b7d70c6
BD		 501 return -ENOSPC;
502 }
10aebc77 503 } else if (hsotg->dedicated_fifos && hs_ep->index != 0) {
ad674a15
RB		 504 can_write = dwc2_readl(hsotg->regs +
505 DTXFSTS(hs_ep->fifo_index));
10aebc77
BD		 506
507 can_write &= 0xffff;
508 can_write *= 4;
5b7d70c6 509 } else {
47a1685f 510 if (GNPTXSTS_NP_TXQ_SPC_AVAIL_GET(gnptxsts) == 0) {
5b7d70c6
BD		 511 dev_dbg(hsotg->dev,
512 "%s: no queue slots available (0x%08x)\n",
513 __func__, gnptxsts);
514
1f91b4cc 515 dwc2_hsotg_en_gsint(hsotg, GINTSTS_NPTXFEMP);
5b7d70c6
BD		 516 return -ENOSPC;
517 }
518
47a1685f 519 can_write = GNPTXSTS_NP_TXF_SPC_AVAIL_GET(gnptxsts);
679f9b7c 520 can_write *= 4; /* fifo size is in 32bit quantities. */
5b7d70c6
BD		 521 }
522
4fca54aa
RB		 523 max_transfer = hs_ep->ep.maxpacket * hs_ep->mc;
524
525 dev_dbg(hsotg->dev, "%s: GNPTXSTS=%08x, can=%d, to=%d, max_transfer %d\n",
9da51974 526 __func__, gnptxsts, can_write, to_write, max_transfer);
5b7d70c6 527
8b9bc460
LM		 528 /*
529 * limit to 512 bytes of data, it seems at least on the non-periodic
5b7d70c6
BD		 530 * FIFO, requests of >512 cause the endpoint to get stuck with a
531 * fragment of the end of the transfer in it.
532 */
811f3303 533 if (can_write > 512 && !periodic)
5b7d70c6
BD		 534 can_write = 512;
535
8b9bc460
LM		 536 /*
537 * limit the write to one max-packet size worth of data, but allow
03e10e5a 538 * the transfer to return that it did not run out of fifo space
8b9bc460
LM		 539 * doing it.
540 */
4fca54aa
RB		 541 if (to_write > max_transfer) {
542 to_write = max_transfer;
03e10e5a 543
5cb2ff0c
RB		 544 /* it's needed only when we do not use dedicated fifos */
545 if (!hsotg->dedicated_fifos)
1f91b4cc 546 dwc2_hsotg_en_gsint(hsotg,
9da51974 547 periodic ? GINTSTS_PTXFEMP :
47a1685f 548 GINTSTS_NPTXFEMP);
03e10e5a
BD		 549 }
550
5b7d70c6
BD		 551 /* see if we can write data */
552
553 if (to_write > can_write) {
554 to_write = can_write;
4fca54aa 555 pkt_round = to_write % max_transfer;
5b7d70c6 556
8b9bc460
LM		 557 /*
558 * Round the write down to an
5b7d70c6
BD		 559 * exact number of packets.
560 *
561 * Note, we do not currently check to see if we can ever
562 * write a full packet or not to the FIFO.
563 */
564
565 if (pkt_round)
566 to_write -= pkt_round;
567
8b9bc460
LM		 568 /*
569 * enable correct FIFO interrupt to alert us when there
570 * is more room left.
571 */
5b7d70c6 572
5cb2ff0c
RB		 573 /* it's needed only when we do not use dedicated fifos */
574 if (!hsotg->dedicated_fifos)
1f91b4cc 575 dwc2_hsotg_en_gsint(hsotg,
9da51974 576 periodic ? GINTSTS_PTXFEMP :
47a1685f 577 GINTSTS_NPTXFEMP);
5b7d70c6
BD		 578 }
579
580 dev_dbg(hsotg->dev, "write %d/%d, can_write %d, done %d\n",
9da51974 581 to_write, hs_req->req.length, can_write, buf_pos);
5b7d70c6
BD		 582
583 if (to_write <= 0)
584 return -ENOSPC;
585
586 hs_req->req.actual = buf_pos + to_write;
587 hs_ep->total_data += to_write;
588
589 if (periodic)
590 hs_ep->fifo_load += to_write;
591
592 to_write = DIV_ROUND_UP(to_write, 4);
593 data = hs_req->req.buf + buf_pos;
594
1a7ed5be 595 iowrite32_rep(hsotg->regs + EPFIFO(hs_ep->index), data, to_write);
5b7d70c6
BD		 596
597 return (to_write >= can_write) ? -ENOSPC : 0;
598}
599
600/**
601 * get_ep_limit - get the maximum data legnth for this endpoint
602 * @hs_ep: The endpoint
603 *
604 * Return the maximum data that can be queued in one go on a given endpoint
605 * so that transfers that are too long can be split.
606 */
9da51974 607static unsigned int get_ep_limit(struct dwc2_hsotg_ep *hs_ep)
5b7d70c6
BD		 608{
609 int index = hs_ep->index;
9da51974
JY		 610 unsigned int maxsize;
611 unsigned int maxpkt;
5b7d70c6
BD		 612
613 if (index != 0) {
47a1685f
DN		 614 maxsize = DXEPTSIZ_XFERSIZE_LIMIT + 1;
615 maxpkt = DXEPTSIZ_PKTCNT_LIMIT + 1;
5b7d70c6 616 } else {
9da51974 617 maxsize = 64 + 64;
66e5c643 618 if (hs_ep->dir_in)
47a1685f 619 maxpkt = DIEPTSIZ0_PKTCNT_LIMIT + 1;
66e5c643 620 else
5b7d70c6 621 maxpkt = 2;
5b7d70c6
BD		 622 }
623
624 /* we made the constant loading easier above by using +1 */
625 maxpkt--;
626 maxsize--;
627
8b9bc460
LM		 628 /*
629 * constrain by packet count if maxpkts*pktsize is greater
630 * than the length register size.
631 */
5b7d70c6
BD		 632
633 if ((maxpkt * hs_ep->ep.maxpacket) < maxsize)
634 maxsize = maxpkt * hs_ep->ep.maxpacket;
635
636 return maxsize;
637}
638
381fc8f8 639/**
38beaec6
JY		 640 * dwc2_hsotg_read_frameno - read current frame number
641 * @hsotg: The device instance
642 *
643 * Return the current frame number
644 */
381fc8f8
VM		 645static u32 dwc2_hsotg_read_frameno(struct dwc2_hsotg *hsotg)
646{
647 u32 dsts;
648
649 dsts = dwc2_readl(hsotg->regs + DSTS);
650 dsts &= DSTS_SOFFN_MASK;
651 dsts >>= DSTS_SOFFN_SHIFT;
652
653 return dsts;
654}
655
cf77b5fb
VA		 656/**
657 * dwc2_gadget_get_chain_limit - get the maximum data payload value of the
658 * DMA descriptor chain prepared for specific endpoint
659 * @hs_ep: The endpoint
660 *
661 * Return the maximum data that can be queued in one go on a given endpoint
662 * depending on its descriptor chain capacity so that transfers that
663 * are too long can be split.
664 */
665static unsigned int dwc2_gadget_get_chain_limit(struct dwc2_hsotg_ep *hs_ep)
666{
667 int is_isoc = hs_ep->isochronous;
668 unsigned int maxsize;
669
670 if (is_isoc)
671 maxsize = hs_ep->dir_in ? DEV_DMA_ISOC_TX_NBYTES_LIMIT :
672 DEV_DMA_ISOC_RX_NBYTES_LIMIT;
673 else
674 maxsize = DEV_DMA_NBYTES_LIMIT;
675
676 /* Above size of one descriptor was chosen, multiple it */
677 maxsize *= MAX_DMA_DESC_NUM_GENERIC;
678
679 return maxsize;
680}
681
e02f9aa6
VA		 682/*
683 * dwc2_gadget_get_desc_params - get DMA descriptor parameters.
684 * @hs_ep: The endpoint
685 * @mask: RX/TX bytes mask to be defined
686 *
687 * Returns maximum data payload for one descriptor after analyzing endpoint
688 * characteristics.
689 * DMA descriptor transfer bytes limit depends on EP type:
690 * Control out - MPS,
691 * Isochronous - descriptor rx/tx bytes bitfield limit,
692 * Control In/Bulk/Interrupt - multiple of mps. This will allow to not
693 * have concatenations from various descriptors within one packet.
694 *
695 * Selects corresponding mask for RX/TX bytes as well.
696 */
697static u32 dwc2_gadget_get_desc_params(struct dwc2_hsotg_ep *hs_ep, u32 *mask)
698{
699 u32 mps = hs_ep->ep.maxpacket;
700 int dir_in = hs_ep->dir_in;
701 u32 desc_size = 0;
702
703 if (!hs_ep->index && !dir_in) {
704 desc_size = mps;
705 *mask = DEV_DMA_NBYTES_MASK;
706 } else if (hs_ep->isochronous) {
707 if (dir_in) {
708 desc_size = DEV_DMA_ISOC_TX_NBYTES_LIMIT;
709 *mask = DEV_DMA_ISOC_TX_NBYTES_MASK;
710 } else {
711 desc_size = DEV_DMA_ISOC_RX_NBYTES_LIMIT;
712 *mask = DEV_DMA_ISOC_RX_NBYTES_MASK;
713 }
714 } else {
715 desc_size = DEV_DMA_NBYTES_LIMIT;
716 *mask = DEV_DMA_NBYTES_MASK;
717
718 /* Round down desc_size to be mps multiple */
719 desc_size -= desc_size % mps;
720 }
721
722 return desc_size;
723}
724
725/*
726 * dwc2_gadget_config_nonisoc_xfer_ddma - prepare non ISOC DMA desc chain.
727 * @hs_ep: The endpoint
728 * @dma_buff: DMA address to use
729 * @len: Length of the transfer
730 *
731 * This function will iterate over descriptor chain and fill its entries
732 * with corresponding information based on transfer data.
733 */
734static void dwc2_gadget_config_nonisoc_xfer_ddma(struct dwc2_hsotg_ep *hs_ep,
735 dma_addr_t dma_buff,
736 unsigned int len)
737{
738 struct dwc2_hsotg *hsotg = hs_ep->parent;
739 int dir_in = hs_ep->dir_in;
740 struct dwc2_dma_desc *desc = hs_ep->desc_list;
741 u32 mps = hs_ep->ep.maxpacket;
742 u32 maxsize = 0;
743 u32 offset = 0;
744 u32 mask = 0;
745 int i;
746
747 maxsize = dwc2_gadget_get_desc_params(hs_ep, &mask);
748
749 hs_ep->desc_count = (len / maxsize) +
750 ((len % maxsize) ? 1 : 0);
751 if (len == 0)
752 hs_ep->desc_count = 1;
753
754 for (i = 0; i < hs_ep->desc_count; ++i) {
755 desc->status = 0;
756 desc->status |= (DEV_DMA_BUFF_STS_HBUSY
757 << DEV_DMA_BUFF_STS_SHIFT);
758
759 if (len > maxsize) {
760 if (!hs_ep->index && !dir_in)
761 desc->status |= (DEV_DMA_L | DEV_DMA_IOC);
762
763 desc->status |= (maxsize <<
764 DEV_DMA_NBYTES_SHIFT & mask);
765 desc->buf = dma_buff + offset;
766
767 len -= maxsize;
768 offset += maxsize;
769 } else {
770 desc->status |= (DEV_DMA_L | DEV_DMA_IOC);
771
772 if (dir_in)
773 desc->status |= (len % mps) ? DEV_DMA_SHORT :
774 ((hs_ep->send_zlp) ? DEV_DMA_SHORT : 0);
775 if (len > maxsize)
776 dev_err(hsotg->dev, "wrong len %d\n", len);
777
778 desc->status |=
779 len << DEV_DMA_NBYTES_SHIFT & mask;
780 desc->buf = dma_buff + offset;
781 }
782
783 desc->status &= ~DEV_DMA_BUFF_STS_MASK;
784 desc->status |= (DEV_DMA_BUFF_STS_HREADY
785 << DEV_DMA_BUFF_STS_SHIFT);
786 desc++;
787 }
788}
789
540ccba0
VA		 790/*
791 * dwc2_gadget_fill_isoc_desc - fills next isochronous descriptor in chain.
792 * @hs_ep: The isochronous endpoint.
793 * @dma_buff: usb requests dma buffer.
794 * @len: usb request transfer length.
795 *
796 * Finds out index of first free entry either in the bottom or up half of
797 * descriptor chain depend on which is under SW control and not processed
798 * by HW. Then fills that descriptor with the data of the arrived usb request,
799 * frame info, sets Last and IOC bits increments next_desc. If filled
800 * descriptor is not the first one, removes L bit from the previous descriptor
801 * status.
802 */
803static int dwc2_gadget_fill_isoc_desc(struct dwc2_hsotg_ep *hs_ep,
804 dma_addr_t dma_buff, unsigned int len)
805{
806 struct dwc2_dma_desc *desc;
807 struct dwc2_hsotg *hsotg = hs_ep->parent;
808 u32 index;
809 u32 maxsize = 0;
810 u32 mask = 0;
811
812 maxsize = dwc2_gadget_get_desc_params(hs_ep, &mask);
813 if (len > maxsize) {
814 dev_err(hsotg->dev, "wrong len %d\n", len);
815 return -EINVAL;
816 }
817
818 /*
819 * If SW has already filled half of chain, then return and wait for
820 * the other chain to be processed by HW.
821 */
822 if (hs_ep->next_desc == MAX_DMA_DESC_NUM_GENERIC / 2)
823 return -EBUSY;
824
825 /* Increment frame number by interval for IN */
826 if (hs_ep->dir_in)
827 dwc2_gadget_incr_frame_num(hs_ep);
828
829 index = (MAX_DMA_DESC_NUM_GENERIC / 2) * hs_ep->isoc_chain_num +
830 hs_ep->next_desc;
831
832 /* Sanity check of calculated index */
833 if ((hs_ep->isoc_chain_num && index > MAX_DMA_DESC_NUM_GENERIC) ||
834 (!hs_ep->isoc_chain_num && index > MAX_DMA_DESC_NUM_GENERIC / 2)) {
835 dev_err(hsotg->dev, "wrong index %d for iso chain\n", index);
836 return -EINVAL;
837 }
838
839 desc = &hs_ep->desc_list[index];
840
841 /* Clear L bit of previous desc if more than one entries in the chain */
842 if (hs_ep->next_desc)
843 hs_ep->desc_list[index - 1].status &= ~DEV_DMA_L;
844
845 dev_dbg(hsotg->dev, "%s: Filling ep %d, dir %s isoc desc # %d\n",
846 __func__, hs_ep->index, hs_ep->dir_in ? "in" : "out", index);
847
848 desc->status = 0;
849 desc->status |= (DEV_DMA_BUFF_STS_HBUSY << DEV_DMA_BUFF_STS_SHIFT);
850
851 desc->buf = dma_buff;
852 desc->status |= (DEV_DMA_L | DEV_DMA_IOC |
853 ((len << DEV_DMA_NBYTES_SHIFT) & mask));
854
855 if (hs_ep->dir_in) {
856 desc->status |= ((hs_ep->mc << DEV_DMA_ISOC_PID_SHIFT) &
857 DEV_DMA_ISOC_PID_MASK) |
858 ((len % hs_ep->ep.maxpacket) ?
859 DEV_DMA_SHORT : 0) |
860 ((hs_ep->target_frame <<
861 DEV_DMA_ISOC_FRNUM_SHIFT) &
862 DEV_DMA_ISOC_FRNUM_MASK);
863 }
864
865 desc->status &= ~DEV_DMA_BUFF_STS_MASK;
866 desc->status |= (DEV_DMA_BUFF_STS_HREADY << DEV_DMA_BUFF_STS_SHIFT);
867
868 /* Update index of last configured entry in the chain */
869 hs_ep->next_desc++;
870
871 return 0;
872}
873
874/*
875 * dwc2_gadget_start_isoc_ddma - start isochronous transfer in DDMA
876 * @hs_ep: The isochronous endpoint.
877 *
878 * Prepare first descriptor chain for isochronous endpoints. Afterwards
879 * write DMA address to HW and enable the endpoint.
880 *
881 * Switch between descriptor chains via isoc_chain_num to give SW opportunity
882 * to prepare second descriptor chain while first one is being processed by HW.
883 */
884static void dwc2_gadget_start_isoc_ddma(struct dwc2_hsotg_ep *hs_ep)
885{
886 struct dwc2_hsotg *hsotg = hs_ep->parent;
887 struct dwc2_hsotg_req *hs_req, *treq;
888 int index = hs_ep->index;
889 int ret;
890 u32 dma_reg;
891 u32 depctl;
892 u32 ctrl;
893
894 if (list_empty(&hs_ep->queue)) {
895 dev_dbg(hsotg->dev, "%s: No requests in queue\n", __func__);
896 return;
897 }
898
899 list_for_each_entry_safe(hs_req, treq, &hs_ep->queue, queue) {
900 ret = dwc2_gadget_fill_isoc_desc(hs_ep, hs_req->req.dma,
901 hs_req->req.length);
902 if (ret) {
903 dev_dbg(hsotg->dev, "%s: desc chain full\n", __func__);
904 break;
905 }
906 }
907
908 depctl = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index);
909 dma_reg = hs_ep->dir_in ? DIEPDMA(index) : DOEPDMA(index);
910
911 /* write descriptor chain address to control register */
912 dwc2_writel(hs_ep->desc_list_dma, hsotg->regs + dma_reg);
913
914 ctrl = dwc2_readl(hsotg->regs + depctl);
915 ctrl |= DXEPCTL_EPENA | DXEPCTL_CNAK;
916 dwc2_writel(ctrl, hsotg->regs + depctl);
917
918 /* Switch ISOC descriptor chain number being processed by SW*/
919 hs_ep->isoc_chain_num = (hs_ep->isoc_chain_num ^ 1) & 0x1;
920 hs_ep->next_desc = 0;
921}
922
5b7d70c6 923/**
1f91b4cc 924 * dwc2_hsotg_start_req - start a USB request from an endpoint's queue
5b7d70c6
BD		 925 * @hsotg: The controller state.
926 * @hs_ep: The endpoint to process a request for
927 * @hs_req: The request to start.
928 * @continuing: True if we are doing more for the current request.
929 *
930 * Start the given request running by setting the endpoint registers
931 * appropriately, and writing any data to the FIFOs.
932 */
1f91b4cc 933static void dwc2_hsotg_start_req(struct dwc2_hsotg *hsotg,
9da51974 934 struct dwc2_hsotg_ep *hs_ep,
1f91b4cc 935 struct dwc2_hsotg_req *hs_req,
5b7d70c6
BD		 936 bool continuing)
937{
938 struct usb_request *ureq = &hs_req->req;
939 int index = hs_ep->index;
940 int dir_in = hs_ep->dir_in;
941 u32 epctrl_reg;
942 u32 epsize_reg;
943 u32 epsize;
944 u32 ctrl;
9da51974
JY		 945 unsigned int length;
946 unsigned int packets;
947 unsigned int maxreq;
aa3e8bc8 948 unsigned int dma_reg;
5b7d70c6
BD		 949
950 if (index != 0) {
951 if (hs_ep->req && !continuing) {
952 dev_err(hsotg->dev, "%s: active request\n", __func__);
953 WARN_ON(1);
954 return;
955 } else if (hs_ep->req != hs_req && continuing) {
956 dev_err(hsotg->dev,
957 "%s: continue different req\n", __func__);
958 WARN_ON(1);
959 return;
960 }
961 }
962
aa3e8bc8 963 dma_reg = dir_in ? DIEPDMA(index) : DOEPDMA(index);
94cb8fd6
LM		 964 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
965 epsize_reg = dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index);
5b7d70c6
BD		 966
967 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n",
95c8bc36 968 __func__, dwc2_readl(hsotg->regs + epctrl_reg), index,
5b7d70c6
BD		 969 hs_ep->dir_in ? "in" : "out");
970
9c39ddc6 971 /* If endpoint is stalled, we will restart request later */
95c8bc36 972 ctrl = dwc2_readl(hsotg->regs + epctrl_reg);
9c39ddc6 973
b2d4c54e 974 if (index && ctrl & DXEPCTL_STALL) {
9c39ddc6
AT		 975 dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index);
976 return;
977 }
978
5b7d70c6 979 length = ureq->length - ureq->actual;
71225bee
LM		 980 dev_dbg(hsotg->dev, "ureq->length:%d ureq->actual:%d\n",
981 ureq->length, ureq->actual);
5b7d70c6 982
cf77b5fb
VA		 983 if (!using_desc_dma(hsotg))
984 maxreq = get_ep_limit(hs_ep);
985 else
986 maxreq = dwc2_gadget_get_chain_limit(hs_ep);
987
5b7d70c6
BD		 988 if (length > maxreq) {
989 int round = maxreq % hs_ep->ep.maxpacket;
990
991 dev_dbg(hsotg->dev, "%s: length %d, max-req %d, r %d\n",
992 __func__, length, maxreq, round);
993
994 /* round down to multiple of packets */
995 if (round)
996 maxreq -= round;
997
998 length = maxreq;
999 }
1000
1001 if (length)
1002 packets = DIV_ROUND_UP(length, hs_ep->ep.maxpacket);
1003 else
1004 packets = 1; /* send one packet if length is zero. */
1005
4fca54aa
RB		 1006 if (hs_ep->isochronous && length > (hs_ep->mc * hs_ep->ep.maxpacket)) {
1007 dev_err(hsotg->dev, "req length > maxpacket*mc\n");
1008 return;
1009 }
1010
5b7d70c6 1011 if (dir_in && index != 0)
4fca54aa 1012 if (hs_ep->isochronous)
47a1685f 1013 epsize = DXEPTSIZ_MC(packets);
4fca54aa 1014 else
47a1685f 1015 epsize = DXEPTSIZ_MC(1);
5b7d70c6
BD		 1016 else
1017 epsize = 0;
1018
f71b5e25
MYK		 1019 /*
1020 * zero length packet should be programmed on its own and should not
1021 * be counted in DIEPTSIZ.PktCnt with other packets.
1022 */
1023 if (dir_in && ureq->zero && !continuing) {
1024 /* Test if zlp is actually required. */
1025 if ((ureq->length >= hs_ep->ep.maxpacket) &&
9da51974 1026 !(ureq->length % hs_ep->ep.maxpacket))
8a20fa45 1027 hs_ep->send_zlp = 1;
5b7d70c6
BD		 1028 }
1029
47a1685f
DN		 1030 epsize |= DXEPTSIZ_PKTCNT(packets);
1031 epsize |= DXEPTSIZ_XFERSIZE(length);
5b7d70c6
BD		 1032
1033 dev_dbg(hsotg->dev, "%s: %d@%d/%d, 0x%08x => 0x%08x\n",
1034 __func__, packets, length, ureq->length, epsize, epsize_reg);
1035
1036 /* store the request as the current one we're doing */
1037 hs_ep->req = hs_req;
1038
aa3e8bc8
VA		 1039 if (using_desc_dma(hsotg)) {
1040 u32 offset = 0;
1041 u32 mps = hs_ep->ep.maxpacket;
1042
1043 /* Adjust length: EP0 - MPS, other OUT EPs - multiple of MPS */
1044 if (!dir_in) {
1045 if (!index)
1046 length = mps;
1047 else if (length % mps)
1048 length += (mps - (length % mps));
1049 }
5b7d70c6 1050
8b9bc460 1051 /*
aa3e8bc8
VA		 1052 * If more data to send, adjust DMA for EP0 out data stage.
1053 * ureq->dma stays unchanged, hence increment it by already
1054 * passed passed data count before starting new transaction.
8b9bc460 1055 */
aa3e8bc8
VA		 1056 if (!index && hsotg->ep0_state == DWC2_EP0_DATA_OUT &&
1057 continuing)
1058 offset = ureq->actual;
1059
1060 /* Fill DDMA chain entries */
1061 dwc2_gadget_config_nonisoc_xfer_ddma(hs_ep, ureq->dma + offset,
1062 length);
1063
1064 /* write descriptor chain address to control register */
1065 dwc2_writel(hs_ep->desc_list_dma, hsotg->regs + dma_reg);
5b7d70c6 1066
aa3e8bc8
VA		 1067 dev_dbg(hsotg->dev, "%s: %08x pad => 0x%08x\n",
1068 __func__, (u32)hs_ep->desc_list_dma, dma_reg);
1069 } else {
1070 /* write size / packets */
1071 dwc2_writel(epsize, hsotg->regs + epsize_reg);
1072
729e6574 1073 if (using_dma(hsotg) && !continuing && (length != 0)) {
aa3e8bc8
VA		 1074 /*
1075 * write DMA address to control register, buffer
1076 * already synced by dwc2_hsotg_ep_queue().
1077 */
5b7d70c6 1078
aa3e8bc8
VA		 1079 dwc2_writel(ureq->dma, hsotg->regs + dma_reg);
1080
1081 dev_dbg(hsotg->dev, "%s: %pad => 0x%08x\n",
1082 __func__, &ureq->dma, dma_reg);
1083 }
5b7d70c6
BD		 1084 }
1085
837e9f00
VM		 1086 if (hs_ep->isochronous && hs_ep->interval == 1) {
1087 hs_ep->target_frame = dwc2_hsotg_read_frameno(hsotg);
1088 dwc2_gadget_incr_frame_num(hs_ep);
1089
1090 if (hs_ep->target_frame & 0x1)
1091 ctrl |= DXEPCTL_SETODDFR;
1092 else
1093 ctrl |= DXEPCTL_SETEVENFR;
1094 }
1095
47a1685f 1096 ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */
71225bee 1097
fe0b94ab 1098 dev_dbg(hsotg->dev, "ep0 state:%d\n", hsotg->ep0_state);
71225bee
LM		 1099
1100 /* For Setup request do not clear NAK */
fe0b94ab 1101 if (!(index == 0 && hsotg->ep0_state == DWC2_EP0_SETUP))
47a1685f 1102 ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */
71225bee 1103
5b7d70c6 1104 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
95c8bc36 1105 dwc2_writel(ctrl, hsotg->regs + epctrl_reg);
5b7d70c6 1106
8b9bc460
LM		 1107 /*
1108 * set these, it seems that DMA support increments past the end
5b7d70c6 1109 * of the packet buffer so we need to calculate the length from
8b9bc460
LM		 1110 * this information.
1111 */
5b7d70c6
BD		 1112 hs_ep->size_loaded = length;
1113 hs_ep->last_load = ureq->actual;
1114
1115 if (dir_in && !using_dma(hsotg)) {
1116 /* set these anyway, we may need them for non-periodic in */
1117 hs_ep->fifo_load = 0;
1118
1f91b4cc 1119 dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req);
5b7d70c6
BD		 1120 }
1121
8b9bc460
LM		 1122 /*
1123 * Note, trying to clear the NAK here causes problems with transmit
1124 * on the S3C6400 ending up with the TXFIFO becoming full.
1125 */
5b7d70c6
BD		 1126
1127 /* check ep is enabled */
95c8bc36 1128 if (!(dwc2_readl(hsotg->regs + epctrl_reg) & DXEPCTL_EPENA))
1a0ed863 1129 dev_dbg(hsotg->dev,
9da51974 1130 "ep%d: failed to become enabled (DXEPCTL=0x%08x)?\n",
95c8bc36 1131 index, dwc2_readl(hsotg->regs + epctrl_reg));
5b7d70c6 1132
47a1685f 1133 dev_dbg(hsotg->dev, "%s: DXEPCTL=0x%08x\n",
95c8bc36 1134 __func__, dwc2_readl(hsotg->regs + epctrl_reg));
afcf4169
RB		 1135
1136 /* enable ep interrupts */
1f91b4cc 1137 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 1);
5b7d70c6
BD		 1138}
1139
1140/**
1f91b4cc 1141 * dwc2_hsotg_map_dma - map the DMA memory being used for the request
5b7d70c6
BD		 1142 * @hsotg: The device state.
1143 * @hs_ep: The endpoint the request is on.
1144 * @req: The request being processed.
1145 *
1146 * We've been asked to queue a request, so ensure that the memory buffer
1147 * is correctly setup for DMA. If we've been passed an extant DMA address
1148 * then ensure the buffer has been synced to memory. If our buffer has no
1149 * DMA memory, then we map the memory and mark our request to allow us to
1150 * cleanup on completion.
8b9bc460 1151 */
1f91b4cc 1152static int dwc2_hsotg_map_dma(struct dwc2_hsotg *hsotg,
9da51974 1153 struct dwc2_hsotg_ep *hs_ep,
5b7d70c6
BD		 1154 struct usb_request *req)
1155{
e58ebcd1 1156 int ret;
5b7d70c6 1157
e58ebcd1
FB		 1158 ret = usb_gadget_map_request(&hsotg->gadget, req, hs_ep->dir_in);
1159 if (ret)
1160 goto dma_error;
5b7d70c6
BD		 1161
1162 return 0;
1163
1164dma_error:
1165 dev_err(hsotg->dev, "%s: failed to map buffer %p, %d bytes\n",
1166 __func__, req->buf, req->length);
1167
1168 return -EIO;
1169}
1170
1f91b4cc 1171static int dwc2_hsotg_handle_unaligned_buf_start(struct dwc2_hsotg *hsotg,
b98866c2
JY		 1172 struct dwc2_hsotg_ep *hs_ep,
1173 struct dwc2_hsotg_req *hs_req)
7d24c1b5
MYK		 1174{
1175 void *req_buf = hs_req->req.buf;
1176
1177 /* If dma is not being used or buffer is aligned */
1178 if (!using_dma(hsotg) || !((long)req_buf & 3))
1179 return 0;
1180
1181 WARN_ON(hs_req->saved_req_buf);
1182
1183 dev_dbg(hsotg->dev, "%s: %s: buf=%p length=%d\n", __func__,
9da51974 1184 hs_ep->ep.name, req_buf, hs_req->req.length);
7d24c1b5
MYK		 1185
1186 hs_req->req.buf = kmalloc(hs_req->req.length, GFP_ATOMIC);
1187 if (!hs_req->req.buf) {
1188 hs_req->req.buf = req_buf;
1189 dev_err(hsotg->dev,
1190 "%s: unable to allocate memory for bounce buffer\n",
1191 __func__);
1192 return -ENOMEM;
1193 }
1194
1195 /* Save actual buffer */
1196 hs_req->saved_req_buf = req_buf;
1197
1198 if (hs_ep->dir_in)
1199 memcpy(hs_req->req.buf, req_buf, hs_req->req.length);
1200 return 0;
1201}
1202
b98866c2
JY		 1203static void
1204dwc2_hsotg_handle_unaligned_buf_complete(struct dwc2_hsotg *hsotg,
1205 struct dwc2_hsotg_ep *hs_ep,
1206 struct dwc2_hsotg_req *hs_req)
7d24c1b5
MYK		 1207{
1208 /* If dma is not being used or buffer was aligned */
1209 if (!using_dma(hsotg) || !hs_req->saved_req_buf)
1210 return;
1211
1212 dev_dbg(hsotg->dev, "%s: %s: status=%d actual-length=%d\n", __func__,
1213 hs_ep->ep.name, hs_req->req.status, hs_req->req.actual);
1214
1215 /* Copy data from bounce buffer on successful out transfer */
1216 if (!hs_ep->dir_in && !hs_req->req.status)
1217 memcpy(hs_req->saved_req_buf, hs_req->req.buf,
9da51974 1218 hs_req->req.actual);
7d24c1b5
MYK		 1219
1220 /* Free bounce buffer */
1221 kfree(hs_req->req.buf);
1222
1223 hs_req->req.buf = hs_req->saved_req_buf;
1224 hs_req->saved_req_buf = NULL;
1225}
1226
381fc8f8
VM		 1227/**
1228 * dwc2_gadget_target_frame_elapsed - Checks target frame
1229 * @hs_ep: The driver endpoint to check
1230 *
1231 * Returns 1 if targeted frame elapsed. If returned 1 then we need to drop
1232 * corresponding transfer.
1233 */
1234static bool dwc2_gadget_target_frame_elapsed(struct dwc2_hsotg_ep *hs_ep)
1235{
1236 struct dwc2_hsotg *hsotg = hs_ep->parent;
1237 u32 target_frame = hs_ep->target_frame;
1238 u32 current_frame = dwc2_hsotg_read_frameno(hsotg);
1239 bool frame_overrun = hs_ep->frame_overrun;
1240
1241 if (!frame_overrun && current_frame >= target_frame)
1242 return true;
1243
1244 if (frame_overrun && current_frame >= target_frame &&
1245 ((current_frame - target_frame) < DSTS_SOFFN_LIMIT / 2))
1246 return true;
1247
1248 return false;
1249}
1250
e02f9aa6
VA		 1251/*
1252 * dwc2_gadget_set_ep0_desc_chain - Set EP's desc chain pointers
1253 * @hsotg: The driver state
1254 * @hs_ep: the ep descriptor chain is for
1255 *
1256 * Called to update EP0 structure's pointers depend on stage of
1257 * control transfer.
1258 */
1259static int dwc2_gadget_set_ep0_desc_chain(struct dwc2_hsotg *hsotg,
1260 struct dwc2_hsotg_ep *hs_ep)
1261{
1262 switch (hsotg->ep0_state) {
1263 case DWC2_EP0_SETUP:
1264 case DWC2_EP0_STATUS_OUT:
1265 hs_ep->desc_list = hsotg->setup_desc[0];
1266 hs_ep->desc_list_dma = hsotg->setup_desc_dma[0];
1267 break;
1268 case DWC2_EP0_DATA_IN:
1269 case DWC2_EP0_STATUS_IN:
1270 hs_ep->desc_list = hsotg->ctrl_in_desc;
1271 hs_ep->desc_list_dma = hsotg->ctrl_in_desc_dma;
1272 break;
1273 case DWC2_EP0_DATA_OUT:
1274 hs_ep->desc_list = hsotg->ctrl_out_desc;
1275 hs_ep->desc_list_dma = hsotg->ctrl_out_desc_dma;
1276 break;
1277 default:
1278 dev_err(hsotg->dev, "invalid EP 0 state in queue %d\n",
1279 hsotg->ep0_state);
1280 return -EINVAL;
1281 }
1282
1283 return 0;
1284}
1285
1f91b4cc 1286static int dwc2_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req,
9da51974 1287 gfp_t gfp_flags)
5b7d70c6 1288{
1f91b4cc
FB		 1289 struct dwc2_hsotg_req *hs_req = our_req(req);
1290 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
941fcce4 1291 struct dwc2_hsotg *hs = hs_ep->parent;
5b7d70c6 1292 bool first;
7d24c1b5 1293 int ret;
5b7d70c6
BD		 1294
1295 dev_dbg(hs->dev, "%s: req %p: %d@%p, noi=%d, zero=%d, snok=%d\n",
1296 ep->name, req, req->length, req->buf, req->no_interrupt,
1297 req->zero, req->short_not_ok);
1298
7ababa92 1299 /* Prevent new request submission when controller is suspended */
88b02f2c
GT		 1300 if (hs->lx_state != DWC2_L0) {
1301 dev_dbg(hs->dev, "%s: submit request only in active state\n",
9da51974 1302 __func__);
7ababa92
GH		 1303 return -EAGAIN;
1304 }
1305
5b7d70c6
BD		 1306 /* initialise status of the request */
1307 INIT_LIST_HEAD(&hs_req->queue);
1308 req->actual = 0;
1309 req->status = -EINPROGRESS;
1310
1f91b4cc 1311 ret = dwc2_hsotg_handle_unaligned_buf_start(hs, hs_ep, hs_req);
7d24c1b5
MYK		 1312 if (ret)
1313 return ret;
1314
5b7d70c6
BD		 1315 /* if we're using DMA, sync the buffers as necessary */
1316 if (using_dma(hs)) {
1f91b4cc 1317 ret = dwc2_hsotg_map_dma(hs, hs_ep, req);
5b7d70c6
BD		 1318 if (ret)
1319 return ret;
1320 }
e02f9aa6
VA		 1321 /* If using descriptor DMA configure EP0 descriptor chain pointers */
1322 if (using_desc_dma(hs) && !hs_ep->index) {
1323 ret = dwc2_gadget_set_ep0_desc_chain(hs, hs_ep);
1324 if (ret)
1325 return ret;
1326 }
5b7d70c6 1327
5b7d70c6
BD		 1328 first = list_empty(&hs_ep->queue);
1329 list_add_tail(&hs_req->queue, &hs_ep->queue);
1330
540ccba0
VA		 1331 /*
1332 * Handle DDMA isochronous transfers separately - just add new entry
1333 * to the half of descriptor chain that is not processed by HW.
1334 * Transfer will be started once SW gets either one of NAK or
1335 * OutTknEpDis interrupts.
1336 */
1337 if (using_desc_dma(hs) && hs_ep->isochronous &&
1338 hs_ep->target_frame != TARGET_FRAME_INITIAL) {
1339 ret = dwc2_gadget_fill_isoc_desc(hs_ep, hs_req->req.dma,
1340 hs_req->req.length);
1341 if (ret)
1342 dev_dbg(hs->dev, "%s: ISO desc chain full\n", __func__);
1343
1344 return 0;
1345 }
1346
837e9f00
VM		 1347 if (first) {
1348 if (!hs_ep->isochronous) {
1349 dwc2_hsotg_start_req(hs, hs_ep, hs_req, false);
1350 return 0;
1351 }
1352
1353 while (dwc2_gadget_target_frame_elapsed(hs_ep))
1354 dwc2_gadget_incr_frame_num(hs_ep);
5b7d70c6 1355
837e9f00
VM		 1356 if (hs_ep->target_frame != TARGET_FRAME_INITIAL)
1357 dwc2_hsotg_start_req(hs, hs_ep, hs_req, false);
1358 }
5b7d70c6
BD		 1359 return 0;
1360}
1361
1f91b4cc 1362static int dwc2_hsotg_ep_queue_lock(struct usb_ep *ep, struct usb_request *req,
9da51974 1363 gfp_t gfp_flags)
5ad1d316 1364{
1f91b4cc 1365 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
941fcce4 1366 struct dwc2_hsotg *hs = hs_ep->parent;
5ad1d316
LM		 1367 unsigned long flags = 0;
1368 int ret = 0;
1369
1370 spin_lock_irqsave(&hs->lock, flags);
1f91b4cc 1371 ret = dwc2_hsotg_ep_queue(ep, req, gfp_flags);
5ad1d316
LM		 1372 spin_unlock_irqrestore(&hs->lock, flags);
1373
1374 return ret;
1375}
1376
1f91b4cc 1377static void dwc2_hsotg_ep_free_request(struct usb_ep *ep,
9da51974 1378 struct usb_request *req)
5b7d70c6 1379{
1f91b4cc 1380 struct dwc2_hsotg_req *hs_req = our_req(req);
5b7d70c6
BD		 1381
1382 kfree(hs_req);
1383}
1384
1385/**
1f91b4cc 1386 * dwc2_hsotg_complete_oursetup - setup completion callback
5b7d70c6
BD		 1387 * @ep: The endpoint the request was on.
1388 * @req: The request completed.
1389 *
1390 * Called on completion of any requests the driver itself
1391 * submitted that need cleaning up.
1392 */
1f91b4cc 1393static void dwc2_hsotg_complete_oursetup(struct usb_ep *ep,
9da51974 1394 struct usb_request *req)
5b7d70c6 1395{
1f91b4cc 1396 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
941fcce4 1397 struct dwc2_hsotg *hsotg = hs_ep->parent;
5b7d70c6
BD		 1398
1399 dev_dbg(hsotg->dev, "%s: ep %p, req %p\n", __func__, ep, req);
1400
1f91b4cc 1401 dwc2_hsotg_ep_free_request(ep, req);
5b7d70c6
BD		 1402}
1403
1404/**
1405 * ep_from_windex - convert control wIndex value to endpoint
1406 * @hsotg: The driver state.
1407 * @windex: The control request wIndex field (in host order).
1408 *
1409 * Convert the given wIndex into a pointer to an driver endpoint
1410 * structure, or return NULL if it is not a valid endpoint.
8b9bc460 1411 */
1f91b4cc 1412static struct dwc2_hsotg_ep *ep_from_windex(struct dwc2_hsotg *hsotg,
9da51974 1413 u32 windex)
5b7d70c6 1414{
1f91b4cc 1415 struct dwc2_hsotg_ep *ep;
5b7d70c6
BD		 1416 int dir = (windex & USB_DIR_IN) ? 1 : 0;
1417 int idx = windex & 0x7F;
1418
1419 if (windex >= 0x100)
1420 return NULL;
1421
b3f489b2 1422 if (idx > hsotg->num_of_eps)
5b7d70c6
BD		 1423 return NULL;
1424
c6f5c050
MYK		 1425 ep = index_to_ep(hsotg, idx, dir);
1426
5b7d70c6
BD		 1427 if (idx && ep->dir_in != dir)
1428 return NULL;
1429
1430 return ep;
1431}
1432
9e14d0a5 1433/**
1f91b4cc 1434 * dwc2_hsotg_set_test_mode - Enable usb Test Modes
9e14d0a5
GH		 1435 * @hsotg: The driver state.
1436 * @testmode: requested usb test mode
1437 * Enable usb Test Mode requested by the Host.
1438 */
1f91b4cc 1439int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode)
9e14d0a5 1440{
95c8bc36 1441 int dctl = dwc2_readl(hsotg->regs + DCTL);
9e14d0a5
GH		 1442
1443 dctl &= ~DCTL_TSTCTL_MASK;
1444 switch (testmode) {
1445 case TEST_J:
1446 case TEST_K:
1447 case TEST_SE0_NAK:
1448 case TEST_PACKET:
1449 case TEST_FORCE_EN:
1450 dctl |= testmode << DCTL_TSTCTL_SHIFT;
1451 break;
1452 default:
1453 return -EINVAL;
1454 }
95c8bc36 1455 dwc2_writel(dctl, hsotg->regs + DCTL);
9e14d0a5
GH		 1456 return 0;
1457}
1458
5b7d70c6 1459/**
1f91b4cc 1460 * dwc2_hsotg_send_reply - send reply to control request
5b7d70c6
BD		 1461 * @hsotg: The device state
1462 * @ep: Endpoint 0
1463 * @buff: Buffer for request
1464 * @length: Length of reply.
1465 *
1466 * Create a request and queue it on the given endpoint. This is useful as
1467 * an internal method of sending replies to certain control requests, etc.
1468 */
1f91b4cc 1469static int dwc2_hsotg_send_reply(struct dwc2_hsotg *hsotg,
9da51974 1470 struct dwc2_hsotg_ep *ep,
5b7d70c6
BD		 1471 void *buff,
1472 int length)
1473{
1474 struct usb_request *req;
1475 int ret;
1476
1477 dev_dbg(hsotg->dev, "%s: buff %p, len %d\n", __func__, buff, length);
1478
1f91b4cc 1479 req = dwc2_hsotg_ep_alloc_request(&ep->ep, GFP_ATOMIC);
5b7d70c6
BD		 1480 hsotg->ep0_reply = req;
1481 if (!req) {
1482 dev_warn(hsotg->dev, "%s: cannot alloc req\n", __func__);
1483 return -ENOMEM;
1484 }
1485
1486 req->buf = hsotg->ep0_buff;
1487 req->length = length;
f71b5e25
MYK		 1488 /*
1489 * zero flag is for sending zlp in DATA IN stage. It has no impact on
1490 * STATUS stage.
1491 */
1492 req->zero = 0;
1f91b4cc 1493 req->complete = dwc2_hsotg_complete_oursetup;
5b7d70c6
BD		 1494
1495 if (length)
1496 memcpy(req->buf, buff, length);
5b7d70c6 1497
1f91b4cc 1498 ret = dwc2_hsotg_ep_queue(&ep->ep, req, GFP_ATOMIC);
5b7d70c6
BD		 1499 if (ret) {
1500 dev_warn(hsotg->dev, "%s: cannot queue req\n", __func__);
1501 return ret;
1502 }
1503
1504 return 0;
1505}
1506
1507/**
1f91b4cc 1508 * dwc2_hsotg_process_req_status - process request GET_STATUS
5b7d70c6
BD		 1509 * @hsotg: The device state
1510 * @ctrl: USB control request
1511 */
1f91b4cc 1512static int dwc2_hsotg_process_req_status(struct dwc2_hsotg *hsotg,
9da51974 1513 struct usb_ctrlrequest *ctrl)
5b7d70c6 1514{
1f91b4cc
FB		 1515 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1516 struct dwc2_hsotg_ep *ep;
5b7d70c6
BD		 1517 __le16 reply;
1518 int ret;
1519
1520 dev_dbg(hsotg->dev, "%s: USB_REQ_GET_STATUS\n", __func__);
1521
1522 if (!ep0->dir_in) {
1523 dev_warn(hsotg->dev, "%s: direction out?\n", __func__);
1524 return -EINVAL;
1525 }
1526
1527 switch (ctrl->bRequestType & USB_RECIP_MASK) {
1528 case USB_RECIP_DEVICE:
38beaec6
JY		 1529 /*
1530 * bit 0 => self powered
1531 * bit 1 => remote wakeup
1532 */
1533 reply = cpu_to_le16(0);
5b7d70c6
BD		 1534 break;
1535
1536 case USB_RECIP_INTERFACE:
1537 /* currently, the data result should be zero */
1538 reply = cpu_to_le16(0);
1539 break;
1540
1541 case USB_RECIP_ENDPOINT:
1542 ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex));
1543 if (!ep)
1544 return -ENOENT;
1545
1546 reply = cpu_to_le16(ep->halted ? 1 : 0);
1547 break;
1548
1549 default:
1550 return 0;
1551 }
1552
1553 if (le16_to_cpu(ctrl->wLength) != 2)
1554 return -EINVAL;
1555
1f91b4cc 1556 ret = dwc2_hsotg_send_reply(hsotg, ep0, &reply, 2);
5b7d70c6
BD		 1557 if (ret) {
1558 dev_err(hsotg->dev, "%s: failed to send reply\n", __func__);
1559 return ret;
1560 }
1561
1562 return 1;
1563}
1564
51da43b5 1565static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now);
5b7d70c6 1566
9c39ddc6
AT		 1567/**
1568 * get_ep_head - return the first request on the endpoint
1569 * @hs_ep: The controller endpoint to get
1570 *
1571 * Get the first request on the endpoint.
1572 */
1f91b4cc 1573static struct dwc2_hsotg_req *get_ep_head(struct dwc2_hsotg_ep *hs_ep)
9c39ddc6 1574{
ffc4b406
MY		 1575 return list_first_entry_or_null(&hs_ep->queue, struct dwc2_hsotg_req,
1576 queue);
9c39ddc6
AT		 1577}
1578
41cc4cd2
VM		 1579/**
1580 * dwc2_gadget_start_next_request - Starts next request from ep queue
1581 * @hs_ep: Endpoint structure
1582 *
1583 * If queue is empty and EP is ISOC-OUT - unmasks OUTTKNEPDIS which is masked
1584 * in its handler. Hence we need to unmask it here to be able to do
1585 * resynchronization.
1586 */
1587static void dwc2_gadget_start_next_request(struct dwc2_hsotg_ep *hs_ep)
1588{
1589 u32 mask;
1590 struct dwc2_hsotg *hsotg = hs_ep->parent;
1591 int dir_in = hs_ep->dir_in;
1592 struct dwc2_hsotg_req *hs_req;
1593 u32 epmsk_reg = dir_in ? DIEPMSK : DOEPMSK;
1594
1595 if (!list_empty(&hs_ep->queue)) {
1596 hs_req = get_ep_head(hs_ep);
1597 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, false);
1598 return;
1599 }
1600 if (!hs_ep->isochronous)
1601 return;
1602
1603 if (dir_in) {
1604 dev_dbg(hsotg->dev, "%s: No more ISOC-IN requests\n",
1605 __func__);
1606 } else {
1607 dev_dbg(hsotg->dev, "%s: No more ISOC-OUT requests\n",
1608 __func__);
1609 mask = dwc2_readl(hsotg->regs + epmsk_reg);
1610 mask |= DOEPMSK_OUTTKNEPDISMSK;
1611 dwc2_writel(mask, hsotg->regs + epmsk_reg);
1612 }
1613}
1614
5b7d70c6 1615/**
1f91b4cc 1616 * dwc2_hsotg_process_req_feature - process request {SET,CLEAR}_FEATURE
5b7d70c6
BD		 1617 * @hsotg: The device state
1618 * @ctrl: USB control request
1619 */
1f91b4cc 1620static int dwc2_hsotg_process_req_feature(struct dwc2_hsotg *hsotg,
9da51974 1621 struct usb_ctrlrequest *ctrl)
5b7d70c6 1622{
1f91b4cc
FB		 1623 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1624 struct dwc2_hsotg_req *hs_req;
5b7d70c6 1625 bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE);
1f91b4cc 1626 struct dwc2_hsotg_ep *ep;
26ab3d0c 1627 int ret;
bd9ef7bf 1628 bool halted;
9e14d0a5
GH		 1629 u32 recip;
1630 u32 wValue;
1631 u32 wIndex;
5b7d70c6
BD		 1632
1633 dev_dbg(hsotg->dev, "%s: %s_FEATURE\n",
1634 __func__, set ? "SET" : "CLEAR");
1635
9e14d0a5
GH		 1636 wValue = le16_to_cpu(ctrl->wValue);
1637 wIndex = le16_to_cpu(ctrl->wIndex);
1638 recip = ctrl->bRequestType & USB_RECIP_MASK;
1639
1640 switch (recip) {
1641 case USB_RECIP_DEVICE:
1642 switch (wValue) {
fa389a6d
VM		 1643 case USB_DEVICE_REMOTE_WAKEUP:
1644 hsotg->remote_wakeup_allowed = 1;
1645 break;
1646
9e14d0a5
GH		 1647 case USB_DEVICE_TEST_MODE:
1648 if ((wIndex & 0xff) != 0)
1649 return -EINVAL;
1650 if (!set)
1651 return -EINVAL;
1652
1653 hsotg->test_mode = wIndex >> 8;
1f91b4cc 1654 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
9e14d0a5
GH		 1655 if (ret) {
1656 dev_err(hsotg->dev,
1657 "%s: failed to send reply\n", __func__);
1658 return ret;
1659 }
1660 break;
1661 default:
1662 return -ENOENT;
1663 }
1664 break;
1665
1666 case USB_RECIP_ENDPOINT:
1667 ep = ep_from_windex(hsotg, wIndex);
5b7d70c6
BD		 1668 if (!ep) {
1669 dev_dbg(hsotg->dev, "%s: no endpoint for 0x%04x\n",
9e14d0a5 1670 __func__, wIndex);
5b7d70c6
BD		 1671 return -ENOENT;
1672 }
1673
9e14d0a5 1674 switch (wValue) {
5b7d70c6 1675 case USB_ENDPOINT_HALT:
bd9ef7bf
RB		 1676 halted = ep->halted;
1677
51da43b5 1678 dwc2_hsotg_ep_sethalt(&ep->ep, set, true);
26ab3d0c 1679
1f91b4cc 1680 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
26ab3d0c
AT		 1681 if (ret) {
1682 dev_err(hsotg->dev,
1683 "%s: failed to send reply\n", __func__);
1684 return ret;
1685 }
9c39ddc6 1686
bd9ef7bf
RB		 1687 /*
1688 * we have to complete all requests for ep if it was
1689 * halted, and the halt was cleared by CLEAR_FEATURE
1690 */
1691
1692 if (!set && halted) {
9c39ddc6
AT		 1693 /*
1694 * If we have request in progress,
1695 * then complete it
1696 */
1697 if (ep->req) {
1698 hs_req = ep->req;
1699 ep->req = NULL;
1700 list_del_init(&hs_req->queue);
c00dd4a6
GH		 1701 if (hs_req->req.complete) {
1702 spin_unlock(&hsotg->lock);
1703 usb_gadget_giveback_request(
1704 &ep->ep, &hs_req->req);
1705 spin_lock(&hsotg->lock);
1706 }
9c39ddc6
AT		 1707 }
1708
1709 /* If we have pending request, then start it */
34c0887f 1710 if (!ep->req)
41cc4cd2 1711 dwc2_gadget_start_next_request(ep);
9c39ddc6
AT		 1712 }
1713
5b7d70c6
BD		 1714 break;
1715
1716 default:
1717 return -ENOENT;
1718 }
9e14d0a5
GH		 1719 break;
1720 default:
1721 return -ENOENT;
1722 }
5b7d70c6
BD		 1723 return 1;
1724}
1725
1f91b4cc 1726static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg);
ab93e014 1727
c9f721b2 1728/**
1f91b4cc 1729 * dwc2_hsotg_stall_ep0 - stall ep0
c9f721b2
RB		 1730 * @hsotg: The device state
1731 *
1732 * Set stall for ep0 as response for setup request.
1733 */
1f91b4cc 1734static void dwc2_hsotg_stall_ep0(struct dwc2_hsotg *hsotg)
e9ebe7c3 1735{
1f91b4cc 1736 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
c9f721b2
RB		 1737 u32 reg;
1738 u32 ctrl;
1739
1740 dev_dbg(hsotg->dev, "ep0 stall (dir=%d)\n", ep0->dir_in);
1741 reg = (ep0->dir_in) ? DIEPCTL0 : DOEPCTL0;
1742
1743 /*
1744 * DxEPCTL_Stall will be cleared by EP once it has
1745 * taken effect, so no need to clear later.
1746 */
1747
95c8bc36 1748 ctrl = dwc2_readl(hsotg->regs + reg);
47a1685f
DN		 1749 ctrl |= DXEPCTL_STALL;
1750 ctrl |= DXEPCTL_CNAK;
95c8bc36 1751 dwc2_writel(ctrl, hsotg->regs + reg);
c9f721b2
RB		 1752
1753 dev_dbg(hsotg->dev,
47a1685f 1754 "written DXEPCTL=0x%08x to %08x (DXEPCTL=0x%08x)\n",
95c8bc36 1755 ctrl, reg, dwc2_readl(hsotg->regs + reg));
c9f721b2
RB		 1756
1757 /*
1758 * complete won't be called, so we enqueue
1759 * setup request here
1760 */
1f91b4cc 1761 dwc2_hsotg_enqueue_setup(hsotg);
c9f721b2
RB		 1762}
1763
5b7d70c6 1764/**
1f91b4cc 1765 * dwc2_hsotg_process_control - process a control request
5b7d70c6
BD		 1766 * @hsotg: The device state
1767 * @ctrl: The control request received
1768 *
1769 * The controller has received the SETUP phase of a control request, and
1770 * needs to work out what to do next (and whether to pass it on to the
1771 * gadget driver).
1772 */
1f91b4cc 1773static void dwc2_hsotg_process_control(struct dwc2_hsotg *hsotg,
9da51974 1774 struct usb_ctrlrequest *ctrl)
5b7d70c6 1775{
1f91b4cc 1776 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
5b7d70c6
BD		 1777 int ret = 0;
1778 u32 dcfg;
1779
e525e743
MYK		 1780 dev_dbg(hsotg->dev,
1781 "ctrl Type=%02x, Req=%02x, V=%04x, I=%04x, L=%04x\n",
1782 ctrl->bRequestType, ctrl->bRequest, ctrl->wValue,
1783 ctrl->wIndex, ctrl->wLength);
5b7d70c6 1784
fe0b94ab
MYK		 1785 if (ctrl->wLength == 0) {
1786 ep0->dir_in = 1;
1787 hsotg->ep0_state = DWC2_EP0_STATUS_IN;
1788 } else if (ctrl->bRequestType & USB_DIR_IN) {
5b7d70c6 1789 ep0->dir_in = 1;
fe0b94ab
MYK		 1790 hsotg->ep0_state = DWC2_EP0_DATA_IN;
1791 } else {
1792 ep0->dir_in = 0;
1793 hsotg->ep0_state = DWC2_EP0_DATA_OUT;
1794 }
5b7d70c6
BD		 1795
1796 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
1797 switch (ctrl->bRequest) {
1798 case USB_REQ_SET_ADDRESS:
6d713c15 1799 hsotg->connected = 1;
95c8bc36 1800 dcfg = dwc2_readl(hsotg->regs + DCFG);
47a1685f 1801 dcfg &= ~DCFG_DEVADDR_MASK;
d5dbd3f7
PZ		 1802 dcfg |= (le16_to_cpu(ctrl->wValue) <<
1803 DCFG_DEVADDR_SHIFT) & DCFG_DEVADDR_MASK;
95c8bc36 1804 dwc2_writel(dcfg, hsotg->regs + DCFG);
5b7d70c6
BD		 1805
1806 dev_info(hsotg->dev, "new address %d\n", ctrl->wValue);
1807
1f91b4cc 1808 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
5b7d70c6
BD		 1809 return;
1810
1811 case USB_REQ_GET_STATUS:
1f91b4cc 1812 ret = dwc2_hsotg_process_req_status(hsotg, ctrl);
5b7d70c6
BD		 1813 break;
1814
1815 case USB_REQ_CLEAR_FEATURE:
1816 case USB_REQ_SET_FEATURE:
1f91b4cc 1817 ret = dwc2_hsotg_process_req_feature(hsotg, ctrl);
5b7d70c6
BD		 1818 break;
1819 }
1820 }
1821
1822 /* as a fallback, try delivering it to the driver to deal with */
1823
1824 if (ret == 0 && hsotg->driver) {
93f599f2 1825 spin_unlock(&hsotg->lock);
5b7d70c6 1826 ret = hsotg->driver->setup(&hsotg->gadget, ctrl);
93f599f2 1827 spin_lock(&hsotg->lock);
5b7d70c6
BD		 1828 if (ret < 0)
1829 dev_dbg(hsotg->dev, "driver->setup() ret %d\n", ret);
1830 }
1831
8b9bc460
LM		 1832 /*
1833 * the request is either unhandlable, or is not formatted correctly
5b7d70c6
BD		 1834 * so respond with a STALL for the status stage to indicate failure.
1835 */
1836
c9f721b2 1837 if (ret < 0)
1f91b4cc 1838 dwc2_hsotg_stall_ep0(hsotg);
5b7d70c6
BD		 1839}
1840
5b7d70c6 1841/**
1f91b4cc 1842 * dwc2_hsotg_complete_setup - completion of a setup transfer
5b7d70c6
BD		 1843 * @ep: The endpoint the request was on.
1844 * @req: The request completed.
1845 *
1846 * Called on completion of any requests the driver itself submitted for
1847 * EP0 setup packets
1848 */
1f91b4cc 1849static void dwc2_hsotg_complete_setup(struct usb_ep *ep,
9da51974 1850 struct usb_request *req)
5b7d70c6 1851{
1f91b4cc 1852 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
941fcce4 1853 struct dwc2_hsotg *hsotg = hs_ep->parent;
5b7d70c6
BD		 1854
1855 if (req->status < 0) {
1856 dev_dbg(hsotg->dev, "%s: failed %d\n", __func__, req->status);
1857 return;
1858 }
1859
93f599f2 1860 spin_lock(&hsotg->lock);
5b7d70c6 1861 if (req->actual == 0)
1f91b4cc 1862 dwc2_hsotg_enqueue_setup(hsotg);
5b7d70c6 1863 else
1f91b4cc 1864 dwc2_hsotg_process_control(hsotg, req->buf);
93f599f2 1865 spin_unlock(&hsotg->lock);
5b7d70c6
BD		 1866}
1867
1868/**
1f91b4cc 1869 * dwc2_hsotg_enqueue_setup - start a request for EP0 packets
5b7d70c6
BD		 1870 * @hsotg: The device state.
1871 *
1872 * Enqueue a request on EP0 if necessary to received any SETUP packets
1873 * received from the host.
1874 */
1f91b4cc 1875static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg)
5b7d70c6
BD		 1876{
1877 struct usb_request *req = hsotg->ctrl_req;
1f91b4cc 1878 struct dwc2_hsotg_req *hs_req = our_req(req);
5b7d70c6
BD		 1879 int ret;
1880
1881 dev_dbg(hsotg->dev, "%s: queueing setup request\n", __func__);
1882
1883 req->zero = 0;
1884 req->length = 8;
1885 req->buf = hsotg->ctrl_buff;
1f91b4cc 1886 req->complete = dwc2_hsotg_complete_setup;
5b7d70c6
BD		 1887
1888 if (!list_empty(&hs_req->queue)) {
1889 dev_dbg(hsotg->dev, "%s already queued???\n", __func__);
1890 return;
1891 }
1892
c6f5c050 1893 hsotg->eps_out[0]->dir_in = 0;
8a20fa45 1894 hsotg->eps_out[0]->send_zlp = 0;
fe0b94ab 1895 hsotg->ep0_state = DWC2_EP0_SETUP;
5b7d70c6 1896
1f91b4cc 1897 ret = dwc2_hsotg_ep_queue(&hsotg->eps_out[0]->ep, req, GFP_ATOMIC);
5b7d70c6
BD		 1898 if (ret < 0) {
1899 dev_err(hsotg->dev, "%s: failed queue (%d)\n", __func__, ret);
8b9bc460
LM		 1900 /*
1901 * Don't think there's much we can do other than watch the
1902 * driver fail.
1903 */
5b7d70c6
BD		 1904 }
1905}
1906
1f91b4cc 1907static void dwc2_hsotg_program_zlp(struct dwc2_hsotg *hsotg,
9da51974 1908 struct dwc2_hsotg_ep *hs_ep)
fe0b94ab
MYK		 1909{
1910 u32 ctrl;
1911 u8 index = hs_ep->index;
1912 u32 epctl_reg = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index);
1913 u32 epsiz_reg = hs_ep->dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index);
1914
ccb34a91
MYK		 1915 if (hs_ep->dir_in)
1916 dev_dbg(hsotg->dev, "Sending zero-length packet on ep%d\n",
e02f9aa6 1917 index);
ccb34a91
MYK		 1918 else
1919 dev_dbg(hsotg->dev, "Receiving zero-length packet on ep%d\n",
e02f9aa6
VA		 1920 index);
1921 if (using_desc_dma(hsotg)) {
1922 /* Not specific buffer needed for ep0 ZLP */
1923 dma_addr_t dma = hs_ep->desc_list_dma;
fe0b94ab 1924
201ec568
MH		 1925 if (!index)
1926 dwc2_gadget_set_ep0_desc_chain(hsotg, hs_ep);
1927
e02f9aa6
VA		 1928 dwc2_gadget_config_nonisoc_xfer_ddma(hs_ep, dma, 0);
1929 } else {
1930 dwc2_writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
1931 DXEPTSIZ_XFERSIZE(0), hsotg->regs +
1932 epsiz_reg);
1933 }
fe0b94ab 1934
95c8bc36 1935 ctrl = dwc2_readl(hsotg->regs + epctl_reg);
fe0b94ab
MYK		 1936 ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */
1937 ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */
1938 ctrl |= DXEPCTL_USBACTEP;
95c8bc36 1939 dwc2_writel(ctrl, hsotg->regs + epctl_reg);
fe0b94ab
MYK		 1940}
1941
5b7d70c6 1942/**
1f91b4cc 1943 * dwc2_hsotg_complete_request - complete a request given to us
5b7d70c6
BD		 1944 * @hsotg: The device state.
1945 * @hs_ep: The endpoint the request was on.
1946 * @hs_req: The request to complete.
1947 * @result: The result code (0 => Ok, otherwise errno)
1948 *
1949 * The given request has finished, so call the necessary completion
1950 * if it has one and then look to see if we can start a new request
1951 * on the endpoint.
1952 *
1953 * Note, expects the ep to already be locked as appropriate.
8b9bc460 1954 */
1f91b4cc 1955static void dwc2_hsotg_complete_request(struct dwc2_hsotg *hsotg,
9da51974 1956 struct dwc2_hsotg_ep *hs_ep,
1f91b4cc 1957 struct dwc2_hsotg_req *hs_req,
5b7d70c6
BD		 1958 int result)
1959{
5b7d70c6
BD		 1960 if (!hs_req) {
1961 dev_dbg(hsotg->dev, "%s: nothing to complete?\n", __func__);
1962 return;
1963 }
1964
1965 dev_dbg(hsotg->dev, "complete: ep %p %s, req %p, %d => %p\n",
1966 hs_ep, hs_ep->ep.name, hs_req, result, hs_req->req.complete);
1967
8b9bc460
LM		 1968 /*
1969 * only replace the status if we've not already set an error
1970 * from a previous transaction
1971 */
5b7d70c6
BD		 1972
1973 if (hs_req->req.status == -EINPROGRESS)
1974 hs_req->req.status = result;
1975
44583fec
YL		 1976 if (using_dma(hsotg))
1977 dwc2_hsotg_unmap_dma(hsotg, hs_ep, hs_req);
1978
1f91b4cc 1979 dwc2_hsotg_handle_unaligned_buf_complete(hsotg, hs_ep, hs_req);
7d24c1b5 1980
5b7d70c6
BD		 1981 hs_ep->req = NULL;
1982 list_del_init(&hs_req->queue);
1983
8b9bc460
LM		 1984 /*
1985 * call the complete request with the locks off, just in case the
1986 * request tries to queue more work for this endpoint.
1987 */
5b7d70c6
BD		 1988
1989 if (hs_req->req.complete) {
22258f49 1990 spin_unlock(&hsotg->lock);
304f7e5e 1991 usb_gadget_giveback_request(&hs_ep->ep, &hs_req->req);
22258f49 1992 spin_lock(&hsotg->lock);
5b7d70c6
BD		 1993 }
1994
540ccba0
VA		 1995 /* In DDMA don't need to proceed to starting of next ISOC request */
1996 if (using_desc_dma(hsotg) && hs_ep->isochronous)
1997 return;
1998
8b9bc460
LM		 1999 /*
2000 * Look to see if there is anything else to do. Note, the completion
5b7d70c6 2001 * of the previous request may have caused a new request to be started
8b9bc460
LM		 2002 * so be careful when doing this.
2003 */
5b7d70c6 2004
34c0887f 2005 if (!hs_ep->req && result >= 0)
41cc4cd2 2006 dwc2_gadget_start_next_request(hs_ep);
5b7d70c6
BD		 2007}
2008
540ccba0
VA		 2009/*
2010 * dwc2_gadget_complete_isoc_request_ddma - complete an isoc request in DDMA
2011 * @hs_ep: The endpoint the request was on.
2012 *
2013 * Get first request from the ep queue, determine descriptor on which complete
2014 * happened. SW based on isoc_chain_num discovers which half of the descriptor
2015 * chain is currently in use by HW, adjusts dma_address and calculates index
2016 * of completed descriptor based on the value of DEPDMA register. Update actual
2017 * length of request, giveback to gadget.
2018 */
2019static void dwc2_gadget_complete_isoc_request_ddma(struct dwc2_hsotg_ep *hs_ep)
2020{
2021 struct dwc2_hsotg *hsotg = hs_ep->parent;
2022 struct dwc2_hsotg_req *hs_req;
2023 struct usb_request *ureq;
2024 int index;
2025 dma_addr_t dma_addr;
2026 u32 dma_reg;
2027 u32 depdma;
2028 u32 desc_sts;
2029 u32 mask;
2030
2031 hs_req = get_ep_head(hs_ep);
2032 if (!hs_req) {
2033 dev_warn(hsotg->dev, "%s: ISOC EP queue empty\n", __func__);
2034 return;
2035 }
2036 ureq = &hs_req->req;
2037
2038 dma_addr = hs_ep->desc_list_dma;
2039
2040 /*
2041 * If lower half of descriptor chain is currently use by SW,
2042 * that means higher half is being processed by HW, so shift
2043 * DMA address to higher half of descriptor chain.
2044 */
2045 if (!hs_ep->isoc_chain_num)
2046 dma_addr += sizeof(struct dwc2_dma_desc) *
2047 (MAX_DMA_DESC_NUM_GENERIC / 2);
2048
2049 dma_reg = hs_ep->dir_in ? DIEPDMA(hs_ep->index) : DOEPDMA(hs_ep->index);
2050 depdma = dwc2_readl(hsotg->regs + dma_reg);
2051
2052 index = (depdma - dma_addr) / sizeof(struct dwc2_dma_desc) - 1;
2053 desc_sts = hs_ep->desc_list[index].status;
2054
2055 mask = hs_ep->dir_in ? DEV_DMA_ISOC_TX_NBYTES_MASK :
2056 DEV_DMA_ISOC_RX_NBYTES_MASK;
2057 ureq->actual = ureq->length -
2058 ((desc_sts & mask) >> DEV_DMA_ISOC_NBYTES_SHIFT);
2059
95d2b037
VA		 2060 /* Adjust actual length for ISOC Out if length is not align of 4 */
2061 if (!hs_ep->dir_in && ureq->length & 0x3)
2062 ureq->actual += 4 - (ureq->length & 0x3);
2063
540ccba0
VA		 2064 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2065}
2066
2067/*
2068 * dwc2_gadget_start_next_isoc_ddma - start next isoc request, if any.
2069 * @hs_ep: The isochronous endpoint to be re-enabled.
2070 *
2071 * If ep has been disabled due to last descriptor servicing (IN endpoint) or
2072 * BNA (OUT endpoint) check the status of other half of descriptor chain that
2073 * was under SW control till HW was busy and restart the endpoint if needed.
2074 */
2075static void dwc2_gadget_start_next_isoc_ddma(struct dwc2_hsotg_ep *hs_ep)
2076{
2077 struct dwc2_hsotg *hsotg = hs_ep->parent;
2078 u32 depctl;
2079 u32 dma_reg;
2080 u32 ctrl;
2081 u32 dma_addr = hs_ep->desc_list_dma;
2082 unsigned char index = hs_ep->index;
2083
2084 dma_reg = hs_ep->dir_in ? DIEPDMA(index) : DOEPDMA(index);
2085 depctl = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index);
2086
2087 ctrl = dwc2_readl(hsotg->regs + depctl);
2088
2089 /*
2090 * EP was disabled if HW has processed last descriptor or BNA was set.
2091 * So restart ep if SW has prepared new descriptor chain in ep_queue
2092 * routine while HW was busy.
2093 */
2094 if (!(ctrl & DXEPCTL_EPENA)) {
2095 if (!hs_ep->next_desc) {
2096 dev_dbg(hsotg->dev, "%s: No more ISOC requests\n",
2097 __func__);
2098 return;
2099 }
2100
2101 dma_addr += sizeof(struct dwc2_dma_desc) *
2102 (MAX_DMA_DESC_NUM_GENERIC / 2) *
2103 hs_ep->isoc_chain_num;
2104 dwc2_writel(dma_addr, hsotg->regs + dma_reg);
2105
2106 ctrl |= DXEPCTL_EPENA | DXEPCTL_CNAK;
2107 dwc2_writel(ctrl, hsotg->regs + depctl);
2108
2109 /* Switch ISOC descriptor chain number being processed by SW*/
2110 hs_ep->isoc_chain_num = (hs_ep->isoc_chain_num ^ 1) & 0x1;
2111 hs_ep->next_desc = 0;
2112
2113 dev_dbg(hsotg->dev, "%s: Restarted isochronous endpoint\n",
2114 __func__);
2115 }
2116}
2117
5b7d70c6 2118/**
1f91b4cc 2119 * dwc2_hsotg_rx_data - receive data from the FIFO for an endpoint
5b7d70c6
BD		 2120 * @hsotg: The device state.
2121 * @ep_idx: The endpoint index for the data
2122 * @size: The size of data in the fifo, in bytes
2123 *
2124 * The FIFO status shows there is data to read from the FIFO for a given
2125 * endpoint, so sort out whether we need to read the data into a request
2126 * that has been made for that endpoint.
2127 */
1f91b4cc 2128static void dwc2_hsotg_rx_data(struct dwc2_hsotg *hsotg, int ep_idx, int size)
5b7d70c6 2129{
1f91b4cc
FB		 2130 struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[ep_idx];
2131 struct dwc2_hsotg_req *hs_req = hs_ep->req;
94cb8fd6 2132 void __iomem *fifo = hsotg->regs + EPFIFO(ep_idx);
5b7d70c6
BD		 2133 int to_read;
2134 int max_req;
2135 int read_ptr;
2136
2137 if (!hs_req) {
95c8bc36 2138 u32 epctl = dwc2_readl(hsotg->regs + DOEPCTL(ep_idx));
5b7d70c6
BD		 2139 int ptr;
2140
6b448af4 2141 dev_dbg(hsotg->dev,
9da51974 2142 "%s: FIFO %d bytes on ep%d but no req (DXEPCTl=0x%08x)\n",
5b7d70c6
BD		 2143 __func__, size, ep_idx, epctl);
2144
2145 /* dump the data from the FIFO, we've nothing we can do */
2146 for (ptr = 0; ptr < size; ptr += 4)
95c8bc36 2147 (void)dwc2_readl(fifo);
5b7d70c6
BD		 2148
2149 return;
2150 }
2151
5b7d70c6
BD		 2152 to_read = size;
2153 read_ptr = hs_req->req.actual;
2154 max_req = hs_req->req.length - read_ptr;
2155
a33e7136
BD		 2156 dev_dbg(hsotg->dev, "%s: read %d/%d, done %d/%d\n",
2157 __func__, to_read, max_req, read_ptr, hs_req->req.length);
2158
5b7d70c6 2159 if (to_read > max_req) {
8b9bc460
LM		 2160 /*
2161 * more data appeared than we where willing
5b7d70c6
BD		 2162 * to deal with in this request.
2163 */
2164
2165 /* currently we don't deal this */
2166 WARN_ON_ONCE(1);
2167 }
2168
5b7d70c6
BD		 2169 hs_ep->total_data += to_read;
2170 hs_req->req.actual += to_read;
2171 to_read = DIV_ROUND_UP(to_read, 4);
2172
8b9bc460
LM		 2173 /*
2174 * note, we might over-write the buffer end by 3 bytes depending on
2175 * alignment of the data.
2176 */
1a7ed5be 2177 ioread32_rep(fifo, hs_req->req.buf + read_ptr, to_read);
5b7d70c6
BD		 2178}
2179
2180/**
1f91b4cc 2181 * dwc2_hsotg_ep0_zlp - send/receive zero-length packet on control endpoint
5b7d70c6 2182 * @hsotg: The device instance
fe0b94ab 2183 * @dir_in: If IN zlp
5b7d70c6
BD		 2184 *
2185 * Generate a zero-length IN packet request for terminating a SETUP
2186 * transaction.
2187 *
2188 * Note, since we don't write any data to the TxFIFO, then it is
25985edc 2189 * currently believed that we do not need to wait for any space in
5b7d70c6
BD		 2190 * the TxFIFO.
2191 */
1f91b4cc 2192static void dwc2_hsotg_ep0_zlp(struct dwc2_hsotg *hsotg, bool dir_in)
5b7d70c6 2193{
c6f5c050 2194 /* eps_out[0] is used in both directions */
fe0b94ab
MYK		 2195 hsotg->eps_out[0]->dir_in = dir_in;
2196 hsotg->ep0_state = dir_in ? DWC2_EP0_STATUS_IN : DWC2_EP0_STATUS_OUT;
5b7d70c6 2197
1f91b4cc 2198 dwc2_hsotg_program_zlp(hsotg, hsotg->eps_out[0]);
5b7d70c6
BD		 2199}
2200
ec1f9d9f 2201static void dwc2_hsotg_change_ep_iso_parity(struct dwc2_hsotg *hsotg,
9da51974 2202 u32 epctl_reg)
ec1f9d9f
RB		 2203{
2204 u32 ctrl;
2205
2206 ctrl = dwc2_readl(hsotg->regs + epctl_reg);
2207 if (ctrl & DXEPCTL_EOFRNUM)
2208 ctrl |= DXEPCTL_SETEVENFR;
2209 else
2210 ctrl |= DXEPCTL_SETODDFR;
2211 dwc2_writel(ctrl, hsotg->regs + epctl_reg);
2212}
2213
aa3e8bc8
VA		 2214/*
2215 * dwc2_gadget_get_xfersize_ddma - get transferred bytes amount from desc
2216 * @hs_ep - The endpoint on which transfer went
2217 *
2218 * Iterate over endpoints descriptor chain and get info on bytes remained
2219 * in DMA descriptors after transfer has completed. Used for non isoc EPs.
2220 */
2221static unsigned int dwc2_gadget_get_xfersize_ddma(struct dwc2_hsotg_ep *hs_ep)
2222{
2223 struct dwc2_hsotg *hsotg = hs_ep->parent;
2224 unsigned int bytes_rem = 0;
2225 struct dwc2_dma_desc *desc = hs_ep->desc_list;
2226 int i;
2227 u32 status;
2228
2229 if (!desc)
2230 return -EINVAL;
2231
2232 for (i = 0; i < hs_ep->desc_count; ++i) {
2233 status = desc->status;
2234 bytes_rem += status & DEV_DMA_NBYTES_MASK;
2235
2236 if (status & DEV_DMA_STS_MASK)
2237 dev_err(hsotg->dev, "descriptor %d closed with %x\n",
2238 i, status & DEV_DMA_STS_MASK);
2239 }
2240
2241 return bytes_rem;
2242}
2243
5b7d70c6 2244/**
1f91b4cc 2245 * dwc2_hsotg_handle_outdone - handle receiving OutDone/SetupDone from RXFIFO
5b7d70c6
BD		 2246 * @hsotg: The device instance
2247 * @epnum: The endpoint received from
5b7d70c6
BD		 2248 *
2249 * The RXFIFO has delivered an OutDone event, which means that the data
2250 * transfer for an OUT endpoint has been completed, either by a short
2251 * packet or by the finish of a transfer.
8b9bc460 2252 */
1f91b4cc 2253static void dwc2_hsotg_handle_outdone(struct dwc2_hsotg *hsotg, int epnum)
5b7d70c6 2254{
95c8bc36 2255 u32 epsize = dwc2_readl(hsotg->regs + DOEPTSIZ(epnum));
1f91b4cc
FB		 2256 struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[epnum];
2257 struct dwc2_hsotg_req *hs_req = hs_ep->req;
5b7d70c6 2258 struct usb_request *req = &hs_req->req;
9da51974 2259 unsigned int size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
5b7d70c6
BD		 2260 int result = 0;
2261
2262 if (!hs_req) {
2263 dev_dbg(hsotg->dev, "%s: no request active\n", __func__);
2264 return;
2265 }
2266
fe0b94ab
MYK		 2267 if (epnum == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_OUT) {
2268 dev_dbg(hsotg->dev, "zlp packet received\n");
1f91b4cc
FB		 2269 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2270 dwc2_hsotg_enqueue_setup(hsotg);
fe0b94ab
MYK		 2271 return;
2272 }
2273
aa3e8bc8
VA		 2274 if (using_desc_dma(hsotg))
2275 size_left = dwc2_gadget_get_xfersize_ddma(hs_ep);
2276
5b7d70c6 2277 if (using_dma(hsotg)) {
9da51974 2278 unsigned int size_done;
5b7d70c6 2279
8b9bc460
LM		 2280 /*
2281 * Calculate the size of the transfer by checking how much
5b7d70c6
BD		 2282 * is left in the endpoint size register and then working it
2283 * out from the amount we loaded for the transfer.
2284 *
2285 * We need to do this as DMA pointers are always 32bit aligned
2286 * so may overshoot/undershoot the transfer.
2287 */
2288
5b7d70c6
BD		 2289 size_done = hs_ep->size_loaded - size_left;
2290 size_done += hs_ep->last_load;
2291
2292 req->actual = size_done;
2293 }
2294
a33e7136
BD		 2295 /* if there is more request to do, schedule new transfer */
2296 if (req->actual < req->length && size_left == 0) {
1f91b4cc 2297 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true);
a33e7136
BD		 2298 return;
2299 }
2300
5b7d70c6
BD		 2301 if (req->actual < req->length && req->short_not_ok) {
2302 dev_dbg(hsotg->dev, "%s: got %d/%d (short not ok) => error\n",
2303 __func__, req->actual, req->length);
2304
8b9bc460
LM		 2305 /*
2306 * todo - what should we return here? there's no one else
2307 * even bothering to check the status.
2308 */
5b7d70c6
BD		 2309 }
2310
ef750c71
VA		 2311 /* DDMA IN status phase will start from StsPhseRcvd interrupt */
2312 if (!using_desc_dma(hsotg) && epnum == 0 &&
2313 hsotg->ep0_state == DWC2_EP0_DATA_OUT) {
fe0b94ab 2314 /* Move to STATUS IN */
1f91b4cc 2315 dwc2_hsotg_ep0_zlp(hsotg, true);
fe0b94ab 2316 return;
5b7d70c6
BD		 2317 }
2318
ec1f9d9f
RB		 2319 /*
2320 * Slave mode OUT transfers do not go through XferComplete so
2321 * adjust the ISOC parity here.
2322 */
2323 if (!using_dma(hsotg)) {
ec1f9d9f
RB		 2324 if (hs_ep->isochronous && hs_ep->interval == 1)
2325 dwc2_hsotg_change_ep_iso_parity(hsotg, DOEPCTL(epnum));
837e9f00
VM		 2326 else if (hs_ep->isochronous && hs_ep->interval > 1)
2327 dwc2_gadget_incr_frame_num(hs_ep);
ec1f9d9f
RB		 2328 }
2329
1f91b4cc 2330 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, result);
5b7d70c6
BD		 2331}
2332
5b7d70c6 2333/**
1f91b4cc 2334 * dwc2_hsotg_handle_rx - RX FIFO has data
5b7d70c6
BD		 2335 * @hsotg: The device instance
2336 *
2337 * The IRQ handler has detected that the RX FIFO has some data in it
2338 * that requires processing, so find out what is in there and do the
2339 * appropriate read.
2340 *
25985edc 2341 * The RXFIFO is a true FIFO, the packets coming out are still in packet
5b7d70c6
BD		 2342 * chunks, so if you have x packets received on an endpoint you'll get x
2343 * FIFO events delivered, each with a packet's worth of data in it.
2344 *
2345 * When using DMA, we should not be processing events from the RXFIFO
2346 * as the actual data should be sent to the memory directly and we turn
2347 * on the completion interrupts to get notifications of transfer completion.
2348 */
1f91b4cc 2349static void dwc2_hsotg_handle_rx(struct dwc2_hsotg *hsotg)
5b7d70c6 2350{
95c8bc36 2351 u32 grxstsr = dwc2_readl(hsotg->regs + GRXSTSP);
5b7d70c6
BD		 2352 u32 epnum, status, size;
2353
2354 WARN_ON(using_dma(hsotg));
2355
47a1685f
DN		 2356 epnum = grxstsr & GRXSTS_EPNUM_MASK;
2357 status = grxstsr & GRXSTS_PKTSTS_MASK;
5b7d70c6 2358
47a1685f
DN		 2359 size = grxstsr & GRXSTS_BYTECNT_MASK;
2360 size >>= GRXSTS_BYTECNT_SHIFT;
5b7d70c6 2361
d7c747c5 2362 dev_dbg(hsotg->dev, "%s: GRXSTSP=0x%08x (%d@%d)\n",
9da51974 2363 __func__, grxstsr, size, epnum);
5b7d70c6 2364
47a1685f
DN		 2365 switch ((status & GRXSTS_PKTSTS_MASK) >> GRXSTS_PKTSTS_SHIFT) {
2366 case GRXSTS_PKTSTS_GLOBALOUTNAK:
2367 dev_dbg(hsotg->dev, "GLOBALOUTNAK\n");
5b7d70c6
BD		 2368 break;
2369
47a1685f 2370 case GRXSTS_PKTSTS_OUTDONE:
5b7d70c6 2371 dev_dbg(hsotg->dev, "OutDone (Frame=0x%08x)\n",
1f91b4cc 2372 dwc2_hsotg_read_frameno(hsotg));
5b7d70c6
BD		 2373
2374 if (!using_dma(hsotg))
1f91b4cc 2375 dwc2_hsotg_handle_outdone(hsotg, epnum);
5b7d70c6
BD		 2376 break;
2377
47a1685f 2378 case GRXSTS_PKTSTS_SETUPDONE:
5b7d70c6
BD		 2379 dev_dbg(hsotg->dev,
2380 "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
1f91b4cc 2381 dwc2_hsotg_read_frameno(hsotg),
95c8bc36 2382 dwc2_readl(hsotg->regs + DOEPCTL(0)));
fe0b94ab 2383 /*
1f91b4cc 2384 * Call dwc2_hsotg_handle_outdone here if it was not called from
fe0b94ab
MYK		 2385 * GRXSTS_PKTSTS_OUTDONE. That is, if the core didn't
2386 * generate GRXSTS_PKTSTS_OUTDONE for setup packet.
2387 */
2388 if (hsotg->ep0_state == DWC2_EP0_SETUP)
1f91b4cc 2389 dwc2_hsotg_handle_outdone(hsotg, epnum);
5b7d70c6
BD		 2390 break;
2391
47a1685f 2392 case GRXSTS_PKTSTS_OUTRX:
1f91b4cc 2393 dwc2_hsotg_rx_data(hsotg, epnum, size);
5b7d70c6
BD		 2394 break;
2395
47a1685f 2396 case GRXSTS_PKTSTS_SETUPRX:
5b7d70c6
BD		 2397 dev_dbg(hsotg->dev,
2398 "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
1f91b4cc 2399 dwc2_hsotg_read_frameno(hsotg),
95c8bc36 2400 dwc2_readl(hsotg->regs + DOEPCTL(0)));
5b7d70c6 2401
fe0b94ab
MYK		 2402 WARN_ON(hsotg->ep0_state != DWC2_EP0_SETUP);
2403
1f91b4cc 2404 dwc2_hsotg_rx_data(hsotg, epnum, size);
5b7d70c6
BD		 2405 break;
2406
2407 default:
2408 dev_warn(hsotg->dev, "%s: unknown status %08x\n",
2409 __func__, grxstsr);
2410
1f91b4cc 2411 dwc2_hsotg_dump(hsotg);
5b7d70c6
BD		 2412 break;
2413 }
2414}
2415
2416/**
1f91b4cc 2417 * dwc2_hsotg_ep0_mps - turn max packet size into register setting
5b7d70c6 2418 * @mps: The maximum packet size in bytes.
8b9bc460 2419 */
1f91b4cc 2420static u32 dwc2_hsotg_ep0_mps(unsigned int mps)
5b7d70c6
BD		 2421{
2422 switch (mps) {
2423 case 64:
94cb8fd6 2424 return D0EPCTL_MPS_64;
5b7d70c6 2425 case 32:
94cb8fd6 2426 return D0EPCTL_MPS_32;
5b7d70c6 2427 case 16:
94cb8fd6 2428 return D0EPCTL_MPS_16;
5b7d70c6 2429 case 8:
94cb8fd6 2430 return D0EPCTL_MPS_8;
5b7d70c6
BD		 2431 }
2432
2433 /* bad max packet size, warn and return invalid result */
2434 WARN_ON(1);
2435 return (u32)-1;
2436}
2437
2438/**
1f91b4cc 2439 * dwc2_hsotg_set_ep_maxpacket - set endpoint's max-packet field
5b7d70c6
BD		 2440 * @hsotg: The driver state.
2441 * @ep: The index number of the endpoint
2442 * @mps: The maximum packet size in bytes
ee2c40de 2443 * @mc: The multicount value
5b7d70c6
BD		 2444 *
2445 * Configure the maximum packet size for the given endpoint, updating
2446 * the hardware control registers to reflect this.
2447 */
1f91b4cc 2448static void dwc2_hsotg_set_ep_maxpacket(struct dwc2_hsotg *hsotg,
ee2c40de
VM		 2449 unsigned int ep, unsigned int mps,
2450 unsigned int mc, unsigned int dir_in)
5b7d70c6 2451{
1f91b4cc 2452 struct dwc2_hsotg_ep *hs_ep;
5b7d70c6 2453 void __iomem *regs = hsotg->regs;
5b7d70c6
BD		 2454 u32 reg;
2455
c6f5c050
MYK		 2456 hs_ep = index_to_ep(hsotg, ep, dir_in);
2457 if (!hs_ep)
2458 return;
2459
5b7d70c6 2460 if (ep == 0) {
ee2c40de
VM		 2461 u32 mps_bytes = mps;
2462
5b7d70c6 2463 /* EP0 is a special case */
ee2c40de
VM		 2464 mps = dwc2_hsotg_ep0_mps(mps_bytes);
2465 if (mps > 3)
5b7d70c6 2466 goto bad_mps;
ee2c40de 2467 hs_ep->ep.maxpacket = mps_bytes;
4fca54aa 2468 hs_ep->mc = 1;
5b7d70c6 2469 } else {
ee2c40de 2470 if (mps > 1024)
5b7d70c6 2471 goto bad_mps;
ee2c40de
VM		 2472 hs_ep->mc = mc;
2473 if (mc > 3)
4fca54aa 2474 goto bad_mps;
ee2c40de 2475 hs_ep->ep.maxpacket = mps;
5b7d70c6
BD		 2476 }
2477
c6f5c050 2478 if (dir_in) {
95c8bc36 2479 reg = dwc2_readl(regs + DIEPCTL(ep));
c6f5c050 2480 reg &= ~DXEPCTL_MPS_MASK;
ee2c40de 2481 reg |= mps;
95c8bc36 2482 dwc2_writel(reg, regs + DIEPCTL(ep));
c6f5c050 2483 } else {
95c8bc36 2484 reg = dwc2_readl(regs + DOEPCTL(ep));
47a1685f 2485 reg &= ~DXEPCTL_MPS_MASK;
ee2c40de 2486 reg |= mps;
95c8bc36 2487 dwc2_writel(reg, regs + DOEPCTL(ep));
659ad60c 2488 }
5b7d70c6
BD		 2489
2490 return;
2491
2492bad_mps:
2493 dev_err(hsotg->dev, "ep%d: bad mps of %d\n", ep, mps);
2494}
2495
9c39ddc6 2496/**
1f91b4cc 2497 * dwc2_hsotg_txfifo_flush - flush Tx FIFO
9c39ddc6
AT		 2498 * @hsotg: The driver state
2499 * @idx: The index for the endpoint (0..15)
2500 */
1f91b4cc 2501static void dwc2_hsotg_txfifo_flush(struct dwc2_hsotg *hsotg, unsigned int idx)
9c39ddc6 2502{
95c8bc36
AS		 2503 dwc2_writel(GRSTCTL_TXFNUM(idx) | GRSTCTL_TXFFLSH,
2504 hsotg->regs + GRSTCTL);
9c39ddc6
AT		 2505
2506 /* wait until the fifo is flushed */
79d6b8c5
SA		 2507 if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL, GRSTCTL_TXFFLSH, 100))
2508 dev_warn(hsotg->dev, "%s: timeout flushing fifo GRSTCTL_TXFFLSH\n",
2509 __func__);
9c39ddc6 2510}
5b7d70c6
BD		 2511
2512/**
1f91b4cc 2513 * dwc2_hsotg_trytx - check to see if anything needs transmitting
5b7d70c6
BD		 2514 * @hsotg: The driver state
2515 * @hs_ep: The driver endpoint to check.
2516 *
2517 * Check to see if there is a request that has data to send, and if so
2518 * make an attempt to write data into the FIFO.
2519 */
1f91b4cc 2520static int dwc2_hsotg_trytx(struct dwc2_hsotg *hsotg,
9da51974 2521 struct dwc2_hsotg_ep *hs_ep)
5b7d70c6 2522{
1f91b4cc 2523 struct dwc2_hsotg_req *hs_req = hs_ep->req;
5b7d70c6 2524
afcf4169
RB		 2525 if (!hs_ep->dir_in || !hs_req) {
2526 /**
2527 * if request is not enqueued, we disable interrupts
2528 * for endpoints, excepting ep0
2529 */
2530 if (hs_ep->index != 0)
1f91b4cc 2531 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index,
9da51974 2532 hs_ep->dir_in, 0);
5b7d70c6 2533 return 0;
afcf4169 2534 }
5b7d70c6
BD		 2535
2536 if (hs_req->req.actual < hs_req->req.length) {
2537 dev_dbg(hsotg->dev, "trying to write more for ep%d\n",
2538 hs_ep->index);
1f91b4cc 2539 return dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req);
5b7d70c6
BD		 2540 }
2541
2542 return 0;
2543}
2544
2545/**
1f91b4cc 2546 * dwc2_hsotg_complete_in - complete IN transfer
5b7d70c6
BD		 2547 * @hsotg: The device state.
2548 * @hs_ep: The endpoint that has just completed.
2549 *
2550 * An IN transfer has been completed, update the transfer's state and then
2551 * call the relevant completion routines.
2552 */
1f91b4cc 2553static void dwc2_hsotg_complete_in(struct dwc2_hsotg *hsotg,
9da51974 2554 struct dwc2_hsotg_ep *hs_ep)
5b7d70c6 2555{
1f91b4cc 2556 struct dwc2_hsotg_req *hs_req = hs_ep->req;
95c8bc36 2557 u32 epsize = dwc2_readl(hsotg->regs + DIEPTSIZ(hs_ep->index));
5b7d70c6
BD		 2558 int size_left, size_done;
2559
2560 if (!hs_req) {
2561 dev_dbg(hsotg->dev, "XferCompl but no req\n");
2562 return;
2563 }
2564
d3ca0259 2565 /* Finish ZLP handling for IN EP0 transactions */
fe0b94ab
MYK		 2566 if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_IN) {
2567 dev_dbg(hsotg->dev, "zlp packet sent\n");
c3b22fe2
RK		 2568
2569 /*
2570 * While send zlp for DWC2_EP0_STATUS_IN EP direction was
2571 * changed to IN. Change back to complete OUT transfer request
2572 */
2573 hs_ep->dir_in = 0;
2574
1f91b4cc 2575 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
9e14d0a5
GH		 2576 if (hsotg->test_mode) {
2577 int ret;
2578
1f91b4cc 2579 ret = dwc2_hsotg_set_test_mode(hsotg, hsotg->test_mode);
9e14d0a5
GH		 2580 if (ret < 0) {
2581 dev_dbg(hsotg->dev, "Invalid Test #%d\n",
9da51974 2582 hsotg->test_mode);
1f91b4cc 2583 dwc2_hsotg_stall_ep0(hsotg);
9e14d0a5
GH		 2584 return;
2585 }
2586 }
1f91b4cc 2587 dwc2_hsotg_enqueue_setup(hsotg);
d3ca0259
LM		 2588 return;
2589 }
2590
8b9bc460
LM		 2591 /*
2592 * Calculate the size of the transfer by checking how much is left
5b7d70c6
BD		 2593 * in the endpoint size register and then working it out from
2594 * the amount we loaded for the transfer.
2595 *
2596 * We do this even for DMA, as the transfer may have incremented
2597 * past the end of the buffer (DMA transfers are always 32bit
2598 * aligned).
2599 */
aa3e8bc8
VA		 2600 if (using_desc_dma(hsotg)) {
2601 size_left = dwc2_gadget_get_xfersize_ddma(hs_ep);
2602 if (size_left < 0)
2603 dev_err(hsotg->dev, "error parsing DDMA results %d\n",
2604 size_left);
2605 } else {
2606 size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
2607 }
5b7d70c6
BD		 2608
2609 size_done = hs_ep->size_loaded - size_left;
2610 size_done += hs_ep->last_load;
2611
2612 if (hs_req->req.actual != size_done)
2613 dev_dbg(hsotg->dev, "%s: adjusting size done %d => %d\n",
2614 __func__, hs_req->req.actual, size_done);
2615
2616 hs_req->req.actual = size_done;
d3ca0259
LM		 2617 dev_dbg(hsotg->dev, "req->length:%d req->actual:%d req->zero:%d\n",
2618 hs_req->req.length, hs_req->req.actual, hs_req->req.zero);
2619
5b7d70c6
BD		 2620 if (!size_left && hs_req->req.actual < hs_req->req.length) {
2621 dev_dbg(hsotg->dev, "%s trying more for req...\n", __func__);
1f91b4cc 2622 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true);
fe0b94ab
MYK		 2623 return;
2624 }
2625
f71b5e25 2626 /* Zlp for all endpoints, for ep0 only in DATA IN stage */
8a20fa45 2627 if (hs_ep->send_zlp) {
1f91b4cc 2628 dwc2_hsotg_program_zlp(hsotg, hs_ep);
8a20fa45 2629 hs_ep->send_zlp = 0;
f71b5e25
MYK		 2630 /* transfer will be completed on next complete interrupt */
2631 return;
2632 }
2633
fe0b94ab
MYK		 2634 if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_DATA_IN) {
2635 /* Move to STATUS OUT */
1f91b4cc 2636 dwc2_hsotg_ep0_zlp(hsotg, false);
fe0b94ab
MYK		 2637 return;
2638 }
2639
1f91b4cc 2640 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
5b7d70c6
BD		 2641}
2642
32601588
VM		 2643/**
2644 * dwc2_gadget_read_ep_interrupts - reads interrupts for given ep
2645 * @hsotg: The device state.
2646 * @idx: Index of ep.
2647 * @dir_in: Endpoint direction 1-in 0-out.
2648 *
2649 * Reads for endpoint with given index and direction, by masking
2650 * epint_reg with coresponding mask.
2651 */
2652static u32 dwc2_gadget_read_ep_interrupts(struct dwc2_hsotg *hsotg,
2653 unsigned int idx, int dir_in)
2654{
2655 u32 epmsk_reg = dir_in ? DIEPMSK : DOEPMSK;
2656 u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx);
2657 u32 ints;
2658 u32 mask;
2659 u32 diepempmsk;
2660
2661 mask = dwc2_readl(hsotg->regs + epmsk_reg);
2662 diepempmsk = dwc2_readl(hsotg->regs + DIEPEMPMSK);
2663 mask |= ((diepempmsk >> idx) & 0x1) ? DIEPMSK_TXFIFOEMPTY : 0;
2664 mask |= DXEPINT_SETUP_RCVD;
2665
2666 ints = dwc2_readl(hsotg->regs + epint_reg);
2667 ints &= mask;
2668 return ints;
2669}
2670
bd9971f0
VM		 2671/**
2672 * dwc2_gadget_handle_ep_disabled - handle DXEPINT_EPDISBLD
2673 * @hs_ep: The endpoint on which interrupt is asserted.
2674 *
2675 * This interrupt indicates that the endpoint has been disabled per the
2676 * application's request.
2677 *
2678 * For IN endpoints flushes txfifo, in case of BULK clears DCTL_CGNPINNAK,
2679 * in case of ISOC completes current request.
2680 *
2681 * For ISOC-OUT endpoints completes expired requests. If there is remaining
2682 * request starts it.
2683 */
2684static void dwc2_gadget_handle_ep_disabled(struct dwc2_hsotg_ep *hs_ep)
2685{
2686 struct dwc2_hsotg *hsotg = hs_ep->parent;
2687 struct dwc2_hsotg_req *hs_req;
2688 unsigned char idx = hs_ep->index;
2689 int dir_in = hs_ep->dir_in;
2690 u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx);
2691 int dctl = dwc2_readl(hsotg->regs + DCTL);
2692
2693 dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__);
2694
2695 if (dir_in) {
2696 int epctl = dwc2_readl(hsotg->regs + epctl_reg);
2697
2698 dwc2_hsotg_txfifo_flush(hsotg, hs_ep->fifo_index);
2699
2700 if (hs_ep->isochronous) {
2701 dwc2_hsotg_complete_in(hsotg, hs_ep);
2702 return;
2703 }
2704
2705 if ((epctl & DXEPCTL_STALL) && (epctl & DXEPCTL_EPTYPE_BULK)) {
2706 int dctl = dwc2_readl(hsotg->regs + DCTL);
2707
2708 dctl |= DCTL_CGNPINNAK;
2709 dwc2_writel(dctl, hsotg->regs + DCTL);
2710 }
2711 return;
2712 }
2713
2714 if (dctl & DCTL_GOUTNAKSTS) {
2715 dctl |= DCTL_CGOUTNAK;
2716 dwc2_writel(dctl, hsotg->regs + DCTL);
2717 }
2718
2719 if (!hs_ep->isochronous)
2720 return;
2721
2722 if (list_empty(&hs_ep->queue)) {
2723 dev_dbg(hsotg->dev, "%s: complete_ep 0x%p, ep->queue empty!\n",
2724 __func__, hs_ep);
2725 return;
2726 }
2727
2728 do {
2729 hs_req = get_ep_head(hs_ep);
2730 if (hs_req)
2731 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req,
2732 -ENODATA);
2733 dwc2_gadget_incr_frame_num(hs_ep);
2734 } while (dwc2_gadget_target_frame_elapsed(hs_ep));
2735
2736 dwc2_gadget_start_next_request(hs_ep);
2737}
2738
5321922c
VM		 2739/**
2740 * dwc2_gadget_handle_out_token_ep_disabled - handle DXEPINT_OUTTKNEPDIS
2741 * @hs_ep: The endpoint on which interrupt is asserted.
2742 *
2743 * This is starting point for ISOC-OUT transfer, synchronization done with
2744 * first out token received from host while corresponding EP is disabled.
2745 *
2746 * Device does not know initial frame in which out token will come. For this
2747 * HW generates OUTTKNEPDIS - out token is received while EP is disabled. Upon
2748 * getting this interrupt SW starts calculation for next transfer frame.
2749 */
2750static void dwc2_gadget_handle_out_token_ep_disabled(struct dwc2_hsotg_ep *ep)
2751{
2752 struct dwc2_hsotg *hsotg = ep->parent;
2753 int dir_in = ep->dir_in;
2754 u32 doepmsk;
540ccba0 2755 u32 tmp;
5321922c
VM		 2756
2757 if (dir_in || !ep->isochronous)
2758 return;
2759
540ccba0
VA		 2760 /*
2761 * Store frame in which irq was asserted here, as
2762 * it can change while completing request below.
2763 */
2764 tmp = dwc2_hsotg_read_frameno(hsotg);
2765
5321922c
VM		 2766 dwc2_hsotg_complete_request(hsotg, ep, get_ep_head(ep), -ENODATA);
2767
540ccba0
VA		 2768 if (using_desc_dma(hsotg)) {
2769 if (ep->target_frame == TARGET_FRAME_INITIAL) {
2770 /* Start first ISO Out */
2771 ep->target_frame = tmp;
2772 dwc2_gadget_start_isoc_ddma(ep);
2773 }
2774 return;
2775 }
2776
5321922c
VM		 2777 if (ep->interval > 1 &&
2778 ep->target_frame == TARGET_FRAME_INITIAL) {
2779 u32 dsts;
2780 u32 ctrl;
2781
2782 dsts = dwc2_readl(hsotg->regs + DSTS);
2783 ep->target_frame = dwc2_hsotg_read_frameno(hsotg);
2784 dwc2_gadget_incr_frame_num(ep);
2785
2786 ctrl = dwc2_readl(hsotg->regs + DOEPCTL(ep->index));
2787 if (ep->target_frame & 0x1)
2788 ctrl |= DXEPCTL_SETODDFR;
2789 else
2790 ctrl |= DXEPCTL_SETEVENFR;
2791
2792 dwc2_writel(ctrl, hsotg->regs + DOEPCTL(ep->index));
2793 }
2794
2795 dwc2_gadget_start_next_request(ep);
2796 doepmsk = dwc2_readl(hsotg->regs + DOEPMSK);
2797 doepmsk &= ~DOEPMSK_OUTTKNEPDISMSK;
2798 dwc2_writel(doepmsk, hsotg->regs + DOEPMSK);
2799}
2800
2801/**
38beaec6
JY		 2802 * dwc2_gadget_handle_nak - handle NAK interrupt
2803 * @hs_ep: The endpoint on which interrupt is asserted.
2804 *
2805 * This is starting point for ISOC-IN transfer, synchronization done with
2806 * first IN token received from host while corresponding EP is disabled.
2807 *
2808 * Device does not know when first one token will arrive from host. On first
2809 * token arrival HW generates 2 interrupts: 'in token received while FIFO empty'
2810 * and 'NAK'. NAK interrupt for ISOC-IN means that token has arrived and ZLP was
2811 * sent in response to that as there was no data in FIFO. SW is basing on this
2812 * interrupt to obtain frame in which token has come and then based on the
2813 * interval calculates next frame for transfer.
2814 */
5321922c
VM		 2815static void dwc2_gadget_handle_nak(struct dwc2_hsotg_ep *hs_ep)
2816{
2817 struct dwc2_hsotg *hsotg = hs_ep->parent;
2818 int dir_in = hs_ep->dir_in;
2819
2820 if (!dir_in || !hs_ep->isochronous)
2821 return;
2822
2823 if (hs_ep->target_frame == TARGET_FRAME_INITIAL) {
2824 hs_ep->target_frame = dwc2_hsotg_read_frameno(hsotg);
540ccba0
VA		 2825
2826 if (using_desc_dma(hsotg)) {
2827 dwc2_gadget_start_isoc_ddma(hs_ep);
2828 return;
2829 }
2830
5321922c
VM		 2831 if (hs_ep->interval > 1) {
2832 u32 ctrl = dwc2_readl(hsotg->regs +
2833 DIEPCTL(hs_ep->index));
2834 if (hs_ep->target_frame & 0x1)
2835 ctrl |= DXEPCTL_SETODDFR;
2836 else
2837 ctrl |= DXEPCTL_SETEVENFR;
2838
2839 dwc2_writel(ctrl, hsotg->regs + DIEPCTL(hs_ep->index));
2840 }
2841
2842 dwc2_hsotg_complete_request(hsotg, hs_ep,
2843 get_ep_head(hs_ep), 0);
2844 }
2845
2846 dwc2_gadget_incr_frame_num(hs_ep);
2847}
2848
5b7d70c6 2849/**
1f91b4cc 2850 * dwc2_hsotg_epint - handle an in/out endpoint interrupt
5b7d70c6
BD		 2851 * @hsotg: The driver state
2852 * @idx: The index for the endpoint (0..15)
2853 * @dir_in: Set if this is an IN endpoint
2854 *
2855 * Process and clear any interrupt pending for an individual endpoint
8b9bc460 2856 */
1f91b4cc 2857static void dwc2_hsotg_epint(struct dwc2_hsotg *hsotg, unsigned int idx,
9da51974 2858 int dir_in)
5b7d70c6 2859{
1f91b4cc 2860 struct dwc2_hsotg_ep *hs_ep = index_to_ep(hsotg, idx, dir_in);
94cb8fd6
LM		 2861 u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx);
2862 u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx);
2863 u32 epsiz_reg = dir_in ? DIEPTSIZ(idx) : DOEPTSIZ(idx);
5b7d70c6 2864 u32 ints;
1479e841 2865 u32 ctrl;
5b7d70c6 2866
32601588 2867 ints = dwc2_gadget_read_ep_interrupts(hsotg, idx, dir_in);
95c8bc36 2868 ctrl = dwc2_readl(hsotg->regs + epctl_reg);
5b7d70c6 2869
a3395f0d 2870 /* Clear endpoint interrupts */
95c8bc36 2871 dwc2_writel(ints, hsotg->regs + epint_reg);
a3395f0d 2872
c6f5c050
MYK		 2873 if (!hs_ep) {
2874 dev_err(hsotg->dev, "%s:Interrupt for unconfigured ep%d(%s)\n",
9da51974 2875 __func__, idx, dir_in ? "in" : "out");
c6f5c050
MYK		 2876 return;
2877 }
2878
5b7d70c6
BD		 2879 dev_dbg(hsotg->dev, "%s: ep%d(%s) DxEPINT=0x%08x\n",
2880 __func__, idx, dir_in ? "in" : "out", ints);
2881
b787d755
MYK		 2882 /* Don't process XferCompl interrupt if it is a setup packet */
2883 if (idx == 0 && (ints & (DXEPINT_SETUP | DXEPINT_SETUP_RCVD)))
2884 ints &= ~DXEPINT_XFERCOMPL;
2885
f0afdb42
VA		 2886 /*
2887 * Don't process XferCompl interrupt in DDMA if EP0 is still in SETUP
2888 * stage and xfercomplete was generated without SETUP phase done
2889 * interrupt. SW should parse received setup packet only after host's
2890 * exit from setup phase of control transfer.
2891 */
2892 if (using_desc_dma(hsotg) && idx == 0 && !hs_ep->dir_in &&
2893 hsotg->ep0_state == DWC2_EP0_SETUP && !(ints & DXEPINT_SETUP))
2894 ints &= ~DXEPINT_XFERCOMPL;
2895
837e9f00 2896 if (ints & DXEPINT_XFERCOMPL) {
5b7d70c6 2897 dev_dbg(hsotg->dev,
47a1685f 2898 "%s: XferCompl: DxEPCTL=0x%08x, DXEPTSIZ=%08x\n",
95c8bc36
AS		 2899 __func__, dwc2_readl(hsotg->regs + epctl_reg),
2900 dwc2_readl(hsotg->regs + epsiz_reg));
5b7d70c6 2901
540ccba0
VA		 2902 /* In DDMA handle isochronous requests separately */
2903 if (using_desc_dma(hsotg) && hs_ep->isochronous) {
2904 dwc2_gadget_complete_isoc_request_ddma(hs_ep);
2905 /* Try to start next isoc request */
2906 dwc2_gadget_start_next_isoc_ddma(hs_ep);
2907 } else if (dir_in) {
2908 /*
2909 * We get OutDone from the FIFO, so we only
2910 * need to look at completing IN requests here
2911 * if operating slave mode
2912 */
837e9f00
VM		 2913 if (hs_ep->isochronous && hs_ep->interval > 1)
2914 dwc2_gadget_incr_frame_num(hs_ep);
2915
1f91b4cc 2916 dwc2_hsotg_complete_in(hsotg, hs_ep);
837e9f00
VM		 2917 if (ints & DXEPINT_NAKINTRPT)
2918 ints &= ~DXEPINT_NAKINTRPT;
5b7d70c6 2919
c9a64ea8 2920 if (idx == 0 && !hs_ep->req)
1f91b4cc 2921 dwc2_hsotg_enqueue_setup(hsotg);
5b7d70c6 2922 } else if (using_dma(hsotg)) {
8b9bc460
LM		 2923 /*
2924 * We're using DMA, we need to fire an OutDone here
2925 * as we ignore the RXFIFO.
2926 */
837e9f00
VM		 2927 if (hs_ep->isochronous && hs_ep->interval > 1)
2928 dwc2_gadget_incr_frame_num(hs_ep);
5b7d70c6 2929
1f91b4cc 2930 dwc2_hsotg_handle_outdone(hsotg, idx);
5b7d70c6 2931 }
5b7d70c6
BD		 2932 }
2933
bd9971f0
VM		 2934 if (ints & DXEPINT_EPDISBLD)
2935 dwc2_gadget_handle_ep_disabled(hs_ep);
9c39ddc6 2936
5321922c
VM		 2937 if (ints & DXEPINT_OUTTKNEPDIS)
2938 dwc2_gadget_handle_out_token_ep_disabled(hs_ep);
2939
2940 if (ints & DXEPINT_NAKINTRPT)
2941 dwc2_gadget_handle_nak(hs_ep);
2942
47a1685f 2943 if (ints & DXEPINT_AHBERR)
5b7d70c6 2944 dev_dbg(hsotg->dev, "%s: AHBErr\n", __func__);
5b7d70c6 2945
47a1685f 2946 if (ints & DXEPINT_SETUP) { /* Setup or Timeout */
5b7d70c6
BD		 2947 dev_dbg(hsotg->dev, "%s: Setup/Timeout\n", __func__);
2948
2949 if (using_dma(hsotg) && idx == 0) {
8b9bc460
LM		 2950 /*
2951 * this is the notification we've received a
5b7d70c6
BD		 2952 * setup packet. In non-DMA mode we'd get this
2953 * from the RXFIFO, instead we need to process
8b9bc460
LM		 2954 * the setup here.
2955 */
5b7d70c6
BD		 2956
2957 if (dir_in)
2958 WARN_ON_ONCE(1);
2959 else
1f91b4cc 2960 dwc2_hsotg_handle_outdone(hsotg, 0);
5b7d70c6 2961 }
5b7d70c6
BD		 2962 }
2963
ef750c71 2964 if (ints & DXEPINT_STSPHSERCVD) {
9d9a6b07
VA		 2965 dev_dbg(hsotg->dev, "%s: StsPhseRcvd\n", __func__);
2966
9e95a66c
MH		 2967 /* Safety check EP0 state when STSPHSERCVD asserted */
2968 if (hsotg->ep0_state == DWC2_EP0_DATA_OUT) {
2969 /* Move to STATUS IN for DDMA */
2970 if (using_desc_dma(hsotg))
2971 dwc2_hsotg_ep0_zlp(hsotg, true);
2972 }
2973
ef750c71
VA		 2974 }
2975
47a1685f 2976 if (ints & DXEPINT_BACK2BACKSETUP)
5b7d70c6 2977 dev_dbg(hsotg->dev, "%s: B2BSetup/INEPNakEff\n", __func__);
5b7d70c6 2978
540ccba0
VA		 2979 if (ints & DXEPINT_BNAINTR) {
2980 dev_dbg(hsotg->dev, "%s: BNA interrupt\n", __func__);
2981
2982 /*
2983 * Try to start next isoc request, if any.
2984 * Sometimes the endpoint remains enabled after BNA interrupt
2985 * assertion, which is not expected, hence we can enter here
2986 * couple of times.
2987 */
2988 if (hs_ep->isochronous)
2989 dwc2_gadget_start_next_isoc_ddma(hs_ep);
2990 }
2991
1479e841 2992 if (dir_in && !hs_ep->isochronous) {
8b9bc460 2993 /* not sure if this is important, but we'll clear it anyway */
26ddef5d 2994 if (ints & DXEPINT_INTKNTXFEMP) {
5b7d70c6
BD		 2995 dev_dbg(hsotg->dev, "%s: ep%d: INTknTXFEmpMsk\n",
2996 __func__, idx);
5b7d70c6
BD		 2997 }
2998
2999 /* this probably means something bad is happening */
26ddef5d 3000 if (ints & DXEPINT_INTKNEPMIS) {
5b7d70c6
BD		 3001 dev_warn(hsotg->dev, "%s: ep%d: INTknEP\n",
3002 __func__, idx);
5b7d70c6 3003 }
10aebc77
BD		 3004
3005 /* FIFO has space or is empty (see GAHBCFG) */
3006 if (hsotg->dedicated_fifos &&
26ddef5d 3007 ints & DXEPINT_TXFEMP) {
10aebc77
BD		 3008 dev_dbg(hsotg->dev, "%s: ep%d: TxFIFOEmpty\n",
3009 __func__, idx);
70fa030f 3010 if (!using_dma(hsotg))
1f91b4cc 3011 dwc2_hsotg_trytx(hsotg, hs_ep);
10aebc77 3012 }
5b7d70c6 3013 }
5b7d70c6
BD		 3014}
3015
3016/**
1f91b4cc 3017 * dwc2_hsotg_irq_enumdone - Handle EnumDone interrupt (enumeration done)
5b7d70c6
BD		 3018 * @hsotg: The device state.
3019 *
3020 * Handle updating the device settings after the enumeration phase has
3021 * been completed.
8b9bc460 3022 */
1f91b4cc 3023static void dwc2_hsotg_irq_enumdone(struct dwc2_hsotg *hsotg)
5b7d70c6 3024{
95c8bc36 3025 u32 dsts = dwc2_readl(hsotg->regs + DSTS);
9b2667f1 3026 int ep0_mps = 0, ep_mps = 8;
5b7d70c6 3027
8b9bc460
LM		 3028 /*
3029 * This should signal the finish of the enumeration phase
5b7d70c6 3030 * of the USB handshaking, so we should now know what rate
8b9bc460
LM		 3031 * we connected at.
3032 */
5b7d70c6
BD		 3033
3034 dev_dbg(hsotg->dev, "EnumDone (DSTS=0x%08x)\n", dsts);
3035
8b9bc460
LM		 3036 /*
3037 * note, since we're limited by the size of transfer on EP0, and
5b7d70c6 3038 * it seems IN transfers must be a even number of packets we do
8b9bc460
LM		 3039 * not advertise a 64byte MPS on EP0.
3040 */
5b7d70c6
BD		 3041
3042 /* catch both EnumSpd_FS and EnumSpd_FS48 */
6d76c92c 3043 switch ((dsts & DSTS_ENUMSPD_MASK) >> DSTS_ENUMSPD_SHIFT) {
47a1685f
DN		 3044 case DSTS_ENUMSPD_FS:
3045 case DSTS_ENUMSPD_FS48:
5b7d70c6 3046 hsotg->gadget.speed = USB_SPEED_FULL;
5b7d70c6 3047 ep0_mps = EP0_MPS_LIMIT;
295538ff 3048 ep_mps = 1023;
5b7d70c6
BD		 3049 break;
3050
47a1685f 3051 case DSTS_ENUMSPD_HS:
5b7d70c6 3052 hsotg->gadget.speed = USB_SPEED_HIGH;
5b7d70c6 3053 ep0_mps = EP0_MPS_LIMIT;
295538ff 3054 ep_mps = 1024;
5b7d70c6
BD		 3055 break;
3056
47a1685f 3057 case DSTS_ENUMSPD_LS:
5b7d70c6 3058 hsotg->gadget.speed = USB_SPEED_LOW;
552d940f
VM		 3059 ep0_mps = 8;
3060 ep_mps = 8;
8b9bc460
LM		 3061 /*
3062 * note, we don't actually support LS in this driver at the
5b7d70c6
BD		 3063 * moment, and the documentation seems to imply that it isn't
3064 * supported by the PHYs on some of the devices.
3065 */
3066 break;
3067 }
e538dfda
MN		 3068 dev_info(hsotg->dev, "new device is %s\n",
3069 usb_speed_string(hsotg->gadget.speed));
5b7d70c6 3070
8b9bc460
LM		 3071 /*
3072 * we should now know the maximum packet size for an
3073 * endpoint, so set the endpoints to a default value.
3074 */
5b7d70c6
BD		 3075
3076 if (ep0_mps) {
3077 int i;
c6f5c050 3078 /* Initialize ep0 for both in and out directions */
ee2c40de
VM		 3079 dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 0, 1);
3080 dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 0, 0);
c6f5c050
MYK		 3081 for (i = 1; i < hsotg->num_of_eps; i++) {
3082 if (hsotg->eps_in[i])
ee2c40de
VM		 3083 dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps,
3084 0, 1);
c6f5c050 3085 if (hsotg->eps_out[i])
ee2c40de
VM		 3086 dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps,
3087 0, 0);
c6f5c050 3088 }
5b7d70c6
BD		 3089 }
3090
3091 /* ensure after enumeration our EP0 is active */
3092
1f91b4cc 3093 dwc2_hsotg_enqueue_setup(hsotg);
5b7d70c6
BD		 3094
3095 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
95c8bc36
AS		 3096 dwc2_readl(hsotg->regs + DIEPCTL0),
3097 dwc2_readl(hsotg->regs + DOEPCTL0));
5b7d70c6
BD		 3098}
3099
3100/**
3101 * kill_all_requests - remove all requests from the endpoint's queue
3102 * @hsotg: The device state.
3103 * @ep: The endpoint the requests may be on.
3104 * @result: The result code to use.
5b7d70c6
BD		 3105 *
3106 * Go through the requests on the given endpoint and mark them
3107 * completed with the given result code.
3108 */
941fcce4 3109static void kill_all_requests(struct dwc2_hsotg *hsotg,
1f91b4cc 3110 struct dwc2_hsotg_ep *ep,
6b448af4 3111 int result)
5b7d70c6 3112{
1f91b4cc 3113 struct dwc2_hsotg_req *req, *treq;
9da51974 3114 unsigned int size;
5b7d70c6 3115
6b448af4 3116 ep->req = NULL;
5b7d70c6 3117
6b448af4 3118 list_for_each_entry_safe(req, treq, &ep->queue, queue)
1f91b4cc 3119 dwc2_hsotg_complete_request(hsotg, ep, req,
9da51974 3120 result);
6b448af4 3121
b203d0a2
RB		 3122 if (!hsotg->dedicated_fifos)
3123 return;
ad674a15 3124 size = (dwc2_readl(hsotg->regs + DTXFSTS(ep->fifo_index)) & 0xffff) * 4;
b203d0a2 3125 if (size < ep->fifo_size)
1f91b4cc 3126 dwc2_hsotg_txfifo_flush(hsotg, ep->fifo_index);
5b7d70c6
BD		 3127}
3128
5b7d70c6 3129/**
1f91b4cc 3130 * dwc2_hsotg_disconnect - disconnect service
5b7d70c6
BD		 3131 * @hsotg: The device state.
3132 *
5e891342
LM		 3133 * The device has been disconnected. Remove all current
3134 * transactions and signal the gadget driver that this
3135 * has happened.
8b9bc460 3136 */
1f91b4cc 3137void dwc2_hsotg_disconnect(struct dwc2_hsotg *hsotg)
5b7d70c6 3138{
9da51974 3139 unsigned int ep;
5b7d70c6 3140
4ace06e8
MS		 3141 if (!hsotg->connected)
3142 return;
3143
3144 hsotg->connected = 0;
9e14d0a5 3145 hsotg->test_mode = 0;
c6f5c050
MYK		 3146
3147 for (ep = 0; ep < hsotg->num_of_eps; ep++) {
3148 if (hsotg->eps_in[ep])
3149 kill_all_requests(hsotg, hsotg->eps_in[ep],
9da51974 3150 -ESHUTDOWN);
c6f5c050
MYK		 3151 if (hsotg->eps_out[ep])
3152 kill_all_requests(hsotg, hsotg->eps_out[ep],
9da51974 3153 -ESHUTDOWN);
c6f5c050 3154 }
5b7d70c6
BD		 3155
3156 call_gadget(hsotg, disconnect);
065d3931 3157 hsotg->lx_state = DWC2_L3;
ce2b21a4
JS		 3158
3159 usb_gadget_set_state(&hsotg->gadget, USB_STATE_NOTATTACHED);
5b7d70c6
BD		 3160}
3161
3162/**
1f91b4cc 3163 * dwc2_hsotg_irq_fifoempty - TX FIFO empty interrupt handler
5b7d70c6
BD		 3164 * @hsotg: The device state:
3165 * @periodic: True if this is a periodic FIFO interrupt
3166 */
1f91b4cc 3167static void dwc2_hsotg_irq_fifoempty(struct dwc2_hsotg *hsotg, bool periodic)
5b7d70c6 3168{
1f91b4cc 3169 struct dwc2_hsotg_ep *ep;
5b7d70c6
BD		 3170 int epno, ret;
3171
3172 /* look through for any more data to transmit */
b3f489b2 3173 for (epno = 0; epno < hsotg->num_of_eps; epno++) {
c6f5c050
MYK		 3174 ep = index_to_ep(hsotg, epno, 1);
3175
3176 if (!ep)
3177 continue;
5b7d70c6
BD		 3178
3179 if (!ep->dir_in)
3180 continue;
3181
3182 if ((periodic && !ep->periodic) ||
3183 (!periodic && ep->periodic))
3184 continue;
3185
1f91b4cc 3186 ret = dwc2_hsotg_trytx(hsotg, ep);
5b7d70c6
BD		 3187 if (ret < 0)
3188 break;
3189 }
3190}
3191
5b7d70c6 3192/* IRQ flags which will trigger a retry around the IRQ loop */
47a1685f
DN		 3193#define IRQ_RETRY_MASK (GINTSTS_NPTXFEMP | \
3194 GINTSTS_PTXFEMP | \
3195 GINTSTS_RXFLVL)
5b7d70c6 3196
8b9bc460 3197/**
1f91b4cc 3198 * dwc2_hsotg_core_init - issue softreset to the core
8b9bc460
LM		 3199 * @hsotg: The device state
3200 *
3201 * Issue a soft reset to the core, and await the core finishing it.
3202 */
1f91b4cc 3203void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg,
9da51974 3204 bool is_usb_reset)
308d734e 3205{
1ee6903b 3206 u32 intmsk;
643cc4de 3207 u32 val;
ecd9a7ad 3208 u32 usbcfg;
79c3b5bb 3209 u32 dcfg = 0;
643cc4de 3210
5390d438
MYK		 3211 /* Kill any ep0 requests as controller will be reinitialized */
3212 kill_all_requests(hsotg, hsotg->eps_out[0], -ECONNRESET);
3213
643cc4de 3214 if (!is_usb_reset)
6e6360b6 3215 if (dwc2_core_reset(hsotg, true))
86de4895 3216 return;
308d734e
LM		 3217
3218 /*
3219 * we must now enable ep0 ready for host detection and then
3220 * set configuration.
3221 */
3222
ecd9a7ad
PR		 3223 /* keep other bits untouched (so e.g. forced modes are not lost) */
3224 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
3225 usbcfg &= ~(GUSBCFG_TOUTCAL_MASK | GUSBCFG_PHYIF16 | GUSBCFG_SRPCAP |
ca02954a 3226 GUSBCFG_HNPCAP | GUSBCFG_USBTRDTIM_MASK);
ecd9a7ad 3227
79c3b5bb 3228 if (hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS &&
38e9002b
VM		 3229 (hsotg->params.speed == DWC2_SPEED_PARAM_FULL ||
3230 hsotg->params.speed == DWC2_SPEED_PARAM_LOW)) {
79c3b5bb
VA		 3231 /* FS/LS Dedicated Transceiver Interface */
3232 usbcfg |= GUSBCFG_PHYSEL;
3233 } else {
3234 /* set the PLL on, remove the HNP/SRP and set the PHY */
3235 val = (hsotg->phyif == GUSBCFG_PHYIF8) ? 9 : 5;
3236 usbcfg |= hsotg->phyif | GUSBCFG_TOUTCAL(7) |
3237 (val << GUSBCFG_USBTRDTIM_SHIFT);
3238 }
ecd9a7ad 3239 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
308d734e 3240
1f91b4cc 3241 dwc2_hsotg_init_fifo(hsotg);
308d734e 3242
643cc4de 3243 if (!is_usb_reset)
abd064a1 3244 dwc2_set_bit(hsotg->regs + DCTL, DCTL_SFTDISCON);
308d734e 3245
79c3b5bb 3246 dcfg |= DCFG_EPMISCNT(1);
38e9002b
VM		 3247
3248 switch (hsotg->params.speed) {
3249 case DWC2_SPEED_PARAM_LOW:
3250 dcfg |= DCFG_DEVSPD_LS;
3251 break;
3252 case DWC2_SPEED_PARAM_FULL:
79c3b5bb
VA		 3253 if (hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS)
3254 dcfg |= DCFG_DEVSPD_FS48;
3255 else
3256 dcfg |= DCFG_DEVSPD_FS;
38e9002b
VM		 3257 break;
3258 default:
79c3b5bb
VA		 3259 dcfg |= DCFG_DEVSPD_HS;
3260 }
38e9002b 3261
79c3b5bb 3262 dwc2_writel(dcfg, hsotg->regs + DCFG);
308d734e
LM		 3263
3264 /* Clear any pending OTG interrupts */
95c8bc36 3265 dwc2_writel(0xffffffff, hsotg->regs + GOTGINT);
308d734e
LM		 3266
3267 /* Clear any pending interrupts */
95c8bc36 3268 dwc2_writel(0xffffffff, hsotg->regs + GINTSTS);
1ee6903b 3269 intmsk = GINTSTS_ERLYSUSP | GINTSTS_SESSREQINT |
47a1685f 3270 GINTSTS_GOUTNAKEFF | GINTSTS_GINNAKEFF |
1ee6903b
GH		 3271 GINTSTS_USBRST | GINTSTS_RESETDET |
3272 GINTSTS_ENUMDONE | GINTSTS_OTGINT |
376f0401
SA		 3273 GINTSTS_USBSUSP | GINTSTS_WKUPINT |
3274 GINTSTS_LPMTRANRCVD;
f4736701
VA		 3275
3276 if (!using_desc_dma(hsotg))
3277 intmsk |= GINTSTS_INCOMPL_SOIN | GINTSTS_INCOMPL_SOOUT;
1ee6903b 3278
95832c00 3279 if (!hsotg->params.external_id_pin_ctl)
1ee6903b
GH		 3280 intmsk |= GINTSTS_CONIDSTSCHNG;
3281
3282 dwc2_writel(intmsk, hsotg->regs + GINTMSK);
308d734e 3283
a5c18f11 3284 if (using_dma(hsotg)) {
95c8bc36 3285 dwc2_writel(GAHBCFG_GLBL_INTR_EN | GAHBCFG_DMA_EN |
d1ac8c80 3286 hsotg->params.ahbcfg,
95c8bc36 3287 hsotg->regs + GAHBCFG);
a5c18f11
VA		 3288
3289 /* Set DDMA mode support in the core if needed */
3290 if (using_desc_dma(hsotg))
abd064a1 3291 dwc2_set_bit(hsotg->regs + DCFG, DCFG_DESCDMA_EN);
a5c18f11
VA		 3292
3293 } else {
95c8bc36
AS		 3294 dwc2_writel(((hsotg->dedicated_fifos) ?
3295 (GAHBCFG_NP_TXF_EMP_LVL |
3296 GAHBCFG_P_TXF_EMP_LVL) : 0) |
3297 GAHBCFG_GLBL_INTR_EN, hsotg->regs + GAHBCFG);
a5c18f11 3298 }
308d734e
LM		 3299
3300 /*
8acc8296
RB		 3301 * If INTknTXFEmpMsk is enabled, it's important to disable ep interrupts
3302 * when we have no data to transfer. Otherwise we get being flooded by
3303 * interrupts.
308d734e
LM		 3304 */
3305
95c8bc36 3306 dwc2_writel(((hsotg->dedicated_fifos && !using_dma(hsotg)) ?
6ff2e832 3307 DIEPMSK_TXFIFOEMPTY | DIEPMSK_INTKNTXFEMPMSK : 0) |
47a1685f 3308 DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK |
837e9f00 3309 DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK,
47a1685f 3310 hsotg->regs + DIEPMSK);
308d734e
LM		 3311
3312 /*
3313 * don't need XferCompl, we get that from RXFIFO in slave mode. In
9d9a6b07 3314 * DMA mode we may need this and StsPhseRcvd.
308d734e 3315 */
9d9a6b07
VA		 3316 dwc2_writel((using_dma(hsotg) ? (DIEPMSK_XFERCOMPLMSK |
3317 DOEPMSK_STSPHSERCVDMSK) : 0) |
47a1685f 3318 DOEPMSK_EPDISBLDMSK | DOEPMSK_AHBERRMSK |
9d9a6b07 3319 DOEPMSK_SETUPMSK,
47a1685f 3320 hsotg->regs + DOEPMSK);
308d734e 3321
ec01f0b2
VA		 3322 /* Enable BNA interrupt for DDMA */
3323 if (using_desc_dma(hsotg))
abd064a1 3324 dwc2_set_bit(hsotg->regs + DOEPMSK, DOEPMSK_BNAMSK);
ec01f0b2 3325
95c8bc36 3326 dwc2_writel(0, hsotg->regs + DAINTMSK);
308d734e
LM		 3327
3328 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
95c8bc36
AS		 3329 dwc2_readl(hsotg->regs + DIEPCTL0),
3330 dwc2_readl(hsotg->regs + DOEPCTL0));
308d734e
LM		 3331
3332 /* enable in and out endpoint interrupts */
1f91b4cc 3333 dwc2_hsotg_en_gsint(hsotg, GINTSTS_OEPINT | GINTSTS_IEPINT);
308d734e
LM		 3334
3335 /*
3336 * Enable the RXFIFO when in slave mode, as this is how we collect
3337 * the data. In DMA mode, we get events from the FIFO but also
3338 * things we cannot process, so do not use it.
3339 */
3340 if (!using_dma(hsotg))
1f91b4cc 3341 dwc2_hsotg_en_gsint(hsotg, GINTSTS_RXFLVL);
308d734e
LM		 3342
3343 /* Enable interrupts for EP0 in and out */
1f91b4cc
FB		 3344 dwc2_hsotg_ctrl_epint(hsotg, 0, 0, 1);
3345 dwc2_hsotg_ctrl_epint(hsotg, 0, 1, 1);
308d734e 3346
643cc4de 3347 if (!is_usb_reset) {
abd064a1 3348 dwc2_set_bit(hsotg->regs + DCTL, DCTL_PWRONPRGDONE);
643cc4de 3349 udelay(10); /* see openiboot */
abd064a1 3350 dwc2_clear_bit(hsotg->regs + DCTL, DCTL_PWRONPRGDONE);
643cc4de 3351 }
308d734e 3352
95c8bc36 3353 dev_dbg(hsotg->dev, "DCTL=0x%08x\n", dwc2_readl(hsotg->regs + DCTL));
308d734e
LM		 3354
3355 /*
94cb8fd6 3356 * DxEPCTL_USBActEp says RO in manual, but seems to be set by
308d734e
LM		 3357 * writing to the EPCTL register..
3358 */
3359
3360 /* set to read 1 8byte packet */
95c8bc36 3361 dwc2_writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
47a1685f 3362 DXEPTSIZ_XFERSIZE(8), hsotg->regs + DOEPTSIZ0);
308d734e 3363
95c8bc36 3364 dwc2_writel(dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) |
47a1685f
DN		 3365 DXEPCTL_CNAK | DXEPCTL_EPENA |
3366 DXEPCTL_USBACTEP,
94cb8fd6 3367 hsotg->regs + DOEPCTL0);
308d734e
LM		 3368
3369 /* enable, but don't activate EP0in */
95c8bc36 3370 dwc2_writel(dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) |
47a1685f 3371 DXEPCTL_USBACTEP, hsotg->regs + DIEPCTL0);
308d734e 3372
308d734e 3373 /* clear global NAKs */
643cc4de
GH		 3374 val = DCTL_CGOUTNAK | DCTL_CGNPINNAK;
3375 if (!is_usb_reset)
3376 val |= DCTL_SFTDISCON;
abd064a1 3377 dwc2_set_bit(hsotg->regs + DCTL, val);
308d734e 3378
21b03405
SA		 3379 /* configure the core to support LPM */
3380 dwc2_gadget_init_lpm(hsotg);
3381
308d734e
LM		 3382 /* must be at-least 3ms to allow bus to see disconnect */
3383 mdelay(3);
3384
065d3931 3385 hsotg->lx_state = DWC2_L0;
755d7395
VM		 3386
3387 dwc2_hsotg_enqueue_setup(hsotg);
3388
3389 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
3390 dwc2_readl(hsotg->regs + DIEPCTL0),
3391 dwc2_readl(hsotg->regs + DOEPCTL0));
ad38dc5d
MS		 3392}
3393
1f91b4cc 3394static void dwc2_hsotg_core_disconnect(struct dwc2_hsotg *hsotg)
ad38dc5d
MS		 3395{
3396 /* set the soft-disconnect bit */
abd064a1 3397 dwc2_set_bit(hsotg->regs + DCTL, DCTL_SFTDISCON);
ad38dc5d 3398}
ac3c81f3 3399
1f91b4cc 3400void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg)
ad38dc5d 3401{
308d734e 3402 /* remove the soft-disconnect and let's go */
abd064a1 3403 dwc2_clear_bit(hsotg->regs + DCTL, DCTL_SFTDISCON);
308d734e
LM		 3404}
3405
381fc8f8
VM		 3406/**
3407 * dwc2_gadget_handle_incomplete_isoc_in - handle incomplete ISO IN Interrupt.
3408 * @hsotg: The device state:
3409 *
3410 * This interrupt indicates one of the following conditions occurred while
3411 * transmitting an ISOC transaction.
3412 * - Corrupted IN Token for ISOC EP.
3413 * - Packet not complete in FIFO.
3414 *
3415 * The following actions will be taken:
3416 * - Determine the EP
3417 * - Disable EP; when 'Endpoint Disabled' interrupt is received Flush FIFO
3418 */
3419static void dwc2_gadget_handle_incomplete_isoc_in(struct dwc2_hsotg *hsotg)
3420{
3421 struct dwc2_hsotg_ep *hs_ep;
3422 u32 epctrl;
1b4977c7 3423 u32 daintmsk;
381fc8f8
VM		 3424 u32 idx;
3425
3426 dev_dbg(hsotg->dev, "Incomplete isoc in interrupt received:\n");
3427
1b4977c7
RK		 3428 daintmsk = dwc2_readl(hsotg->regs + DAINTMSK);
3429
381fc8f8
VM		 3430 for (idx = 1; idx <= hsotg->num_of_eps; idx++) {
3431 hs_ep = hsotg->eps_in[idx];
1b4977c7
RK		 3432 /* Proceed only unmasked ISOC EPs */
3433 if (!hs_ep->isochronous || (BIT(idx) & ~daintmsk))
3434 continue;
3435
381fc8f8 3436 epctrl = dwc2_readl(hsotg->regs + DIEPCTL(idx));
1b4977c7 3437 if ((epctrl & DXEPCTL_EPENA) &&
381fc8f8
VM		 3438 dwc2_gadget_target_frame_elapsed(hs_ep)) {
3439 epctrl |= DXEPCTL_SNAK;
3440 epctrl |= DXEPCTL_EPDIS;
3441 dwc2_writel(epctrl, hsotg->regs + DIEPCTL(idx));
3442 }
3443 }
3444
3445 /* Clear interrupt */
3446 dwc2_writel(GINTSTS_INCOMPL_SOIN, hsotg->regs + GINTSTS);
3447}
3448
3449/**
3450 * dwc2_gadget_handle_incomplete_isoc_out - handle incomplete ISO OUT Interrupt
3451 * @hsotg: The device state:
3452 *
3453 * This interrupt indicates one of the following conditions occurred while
3454 * transmitting an ISOC transaction.
3455 * - Corrupted OUT Token for ISOC EP.
3456 * - Packet not complete in FIFO.
3457 *
3458 * The following actions will be taken:
3459 * - Determine the EP
3460 * - Set DCTL_SGOUTNAK and unmask GOUTNAKEFF if target frame elapsed.
3461 */
3462static void dwc2_gadget_handle_incomplete_isoc_out(struct dwc2_hsotg *hsotg)
3463{
3464 u32 gintsts;
3465 u32 gintmsk;
689efb26 3466 u32 daintmsk;
381fc8f8
VM		 3467 u32 epctrl;
3468 struct dwc2_hsotg_ep *hs_ep;
3469 int idx;
3470
3471 dev_dbg(hsotg->dev, "%s: GINTSTS_INCOMPL_SOOUT\n", __func__);
3472
689efb26
RK		 3473 daintmsk = dwc2_readl(hsotg->regs + DAINTMSK);
3474 daintmsk >>= DAINT_OUTEP_SHIFT;
3475
381fc8f8
VM		 3476 for (idx = 1; idx <= hsotg->num_of_eps; idx++) {
3477 hs_ep = hsotg->eps_out[idx];
689efb26
RK		 3478 /* Proceed only unmasked ISOC EPs */
3479 if (!hs_ep->isochronous || (BIT(idx) & ~daintmsk))
3480 continue;
3481
381fc8f8 3482 epctrl = dwc2_readl(hsotg->regs + DOEPCTL(idx));
689efb26 3483 if ((epctrl & DXEPCTL_EPENA) &&
381fc8f8
VM		 3484 dwc2_gadget_target_frame_elapsed(hs_ep)) {
3485 /* Unmask GOUTNAKEFF interrupt */
3486 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
3487 gintmsk |= GINTSTS_GOUTNAKEFF;
3488 dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
3489
3490 gintsts = dwc2_readl(hsotg->regs + GINTSTS);
689efb26 3491 if (!(gintsts & GINTSTS_GOUTNAKEFF)) {
abd064a1 3492 dwc2_set_bit(hsotg->regs + DCTL, DCTL_SGOUTNAK);
689efb26
RK		 3493 break;
3494 }
381fc8f8
VM		 3495 }
3496 }
3497
3498 /* Clear interrupt */
3499 dwc2_writel(GINTSTS_INCOMPL_SOOUT, hsotg->regs + GINTSTS);
3500}
3501
5b7d70c6 3502/**
1f91b4cc 3503 * dwc2_hsotg_irq - handle device interrupt
5b7d70c6
BD		 3504 * @irq: The IRQ number triggered
3505 * @pw: The pw value when registered the handler.
3506 */
1f91b4cc 3507static irqreturn_t dwc2_hsotg_irq(int irq, void *pw)
5b7d70c6 3508{
941fcce4 3509 struct dwc2_hsotg *hsotg = pw;
5b7d70c6
BD		 3510 int retry_count = 8;
3511 u32 gintsts;
3512 u32 gintmsk;
3513
ee3de8d7
VM		 3514 if (!dwc2_is_device_mode(hsotg))
3515 return IRQ_NONE;
3516
5ad1d316 3517 spin_lock(&hsotg->lock);
5b7d70c6 3518irq_retry:
95c8bc36
AS		 3519 gintsts = dwc2_readl(hsotg->regs + GINTSTS);
3520 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
5b7d70c6
BD		 3521
3522 dev_dbg(hsotg->dev, "%s: %08x %08x (%08x) retry %d\n",
3523 __func__, gintsts, gintsts & gintmsk, gintmsk, retry_count);
3524
3525 gintsts &= gintmsk;
3526
8fc37b82
MYK		 3527 if (gintsts & GINTSTS_RESETDET) {
3528 dev_dbg(hsotg->dev, "%s: USBRstDet\n", __func__);
3529
3530 dwc2_writel(GINTSTS_RESETDET, hsotg->regs + GINTSTS);
3531
3532 /* This event must be used only if controller is suspended */
3533 if (hsotg->lx_state == DWC2_L2) {
41ba9b9b 3534 dwc2_exit_partial_power_down(hsotg, true);
8fc37b82
MYK		 3535 hsotg->lx_state = DWC2_L0;
3536 }
3537 }
3538
3539 if (gintsts & (GINTSTS_USBRST | GINTSTS_RESETDET)) {
8fc37b82
MYK		 3540 u32 usb_status = dwc2_readl(hsotg->regs + GOTGCTL);
3541 u32 connected = hsotg->connected;
3542
3543 dev_dbg(hsotg->dev, "%s: USBRst\n", __func__);
3544 dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n",
3545 dwc2_readl(hsotg->regs + GNPTXSTS));
3546
3547 dwc2_writel(GINTSTS_USBRST, hsotg->regs + GINTSTS);
3548
3549 /* Report disconnection if it is not already done. */
3550 dwc2_hsotg_disconnect(hsotg);
3551
307bc11f 3552 /* Reset device address to zero */
abd064a1 3553 dwc2_clear_bit(hsotg->regs + DCFG, DCFG_DEVADDR_MASK);
307bc11f 3554
8fc37b82
MYK		 3555 if (usb_status & GOTGCTL_BSESVLD && connected)
3556 dwc2_hsotg_core_init_disconnected(hsotg, true);
3557 }
3558
47a1685f 3559 if (gintsts & GINTSTS_ENUMDONE) {
95c8bc36 3560 dwc2_writel(GINTSTS_ENUMDONE, hsotg->regs + GINTSTS);
a3395f0d 3561
1f91b4cc 3562 dwc2_hsotg_irq_enumdone(hsotg);
5b7d70c6
BD		 3563 }
3564
47a1685f 3565 if (gintsts & (GINTSTS_OEPINT | GINTSTS_IEPINT)) {
95c8bc36
AS		 3566 u32 daint = dwc2_readl(hsotg->regs + DAINT);
3567 u32 daintmsk = dwc2_readl(hsotg->regs + DAINTMSK);
7e804650 3568 u32 daint_out, daint_in;
5b7d70c6
BD		 3569 int ep;
3570
7e804650 3571 daint &= daintmsk;
47a1685f
DN		 3572 daint_out = daint >> DAINT_OUTEP_SHIFT;
3573 daint_in = daint & ~(daint_out << DAINT_OUTEP_SHIFT);
7e804650 3574
5b7d70c6
BD		 3575 dev_dbg(hsotg->dev, "%s: daint=%08x\n", __func__, daint);
3576
cec87f1d
MYK		 3577 for (ep = 0; ep < hsotg->num_of_eps && daint_out;
3578 ep++, daint_out >>= 1) {
5b7d70c6 3579 if (daint_out & 1)
1f91b4cc 3580 dwc2_hsotg_epint(hsotg, ep, 0);
5b7d70c6
BD		 3581 }
3582
cec87f1d
MYK		 3583 for (ep = 0; ep < hsotg->num_of_eps && daint_in;
3584 ep++, daint_in >>= 1) {
5b7d70c6 3585 if (daint_in & 1)
1f91b4cc 3586 dwc2_hsotg_epint(hsotg, ep, 1);
5b7d70c6 3587 }
5b7d70c6
BD		 3588 }
3589
5b7d70c6
BD		 3590 /* check both FIFOs */
3591
47a1685f 3592 if (gintsts & GINTSTS_NPTXFEMP) {
5b7d70c6
BD		 3593 dev_dbg(hsotg->dev, "NPTxFEmp\n");
3594
8b9bc460
LM		 3595 /*
3596 * Disable the interrupt to stop it happening again
5b7d70c6 3597 * unless one of these endpoint routines decides that
8b9bc460
LM		 3598 * it needs re-enabling
3599 */
5b7d70c6 3600
1f91b4cc
FB		 3601 dwc2_hsotg_disable_gsint(hsotg, GINTSTS_NPTXFEMP);
3602 dwc2_hsotg_irq_fifoempty(hsotg, false);
5b7d70c6
BD		 3603 }
3604
47a1685f 3605 if (gintsts & GINTSTS_PTXFEMP) {
5b7d70c6
BD		 3606 dev_dbg(hsotg->dev, "PTxFEmp\n");
3607
94cb8fd6 3608 /* See note in GINTSTS_NPTxFEmp */
5b7d70c6 3609
1f91b4cc
FB		 3610 dwc2_hsotg_disable_gsint(hsotg, GINTSTS_PTXFEMP);
3611 dwc2_hsotg_irq_fifoempty(hsotg, true);
5b7d70c6
BD		 3612 }
3613
47a1685f 3614 if (gintsts & GINTSTS_RXFLVL) {
8b9bc460
LM		 3615 /*
3616 * note, since GINTSTS_RxFLvl doubles as FIFO-not-empty,
1f91b4cc 3617 * we need to retry dwc2_hsotg_handle_rx if this is still
8b9bc460
LM		 3618 * set.
3619 */
5b7d70c6 3620
1f91b4cc 3621 dwc2_hsotg_handle_rx(hsotg);
5b7d70c6
BD		 3622 }
3623
47a1685f 3624 if (gintsts & GINTSTS_ERLYSUSP) {
94cb8fd6 3625 dev_dbg(hsotg->dev, "GINTSTS_ErlySusp\n");
95c8bc36 3626 dwc2_writel(GINTSTS_ERLYSUSP, hsotg->regs + GINTSTS);
5b7d70c6
BD		 3627 }
3628
8b9bc460
LM		 3629 /*
3630 * these next two seem to crop-up occasionally causing the core
5b7d70c6 3631 * to shutdown the USB transfer, so try clearing them and logging
8b9bc460
LM		 3632 * the occurrence.
3633 */
5b7d70c6 3634
47a1685f 3635 if (gintsts & GINTSTS_GOUTNAKEFF) {
837e9f00
VM		 3636 u8 idx;
3637 u32 epctrl;
3638 u32 gintmsk;
d8484552 3639 u32 daintmsk;
837e9f00
VM		 3640 struct dwc2_hsotg_ep *hs_ep;
3641
d8484552
RK		 3642 daintmsk = dwc2_readl(hsotg->regs + DAINTMSK);
3643 daintmsk >>= DAINT_OUTEP_SHIFT;
837e9f00
VM		 3644 /* Mask this interrupt */
3645 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
3646 gintmsk &= ~GINTSTS_GOUTNAKEFF;
3647 dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
3648
3649 dev_dbg(hsotg->dev, "GOUTNakEff triggered\n");
3650 for (idx = 1; idx <= hsotg->num_of_eps; idx++) {
3651 hs_ep = hsotg->eps_out[idx];
d8484552
RK		 3652 /* Proceed only unmasked ISOC EPs */
3653 if (!hs_ep->isochronous || (BIT(idx) & ~daintmsk))
3654 continue;
3655
837e9f00
VM		 3656 epctrl = dwc2_readl(hsotg->regs + DOEPCTL(idx));
3657
d8484552 3658 if (epctrl & DXEPCTL_EPENA) {
837e9f00
VM		 3659 epctrl |= DXEPCTL_SNAK;
3660 epctrl |= DXEPCTL_EPDIS;
3661 dwc2_writel(epctrl, hsotg->regs + DOEPCTL(idx));
3662 }
3663 }
a3395f0d 3664
837e9f00 3665 /* This interrupt bit is cleared in DXEPINT_EPDISBLD handler */
5b7d70c6
BD		 3666 }
3667
47a1685f 3668 if (gintsts & GINTSTS_GINNAKEFF) {
5b7d70c6
BD		 3669 dev_info(hsotg->dev, "GINNakEff triggered\n");
3670
abd064a1 3671 dwc2_set_bit(hsotg->regs + DCTL, DCTL_CGNPINNAK);
a3395f0d 3672
1f91b4cc 3673 dwc2_hsotg_dump(hsotg);
5b7d70c6
BD		 3674 }
3675
381fc8f8
VM		 3676 if (gintsts & GINTSTS_INCOMPL_SOIN)
3677 dwc2_gadget_handle_incomplete_isoc_in(hsotg);
ec1f9d9f 3678
381fc8f8
VM		 3679 if (gintsts & GINTSTS_INCOMPL_SOOUT)
3680 dwc2_gadget_handle_incomplete_isoc_out(hsotg);
ec1f9d9f 3681
8b9bc460
LM		 3682 /*
3683 * if we've had fifo events, we should try and go around the
3684 * loop again to see if there's any point in returning yet.
3685 */
5b7d70c6
BD		 3686
3687 if (gintsts & IRQ_RETRY_MASK && --retry_count > 0)
77b6200e 3688 goto irq_retry;
5b7d70c6 3689
5ad1d316
LM		 3690 spin_unlock(&hsotg->lock);
3691
5b7d70c6
BD		 3692 return IRQ_HANDLED;
3693}
3694
a4f82771
VA		 3695static void dwc2_hsotg_ep_stop_xfr(struct dwc2_hsotg *hsotg,
3696 struct dwc2_hsotg_ep *hs_ep)
3697{
3698 u32 epctrl_reg;
3699 u32 epint_reg;
3700
3701 epctrl_reg = hs_ep->dir_in ? DIEPCTL(hs_ep->index) :
3702 DOEPCTL(hs_ep->index);
3703 epint_reg = hs_ep->dir_in ? DIEPINT(hs_ep->index) :
3704 DOEPINT(hs_ep->index);
3705
3706 dev_dbg(hsotg->dev, "%s: stopping transfer on %s\n", __func__,
3707 hs_ep->name);
3708
3709 if (hs_ep->dir_in) {
3710 if (hsotg->dedicated_fifos || hs_ep->periodic) {
abd064a1 3711 dwc2_set_bit(hsotg->regs + epctrl_reg, DXEPCTL_SNAK);
a4f82771
VA		 3712 /* Wait for Nak effect */
3713 if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg,
3714 DXEPINT_INEPNAKEFF, 100))
3715 dev_warn(hsotg->dev,
3716 "%s: timeout DIEPINT.NAKEFF\n",
3717 __func__);
3718 } else {
abd064a1 3719 dwc2_set_bit(hsotg->regs + DCTL, DCTL_SGNPINNAK);
a4f82771
VA		 3720 /* Wait for Nak effect */
3721 if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS,
3722 GINTSTS_GINNAKEFF, 100))
3723 dev_warn(hsotg->dev,
3724 "%s: timeout GINTSTS.GINNAKEFF\n",
3725 __func__);
3726 }
3727 } else {
3728 if (!(dwc2_readl(hsotg->regs + GINTSTS) & GINTSTS_GOUTNAKEFF))
abd064a1 3729 dwc2_set_bit(hsotg->regs + DCTL, DCTL_SGOUTNAK);
a4f82771
VA		 3730
3731 /* Wait for global nak to take effect */
3732 if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS,
3733 GINTSTS_GOUTNAKEFF, 100))
3734 dev_warn(hsotg->dev, "%s: timeout GINTSTS.GOUTNAKEFF\n",
3735 __func__);
3736 }
3737
3738 /* Disable ep */
abd064a1 3739 dwc2_set_bit(hsotg->regs + epctrl_reg, DXEPCTL_EPDIS | DXEPCTL_SNAK);
a4f82771
VA		 3740
3741 /* Wait for ep to be disabled */
3742 if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg, DXEPINT_EPDISBLD, 100))
3743 dev_warn(hsotg->dev,
3744 "%s: timeout DOEPCTL.EPDisable\n", __func__);
3745
3746 /* Clear EPDISBLD interrupt */
abd064a1 3747 dwc2_set_bit(hsotg->regs + epint_reg, DXEPINT_EPDISBLD);
a4f82771
VA		 3748
3749 if (hs_ep->dir_in) {
3750 unsigned short fifo_index;
3751
3752 if (hsotg->dedicated_fifos || hs_ep->periodic)
3753 fifo_index = hs_ep->fifo_index;
3754 else
3755 fifo_index = 0;
3756
3757 /* Flush TX FIFO */
3758 dwc2_flush_tx_fifo(hsotg, fifo_index);
3759
3760 /* Clear Global In NP NAK in Shared FIFO for non periodic ep */
3761 if (!hsotg->dedicated_fifos && !hs_ep->periodic)
abd064a1 3762 dwc2_set_bit(hsotg->regs + DCTL, DCTL_CGNPINNAK);
a4f82771
VA		 3763
3764 } else {
3765 /* Remove global NAKs */
abd064a1 3766 dwc2_set_bit(hsotg->regs + DCTL, DCTL_CGOUTNAK);
a4f82771
VA		 3767 }
3768}
3769
5b7d70c6 3770/**
1f91b4cc 3771 * dwc2_hsotg_ep_enable - enable the given endpoint
5b7d70c6
BD		 3772 * @ep: The USB endpint to configure
3773 * @desc: The USB endpoint descriptor to configure with.
3774 *
3775 * This is called from the USB gadget code's usb_ep_enable().
8b9bc460 3776 */
1f91b4cc 3777static int dwc2_hsotg_ep_enable(struct usb_ep *ep,
9da51974 3778 const struct usb_endpoint_descriptor *desc)
5b7d70c6 3779{
1f91b4cc 3780 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
941fcce4 3781 struct dwc2_hsotg *hsotg = hs_ep->parent;
5b7d70c6 3782 unsigned long flags;
ca4c55ad 3783 unsigned int index = hs_ep->index;
5b7d70c6
BD		 3784 u32 epctrl_reg;
3785 u32 epctrl;
3786 u32 mps;
ee2c40de 3787 u32 mc;
837e9f00 3788 u32 mask;
ca4c55ad
MYK		 3789 unsigned int dir_in;
3790 unsigned int i, val, size;
19c190f9 3791 int ret = 0;
5b7d70c6
BD		 3792
3793 dev_dbg(hsotg->dev,
3794 "%s: ep %s: a 0x%02x, attr 0x%02x, mps 0x%04x, intr %d\n",
3795 __func__, ep->name, desc->bEndpointAddress, desc->bmAttributes,
3796 desc->wMaxPacketSize, desc->bInterval);
3797
3798 /* not to be called for EP0 */
8c3d6092
VA		 3799 if (index == 0) {
3800 dev_err(hsotg->dev, "%s: called for EP 0\n", __func__);
3801 return -EINVAL;
3802 }
5b7d70c6
BD		 3803
3804 dir_in = (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) ? 1 : 0;
3805 if (dir_in != hs_ep->dir_in) {
3806 dev_err(hsotg->dev, "%s: direction mismatch!\n", __func__);
3807 return -EINVAL;
3808 }
3809
29cc8897 3810 mps = usb_endpoint_maxp(desc);
ee2c40de 3811 mc = usb_endpoint_maxp_mult(desc);
5b7d70c6 3812
1f91b4cc 3813 /* note, we handle this here instead of dwc2_hsotg_set_ep_maxpacket */
5b7d70c6 3814
94cb8fd6 3815 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
95c8bc36 3816 epctrl = dwc2_readl(hsotg->regs + epctrl_reg);
5b7d70c6
BD		 3817
3818 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x from 0x%08x\n",
3819 __func__, epctrl, epctrl_reg);
3820
5f54c54b 3821 /* Allocate DMA descriptor chain for non-ctrl endpoints */
9383e084
VM		 3822 if (using_desc_dma(hsotg) && !hs_ep->desc_list) {
3823 hs_ep->desc_list = dmam_alloc_coherent(hsotg->dev,
5f54c54b
VA		 3824 MAX_DMA_DESC_NUM_GENERIC *
3825 sizeof(struct dwc2_dma_desc),
86e881e7 3826 &hs_ep->desc_list_dma, GFP_ATOMIC);
5f54c54b
VA		 3827 if (!hs_ep->desc_list) {
3828 ret = -ENOMEM;
3829 goto error2;
3830 }
3831 }
3832
22258f49 3833 spin_lock_irqsave(&hsotg->lock, flags);
5b7d70c6 3834
47a1685f
DN		 3835 epctrl &= ~(DXEPCTL_EPTYPE_MASK | DXEPCTL_MPS_MASK);
3836 epctrl |= DXEPCTL_MPS(mps);
5b7d70c6 3837
8b9bc460
LM		 3838 /*
3839 * mark the endpoint as active, otherwise the core may ignore
3840 * transactions entirely for this endpoint
3841 */
47a1685f 3842 epctrl |= DXEPCTL_USBACTEP;
5b7d70c6 3843
5b7d70c6 3844 /* update the endpoint state */
ee2c40de 3845 dwc2_hsotg_set_ep_maxpacket(hsotg, hs_ep->index, mps, mc, dir_in);
5b7d70c6
BD		 3846
3847 /* default, set to non-periodic */
1479e841 3848 hs_ep->isochronous = 0;
5b7d70c6 3849 hs_ep->periodic = 0;
a18ed7b0 3850 hs_ep->halted = 0;
1479e841 3851 hs_ep->interval = desc->bInterval;
4fca54aa 3852
5b7d70c6
BD		 3853 switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
3854 case USB_ENDPOINT_XFER_ISOC:
47a1685f
DN		 3855 epctrl |= DXEPCTL_EPTYPE_ISO;
3856 epctrl |= DXEPCTL_SETEVENFR;
1479e841 3857 hs_ep->isochronous = 1;
142bd33f 3858 hs_ep->interval = 1 << (desc->bInterval - 1);
837e9f00 3859 hs_ep->target_frame = TARGET_FRAME_INITIAL;
ab7d2192
VA		 3860 hs_ep->isoc_chain_num = 0;
3861 hs_ep->next_desc = 0;
837e9f00 3862 if (dir_in) {
1479e841 3863 hs_ep->periodic = 1;
837e9f00
VM		 3864 mask = dwc2_readl(hsotg->regs + DIEPMSK);
3865 mask |= DIEPMSK_NAKMSK;
3866 dwc2_writel(mask, hsotg->regs + DIEPMSK);
3867 } else {
3868 mask = dwc2_readl(hsotg->regs + DOEPMSK);
3869 mask |= DOEPMSK_OUTTKNEPDISMSK;
3870 dwc2_writel(mask, hsotg->regs + DOEPMSK);
3871 }
1479e841 3872 break;
5b7d70c6
BD		 3873
3874 case USB_ENDPOINT_XFER_BULK:
47a1685f 3875 epctrl |= DXEPCTL_EPTYPE_BULK;
5b7d70c6
BD		 3876 break;
3877
3878 case USB_ENDPOINT_XFER_INT:
b203d0a2 3879 if (dir_in)
5b7d70c6 3880 hs_ep->periodic = 1;
5b7d70c6 3881
142bd33f
VM		 3882 if (hsotg->gadget.speed == USB_SPEED_HIGH)
3883 hs_ep->interval = 1 << (desc->bInterval - 1);
3884
47a1685f 3885 epctrl |= DXEPCTL_EPTYPE_INTERRUPT;
5b7d70c6
BD		 3886 break;
3887
3888 case USB_ENDPOINT_XFER_CONTROL:
47a1685f 3889 epctrl |= DXEPCTL_EPTYPE_CONTROL;
5b7d70c6
BD		 3890 break;
3891 }
3892
8b9bc460
LM		 3893 /*
3894 * if the hardware has dedicated fifos, we must give each IN EP
10aebc77
BD		 3895 * a unique tx-fifo even if it is non-periodic.
3896 */
21f3bb52 3897 if (dir_in && hsotg->dedicated_fifos) {
ca4c55ad
MYK		 3898 u32 fifo_index = 0;
3899 u32 fifo_size = UINT_MAX;
9da51974
JY		 3900
3901 size = hs_ep->ep.maxpacket * hs_ep->mc;
5f2196bd 3902 for (i = 1; i < hsotg->num_of_eps; ++i) {
9da51974 3903 if (hsotg->fifo_map & (1 << i))
b203d0a2 3904 continue;
95c8bc36 3905 val = dwc2_readl(hsotg->regs + DPTXFSIZN(i));
9da51974 3906 val = (val >> FIFOSIZE_DEPTH_SHIFT) * 4;
b203d0a2
RB		 3907 if (val < size)
3908 continue;
ca4c55ad
MYK		 3909 /* Search for smallest acceptable fifo */
3910 if (val < fifo_size) {
3911 fifo_size = val;
3912 fifo_index = i;
3913 }
b203d0a2 3914 }
ca4c55ad 3915 if (!fifo_index) {
5f2196bd
MYK		 3916 dev_err(hsotg->dev,
3917 "%s: No suitable fifo found\n", __func__);
b585a48b 3918 ret = -ENOMEM;
5f54c54b 3919 goto error1;
b585a48b 3920 }
ca4c55ad
MYK		 3921 hsotg->fifo_map |= 1 << fifo_index;
3922 epctrl |= DXEPCTL_TXFNUM(fifo_index);
3923 hs_ep->fifo_index = fifo_index;
3924 hs_ep->fifo_size = fifo_size;
b203d0a2 3925 }
10aebc77 3926
5b7d70c6 3927 /* for non control endpoints, set PID to D0 */
837e9f00 3928 if (index && !hs_ep->isochronous)
47a1685f 3929 epctrl |= DXEPCTL_SETD0PID;
5b7d70c6
BD		 3930
3931 dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n",
3932 __func__, epctrl);
3933
95c8bc36 3934 dwc2_writel(epctrl, hsotg->regs + epctrl_reg);
5b7d70c6 3935 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x\n",
95c8bc36 3936 __func__, dwc2_readl(hsotg->regs + epctrl_reg));
5b7d70c6
BD		 3937
3938 /* enable the endpoint interrupt */
1f91b4cc 3939 dwc2_hsotg_ctrl_epint(hsotg, index, dir_in, 1);
5b7d70c6 3940
5f54c54b 3941error1:
22258f49 3942 spin_unlock_irqrestore(&hsotg->lock, flags);
5f54c54b
VA		 3943
3944error2:
3945 if (ret && using_desc_dma(hsotg) && hs_ep->desc_list) {
9383e084 3946 dmam_free_coherent(hsotg->dev, MAX_DMA_DESC_NUM_GENERIC *
5f54c54b
VA		 3947 sizeof(struct dwc2_dma_desc),
3948 hs_ep->desc_list, hs_ep->desc_list_dma);
3949 hs_ep->desc_list = NULL;
3950 }
3951
19c190f9 3952 return ret;
5b7d70c6
BD		 3953}
3954
8b9bc460 3955/**
1f91b4cc 3956 * dwc2_hsotg_ep_disable - disable given endpoint
8b9bc460
LM		 3957 * @ep: The endpoint to disable.
3958 */
1f91b4cc 3959static int dwc2_hsotg_ep_disable(struct usb_ep *ep)
5b7d70c6 3960{
1f91b4cc 3961 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
941fcce4 3962 struct dwc2_hsotg *hsotg = hs_ep->parent;
5b7d70c6
BD		 3963 int dir_in = hs_ep->dir_in;
3964 int index = hs_ep->index;
3965 unsigned long flags;
3966 u32 epctrl_reg;
3967 u32 ctrl;
3968
1e011293 3969 dev_dbg(hsotg->dev, "%s(ep %p)\n", __func__, ep);
5b7d70c6 3970
c6f5c050 3971 if (ep == &hsotg->eps_out[0]->ep) {
5b7d70c6
BD		 3972 dev_err(hsotg->dev, "%s: called for ep0\n", __func__);
3973 return -EINVAL;
9b481092
JS		 3974 }
3975
3976 if (hsotg->op_state != OTG_STATE_B_PERIPHERAL) {
3977 dev_err(hsotg->dev, "%s: called in host mode?\n", __func__);
3978 return -EINVAL;
5b7d70c6
BD		 3979 }
3980
94cb8fd6 3981 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
5b7d70c6 3982
5ad1d316 3983 spin_lock_irqsave(&hsotg->lock, flags);
5b7d70c6 3984
95c8bc36 3985 ctrl = dwc2_readl(hsotg->regs + epctrl_reg);
a4f82771
VA		 3986
3987 if (ctrl & DXEPCTL_EPENA)
3988 dwc2_hsotg_ep_stop_xfr(hsotg, hs_ep);
3989
47a1685f
DN		 3990 ctrl &= ~DXEPCTL_EPENA;
3991 ctrl &= ~DXEPCTL_USBACTEP;
3992 ctrl |= DXEPCTL_SNAK;
5b7d70c6
BD		 3993
3994 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
95c8bc36 3995 dwc2_writel(ctrl, hsotg->regs + epctrl_reg);
5b7d70c6
BD		 3996
3997 /* disable endpoint interrupts */
1f91b4cc 3998 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 0);
5b7d70c6 3999
1141ea01
MYK		 4000 /* terminate all requests with shutdown */
4001 kill_all_requests(hsotg, hs_ep, -ESHUTDOWN);
4002
1c07b20e
RB		 4003 hsotg->fifo_map &= ~(1 << hs_ep->fifo_index);
4004 hs_ep->fifo_index = 0;
4005 hs_ep->fifo_size = 0;
4006
22258f49 4007 spin_unlock_irqrestore(&hsotg->lock, flags);
5b7d70c6
BD		 4008 return 0;
4009}
4010
4011/**
4012 * on_list - check request is on the given endpoint
4013 * @ep: The endpoint to check.
4014 * @test: The request to test if it is on the endpoint.
8b9bc460 4015 */
1f91b4cc 4016static bool on_list(struct dwc2_hsotg_ep *ep, struct dwc2_hsotg_req *test)
5b7d70c6 4017{
1f91b4cc 4018 struct dwc2_hsotg_req *req, *treq;
5b7d70c6
BD		 4019
4020 list_for_each_entry_safe(req, treq, &ep->queue, queue) {
4021 if (req == test)
4022 return true;
4023 }
4024
4025 return false;
4026}
4027
8b9bc460 4028/**
1f91b4cc 4029 * dwc2_hsotg_ep_dequeue - dequeue given endpoint
8b9bc460
LM		 4030 * @ep: The endpoint to dequeue.
4031 * @req: The request to be removed from a queue.
4032 */
1f91b4cc 4033static int dwc2_hsotg_ep_dequeue(struct usb_ep *ep, struct usb_request *req)
5b7d70c6 4034{
1f91b4cc
FB		 4035 struct dwc2_hsotg_req *hs_req = our_req(req);
4036 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
941fcce4 4037 struct dwc2_hsotg *hs = hs_ep->parent;
5b7d70c6
BD		 4038 unsigned long flags;
4039
1e011293 4040 dev_dbg(hs->dev, "ep_dequeue(%p,%p)\n", ep, req);
5b7d70c6 4041
22258f49 4042 spin_lock_irqsave(&hs->lock, flags);
5b7d70c6
BD		 4043
4044 if (!on_list(hs_ep, hs_req)) {
22258f49 4045 spin_unlock_irqrestore(&hs->lock, flags);
5b7d70c6
BD		 4046 return -EINVAL;
4047 }
4048
c524dd5f
MYK		 4049 /* Dequeue already started request */
4050 if (req == &hs_ep->req->req)
4051 dwc2_hsotg_ep_stop_xfr(hs, hs_ep);
4052
1f91b4cc 4053 dwc2_hsotg_complete_request(hs, hs_ep, hs_req, -ECONNRESET);
22258f49 4054 spin_unlock_irqrestore(&hs->lock, flags);
5b7d70c6
BD		 4055
4056 return 0;
4057}
4058
8b9bc460 4059/**
1f91b4cc 4060 * dwc2_hsotg_ep_sethalt - set halt on a given endpoint
8b9bc460
LM		 4061 * @ep: The endpoint to set halt.
4062 * @value: Set or unset the halt.
51da43b5
VA		 4063 * @now: If true, stall the endpoint now. Otherwise return -EAGAIN if
4064 * the endpoint is busy processing requests.
4065 *
4066 * We need to stall the endpoint immediately if request comes from set_feature
4067 * protocol command handler.
8b9bc460 4068 */
51da43b5 4069static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now)
5b7d70c6 4070{
1f91b4cc 4071 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
941fcce4 4072 struct dwc2_hsotg *hs = hs_ep->parent;
5b7d70c6 4073 int index = hs_ep->index;
5b7d70c6
BD		 4074 u32 epreg;
4075 u32 epctl;
9c39ddc6 4076 u32 xfertype;
5b7d70c6
BD		 4077
4078 dev_info(hs->dev, "%s(ep %p %s, %d)\n", __func__, ep, ep->name, value);
4079
c9f721b2
RB		 4080 if (index == 0) {
4081 if (value)
1f91b4cc 4082 dwc2_hsotg_stall_ep0(hs);
c9f721b2
RB		 4083 else
4084 dev_warn(hs->dev,
4085 "%s: can't clear halt on ep0\n", __func__);
4086 return 0;
4087 }
4088
15186f10
VA		 4089 if (hs_ep->isochronous) {
4090 dev_err(hs->dev, "%s is Isochronous Endpoint\n", ep->name);
4091 return -EINVAL;
4092 }
4093
51da43b5
VA		 4094 if (!now && value && !list_empty(&hs_ep->queue)) {
4095 dev_dbg(hs->dev, "%s request is pending, cannot halt\n",
4096 ep->name);
4097 return -EAGAIN;
4098 }
4099
c6f5c050
MYK		 4100 if (hs_ep->dir_in) {
4101 epreg = DIEPCTL(index);
95c8bc36 4102 epctl = dwc2_readl(hs->regs + epreg);
c6f5c050
MYK		 4103
4104 if (value) {
5a350d53 4105 epctl |= DXEPCTL_STALL | DXEPCTL_SNAK;
c6f5c050
MYK		 4106 if (epctl & DXEPCTL_EPENA)
4107 epctl |= DXEPCTL_EPDIS;
4108 } else {
4109 epctl &= ~DXEPCTL_STALL;
4110 xfertype = epctl & DXEPCTL_EPTYPE_MASK;
4111 if (xfertype == DXEPCTL_EPTYPE_BULK ||
9da51974 4112 xfertype == DXEPCTL_EPTYPE_INTERRUPT)
77b6200e 4113 epctl |= DXEPCTL_SETD0PID;
c6f5c050 4114 }
95c8bc36 4115 dwc2_writel(epctl, hs->regs + epreg);
9c39ddc6 4116 } else {
c6f5c050 4117 epreg = DOEPCTL(index);
95c8bc36 4118 epctl = dwc2_readl(hs->regs + epreg);
5b7d70c6 4119
34c0887f 4120 if (value) {
c6f5c050 4121 epctl |= DXEPCTL_STALL;
34c0887f 4122 } else {
c6f5c050
MYK		 4123 epctl &= ~DXEPCTL_STALL;
4124 xfertype = epctl & DXEPCTL_EPTYPE_MASK;
4125 if (xfertype == DXEPCTL_EPTYPE_BULK ||
9da51974 4126 xfertype == DXEPCTL_EPTYPE_INTERRUPT)
77b6200e 4127 epctl |= DXEPCTL_SETD0PID;
c6f5c050 4128 }
95c8bc36 4129 dwc2_writel(epctl, hs->regs + epreg);
9c39ddc6 4130 }
5b7d70c6 4131
a18ed7b0
RB		 4132 hs_ep->halted = value;
4133
5b7d70c6
BD		 4134 return 0;
4135}
4136
5ad1d316 4137/**
1f91b4cc 4138 * dwc2_hsotg_ep_sethalt_lock - set halt on a given endpoint with lock held
5ad1d316
LM		 4139 * @ep: The endpoint to set halt.
4140 * @value: Set or unset the halt.
4141 */
1f91b4cc 4142static int dwc2_hsotg_ep_sethalt_lock(struct usb_ep *ep, int value)
5ad1d316 4143{
1f91b4cc 4144 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
941fcce4 4145 struct dwc2_hsotg *hs = hs_ep->parent;
5ad1d316
LM		 4146 unsigned long flags = 0;
4147 int ret = 0;
4148
4149 spin_lock_irqsave(&hs->lock, flags);
51da43b5 4150 ret = dwc2_hsotg_ep_sethalt(ep, value, false);
5ad1d316
LM		 4151 spin_unlock_irqrestore(&hs->lock, flags);
4152
4153 return ret;
4154}
4155
ebce561a 4156static const struct usb_ep_ops dwc2_hsotg_ep_ops = {
1f91b4cc
FB		 4157 .enable = dwc2_hsotg_ep_enable,
4158 .disable = dwc2_hsotg_ep_disable,
4159 .alloc_request = dwc2_hsotg_ep_alloc_request,
4160 .free_request = dwc2_hsotg_ep_free_request,
4161 .queue = dwc2_hsotg_ep_queue_lock,
4162 .dequeue = dwc2_hsotg_ep_dequeue,
4163 .set_halt = dwc2_hsotg_ep_sethalt_lock,
25985edc 4164 /* note, don't believe we have any call for the fifo routines */
5b7d70c6
BD		 4165};
4166
8b9bc460 4167/**
9da51974 4168 * dwc2_hsotg_init - initialize the usb core
8b9bc460
LM		 4169 * @hsotg: The driver state
4170 */
1f91b4cc 4171static void dwc2_hsotg_init(struct dwc2_hsotg *hsotg)
b3f489b2 4172{
fa4a8d72 4173 u32 trdtim;
ecd9a7ad 4174 u32 usbcfg;
b3f489b2
LM		 4175 /* unmask subset of endpoint interrupts */
4176
95c8bc36
AS		 4177 dwc2_writel(DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK |
4178 DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK,
4179 hsotg->regs + DIEPMSK);
b3f489b2 4180
95c8bc36
AS		 4181 dwc2_writel(DOEPMSK_SETUPMSK | DOEPMSK_AHBERRMSK |
4182 DOEPMSK_EPDISBLDMSK | DOEPMSK_XFERCOMPLMSK,
4183 hsotg->regs + DOEPMSK);
b3f489b2 4184
95c8bc36 4185 dwc2_writel(0, hsotg->regs + DAINTMSK);
b3f489b2
LM		 4186
4187 /* Be in disconnected state until gadget is registered */
abd064a1 4188 dwc2_set_bit(hsotg->regs + DCTL, DCTL_SFTDISCON);
b3f489b2 4189
b3f489b2
LM		 4190 /* setup fifos */
4191
4192 dev_dbg(hsotg->dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
95c8bc36
AS		 4193 dwc2_readl(hsotg->regs + GRXFSIZ),
4194 dwc2_readl(hsotg->regs + GNPTXFSIZ));
b3f489b2 4195
1f91b4cc 4196 dwc2_hsotg_init_fifo(hsotg);
b3f489b2 4197
ecd9a7ad
PR		 4198 /* keep other bits untouched (so e.g. forced modes are not lost) */
4199 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
4200 usbcfg &= ~(GUSBCFG_TOUTCAL_MASK | GUSBCFG_PHYIF16 | GUSBCFG_SRPCAP |
ca02954a 4201 GUSBCFG_HNPCAP | GUSBCFG_USBTRDTIM_MASK);
ecd9a7ad 4202
b3f489b2 4203 /* set the PLL on, remove the HNP/SRP and set the PHY */
fa4a8d72 4204 trdtim = (hsotg->phyif == GUSBCFG_PHYIF8) ? 9 : 5;
ecd9a7ad
PR		 4205 usbcfg |= hsotg->phyif | GUSBCFG_TOUTCAL(7) |
4206 (trdtim << GUSBCFG_USBTRDTIM_SHIFT);
4207 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
b3f489b2 4208
f5090044 4209 if (using_dma(hsotg))
abd064a1 4210 dwc2_set_bit(hsotg->regs + GAHBCFG, GAHBCFG_DMA_EN);
b3f489b2
LM		 4211}
4212
8b9bc460 4213/**
1f91b4cc 4214 * dwc2_hsotg_udc_start - prepare the udc for work
8b9bc460
LM		 4215 * @gadget: The usb gadget state
4216 * @driver: The usb gadget driver
4217 *
4218 * Perform initialization to prepare udc device and driver
4219 * to work.
4220 */
1f91b4cc 4221static int dwc2_hsotg_udc_start(struct usb_gadget *gadget,
9da51974 4222 struct usb_gadget_driver *driver)
5b7d70c6 4223{
941fcce4 4224 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
5b9451f8 4225 unsigned long flags;
5b7d70c6
BD		 4226 int ret;
4227
4228 if (!hsotg) {
a023da33 4229 pr_err("%s: called with no device\n", __func__);
5b7d70c6
BD		 4230 return -ENODEV;
4231 }
4232
4233 if (!driver) {
4234 dev_err(hsotg->dev, "%s: no driver\n", __func__);
4235 return -EINVAL;
4236 }
4237
7177aed4 4238 if (driver->max_speed < USB_SPEED_FULL)
5b7d70c6 4239 dev_err(hsotg->dev, "%s: bad speed\n", __func__);
5b7d70c6 4240
f65f0f10 4241 if (!driver->setup) {
5b7d70c6
BD		 4242 dev_err(hsotg->dev, "%s: missing entry points\n", __func__);
4243 return -EINVAL;
4244 }
4245
4246 WARN_ON(hsotg->driver);
4247
4248 driver->driver.bus = NULL;
4249 hsotg->driver = driver;
7d7b2292 4250 hsotg->gadget.dev.of_node = hsotg->dev->of_node;
5b7d70c6
BD		 4251 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
4252
09a75e85
MS		 4253 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) {
4254 ret = dwc2_lowlevel_hw_enable(hsotg);
4255 if (ret)
4256 goto err;
5b7d70c6
BD		 4257 }
4258
f6c01592
GH		 4259 if (!IS_ERR_OR_NULL(hsotg->uphy))
4260 otg_set_peripheral(hsotg->uphy->otg, &hsotg->gadget);
c816c47f 4261
5b9451f8 4262 spin_lock_irqsave(&hsotg->lock, flags);
d0f0ac56
JY		 4263 if (dwc2_hw_is_device(hsotg)) {
4264 dwc2_hsotg_init(hsotg);
4265 dwc2_hsotg_core_init_disconnected(hsotg, false);
4266 }
4267
dc6e69e6 4268 hsotg->enabled = 0;
5b9451f8
MS		 4269 spin_unlock_irqrestore(&hsotg->lock, flags);
4270
5b7d70c6 4271 dev_info(hsotg->dev, "bound driver %s\n", driver->driver.name);
5b9451f8 4272
5b7d70c6
BD		 4273 return 0;
4274
4275err:
4276 hsotg->driver = NULL;
5b7d70c6
BD		 4277 return ret;
4278}
4279
8b9bc460 4280/**
1f91b4cc 4281 * dwc2_hsotg_udc_stop - stop the udc
8b9bc460
LM		 4282 * @gadget: The usb gadget state
4283 * @driver: The usb gadget driver
4284 *
4285 * Stop udc hw block and stay tunned for future transmissions
4286 */
1f91b4cc 4287static int dwc2_hsotg_udc_stop(struct usb_gadget *gadget)
5b7d70c6 4288{
941fcce4 4289 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
2b19a52c 4290 unsigned long flags = 0;
5b7d70c6
BD		 4291 int ep;
4292
4293 if (!hsotg)
4294 return -ENODEV;
4295
5b7d70c6 4296 /* all endpoints should be shutdown */
c6f5c050
MYK		 4297 for (ep = 1; ep < hsotg->num_of_eps; ep++) {
4298 if (hsotg->eps_in[ep])
1f91b4cc 4299 dwc2_hsotg_ep_disable(&hsotg->eps_in[ep]->ep);
c6f5c050 4300 if (hsotg->eps_out[ep])
1f91b4cc 4301 dwc2_hsotg_ep_disable(&hsotg->eps_out[ep]->ep);
c6f5c050 4302 }
5b7d70c6 4303
2b19a52c
LM		 4304 spin_lock_irqsave(&hsotg->lock, flags);
4305
32805c35 4306 hsotg->driver = NULL;
5b7d70c6 4307 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
dc6e69e6 4308 hsotg->enabled = 0;
5b7d70c6 4309
2b19a52c
LM		 4310 spin_unlock_irqrestore(&hsotg->lock, flags);
4311
f6c01592
GH		 4312 if (!IS_ERR_OR_NULL(hsotg->uphy))
4313 otg_set_peripheral(hsotg->uphy->otg, NULL);
c816c47f 4314
09a75e85
MS		 4315 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
4316 dwc2_lowlevel_hw_disable(hsotg);
5b7d70c6
BD		 4317
4318 return 0;
4319}
5b7d70c6 4320
8b9bc460 4321/**
1f91b4cc 4322 * dwc2_hsotg_gadget_getframe - read the frame number
8b9bc460
LM		 4323 * @gadget: The usb gadget state
4324 *
4325 * Read the {micro} frame number
4326 */
1f91b4cc 4327static int dwc2_hsotg_gadget_getframe(struct usb_gadget *gadget)
5b7d70c6 4328{
1f91b4cc 4329 return dwc2_hsotg_read_frameno(to_hsotg(gadget));
5b7d70c6
BD		 4330}
4331
a188b689 4332/**
1f91b4cc 4333 * dwc2_hsotg_pullup - connect/disconnect the USB PHY
a188b689
LM		 4334 * @gadget: The usb gadget state
4335 * @is_on: Current state of the USB PHY
4336 *
4337 * Connect/Disconnect the USB PHY pullup
4338 */
1f91b4cc 4339static int dwc2_hsotg_pullup(struct usb_gadget *gadget, int is_on)
a188b689 4340{
941fcce4 4341 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
a188b689
LM		 4342 unsigned long flags = 0;
4343
77ba9119 4344 dev_dbg(hsotg->dev, "%s: is_on: %d op_state: %d\n", __func__, is_on,
9da51974 4345 hsotg->op_state);
77ba9119
GH		 4346
4347 /* Don't modify pullup state while in host mode */
4348 if (hsotg->op_state != OTG_STATE_B_PERIPHERAL) {
4349 hsotg->enabled = is_on;
4350 return 0;
4351 }
a188b689
LM		 4352
4353 spin_lock_irqsave(&hsotg->lock, flags);
4354 if (is_on) {
dc6e69e6 4355 hsotg->enabled = 1;
1f91b4cc 4356 dwc2_hsotg_core_init_disconnected(hsotg, false);
66e77a24
RK		 4357 /* Enable ACG feature in device mode,if supported */
4358 dwc2_enable_acg(hsotg);
1f91b4cc 4359 dwc2_hsotg_core_connect(hsotg);
a188b689 4360 } else {
1f91b4cc
FB		 4361 dwc2_hsotg_core_disconnect(hsotg);
4362 dwc2_hsotg_disconnect(hsotg);
dc6e69e6 4363 hsotg->enabled = 0;
a188b689
LM		 4364 }
4365
4366 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
4367 spin_unlock_irqrestore(&hsotg->lock, flags);
4368
4369 return 0;
4370}
4371
1f91b4cc 4372static int dwc2_hsotg_vbus_session(struct usb_gadget *gadget, int is_active)
83d98223
GH		 4373{
4374 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4375 unsigned long flags;
4376
4377 dev_dbg(hsotg->dev, "%s: is_active: %d\n", __func__, is_active);
4378 spin_lock_irqsave(&hsotg->lock, flags);
4379
61f7223b 4380 /*
41ba9b9b 4381 * If controller is hibernated, it must exit from power_down
61f7223b
GH		 4382 * before being initialized / de-initialized
4383 */
4384 if (hsotg->lx_state == DWC2_L2)
41ba9b9b 4385 dwc2_exit_partial_power_down(hsotg, false);
61f7223b 4386
83d98223 4387 if (is_active) {
cd0e641c 4388 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
065d3931 4389
1f91b4cc 4390 dwc2_hsotg_core_init_disconnected(hsotg, false);
66e77a24
RK		 4391 if (hsotg->enabled) {
4392 /* Enable ACG feature in device mode,if supported */
4393 dwc2_enable_acg(hsotg);
1f91b4cc 4394 dwc2_hsotg_core_connect(hsotg);
66e77a24 4395 }
83d98223 4396 } else {
1f91b4cc
FB		 4397 dwc2_hsotg_core_disconnect(hsotg);
4398 dwc2_hsotg_disconnect(hsotg);
83d98223
GH		 4399 }
4400
4401 spin_unlock_irqrestore(&hsotg->lock, flags);
4402 return 0;
4403}
4404
596d696a 4405/**
1f91b4cc 4406 * dwc2_hsotg_vbus_draw - report bMaxPower field
596d696a
GH		 4407 * @gadget: The usb gadget state
4408 * @mA: Amount of current
4409 *
4410 * Report how much power the device may consume to the phy.
4411 */
9da51974 4412static int dwc2_hsotg_vbus_draw(struct usb_gadget *gadget, unsigned int mA)
596d696a
GH		 4413{
4414 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4415
4416 if (IS_ERR_OR_NULL(hsotg->uphy))
4417 return -ENOTSUPP;
4418 return usb_phy_set_power(hsotg->uphy, mA);
4419}
4420
1f91b4cc
FB		 4421static const struct usb_gadget_ops dwc2_hsotg_gadget_ops = {
4422 .get_frame = dwc2_hsotg_gadget_getframe,
4423 .udc_start = dwc2_hsotg_udc_start,
4424 .udc_stop = dwc2_hsotg_udc_stop,
4425 .pullup = dwc2_hsotg_pullup,
4426 .vbus_session = dwc2_hsotg_vbus_session,
4427 .vbus_draw = dwc2_hsotg_vbus_draw,
5b7d70c6
BD		 4428};
4429
4430/**
1f91b4cc 4431 * dwc2_hsotg_initep - initialise a single endpoint
5b7d70c6
BD		 4432 * @hsotg: The device state.
4433 * @hs_ep: The endpoint to be initialised.
4434 * @epnum: The endpoint number
4435 *
4436 * Initialise the given endpoint (as part of the probe and device state
4437 * creation) to give to the gadget driver. Setup the endpoint name, any
4438 * direction information and other state that may be required.
4439 */
1f91b4cc 4440static void dwc2_hsotg_initep(struct dwc2_hsotg *hsotg,
9da51974 4441 struct dwc2_hsotg_ep *hs_ep,
c6f5c050
MYK		 4442 int epnum,
4443 bool dir_in)
5b7d70c6 4444{
5b7d70c6
BD		 4445 char *dir;
4446
4447 if (epnum == 0)
4448 dir = "";
c6f5c050 4449 else if (dir_in)
5b7d70c6 4450 dir = "in";
c6f5c050
MYK		 4451 else
4452 dir = "out";
5b7d70c6 4453
c6f5c050 4454 hs_ep->dir_in = dir_in;
5b7d70c6
BD		 4455 hs_ep->index = epnum;
4456
4457 snprintf(hs_ep->name, sizeof(hs_ep->name), "ep%d%s", epnum, dir);
4458
4459 INIT_LIST_HEAD(&hs_ep->queue);
4460 INIT_LIST_HEAD(&hs_ep->ep.ep_list);
4461
5b7d70c6
BD		 4462 /* add to the list of endpoints known by the gadget driver */
4463 if (epnum)
4464 list_add_tail(&hs_ep->ep.ep_list, &hsotg->gadget.ep_list);
4465
4466 hs_ep->parent = hsotg;
4467 hs_ep->ep.name = hs_ep->name;
38e9002b
VM		 4468
4469 if (hsotg->params.speed == DWC2_SPEED_PARAM_LOW)
4470 usb_ep_set_maxpacket_limit(&hs_ep->ep, 8);
4471 else
4472 usb_ep_set_maxpacket_limit(&hs_ep->ep,
4473 epnum ? 1024 : EP0_MPS_LIMIT);
1f91b4cc 4474 hs_ep->ep.ops = &dwc2_hsotg_ep_ops;
5b7d70c6 4475
2954522f
RB		 4476 if (epnum == 0) {
4477 hs_ep->ep.caps.type_control = true;
4478 } else {
38e9002b
VM		 4479 if (hsotg->params.speed != DWC2_SPEED_PARAM_LOW) {
4480 hs_ep->ep.caps.type_iso = true;
4481 hs_ep->ep.caps.type_bulk = true;
4482 }
2954522f
RB		 4483 hs_ep->ep.caps.type_int = true;
4484 }
4485
4486 if (dir_in)
4487 hs_ep->ep.caps.dir_in = true;
4488 else
4489 hs_ep->ep.caps.dir_out = true;
4490
8b9bc460
LM		 4491 /*
4492 * if we're using dma, we need to set the next-endpoint pointer
5b7d70c6
BD		 4493 * to be something valid.
4494 */
4495
4496 if (using_dma(hsotg)) {
47a1685f 4497 u32 next = DXEPCTL_NEXTEP((epnum + 1) % 15);
9da51974 4498
c6f5c050 4499 if (dir_in)
95c8bc36 4500 dwc2_writel(next, hsotg->regs + DIEPCTL(epnum));
c6f5c050 4501 else
95c8bc36 4502 dwc2_writel(next, hsotg->regs + DOEPCTL(epnum));
5b7d70c6
BD		 4503 }
4504}
4505
b3f489b2 4506/**
1f91b4cc 4507 * dwc2_hsotg_hw_cfg - read HW configuration registers
b3f489b2
LM		 4508 * @param: The device state
4509 *
4510 * Read the USB core HW configuration registers
4511 */
1f91b4cc 4512static int dwc2_hsotg_hw_cfg(struct dwc2_hsotg *hsotg)
5b7d70c6 4513{
c6f5c050
MYK		 4514 u32 cfg;
4515 u32 ep_type;
4516 u32 i;
4517
b3f489b2 4518 /* check hardware configuration */
5b7d70c6 4519
43e90349
JY		 4520 hsotg->num_of_eps = hsotg->hw_params.num_dev_ep;
4521
c6f5c050
MYK		 4522 /* Add ep0 */
4523 hsotg->num_of_eps++;
10aebc77 4524
b98866c2
JY		 4525 hsotg->eps_in[0] = devm_kzalloc(hsotg->dev,
4526 sizeof(struct dwc2_hsotg_ep),
4527 GFP_KERNEL);
c6f5c050
MYK		 4528 if (!hsotg->eps_in[0])
4529 return -ENOMEM;
1f91b4cc 4530 /* Same dwc2_hsotg_ep is used in both directions for ep0 */
c6f5c050
MYK		 4531 hsotg->eps_out[0] = hsotg->eps_in[0];
4532
43e90349 4533 cfg = hsotg->hw_params.dev_ep_dirs;
251a17f5 4534 for (i = 1, cfg >>= 2; i < hsotg->num_of_eps; i++, cfg >>= 2) {
c6f5c050
MYK		 4535 ep_type = cfg & 3;
4536 /* Direction in or both */
4537 if (!(ep_type & 2)) {
4538 hsotg->eps_in[i] = devm_kzalloc(hsotg->dev,
1f91b4cc 4539 sizeof(struct dwc2_hsotg_ep), GFP_KERNEL);
c6f5c050
MYK		 4540 if (!hsotg->eps_in[i])
4541 return -ENOMEM;
4542 }
4543 /* Direction out or both */
4544 if (!(ep_type & 1)) {
4545 hsotg->eps_out[i] = devm_kzalloc(hsotg->dev,
1f91b4cc 4546 sizeof(struct dwc2_hsotg_ep), GFP_KERNEL);
c6f5c050
MYK		 4547 if (!hsotg->eps_out[i])
4548 return -ENOMEM;
4549 }
4550 }
4551
43e90349
JY		 4552 hsotg->fifo_mem = hsotg->hw_params.total_fifo_size;
4553 hsotg->dedicated_fifos = hsotg->hw_params.en_multiple_tx_fifo;
10aebc77 4554
cff9eb75
MS		 4555 dev_info(hsotg->dev, "EPs: %d, %s fifos, %d entries in SPRAM\n",
4556 hsotg->num_of_eps,
4557 hsotg->dedicated_fifos ? "dedicated" : "shared",
4558 hsotg->fifo_mem);
c6f5c050 4559 return 0;
5b7d70c6
BD		 4560}
4561
8b9bc460 4562/**
1f91b4cc 4563 * dwc2_hsotg_dump - dump state of the udc
8b9bc460
LM		 4564 * @param: The device state
4565 */
1f91b4cc 4566static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg)
5b7d70c6 4567{
83a01804 4568#ifdef DEBUG
5b7d70c6
BD		 4569 struct device *dev = hsotg->dev;
4570 void __iomem *regs = hsotg->regs;
4571 u32 val;
4572 int idx;
4573
4574 dev_info(dev, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n",
95c8bc36
AS		 4575 dwc2_readl(regs + DCFG), dwc2_readl(regs + DCTL),
4576 dwc2_readl(regs + DIEPMSK));
5b7d70c6 4577
f889f23d 4578 dev_info(dev, "GAHBCFG=0x%08x, GHWCFG1=0x%08x\n",
95c8bc36 4579 dwc2_readl(regs + GAHBCFG), dwc2_readl(regs + GHWCFG1));
5b7d70c6
BD		 4580
4581 dev_info(dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
95c8bc36 4582 dwc2_readl(regs + GRXFSIZ), dwc2_readl(regs + GNPTXFSIZ));
5b7d70c6
BD		 4583
4584 /* show periodic fifo settings */
4585
364f8e93 4586 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
95c8bc36 4587 val = dwc2_readl(regs + DPTXFSIZN(idx));
5b7d70c6 4588 dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx,
47a1685f
DN		 4589 val >> FIFOSIZE_DEPTH_SHIFT,
4590 val & FIFOSIZE_STARTADDR_MASK);
5b7d70c6
BD		 4591 }
4592
364f8e93 4593 for (idx = 0; idx < hsotg->num_of_eps; idx++) {
5b7d70c6
BD		 4594 dev_info(dev,
4595 "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx,
95c8bc36
AS		 4596 dwc2_readl(regs + DIEPCTL(idx)),
4597 dwc2_readl(regs + DIEPTSIZ(idx)),
4598 dwc2_readl(regs + DIEPDMA(idx)));
5b7d70c6 4599
95c8bc36 4600 val = dwc2_readl(regs + DOEPCTL(idx));
5b7d70c6
BD		 4601 dev_info(dev,
4602 "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n",
95c8bc36
AS		 4603 idx, dwc2_readl(regs + DOEPCTL(idx)),
4604 dwc2_readl(regs + DOEPTSIZ(idx)),
4605 dwc2_readl(regs + DOEPDMA(idx)));
5b7d70c6
BD		 4606 }
4607
4608 dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n",
95c8bc36 4609 dwc2_readl(regs + DVBUSDIS), dwc2_readl(regs + DVBUSPULSE));
83a01804 4610#endif
5b7d70c6
BD		 4611}
4612
8b9bc460 4613/**
117777b2
DN		 4614 * dwc2_gadget_init - init function for gadget
4615 * @dwc2: The data structure for the DWC2 driver.
8b9bc460 4616 */
f3768997 4617int dwc2_gadget_init(struct dwc2_hsotg *hsotg)
5b7d70c6 4618{
117777b2 4619 struct device *dev = hsotg->dev;
5b7d70c6
BD		 4620 int epnum;
4621 int ret;
43e90349 4622
0a176279
GH		 4623 /* Dump fifo information */
4624 dev_dbg(dev, "NonPeriodic TXFIFO size: %d\n",
05ee799f
JY		 4625 hsotg->params.g_np_tx_fifo_size);
4626 dev_dbg(dev, "RXFIFO size: %d\n", hsotg->params.g_rx_fifo_size);
5b7d70c6 4627
d327ab5b 4628 hsotg->gadget.max_speed = USB_SPEED_HIGH;
1f91b4cc 4629 hsotg->gadget.ops = &dwc2_hsotg_gadget_ops;
5b7d70c6 4630 hsotg->gadget.name = dev_name(dev);
fa389a6d 4631 hsotg->remote_wakeup_allowed = 0;
7455f8b7
JY		 4632
4633 if (hsotg->params.lpm)
4634 hsotg->gadget.lpm_capable = true;
4635
097ee662
GH		 4636 if (hsotg->dr_mode == USB_DR_MODE_OTG)
4637 hsotg->gadget.is_otg = 1;
ec4cc657
MYK		 4638 else if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
4639 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
5b7d70c6 4640
1f91b4cc 4641 ret = dwc2_hsotg_hw_cfg(hsotg);
c6f5c050
MYK		 4642 if (ret) {
4643 dev_err(hsotg->dev, "Hardware configuration failed: %d\n", ret);
09a75e85 4644 return ret;
c6f5c050
MYK		 4645 }
4646
3f95001d
MYK		 4647 hsotg->ctrl_buff = devm_kzalloc(hsotg->dev,
4648 DWC2_CTRL_BUFF_SIZE, GFP_KERNEL);
8bae0f8c 4649 if (!hsotg->ctrl_buff)
09a75e85 4650 return -ENOMEM;
3f95001d
MYK		 4651
4652 hsotg->ep0_buff = devm_kzalloc(hsotg->dev,
4653 DWC2_CTRL_BUFF_SIZE, GFP_KERNEL);
8bae0f8c 4654 if (!hsotg->ep0_buff)
09a75e85 4655 return -ENOMEM;
3f95001d 4656
0f6b80c0
VA		 4657 if (using_desc_dma(hsotg)) {
4658 ret = dwc2_gadget_alloc_ctrl_desc_chains(hsotg);
4659 if (ret < 0)
4660 return ret;
4661 }
4662
f3768997
VM		 4663 ret = devm_request_irq(hsotg->dev, hsotg->irq, dwc2_hsotg_irq,
4664 IRQF_SHARED, dev_name(hsotg->dev), hsotg);
eb3c56c5 4665 if (ret < 0) {
db8178c3 4666 dev_err(dev, "cannot claim IRQ for gadget\n");
09a75e85 4667 return ret;
eb3c56c5
MS		 4668 }
4669
b3f489b2
LM		 4670 /* hsotg->num_of_eps holds number of EPs other than ep0 */
4671
4672 if (hsotg->num_of_eps == 0) {
4673 dev_err(dev, "wrong number of EPs (zero)\n");
09a75e85 4674 return -EINVAL;
b3f489b2
LM		 4675 }
4676
b3f489b2
LM		 4677 /* setup endpoint information */
4678
4679 INIT_LIST_HEAD(&hsotg->gadget.ep_list);
c6f5c050 4680 hsotg->gadget.ep0 = &hsotg->eps_out[0]->ep;
b3f489b2
LM		 4681
4682 /* allocate EP0 request */
4683
1f91b4cc 4684 hsotg->ctrl_req = dwc2_hsotg_ep_alloc_request(&hsotg->eps_out[0]->ep,
b3f489b2
LM		 4685 GFP_KERNEL);
4686 if (!hsotg->ctrl_req) {
4687 dev_err(dev, "failed to allocate ctrl req\n");
09a75e85 4688 return -ENOMEM;
b3f489b2 4689 }
5b7d70c6
BD		 4690
4691 /* initialise the endpoints now the core has been initialised */
c6f5c050
MYK		 4692 for (epnum = 0; epnum < hsotg->num_of_eps; epnum++) {
4693 if (hsotg->eps_in[epnum])
1f91b4cc 4694 dwc2_hsotg_initep(hsotg, hsotg->eps_in[epnum],
9da51974 4695 epnum, 1);
c6f5c050 4696 if (hsotg->eps_out[epnum])
1f91b4cc 4697 dwc2_hsotg_initep(hsotg, hsotg->eps_out[epnum],
9da51974 4698 epnum, 0);
c6f5c050 4699 }
5b7d70c6 4700
117777b2 4701 ret = usb_add_gadget_udc(dev, &hsotg->gadget);
0f91349b 4702 if (ret)
09a75e85 4703 return ret;
0f91349b 4704
1f91b4cc 4705 dwc2_hsotg_dump(hsotg);
5b7d70c6 4706
5b7d70c6 4707 return 0;
5b7d70c6
BD		 4708}
4709
8b9bc460 4710/**
1f91b4cc 4711 * dwc2_hsotg_remove - remove function for hsotg driver
8b9bc460
LM		 4712 * @pdev: The platform information for the driver
4713 */
1f91b4cc 4714int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg)
5b7d70c6 4715{
0f91349b 4716 usb_del_gadget_udc(&hsotg->gadget);
31ee04de 4717
5b7d70c6
BD		 4718 return 0;
4719}
4720
1f91b4cc 4721int dwc2_hsotg_suspend(struct dwc2_hsotg *hsotg)
b83e333a 4722{
b83e333a 4723 unsigned long flags;
b83e333a 4724
9e779778 4725 if (hsotg->lx_state != DWC2_L0)
09a75e85 4726 return 0;
9e779778 4727
dc6e69e6
MS		 4728 if (hsotg->driver) {
4729 int ep;
4730
b83e333a
MS		 4731 dev_info(hsotg->dev, "suspending usb gadget %s\n",
4732 hsotg->driver->driver.name);
4733
dc6e69e6
MS		 4734 spin_lock_irqsave(&hsotg->lock, flags);
4735 if (hsotg->enabled)
1f91b4cc
FB		 4736 dwc2_hsotg_core_disconnect(hsotg);
4737 dwc2_hsotg_disconnect(hsotg);
dc6e69e6
MS		 4738 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
4739 spin_unlock_irqrestore(&hsotg->lock, flags);
b83e333a 4740
c6f5c050
MYK		 4741 for (ep = 0; ep < hsotg->num_of_eps; ep++) {
4742 if (hsotg->eps_in[ep])
1f91b4cc 4743 dwc2_hsotg_ep_disable(&hsotg->eps_in[ep]->ep);
c6f5c050 4744 if (hsotg->eps_out[ep])
1f91b4cc 4745 dwc2_hsotg_ep_disable(&hsotg->eps_out[ep]->ep);
c6f5c050 4746 }
b83e333a
MS		 4747 }
4748
09a75e85 4749 return 0;
b83e333a
MS		 4750}
4751
1f91b4cc 4752int dwc2_hsotg_resume(struct dwc2_hsotg *hsotg)
b83e333a 4753{
b83e333a 4754 unsigned long flags;
b83e333a 4755
9e779778 4756 if (hsotg->lx_state == DWC2_L2)
09a75e85 4757 return 0;
9e779778 4758
b83e333a
MS		 4759 if (hsotg->driver) {
4760 dev_info(hsotg->dev, "resuming usb gadget %s\n",
4761 hsotg->driver->driver.name);
d00b4142 4762
dc6e69e6 4763 spin_lock_irqsave(&hsotg->lock, flags);
1f91b4cc 4764 dwc2_hsotg_core_init_disconnected(hsotg, false);
66e77a24
RK		 4765 if (hsotg->enabled) {
4766 /* Enable ACG feature in device mode,if supported */
4767 dwc2_enable_acg(hsotg);
1f91b4cc 4768 dwc2_hsotg_core_connect(hsotg);
66e77a24 4769 }
dc6e69e6
MS		 4770 spin_unlock_irqrestore(&hsotg->lock, flags);
4771 }
b83e333a 4772
09a75e85 4773 return 0;
b83e333a 4774}
58e52ff6
JY		 4775
4776/**
4777 * dwc2_backup_device_registers() - Backup controller device registers.
4778 * When suspending usb bus, registers needs to be backuped
4779 * if controller power is disabled once suspended.
4780 *
4781 * @hsotg: Programming view of the DWC_otg controller
4782 */
4783int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg)
4784{
4785 struct dwc2_dregs_backup *dr;
4786 int i;
4787
4788 dev_dbg(hsotg->dev, "%s\n", __func__);
4789
4790 /* Backup dev regs */
4791 dr = &hsotg->dr_backup;
4792
4793 dr->dcfg = dwc2_readl(hsotg->regs + DCFG);
4794 dr->dctl = dwc2_readl(hsotg->regs + DCTL);
4795 dr->daintmsk = dwc2_readl(hsotg->regs + DAINTMSK);
4796 dr->diepmsk = dwc2_readl(hsotg->regs + DIEPMSK);
4797 dr->doepmsk = dwc2_readl(hsotg->regs + DOEPMSK);
4798
4799 for (i = 0; i < hsotg->num_of_eps; i++) {
4800 /* Backup IN EPs */
4801 dr->diepctl[i] = dwc2_readl(hsotg->regs + DIEPCTL(i));
4802
4803 /* Ensure DATA PID is correctly configured */
4804 if (dr->diepctl[i] & DXEPCTL_DPID)
4805 dr->diepctl[i] |= DXEPCTL_SETD1PID;
4806 else
4807 dr->diepctl[i] |= DXEPCTL_SETD0PID;
4808
4809 dr->dieptsiz[i] = dwc2_readl(hsotg->regs + DIEPTSIZ(i));
4810 dr->diepdma[i] = dwc2_readl(hsotg->regs + DIEPDMA(i));
4811
4812 /* Backup OUT EPs */
4813 dr->doepctl[i] = dwc2_readl(hsotg->regs + DOEPCTL(i));
4814
4815 /* Ensure DATA PID is correctly configured */
4816 if (dr->doepctl[i] & DXEPCTL_DPID)
4817 dr->doepctl[i] |= DXEPCTL_SETD1PID;
4818 else
4819 dr->doepctl[i] |= DXEPCTL_SETD0PID;
4820
4821 dr->doeptsiz[i] = dwc2_readl(hsotg->regs + DOEPTSIZ(i));
4822 dr->doepdma[i] = dwc2_readl(hsotg->regs + DOEPDMA(i));
af7c2bd3 4823 dr->dtxfsiz[i] = dwc2_readl(hsotg->regs + DPTXFSIZN(i));
58e52ff6
JY		 4824 }
4825 dr->valid = true;
4826 return 0;
4827}
4828
4829/**
4830 * dwc2_restore_device_registers() - Restore controller device registers.
4831 * When resuming usb bus, device registers needs to be restored
4832 * if controller power were disabled.
4833 *
4834 * @hsotg: Programming view of the DWC_otg controller
9a5d2816
VM		 4835 * @remote_wakeup: Indicates whether resume is initiated by Device or Host.
4836 *
4837 * Return: 0 if successful, negative error code otherwise
58e52ff6 4838 */
9a5d2816 4839int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg, int remote_wakeup)
58e52ff6
JY		 4840{
4841 struct dwc2_dregs_backup *dr;
58e52ff6
JY		 4842 int i;
4843
4844 dev_dbg(hsotg->dev, "%s\n", __func__);
4845
4846 /* Restore dev regs */
4847 dr = &hsotg->dr_backup;
4848 if (!dr->valid) {
4849 dev_err(hsotg->dev, "%s: no device registers to restore\n",
4850 __func__);
4851 return -EINVAL;
4852 }
4853 dr->valid = false;
4854
9a5d2816
VM		 4855 if (!remote_wakeup)
4856 dwc2_writel(dr->dctl, hsotg->regs + DCTL);
4857
58e52ff6
JY		 4858 dwc2_writel(dr->daintmsk, hsotg->regs + DAINTMSK);
4859 dwc2_writel(dr->diepmsk, hsotg->regs + DIEPMSK);
4860 dwc2_writel(dr->doepmsk, hsotg->regs + DOEPMSK);
4861
4862 for (i = 0; i < hsotg->num_of_eps; i++) {
4863 /* Restore IN EPs */
58e52ff6
JY		 4864 dwc2_writel(dr->dieptsiz[i], hsotg->regs + DIEPTSIZ(i));
4865 dwc2_writel(dr->diepdma[i], hsotg->regs + DIEPDMA(i));
9a5d2816
VM		 4866 dwc2_writel(dr->doeptsiz[i], hsotg->regs + DOEPTSIZ(i));
4867 /** WA for enabled EPx's IN in DDMA mode. On entering to
4868 * hibernation wrong value read and saved from DIEPDMAx,
4869 * as result BNA interrupt asserted on hibernation exit
4870 * by restoring from saved area.
4871 */
4872 if (hsotg->params.g_dma_desc &&
4873 (dr->diepctl[i] & DXEPCTL_EPENA))
4874 dr->diepdma[i] = hsotg->eps_in[i]->desc_list_dma;
af7c2bd3 4875 dwc2_writel(dr->dtxfsiz[i], hsotg->regs + DPTXFSIZN(i));
9a5d2816 4876 dwc2_writel(dr->diepctl[i], hsotg->regs + DIEPCTL(i));
58e52ff6 4877 /* Restore OUT EPs */
58e52ff6 4878 dwc2_writel(dr->doeptsiz[i], hsotg->regs + DOEPTSIZ(i));
9a5d2816
VM		 4879 /* WA for enabled EPx's OUT in DDMA mode. On entering to
4880 * hibernation wrong value read and saved from DOEPDMAx,
4881 * as result BNA interrupt asserted on hibernation exit
4882 * by restoring from saved area.
4883 */
4884 if (hsotg->params.g_dma_desc &&
4885 (dr->doepctl[i] & DXEPCTL_EPENA))
4886 dr->doepdma[i] = hsotg->eps_out[i]->desc_list_dma;
58e52ff6 4887 dwc2_writel(dr->doepdma[i], hsotg->regs + DOEPDMA(i));
9a5d2816 4888 dwc2_writel(dr->doepctl[i], hsotg->regs + DOEPCTL(i));
58e52ff6
JY		 4889 }
4890
58e52ff6
JY		 4891 return 0;
4892}
21b03405
SA		 4893
4894/**
4895 * dwc2_gadget_init_lpm - Configure the core to support LPM in device mode
4896 *
4897 * @hsotg: Programming view of DWC_otg controller
4898 *
4899 */
4900void dwc2_gadget_init_lpm(struct dwc2_hsotg *hsotg)
4901{
4902 u32 val;
4903
4904 if (!hsotg->params.lpm)
4905 return;
4906
4907 val = GLPMCFG_LPMCAP | GLPMCFG_APPL1RES;
4908 val |= hsotg->params.hird_threshold_en ? GLPMCFG_HIRD_THRES_EN : 0;
4909 val |= hsotg->params.lpm_clock_gating ? GLPMCFG_ENBLSLPM : 0;
4910 val |= hsotg->params.hird_threshold << GLPMCFG_HIRD_THRES_SHIFT;
4911 val |= hsotg->params.besl ? GLPMCFG_ENBESL : 0;
4912 dwc2_writel(val, hsotg->regs + GLPMCFG);
4913 dev_dbg(hsotg->dev, "GLPMCFG=0x%08x\n", dwc2_readl(hsotg->regs
4914 + GLPMCFG));
4915}
c5c403dc
VM		 4916
4917/**
4918 * dwc2_gadget_enter_hibernation() - Put controller in Hibernation.
4919 *
4920 * @hsotg: Programming view of the DWC_otg controller
4921 *
4922 * Return non-zero if failed to enter to hibernation.
4923 */
4924int dwc2_gadget_enter_hibernation(struct dwc2_hsotg *hsotg)
4925{
4926 u32 gpwrdn;
4927 int ret = 0;
4928
4929 /* Change to L2(suspend) state */
4930 hsotg->lx_state = DWC2_L2;
4931 dev_dbg(hsotg->dev, "Start of hibernation completed\n");
4932 ret = dwc2_backup_global_registers(hsotg);
4933 if (ret) {
4934 dev_err(hsotg->dev, "%s: failed to backup global registers\n",
4935 __func__);
4936 return ret;
4937 }
4938 ret = dwc2_backup_device_registers(hsotg);
4939 if (ret) {
4940 dev_err(hsotg->dev, "%s: failed to backup device registers\n",
4941 __func__);
4942 return ret;
4943 }
4944
4945 gpwrdn = GPWRDN_PWRDNRSTN;
4946 gpwrdn |= GPWRDN_PMUACTV;
4947 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN);
4948 udelay(10);
4949
4950 /* Set flag to indicate that we are in hibernation */
4951 hsotg->hibernated = 1;
4952
4953 /* Enable interrupts from wake up logic */
4954 gpwrdn = dwc2_readl(hsotg->regs + GPWRDN);
4955 gpwrdn |= GPWRDN_PMUINTSEL;
4956 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN);
4957 udelay(10);
4958
4959 /* Unmask device mode interrupts in GPWRDN */
4960 gpwrdn = dwc2_readl(hsotg->regs + GPWRDN);
4961 gpwrdn |= GPWRDN_RST_DET_MSK;
4962 gpwrdn |= GPWRDN_LNSTSCHG_MSK;
4963 gpwrdn |= GPWRDN_STS_CHGINT_MSK;
4964 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN);
4965 udelay(10);
4966
4967 /* Enable Power Down Clamp */
4968 gpwrdn = dwc2_readl(hsotg->regs + GPWRDN);
4969 gpwrdn |= GPWRDN_PWRDNCLMP;
4970 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN);
4971 udelay(10);
4972
4973 /* Switch off VDD */
4974 gpwrdn = dwc2_readl(hsotg->regs + GPWRDN);
4975 gpwrdn |= GPWRDN_PWRDNSWTCH;
4976 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN);
4977 udelay(10);
4978
4979 /* Save gpwrdn register for further usage if stschng interrupt */
4980 hsotg->gr_backup.gpwrdn = dwc2_readl(hsotg->regs + GPWRDN);
4981 dev_dbg(hsotg->dev, "Hibernation completed\n");
4982
4983 return ret;
4984}
4985
4986/**
4987 * dwc2_gadget_exit_hibernation()
4988 * This function is for exiting from Device mode hibernation by host initiated
4989 * resume/reset and device initiated remote-wakeup.
4990 *
4991 * @hsotg: Programming view of the DWC_otg controller
4992 * @rem_wakeup: indicates whether resume is initiated by Device or Host.
4993 * @param reset: indicates whether resume is initiated by Reset.
4994 *
4995 * Return non-zero if failed to exit from hibernation.
4996 */
4997int dwc2_gadget_exit_hibernation(struct dwc2_hsotg *hsotg,
4998 int rem_wakeup, int reset)
4999{
5000 u32 pcgcctl;
5001 u32 gpwrdn;
5002 u32 dctl;
5003 int ret = 0;
5004 struct dwc2_gregs_backup *gr;
5005 struct dwc2_dregs_backup *dr;
5006
5007 gr = &hsotg->gr_backup;
5008 dr = &hsotg->dr_backup;
5009
5010 if (!hsotg->hibernated) {
5011 dev_dbg(hsotg->dev, "Already exited from Hibernation\n");
5012 return 1;
5013 }
5014 dev_dbg(hsotg->dev,
5015 "%s: called with rem_wakeup = %d reset = %d\n",
5016 __func__, rem_wakeup, reset);
5017
5018 dwc2_hib_restore_common(hsotg, rem_wakeup, 0);
5019
5020 if (!reset) {
5021 /* Clear all pending interupts */
5022 dwc2_writel(0xffffffff, hsotg->regs + GINTSTS);
5023 }
5024
5025 /* De-assert Restore */
5026 gpwrdn = dwc2_readl(hsotg->regs + GPWRDN);
5027 gpwrdn &= ~GPWRDN_RESTORE;
5028 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN);
5029 udelay(10);
5030
5031 if (!rem_wakeup) {
5032 pcgcctl = dwc2_readl(hsotg->regs + PCGCTL);
5033 pcgcctl &= ~PCGCTL_RSTPDWNMODULE;
5034 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
5035 }
5036
5037 /* Restore GUSBCFG, DCFG and DCTL */
5038 dwc2_writel(gr->gusbcfg, hsotg->regs + GUSBCFG);
5039 dwc2_writel(dr->dcfg, hsotg->regs + DCFG);
5040 dwc2_writel(dr->dctl, hsotg->regs + DCTL);
5041
5042 /* De-assert Wakeup Logic */
5043 gpwrdn = dwc2_readl(hsotg->regs + GPWRDN);
5044 gpwrdn &= ~GPWRDN_PMUACTV;
5045 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN);
5046
5047 if (rem_wakeup) {
5048 udelay(10);
5049 /* Start Remote Wakeup Signaling */
5050 dwc2_writel(dr->dctl | DCTL_RMTWKUPSIG, hsotg->regs + DCTL);
5051 } else {
5052 udelay(50);
5053 /* Set Device programming done bit */
5054 dctl = dwc2_readl(hsotg->regs + DCTL);
5055 dctl |= DCTL_PWRONPRGDONE;
5056 dwc2_writel(dctl, hsotg->regs + DCTL);
5057 }
5058 /* Wait for interrupts which must be cleared */
5059 mdelay(2);
5060 /* Clear all pending interupts */
5061 dwc2_writel(0xffffffff, hsotg->regs + GINTSTS);
5062
5063 /* Restore global registers */
5064 ret = dwc2_restore_global_registers(hsotg);
5065 if (ret) {
5066 dev_err(hsotg->dev, "%s: failed to restore registers\n",
5067 __func__);
5068 return ret;
5069 }
5070
5071 /* Restore device registers */
5072 ret = dwc2_restore_device_registers(hsotg, rem_wakeup);
5073 if (ret) {
5074 dev_err(hsotg->dev, "%s: failed to restore device registers\n",
5075 __func__);
5076 return ret;
5077 }
5078
5079 if (rem_wakeup) {
5080 mdelay(10);
5081 dctl = dwc2_readl(hsotg->regs + DCTL);
5082 dctl &= ~DCTL_RMTWKUPSIG;
5083 dwc2_writel(dctl, hsotg->regs + DCTL);
5084 }
5085
5086 hsotg->hibernated = 0;
5087 hsotg->lx_state = DWC2_L0;
5088 dev_dbg(hsotg->dev, "Hibernation recovery completes here\n");
5089
5090 return ret;
5091}
Linux 6.x block layer and io_uring tree(s)