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5fd54ace | 1 | // SPDX-License-Identifier: GPL-2.0 |
8b9bc460 | 2 | /** |
dfbc6fa3 AT |
3 | * Copyright (c) 2011 Samsung Electronics Co., Ltd. |
4 | * http://www.samsung.com | |
5b7d70c6 BD |
5 | * |
6 | * Copyright 2008 Openmoko, Inc. | |
7 | * Copyright 2008 Simtec Electronics | |
8 | * Ben Dooks <ben@simtec.co.uk> | |
9 | * http://armlinux.simtec.co.uk/ | |
10 | * | |
11 | * S3C USB2.0 High-speed / OtG driver | |
8b9bc460 | 12 | */ |
5b7d70c6 BD |
13 | |
14 | #include <linux/kernel.h> | |
15 | #include <linux/module.h> | |
16 | #include <linux/spinlock.h> | |
17 | #include <linux/interrupt.h> | |
18 | #include <linux/platform_device.h> | |
19 | #include <linux/dma-mapping.h> | |
7ad8096e | 20 | #include <linux/mutex.h> |
5b7d70c6 BD |
21 | #include <linux/seq_file.h> |
22 | #include <linux/delay.h> | |
23 | #include <linux/io.h> | |
5a0e3ad6 | 24 | #include <linux/slab.h> |
c50f056c | 25 | #include <linux/of_platform.h> |
5b7d70c6 BD |
26 | |
27 | #include <linux/usb/ch9.h> | |
28 | #include <linux/usb/gadget.h> | |
b2e587db | 29 | #include <linux/usb/phy.h> |
5b7d70c6 | 30 | |
f7c0b143 | 31 | #include "core.h" |
941fcce4 | 32 | #include "hw.h" |
5b7d70c6 BD |
33 | |
34 | /* conversion functions */ | |
1f91b4cc | 35 | static inline struct dwc2_hsotg_req *our_req(struct usb_request *req) |
5b7d70c6 | 36 | { |
1f91b4cc | 37 | return container_of(req, struct dwc2_hsotg_req, req); |
5b7d70c6 BD |
38 | } |
39 | ||
1f91b4cc | 40 | static inline struct dwc2_hsotg_ep *our_ep(struct usb_ep *ep) |
5b7d70c6 | 41 | { |
1f91b4cc | 42 | return container_of(ep, struct dwc2_hsotg_ep, ep); |
5b7d70c6 BD |
43 | } |
44 | ||
941fcce4 | 45 | static inline struct dwc2_hsotg *to_hsotg(struct usb_gadget *gadget) |
5b7d70c6 | 46 | { |
941fcce4 | 47 | return container_of(gadget, struct dwc2_hsotg, gadget); |
5b7d70c6 BD |
48 | } |
49 | ||
50 | static inline void __orr32(void __iomem *ptr, u32 val) | |
51 | { | |
95c8bc36 | 52 | dwc2_writel(dwc2_readl(ptr) | val, ptr); |
5b7d70c6 BD |
53 | } |
54 | ||
55 | static inline void __bic32(void __iomem *ptr, u32 val) | |
56 | { | |
95c8bc36 | 57 | dwc2_writel(dwc2_readl(ptr) & ~val, ptr); |
5b7d70c6 BD |
58 | } |
59 | ||
1f91b4cc | 60 | static inline struct dwc2_hsotg_ep *index_to_ep(struct dwc2_hsotg *hsotg, |
c6f5c050 MYK |
61 | u32 ep_index, u32 dir_in) |
62 | { | |
63 | if (dir_in) | |
64 | return hsotg->eps_in[ep_index]; | |
65 | else | |
66 | return hsotg->eps_out[ep_index]; | |
67 | } | |
68 | ||
997f4f81 | 69 | /* forward declaration of functions */ |
1f91b4cc | 70 | static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg); |
5b7d70c6 BD |
71 | |
72 | /** | |
73 | * using_dma - return the DMA status of the driver. | |
74 | * @hsotg: The driver state. | |
75 | * | |
76 | * Return true if we're using DMA. | |
77 | * | |
78 | * Currently, we have the DMA support code worked into everywhere | |
79 | * that needs it, but the AMBA DMA implementation in the hardware can | |
80 | * only DMA from 32bit aligned addresses. This means that gadgets such | |
81 | * as the CDC Ethernet cannot work as they often pass packets which are | |
82 | * not 32bit aligned. | |
83 | * | |
84 | * Unfortunately the choice to use DMA or not is global to the controller | |
85 | * and seems to be only settable when the controller is being put through | |
86 | * a core reset. This means we either need to fix the gadgets to take | |
87 | * account of DMA alignment, or add bounce buffers (yuerk). | |
88 | * | |
edd74be8 | 89 | * g_using_dma is set depending on dts flag. |
5b7d70c6 | 90 | */ |
941fcce4 | 91 | static inline bool using_dma(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 92 | { |
05ee799f | 93 | return hsotg->params.g_dma; |
5b7d70c6 BD |
94 | } |
95 | ||
dec4b556 VA |
96 | /* |
97 | * using_desc_dma - return the descriptor DMA status of the driver. | |
98 | * @hsotg: The driver state. | |
99 | * | |
100 | * Return true if we're using descriptor DMA. | |
101 | */ | |
102 | static inline bool using_desc_dma(struct dwc2_hsotg *hsotg) | |
103 | { | |
104 | return hsotg->params.g_dma_desc; | |
105 | } | |
106 | ||
92d1635d VM |
107 | /** |
108 | * dwc2_gadget_incr_frame_num - Increments the targeted frame number. | |
109 | * @hs_ep: The endpoint | |
110 | * @increment: The value to increment by | |
111 | * | |
112 | * This function will also check if the frame number overruns DSTS_SOFFN_LIMIT. | |
113 | * If an overrun occurs it will wrap the value and set the frame_overrun flag. | |
114 | */ | |
115 | static inline void dwc2_gadget_incr_frame_num(struct dwc2_hsotg_ep *hs_ep) | |
116 | { | |
117 | hs_ep->target_frame += hs_ep->interval; | |
118 | if (hs_ep->target_frame > DSTS_SOFFN_LIMIT) { | |
119 | hs_ep->frame_overrun = 1; | |
120 | hs_ep->target_frame &= DSTS_SOFFN_LIMIT; | |
121 | } else { | |
122 | hs_ep->frame_overrun = 0; | |
123 | } | |
124 | } | |
125 | ||
5b7d70c6 | 126 | /** |
1f91b4cc | 127 | * dwc2_hsotg_en_gsint - enable one or more of the general interrupt |
5b7d70c6 BD |
128 | * @hsotg: The device state |
129 | * @ints: A bitmask of the interrupts to enable | |
130 | */ | |
1f91b4cc | 131 | static void dwc2_hsotg_en_gsint(struct dwc2_hsotg *hsotg, u32 ints) |
5b7d70c6 | 132 | { |
95c8bc36 | 133 | u32 gsintmsk = dwc2_readl(hsotg->regs + GINTMSK); |
5b7d70c6 BD |
134 | u32 new_gsintmsk; |
135 | ||
136 | new_gsintmsk = gsintmsk | ints; | |
137 | ||
138 | if (new_gsintmsk != gsintmsk) { | |
139 | dev_dbg(hsotg->dev, "gsintmsk now 0x%08x\n", new_gsintmsk); | |
95c8bc36 | 140 | dwc2_writel(new_gsintmsk, hsotg->regs + GINTMSK); |
5b7d70c6 BD |
141 | } |
142 | } | |
143 | ||
144 | /** | |
1f91b4cc | 145 | * dwc2_hsotg_disable_gsint - disable one or more of the general interrupt |
5b7d70c6 BD |
146 | * @hsotg: The device state |
147 | * @ints: A bitmask of the interrupts to enable | |
148 | */ | |
1f91b4cc | 149 | static void dwc2_hsotg_disable_gsint(struct dwc2_hsotg *hsotg, u32 ints) |
5b7d70c6 | 150 | { |
95c8bc36 | 151 | u32 gsintmsk = dwc2_readl(hsotg->regs + GINTMSK); |
5b7d70c6 BD |
152 | u32 new_gsintmsk; |
153 | ||
154 | new_gsintmsk = gsintmsk & ~ints; | |
155 | ||
156 | if (new_gsintmsk != gsintmsk) | |
95c8bc36 | 157 | dwc2_writel(new_gsintmsk, hsotg->regs + GINTMSK); |
5b7d70c6 BD |
158 | } |
159 | ||
160 | /** | |
1f91b4cc | 161 | * dwc2_hsotg_ctrl_epint - enable/disable an endpoint irq |
5b7d70c6 BD |
162 | * @hsotg: The device state |
163 | * @ep: The endpoint index | |
164 | * @dir_in: True if direction is in. | |
165 | * @en: The enable value, true to enable | |
166 | * | |
167 | * Set or clear the mask for an individual endpoint's interrupt | |
168 | * request. | |
169 | */ | |
1f91b4cc | 170 | static void dwc2_hsotg_ctrl_epint(struct dwc2_hsotg *hsotg, |
9da51974 | 171 | unsigned int ep, unsigned int dir_in, |
5b7d70c6 BD |
172 | unsigned int en) |
173 | { | |
174 | unsigned long flags; | |
175 | u32 bit = 1 << ep; | |
176 | u32 daint; | |
177 | ||
178 | if (!dir_in) | |
179 | bit <<= 16; | |
180 | ||
181 | local_irq_save(flags); | |
95c8bc36 | 182 | daint = dwc2_readl(hsotg->regs + DAINTMSK); |
5b7d70c6 BD |
183 | if (en) |
184 | daint |= bit; | |
185 | else | |
186 | daint &= ~bit; | |
95c8bc36 | 187 | dwc2_writel(daint, hsotg->regs + DAINTMSK); |
5b7d70c6 BD |
188 | local_irq_restore(flags); |
189 | } | |
190 | ||
c138ecfa SA |
191 | /** |
192 | * dwc2_hsotg_tx_fifo_count - return count of TX FIFOs in device mode | |
193 | */ | |
194 | int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg *hsotg) | |
195 | { | |
196 | if (hsotg->hw_params.en_multiple_tx_fifo) | |
197 | /* In dedicated FIFO mode we need count of IN EPs */ | |
198 | return (dwc2_readl(hsotg->regs + GHWCFG4) & | |
199 | GHWCFG4_NUM_IN_EPS_MASK) >> GHWCFG4_NUM_IN_EPS_SHIFT; | |
200 | else | |
201 | /* In shared FIFO mode we need count of Periodic IN EPs */ | |
202 | return hsotg->hw_params.num_dev_perio_in_ep; | |
203 | } | |
204 | ||
205 | /** | |
206 | * dwc2_hsotg_ep_info_size - return Endpoint Info Control block size in DWORDs | |
207 | */ | |
208 | static int dwc2_hsotg_ep_info_size(struct dwc2_hsotg *hsotg) | |
209 | { | |
210 | int val = 0; | |
211 | int i; | |
212 | u32 ep_dirs; | |
213 | ||
214 | /* | |
215 | * Don't need additional space for ep info control registers in | |
216 | * slave mode. | |
217 | */ | |
218 | if (!using_dma(hsotg)) { | |
219 | dev_dbg(hsotg->dev, "Buffer DMA ep info size 0\n"); | |
220 | return 0; | |
221 | } | |
222 | ||
223 | /* | |
224 | * Buffer DMA mode - 1 location per endpoit | |
225 | * Descriptor DMA mode - 4 locations per endpoint | |
226 | */ | |
227 | ep_dirs = hsotg->hw_params.dev_ep_dirs; | |
228 | ||
229 | for (i = 0; i <= hsotg->hw_params.num_dev_ep; i++) { | |
230 | val += ep_dirs & 3 ? 1 : 2; | |
231 | ep_dirs >>= 2; | |
232 | } | |
233 | ||
234 | if (using_desc_dma(hsotg)) | |
235 | val = val * 4; | |
236 | ||
237 | return val; | |
238 | } | |
239 | ||
240 | /** | |
241 | * dwc2_hsotg_tx_fifo_total_depth - return total FIFO depth available for | |
242 | * device mode TX FIFOs | |
243 | */ | |
244 | int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg) | |
245 | { | |
246 | int ep_info_size; | |
247 | int addr; | |
248 | int tx_addr_max; | |
249 | u32 np_tx_fifo_size; | |
250 | ||
251 | np_tx_fifo_size = min_t(u32, hsotg->hw_params.dev_nperio_tx_fifo_size, | |
252 | hsotg->params.g_np_tx_fifo_size); | |
253 | ||
254 | /* Get Endpoint Info Control block size in DWORDs. */ | |
255 | ep_info_size = dwc2_hsotg_ep_info_size(hsotg); | |
256 | tx_addr_max = hsotg->hw_params.total_fifo_size - ep_info_size; | |
257 | ||
258 | addr = hsotg->params.g_rx_fifo_size + np_tx_fifo_size; | |
259 | if (tx_addr_max <= addr) | |
260 | return 0; | |
261 | ||
262 | return tx_addr_max - addr; | |
263 | } | |
264 | ||
265 | /** | |
266 | * dwc2_hsotg_tx_fifo_average_depth - returns average depth of device mode | |
267 | * TX FIFOs | |
268 | */ | |
269 | int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg *hsotg) | |
270 | { | |
271 | int tx_fifo_count; | |
272 | int tx_fifo_depth; | |
273 | ||
274 | tx_fifo_depth = dwc2_hsotg_tx_fifo_total_depth(hsotg); | |
275 | ||
276 | tx_fifo_count = dwc2_hsotg_tx_fifo_count(hsotg); | |
277 | ||
278 | if (!tx_fifo_count) | |
279 | return tx_fifo_depth; | |
280 | else | |
281 | return tx_fifo_depth / tx_fifo_count; | |
282 | } | |
283 | ||
5b7d70c6 | 284 | /** |
1f91b4cc | 285 | * dwc2_hsotg_init_fifo - initialise non-periodic FIFOs |
5b7d70c6 BD |
286 | * @hsotg: The device instance. |
287 | */ | |
1f91b4cc | 288 | static void dwc2_hsotg_init_fifo(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 289 | { |
2317eacd | 290 | unsigned int ep; |
0f002d20 | 291 | unsigned int addr; |
1703a6d3 | 292 | int timeout; |
0f002d20 | 293 | u32 val; |
05ee799f | 294 | u32 *txfsz = hsotg->params.g_tx_fifo_size; |
0f002d20 | 295 | |
7fcbc95c GH |
296 | /* Reset fifo map if not correctly cleared during previous session */ |
297 | WARN_ON(hsotg->fifo_map); | |
298 | hsotg->fifo_map = 0; | |
299 | ||
0a176279 | 300 | /* set RX/NPTX FIFO sizes */ |
05ee799f JY |
301 | dwc2_writel(hsotg->params.g_rx_fifo_size, hsotg->regs + GRXFSIZ); |
302 | dwc2_writel((hsotg->params.g_rx_fifo_size << FIFOSIZE_STARTADDR_SHIFT) | | |
303 | (hsotg->params.g_np_tx_fifo_size << FIFOSIZE_DEPTH_SHIFT), | |
304 | hsotg->regs + GNPTXFSIZ); | |
0f002d20 | 305 | |
8b9bc460 LM |
306 | /* |
307 | * arange all the rest of the TX FIFOs, as some versions of this | |
0f002d20 BD |
308 | * block have overlapping default addresses. This also ensures |
309 | * that if the settings have been changed, then they are set to | |
8b9bc460 LM |
310 | * known values. |
311 | */ | |
0f002d20 BD |
312 | |
313 | /* start at the end of the GNPTXFSIZ, rounded up */ | |
05ee799f | 314 | addr = hsotg->params.g_rx_fifo_size + hsotg->params.g_np_tx_fifo_size; |
0f002d20 | 315 | |
8b9bc460 | 316 | /* |
0a176279 | 317 | * Configure fifos sizes from provided configuration and assign |
b203d0a2 RB |
318 | * them to endpoints dynamically according to maxpacket size value of |
319 | * given endpoint. | |
8b9bc460 | 320 | */ |
2317eacd | 321 | for (ep = 1; ep < MAX_EPS_CHANNELS; ep++) { |
05ee799f | 322 | if (!txfsz[ep]) |
3fa95385 JY |
323 | continue; |
324 | val = addr; | |
05ee799f JY |
325 | val |= txfsz[ep] << FIFOSIZE_DEPTH_SHIFT; |
326 | WARN_ONCE(addr + txfsz[ep] > hsotg->fifo_mem, | |
3fa95385 | 327 | "insufficient fifo memory"); |
05ee799f | 328 | addr += txfsz[ep]; |
0f002d20 | 329 | |
2317eacd | 330 | dwc2_writel(val, hsotg->regs + DPTXFSIZN(ep)); |
05ee799f | 331 | val = dwc2_readl(hsotg->regs + DPTXFSIZN(ep)); |
0f002d20 | 332 | } |
1703a6d3 | 333 | |
f87c842f SA |
334 | dwc2_writel(hsotg->hw_params.total_fifo_size | |
335 | addr << GDFIFOCFG_EPINFOBASE_SHIFT, | |
336 | hsotg->regs + GDFIFOCFG); | |
8b9bc460 LM |
337 | /* |
338 | * according to p428 of the design guide, we need to ensure that | |
339 | * all fifos are flushed before continuing | |
340 | */ | |
1703a6d3 | 341 | |
95c8bc36 | 342 | dwc2_writel(GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH | |
47a1685f | 343 | GRSTCTL_RXFFLSH, hsotg->regs + GRSTCTL); |
1703a6d3 BD |
344 | |
345 | /* wait until the fifos are both flushed */ | |
346 | timeout = 100; | |
347 | while (1) { | |
95c8bc36 | 348 | val = dwc2_readl(hsotg->regs + GRSTCTL); |
1703a6d3 | 349 | |
47a1685f | 350 | if ((val & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH)) == 0) |
1703a6d3 BD |
351 | break; |
352 | ||
353 | if (--timeout == 0) { | |
354 | dev_err(hsotg->dev, | |
355 | "%s: timeout flushing fifos (GRSTCTL=%08x)\n", | |
356 | __func__, val); | |
48b20bcb | 357 | break; |
1703a6d3 BD |
358 | } |
359 | ||
360 | udelay(1); | |
361 | } | |
362 | ||
363 | dev_dbg(hsotg->dev, "FIFOs reset, timeout at %d\n", timeout); | |
5b7d70c6 BD |
364 | } |
365 | ||
366 | /** | |
367 | * @ep: USB endpoint to allocate request for. | |
368 | * @flags: Allocation flags | |
369 | * | |
370 | * Allocate a new USB request structure appropriate for the specified endpoint | |
371 | */ | |
1f91b4cc | 372 | static struct usb_request *dwc2_hsotg_ep_alloc_request(struct usb_ep *ep, |
9da51974 | 373 | gfp_t flags) |
5b7d70c6 | 374 | { |
1f91b4cc | 375 | struct dwc2_hsotg_req *req; |
5b7d70c6 | 376 | |
ec33efe2 | 377 | req = kzalloc(sizeof(*req), flags); |
5b7d70c6 BD |
378 | if (!req) |
379 | return NULL; | |
380 | ||
381 | INIT_LIST_HEAD(&req->queue); | |
382 | ||
5b7d70c6 BD |
383 | return &req->req; |
384 | } | |
385 | ||
386 | /** | |
387 | * is_ep_periodic - return true if the endpoint is in periodic mode. | |
388 | * @hs_ep: The endpoint to query. | |
389 | * | |
390 | * Returns true if the endpoint is in periodic mode, meaning it is being | |
391 | * used for an Interrupt or ISO transfer. | |
392 | */ | |
1f91b4cc | 393 | static inline int is_ep_periodic(struct dwc2_hsotg_ep *hs_ep) |
5b7d70c6 BD |
394 | { |
395 | return hs_ep->periodic; | |
396 | } | |
397 | ||
398 | /** | |
1f91b4cc | 399 | * dwc2_hsotg_unmap_dma - unmap the DMA memory being used for the request |
5b7d70c6 BD |
400 | * @hsotg: The device state. |
401 | * @hs_ep: The endpoint for the request | |
402 | * @hs_req: The request being processed. | |
403 | * | |
1f91b4cc | 404 | * This is the reverse of dwc2_hsotg_map_dma(), called for the completion |
5b7d70c6 | 405 | * of a request to ensure the buffer is ready for access by the caller. |
8b9bc460 | 406 | */ |
1f91b4cc | 407 | static void dwc2_hsotg_unmap_dma(struct dwc2_hsotg *hsotg, |
9da51974 | 408 | struct dwc2_hsotg_ep *hs_ep, |
1f91b4cc | 409 | struct dwc2_hsotg_req *hs_req) |
5b7d70c6 BD |
410 | { |
411 | struct usb_request *req = &hs_req->req; | |
9da51974 | 412 | |
17d966a3 | 413 | usb_gadget_unmap_request(&hsotg->gadget, req, hs_ep->dir_in); |
5b7d70c6 BD |
414 | } |
415 | ||
0f6b80c0 VA |
416 | /* |
417 | * dwc2_gadget_alloc_ctrl_desc_chains - allocate DMA descriptor chains | |
418 | * for Control endpoint | |
419 | * @hsotg: The device state. | |
420 | * | |
421 | * This function will allocate 4 descriptor chains for EP 0: 2 for | |
422 | * Setup stage, per one for IN and OUT data/status transactions. | |
423 | */ | |
424 | static int dwc2_gadget_alloc_ctrl_desc_chains(struct dwc2_hsotg *hsotg) | |
425 | { | |
426 | hsotg->setup_desc[0] = | |
427 | dmam_alloc_coherent(hsotg->dev, | |
428 | sizeof(struct dwc2_dma_desc), | |
429 | &hsotg->setup_desc_dma[0], | |
430 | GFP_KERNEL); | |
431 | if (!hsotg->setup_desc[0]) | |
432 | goto fail; | |
433 | ||
434 | hsotg->setup_desc[1] = | |
435 | dmam_alloc_coherent(hsotg->dev, | |
436 | sizeof(struct dwc2_dma_desc), | |
437 | &hsotg->setup_desc_dma[1], | |
438 | GFP_KERNEL); | |
439 | if (!hsotg->setup_desc[1]) | |
440 | goto fail; | |
441 | ||
442 | hsotg->ctrl_in_desc = | |
443 | dmam_alloc_coherent(hsotg->dev, | |
444 | sizeof(struct dwc2_dma_desc), | |
445 | &hsotg->ctrl_in_desc_dma, | |
446 | GFP_KERNEL); | |
447 | if (!hsotg->ctrl_in_desc) | |
448 | goto fail; | |
449 | ||
450 | hsotg->ctrl_out_desc = | |
451 | dmam_alloc_coherent(hsotg->dev, | |
452 | sizeof(struct dwc2_dma_desc), | |
453 | &hsotg->ctrl_out_desc_dma, | |
454 | GFP_KERNEL); | |
455 | if (!hsotg->ctrl_out_desc) | |
456 | goto fail; | |
457 | ||
458 | return 0; | |
459 | ||
460 | fail: | |
461 | return -ENOMEM; | |
462 | } | |
463 | ||
5b7d70c6 | 464 | /** |
1f91b4cc | 465 | * dwc2_hsotg_write_fifo - write packet Data to the TxFIFO |
5b7d70c6 BD |
466 | * @hsotg: The controller state. |
467 | * @hs_ep: The endpoint we're going to write for. | |
468 | * @hs_req: The request to write data for. | |
469 | * | |
470 | * This is called when the TxFIFO has some space in it to hold a new | |
471 | * transmission and we have something to give it. The actual setup of | |
472 | * the data size is done elsewhere, so all we have to do is to actually | |
473 | * write the data. | |
474 | * | |
475 | * The return value is zero if there is more space (or nothing was done) | |
476 | * otherwise -ENOSPC is returned if the FIFO space was used up. | |
477 | * | |
478 | * This routine is only needed for PIO | |
8b9bc460 | 479 | */ |
1f91b4cc | 480 | static int dwc2_hsotg_write_fifo(struct dwc2_hsotg *hsotg, |
9da51974 | 481 | struct dwc2_hsotg_ep *hs_ep, |
1f91b4cc | 482 | struct dwc2_hsotg_req *hs_req) |
5b7d70c6 BD |
483 | { |
484 | bool periodic = is_ep_periodic(hs_ep); | |
95c8bc36 | 485 | u32 gnptxsts = dwc2_readl(hsotg->regs + GNPTXSTS); |
5b7d70c6 BD |
486 | int buf_pos = hs_req->req.actual; |
487 | int to_write = hs_ep->size_loaded; | |
488 | void *data; | |
489 | int can_write; | |
490 | int pkt_round; | |
4fca54aa | 491 | int max_transfer; |
5b7d70c6 BD |
492 | |
493 | to_write -= (buf_pos - hs_ep->last_load); | |
494 | ||
495 | /* if there's nothing to write, get out early */ | |
496 | if (to_write == 0) | |
497 | return 0; | |
498 | ||
10aebc77 | 499 | if (periodic && !hsotg->dedicated_fifos) { |
95c8bc36 | 500 | u32 epsize = dwc2_readl(hsotg->regs + DIEPTSIZ(hs_ep->index)); |
5b7d70c6 BD |
501 | int size_left; |
502 | int size_done; | |
503 | ||
8b9bc460 LM |
504 | /* |
505 | * work out how much data was loaded so we can calculate | |
506 | * how much data is left in the fifo. | |
507 | */ | |
5b7d70c6 | 508 | |
47a1685f | 509 | size_left = DXEPTSIZ_XFERSIZE_GET(epsize); |
5b7d70c6 | 510 | |
8b9bc460 LM |
511 | /* |
512 | * if shared fifo, we cannot write anything until the | |
e7a9ff54 BD |
513 | * previous data has been completely sent. |
514 | */ | |
515 | if (hs_ep->fifo_load != 0) { | |
1f91b4cc | 516 | dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP); |
e7a9ff54 BD |
517 | return -ENOSPC; |
518 | } | |
519 | ||
5b7d70c6 BD |
520 | dev_dbg(hsotg->dev, "%s: left=%d, load=%d, fifo=%d, size %d\n", |
521 | __func__, size_left, | |
522 | hs_ep->size_loaded, hs_ep->fifo_load, hs_ep->fifo_size); | |
523 | ||
524 | /* how much of the data has moved */ | |
525 | size_done = hs_ep->size_loaded - size_left; | |
526 | ||
527 | /* how much data is left in the fifo */ | |
528 | can_write = hs_ep->fifo_load - size_done; | |
529 | dev_dbg(hsotg->dev, "%s: => can_write1=%d\n", | |
530 | __func__, can_write); | |
531 | ||
532 | can_write = hs_ep->fifo_size - can_write; | |
533 | dev_dbg(hsotg->dev, "%s: => can_write2=%d\n", | |
534 | __func__, can_write); | |
535 | ||
536 | if (can_write <= 0) { | |
1f91b4cc | 537 | dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP); |
5b7d70c6 BD |
538 | return -ENOSPC; |
539 | } | |
10aebc77 | 540 | } else if (hsotg->dedicated_fifos && hs_ep->index != 0) { |
ad674a15 RB |
541 | can_write = dwc2_readl(hsotg->regs + |
542 | DTXFSTS(hs_ep->fifo_index)); | |
10aebc77 BD |
543 | |
544 | can_write &= 0xffff; | |
545 | can_write *= 4; | |
5b7d70c6 | 546 | } else { |
47a1685f | 547 | if (GNPTXSTS_NP_TXQ_SPC_AVAIL_GET(gnptxsts) == 0) { |
5b7d70c6 BD |
548 | dev_dbg(hsotg->dev, |
549 | "%s: no queue slots available (0x%08x)\n", | |
550 | __func__, gnptxsts); | |
551 | ||
1f91b4cc | 552 | dwc2_hsotg_en_gsint(hsotg, GINTSTS_NPTXFEMP); |
5b7d70c6 BD |
553 | return -ENOSPC; |
554 | } | |
555 | ||
47a1685f | 556 | can_write = GNPTXSTS_NP_TXF_SPC_AVAIL_GET(gnptxsts); |
679f9b7c | 557 | can_write *= 4; /* fifo size is in 32bit quantities. */ |
5b7d70c6 BD |
558 | } |
559 | ||
4fca54aa RB |
560 | max_transfer = hs_ep->ep.maxpacket * hs_ep->mc; |
561 | ||
562 | dev_dbg(hsotg->dev, "%s: GNPTXSTS=%08x, can=%d, to=%d, max_transfer %d\n", | |
9da51974 | 563 | __func__, gnptxsts, can_write, to_write, max_transfer); |
5b7d70c6 | 564 | |
8b9bc460 LM |
565 | /* |
566 | * limit to 512 bytes of data, it seems at least on the non-periodic | |
5b7d70c6 BD |
567 | * FIFO, requests of >512 cause the endpoint to get stuck with a |
568 | * fragment of the end of the transfer in it. | |
569 | */ | |
811f3303 | 570 | if (can_write > 512 && !periodic) |
5b7d70c6 BD |
571 | can_write = 512; |
572 | ||
8b9bc460 LM |
573 | /* |
574 | * limit the write to one max-packet size worth of data, but allow | |
03e10e5a | 575 | * the transfer to return that it did not run out of fifo space |
8b9bc460 LM |
576 | * doing it. |
577 | */ | |
4fca54aa RB |
578 | if (to_write > max_transfer) { |
579 | to_write = max_transfer; | |
03e10e5a | 580 | |
5cb2ff0c RB |
581 | /* it's needed only when we do not use dedicated fifos */ |
582 | if (!hsotg->dedicated_fifos) | |
1f91b4cc | 583 | dwc2_hsotg_en_gsint(hsotg, |
9da51974 | 584 | periodic ? GINTSTS_PTXFEMP : |
47a1685f | 585 | GINTSTS_NPTXFEMP); |
03e10e5a BD |
586 | } |
587 | ||
5b7d70c6 BD |
588 | /* see if we can write data */ |
589 | ||
590 | if (to_write > can_write) { | |
591 | to_write = can_write; | |
4fca54aa | 592 | pkt_round = to_write % max_transfer; |
5b7d70c6 | 593 | |
8b9bc460 LM |
594 | /* |
595 | * Round the write down to an | |
5b7d70c6 BD |
596 | * exact number of packets. |
597 | * | |
598 | * Note, we do not currently check to see if we can ever | |
599 | * write a full packet or not to the FIFO. | |
600 | */ | |
601 | ||
602 | if (pkt_round) | |
603 | to_write -= pkt_round; | |
604 | ||
8b9bc460 LM |
605 | /* |
606 | * enable correct FIFO interrupt to alert us when there | |
607 | * is more room left. | |
608 | */ | |
5b7d70c6 | 609 | |
5cb2ff0c RB |
610 | /* it's needed only when we do not use dedicated fifos */ |
611 | if (!hsotg->dedicated_fifos) | |
1f91b4cc | 612 | dwc2_hsotg_en_gsint(hsotg, |
9da51974 | 613 | periodic ? GINTSTS_PTXFEMP : |
47a1685f | 614 | GINTSTS_NPTXFEMP); |
5b7d70c6 BD |
615 | } |
616 | ||
617 | dev_dbg(hsotg->dev, "write %d/%d, can_write %d, done %d\n", | |
9da51974 | 618 | to_write, hs_req->req.length, can_write, buf_pos); |
5b7d70c6 BD |
619 | |
620 | if (to_write <= 0) | |
621 | return -ENOSPC; | |
622 | ||
623 | hs_req->req.actual = buf_pos + to_write; | |
624 | hs_ep->total_data += to_write; | |
625 | ||
626 | if (periodic) | |
627 | hs_ep->fifo_load += to_write; | |
628 | ||
629 | to_write = DIV_ROUND_UP(to_write, 4); | |
630 | data = hs_req->req.buf + buf_pos; | |
631 | ||
1a7ed5be | 632 | iowrite32_rep(hsotg->regs + EPFIFO(hs_ep->index), data, to_write); |
5b7d70c6 BD |
633 | |
634 | return (to_write >= can_write) ? -ENOSPC : 0; | |
635 | } | |
636 | ||
637 | /** | |
638 | * get_ep_limit - get the maximum data legnth for this endpoint | |
639 | * @hs_ep: The endpoint | |
640 | * | |
641 | * Return the maximum data that can be queued in one go on a given endpoint | |
642 | * so that transfers that are too long can be split. | |
643 | */ | |
9da51974 | 644 | static unsigned int get_ep_limit(struct dwc2_hsotg_ep *hs_ep) |
5b7d70c6 BD |
645 | { |
646 | int index = hs_ep->index; | |
9da51974 JY |
647 | unsigned int maxsize; |
648 | unsigned int maxpkt; | |
5b7d70c6 BD |
649 | |
650 | if (index != 0) { | |
47a1685f DN |
651 | maxsize = DXEPTSIZ_XFERSIZE_LIMIT + 1; |
652 | maxpkt = DXEPTSIZ_PKTCNT_LIMIT + 1; | |
5b7d70c6 | 653 | } else { |
9da51974 | 654 | maxsize = 64 + 64; |
66e5c643 | 655 | if (hs_ep->dir_in) |
47a1685f | 656 | maxpkt = DIEPTSIZ0_PKTCNT_LIMIT + 1; |
66e5c643 | 657 | else |
5b7d70c6 | 658 | maxpkt = 2; |
5b7d70c6 BD |
659 | } |
660 | ||
661 | /* we made the constant loading easier above by using +1 */ | |
662 | maxpkt--; | |
663 | maxsize--; | |
664 | ||
8b9bc460 LM |
665 | /* |
666 | * constrain by packet count if maxpkts*pktsize is greater | |
667 | * than the length register size. | |
668 | */ | |
5b7d70c6 BD |
669 | |
670 | if ((maxpkt * hs_ep->ep.maxpacket) < maxsize) | |
671 | maxsize = maxpkt * hs_ep->ep.maxpacket; | |
672 | ||
673 | return maxsize; | |
674 | } | |
675 | ||
381fc8f8 | 676 | /** |
38beaec6 JY |
677 | * dwc2_hsotg_read_frameno - read current frame number |
678 | * @hsotg: The device instance | |
679 | * | |
680 | * Return the current frame number | |
681 | */ | |
381fc8f8 VM |
682 | static u32 dwc2_hsotg_read_frameno(struct dwc2_hsotg *hsotg) |
683 | { | |
684 | u32 dsts; | |
685 | ||
686 | dsts = dwc2_readl(hsotg->regs + DSTS); | |
687 | dsts &= DSTS_SOFFN_MASK; | |
688 | dsts >>= DSTS_SOFFN_SHIFT; | |
689 | ||
690 | return dsts; | |
691 | } | |
692 | ||
cf77b5fb VA |
693 | /** |
694 | * dwc2_gadget_get_chain_limit - get the maximum data payload value of the | |
695 | * DMA descriptor chain prepared for specific endpoint | |
696 | * @hs_ep: The endpoint | |
697 | * | |
698 | * Return the maximum data that can be queued in one go on a given endpoint | |
699 | * depending on its descriptor chain capacity so that transfers that | |
700 | * are too long can be split. | |
701 | */ | |
702 | static unsigned int dwc2_gadget_get_chain_limit(struct dwc2_hsotg_ep *hs_ep) | |
703 | { | |
704 | int is_isoc = hs_ep->isochronous; | |
705 | unsigned int maxsize; | |
706 | ||
707 | if (is_isoc) | |
708 | maxsize = hs_ep->dir_in ? DEV_DMA_ISOC_TX_NBYTES_LIMIT : | |
709 | DEV_DMA_ISOC_RX_NBYTES_LIMIT; | |
710 | else | |
711 | maxsize = DEV_DMA_NBYTES_LIMIT; | |
712 | ||
713 | /* Above size of one descriptor was chosen, multiple it */ | |
714 | maxsize *= MAX_DMA_DESC_NUM_GENERIC; | |
715 | ||
716 | return maxsize; | |
717 | } | |
718 | ||
e02f9aa6 VA |
719 | /* |
720 | * dwc2_gadget_get_desc_params - get DMA descriptor parameters. | |
721 | * @hs_ep: The endpoint | |
722 | * @mask: RX/TX bytes mask to be defined | |
723 | * | |
724 | * Returns maximum data payload for one descriptor after analyzing endpoint | |
725 | * characteristics. | |
726 | * DMA descriptor transfer bytes limit depends on EP type: | |
727 | * Control out - MPS, | |
728 | * Isochronous - descriptor rx/tx bytes bitfield limit, | |
729 | * Control In/Bulk/Interrupt - multiple of mps. This will allow to not | |
730 | * have concatenations from various descriptors within one packet. | |
731 | * | |
732 | * Selects corresponding mask for RX/TX bytes as well. | |
733 | */ | |
734 | static u32 dwc2_gadget_get_desc_params(struct dwc2_hsotg_ep *hs_ep, u32 *mask) | |
735 | { | |
736 | u32 mps = hs_ep->ep.maxpacket; | |
737 | int dir_in = hs_ep->dir_in; | |
738 | u32 desc_size = 0; | |
739 | ||
740 | if (!hs_ep->index && !dir_in) { | |
741 | desc_size = mps; | |
742 | *mask = DEV_DMA_NBYTES_MASK; | |
743 | } else if (hs_ep->isochronous) { | |
744 | if (dir_in) { | |
745 | desc_size = DEV_DMA_ISOC_TX_NBYTES_LIMIT; | |
746 | *mask = DEV_DMA_ISOC_TX_NBYTES_MASK; | |
747 | } else { | |
748 | desc_size = DEV_DMA_ISOC_RX_NBYTES_LIMIT; | |
749 | *mask = DEV_DMA_ISOC_RX_NBYTES_MASK; | |
750 | } | |
751 | } else { | |
752 | desc_size = DEV_DMA_NBYTES_LIMIT; | |
753 | *mask = DEV_DMA_NBYTES_MASK; | |
754 | ||
755 | /* Round down desc_size to be mps multiple */ | |
756 | desc_size -= desc_size % mps; | |
757 | } | |
758 | ||
759 | return desc_size; | |
760 | } | |
761 | ||
762 | /* | |
763 | * dwc2_gadget_config_nonisoc_xfer_ddma - prepare non ISOC DMA desc chain. | |
764 | * @hs_ep: The endpoint | |
765 | * @dma_buff: DMA address to use | |
766 | * @len: Length of the transfer | |
767 | * | |
768 | * This function will iterate over descriptor chain and fill its entries | |
769 | * with corresponding information based on transfer data. | |
770 | */ | |
771 | static void dwc2_gadget_config_nonisoc_xfer_ddma(struct dwc2_hsotg_ep *hs_ep, | |
772 | dma_addr_t dma_buff, | |
773 | unsigned int len) | |
774 | { | |
775 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
776 | int dir_in = hs_ep->dir_in; | |
777 | struct dwc2_dma_desc *desc = hs_ep->desc_list; | |
778 | u32 mps = hs_ep->ep.maxpacket; | |
779 | u32 maxsize = 0; | |
780 | u32 offset = 0; | |
781 | u32 mask = 0; | |
782 | int i; | |
783 | ||
784 | maxsize = dwc2_gadget_get_desc_params(hs_ep, &mask); | |
785 | ||
786 | hs_ep->desc_count = (len / maxsize) + | |
787 | ((len % maxsize) ? 1 : 0); | |
788 | if (len == 0) | |
789 | hs_ep->desc_count = 1; | |
790 | ||
791 | for (i = 0; i < hs_ep->desc_count; ++i) { | |
792 | desc->status = 0; | |
793 | desc->status |= (DEV_DMA_BUFF_STS_HBUSY | |
794 | << DEV_DMA_BUFF_STS_SHIFT); | |
795 | ||
796 | if (len > maxsize) { | |
797 | if (!hs_ep->index && !dir_in) | |
798 | desc->status |= (DEV_DMA_L | DEV_DMA_IOC); | |
799 | ||
800 | desc->status |= (maxsize << | |
801 | DEV_DMA_NBYTES_SHIFT & mask); | |
802 | desc->buf = dma_buff + offset; | |
803 | ||
804 | len -= maxsize; | |
805 | offset += maxsize; | |
806 | } else { | |
807 | desc->status |= (DEV_DMA_L | DEV_DMA_IOC); | |
808 | ||
809 | if (dir_in) | |
810 | desc->status |= (len % mps) ? DEV_DMA_SHORT : | |
811 | ((hs_ep->send_zlp) ? DEV_DMA_SHORT : 0); | |
812 | if (len > maxsize) | |
813 | dev_err(hsotg->dev, "wrong len %d\n", len); | |
814 | ||
815 | desc->status |= | |
816 | len << DEV_DMA_NBYTES_SHIFT & mask; | |
817 | desc->buf = dma_buff + offset; | |
818 | } | |
819 | ||
820 | desc->status &= ~DEV_DMA_BUFF_STS_MASK; | |
821 | desc->status |= (DEV_DMA_BUFF_STS_HREADY | |
822 | << DEV_DMA_BUFF_STS_SHIFT); | |
823 | desc++; | |
824 | } | |
825 | } | |
826 | ||
540ccba0 VA |
827 | /* |
828 | * dwc2_gadget_fill_isoc_desc - fills next isochronous descriptor in chain. | |
829 | * @hs_ep: The isochronous endpoint. | |
830 | * @dma_buff: usb requests dma buffer. | |
831 | * @len: usb request transfer length. | |
832 | * | |
833 | * Finds out index of first free entry either in the bottom or up half of | |
834 | * descriptor chain depend on which is under SW control and not processed | |
835 | * by HW. Then fills that descriptor with the data of the arrived usb request, | |
836 | * frame info, sets Last and IOC bits increments next_desc. If filled | |
837 | * descriptor is not the first one, removes L bit from the previous descriptor | |
838 | * status. | |
839 | */ | |
840 | static int dwc2_gadget_fill_isoc_desc(struct dwc2_hsotg_ep *hs_ep, | |
841 | dma_addr_t dma_buff, unsigned int len) | |
842 | { | |
843 | struct dwc2_dma_desc *desc; | |
844 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
845 | u32 index; | |
846 | u32 maxsize = 0; | |
847 | u32 mask = 0; | |
848 | ||
849 | maxsize = dwc2_gadget_get_desc_params(hs_ep, &mask); | |
850 | if (len > maxsize) { | |
851 | dev_err(hsotg->dev, "wrong len %d\n", len); | |
852 | return -EINVAL; | |
853 | } | |
854 | ||
855 | /* | |
856 | * If SW has already filled half of chain, then return and wait for | |
857 | * the other chain to be processed by HW. | |
858 | */ | |
859 | if (hs_ep->next_desc == MAX_DMA_DESC_NUM_GENERIC / 2) | |
860 | return -EBUSY; | |
861 | ||
862 | /* Increment frame number by interval for IN */ | |
863 | if (hs_ep->dir_in) | |
864 | dwc2_gadget_incr_frame_num(hs_ep); | |
865 | ||
866 | index = (MAX_DMA_DESC_NUM_GENERIC / 2) * hs_ep->isoc_chain_num + | |
867 | hs_ep->next_desc; | |
868 | ||
869 | /* Sanity check of calculated index */ | |
870 | if ((hs_ep->isoc_chain_num && index > MAX_DMA_DESC_NUM_GENERIC) || | |
871 | (!hs_ep->isoc_chain_num && index > MAX_DMA_DESC_NUM_GENERIC / 2)) { | |
872 | dev_err(hsotg->dev, "wrong index %d for iso chain\n", index); | |
873 | return -EINVAL; | |
874 | } | |
875 | ||
876 | desc = &hs_ep->desc_list[index]; | |
877 | ||
878 | /* Clear L bit of previous desc if more than one entries in the chain */ | |
879 | if (hs_ep->next_desc) | |
880 | hs_ep->desc_list[index - 1].status &= ~DEV_DMA_L; | |
881 | ||
882 | dev_dbg(hsotg->dev, "%s: Filling ep %d, dir %s isoc desc # %d\n", | |
883 | __func__, hs_ep->index, hs_ep->dir_in ? "in" : "out", index); | |
884 | ||
885 | desc->status = 0; | |
886 | desc->status |= (DEV_DMA_BUFF_STS_HBUSY << DEV_DMA_BUFF_STS_SHIFT); | |
887 | ||
888 | desc->buf = dma_buff; | |
889 | desc->status |= (DEV_DMA_L | DEV_DMA_IOC | | |
890 | ((len << DEV_DMA_NBYTES_SHIFT) & mask)); | |
891 | ||
892 | if (hs_ep->dir_in) { | |
893 | desc->status |= ((hs_ep->mc << DEV_DMA_ISOC_PID_SHIFT) & | |
894 | DEV_DMA_ISOC_PID_MASK) | | |
895 | ((len % hs_ep->ep.maxpacket) ? | |
896 | DEV_DMA_SHORT : 0) | | |
897 | ((hs_ep->target_frame << | |
898 | DEV_DMA_ISOC_FRNUM_SHIFT) & | |
899 | DEV_DMA_ISOC_FRNUM_MASK); | |
900 | } | |
901 | ||
902 | desc->status &= ~DEV_DMA_BUFF_STS_MASK; | |
903 | desc->status |= (DEV_DMA_BUFF_STS_HREADY << DEV_DMA_BUFF_STS_SHIFT); | |
904 | ||
905 | /* Update index of last configured entry in the chain */ | |
906 | hs_ep->next_desc++; | |
907 | ||
908 | return 0; | |
909 | } | |
910 | ||
911 | /* | |
912 | * dwc2_gadget_start_isoc_ddma - start isochronous transfer in DDMA | |
913 | * @hs_ep: The isochronous endpoint. | |
914 | * | |
915 | * Prepare first descriptor chain for isochronous endpoints. Afterwards | |
916 | * write DMA address to HW and enable the endpoint. | |
917 | * | |
918 | * Switch between descriptor chains via isoc_chain_num to give SW opportunity | |
919 | * to prepare second descriptor chain while first one is being processed by HW. | |
920 | */ | |
921 | static void dwc2_gadget_start_isoc_ddma(struct dwc2_hsotg_ep *hs_ep) | |
922 | { | |
923 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
924 | struct dwc2_hsotg_req *hs_req, *treq; | |
925 | int index = hs_ep->index; | |
926 | int ret; | |
927 | u32 dma_reg; | |
928 | u32 depctl; | |
929 | u32 ctrl; | |
930 | ||
931 | if (list_empty(&hs_ep->queue)) { | |
932 | dev_dbg(hsotg->dev, "%s: No requests in queue\n", __func__); | |
933 | return; | |
934 | } | |
935 | ||
936 | list_for_each_entry_safe(hs_req, treq, &hs_ep->queue, queue) { | |
937 | ret = dwc2_gadget_fill_isoc_desc(hs_ep, hs_req->req.dma, | |
938 | hs_req->req.length); | |
939 | if (ret) { | |
940 | dev_dbg(hsotg->dev, "%s: desc chain full\n", __func__); | |
941 | break; | |
942 | } | |
943 | } | |
944 | ||
945 | depctl = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index); | |
946 | dma_reg = hs_ep->dir_in ? DIEPDMA(index) : DOEPDMA(index); | |
947 | ||
948 | /* write descriptor chain address to control register */ | |
949 | dwc2_writel(hs_ep->desc_list_dma, hsotg->regs + dma_reg); | |
950 | ||
951 | ctrl = dwc2_readl(hsotg->regs + depctl); | |
952 | ctrl |= DXEPCTL_EPENA | DXEPCTL_CNAK; | |
953 | dwc2_writel(ctrl, hsotg->regs + depctl); | |
954 | ||
955 | /* Switch ISOC descriptor chain number being processed by SW*/ | |
956 | hs_ep->isoc_chain_num = (hs_ep->isoc_chain_num ^ 1) & 0x1; | |
957 | hs_ep->next_desc = 0; | |
958 | } | |
959 | ||
5b7d70c6 | 960 | /** |
1f91b4cc | 961 | * dwc2_hsotg_start_req - start a USB request from an endpoint's queue |
5b7d70c6 BD |
962 | * @hsotg: The controller state. |
963 | * @hs_ep: The endpoint to process a request for | |
964 | * @hs_req: The request to start. | |
965 | * @continuing: True if we are doing more for the current request. | |
966 | * | |
967 | * Start the given request running by setting the endpoint registers | |
968 | * appropriately, and writing any data to the FIFOs. | |
969 | */ | |
1f91b4cc | 970 | static void dwc2_hsotg_start_req(struct dwc2_hsotg *hsotg, |
9da51974 | 971 | struct dwc2_hsotg_ep *hs_ep, |
1f91b4cc | 972 | struct dwc2_hsotg_req *hs_req, |
5b7d70c6 BD |
973 | bool continuing) |
974 | { | |
975 | struct usb_request *ureq = &hs_req->req; | |
976 | int index = hs_ep->index; | |
977 | int dir_in = hs_ep->dir_in; | |
978 | u32 epctrl_reg; | |
979 | u32 epsize_reg; | |
980 | u32 epsize; | |
981 | u32 ctrl; | |
9da51974 JY |
982 | unsigned int length; |
983 | unsigned int packets; | |
984 | unsigned int maxreq; | |
aa3e8bc8 | 985 | unsigned int dma_reg; |
5b7d70c6 BD |
986 | |
987 | if (index != 0) { | |
988 | if (hs_ep->req && !continuing) { | |
989 | dev_err(hsotg->dev, "%s: active request\n", __func__); | |
990 | WARN_ON(1); | |
991 | return; | |
992 | } else if (hs_ep->req != hs_req && continuing) { | |
993 | dev_err(hsotg->dev, | |
994 | "%s: continue different req\n", __func__); | |
995 | WARN_ON(1); | |
996 | return; | |
997 | } | |
998 | } | |
999 | ||
aa3e8bc8 | 1000 | dma_reg = dir_in ? DIEPDMA(index) : DOEPDMA(index); |
94cb8fd6 LM |
1001 | epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index); |
1002 | epsize_reg = dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index); | |
5b7d70c6 BD |
1003 | |
1004 | dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n", | |
95c8bc36 | 1005 | __func__, dwc2_readl(hsotg->regs + epctrl_reg), index, |
5b7d70c6 BD |
1006 | hs_ep->dir_in ? "in" : "out"); |
1007 | ||
9c39ddc6 | 1008 | /* If endpoint is stalled, we will restart request later */ |
95c8bc36 | 1009 | ctrl = dwc2_readl(hsotg->regs + epctrl_reg); |
9c39ddc6 | 1010 | |
b2d4c54e | 1011 | if (index && ctrl & DXEPCTL_STALL) { |
9c39ddc6 AT |
1012 | dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index); |
1013 | return; | |
1014 | } | |
1015 | ||
5b7d70c6 | 1016 | length = ureq->length - ureq->actual; |
71225bee LM |
1017 | dev_dbg(hsotg->dev, "ureq->length:%d ureq->actual:%d\n", |
1018 | ureq->length, ureq->actual); | |
5b7d70c6 | 1019 | |
cf77b5fb VA |
1020 | if (!using_desc_dma(hsotg)) |
1021 | maxreq = get_ep_limit(hs_ep); | |
1022 | else | |
1023 | maxreq = dwc2_gadget_get_chain_limit(hs_ep); | |
1024 | ||
5b7d70c6 BD |
1025 | if (length > maxreq) { |
1026 | int round = maxreq % hs_ep->ep.maxpacket; | |
1027 | ||
1028 | dev_dbg(hsotg->dev, "%s: length %d, max-req %d, r %d\n", | |
1029 | __func__, length, maxreq, round); | |
1030 | ||
1031 | /* round down to multiple of packets */ | |
1032 | if (round) | |
1033 | maxreq -= round; | |
1034 | ||
1035 | length = maxreq; | |
1036 | } | |
1037 | ||
1038 | if (length) | |
1039 | packets = DIV_ROUND_UP(length, hs_ep->ep.maxpacket); | |
1040 | else | |
1041 | packets = 1; /* send one packet if length is zero. */ | |
1042 | ||
4fca54aa RB |
1043 | if (hs_ep->isochronous && length > (hs_ep->mc * hs_ep->ep.maxpacket)) { |
1044 | dev_err(hsotg->dev, "req length > maxpacket*mc\n"); | |
1045 | return; | |
1046 | } | |
1047 | ||
5b7d70c6 | 1048 | if (dir_in && index != 0) |
4fca54aa | 1049 | if (hs_ep->isochronous) |
47a1685f | 1050 | epsize = DXEPTSIZ_MC(packets); |
4fca54aa | 1051 | else |
47a1685f | 1052 | epsize = DXEPTSIZ_MC(1); |
5b7d70c6 BD |
1053 | else |
1054 | epsize = 0; | |
1055 | ||
f71b5e25 MYK |
1056 | /* |
1057 | * zero length packet should be programmed on its own and should not | |
1058 | * be counted in DIEPTSIZ.PktCnt with other packets. | |
1059 | */ | |
1060 | if (dir_in && ureq->zero && !continuing) { | |
1061 | /* Test if zlp is actually required. */ | |
1062 | if ((ureq->length >= hs_ep->ep.maxpacket) && | |
9da51974 | 1063 | !(ureq->length % hs_ep->ep.maxpacket)) |
8a20fa45 | 1064 | hs_ep->send_zlp = 1; |
5b7d70c6 BD |
1065 | } |
1066 | ||
47a1685f DN |
1067 | epsize |= DXEPTSIZ_PKTCNT(packets); |
1068 | epsize |= DXEPTSIZ_XFERSIZE(length); | |
5b7d70c6 BD |
1069 | |
1070 | dev_dbg(hsotg->dev, "%s: %d@%d/%d, 0x%08x => 0x%08x\n", | |
1071 | __func__, packets, length, ureq->length, epsize, epsize_reg); | |
1072 | ||
1073 | /* store the request as the current one we're doing */ | |
1074 | hs_ep->req = hs_req; | |
1075 | ||
aa3e8bc8 VA |
1076 | if (using_desc_dma(hsotg)) { |
1077 | u32 offset = 0; | |
1078 | u32 mps = hs_ep->ep.maxpacket; | |
1079 | ||
1080 | /* Adjust length: EP0 - MPS, other OUT EPs - multiple of MPS */ | |
1081 | if (!dir_in) { | |
1082 | if (!index) | |
1083 | length = mps; | |
1084 | else if (length % mps) | |
1085 | length += (mps - (length % mps)); | |
1086 | } | |
5b7d70c6 | 1087 | |
8b9bc460 | 1088 | /* |
aa3e8bc8 VA |
1089 | * If more data to send, adjust DMA for EP0 out data stage. |
1090 | * ureq->dma stays unchanged, hence increment it by already | |
1091 | * passed passed data count before starting new transaction. | |
8b9bc460 | 1092 | */ |
aa3e8bc8 VA |
1093 | if (!index && hsotg->ep0_state == DWC2_EP0_DATA_OUT && |
1094 | continuing) | |
1095 | offset = ureq->actual; | |
1096 | ||
1097 | /* Fill DDMA chain entries */ | |
1098 | dwc2_gadget_config_nonisoc_xfer_ddma(hs_ep, ureq->dma + offset, | |
1099 | length); | |
1100 | ||
1101 | /* write descriptor chain address to control register */ | |
1102 | dwc2_writel(hs_ep->desc_list_dma, hsotg->regs + dma_reg); | |
5b7d70c6 | 1103 | |
aa3e8bc8 VA |
1104 | dev_dbg(hsotg->dev, "%s: %08x pad => 0x%08x\n", |
1105 | __func__, (u32)hs_ep->desc_list_dma, dma_reg); | |
1106 | } else { | |
1107 | /* write size / packets */ | |
1108 | dwc2_writel(epsize, hsotg->regs + epsize_reg); | |
1109 | ||
729e6574 | 1110 | if (using_dma(hsotg) && !continuing && (length != 0)) { |
aa3e8bc8 VA |
1111 | /* |
1112 | * write DMA address to control register, buffer | |
1113 | * already synced by dwc2_hsotg_ep_queue(). | |
1114 | */ | |
5b7d70c6 | 1115 | |
aa3e8bc8 VA |
1116 | dwc2_writel(ureq->dma, hsotg->regs + dma_reg); |
1117 | ||
1118 | dev_dbg(hsotg->dev, "%s: %pad => 0x%08x\n", | |
1119 | __func__, &ureq->dma, dma_reg); | |
1120 | } | |
5b7d70c6 BD |
1121 | } |
1122 | ||
837e9f00 VM |
1123 | if (hs_ep->isochronous && hs_ep->interval == 1) { |
1124 | hs_ep->target_frame = dwc2_hsotg_read_frameno(hsotg); | |
1125 | dwc2_gadget_incr_frame_num(hs_ep); | |
1126 | ||
1127 | if (hs_ep->target_frame & 0x1) | |
1128 | ctrl |= DXEPCTL_SETODDFR; | |
1129 | else | |
1130 | ctrl |= DXEPCTL_SETEVENFR; | |
1131 | } | |
1132 | ||
47a1685f | 1133 | ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */ |
71225bee | 1134 | |
fe0b94ab | 1135 | dev_dbg(hsotg->dev, "ep0 state:%d\n", hsotg->ep0_state); |
71225bee LM |
1136 | |
1137 | /* For Setup request do not clear NAK */ | |
fe0b94ab | 1138 | if (!(index == 0 && hsotg->ep0_state == DWC2_EP0_SETUP)) |
47a1685f | 1139 | ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */ |
71225bee | 1140 | |
5b7d70c6 | 1141 | dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl); |
95c8bc36 | 1142 | dwc2_writel(ctrl, hsotg->regs + epctrl_reg); |
5b7d70c6 | 1143 | |
8b9bc460 LM |
1144 | /* |
1145 | * set these, it seems that DMA support increments past the end | |
5b7d70c6 | 1146 | * of the packet buffer so we need to calculate the length from |
8b9bc460 LM |
1147 | * this information. |
1148 | */ | |
5b7d70c6 BD |
1149 | hs_ep->size_loaded = length; |
1150 | hs_ep->last_load = ureq->actual; | |
1151 | ||
1152 | if (dir_in && !using_dma(hsotg)) { | |
1153 | /* set these anyway, we may need them for non-periodic in */ | |
1154 | hs_ep->fifo_load = 0; | |
1155 | ||
1f91b4cc | 1156 | dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req); |
5b7d70c6 BD |
1157 | } |
1158 | ||
8b9bc460 LM |
1159 | /* |
1160 | * Note, trying to clear the NAK here causes problems with transmit | |
1161 | * on the S3C6400 ending up with the TXFIFO becoming full. | |
1162 | */ | |
5b7d70c6 BD |
1163 | |
1164 | /* check ep is enabled */ | |
95c8bc36 | 1165 | if (!(dwc2_readl(hsotg->regs + epctrl_reg) & DXEPCTL_EPENA)) |
1a0ed863 | 1166 | dev_dbg(hsotg->dev, |
9da51974 | 1167 | "ep%d: failed to become enabled (DXEPCTL=0x%08x)?\n", |
95c8bc36 | 1168 | index, dwc2_readl(hsotg->regs + epctrl_reg)); |
5b7d70c6 | 1169 | |
47a1685f | 1170 | dev_dbg(hsotg->dev, "%s: DXEPCTL=0x%08x\n", |
95c8bc36 | 1171 | __func__, dwc2_readl(hsotg->regs + epctrl_reg)); |
afcf4169 RB |
1172 | |
1173 | /* enable ep interrupts */ | |
1f91b4cc | 1174 | dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 1); |
5b7d70c6 BD |
1175 | } |
1176 | ||
1177 | /** | |
1f91b4cc | 1178 | * dwc2_hsotg_map_dma - map the DMA memory being used for the request |
5b7d70c6 BD |
1179 | * @hsotg: The device state. |
1180 | * @hs_ep: The endpoint the request is on. | |
1181 | * @req: The request being processed. | |
1182 | * | |
1183 | * We've been asked to queue a request, so ensure that the memory buffer | |
1184 | * is correctly setup for DMA. If we've been passed an extant DMA address | |
1185 | * then ensure the buffer has been synced to memory. If our buffer has no | |
1186 | * DMA memory, then we map the memory and mark our request to allow us to | |
1187 | * cleanup on completion. | |
8b9bc460 | 1188 | */ |
1f91b4cc | 1189 | static int dwc2_hsotg_map_dma(struct dwc2_hsotg *hsotg, |
9da51974 | 1190 | struct dwc2_hsotg_ep *hs_ep, |
5b7d70c6 BD |
1191 | struct usb_request *req) |
1192 | { | |
e58ebcd1 | 1193 | int ret; |
5b7d70c6 | 1194 | |
e58ebcd1 FB |
1195 | ret = usb_gadget_map_request(&hsotg->gadget, req, hs_ep->dir_in); |
1196 | if (ret) | |
1197 | goto dma_error; | |
5b7d70c6 BD |
1198 | |
1199 | return 0; | |
1200 | ||
1201 | dma_error: | |
1202 | dev_err(hsotg->dev, "%s: failed to map buffer %p, %d bytes\n", | |
1203 | __func__, req->buf, req->length); | |
1204 | ||
1205 | return -EIO; | |
1206 | } | |
1207 | ||
1f91b4cc | 1208 | static int dwc2_hsotg_handle_unaligned_buf_start(struct dwc2_hsotg *hsotg, |
b98866c2 JY |
1209 | struct dwc2_hsotg_ep *hs_ep, |
1210 | struct dwc2_hsotg_req *hs_req) | |
7d24c1b5 MYK |
1211 | { |
1212 | void *req_buf = hs_req->req.buf; | |
1213 | ||
1214 | /* If dma is not being used or buffer is aligned */ | |
1215 | if (!using_dma(hsotg) || !((long)req_buf & 3)) | |
1216 | return 0; | |
1217 | ||
1218 | WARN_ON(hs_req->saved_req_buf); | |
1219 | ||
1220 | dev_dbg(hsotg->dev, "%s: %s: buf=%p length=%d\n", __func__, | |
9da51974 | 1221 | hs_ep->ep.name, req_buf, hs_req->req.length); |
7d24c1b5 MYK |
1222 | |
1223 | hs_req->req.buf = kmalloc(hs_req->req.length, GFP_ATOMIC); | |
1224 | if (!hs_req->req.buf) { | |
1225 | hs_req->req.buf = req_buf; | |
1226 | dev_err(hsotg->dev, | |
1227 | "%s: unable to allocate memory for bounce buffer\n", | |
1228 | __func__); | |
1229 | return -ENOMEM; | |
1230 | } | |
1231 | ||
1232 | /* Save actual buffer */ | |
1233 | hs_req->saved_req_buf = req_buf; | |
1234 | ||
1235 | if (hs_ep->dir_in) | |
1236 | memcpy(hs_req->req.buf, req_buf, hs_req->req.length); | |
1237 | return 0; | |
1238 | } | |
1239 | ||
b98866c2 JY |
1240 | static void |
1241 | dwc2_hsotg_handle_unaligned_buf_complete(struct dwc2_hsotg *hsotg, | |
1242 | struct dwc2_hsotg_ep *hs_ep, | |
1243 | struct dwc2_hsotg_req *hs_req) | |
7d24c1b5 MYK |
1244 | { |
1245 | /* If dma is not being used or buffer was aligned */ | |
1246 | if (!using_dma(hsotg) || !hs_req->saved_req_buf) | |
1247 | return; | |
1248 | ||
1249 | dev_dbg(hsotg->dev, "%s: %s: status=%d actual-length=%d\n", __func__, | |
1250 | hs_ep->ep.name, hs_req->req.status, hs_req->req.actual); | |
1251 | ||
1252 | /* Copy data from bounce buffer on successful out transfer */ | |
1253 | if (!hs_ep->dir_in && !hs_req->req.status) | |
1254 | memcpy(hs_req->saved_req_buf, hs_req->req.buf, | |
9da51974 | 1255 | hs_req->req.actual); |
7d24c1b5 MYK |
1256 | |
1257 | /* Free bounce buffer */ | |
1258 | kfree(hs_req->req.buf); | |
1259 | ||
1260 | hs_req->req.buf = hs_req->saved_req_buf; | |
1261 | hs_req->saved_req_buf = NULL; | |
1262 | } | |
1263 | ||
381fc8f8 VM |
1264 | /** |
1265 | * dwc2_gadget_target_frame_elapsed - Checks target frame | |
1266 | * @hs_ep: The driver endpoint to check | |
1267 | * | |
1268 | * Returns 1 if targeted frame elapsed. If returned 1 then we need to drop | |
1269 | * corresponding transfer. | |
1270 | */ | |
1271 | static bool dwc2_gadget_target_frame_elapsed(struct dwc2_hsotg_ep *hs_ep) | |
1272 | { | |
1273 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
1274 | u32 target_frame = hs_ep->target_frame; | |
1275 | u32 current_frame = dwc2_hsotg_read_frameno(hsotg); | |
1276 | bool frame_overrun = hs_ep->frame_overrun; | |
1277 | ||
1278 | if (!frame_overrun && current_frame >= target_frame) | |
1279 | return true; | |
1280 | ||
1281 | if (frame_overrun && current_frame >= target_frame && | |
1282 | ((current_frame - target_frame) < DSTS_SOFFN_LIMIT / 2)) | |
1283 | return true; | |
1284 | ||
1285 | return false; | |
1286 | } | |
1287 | ||
e02f9aa6 VA |
1288 | /* |
1289 | * dwc2_gadget_set_ep0_desc_chain - Set EP's desc chain pointers | |
1290 | * @hsotg: The driver state | |
1291 | * @hs_ep: the ep descriptor chain is for | |
1292 | * | |
1293 | * Called to update EP0 structure's pointers depend on stage of | |
1294 | * control transfer. | |
1295 | */ | |
1296 | static int dwc2_gadget_set_ep0_desc_chain(struct dwc2_hsotg *hsotg, | |
1297 | struct dwc2_hsotg_ep *hs_ep) | |
1298 | { | |
1299 | switch (hsotg->ep0_state) { | |
1300 | case DWC2_EP0_SETUP: | |
1301 | case DWC2_EP0_STATUS_OUT: | |
1302 | hs_ep->desc_list = hsotg->setup_desc[0]; | |
1303 | hs_ep->desc_list_dma = hsotg->setup_desc_dma[0]; | |
1304 | break; | |
1305 | case DWC2_EP0_DATA_IN: | |
1306 | case DWC2_EP0_STATUS_IN: | |
1307 | hs_ep->desc_list = hsotg->ctrl_in_desc; | |
1308 | hs_ep->desc_list_dma = hsotg->ctrl_in_desc_dma; | |
1309 | break; | |
1310 | case DWC2_EP0_DATA_OUT: | |
1311 | hs_ep->desc_list = hsotg->ctrl_out_desc; | |
1312 | hs_ep->desc_list_dma = hsotg->ctrl_out_desc_dma; | |
1313 | break; | |
1314 | default: | |
1315 | dev_err(hsotg->dev, "invalid EP 0 state in queue %d\n", | |
1316 | hsotg->ep0_state); | |
1317 | return -EINVAL; | |
1318 | } | |
1319 | ||
1320 | return 0; | |
1321 | } | |
1322 | ||
1f91b4cc | 1323 | static int dwc2_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req, |
9da51974 | 1324 | gfp_t gfp_flags) |
5b7d70c6 | 1325 | { |
1f91b4cc FB |
1326 | struct dwc2_hsotg_req *hs_req = our_req(req); |
1327 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); | |
941fcce4 | 1328 | struct dwc2_hsotg *hs = hs_ep->parent; |
5b7d70c6 | 1329 | bool first; |
7d24c1b5 | 1330 | int ret; |
5b7d70c6 BD |
1331 | |
1332 | dev_dbg(hs->dev, "%s: req %p: %d@%p, noi=%d, zero=%d, snok=%d\n", | |
1333 | ep->name, req, req->length, req->buf, req->no_interrupt, | |
1334 | req->zero, req->short_not_ok); | |
1335 | ||
7ababa92 GH |
1336 | /* Prevent new request submission when controller is suspended */ |
1337 | if (hs->lx_state == DWC2_L2) { | |
1338 | dev_dbg(hs->dev, "%s: don't submit request while suspended\n", | |
9da51974 | 1339 | __func__); |
7ababa92 GH |
1340 | return -EAGAIN; |
1341 | } | |
1342 | ||
5b7d70c6 BD |
1343 | /* initialise status of the request */ |
1344 | INIT_LIST_HEAD(&hs_req->queue); | |
1345 | req->actual = 0; | |
1346 | req->status = -EINPROGRESS; | |
1347 | ||
1f91b4cc | 1348 | ret = dwc2_hsotg_handle_unaligned_buf_start(hs, hs_ep, hs_req); |
7d24c1b5 MYK |
1349 | if (ret) |
1350 | return ret; | |
1351 | ||
5b7d70c6 BD |
1352 | /* if we're using DMA, sync the buffers as necessary */ |
1353 | if (using_dma(hs)) { | |
1f91b4cc | 1354 | ret = dwc2_hsotg_map_dma(hs, hs_ep, req); |
5b7d70c6 BD |
1355 | if (ret) |
1356 | return ret; | |
1357 | } | |
e02f9aa6 VA |
1358 | /* If using descriptor DMA configure EP0 descriptor chain pointers */ |
1359 | if (using_desc_dma(hs) && !hs_ep->index) { | |
1360 | ret = dwc2_gadget_set_ep0_desc_chain(hs, hs_ep); | |
1361 | if (ret) | |
1362 | return ret; | |
1363 | } | |
5b7d70c6 | 1364 | |
5b7d70c6 BD |
1365 | first = list_empty(&hs_ep->queue); |
1366 | list_add_tail(&hs_req->queue, &hs_ep->queue); | |
1367 | ||
540ccba0 VA |
1368 | /* |
1369 | * Handle DDMA isochronous transfers separately - just add new entry | |
1370 | * to the half of descriptor chain that is not processed by HW. | |
1371 | * Transfer will be started once SW gets either one of NAK or | |
1372 | * OutTknEpDis interrupts. | |
1373 | */ | |
1374 | if (using_desc_dma(hs) && hs_ep->isochronous && | |
1375 | hs_ep->target_frame != TARGET_FRAME_INITIAL) { | |
1376 | ret = dwc2_gadget_fill_isoc_desc(hs_ep, hs_req->req.dma, | |
1377 | hs_req->req.length); | |
1378 | if (ret) | |
1379 | dev_dbg(hs->dev, "%s: ISO desc chain full\n", __func__); | |
1380 | ||
1381 | return 0; | |
1382 | } | |
1383 | ||
837e9f00 VM |
1384 | if (first) { |
1385 | if (!hs_ep->isochronous) { | |
1386 | dwc2_hsotg_start_req(hs, hs_ep, hs_req, false); | |
1387 | return 0; | |
1388 | } | |
1389 | ||
1390 | while (dwc2_gadget_target_frame_elapsed(hs_ep)) | |
1391 | dwc2_gadget_incr_frame_num(hs_ep); | |
5b7d70c6 | 1392 | |
837e9f00 VM |
1393 | if (hs_ep->target_frame != TARGET_FRAME_INITIAL) |
1394 | dwc2_hsotg_start_req(hs, hs_ep, hs_req, false); | |
1395 | } | |
5b7d70c6 BD |
1396 | return 0; |
1397 | } | |
1398 | ||
1f91b4cc | 1399 | static int dwc2_hsotg_ep_queue_lock(struct usb_ep *ep, struct usb_request *req, |
9da51974 | 1400 | gfp_t gfp_flags) |
5ad1d316 | 1401 | { |
1f91b4cc | 1402 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 1403 | struct dwc2_hsotg *hs = hs_ep->parent; |
5ad1d316 LM |
1404 | unsigned long flags = 0; |
1405 | int ret = 0; | |
1406 | ||
1407 | spin_lock_irqsave(&hs->lock, flags); | |
1f91b4cc | 1408 | ret = dwc2_hsotg_ep_queue(ep, req, gfp_flags); |
5ad1d316 LM |
1409 | spin_unlock_irqrestore(&hs->lock, flags); |
1410 | ||
1411 | return ret; | |
1412 | } | |
1413 | ||
1f91b4cc | 1414 | static void dwc2_hsotg_ep_free_request(struct usb_ep *ep, |
9da51974 | 1415 | struct usb_request *req) |
5b7d70c6 | 1416 | { |
1f91b4cc | 1417 | struct dwc2_hsotg_req *hs_req = our_req(req); |
5b7d70c6 BD |
1418 | |
1419 | kfree(hs_req); | |
1420 | } | |
1421 | ||
1422 | /** | |
1f91b4cc | 1423 | * dwc2_hsotg_complete_oursetup - setup completion callback |
5b7d70c6 BD |
1424 | * @ep: The endpoint the request was on. |
1425 | * @req: The request completed. | |
1426 | * | |
1427 | * Called on completion of any requests the driver itself | |
1428 | * submitted that need cleaning up. | |
1429 | */ | |
1f91b4cc | 1430 | static void dwc2_hsotg_complete_oursetup(struct usb_ep *ep, |
9da51974 | 1431 | struct usb_request *req) |
5b7d70c6 | 1432 | { |
1f91b4cc | 1433 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 1434 | struct dwc2_hsotg *hsotg = hs_ep->parent; |
5b7d70c6 BD |
1435 | |
1436 | dev_dbg(hsotg->dev, "%s: ep %p, req %p\n", __func__, ep, req); | |
1437 | ||
1f91b4cc | 1438 | dwc2_hsotg_ep_free_request(ep, req); |
5b7d70c6 BD |
1439 | } |
1440 | ||
1441 | /** | |
1442 | * ep_from_windex - convert control wIndex value to endpoint | |
1443 | * @hsotg: The driver state. | |
1444 | * @windex: The control request wIndex field (in host order). | |
1445 | * | |
1446 | * Convert the given wIndex into a pointer to an driver endpoint | |
1447 | * structure, or return NULL if it is not a valid endpoint. | |
8b9bc460 | 1448 | */ |
1f91b4cc | 1449 | static struct dwc2_hsotg_ep *ep_from_windex(struct dwc2_hsotg *hsotg, |
9da51974 | 1450 | u32 windex) |
5b7d70c6 | 1451 | { |
1f91b4cc | 1452 | struct dwc2_hsotg_ep *ep; |
5b7d70c6 BD |
1453 | int dir = (windex & USB_DIR_IN) ? 1 : 0; |
1454 | int idx = windex & 0x7F; | |
1455 | ||
1456 | if (windex >= 0x100) | |
1457 | return NULL; | |
1458 | ||
b3f489b2 | 1459 | if (idx > hsotg->num_of_eps) |
5b7d70c6 BD |
1460 | return NULL; |
1461 | ||
c6f5c050 MYK |
1462 | ep = index_to_ep(hsotg, idx, dir); |
1463 | ||
5b7d70c6 BD |
1464 | if (idx && ep->dir_in != dir) |
1465 | return NULL; | |
1466 | ||
1467 | return ep; | |
1468 | } | |
1469 | ||
9e14d0a5 | 1470 | /** |
1f91b4cc | 1471 | * dwc2_hsotg_set_test_mode - Enable usb Test Modes |
9e14d0a5 GH |
1472 | * @hsotg: The driver state. |
1473 | * @testmode: requested usb test mode | |
1474 | * Enable usb Test Mode requested by the Host. | |
1475 | */ | |
1f91b4cc | 1476 | int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode) |
9e14d0a5 | 1477 | { |
95c8bc36 | 1478 | int dctl = dwc2_readl(hsotg->regs + DCTL); |
9e14d0a5 GH |
1479 | |
1480 | dctl &= ~DCTL_TSTCTL_MASK; | |
1481 | switch (testmode) { | |
1482 | case TEST_J: | |
1483 | case TEST_K: | |
1484 | case TEST_SE0_NAK: | |
1485 | case TEST_PACKET: | |
1486 | case TEST_FORCE_EN: | |
1487 | dctl |= testmode << DCTL_TSTCTL_SHIFT; | |
1488 | break; | |
1489 | default: | |
1490 | return -EINVAL; | |
1491 | } | |
95c8bc36 | 1492 | dwc2_writel(dctl, hsotg->regs + DCTL); |
9e14d0a5 GH |
1493 | return 0; |
1494 | } | |
1495 | ||
5b7d70c6 | 1496 | /** |
1f91b4cc | 1497 | * dwc2_hsotg_send_reply - send reply to control request |
5b7d70c6 BD |
1498 | * @hsotg: The device state |
1499 | * @ep: Endpoint 0 | |
1500 | * @buff: Buffer for request | |
1501 | * @length: Length of reply. | |
1502 | * | |
1503 | * Create a request and queue it on the given endpoint. This is useful as | |
1504 | * an internal method of sending replies to certain control requests, etc. | |
1505 | */ | |
1f91b4cc | 1506 | static int dwc2_hsotg_send_reply(struct dwc2_hsotg *hsotg, |
9da51974 | 1507 | struct dwc2_hsotg_ep *ep, |
5b7d70c6 BD |
1508 | void *buff, |
1509 | int length) | |
1510 | { | |
1511 | struct usb_request *req; | |
1512 | int ret; | |
1513 | ||
1514 | dev_dbg(hsotg->dev, "%s: buff %p, len %d\n", __func__, buff, length); | |
1515 | ||
1f91b4cc | 1516 | req = dwc2_hsotg_ep_alloc_request(&ep->ep, GFP_ATOMIC); |
5b7d70c6 BD |
1517 | hsotg->ep0_reply = req; |
1518 | if (!req) { | |
1519 | dev_warn(hsotg->dev, "%s: cannot alloc req\n", __func__); | |
1520 | return -ENOMEM; | |
1521 | } | |
1522 | ||
1523 | req->buf = hsotg->ep0_buff; | |
1524 | req->length = length; | |
f71b5e25 MYK |
1525 | /* |
1526 | * zero flag is for sending zlp in DATA IN stage. It has no impact on | |
1527 | * STATUS stage. | |
1528 | */ | |
1529 | req->zero = 0; | |
1f91b4cc | 1530 | req->complete = dwc2_hsotg_complete_oursetup; |
5b7d70c6 BD |
1531 | |
1532 | if (length) | |
1533 | memcpy(req->buf, buff, length); | |
5b7d70c6 | 1534 | |
1f91b4cc | 1535 | ret = dwc2_hsotg_ep_queue(&ep->ep, req, GFP_ATOMIC); |
5b7d70c6 BD |
1536 | if (ret) { |
1537 | dev_warn(hsotg->dev, "%s: cannot queue req\n", __func__); | |
1538 | return ret; | |
1539 | } | |
1540 | ||
1541 | return 0; | |
1542 | } | |
1543 | ||
1544 | /** | |
1f91b4cc | 1545 | * dwc2_hsotg_process_req_status - process request GET_STATUS |
5b7d70c6 BD |
1546 | * @hsotg: The device state |
1547 | * @ctrl: USB control request | |
1548 | */ | |
1f91b4cc | 1549 | static int dwc2_hsotg_process_req_status(struct dwc2_hsotg *hsotg, |
9da51974 | 1550 | struct usb_ctrlrequest *ctrl) |
5b7d70c6 | 1551 | { |
1f91b4cc FB |
1552 | struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0]; |
1553 | struct dwc2_hsotg_ep *ep; | |
5b7d70c6 BD |
1554 | __le16 reply; |
1555 | int ret; | |
1556 | ||
1557 | dev_dbg(hsotg->dev, "%s: USB_REQ_GET_STATUS\n", __func__); | |
1558 | ||
1559 | if (!ep0->dir_in) { | |
1560 | dev_warn(hsotg->dev, "%s: direction out?\n", __func__); | |
1561 | return -EINVAL; | |
1562 | } | |
1563 | ||
1564 | switch (ctrl->bRequestType & USB_RECIP_MASK) { | |
1565 | case USB_RECIP_DEVICE: | |
38beaec6 JY |
1566 | /* |
1567 | * bit 0 => self powered | |
1568 | * bit 1 => remote wakeup | |
1569 | */ | |
1570 | reply = cpu_to_le16(0); | |
5b7d70c6 BD |
1571 | break; |
1572 | ||
1573 | case USB_RECIP_INTERFACE: | |
1574 | /* currently, the data result should be zero */ | |
1575 | reply = cpu_to_le16(0); | |
1576 | break; | |
1577 | ||
1578 | case USB_RECIP_ENDPOINT: | |
1579 | ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex)); | |
1580 | if (!ep) | |
1581 | return -ENOENT; | |
1582 | ||
1583 | reply = cpu_to_le16(ep->halted ? 1 : 0); | |
1584 | break; | |
1585 | ||
1586 | default: | |
1587 | return 0; | |
1588 | } | |
1589 | ||
1590 | if (le16_to_cpu(ctrl->wLength) != 2) | |
1591 | return -EINVAL; | |
1592 | ||
1f91b4cc | 1593 | ret = dwc2_hsotg_send_reply(hsotg, ep0, &reply, 2); |
5b7d70c6 BD |
1594 | if (ret) { |
1595 | dev_err(hsotg->dev, "%s: failed to send reply\n", __func__); | |
1596 | return ret; | |
1597 | } | |
1598 | ||
1599 | return 1; | |
1600 | } | |
1601 | ||
51da43b5 | 1602 | static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now); |
5b7d70c6 | 1603 | |
9c39ddc6 AT |
1604 | /** |
1605 | * get_ep_head - return the first request on the endpoint | |
1606 | * @hs_ep: The controller endpoint to get | |
1607 | * | |
1608 | * Get the first request on the endpoint. | |
1609 | */ | |
1f91b4cc | 1610 | static struct dwc2_hsotg_req *get_ep_head(struct dwc2_hsotg_ep *hs_ep) |
9c39ddc6 | 1611 | { |
ffc4b406 MY |
1612 | return list_first_entry_or_null(&hs_ep->queue, struct dwc2_hsotg_req, |
1613 | queue); | |
9c39ddc6 AT |
1614 | } |
1615 | ||
41cc4cd2 VM |
1616 | /** |
1617 | * dwc2_gadget_start_next_request - Starts next request from ep queue | |
1618 | * @hs_ep: Endpoint structure | |
1619 | * | |
1620 | * If queue is empty and EP is ISOC-OUT - unmasks OUTTKNEPDIS which is masked | |
1621 | * in its handler. Hence we need to unmask it here to be able to do | |
1622 | * resynchronization. | |
1623 | */ | |
1624 | static void dwc2_gadget_start_next_request(struct dwc2_hsotg_ep *hs_ep) | |
1625 | { | |
1626 | u32 mask; | |
1627 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
1628 | int dir_in = hs_ep->dir_in; | |
1629 | struct dwc2_hsotg_req *hs_req; | |
1630 | u32 epmsk_reg = dir_in ? DIEPMSK : DOEPMSK; | |
1631 | ||
1632 | if (!list_empty(&hs_ep->queue)) { | |
1633 | hs_req = get_ep_head(hs_ep); | |
1634 | dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, false); | |
1635 | return; | |
1636 | } | |
1637 | if (!hs_ep->isochronous) | |
1638 | return; | |
1639 | ||
1640 | if (dir_in) { | |
1641 | dev_dbg(hsotg->dev, "%s: No more ISOC-IN requests\n", | |
1642 | __func__); | |
1643 | } else { | |
1644 | dev_dbg(hsotg->dev, "%s: No more ISOC-OUT requests\n", | |
1645 | __func__); | |
1646 | mask = dwc2_readl(hsotg->regs + epmsk_reg); | |
1647 | mask |= DOEPMSK_OUTTKNEPDISMSK; | |
1648 | dwc2_writel(mask, hsotg->regs + epmsk_reg); | |
1649 | } | |
1650 | } | |
1651 | ||
5b7d70c6 | 1652 | /** |
1f91b4cc | 1653 | * dwc2_hsotg_process_req_feature - process request {SET,CLEAR}_FEATURE |
5b7d70c6 BD |
1654 | * @hsotg: The device state |
1655 | * @ctrl: USB control request | |
1656 | */ | |
1f91b4cc | 1657 | static int dwc2_hsotg_process_req_feature(struct dwc2_hsotg *hsotg, |
9da51974 | 1658 | struct usb_ctrlrequest *ctrl) |
5b7d70c6 | 1659 | { |
1f91b4cc FB |
1660 | struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0]; |
1661 | struct dwc2_hsotg_req *hs_req; | |
5b7d70c6 | 1662 | bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE); |
1f91b4cc | 1663 | struct dwc2_hsotg_ep *ep; |
26ab3d0c | 1664 | int ret; |
bd9ef7bf | 1665 | bool halted; |
9e14d0a5 GH |
1666 | u32 recip; |
1667 | u32 wValue; | |
1668 | u32 wIndex; | |
5b7d70c6 BD |
1669 | |
1670 | dev_dbg(hsotg->dev, "%s: %s_FEATURE\n", | |
1671 | __func__, set ? "SET" : "CLEAR"); | |
1672 | ||
9e14d0a5 GH |
1673 | wValue = le16_to_cpu(ctrl->wValue); |
1674 | wIndex = le16_to_cpu(ctrl->wIndex); | |
1675 | recip = ctrl->bRequestType & USB_RECIP_MASK; | |
1676 | ||
1677 | switch (recip) { | |
1678 | case USB_RECIP_DEVICE: | |
1679 | switch (wValue) { | |
1680 | case USB_DEVICE_TEST_MODE: | |
1681 | if ((wIndex & 0xff) != 0) | |
1682 | return -EINVAL; | |
1683 | if (!set) | |
1684 | return -EINVAL; | |
1685 | ||
1686 | hsotg->test_mode = wIndex >> 8; | |
1f91b4cc | 1687 | ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0); |
9e14d0a5 GH |
1688 | if (ret) { |
1689 | dev_err(hsotg->dev, | |
1690 | "%s: failed to send reply\n", __func__); | |
1691 | return ret; | |
1692 | } | |
1693 | break; | |
1694 | default: | |
1695 | return -ENOENT; | |
1696 | } | |
1697 | break; | |
1698 | ||
1699 | case USB_RECIP_ENDPOINT: | |
1700 | ep = ep_from_windex(hsotg, wIndex); | |
5b7d70c6 BD |
1701 | if (!ep) { |
1702 | dev_dbg(hsotg->dev, "%s: no endpoint for 0x%04x\n", | |
9e14d0a5 | 1703 | __func__, wIndex); |
5b7d70c6 BD |
1704 | return -ENOENT; |
1705 | } | |
1706 | ||
9e14d0a5 | 1707 | switch (wValue) { |
5b7d70c6 | 1708 | case USB_ENDPOINT_HALT: |
bd9ef7bf RB |
1709 | halted = ep->halted; |
1710 | ||
51da43b5 | 1711 | dwc2_hsotg_ep_sethalt(&ep->ep, set, true); |
26ab3d0c | 1712 | |
1f91b4cc | 1713 | ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0); |
26ab3d0c AT |
1714 | if (ret) { |
1715 | dev_err(hsotg->dev, | |
1716 | "%s: failed to send reply\n", __func__); | |
1717 | return ret; | |
1718 | } | |
9c39ddc6 | 1719 | |
bd9ef7bf RB |
1720 | /* |
1721 | * we have to complete all requests for ep if it was | |
1722 | * halted, and the halt was cleared by CLEAR_FEATURE | |
1723 | */ | |
1724 | ||
1725 | if (!set && halted) { | |
9c39ddc6 AT |
1726 | /* |
1727 | * If we have request in progress, | |
1728 | * then complete it | |
1729 | */ | |
1730 | if (ep->req) { | |
1731 | hs_req = ep->req; | |
1732 | ep->req = NULL; | |
1733 | list_del_init(&hs_req->queue); | |
c00dd4a6 GH |
1734 | if (hs_req->req.complete) { |
1735 | spin_unlock(&hsotg->lock); | |
1736 | usb_gadget_giveback_request( | |
1737 | &ep->ep, &hs_req->req); | |
1738 | spin_lock(&hsotg->lock); | |
1739 | } | |
9c39ddc6 AT |
1740 | } |
1741 | ||
1742 | /* If we have pending request, then start it */ | |
34c0887f | 1743 | if (!ep->req) |
41cc4cd2 | 1744 | dwc2_gadget_start_next_request(ep); |
9c39ddc6 AT |
1745 | } |
1746 | ||
5b7d70c6 BD |
1747 | break; |
1748 | ||
1749 | default: | |
1750 | return -ENOENT; | |
1751 | } | |
9e14d0a5 GH |
1752 | break; |
1753 | default: | |
1754 | return -ENOENT; | |
1755 | } | |
5b7d70c6 BD |
1756 | return 1; |
1757 | } | |
1758 | ||
1f91b4cc | 1759 | static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg); |
ab93e014 | 1760 | |
c9f721b2 | 1761 | /** |
1f91b4cc | 1762 | * dwc2_hsotg_stall_ep0 - stall ep0 |
c9f721b2 RB |
1763 | * @hsotg: The device state |
1764 | * | |
1765 | * Set stall for ep0 as response for setup request. | |
1766 | */ | |
1f91b4cc | 1767 | static void dwc2_hsotg_stall_ep0(struct dwc2_hsotg *hsotg) |
e9ebe7c3 | 1768 | { |
1f91b4cc | 1769 | struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0]; |
c9f721b2 RB |
1770 | u32 reg; |
1771 | u32 ctrl; | |
1772 | ||
1773 | dev_dbg(hsotg->dev, "ep0 stall (dir=%d)\n", ep0->dir_in); | |
1774 | reg = (ep0->dir_in) ? DIEPCTL0 : DOEPCTL0; | |
1775 | ||
1776 | /* | |
1777 | * DxEPCTL_Stall will be cleared by EP once it has | |
1778 | * taken effect, so no need to clear later. | |
1779 | */ | |
1780 | ||
95c8bc36 | 1781 | ctrl = dwc2_readl(hsotg->regs + reg); |
47a1685f DN |
1782 | ctrl |= DXEPCTL_STALL; |
1783 | ctrl |= DXEPCTL_CNAK; | |
95c8bc36 | 1784 | dwc2_writel(ctrl, hsotg->regs + reg); |
c9f721b2 RB |
1785 | |
1786 | dev_dbg(hsotg->dev, | |
47a1685f | 1787 | "written DXEPCTL=0x%08x to %08x (DXEPCTL=0x%08x)\n", |
95c8bc36 | 1788 | ctrl, reg, dwc2_readl(hsotg->regs + reg)); |
c9f721b2 RB |
1789 | |
1790 | /* | |
1791 | * complete won't be called, so we enqueue | |
1792 | * setup request here | |
1793 | */ | |
1f91b4cc | 1794 | dwc2_hsotg_enqueue_setup(hsotg); |
c9f721b2 RB |
1795 | } |
1796 | ||
5b7d70c6 | 1797 | /** |
1f91b4cc | 1798 | * dwc2_hsotg_process_control - process a control request |
5b7d70c6 BD |
1799 | * @hsotg: The device state |
1800 | * @ctrl: The control request received | |
1801 | * | |
1802 | * The controller has received the SETUP phase of a control request, and | |
1803 | * needs to work out what to do next (and whether to pass it on to the | |
1804 | * gadget driver). | |
1805 | */ | |
1f91b4cc | 1806 | static void dwc2_hsotg_process_control(struct dwc2_hsotg *hsotg, |
9da51974 | 1807 | struct usb_ctrlrequest *ctrl) |
5b7d70c6 | 1808 | { |
1f91b4cc | 1809 | struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0]; |
5b7d70c6 BD |
1810 | int ret = 0; |
1811 | u32 dcfg; | |
1812 | ||
e525e743 MYK |
1813 | dev_dbg(hsotg->dev, |
1814 | "ctrl Type=%02x, Req=%02x, V=%04x, I=%04x, L=%04x\n", | |
1815 | ctrl->bRequestType, ctrl->bRequest, ctrl->wValue, | |
1816 | ctrl->wIndex, ctrl->wLength); | |
5b7d70c6 | 1817 | |
fe0b94ab MYK |
1818 | if (ctrl->wLength == 0) { |
1819 | ep0->dir_in = 1; | |
1820 | hsotg->ep0_state = DWC2_EP0_STATUS_IN; | |
1821 | } else if (ctrl->bRequestType & USB_DIR_IN) { | |
5b7d70c6 | 1822 | ep0->dir_in = 1; |
fe0b94ab MYK |
1823 | hsotg->ep0_state = DWC2_EP0_DATA_IN; |
1824 | } else { | |
1825 | ep0->dir_in = 0; | |
1826 | hsotg->ep0_state = DWC2_EP0_DATA_OUT; | |
1827 | } | |
5b7d70c6 BD |
1828 | |
1829 | if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) { | |
1830 | switch (ctrl->bRequest) { | |
1831 | case USB_REQ_SET_ADDRESS: | |
6d713c15 | 1832 | hsotg->connected = 1; |
95c8bc36 | 1833 | dcfg = dwc2_readl(hsotg->regs + DCFG); |
47a1685f | 1834 | dcfg &= ~DCFG_DEVADDR_MASK; |
d5dbd3f7 PZ |
1835 | dcfg |= (le16_to_cpu(ctrl->wValue) << |
1836 | DCFG_DEVADDR_SHIFT) & DCFG_DEVADDR_MASK; | |
95c8bc36 | 1837 | dwc2_writel(dcfg, hsotg->regs + DCFG); |
5b7d70c6 BD |
1838 | |
1839 | dev_info(hsotg->dev, "new address %d\n", ctrl->wValue); | |
1840 | ||
1f91b4cc | 1841 | ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0); |
5b7d70c6 BD |
1842 | return; |
1843 | ||
1844 | case USB_REQ_GET_STATUS: | |
1f91b4cc | 1845 | ret = dwc2_hsotg_process_req_status(hsotg, ctrl); |
5b7d70c6 BD |
1846 | break; |
1847 | ||
1848 | case USB_REQ_CLEAR_FEATURE: | |
1849 | case USB_REQ_SET_FEATURE: | |
1f91b4cc | 1850 | ret = dwc2_hsotg_process_req_feature(hsotg, ctrl); |
5b7d70c6 BD |
1851 | break; |
1852 | } | |
1853 | } | |
1854 | ||
1855 | /* as a fallback, try delivering it to the driver to deal with */ | |
1856 | ||
1857 | if (ret == 0 && hsotg->driver) { | |
93f599f2 | 1858 | spin_unlock(&hsotg->lock); |
5b7d70c6 | 1859 | ret = hsotg->driver->setup(&hsotg->gadget, ctrl); |
93f599f2 | 1860 | spin_lock(&hsotg->lock); |
5b7d70c6 BD |
1861 | if (ret < 0) |
1862 | dev_dbg(hsotg->dev, "driver->setup() ret %d\n", ret); | |
1863 | } | |
1864 | ||
8b9bc460 LM |
1865 | /* |
1866 | * the request is either unhandlable, or is not formatted correctly | |
5b7d70c6 BD |
1867 | * so respond with a STALL for the status stage to indicate failure. |
1868 | */ | |
1869 | ||
c9f721b2 | 1870 | if (ret < 0) |
1f91b4cc | 1871 | dwc2_hsotg_stall_ep0(hsotg); |
5b7d70c6 BD |
1872 | } |
1873 | ||
5b7d70c6 | 1874 | /** |
1f91b4cc | 1875 | * dwc2_hsotg_complete_setup - completion of a setup transfer |
5b7d70c6 BD |
1876 | * @ep: The endpoint the request was on. |
1877 | * @req: The request completed. | |
1878 | * | |
1879 | * Called on completion of any requests the driver itself submitted for | |
1880 | * EP0 setup packets | |
1881 | */ | |
1f91b4cc | 1882 | static void dwc2_hsotg_complete_setup(struct usb_ep *ep, |
9da51974 | 1883 | struct usb_request *req) |
5b7d70c6 | 1884 | { |
1f91b4cc | 1885 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 1886 | struct dwc2_hsotg *hsotg = hs_ep->parent; |
5b7d70c6 BD |
1887 | |
1888 | if (req->status < 0) { | |
1889 | dev_dbg(hsotg->dev, "%s: failed %d\n", __func__, req->status); | |
1890 | return; | |
1891 | } | |
1892 | ||
93f599f2 | 1893 | spin_lock(&hsotg->lock); |
5b7d70c6 | 1894 | if (req->actual == 0) |
1f91b4cc | 1895 | dwc2_hsotg_enqueue_setup(hsotg); |
5b7d70c6 | 1896 | else |
1f91b4cc | 1897 | dwc2_hsotg_process_control(hsotg, req->buf); |
93f599f2 | 1898 | spin_unlock(&hsotg->lock); |
5b7d70c6 BD |
1899 | } |
1900 | ||
1901 | /** | |
1f91b4cc | 1902 | * dwc2_hsotg_enqueue_setup - start a request for EP0 packets |
5b7d70c6 BD |
1903 | * @hsotg: The device state. |
1904 | * | |
1905 | * Enqueue a request on EP0 if necessary to received any SETUP packets | |
1906 | * received from the host. | |
1907 | */ | |
1f91b4cc | 1908 | static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg) |
5b7d70c6 BD |
1909 | { |
1910 | struct usb_request *req = hsotg->ctrl_req; | |
1f91b4cc | 1911 | struct dwc2_hsotg_req *hs_req = our_req(req); |
5b7d70c6 BD |
1912 | int ret; |
1913 | ||
1914 | dev_dbg(hsotg->dev, "%s: queueing setup request\n", __func__); | |
1915 | ||
1916 | req->zero = 0; | |
1917 | req->length = 8; | |
1918 | req->buf = hsotg->ctrl_buff; | |
1f91b4cc | 1919 | req->complete = dwc2_hsotg_complete_setup; |
5b7d70c6 BD |
1920 | |
1921 | if (!list_empty(&hs_req->queue)) { | |
1922 | dev_dbg(hsotg->dev, "%s already queued???\n", __func__); | |
1923 | return; | |
1924 | } | |
1925 | ||
c6f5c050 | 1926 | hsotg->eps_out[0]->dir_in = 0; |
8a20fa45 | 1927 | hsotg->eps_out[0]->send_zlp = 0; |
fe0b94ab | 1928 | hsotg->ep0_state = DWC2_EP0_SETUP; |
5b7d70c6 | 1929 | |
1f91b4cc | 1930 | ret = dwc2_hsotg_ep_queue(&hsotg->eps_out[0]->ep, req, GFP_ATOMIC); |
5b7d70c6 BD |
1931 | if (ret < 0) { |
1932 | dev_err(hsotg->dev, "%s: failed queue (%d)\n", __func__, ret); | |
8b9bc460 LM |
1933 | /* |
1934 | * Don't think there's much we can do other than watch the | |
1935 | * driver fail. | |
1936 | */ | |
5b7d70c6 BD |
1937 | } |
1938 | } | |
1939 | ||
1f91b4cc | 1940 | static void dwc2_hsotg_program_zlp(struct dwc2_hsotg *hsotg, |
9da51974 | 1941 | struct dwc2_hsotg_ep *hs_ep) |
fe0b94ab MYK |
1942 | { |
1943 | u32 ctrl; | |
1944 | u8 index = hs_ep->index; | |
1945 | u32 epctl_reg = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index); | |
1946 | u32 epsiz_reg = hs_ep->dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index); | |
1947 | ||
ccb34a91 MYK |
1948 | if (hs_ep->dir_in) |
1949 | dev_dbg(hsotg->dev, "Sending zero-length packet on ep%d\n", | |
e02f9aa6 | 1950 | index); |
ccb34a91 MYK |
1951 | else |
1952 | dev_dbg(hsotg->dev, "Receiving zero-length packet on ep%d\n", | |
e02f9aa6 VA |
1953 | index); |
1954 | if (using_desc_dma(hsotg)) { | |
1955 | /* Not specific buffer needed for ep0 ZLP */ | |
1956 | dma_addr_t dma = hs_ep->desc_list_dma; | |
fe0b94ab | 1957 | |
e02f9aa6 VA |
1958 | dwc2_gadget_set_ep0_desc_chain(hsotg, hs_ep); |
1959 | dwc2_gadget_config_nonisoc_xfer_ddma(hs_ep, dma, 0); | |
1960 | } else { | |
1961 | dwc2_writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) | | |
1962 | DXEPTSIZ_XFERSIZE(0), hsotg->regs + | |
1963 | epsiz_reg); | |
1964 | } | |
fe0b94ab | 1965 | |
95c8bc36 | 1966 | ctrl = dwc2_readl(hsotg->regs + epctl_reg); |
fe0b94ab MYK |
1967 | ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */ |
1968 | ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */ | |
1969 | ctrl |= DXEPCTL_USBACTEP; | |
95c8bc36 | 1970 | dwc2_writel(ctrl, hsotg->regs + epctl_reg); |
fe0b94ab MYK |
1971 | } |
1972 | ||
5b7d70c6 | 1973 | /** |
1f91b4cc | 1974 | * dwc2_hsotg_complete_request - complete a request given to us |
5b7d70c6 BD |
1975 | * @hsotg: The device state. |
1976 | * @hs_ep: The endpoint the request was on. | |
1977 | * @hs_req: The request to complete. | |
1978 | * @result: The result code (0 => Ok, otherwise errno) | |
1979 | * | |
1980 | * The given request has finished, so call the necessary completion | |
1981 | * if it has one and then look to see if we can start a new request | |
1982 | * on the endpoint. | |
1983 | * | |
1984 | * Note, expects the ep to already be locked as appropriate. | |
8b9bc460 | 1985 | */ |
1f91b4cc | 1986 | static void dwc2_hsotg_complete_request(struct dwc2_hsotg *hsotg, |
9da51974 | 1987 | struct dwc2_hsotg_ep *hs_ep, |
1f91b4cc | 1988 | struct dwc2_hsotg_req *hs_req, |
5b7d70c6 BD |
1989 | int result) |
1990 | { | |
5b7d70c6 BD |
1991 | if (!hs_req) { |
1992 | dev_dbg(hsotg->dev, "%s: nothing to complete?\n", __func__); | |
1993 | return; | |
1994 | } | |
1995 | ||
1996 | dev_dbg(hsotg->dev, "complete: ep %p %s, req %p, %d => %p\n", | |
1997 | hs_ep, hs_ep->ep.name, hs_req, result, hs_req->req.complete); | |
1998 | ||
8b9bc460 LM |
1999 | /* |
2000 | * only replace the status if we've not already set an error | |
2001 | * from a previous transaction | |
2002 | */ | |
5b7d70c6 BD |
2003 | |
2004 | if (hs_req->req.status == -EINPROGRESS) | |
2005 | hs_req->req.status = result; | |
2006 | ||
44583fec YL |
2007 | if (using_dma(hsotg)) |
2008 | dwc2_hsotg_unmap_dma(hsotg, hs_ep, hs_req); | |
2009 | ||
1f91b4cc | 2010 | dwc2_hsotg_handle_unaligned_buf_complete(hsotg, hs_ep, hs_req); |
7d24c1b5 | 2011 | |
5b7d70c6 BD |
2012 | hs_ep->req = NULL; |
2013 | list_del_init(&hs_req->queue); | |
2014 | ||
8b9bc460 LM |
2015 | /* |
2016 | * call the complete request with the locks off, just in case the | |
2017 | * request tries to queue more work for this endpoint. | |
2018 | */ | |
5b7d70c6 BD |
2019 | |
2020 | if (hs_req->req.complete) { | |
22258f49 | 2021 | spin_unlock(&hsotg->lock); |
304f7e5e | 2022 | usb_gadget_giveback_request(&hs_ep->ep, &hs_req->req); |
22258f49 | 2023 | spin_lock(&hsotg->lock); |
5b7d70c6 BD |
2024 | } |
2025 | ||
540ccba0 VA |
2026 | /* In DDMA don't need to proceed to starting of next ISOC request */ |
2027 | if (using_desc_dma(hsotg) && hs_ep->isochronous) | |
2028 | return; | |
2029 | ||
8b9bc460 LM |
2030 | /* |
2031 | * Look to see if there is anything else to do. Note, the completion | |
5b7d70c6 | 2032 | * of the previous request may have caused a new request to be started |
8b9bc460 LM |
2033 | * so be careful when doing this. |
2034 | */ | |
5b7d70c6 | 2035 | |
34c0887f | 2036 | if (!hs_ep->req && result >= 0) |
41cc4cd2 | 2037 | dwc2_gadget_start_next_request(hs_ep); |
5b7d70c6 BD |
2038 | } |
2039 | ||
540ccba0 VA |
2040 | /* |
2041 | * dwc2_gadget_complete_isoc_request_ddma - complete an isoc request in DDMA | |
2042 | * @hs_ep: The endpoint the request was on. | |
2043 | * | |
2044 | * Get first request from the ep queue, determine descriptor on which complete | |
2045 | * happened. SW based on isoc_chain_num discovers which half of the descriptor | |
2046 | * chain is currently in use by HW, adjusts dma_address and calculates index | |
2047 | * of completed descriptor based on the value of DEPDMA register. Update actual | |
2048 | * length of request, giveback to gadget. | |
2049 | */ | |
2050 | static void dwc2_gadget_complete_isoc_request_ddma(struct dwc2_hsotg_ep *hs_ep) | |
2051 | { | |
2052 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
2053 | struct dwc2_hsotg_req *hs_req; | |
2054 | struct usb_request *ureq; | |
2055 | int index; | |
2056 | dma_addr_t dma_addr; | |
2057 | u32 dma_reg; | |
2058 | u32 depdma; | |
2059 | u32 desc_sts; | |
2060 | u32 mask; | |
2061 | ||
2062 | hs_req = get_ep_head(hs_ep); | |
2063 | if (!hs_req) { | |
2064 | dev_warn(hsotg->dev, "%s: ISOC EP queue empty\n", __func__); | |
2065 | return; | |
2066 | } | |
2067 | ureq = &hs_req->req; | |
2068 | ||
2069 | dma_addr = hs_ep->desc_list_dma; | |
2070 | ||
2071 | /* | |
2072 | * If lower half of descriptor chain is currently use by SW, | |
2073 | * that means higher half is being processed by HW, so shift | |
2074 | * DMA address to higher half of descriptor chain. | |
2075 | */ | |
2076 | if (!hs_ep->isoc_chain_num) | |
2077 | dma_addr += sizeof(struct dwc2_dma_desc) * | |
2078 | (MAX_DMA_DESC_NUM_GENERIC / 2); | |
2079 | ||
2080 | dma_reg = hs_ep->dir_in ? DIEPDMA(hs_ep->index) : DOEPDMA(hs_ep->index); | |
2081 | depdma = dwc2_readl(hsotg->regs + dma_reg); | |
2082 | ||
2083 | index = (depdma - dma_addr) / sizeof(struct dwc2_dma_desc) - 1; | |
2084 | desc_sts = hs_ep->desc_list[index].status; | |
2085 | ||
2086 | mask = hs_ep->dir_in ? DEV_DMA_ISOC_TX_NBYTES_MASK : | |
2087 | DEV_DMA_ISOC_RX_NBYTES_MASK; | |
2088 | ureq->actual = ureq->length - | |
2089 | ((desc_sts & mask) >> DEV_DMA_ISOC_NBYTES_SHIFT); | |
2090 | ||
95d2b037 VA |
2091 | /* Adjust actual length for ISOC Out if length is not align of 4 */ |
2092 | if (!hs_ep->dir_in && ureq->length & 0x3) | |
2093 | ureq->actual += 4 - (ureq->length & 0x3); | |
2094 | ||
540ccba0 VA |
2095 | dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0); |
2096 | } | |
2097 | ||
2098 | /* | |
2099 | * dwc2_gadget_start_next_isoc_ddma - start next isoc request, if any. | |
2100 | * @hs_ep: The isochronous endpoint to be re-enabled. | |
2101 | * | |
2102 | * If ep has been disabled due to last descriptor servicing (IN endpoint) or | |
2103 | * BNA (OUT endpoint) check the status of other half of descriptor chain that | |
2104 | * was under SW control till HW was busy and restart the endpoint if needed. | |
2105 | */ | |
2106 | static void dwc2_gadget_start_next_isoc_ddma(struct dwc2_hsotg_ep *hs_ep) | |
2107 | { | |
2108 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
2109 | u32 depctl; | |
2110 | u32 dma_reg; | |
2111 | u32 ctrl; | |
2112 | u32 dma_addr = hs_ep->desc_list_dma; | |
2113 | unsigned char index = hs_ep->index; | |
2114 | ||
2115 | dma_reg = hs_ep->dir_in ? DIEPDMA(index) : DOEPDMA(index); | |
2116 | depctl = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index); | |
2117 | ||
2118 | ctrl = dwc2_readl(hsotg->regs + depctl); | |
2119 | ||
2120 | /* | |
2121 | * EP was disabled if HW has processed last descriptor or BNA was set. | |
2122 | * So restart ep if SW has prepared new descriptor chain in ep_queue | |
2123 | * routine while HW was busy. | |
2124 | */ | |
2125 | if (!(ctrl & DXEPCTL_EPENA)) { | |
2126 | if (!hs_ep->next_desc) { | |
2127 | dev_dbg(hsotg->dev, "%s: No more ISOC requests\n", | |
2128 | __func__); | |
2129 | return; | |
2130 | } | |
2131 | ||
2132 | dma_addr += sizeof(struct dwc2_dma_desc) * | |
2133 | (MAX_DMA_DESC_NUM_GENERIC / 2) * | |
2134 | hs_ep->isoc_chain_num; | |
2135 | dwc2_writel(dma_addr, hsotg->regs + dma_reg); | |
2136 | ||
2137 | ctrl |= DXEPCTL_EPENA | DXEPCTL_CNAK; | |
2138 | dwc2_writel(ctrl, hsotg->regs + depctl); | |
2139 | ||
2140 | /* Switch ISOC descriptor chain number being processed by SW*/ | |
2141 | hs_ep->isoc_chain_num = (hs_ep->isoc_chain_num ^ 1) & 0x1; | |
2142 | hs_ep->next_desc = 0; | |
2143 | ||
2144 | dev_dbg(hsotg->dev, "%s: Restarted isochronous endpoint\n", | |
2145 | __func__); | |
2146 | } | |
2147 | } | |
2148 | ||
5b7d70c6 | 2149 | /** |
1f91b4cc | 2150 | * dwc2_hsotg_rx_data - receive data from the FIFO for an endpoint |
5b7d70c6 BD |
2151 | * @hsotg: The device state. |
2152 | * @ep_idx: The endpoint index for the data | |
2153 | * @size: The size of data in the fifo, in bytes | |
2154 | * | |
2155 | * The FIFO status shows there is data to read from the FIFO for a given | |
2156 | * endpoint, so sort out whether we need to read the data into a request | |
2157 | * that has been made for that endpoint. | |
2158 | */ | |
1f91b4cc | 2159 | static void dwc2_hsotg_rx_data(struct dwc2_hsotg *hsotg, int ep_idx, int size) |
5b7d70c6 | 2160 | { |
1f91b4cc FB |
2161 | struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[ep_idx]; |
2162 | struct dwc2_hsotg_req *hs_req = hs_ep->req; | |
94cb8fd6 | 2163 | void __iomem *fifo = hsotg->regs + EPFIFO(ep_idx); |
5b7d70c6 BD |
2164 | int to_read; |
2165 | int max_req; | |
2166 | int read_ptr; | |
2167 | ||
2168 | if (!hs_req) { | |
95c8bc36 | 2169 | u32 epctl = dwc2_readl(hsotg->regs + DOEPCTL(ep_idx)); |
5b7d70c6 BD |
2170 | int ptr; |
2171 | ||
6b448af4 | 2172 | dev_dbg(hsotg->dev, |
9da51974 | 2173 | "%s: FIFO %d bytes on ep%d but no req (DXEPCTl=0x%08x)\n", |
5b7d70c6 BD |
2174 | __func__, size, ep_idx, epctl); |
2175 | ||
2176 | /* dump the data from the FIFO, we've nothing we can do */ | |
2177 | for (ptr = 0; ptr < size; ptr += 4) | |
95c8bc36 | 2178 | (void)dwc2_readl(fifo); |
5b7d70c6 BD |
2179 | |
2180 | return; | |
2181 | } | |
2182 | ||
5b7d70c6 BD |
2183 | to_read = size; |
2184 | read_ptr = hs_req->req.actual; | |
2185 | max_req = hs_req->req.length - read_ptr; | |
2186 | ||
a33e7136 BD |
2187 | dev_dbg(hsotg->dev, "%s: read %d/%d, done %d/%d\n", |
2188 | __func__, to_read, max_req, read_ptr, hs_req->req.length); | |
2189 | ||
5b7d70c6 | 2190 | if (to_read > max_req) { |
8b9bc460 LM |
2191 | /* |
2192 | * more data appeared than we where willing | |
5b7d70c6 BD |
2193 | * to deal with in this request. |
2194 | */ | |
2195 | ||
2196 | /* currently we don't deal this */ | |
2197 | WARN_ON_ONCE(1); | |
2198 | } | |
2199 | ||
5b7d70c6 BD |
2200 | hs_ep->total_data += to_read; |
2201 | hs_req->req.actual += to_read; | |
2202 | to_read = DIV_ROUND_UP(to_read, 4); | |
2203 | ||
8b9bc460 LM |
2204 | /* |
2205 | * note, we might over-write the buffer end by 3 bytes depending on | |
2206 | * alignment of the data. | |
2207 | */ | |
1a7ed5be | 2208 | ioread32_rep(fifo, hs_req->req.buf + read_ptr, to_read); |
5b7d70c6 BD |
2209 | } |
2210 | ||
2211 | /** | |
1f91b4cc | 2212 | * dwc2_hsotg_ep0_zlp - send/receive zero-length packet on control endpoint |
5b7d70c6 | 2213 | * @hsotg: The device instance |
fe0b94ab | 2214 | * @dir_in: If IN zlp |
5b7d70c6 BD |
2215 | * |
2216 | * Generate a zero-length IN packet request for terminating a SETUP | |
2217 | * transaction. | |
2218 | * | |
2219 | * Note, since we don't write any data to the TxFIFO, then it is | |
25985edc | 2220 | * currently believed that we do not need to wait for any space in |
5b7d70c6 BD |
2221 | * the TxFIFO. |
2222 | */ | |
1f91b4cc | 2223 | static void dwc2_hsotg_ep0_zlp(struct dwc2_hsotg *hsotg, bool dir_in) |
5b7d70c6 | 2224 | { |
c6f5c050 | 2225 | /* eps_out[0] is used in both directions */ |
fe0b94ab MYK |
2226 | hsotg->eps_out[0]->dir_in = dir_in; |
2227 | hsotg->ep0_state = dir_in ? DWC2_EP0_STATUS_IN : DWC2_EP0_STATUS_OUT; | |
5b7d70c6 | 2228 | |
1f91b4cc | 2229 | dwc2_hsotg_program_zlp(hsotg, hsotg->eps_out[0]); |
5b7d70c6 BD |
2230 | } |
2231 | ||
ec1f9d9f | 2232 | static void dwc2_hsotg_change_ep_iso_parity(struct dwc2_hsotg *hsotg, |
9da51974 | 2233 | u32 epctl_reg) |
ec1f9d9f RB |
2234 | { |
2235 | u32 ctrl; | |
2236 | ||
2237 | ctrl = dwc2_readl(hsotg->regs + epctl_reg); | |
2238 | if (ctrl & DXEPCTL_EOFRNUM) | |
2239 | ctrl |= DXEPCTL_SETEVENFR; | |
2240 | else | |
2241 | ctrl |= DXEPCTL_SETODDFR; | |
2242 | dwc2_writel(ctrl, hsotg->regs + epctl_reg); | |
2243 | } | |
2244 | ||
aa3e8bc8 VA |
2245 | /* |
2246 | * dwc2_gadget_get_xfersize_ddma - get transferred bytes amount from desc | |
2247 | * @hs_ep - The endpoint on which transfer went | |
2248 | * | |
2249 | * Iterate over endpoints descriptor chain and get info on bytes remained | |
2250 | * in DMA descriptors after transfer has completed. Used for non isoc EPs. | |
2251 | */ | |
2252 | static unsigned int dwc2_gadget_get_xfersize_ddma(struct dwc2_hsotg_ep *hs_ep) | |
2253 | { | |
2254 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
2255 | unsigned int bytes_rem = 0; | |
2256 | struct dwc2_dma_desc *desc = hs_ep->desc_list; | |
2257 | int i; | |
2258 | u32 status; | |
2259 | ||
2260 | if (!desc) | |
2261 | return -EINVAL; | |
2262 | ||
2263 | for (i = 0; i < hs_ep->desc_count; ++i) { | |
2264 | status = desc->status; | |
2265 | bytes_rem += status & DEV_DMA_NBYTES_MASK; | |
2266 | ||
2267 | if (status & DEV_DMA_STS_MASK) | |
2268 | dev_err(hsotg->dev, "descriptor %d closed with %x\n", | |
2269 | i, status & DEV_DMA_STS_MASK); | |
2270 | } | |
2271 | ||
2272 | return bytes_rem; | |
2273 | } | |
2274 | ||
5b7d70c6 | 2275 | /** |
1f91b4cc | 2276 | * dwc2_hsotg_handle_outdone - handle receiving OutDone/SetupDone from RXFIFO |
5b7d70c6 BD |
2277 | * @hsotg: The device instance |
2278 | * @epnum: The endpoint received from | |
5b7d70c6 BD |
2279 | * |
2280 | * The RXFIFO has delivered an OutDone event, which means that the data | |
2281 | * transfer for an OUT endpoint has been completed, either by a short | |
2282 | * packet or by the finish of a transfer. | |
8b9bc460 | 2283 | */ |
1f91b4cc | 2284 | static void dwc2_hsotg_handle_outdone(struct dwc2_hsotg *hsotg, int epnum) |
5b7d70c6 | 2285 | { |
95c8bc36 | 2286 | u32 epsize = dwc2_readl(hsotg->regs + DOEPTSIZ(epnum)); |
1f91b4cc FB |
2287 | struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[epnum]; |
2288 | struct dwc2_hsotg_req *hs_req = hs_ep->req; | |
5b7d70c6 | 2289 | struct usb_request *req = &hs_req->req; |
9da51974 | 2290 | unsigned int size_left = DXEPTSIZ_XFERSIZE_GET(epsize); |
5b7d70c6 BD |
2291 | int result = 0; |
2292 | ||
2293 | if (!hs_req) { | |
2294 | dev_dbg(hsotg->dev, "%s: no request active\n", __func__); | |
2295 | return; | |
2296 | } | |
2297 | ||
fe0b94ab MYK |
2298 | if (epnum == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_OUT) { |
2299 | dev_dbg(hsotg->dev, "zlp packet received\n"); | |
1f91b4cc FB |
2300 | dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0); |
2301 | dwc2_hsotg_enqueue_setup(hsotg); | |
fe0b94ab MYK |
2302 | return; |
2303 | } | |
2304 | ||
aa3e8bc8 VA |
2305 | if (using_desc_dma(hsotg)) |
2306 | size_left = dwc2_gadget_get_xfersize_ddma(hs_ep); | |
2307 | ||
5b7d70c6 | 2308 | if (using_dma(hsotg)) { |
9da51974 | 2309 | unsigned int size_done; |
5b7d70c6 | 2310 | |
8b9bc460 LM |
2311 | /* |
2312 | * Calculate the size of the transfer by checking how much | |
5b7d70c6 BD |
2313 | * is left in the endpoint size register and then working it |
2314 | * out from the amount we loaded for the transfer. | |
2315 | * | |
2316 | * We need to do this as DMA pointers are always 32bit aligned | |
2317 | * so may overshoot/undershoot the transfer. | |
2318 | */ | |
2319 | ||
5b7d70c6 BD |
2320 | size_done = hs_ep->size_loaded - size_left; |
2321 | size_done += hs_ep->last_load; | |
2322 | ||
2323 | req->actual = size_done; | |
2324 | } | |
2325 | ||
a33e7136 BD |
2326 | /* if there is more request to do, schedule new transfer */ |
2327 | if (req->actual < req->length && size_left == 0) { | |
1f91b4cc | 2328 | dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true); |
a33e7136 BD |
2329 | return; |
2330 | } | |
2331 | ||
5b7d70c6 BD |
2332 | if (req->actual < req->length && req->short_not_ok) { |
2333 | dev_dbg(hsotg->dev, "%s: got %d/%d (short not ok) => error\n", | |
2334 | __func__, req->actual, req->length); | |
2335 | ||
8b9bc460 LM |
2336 | /* |
2337 | * todo - what should we return here? there's no one else | |
2338 | * even bothering to check the status. | |
2339 | */ | |
5b7d70c6 BD |
2340 | } |
2341 | ||
ef750c71 VA |
2342 | /* DDMA IN status phase will start from StsPhseRcvd interrupt */ |
2343 | if (!using_desc_dma(hsotg) && epnum == 0 && | |
2344 | hsotg->ep0_state == DWC2_EP0_DATA_OUT) { | |
fe0b94ab | 2345 | /* Move to STATUS IN */ |
1f91b4cc | 2346 | dwc2_hsotg_ep0_zlp(hsotg, true); |
fe0b94ab | 2347 | return; |
5b7d70c6 BD |
2348 | } |
2349 | ||
ec1f9d9f RB |
2350 | /* |
2351 | * Slave mode OUT transfers do not go through XferComplete so | |
2352 | * adjust the ISOC parity here. | |
2353 | */ | |
2354 | if (!using_dma(hsotg)) { | |
ec1f9d9f RB |
2355 | if (hs_ep->isochronous && hs_ep->interval == 1) |
2356 | dwc2_hsotg_change_ep_iso_parity(hsotg, DOEPCTL(epnum)); | |
837e9f00 VM |
2357 | else if (hs_ep->isochronous && hs_ep->interval > 1) |
2358 | dwc2_gadget_incr_frame_num(hs_ep); | |
ec1f9d9f RB |
2359 | } |
2360 | ||
1f91b4cc | 2361 | dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, result); |
5b7d70c6 BD |
2362 | } |
2363 | ||
5b7d70c6 | 2364 | /** |
1f91b4cc | 2365 | * dwc2_hsotg_handle_rx - RX FIFO has data |
5b7d70c6 BD |
2366 | * @hsotg: The device instance |
2367 | * | |
2368 | * The IRQ handler has detected that the RX FIFO has some data in it | |
2369 | * that requires processing, so find out what is in there and do the | |
2370 | * appropriate read. | |
2371 | * | |
25985edc | 2372 | * The RXFIFO is a true FIFO, the packets coming out are still in packet |
5b7d70c6 BD |
2373 | * chunks, so if you have x packets received on an endpoint you'll get x |
2374 | * FIFO events delivered, each with a packet's worth of data in it. | |
2375 | * | |
2376 | * When using DMA, we should not be processing events from the RXFIFO | |
2377 | * as the actual data should be sent to the memory directly and we turn | |
2378 | * on the completion interrupts to get notifications of transfer completion. | |
2379 | */ | |
1f91b4cc | 2380 | static void dwc2_hsotg_handle_rx(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 2381 | { |
95c8bc36 | 2382 | u32 grxstsr = dwc2_readl(hsotg->regs + GRXSTSP); |
5b7d70c6 BD |
2383 | u32 epnum, status, size; |
2384 | ||
2385 | WARN_ON(using_dma(hsotg)); | |
2386 | ||
47a1685f DN |
2387 | epnum = grxstsr & GRXSTS_EPNUM_MASK; |
2388 | status = grxstsr & GRXSTS_PKTSTS_MASK; | |
5b7d70c6 | 2389 | |
47a1685f DN |
2390 | size = grxstsr & GRXSTS_BYTECNT_MASK; |
2391 | size >>= GRXSTS_BYTECNT_SHIFT; | |
5b7d70c6 | 2392 | |
d7c747c5 | 2393 | dev_dbg(hsotg->dev, "%s: GRXSTSP=0x%08x (%d@%d)\n", |
9da51974 | 2394 | __func__, grxstsr, size, epnum); |
5b7d70c6 | 2395 | |
47a1685f DN |
2396 | switch ((status & GRXSTS_PKTSTS_MASK) >> GRXSTS_PKTSTS_SHIFT) { |
2397 | case GRXSTS_PKTSTS_GLOBALOUTNAK: | |
2398 | dev_dbg(hsotg->dev, "GLOBALOUTNAK\n"); | |
5b7d70c6 BD |
2399 | break; |
2400 | ||
47a1685f | 2401 | case GRXSTS_PKTSTS_OUTDONE: |
5b7d70c6 | 2402 | dev_dbg(hsotg->dev, "OutDone (Frame=0x%08x)\n", |
1f91b4cc | 2403 | dwc2_hsotg_read_frameno(hsotg)); |
5b7d70c6 BD |
2404 | |
2405 | if (!using_dma(hsotg)) | |
1f91b4cc | 2406 | dwc2_hsotg_handle_outdone(hsotg, epnum); |
5b7d70c6 BD |
2407 | break; |
2408 | ||
47a1685f | 2409 | case GRXSTS_PKTSTS_SETUPDONE: |
5b7d70c6 BD |
2410 | dev_dbg(hsotg->dev, |
2411 | "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n", | |
1f91b4cc | 2412 | dwc2_hsotg_read_frameno(hsotg), |
95c8bc36 | 2413 | dwc2_readl(hsotg->regs + DOEPCTL(0))); |
fe0b94ab | 2414 | /* |
1f91b4cc | 2415 | * Call dwc2_hsotg_handle_outdone here if it was not called from |
fe0b94ab MYK |
2416 | * GRXSTS_PKTSTS_OUTDONE. That is, if the core didn't |
2417 | * generate GRXSTS_PKTSTS_OUTDONE for setup packet. | |
2418 | */ | |
2419 | if (hsotg->ep0_state == DWC2_EP0_SETUP) | |
1f91b4cc | 2420 | dwc2_hsotg_handle_outdone(hsotg, epnum); |
5b7d70c6 BD |
2421 | break; |
2422 | ||
47a1685f | 2423 | case GRXSTS_PKTSTS_OUTRX: |
1f91b4cc | 2424 | dwc2_hsotg_rx_data(hsotg, epnum, size); |
5b7d70c6 BD |
2425 | break; |
2426 | ||
47a1685f | 2427 | case GRXSTS_PKTSTS_SETUPRX: |
5b7d70c6 BD |
2428 | dev_dbg(hsotg->dev, |
2429 | "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n", | |
1f91b4cc | 2430 | dwc2_hsotg_read_frameno(hsotg), |
95c8bc36 | 2431 | dwc2_readl(hsotg->regs + DOEPCTL(0))); |
5b7d70c6 | 2432 | |
fe0b94ab MYK |
2433 | WARN_ON(hsotg->ep0_state != DWC2_EP0_SETUP); |
2434 | ||
1f91b4cc | 2435 | dwc2_hsotg_rx_data(hsotg, epnum, size); |
5b7d70c6 BD |
2436 | break; |
2437 | ||
2438 | default: | |
2439 | dev_warn(hsotg->dev, "%s: unknown status %08x\n", | |
2440 | __func__, grxstsr); | |
2441 | ||
1f91b4cc | 2442 | dwc2_hsotg_dump(hsotg); |
5b7d70c6 BD |
2443 | break; |
2444 | } | |
2445 | } | |
2446 | ||
2447 | /** | |
1f91b4cc | 2448 | * dwc2_hsotg_ep0_mps - turn max packet size into register setting |
5b7d70c6 | 2449 | * @mps: The maximum packet size in bytes. |
8b9bc460 | 2450 | */ |
1f91b4cc | 2451 | static u32 dwc2_hsotg_ep0_mps(unsigned int mps) |
5b7d70c6 BD |
2452 | { |
2453 | switch (mps) { | |
2454 | case 64: | |
94cb8fd6 | 2455 | return D0EPCTL_MPS_64; |
5b7d70c6 | 2456 | case 32: |
94cb8fd6 | 2457 | return D0EPCTL_MPS_32; |
5b7d70c6 | 2458 | case 16: |
94cb8fd6 | 2459 | return D0EPCTL_MPS_16; |
5b7d70c6 | 2460 | case 8: |
94cb8fd6 | 2461 | return D0EPCTL_MPS_8; |
5b7d70c6 BD |
2462 | } |
2463 | ||
2464 | /* bad max packet size, warn and return invalid result */ | |
2465 | WARN_ON(1); | |
2466 | return (u32)-1; | |
2467 | } | |
2468 | ||
2469 | /** | |
1f91b4cc | 2470 | * dwc2_hsotg_set_ep_maxpacket - set endpoint's max-packet field |
5b7d70c6 BD |
2471 | * @hsotg: The driver state. |
2472 | * @ep: The index number of the endpoint | |
2473 | * @mps: The maximum packet size in bytes | |
ee2c40de | 2474 | * @mc: The multicount value |
5b7d70c6 BD |
2475 | * |
2476 | * Configure the maximum packet size for the given endpoint, updating | |
2477 | * the hardware control registers to reflect this. | |
2478 | */ | |
1f91b4cc | 2479 | static void dwc2_hsotg_set_ep_maxpacket(struct dwc2_hsotg *hsotg, |
ee2c40de VM |
2480 | unsigned int ep, unsigned int mps, |
2481 | unsigned int mc, unsigned int dir_in) | |
5b7d70c6 | 2482 | { |
1f91b4cc | 2483 | struct dwc2_hsotg_ep *hs_ep; |
5b7d70c6 | 2484 | void __iomem *regs = hsotg->regs; |
5b7d70c6 BD |
2485 | u32 reg; |
2486 | ||
c6f5c050 MYK |
2487 | hs_ep = index_to_ep(hsotg, ep, dir_in); |
2488 | if (!hs_ep) | |
2489 | return; | |
2490 | ||
5b7d70c6 | 2491 | if (ep == 0) { |
ee2c40de VM |
2492 | u32 mps_bytes = mps; |
2493 | ||
5b7d70c6 | 2494 | /* EP0 is a special case */ |
ee2c40de VM |
2495 | mps = dwc2_hsotg_ep0_mps(mps_bytes); |
2496 | if (mps > 3) | |
5b7d70c6 | 2497 | goto bad_mps; |
ee2c40de | 2498 | hs_ep->ep.maxpacket = mps_bytes; |
4fca54aa | 2499 | hs_ep->mc = 1; |
5b7d70c6 | 2500 | } else { |
ee2c40de | 2501 | if (mps > 1024) |
5b7d70c6 | 2502 | goto bad_mps; |
ee2c40de VM |
2503 | hs_ep->mc = mc; |
2504 | if (mc > 3) | |
4fca54aa | 2505 | goto bad_mps; |
ee2c40de | 2506 | hs_ep->ep.maxpacket = mps; |
5b7d70c6 BD |
2507 | } |
2508 | ||
c6f5c050 | 2509 | if (dir_in) { |
95c8bc36 | 2510 | reg = dwc2_readl(regs + DIEPCTL(ep)); |
c6f5c050 | 2511 | reg &= ~DXEPCTL_MPS_MASK; |
ee2c40de | 2512 | reg |= mps; |
95c8bc36 | 2513 | dwc2_writel(reg, regs + DIEPCTL(ep)); |
c6f5c050 | 2514 | } else { |
95c8bc36 | 2515 | reg = dwc2_readl(regs + DOEPCTL(ep)); |
47a1685f | 2516 | reg &= ~DXEPCTL_MPS_MASK; |
ee2c40de | 2517 | reg |= mps; |
95c8bc36 | 2518 | dwc2_writel(reg, regs + DOEPCTL(ep)); |
659ad60c | 2519 | } |
5b7d70c6 BD |
2520 | |
2521 | return; | |
2522 | ||
2523 | bad_mps: | |
2524 | dev_err(hsotg->dev, "ep%d: bad mps of %d\n", ep, mps); | |
2525 | } | |
2526 | ||
9c39ddc6 | 2527 | /** |
1f91b4cc | 2528 | * dwc2_hsotg_txfifo_flush - flush Tx FIFO |
9c39ddc6 AT |
2529 | * @hsotg: The driver state |
2530 | * @idx: The index for the endpoint (0..15) | |
2531 | */ | |
1f91b4cc | 2532 | static void dwc2_hsotg_txfifo_flush(struct dwc2_hsotg *hsotg, unsigned int idx) |
9c39ddc6 AT |
2533 | { |
2534 | int timeout; | |
2535 | int val; | |
2536 | ||
95c8bc36 AS |
2537 | dwc2_writel(GRSTCTL_TXFNUM(idx) | GRSTCTL_TXFFLSH, |
2538 | hsotg->regs + GRSTCTL); | |
9c39ddc6 AT |
2539 | |
2540 | /* wait until the fifo is flushed */ | |
2541 | timeout = 100; | |
2542 | ||
2543 | while (1) { | |
95c8bc36 | 2544 | val = dwc2_readl(hsotg->regs + GRSTCTL); |
9c39ddc6 | 2545 | |
47a1685f | 2546 | if ((val & (GRSTCTL_TXFFLSH)) == 0) |
9c39ddc6 AT |
2547 | break; |
2548 | ||
2549 | if (--timeout == 0) { | |
2550 | dev_err(hsotg->dev, | |
2551 | "%s: timeout flushing fifo (GRSTCTL=%08x)\n", | |
2552 | __func__, val); | |
e0cbe595 | 2553 | break; |
9c39ddc6 AT |
2554 | } |
2555 | ||
2556 | udelay(1); | |
2557 | } | |
2558 | } | |
5b7d70c6 BD |
2559 | |
2560 | /** | |
1f91b4cc | 2561 | * dwc2_hsotg_trytx - check to see if anything needs transmitting |
5b7d70c6 BD |
2562 | * @hsotg: The driver state |
2563 | * @hs_ep: The driver endpoint to check. | |
2564 | * | |
2565 | * Check to see if there is a request that has data to send, and if so | |
2566 | * make an attempt to write data into the FIFO. | |
2567 | */ | |
1f91b4cc | 2568 | static int dwc2_hsotg_trytx(struct dwc2_hsotg *hsotg, |
9da51974 | 2569 | struct dwc2_hsotg_ep *hs_ep) |
5b7d70c6 | 2570 | { |
1f91b4cc | 2571 | struct dwc2_hsotg_req *hs_req = hs_ep->req; |
5b7d70c6 | 2572 | |
afcf4169 RB |
2573 | if (!hs_ep->dir_in || !hs_req) { |
2574 | /** | |
2575 | * if request is not enqueued, we disable interrupts | |
2576 | * for endpoints, excepting ep0 | |
2577 | */ | |
2578 | if (hs_ep->index != 0) | |
1f91b4cc | 2579 | dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, |
9da51974 | 2580 | hs_ep->dir_in, 0); |
5b7d70c6 | 2581 | return 0; |
afcf4169 | 2582 | } |
5b7d70c6 BD |
2583 | |
2584 | if (hs_req->req.actual < hs_req->req.length) { | |
2585 | dev_dbg(hsotg->dev, "trying to write more for ep%d\n", | |
2586 | hs_ep->index); | |
1f91b4cc | 2587 | return dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req); |
5b7d70c6 BD |
2588 | } |
2589 | ||
2590 | return 0; | |
2591 | } | |
2592 | ||
2593 | /** | |
1f91b4cc | 2594 | * dwc2_hsotg_complete_in - complete IN transfer |
5b7d70c6 BD |
2595 | * @hsotg: The device state. |
2596 | * @hs_ep: The endpoint that has just completed. | |
2597 | * | |
2598 | * An IN transfer has been completed, update the transfer's state and then | |
2599 | * call the relevant completion routines. | |
2600 | */ | |
1f91b4cc | 2601 | static void dwc2_hsotg_complete_in(struct dwc2_hsotg *hsotg, |
9da51974 | 2602 | struct dwc2_hsotg_ep *hs_ep) |
5b7d70c6 | 2603 | { |
1f91b4cc | 2604 | struct dwc2_hsotg_req *hs_req = hs_ep->req; |
95c8bc36 | 2605 | u32 epsize = dwc2_readl(hsotg->regs + DIEPTSIZ(hs_ep->index)); |
5b7d70c6 BD |
2606 | int size_left, size_done; |
2607 | ||
2608 | if (!hs_req) { | |
2609 | dev_dbg(hsotg->dev, "XferCompl but no req\n"); | |
2610 | return; | |
2611 | } | |
2612 | ||
d3ca0259 | 2613 | /* Finish ZLP handling for IN EP0 transactions */ |
fe0b94ab MYK |
2614 | if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_IN) { |
2615 | dev_dbg(hsotg->dev, "zlp packet sent\n"); | |
c3b22fe2 RK |
2616 | |
2617 | /* | |
2618 | * While send zlp for DWC2_EP0_STATUS_IN EP direction was | |
2619 | * changed to IN. Change back to complete OUT transfer request | |
2620 | */ | |
2621 | hs_ep->dir_in = 0; | |
2622 | ||
1f91b4cc | 2623 | dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0); |
9e14d0a5 GH |
2624 | if (hsotg->test_mode) { |
2625 | int ret; | |
2626 | ||
1f91b4cc | 2627 | ret = dwc2_hsotg_set_test_mode(hsotg, hsotg->test_mode); |
9e14d0a5 GH |
2628 | if (ret < 0) { |
2629 | dev_dbg(hsotg->dev, "Invalid Test #%d\n", | |
9da51974 | 2630 | hsotg->test_mode); |
1f91b4cc | 2631 | dwc2_hsotg_stall_ep0(hsotg); |
9e14d0a5 GH |
2632 | return; |
2633 | } | |
2634 | } | |
1f91b4cc | 2635 | dwc2_hsotg_enqueue_setup(hsotg); |
d3ca0259 LM |
2636 | return; |
2637 | } | |
2638 | ||
8b9bc460 LM |
2639 | /* |
2640 | * Calculate the size of the transfer by checking how much is left | |
5b7d70c6 BD |
2641 | * in the endpoint size register and then working it out from |
2642 | * the amount we loaded for the transfer. | |
2643 | * | |
2644 | * We do this even for DMA, as the transfer may have incremented | |
2645 | * past the end of the buffer (DMA transfers are always 32bit | |
2646 | * aligned). | |
2647 | */ | |
aa3e8bc8 VA |
2648 | if (using_desc_dma(hsotg)) { |
2649 | size_left = dwc2_gadget_get_xfersize_ddma(hs_ep); | |
2650 | if (size_left < 0) | |
2651 | dev_err(hsotg->dev, "error parsing DDMA results %d\n", | |
2652 | size_left); | |
2653 | } else { | |
2654 | size_left = DXEPTSIZ_XFERSIZE_GET(epsize); | |
2655 | } | |
5b7d70c6 BD |
2656 | |
2657 | size_done = hs_ep->size_loaded - size_left; | |
2658 | size_done += hs_ep->last_load; | |
2659 | ||
2660 | if (hs_req->req.actual != size_done) | |
2661 | dev_dbg(hsotg->dev, "%s: adjusting size done %d => %d\n", | |
2662 | __func__, hs_req->req.actual, size_done); | |
2663 | ||
2664 | hs_req->req.actual = size_done; | |
d3ca0259 LM |
2665 | dev_dbg(hsotg->dev, "req->length:%d req->actual:%d req->zero:%d\n", |
2666 | hs_req->req.length, hs_req->req.actual, hs_req->req.zero); | |
2667 | ||
5b7d70c6 BD |
2668 | if (!size_left && hs_req->req.actual < hs_req->req.length) { |
2669 | dev_dbg(hsotg->dev, "%s trying more for req...\n", __func__); | |
1f91b4cc | 2670 | dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true); |
fe0b94ab MYK |
2671 | return; |
2672 | } | |
2673 | ||
f71b5e25 | 2674 | /* Zlp for all endpoints, for ep0 only in DATA IN stage */ |
8a20fa45 | 2675 | if (hs_ep->send_zlp) { |
1f91b4cc | 2676 | dwc2_hsotg_program_zlp(hsotg, hs_ep); |
8a20fa45 | 2677 | hs_ep->send_zlp = 0; |
f71b5e25 MYK |
2678 | /* transfer will be completed on next complete interrupt */ |
2679 | return; | |
2680 | } | |
2681 | ||
fe0b94ab MYK |
2682 | if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_DATA_IN) { |
2683 | /* Move to STATUS OUT */ | |
1f91b4cc | 2684 | dwc2_hsotg_ep0_zlp(hsotg, false); |
fe0b94ab MYK |
2685 | return; |
2686 | } | |
2687 | ||
1f91b4cc | 2688 | dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0); |
5b7d70c6 BD |
2689 | } |
2690 | ||
32601588 VM |
2691 | /** |
2692 | * dwc2_gadget_read_ep_interrupts - reads interrupts for given ep | |
2693 | * @hsotg: The device state. | |
2694 | * @idx: Index of ep. | |
2695 | * @dir_in: Endpoint direction 1-in 0-out. | |
2696 | * | |
2697 | * Reads for endpoint with given index and direction, by masking | |
2698 | * epint_reg with coresponding mask. | |
2699 | */ | |
2700 | static u32 dwc2_gadget_read_ep_interrupts(struct dwc2_hsotg *hsotg, | |
2701 | unsigned int idx, int dir_in) | |
2702 | { | |
2703 | u32 epmsk_reg = dir_in ? DIEPMSK : DOEPMSK; | |
2704 | u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx); | |
2705 | u32 ints; | |
2706 | u32 mask; | |
2707 | u32 diepempmsk; | |
2708 | ||
2709 | mask = dwc2_readl(hsotg->regs + epmsk_reg); | |
2710 | diepempmsk = dwc2_readl(hsotg->regs + DIEPEMPMSK); | |
2711 | mask |= ((diepempmsk >> idx) & 0x1) ? DIEPMSK_TXFIFOEMPTY : 0; | |
2712 | mask |= DXEPINT_SETUP_RCVD; | |
2713 | ||
2714 | ints = dwc2_readl(hsotg->regs + epint_reg); | |
2715 | ints &= mask; | |
2716 | return ints; | |
2717 | } | |
2718 | ||
bd9971f0 VM |
2719 | /** |
2720 | * dwc2_gadget_handle_ep_disabled - handle DXEPINT_EPDISBLD | |
2721 | * @hs_ep: The endpoint on which interrupt is asserted. | |
2722 | * | |
2723 | * This interrupt indicates that the endpoint has been disabled per the | |
2724 | * application's request. | |
2725 | * | |
2726 | * For IN endpoints flushes txfifo, in case of BULK clears DCTL_CGNPINNAK, | |
2727 | * in case of ISOC completes current request. | |
2728 | * | |
2729 | * For ISOC-OUT endpoints completes expired requests. If there is remaining | |
2730 | * request starts it. | |
2731 | */ | |
2732 | static void dwc2_gadget_handle_ep_disabled(struct dwc2_hsotg_ep *hs_ep) | |
2733 | { | |
2734 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
2735 | struct dwc2_hsotg_req *hs_req; | |
2736 | unsigned char idx = hs_ep->index; | |
2737 | int dir_in = hs_ep->dir_in; | |
2738 | u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx); | |
2739 | int dctl = dwc2_readl(hsotg->regs + DCTL); | |
2740 | ||
2741 | dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__); | |
2742 | ||
2743 | if (dir_in) { | |
2744 | int epctl = dwc2_readl(hsotg->regs + epctl_reg); | |
2745 | ||
2746 | dwc2_hsotg_txfifo_flush(hsotg, hs_ep->fifo_index); | |
2747 | ||
2748 | if (hs_ep->isochronous) { | |
2749 | dwc2_hsotg_complete_in(hsotg, hs_ep); | |
2750 | return; | |
2751 | } | |
2752 | ||
2753 | if ((epctl & DXEPCTL_STALL) && (epctl & DXEPCTL_EPTYPE_BULK)) { | |
2754 | int dctl = dwc2_readl(hsotg->regs + DCTL); | |
2755 | ||
2756 | dctl |= DCTL_CGNPINNAK; | |
2757 | dwc2_writel(dctl, hsotg->regs + DCTL); | |
2758 | } | |
2759 | return; | |
2760 | } | |
2761 | ||
2762 | if (dctl & DCTL_GOUTNAKSTS) { | |
2763 | dctl |= DCTL_CGOUTNAK; | |
2764 | dwc2_writel(dctl, hsotg->regs + DCTL); | |
2765 | } | |
2766 | ||
2767 | if (!hs_ep->isochronous) | |
2768 | return; | |
2769 | ||
2770 | if (list_empty(&hs_ep->queue)) { | |
2771 | dev_dbg(hsotg->dev, "%s: complete_ep 0x%p, ep->queue empty!\n", | |
2772 | __func__, hs_ep); | |
2773 | return; | |
2774 | } | |
2775 | ||
2776 | do { | |
2777 | hs_req = get_ep_head(hs_ep); | |
2778 | if (hs_req) | |
2779 | dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, | |
2780 | -ENODATA); | |
2781 | dwc2_gadget_incr_frame_num(hs_ep); | |
2782 | } while (dwc2_gadget_target_frame_elapsed(hs_ep)); | |
2783 | ||
2784 | dwc2_gadget_start_next_request(hs_ep); | |
2785 | } | |
2786 | ||
5321922c VM |
2787 | /** |
2788 | * dwc2_gadget_handle_out_token_ep_disabled - handle DXEPINT_OUTTKNEPDIS | |
2789 | * @hs_ep: The endpoint on which interrupt is asserted. | |
2790 | * | |
2791 | * This is starting point for ISOC-OUT transfer, synchronization done with | |
2792 | * first out token received from host while corresponding EP is disabled. | |
2793 | * | |
2794 | * Device does not know initial frame in which out token will come. For this | |
2795 | * HW generates OUTTKNEPDIS - out token is received while EP is disabled. Upon | |
2796 | * getting this interrupt SW starts calculation for next transfer frame. | |
2797 | */ | |
2798 | static void dwc2_gadget_handle_out_token_ep_disabled(struct dwc2_hsotg_ep *ep) | |
2799 | { | |
2800 | struct dwc2_hsotg *hsotg = ep->parent; | |
2801 | int dir_in = ep->dir_in; | |
2802 | u32 doepmsk; | |
540ccba0 | 2803 | u32 tmp; |
5321922c VM |
2804 | |
2805 | if (dir_in || !ep->isochronous) | |
2806 | return; | |
2807 | ||
540ccba0 VA |
2808 | /* |
2809 | * Store frame in which irq was asserted here, as | |
2810 | * it can change while completing request below. | |
2811 | */ | |
2812 | tmp = dwc2_hsotg_read_frameno(hsotg); | |
2813 | ||
5321922c VM |
2814 | dwc2_hsotg_complete_request(hsotg, ep, get_ep_head(ep), -ENODATA); |
2815 | ||
540ccba0 VA |
2816 | if (using_desc_dma(hsotg)) { |
2817 | if (ep->target_frame == TARGET_FRAME_INITIAL) { | |
2818 | /* Start first ISO Out */ | |
2819 | ep->target_frame = tmp; | |
2820 | dwc2_gadget_start_isoc_ddma(ep); | |
2821 | } | |
2822 | return; | |
2823 | } | |
2824 | ||
5321922c VM |
2825 | if (ep->interval > 1 && |
2826 | ep->target_frame == TARGET_FRAME_INITIAL) { | |
2827 | u32 dsts; | |
2828 | u32 ctrl; | |
2829 | ||
2830 | dsts = dwc2_readl(hsotg->regs + DSTS); | |
2831 | ep->target_frame = dwc2_hsotg_read_frameno(hsotg); | |
2832 | dwc2_gadget_incr_frame_num(ep); | |
2833 | ||
2834 | ctrl = dwc2_readl(hsotg->regs + DOEPCTL(ep->index)); | |
2835 | if (ep->target_frame & 0x1) | |
2836 | ctrl |= DXEPCTL_SETODDFR; | |
2837 | else | |
2838 | ctrl |= DXEPCTL_SETEVENFR; | |
2839 | ||
2840 | dwc2_writel(ctrl, hsotg->regs + DOEPCTL(ep->index)); | |
2841 | } | |
2842 | ||
2843 | dwc2_gadget_start_next_request(ep); | |
2844 | doepmsk = dwc2_readl(hsotg->regs + DOEPMSK); | |
2845 | doepmsk &= ~DOEPMSK_OUTTKNEPDISMSK; | |
2846 | dwc2_writel(doepmsk, hsotg->regs + DOEPMSK); | |
2847 | } | |
2848 | ||
2849 | /** | |
38beaec6 JY |
2850 | * dwc2_gadget_handle_nak - handle NAK interrupt |
2851 | * @hs_ep: The endpoint on which interrupt is asserted. | |
2852 | * | |
2853 | * This is starting point for ISOC-IN transfer, synchronization done with | |
2854 | * first IN token received from host while corresponding EP is disabled. | |
2855 | * | |
2856 | * Device does not know when first one token will arrive from host. On first | |
2857 | * token arrival HW generates 2 interrupts: 'in token received while FIFO empty' | |
2858 | * and 'NAK'. NAK interrupt for ISOC-IN means that token has arrived and ZLP was | |
2859 | * sent in response to that as there was no data in FIFO. SW is basing on this | |
2860 | * interrupt to obtain frame in which token has come and then based on the | |
2861 | * interval calculates next frame for transfer. | |
2862 | */ | |
5321922c VM |
2863 | static void dwc2_gadget_handle_nak(struct dwc2_hsotg_ep *hs_ep) |
2864 | { | |
2865 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
2866 | int dir_in = hs_ep->dir_in; | |
2867 | ||
2868 | if (!dir_in || !hs_ep->isochronous) | |
2869 | return; | |
2870 | ||
2871 | if (hs_ep->target_frame == TARGET_FRAME_INITIAL) { | |
2872 | hs_ep->target_frame = dwc2_hsotg_read_frameno(hsotg); | |
540ccba0 VA |
2873 | |
2874 | if (using_desc_dma(hsotg)) { | |
2875 | dwc2_gadget_start_isoc_ddma(hs_ep); | |
2876 | return; | |
2877 | } | |
2878 | ||
5321922c VM |
2879 | if (hs_ep->interval > 1) { |
2880 | u32 ctrl = dwc2_readl(hsotg->regs + | |
2881 | DIEPCTL(hs_ep->index)); | |
2882 | if (hs_ep->target_frame & 0x1) | |
2883 | ctrl |= DXEPCTL_SETODDFR; | |
2884 | else | |
2885 | ctrl |= DXEPCTL_SETEVENFR; | |
2886 | ||
2887 | dwc2_writel(ctrl, hsotg->regs + DIEPCTL(hs_ep->index)); | |
2888 | } | |
2889 | ||
2890 | dwc2_hsotg_complete_request(hsotg, hs_ep, | |
2891 | get_ep_head(hs_ep), 0); | |
2892 | } | |
2893 | ||
2894 | dwc2_gadget_incr_frame_num(hs_ep); | |
2895 | } | |
2896 | ||
5b7d70c6 | 2897 | /** |
1f91b4cc | 2898 | * dwc2_hsotg_epint - handle an in/out endpoint interrupt |
5b7d70c6 BD |
2899 | * @hsotg: The driver state |
2900 | * @idx: The index for the endpoint (0..15) | |
2901 | * @dir_in: Set if this is an IN endpoint | |
2902 | * | |
2903 | * Process and clear any interrupt pending for an individual endpoint | |
8b9bc460 | 2904 | */ |
1f91b4cc | 2905 | static void dwc2_hsotg_epint(struct dwc2_hsotg *hsotg, unsigned int idx, |
9da51974 | 2906 | int dir_in) |
5b7d70c6 | 2907 | { |
1f91b4cc | 2908 | struct dwc2_hsotg_ep *hs_ep = index_to_ep(hsotg, idx, dir_in); |
94cb8fd6 LM |
2909 | u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx); |
2910 | u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx); | |
2911 | u32 epsiz_reg = dir_in ? DIEPTSIZ(idx) : DOEPTSIZ(idx); | |
5b7d70c6 | 2912 | u32 ints; |
1479e841 | 2913 | u32 ctrl; |
5b7d70c6 | 2914 | |
32601588 | 2915 | ints = dwc2_gadget_read_ep_interrupts(hsotg, idx, dir_in); |
95c8bc36 | 2916 | ctrl = dwc2_readl(hsotg->regs + epctl_reg); |
5b7d70c6 | 2917 | |
a3395f0d | 2918 | /* Clear endpoint interrupts */ |
95c8bc36 | 2919 | dwc2_writel(ints, hsotg->regs + epint_reg); |
a3395f0d | 2920 | |
c6f5c050 MYK |
2921 | if (!hs_ep) { |
2922 | dev_err(hsotg->dev, "%s:Interrupt for unconfigured ep%d(%s)\n", | |
9da51974 | 2923 | __func__, idx, dir_in ? "in" : "out"); |
c6f5c050 MYK |
2924 | return; |
2925 | } | |
2926 | ||
5b7d70c6 BD |
2927 | dev_dbg(hsotg->dev, "%s: ep%d(%s) DxEPINT=0x%08x\n", |
2928 | __func__, idx, dir_in ? "in" : "out", ints); | |
2929 | ||
b787d755 MYK |
2930 | /* Don't process XferCompl interrupt if it is a setup packet */ |
2931 | if (idx == 0 && (ints & (DXEPINT_SETUP | DXEPINT_SETUP_RCVD))) | |
2932 | ints &= ~DXEPINT_XFERCOMPL; | |
2933 | ||
f0afdb42 VA |
2934 | /* |
2935 | * Don't process XferCompl interrupt in DDMA if EP0 is still in SETUP | |
2936 | * stage and xfercomplete was generated without SETUP phase done | |
2937 | * interrupt. SW should parse received setup packet only after host's | |
2938 | * exit from setup phase of control transfer. | |
2939 | */ | |
2940 | if (using_desc_dma(hsotg) && idx == 0 && !hs_ep->dir_in && | |
2941 | hsotg->ep0_state == DWC2_EP0_SETUP && !(ints & DXEPINT_SETUP)) | |
2942 | ints &= ~DXEPINT_XFERCOMPL; | |
2943 | ||
837e9f00 | 2944 | if (ints & DXEPINT_XFERCOMPL) { |
5b7d70c6 | 2945 | dev_dbg(hsotg->dev, |
47a1685f | 2946 | "%s: XferCompl: DxEPCTL=0x%08x, DXEPTSIZ=%08x\n", |
95c8bc36 AS |
2947 | __func__, dwc2_readl(hsotg->regs + epctl_reg), |
2948 | dwc2_readl(hsotg->regs + epsiz_reg)); | |
5b7d70c6 | 2949 | |
540ccba0 VA |
2950 | /* In DDMA handle isochronous requests separately */ |
2951 | if (using_desc_dma(hsotg) && hs_ep->isochronous) { | |
2952 | dwc2_gadget_complete_isoc_request_ddma(hs_ep); | |
2953 | /* Try to start next isoc request */ | |
2954 | dwc2_gadget_start_next_isoc_ddma(hs_ep); | |
2955 | } else if (dir_in) { | |
2956 | /* | |
2957 | * We get OutDone from the FIFO, so we only | |
2958 | * need to look at completing IN requests here | |
2959 | * if operating slave mode | |
2960 | */ | |
837e9f00 VM |
2961 | if (hs_ep->isochronous && hs_ep->interval > 1) |
2962 | dwc2_gadget_incr_frame_num(hs_ep); | |
2963 | ||
1f91b4cc | 2964 | dwc2_hsotg_complete_in(hsotg, hs_ep); |
837e9f00 VM |
2965 | if (ints & DXEPINT_NAKINTRPT) |
2966 | ints &= ~DXEPINT_NAKINTRPT; | |
5b7d70c6 | 2967 | |
c9a64ea8 | 2968 | if (idx == 0 && !hs_ep->req) |
1f91b4cc | 2969 | dwc2_hsotg_enqueue_setup(hsotg); |
5b7d70c6 | 2970 | } else if (using_dma(hsotg)) { |
8b9bc460 LM |
2971 | /* |
2972 | * We're using DMA, we need to fire an OutDone here | |
2973 | * as we ignore the RXFIFO. | |
2974 | */ | |
837e9f00 VM |
2975 | if (hs_ep->isochronous && hs_ep->interval > 1) |
2976 | dwc2_gadget_incr_frame_num(hs_ep); | |
5b7d70c6 | 2977 | |
1f91b4cc | 2978 | dwc2_hsotg_handle_outdone(hsotg, idx); |
5b7d70c6 | 2979 | } |
5b7d70c6 BD |
2980 | } |
2981 | ||
bd9971f0 VM |
2982 | if (ints & DXEPINT_EPDISBLD) |
2983 | dwc2_gadget_handle_ep_disabled(hs_ep); | |
9c39ddc6 | 2984 | |
5321922c VM |
2985 | if (ints & DXEPINT_OUTTKNEPDIS) |
2986 | dwc2_gadget_handle_out_token_ep_disabled(hs_ep); | |
2987 | ||
2988 | if (ints & DXEPINT_NAKINTRPT) | |
2989 | dwc2_gadget_handle_nak(hs_ep); | |
2990 | ||
47a1685f | 2991 | if (ints & DXEPINT_AHBERR) |
5b7d70c6 | 2992 | dev_dbg(hsotg->dev, "%s: AHBErr\n", __func__); |
5b7d70c6 | 2993 | |
47a1685f | 2994 | if (ints & DXEPINT_SETUP) { /* Setup or Timeout */ |
5b7d70c6 BD |
2995 | dev_dbg(hsotg->dev, "%s: Setup/Timeout\n", __func__); |
2996 | ||
2997 | if (using_dma(hsotg) && idx == 0) { | |
8b9bc460 LM |
2998 | /* |
2999 | * this is the notification we've received a | |
5b7d70c6 BD |
3000 | * setup packet. In non-DMA mode we'd get this |
3001 | * from the RXFIFO, instead we need to process | |
8b9bc460 LM |
3002 | * the setup here. |
3003 | */ | |
5b7d70c6 BD |
3004 | |
3005 | if (dir_in) | |
3006 | WARN_ON_ONCE(1); | |
3007 | else | |
1f91b4cc | 3008 | dwc2_hsotg_handle_outdone(hsotg, 0); |
5b7d70c6 | 3009 | } |
5b7d70c6 BD |
3010 | } |
3011 | ||
ef750c71 | 3012 | if (ints & DXEPINT_STSPHSERCVD) { |
9d9a6b07 VA |
3013 | dev_dbg(hsotg->dev, "%s: StsPhseRcvd\n", __func__); |
3014 | ||
ef750c71 VA |
3015 | /* Move to STATUS IN for DDMA */ |
3016 | if (using_desc_dma(hsotg)) | |
3017 | dwc2_hsotg_ep0_zlp(hsotg, true); | |
3018 | } | |
3019 | ||
47a1685f | 3020 | if (ints & DXEPINT_BACK2BACKSETUP) |
5b7d70c6 | 3021 | dev_dbg(hsotg->dev, "%s: B2BSetup/INEPNakEff\n", __func__); |
5b7d70c6 | 3022 | |
540ccba0 VA |
3023 | if (ints & DXEPINT_BNAINTR) { |
3024 | dev_dbg(hsotg->dev, "%s: BNA interrupt\n", __func__); | |
3025 | ||
3026 | /* | |
3027 | * Try to start next isoc request, if any. | |
3028 | * Sometimes the endpoint remains enabled after BNA interrupt | |
3029 | * assertion, which is not expected, hence we can enter here | |
3030 | * couple of times. | |
3031 | */ | |
3032 | if (hs_ep->isochronous) | |
3033 | dwc2_gadget_start_next_isoc_ddma(hs_ep); | |
3034 | } | |
3035 | ||
1479e841 | 3036 | if (dir_in && !hs_ep->isochronous) { |
8b9bc460 | 3037 | /* not sure if this is important, but we'll clear it anyway */ |
26ddef5d | 3038 | if (ints & DXEPINT_INTKNTXFEMP) { |
5b7d70c6 BD |
3039 | dev_dbg(hsotg->dev, "%s: ep%d: INTknTXFEmpMsk\n", |
3040 | __func__, idx); | |
5b7d70c6 BD |
3041 | } |
3042 | ||
3043 | /* this probably means something bad is happening */ | |
26ddef5d | 3044 | if (ints & DXEPINT_INTKNEPMIS) { |
5b7d70c6 BD |
3045 | dev_warn(hsotg->dev, "%s: ep%d: INTknEP\n", |
3046 | __func__, idx); | |
5b7d70c6 | 3047 | } |
10aebc77 BD |
3048 | |
3049 | /* FIFO has space or is empty (see GAHBCFG) */ | |
3050 | if (hsotg->dedicated_fifos && | |
26ddef5d | 3051 | ints & DXEPINT_TXFEMP) { |
10aebc77 BD |
3052 | dev_dbg(hsotg->dev, "%s: ep%d: TxFIFOEmpty\n", |
3053 | __func__, idx); | |
70fa030f | 3054 | if (!using_dma(hsotg)) |
1f91b4cc | 3055 | dwc2_hsotg_trytx(hsotg, hs_ep); |
10aebc77 | 3056 | } |
5b7d70c6 | 3057 | } |
5b7d70c6 BD |
3058 | } |
3059 | ||
3060 | /** | |
1f91b4cc | 3061 | * dwc2_hsotg_irq_enumdone - Handle EnumDone interrupt (enumeration done) |
5b7d70c6 BD |
3062 | * @hsotg: The device state. |
3063 | * | |
3064 | * Handle updating the device settings after the enumeration phase has | |
3065 | * been completed. | |
8b9bc460 | 3066 | */ |
1f91b4cc | 3067 | static void dwc2_hsotg_irq_enumdone(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 3068 | { |
95c8bc36 | 3069 | u32 dsts = dwc2_readl(hsotg->regs + DSTS); |
9b2667f1 | 3070 | int ep0_mps = 0, ep_mps = 8; |
5b7d70c6 | 3071 | |
8b9bc460 LM |
3072 | /* |
3073 | * This should signal the finish of the enumeration phase | |
5b7d70c6 | 3074 | * of the USB handshaking, so we should now know what rate |
8b9bc460 LM |
3075 | * we connected at. |
3076 | */ | |
5b7d70c6 BD |
3077 | |
3078 | dev_dbg(hsotg->dev, "EnumDone (DSTS=0x%08x)\n", dsts); | |
3079 | ||
8b9bc460 LM |
3080 | /* |
3081 | * note, since we're limited by the size of transfer on EP0, and | |
5b7d70c6 | 3082 | * it seems IN transfers must be a even number of packets we do |
8b9bc460 LM |
3083 | * not advertise a 64byte MPS on EP0. |
3084 | */ | |
5b7d70c6 BD |
3085 | |
3086 | /* catch both EnumSpd_FS and EnumSpd_FS48 */ | |
6d76c92c | 3087 | switch ((dsts & DSTS_ENUMSPD_MASK) >> DSTS_ENUMSPD_SHIFT) { |
47a1685f DN |
3088 | case DSTS_ENUMSPD_FS: |
3089 | case DSTS_ENUMSPD_FS48: | |
5b7d70c6 | 3090 | hsotg->gadget.speed = USB_SPEED_FULL; |
5b7d70c6 | 3091 | ep0_mps = EP0_MPS_LIMIT; |
295538ff | 3092 | ep_mps = 1023; |
5b7d70c6 BD |
3093 | break; |
3094 | ||
47a1685f | 3095 | case DSTS_ENUMSPD_HS: |
5b7d70c6 | 3096 | hsotg->gadget.speed = USB_SPEED_HIGH; |
5b7d70c6 | 3097 | ep0_mps = EP0_MPS_LIMIT; |
295538ff | 3098 | ep_mps = 1024; |
5b7d70c6 BD |
3099 | break; |
3100 | ||
47a1685f | 3101 | case DSTS_ENUMSPD_LS: |
5b7d70c6 | 3102 | hsotg->gadget.speed = USB_SPEED_LOW; |
552d940f VM |
3103 | ep0_mps = 8; |
3104 | ep_mps = 8; | |
8b9bc460 LM |
3105 | /* |
3106 | * note, we don't actually support LS in this driver at the | |
5b7d70c6 BD |
3107 | * moment, and the documentation seems to imply that it isn't |
3108 | * supported by the PHYs on some of the devices. | |
3109 | */ | |
3110 | break; | |
3111 | } | |
e538dfda MN |
3112 | dev_info(hsotg->dev, "new device is %s\n", |
3113 | usb_speed_string(hsotg->gadget.speed)); | |
5b7d70c6 | 3114 | |
8b9bc460 LM |
3115 | /* |
3116 | * we should now know the maximum packet size for an | |
3117 | * endpoint, so set the endpoints to a default value. | |
3118 | */ | |
5b7d70c6 BD |
3119 | |
3120 | if (ep0_mps) { | |
3121 | int i; | |
c6f5c050 | 3122 | /* Initialize ep0 for both in and out directions */ |
ee2c40de VM |
3123 | dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 0, 1); |
3124 | dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 0, 0); | |
c6f5c050 MYK |
3125 | for (i = 1; i < hsotg->num_of_eps; i++) { |
3126 | if (hsotg->eps_in[i]) | |
ee2c40de VM |
3127 | dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps, |
3128 | 0, 1); | |
c6f5c050 | 3129 | if (hsotg->eps_out[i]) |
ee2c40de VM |
3130 | dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps, |
3131 | 0, 0); | |
c6f5c050 | 3132 | } |
5b7d70c6 BD |
3133 | } |
3134 | ||
3135 | /* ensure after enumeration our EP0 is active */ | |
3136 | ||
1f91b4cc | 3137 | dwc2_hsotg_enqueue_setup(hsotg); |
5b7d70c6 BD |
3138 | |
3139 | dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n", | |
95c8bc36 AS |
3140 | dwc2_readl(hsotg->regs + DIEPCTL0), |
3141 | dwc2_readl(hsotg->regs + DOEPCTL0)); | |
5b7d70c6 BD |
3142 | } |
3143 | ||
3144 | /** | |
3145 | * kill_all_requests - remove all requests from the endpoint's queue | |
3146 | * @hsotg: The device state. | |
3147 | * @ep: The endpoint the requests may be on. | |
3148 | * @result: The result code to use. | |
5b7d70c6 BD |
3149 | * |
3150 | * Go through the requests on the given endpoint and mark them | |
3151 | * completed with the given result code. | |
3152 | */ | |
941fcce4 | 3153 | static void kill_all_requests(struct dwc2_hsotg *hsotg, |
1f91b4cc | 3154 | struct dwc2_hsotg_ep *ep, |
6b448af4 | 3155 | int result) |
5b7d70c6 | 3156 | { |
1f91b4cc | 3157 | struct dwc2_hsotg_req *req, *treq; |
9da51974 | 3158 | unsigned int size; |
5b7d70c6 | 3159 | |
6b448af4 | 3160 | ep->req = NULL; |
5b7d70c6 | 3161 | |
6b448af4 | 3162 | list_for_each_entry_safe(req, treq, &ep->queue, queue) |
1f91b4cc | 3163 | dwc2_hsotg_complete_request(hsotg, ep, req, |
9da51974 | 3164 | result); |
6b448af4 | 3165 | |
b203d0a2 RB |
3166 | if (!hsotg->dedicated_fifos) |
3167 | return; | |
ad674a15 | 3168 | size = (dwc2_readl(hsotg->regs + DTXFSTS(ep->fifo_index)) & 0xffff) * 4; |
b203d0a2 | 3169 | if (size < ep->fifo_size) |
1f91b4cc | 3170 | dwc2_hsotg_txfifo_flush(hsotg, ep->fifo_index); |
5b7d70c6 BD |
3171 | } |
3172 | ||
5b7d70c6 | 3173 | /** |
1f91b4cc | 3174 | * dwc2_hsotg_disconnect - disconnect service |
5b7d70c6 BD |
3175 | * @hsotg: The device state. |
3176 | * | |
5e891342 LM |
3177 | * The device has been disconnected. Remove all current |
3178 | * transactions and signal the gadget driver that this | |
3179 | * has happened. | |
8b9bc460 | 3180 | */ |
1f91b4cc | 3181 | void dwc2_hsotg_disconnect(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 3182 | { |
9da51974 | 3183 | unsigned int ep; |
5b7d70c6 | 3184 | |
4ace06e8 MS |
3185 | if (!hsotg->connected) |
3186 | return; | |
3187 | ||
3188 | hsotg->connected = 0; | |
9e14d0a5 | 3189 | hsotg->test_mode = 0; |
c6f5c050 MYK |
3190 | |
3191 | for (ep = 0; ep < hsotg->num_of_eps; ep++) { | |
3192 | if (hsotg->eps_in[ep]) | |
3193 | kill_all_requests(hsotg, hsotg->eps_in[ep], | |
9da51974 | 3194 | -ESHUTDOWN); |
c6f5c050 MYK |
3195 | if (hsotg->eps_out[ep]) |
3196 | kill_all_requests(hsotg, hsotg->eps_out[ep], | |
9da51974 | 3197 | -ESHUTDOWN); |
c6f5c050 | 3198 | } |
5b7d70c6 BD |
3199 | |
3200 | call_gadget(hsotg, disconnect); | |
065d3931 | 3201 | hsotg->lx_state = DWC2_L3; |
ce2b21a4 JS |
3202 | |
3203 | usb_gadget_set_state(&hsotg->gadget, USB_STATE_NOTATTACHED); | |
5b7d70c6 BD |
3204 | } |
3205 | ||
3206 | /** | |
1f91b4cc | 3207 | * dwc2_hsotg_irq_fifoempty - TX FIFO empty interrupt handler |
5b7d70c6 BD |
3208 | * @hsotg: The device state: |
3209 | * @periodic: True if this is a periodic FIFO interrupt | |
3210 | */ | |
1f91b4cc | 3211 | static void dwc2_hsotg_irq_fifoempty(struct dwc2_hsotg *hsotg, bool periodic) |
5b7d70c6 | 3212 | { |
1f91b4cc | 3213 | struct dwc2_hsotg_ep *ep; |
5b7d70c6 BD |
3214 | int epno, ret; |
3215 | ||
3216 | /* look through for any more data to transmit */ | |
b3f489b2 | 3217 | for (epno = 0; epno < hsotg->num_of_eps; epno++) { |
c6f5c050 MYK |
3218 | ep = index_to_ep(hsotg, epno, 1); |
3219 | ||
3220 | if (!ep) | |
3221 | continue; | |
5b7d70c6 BD |
3222 | |
3223 | if (!ep->dir_in) | |
3224 | continue; | |
3225 | ||
3226 | if ((periodic && !ep->periodic) || | |
3227 | (!periodic && ep->periodic)) | |
3228 | continue; | |
3229 | ||
1f91b4cc | 3230 | ret = dwc2_hsotg_trytx(hsotg, ep); |
5b7d70c6 BD |
3231 | if (ret < 0) |
3232 | break; | |
3233 | } | |
3234 | } | |
3235 | ||
5b7d70c6 | 3236 | /* IRQ flags which will trigger a retry around the IRQ loop */ |
47a1685f DN |
3237 | #define IRQ_RETRY_MASK (GINTSTS_NPTXFEMP | \ |
3238 | GINTSTS_PTXFEMP | \ | |
3239 | GINTSTS_RXFLVL) | |
5b7d70c6 | 3240 | |
8b9bc460 | 3241 | /** |
1f91b4cc | 3242 | * dwc2_hsotg_core_init - issue softreset to the core |
8b9bc460 LM |
3243 | * @hsotg: The device state |
3244 | * | |
3245 | * Issue a soft reset to the core, and await the core finishing it. | |
3246 | */ | |
1f91b4cc | 3247 | void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg, |
9da51974 | 3248 | bool is_usb_reset) |
308d734e | 3249 | { |
1ee6903b | 3250 | u32 intmsk; |
643cc4de | 3251 | u32 val; |
ecd9a7ad | 3252 | u32 usbcfg; |
79c3b5bb | 3253 | u32 dcfg = 0; |
643cc4de | 3254 | |
5390d438 MYK |
3255 | /* Kill any ep0 requests as controller will be reinitialized */ |
3256 | kill_all_requests(hsotg, hsotg->eps_out[0], -ECONNRESET); | |
3257 | ||
643cc4de | 3258 | if (!is_usb_reset) |
6e6360b6 | 3259 | if (dwc2_core_reset(hsotg, true)) |
86de4895 | 3260 | return; |
308d734e LM |
3261 | |
3262 | /* | |
3263 | * we must now enable ep0 ready for host detection and then | |
3264 | * set configuration. | |
3265 | */ | |
3266 | ||
ecd9a7ad PR |
3267 | /* keep other bits untouched (so e.g. forced modes are not lost) */ |
3268 | usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); | |
3269 | usbcfg &= ~(GUSBCFG_TOUTCAL_MASK | GUSBCFG_PHYIF16 | GUSBCFG_SRPCAP | | |
ca02954a | 3270 | GUSBCFG_HNPCAP | GUSBCFG_USBTRDTIM_MASK); |
ecd9a7ad | 3271 | |
79c3b5bb | 3272 | if (hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS && |
38e9002b VM |
3273 | (hsotg->params.speed == DWC2_SPEED_PARAM_FULL || |
3274 | hsotg->params.speed == DWC2_SPEED_PARAM_LOW)) { | |
79c3b5bb VA |
3275 | /* FS/LS Dedicated Transceiver Interface */ |
3276 | usbcfg |= GUSBCFG_PHYSEL; | |
3277 | } else { | |
3278 | /* set the PLL on, remove the HNP/SRP and set the PHY */ | |
3279 | val = (hsotg->phyif == GUSBCFG_PHYIF8) ? 9 : 5; | |
3280 | usbcfg |= hsotg->phyif | GUSBCFG_TOUTCAL(7) | | |
3281 | (val << GUSBCFG_USBTRDTIM_SHIFT); | |
3282 | } | |
ecd9a7ad | 3283 | dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); |
308d734e | 3284 | |
1f91b4cc | 3285 | dwc2_hsotg_init_fifo(hsotg); |
308d734e | 3286 | |
643cc4de GH |
3287 | if (!is_usb_reset) |
3288 | __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON); | |
308d734e | 3289 | |
79c3b5bb | 3290 | dcfg |= DCFG_EPMISCNT(1); |
38e9002b VM |
3291 | |
3292 | switch (hsotg->params.speed) { | |
3293 | case DWC2_SPEED_PARAM_LOW: | |
3294 | dcfg |= DCFG_DEVSPD_LS; | |
3295 | break; | |
3296 | case DWC2_SPEED_PARAM_FULL: | |
79c3b5bb VA |
3297 | if (hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS) |
3298 | dcfg |= DCFG_DEVSPD_FS48; | |
3299 | else | |
3300 | dcfg |= DCFG_DEVSPD_FS; | |
38e9002b VM |
3301 | break; |
3302 | default: | |
79c3b5bb VA |
3303 | dcfg |= DCFG_DEVSPD_HS; |
3304 | } | |
38e9002b | 3305 | |
79c3b5bb | 3306 | dwc2_writel(dcfg, hsotg->regs + DCFG); |
308d734e LM |
3307 | |
3308 | /* Clear any pending OTG interrupts */ | |
95c8bc36 | 3309 | dwc2_writel(0xffffffff, hsotg->regs + GOTGINT); |
308d734e LM |
3310 | |
3311 | /* Clear any pending interrupts */ | |
95c8bc36 | 3312 | dwc2_writel(0xffffffff, hsotg->regs + GINTSTS); |
1ee6903b | 3313 | intmsk = GINTSTS_ERLYSUSP | GINTSTS_SESSREQINT | |
47a1685f | 3314 | GINTSTS_GOUTNAKEFF | GINTSTS_GINNAKEFF | |
1ee6903b GH |
3315 | GINTSTS_USBRST | GINTSTS_RESETDET | |
3316 | GINTSTS_ENUMDONE | GINTSTS_OTGINT | | |
f4736701 VA |
3317 | GINTSTS_USBSUSP | GINTSTS_WKUPINT; |
3318 | ||
3319 | if (!using_desc_dma(hsotg)) | |
3320 | intmsk |= GINTSTS_INCOMPL_SOIN | GINTSTS_INCOMPL_SOOUT; | |
1ee6903b | 3321 | |
95832c00 | 3322 | if (!hsotg->params.external_id_pin_ctl) |
1ee6903b GH |
3323 | intmsk |= GINTSTS_CONIDSTSCHNG; |
3324 | ||
3325 | dwc2_writel(intmsk, hsotg->regs + GINTMSK); | |
308d734e | 3326 | |
a5c18f11 | 3327 | if (using_dma(hsotg)) { |
95c8bc36 AS |
3328 | dwc2_writel(GAHBCFG_GLBL_INTR_EN | GAHBCFG_DMA_EN | |
3329 | (GAHBCFG_HBSTLEN_INCR4 << GAHBCFG_HBSTLEN_SHIFT), | |
3330 | hsotg->regs + GAHBCFG); | |
a5c18f11 VA |
3331 | |
3332 | /* Set DDMA mode support in the core if needed */ | |
3333 | if (using_desc_dma(hsotg)) | |
3334 | __orr32(hsotg->regs + DCFG, DCFG_DESCDMA_EN); | |
3335 | ||
3336 | } else { | |
95c8bc36 AS |
3337 | dwc2_writel(((hsotg->dedicated_fifos) ? |
3338 | (GAHBCFG_NP_TXF_EMP_LVL | | |
3339 | GAHBCFG_P_TXF_EMP_LVL) : 0) | | |
3340 | GAHBCFG_GLBL_INTR_EN, hsotg->regs + GAHBCFG); | |
a5c18f11 | 3341 | } |
308d734e LM |
3342 | |
3343 | /* | |
8acc8296 RB |
3344 | * If INTknTXFEmpMsk is enabled, it's important to disable ep interrupts |
3345 | * when we have no data to transfer. Otherwise we get being flooded by | |
3346 | * interrupts. | |
308d734e LM |
3347 | */ |
3348 | ||
95c8bc36 | 3349 | dwc2_writel(((hsotg->dedicated_fifos && !using_dma(hsotg)) ? |
6ff2e832 | 3350 | DIEPMSK_TXFIFOEMPTY | DIEPMSK_INTKNTXFEMPMSK : 0) | |
47a1685f | 3351 | DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK | |
837e9f00 | 3352 | DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK, |
47a1685f | 3353 | hsotg->regs + DIEPMSK); |
308d734e LM |
3354 | |
3355 | /* | |
3356 | * don't need XferCompl, we get that from RXFIFO in slave mode. In | |
9d9a6b07 | 3357 | * DMA mode we may need this and StsPhseRcvd. |
308d734e | 3358 | */ |
9d9a6b07 VA |
3359 | dwc2_writel((using_dma(hsotg) ? (DIEPMSK_XFERCOMPLMSK | |
3360 | DOEPMSK_STSPHSERCVDMSK) : 0) | | |
47a1685f | 3361 | DOEPMSK_EPDISBLDMSK | DOEPMSK_AHBERRMSK | |
9d9a6b07 | 3362 | DOEPMSK_SETUPMSK, |
47a1685f | 3363 | hsotg->regs + DOEPMSK); |
308d734e | 3364 | |
ec01f0b2 VA |
3365 | /* Enable BNA interrupt for DDMA */ |
3366 | if (using_desc_dma(hsotg)) | |
3367 | __orr32(hsotg->regs + DOEPMSK, DOEPMSK_BNAMSK); | |
3368 | ||
95c8bc36 | 3369 | dwc2_writel(0, hsotg->regs + DAINTMSK); |
308d734e LM |
3370 | |
3371 | dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n", | |
95c8bc36 AS |
3372 | dwc2_readl(hsotg->regs + DIEPCTL0), |
3373 | dwc2_readl(hsotg->regs + DOEPCTL0)); | |
308d734e LM |
3374 | |
3375 | /* enable in and out endpoint interrupts */ | |
1f91b4cc | 3376 | dwc2_hsotg_en_gsint(hsotg, GINTSTS_OEPINT | GINTSTS_IEPINT); |
308d734e LM |
3377 | |
3378 | /* | |
3379 | * Enable the RXFIFO when in slave mode, as this is how we collect | |
3380 | * the data. In DMA mode, we get events from the FIFO but also | |
3381 | * things we cannot process, so do not use it. | |
3382 | */ | |
3383 | if (!using_dma(hsotg)) | |
1f91b4cc | 3384 | dwc2_hsotg_en_gsint(hsotg, GINTSTS_RXFLVL); |
308d734e LM |
3385 | |
3386 | /* Enable interrupts for EP0 in and out */ | |
1f91b4cc FB |
3387 | dwc2_hsotg_ctrl_epint(hsotg, 0, 0, 1); |
3388 | dwc2_hsotg_ctrl_epint(hsotg, 0, 1, 1); | |
308d734e | 3389 | |
643cc4de GH |
3390 | if (!is_usb_reset) { |
3391 | __orr32(hsotg->regs + DCTL, DCTL_PWRONPRGDONE); | |
3392 | udelay(10); /* see openiboot */ | |
3393 | __bic32(hsotg->regs + DCTL, DCTL_PWRONPRGDONE); | |
3394 | } | |
308d734e | 3395 | |
95c8bc36 | 3396 | dev_dbg(hsotg->dev, "DCTL=0x%08x\n", dwc2_readl(hsotg->regs + DCTL)); |
308d734e LM |
3397 | |
3398 | /* | |
94cb8fd6 | 3399 | * DxEPCTL_USBActEp says RO in manual, but seems to be set by |
308d734e LM |
3400 | * writing to the EPCTL register.. |
3401 | */ | |
3402 | ||
3403 | /* set to read 1 8byte packet */ | |
95c8bc36 | 3404 | dwc2_writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) | |
47a1685f | 3405 | DXEPTSIZ_XFERSIZE(8), hsotg->regs + DOEPTSIZ0); |
308d734e | 3406 | |
95c8bc36 | 3407 | dwc2_writel(dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) | |
47a1685f DN |
3408 | DXEPCTL_CNAK | DXEPCTL_EPENA | |
3409 | DXEPCTL_USBACTEP, | |
94cb8fd6 | 3410 | hsotg->regs + DOEPCTL0); |
308d734e LM |
3411 | |
3412 | /* enable, but don't activate EP0in */ | |
95c8bc36 | 3413 | dwc2_writel(dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) | |
47a1685f | 3414 | DXEPCTL_USBACTEP, hsotg->regs + DIEPCTL0); |
308d734e | 3415 | |
1f91b4cc | 3416 | dwc2_hsotg_enqueue_setup(hsotg); |
308d734e LM |
3417 | |
3418 | dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n", | |
95c8bc36 AS |
3419 | dwc2_readl(hsotg->regs + DIEPCTL0), |
3420 | dwc2_readl(hsotg->regs + DOEPCTL0)); | |
308d734e LM |
3421 | |
3422 | /* clear global NAKs */ | |
643cc4de GH |
3423 | val = DCTL_CGOUTNAK | DCTL_CGNPINNAK; |
3424 | if (!is_usb_reset) | |
3425 | val |= DCTL_SFTDISCON; | |
3426 | __orr32(hsotg->regs + DCTL, val); | |
308d734e LM |
3427 | |
3428 | /* must be at-least 3ms to allow bus to see disconnect */ | |
3429 | mdelay(3); | |
3430 | ||
065d3931 | 3431 | hsotg->lx_state = DWC2_L0; |
ad38dc5d MS |
3432 | } |
3433 | ||
1f91b4cc | 3434 | static void dwc2_hsotg_core_disconnect(struct dwc2_hsotg *hsotg) |
ad38dc5d MS |
3435 | { |
3436 | /* set the soft-disconnect bit */ | |
3437 | __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON); | |
3438 | } | |
ac3c81f3 | 3439 | |
1f91b4cc | 3440 | void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg) |
ad38dc5d | 3441 | { |
308d734e | 3442 | /* remove the soft-disconnect and let's go */ |
47a1685f | 3443 | __bic32(hsotg->regs + DCTL, DCTL_SFTDISCON); |
308d734e LM |
3444 | } |
3445 | ||
381fc8f8 VM |
3446 | /** |
3447 | * dwc2_gadget_handle_incomplete_isoc_in - handle incomplete ISO IN Interrupt. | |
3448 | * @hsotg: The device state: | |
3449 | * | |
3450 | * This interrupt indicates one of the following conditions occurred while | |
3451 | * transmitting an ISOC transaction. | |
3452 | * - Corrupted IN Token for ISOC EP. | |
3453 | * - Packet not complete in FIFO. | |
3454 | * | |
3455 | * The following actions will be taken: | |
3456 | * - Determine the EP | |
3457 | * - Disable EP; when 'Endpoint Disabled' interrupt is received Flush FIFO | |
3458 | */ | |
3459 | static void dwc2_gadget_handle_incomplete_isoc_in(struct dwc2_hsotg *hsotg) | |
3460 | { | |
3461 | struct dwc2_hsotg_ep *hs_ep; | |
3462 | u32 epctrl; | |
3463 | u32 idx; | |
3464 | ||
3465 | dev_dbg(hsotg->dev, "Incomplete isoc in interrupt received:\n"); | |
3466 | ||
3467 | for (idx = 1; idx <= hsotg->num_of_eps; idx++) { | |
3468 | hs_ep = hsotg->eps_in[idx]; | |
3469 | epctrl = dwc2_readl(hsotg->regs + DIEPCTL(idx)); | |
3470 | if ((epctrl & DXEPCTL_EPENA) && hs_ep->isochronous && | |
3471 | dwc2_gadget_target_frame_elapsed(hs_ep)) { | |
3472 | epctrl |= DXEPCTL_SNAK; | |
3473 | epctrl |= DXEPCTL_EPDIS; | |
3474 | dwc2_writel(epctrl, hsotg->regs + DIEPCTL(idx)); | |
3475 | } | |
3476 | } | |
3477 | ||
3478 | /* Clear interrupt */ | |
3479 | dwc2_writel(GINTSTS_INCOMPL_SOIN, hsotg->regs + GINTSTS); | |
3480 | } | |
3481 | ||
3482 | /** | |
3483 | * dwc2_gadget_handle_incomplete_isoc_out - handle incomplete ISO OUT Interrupt | |
3484 | * @hsotg: The device state: | |
3485 | * | |
3486 | * This interrupt indicates one of the following conditions occurred while | |
3487 | * transmitting an ISOC transaction. | |
3488 | * - Corrupted OUT Token for ISOC EP. | |
3489 | * - Packet not complete in FIFO. | |
3490 | * | |
3491 | * The following actions will be taken: | |
3492 | * - Determine the EP | |
3493 | * - Set DCTL_SGOUTNAK and unmask GOUTNAKEFF if target frame elapsed. | |
3494 | */ | |
3495 | static void dwc2_gadget_handle_incomplete_isoc_out(struct dwc2_hsotg *hsotg) | |
3496 | { | |
3497 | u32 gintsts; | |
3498 | u32 gintmsk; | |
3499 | u32 epctrl; | |
3500 | struct dwc2_hsotg_ep *hs_ep; | |
3501 | int idx; | |
3502 | ||
3503 | dev_dbg(hsotg->dev, "%s: GINTSTS_INCOMPL_SOOUT\n", __func__); | |
3504 | ||
3505 | for (idx = 1; idx <= hsotg->num_of_eps; idx++) { | |
3506 | hs_ep = hsotg->eps_out[idx]; | |
3507 | epctrl = dwc2_readl(hsotg->regs + DOEPCTL(idx)); | |
3508 | if ((epctrl & DXEPCTL_EPENA) && hs_ep->isochronous && | |
3509 | dwc2_gadget_target_frame_elapsed(hs_ep)) { | |
3510 | /* Unmask GOUTNAKEFF interrupt */ | |
3511 | gintmsk = dwc2_readl(hsotg->regs + GINTMSK); | |
3512 | gintmsk |= GINTSTS_GOUTNAKEFF; | |
3513 | dwc2_writel(gintmsk, hsotg->regs + GINTMSK); | |
3514 | ||
3515 | gintsts = dwc2_readl(hsotg->regs + GINTSTS); | |
3516 | if (!(gintsts & GINTSTS_GOUTNAKEFF)) | |
3517 | __orr32(hsotg->regs + DCTL, DCTL_SGOUTNAK); | |
3518 | } | |
3519 | } | |
3520 | ||
3521 | /* Clear interrupt */ | |
3522 | dwc2_writel(GINTSTS_INCOMPL_SOOUT, hsotg->regs + GINTSTS); | |
3523 | } | |
3524 | ||
5b7d70c6 | 3525 | /** |
1f91b4cc | 3526 | * dwc2_hsotg_irq - handle device interrupt |
5b7d70c6 BD |
3527 | * @irq: The IRQ number triggered |
3528 | * @pw: The pw value when registered the handler. | |
3529 | */ | |
1f91b4cc | 3530 | static irqreturn_t dwc2_hsotg_irq(int irq, void *pw) |
5b7d70c6 | 3531 | { |
941fcce4 | 3532 | struct dwc2_hsotg *hsotg = pw; |
5b7d70c6 BD |
3533 | int retry_count = 8; |
3534 | u32 gintsts; | |
3535 | u32 gintmsk; | |
3536 | ||
ee3de8d7 VM |
3537 | if (!dwc2_is_device_mode(hsotg)) |
3538 | return IRQ_NONE; | |
3539 | ||
5ad1d316 | 3540 | spin_lock(&hsotg->lock); |
5b7d70c6 | 3541 | irq_retry: |
95c8bc36 AS |
3542 | gintsts = dwc2_readl(hsotg->regs + GINTSTS); |
3543 | gintmsk = dwc2_readl(hsotg->regs + GINTMSK); | |
5b7d70c6 BD |
3544 | |
3545 | dev_dbg(hsotg->dev, "%s: %08x %08x (%08x) retry %d\n", | |
3546 | __func__, gintsts, gintsts & gintmsk, gintmsk, retry_count); | |
3547 | ||
3548 | gintsts &= gintmsk; | |
3549 | ||
8fc37b82 MYK |
3550 | if (gintsts & GINTSTS_RESETDET) { |
3551 | dev_dbg(hsotg->dev, "%s: USBRstDet\n", __func__); | |
3552 | ||
3553 | dwc2_writel(GINTSTS_RESETDET, hsotg->regs + GINTSTS); | |
3554 | ||
3555 | /* This event must be used only if controller is suspended */ | |
3556 | if (hsotg->lx_state == DWC2_L2) { | |
3557 | dwc2_exit_hibernation(hsotg, true); | |
3558 | hsotg->lx_state = DWC2_L0; | |
3559 | } | |
3560 | } | |
3561 | ||
3562 | if (gintsts & (GINTSTS_USBRST | GINTSTS_RESETDET)) { | |
8fc37b82 MYK |
3563 | u32 usb_status = dwc2_readl(hsotg->regs + GOTGCTL); |
3564 | u32 connected = hsotg->connected; | |
3565 | ||
3566 | dev_dbg(hsotg->dev, "%s: USBRst\n", __func__); | |
3567 | dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n", | |
3568 | dwc2_readl(hsotg->regs + GNPTXSTS)); | |
3569 | ||
3570 | dwc2_writel(GINTSTS_USBRST, hsotg->regs + GINTSTS); | |
3571 | ||
3572 | /* Report disconnection if it is not already done. */ | |
3573 | dwc2_hsotg_disconnect(hsotg); | |
3574 | ||
307bc11f MH |
3575 | /* Reset device address to zero */ |
3576 | __bic32(hsotg->regs + DCFG, DCFG_DEVADDR_MASK); | |
3577 | ||
8fc37b82 MYK |
3578 | if (usb_status & GOTGCTL_BSESVLD && connected) |
3579 | dwc2_hsotg_core_init_disconnected(hsotg, true); | |
3580 | } | |
3581 | ||
47a1685f | 3582 | if (gintsts & GINTSTS_ENUMDONE) { |
95c8bc36 | 3583 | dwc2_writel(GINTSTS_ENUMDONE, hsotg->regs + GINTSTS); |
a3395f0d | 3584 | |
1f91b4cc | 3585 | dwc2_hsotg_irq_enumdone(hsotg); |
5b7d70c6 BD |
3586 | } |
3587 | ||
47a1685f | 3588 | if (gintsts & (GINTSTS_OEPINT | GINTSTS_IEPINT)) { |
95c8bc36 AS |
3589 | u32 daint = dwc2_readl(hsotg->regs + DAINT); |
3590 | u32 daintmsk = dwc2_readl(hsotg->regs + DAINTMSK); | |
7e804650 | 3591 | u32 daint_out, daint_in; |
5b7d70c6 BD |
3592 | int ep; |
3593 | ||
7e804650 | 3594 | daint &= daintmsk; |
47a1685f DN |
3595 | daint_out = daint >> DAINT_OUTEP_SHIFT; |
3596 | daint_in = daint & ~(daint_out << DAINT_OUTEP_SHIFT); | |
7e804650 | 3597 | |
5b7d70c6 BD |
3598 | dev_dbg(hsotg->dev, "%s: daint=%08x\n", __func__, daint); |
3599 | ||
cec87f1d MYK |
3600 | for (ep = 0; ep < hsotg->num_of_eps && daint_out; |
3601 | ep++, daint_out >>= 1) { | |
5b7d70c6 | 3602 | if (daint_out & 1) |
1f91b4cc | 3603 | dwc2_hsotg_epint(hsotg, ep, 0); |
5b7d70c6 BD |
3604 | } |
3605 | ||
cec87f1d MYK |
3606 | for (ep = 0; ep < hsotg->num_of_eps && daint_in; |
3607 | ep++, daint_in >>= 1) { | |
5b7d70c6 | 3608 | if (daint_in & 1) |
1f91b4cc | 3609 | dwc2_hsotg_epint(hsotg, ep, 1); |
5b7d70c6 | 3610 | } |
5b7d70c6 BD |
3611 | } |
3612 | ||
5b7d70c6 BD |
3613 | /* check both FIFOs */ |
3614 | ||
47a1685f | 3615 | if (gintsts & GINTSTS_NPTXFEMP) { |
5b7d70c6 BD |
3616 | dev_dbg(hsotg->dev, "NPTxFEmp\n"); |
3617 | ||
8b9bc460 LM |
3618 | /* |
3619 | * Disable the interrupt to stop it happening again | |
5b7d70c6 | 3620 | * unless one of these endpoint routines decides that |
8b9bc460 LM |
3621 | * it needs re-enabling |
3622 | */ | |
5b7d70c6 | 3623 | |
1f91b4cc FB |
3624 | dwc2_hsotg_disable_gsint(hsotg, GINTSTS_NPTXFEMP); |
3625 | dwc2_hsotg_irq_fifoempty(hsotg, false); | |
5b7d70c6 BD |
3626 | } |
3627 | ||
47a1685f | 3628 | if (gintsts & GINTSTS_PTXFEMP) { |
5b7d70c6 BD |
3629 | dev_dbg(hsotg->dev, "PTxFEmp\n"); |
3630 | ||
94cb8fd6 | 3631 | /* See note in GINTSTS_NPTxFEmp */ |
5b7d70c6 | 3632 | |
1f91b4cc FB |
3633 | dwc2_hsotg_disable_gsint(hsotg, GINTSTS_PTXFEMP); |
3634 | dwc2_hsotg_irq_fifoempty(hsotg, true); | |
5b7d70c6 BD |
3635 | } |
3636 | ||
47a1685f | 3637 | if (gintsts & GINTSTS_RXFLVL) { |
8b9bc460 LM |
3638 | /* |
3639 | * note, since GINTSTS_RxFLvl doubles as FIFO-not-empty, | |
1f91b4cc | 3640 | * we need to retry dwc2_hsotg_handle_rx if this is still |
8b9bc460 LM |
3641 | * set. |
3642 | */ | |
5b7d70c6 | 3643 | |
1f91b4cc | 3644 | dwc2_hsotg_handle_rx(hsotg); |
5b7d70c6 BD |
3645 | } |
3646 | ||
47a1685f | 3647 | if (gintsts & GINTSTS_ERLYSUSP) { |
94cb8fd6 | 3648 | dev_dbg(hsotg->dev, "GINTSTS_ErlySusp\n"); |
95c8bc36 | 3649 | dwc2_writel(GINTSTS_ERLYSUSP, hsotg->regs + GINTSTS); |
5b7d70c6 BD |
3650 | } |
3651 | ||
8b9bc460 LM |
3652 | /* |
3653 | * these next two seem to crop-up occasionally causing the core | |
5b7d70c6 | 3654 | * to shutdown the USB transfer, so try clearing them and logging |
8b9bc460 LM |
3655 | * the occurrence. |
3656 | */ | |
5b7d70c6 | 3657 | |
47a1685f | 3658 | if (gintsts & GINTSTS_GOUTNAKEFF) { |
837e9f00 VM |
3659 | u8 idx; |
3660 | u32 epctrl; | |
3661 | u32 gintmsk; | |
3662 | struct dwc2_hsotg_ep *hs_ep; | |
3663 | ||
3664 | /* Mask this interrupt */ | |
3665 | gintmsk = dwc2_readl(hsotg->regs + GINTMSK); | |
3666 | gintmsk &= ~GINTSTS_GOUTNAKEFF; | |
3667 | dwc2_writel(gintmsk, hsotg->regs + GINTMSK); | |
3668 | ||
3669 | dev_dbg(hsotg->dev, "GOUTNakEff triggered\n"); | |
3670 | for (idx = 1; idx <= hsotg->num_of_eps; idx++) { | |
3671 | hs_ep = hsotg->eps_out[idx]; | |
3672 | epctrl = dwc2_readl(hsotg->regs + DOEPCTL(idx)); | |
3673 | ||
3674 | if ((epctrl & DXEPCTL_EPENA) && hs_ep->isochronous) { | |
3675 | epctrl |= DXEPCTL_SNAK; | |
3676 | epctrl |= DXEPCTL_EPDIS; | |
3677 | dwc2_writel(epctrl, hsotg->regs + DOEPCTL(idx)); | |
3678 | } | |
3679 | } | |
a3395f0d | 3680 | |
837e9f00 | 3681 | /* This interrupt bit is cleared in DXEPINT_EPDISBLD handler */ |
5b7d70c6 BD |
3682 | } |
3683 | ||
47a1685f | 3684 | if (gintsts & GINTSTS_GINNAKEFF) { |
5b7d70c6 BD |
3685 | dev_info(hsotg->dev, "GINNakEff triggered\n"); |
3686 | ||
3be99cd0 | 3687 | __orr32(hsotg->regs + DCTL, DCTL_CGNPINNAK); |
a3395f0d | 3688 | |
1f91b4cc | 3689 | dwc2_hsotg_dump(hsotg); |
5b7d70c6 BD |
3690 | } |
3691 | ||
381fc8f8 VM |
3692 | if (gintsts & GINTSTS_INCOMPL_SOIN) |
3693 | dwc2_gadget_handle_incomplete_isoc_in(hsotg); | |
ec1f9d9f | 3694 | |
381fc8f8 VM |
3695 | if (gintsts & GINTSTS_INCOMPL_SOOUT) |
3696 | dwc2_gadget_handle_incomplete_isoc_out(hsotg); | |
ec1f9d9f | 3697 | |
8b9bc460 LM |
3698 | /* |
3699 | * if we've had fifo events, we should try and go around the | |
3700 | * loop again to see if there's any point in returning yet. | |
3701 | */ | |
5b7d70c6 BD |
3702 | |
3703 | if (gintsts & IRQ_RETRY_MASK && --retry_count > 0) | |
77b6200e | 3704 | goto irq_retry; |
5b7d70c6 | 3705 | |
5ad1d316 LM |
3706 | spin_unlock(&hsotg->lock); |
3707 | ||
5b7d70c6 BD |
3708 | return IRQ_HANDLED; |
3709 | } | |
3710 | ||
a4f82771 VA |
3711 | static int dwc2_hsotg_wait_bit_set(struct dwc2_hsotg *hs_otg, u32 reg, |
3712 | u32 bit, u32 timeout) | |
3713 | { | |
3714 | u32 i; | |
3715 | ||
3716 | for (i = 0; i < timeout; i++) { | |
3717 | if (dwc2_readl(hs_otg->regs + reg) & bit) | |
3718 | return 0; | |
3719 | udelay(1); | |
3720 | } | |
3721 | ||
3722 | return -ETIMEDOUT; | |
3723 | } | |
3724 | ||
3725 | static void dwc2_hsotg_ep_stop_xfr(struct dwc2_hsotg *hsotg, | |
3726 | struct dwc2_hsotg_ep *hs_ep) | |
3727 | { | |
3728 | u32 epctrl_reg; | |
3729 | u32 epint_reg; | |
3730 | ||
3731 | epctrl_reg = hs_ep->dir_in ? DIEPCTL(hs_ep->index) : | |
3732 | DOEPCTL(hs_ep->index); | |
3733 | epint_reg = hs_ep->dir_in ? DIEPINT(hs_ep->index) : | |
3734 | DOEPINT(hs_ep->index); | |
3735 | ||
3736 | dev_dbg(hsotg->dev, "%s: stopping transfer on %s\n", __func__, | |
3737 | hs_ep->name); | |
3738 | ||
3739 | if (hs_ep->dir_in) { | |
3740 | if (hsotg->dedicated_fifos || hs_ep->periodic) { | |
3741 | __orr32(hsotg->regs + epctrl_reg, DXEPCTL_SNAK); | |
3742 | /* Wait for Nak effect */ | |
3743 | if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg, | |
3744 | DXEPINT_INEPNAKEFF, 100)) | |
3745 | dev_warn(hsotg->dev, | |
3746 | "%s: timeout DIEPINT.NAKEFF\n", | |
3747 | __func__); | |
3748 | } else { | |
3749 | __orr32(hsotg->regs + DCTL, DCTL_SGNPINNAK); | |
3750 | /* Wait for Nak effect */ | |
3751 | if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS, | |
3752 | GINTSTS_GINNAKEFF, 100)) | |
3753 | dev_warn(hsotg->dev, | |
3754 | "%s: timeout GINTSTS.GINNAKEFF\n", | |
3755 | __func__); | |
3756 | } | |
3757 | } else { | |
3758 | if (!(dwc2_readl(hsotg->regs + GINTSTS) & GINTSTS_GOUTNAKEFF)) | |
3759 | __orr32(hsotg->regs + DCTL, DCTL_SGOUTNAK); | |
3760 | ||
3761 | /* Wait for global nak to take effect */ | |
3762 | if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS, | |
3763 | GINTSTS_GOUTNAKEFF, 100)) | |
3764 | dev_warn(hsotg->dev, "%s: timeout GINTSTS.GOUTNAKEFF\n", | |
3765 | __func__); | |
3766 | } | |
3767 | ||
3768 | /* Disable ep */ | |
3769 | __orr32(hsotg->regs + epctrl_reg, DXEPCTL_EPDIS | DXEPCTL_SNAK); | |
3770 | ||
3771 | /* Wait for ep to be disabled */ | |
3772 | if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg, DXEPINT_EPDISBLD, 100)) | |
3773 | dev_warn(hsotg->dev, | |
3774 | "%s: timeout DOEPCTL.EPDisable\n", __func__); | |
3775 | ||
3776 | /* Clear EPDISBLD interrupt */ | |
3777 | __orr32(hsotg->regs + epint_reg, DXEPINT_EPDISBLD); | |
3778 | ||
3779 | if (hs_ep->dir_in) { | |
3780 | unsigned short fifo_index; | |
3781 | ||
3782 | if (hsotg->dedicated_fifos || hs_ep->periodic) | |
3783 | fifo_index = hs_ep->fifo_index; | |
3784 | else | |
3785 | fifo_index = 0; | |
3786 | ||
3787 | /* Flush TX FIFO */ | |
3788 | dwc2_flush_tx_fifo(hsotg, fifo_index); | |
3789 | ||
3790 | /* Clear Global In NP NAK in Shared FIFO for non periodic ep */ | |
3791 | if (!hsotg->dedicated_fifos && !hs_ep->periodic) | |
3792 | __orr32(hsotg->regs + DCTL, DCTL_CGNPINNAK); | |
3793 | ||
3794 | } else { | |
3795 | /* Remove global NAKs */ | |
3796 | __orr32(hsotg->regs + DCTL, DCTL_CGOUTNAK); | |
3797 | } | |
3798 | } | |
3799 | ||
5b7d70c6 | 3800 | /** |
1f91b4cc | 3801 | * dwc2_hsotg_ep_enable - enable the given endpoint |
5b7d70c6 BD |
3802 | * @ep: The USB endpint to configure |
3803 | * @desc: The USB endpoint descriptor to configure with. | |
3804 | * | |
3805 | * This is called from the USB gadget code's usb_ep_enable(). | |
8b9bc460 | 3806 | */ |
1f91b4cc | 3807 | static int dwc2_hsotg_ep_enable(struct usb_ep *ep, |
9da51974 | 3808 | const struct usb_endpoint_descriptor *desc) |
5b7d70c6 | 3809 | { |
1f91b4cc | 3810 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 3811 | struct dwc2_hsotg *hsotg = hs_ep->parent; |
5b7d70c6 | 3812 | unsigned long flags; |
ca4c55ad | 3813 | unsigned int index = hs_ep->index; |
5b7d70c6 BD |
3814 | u32 epctrl_reg; |
3815 | u32 epctrl; | |
3816 | u32 mps; | |
ee2c40de | 3817 | u32 mc; |
837e9f00 | 3818 | u32 mask; |
ca4c55ad MYK |
3819 | unsigned int dir_in; |
3820 | unsigned int i, val, size; | |
19c190f9 | 3821 | int ret = 0; |
5b7d70c6 BD |
3822 | |
3823 | dev_dbg(hsotg->dev, | |
3824 | "%s: ep %s: a 0x%02x, attr 0x%02x, mps 0x%04x, intr %d\n", | |
3825 | __func__, ep->name, desc->bEndpointAddress, desc->bmAttributes, | |
3826 | desc->wMaxPacketSize, desc->bInterval); | |
3827 | ||
3828 | /* not to be called for EP0 */ | |
8c3d6092 VA |
3829 | if (index == 0) { |
3830 | dev_err(hsotg->dev, "%s: called for EP 0\n", __func__); | |
3831 | return -EINVAL; | |
3832 | } | |
5b7d70c6 BD |
3833 | |
3834 | dir_in = (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) ? 1 : 0; | |
3835 | if (dir_in != hs_ep->dir_in) { | |
3836 | dev_err(hsotg->dev, "%s: direction mismatch!\n", __func__); | |
3837 | return -EINVAL; | |
3838 | } | |
3839 | ||
29cc8897 | 3840 | mps = usb_endpoint_maxp(desc); |
ee2c40de | 3841 | mc = usb_endpoint_maxp_mult(desc); |
5b7d70c6 | 3842 | |
1f91b4cc | 3843 | /* note, we handle this here instead of dwc2_hsotg_set_ep_maxpacket */ |
5b7d70c6 | 3844 | |
94cb8fd6 | 3845 | epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index); |
95c8bc36 | 3846 | epctrl = dwc2_readl(hsotg->regs + epctrl_reg); |
5b7d70c6 BD |
3847 | |
3848 | dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x from 0x%08x\n", | |
3849 | __func__, epctrl, epctrl_reg); | |
3850 | ||
5f54c54b | 3851 | /* Allocate DMA descriptor chain for non-ctrl endpoints */ |
9383e084 VM |
3852 | if (using_desc_dma(hsotg) && !hs_ep->desc_list) { |
3853 | hs_ep->desc_list = dmam_alloc_coherent(hsotg->dev, | |
5f54c54b VA |
3854 | MAX_DMA_DESC_NUM_GENERIC * |
3855 | sizeof(struct dwc2_dma_desc), | |
86e881e7 | 3856 | &hs_ep->desc_list_dma, GFP_ATOMIC); |
5f54c54b VA |
3857 | if (!hs_ep->desc_list) { |
3858 | ret = -ENOMEM; | |
3859 | goto error2; | |
3860 | } | |
3861 | } | |
3862 | ||
22258f49 | 3863 | spin_lock_irqsave(&hsotg->lock, flags); |
5b7d70c6 | 3864 | |
47a1685f DN |
3865 | epctrl &= ~(DXEPCTL_EPTYPE_MASK | DXEPCTL_MPS_MASK); |
3866 | epctrl |= DXEPCTL_MPS(mps); | |
5b7d70c6 | 3867 | |
8b9bc460 LM |
3868 | /* |
3869 | * mark the endpoint as active, otherwise the core may ignore | |
3870 | * transactions entirely for this endpoint | |
3871 | */ | |
47a1685f | 3872 | epctrl |= DXEPCTL_USBACTEP; |
5b7d70c6 | 3873 | |
5b7d70c6 | 3874 | /* update the endpoint state */ |
ee2c40de | 3875 | dwc2_hsotg_set_ep_maxpacket(hsotg, hs_ep->index, mps, mc, dir_in); |
5b7d70c6 BD |
3876 | |
3877 | /* default, set to non-periodic */ | |
1479e841 | 3878 | hs_ep->isochronous = 0; |
5b7d70c6 | 3879 | hs_ep->periodic = 0; |
a18ed7b0 | 3880 | hs_ep->halted = 0; |
1479e841 | 3881 | hs_ep->interval = desc->bInterval; |
4fca54aa | 3882 | |
5b7d70c6 BD |
3883 | switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) { |
3884 | case USB_ENDPOINT_XFER_ISOC: | |
47a1685f DN |
3885 | epctrl |= DXEPCTL_EPTYPE_ISO; |
3886 | epctrl |= DXEPCTL_SETEVENFR; | |
1479e841 | 3887 | hs_ep->isochronous = 1; |
142bd33f | 3888 | hs_ep->interval = 1 << (desc->bInterval - 1); |
837e9f00 | 3889 | hs_ep->target_frame = TARGET_FRAME_INITIAL; |
ab7d2192 VA |
3890 | hs_ep->isoc_chain_num = 0; |
3891 | hs_ep->next_desc = 0; | |
837e9f00 | 3892 | if (dir_in) { |
1479e841 | 3893 | hs_ep->periodic = 1; |
837e9f00 VM |
3894 | mask = dwc2_readl(hsotg->regs + DIEPMSK); |
3895 | mask |= DIEPMSK_NAKMSK; | |
3896 | dwc2_writel(mask, hsotg->regs + DIEPMSK); | |
3897 | } else { | |
3898 | mask = dwc2_readl(hsotg->regs + DOEPMSK); | |
3899 | mask |= DOEPMSK_OUTTKNEPDISMSK; | |
3900 | dwc2_writel(mask, hsotg->regs + DOEPMSK); | |
3901 | } | |
1479e841 | 3902 | break; |
5b7d70c6 BD |
3903 | |
3904 | case USB_ENDPOINT_XFER_BULK: | |
47a1685f | 3905 | epctrl |= DXEPCTL_EPTYPE_BULK; |
5b7d70c6 BD |
3906 | break; |
3907 | ||
3908 | case USB_ENDPOINT_XFER_INT: | |
b203d0a2 | 3909 | if (dir_in) |
5b7d70c6 | 3910 | hs_ep->periodic = 1; |
5b7d70c6 | 3911 | |
142bd33f VM |
3912 | if (hsotg->gadget.speed == USB_SPEED_HIGH) |
3913 | hs_ep->interval = 1 << (desc->bInterval - 1); | |
3914 | ||
47a1685f | 3915 | epctrl |= DXEPCTL_EPTYPE_INTERRUPT; |
5b7d70c6 BD |
3916 | break; |
3917 | ||
3918 | case USB_ENDPOINT_XFER_CONTROL: | |
47a1685f | 3919 | epctrl |= DXEPCTL_EPTYPE_CONTROL; |
5b7d70c6 BD |
3920 | break; |
3921 | } | |
3922 | ||
8b9bc460 LM |
3923 | /* |
3924 | * if the hardware has dedicated fifos, we must give each IN EP | |
10aebc77 BD |
3925 | * a unique tx-fifo even if it is non-periodic. |
3926 | */ | |
21f3bb52 | 3927 | if (dir_in && hsotg->dedicated_fifos) { |
ca4c55ad MYK |
3928 | u32 fifo_index = 0; |
3929 | u32 fifo_size = UINT_MAX; | |
9da51974 JY |
3930 | |
3931 | size = hs_ep->ep.maxpacket * hs_ep->mc; | |
5f2196bd | 3932 | for (i = 1; i < hsotg->num_of_eps; ++i) { |
9da51974 | 3933 | if (hsotg->fifo_map & (1 << i)) |
b203d0a2 | 3934 | continue; |
95c8bc36 | 3935 | val = dwc2_readl(hsotg->regs + DPTXFSIZN(i)); |
9da51974 | 3936 | val = (val >> FIFOSIZE_DEPTH_SHIFT) * 4; |
b203d0a2 RB |
3937 | if (val < size) |
3938 | continue; | |
ca4c55ad MYK |
3939 | /* Search for smallest acceptable fifo */ |
3940 | if (val < fifo_size) { | |
3941 | fifo_size = val; | |
3942 | fifo_index = i; | |
3943 | } | |
b203d0a2 | 3944 | } |
ca4c55ad | 3945 | if (!fifo_index) { |
5f2196bd MYK |
3946 | dev_err(hsotg->dev, |
3947 | "%s: No suitable fifo found\n", __func__); | |
b585a48b | 3948 | ret = -ENOMEM; |
5f54c54b | 3949 | goto error1; |
b585a48b | 3950 | } |
ca4c55ad MYK |
3951 | hsotg->fifo_map |= 1 << fifo_index; |
3952 | epctrl |= DXEPCTL_TXFNUM(fifo_index); | |
3953 | hs_ep->fifo_index = fifo_index; | |
3954 | hs_ep->fifo_size = fifo_size; | |
b203d0a2 | 3955 | } |
10aebc77 | 3956 | |
5b7d70c6 | 3957 | /* for non control endpoints, set PID to D0 */ |
837e9f00 | 3958 | if (index && !hs_ep->isochronous) |
47a1685f | 3959 | epctrl |= DXEPCTL_SETD0PID; |
5b7d70c6 BD |
3960 | |
3961 | dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n", | |
3962 | __func__, epctrl); | |
3963 | ||
95c8bc36 | 3964 | dwc2_writel(epctrl, hsotg->regs + epctrl_reg); |
5b7d70c6 | 3965 | dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x\n", |
95c8bc36 | 3966 | __func__, dwc2_readl(hsotg->regs + epctrl_reg)); |
5b7d70c6 BD |
3967 | |
3968 | /* enable the endpoint interrupt */ | |
1f91b4cc | 3969 | dwc2_hsotg_ctrl_epint(hsotg, index, dir_in, 1); |
5b7d70c6 | 3970 | |
5f54c54b | 3971 | error1: |
22258f49 | 3972 | spin_unlock_irqrestore(&hsotg->lock, flags); |
5f54c54b VA |
3973 | |
3974 | error2: | |
3975 | if (ret && using_desc_dma(hsotg) && hs_ep->desc_list) { | |
9383e084 | 3976 | dmam_free_coherent(hsotg->dev, MAX_DMA_DESC_NUM_GENERIC * |
5f54c54b VA |
3977 | sizeof(struct dwc2_dma_desc), |
3978 | hs_ep->desc_list, hs_ep->desc_list_dma); | |
3979 | hs_ep->desc_list = NULL; | |
3980 | } | |
3981 | ||
19c190f9 | 3982 | return ret; |
5b7d70c6 BD |
3983 | } |
3984 | ||
8b9bc460 | 3985 | /** |
1f91b4cc | 3986 | * dwc2_hsotg_ep_disable - disable given endpoint |
8b9bc460 LM |
3987 | * @ep: The endpoint to disable. |
3988 | */ | |
1f91b4cc | 3989 | static int dwc2_hsotg_ep_disable(struct usb_ep *ep) |
5b7d70c6 | 3990 | { |
1f91b4cc | 3991 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 3992 | struct dwc2_hsotg *hsotg = hs_ep->parent; |
5b7d70c6 BD |
3993 | int dir_in = hs_ep->dir_in; |
3994 | int index = hs_ep->index; | |
3995 | unsigned long flags; | |
3996 | u32 epctrl_reg; | |
3997 | u32 ctrl; | |
3998 | ||
1e011293 | 3999 | dev_dbg(hsotg->dev, "%s(ep %p)\n", __func__, ep); |
5b7d70c6 | 4000 | |
c6f5c050 | 4001 | if (ep == &hsotg->eps_out[0]->ep) { |
5b7d70c6 BD |
4002 | dev_err(hsotg->dev, "%s: called for ep0\n", __func__); |
4003 | return -EINVAL; | |
9b481092 JS |
4004 | } |
4005 | ||
4006 | if (hsotg->op_state != OTG_STATE_B_PERIPHERAL) { | |
4007 | dev_err(hsotg->dev, "%s: called in host mode?\n", __func__); | |
4008 | return -EINVAL; | |
5b7d70c6 BD |
4009 | } |
4010 | ||
94cb8fd6 | 4011 | epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index); |
5b7d70c6 | 4012 | |
5ad1d316 | 4013 | spin_lock_irqsave(&hsotg->lock, flags); |
5b7d70c6 | 4014 | |
95c8bc36 | 4015 | ctrl = dwc2_readl(hsotg->regs + epctrl_reg); |
a4f82771 VA |
4016 | |
4017 | if (ctrl & DXEPCTL_EPENA) | |
4018 | dwc2_hsotg_ep_stop_xfr(hsotg, hs_ep); | |
4019 | ||
47a1685f DN |
4020 | ctrl &= ~DXEPCTL_EPENA; |
4021 | ctrl &= ~DXEPCTL_USBACTEP; | |
4022 | ctrl |= DXEPCTL_SNAK; | |
5b7d70c6 BD |
4023 | |
4024 | dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl); | |
95c8bc36 | 4025 | dwc2_writel(ctrl, hsotg->regs + epctrl_reg); |
5b7d70c6 BD |
4026 | |
4027 | /* disable endpoint interrupts */ | |
1f91b4cc | 4028 | dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 0); |
5b7d70c6 | 4029 | |
1141ea01 MYK |
4030 | /* terminate all requests with shutdown */ |
4031 | kill_all_requests(hsotg, hs_ep, -ESHUTDOWN); | |
4032 | ||
1c07b20e RB |
4033 | hsotg->fifo_map &= ~(1 << hs_ep->fifo_index); |
4034 | hs_ep->fifo_index = 0; | |
4035 | hs_ep->fifo_size = 0; | |
4036 | ||
22258f49 | 4037 | spin_unlock_irqrestore(&hsotg->lock, flags); |
5b7d70c6 BD |
4038 | return 0; |
4039 | } | |
4040 | ||
4041 | /** | |
4042 | * on_list - check request is on the given endpoint | |
4043 | * @ep: The endpoint to check. | |
4044 | * @test: The request to test if it is on the endpoint. | |
8b9bc460 | 4045 | */ |
1f91b4cc | 4046 | static bool on_list(struct dwc2_hsotg_ep *ep, struct dwc2_hsotg_req *test) |
5b7d70c6 | 4047 | { |
1f91b4cc | 4048 | struct dwc2_hsotg_req *req, *treq; |
5b7d70c6 BD |
4049 | |
4050 | list_for_each_entry_safe(req, treq, &ep->queue, queue) { | |
4051 | if (req == test) | |
4052 | return true; | |
4053 | } | |
4054 | ||
4055 | return false; | |
4056 | } | |
4057 | ||
8b9bc460 | 4058 | /** |
1f91b4cc | 4059 | * dwc2_hsotg_ep_dequeue - dequeue given endpoint |
8b9bc460 LM |
4060 | * @ep: The endpoint to dequeue. |
4061 | * @req: The request to be removed from a queue. | |
4062 | */ | |
1f91b4cc | 4063 | static int dwc2_hsotg_ep_dequeue(struct usb_ep *ep, struct usb_request *req) |
5b7d70c6 | 4064 | { |
1f91b4cc FB |
4065 | struct dwc2_hsotg_req *hs_req = our_req(req); |
4066 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); | |
941fcce4 | 4067 | struct dwc2_hsotg *hs = hs_ep->parent; |
5b7d70c6 BD |
4068 | unsigned long flags; |
4069 | ||
1e011293 | 4070 | dev_dbg(hs->dev, "ep_dequeue(%p,%p)\n", ep, req); |
5b7d70c6 | 4071 | |
22258f49 | 4072 | spin_lock_irqsave(&hs->lock, flags); |
5b7d70c6 BD |
4073 | |
4074 | if (!on_list(hs_ep, hs_req)) { | |
22258f49 | 4075 | spin_unlock_irqrestore(&hs->lock, flags); |
5b7d70c6 BD |
4076 | return -EINVAL; |
4077 | } | |
4078 | ||
c524dd5f MYK |
4079 | /* Dequeue already started request */ |
4080 | if (req == &hs_ep->req->req) | |
4081 | dwc2_hsotg_ep_stop_xfr(hs, hs_ep); | |
4082 | ||
1f91b4cc | 4083 | dwc2_hsotg_complete_request(hs, hs_ep, hs_req, -ECONNRESET); |
22258f49 | 4084 | spin_unlock_irqrestore(&hs->lock, flags); |
5b7d70c6 BD |
4085 | |
4086 | return 0; | |
4087 | } | |
4088 | ||
8b9bc460 | 4089 | /** |
1f91b4cc | 4090 | * dwc2_hsotg_ep_sethalt - set halt on a given endpoint |
8b9bc460 LM |
4091 | * @ep: The endpoint to set halt. |
4092 | * @value: Set or unset the halt. | |
51da43b5 VA |
4093 | * @now: If true, stall the endpoint now. Otherwise return -EAGAIN if |
4094 | * the endpoint is busy processing requests. | |
4095 | * | |
4096 | * We need to stall the endpoint immediately if request comes from set_feature | |
4097 | * protocol command handler. | |
8b9bc460 | 4098 | */ |
51da43b5 | 4099 | static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now) |
5b7d70c6 | 4100 | { |
1f91b4cc | 4101 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 4102 | struct dwc2_hsotg *hs = hs_ep->parent; |
5b7d70c6 | 4103 | int index = hs_ep->index; |
5b7d70c6 BD |
4104 | u32 epreg; |
4105 | u32 epctl; | |
9c39ddc6 | 4106 | u32 xfertype; |
5b7d70c6 BD |
4107 | |
4108 | dev_info(hs->dev, "%s(ep %p %s, %d)\n", __func__, ep, ep->name, value); | |
4109 | ||
c9f721b2 RB |
4110 | if (index == 0) { |
4111 | if (value) | |
1f91b4cc | 4112 | dwc2_hsotg_stall_ep0(hs); |
c9f721b2 RB |
4113 | else |
4114 | dev_warn(hs->dev, | |
4115 | "%s: can't clear halt on ep0\n", __func__); | |
4116 | return 0; | |
4117 | } | |
4118 | ||
15186f10 VA |
4119 | if (hs_ep->isochronous) { |
4120 | dev_err(hs->dev, "%s is Isochronous Endpoint\n", ep->name); | |
4121 | return -EINVAL; | |
4122 | } | |
4123 | ||
51da43b5 VA |
4124 | if (!now && value && !list_empty(&hs_ep->queue)) { |
4125 | dev_dbg(hs->dev, "%s request is pending, cannot halt\n", | |
4126 | ep->name); | |
4127 | return -EAGAIN; | |
4128 | } | |
4129 | ||
c6f5c050 MYK |
4130 | if (hs_ep->dir_in) { |
4131 | epreg = DIEPCTL(index); | |
95c8bc36 | 4132 | epctl = dwc2_readl(hs->regs + epreg); |
c6f5c050 MYK |
4133 | |
4134 | if (value) { | |
5a350d53 | 4135 | epctl |= DXEPCTL_STALL | DXEPCTL_SNAK; |
c6f5c050 MYK |
4136 | if (epctl & DXEPCTL_EPENA) |
4137 | epctl |= DXEPCTL_EPDIS; | |
4138 | } else { | |
4139 | epctl &= ~DXEPCTL_STALL; | |
4140 | xfertype = epctl & DXEPCTL_EPTYPE_MASK; | |
4141 | if (xfertype == DXEPCTL_EPTYPE_BULK || | |
9da51974 | 4142 | xfertype == DXEPCTL_EPTYPE_INTERRUPT) |
77b6200e | 4143 | epctl |= DXEPCTL_SETD0PID; |
c6f5c050 | 4144 | } |
95c8bc36 | 4145 | dwc2_writel(epctl, hs->regs + epreg); |
9c39ddc6 | 4146 | } else { |
c6f5c050 | 4147 | epreg = DOEPCTL(index); |
95c8bc36 | 4148 | epctl = dwc2_readl(hs->regs + epreg); |
5b7d70c6 | 4149 | |
34c0887f | 4150 | if (value) { |
c6f5c050 | 4151 | epctl |= DXEPCTL_STALL; |
34c0887f | 4152 | } else { |
c6f5c050 MYK |
4153 | epctl &= ~DXEPCTL_STALL; |
4154 | xfertype = epctl & DXEPCTL_EPTYPE_MASK; | |
4155 | if (xfertype == DXEPCTL_EPTYPE_BULK || | |
9da51974 | 4156 | xfertype == DXEPCTL_EPTYPE_INTERRUPT) |
77b6200e | 4157 | epctl |= DXEPCTL_SETD0PID; |
c6f5c050 | 4158 | } |
95c8bc36 | 4159 | dwc2_writel(epctl, hs->regs + epreg); |
9c39ddc6 | 4160 | } |
5b7d70c6 | 4161 | |
a18ed7b0 RB |
4162 | hs_ep->halted = value; |
4163 | ||
5b7d70c6 BD |
4164 | return 0; |
4165 | } | |
4166 | ||
5ad1d316 | 4167 | /** |
1f91b4cc | 4168 | * dwc2_hsotg_ep_sethalt_lock - set halt on a given endpoint with lock held |
5ad1d316 LM |
4169 | * @ep: The endpoint to set halt. |
4170 | * @value: Set or unset the halt. | |
4171 | */ | |
1f91b4cc | 4172 | static int dwc2_hsotg_ep_sethalt_lock(struct usb_ep *ep, int value) |
5ad1d316 | 4173 | { |
1f91b4cc | 4174 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 4175 | struct dwc2_hsotg *hs = hs_ep->parent; |
5ad1d316 LM |
4176 | unsigned long flags = 0; |
4177 | int ret = 0; | |
4178 | ||
4179 | spin_lock_irqsave(&hs->lock, flags); | |
51da43b5 | 4180 | ret = dwc2_hsotg_ep_sethalt(ep, value, false); |
5ad1d316 LM |
4181 | spin_unlock_irqrestore(&hs->lock, flags); |
4182 | ||
4183 | return ret; | |
4184 | } | |
4185 | ||
ebce561a | 4186 | static const struct usb_ep_ops dwc2_hsotg_ep_ops = { |
1f91b4cc FB |
4187 | .enable = dwc2_hsotg_ep_enable, |
4188 | .disable = dwc2_hsotg_ep_disable, | |
4189 | .alloc_request = dwc2_hsotg_ep_alloc_request, | |
4190 | .free_request = dwc2_hsotg_ep_free_request, | |
4191 | .queue = dwc2_hsotg_ep_queue_lock, | |
4192 | .dequeue = dwc2_hsotg_ep_dequeue, | |
4193 | .set_halt = dwc2_hsotg_ep_sethalt_lock, | |
25985edc | 4194 | /* note, don't believe we have any call for the fifo routines */ |
5b7d70c6 BD |
4195 | }; |
4196 | ||
8b9bc460 | 4197 | /** |
9da51974 | 4198 | * dwc2_hsotg_init - initialize the usb core |
8b9bc460 LM |
4199 | * @hsotg: The driver state |
4200 | */ | |
1f91b4cc | 4201 | static void dwc2_hsotg_init(struct dwc2_hsotg *hsotg) |
b3f489b2 | 4202 | { |
fa4a8d72 | 4203 | u32 trdtim; |
ecd9a7ad | 4204 | u32 usbcfg; |
b3f489b2 LM |
4205 | /* unmask subset of endpoint interrupts */ |
4206 | ||
95c8bc36 AS |
4207 | dwc2_writel(DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK | |
4208 | DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK, | |
4209 | hsotg->regs + DIEPMSK); | |
b3f489b2 | 4210 | |
95c8bc36 AS |
4211 | dwc2_writel(DOEPMSK_SETUPMSK | DOEPMSK_AHBERRMSK | |
4212 | DOEPMSK_EPDISBLDMSK | DOEPMSK_XFERCOMPLMSK, | |
4213 | hsotg->regs + DOEPMSK); | |
b3f489b2 | 4214 | |
95c8bc36 | 4215 | dwc2_writel(0, hsotg->regs + DAINTMSK); |
b3f489b2 LM |
4216 | |
4217 | /* Be in disconnected state until gadget is registered */ | |
47a1685f | 4218 | __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON); |
b3f489b2 | 4219 | |
b3f489b2 LM |
4220 | /* setup fifos */ |
4221 | ||
4222 | dev_dbg(hsotg->dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n", | |
95c8bc36 AS |
4223 | dwc2_readl(hsotg->regs + GRXFSIZ), |
4224 | dwc2_readl(hsotg->regs + GNPTXFSIZ)); | |
b3f489b2 | 4225 | |
1f91b4cc | 4226 | dwc2_hsotg_init_fifo(hsotg); |
b3f489b2 | 4227 | |
ecd9a7ad PR |
4228 | /* keep other bits untouched (so e.g. forced modes are not lost) */ |
4229 | usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); | |
4230 | usbcfg &= ~(GUSBCFG_TOUTCAL_MASK | GUSBCFG_PHYIF16 | GUSBCFG_SRPCAP | | |
ca02954a | 4231 | GUSBCFG_HNPCAP | GUSBCFG_USBTRDTIM_MASK); |
ecd9a7ad | 4232 | |
b3f489b2 | 4233 | /* set the PLL on, remove the HNP/SRP and set the PHY */ |
fa4a8d72 | 4234 | trdtim = (hsotg->phyif == GUSBCFG_PHYIF8) ? 9 : 5; |
ecd9a7ad PR |
4235 | usbcfg |= hsotg->phyif | GUSBCFG_TOUTCAL(7) | |
4236 | (trdtim << GUSBCFG_USBTRDTIM_SHIFT); | |
4237 | dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); | |
b3f489b2 | 4238 | |
f5090044 GH |
4239 | if (using_dma(hsotg)) |
4240 | __orr32(hsotg->regs + GAHBCFG, GAHBCFG_DMA_EN); | |
b3f489b2 LM |
4241 | } |
4242 | ||
8b9bc460 | 4243 | /** |
1f91b4cc | 4244 | * dwc2_hsotg_udc_start - prepare the udc for work |
8b9bc460 LM |
4245 | * @gadget: The usb gadget state |
4246 | * @driver: The usb gadget driver | |
4247 | * | |
4248 | * Perform initialization to prepare udc device and driver | |
4249 | * to work. | |
4250 | */ | |
1f91b4cc | 4251 | static int dwc2_hsotg_udc_start(struct usb_gadget *gadget, |
9da51974 | 4252 | struct usb_gadget_driver *driver) |
5b7d70c6 | 4253 | { |
941fcce4 | 4254 | struct dwc2_hsotg *hsotg = to_hsotg(gadget); |
5b9451f8 | 4255 | unsigned long flags; |
5b7d70c6 BD |
4256 | int ret; |
4257 | ||
4258 | if (!hsotg) { | |
a023da33 | 4259 | pr_err("%s: called with no device\n", __func__); |
5b7d70c6 BD |
4260 | return -ENODEV; |
4261 | } | |
4262 | ||
4263 | if (!driver) { | |
4264 | dev_err(hsotg->dev, "%s: no driver\n", __func__); | |
4265 | return -EINVAL; | |
4266 | } | |
4267 | ||
7177aed4 | 4268 | if (driver->max_speed < USB_SPEED_FULL) |
5b7d70c6 | 4269 | dev_err(hsotg->dev, "%s: bad speed\n", __func__); |
5b7d70c6 | 4270 | |
f65f0f10 | 4271 | if (!driver->setup) { |
5b7d70c6 BD |
4272 | dev_err(hsotg->dev, "%s: missing entry points\n", __func__); |
4273 | return -EINVAL; | |
4274 | } | |
4275 | ||
4276 | WARN_ON(hsotg->driver); | |
4277 | ||
4278 | driver->driver.bus = NULL; | |
4279 | hsotg->driver = driver; | |
7d7b2292 | 4280 | hsotg->gadget.dev.of_node = hsotg->dev->of_node; |
5b7d70c6 BD |
4281 | hsotg->gadget.speed = USB_SPEED_UNKNOWN; |
4282 | ||
09a75e85 MS |
4283 | if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) { |
4284 | ret = dwc2_lowlevel_hw_enable(hsotg); | |
4285 | if (ret) | |
4286 | goto err; | |
5b7d70c6 BD |
4287 | } |
4288 | ||
f6c01592 GH |
4289 | if (!IS_ERR_OR_NULL(hsotg->uphy)) |
4290 | otg_set_peripheral(hsotg->uphy->otg, &hsotg->gadget); | |
c816c47f | 4291 | |
5b9451f8 | 4292 | spin_lock_irqsave(&hsotg->lock, flags); |
d0f0ac56 JY |
4293 | if (dwc2_hw_is_device(hsotg)) { |
4294 | dwc2_hsotg_init(hsotg); | |
4295 | dwc2_hsotg_core_init_disconnected(hsotg, false); | |
4296 | } | |
4297 | ||
dc6e69e6 | 4298 | hsotg->enabled = 0; |
5b9451f8 MS |
4299 | spin_unlock_irqrestore(&hsotg->lock, flags); |
4300 | ||
5b7d70c6 | 4301 | dev_info(hsotg->dev, "bound driver %s\n", driver->driver.name); |
5b9451f8 | 4302 | |
5b7d70c6 BD |
4303 | return 0; |
4304 | ||
4305 | err: | |
4306 | hsotg->driver = NULL; | |
5b7d70c6 BD |
4307 | return ret; |
4308 | } | |
4309 | ||
8b9bc460 | 4310 | /** |
1f91b4cc | 4311 | * dwc2_hsotg_udc_stop - stop the udc |
8b9bc460 LM |
4312 | * @gadget: The usb gadget state |
4313 | * @driver: The usb gadget driver | |
4314 | * | |
4315 | * Stop udc hw block and stay tunned for future transmissions | |
4316 | */ | |
1f91b4cc | 4317 | static int dwc2_hsotg_udc_stop(struct usb_gadget *gadget) |
5b7d70c6 | 4318 | { |
941fcce4 | 4319 | struct dwc2_hsotg *hsotg = to_hsotg(gadget); |
2b19a52c | 4320 | unsigned long flags = 0; |
5b7d70c6 BD |
4321 | int ep; |
4322 | ||
4323 | if (!hsotg) | |
4324 | return -ENODEV; | |
4325 | ||
5b7d70c6 | 4326 | /* all endpoints should be shutdown */ |
c6f5c050 MYK |
4327 | for (ep = 1; ep < hsotg->num_of_eps; ep++) { |
4328 | if (hsotg->eps_in[ep]) | |
1f91b4cc | 4329 | dwc2_hsotg_ep_disable(&hsotg->eps_in[ep]->ep); |
c6f5c050 | 4330 | if (hsotg->eps_out[ep]) |
1f91b4cc | 4331 | dwc2_hsotg_ep_disable(&hsotg->eps_out[ep]->ep); |
c6f5c050 | 4332 | } |
5b7d70c6 | 4333 | |
2b19a52c LM |
4334 | spin_lock_irqsave(&hsotg->lock, flags); |
4335 | ||
32805c35 | 4336 | hsotg->driver = NULL; |
5b7d70c6 | 4337 | hsotg->gadget.speed = USB_SPEED_UNKNOWN; |
dc6e69e6 | 4338 | hsotg->enabled = 0; |
5b7d70c6 | 4339 | |
2b19a52c LM |
4340 | spin_unlock_irqrestore(&hsotg->lock, flags); |
4341 | ||
f6c01592 GH |
4342 | if (!IS_ERR_OR_NULL(hsotg->uphy)) |
4343 | otg_set_peripheral(hsotg->uphy->otg, NULL); | |
c816c47f | 4344 | |
09a75e85 MS |
4345 | if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) |
4346 | dwc2_lowlevel_hw_disable(hsotg); | |
5b7d70c6 BD |
4347 | |
4348 | return 0; | |
4349 | } | |
5b7d70c6 | 4350 | |
8b9bc460 | 4351 | /** |
1f91b4cc | 4352 | * dwc2_hsotg_gadget_getframe - read the frame number |
8b9bc460 LM |
4353 | * @gadget: The usb gadget state |
4354 | * | |
4355 | * Read the {micro} frame number | |
4356 | */ | |
1f91b4cc | 4357 | static int dwc2_hsotg_gadget_getframe(struct usb_gadget *gadget) |
5b7d70c6 | 4358 | { |
1f91b4cc | 4359 | return dwc2_hsotg_read_frameno(to_hsotg(gadget)); |
5b7d70c6 BD |
4360 | } |
4361 | ||
a188b689 | 4362 | /** |
1f91b4cc | 4363 | * dwc2_hsotg_pullup - connect/disconnect the USB PHY |
a188b689 LM |
4364 | * @gadget: The usb gadget state |
4365 | * @is_on: Current state of the USB PHY | |
4366 | * | |
4367 | * Connect/Disconnect the USB PHY pullup | |
4368 | */ | |
1f91b4cc | 4369 | static int dwc2_hsotg_pullup(struct usb_gadget *gadget, int is_on) |
a188b689 | 4370 | { |
941fcce4 | 4371 | struct dwc2_hsotg *hsotg = to_hsotg(gadget); |
a188b689 LM |
4372 | unsigned long flags = 0; |
4373 | ||
77ba9119 | 4374 | dev_dbg(hsotg->dev, "%s: is_on: %d op_state: %d\n", __func__, is_on, |
9da51974 | 4375 | hsotg->op_state); |
77ba9119 GH |
4376 | |
4377 | /* Don't modify pullup state while in host mode */ | |
4378 | if (hsotg->op_state != OTG_STATE_B_PERIPHERAL) { | |
4379 | hsotg->enabled = is_on; | |
4380 | return 0; | |
4381 | } | |
a188b689 LM |
4382 | |
4383 | spin_lock_irqsave(&hsotg->lock, flags); | |
4384 | if (is_on) { | |
dc6e69e6 | 4385 | hsotg->enabled = 1; |
1f91b4cc FB |
4386 | dwc2_hsotg_core_init_disconnected(hsotg, false); |
4387 | dwc2_hsotg_core_connect(hsotg); | |
a188b689 | 4388 | } else { |
1f91b4cc FB |
4389 | dwc2_hsotg_core_disconnect(hsotg); |
4390 | dwc2_hsotg_disconnect(hsotg); | |
dc6e69e6 | 4391 | hsotg->enabled = 0; |
a188b689 LM |
4392 | } |
4393 | ||
4394 | hsotg->gadget.speed = USB_SPEED_UNKNOWN; | |
4395 | spin_unlock_irqrestore(&hsotg->lock, flags); | |
4396 | ||
4397 | return 0; | |
4398 | } | |
4399 | ||
1f91b4cc | 4400 | static int dwc2_hsotg_vbus_session(struct usb_gadget *gadget, int is_active) |
83d98223 GH |
4401 | { |
4402 | struct dwc2_hsotg *hsotg = to_hsotg(gadget); | |
4403 | unsigned long flags; | |
4404 | ||
4405 | dev_dbg(hsotg->dev, "%s: is_active: %d\n", __func__, is_active); | |
4406 | spin_lock_irqsave(&hsotg->lock, flags); | |
4407 | ||
61f7223b GH |
4408 | /* |
4409 | * If controller is hibernated, it must exit from hibernation | |
4410 | * before being initialized / de-initialized | |
4411 | */ | |
4412 | if (hsotg->lx_state == DWC2_L2) | |
4413 | dwc2_exit_hibernation(hsotg, false); | |
4414 | ||
83d98223 | 4415 | if (is_active) { |
cd0e641c | 4416 | hsotg->op_state = OTG_STATE_B_PERIPHERAL; |
065d3931 | 4417 | |
1f91b4cc | 4418 | dwc2_hsotg_core_init_disconnected(hsotg, false); |
83d98223 | 4419 | if (hsotg->enabled) |
1f91b4cc | 4420 | dwc2_hsotg_core_connect(hsotg); |
83d98223 | 4421 | } else { |
1f91b4cc FB |
4422 | dwc2_hsotg_core_disconnect(hsotg); |
4423 | dwc2_hsotg_disconnect(hsotg); | |
83d98223 GH |
4424 | } |
4425 | ||
4426 | spin_unlock_irqrestore(&hsotg->lock, flags); | |
4427 | return 0; | |
4428 | } | |
4429 | ||
596d696a | 4430 | /** |
1f91b4cc | 4431 | * dwc2_hsotg_vbus_draw - report bMaxPower field |
596d696a GH |
4432 | * @gadget: The usb gadget state |
4433 | * @mA: Amount of current | |
4434 | * | |
4435 | * Report how much power the device may consume to the phy. | |
4436 | */ | |
9da51974 | 4437 | static int dwc2_hsotg_vbus_draw(struct usb_gadget *gadget, unsigned int mA) |
596d696a GH |
4438 | { |
4439 | struct dwc2_hsotg *hsotg = to_hsotg(gadget); | |
4440 | ||
4441 | if (IS_ERR_OR_NULL(hsotg->uphy)) | |
4442 | return -ENOTSUPP; | |
4443 | return usb_phy_set_power(hsotg->uphy, mA); | |
4444 | } | |
4445 | ||
1f91b4cc FB |
4446 | static const struct usb_gadget_ops dwc2_hsotg_gadget_ops = { |
4447 | .get_frame = dwc2_hsotg_gadget_getframe, | |
4448 | .udc_start = dwc2_hsotg_udc_start, | |
4449 | .udc_stop = dwc2_hsotg_udc_stop, | |
4450 | .pullup = dwc2_hsotg_pullup, | |
4451 | .vbus_session = dwc2_hsotg_vbus_session, | |
4452 | .vbus_draw = dwc2_hsotg_vbus_draw, | |
5b7d70c6 BD |
4453 | }; |
4454 | ||
4455 | /** | |
1f91b4cc | 4456 | * dwc2_hsotg_initep - initialise a single endpoint |
5b7d70c6 BD |
4457 | * @hsotg: The device state. |
4458 | * @hs_ep: The endpoint to be initialised. | |
4459 | * @epnum: The endpoint number | |
4460 | * | |
4461 | * Initialise the given endpoint (as part of the probe and device state | |
4462 | * creation) to give to the gadget driver. Setup the endpoint name, any | |
4463 | * direction information and other state that may be required. | |
4464 | */ | |
1f91b4cc | 4465 | static void dwc2_hsotg_initep(struct dwc2_hsotg *hsotg, |
9da51974 | 4466 | struct dwc2_hsotg_ep *hs_ep, |
c6f5c050 MYK |
4467 | int epnum, |
4468 | bool dir_in) | |
5b7d70c6 | 4469 | { |
5b7d70c6 BD |
4470 | char *dir; |
4471 | ||
4472 | if (epnum == 0) | |
4473 | dir = ""; | |
c6f5c050 | 4474 | else if (dir_in) |
5b7d70c6 | 4475 | dir = "in"; |
c6f5c050 MYK |
4476 | else |
4477 | dir = "out"; | |
5b7d70c6 | 4478 | |
c6f5c050 | 4479 | hs_ep->dir_in = dir_in; |
5b7d70c6 BD |
4480 | hs_ep->index = epnum; |
4481 | ||
4482 | snprintf(hs_ep->name, sizeof(hs_ep->name), "ep%d%s", epnum, dir); | |
4483 | ||
4484 | INIT_LIST_HEAD(&hs_ep->queue); | |
4485 | INIT_LIST_HEAD(&hs_ep->ep.ep_list); | |
4486 | ||
5b7d70c6 BD |
4487 | /* add to the list of endpoints known by the gadget driver */ |
4488 | if (epnum) | |
4489 | list_add_tail(&hs_ep->ep.ep_list, &hsotg->gadget.ep_list); | |
4490 | ||
4491 | hs_ep->parent = hsotg; | |
4492 | hs_ep->ep.name = hs_ep->name; | |
38e9002b VM |
4493 | |
4494 | if (hsotg->params.speed == DWC2_SPEED_PARAM_LOW) | |
4495 | usb_ep_set_maxpacket_limit(&hs_ep->ep, 8); | |
4496 | else | |
4497 | usb_ep_set_maxpacket_limit(&hs_ep->ep, | |
4498 | epnum ? 1024 : EP0_MPS_LIMIT); | |
1f91b4cc | 4499 | hs_ep->ep.ops = &dwc2_hsotg_ep_ops; |
5b7d70c6 | 4500 | |
2954522f RB |
4501 | if (epnum == 0) { |
4502 | hs_ep->ep.caps.type_control = true; | |
4503 | } else { | |
38e9002b VM |
4504 | if (hsotg->params.speed != DWC2_SPEED_PARAM_LOW) { |
4505 | hs_ep->ep.caps.type_iso = true; | |
4506 | hs_ep->ep.caps.type_bulk = true; | |
4507 | } | |
2954522f RB |
4508 | hs_ep->ep.caps.type_int = true; |
4509 | } | |
4510 | ||
4511 | if (dir_in) | |
4512 | hs_ep->ep.caps.dir_in = true; | |
4513 | else | |
4514 | hs_ep->ep.caps.dir_out = true; | |
4515 | ||
8b9bc460 LM |
4516 | /* |
4517 | * if we're using dma, we need to set the next-endpoint pointer | |
5b7d70c6 BD |
4518 | * to be something valid. |
4519 | */ | |
4520 | ||
4521 | if (using_dma(hsotg)) { | |
47a1685f | 4522 | u32 next = DXEPCTL_NEXTEP((epnum + 1) % 15); |
9da51974 | 4523 | |
c6f5c050 | 4524 | if (dir_in) |
95c8bc36 | 4525 | dwc2_writel(next, hsotg->regs + DIEPCTL(epnum)); |
c6f5c050 | 4526 | else |
95c8bc36 | 4527 | dwc2_writel(next, hsotg->regs + DOEPCTL(epnum)); |
5b7d70c6 BD |
4528 | } |
4529 | } | |
4530 | ||
b3f489b2 | 4531 | /** |
1f91b4cc | 4532 | * dwc2_hsotg_hw_cfg - read HW configuration registers |
b3f489b2 LM |
4533 | * @param: The device state |
4534 | * | |
4535 | * Read the USB core HW configuration registers | |
4536 | */ | |
1f91b4cc | 4537 | static int dwc2_hsotg_hw_cfg(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 4538 | { |
c6f5c050 MYK |
4539 | u32 cfg; |
4540 | u32 ep_type; | |
4541 | u32 i; | |
4542 | ||
b3f489b2 | 4543 | /* check hardware configuration */ |
5b7d70c6 | 4544 | |
43e90349 JY |
4545 | hsotg->num_of_eps = hsotg->hw_params.num_dev_ep; |
4546 | ||
c6f5c050 MYK |
4547 | /* Add ep0 */ |
4548 | hsotg->num_of_eps++; | |
10aebc77 | 4549 | |
b98866c2 JY |
4550 | hsotg->eps_in[0] = devm_kzalloc(hsotg->dev, |
4551 | sizeof(struct dwc2_hsotg_ep), | |
4552 | GFP_KERNEL); | |
c6f5c050 MYK |
4553 | if (!hsotg->eps_in[0]) |
4554 | return -ENOMEM; | |
1f91b4cc | 4555 | /* Same dwc2_hsotg_ep is used in both directions for ep0 */ |
c6f5c050 MYK |
4556 | hsotg->eps_out[0] = hsotg->eps_in[0]; |
4557 | ||
43e90349 | 4558 | cfg = hsotg->hw_params.dev_ep_dirs; |
251a17f5 | 4559 | for (i = 1, cfg >>= 2; i < hsotg->num_of_eps; i++, cfg >>= 2) { |
c6f5c050 MYK |
4560 | ep_type = cfg & 3; |
4561 | /* Direction in or both */ | |
4562 | if (!(ep_type & 2)) { | |
4563 | hsotg->eps_in[i] = devm_kzalloc(hsotg->dev, | |
1f91b4cc | 4564 | sizeof(struct dwc2_hsotg_ep), GFP_KERNEL); |
c6f5c050 MYK |
4565 | if (!hsotg->eps_in[i]) |
4566 | return -ENOMEM; | |
4567 | } | |
4568 | /* Direction out or both */ | |
4569 | if (!(ep_type & 1)) { | |
4570 | hsotg->eps_out[i] = devm_kzalloc(hsotg->dev, | |
1f91b4cc | 4571 | sizeof(struct dwc2_hsotg_ep), GFP_KERNEL); |
c6f5c050 MYK |
4572 | if (!hsotg->eps_out[i]) |
4573 | return -ENOMEM; | |
4574 | } | |
4575 | } | |
4576 | ||
43e90349 JY |
4577 | hsotg->fifo_mem = hsotg->hw_params.total_fifo_size; |
4578 | hsotg->dedicated_fifos = hsotg->hw_params.en_multiple_tx_fifo; | |
10aebc77 | 4579 | |
cff9eb75 MS |
4580 | dev_info(hsotg->dev, "EPs: %d, %s fifos, %d entries in SPRAM\n", |
4581 | hsotg->num_of_eps, | |
4582 | hsotg->dedicated_fifos ? "dedicated" : "shared", | |
4583 | hsotg->fifo_mem); | |
c6f5c050 | 4584 | return 0; |
5b7d70c6 BD |
4585 | } |
4586 | ||
8b9bc460 | 4587 | /** |
1f91b4cc | 4588 | * dwc2_hsotg_dump - dump state of the udc |
8b9bc460 LM |
4589 | * @param: The device state |
4590 | */ | |
1f91b4cc | 4591 | static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 4592 | { |
83a01804 | 4593 | #ifdef DEBUG |
5b7d70c6 BD |
4594 | struct device *dev = hsotg->dev; |
4595 | void __iomem *regs = hsotg->regs; | |
4596 | u32 val; | |
4597 | int idx; | |
4598 | ||
4599 | dev_info(dev, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n", | |
95c8bc36 AS |
4600 | dwc2_readl(regs + DCFG), dwc2_readl(regs + DCTL), |
4601 | dwc2_readl(regs + DIEPMSK)); | |
5b7d70c6 | 4602 | |
f889f23d | 4603 | dev_info(dev, "GAHBCFG=0x%08x, GHWCFG1=0x%08x\n", |
95c8bc36 | 4604 | dwc2_readl(regs + GAHBCFG), dwc2_readl(regs + GHWCFG1)); |
5b7d70c6 BD |
4605 | |
4606 | dev_info(dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n", | |
95c8bc36 | 4607 | dwc2_readl(regs + GRXFSIZ), dwc2_readl(regs + GNPTXFSIZ)); |
5b7d70c6 BD |
4608 | |
4609 | /* show periodic fifo settings */ | |
4610 | ||
364f8e93 | 4611 | for (idx = 1; idx < hsotg->num_of_eps; idx++) { |
95c8bc36 | 4612 | val = dwc2_readl(regs + DPTXFSIZN(idx)); |
5b7d70c6 | 4613 | dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx, |
47a1685f DN |
4614 | val >> FIFOSIZE_DEPTH_SHIFT, |
4615 | val & FIFOSIZE_STARTADDR_MASK); | |
5b7d70c6 BD |
4616 | } |
4617 | ||
364f8e93 | 4618 | for (idx = 0; idx < hsotg->num_of_eps; idx++) { |
5b7d70c6 BD |
4619 | dev_info(dev, |
4620 | "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx, | |
95c8bc36 AS |
4621 | dwc2_readl(regs + DIEPCTL(idx)), |
4622 | dwc2_readl(regs + DIEPTSIZ(idx)), | |
4623 | dwc2_readl(regs + DIEPDMA(idx))); | |
5b7d70c6 | 4624 | |
95c8bc36 | 4625 | val = dwc2_readl(regs + DOEPCTL(idx)); |
5b7d70c6 BD |
4626 | dev_info(dev, |
4627 | "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", | |
95c8bc36 AS |
4628 | idx, dwc2_readl(regs + DOEPCTL(idx)), |
4629 | dwc2_readl(regs + DOEPTSIZ(idx)), | |
4630 | dwc2_readl(regs + DOEPDMA(idx))); | |
5b7d70c6 BD |
4631 | } |
4632 | ||
4633 | dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n", | |
95c8bc36 | 4634 | dwc2_readl(regs + DVBUSDIS), dwc2_readl(regs + DVBUSPULSE)); |
83a01804 | 4635 | #endif |
5b7d70c6 BD |
4636 | } |
4637 | ||
8b9bc460 | 4638 | /** |
117777b2 DN |
4639 | * dwc2_gadget_init - init function for gadget |
4640 | * @dwc2: The data structure for the DWC2 driver. | |
4641 | * @irq: The IRQ number for the controller. | |
8b9bc460 | 4642 | */ |
117777b2 | 4643 | int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq) |
5b7d70c6 | 4644 | { |
117777b2 | 4645 | struct device *dev = hsotg->dev; |
5b7d70c6 BD |
4646 | int epnum; |
4647 | int ret; | |
43e90349 | 4648 | |
0a176279 GH |
4649 | /* Dump fifo information */ |
4650 | dev_dbg(dev, "NonPeriodic TXFIFO size: %d\n", | |
05ee799f JY |
4651 | hsotg->params.g_np_tx_fifo_size); |
4652 | dev_dbg(dev, "RXFIFO size: %d\n", hsotg->params.g_rx_fifo_size); | |
5b7d70c6 | 4653 | |
d327ab5b | 4654 | hsotg->gadget.max_speed = USB_SPEED_HIGH; |
1f91b4cc | 4655 | hsotg->gadget.ops = &dwc2_hsotg_gadget_ops; |
5b7d70c6 | 4656 | hsotg->gadget.name = dev_name(dev); |
097ee662 GH |
4657 | if (hsotg->dr_mode == USB_DR_MODE_OTG) |
4658 | hsotg->gadget.is_otg = 1; | |
ec4cc657 MYK |
4659 | else if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) |
4660 | hsotg->op_state = OTG_STATE_B_PERIPHERAL; | |
5b7d70c6 | 4661 | |
1f91b4cc | 4662 | ret = dwc2_hsotg_hw_cfg(hsotg); |
c6f5c050 MYK |
4663 | if (ret) { |
4664 | dev_err(hsotg->dev, "Hardware configuration failed: %d\n", ret); | |
09a75e85 | 4665 | return ret; |
c6f5c050 MYK |
4666 | } |
4667 | ||
3f95001d MYK |
4668 | hsotg->ctrl_buff = devm_kzalloc(hsotg->dev, |
4669 | DWC2_CTRL_BUFF_SIZE, GFP_KERNEL); | |
8bae0f8c | 4670 | if (!hsotg->ctrl_buff) |
09a75e85 | 4671 | return -ENOMEM; |
3f95001d MYK |
4672 | |
4673 | hsotg->ep0_buff = devm_kzalloc(hsotg->dev, | |
4674 | DWC2_CTRL_BUFF_SIZE, GFP_KERNEL); | |
8bae0f8c | 4675 | if (!hsotg->ep0_buff) |
09a75e85 | 4676 | return -ENOMEM; |
3f95001d | 4677 | |
0f6b80c0 VA |
4678 | if (using_desc_dma(hsotg)) { |
4679 | ret = dwc2_gadget_alloc_ctrl_desc_chains(hsotg); | |
4680 | if (ret < 0) | |
4681 | return ret; | |
4682 | } | |
4683 | ||
1f91b4cc | 4684 | ret = devm_request_irq(hsotg->dev, irq, dwc2_hsotg_irq, IRQF_SHARED, |
9da51974 | 4685 | dev_name(hsotg->dev), hsotg); |
eb3c56c5 | 4686 | if (ret < 0) { |
db8178c3 | 4687 | dev_err(dev, "cannot claim IRQ for gadget\n"); |
09a75e85 | 4688 | return ret; |
eb3c56c5 MS |
4689 | } |
4690 | ||
b3f489b2 LM |
4691 | /* hsotg->num_of_eps holds number of EPs other than ep0 */ |
4692 | ||
4693 | if (hsotg->num_of_eps == 0) { | |
4694 | dev_err(dev, "wrong number of EPs (zero)\n"); | |
09a75e85 | 4695 | return -EINVAL; |
b3f489b2 LM |
4696 | } |
4697 | ||
b3f489b2 LM |
4698 | /* setup endpoint information */ |
4699 | ||
4700 | INIT_LIST_HEAD(&hsotg->gadget.ep_list); | |
c6f5c050 | 4701 | hsotg->gadget.ep0 = &hsotg->eps_out[0]->ep; |
b3f489b2 LM |
4702 | |
4703 | /* allocate EP0 request */ | |
4704 | ||
1f91b4cc | 4705 | hsotg->ctrl_req = dwc2_hsotg_ep_alloc_request(&hsotg->eps_out[0]->ep, |
b3f489b2 LM |
4706 | GFP_KERNEL); |
4707 | if (!hsotg->ctrl_req) { | |
4708 | dev_err(dev, "failed to allocate ctrl req\n"); | |
09a75e85 | 4709 | return -ENOMEM; |
b3f489b2 | 4710 | } |
5b7d70c6 BD |
4711 | |
4712 | /* initialise the endpoints now the core has been initialised */ | |
c6f5c050 MYK |
4713 | for (epnum = 0; epnum < hsotg->num_of_eps; epnum++) { |
4714 | if (hsotg->eps_in[epnum]) | |
1f91b4cc | 4715 | dwc2_hsotg_initep(hsotg, hsotg->eps_in[epnum], |
9da51974 | 4716 | epnum, 1); |
c6f5c050 | 4717 | if (hsotg->eps_out[epnum]) |
1f91b4cc | 4718 | dwc2_hsotg_initep(hsotg, hsotg->eps_out[epnum], |
9da51974 | 4719 | epnum, 0); |
c6f5c050 | 4720 | } |
5b7d70c6 | 4721 | |
117777b2 | 4722 | ret = usb_add_gadget_udc(dev, &hsotg->gadget); |
0f91349b | 4723 | if (ret) |
09a75e85 | 4724 | return ret; |
0f91349b | 4725 | |
1f91b4cc | 4726 | dwc2_hsotg_dump(hsotg); |
5b7d70c6 | 4727 | |
5b7d70c6 | 4728 | return 0; |
5b7d70c6 BD |
4729 | } |
4730 | ||
8b9bc460 | 4731 | /** |
1f91b4cc | 4732 | * dwc2_hsotg_remove - remove function for hsotg driver |
8b9bc460 LM |
4733 | * @pdev: The platform information for the driver |
4734 | */ | |
1f91b4cc | 4735 | int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 4736 | { |
0f91349b | 4737 | usb_del_gadget_udc(&hsotg->gadget); |
31ee04de | 4738 | |
5b7d70c6 BD |
4739 | return 0; |
4740 | } | |
4741 | ||
1f91b4cc | 4742 | int dwc2_hsotg_suspend(struct dwc2_hsotg *hsotg) |
b83e333a | 4743 | { |
b83e333a | 4744 | unsigned long flags; |
b83e333a | 4745 | |
9e779778 | 4746 | if (hsotg->lx_state != DWC2_L0) |
09a75e85 | 4747 | return 0; |
9e779778 | 4748 | |
dc6e69e6 MS |
4749 | if (hsotg->driver) { |
4750 | int ep; | |
4751 | ||
b83e333a MS |
4752 | dev_info(hsotg->dev, "suspending usb gadget %s\n", |
4753 | hsotg->driver->driver.name); | |
4754 | ||
dc6e69e6 MS |
4755 | spin_lock_irqsave(&hsotg->lock, flags); |
4756 | if (hsotg->enabled) | |
1f91b4cc FB |
4757 | dwc2_hsotg_core_disconnect(hsotg); |
4758 | dwc2_hsotg_disconnect(hsotg); | |
dc6e69e6 MS |
4759 | hsotg->gadget.speed = USB_SPEED_UNKNOWN; |
4760 | spin_unlock_irqrestore(&hsotg->lock, flags); | |
b83e333a | 4761 | |
c6f5c050 MYK |
4762 | for (ep = 0; ep < hsotg->num_of_eps; ep++) { |
4763 | if (hsotg->eps_in[ep]) | |
1f91b4cc | 4764 | dwc2_hsotg_ep_disable(&hsotg->eps_in[ep]->ep); |
c6f5c050 | 4765 | if (hsotg->eps_out[ep]) |
1f91b4cc | 4766 | dwc2_hsotg_ep_disable(&hsotg->eps_out[ep]->ep); |
c6f5c050 | 4767 | } |
b83e333a MS |
4768 | } |
4769 | ||
09a75e85 | 4770 | return 0; |
b83e333a MS |
4771 | } |
4772 | ||
1f91b4cc | 4773 | int dwc2_hsotg_resume(struct dwc2_hsotg *hsotg) |
b83e333a | 4774 | { |
b83e333a | 4775 | unsigned long flags; |
b83e333a | 4776 | |
9e779778 | 4777 | if (hsotg->lx_state == DWC2_L2) |
09a75e85 | 4778 | return 0; |
9e779778 | 4779 | |
b83e333a MS |
4780 | if (hsotg->driver) { |
4781 | dev_info(hsotg->dev, "resuming usb gadget %s\n", | |
4782 | hsotg->driver->driver.name); | |
d00b4142 | 4783 | |
dc6e69e6 | 4784 | spin_lock_irqsave(&hsotg->lock, flags); |
1f91b4cc | 4785 | dwc2_hsotg_core_init_disconnected(hsotg, false); |
dc6e69e6 | 4786 | if (hsotg->enabled) |
1f91b4cc | 4787 | dwc2_hsotg_core_connect(hsotg); |
dc6e69e6 MS |
4788 | spin_unlock_irqrestore(&hsotg->lock, flags); |
4789 | } | |
b83e333a | 4790 | |
09a75e85 | 4791 | return 0; |
b83e333a | 4792 | } |
58e52ff6 JY |
4793 | |
4794 | /** | |
4795 | * dwc2_backup_device_registers() - Backup controller device registers. | |
4796 | * When suspending usb bus, registers needs to be backuped | |
4797 | * if controller power is disabled once suspended. | |
4798 | * | |
4799 | * @hsotg: Programming view of the DWC_otg controller | |
4800 | */ | |
4801 | int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg) | |
4802 | { | |
4803 | struct dwc2_dregs_backup *dr; | |
4804 | int i; | |
4805 | ||
4806 | dev_dbg(hsotg->dev, "%s\n", __func__); | |
4807 | ||
4808 | /* Backup dev regs */ | |
4809 | dr = &hsotg->dr_backup; | |
4810 | ||
4811 | dr->dcfg = dwc2_readl(hsotg->regs + DCFG); | |
4812 | dr->dctl = dwc2_readl(hsotg->regs + DCTL); | |
4813 | dr->daintmsk = dwc2_readl(hsotg->regs + DAINTMSK); | |
4814 | dr->diepmsk = dwc2_readl(hsotg->regs + DIEPMSK); | |
4815 | dr->doepmsk = dwc2_readl(hsotg->regs + DOEPMSK); | |
4816 | ||
4817 | for (i = 0; i < hsotg->num_of_eps; i++) { | |
4818 | /* Backup IN EPs */ | |
4819 | dr->diepctl[i] = dwc2_readl(hsotg->regs + DIEPCTL(i)); | |
4820 | ||
4821 | /* Ensure DATA PID is correctly configured */ | |
4822 | if (dr->diepctl[i] & DXEPCTL_DPID) | |
4823 | dr->diepctl[i] |= DXEPCTL_SETD1PID; | |
4824 | else | |
4825 | dr->diepctl[i] |= DXEPCTL_SETD0PID; | |
4826 | ||
4827 | dr->dieptsiz[i] = dwc2_readl(hsotg->regs + DIEPTSIZ(i)); | |
4828 | dr->diepdma[i] = dwc2_readl(hsotg->regs + DIEPDMA(i)); | |
4829 | ||
4830 | /* Backup OUT EPs */ | |
4831 | dr->doepctl[i] = dwc2_readl(hsotg->regs + DOEPCTL(i)); | |
4832 | ||
4833 | /* Ensure DATA PID is correctly configured */ | |
4834 | if (dr->doepctl[i] & DXEPCTL_DPID) | |
4835 | dr->doepctl[i] |= DXEPCTL_SETD1PID; | |
4836 | else | |
4837 | dr->doepctl[i] |= DXEPCTL_SETD0PID; | |
4838 | ||
4839 | dr->doeptsiz[i] = dwc2_readl(hsotg->regs + DOEPTSIZ(i)); | |
4840 | dr->doepdma[i] = dwc2_readl(hsotg->regs + DOEPDMA(i)); | |
4841 | } | |
4842 | dr->valid = true; | |
4843 | return 0; | |
4844 | } | |
4845 | ||
4846 | /** | |
4847 | * dwc2_restore_device_registers() - Restore controller device registers. | |
4848 | * When resuming usb bus, device registers needs to be restored | |
4849 | * if controller power were disabled. | |
4850 | * | |
4851 | * @hsotg: Programming view of the DWC_otg controller | |
4852 | */ | |
4853 | int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg) | |
4854 | { | |
4855 | struct dwc2_dregs_backup *dr; | |
4856 | u32 dctl; | |
4857 | int i; | |
4858 | ||
4859 | dev_dbg(hsotg->dev, "%s\n", __func__); | |
4860 | ||
4861 | /* Restore dev regs */ | |
4862 | dr = &hsotg->dr_backup; | |
4863 | if (!dr->valid) { | |
4864 | dev_err(hsotg->dev, "%s: no device registers to restore\n", | |
4865 | __func__); | |
4866 | return -EINVAL; | |
4867 | } | |
4868 | dr->valid = false; | |
4869 | ||
4870 | dwc2_writel(dr->dcfg, hsotg->regs + DCFG); | |
4871 | dwc2_writel(dr->dctl, hsotg->regs + DCTL); | |
4872 | dwc2_writel(dr->daintmsk, hsotg->regs + DAINTMSK); | |
4873 | dwc2_writel(dr->diepmsk, hsotg->regs + DIEPMSK); | |
4874 | dwc2_writel(dr->doepmsk, hsotg->regs + DOEPMSK); | |
4875 | ||
4876 | for (i = 0; i < hsotg->num_of_eps; i++) { | |
4877 | /* Restore IN EPs */ | |
4878 | dwc2_writel(dr->diepctl[i], hsotg->regs + DIEPCTL(i)); | |
4879 | dwc2_writel(dr->dieptsiz[i], hsotg->regs + DIEPTSIZ(i)); | |
4880 | dwc2_writel(dr->diepdma[i], hsotg->regs + DIEPDMA(i)); | |
4881 | ||
4882 | /* Restore OUT EPs */ | |
4883 | dwc2_writel(dr->doepctl[i], hsotg->regs + DOEPCTL(i)); | |
4884 | dwc2_writel(dr->doeptsiz[i], hsotg->regs + DOEPTSIZ(i)); | |
4885 | dwc2_writel(dr->doepdma[i], hsotg->regs + DOEPDMA(i)); | |
4886 | } | |
4887 | ||
4888 | /* Set the Power-On Programming done bit */ | |
4889 | dctl = dwc2_readl(hsotg->regs + DCTL); | |
4890 | dctl |= DCTL_PWRONPRGDONE; | |
4891 | dwc2_writel(dctl, hsotg->regs + DCTL); | |
4892 | ||
4893 | return 0; | |
4894 | } |