Commit | Line | Data |
---|---|---|
8b9bc460 | 1 | /** |
dfbc6fa3 AT |
2 | * Copyright (c) 2011 Samsung Electronics Co., Ltd. |
3 | * http://www.samsung.com | |
5b7d70c6 BD |
4 | * |
5 | * Copyright 2008 Openmoko, Inc. | |
6 | * Copyright 2008 Simtec Electronics | |
7 | * Ben Dooks <ben@simtec.co.uk> | |
8 | * http://armlinux.simtec.co.uk/ | |
9 | * | |
10 | * S3C USB2.0 High-speed / OtG driver | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License version 2 as | |
14 | * published by the Free Software Foundation. | |
8b9bc460 | 15 | */ |
5b7d70c6 BD |
16 | |
17 | #include <linux/kernel.h> | |
18 | #include <linux/module.h> | |
19 | #include <linux/spinlock.h> | |
20 | #include <linux/interrupt.h> | |
21 | #include <linux/platform_device.h> | |
22 | #include <linux/dma-mapping.h> | |
7ad8096e | 23 | #include <linux/mutex.h> |
5b7d70c6 BD |
24 | #include <linux/seq_file.h> |
25 | #include <linux/delay.h> | |
26 | #include <linux/io.h> | |
5a0e3ad6 | 27 | #include <linux/slab.h> |
c50f056c | 28 | #include <linux/of_platform.h> |
5b7d70c6 BD |
29 | |
30 | #include <linux/usb/ch9.h> | |
31 | #include <linux/usb/gadget.h> | |
b2e587db | 32 | #include <linux/usb/phy.h> |
5b7d70c6 | 33 | |
f7c0b143 | 34 | #include "core.h" |
941fcce4 | 35 | #include "hw.h" |
5b7d70c6 BD |
36 | |
37 | /* conversion functions */ | |
1f91b4cc | 38 | static inline struct dwc2_hsotg_req *our_req(struct usb_request *req) |
5b7d70c6 | 39 | { |
1f91b4cc | 40 | return container_of(req, struct dwc2_hsotg_req, req); |
5b7d70c6 BD |
41 | } |
42 | ||
1f91b4cc | 43 | static inline struct dwc2_hsotg_ep *our_ep(struct usb_ep *ep) |
5b7d70c6 | 44 | { |
1f91b4cc | 45 | return container_of(ep, struct dwc2_hsotg_ep, ep); |
5b7d70c6 BD |
46 | } |
47 | ||
941fcce4 | 48 | static inline struct dwc2_hsotg *to_hsotg(struct usb_gadget *gadget) |
5b7d70c6 | 49 | { |
941fcce4 | 50 | return container_of(gadget, struct dwc2_hsotg, gadget); |
5b7d70c6 BD |
51 | } |
52 | ||
53 | static inline void __orr32(void __iomem *ptr, u32 val) | |
54 | { | |
95c8bc36 | 55 | dwc2_writel(dwc2_readl(ptr) | val, ptr); |
5b7d70c6 BD |
56 | } |
57 | ||
58 | static inline void __bic32(void __iomem *ptr, u32 val) | |
59 | { | |
95c8bc36 | 60 | dwc2_writel(dwc2_readl(ptr) & ~val, ptr); |
5b7d70c6 BD |
61 | } |
62 | ||
1f91b4cc | 63 | static inline struct dwc2_hsotg_ep *index_to_ep(struct dwc2_hsotg *hsotg, |
c6f5c050 MYK |
64 | u32 ep_index, u32 dir_in) |
65 | { | |
66 | if (dir_in) | |
67 | return hsotg->eps_in[ep_index]; | |
68 | else | |
69 | return hsotg->eps_out[ep_index]; | |
70 | } | |
71 | ||
997f4f81 | 72 | /* forward declaration of functions */ |
1f91b4cc | 73 | static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg); |
5b7d70c6 BD |
74 | |
75 | /** | |
76 | * using_dma - return the DMA status of the driver. | |
77 | * @hsotg: The driver state. | |
78 | * | |
79 | * Return true if we're using DMA. | |
80 | * | |
81 | * Currently, we have the DMA support code worked into everywhere | |
82 | * that needs it, but the AMBA DMA implementation in the hardware can | |
83 | * only DMA from 32bit aligned addresses. This means that gadgets such | |
84 | * as the CDC Ethernet cannot work as they often pass packets which are | |
85 | * not 32bit aligned. | |
86 | * | |
87 | * Unfortunately the choice to use DMA or not is global to the controller | |
88 | * and seems to be only settable when the controller is being put through | |
89 | * a core reset. This means we either need to fix the gadgets to take | |
90 | * account of DMA alignment, or add bounce buffers (yuerk). | |
91 | * | |
edd74be8 | 92 | * g_using_dma is set depending on dts flag. |
5b7d70c6 | 93 | */ |
941fcce4 | 94 | static inline bool using_dma(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 95 | { |
05ee799f | 96 | return hsotg->params.g_dma; |
5b7d70c6 BD |
97 | } |
98 | ||
dec4b556 VA |
99 | /* |
100 | * using_desc_dma - return the descriptor DMA status of the driver. | |
101 | * @hsotg: The driver state. | |
102 | * | |
103 | * Return true if we're using descriptor DMA. | |
104 | */ | |
105 | static inline bool using_desc_dma(struct dwc2_hsotg *hsotg) | |
106 | { | |
107 | return hsotg->params.g_dma_desc; | |
108 | } | |
109 | ||
92d1635d VM |
110 | /** |
111 | * dwc2_gadget_incr_frame_num - Increments the targeted frame number. | |
112 | * @hs_ep: The endpoint | |
113 | * @increment: The value to increment by | |
114 | * | |
115 | * This function will also check if the frame number overruns DSTS_SOFFN_LIMIT. | |
116 | * If an overrun occurs it will wrap the value and set the frame_overrun flag. | |
117 | */ | |
118 | static inline void dwc2_gadget_incr_frame_num(struct dwc2_hsotg_ep *hs_ep) | |
119 | { | |
120 | hs_ep->target_frame += hs_ep->interval; | |
121 | if (hs_ep->target_frame > DSTS_SOFFN_LIMIT) { | |
122 | hs_ep->frame_overrun = 1; | |
123 | hs_ep->target_frame &= DSTS_SOFFN_LIMIT; | |
124 | } else { | |
125 | hs_ep->frame_overrun = 0; | |
126 | } | |
127 | } | |
128 | ||
5b7d70c6 | 129 | /** |
1f91b4cc | 130 | * dwc2_hsotg_en_gsint - enable one or more of the general interrupt |
5b7d70c6 BD |
131 | * @hsotg: The device state |
132 | * @ints: A bitmask of the interrupts to enable | |
133 | */ | |
1f91b4cc | 134 | static void dwc2_hsotg_en_gsint(struct dwc2_hsotg *hsotg, u32 ints) |
5b7d70c6 | 135 | { |
95c8bc36 | 136 | u32 gsintmsk = dwc2_readl(hsotg->regs + GINTMSK); |
5b7d70c6 BD |
137 | u32 new_gsintmsk; |
138 | ||
139 | new_gsintmsk = gsintmsk | ints; | |
140 | ||
141 | if (new_gsintmsk != gsintmsk) { | |
142 | dev_dbg(hsotg->dev, "gsintmsk now 0x%08x\n", new_gsintmsk); | |
95c8bc36 | 143 | dwc2_writel(new_gsintmsk, hsotg->regs + GINTMSK); |
5b7d70c6 BD |
144 | } |
145 | } | |
146 | ||
147 | /** | |
1f91b4cc | 148 | * dwc2_hsotg_disable_gsint - disable one or more of the general interrupt |
5b7d70c6 BD |
149 | * @hsotg: The device state |
150 | * @ints: A bitmask of the interrupts to enable | |
151 | */ | |
1f91b4cc | 152 | static void dwc2_hsotg_disable_gsint(struct dwc2_hsotg *hsotg, u32 ints) |
5b7d70c6 | 153 | { |
95c8bc36 | 154 | u32 gsintmsk = dwc2_readl(hsotg->regs + GINTMSK); |
5b7d70c6 BD |
155 | u32 new_gsintmsk; |
156 | ||
157 | new_gsintmsk = gsintmsk & ~ints; | |
158 | ||
159 | if (new_gsintmsk != gsintmsk) | |
95c8bc36 | 160 | dwc2_writel(new_gsintmsk, hsotg->regs + GINTMSK); |
5b7d70c6 BD |
161 | } |
162 | ||
163 | /** | |
1f91b4cc | 164 | * dwc2_hsotg_ctrl_epint - enable/disable an endpoint irq |
5b7d70c6 BD |
165 | * @hsotg: The device state |
166 | * @ep: The endpoint index | |
167 | * @dir_in: True if direction is in. | |
168 | * @en: The enable value, true to enable | |
169 | * | |
170 | * Set or clear the mask for an individual endpoint's interrupt | |
171 | * request. | |
172 | */ | |
1f91b4cc | 173 | static void dwc2_hsotg_ctrl_epint(struct dwc2_hsotg *hsotg, |
5b7d70c6 BD |
174 | unsigned int ep, unsigned int dir_in, |
175 | unsigned int en) | |
176 | { | |
177 | unsigned long flags; | |
178 | u32 bit = 1 << ep; | |
179 | u32 daint; | |
180 | ||
181 | if (!dir_in) | |
182 | bit <<= 16; | |
183 | ||
184 | local_irq_save(flags); | |
95c8bc36 | 185 | daint = dwc2_readl(hsotg->regs + DAINTMSK); |
5b7d70c6 BD |
186 | if (en) |
187 | daint |= bit; | |
188 | else | |
189 | daint &= ~bit; | |
95c8bc36 | 190 | dwc2_writel(daint, hsotg->regs + DAINTMSK); |
5b7d70c6 BD |
191 | local_irq_restore(flags); |
192 | } | |
193 | ||
194 | /** | |
1f91b4cc | 195 | * dwc2_hsotg_init_fifo - initialise non-periodic FIFOs |
5b7d70c6 BD |
196 | * @hsotg: The device instance. |
197 | */ | |
1f91b4cc | 198 | static void dwc2_hsotg_init_fifo(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 199 | { |
2317eacd | 200 | unsigned int ep; |
0f002d20 | 201 | unsigned int addr; |
1703a6d3 | 202 | int timeout; |
0f002d20 | 203 | u32 val; |
05ee799f | 204 | u32 *txfsz = hsotg->params.g_tx_fifo_size; |
0f002d20 | 205 | |
7fcbc95c GH |
206 | /* Reset fifo map if not correctly cleared during previous session */ |
207 | WARN_ON(hsotg->fifo_map); | |
208 | hsotg->fifo_map = 0; | |
209 | ||
0a176279 | 210 | /* set RX/NPTX FIFO sizes */ |
05ee799f JY |
211 | dwc2_writel(hsotg->params.g_rx_fifo_size, hsotg->regs + GRXFSIZ); |
212 | dwc2_writel((hsotg->params.g_rx_fifo_size << FIFOSIZE_STARTADDR_SHIFT) | | |
213 | (hsotg->params.g_np_tx_fifo_size << FIFOSIZE_DEPTH_SHIFT), | |
214 | hsotg->regs + GNPTXFSIZ); | |
0f002d20 | 215 | |
8b9bc460 LM |
216 | /* |
217 | * arange all the rest of the TX FIFOs, as some versions of this | |
0f002d20 BD |
218 | * block have overlapping default addresses. This also ensures |
219 | * that if the settings have been changed, then they are set to | |
8b9bc460 LM |
220 | * known values. |
221 | */ | |
0f002d20 BD |
222 | |
223 | /* start at the end of the GNPTXFSIZ, rounded up */ | |
05ee799f | 224 | addr = hsotg->params.g_rx_fifo_size + hsotg->params.g_np_tx_fifo_size; |
0f002d20 | 225 | |
8b9bc460 | 226 | /* |
0a176279 | 227 | * Configure fifos sizes from provided configuration and assign |
b203d0a2 RB |
228 | * them to endpoints dynamically according to maxpacket size value of |
229 | * given endpoint. | |
8b9bc460 | 230 | */ |
2317eacd | 231 | for (ep = 1; ep < MAX_EPS_CHANNELS; ep++) { |
05ee799f | 232 | if (!txfsz[ep]) |
3fa95385 JY |
233 | continue; |
234 | val = addr; | |
05ee799f JY |
235 | val |= txfsz[ep] << FIFOSIZE_DEPTH_SHIFT; |
236 | WARN_ONCE(addr + txfsz[ep] > hsotg->fifo_mem, | |
3fa95385 | 237 | "insufficient fifo memory"); |
05ee799f | 238 | addr += txfsz[ep]; |
0f002d20 | 239 | |
2317eacd | 240 | dwc2_writel(val, hsotg->regs + DPTXFSIZN(ep)); |
05ee799f | 241 | val = dwc2_readl(hsotg->regs + DPTXFSIZN(ep)); |
0f002d20 | 242 | } |
1703a6d3 | 243 | |
8b9bc460 LM |
244 | /* |
245 | * according to p428 of the design guide, we need to ensure that | |
246 | * all fifos are flushed before continuing | |
247 | */ | |
1703a6d3 | 248 | |
95c8bc36 | 249 | dwc2_writel(GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH | |
47a1685f | 250 | GRSTCTL_RXFFLSH, hsotg->regs + GRSTCTL); |
1703a6d3 BD |
251 | |
252 | /* wait until the fifos are both flushed */ | |
253 | timeout = 100; | |
254 | while (1) { | |
95c8bc36 | 255 | val = dwc2_readl(hsotg->regs + GRSTCTL); |
1703a6d3 | 256 | |
47a1685f | 257 | if ((val & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH)) == 0) |
1703a6d3 BD |
258 | break; |
259 | ||
260 | if (--timeout == 0) { | |
261 | dev_err(hsotg->dev, | |
262 | "%s: timeout flushing fifos (GRSTCTL=%08x)\n", | |
263 | __func__, val); | |
48b20bcb | 264 | break; |
1703a6d3 BD |
265 | } |
266 | ||
267 | udelay(1); | |
268 | } | |
269 | ||
270 | dev_dbg(hsotg->dev, "FIFOs reset, timeout at %d\n", timeout); | |
5b7d70c6 BD |
271 | } |
272 | ||
273 | /** | |
274 | * @ep: USB endpoint to allocate request for. | |
275 | * @flags: Allocation flags | |
276 | * | |
277 | * Allocate a new USB request structure appropriate for the specified endpoint | |
278 | */ | |
1f91b4cc | 279 | static struct usb_request *dwc2_hsotg_ep_alloc_request(struct usb_ep *ep, |
0978f8c5 | 280 | gfp_t flags) |
5b7d70c6 | 281 | { |
1f91b4cc | 282 | struct dwc2_hsotg_req *req; |
5b7d70c6 | 283 | |
1f91b4cc | 284 | req = kzalloc(sizeof(struct dwc2_hsotg_req), flags); |
5b7d70c6 BD |
285 | if (!req) |
286 | return NULL; | |
287 | ||
288 | INIT_LIST_HEAD(&req->queue); | |
289 | ||
5b7d70c6 BD |
290 | return &req->req; |
291 | } | |
292 | ||
293 | /** | |
294 | * is_ep_periodic - return true if the endpoint is in periodic mode. | |
295 | * @hs_ep: The endpoint to query. | |
296 | * | |
297 | * Returns true if the endpoint is in periodic mode, meaning it is being | |
298 | * used for an Interrupt or ISO transfer. | |
299 | */ | |
1f91b4cc | 300 | static inline int is_ep_periodic(struct dwc2_hsotg_ep *hs_ep) |
5b7d70c6 BD |
301 | { |
302 | return hs_ep->periodic; | |
303 | } | |
304 | ||
305 | /** | |
1f91b4cc | 306 | * dwc2_hsotg_unmap_dma - unmap the DMA memory being used for the request |
5b7d70c6 BD |
307 | * @hsotg: The device state. |
308 | * @hs_ep: The endpoint for the request | |
309 | * @hs_req: The request being processed. | |
310 | * | |
1f91b4cc | 311 | * This is the reverse of dwc2_hsotg_map_dma(), called for the completion |
5b7d70c6 | 312 | * of a request to ensure the buffer is ready for access by the caller. |
8b9bc460 | 313 | */ |
1f91b4cc FB |
314 | static void dwc2_hsotg_unmap_dma(struct dwc2_hsotg *hsotg, |
315 | struct dwc2_hsotg_ep *hs_ep, | |
316 | struct dwc2_hsotg_req *hs_req) | |
5b7d70c6 BD |
317 | { |
318 | struct usb_request *req = &hs_req->req; | |
5b7d70c6 BD |
319 | |
320 | /* ignore this if we're not moving any data */ | |
321 | if (hs_req->req.length == 0) | |
322 | return; | |
323 | ||
17d966a3 | 324 | usb_gadget_unmap_request(&hsotg->gadget, req, hs_ep->dir_in); |
5b7d70c6 BD |
325 | } |
326 | ||
327 | /** | |
1f91b4cc | 328 | * dwc2_hsotg_write_fifo - write packet Data to the TxFIFO |
5b7d70c6 BD |
329 | * @hsotg: The controller state. |
330 | * @hs_ep: The endpoint we're going to write for. | |
331 | * @hs_req: The request to write data for. | |
332 | * | |
333 | * This is called when the TxFIFO has some space in it to hold a new | |
334 | * transmission and we have something to give it. The actual setup of | |
335 | * the data size is done elsewhere, so all we have to do is to actually | |
336 | * write the data. | |
337 | * | |
338 | * The return value is zero if there is more space (or nothing was done) | |
339 | * otherwise -ENOSPC is returned if the FIFO space was used up. | |
340 | * | |
341 | * This routine is only needed for PIO | |
8b9bc460 | 342 | */ |
1f91b4cc FB |
343 | static int dwc2_hsotg_write_fifo(struct dwc2_hsotg *hsotg, |
344 | struct dwc2_hsotg_ep *hs_ep, | |
345 | struct dwc2_hsotg_req *hs_req) | |
5b7d70c6 BD |
346 | { |
347 | bool periodic = is_ep_periodic(hs_ep); | |
95c8bc36 | 348 | u32 gnptxsts = dwc2_readl(hsotg->regs + GNPTXSTS); |
5b7d70c6 BD |
349 | int buf_pos = hs_req->req.actual; |
350 | int to_write = hs_ep->size_loaded; | |
351 | void *data; | |
352 | int can_write; | |
353 | int pkt_round; | |
4fca54aa | 354 | int max_transfer; |
5b7d70c6 BD |
355 | |
356 | to_write -= (buf_pos - hs_ep->last_load); | |
357 | ||
358 | /* if there's nothing to write, get out early */ | |
359 | if (to_write == 0) | |
360 | return 0; | |
361 | ||
10aebc77 | 362 | if (periodic && !hsotg->dedicated_fifos) { |
95c8bc36 | 363 | u32 epsize = dwc2_readl(hsotg->regs + DIEPTSIZ(hs_ep->index)); |
5b7d70c6 BD |
364 | int size_left; |
365 | int size_done; | |
366 | ||
8b9bc460 LM |
367 | /* |
368 | * work out how much data was loaded so we can calculate | |
369 | * how much data is left in the fifo. | |
370 | */ | |
5b7d70c6 | 371 | |
47a1685f | 372 | size_left = DXEPTSIZ_XFERSIZE_GET(epsize); |
5b7d70c6 | 373 | |
8b9bc460 LM |
374 | /* |
375 | * if shared fifo, we cannot write anything until the | |
e7a9ff54 BD |
376 | * previous data has been completely sent. |
377 | */ | |
378 | if (hs_ep->fifo_load != 0) { | |
1f91b4cc | 379 | dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP); |
e7a9ff54 BD |
380 | return -ENOSPC; |
381 | } | |
382 | ||
5b7d70c6 BD |
383 | dev_dbg(hsotg->dev, "%s: left=%d, load=%d, fifo=%d, size %d\n", |
384 | __func__, size_left, | |
385 | hs_ep->size_loaded, hs_ep->fifo_load, hs_ep->fifo_size); | |
386 | ||
387 | /* how much of the data has moved */ | |
388 | size_done = hs_ep->size_loaded - size_left; | |
389 | ||
390 | /* how much data is left in the fifo */ | |
391 | can_write = hs_ep->fifo_load - size_done; | |
392 | dev_dbg(hsotg->dev, "%s: => can_write1=%d\n", | |
393 | __func__, can_write); | |
394 | ||
395 | can_write = hs_ep->fifo_size - can_write; | |
396 | dev_dbg(hsotg->dev, "%s: => can_write2=%d\n", | |
397 | __func__, can_write); | |
398 | ||
399 | if (can_write <= 0) { | |
1f91b4cc | 400 | dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP); |
5b7d70c6 BD |
401 | return -ENOSPC; |
402 | } | |
10aebc77 | 403 | } else if (hsotg->dedicated_fifos && hs_ep->index != 0) { |
ad674a15 RB |
404 | can_write = dwc2_readl(hsotg->regs + |
405 | DTXFSTS(hs_ep->fifo_index)); | |
10aebc77 BD |
406 | |
407 | can_write &= 0xffff; | |
408 | can_write *= 4; | |
5b7d70c6 | 409 | } else { |
47a1685f | 410 | if (GNPTXSTS_NP_TXQ_SPC_AVAIL_GET(gnptxsts) == 0) { |
5b7d70c6 BD |
411 | dev_dbg(hsotg->dev, |
412 | "%s: no queue slots available (0x%08x)\n", | |
413 | __func__, gnptxsts); | |
414 | ||
1f91b4cc | 415 | dwc2_hsotg_en_gsint(hsotg, GINTSTS_NPTXFEMP); |
5b7d70c6 BD |
416 | return -ENOSPC; |
417 | } | |
418 | ||
47a1685f | 419 | can_write = GNPTXSTS_NP_TXF_SPC_AVAIL_GET(gnptxsts); |
679f9b7c | 420 | can_write *= 4; /* fifo size is in 32bit quantities. */ |
5b7d70c6 BD |
421 | } |
422 | ||
4fca54aa RB |
423 | max_transfer = hs_ep->ep.maxpacket * hs_ep->mc; |
424 | ||
425 | dev_dbg(hsotg->dev, "%s: GNPTXSTS=%08x, can=%d, to=%d, max_transfer %d\n", | |
426 | __func__, gnptxsts, can_write, to_write, max_transfer); | |
5b7d70c6 | 427 | |
8b9bc460 LM |
428 | /* |
429 | * limit to 512 bytes of data, it seems at least on the non-periodic | |
5b7d70c6 BD |
430 | * FIFO, requests of >512 cause the endpoint to get stuck with a |
431 | * fragment of the end of the transfer in it. | |
432 | */ | |
811f3303 | 433 | if (can_write > 512 && !periodic) |
5b7d70c6 BD |
434 | can_write = 512; |
435 | ||
8b9bc460 LM |
436 | /* |
437 | * limit the write to one max-packet size worth of data, but allow | |
03e10e5a | 438 | * the transfer to return that it did not run out of fifo space |
8b9bc460 LM |
439 | * doing it. |
440 | */ | |
4fca54aa RB |
441 | if (to_write > max_transfer) { |
442 | to_write = max_transfer; | |
03e10e5a | 443 | |
5cb2ff0c RB |
444 | /* it's needed only when we do not use dedicated fifos */ |
445 | if (!hsotg->dedicated_fifos) | |
1f91b4cc | 446 | dwc2_hsotg_en_gsint(hsotg, |
47a1685f DN |
447 | periodic ? GINTSTS_PTXFEMP : |
448 | GINTSTS_NPTXFEMP); | |
03e10e5a BD |
449 | } |
450 | ||
5b7d70c6 BD |
451 | /* see if we can write data */ |
452 | ||
453 | if (to_write > can_write) { | |
454 | to_write = can_write; | |
4fca54aa | 455 | pkt_round = to_write % max_transfer; |
5b7d70c6 | 456 | |
8b9bc460 LM |
457 | /* |
458 | * Round the write down to an | |
5b7d70c6 BD |
459 | * exact number of packets. |
460 | * | |
461 | * Note, we do not currently check to see if we can ever | |
462 | * write a full packet or not to the FIFO. | |
463 | */ | |
464 | ||
465 | if (pkt_round) | |
466 | to_write -= pkt_round; | |
467 | ||
8b9bc460 LM |
468 | /* |
469 | * enable correct FIFO interrupt to alert us when there | |
470 | * is more room left. | |
471 | */ | |
5b7d70c6 | 472 | |
5cb2ff0c RB |
473 | /* it's needed only when we do not use dedicated fifos */ |
474 | if (!hsotg->dedicated_fifos) | |
1f91b4cc | 475 | dwc2_hsotg_en_gsint(hsotg, |
47a1685f DN |
476 | periodic ? GINTSTS_PTXFEMP : |
477 | GINTSTS_NPTXFEMP); | |
5b7d70c6 BD |
478 | } |
479 | ||
480 | dev_dbg(hsotg->dev, "write %d/%d, can_write %d, done %d\n", | |
481 | to_write, hs_req->req.length, can_write, buf_pos); | |
482 | ||
483 | if (to_write <= 0) | |
484 | return -ENOSPC; | |
485 | ||
486 | hs_req->req.actual = buf_pos + to_write; | |
487 | hs_ep->total_data += to_write; | |
488 | ||
489 | if (periodic) | |
490 | hs_ep->fifo_load += to_write; | |
491 | ||
492 | to_write = DIV_ROUND_UP(to_write, 4); | |
493 | data = hs_req->req.buf + buf_pos; | |
494 | ||
1a7ed5be | 495 | iowrite32_rep(hsotg->regs + EPFIFO(hs_ep->index), data, to_write); |
5b7d70c6 BD |
496 | |
497 | return (to_write >= can_write) ? -ENOSPC : 0; | |
498 | } | |
499 | ||
500 | /** | |
501 | * get_ep_limit - get the maximum data legnth for this endpoint | |
502 | * @hs_ep: The endpoint | |
503 | * | |
504 | * Return the maximum data that can be queued in one go on a given endpoint | |
505 | * so that transfers that are too long can be split. | |
506 | */ | |
1f91b4cc | 507 | static unsigned get_ep_limit(struct dwc2_hsotg_ep *hs_ep) |
5b7d70c6 BD |
508 | { |
509 | int index = hs_ep->index; | |
510 | unsigned maxsize; | |
511 | unsigned maxpkt; | |
512 | ||
513 | if (index != 0) { | |
47a1685f DN |
514 | maxsize = DXEPTSIZ_XFERSIZE_LIMIT + 1; |
515 | maxpkt = DXEPTSIZ_PKTCNT_LIMIT + 1; | |
5b7d70c6 | 516 | } else { |
b05ca580 | 517 | maxsize = 64+64; |
66e5c643 | 518 | if (hs_ep->dir_in) |
47a1685f | 519 | maxpkt = DIEPTSIZ0_PKTCNT_LIMIT + 1; |
66e5c643 | 520 | else |
5b7d70c6 | 521 | maxpkt = 2; |
5b7d70c6 BD |
522 | } |
523 | ||
524 | /* we made the constant loading easier above by using +1 */ | |
525 | maxpkt--; | |
526 | maxsize--; | |
527 | ||
8b9bc460 LM |
528 | /* |
529 | * constrain by packet count if maxpkts*pktsize is greater | |
530 | * than the length register size. | |
531 | */ | |
5b7d70c6 BD |
532 | |
533 | if ((maxpkt * hs_ep->ep.maxpacket) < maxsize) | |
534 | maxsize = maxpkt * hs_ep->ep.maxpacket; | |
535 | ||
536 | return maxsize; | |
537 | } | |
538 | ||
381fc8f8 VM |
539 | /** |
540 | * dwc2_hsotg_read_frameno - read current frame number | |
541 | * @hsotg: The device instance | |
542 | * | |
543 | * Return the current frame number | |
544 | */ | |
545 | static u32 dwc2_hsotg_read_frameno(struct dwc2_hsotg *hsotg) | |
546 | { | |
547 | u32 dsts; | |
548 | ||
549 | dsts = dwc2_readl(hsotg->regs + DSTS); | |
550 | dsts &= DSTS_SOFFN_MASK; | |
551 | dsts >>= DSTS_SOFFN_SHIFT; | |
552 | ||
553 | return dsts; | |
554 | } | |
555 | ||
5b7d70c6 | 556 | /** |
1f91b4cc | 557 | * dwc2_hsotg_start_req - start a USB request from an endpoint's queue |
5b7d70c6 BD |
558 | * @hsotg: The controller state. |
559 | * @hs_ep: The endpoint to process a request for | |
560 | * @hs_req: The request to start. | |
561 | * @continuing: True if we are doing more for the current request. | |
562 | * | |
563 | * Start the given request running by setting the endpoint registers | |
564 | * appropriately, and writing any data to the FIFOs. | |
565 | */ | |
1f91b4cc FB |
566 | static void dwc2_hsotg_start_req(struct dwc2_hsotg *hsotg, |
567 | struct dwc2_hsotg_ep *hs_ep, | |
568 | struct dwc2_hsotg_req *hs_req, | |
5b7d70c6 BD |
569 | bool continuing) |
570 | { | |
571 | struct usb_request *ureq = &hs_req->req; | |
572 | int index = hs_ep->index; | |
573 | int dir_in = hs_ep->dir_in; | |
574 | u32 epctrl_reg; | |
575 | u32 epsize_reg; | |
576 | u32 epsize; | |
577 | u32 ctrl; | |
578 | unsigned length; | |
579 | unsigned packets; | |
580 | unsigned maxreq; | |
581 | ||
582 | if (index != 0) { | |
583 | if (hs_ep->req && !continuing) { | |
584 | dev_err(hsotg->dev, "%s: active request\n", __func__); | |
585 | WARN_ON(1); | |
586 | return; | |
587 | } else if (hs_ep->req != hs_req && continuing) { | |
588 | dev_err(hsotg->dev, | |
589 | "%s: continue different req\n", __func__); | |
590 | WARN_ON(1); | |
591 | return; | |
592 | } | |
593 | } | |
594 | ||
94cb8fd6 LM |
595 | epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index); |
596 | epsize_reg = dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index); | |
5b7d70c6 BD |
597 | |
598 | dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n", | |
95c8bc36 | 599 | __func__, dwc2_readl(hsotg->regs + epctrl_reg), index, |
5b7d70c6 BD |
600 | hs_ep->dir_in ? "in" : "out"); |
601 | ||
9c39ddc6 | 602 | /* If endpoint is stalled, we will restart request later */ |
95c8bc36 | 603 | ctrl = dwc2_readl(hsotg->regs + epctrl_reg); |
9c39ddc6 | 604 | |
b2d4c54e | 605 | if (index && ctrl & DXEPCTL_STALL) { |
9c39ddc6 AT |
606 | dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index); |
607 | return; | |
608 | } | |
609 | ||
5b7d70c6 | 610 | length = ureq->length - ureq->actual; |
71225bee LM |
611 | dev_dbg(hsotg->dev, "ureq->length:%d ureq->actual:%d\n", |
612 | ureq->length, ureq->actual); | |
5b7d70c6 BD |
613 | |
614 | maxreq = get_ep_limit(hs_ep); | |
615 | if (length > maxreq) { | |
616 | int round = maxreq % hs_ep->ep.maxpacket; | |
617 | ||
618 | dev_dbg(hsotg->dev, "%s: length %d, max-req %d, r %d\n", | |
619 | __func__, length, maxreq, round); | |
620 | ||
621 | /* round down to multiple of packets */ | |
622 | if (round) | |
623 | maxreq -= round; | |
624 | ||
625 | length = maxreq; | |
626 | } | |
627 | ||
628 | if (length) | |
629 | packets = DIV_ROUND_UP(length, hs_ep->ep.maxpacket); | |
630 | else | |
631 | packets = 1; /* send one packet if length is zero. */ | |
632 | ||
4fca54aa RB |
633 | if (hs_ep->isochronous && length > (hs_ep->mc * hs_ep->ep.maxpacket)) { |
634 | dev_err(hsotg->dev, "req length > maxpacket*mc\n"); | |
635 | return; | |
636 | } | |
637 | ||
5b7d70c6 | 638 | if (dir_in && index != 0) |
4fca54aa | 639 | if (hs_ep->isochronous) |
47a1685f | 640 | epsize = DXEPTSIZ_MC(packets); |
4fca54aa | 641 | else |
47a1685f | 642 | epsize = DXEPTSIZ_MC(1); |
5b7d70c6 BD |
643 | else |
644 | epsize = 0; | |
645 | ||
f71b5e25 MYK |
646 | /* |
647 | * zero length packet should be programmed on its own and should not | |
648 | * be counted in DIEPTSIZ.PktCnt with other packets. | |
649 | */ | |
650 | if (dir_in && ureq->zero && !continuing) { | |
651 | /* Test if zlp is actually required. */ | |
652 | if ((ureq->length >= hs_ep->ep.maxpacket) && | |
653 | !(ureq->length % hs_ep->ep.maxpacket)) | |
8a20fa45 | 654 | hs_ep->send_zlp = 1; |
5b7d70c6 BD |
655 | } |
656 | ||
47a1685f DN |
657 | epsize |= DXEPTSIZ_PKTCNT(packets); |
658 | epsize |= DXEPTSIZ_XFERSIZE(length); | |
5b7d70c6 BD |
659 | |
660 | dev_dbg(hsotg->dev, "%s: %d@%d/%d, 0x%08x => 0x%08x\n", | |
661 | __func__, packets, length, ureq->length, epsize, epsize_reg); | |
662 | ||
663 | /* store the request as the current one we're doing */ | |
664 | hs_ep->req = hs_req; | |
665 | ||
666 | /* write size / packets */ | |
95c8bc36 | 667 | dwc2_writel(epsize, hsotg->regs + epsize_reg); |
5b7d70c6 | 668 | |
db1d8ba3 | 669 | if (using_dma(hsotg) && !continuing) { |
5b7d70c6 BD |
670 | unsigned int dma_reg; |
671 | ||
8b9bc460 LM |
672 | /* |
673 | * write DMA address to control register, buffer already | |
1f91b4cc | 674 | * synced by dwc2_hsotg_ep_queue(). |
8b9bc460 | 675 | */ |
5b7d70c6 | 676 | |
94cb8fd6 | 677 | dma_reg = dir_in ? DIEPDMA(index) : DOEPDMA(index); |
95c8bc36 | 678 | dwc2_writel(ureq->dma, hsotg->regs + dma_reg); |
5b7d70c6 | 679 | |
0cc4cf6f | 680 | dev_dbg(hsotg->dev, "%s: %pad => 0x%08x\n", |
8b3bc14f | 681 | __func__, &ureq->dma, dma_reg); |
5b7d70c6 BD |
682 | } |
683 | ||
837e9f00 VM |
684 | if (hs_ep->isochronous && hs_ep->interval == 1) { |
685 | hs_ep->target_frame = dwc2_hsotg_read_frameno(hsotg); | |
686 | dwc2_gadget_incr_frame_num(hs_ep); | |
687 | ||
688 | if (hs_ep->target_frame & 0x1) | |
689 | ctrl |= DXEPCTL_SETODDFR; | |
690 | else | |
691 | ctrl |= DXEPCTL_SETEVENFR; | |
692 | } | |
693 | ||
47a1685f | 694 | ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */ |
71225bee | 695 | |
fe0b94ab | 696 | dev_dbg(hsotg->dev, "ep0 state:%d\n", hsotg->ep0_state); |
71225bee LM |
697 | |
698 | /* For Setup request do not clear NAK */ | |
fe0b94ab | 699 | if (!(index == 0 && hsotg->ep0_state == DWC2_EP0_SETUP)) |
47a1685f | 700 | ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */ |
71225bee | 701 | |
5b7d70c6 | 702 | dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl); |
95c8bc36 | 703 | dwc2_writel(ctrl, hsotg->regs + epctrl_reg); |
5b7d70c6 | 704 | |
8b9bc460 LM |
705 | /* |
706 | * set these, it seems that DMA support increments past the end | |
5b7d70c6 | 707 | * of the packet buffer so we need to calculate the length from |
8b9bc460 LM |
708 | * this information. |
709 | */ | |
5b7d70c6 BD |
710 | hs_ep->size_loaded = length; |
711 | hs_ep->last_load = ureq->actual; | |
712 | ||
713 | if (dir_in && !using_dma(hsotg)) { | |
714 | /* set these anyway, we may need them for non-periodic in */ | |
715 | hs_ep->fifo_load = 0; | |
716 | ||
1f91b4cc | 717 | dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req); |
5b7d70c6 BD |
718 | } |
719 | ||
8b9bc460 LM |
720 | /* |
721 | * Note, trying to clear the NAK here causes problems with transmit | |
722 | * on the S3C6400 ending up with the TXFIFO becoming full. | |
723 | */ | |
5b7d70c6 BD |
724 | |
725 | /* check ep is enabled */ | |
95c8bc36 | 726 | if (!(dwc2_readl(hsotg->regs + epctrl_reg) & DXEPCTL_EPENA)) |
1a0ed863 | 727 | dev_dbg(hsotg->dev, |
47a1685f | 728 | "ep%d: failed to become enabled (DXEPCTL=0x%08x)?\n", |
95c8bc36 | 729 | index, dwc2_readl(hsotg->regs + epctrl_reg)); |
5b7d70c6 | 730 | |
47a1685f | 731 | dev_dbg(hsotg->dev, "%s: DXEPCTL=0x%08x\n", |
95c8bc36 | 732 | __func__, dwc2_readl(hsotg->regs + epctrl_reg)); |
afcf4169 RB |
733 | |
734 | /* enable ep interrupts */ | |
1f91b4cc | 735 | dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 1); |
5b7d70c6 BD |
736 | } |
737 | ||
738 | /** | |
1f91b4cc | 739 | * dwc2_hsotg_map_dma - map the DMA memory being used for the request |
5b7d70c6 BD |
740 | * @hsotg: The device state. |
741 | * @hs_ep: The endpoint the request is on. | |
742 | * @req: The request being processed. | |
743 | * | |
744 | * We've been asked to queue a request, so ensure that the memory buffer | |
745 | * is correctly setup for DMA. If we've been passed an extant DMA address | |
746 | * then ensure the buffer has been synced to memory. If our buffer has no | |
747 | * DMA memory, then we map the memory and mark our request to allow us to | |
748 | * cleanup on completion. | |
8b9bc460 | 749 | */ |
1f91b4cc FB |
750 | static int dwc2_hsotg_map_dma(struct dwc2_hsotg *hsotg, |
751 | struct dwc2_hsotg_ep *hs_ep, | |
5b7d70c6 BD |
752 | struct usb_request *req) |
753 | { | |
1f91b4cc | 754 | struct dwc2_hsotg_req *hs_req = our_req(req); |
e58ebcd1 | 755 | int ret; |
5b7d70c6 BD |
756 | |
757 | /* if the length is zero, ignore the DMA data */ | |
758 | if (hs_req->req.length == 0) | |
759 | return 0; | |
760 | ||
e58ebcd1 FB |
761 | ret = usb_gadget_map_request(&hsotg->gadget, req, hs_ep->dir_in); |
762 | if (ret) | |
763 | goto dma_error; | |
5b7d70c6 BD |
764 | |
765 | return 0; | |
766 | ||
767 | dma_error: | |
768 | dev_err(hsotg->dev, "%s: failed to map buffer %p, %d bytes\n", | |
769 | __func__, req->buf, req->length); | |
770 | ||
771 | return -EIO; | |
772 | } | |
773 | ||
1f91b4cc FB |
774 | static int dwc2_hsotg_handle_unaligned_buf_start(struct dwc2_hsotg *hsotg, |
775 | struct dwc2_hsotg_ep *hs_ep, struct dwc2_hsotg_req *hs_req) | |
7d24c1b5 MYK |
776 | { |
777 | void *req_buf = hs_req->req.buf; | |
778 | ||
779 | /* If dma is not being used or buffer is aligned */ | |
780 | if (!using_dma(hsotg) || !((long)req_buf & 3)) | |
781 | return 0; | |
782 | ||
783 | WARN_ON(hs_req->saved_req_buf); | |
784 | ||
785 | dev_dbg(hsotg->dev, "%s: %s: buf=%p length=%d\n", __func__, | |
786 | hs_ep->ep.name, req_buf, hs_req->req.length); | |
787 | ||
788 | hs_req->req.buf = kmalloc(hs_req->req.length, GFP_ATOMIC); | |
789 | if (!hs_req->req.buf) { | |
790 | hs_req->req.buf = req_buf; | |
791 | dev_err(hsotg->dev, | |
792 | "%s: unable to allocate memory for bounce buffer\n", | |
793 | __func__); | |
794 | return -ENOMEM; | |
795 | } | |
796 | ||
797 | /* Save actual buffer */ | |
798 | hs_req->saved_req_buf = req_buf; | |
799 | ||
800 | if (hs_ep->dir_in) | |
801 | memcpy(hs_req->req.buf, req_buf, hs_req->req.length); | |
802 | return 0; | |
803 | } | |
804 | ||
1f91b4cc FB |
805 | static void dwc2_hsotg_handle_unaligned_buf_complete(struct dwc2_hsotg *hsotg, |
806 | struct dwc2_hsotg_ep *hs_ep, struct dwc2_hsotg_req *hs_req) | |
7d24c1b5 MYK |
807 | { |
808 | /* If dma is not being used or buffer was aligned */ | |
809 | if (!using_dma(hsotg) || !hs_req->saved_req_buf) | |
810 | return; | |
811 | ||
812 | dev_dbg(hsotg->dev, "%s: %s: status=%d actual-length=%d\n", __func__, | |
813 | hs_ep->ep.name, hs_req->req.status, hs_req->req.actual); | |
814 | ||
815 | /* Copy data from bounce buffer on successful out transfer */ | |
816 | if (!hs_ep->dir_in && !hs_req->req.status) | |
817 | memcpy(hs_req->saved_req_buf, hs_req->req.buf, | |
818 | hs_req->req.actual); | |
819 | ||
820 | /* Free bounce buffer */ | |
821 | kfree(hs_req->req.buf); | |
822 | ||
823 | hs_req->req.buf = hs_req->saved_req_buf; | |
824 | hs_req->saved_req_buf = NULL; | |
825 | } | |
826 | ||
381fc8f8 VM |
827 | /** |
828 | * dwc2_gadget_target_frame_elapsed - Checks target frame | |
829 | * @hs_ep: The driver endpoint to check | |
830 | * | |
831 | * Returns 1 if targeted frame elapsed. If returned 1 then we need to drop | |
832 | * corresponding transfer. | |
833 | */ | |
834 | static bool dwc2_gadget_target_frame_elapsed(struct dwc2_hsotg_ep *hs_ep) | |
835 | { | |
836 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
837 | u32 target_frame = hs_ep->target_frame; | |
838 | u32 current_frame = dwc2_hsotg_read_frameno(hsotg); | |
839 | bool frame_overrun = hs_ep->frame_overrun; | |
840 | ||
841 | if (!frame_overrun && current_frame >= target_frame) | |
842 | return true; | |
843 | ||
844 | if (frame_overrun && current_frame >= target_frame && | |
845 | ((current_frame - target_frame) < DSTS_SOFFN_LIMIT / 2)) | |
846 | return true; | |
847 | ||
848 | return false; | |
849 | } | |
850 | ||
1f91b4cc | 851 | static int dwc2_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req, |
5b7d70c6 BD |
852 | gfp_t gfp_flags) |
853 | { | |
1f91b4cc FB |
854 | struct dwc2_hsotg_req *hs_req = our_req(req); |
855 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); | |
941fcce4 | 856 | struct dwc2_hsotg *hs = hs_ep->parent; |
5b7d70c6 | 857 | bool first; |
7d24c1b5 | 858 | int ret; |
5b7d70c6 BD |
859 | |
860 | dev_dbg(hs->dev, "%s: req %p: %d@%p, noi=%d, zero=%d, snok=%d\n", | |
861 | ep->name, req, req->length, req->buf, req->no_interrupt, | |
862 | req->zero, req->short_not_ok); | |
863 | ||
7ababa92 GH |
864 | /* Prevent new request submission when controller is suspended */ |
865 | if (hs->lx_state == DWC2_L2) { | |
866 | dev_dbg(hs->dev, "%s: don't submit request while suspended\n", | |
867 | __func__); | |
868 | return -EAGAIN; | |
869 | } | |
870 | ||
5b7d70c6 BD |
871 | /* initialise status of the request */ |
872 | INIT_LIST_HEAD(&hs_req->queue); | |
873 | req->actual = 0; | |
874 | req->status = -EINPROGRESS; | |
875 | ||
1f91b4cc | 876 | ret = dwc2_hsotg_handle_unaligned_buf_start(hs, hs_ep, hs_req); |
7d24c1b5 MYK |
877 | if (ret) |
878 | return ret; | |
879 | ||
5b7d70c6 BD |
880 | /* if we're using DMA, sync the buffers as necessary */ |
881 | if (using_dma(hs)) { | |
1f91b4cc | 882 | ret = dwc2_hsotg_map_dma(hs, hs_ep, req); |
5b7d70c6 BD |
883 | if (ret) |
884 | return ret; | |
885 | } | |
886 | ||
5b7d70c6 BD |
887 | first = list_empty(&hs_ep->queue); |
888 | list_add_tail(&hs_req->queue, &hs_ep->queue); | |
889 | ||
837e9f00 VM |
890 | if (first) { |
891 | if (!hs_ep->isochronous) { | |
892 | dwc2_hsotg_start_req(hs, hs_ep, hs_req, false); | |
893 | return 0; | |
894 | } | |
895 | ||
896 | while (dwc2_gadget_target_frame_elapsed(hs_ep)) | |
897 | dwc2_gadget_incr_frame_num(hs_ep); | |
5b7d70c6 | 898 | |
837e9f00 VM |
899 | if (hs_ep->target_frame != TARGET_FRAME_INITIAL) |
900 | dwc2_hsotg_start_req(hs, hs_ep, hs_req, false); | |
901 | } | |
5b7d70c6 BD |
902 | return 0; |
903 | } | |
904 | ||
1f91b4cc | 905 | static int dwc2_hsotg_ep_queue_lock(struct usb_ep *ep, struct usb_request *req, |
5ad1d316 LM |
906 | gfp_t gfp_flags) |
907 | { | |
1f91b4cc | 908 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 909 | struct dwc2_hsotg *hs = hs_ep->parent; |
5ad1d316 LM |
910 | unsigned long flags = 0; |
911 | int ret = 0; | |
912 | ||
913 | spin_lock_irqsave(&hs->lock, flags); | |
1f91b4cc | 914 | ret = dwc2_hsotg_ep_queue(ep, req, gfp_flags); |
5ad1d316 LM |
915 | spin_unlock_irqrestore(&hs->lock, flags); |
916 | ||
917 | return ret; | |
918 | } | |
919 | ||
1f91b4cc | 920 | static void dwc2_hsotg_ep_free_request(struct usb_ep *ep, |
5b7d70c6 BD |
921 | struct usb_request *req) |
922 | { | |
1f91b4cc | 923 | struct dwc2_hsotg_req *hs_req = our_req(req); |
5b7d70c6 BD |
924 | |
925 | kfree(hs_req); | |
926 | } | |
927 | ||
928 | /** | |
1f91b4cc | 929 | * dwc2_hsotg_complete_oursetup - setup completion callback |
5b7d70c6 BD |
930 | * @ep: The endpoint the request was on. |
931 | * @req: The request completed. | |
932 | * | |
933 | * Called on completion of any requests the driver itself | |
934 | * submitted that need cleaning up. | |
935 | */ | |
1f91b4cc | 936 | static void dwc2_hsotg_complete_oursetup(struct usb_ep *ep, |
5b7d70c6 BD |
937 | struct usb_request *req) |
938 | { | |
1f91b4cc | 939 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 940 | struct dwc2_hsotg *hsotg = hs_ep->parent; |
5b7d70c6 BD |
941 | |
942 | dev_dbg(hsotg->dev, "%s: ep %p, req %p\n", __func__, ep, req); | |
943 | ||
1f91b4cc | 944 | dwc2_hsotg_ep_free_request(ep, req); |
5b7d70c6 BD |
945 | } |
946 | ||
947 | /** | |
948 | * ep_from_windex - convert control wIndex value to endpoint | |
949 | * @hsotg: The driver state. | |
950 | * @windex: The control request wIndex field (in host order). | |
951 | * | |
952 | * Convert the given wIndex into a pointer to an driver endpoint | |
953 | * structure, or return NULL if it is not a valid endpoint. | |
8b9bc460 | 954 | */ |
1f91b4cc | 955 | static struct dwc2_hsotg_ep *ep_from_windex(struct dwc2_hsotg *hsotg, |
5b7d70c6 BD |
956 | u32 windex) |
957 | { | |
1f91b4cc | 958 | struct dwc2_hsotg_ep *ep; |
5b7d70c6 BD |
959 | int dir = (windex & USB_DIR_IN) ? 1 : 0; |
960 | int idx = windex & 0x7F; | |
961 | ||
962 | if (windex >= 0x100) | |
963 | return NULL; | |
964 | ||
b3f489b2 | 965 | if (idx > hsotg->num_of_eps) |
5b7d70c6 BD |
966 | return NULL; |
967 | ||
c6f5c050 MYK |
968 | ep = index_to_ep(hsotg, idx, dir); |
969 | ||
5b7d70c6 BD |
970 | if (idx && ep->dir_in != dir) |
971 | return NULL; | |
972 | ||
973 | return ep; | |
974 | } | |
975 | ||
9e14d0a5 | 976 | /** |
1f91b4cc | 977 | * dwc2_hsotg_set_test_mode - Enable usb Test Modes |
9e14d0a5 GH |
978 | * @hsotg: The driver state. |
979 | * @testmode: requested usb test mode | |
980 | * Enable usb Test Mode requested by the Host. | |
981 | */ | |
1f91b4cc | 982 | int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode) |
9e14d0a5 | 983 | { |
95c8bc36 | 984 | int dctl = dwc2_readl(hsotg->regs + DCTL); |
9e14d0a5 GH |
985 | |
986 | dctl &= ~DCTL_TSTCTL_MASK; | |
987 | switch (testmode) { | |
988 | case TEST_J: | |
989 | case TEST_K: | |
990 | case TEST_SE0_NAK: | |
991 | case TEST_PACKET: | |
992 | case TEST_FORCE_EN: | |
993 | dctl |= testmode << DCTL_TSTCTL_SHIFT; | |
994 | break; | |
995 | default: | |
996 | return -EINVAL; | |
997 | } | |
95c8bc36 | 998 | dwc2_writel(dctl, hsotg->regs + DCTL); |
9e14d0a5 GH |
999 | return 0; |
1000 | } | |
1001 | ||
5b7d70c6 | 1002 | /** |
1f91b4cc | 1003 | * dwc2_hsotg_send_reply - send reply to control request |
5b7d70c6 BD |
1004 | * @hsotg: The device state |
1005 | * @ep: Endpoint 0 | |
1006 | * @buff: Buffer for request | |
1007 | * @length: Length of reply. | |
1008 | * | |
1009 | * Create a request and queue it on the given endpoint. This is useful as | |
1010 | * an internal method of sending replies to certain control requests, etc. | |
1011 | */ | |
1f91b4cc FB |
1012 | static int dwc2_hsotg_send_reply(struct dwc2_hsotg *hsotg, |
1013 | struct dwc2_hsotg_ep *ep, | |
5b7d70c6 BD |
1014 | void *buff, |
1015 | int length) | |
1016 | { | |
1017 | struct usb_request *req; | |
1018 | int ret; | |
1019 | ||
1020 | dev_dbg(hsotg->dev, "%s: buff %p, len %d\n", __func__, buff, length); | |
1021 | ||
1f91b4cc | 1022 | req = dwc2_hsotg_ep_alloc_request(&ep->ep, GFP_ATOMIC); |
5b7d70c6 BD |
1023 | hsotg->ep0_reply = req; |
1024 | if (!req) { | |
1025 | dev_warn(hsotg->dev, "%s: cannot alloc req\n", __func__); | |
1026 | return -ENOMEM; | |
1027 | } | |
1028 | ||
1029 | req->buf = hsotg->ep0_buff; | |
1030 | req->length = length; | |
f71b5e25 MYK |
1031 | /* |
1032 | * zero flag is for sending zlp in DATA IN stage. It has no impact on | |
1033 | * STATUS stage. | |
1034 | */ | |
1035 | req->zero = 0; | |
1f91b4cc | 1036 | req->complete = dwc2_hsotg_complete_oursetup; |
5b7d70c6 BD |
1037 | |
1038 | if (length) | |
1039 | memcpy(req->buf, buff, length); | |
5b7d70c6 | 1040 | |
1f91b4cc | 1041 | ret = dwc2_hsotg_ep_queue(&ep->ep, req, GFP_ATOMIC); |
5b7d70c6 BD |
1042 | if (ret) { |
1043 | dev_warn(hsotg->dev, "%s: cannot queue req\n", __func__); | |
1044 | return ret; | |
1045 | } | |
1046 | ||
1047 | return 0; | |
1048 | } | |
1049 | ||
1050 | /** | |
1f91b4cc | 1051 | * dwc2_hsotg_process_req_status - process request GET_STATUS |
5b7d70c6 BD |
1052 | * @hsotg: The device state |
1053 | * @ctrl: USB control request | |
1054 | */ | |
1f91b4cc | 1055 | static int dwc2_hsotg_process_req_status(struct dwc2_hsotg *hsotg, |
5b7d70c6 BD |
1056 | struct usb_ctrlrequest *ctrl) |
1057 | { | |
1f91b4cc FB |
1058 | struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0]; |
1059 | struct dwc2_hsotg_ep *ep; | |
5b7d70c6 BD |
1060 | __le16 reply; |
1061 | int ret; | |
1062 | ||
1063 | dev_dbg(hsotg->dev, "%s: USB_REQ_GET_STATUS\n", __func__); | |
1064 | ||
1065 | if (!ep0->dir_in) { | |
1066 | dev_warn(hsotg->dev, "%s: direction out?\n", __func__); | |
1067 | return -EINVAL; | |
1068 | } | |
1069 | ||
1070 | switch (ctrl->bRequestType & USB_RECIP_MASK) { | |
1071 | case USB_RECIP_DEVICE: | |
1072 | reply = cpu_to_le16(0); /* bit 0 => self powered, | |
1073 | * bit 1 => remote wakeup */ | |
1074 | break; | |
1075 | ||
1076 | case USB_RECIP_INTERFACE: | |
1077 | /* currently, the data result should be zero */ | |
1078 | reply = cpu_to_le16(0); | |
1079 | break; | |
1080 | ||
1081 | case USB_RECIP_ENDPOINT: | |
1082 | ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex)); | |
1083 | if (!ep) | |
1084 | return -ENOENT; | |
1085 | ||
1086 | reply = cpu_to_le16(ep->halted ? 1 : 0); | |
1087 | break; | |
1088 | ||
1089 | default: | |
1090 | return 0; | |
1091 | } | |
1092 | ||
1093 | if (le16_to_cpu(ctrl->wLength) != 2) | |
1094 | return -EINVAL; | |
1095 | ||
1f91b4cc | 1096 | ret = dwc2_hsotg_send_reply(hsotg, ep0, &reply, 2); |
5b7d70c6 BD |
1097 | if (ret) { |
1098 | dev_err(hsotg->dev, "%s: failed to send reply\n", __func__); | |
1099 | return ret; | |
1100 | } | |
1101 | ||
1102 | return 1; | |
1103 | } | |
1104 | ||
51da43b5 | 1105 | static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now); |
5b7d70c6 | 1106 | |
9c39ddc6 AT |
1107 | /** |
1108 | * get_ep_head - return the first request on the endpoint | |
1109 | * @hs_ep: The controller endpoint to get | |
1110 | * | |
1111 | * Get the first request on the endpoint. | |
1112 | */ | |
1f91b4cc | 1113 | static struct dwc2_hsotg_req *get_ep_head(struct dwc2_hsotg_ep *hs_ep) |
9c39ddc6 | 1114 | { |
ffc4b406 MY |
1115 | return list_first_entry_or_null(&hs_ep->queue, struct dwc2_hsotg_req, |
1116 | queue); | |
9c39ddc6 AT |
1117 | } |
1118 | ||
41cc4cd2 VM |
1119 | /** |
1120 | * dwc2_gadget_start_next_request - Starts next request from ep queue | |
1121 | * @hs_ep: Endpoint structure | |
1122 | * | |
1123 | * If queue is empty and EP is ISOC-OUT - unmasks OUTTKNEPDIS which is masked | |
1124 | * in its handler. Hence we need to unmask it here to be able to do | |
1125 | * resynchronization. | |
1126 | */ | |
1127 | static void dwc2_gadget_start_next_request(struct dwc2_hsotg_ep *hs_ep) | |
1128 | { | |
1129 | u32 mask; | |
1130 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
1131 | int dir_in = hs_ep->dir_in; | |
1132 | struct dwc2_hsotg_req *hs_req; | |
1133 | u32 epmsk_reg = dir_in ? DIEPMSK : DOEPMSK; | |
1134 | ||
1135 | if (!list_empty(&hs_ep->queue)) { | |
1136 | hs_req = get_ep_head(hs_ep); | |
1137 | dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, false); | |
1138 | return; | |
1139 | } | |
1140 | if (!hs_ep->isochronous) | |
1141 | return; | |
1142 | ||
1143 | if (dir_in) { | |
1144 | dev_dbg(hsotg->dev, "%s: No more ISOC-IN requests\n", | |
1145 | __func__); | |
1146 | } else { | |
1147 | dev_dbg(hsotg->dev, "%s: No more ISOC-OUT requests\n", | |
1148 | __func__); | |
1149 | mask = dwc2_readl(hsotg->regs + epmsk_reg); | |
1150 | mask |= DOEPMSK_OUTTKNEPDISMSK; | |
1151 | dwc2_writel(mask, hsotg->regs + epmsk_reg); | |
1152 | } | |
1153 | } | |
1154 | ||
5b7d70c6 | 1155 | /** |
1f91b4cc | 1156 | * dwc2_hsotg_process_req_feature - process request {SET,CLEAR}_FEATURE |
5b7d70c6 BD |
1157 | * @hsotg: The device state |
1158 | * @ctrl: USB control request | |
1159 | */ | |
1f91b4cc | 1160 | static int dwc2_hsotg_process_req_feature(struct dwc2_hsotg *hsotg, |
5b7d70c6 BD |
1161 | struct usb_ctrlrequest *ctrl) |
1162 | { | |
1f91b4cc FB |
1163 | struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0]; |
1164 | struct dwc2_hsotg_req *hs_req; | |
5b7d70c6 | 1165 | bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE); |
1f91b4cc | 1166 | struct dwc2_hsotg_ep *ep; |
26ab3d0c | 1167 | int ret; |
bd9ef7bf | 1168 | bool halted; |
9e14d0a5 GH |
1169 | u32 recip; |
1170 | u32 wValue; | |
1171 | u32 wIndex; | |
5b7d70c6 BD |
1172 | |
1173 | dev_dbg(hsotg->dev, "%s: %s_FEATURE\n", | |
1174 | __func__, set ? "SET" : "CLEAR"); | |
1175 | ||
9e14d0a5 GH |
1176 | wValue = le16_to_cpu(ctrl->wValue); |
1177 | wIndex = le16_to_cpu(ctrl->wIndex); | |
1178 | recip = ctrl->bRequestType & USB_RECIP_MASK; | |
1179 | ||
1180 | switch (recip) { | |
1181 | case USB_RECIP_DEVICE: | |
1182 | switch (wValue) { | |
1183 | case USB_DEVICE_TEST_MODE: | |
1184 | if ((wIndex & 0xff) != 0) | |
1185 | return -EINVAL; | |
1186 | if (!set) | |
1187 | return -EINVAL; | |
1188 | ||
1189 | hsotg->test_mode = wIndex >> 8; | |
1f91b4cc | 1190 | ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0); |
9e14d0a5 GH |
1191 | if (ret) { |
1192 | dev_err(hsotg->dev, | |
1193 | "%s: failed to send reply\n", __func__); | |
1194 | return ret; | |
1195 | } | |
1196 | break; | |
1197 | default: | |
1198 | return -ENOENT; | |
1199 | } | |
1200 | break; | |
1201 | ||
1202 | case USB_RECIP_ENDPOINT: | |
1203 | ep = ep_from_windex(hsotg, wIndex); | |
5b7d70c6 BD |
1204 | if (!ep) { |
1205 | dev_dbg(hsotg->dev, "%s: no endpoint for 0x%04x\n", | |
9e14d0a5 | 1206 | __func__, wIndex); |
5b7d70c6 BD |
1207 | return -ENOENT; |
1208 | } | |
1209 | ||
9e14d0a5 | 1210 | switch (wValue) { |
5b7d70c6 | 1211 | case USB_ENDPOINT_HALT: |
bd9ef7bf RB |
1212 | halted = ep->halted; |
1213 | ||
51da43b5 | 1214 | dwc2_hsotg_ep_sethalt(&ep->ep, set, true); |
26ab3d0c | 1215 | |
1f91b4cc | 1216 | ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0); |
26ab3d0c AT |
1217 | if (ret) { |
1218 | dev_err(hsotg->dev, | |
1219 | "%s: failed to send reply\n", __func__); | |
1220 | return ret; | |
1221 | } | |
9c39ddc6 | 1222 | |
bd9ef7bf RB |
1223 | /* |
1224 | * we have to complete all requests for ep if it was | |
1225 | * halted, and the halt was cleared by CLEAR_FEATURE | |
1226 | */ | |
1227 | ||
1228 | if (!set && halted) { | |
9c39ddc6 AT |
1229 | /* |
1230 | * If we have request in progress, | |
1231 | * then complete it | |
1232 | */ | |
1233 | if (ep->req) { | |
1234 | hs_req = ep->req; | |
1235 | ep->req = NULL; | |
1236 | list_del_init(&hs_req->queue); | |
c00dd4a6 GH |
1237 | if (hs_req->req.complete) { |
1238 | spin_unlock(&hsotg->lock); | |
1239 | usb_gadget_giveback_request( | |
1240 | &ep->ep, &hs_req->req); | |
1241 | spin_lock(&hsotg->lock); | |
1242 | } | |
9c39ddc6 AT |
1243 | } |
1244 | ||
1245 | /* If we have pending request, then start it */ | |
c00dd4a6 | 1246 | if (!ep->req) { |
41cc4cd2 | 1247 | dwc2_gadget_start_next_request(ep); |
9c39ddc6 AT |
1248 | } |
1249 | } | |
1250 | ||
5b7d70c6 BD |
1251 | break; |
1252 | ||
1253 | default: | |
1254 | return -ENOENT; | |
1255 | } | |
9e14d0a5 GH |
1256 | break; |
1257 | default: | |
1258 | return -ENOENT; | |
1259 | } | |
5b7d70c6 BD |
1260 | return 1; |
1261 | } | |
1262 | ||
1f91b4cc | 1263 | static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg); |
ab93e014 | 1264 | |
c9f721b2 | 1265 | /** |
1f91b4cc | 1266 | * dwc2_hsotg_stall_ep0 - stall ep0 |
c9f721b2 RB |
1267 | * @hsotg: The device state |
1268 | * | |
1269 | * Set stall for ep0 as response for setup request. | |
1270 | */ | |
1f91b4cc | 1271 | static void dwc2_hsotg_stall_ep0(struct dwc2_hsotg *hsotg) |
e9ebe7c3 | 1272 | { |
1f91b4cc | 1273 | struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0]; |
c9f721b2 RB |
1274 | u32 reg; |
1275 | u32 ctrl; | |
1276 | ||
1277 | dev_dbg(hsotg->dev, "ep0 stall (dir=%d)\n", ep0->dir_in); | |
1278 | reg = (ep0->dir_in) ? DIEPCTL0 : DOEPCTL0; | |
1279 | ||
1280 | /* | |
1281 | * DxEPCTL_Stall will be cleared by EP once it has | |
1282 | * taken effect, so no need to clear later. | |
1283 | */ | |
1284 | ||
95c8bc36 | 1285 | ctrl = dwc2_readl(hsotg->regs + reg); |
47a1685f DN |
1286 | ctrl |= DXEPCTL_STALL; |
1287 | ctrl |= DXEPCTL_CNAK; | |
95c8bc36 | 1288 | dwc2_writel(ctrl, hsotg->regs + reg); |
c9f721b2 RB |
1289 | |
1290 | dev_dbg(hsotg->dev, | |
47a1685f | 1291 | "written DXEPCTL=0x%08x to %08x (DXEPCTL=0x%08x)\n", |
95c8bc36 | 1292 | ctrl, reg, dwc2_readl(hsotg->regs + reg)); |
c9f721b2 RB |
1293 | |
1294 | /* | |
1295 | * complete won't be called, so we enqueue | |
1296 | * setup request here | |
1297 | */ | |
1f91b4cc | 1298 | dwc2_hsotg_enqueue_setup(hsotg); |
c9f721b2 RB |
1299 | } |
1300 | ||
5b7d70c6 | 1301 | /** |
1f91b4cc | 1302 | * dwc2_hsotg_process_control - process a control request |
5b7d70c6 BD |
1303 | * @hsotg: The device state |
1304 | * @ctrl: The control request received | |
1305 | * | |
1306 | * The controller has received the SETUP phase of a control request, and | |
1307 | * needs to work out what to do next (and whether to pass it on to the | |
1308 | * gadget driver). | |
1309 | */ | |
1f91b4cc | 1310 | static void dwc2_hsotg_process_control(struct dwc2_hsotg *hsotg, |
5b7d70c6 BD |
1311 | struct usb_ctrlrequest *ctrl) |
1312 | { | |
1f91b4cc | 1313 | struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0]; |
5b7d70c6 BD |
1314 | int ret = 0; |
1315 | u32 dcfg; | |
1316 | ||
e525e743 MYK |
1317 | dev_dbg(hsotg->dev, |
1318 | "ctrl Type=%02x, Req=%02x, V=%04x, I=%04x, L=%04x\n", | |
1319 | ctrl->bRequestType, ctrl->bRequest, ctrl->wValue, | |
1320 | ctrl->wIndex, ctrl->wLength); | |
5b7d70c6 | 1321 | |
fe0b94ab MYK |
1322 | if (ctrl->wLength == 0) { |
1323 | ep0->dir_in = 1; | |
1324 | hsotg->ep0_state = DWC2_EP0_STATUS_IN; | |
1325 | } else if (ctrl->bRequestType & USB_DIR_IN) { | |
5b7d70c6 | 1326 | ep0->dir_in = 1; |
fe0b94ab MYK |
1327 | hsotg->ep0_state = DWC2_EP0_DATA_IN; |
1328 | } else { | |
1329 | ep0->dir_in = 0; | |
1330 | hsotg->ep0_state = DWC2_EP0_DATA_OUT; | |
1331 | } | |
5b7d70c6 BD |
1332 | |
1333 | if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) { | |
1334 | switch (ctrl->bRequest) { | |
1335 | case USB_REQ_SET_ADDRESS: | |
6d713c15 | 1336 | hsotg->connected = 1; |
95c8bc36 | 1337 | dcfg = dwc2_readl(hsotg->regs + DCFG); |
47a1685f | 1338 | dcfg &= ~DCFG_DEVADDR_MASK; |
d5dbd3f7 PZ |
1339 | dcfg |= (le16_to_cpu(ctrl->wValue) << |
1340 | DCFG_DEVADDR_SHIFT) & DCFG_DEVADDR_MASK; | |
95c8bc36 | 1341 | dwc2_writel(dcfg, hsotg->regs + DCFG); |
5b7d70c6 BD |
1342 | |
1343 | dev_info(hsotg->dev, "new address %d\n", ctrl->wValue); | |
1344 | ||
1f91b4cc | 1345 | ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0); |
5b7d70c6 BD |
1346 | return; |
1347 | ||
1348 | case USB_REQ_GET_STATUS: | |
1f91b4cc | 1349 | ret = dwc2_hsotg_process_req_status(hsotg, ctrl); |
5b7d70c6 BD |
1350 | break; |
1351 | ||
1352 | case USB_REQ_CLEAR_FEATURE: | |
1353 | case USB_REQ_SET_FEATURE: | |
1f91b4cc | 1354 | ret = dwc2_hsotg_process_req_feature(hsotg, ctrl); |
5b7d70c6 BD |
1355 | break; |
1356 | } | |
1357 | } | |
1358 | ||
1359 | /* as a fallback, try delivering it to the driver to deal with */ | |
1360 | ||
1361 | if (ret == 0 && hsotg->driver) { | |
93f599f2 | 1362 | spin_unlock(&hsotg->lock); |
5b7d70c6 | 1363 | ret = hsotg->driver->setup(&hsotg->gadget, ctrl); |
93f599f2 | 1364 | spin_lock(&hsotg->lock); |
5b7d70c6 BD |
1365 | if (ret < 0) |
1366 | dev_dbg(hsotg->dev, "driver->setup() ret %d\n", ret); | |
1367 | } | |
1368 | ||
8b9bc460 LM |
1369 | /* |
1370 | * the request is either unhandlable, or is not formatted correctly | |
5b7d70c6 BD |
1371 | * so respond with a STALL for the status stage to indicate failure. |
1372 | */ | |
1373 | ||
c9f721b2 | 1374 | if (ret < 0) |
1f91b4cc | 1375 | dwc2_hsotg_stall_ep0(hsotg); |
5b7d70c6 BD |
1376 | } |
1377 | ||
5b7d70c6 | 1378 | /** |
1f91b4cc | 1379 | * dwc2_hsotg_complete_setup - completion of a setup transfer |
5b7d70c6 BD |
1380 | * @ep: The endpoint the request was on. |
1381 | * @req: The request completed. | |
1382 | * | |
1383 | * Called on completion of any requests the driver itself submitted for | |
1384 | * EP0 setup packets | |
1385 | */ | |
1f91b4cc | 1386 | static void dwc2_hsotg_complete_setup(struct usb_ep *ep, |
5b7d70c6 BD |
1387 | struct usb_request *req) |
1388 | { | |
1f91b4cc | 1389 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 1390 | struct dwc2_hsotg *hsotg = hs_ep->parent; |
5b7d70c6 BD |
1391 | |
1392 | if (req->status < 0) { | |
1393 | dev_dbg(hsotg->dev, "%s: failed %d\n", __func__, req->status); | |
1394 | return; | |
1395 | } | |
1396 | ||
93f599f2 | 1397 | spin_lock(&hsotg->lock); |
5b7d70c6 | 1398 | if (req->actual == 0) |
1f91b4cc | 1399 | dwc2_hsotg_enqueue_setup(hsotg); |
5b7d70c6 | 1400 | else |
1f91b4cc | 1401 | dwc2_hsotg_process_control(hsotg, req->buf); |
93f599f2 | 1402 | spin_unlock(&hsotg->lock); |
5b7d70c6 BD |
1403 | } |
1404 | ||
1405 | /** | |
1f91b4cc | 1406 | * dwc2_hsotg_enqueue_setup - start a request for EP0 packets |
5b7d70c6 BD |
1407 | * @hsotg: The device state. |
1408 | * | |
1409 | * Enqueue a request on EP0 if necessary to received any SETUP packets | |
1410 | * received from the host. | |
1411 | */ | |
1f91b4cc | 1412 | static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg) |
5b7d70c6 BD |
1413 | { |
1414 | struct usb_request *req = hsotg->ctrl_req; | |
1f91b4cc | 1415 | struct dwc2_hsotg_req *hs_req = our_req(req); |
5b7d70c6 BD |
1416 | int ret; |
1417 | ||
1418 | dev_dbg(hsotg->dev, "%s: queueing setup request\n", __func__); | |
1419 | ||
1420 | req->zero = 0; | |
1421 | req->length = 8; | |
1422 | req->buf = hsotg->ctrl_buff; | |
1f91b4cc | 1423 | req->complete = dwc2_hsotg_complete_setup; |
5b7d70c6 BD |
1424 | |
1425 | if (!list_empty(&hs_req->queue)) { | |
1426 | dev_dbg(hsotg->dev, "%s already queued???\n", __func__); | |
1427 | return; | |
1428 | } | |
1429 | ||
c6f5c050 | 1430 | hsotg->eps_out[0]->dir_in = 0; |
8a20fa45 | 1431 | hsotg->eps_out[0]->send_zlp = 0; |
fe0b94ab | 1432 | hsotg->ep0_state = DWC2_EP0_SETUP; |
5b7d70c6 | 1433 | |
1f91b4cc | 1434 | ret = dwc2_hsotg_ep_queue(&hsotg->eps_out[0]->ep, req, GFP_ATOMIC); |
5b7d70c6 BD |
1435 | if (ret < 0) { |
1436 | dev_err(hsotg->dev, "%s: failed queue (%d)\n", __func__, ret); | |
8b9bc460 LM |
1437 | /* |
1438 | * Don't think there's much we can do other than watch the | |
1439 | * driver fail. | |
1440 | */ | |
5b7d70c6 BD |
1441 | } |
1442 | } | |
1443 | ||
1f91b4cc FB |
1444 | static void dwc2_hsotg_program_zlp(struct dwc2_hsotg *hsotg, |
1445 | struct dwc2_hsotg_ep *hs_ep) | |
fe0b94ab MYK |
1446 | { |
1447 | u32 ctrl; | |
1448 | u8 index = hs_ep->index; | |
1449 | u32 epctl_reg = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index); | |
1450 | u32 epsiz_reg = hs_ep->dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index); | |
1451 | ||
ccb34a91 MYK |
1452 | if (hs_ep->dir_in) |
1453 | dev_dbg(hsotg->dev, "Sending zero-length packet on ep%d\n", | |
1454 | index); | |
1455 | else | |
1456 | dev_dbg(hsotg->dev, "Receiving zero-length packet on ep%d\n", | |
1457 | index); | |
fe0b94ab | 1458 | |
95c8bc36 AS |
1459 | dwc2_writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) | |
1460 | DXEPTSIZ_XFERSIZE(0), hsotg->regs + | |
1461 | epsiz_reg); | |
fe0b94ab | 1462 | |
95c8bc36 | 1463 | ctrl = dwc2_readl(hsotg->regs + epctl_reg); |
fe0b94ab MYK |
1464 | ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */ |
1465 | ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */ | |
1466 | ctrl |= DXEPCTL_USBACTEP; | |
95c8bc36 | 1467 | dwc2_writel(ctrl, hsotg->regs + epctl_reg); |
fe0b94ab MYK |
1468 | } |
1469 | ||
5b7d70c6 | 1470 | /** |
1f91b4cc | 1471 | * dwc2_hsotg_complete_request - complete a request given to us |
5b7d70c6 BD |
1472 | * @hsotg: The device state. |
1473 | * @hs_ep: The endpoint the request was on. | |
1474 | * @hs_req: The request to complete. | |
1475 | * @result: The result code (0 => Ok, otherwise errno) | |
1476 | * | |
1477 | * The given request has finished, so call the necessary completion | |
1478 | * if it has one and then look to see if we can start a new request | |
1479 | * on the endpoint. | |
1480 | * | |
1481 | * Note, expects the ep to already be locked as appropriate. | |
8b9bc460 | 1482 | */ |
1f91b4cc FB |
1483 | static void dwc2_hsotg_complete_request(struct dwc2_hsotg *hsotg, |
1484 | struct dwc2_hsotg_ep *hs_ep, | |
1485 | struct dwc2_hsotg_req *hs_req, | |
5b7d70c6 BD |
1486 | int result) |
1487 | { | |
5b7d70c6 BD |
1488 | |
1489 | if (!hs_req) { | |
1490 | dev_dbg(hsotg->dev, "%s: nothing to complete?\n", __func__); | |
1491 | return; | |
1492 | } | |
1493 | ||
1494 | dev_dbg(hsotg->dev, "complete: ep %p %s, req %p, %d => %p\n", | |
1495 | hs_ep, hs_ep->ep.name, hs_req, result, hs_req->req.complete); | |
1496 | ||
8b9bc460 LM |
1497 | /* |
1498 | * only replace the status if we've not already set an error | |
1499 | * from a previous transaction | |
1500 | */ | |
5b7d70c6 BD |
1501 | |
1502 | if (hs_req->req.status == -EINPROGRESS) | |
1503 | hs_req->req.status = result; | |
1504 | ||
44583fec YL |
1505 | if (using_dma(hsotg)) |
1506 | dwc2_hsotg_unmap_dma(hsotg, hs_ep, hs_req); | |
1507 | ||
1f91b4cc | 1508 | dwc2_hsotg_handle_unaligned_buf_complete(hsotg, hs_ep, hs_req); |
7d24c1b5 | 1509 | |
5b7d70c6 BD |
1510 | hs_ep->req = NULL; |
1511 | list_del_init(&hs_req->queue); | |
1512 | ||
8b9bc460 LM |
1513 | /* |
1514 | * call the complete request with the locks off, just in case the | |
1515 | * request tries to queue more work for this endpoint. | |
1516 | */ | |
5b7d70c6 BD |
1517 | |
1518 | if (hs_req->req.complete) { | |
22258f49 | 1519 | spin_unlock(&hsotg->lock); |
304f7e5e | 1520 | usb_gadget_giveback_request(&hs_ep->ep, &hs_req->req); |
22258f49 | 1521 | spin_lock(&hsotg->lock); |
5b7d70c6 BD |
1522 | } |
1523 | ||
8b9bc460 LM |
1524 | /* |
1525 | * Look to see if there is anything else to do. Note, the completion | |
5b7d70c6 | 1526 | * of the previous request may have caused a new request to be started |
8b9bc460 LM |
1527 | * so be careful when doing this. |
1528 | */ | |
5b7d70c6 BD |
1529 | |
1530 | if (!hs_ep->req && result >= 0) { | |
41cc4cd2 | 1531 | dwc2_gadget_start_next_request(hs_ep); |
5b7d70c6 BD |
1532 | } |
1533 | } | |
1534 | ||
5b7d70c6 | 1535 | /** |
1f91b4cc | 1536 | * dwc2_hsotg_rx_data - receive data from the FIFO for an endpoint |
5b7d70c6 BD |
1537 | * @hsotg: The device state. |
1538 | * @ep_idx: The endpoint index for the data | |
1539 | * @size: The size of data in the fifo, in bytes | |
1540 | * | |
1541 | * The FIFO status shows there is data to read from the FIFO for a given | |
1542 | * endpoint, so sort out whether we need to read the data into a request | |
1543 | * that has been made for that endpoint. | |
1544 | */ | |
1f91b4cc | 1545 | static void dwc2_hsotg_rx_data(struct dwc2_hsotg *hsotg, int ep_idx, int size) |
5b7d70c6 | 1546 | { |
1f91b4cc FB |
1547 | struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[ep_idx]; |
1548 | struct dwc2_hsotg_req *hs_req = hs_ep->req; | |
94cb8fd6 | 1549 | void __iomem *fifo = hsotg->regs + EPFIFO(ep_idx); |
5b7d70c6 BD |
1550 | int to_read; |
1551 | int max_req; | |
1552 | int read_ptr; | |
1553 | ||
22258f49 | 1554 | |
5b7d70c6 | 1555 | if (!hs_req) { |
95c8bc36 | 1556 | u32 epctl = dwc2_readl(hsotg->regs + DOEPCTL(ep_idx)); |
5b7d70c6 BD |
1557 | int ptr; |
1558 | ||
6b448af4 | 1559 | dev_dbg(hsotg->dev, |
47a1685f | 1560 | "%s: FIFO %d bytes on ep%d but no req (DXEPCTl=0x%08x)\n", |
5b7d70c6 BD |
1561 | __func__, size, ep_idx, epctl); |
1562 | ||
1563 | /* dump the data from the FIFO, we've nothing we can do */ | |
1564 | for (ptr = 0; ptr < size; ptr += 4) | |
95c8bc36 | 1565 | (void)dwc2_readl(fifo); |
5b7d70c6 BD |
1566 | |
1567 | return; | |
1568 | } | |
1569 | ||
5b7d70c6 BD |
1570 | to_read = size; |
1571 | read_ptr = hs_req->req.actual; | |
1572 | max_req = hs_req->req.length - read_ptr; | |
1573 | ||
a33e7136 BD |
1574 | dev_dbg(hsotg->dev, "%s: read %d/%d, done %d/%d\n", |
1575 | __func__, to_read, max_req, read_ptr, hs_req->req.length); | |
1576 | ||
5b7d70c6 | 1577 | if (to_read > max_req) { |
8b9bc460 LM |
1578 | /* |
1579 | * more data appeared than we where willing | |
5b7d70c6 BD |
1580 | * to deal with in this request. |
1581 | */ | |
1582 | ||
1583 | /* currently we don't deal this */ | |
1584 | WARN_ON_ONCE(1); | |
1585 | } | |
1586 | ||
5b7d70c6 BD |
1587 | hs_ep->total_data += to_read; |
1588 | hs_req->req.actual += to_read; | |
1589 | to_read = DIV_ROUND_UP(to_read, 4); | |
1590 | ||
8b9bc460 LM |
1591 | /* |
1592 | * note, we might over-write the buffer end by 3 bytes depending on | |
1593 | * alignment of the data. | |
1594 | */ | |
1a7ed5be | 1595 | ioread32_rep(fifo, hs_req->req.buf + read_ptr, to_read); |
5b7d70c6 BD |
1596 | } |
1597 | ||
1598 | /** | |
1f91b4cc | 1599 | * dwc2_hsotg_ep0_zlp - send/receive zero-length packet on control endpoint |
5b7d70c6 | 1600 | * @hsotg: The device instance |
fe0b94ab | 1601 | * @dir_in: If IN zlp |
5b7d70c6 BD |
1602 | * |
1603 | * Generate a zero-length IN packet request for terminating a SETUP | |
1604 | * transaction. | |
1605 | * | |
1606 | * Note, since we don't write any data to the TxFIFO, then it is | |
25985edc | 1607 | * currently believed that we do not need to wait for any space in |
5b7d70c6 BD |
1608 | * the TxFIFO. |
1609 | */ | |
1f91b4cc | 1610 | static void dwc2_hsotg_ep0_zlp(struct dwc2_hsotg *hsotg, bool dir_in) |
5b7d70c6 | 1611 | { |
c6f5c050 | 1612 | /* eps_out[0] is used in both directions */ |
fe0b94ab MYK |
1613 | hsotg->eps_out[0]->dir_in = dir_in; |
1614 | hsotg->ep0_state = dir_in ? DWC2_EP0_STATUS_IN : DWC2_EP0_STATUS_OUT; | |
5b7d70c6 | 1615 | |
1f91b4cc | 1616 | dwc2_hsotg_program_zlp(hsotg, hsotg->eps_out[0]); |
5b7d70c6 BD |
1617 | } |
1618 | ||
ec1f9d9f RB |
1619 | static void dwc2_hsotg_change_ep_iso_parity(struct dwc2_hsotg *hsotg, |
1620 | u32 epctl_reg) | |
1621 | { | |
1622 | u32 ctrl; | |
1623 | ||
1624 | ctrl = dwc2_readl(hsotg->regs + epctl_reg); | |
1625 | if (ctrl & DXEPCTL_EOFRNUM) | |
1626 | ctrl |= DXEPCTL_SETEVENFR; | |
1627 | else | |
1628 | ctrl |= DXEPCTL_SETODDFR; | |
1629 | dwc2_writel(ctrl, hsotg->regs + epctl_reg); | |
1630 | } | |
1631 | ||
5b7d70c6 | 1632 | /** |
1f91b4cc | 1633 | * dwc2_hsotg_handle_outdone - handle receiving OutDone/SetupDone from RXFIFO |
5b7d70c6 BD |
1634 | * @hsotg: The device instance |
1635 | * @epnum: The endpoint received from | |
5b7d70c6 BD |
1636 | * |
1637 | * The RXFIFO has delivered an OutDone event, which means that the data | |
1638 | * transfer for an OUT endpoint has been completed, either by a short | |
1639 | * packet or by the finish of a transfer. | |
8b9bc460 | 1640 | */ |
1f91b4cc | 1641 | static void dwc2_hsotg_handle_outdone(struct dwc2_hsotg *hsotg, int epnum) |
5b7d70c6 | 1642 | { |
95c8bc36 | 1643 | u32 epsize = dwc2_readl(hsotg->regs + DOEPTSIZ(epnum)); |
1f91b4cc FB |
1644 | struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[epnum]; |
1645 | struct dwc2_hsotg_req *hs_req = hs_ep->req; | |
5b7d70c6 | 1646 | struct usb_request *req = &hs_req->req; |
47a1685f | 1647 | unsigned size_left = DXEPTSIZ_XFERSIZE_GET(epsize); |
5b7d70c6 BD |
1648 | int result = 0; |
1649 | ||
1650 | if (!hs_req) { | |
1651 | dev_dbg(hsotg->dev, "%s: no request active\n", __func__); | |
1652 | return; | |
1653 | } | |
1654 | ||
fe0b94ab MYK |
1655 | if (epnum == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_OUT) { |
1656 | dev_dbg(hsotg->dev, "zlp packet received\n"); | |
1f91b4cc FB |
1657 | dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0); |
1658 | dwc2_hsotg_enqueue_setup(hsotg); | |
fe0b94ab MYK |
1659 | return; |
1660 | } | |
1661 | ||
5b7d70c6 | 1662 | if (using_dma(hsotg)) { |
5b7d70c6 | 1663 | unsigned size_done; |
5b7d70c6 | 1664 | |
8b9bc460 LM |
1665 | /* |
1666 | * Calculate the size of the transfer by checking how much | |
5b7d70c6 BD |
1667 | * is left in the endpoint size register and then working it |
1668 | * out from the amount we loaded for the transfer. | |
1669 | * | |
1670 | * We need to do this as DMA pointers are always 32bit aligned | |
1671 | * so may overshoot/undershoot the transfer. | |
1672 | */ | |
1673 | ||
5b7d70c6 BD |
1674 | size_done = hs_ep->size_loaded - size_left; |
1675 | size_done += hs_ep->last_load; | |
1676 | ||
1677 | req->actual = size_done; | |
1678 | } | |
1679 | ||
a33e7136 BD |
1680 | /* if there is more request to do, schedule new transfer */ |
1681 | if (req->actual < req->length && size_left == 0) { | |
1f91b4cc | 1682 | dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true); |
a33e7136 BD |
1683 | return; |
1684 | } | |
1685 | ||
5b7d70c6 BD |
1686 | if (req->actual < req->length && req->short_not_ok) { |
1687 | dev_dbg(hsotg->dev, "%s: got %d/%d (short not ok) => error\n", | |
1688 | __func__, req->actual, req->length); | |
1689 | ||
8b9bc460 LM |
1690 | /* |
1691 | * todo - what should we return here? there's no one else | |
1692 | * even bothering to check the status. | |
1693 | */ | |
5b7d70c6 BD |
1694 | } |
1695 | ||
fe0b94ab MYK |
1696 | if (epnum == 0 && hsotg->ep0_state == DWC2_EP0_DATA_OUT) { |
1697 | /* Move to STATUS IN */ | |
1f91b4cc | 1698 | dwc2_hsotg_ep0_zlp(hsotg, true); |
fe0b94ab | 1699 | return; |
5b7d70c6 BD |
1700 | } |
1701 | ||
ec1f9d9f RB |
1702 | /* |
1703 | * Slave mode OUT transfers do not go through XferComplete so | |
1704 | * adjust the ISOC parity here. | |
1705 | */ | |
1706 | if (!using_dma(hsotg)) { | |
ec1f9d9f RB |
1707 | if (hs_ep->isochronous && hs_ep->interval == 1) |
1708 | dwc2_hsotg_change_ep_iso_parity(hsotg, DOEPCTL(epnum)); | |
837e9f00 VM |
1709 | else if (hs_ep->isochronous && hs_ep->interval > 1) |
1710 | dwc2_gadget_incr_frame_num(hs_ep); | |
ec1f9d9f RB |
1711 | } |
1712 | ||
1f91b4cc | 1713 | dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, result); |
5b7d70c6 BD |
1714 | } |
1715 | ||
5b7d70c6 | 1716 | /** |
1f91b4cc | 1717 | * dwc2_hsotg_handle_rx - RX FIFO has data |
5b7d70c6 BD |
1718 | * @hsotg: The device instance |
1719 | * | |
1720 | * The IRQ handler has detected that the RX FIFO has some data in it | |
1721 | * that requires processing, so find out what is in there and do the | |
1722 | * appropriate read. | |
1723 | * | |
25985edc | 1724 | * The RXFIFO is a true FIFO, the packets coming out are still in packet |
5b7d70c6 BD |
1725 | * chunks, so if you have x packets received on an endpoint you'll get x |
1726 | * FIFO events delivered, each with a packet's worth of data in it. | |
1727 | * | |
1728 | * When using DMA, we should not be processing events from the RXFIFO | |
1729 | * as the actual data should be sent to the memory directly and we turn | |
1730 | * on the completion interrupts to get notifications of transfer completion. | |
1731 | */ | |
1f91b4cc | 1732 | static void dwc2_hsotg_handle_rx(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 1733 | { |
95c8bc36 | 1734 | u32 grxstsr = dwc2_readl(hsotg->regs + GRXSTSP); |
5b7d70c6 BD |
1735 | u32 epnum, status, size; |
1736 | ||
1737 | WARN_ON(using_dma(hsotg)); | |
1738 | ||
47a1685f DN |
1739 | epnum = grxstsr & GRXSTS_EPNUM_MASK; |
1740 | status = grxstsr & GRXSTS_PKTSTS_MASK; | |
5b7d70c6 | 1741 | |
47a1685f DN |
1742 | size = grxstsr & GRXSTS_BYTECNT_MASK; |
1743 | size >>= GRXSTS_BYTECNT_SHIFT; | |
5b7d70c6 | 1744 | |
d7c747c5 | 1745 | dev_dbg(hsotg->dev, "%s: GRXSTSP=0x%08x (%d@%d)\n", |
5b7d70c6 BD |
1746 | __func__, grxstsr, size, epnum); |
1747 | ||
47a1685f DN |
1748 | switch ((status & GRXSTS_PKTSTS_MASK) >> GRXSTS_PKTSTS_SHIFT) { |
1749 | case GRXSTS_PKTSTS_GLOBALOUTNAK: | |
1750 | dev_dbg(hsotg->dev, "GLOBALOUTNAK\n"); | |
5b7d70c6 BD |
1751 | break; |
1752 | ||
47a1685f | 1753 | case GRXSTS_PKTSTS_OUTDONE: |
5b7d70c6 | 1754 | dev_dbg(hsotg->dev, "OutDone (Frame=0x%08x)\n", |
1f91b4cc | 1755 | dwc2_hsotg_read_frameno(hsotg)); |
5b7d70c6 BD |
1756 | |
1757 | if (!using_dma(hsotg)) | |
1f91b4cc | 1758 | dwc2_hsotg_handle_outdone(hsotg, epnum); |
5b7d70c6 BD |
1759 | break; |
1760 | ||
47a1685f | 1761 | case GRXSTS_PKTSTS_SETUPDONE: |
5b7d70c6 BD |
1762 | dev_dbg(hsotg->dev, |
1763 | "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n", | |
1f91b4cc | 1764 | dwc2_hsotg_read_frameno(hsotg), |
95c8bc36 | 1765 | dwc2_readl(hsotg->regs + DOEPCTL(0))); |
fe0b94ab | 1766 | /* |
1f91b4cc | 1767 | * Call dwc2_hsotg_handle_outdone here if it was not called from |
fe0b94ab MYK |
1768 | * GRXSTS_PKTSTS_OUTDONE. That is, if the core didn't |
1769 | * generate GRXSTS_PKTSTS_OUTDONE for setup packet. | |
1770 | */ | |
1771 | if (hsotg->ep0_state == DWC2_EP0_SETUP) | |
1f91b4cc | 1772 | dwc2_hsotg_handle_outdone(hsotg, epnum); |
5b7d70c6 BD |
1773 | break; |
1774 | ||
47a1685f | 1775 | case GRXSTS_PKTSTS_OUTRX: |
1f91b4cc | 1776 | dwc2_hsotg_rx_data(hsotg, epnum, size); |
5b7d70c6 BD |
1777 | break; |
1778 | ||
47a1685f | 1779 | case GRXSTS_PKTSTS_SETUPRX: |
5b7d70c6 BD |
1780 | dev_dbg(hsotg->dev, |
1781 | "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n", | |
1f91b4cc | 1782 | dwc2_hsotg_read_frameno(hsotg), |
95c8bc36 | 1783 | dwc2_readl(hsotg->regs + DOEPCTL(0))); |
5b7d70c6 | 1784 | |
fe0b94ab MYK |
1785 | WARN_ON(hsotg->ep0_state != DWC2_EP0_SETUP); |
1786 | ||
1f91b4cc | 1787 | dwc2_hsotg_rx_data(hsotg, epnum, size); |
5b7d70c6 BD |
1788 | break; |
1789 | ||
1790 | default: | |
1791 | dev_warn(hsotg->dev, "%s: unknown status %08x\n", | |
1792 | __func__, grxstsr); | |
1793 | ||
1f91b4cc | 1794 | dwc2_hsotg_dump(hsotg); |
5b7d70c6 BD |
1795 | break; |
1796 | } | |
1797 | } | |
1798 | ||
1799 | /** | |
1f91b4cc | 1800 | * dwc2_hsotg_ep0_mps - turn max packet size into register setting |
5b7d70c6 | 1801 | * @mps: The maximum packet size in bytes. |
8b9bc460 | 1802 | */ |
1f91b4cc | 1803 | static u32 dwc2_hsotg_ep0_mps(unsigned int mps) |
5b7d70c6 BD |
1804 | { |
1805 | switch (mps) { | |
1806 | case 64: | |
94cb8fd6 | 1807 | return D0EPCTL_MPS_64; |
5b7d70c6 | 1808 | case 32: |
94cb8fd6 | 1809 | return D0EPCTL_MPS_32; |
5b7d70c6 | 1810 | case 16: |
94cb8fd6 | 1811 | return D0EPCTL_MPS_16; |
5b7d70c6 | 1812 | case 8: |
94cb8fd6 | 1813 | return D0EPCTL_MPS_8; |
5b7d70c6 BD |
1814 | } |
1815 | ||
1816 | /* bad max packet size, warn and return invalid result */ | |
1817 | WARN_ON(1); | |
1818 | return (u32)-1; | |
1819 | } | |
1820 | ||
1821 | /** | |
1f91b4cc | 1822 | * dwc2_hsotg_set_ep_maxpacket - set endpoint's max-packet field |
5b7d70c6 BD |
1823 | * @hsotg: The driver state. |
1824 | * @ep: The index number of the endpoint | |
1825 | * @mps: The maximum packet size in bytes | |
ee2c40de | 1826 | * @mc: The multicount value |
5b7d70c6 BD |
1827 | * |
1828 | * Configure the maximum packet size for the given endpoint, updating | |
1829 | * the hardware control registers to reflect this. | |
1830 | */ | |
1f91b4cc | 1831 | static void dwc2_hsotg_set_ep_maxpacket(struct dwc2_hsotg *hsotg, |
ee2c40de VM |
1832 | unsigned int ep, unsigned int mps, |
1833 | unsigned int mc, unsigned int dir_in) | |
5b7d70c6 | 1834 | { |
1f91b4cc | 1835 | struct dwc2_hsotg_ep *hs_ep; |
5b7d70c6 | 1836 | void __iomem *regs = hsotg->regs; |
5b7d70c6 BD |
1837 | u32 reg; |
1838 | ||
c6f5c050 MYK |
1839 | hs_ep = index_to_ep(hsotg, ep, dir_in); |
1840 | if (!hs_ep) | |
1841 | return; | |
1842 | ||
5b7d70c6 | 1843 | if (ep == 0) { |
ee2c40de VM |
1844 | u32 mps_bytes = mps; |
1845 | ||
5b7d70c6 | 1846 | /* EP0 is a special case */ |
ee2c40de VM |
1847 | mps = dwc2_hsotg_ep0_mps(mps_bytes); |
1848 | if (mps > 3) | |
5b7d70c6 | 1849 | goto bad_mps; |
ee2c40de | 1850 | hs_ep->ep.maxpacket = mps_bytes; |
4fca54aa | 1851 | hs_ep->mc = 1; |
5b7d70c6 | 1852 | } else { |
ee2c40de | 1853 | if (mps > 1024) |
5b7d70c6 | 1854 | goto bad_mps; |
ee2c40de VM |
1855 | hs_ep->mc = mc; |
1856 | if (mc > 3) | |
4fca54aa | 1857 | goto bad_mps; |
ee2c40de | 1858 | hs_ep->ep.maxpacket = mps; |
5b7d70c6 BD |
1859 | } |
1860 | ||
c6f5c050 | 1861 | if (dir_in) { |
95c8bc36 | 1862 | reg = dwc2_readl(regs + DIEPCTL(ep)); |
c6f5c050 | 1863 | reg &= ~DXEPCTL_MPS_MASK; |
ee2c40de | 1864 | reg |= mps; |
95c8bc36 | 1865 | dwc2_writel(reg, regs + DIEPCTL(ep)); |
c6f5c050 | 1866 | } else { |
95c8bc36 | 1867 | reg = dwc2_readl(regs + DOEPCTL(ep)); |
47a1685f | 1868 | reg &= ~DXEPCTL_MPS_MASK; |
ee2c40de | 1869 | reg |= mps; |
95c8bc36 | 1870 | dwc2_writel(reg, regs + DOEPCTL(ep)); |
659ad60c | 1871 | } |
5b7d70c6 BD |
1872 | |
1873 | return; | |
1874 | ||
1875 | bad_mps: | |
1876 | dev_err(hsotg->dev, "ep%d: bad mps of %d\n", ep, mps); | |
1877 | } | |
1878 | ||
9c39ddc6 | 1879 | /** |
1f91b4cc | 1880 | * dwc2_hsotg_txfifo_flush - flush Tx FIFO |
9c39ddc6 AT |
1881 | * @hsotg: The driver state |
1882 | * @idx: The index for the endpoint (0..15) | |
1883 | */ | |
1f91b4cc | 1884 | static void dwc2_hsotg_txfifo_flush(struct dwc2_hsotg *hsotg, unsigned int idx) |
9c39ddc6 AT |
1885 | { |
1886 | int timeout; | |
1887 | int val; | |
1888 | ||
95c8bc36 AS |
1889 | dwc2_writel(GRSTCTL_TXFNUM(idx) | GRSTCTL_TXFFLSH, |
1890 | hsotg->regs + GRSTCTL); | |
9c39ddc6 AT |
1891 | |
1892 | /* wait until the fifo is flushed */ | |
1893 | timeout = 100; | |
1894 | ||
1895 | while (1) { | |
95c8bc36 | 1896 | val = dwc2_readl(hsotg->regs + GRSTCTL); |
9c39ddc6 | 1897 | |
47a1685f | 1898 | if ((val & (GRSTCTL_TXFFLSH)) == 0) |
9c39ddc6 AT |
1899 | break; |
1900 | ||
1901 | if (--timeout == 0) { | |
1902 | dev_err(hsotg->dev, | |
1903 | "%s: timeout flushing fifo (GRSTCTL=%08x)\n", | |
1904 | __func__, val); | |
e0cbe595 | 1905 | break; |
9c39ddc6 AT |
1906 | } |
1907 | ||
1908 | udelay(1); | |
1909 | } | |
1910 | } | |
5b7d70c6 BD |
1911 | |
1912 | /** | |
1f91b4cc | 1913 | * dwc2_hsotg_trytx - check to see if anything needs transmitting |
5b7d70c6 BD |
1914 | * @hsotg: The driver state |
1915 | * @hs_ep: The driver endpoint to check. | |
1916 | * | |
1917 | * Check to see if there is a request that has data to send, and if so | |
1918 | * make an attempt to write data into the FIFO. | |
1919 | */ | |
1f91b4cc FB |
1920 | static int dwc2_hsotg_trytx(struct dwc2_hsotg *hsotg, |
1921 | struct dwc2_hsotg_ep *hs_ep) | |
5b7d70c6 | 1922 | { |
1f91b4cc | 1923 | struct dwc2_hsotg_req *hs_req = hs_ep->req; |
5b7d70c6 | 1924 | |
afcf4169 RB |
1925 | if (!hs_ep->dir_in || !hs_req) { |
1926 | /** | |
1927 | * if request is not enqueued, we disable interrupts | |
1928 | * for endpoints, excepting ep0 | |
1929 | */ | |
1930 | if (hs_ep->index != 0) | |
1f91b4cc | 1931 | dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, |
afcf4169 | 1932 | hs_ep->dir_in, 0); |
5b7d70c6 | 1933 | return 0; |
afcf4169 | 1934 | } |
5b7d70c6 BD |
1935 | |
1936 | if (hs_req->req.actual < hs_req->req.length) { | |
1937 | dev_dbg(hsotg->dev, "trying to write more for ep%d\n", | |
1938 | hs_ep->index); | |
1f91b4cc | 1939 | return dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req); |
5b7d70c6 BD |
1940 | } |
1941 | ||
1942 | return 0; | |
1943 | } | |
1944 | ||
1945 | /** | |
1f91b4cc | 1946 | * dwc2_hsotg_complete_in - complete IN transfer |
5b7d70c6 BD |
1947 | * @hsotg: The device state. |
1948 | * @hs_ep: The endpoint that has just completed. | |
1949 | * | |
1950 | * An IN transfer has been completed, update the transfer's state and then | |
1951 | * call the relevant completion routines. | |
1952 | */ | |
1f91b4cc FB |
1953 | static void dwc2_hsotg_complete_in(struct dwc2_hsotg *hsotg, |
1954 | struct dwc2_hsotg_ep *hs_ep) | |
5b7d70c6 | 1955 | { |
1f91b4cc | 1956 | struct dwc2_hsotg_req *hs_req = hs_ep->req; |
95c8bc36 | 1957 | u32 epsize = dwc2_readl(hsotg->regs + DIEPTSIZ(hs_ep->index)); |
5b7d70c6 BD |
1958 | int size_left, size_done; |
1959 | ||
1960 | if (!hs_req) { | |
1961 | dev_dbg(hsotg->dev, "XferCompl but no req\n"); | |
1962 | return; | |
1963 | } | |
1964 | ||
d3ca0259 | 1965 | /* Finish ZLP handling for IN EP0 transactions */ |
fe0b94ab MYK |
1966 | if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_IN) { |
1967 | dev_dbg(hsotg->dev, "zlp packet sent\n"); | |
1f91b4cc | 1968 | dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0); |
9e14d0a5 GH |
1969 | if (hsotg->test_mode) { |
1970 | int ret; | |
1971 | ||
1f91b4cc | 1972 | ret = dwc2_hsotg_set_test_mode(hsotg, hsotg->test_mode); |
9e14d0a5 GH |
1973 | if (ret < 0) { |
1974 | dev_dbg(hsotg->dev, "Invalid Test #%d\n", | |
1975 | hsotg->test_mode); | |
1f91b4cc | 1976 | dwc2_hsotg_stall_ep0(hsotg); |
9e14d0a5 GH |
1977 | return; |
1978 | } | |
1979 | } | |
1f91b4cc | 1980 | dwc2_hsotg_enqueue_setup(hsotg); |
d3ca0259 LM |
1981 | return; |
1982 | } | |
1983 | ||
8b9bc460 LM |
1984 | /* |
1985 | * Calculate the size of the transfer by checking how much is left | |
5b7d70c6 BD |
1986 | * in the endpoint size register and then working it out from |
1987 | * the amount we loaded for the transfer. | |
1988 | * | |
1989 | * We do this even for DMA, as the transfer may have incremented | |
1990 | * past the end of the buffer (DMA transfers are always 32bit | |
1991 | * aligned). | |
1992 | */ | |
1993 | ||
47a1685f | 1994 | size_left = DXEPTSIZ_XFERSIZE_GET(epsize); |
5b7d70c6 BD |
1995 | |
1996 | size_done = hs_ep->size_loaded - size_left; | |
1997 | size_done += hs_ep->last_load; | |
1998 | ||
1999 | if (hs_req->req.actual != size_done) | |
2000 | dev_dbg(hsotg->dev, "%s: adjusting size done %d => %d\n", | |
2001 | __func__, hs_req->req.actual, size_done); | |
2002 | ||
2003 | hs_req->req.actual = size_done; | |
d3ca0259 LM |
2004 | dev_dbg(hsotg->dev, "req->length:%d req->actual:%d req->zero:%d\n", |
2005 | hs_req->req.length, hs_req->req.actual, hs_req->req.zero); | |
2006 | ||
5b7d70c6 BD |
2007 | if (!size_left && hs_req->req.actual < hs_req->req.length) { |
2008 | dev_dbg(hsotg->dev, "%s trying more for req...\n", __func__); | |
1f91b4cc | 2009 | dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true); |
fe0b94ab MYK |
2010 | return; |
2011 | } | |
2012 | ||
f71b5e25 | 2013 | /* Zlp for all endpoints, for ep0 only in DATA IN stage */ |
8a20fa45 | 2014 | if (hs_ep->send_zlp) { |
1f91b4cc | 2015 | dwc2_hsotg_program_zlp(hsotg, hs_ep); |
8a20fa45 | 2016 | hs_ep->send_zlp = 0; |
f71b5e25 MYK |
2017 | /* transfer will be completed on next complete interrupt */ |
2018 | return; | |
2019 | } | |
2020 | ||
fe0b94ab MYK |
2021 | if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_DATA_IN) { |
2022 | /* Move to STATUS OUT */ | |
1f91b4cc | 2023 | dwc2_hsotg_ep0_zlp(hsotg, false); |
fe0b94ab MYK |
2024 | return; |
2025 | } | |
2026 | ||
1f91b4cc | 2027 | dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0); |
5b7d70c6 BD |
2028 | } |
2029 | ||
32601588 VM |
2030 | /** |
2031 | * dwc2_gadget_read_ep_interrupts - reads interrupts for given ep | |
2032 | * @hsotg: The device state. | |
2033 | * @idx: Index of ep. | |
2034 | * @dir_in: Endpoint direction 1-in 0-out. | |
2035 | * | |
2036 | * Reads for endpoint with given index and direction, by masking | |
2037 | * epint_reg with coresponding mask. | |
2038 | */ | |
2039 | static u32 dwc2_gadget_read_ep_interrupts(struct dwc2_hsotg *hsotg, | |
2040 | unsigned int idx, int dir_in) | |
2041 | { | |
2042 | u32 epmsk_reg = dir_in ? DIEPMSK : DOEPMSK; | |
2043 | u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx); | |
2044 | u32 ints; | |
2045 | u32 mask; | |
2046 | u32 diepempmsk; | |
2047 | ||
2048 | mask = dwc2_readl(hsotg->regs + epmsk_reg); | |
2049 | diepempmsk = dwc2_readl(hsotg->regs + DIEPEMPMSK); | |
2050 | mask |= ((diepempmsk >> idx) & 0x1) ? DIEPMSK_TXFIFOEMPTY : 0; | |
2051 | mask |= DXEPINT_SETUP_RCVD; | |
2052 | ||
2053 | ints = dwc2_readl(hsotg->regs + epint_reg); | |
2054 | ints &= mask; | |
2055 | return ints; | |
2056 | } | |
2057 | ||
bd9971f0 VM |
2058 | /** |
2059 | * dwc2_gadget_handle_ep_disabled - handle DXEPINT_EPDISBLD | |
2060 | * @hs_ep: The endpoint on which interrupt is asserted. | |
2061 | * | |
2062 | * This interrupt indicates that the endpoint has been disabled per the | |
2063 | * application's request. | |
2064 | * | |
2065 | * For IN endpoints flushes txfifo, in case of BULK clears DCTL_CGNPINNAK, | |
2066 | * in case of ISOC completes current request. | |
2067 | * | |
2068 | * For ISOC-OUT endpoints completes expired requests. If there is remaining | |
2069 | * request starts it. | |
2070 | */ | |
2071 | static void dwc2_gadget_handle_ep_disabled(struct dwc2_hsotg_ep *hs_ep) | |
2072 | { | |
2073 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
2074 | struct dwc2_hsotg_req *hs_req; | |
2075 | unsigned char idx = hs_ep->index; | |
2076 | int dir_in = hs_ep->dir_in; | |
2077 | u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx); | |
2078 | int dctl = dwc2_readl(hsotg->regs + DCTL); | |
2079 | ||
2080 | dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__); | |
2081 | ||
2082 | if (dir_in) { | |
2083 | int epctl = dwc2_readl(hsotg->regs + epctl_reg); | |
2084 | ||
2085 | dwc2_hsotg_txfifo_flush(hsotg, hs_ep->fifo_index); | |
2086 | ||
2087 | if (hs_ep->isochronous) { | |
2088 | dwc2_hsotg_complete_in(hsotg, hs_ep); | |
2089 | return; | |
2090 | } | |
2091 | ||
2092 | if ((epctl & DXEPCTL_STALL) && (epctl & DXEPCTL_EPTYPE_BULK)) { | |
2093 | int dctl = dwc2_readl(hsotg->regs + DCTL); | |
2094 | ||
2095 | dctl |= DCTL_CGNPINNAK; | |
2096 | dwc2_writel(dctl, hsotg->regs + DCTL); | |
2097 | } | |
2098 | return; | |
2099 | } | |
2100 | ||
2101 | if (dctl & DCTL_GOUTNAKSTS) { | |
2102 | dctl |= DCTL_CGOUTNAK; | |
2103 | dwc2_writel(dctl, hsotg->regs + DCTL); | |
2104 | } | |
2105 | ||
2106 | if (!hs_ep->isochronous) | |
2107 | return; | |
2108 | ||
2109 | if (list_empty(&hs_ep->queue)) { | |
2110 | dev_dbg(hsotg->dev, "%s: complete_ep 0x%p, ep->queue empty!\n", | |
2111 | __func__, hs_ep); | |
2112 | return; | |
2113 | } | |
2114 | ||
2115 | do { | |
2116 | hs_req = get_ep_head(hs_ep); | |
2117 | if (hs_req) | |
2118 | dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, | |
2119 | -ENODATA); | |
2120 | dwc2_gadget_incr_frame_num(hs_ep); | |
2121 | } while (dwc2_gadget_target_frame_elapsed(hs_ep)); | |
2122 | ||
2123 | dwc2_gadget_start_next_request(hs_ep); | |
2124 | } | |
2125 | ||
5321922c VM |
2126 | /** |
2127 | * dwc2_gadget_handle_out_token_ep_disabled - handle DXEPINT_OUTTKNEPDIS | |
2128 | * @hs_ep: The endpoint on which interrupt is asserted. | |
2129 | * | |
2130 | * This is starting point for ISOC-OUT transfer, synchronization done with | |
2131 | * first out token received from host while corresponding EP is disabled. | |
2132 | * | |
2133 | * Device does not know initial frame in which out token will come. For this | |
2134 | * HW generates OUTTKNEPDIS - out token is received while EP is disabled. Upon | |
2135 | * getting this interrupt SW starts calculation for next transfer frame. | |
2136 | */ | |
2137 | static void dwc2_gadget_handle_out_token_ep_disabled(struct dwc2_hsotg_ep *ep) | |
2138 | { | |
2139 | struct dwc2_hsotg *hsotg = ep->parent; | |
2140 | int dir_in = ep->dir_in; | |
2141 | u32 doepmsk; | |
2142 | ||
2143 | if (dir_in || !ep->isochronous) | |
2144 | return; | |
2145 | ||
2146 | dwc2_hsotg_complete_request(hsotg, ep, get_ep_head(ep), -ENODATA); | |
2147 | ||
2148 | if (ep->interval > 1 && | |
2149 | ep->target_frame == TARGET_FRAME_INITIAL) { | |
2150 | u32 dsts; | |
2151 | u32 ctrl; | |
2152 | ||
2153 | dsts = dwc2_readl(hsotg->regs + DSTS); | |
2154 | ep->target_frame = dwc2_hsotg_read_frameno(hsotg); | |
2155 | dwc2_gadget_incr_frame_num(ep); | |
2156 | ||
2157 | ctrl = dwc2_readl(hsotg->regs + DOEPCTL(ep->index)); | |
2158 | if (ep->target_frame & 0x1) | |
2159 | ctrl |= DXEPCTL_SETODDFR; | |
2160 | else | |
2161 | ctrl |= DXEPCTL_SETEVENFR; | |
2162 | ||
2163 | dwc2_writel(ctrl, hsotg->regs + DOEPCTL(ep->index)); | |
2164 | } | |
2165 | ||
2166 | dwc2_gadget_start_next_request(ep); | |
2167 | doepmsk = dwc2_readl(hsotg->regs + DOEPMSK); | |
2168 | doepmsk &= ~DOEPMSK_OUTTKNEPDISMSK; | |
2169 | dwc2_writel(doepmsk, hsotg->regs + DOEPMSK); | |
2170 | } | |
2171 | ||
2172 | /** | |
2173 | * dwc2_gadget_handle_nak - handle NAK interrupt | |
2174 | * @hs_ep: The endpoint on which interrupt is asserted. | |
2175 | * | |
2176 | * This is starting point for ISOC-IN transfer, synchronization done with | |
2177 | * first IN token received from host while corresponding EP is disabled. | |
2178 | * | |
2179 | * Device does not know when first one token will arrive from host. On first | |
2180 | * token arrival HW generates 2 interrupts: 'in token received while FIFO empty' | |
2181 | * and 'NAK'. NAK interrupt for ISOC-IN means that token has arrived and ZLP was | |
2182 | * sent in response to that as there was no data in FIFO. SW is basing on this | |
2183 | * interrupt to obtain frame in which token has come and then based on the | |
2184 | * interval calculates next frame for transfer. | |
2185 | */ | |
2186 | static void dwc2_gadget_handle_nak(struct dwc2_hsotg_ep *hs_ep) | |
2187 | { | |
2188 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
2189 | int dir_in = hs_ep->dir_in; | |
2190 | ||
2191 | if (!dir_in || !hs_ep->isochronous) | |
2192 | return; | |
2193 | ||
2194 | if (hs_ep->target_frame == TARGET_FRAME_INITIAL) { | |
2195 | hs_ep->target_frame = dwc2_hsotg_read_frameno(hsotg); | |
2196 | if (hs_ep->interval > 1) { | |
2197 | u32 ctrl = dwc2_readl(hsotg->regs + | |
2198 | DIEPCTL(hs_ep->index)); | |
2199 | if (hs_ep->target_frame & 0x1) | |
2200 | ctrl |= DXEPCTL_SETODDFR; | |
2201 | else | |
2202 | ctrl |= DXEPCTL_SETEVENFR; | |
2203 | ||
2204 | dwc2_writel(ctrl, hsotg->regs + DIEPCTL(hs_ep->index)); | |
2205 | } | |
2206 | ||
2207 | dwc2_hsotg_complete_request(hsotg, hs_ep, | |
2208 | get_ep_head(hs_ep), 0); | |
2209 | } | |
2210 | ||
2211 | dwc2_gadget_incr_frame_num(hs_ep); | |
2212 | } | |
2213 | ||
5b7d70c6 | 2214 | /** |
1f91b4cc | 2215 | * dwc2_hsotg_epint - handle an in/out endpoint interrupt |
5b7d70c6 BD |
2216 | * @hsotg: The driver state |
2217 | * @idx: The index for the endpoint (0..15) | |
2218 | * @dir_in: Set if this is an IN endpoint | |
2219 | * | |
2220 | * Process and clear any interrupt pending for an individual endpoint | |
8b9bc460 | 2221 | */ |
1f91b4cc | 2222 | static void dwc2_hsotg_epint(struct dwc2_hsotg *hsotg, unsigned int idx, |
5b7d70c6 BD |
2223 | int dir_in) |
2224 | { | |
1f91b4cc | 2225 | struct dwc2_hsotg_ep *hs_ep = index_to_ep(hsotg, idx, dir_in); |
94cb8fd6 LM |
2226 | u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx); |
2227 | u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx); | |
2228 | u32 epsiz_reg = dir_in ? DIEPTSIZ(idx) : DOEPTSIZ(idx); | |
5b7d70c6 | 2229 | u32 ints; |
1479e841 | 2230 | u32 ctrl; |
5b7d70c6 | 2231 | |
32601588 | 2232 | ints = dwc2_gadget_read_ep_interrupts(hsotg, idx, dir_in); |
95c8bc36 | 2233 | ctrl = dwc2_readl(hsotg->regs + epctl_reg); |
5b7d70c6 | 2234 | |
a3395f0d | 2235 | /* Clear endpoint interrupts */ |
95c8bc36 | 2236 | dwc2_writel(ints, hsotg->regs + epint_reg); |
a3395f0d | 2237 | |
c6f5c050 MYK |
2238 | if (!hs_ep) { |
2239 | dev_err(hsotg->dev, "%s:Interrupt for unconfigured ep%d(%s)\n", | |
2240 | __func__, idx, dir_in ? "in" : "out"); | |
2241 | return; | |
2242 | } | |
2243 | ||
5b7d70c6 BD |
2244 | dev_dbg(hsotg->dev, "%s: ep%d(%s) DxEPINT=0x%08x\n", |
2245 | __func__, idx, dir_in ? "in" : "out", ints); | |
2246 | ||
b787d755 MYK |
2247 | /* Don't process XferCompl interrupt if it is a setup packet */ |
2248 | if (idx == 0 && (ints & (DXEPINT_SETUP | DXEPINT_SETUP_RCVD))) | |
2249 | ints &= ~DXEPINT_XFERCOMPL; | |
2250 | ||
837e9f00 VM |
2251 | if (ints & DXEPINT_STSPHSERCVD) |
2252 | dev_dbg(hsotg->dev, "%s: StsPhseRcvd asserted\n", __func__); | |
1479e841 | 2253 | |
837e9f00 | 2254 | if (ints & DXEPINT_XFERCOMPL) { |
5b7d70c6 | 2255 | dev_dbg(hsotg->dev, |
47a1685f | 2256 | "%s: XferCompl: DxEPCTL=0x%08x, DXEPTSIZ=%08x\n", |
95c8bc36 AS |
2257 | __func__, dwc2_readl(hsotg->regs + epctl_reg), |
2258 | dwc2_readl(hsotg->regs + epsiz_reg)); | |
5b7d70c6 | 2259 | |
8b9bc460 LM |
2260 | /* |
2261 | * we get OutDone from the FIFO, so we only need to look | |
2262 | * at completing IN requests here | |
2263 | */ | |
5b7d70c6 | 2264 | if (dir_in) { |
837e9f00 VM |
2265 | if (hs_ep->isochronous && hs_ep->interval > 1) |
2266 | dwc2_gadget_incr_frame_num(hs_ep); | |
2267 | ||
1f91b4cc | 2268 | dwc2_hsotg_complete_in(hsotg, hs_ep); |
837e9f00 VM |
2269 | if (ints & DXEPINT_NAKINTRPT) |
2270 | ints &= ~DXEPINT_NAKINTRPT; | |
5b7d70c6 | 2271 | |
c9a64ea8 | 2272 | if (idx == 0 && !hs_ep->req) |
1f91b4cc | 2273 | dwc2_hsotg_enqueue_setup(hsotg); |
5b7d70c6 | 2274 | } else if (using_dma(hsotg)) { |
8b9bc460 LM |
2275 | /* |
2276 | * We're using DMA, we need to fire an OutDone here | |
2277 | * as we ignore the RXFIFO. | |
2278 | */ | |
837e9f00 VM |
2279 | if (hs_ep->isochronous && hs_ep->interval > 1) |
2280 | dwc2_gadget_incr_frame_num(hs_ep); | |
5b7d70c6 | 2281 | |
1f91b4cc | 2282 | dwc2_hsotg_handle_outdone(hsotg, idx); |
5b7d70c6 | 2283 | } |
5b7d70c6 BD |
2284 | } |
2285 | ||
bd9971f0 VM |
2286 | if (ints & DXEPINT_EPDISBLD) |
2287 | dwc2_gadget_handle_ep_disabled(hs_ep); | |
9c39ddc6 | 2288 | |
5321922c VM |
2289 | if (ints & DXEPINT_OUTTKNEPDIS) |
2290 | dwc2_gadget_handle_out_token_ep_disabled(hs_ep); | |
2291 | ||
2292 | if (ints & DXEPINT_NAKINTRPT) | |
2293 | dwc2_gadget_handle_nak(hs_ep); | |
2294 | ||
47a1685f | 2295 | if (ints & DXEPINT_AHBERR) |
5b7d70c6 | 2296 | dev_dbg(hsotg->dev, "%s: AHBErr\n", __func__); |
5b7d70c6 | 2297 | |
47a1685f | 2298 | if (ints & DXEPINT_SETUP) { /* Setup or Timeout */ |
5b7d70c6 BD |
2299 | dev_dbg(hsotg->dev, "%s: Setup/Timeout\n", __func__); |
2300 | ||
2301 | if (using_dma(hsotg) && idx == 0) { | |
8b9bc460 LM |
2302 | /* |
2303 | * this is the notification we've received a | |
5b7d70c6 BD |
2304 | * setup packet. In non-DMA mode we'd get this |
2305 | * from the RXFIFO, instead we need to process | |
8b9bc460 LM |
2306 | * the setup here. |
2307 | */ | |
5b7d70c6 BD |
2308 | |
2309 | if (dir_in) | |
2310 | WARN_ON_ONCE(1); | |
2311 | else | |
1f91b4cc | 2312 | dwc2_hsotg_handle_outdone(hsotg, 0); |
5b7d70c6 | 2313 | } |
5b7d70c6 BD |
2314 | } |
2315 | ||
47a1685f | 2316 | if (ints & DXEPINT_BACK2BACKSETUP) |
5b7d70c6 | 2317 | dev_dbg(hsotg->dev, "%s: B2BSetup/INEPNakEff\n", __func__); |
5b7d70c6 | 2318 | |
1479e841 | 2319 | if (dir_in && !hs_ep->isochronous) { |
8b9bc460 | 2320 | /* not sure if this is important, but we'll clear it anyway */ |
26ddef5d | 2321 | if (ints & DXEPINT_INTKNTXFEMP) { |
5b7d70c6 BD |
2322 | dev_dbg(hsotg->dev, "%s: ep%d: INTknTXFEmpMsk\n", |
2323 | __func__, idx); | |
5b7d70c6 BD |
2324 | } |
2325 | ||
2326 | /* this probably means something bad is happening */ | |
26ddef5d | 2327 | if (ints & DXEPINT_INTKNEPMIS) { |
5b7d70c6 BD |
2328 | dev_warn(hsotg->dev, "%s: ep%d: INTknEP\n", |
2329 | __func__, idx); | |
5b7d70c6 | 2330 | } |
10aebc77 BD |
2331 | |
2332 | /* FIFO has space or is empty (see GAHBCFG) */ | |
2333 | if (hsotg->dedicated_fifos && | |
26ddef5d | 2334 | ints & DXEPINT_TXFEMP) { |
10aebc77 BD |
2335 | dev_dbg(hsotg->dev, "%s: ep%d: TxFIFOEmpty\n", |
2336 | __func__, idx); | |
70fa030f | 2337 | if (!using_dma(hsotg)) |
1f91b4cc | 2338 | dwc2_hsotg_trytx(hsotg, hs_ep); |
10aebc77 | 2339 | } |
5b7d70c6 | 2340 | } |
5b7d70c6 BD |
2341 | } |
2342 | ||
2343 | /** | |
1f91b4cc | 2344 | * dwc2_hsotg_irq_enumdone - Handle EnumDone interrupt (enumeration done) |
5b7d70c6 BD |
2345 | * @hsotg: The device state. |
2346 | * | |
2347 | * Handle updating the device settings after the enumeration phase has | |
2348 | * been completed. | |
8b9bc460 | 2349 | */ |
1f91b4cc | 2350 | static void dwc2_hsotg_irq_enumdone(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 2351 | { |
95c8bc36 | 2352 | u32 dsts = dwc2_readl(hsotg->regs + DSTS); |
9b2667f1 | 2353 | int ep0_mps = 0, ep_mps = 8; |
5b7d70c6 | 2354 | |
8b9bc460 LM |
2355 | /* |
2356 | * This should signal the finish of the enumeration phase | |
5b7d70c6 | 2357 | * of the USB handshaking, so we should now know what rate |
8b9bc460 LM |
2358 | * we connected at. |
2359 | */ | |
5b7d70c6 BD |
2360 | |
2361 | dev_dbg(hsotg->dev, "EnumDone (DSTS=0x%08x)\n", dsts); | |
2362 | ||
8b9bc460 LM |
2363 | /* |
2364 | * note, since we're limited by the size of transfer on EP0, and | |
5b7d70c6 | 2365 | * it seems IN transfers must be a even number of packets we do |
8b9bc460 LM |
2366 | * not advertise a 64byte MPS on EP0. |
2367 | */ | |
5b7d70c6 BD |
2368 | |
2369 | /* catch both EnumSpd_FS and EnumSpd_FS48 */ | |
6d76c92c | 2370 | switch ((dsts & DSTS_ENUMSPD_MASK) >> DSTS_ENUMSPD_SHIFT) { |
47a1685f DN |
2371 | case DSTS_ENUMSPD_FS: |
2372 | case DSTS_ENUMSPD_FS48: | |
5b7d70c6 | 2373 | hsotg->gadget.speed = USB_SPEED_FULL; |
5b7d70c6 | 2374 | ep0_mps = EP0_MPS_LIMIT; |
295538ff | 2375 | ep_mps = 1023; |
5b7d70c6 BD |
2376 | break; |
2377 | ||
47a1685f | 2378 | case DSTS_ENUMSPD_HS: |
5b7d70c6 | 2379 | hsotg->gadget.speed = USB_SPEED_HIGH; |
5b7d70c6 | 2380 | ep0_mps = EP0_MPS_LIMIT; |
295538ff | 2381 | ep_mps = 1024; |
5b7d70c6 BD |
2382 | break; |
2383 | ||
47a1685f | 2384 | case DSTS_ENUMSPD_LS: |
5b7d70c6 | 2385 | hsotg->gadget.speed = USB_SPEED_LOW; |
8b9bc460 LM |
2386 | /* |
2387 | * note, we don't actually support LS in this driver at the | |
5b7d70c6 BD |
2388 | * moment, and the documentation seems to imply that it isn't |
2389 | * supported by the PHYs on some of the devices. | |
2390 | */ | |
2391 | break; | |
2392 | } | |
e538dfda MN |
2393 | dev_info(hsotg->dev, "new device is %s\n", |
2394 | usb_speed_string(hsotg->gadget.speed)); | |
5b7d70c6 | 2395 | |
8b9bc460 LM |
2396 | /* |
2397 | * we should now know the maximum packet size for an | |
2398 | * endpoint, so set the endpoints to a default value. | |
2399 | */ | |
5b7d70c6 BD |
2400 | |
2401 | if (ep0_mps) { | |
2402 | int i; | |
c6f5c050 | 2403 | /* Initialize ep0 for both in and out directions */ |
ee2c40de VM |
2404 | dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 0, 1); |
2405 | dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 0, 0); | |
c6f5c050 MYK |
2406 | for (i = 1; i < hsotg->num_of_eps; i++) { |
2407 | if (hsotg->eps_in[i]) | |
ee2c40de VM |
2408 | dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps, |
2409 | 0, 1); | |
c6f5c050 | 2410 | if (hsotg->eps_out[i]) |
ee2c40de VM |
2411 | dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps, |
2412 | 0, 0); | |
c6f5c050 | 2413 | } |
5b7d70c6 BD |
2414 | } |
2415 | ||
2416 | /* ensure after enumeration our EP0 is active */ | |
2417 | ||
1f91b4cc | 2418 | dwc2_hsotg_enqueue_setup(hsotg); |
5b7d70c6 BD |
2419 | |
2420 | dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n", | |
95c8bc36 AS |
2421 | dwc2_readl(hsotg->regs + DIEPCTL0), |
2422 | dwc2_readl(hsotg->regs + DOEPCTL0)); | |
5b7d70c6 BD |
2423 | } |
2424 | ||
2425 | /** | |
2426 | * kill_all_requests - remove all requests from the endpoint's queue | |
2427 | * @hsotg: The device state. | |
2428 | * @ep: The endpoint the requests may be on. | |
2429 | * @result: The result code to use. | |
5b7d70c6 BD |
2430 | * |
2431 | * Go through the requests on the given endpoint and mark them | |
2432 | * completed with the given result code. | |
2433 | */ | |
941fcce4 | 2434 | static void kill_all_requests(struct dwc2_hsotg *hsotg, |
1f91b4cc | 2435 | struct dwc2_hsotg_ep *ep, |
6b448af4 | 2436 | int result) |
5b7d70c6 | 2437 | { |
1f91b4cc | 2438 | struct dwc2_hsotg_req *req, *treq; |
b203d0a2 | 2439 | unsigned size; |
5b7d70c6 | 2440 | |
6b448af4 | 2441 | ep->req = NULL; |
5b7d70c6 | 2442 | |
6b448af4 | 2443 | list_for_each_entry_safe(req, treq, &ep->queue, queue) |
1f91b4cc | 2444 | dwc2_hsotg_complete_request(hsotg, ep, req, |
5b7d70c6 | 2445 | result); |
6b448af4 | 2446 | |
b203d0a2 RB |
2447 | if (!hsotg->dedicated_fifos) |
2448 | return; | |
ad674a15 | 2449 | size = (dwc2_readl(hsotg->regs + DTXFSTS(ep->fifo_index)) & 0xffff) * 4; |
b203d0a2 | 2450 | if (size < ep->fifo_size) |
1f91b4cc | 2451 | dwc2_hsotg_txfifo_flush(hsotg, ep->fifo_index); |
5b7d70c6 BD |
2452 | } |
2453 | ||
5b7d70c6 | 2454 | /** |
1f91b4cc | 2455 | * dwc2_hsotg_disconnect - disconnect service |
5b7d70c6 BD |
2456 | * @hsotg: The device state. |
2457 | * | |
5e891342 LM |
2458 | * The device has been disconnected. Remove all current |
2459 | * transactions and signal the gadget driver that this | |
2460 | * has happened. | |
8b9bc460 | 2461 | */ |
1f91b4cc | 2462 | void dwc2_hsotg_disconnect(struct dwc2_hsotg *hsotg) |
5b7d70c6 BD |
2463 | { |
2464 | unsigned ep; | |
2465 | ||
4ace06e8 MS |
2466 | if (!hsotg->connected) |
2467 | return; | |
2468 | ||
2469 | hsotg->connected = 0; | |
9e14d0a5 | 2470 | hsotg->test_mode = 0; |
c6f5c050 MYK |
2471 | |
2472 | for (ep = 0; ep < hsotg->num_of_eps; ep++) { | |
2473 | if (hsotg->eps_in[ep]) | |
2474 | kill_all_requests(hsotg, hsotg->eps_in[ep], | |
2475 | -ESHUTDOWN); | |
2476 | if (hsotg->eps_out[ep]) | |
2477 | kill_all_requests(hsotg, hsotg->eps_out[ep], | |
2478 | -ESHUTDOWN); | |
2479 | } | |
5b7d70c6 BD |
2480 | |
2481 | call_gadget(hsotg, disconnect); | |
065d3931 | 2482 | hsotg->lx_state = DWC2_L3; |
5b7d70c6 BD |
2483 | } |
2484 | ||
2485 | /** | |
1f91b4cc | 2486 | * dwc2_hsotg_irq_fifoempty - TX FIFO empty interrupt handler |
5b7d70c6 BD |
2487 | * @hsotg: The device state: |
2488 | * @periodic: True if this is a periodic FIFO interrupt | |
2489 | */ | |
1f91b4cc | 2490 | static void dwc2_hsotg_irq_fifoempty(struct dwc2_hsotg *hsotg, bool periodic) |
5b7d70c6 | 2491 | { |
1f91b4cc | 2492 | struct dwc2_hsotg_ep *ep; |
5b7d70c6 BD |
2493 | int epno, ret; |
2494 | ||
2495 | /* look through for any more data to transmit */ | |
b3f489b2 | 2496 | for (epno = 0; epno < hsotg->num_of_eps; epno++) { |
c6f5c050 MYK |
2497 | ep = index_to_ep(hsotg, epno, 1); |
2498 | ||
2499 | if (!ep) | |
2500 | continue; | |
5b7d70c6 BD |
2501 | |
2502 | if (!ep->dir_in) | |
2503 | continue; | |
2504 | ||
2505 | if ((periodic && !ep->periodic) || | |
2506 | (!periodic && ep->periodic)) | |
2507 | continue; | |
2508 | ||
1f91b4cc | 2509 | ret = dwc2_hsotg_trytx(hsotg, ep); |
5b7d70c6 BD |
2510 | if (ret < 0) |
2511 | break; | |
2512 | } | |
2513 | } | |
2514 | ||
5b7d70c6 | 2515 | /* IRQ flags which will trigger a retry around the IRQ loop */ |
47a1685f DN |
2516 | #define IRQ_RETRY_MASK (GINTSTS_NPTXFEMP | \ |
2517 | GINTSTS_PTXFEMP | \ | |
2518 | GINTSTS_RXFLVL) | |
5b7d70c6 | 2519 | |
8b9bc460 | 2520 | /** |
1f91b4cc | 2521 | * dwc2_hsotg_core_init - issue softreset to the core |
8b9bc460 LM |
2522 | * @hsotg: The device state |
2523 | * | |
2524 | * Issue a soft reset to the core, and await the core finishing it. | |
2525 | */ | |
1f91b4cc | 2526 | void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg, |
643cc4de | 2527 | bool is_usb_reset) |
308d734e | 2528 | { |
1ee6903b | 2529 | u32 intmsk; |
643cc4de | 2530 | u32 val; |
ecd9a7ad | 2531 | u32 usbcfg; |
643cc4de | 2532 | |
5390d438 MYK |
2533 | /* Kill any ep0 requests as controller will be reinitialized */ |
2534 | kill_all_requests(hsotg, hsotg->eps_out[0], -ECONNRESET); | |
2535 | ||
643cc4de | 2536 | if (!is_usb_reset) |
241729ba | 2537 | if (dwc2_core_reset(hsotg)) |
86de4895 | 2538 | return; |
308d734e LM |
2539 | |
2540 | /* | |
2541 | * we must now enable ep0 ready for host detection and then | |
2542 | * set configuration. | |
2543 | */ | |
2544 | ||
ecd9a7ad PR |
2545 | /* keep other bits untouched (so e.g. forced modes are not lost) */ |
2546 | usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); | |
2547 | usbcfg &= ~(GUSBCFG_TOUTCAL_MASK | GUSBCFG_PHYIF16 | GUSBCFG_SRPCAP | | |
2548 | GUSBCFG_HNPCAP); | |
2549 | ||
308d734e | 2550 | /* set the PLL on, remove the HNP/SRP and set the PHY */ |
fa4a8d72 | 2551 | val = (hsotg->phyif == GUSBCFG_PHYIF8) ? 9 : 5; |
ecd9a7ad PR |
2552 | usbcfg |= hsotg->phyif | GUSBCFG_TOUTCAL(7) | |
2553 | (val << GUSBCFG_USBTRDTIM_SHIFT); | |
2554 | dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); | |
308d734e | 2555 | |
1f91b4cc | 2556 | dwc2_hsotg_init_fifo(hsotg); |
308d734e | 2557 | |
643cc4de GH |
2558 | if (!is_usb_reset) |
2559 | __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON); | |
308d734e | 2560 | |
95c8bc36 | 2561 | dwc2_writel(DCFG_EPMISCNT(1) | DCFG_DEVSPD_HS, hsotg->regs + DCFG); |
308d734e LM |
2562 | |
2563 | /* Clear any pending OTG interrupts */ | |
95c8bc36 | 2564 | dwc2_writel(0xffffffff, hsotg->regs + GOTGINT); |
308d734e LM |
2565 | |
2566 | /* Clear any pending interrupts */ | |
95c8bc36 | 2567 | dwc2_writel(0xffffffff, hsotg->regs + GINTSTS); |
1ee6903b | 2568 | intmsk = GINTSTS_ERLYSUSP | GINTSTS_SESSREQINT | |
47a1685f | 2569 | GINTSTS_GOUTNAKEFF | GINTSTS_GINNAKEFF | |
1ee6903b GH |
2570 | GINTSTS_USBRST | GINTSTS_RESETDET | |
2571 | GINTSTS_ENUMDONE | GINTSTS_OTGINT | | |
ec1f9d9f RB |
2572 | GINTSTS_USBSUSP | GINTSTS_WKUPINT | |
2573 | GINTSTS_INCOMPL_SOIN | GINTSTS_INCOMPL_SOOUT; | |
1ee6903b | 2574 | |
bea8e86c | 2575 | if (hsotg->params.external_id_pin_ctl <= 0) |
1ee6903b GH |
2576 | intmsk |= GINTSTS_CONIDSTSCHNG; |
2577 | ||
2578 | dwc2_writel(intmsk, hsotg->regs + GINTMSK); | |
308d734e LM |
2579 | |
2580 | if (using_dma(hsotg)) | |
95c8bc36 AS |
2581 | dwc2_writel(GAHBCFG_GLBL_INTR_EN | GAHBCFG_DMA_EN | |
2582 | (GAHBCFG_HBSTLEN_INCR4 << GAHBCFG_HBSTLEN_SHIFT), | |
2583 | hsotg->regs + GAHBCFG); | |
308d734e | 2584 | else |
95c8bc36 AS |
2585 | dwc2_writel(((hsotg->dedicated_fifos) ? |
2586 | (GAHBCFG_NP_TXF_EMP_LVL | | |
2587 | GAHBCFG_P_TXF_EMP_LVL) : 0) | | |
2588 | GAHBCFG_GLBL_INTR_EN, hsotg->regs + GAHBCFG); | |
308d734e LM |
2589 | |
2590 | /* | |
8acc8296 RB |
2591 | * If INTknTXFEmpMsk is enabled, it's important to disable ep interrupts |
2592 | * when we have no data to transfer. Otherwise we get being flooded by | |
2593 | * interrupts. | |
308d734e LM |
2594 | */ |
2595 | ||
95c8bc36 | 2596 | dwc2_writel(((hsotg->dedicated_fifos && !using_dma(hsotg)) ? |
6ff2e832 | 2597 | DIEPMSK_TXFIFOEMPTY | DIEPMSK_INTKNTXFEMPMSK : 0) | |
47a1685f | 2598 | DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK | |
837e9f00 | 2599 | DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK, |
47a1685f | 2600 | hsotg->regs + DIEPMSK); |
308d734e LM |
2601 | |
2602 | /* | |
2603 | * don't need XferCompl, we get that from RXFIFO in slave mode. In | |
2604 | * DMA mode we may need this. | |
2605 | */ | |
837e9f00 | 2606 | dwc2_writel((using_dma(hsotg) ? (DIEPMSK_XFERCOMPLMSK) : 0) | |
47a1685f | 2607 | DOEPMSK_EPDISBLDMSK | DOEPMSK_AHBERRMSK | |
837e9f00 | 2608 | DOEPMSK_SETUPMSK | DOEPMSK_STSPHSERCVDMSK, |
47a1685f | 2609 | hsotg->regs + DOEPMSK); |
308d734e | 2610 | |
95c8bc36 | 2611 | dwc2_writel(0, hsotg->regs + DAINTMSK); |
308d734e LM |
2612 | |
2613 | dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n", | |
95c8bc36 AS |
2614 | dwc2_readl(hsotg->regs + DIEPCTL0), |
2615 | dwc2_readl(hsotg->regs + DOEPCTL0)); | |
308d734e LM |
2616 | |
2617 | /* enable in and out endpoint interrupts */ | |
1f91b4cc | 2618 | dwc2_hsotg_en_gsint(hsotg, GINTSTS_OEPINT | GINTSTS_IEPINT); |
308d734e LM |
2619 | |
2620 | /* | |
2621 | * Enable the RXFIFO when in slave mode, as this is how we collect | |
2622 | * the data. In DMA mode, we get events from the FIFO but also | |
2623 | * things we cannot process, so do not use it. | |
2624 | */ | |
2625 | if (!using_dma(hsotg)) | |
1f91b4cc | 2626 | dwc2_hsotg_en_gsint(hsotg, GINTSTS_RXFLVL); |
308d734e LM |
2627 | |
2628 | /* Enable interrupts for EP0 in and out */ | |
1f91b4cc FB |
2629 | dwc2_hsotg_ctrl_epint(hsotg, 0, 0, 1); |
2630 | dwc2_hsotg_ctrl_epint(hsotg, 0, 1, 1); | |
308d734e | 2631 | |
643cc4de GH |
2632 | if (!is_usb_reset) { |
2633 | __orr32(hsotg->regs + DCTL, DCTL_PWRONPRGDONE); | |
2634 | udelay(10); /* see openiboot */ | |
2635 | __bic32(hsotg->regs + DCTL, DCTL_PWRONPRGDONE); | |
2636 | } | |
308d734e | 2637 | |
95c8bc36 | 2638 | dev_dbg(hsotg->dev, "DCTL=0x%08x\n", dwc2_readl(hsotg->regs + DCTL)); |
308d734e LM |
2639 | |
2640 | /* | |
94cb8fd6 | 2641 | * DxEPCTL_USBActEp says RO in manual, but seems to be set by |
308d734e LM |
2642 | * writing to the EPCTL register.. |
2643 | */ | |
2644 | ||
2645 | /* set to read 1 8byte packet */ | |
95c8bc36 | 2646 | dwc2_writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) | |
47a1685f | 2647 | DXEPTSIZ_XFERSIZE(8), hsotg->regs + DOEPTSIZ0); |
308d734e | 2648 | |
95c8bc36 | 2649 | dwc2_writel(dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) | |
47a1685f DN |
2650 | DXEPCTL_CNAK | DXEPCTL_EPENA | |
2651 | DXEPCTL_USBACTEP, | |
94cb8fd6 | 2652 | hsotg->regs + DOEPCTL0); |
308d734e LM |
2653 | |
2654 | /* enable, but don't activate EP0in */ | |
95c8bc36 | 2655 | dwc2_writel(dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) | |
47a1685f | 2656 | DXEPCTL_USBACTEP, hsotg->regs + DIEPCTL0); |
308d734e | 2657 | |
1f91b4cc | 2658 | dwc2_hsotg_enqueue_setup(hsotg); |
308d734e LM |
2659 | |
2660 | dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n", | |
95c8bc36 AS |
2661 | dwc2_readl(hsotg->regs + DIEPCTL0), |
2662 | dwc2_readl(hsotg->regs + DOEPCTL0)); | |
308d734e LM |
2663 | |
2664 | /* clear global NAKs */ | |
643cc4de GH |
2665 | val = DCTL_CGOUTNAK | DCTL_CGNPINNAK; |
2666 | if (!is_usb_reset) | |
2667 | val |= DCTL_SFTDISCON; | |
2668 | __orr32(hsotg->regs + DCTL, val); | |
308d734e LM |
2669 | |
2670 | /* must be at-least 3ms to allow bus to see disconnect */ | |
2671 | mdelay(3); | |
2672 | ||
065d3931 | 2673 | hsotg->lx_state = DWC2_L0; |
ad38dc5d MS |
2674 | } |
2675 | ||
1f91b4cc | 2676 | static void dwc2_hsotg_core_disconnect(struct dwc2_hsotg *hsotg) |
ad38dc5d MS |
2677 | { |
2678 | /* set the soft-disconnect bit */ | |
2679 | __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON); | |
2680 | } | |
ac3c81f3 | 2681 | |
1f91b4cc | 2682 | void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg) |
ad38dc5d | 2683 | { |
308d734e | 2684 | /* remove the soft-disconnect and let's go */ |
47a1685f | 2685 | __bic32(hsotg->regs + DCTL, DCTL_SFTDISCON); |
308d734e LM |
2686 | } |
2687 | ||
381fc8f8 VM |
2688 | /** |
2689 | * dwc2_gadget_handle_incomplete_isoc_in - handle incomplete ISO IN Interrupt. | |
2690 | * @hsotg: The device state: | |
2691 | * | |
2692 | * This interrupt indicates one of the following conditions occurred while | |
2693 | * transmitting an ISOC transaction. | |
2694 | * - Corrupted IN Token for ISOC EP. | |
2695 | * - Packet not complete in FIFO. | |
2696 | * | |
2697 | * The following actions will be taken: | |
2698 | * - Determine the EP | |
2699 | * - Disable EP; when 'Endpoint Disabled' interrupt is received Flush FIFO | |
2700 | */ | |
2701 | static void dwc2_gadget_handle_incomplete_isoc_in(struct dwc2_hsotg *hsotg) | |
2702 | { | |
2703 | struct dwc2_hsotg_ep *hs_ep; | |
2704 | u32 epctrl; | |
2705 | u32 idx; | |
2706 | ||
2707 | dev_dbg(hsotg->dev, "Incomplete isoc in interrupt received:\n"); | |
2708 | ||
2709 | for (idx = 1; idx <= hsotg->num_of_eps; idx++) { | |
2710 | hs_ep = hsotg->eps_in[idx]; | |
2711 | epctrl = dwc2_readl(hsotg->regs + DIEPCTL(idx)); | |
2712 | if ((epctrl & DXEPCTL_EPENA) && hs_ep->isochronous && | |
2713 | dwc2_gadget_target_frame_elapsed(hs_ep)) { | |
2714 | epctrl |= DXEPCTL_SNAK; | |
2715 | epctrl |= DXEPCTL_EPDIS; | |
2716 | dwc2_writel(epctrl, hsotg->regs + DIEPCTL(idx)); | |
2717 | } | |
2718 | } | |
2719 | ||
2720 | /* Clear interrupt */ | |
2721 | dwc2_writel(GINTSTS_INCOMPL_SOIN, hsotg->regs + GINTSTS); | |
2722 | } | |
2723 | ||
2724 | /** | |
2725 | * dwc2_gadget_handle_incomplete_isoc_out - handle incomplete ISO OUT Interrupt | |
2726 | * @hsotg: The device state: | |
2727 | * | |
2728 | * This interrupt indicates one of the following conditions occurred while | |
2729 | * transmitting an ISOC transaction. | |
2730 | * - Corrupted OUT Token for ISOC EP. | |
2731 | * - Packet not complete in FIFO. | |
2732 | * | |
2733 | * The following actions will be taken: | |
2734 | * - Determine the EP | |
2735 | * - Set DCTL_SGOUTNAK and unmask GOUTNAKEFF if target frame elapsed. | |
2736 | */ | |
2737 | static void dwc2_gadget_handle_incomplete_isoc_out(struct dwc2_hsotg *hsotg) | |
2738 | { | |
2739 | u32 gintsts; | |
2740 | u32 gintmsk; | |
2741 | u32 epctrl; | |
2742 | struct dwc2_hsotg_ep *hs_ep; | |
2743 | int idx; | |
2744 | ||
2745 | dev_dbg(hsotg->dev, "%s: GINTSTS_INCOMPL_SOOUT\n", __func__); | |
2746 | ||
2747 | for (idx = 1; idx <= hsotg->num_of_eps; idx++) { | |
2748 | hs_ep = hsotg->eps_out[idx]; | |
2749 | epctrl = dwc2_readl(hsotg->regs + DOEPCTL(idx)); | |
2750 | if ((epctrl & DXEPCTL_EPENA) && hs_ep->isochronous && | |
2751 | dwc2_gadget_target_frame_elapsed(hs_ep)) { | |
2752 | /* Unmask GOUTNAKEFF interrupt */ | |
2753 | gintmsk = dwc2_readl(hsotg->regs + GINTMSK); | |
2754 | gintmsk |= GINTSTS_GOUTNAKEFF; | |
2755 | dwc2_writel(gintmsk, hsotg->regs + GINTMSK); | |
2756 | ||
2757 | gintsts = dwc2_readl(hsotg->regs + GINTSTS); | |
2758 | if (!(gintsts & GINTSTS_GOUTNAKEFF)) | |
2759 | __orr32(hsotg->regs + DCTL, DCTL_SGOUTNAK); | |
2760 | } | |
2761 | } | |
2762 | ||
2763 | /* Clear interrupt */ | |
2764 | dwc2_writel(GINTSTS_INCOMPL_SOOUT, hsotg->regs + GINTSTS); | |
2765 | } | |
2766 | ||
5b7d70c6 | 2767 | /** |
1f91b4cc | 2768 | * dwc2_hsotg_irq - handle device interrupt |
5b7d70c6 BD |
2769 | * @irq: The IRQ number triggered |
2770 | * @pw: The pw value when registered the handler. | |
2771 | */ | |
1f91b4cc | 2772 | static irqreturn_t dwc2_hsotg_irq(int irq, void *pw) |
5b7d70c6 | 2773 | { |
941fcce4 | 2774 | struct dwc2_hsotg *hsotg = pw; |
5b7d70c6 BD |
2775 | int retry_count = 8; |
2776 | u32 gintsts; | |
2777 | u32 gintmsk; | |
2778 | ||
ee3de8d7 VM |
2779 | if (!dwc2_is_device_mode(hsotg)) |
2780 | return IRQ_NONE; | |
2781 | ||
5ad1d316 | 2782 | spin_lock(&hsotg->lock); |
5b7d70c6 | 2783 | irq_retry: |
95c8bc36 AS |
2784 | gintsts = dwc2_readl(hsotg->regs + GINTSTS); |
2785 | gintmsk = dwc2_readl(hsotg->regs + GINTMSK); | |
5b7d70c6 BD |
2786 | |
2787 | dev_dbg(hsotg->dev, "%s: %08x %08x (%08x) retry %d\n", | |
2788 | __func__, gintsts, gintsts & gintmsk, gintmsk, retry_count); | |
2789 | ||
2790 | gintsts &= gintmsk; | |
2791 | ||
8fc37b82 MYK |
2792 | if (gintsts & GINTSTS_RESETDET) { |
2793 | dev_dbg(hsotg->dev, "%s: USBRstDet\n", __func__); | |
2794 | ||
2795 | dwc2_writel(GINTSTS_RESETDET, hsotg->regs + GINTSTS); | |
2796 | ||
2797 | /* This event must be used only if controller is suspended */ | |
2798 | if (hsotg->lx_state == DWC2_L2) { | |
2799 | dwc2_exit_hibernation(hsotg, true); | |
2800 | hsotg->lx_state = DWC2_L0; | |
2801 | } | |
2802 | } | |
2803 | ||
2804 | if (gintsts & (GINTSTS_USBRST | GINTSTS_RESETDET)) { | |
2805 | ||
2806 | u32 usb_status = dwc2_readl(hsotg->regs + GOTGCTL); | |
2807 | u32 connected = hsotg->connected; | |
2808 | ||
2809 | dev_dbg(hsotg->dev, "%s: USBRst\n", __func__); | |
2810 | dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n", | |
2811 | dwc2_readl(hsotg->regs + GNPTXSTS)); | |
2812 | ||
2813 | dwc2_writel(GINTSTS_USBRST, hsotg->regs + GINTSTS); | |
2814 | ||
2815 | /* Report disconnection if it is not already done. */ | |
2816 | dwc2_hsotg_disconnect(hsotg); | |
2817 | ||
2818 | if (usb_status & GOTGCTL_BSESVLD && connected) | |
2819 | dwc2_hsotg_core_init_disconnected(hsotg, true); | |
2820 | } | |
2821 | ||
47a1685f | 2822 | if (gintsts & GINTSTS_ENUMDONE) { |
95c8bc36 | 2823 | dwc2_writel(GINTSTS_ENUMDONE, hsotg->regs + GINTSTS); |
a3395f0d | 2824 | |
1f91b4cc | 2825 | dwc2_hsotg_irq_enumdone(hsotg); |
5b7d70c6 BD |
2826 | } |
2827 | ||
47a1685f | 2828 | if (gintsts & (GINTSTS_OEPINT | GINTSTS_IEPINT)) { |
95c8bc36 AS |
2829 | u32 daint = dwc2_readl(hsotg->regs + DAINT); |
2830 | u32 daintmsk = dwc2_readl(hsotg->regs + DAINTMSK); | |
7e804650 | 2831 | u32 daint_out, daint_in; |
5b7d70c6 BD |
2832 | int ep; |
2833 | ||
7e804650 | 2834 | daint &= daintmsk; |
47a1685f DN |
2835 | daint_out = daint >> DAINT_OUTEP_SHIFT; |
2836 | daint_in = daint & ~(daint_out << DAINT_OUTEP_SHIFT); | |
7e804650 | 2837 | |
5b7d70c6 BD |
2838 | dev_dbg(hsotg->dev, "%s: daint=%08x\n", __func__, daint); |
2839 | ||
cec87f1d MYK |
2840 | for (ep = 0; ep < hsotg->num_of_eps && daint_out; |
2841 | ep++, daint_out >>= 1) { | |
5b7d70c6 | 2842 | if (daint_out & 1) |
1f91b4cc | 2843 | dwc2_hsotg_epint(hsotg, ep, 0); |
5b7d70c6 BD |
2844 | } |
2845 | ||
cec87f1d MYK |
2846 | for (ep = 0; ep < hsotg->num_of_eps && daint_in; |
2847 | ep++, daint_in >>= 1) { | |
5b7d70c6 | 2848 | if (daint_in & 1) |
1f91b4cc | 2849 | dwc2_hsotg_epint(hsotg, ep, 1); |
5b7d70c6 | 2850 | } |
5b7d70c6 BD |
2851 | } |
2852 | ||
5b7d70c6 BD |
2853 | /* check both FIFOs */ |
2854 | ||
47a1685f | 2855 | if (gintsts & GINTSTS_NPTXFEMP) { |
5b7d70c6 BD |
2856 | dev_dbg(hsotg->dev, "NPTxFEmp\n"); |
2857 | ||
8b9bc460 LM |
2858 | /* |
2859 | * Disable the interrupt to stop it happening again | |
5b7d70c6 | 2860 | * unless one of these endpoint routines decides that |
8b9bc460 LM |
2861 | * it needs re-enabling |
2862 | */ | |
5b7d70c6 | 2863 | |
1f91b4cc FB |
2864 | dwc2_hsotg_disable_gsint(hsotg, GINTSTS_NPTXFEMP); |
2865 | dwc2_hsotg_irq_fifoempty(hsotg, false); | |
5b7d70c6 BD |
2866 | } |
2867 | ||
47a1685f | 2868 | if (gintsts & GINTSTS_PTXFEMP) { |
5b7d70c6 BD |
2869 | dev_dbg(hsotg->dev, "PTxFEmp\n"); |
2870 | ||
94cb8fd6 | 2871 | /* See note in GINTSTS_NPTxFEmp */ |
5b7d70c6 | 2872 | |
1f91b4cc FB |
2873 | dwc2_hsotg_disable_gsint(hsotg, GINTSTS_PTXFEMP); |
2874 | dwc2_hsotg_irq_fifoempty(hsotg, true); | |
5b7d70c6 BD |
2875 | } |
2876 | ||
47a1685f | 2877 | if (gintsts & GINTSTS_RXFLVL) { |
8b9bc460 LM |
2878 | /* |
2879 | * note, since GINTSTS_RxFLvl doubles as FIFO-not-empty, | |
1f91b4cc | 2880 | * we need to retry dwc2_hsotg_handle_rx if this is still |
8b9bc460 LM |
2881 | * set. |
2882 | */ | |
5b7d70c6 | 2883 | |
1f91b4cc | 2884 | dwc2_hsotg_handle_rx(hsotg); |
5b7d70c6 BD |
2885 | } |
2886 | ||
47a1685f | 2887 | if (gintsts & GINTSTS_ERLYSUSP) { |
94cb8fd6 | 2888 | dev_dbg(hsotg->dev, "GINTSTS_ErlySusp\n"); |
95c8bc36 | 2889 | dwc2_writel(GINTSTS_ERLYSUSP, hsotg->regs + GINTSTS); |
5b7d70c6 BD |
2890 | } |
2891 | ||
8b9bc460 LM |
2892 | /* |
2893 | * these next two seem to crop-up occasionally causing the core | |
5b7d70c6 | 2894 | * to shutdown the USB transfer, so try clearing them and logging |
8b9bc460 LM |
2895 | * the occurrence. |
2896 | */ | |
5b7d70c6 | 2897 | |
47a1685f | 2898 | if (gintsts & GINTSTS_GOUTNAKEFF) { |
837e9f00 VM |
2899 | u8 idx; |
2900 | u32 epctrl; | |
2901 | u32 gintmsk; | |
2902 | struct dwc2_hsotg_ep *hs_ep; | |
2903 | ||
2904 | /* Mask this interrupt */ | |
2905 | gintmsk = dwc2_readl(hsotg->regs + GINTMSK); | |
2906 | gintmsk &= ~GINTSTS_GOUTNAKEFF; | |
2907 | dwc2_writel(gintmsk, hsotg->regs + GINTMSK); | |
2908 | ||
2909 | dev_dbg(hsotg->dev, "GOUTNakEff triggered\n"); | |
2910 | for (idx = 1; idx <= hsotg->num_of_eps; idx++) { | |
2911 | hs_ep = hsotg->eps_out[idx]; | |
2912 | epctrl = dwc2_readl(hsotg->regs + DOEPCTL(idx)); | |
2913 | ||
2914 | if ((epctrl & DXEPCTL_EPENA) && hs_ep->isochronous) { | |
2915 | epctrl |= DXEPCTL_SNAK; | |
2916 | epctrl |= DXEPCTL_EPDIS; | |
2917 | dwc2_writel(epctrl, hsotg->regs + DOEPCTL(idx)); | |
2918 | } | |
2919 | } | |
a3395f0d | 2920 | |
837e9f00 | 2921 | /* This interrupt bit is cleared in DXEPINT_EPDISBLD handler */ |
5b7d70c6 BD |
2922 | } |
2923 | ||
47a1685f | 2924 | if (gintsts & GINTSTS_GINNAKEFF) { |
5b7d70c6 BD |
2925 | dev_info(hsotg->dev, "GINNakEff triggered\n"); |
2926 | ||
3be99cd0 | 2927 | __orr32(hsotg->regs + DCTL, DCTL_CGNPINNAK); |
a3395f0d | 2928 | |
1f91b4cc | 2929 | dwc2_hsotg_dump(hsotg); |
5b7d70c6 BD |
2930 | } |
2931 | ||
381fc8f8 VM |
2932 | if (gintsts & GINTSTS_INCOMPL_SOIN) |
2933 | dwc2_gadget_handle_incomplete_isoc_in(hsotg); | |
ec1f9d9f | 2934 | |
381fc8f8 VM |
2935 | if (gintsts & GINTSTS_INCOMPL_SOOUT) |
2936 | dwc2_gadget_handle_incomplete_isoc_out(hsotg); | |
ec1f9d9f | 2937 | |
8b9bc460 LM |
2938 | /* |
2939 | * if we've had fifo events, we should try and go around the | |
2940 | * loop again to see if there's any point in returning yet. | |
2941 | */ | |
5b7d70c6 BD |
2942 | |
2943 | if (gintsts & IRQ_RETRY_MASK && --retry_count > 0) | |
2944 | goto irq_retry; | |
2945 | ||
5ad1d316 LM |
2946 | spin_unlock(&hsotg->lock); |
2947 | ||
5b7d70c6 BD |
2948 | return IRQ_HANDLED; |
2949 | } | |
2950 | ||
2951 | /** | |
1f91b4cc | 2952 | * dwc2_hsotg_ep_enable - enable the given endpoint |
5b7d70c6 BD |
2953 | * @ep: The USB endpint to configure |
2954 | * @desc: The USB endpoint descriptor to configure with. | |
2955 | * | |
2956 | * This is called from the USB gadget code's usb_ep_enable(). | |
8b9bc460 | 2957 | */ |
1f91b4cc | 2958 | static int dwc2_hsotg_ep_enable(struct usb_ep *ep, |
5b7d70c6 BD |
2959 | const struct usb_endpoint_descriptor *desc) |
2960 | { | |
1f91b4cc | 2961 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 2962 | struct dwc2_hsotg *hsotg = hs_ep->parent; |
5b7d70c6 | 2963 | unsigned long flags; |
ca4c55ad | 2964 | unsigned int index = hs_ep->index; |
5b7d70c6 BD |
2965 | u32 epctrl_reg; |
2966 | u32 epctrl; | |
2967 | u32 mps; | |
ee2c40de | 2968 | u32 mc; |
837e9f00 | 2969 | u32 mask; |
ca4c55ad MYK |
2970 | unsigned int dir_in; |
2971 | unsigned int i, val, size; | |
19c190f9 | 2972 | int ret = 0; |
5b7d70c6 BD |
2973 | |
2974 | dev_dbg(hsotg->dev, | |
2975 | "%s: ep %s: a 0x%02x, attr 0x%02x, mps 0x%04x, intr %d\n", | |
2976 | __func__, ep->name, desc->bEndpointAddress, desc->bmAttributes, | |
2977 | desc->wMaxPacketSize, desc->bInterval); | |
2978 | ||
2979 | /* not to be called for EP0 */ | |
8c3d6092 VA |
2980 | if (index == 0) { |
2981 | dev_err(hsotg->dev, "%s: called for EP 0\n", __func__); | |
2982 | return -EINVAL; | |
2983 | } | |
5b7d70c6 BD |
2984 | |
2985 | dir_in = (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) ? 1 : 0; | |
2986 | if (dir_in != hs_ep->dir_in) { | |
2987 | dev_err(hsotg->dev, "%s: direction mismatch!\n", __func__); | |
2988 | return -EINVAL; | |
2989 | } | |
2990 | ||
29cc8897 | 2991 | mps = usb_endpoint_maxp(desc); |
ee2c40de | 2992 | mc = usb_endpoint_maxp_mult(desc); |
5b7d70c6 | 2993 | |
1f91b4cc | 2994 | /* note, we handle this here instead of dwc2_hsotg_set_ep_maxpacket */ |
5b7d70c6 | 2995 | |
94cb8fd6 | 2996 | epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index); |
95c8bc36 | 2997 | epctrl = dwc2_readl(hsotg->regs + epctrl_reg); |
5b7d70c6 BD |
2998 | |
2999 | dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x from 0x%08x\n", | |
3000 | __func__, epctrl, epctrl_reg); | |
3001 | ||
22258f49 | 3002 | spin_lock_irqsave(&hsotg->lock, flags); |
5b7d70c6 | 3003 | |
47a1685f DN |
3004 | epctrl &= ~(DXEPCTL_EPTYPE_MASK | DXEPCTL_MPS_MASK); |
3005 | epctrl |= DXEPCTL_MPS(mps); | |
5b7d70c6 | 3006 | |
8b9bc460 LM |
3007 | /* |
3008 | * mark the endpoint as active, otherwise the core may ignore | |
3009 | * transactions entirely for this endpoint | |
3010 | */ | |
47a1685f | 3011 | epctrl |= DXEPCTL_USBACTEP; |
5b7d70c6 | 3012 | |
5b7d70c6 | 3013 | /* update the endpoint state */ |
ee2c40de | 3014 | dwc2_hsotg_set_ep_maxpacket(hsotg, hs_ep->index, mps, mc, dir_in); |
5b7d70c6 BD |
3015 | |
3016 | /* default, set to non-periodic */ | |
1479e841 | 3017 | hs_ep->isochronous = 0; |
5b7d70c6 | 3018 | hs_ep->periodic = 0; |
a18ed7b0 | 3019 | hs_ep->halted = 0; |
1479e841 | 3020 | hs_ep->interval = desc->bInterval; |
4fca54aa | 3021 | |
5b7d70c6 BD |
3022 | switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) { |
3023 | case USB_ENDPOINT_XFER_ISOC: | |
47a1685f DN |
3024 | epctrl |= DXEPCTL_EPTYPE_ISO; |
3025 | epctrl |= DXEPCTL_SETEVENFR; | |
1479e841 | 3026 | hs_ep->isochronous = 1; |
142bd33f | 3027 | hs_ep->interval = 1 << (desc->bInterval - 1); |
837e9f00 VM |
3028 | hs_ep->target_frame = TARGET_FRAME_INITIAL; |
3029 | if (dir_in) { | |
1479e841 | 3030 | hs_ep->periodic = 1; |
837e9f00 VM |
3031 | mask = dwc2_readl(hsotg->regs + DIEPMSK); |
3032 | mask |= DIEPMSK_NAKMSK; | |
3033 | dwc2_writel(mask, hsotg->regs + DIEPMSK); | |
3034 | } else { | |
3035 | mask = dwc2_readl(hsotg->regs + DOEPMSK); | |
3036 | mask |= DOEPMSK_OUTTKNEPDISMSK; | |
3037 | dwc2_writel(mask, hsotg->regs + DOEPMSK); | |
3038 | } | |
1479e841 | 3039 | break; |
5b7d70c6 BD |
3040 | |
3041 | case USB_ENDPOINT_XFER_BULK: | |
47a1685f | 3042 | epctrl |= DXEPCTL_EPTYPE_BULK; |
5b7d70c6 BD |
3043 | break; |
3044 | ||
3045 | case USB_ENDPOINT_XFER_INT: | |
b203d0a2 | 3046 | if (dir_in) |
5b7d70c6 | 3047 | hs_ep->periodic = 1; |
5b7d70c6 | 3048 | |
142bd33f VM |
3049 | if (hsotg->gadget.speed == USB_SPEED_HIGH) |
3050 | hs_ep->interval = 1 << (desc->bInterval - 1); | |
3051 | ||
47a1685f | 3052 | epctrl |= DXEPCTL_EPTYPE_INTERRUPT; |
5b7d70c6 BD |
3053 | break; |
3054 | ||
3055 | case USB_ENDPOINT_XFER_CONTROL: | |
47a1685f | 3056 | epctrl |= DXEPCTL_EPTYPE_CONTROL; |
5b7d70c6 BD |
3057 | break; |
3058 | } | |
3059 | ||
8b9bc460 LM |
3060 | /* |
3061 | * if the hardware has dedicated fifos, we must give each IN EP | |
10aebc77 BD |
3062 | * a unique tx-fifo even if it is non-periodic. |
3063 | */ | |
21f3bb52 | 3064 | if (dir_in && hsotg->dedicated_fifos) { |
ca4c55ad MYK |
3065 | u32 fifo_index = 0; |
3066 | u32 fifo_size = UINT_MAX; | |
b203d0a2 | 3067 | size = hs_ep->ep.maxpacket*hs_ep->mc; |
5f2196bd | 3068 | for (i = 1; i < hsotg->num_of_eps; ++i) { |
b203d0a2 RB |
3069 | if (hsotg->fifo_map & (1<<i)) |
3070 | continue; | |
95c8bc36 | 3071 | val = dwc2_readl(hsotg->regs + DPTXFSIZN(i)); |
b203d0a2 RB |
3072 | val = (val >> FIFOSIZE_DEPTH_SHIFT)*4; |
3073 | if (val < size) | |
3074 | continue; | |
ca4c55ad MYK |
3075 | /* Search for smallest acceptable fifo */ |
3076 | if (val < fifo_size) { | |
3077 | fifo_size = val; | |
3078 | fifo_index = i; | |
3079 | } | |
b203d0a2 | 3080 | } |
ca4c55ad | 3081 | if (!fifo_index) { |
5f2196bd MYK |
3082 | dev_err(hsotg->dev, |
3083 | "%s: No suitable fifo found\n", __func__); | |
b585a48b SM |
3084 | ret = -ENOMEM; |
3085 | goto error; | |
3086 | } | |
ca4c55ad MYK |
3087 | hsotg->fifo_map |= 1 << fifo_index; |
3088 | epctrl |= DXEPCTL_TXFNUM(fifo_index); | |
3089 | hs_ep->fifo_index = fifo_index; | |
3090 | hs_ep->fifo_size = fifo_size; | |
b203d0a2 | 3091 | } |
10aebc77 | 3092 | |
5b7d70c6 | 3093 | /* for non control endpoints, set PID to D0 */ |
837e9f00 | 3094 | if (index && !hs_ep->isochronous) |
47a1685f | 3095 | epctrl |= DXEPCTL_SETD0PID; |
5b7d70c6 BD |
3096 | |
3097 | dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n", | |
3098 | __func__, epctrl); | |
3099 | ||
95c8bc36 | 3100 | dwc2_writel(epctrl, hsotg->regs + epctrl_reg); |
5b7d70c6 | 3101 | dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x\n", |
95c8bc36 | 3102 | __func__, dwc2_readl(hsotg->regs + epctrl_reg)); |
5b7d70c6 BD |
3103 | |
3104 | /* enable the endpoint interrupt */ | |
1f91b4cc | 3105 | dwc2_hsotg_ctrl_epint(hsotg, index, dir_in, 1); |
5b7d70c6 | 3106 | |
b585a48b | 3107 | error: |
22258f49 | 3108 | spin_unlock_irqrestore(&hsotg->lock, flags); |
19c190f9 | 3109 | return ret; |
5b7d70c6 BD |
3110 | } |
3111 | ||
8b9bc460 | 3112 | /** |
1f91b4cc | 3113 | * dwc2_hsotg_ep_disable - disable given endpoint |
8b9bc460 LM |
3114 | * @ep: The endpoint to disable. |
3115 | */ | |
1f91b4cc | 3116 | static int dwc2_hsotg_ep_disable(struct usb_ep *ep) |
5b7d70c6 | 3117 | { |
1f91b4cc | 3118 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 3119 | struct dwc2_hsotg *hsotg = hs_ep->parent; |
5b7d70c6 BD |
3120 | int dir_in = hs_ep->dir_in; |
3121 | int index = hs_ep->index; | |
3122 | unsigned long flags; | |
3123 | u32 epctrl_reg; | |
3124 | u32 ctrl; | |
3125 | ||
1e011293 | 3126 | dev_dbg(hsotg->dev, "%s(ep %p)\n", __func__, ep); |
5b7d70c6 | 3127 | |
c6f5c050 | 3128 | if (ep == &hsotg->eps_out[0]->ep) { |
5b7d70c6 BD |
3129 | dev_err(hsotg->dev, "%s: called for ep0\n", __func__); |
3130 | return -EINVAL; | |
3131 | } | |
3132 | ||
94cb8fd6 | 3133 | epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index); |
5b7d70c6 | 3134 | |
5ad1d316 | 3135 | spin_lock_irqsave(&hsotg->lock, flags); |
5b7d70c6 | 3136 | |
95c8bc36 | 3137 | ctrl = dwc2_readl(hsotg->regs + epctrl_reg); |
47a1685f DN |
3138 | ctrl &= ~DXEPCTL_EPENA; |
3139 | ctrl &= ~DXEPCTL_USBACTEP; | |
3140 | ctrl |= DXEPCTL_SNAK; | |
5b7d70c6 BD |
3141 | |
3142 | dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl); | |
95c8bc36 | 3143 | dwc2_writel(ctrl, hsotg->regs + epctrl_reg); |
5b7d70c6 BD |
3144 | |
3145 | /* disable endpoint interrupts */ | |
1f91b4cc | 3146 | dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 0); |
5b7d70c6 | 3147 | |
1141ea01 MYK |
3148 | /* terminate all requests with shutdown */ |
3149 | kill_all_requests(hsotg, hs_ep, -ESHUTDOWN); | |
3150 | ||
1c07b20e RB |
3151 | hsotg->fifo_map &= ~(1 << hs_ep->fifo_index); |
3152 | hs_ep->fifo_index = 0; | |
3153 | hs_ep->fifo_size = 0; | |
3154 | ||
22258f49 | 3155 | spin_unlock_irqrestore(&hsotg->lock, flags); |
5b7d70c6 BD |
3156 | return 0; |
3157 | } | |
3158 | ||
3159 | /** | |
3160 | * on_list - check request is on the given endpoint | |
3161 | * @ep: The endpoint to check. | |
3162 | * @test: The request to test if it is on the endpoint. | |
8b9bc460 | 3163 | */ |
1f91b4cc | 3164 | static bool on_list(struct dwc2_hsotg_ep *ep, struct dwc2_hsotg_req *test) |
5b7d70c6 | 3165 | { |
1f91b4cc | 3166 | struct dwc2_hsotg_req *req, *treq; |
5b7d70c6 BD |
3167 | |
3168 | list_for_each_entry_safe(req, treq, &ep->queue, queue) { | |
3169 | if (req == test) | |
3170 | return true; | |
3171 | } | |
3172 | ||
3173 | return false; | |
3174 | } | |
3175 | ||
c524dd5f MYK |
3176 | static int dwc2_hsotg_wait_bit_set(struct dwc2_hsotg *hs_otg, u32 reg, |
3177 | u32 bit, u32 timeout) | |
3178 | { | |
3179 | u32 i; | |
3180 | ||
3181 | for (i = 0; i < timeout; i++) { | |
3182 | if (dwc2_readl(hs_otg->regs + reg) & bit) | |
3183 | return 0; | |
3184 | udelay(1); | |
3185 | } | |
3186 | ||
3187 | return -ETIMEDOUT; | |
3188 | } | |
3189 | ||
3190 | static void dwc2_hsotg_ep_stop_xfr(struct dwc2_hsotg *hsotg, | |
3191 | struct dwc2_hsotg_ep *hs_ep) | |
3192 | { | |
3193 | u32 epctrl_reg; | |
3194 | u32 epint_reg; | |
3195 | ||
3196 | epctrl_reg = hs_ep->dir_in ? DIEPCTL(hs_ep->index) : | |
3197 | DOEPCTL(hs_ep->index); | |
3198 | epint_reg = hs_ep->dir_in ? DIEPINT(hs_ep->index) : | |
3199 | DOEPINT(hs_ep->index); | |
3200 | ||
3201 | dev_dbg(hsotg->dev, "%s: stopping transfer on %s\n", __func__, | |
3202 | hs_ep->name); | |
3203 | if (hs_ep->dir_in) { | |
3204 | __orr32(hsotg->regs + epctrl_reg, DXEPCTL_SNAK); | |
3205 | /* Wait for Nak effect */ | |
3206 | if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg, | |
3207 | DXEPINT_INEPNAKEFF, 100)) | |
3208 | dev_warn(hsotg->dev, | |
3209 | "%s: timeout DIEPINT.NAKEFF\n", __func__); | |
3210 | } else { | |
6b58cb07 VM |
3211 | if (!(dwc2_readl(hsotg->regs + GINTSTS) & GINTSTS_GOUTNAKEFF)) |
3212 | __orr32(hsotg->regs + DCTL, DCTL_SGOUTNAK); | |
c524dd5f MYK |
3213 | |
3214 | /* Wait for global nak to take effect */ | |
3215 | if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS, | |
0676c7e7 | 3216 | GINTSTS_GOUTNAKEFF, 100)) |
c524dd5f | 3217 | dev_warn(hsotg->dev, |
0676c7e7 | 3218 | "%s: timeout GINTSTS.GOUTNAKEFF\n", __func__); |
c524dd5f MYK |
3219 | } |
3220 | ||
3221 | /* Disable ep */ | |
3222 | __orr32(hsotg->regs + epctrl_reg, DXEPCTL_EPDIS | DXEPCTL_SNAK); | |
3223 | ||
3224 | /* Wait for ep to be disabled */ | |
3225 | if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg, DXEPINT_EPDISBLD, 100)) | |
3226 | dev_warn(hsotg->dev, | |
3227 | "%s: timeout DOEPCTL.EPDisable\n", __func__); | |
3228 | ||
3229 | if (hs_ep->dir_in) { | |
3230 | if (hsotg->dedicated_fifos) { | |
3231 | dwc2_writel(GRSTCTL_TXFNUM(hs_ep->fifo_index) | | |
3232 | GRSTCTL_TXFFLSH, hsotg->regs + GRSTCTL); | |
3233 | /* Wait for fifo flush */ | |
3234 | if (dwc2_hsotg_wait_bit_set(hsotg, GRSTCTL, | |
3235 | GRSTCTL_TXFFLSH, 100)) | |
3236 | dev_warn(hsotg->dev, | |
3237 | "%s: timeout flushing fifos\n", | |
3238 | __func__); | |
3239 | } | |
3240 | /* TODO: Flush shared tx fifo */ | |
3241 | } else { | |
3242 | /* Remove global NAKs */ | |
0676c7e7 | 3243 | __bic32(hsotg->regs + DCTL, DCTL_SGOUTNAK); |
c524dd5f MYK |
3244 | } |
3245 | } | |
3246 | ||
8b9bc460 | 3247 | /** |
1f91b4cc | 3248 | * dwc2_hsotg_ep_dequeue - dequeue given endpoint |
8b9bc460 LM |
3249 | * @ep: The endpoint to dequeue. |
3250 | * @req: The request to be removed from a queue. | |
3251 | */ | |
1f91b4cc | 3252 | static int dwc2_hsotg_ep_dequeue(struct usb_ep *ep, struct usb_request *req) |
5b7d70c6 | 3253 | { |
1f91b4cc FB |
3254 | struct dwc2_hsotg_req *hs_req = our_req(req); |
3255 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); | |
941fcce4 | 3256 | struct dwc2_hsotg *hs = hs_ep->parent; |
5b7d70c6 BD |
3257 | unsigned long flags; |
3258 | ||
1e011293 | 3259 | dev_dbg(hs->dev, "ep_dequeue(%p,%p)\n", ep, req); |
5b7d70c6 | 3260 | |
22258f49 | 3261 | spin_lock_irqsave(&hs->lock, flags); |
5b7d70c6 BD |
3262 | |
3263 | if (!on_list(hs_ep, hs_req)) { | |
22258f49 | 3264 | spin_unlock_irqrestore(&hs->lock, flags); |
5b7d70c6 BD |
3265 | return -EINVAL; |
3266 | } | |
3267 | ||
c524dd5f MYK |
3268 | /* Dequeue already started request */ |
3269 | if (req == &hs_ep->req->req) | |
3270 | dwc2_hsotg_ep_stop_xfr(hs, hs_ep); | |
3271 | ||
1f91b4cc | 3272 | dwc2_hsotg_complete_request(hs, hs_ep, hs_req, -ECONNRESET); |
22258f49 | 3273 | spin_unlock_irqrestore(&hs->lock, flags); |
5b7d70c6 BD |
3274 | |
3275 | return 0; | |
3276 | } | |
3277 | ||
8b9bc460 | 3278 | /** |
1f91b4cc | 3279 | * dwc2_hsotg_ep_sethalt - set halt on a given endpoint |
8b9bc460 LM |
3280 | * @ep: The endpoint to set halt. |
3281 | * @value: Set or unset the halt. | |
51da43b5 VA |
3282 | * @now: If true, stall the endpoint now. Otherwise return -EAGAIN if |
3283 | * the endpoint is busy processing requests. | |
3284 | * | |
3285 | * We need to stall the endpoint immediately if request comes from set_feature | |
3286 | * protocol command handler. | |
8b9bc460 | 3287 | */ |
51da43b5 | 3288 | static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now) |
5b7d70c6 | 3289 | { |
1f91b4cc | 3290 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 3291 | struct dwc2_hsotg *hs = hs_ep->parent; |
5b7d70c6 | 3292 | int index = hs_ep->index; |
5b7d70c6 BD |
3293 | u32 epreg; |
3294 | u32 epctl; | |
9c39ddc6 | 3295 | u32 xfertype; |
5b7d70c6 BD |
3296 | |
3297 | dev_info(hs->dev, "%s(ep %p %s, %d)\n", __func__, ep, ep->name, value); | |
3298 | ||
c9f721b2 RB |
3299 | if (index == 0) { |
3300 | if (value) | |
1f91b4cc | 3301 | dwc2_hsotg_stall_ep0(hs); |
c9f721b2 RB |
3302 | else |
3303 | dev_warn(hs->dev, | |
3304 | "%s: can't clear halt on ep0\n", __func__); | |
3305 | return 0; | |
3306 | } | |
3307 | ||
15186f10 VA |
3308 | if (hs_ep->isochronous) { |
3309 | dev_err(hs->dev, "%s is Isochronous Endpoint\n", ep->name); | |
3310 | return -EINVAL; | |
3311 | } | |
3312 | ||
51da43b5 VA |
3313 | if (!now && value && !list_empty(&hs_ep->queue)) { |
3314 | dev_dbg(hs->dev, "%s request is pending, cannot halt\n", | |
3315 | ep->name); | |
3316 | return -EAGAIN; | |
3317 | } | |
3318 | ||
c6f5c050 MYK |
3319 | if (hs_ep->dir_in) { |
3320 | epreg = DIEPCTL(index); | |
95c8bc36 | 3321 | epctl = dwc2_readl(hs->regs + epreg); |
c6f5c050 MYK |
3322 | |
3323 | if (value) { | |
5a350d53 | 3324 | epctl |= DXEPCTL_STALL | DXEPCTL_SNAK; |
c6f5c050 MYK |
3325 | if (epctl & DXEPCTL_EPENA) |
3326 | epctl |= DXEPCTL_EPDIS; | |
3327 | } else { | |
3328 | epctl &= ~DXEPCTL_STALL; | |
3329 | xfertype = epctl & DXEPCTL_EPTYPE_MASK; | |
3330 | if (xfertype == DXEPCTL_EPTYPE_BULK || | |
3331 | xfertype == DXEPCTL_EPTYPE_INTERRUPT) | |
3332 | epctl |= DXEPCTL_SETD0PID; | |
3333 | } | |
95c8bc36 | 3334 | dwc2_writel(epctl, hs->regs + epreg); |
9c39ddc6 | 3335 | } else { |
5b7d70c6 | 3336 | |
c6f5c050 | 3337 | epreg = DOEPCTL(index); |
95c8bc36 | 3338 | epctl = dwc2_readl(hs->regs + epreg); |
5b7d70c6 | 3339 | |
c6f5c050 MYK |
3340 | if (value) |
3341 | epctl |= DXEPCTL_STALL; | |
3342 | else { | |
3343 | epctl &= ~DXEPCTL_STALL; | |
3344 | xfertype = epctl & DXEPCTL_EPTYPE_MASK; | |
3345 | if (xfertype == DXEPCTL_EPTYPE_BULK || | |
3346 | xfertype == DXEPCTL_EPTYPE_INTERRUPT) | |
3347 | epctl |= DXEPCTL_SETD0PID; | |
3348 | } | |
95c8bc36 | 3349 | dwc2_writel(epctl, hs->regs + epreg); |
9c39ddc6 | 3350 | } |
5b7d70c6 | 3351 | |
a18ed7b0 RB |
3352 | hs_ep->halted = value; |
3353 | ||
5b7d70c6 BD |
3354 | return 0; |
3355 | } | |
3356 | ||
5ad1d316 | 3357 | /** |
1f91b4cc | 3358 | * dwc2_hsotg_ep_sethalt_lock - set halt on a given endpoint with lock held |
5ad1d316 LM |
3359 | * @ep: The endpoint to set halt. |
3360 | * @value: Set or unset the halt. | |
3361 | */ | |
1f91b4cc | 3362 | static int dwc2_hsotg_ep_sethalt_lock(struct usb_ep *ep, int value) |
5ad1d316 | 3363 | { |
1f91b4cc | 3364 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 3365 | struct dwc2_hsotg *hs = hs_ep->parent; |
5ad1d316 LM |
3366 | unsigned long flags = 0; |
3367 | int ret = 0; | |
3368 | ||
3369 | spin_lock_irqsave(&hs->lock, flags); | |
51da43b5 | 3370 | ret = dwc2_hsotg_ep_sethalt(ep, value, false); |
5ad1d316 LM |
3371 | spin_unlock_irqrestore(&hs->lock, flags); |
3372 | ||
3373 | return ret; | |
3374 | } | |
3375 | ||
1f91b4cc FB |
3376 | static struct usb_ep_ops dwc2_hsotg_ep_ops = { |
3377 | .enable = dwc2_hsotg_ep_enable, | |
3378 | .disable = dwc2_hsotg_ep_disable, | |
3379 | .alloc_request = dwc2_hsotg_ep_alloc_request, | |
3380 | .free_request = dwc2_hsotg_ep_free_request, | |
3381 | .queue = dwc2_hsotg_ep_queue_lock, | |
3382 | .dequeue = dwc2_hsotg_ep_dequeue, | |
3383 | .set_halt = dwc2_hsotg_ep_sethalt_lock, | |
25985edc | 3384 | /* note, don't believe we have any call for the fifo routines */ |
5b7d70c6 BD |
3385 | }; |
3386 | ||
8b9bc460 | 3387 | /** |
1f91b4cc | 3388 | * dwc2_hsotg_init - initalize the usb core |
8b9bc460 LM |
3389 | * @hsotg: The driver state |
3390 | */ | |
1f91b4cc | 3391 | static void dwc2_hsotg_init(struct dwc2_hsotg *hsotg) |
b3f489b2 | 3392 | { |
fa4a8d72 | 3393 | u32 trdtim; |
ecd9a7ad | 3394 | u32 usbcfg; |
b3f489b2 LM |
3395 | /* unmask subset of endpoint interrupts */ |
3396 | ||
95c8bc36 AS |
3397 | dwc2_writel(DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK | |
3398 | DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK, | |
3399 | hsotg->regs + DIEPMSK); | |
b3f489b2 | 3400 | |
95c8bc36 AS |
3401 | dwc2_writel(DOEPMSK_SETUPMSK | DOEPMSK_AHBERRMSK | |
3402 | DOEPMSK_EPDISBLDMSK | DOEPMSK_XFERCOMPLMSK, | |
3403 | hsotg->regs + DOEPMSK); | |
b3f489b2 | 3404 | |
95c8bc36 | 3405 | dwc2_writel(0, hsotg->regs + DAINTMSK); |
b3f489b2 LM |
3406 | |
3407 | /* Be in disconnected state until gadget is registered */ | |
47a1685f | 3408 | __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON); |
b3f489b2 | 3409 | |
b3f489b2 LM |
3410 | /* setup fifos */ |
3411 | ||
3412 | dev_dbg(hsotg->dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n", | |
95c8bc36 AS |
3413 | dwc2_readl(hsotg->regs + GRXFSIZ), |
3414 | dwc2_readl(hsotg->regs + GNPTXFSIZ)); | |
b3f489b2 | 3415 | |
1f91b4cc | 3416 | dwc2_hsotg_init_fifo(hsotg); |
b3f489b2 | 3417 | |
ecd9a7ad PR |
3418 | /* keep other bits untouched (so e.g. forced modes are not lost) */ |
3419 | usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); | |
3420 | usbcfg &= ~(GUSBCFG_TOUTCAL_MASK | GUSBCFG_PHYIF16 | GUSBCFG_SRPCAP | | |
3421 | GUSBCFG_HNPCAP); | |
3422 | ||
b3f489b2 | 3423 | /* set the PLL on, remove the HNP/SRP and set the PHY */ |
fa4a8d72 | 3424 | trdtim = (hsotg->phyif == GUSBCFG_PHYIF8) ? 9 : 5; |
ecd9a7ad PR |
3425 | usbcfg |= hsotg->phyif | GUSBCFG_TOUTCAL(7) | |
3426 | (trdtim << GUSBCFG_USBTRDTIM_SHIFT); | |
3427 | dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); | |
b3f489b2 | 3428 | |
f5090044 GH |
3429 | if (using_dma(hsotg)) |
3430 | __orr32(hsotg->regs + GAHBCFG, GAHBCFG_DMA_EN); | |
b3f489b2 LM |
3431 | } |
3432 | ||
8b9bc460 | 3433 | /** |
1f91b4cc | 3434 | * dwc2_hsotg_udc_start - prepare the udc for work |
8b9bc460 LM |
3435 | * @gadget: The usb gadget state |
3436 | * @driver: The usb gadget driver | |
3437 | * | |
3438 | * Perform initialization to prepare udc device and driver | |
3439 | * to work. | |
3440 | */ | |
1f91b4cc | 3441 | static int dwc2_hsotg_udc_start(struct usb_gadget *gadget, |
f65f0f10 | 3442 | struct usb_gadget_driver *driver) |
5b7d70c6 | 3443 | { |
941fcce4 | 3444 | struct dwc2_hsotg *hsotg = to_hsotg(gadget); |
5b9451f8 | 3445 | unsigned long flags; |
5b7d70c6 BD |
3446 | int ret; |
3447 | ||
3448 | if (!hsotg) { | |
a023da33 | 3449 | pr_err("%s: called with no device\n", __func__); |
5b7d70c6 BD |
3450 | return -ENODEV; |
3451 | } | |
3452 | ||
3453 | if (!driver) { | |
3454 | dev_err(hsotg->dev, "%s: no driver\n", __func__); | |
3455 | return -EINVAL; | |
3456 | } | |
3457 | ||
7177aed4 | 3458 | if (driver->max_speed < USB_SPEED_FULL) |
5b7d70c6 | 3459 | dev_err(hsotg->dev, "%s: bad speed\n", __func__); |
5b7d70c6 | 3460 | |
f65f0f10 | 3461 | if (!driver->setup) { |
5b7d70c6 BD |
3462 | dev_err(hsotg->dev, "%s: missing entry points\n", __func__); |
3463 | return -EINVAL; | |
3464 | } | |
3465 | ||
3466 | WARN_ON(hsotg->driver); | |
3467 | ||
3468 | driver->driver.bus = NULL; | |
3469 | hsotg->driver = driver; | |
7d7b2292 | 3470 | hsotg->gadget.dev.of_node = hsotg->dev->of_node; |
5b7d70c6 BD |
3471 | hsotg->gadget.speed = USB_SPEED_UNKNOWN; |
3472 | ||
09a75e85 MS |
3473 | if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) { |
3474 | ret = dwc2_lowlevel_hw_enable(hsotg); | |
3475 | if (ret) | |
3476 | goto err; | |
5b7d70c6 BD |
3477 | } |
3478 | ||
f6c01592 GH |
3479 | if (!IS_ERR_OR_NULL(hsotg->uphy)) |
3480 | otg_set_peripheral(hsotg->uphy->otg, &hsotg->gadget); | |
c816c47f | 3481 | |
5b9451f8 | 3482 | spin_lock_irqsave(&hsotg->lock, flags); |
d0f0ac56 JY |
3483 | if (dwc2_hw_is_device(hsotg)) { |
3484 | dwc2_hsotg_init(hsotg); | |
3485 | dwc2_hsotg_core_init_disconnected(hsotg, false); | |
3486 | } | |
3487 | ||
dc6e69e6 | 3488 | hsotg->enabled = 0; |
5b9451f8 MS |
3489 | spin_unlock_irqrestore(&hsotg->lock, flags); |
3490 | ||
5b7d70c6 | 3491 | dev_info(hsotg->dev, "bound driver %s\n", driver->driver.name); |
5b9451f8 | 3492 | |
5b7d70c6 BD |
3493 | return 0; |
3494 | ||
3495 | err: | |
3496 | hsotg->driver = NULL; | |
5b7d70c6 BD |
3497 | return ret; |
3498 | } | |
3499 | ||
8b9bc460 | 3500 | /** |
1f91b4cc | 3501 | * dwc2_hsotg_udc_stop - stop the udc |
8b9bc460 LM |
3502 | * @gadget: The usb gadget state |
3503 | * @driver: The usb gadget driver | |
3504 | * | |
3505 | * Stop udc hw block and stay tunned for future transmissions | |
3506 | */ | |
1f91b4cc | 3507 | static int dwc2_hsotg_udc_stop(struct usb_gadget *gadget) |
5b7d70c6 | 3508 | { |
941fcce4 | 3509 | struct dwc2_hsotg *hsotg = to_hsotg(gadget); |
2b19a52c | 3510 | unsigned long flags = 0; |
5b7d70c6 BD |
3511 | int ep; |
3512 | ||
3513 | if (!hsotg) | |
3514 | return -ENODEV; | |
3515 | ||
5b7d70c6 | 3516 | /* all endpoints should be shutdown */ |
c6f5c050 MYK |
3517 | for (ep = 1; ep < hsotg->num_of_eps; ep++) { |
3518 | if (hsotg->eps_in[ep]) | |
1f91b4cc | 3519 | dwc2_hsotg_ep_disable(&hsotg->eps_in[ep]->ep); |
c6f5c050 | 3520 | if (hsotg->eps_out[ep]) |
1f91b4cc | 3521 | dwc2_hsotg_ep_disable(&hsotg->eps_out[ep]->ep); |
c6f5c050 | 3522 | } |
5b7d70c6 | 3523 | |
2b19a52c LM |
3524 | spin_lock_irqsave(&hsotg->lock, flags); |
3525 | ||
32805c35 | 3526 | hsotg->driver = NULL; |
5b7d70c6 | 3527 | hsotg->gadget.speed = USB_SPEED_UNKNOWN; |
dc6e69e6 | 3528 | hsotg->enabled = 0; |
5b7d70c6 | 3529 | |
2b19a52c LM |
3530 | spin_unlock_irqrestore(&hsotg->lock, flags); |
3531 | ||
f6c01592 GH |
3532 | if (!IS_ERR_OR_NULL(hsotg->uphy)) |
3533 | otg_set_peripheral(hsotg->uphy->otg, NULL); | |
c816c47f | 3534 | |
09a75e85 MS |
3535 | if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) |
3536 | dwc2_lowlevel_hw_disable(hsotg); | |
5b7d70c6 BD |
3537 | |
3538 | return 0; | |
3539 | } | |
5b7d70c6 | 3540 | |
8b9bc460 | 3541 | /** |
1f91b4cc | 3542 | * dwc2_hsotg_gadget_getframe - read the frame number |
8b9bc460 LM |
3543 | * @gadget: The usb gadget state |
3544 | * | |
3545 | * Read the {micro} frame number | |
3546 | */ | |
1f91b4cc | 3547 | static int dwc2_hsotg_gadget_getframe(struct usb_gadget *gadget) |
5b7d70c6 | 3548 | { |
1f91b4cc | 3549 | return dwc2_hsotg_read_frameno(to_hsotg(gadget)); |
5b7d70c6 BD |
3550 | } |
3551 | ||
a188b689 | 3552 | /** |
1f91b4cc | 3553 | * dwc2_hsotg_pullup - connect/disconnect the USB PHY |
a188b689 LM |
3554 | * @gadget: The usb gadget state |
3555 | * @is_on: Current state of the USB PHY | |
3556 | * | |
3557 | * Connect/Disconnect the USB PHY pullup | |
3558 | */ | |
1f91b4cc | 3559 | static int dwc2_hsotg_pullup(struct usb_gadget *gadget, int is_on) |
a188b689 | 3560 | { |
941fcce4 | 3561 | struct dwc2_hsotg *hsotg = to_hsotg(gadget); |
a188b689 LM |
3562 | unsigned long flags = 0; |
3563 | ||
77ba9119 GH |
3564 | dev_dbg(hsotg->dev, "%s: is_on: %d op_state: %d\n", __func__, is_on, |
3565 | hsotg->op_state); | |
3566 | ||
3567 | /* Don't modify pullup state while in host mode */ | |
3568 | if (hsotg->op_state != OTG_STATE_B_PERIPHERAL) { | |
3569 | hsotg->enabled = is_on; | |
3570 | return 0; | |
3571 | } | |
a188b689 LM |
3572 | |
3573 | spin_lock_irqsave(&hsotg->lock, flags); | |
3574 | if (is_on) { | |
dc6e69e6 | 3575 | hsotg->enabled = 1; |
1f91b4cc FB |
3576 | dwc2_hsotg_core_init_disconnected(hsotg, false); |
3577 | dwc2_hsotg_core_connect(hsotg); | |
a188b689 | 3578 | } else { |
1f91b4cc FB |
3579 | dwc2_hsotg_core_disconnect(hsotg); |
3580 | dwc2_hsotg_disconnect(hsotg); | |
dc6e69e6 | 3581 | hsotg->enabled = 0; |
a188b689 LM |
3582 | } |
3583 | ||
3584 | hsotg->gadget.speed = USB_SPEED_UNKNOWN; | |
3585 | spin_unlock_irqrestore(&hsotg->lock, flags); | |
3586 | ||
3587 | return 0; | |
3588 | } | |
3589 | ||
1f91b4cc | 3590 | static int dwc2_hsotg_vbus_session(struct usb_gadget *gadget, int is_active) |
83d98223 GH |
3591 | { |
3592 | struct dwc2_hsotg *hsotg = to_hsotg(gadget); | |
3593 | unsigned long flags; | |
3594 | ||
3595 | dev_dbg(hsotg->dev, "%s: is_active: %d\n", __func__, is_active); | |
3596 | spin_lock_irqsave(&hsotg->lock, flags); | |
3597 | ||
61f7223b GH |
3598 | /* |
3599 | * If controller is hibernated, it must exit from hibernation | |
3600 | * before being initialized / de-initialized | |
3601 | */ | |
3602 | if (hsotg->lx_state == DWC2_L2) | |
3603 | dwc2_exit_hibernation(hsotg, false); | |
3604 | ||
83d98223 | 3605 | if (is_active) { |
cd0e641c | 3606 | hsotg->op_state = OTG_STATE_B_PERIPHERAL; |
065d3931 | 3607 | |
1f91b4cc | 3608 | dwc2_hsotg_core_init_disconnected(hsotg, false); |
83d98223 | 3609 | if (hsotg->enabled) |
1f91b4cc | 3610 | dwc2_hsotg_core_connect(hsotg); |
83d98223 | 3611 | } else { |
1f91b4cc FB |
3612 | dwc2_hsotg_core_disconnect(hsotg); |
3613 | dwc2_hsotg_disconnect(hsotg); | |
83d98223 GH |
3614 | } |
3615 | ||
3616 | spin_unlock_irqrestore(&hsotg->lock, flags); | |
3617 | return 0; | |
3618 | } | |
3619 | ||
596d696a | 3620 | /** |
1f91b4cc | 3621 | * dwc2_hsotg_vbus_draw - report bMaxPower field |
596d696a GH |
3622 | * @gadget: The usb gadget state |
3623 | * @mA: Amount of current | |
3624 | * | |
3625 | * Report how much power the device may consume to the phy. | |
3626 | */ | |
1f91b4cc | 3627 | static int dwc2_hsotg_vbus_draw(struct usb_gadget *gadget, unsigned mA) |
596d696a GH |
3628 | { |
3629 | struct dwc2_hsotg *hsotg = to_hsotg(gadget); | |
3630 | ||
3631 | if (IS_ERR_OR_NULL(hsotg->uphy)) | |
3632 | return -ENOTSUPP; | |
3633 | return usb_phy_set_power(hsotg->uphy, mA); | |
3634 | } | |
3635 | ||
1f91b4cc FB |
3636 | static const struct usb_gadget_ops dwc2_hsotg_gadget_ops = { |
3637 | .get_frame = dwc2_hsotg_gadget_getframe, | |
3638 | .udc_start = dwc2_hsotg_udc_start, | |
3639 | .udc_stop = dwc2_hsotg_udc_stop, | |
3640 | .pullup = dwc2_hsotg_pullup, | |
3641 | .vbus_session = dwc2_hsotg_vbus_session, | |
3642 | .vbus_draw = dwc2_hsotg_vbus_draw, | |
5b7d70c6 BD |
3643 | }; |
3644 | ||
3645 | /** | |
1f91b4cc | 3646 | * dwc2_hsotg_initep - initialise a single endpoint |
5b7d70c6 BD |
3647 | * @hsotg: The device state. |
3648 | * @hs_ep: The endpoint to be initialised. | |
3649 | * @epnum: The endpoint number | |
3650 | * | |
3651 | * Initialise the given endpoint (as part of the probe and device state | |
3652 | * creation) to give to the gadget driver. Setup the endpoint name, any | |
3653 | * direction information and other state that may be required. | |
3654 | */ | |
1f91b4cc FB |
3655 | static void dwc2_hsotg_initep(struct dwc2_hsotg *hsotg, |
3656 | struct dwc2_hsotg_ep *hs_ep, | |
c6f5c050 MYK |
3657 | int epnum, |
3658 | bool dir_in) | |
5b7d70c6 | 3659 | { |
5b7d70c6 BD |
3660 | char *dir; |
3661 | ||
3662 | if (epnum == 0) | |
3663 | dir = ""; | |
c6f5c050 | 3664 | else if (dir_in) |
5b7d70c6 | 3665 | dir = "in"; |
c6f5c050 MYK |
3666 | else |
3667 | dir = "out"; | |
5b7d70c6 | 3668 | |
c6f5c050 | 3669 | hs_ep->dir_in = dir_in; |
5b7d70c6 BD |
3670 | hs_ep->index = epnum; |
3671 | ||
3672 | snprintf(hs_ep->name, sizeof(hs_ep->name), "ep%d%s", epnum, dir); | |
3673 | ||
3674 | INIT_LIST_HEAD(&hs_ep->queue); | |
3675 | INIT_LIST_HEAD(&hs_ep->ep.ep_list); | |
3676 | ||
5b7d70c6 BD |
3677 | /* add to the list of endpoints known by the gadget driver */ |
3678 | if (epnum) | |
3679 | list_add_tail(&hs_ep->ep.ep_list, &hsotg->gadget.ep_list); | |
3680 | ||
3681 | hs_ep->parent = hsotg; | |
3682 | hs_ep->ep.name = hs_ep->name; | |
e117e742 | 3683 | usb_ep_set_maxpacket_limit(&hs_ep->ep, epnum ? 1024 : EP0_MPS_LIMIT); |
1f91b4cc | 3684 | hs_ep->ep.ops = &dwc2_hsotg_ep_ops; |
5b7d70c6 | 3685 | |
2954522f RB |
3686 | if (epnum == 0) { |
3687 | hs_ep->ep.caps.type_control = true; | |
3688 | } else { | |
3689 | hs_ep->ep.caps.type_iso = true; | |
3690 | hs_ep->ep.caps.type_bulk = true; | |
3691 | hs_ep->ep.caps.type_int = true; | |
3692 | } | |
3693 | ||
3694 | if (dir_in) | |
3695 | hs_ep->ep.caps.dir_in = true; | |
3696 | else | |
3697 | hs_ep->ep.caps.dir_out = true; | |
3698 | ||
8b9bc460 LM |
3699 | /* |
3700 | * if we're using dma, we need to set the next-endpoint pointer | |
5b7d70c6 BD |
3701 | * to be something valid. |
3702 | */ | |
3703 | ||
3704 | if (using_dma(hsotg)) { | |
47a1685f | 3705 | u32 next = DXEPCTL_NEXTEP((epnum + 1) % 15); |
c6f5c050 | 3706 | if (dir_in) |
95c8bc36 | 3707 | dwc2_writel(next, hsotg->regs + DIEPCTL(epnum)); |
c6f5c050 | 3708 | else |
95c8bc36 | 3709 | dwc2_writel(next, hsotg->regs + DOEPCTL(epnum)); |
5b7d70c6 BD |
3710 | } |
3711 | } | |
3712 | ||
b3f489b2 | 3713 | /** |
1f91b4cc | 3714 | * dwc2_hsotg_hw_cfg - read HW configuration registers |
b3f489b2 LM |
3715 | * @param: The device state |
3716 | * | |
3717 | * Read the USB core HW configuration registers | |
3718 | */ | |
1f91b4cc | 3719 | static int dwc2_hsotg_hw_cfg(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 3720 | { |
c6f5c050 MYK |
3721 | u32 cfg; |
3722 | u32 ep_type; | |
3723 | u32 i; | |
3724 | ||
b3f489b2 | 3725 | /* check hardware configuration */ |
5b7d70c6 | 3726 | |
43e90349 JY |
3727 | hsotg->num_of_eps = hsotg->hw_params.num_dev_ep; |
3728 | ||
c6f5c050 MYK |
3729 | /* Add ep0 */ |
3730 | hsotg->num_of_eps++; | |
10aebc77 | 3731 | |
1f91b4cc | 3732 | hsotg->eps_in[0] = devm_kzalloc(hsotg->dev, sizeof(struct dwc2_hsotg_ep), |
c6f5c050 MYK |
3733 | GFP_KERNEL); |
3734 | if (!hsotg->eps_in[0]) | |
3735 | return -ENOMEM; | |
1f91b4cc | 3736 | /* Same dwc2_hsotg_ep is used in both directions for ep0 */ |
c6f5c050 MYK |
3737 | hsotg->eps_out[0] = hsotg->eps_in[0]; |
3738 | ||
43e90349 | 3739 | cfg = hsotg->hw_params.dev_ep_dirs; |
251a17f5 | 3740 | for (i = 1, cfg >>= 2; i < hsotg->num_of_eps; i++, cfg >>= 2) { |
c6f5c050 MYK |
3741 | ep_type = cfg & 3; |
3742 | /* Direction in or both */ | |
3743 | if (!(ep_type & 2)) { | |
3744 | hsotg->eps_in[i] = devm_kzalloc(hsotg->dev, | |
1f91b4cc | 3745 | sizeof(struct dwc2_hsotg_ep), GFP_KERNEL); |
c6f5c050 MYK |
3746 | if (!hsotg->eps_in[i]) |
3747 | return -ENOMEM; | |
3748 | } | |
3749 | /* Direction out or both */ | |
3750 | if (!(ep_type & 1)) { | |
3751 | hsotg->eps_out[i] = devm_kzalloc(hsotg->dev, | |
1f91b4cc | 3752 | sizeof(struct dwc2_hsotg_ep), GFP_KERNEL); |
c6f5c050 MYK |
3753 | if (!hsotg->eps_out[i]) |
3754 | return -ENOMEM; | |
3755 | } | |
3756 | } | |
3757 | ||
43e90349 JY |
3758 | hsotg->fifo_mem = hsotg->hw_params.total_fifo_size; |
3759 | hsotg->dedicated_fifos = hsotg->hw_params.en_multiple_tx_fifo; | |
10aebc77 | 3760 | |
cff9eb75 MS |
3761 | dev_info(hsotg->dev, "EPs: %d, %s fifos, %d entries in SPRAM\n", |
3762 | hsotg->num_of_eps, | |
3763 | hsotg->dedicated_fifos ? "dedicated" : "shared", | |
3764 | hsotg->fifo_mem); | |
c6f5c050 | 3765 | return 0; |
5b7d70c6 BD |
3766 | } |
3767 | ||
8b9bc460 | 3768 | /** |
1f91b4cc | 3769 | * dwc2_hsotg_dump - dump state of the udc |
8b9bc460 LM |
3770 | * @param: The device state |
3771 | */ | |
1f91b4cc | 3772 | static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 3773 | { |
83a01804 | 3774 | #ifdef DEBUG |
5b7d70c6 BD |
3775 | struct device *dev = hsotg->dev; |
3776 | void __iomem *regs = hsotg->regs; | |
3777 | u32 val; | |
3778 | int idx; | |
3779 | ||
3780 | dev_info(dev, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n", | |
95c8bc36 AS |
3781 | dwc2_readl(regs + DCFG), dwc2_readl(regs + DCTL), |
3782 | dwc2_readl(regs + DIEPMSK)); | |
5b7d70c6 | 3783 | |
f889f23d | 3784 | dev_info(dev, "GAHBCFG=0x%08x, GHWCFG1=0x%08x\n", |
95c8bc36 | 3785 | dwc2_readl(regs + GAHBCFG), dwc2_readl(regs + GHWCFG1)); |
5b7d70c6 BD |
3786 | |
3787 | dev_info(dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n", | |
95c8bc36 | 3788 | dwc2_readl(regs + GRXFSIZ), dwc2_readl(regs + GNPTXFSIZ)); |
5b7d70c6 BD |
3789 | |
3790 | /* show periodic fifo settings */ | |
3791 | ||
364f8e93 | 3792 | for (idx = 1; idx < hsotg->num_of_eps; idx++) { |
95c8bc36 | 3793 | val = dwc2_readl(regs + DPTXFSIZN(idx)); |
5b7d70c6 | 3794 | dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx, |
47a1685f DN |
3795 | val >> FIFOSIZE_DEPTH_SHIFT, |
3796 | val & FIFOSIZE_STARTADDR_MASK); | |
5b7d70c6 BD |
3797 | } |
3798 | ||
364f8e93 | 3799 | for (idx = 0; idx < hsotg->num_of_eps; idx++) { |
5b7d70c6 BD |
3800 | dev_info(dev, |
3801 | "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx, | |
95c8bc36 AS |
3802 | dwc2_readl(regs + DIEPCTL(idx)), |
3803 | dwc2_readl(regs + DIEPTSIZ(idx)), | |
3804 | dwc2_readl(regs + DIEPDMA(idx))); | |
5b7d70c6 | 3805 | |
95c8bc36 | 3806 | val = dwc2_readl(regs + DOEPCTL(idx)); |
5b7d70c6 BD |
3807 | dev_info(dev, |
3808 | "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", | |
95c8bc36 AS |
3809 | idx, dwc2_readl(regs + DOEPCTL(idx)), |
3810 | dwc2_readl(regs + DOEPTSIZ(idx)), | |
3811 | dwc2_readl(regs + DOEPDMA(idx))); | |
5b7d70c6 BD |
3812 | |
3813 | } | |
3814 | ||
3815 | dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n", | |
95c8bc36 | 3816 | dwc2_readl(regs + DVBUSDIS), dwc2_readl(regs + DVBUSPULSE)); |
83a01804 | 3817 | #endif |
5b7d70c6 BD |
3818 | } |
3819 | ||
8b9bc460 | 3820 | /** |
117777b2 DN |
3821 | * dwc2_gadget_init - init function for gadget |
3822 | * @dwc2: The data structure for the DWC2 driver. | |
3823 | * @irq: The IRQ number for the controller. | |
8b9bc460 | 3824 | */ |
117777b2 | 3825 | int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq) |
5b7d70c6 | 3826 | { |
117777b2 | 3827 | struct device *dev = hsotg->dev; |
5b7d70c6 BD |
3828 | int epnum; |
3829 | int ret; | |
43e90349 | 3830 | |
0a176279 GH |
3831 | /* Dump fifo information */ |
3832 | dev_dbg(dev, "NonPeriodic TXFIFO size: %d\n", | |
05ee799f JY |
3833 | hsotg->params.g_np_tx_fifo_size); |
3834 | dev_dbg(dev, "RXFIFO size: %d\n", hsotg->params.g_rx_fifo_size); | |
5b7d70c6 | 3835 | |
d327ab5b | 3836 | hsotg->gadget.max_speed = USB_SPEED_HIGH; |
1f91b4cc | 3837 | hsotg->gadget.ops = &dwc2_hsotg_gadget_ops; |
5b7d70c6 | 3838 | hsotg->gadget.name = dev_name(dev); |
097ee662 GH |
3839 | if (hsotg->dr_mode == USB_DR_MODE_OTG) |
3840 | hsotg->gadget.is_otg = 1; | |
ec4cc657 MYK |
3841 | else if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) |
3842 | hsotg->op_state = OTG_STATE_B_PERIPHERAL; | |
5b7d70c6 | 3843 | |
1f91b4cc | 3844 | ret = dwc2_hsotg_hw_cfg(hsotg); |
c6f5c050 MYK |
3845 | if (ret) { |
3846 | dev_err(hsotg->dev, "Hardware configuration failed: %d\n", ret); | |
09a75e85 | 3847 | return ret; |
c6f5c050 MYK |
3848 | } |
3849 | ||
3f95001d MYK |
3850 | hsotg->ctrl_buff = devm_kzalloc(hsotg->dev, |
3851 | DWC2_CTRL_BUFF_SIZE, GFP_KERNEL); | |
8bae0f8c | 3852 | if (!hsotg->ctrl_buff) |
09a75e85 | 3853 | return -ENOMEM; |
3f95001d MYK |
3854 | |
3855 | hsotg->ep0_buff = devm_kzalloc(hsotg->dev, | |
3856 | DWC2_CTRL_BUFF_SIZE, GFP_KERNEL); | |
8bae0f8c | 3857 | if (!hsotg->ep0_buff) |
09a75e85 | 3858 | return -ENOMEM; |
3f95001d | 3859 | |
1f91b4cc | 3860 | ret = devm_request_irq(hsotg->dev, irq, dwc2_hsotg_irq, IRQF_SHARED, |
db8178c3 | 3861 | dev_name(hsotg->dev), hsotg); |
eb3c56c5 | 3862 | if (ret < 0) { |
db8178c3 | 3863 | dev_err(dev, "cannot claim IRQ for gadget\n"); |
09a75e85 | 3864 | return ret; |
eb3c56c5 MS |
3865 | } |
3866 | ||
b3f489b2 LM |
3867 | /* hsotg->num_of_eps holds number of EPs other than ep0 */ |
3868 | ||
3869 | if (hsotg->num_of_eps == 0) { | |
3870 | dev_err(dev, "wrong number of EPs (zero)\n"); | |
09a75e85 | 3871 | return -EINVAL; |
b3f489b2 LM |
3872 | } |
3873 | ||
b3f489b2 LM |
3874 | /* setup endpoint information */ |
3875 | ||
3876 | INIT_LIST_HEAD(&hsotg->gadget.ep_list); | |
c6f5c050 | 3877 | hsotg->gadget.ep0 = &hsotg->eps_out[0]->ep; |
b3f489b2 LM |
3878 | |
3879 | /* allocate EP0 request */ | |
3880 | ||
1f91b4cc | 3881 | hsotg->ctrl_req = dwc2_hsotg_ep_alloc_request(&hsotg->eps_out[0]->ep, |
b3f489b2 LM |
3882 | GFP_KERNEL); |
3883 | if (!hsotg->ctrl_req) { | |
3884 | dev_err(dev, "failed to allocate ctrl req\n"); | |
09a75e85 | 3885 | return -ENOMEM; |
b3f489b2 | 3886 | } |
5b7d70c6 BD |
3887 | |
3888 | /* initialise the endpoints now the core has been initialised */ | |
c6f5c050 MYK |
3889 | for (epnum = 0; epnum < hsotg->num_of_eps; epnum++) { |
3890 | if (hsotg->eps_in[epnum]) | |
1f91b4cc | 3891 | dwc2_hsotg_initep(hsotg, hsotg->eps_in[epnum], |
c6f5c050 MYK |
3892 | epnum, 1); |
3893 | if (hsotg->eps_out[epnum]) | |
1f91b4cc | 3894 | dwc2_hsotg_initep(hsotg, hsotg->eps_out[epnum], |
c6f5c050 MYK |
3895 | epnum, 0); |
3896 | } | |
5b7d70c6 | 3897 | |
117777b2 | 3898 | ret = usb_add_gadget_udc(dev, &hsotg->gadget); |
0f91349b | 3899 | if (ret) |
09a75e85 | 3900 | return ret; |
0f91349b | 3901 | |
1f91b4cc | 3902 | dwc2_hsotg_dump(hsotg); |
5b7d70c6 | 3903 | |
5b7d70c6 | 3904 | return 0; |
5b7d70c6 BD |
3905 | } |
3906 | ||
8b9bc460 | 3907 | /** |
1f91b4cc | 3908 | * dwc2_hsotg_remove - remove function for hsotg driver |
8b9bc460 LM |
3909 | * @pdev: The platform information for the driver |
3910 | */ | |
1f91b4cc | 3911 | int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 3912 | { |
0f91349b | 3913 | usb_del_gadget_udc(&hsotg->gadget); |
31ee04de | 3914 | |
5b7d70c6 BD |
3915 | return 0; |
3916 | } | |
3917 | ||
1f91b4cc | 3918 | int dwc2_hsotg_suspend(struct dwc2_hsotg *hsotg) |
b83e333a | 3919 | { |
b83e333a | 3920 | unsigned long flags; |
b83e333a | 3921 | |
9e779778 | 3922 | if (hsotg->lx_state != DWC2_L0) |
09a75e85 | 3923 | return 0; |
9e779778 | 3924 | |
dc6e69e6 MS |
3925 | if (hsotg->driver) { |
3926 | int ep; | |
3927 | ||
b83e333a MS |
3928 | dev_info(hsotg->dev, "suspending usb gadget %s\n", |
3929 | hsotg->driver->driver.name); | |
3930 | ||
dc6e69e6 MS |
3931 | spin_lock_irqsave(&hsotg->lock, flags); |
3932 | if (hsotg->enabled) | |
1f91b4cc FB |
3933 | dwc2_hsotg_core_disconnect(hsotg); |
3934 | dwc2_hsotg_disconnect(hsotg); | |
dc6e69e6 MS |
3935 | hsotg->gadget.speed = USB_SPEED_UNKNOWN; |
3936 | spin_unlock_irqrestore(&hsotg->lock, flags); | |
b83e333a | 3937 | |
c6f5c050 MYK |
3938 | for (ep = 0; ep < hsotg->num_of_eps; ep++) { |
3939 | if (hsotg->eps_in[ep]) | |
1f91b4cc | 3940 | dwc2_hsotg_ep_disable(&hsotg->eps_in[ep]->ep); |
c6f5c050 | 3941 | if (hsotg->eps_out[ep]) |
1f91b4cc | 3942 | dwc2_hsotg_ep_disable(&hsotg->eps_out[ep]->ep); |
c6f5c050 | 3943 | } |
b83e333a MS |
3944 | } |
3945 | ||
09a75e85 | 3946 | return 0; |
b83e333a MS |
3947 | } |
3948 | ||
1f91b4cc | 3949 | int dwc2_hsotg_resume(struct dwc2_hsotg *hsotg) |
b83e333a | 3950 | { |
b83e333a | 3951 | unsigned long flags; |
b83e333a | 3952 | |
9e779778 | 3953 | if (hsotg->lx_state == DWC2_L2) |
09a75e85 | 3954 | return 0; |
9e779778 | 3955 | |
b83e333a MS |
3956 | if (hsotg->driver) { |
3957 | dev_info(hsotg->dev, "resuming usb gadget %s\n", | |
3958 | hsotg->driver->driver.name); | |
d00b4142 | 3959 | |
dc6e69e6 | 3960 | spin_lock_irqsave(&hsotg->lock, flags); |
1f91b4cc | 3961 | dwc2_hsotg_core_init_disconnected(hsotg, false); |
dc6e69e6 | 3962 | if (hsotg->enabled) |
1f91b4cc | 3963 | dwc2_hsotg_core_connect(hsotg); |
dc6e69e6 MS |
3964 | spin_unlock_irqrestore(&hsotg->lock, flags); |
3965 | } | |
b83e333a | 3966 | |
09a75e85 | 3967 | return 0; |
b83e333a | 3968 | } |
58e52ff6 JY |
3969 | |
3970 | /** | |
3971 | * dwc2_backup_device_registers() - Backup controller device registers. | |
3972 | * When suspending usb bus, registers needs to be backuped | |
3973 | * if controller power is disabled once suspended. | |
3974 | * | |
3975 | * @hsotg: Programming view of the DWC_otg controller | |
3976 | */ | |
3977 | int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg) | |
3978 | { | |
3979 | struct dwc2_dregs_backup *dr; | |
3980 | int i; | |
3981 | ||
3982 | dev_dbg(hsotg->dev, "%s\n", __func__); | |
3983 | ||
3984 | /* Backup dev regs */ | |
3985 | dr = &hsotg->dr_backup; | |
3986 | ||
3987 | dr->dcfg = dwc2_readl(hsotg->regs + DCFG); | |
3988 | dr->dctl = dwc2_readl(hsotg->regs + DCTL); | |
3989 | dr->daintmsk = dwc2_readl(hsotg->regs + DAINTMSK); | |
3990 | dr->diepmsk = dwc2_readl(hsotg->regs + DIEPMSK); | |
3991 | dr->doepmsk = dwc2_readl(hsotg->regs + DOEPMSK); | |
3992 | ||
3993 | for (i = 0; i < hsotg->num_of_eps; i++) { | |
3994 | /* Backup IN EPs */ | |
3995 | dr->diepctl[i] = dwc2_readl(hsotg->regs + DIEPCTL(i)); | |
3996 | ||
3997 | /* Ensure DATA PID is correctly configured */ | |
3998 | if (dr->diepctl[i] & DXEPCTL_DPID) | |
3999 | dr->diepctl[i] |= DXEPCTL_SETD1PID; | |
4000 | else | |
4001 | dr->diepctl[i] |= DXEPCTL_SETD0PID; | |
4002 | ||
4003 | dr->dieptsiz[i] = dwc2_readl(hsotg->regs + DIEPTSIZ(i)); | |
4004 | dr->diepdma[i] = dwc2_readl(hsotg->regs + DIEPDMA(i)); | |
4005 | ||
4006 | /* Backup OUT EPs */ | |
4007 | dr->doepctl[i] = dwc2_readl(hsotg->regs + DOEPCTL(i)); | |
4008 | ||
4009 | /* Ensure DATA PID is correctly configured */ | |
4010 | if (dr->doepctl[i] & DXEPCTL_DPID) | |
4011 | dr->doepctl[i] |= DXEPCTL_SETD1PID; | |
4012 | else | |
4013 | dr->doepctl[i] |= DXEPCTL_SETD0PID; | |
4014 | ||
4015 | dr->doeptsiz[i] = dwc2_readl(hsotg->regs + DOEPTSIZ(i)); | |
4016 | dr->doepdma[i] = dwc2_readl(hsotg->regs + DOEPDMA(i)); | |
4017 | } | |
4018 | dr->valid = true; | |
4019 | return 0; | |
4020 | } | |
4021 | ||
4022 | /** | |
4023 | * dwc2_restore_device_registers() - Restore controller device registers. | |
4024 | * When resuming usb bus, device registers needs to be restored | |
4025 | * if controller power were disabled. | |
4026 | * | |
4027 | * @hsotg: Programming view of the DWC_otg controller | |
4028 | */ | |
4029 | int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg) | |
4030 | { | |
4031 | struct dwc2_dregs_backup *dr; | |
4032 | u32 dctl; | |
4033 | int i; | |
4034 | ||
4035 | dev_dbg(hsotg->dev, "%s\n", __func__); | |
4036 | ||
4037 | /* Restore dev regs */ | |
4038 | dr = &hsotg->dr_backup; | |
4039 | if (!dr->valid) { | |
4040 | dev_err(hsotg->dev, "%s: no device registers to restore\n", | |
4041 | __func__); | |
4042 | return -EINVAL; | |
4043 | } | |
4044 | dr->valid = false; | |
4045 | ||
4046 | dwc2_writel(dr->dcfg, hsotg->regs + DCFG); | |
4047 | dwc2_writel(dr->dctl, hsotg->regs + DCTL); | |
4048 | dwc2_writel(dr->daintmsk, hsotg->regs + DAINTMSK); | |
4049 | dwc2_writel(dr->diepmsk, hsotg->regs + DIEPMSK); | |
4050 | dwc2_writel(dr->doepmsk, hsotg->regs + DOEPMSK); | |
4051 | ||
4052 | for (i = 0; i < hsotg->num_of_eps; i++) { | |
4053 | /* Restore IN EPs */ | |
4054 | dwc2_writel(dr->diepctl[i], hsotg->regs + DIEPCTL(i)); | |
4055 | dwc2_writel(dr->dieptsiz[i], hsotg->regs + DIEPTSIZ(i)); | |
4056 | dwc2_writel(dr->diepdma[i], hsotg->regs + DIEPDMA(i)); | |
4057 | ||
4058 | /* Restore OUT EPs */ | |
4059 | dwc2_writel(dr->doepctl[i], hsotg->regs + DOEPCTL(i)); | |
4060 | dwc2_writel(dr->doeptsiz[i], hsotg->regs + DOEPTSIZ(i)); | |
4061 | dwc2_writel(dr->doepdma[i], hsotg->regs + DOEPDMA(i)); | |
4062 | } | |
4063 | ||
4064 | /* Set the Power-On Programming done bit */ | |
4065 | dctl = dwc2_readl(hsotg->regs + DCTL); | |
4066 | dctl |= DCTL_PWRONPRGDONE; | |
4067 | dwc2_writel(dctl, hsotg->regs + DCTL); | |
4068 | ||
4069 | return 0; | |
4070 | } |