Commit | Line | Data |
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8b9bc460 | 1 | /** |
dfbc6fa3 AT |
2 | * Copyright (c) 2011 Samsung Electronics Co., Ltd. |
3 | * http://www.samsung.com | |
5b7d70c6 BD |
4 | * |
5 | * Copyright 2008 Openmoko, Inc. | |
6 | * Copyright 2008 Simtec Electronics | |
7 | * Ben Dooks <ben@simtec.co.uk> | |
8 | * http://armlinux.simtec.co.uk/ | |
9 | * | |
10 | * S3C USB2.0 High-speed / OtG driver | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License version 2 as | |
14 | * published by the Free Software Foundation. | |
8b9bc460 | 15 | */ |
5b7d70c6 BD |
16 | |
17 | #include <linux/kernel.h> | |
18 | #include <linux/module.h> | |
19 | #include <linux/spinlock.h> | |
20 | #include <linux/interrupt.h> | |
21 | #include <linux/platform_device.h> | |
22 | #include <linux/dma-mapping.h> | |
23 | #include <linux/debugfs.h> | |
7ad8096e | 24 | #include <linux/mutex.h> |
5b7d70c6 BD |
25 | #include <linux/seq_file.h> |
26 | #include <linux/delay.h> | |
27 | #include <linux/io.h> | |
5a0e3ad6 | 28 | #include <linux/slab.h> |
e50bf385 | 29 | #include <linux/clk.h> |
fc9a731e | 30 | #include <linux/regulator/consumer.h> |
c50f056c | 31 | #include <linux/of_platform.h> |
74084844 | 32 | #include <linux/phy/phy.h> |
5b7d70c6 BD |
33 | |
34 | #include <linux/usb/ch9.h> | |
35 | #include <linux/usb/gadget.h> | |
b2e587db | 36 | #include <linux/usb/phy.h> |
126625e1 | 37 | #include <linux/platform_data/s3c-hsotg.h> |
9e14d0a5 | 38 | #include <linux/uaccess.h> |
5b7d70c6 | 39 | |
f7c0b143 | 40 | #include "core.h" |
941fcce4 | 41 | #include "hw.h" |
5b7d70c6 BD |
42 | |
43 | /* conversion functions */ | |
44 | static inline struct s3c_hsotg_req *our_req(struct usb_request *req) | |
45 | { | |
46 | return container_of(req, struct s3c_hsotg_req, req); | |
47 | } | |
48 | ||
49 | static inline struct s3c_hsotg_ep *our_ep(struct usb_ep *ep) | |
50 | { | |
51 | return container_of(ep, struct s3c_hsotg_ep, ep); | |
52 | } | |
53 | ||
941fcce4 | 54 | static inline struct dwc2_hsotg *to_hsotg(struct usb_gadget *gadget) |
5b7d70c6 | 55 | { |
941fcce4 | 56 | return container_of(gadget, struct dwc2_hsotg, gadget); |
5b7d70c6 BD |
57 | } |
58 | ||
59 | static inline void __orr32(void __iomem *ptr, u32 val) | |
60 | { | |
61 | writel(readl(ptr) | val, ptr); | |
62 | } | |
63 | ||
64 | static inline void __bic32(void __iomem *ptr, u32 val) | |
65 | { | |
66 | writel(readl(ptr) & ~val, ptr); | |
67 | } | |
68 | ||
c6f5c050 MYK |
69 | static inline struct s3c_hsotg_ep *index_to_ep(struct dwc2_hsotg *hsotg, |
70 | u32 ep_index, u32 dir_in) | |
71 | { | |
72 | if (dir_in) | |
73 | return hsotg->eps_in[ep_index]; | |
74 | else | |
75 | return hsotg->eps_out[ep_index]; | |
76 | } | |
77 | ||
997f4f81 | 78 | /* forward declaration of functions */ |
941fcce4 | 79 | static void s3c_hsotg_dump(struct dwc2_hsotg *hsotg); |
5b7d70c6 BD |
80 | |
81 | /** | |
82 | * using_dma - return the DMA status of the driver. | |
83 | * @hsotg: The driver state. | |
84 | * | |
85 | * Return true if we're using DMA. | |
86 | * | |
87 | * Currently, we have the DMA support code worked into everywhere | |
88 | * that needs it, but the AMBA DMA implementation in the hardware can | |
89 | * only DMA from 32bit aligned addresses. This means that gadgets such | |
90 | * as the CDC Ethernet cannot work as they often pass packets which are | |
91 | * not 32bit aligned. | |
92 | * | |
93 | * Unfortunately the choice to use DMA or not is global to the controller | |
94 | * and seems to be only settable when the controller is being put through | |
95 | * a core reset. This means we either need to fix the gadgets to take | |
96 | * account of DMA alignment, or add bounce buffers (yuerk). | |
97 | * | |
edd74be8 | 98 | * g_using_dma is set depending on dts flag. |
5b7d70c6 | 99 | */ |
941fcce4 | 100 | static inline bool using_dma(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 101 | { |
edd74be8 | 102 | return hsotg->g_using_dma; |
5b7d70c6 BD |
103 | } |
104 | ||
105 | /** | |
106 | * s3c_hsotg_en_gsint - enable one or more of the general interrupt | |
107 | * @hsotg: The device state | |
108 | * @ints: A bitmask of the interrupts to enable | |
109 | */ | |
941fcce4 | 110 | static void s3c_hsotg_en_gsint(struct dwc2_hsotg *hsotg, u32 ints) |
5b7d70c6 | 111 | { |
94cb8fd6 | 112 | u32 gsintmsk = readl(hsotg->regs + GINTMSK); |
5b7d70c6 BD |
113 | u32 new_gsintmsk; |
114 | ||
115 | new_gsintmsk = gsintmsk | ints; | |
116 | ||
117 | if (new_gsintmsk != gsintmsk) { | |
118 | dev_dbg(hsotg->dev, "gsintmsk now 0x%08x\n", new_gsintmsk); | |
94cb8fd6 | 119 | writel(new_gsintmsk, hsotg->regs + GINTMSK); |
5b7d70c6 BD |
120 | } |
121 | } | |
122 | ||
123 | /** | |
124 | * s3c_hsotg_disable_gsint - disable one or more of the general interrupt | |
125 | * @hsotg: The device state | |
126 | * @ints: A bitmask of the interrupts to enable | |
127 | */ | |
941fcce4 | 128 | static void s3c_hsotg_disable_gsint(struct dwc2_hsotg *hsotg, u32 ints) |
5b7d70c6 | 129 | { |
94cb8fd6 | 130 | u32 gsintmsk = readl(hsotg->regs + GINTMSK); |
5b7d70c6 BD |
131 | u32 new_gsintmsk; |
132 | ||
133 | new_gsintmsk = gsintmsk & ~ints; | |
134 | ||
135 | if (new_gsintmsk != gsintmsk) | |
94cb8fd6 | 136 | writel(new_gsintmsk, hsotg->regs + GINTMSK); |
5b7d70c6 BD |
137 | } |
138 | ||
139 | /** | |
140 | * s3c_hsotg_ctrl_epint - enable/disable an endpoint irq | |
141 | * @hsotg: The device state | |
142 | * @ep: The endpoint index | |
143 | * @dir_in: True if direction is in. | |
144 | * @en: The enable value, true to enable | |
145 | * | |
146 | * Set or clear the mask for an individual endpoint's interrupt | |
147 | * request. | |
148 | */ | |
941fcce4 | 149 | static void s3c_hsotg_ctrl_epint(struct dwc2_hsotg *hsotg, |
5b7d70c6 BD |
150 | unsigned int ep, unsigned int dir_in, |
151 | unsigned int en) | |
152 | { | |
153 | unsigned long flags; | |
154 | u32 bit = 1 << ep; | |
155 | u32 daint; | |
156 | ||
157 | if (!dir_in) | |
158 | bit <<= 16; | |
159 | ||
160 | local_irq_save(flags); | |
94cb8fd6 | 161 | daint = readl(hsotg->regs + DAINTMSK); |
5b7d70c6 BD |
162 | if (en) |
163 | daint |= bit; | |
164 | else | |
165 | daint &= ~bit; | |
94cb8fd6 | 166 | writel(daint, hsotg->regs + DAINTMSK); |
5b7d70c6 BD |
167 | local_irq_restore(flags); |
168 | } | |
169 | ||
170 | /** | |
171 | * s3c_hsotg_init_fifo - initialise non-periodic FIFOs | |
172 | * @hsotg: The device instance. | |
173 | */ | |
941fcce4 | 174 | static void s3c_hsotg_init_fifo(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 175 | { |
0f002d20 BD |
176 | unsigned int ep; |
177 | unsigned int addr; | |
1703a6d3 | 178 | int timeout; |
0f002d20 BD |
179 | u32 val; |
180 | ||
7fcbc95c GH |
181 | /* Reset fifo map if not correctly cleared during previous session */ |
182 | WARN_ON(hsotg->fifo_map); | |
183 | hsotg->fifo_map = 0; | |
184 | ||
0a176279 GH |
185 | /* set RX/NPTX FIFO sizes */ |
186 | writel(hsotg->g_rx_fifo_sz, hsotg->regs + GRXFSIZ); | |
187 | writel((hsotg->g_rx_fifo_sz << FIFOSIZE_STARTADDR_SHIFT) | | |
188 | (hsotg->g_np_g_tx_fifo_sz << FIFOSIZE_DEPTH_SHIFT), | |
189 | hsotg->regs + GNPTXFSIZ); | |
0f002d20 | 190 | |
8b9bc460 LM |
191 | /* |
192 | * arange all the rest of the TX FIFOs, as some versions of this | |
0f002d20 BD |
193 | * block have overlapping default addresses. This also ensures |
194 | * that if the settings have been changed, then they are set to | |
8b9bc460 LM |
195 | * known values. |
196 | */ | |
0f002d20 BD |
197 | |
198 | /* start at the end of the GNPTXFSIZ, rounded up */ | |
0a176279 | 199 | addr = hsotg->g_rx_fifo_sz + hsotg->g_np_g_tx_fifo_sz; |
0f002d20 | 200 | |
8b9bc460 | 201 | /* |
0a176279 | 202 | * Configure fifos sizes from provided configuration and assign |
b203d0a2 RB |
203 | * them to endpoints dynamically according to maxpacket size value of |
204 | * given endpoint. | |
8b9bc460 | 205 | */ |
0a176279 GH |
206 | for (ep = 1; ep < MAX_EPS_CHANNELS; ep++) { |
207 | if (!hsotg->g_tx_fifo_sz[ep]) | |
208 | continue; | |
0f002d20 | 209 | val = addr; |
0a176279 GH |
210 | val |= hsotg->g_tx_fifo_sz[ep] << FIFOSIZE_DEPTH_SHIFT; |
211 | WARN_ONCE(addr + hsotg->g_tx_fifo_sz[ep] > hsotg->fifo_mem, | |
cff9eb75 | 212 | "insufficient fifo memory"); |
0a176279 | 213 | addr += hsotg->g_tx_fifo_sz[ep]; |
0f002d20 | 214 | |
47a1685f | 215 | writel(val, hsotg->regs + DPTXFSIZN(ep)); |
0f002d20 | 216 | } |
1703a6d3 | 217 | |
8b9bc460 LM |
218 | /* |
219 | * according to p428 of the design guide, we need to ensure that | |
220 | * all fifos are flushed before continuing | |
221 | */ | |
1703a6d3 | 222 | |
47a1685f DN |
223 | writel(GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH | |
224 | GRSTCTL_RXFFLSH, hsotg->regs + GRSTCTL); | |
1703a6d3 BD |
225 | |
226 | /* wait until the fifos are both flushed */ | |
227 | timeout = 100; | |
228 | while (1) { | |
94cb8fd6 | 229 | val = readl(hsotg->regs + GRSTCTL); |
1703a6d3 | 230 | |
47a1685f | 231 | if ((val & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH)) == 0) |
1703a6d3 BD |
232 | break; |
233 | ||
234 | if (--timeout == 0) { | |
235 | dev_err(hsotg->dev, | |
236 | "%s: timeout flushing fifos (GRSTCTL=%08x)\n", | |
237 | __func__, val); | |
48b20bcb | 238 | break; |
1703a6d3 BD |
239 | } |
240 | ||
241 | udelay(1); | |
242 | } | |
243 | ||
244 | dev_dbg(hsotg->dev, "FIFOs reset, timeout at %d\n", timeout); | |
5b7d70c6 BD |
245 | } |
246 | ||
247 | /** | |
248 | * @ep: USB endpoint to allocate request for. | |
249 | * @flags: Allocation flags | |
250 | * | |
251 | * Allocate a new USB request structure appropriate for the specified endpoint | |
252 | */ | |
0978f8c5 MB |
253 | static struct usb_request *s3c_hsotg_ep_alloc_request(struct usb_ep *ep, |
254 | gfp_t flags) | |
5b7d70c6 BD |
255 | { |
256 | struct s3c_hsotg_req *req; | |
257 | ||
258 | req = kzalloc(sizeof(struct s3c_hsotg_req), flags); | |
259 | if (!req) | |
260 | return NULL; | |
261 | ||
262 | INIT_LIST_HEAD(&req->queue); | |
263 | ||
5b7d70c6 BD |
264 | return &req->req; |
265 | } | |
266 | ||
267 | /** | |
268 | * is_ep_periodic - return true if the endpoint is in periodic mode. | |
269 | * @hs_ep: The endpoint to query. | |
270 | * | |
271 | * Returns true if the endpoint is in periodic mode, meaning it is being | |
272 | * used for an Interrupt or ISO transfer. | |
273 | */ | |
274 | static inline int is_ep_periodic(struct s3c_hsotg_ep *hs_ep) | |
275 | { | |
276 | return hs_ep->periodic; | |
277 | } | |
278 | ||
279 | /** | |
280 | * s3c_hsotg_unmap_dma - unmap the DMA memory being used for the request | |
281 | * @hsotg: The device state. | |
282 | * @hs_ep: The endpoint for the request | |
283 | * @hs_req: The request being processed. | |
284 | * | |
285 | * This is the reverse of s3c_hsotg_map_dma(), called for the completion | |
286 | * of a request to ensure the buffer is ready for access by the caller. | |
8b9bc460 | 287 | */ |
941fcce4 | 288 | static void s3c_hsotg_unmap_dma(struct dwc2_hsotg *hsotg, |
5b7d70c6 BD |
289 | struct s3c_hsotg_ep *hs_ep, |
290 | struct s3c_hsotg_req *hs_req) | |
291 | { | |
292 | struct usb_request *req = &hs_req->req; | |
5b7d70c6 BD |
293 | |
294 | /* ignore this if we're not moving any data */ | |
295 | if (hs_req->req.length == 0) | |
296 | return; | |
297 | ||
17d966a3 | 298 | usb_gadget_unmap_request(&hsotg->gadget, req, hs_ep->dir_in); |
5b7d70c6 BD |
299 | } |
300 | ||
301 | /** | |
302 | * s3c_hsotg_write_fifo - write packet Data to the TxFIFO | |
303 | * @hsotg: The controller state. | |
304 | * @hs_ep: The endpoint we're going to write for. | |
305 | * @hs_req: The request to write data for. | |
306 | * | |
307 | * This is called when the TxFIFO has some space in it to hold a new | |
308 | * transmission and we have something to give it. The actual setup of | |
309 | * the data size is done elsewhere, so all we have to do is to actually | |
310 | * write the data. | |
311 | * | |
312 | * The return value is zero if there is more space (or nothing was done) | |
313 | * otherwise -ENOSPC is returned if the FIFO space was used up. | |
314 | * | |
315 | * This routine is only needed for PIO | |
8b9bc460 | 316 | */ |
941fcce4 | 317 | static int s3c_hsotg_write_fifo(struct dwc2_hsotg *hsotg, |
5b7d70c6 BD |
318 | struct s3c_hsotg_ep *hs_ep, |
319 | struct s3c_hsotg_req *hs_req) | |
320 | { | |
321 | bool periodic = is_ep_periodic(hs_ep); | |
94cb8fd6 | 322 | u32 gnptxsts = readl(hsotg->regs + GNPTXSTS); |
5b7d70c6 BD |
323 | int buf_pos = hs_req->req.actual; |
324 | int to_write = hs_ep->size_loaded; | |
325 | void *data; | |
326 | int can_write; | |
327 | int pkt_round; | |
4fca54aa | 328 | int max_transfer; |
5b7d70c6 BD |
329 | |
330 | to_write -= (buf_pos - hs_ep->last_load); | |
331 | ||
332 | /* if there's nothing to write, get out early */ | |
333 | if (to_write == 0) | |
334 | return 0; | |
335 | ||
10aebc77 | 336 | if (periodic && !hsotg->dedicated_fifos) { |
94cb8fd6 | 337 | u32 epsize = readl(hsotg->regs + DIEPTSIZ(hs_ep->index)); |
5b7d70c6 BD |
338 | int size_left; |
339 | int size_done; | |
340 | ||
8b9bc460 LM |
341 | /* |
342 | * work out how much data was loaded so we can calculate | |
343 | * how much data is left in the fifo. | |
344 | */ | |
5b7d70c6 | 345 | |
47a1685f | 346 | size_left = DXEPTSIZ_XFERSIZE_GET(epsize); |
5b7d70c6 | 347 | |
8b9bc460 LM |
348 | /* |
349 | * if shared fifo, we cannot write anything until the | |
e7a9ff54 BD |
350 | * previous data has been completely sent. |
351 | */ | |
352 | if (hs_ep->fifo_load != 0) { | |
47a1685f | 353 | s3c_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP); |
e7a9ff54 BD |
354 | return -ENOSPC; |
355 | } | |
356 | ||
5b7d70c6 BD |
357 | dev_dbg(hsotg->dev, "%s: left=%d, load=%d, fifo=%d, size %d\n", |
358 | __func__, size_left, | |
359 | hs_ep->size_loaded, hs_ep->fifo_load, hs_ep->fifo_size); | |
360 | ||
361 | /* how much of the data has moved */ | |
362 | size_done = hs_ep->size_loaded - size_left; | |
363 | ||
364 | /* how much data is left in the fifo */ | |
365 | can_write = hs_ep->fifo_load - size_done; | |
366 | dev_dbg(hsotg->dev, "%s: => can_write1=%d\n", | |
367 | __func__, can_write); | |
368 | ||
369 | can_write = hs_ep->fifo_size - can_write; | |
370 | dev_dbg(hsotg->dev, "%s: => can_write2=%d\n", | |
371 | __func__, can_write); | |
372 | ||
373 | if (can_write <= 0) { | |
47a1685f | 374 | s3c_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP); |
5b7d70c6 BD |
375 | return -ENOSPC; |
376 | } | |
10aebc77 | 377 | } else if (hsotg->dedicated_fifos && hs_ep->index != 0) { |
94cb8fd6 | 378 | can_write = readl(hsotg->regs + DTXFSTS(hs_ep->index)); |
10aebc77 BD |
379 | |
380 | can_write &= 0xffff; | |
381 | can_write *= 4; | |
5b7d70c6 | 382 | } else { |
47a1685f | 383 | if (GNPTXSTS_NP_TXQ_SPC_AVAIL_GET(gnptxsts) == 0) { |
5b7d70c6 BD |
384 | dev_dbg(hsotg->dev, |
385 | "%s: no queue slots available (0x%08x)\n", | |
386 | __func__, gnptxsts); | |
387 | ||
47a1685f | 388 | s3c_hsotg_en_gsint(hsotg, GINTSTS_NPTXFEMP); |
5b7d70c6 BD |
389 | return -ENOSPC; |
390 | } | |
391 | ||
47a1685f | 392 | can_write = GNPTXSTS_NP_TXF_SPC_AVAIL_GET(gnptxsts); |
679f9b7c | 393 | can_write *= 4; /* fifo size is in 32bit quantities. */ |
5b7d70c6 BD |
394 | } |
395 | ||
4fca54aa RB |
396 | max_transfer = hs_ep->ep.maxpacket * hs_ep->mc; |
397 | ||
398 | dev_dbg(hsotg->dev, "%s: GNPTXSTS=%08x, can=%d, to=%d, max_transfer %d\n", | |
399 | __func__, gnptxsts, can_write, to_write, max_transfer); | |
5b7d70c6 | 400 | |
8b9bc460 LM |
401 | /* |
402 | * limit to 512 bytes of data, it seems at least on the non-periodic | |
5b7d70c6 BD |
403 | * FIFO, requests of >512 cause the endpoint to get stuck with a |
404 | * fragment of the end of the transfer in it. | |
405 | */ | |
811f3303 | 406 | if (can_write > 512 && !periodic) |
5b7d70c6 BD |
407 | can_write = 512; |
408 | ||
8b9bc460 LM |
409 | /* |
410 | * limit the write to one max-packet size worth of data, but allow | |
03e10e5a | 411 | * the transfer to return that it did not run out of fifo space |
8b9bc460 LM |
412 | * doing it. |
413 | */ | |
4fca54aa RB |
414 | if (to_write > max_transfer) { |
415 | to_write = max_transfer; | |
03e10e5a | 416 | |
5cb2ff0c RB |
417 | /* it's needed only when we do not use dedicated fifos */ |
418 | if (!hsotg->dedicated_fifos) | |
419 | s3c_hsotg_en_gsint(hsotg, | |
47a1685f DN |
420 | periodic ? GINTSTS_PTXFEMP : |
421 | GINTSTS_NPTXFEMP); | |
03e10e5a BD |
422 | } |
423 | ||
5b7d70c6 BD |
424 | /* see if we can write data */ |
425 | ||
426 | if (to_write > can_write) { | |
427 | to_write = can_write; | |
4fca54aa | 428 | pkt_round = to_write % max_transfer; |
5b7d70c6 | 429 | |
8b9bc460 LM |
430 | /* |
431 | * Round the write down to an | |
5b7d70c6 BD |
432 | * exact number of packets. |
433 | * | |
434 | * Note, we do not currently check to see if we can ever | |
435 | * write a full packet or not to the FIFO. | |
436 | */ | |
437 | ||
438 | if (pkt_round) | |
439 | to_write -= pkt_round; | |
440 | ||
8b9bc460 LM |
441 | /* |
442 | * enable correct FIFO interrupt to alert us when there | |
443 | * is more room left. | |
444 | */ | |
5b7d70c6 | 445 | |
5cb2ff0c RB |
446 | /* it's needed only when we do not use dedicated fifos */ |
447 | if (!hsotg->dedicated_fifos) | |
448 | s3c_hsotg_en_gsint(hsotg, | |
47a1685f DN |
449 | periodic ? GINTSTS_PTXFEMP : |
450 | GINTSTS_NPTXFEMP); | |
5b7d70c6 BD |
451 | } |
452 | ||
453 | dev_dbg(hsotg->dev, "write %d/%d, can_write %d, done %d\n", | |
454 | to_write, hs_req->req.length, can_write, buf_pos); | |
455 | ||
456 | if (to_write <= 0) | |
457 | return -ENOSPC; | |
458 | ||
459 | hs_req->req.actual = buf_pos + to_write; | |
460 | hs_ep->total_data += to_write; | |
461 | ||
462 | if (periodic) | |
463 | hs_ep->fifo_load += to_write; | |
464 | ||
465 | to_write = DIV_ROUND_UP(to_write, 4); | |
466 | data = hs_req->req.buf + buf_pos; | |
467 | ||
1a7ed5be | 468 | iowrite32_rep(hsotg->regs + EPFIFO(hs_ep->index), data, to_write); |
5b7d70c6 BD |
469 | |
470 | return (to_write >= can_write) ? -ENOSPC : 0; | |
471 | } | |
472 | ||
473 | /** | |
474 | * get_ep_limit - get the maximum data legnth for this endpoint | |
475 | * @hs_ep: The endpoint | |
476 | * | |
477 | * Return the maximum data that can be queued in one go on a given endpoint | |
478 | * so that transfers that are too long can be split. | |
479 | */ | |
480 | static unsigned get_ep_limit(struct s3c_hsotg_ep *hs_ep) | |
481 | { | |
482 | int index = hs_ep->index; | |
483 | unsigned maxsize; | |
484 | unsigned maxpkt; | |
485 | ||
486 | if (index != 0) { | |
47a1685f DN |
487 | maxsize = DXEPTSIZ_XFERSIZE_LIMIT + 1; |
488 | maxpkt = DXEPTSIZ_PKTCNT_LIMIT + 1; | |
5b7d70c6 | 489 | } else { |
b05ca580 | 490 | maxsize = 64+64; |
66e5c643 | 491 | if (hs_ep->dir_in) |
47a1685f | 492 | maxpkt = DIEPTSIZ0_PKTCNT_LIMIT + 1; |
66e5c643 | 493 | else |
5b7d70c6 | 494 | maxpkt = 2; |
5b7d70c6 BD |
495 | } |
496 | ||
497 | /* we made the constant loading easier above by using +1 */ | |
498 | maxpkt--; | |
499 | maxsize--; | |
500 | ||
8b9bc460 LM |
501 | /* |
502 | * constrain by packet count if maxpkts*pktsize is greater | |
503 | * than the length register size. | |
504 | */ | |
5b7d70c6 BD |
505 | |
506 | if ((maxpkt * hs_ep->ep.maxpacket) < maxsize) | |
507 | maxsize = maxpkt * hs_ep->ep.maxpacket; | |
508 | ||
509 | return maxsize; | |
510 | } | |
511 | ||
512 | /** | |
513 | * s3c_hsotg_start_req - start a USB request from an endpoint's queue | |
514 | * @hsotg: The controller state. | |
515 | * @hs_ep: The endpoint to process a request for | |
516 | * @hs_req: The request to start. | |
517 | * @continuing: True if we are doing more for the current request. | |
518 | * | |
519 | * Start the given request running by setting the endpoint registers | |
520 | * appropriately, and writing any data to the FIFOs. | |
521 | */ | |
941fcce4 | 522 | static void s3c_hsotg_start_req(struct dwc2_hsotg *hsotg, |
5b7d70c6 BD |
523 | struct s3c_hsotg_ep *hs_ep, |
524 | struct s3c_hsotg_req *hs_req, | |
525 | bool continuing) | |
526 | { | |
527 | struct usb_request *ureq = &hs_req->req; | |
528 | int index = hs_ep->index; | |
529 | int dir_in = hs_ep->dir_in; | |
530 | u32 epctrl_reg; | |
531 | u32 epsize_reg; | |
532 | u32 epsize; | |
533 | u32 ctrl; | |
534 | unsigned length; | |
535 | unsigned packets; | |
536 | unsigned maxreq; | |
537 | ||
538 | if (index != 0) { | |
539 | if (hs_ep->req && !continuing) { | |
540 | dev_err(hsotg->dev, "%s: active request\n", __func__); | |
541 | WARN_ON(1); | |
542 | return; | |
543 | } else if (hs_ep->req != hs_req && continuing) { | |
544 | dev_err(hsotg->dev, | |
545 | "%s: continue different req\n", __func__); | |
546 | WARN_ON(1); | |
547 | return; | |
548 | } | |
549 | } | |
550 | ||
94cb8fd6 LM |
551 | epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index); |
552 | epsize_reg = dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index); | |
5b7d70c6 BD |
553 | |
554 | dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n", | |
555 | __func__, readl(hsotg->regs + epctrl_reg), index, | |
556 | hs_ep->dir_in ? "in" : "out"); | |
557 | ||
9c39ddc6 AT |
558 | /* If endpoint is stalled, we will restart request later */ |
559 | ctrl = readl(hsotg->regs + epctrl_reg); | |
560 | ||
47a1685f | 561 | if (ctrl & DXEPCTL_STALL) { |
9c39ddc6 AT |
562 | dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index); |
563 | return; | |
564 | } | |
565 | ||
5b7d70c6 | 566 | length = ureq->length - ureq->actual; |
71225bee LM |
567 | dev_dbg(hsotg->dev, "ureq->length:%d ureq->actual:%d\n", |
568 | ureq->length, ureq->actual); | |
5b7d70c6 BD |
569 | |
570 | maxreq = get_ep_limit(hs_ep); | |
571 | if (length > maxreq) { | |
572 | int round = maxreq % hs_ep->ep.maxpacket; | |
573 | ||
574 | dev_dbg(hsotg->dev, "%s: length %d, max-req %d, r %d\n", | |
575 | __func__, length, maxreq, round); | |
576 | ||
577 | /* round down to multiple of packets */ | |
578 | if (round) | |
579 | maxreq -= round; | |
580 | ||
581 | length = maxreq; | |
582 | } | |
583 | ||
584 | if (length) | |
585 | packets = DIV_ROUND_UP(length, hs_ep->ep.maxpacket); | |
586 | else | |
587 | packets = 1; /* send one packet if length is zero. */ | |
588 | ||
4fca54aa RB |
589 | if (hs_ep->isochronous && length > (hs_ep->mc * hs_ep->ep.maxpacket)) { |
590 | dev_err(hsotg->dev, "req length > maxpacket*mc\n"); | |
591 | return; | |
592 | } | |
593 | ||
5b7d70c6 | 594 | if (dir_in && index != 0) |
4fca54aa | 595 | if (hs_ep->isochronous) |
47a1685f | 596 | epsize = DXEPTSIZ_MC(packets); |
4fca54aa | 597 | else |
47a1685f | 598 | epsize = DXEPTSIZ_MC(1); |
5b7d70c6 BD |
599 | else |
600 | epsize = 0; | |
601 | ||
f71b5e25 MYK |
602 | /* |
603 | * zero length packet should be programmed on its own and should not | |
604 | * be counted in DIEPTSIZ.PktCnt with other packets. | |
605 | */ | |
606 | if (dir_in && ureq->zero && !continuing) { | |
607 | /* Test if zlp is actually required. */ | |
608 | if ((ureq->length >= hs_ep->ep.maxpacket) && | |
609 | !(ureq->length % hs_ep->ep.maxpacket)) | |
8a20fa45 | 610 | hs_ep->send_zlp = 1; |
5b7d70c6 BD |
611 | } |
612 | ||
47a1685f DN |
613 | epsize |= DXEPTSIZ_PKTCNT(packets); |
614 | epsize |= DXEPTSIZ_XFERSIZE(length); | |
5b7d70c6 BD |
615 | |
616 | dev_dbg(hsotg->dev, "%s: %d@%d/%d, 0x%08x => 0x%08x\n", | |
617 | __func__, packets, length, ureq->length, epsize, epsize_reg); | |
618 | ||
619 | /* store the request as the current one we're doing */ | |
620 | hs_ep->req = hs_req; | |
621 | ||
622 | /* write size / packets */ | |
623 | writel(epsize, hsotg->regs + epsize_reg); | |
624 | ||
db1d8ba3 | 625 | if (using_dma(hsotg) && !continuing) { |
5b7d70c6 BD |
626 | unsigned int dma_reg; |
627 | ||
8b9bc460 LM |
628 | /* |
629 | * write DMA address to control register, buffer already | |
630 | * synced by s3c_hsotg_ep_queue(). | |
631 | */ | |
5b7d70c6 | 632 | |
94cb8fd6 | 633 | dma_reg = dir_in ? DIEPDMA(index) : DOEPDMA(index); |
5b7d70c6 BD |
634 | writel(ureq->dma, hsotg->regs + dma_reg); |
635 | ||
0cc4cf6f | 636 | dev_dbg(hsotg->dev, "%s: %pad => 0x%08x\n", |
8b3bc14f | 637 | __func__, &ureq->dma, dma_reg); |
5b7d70c6 BD |
638 | } |
639 | ||
47a1685f DN |
640 | ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */ |
641 | ctrl |= DXEPCTL_USBACTEP; | |
71225bee | 642 | |
fe0b94ab | 643 | dev_dbg(hsotg->dev, "ep0 state:%d\n", hsotg->ep0_state); |
71225bee LM |
644 | |
645 | /* For Setup request do not clear NAK */ | |
fe0b94ab | 646 | if (!(index == 0 && hsotg->ep0_state == DWC2_EP0_SETUP)) |
47a1685f | 647 | ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */ |
71225bee | 648 | |
5b7d70c6 BD |
649 | dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl); |
650 | writel(ctrl, hsotg->regs + epctrl_reg); | |
651 | ||
8b9bc460 LM |
652 | /* |
653 | * set these, it seems that DMA support increments past the end | |
5b7d70c6 | 654 | * of the packet buffer so we need to calculate the length from |
8b9bc460 LM |
655 | * this information. |
656 | */ | |
5b7d70c6 BD |
657 | hs_ep->size_loaded = length; |
658 | hs_ep->last_load = ureq->actual; | |
659 | ||
660 | if (dir_in && !using_dma(hsotg)) { | |
661 | /* set these anyway, we may need them for non-periodic in */ | |
662 | hs_ep->fifo_load = 0; | |
663 | ||
664 | s3c_hsotg_write_fifo(hsotg, hs_ep, hs_req); | |
665 | } | |
666 | ||
8b9bc460 LM |
667 | /* |
668 | * clear the INTknTXFEmpMsk when we start request, more as a aide | |
669 | * to debugging to see what is going on. | |
670 | */ | |
5b7d70c6 | 671 | if (dir_in) |
47a1685f | 672 | writel(DIEPMSK_INTKNTXFEMPMSK, |
94cb8fd6 | 673 | hsotg->regs + DIEPINT(index)); |
5b7d70c6 | 674 | |
8b9bc460 LM |
675 | /* |
676 | * Note, trying to clear the NAK here causes problems with transmit | |
677 | * on the S3C6400 ending up with the TXFIFO becoming full. | |
678 | */ | |
5b7d70c6 BD |
679 | |
680 | /* check ep is enabled */ | |
47a1685f | 681 | if (!(readl(hsotg->regs + epctrl_reg) & DXEPCTL_EPENA)) |
1a0ed863 | 682 | dev_dbg(hsotg->dev, |
47a1685f | 683 | "ep%d: failed to become enabled (DXEPCTL=0x%08x)?\n", |
5b7d70c6 BD |
684 | index, readl(hsotg->regs + epctrl_reg)); |
685 | ||
47a1685f | 686 | dev_dbg(hsotg->dev, "%s: DXEPCTL=0x%08x\n", |
5b7d70c6 | 687 | __func__, readl(hsotg->regs + epctrl_reg)); |
afcf4169 RB |
688 | |
689 | /* enable ep interrupts */ | |
690 | s3c_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 1); | |
5b7d70c6 BD |
691 | } |
692 | ||
693 | /** | |
694 | * s3c_hsotg_map_dma - map the DMA memory being used for the request | |
695 | * @hsotg: The device state. | |
696 | * @hs_ep: The endpoint the request is on. | |
697 | * @req: The request being processed. | |
698 | * | |
699 | * We've been asked to queue a request, so ensure that the memory buffer | |
700 | * is correctly setup for DMA. If we've been passed an extant DMA address | |
701 | * then ensure the buffer has been synced to memory. If our buffer has no | |
702 | * DMA memory, then we map the memory and mark our request to allow us to | |
703 | * cleanup on completion. | |
8b9bc460 | 704 | */ |
941fcce4 | 705 | static int s3c_hsotg_map_dma(struct dwc2_hsotg *hsotg, |
5b7d70c6 BD |
706 | struct s3c_hsotg_ep *hs_ep, |
707 | struct usb_request *req) | |
708 | { | |
5b7d70c6 | 709 | struct s3c_hsotg_req *hs_req = our_req(req); |
e58ebcd1 | 710 | int ret; |
5b7d70c6 BD |
711 | |
712 | /* if the length is zero, ignore the DMA data */ | |
713 | if (hs_req->req.length == 0) | |
714 | return 0; | |
715 | ||
e58ebcd1 FB |
716 | ret = usb_gadget_map_request(&hsotg->gadget, req, hs_ep->dir_in); |
717 | if (ret) | |
718 | goto dma_error; | |
5b7d70c6 BD |
719 | |
720 | return 0; | |
721 | ||
722 | dma_error: | |
723 | dev_err(hsotg->dev, "%s: failed to map buffer %p, %d bytes\n", | |
724 | __func__, req->buf, req->length); | |
725 | ||
726 | return -EIO; | |
727 | } | |
728 | ||
729 | static int s3c_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req, | |
730 | gfp_t gfp_flags) | |
731 | { | |
732 | struct s3c_hsotg_req *hs_req = our_req(req); | |
733 | struct s3c_hsotg_ep *hs_ep = our_ep(ep); | |
941fcce4 | 734 | struct dwc2_hsotg *hs = hs_ep->parent; |
5b7d70c6 BD |
735 | bool first; |
736 | ||
737 | dev_dbg(hs->dev, "%s: req %p: %d@%p, noi=%d, zero=%d, snok=%d\n", | |
738 | ep->name, req, req->length, req->buf, req->no_interrupt, | |
739 | req->zero, req->short_not_ok); | |
740 | ||
741 | /* initialise status of the request */ | |
742 | INIT_LIST_HEAD(&hs_req->queue); | |
743 | req->actual = 0; | |
744 | req->status = -EINPROGRESS; | |
745 | ||
746 | /* if we're using DMA, sync the buffers as necessary */ | |
747 | if (using_dma(hs)) { | |
748 | int ret = s3c_hsotg_map_dma(hs, hs_ep, req); | |
749 | if (ret) | |
750 | return ret; | |
751 | } | |
752 | ||
5b7d70c6 BD |
753 | first = list_empty(&hs_ep->queue); |
754 | list_add_tail(&hs_req->queue, &hs_ep->queue); | |
755 | ||
756 | if (first) | |
757 | s3c_hsotg_start_req(hs, hs_ep, hs_req, false); | |
758 | ||
5b7d70c6 BD |
759 | return 0; |
760 | } | |
761 | ||
5ad1d316 LM |
762 | static int s3c_hsotg_ep_queue_lock(struct usb_ep *ep, struct usb_request *req, |
763 | gfp_t gfp_flags) | |
764 | { | |
765 | struct s3c_hsotg_ep *hs_ep = our_ep(ep); | |
941fcce4 | 766 | struct dwc2_hsotg *hs = hs_ep->parent; |
5ad1d316 LM |
767 | unsigned long flags = 0; |
768 | int ret = 0; | |
769 | ||
770 | spin_lock_irqsave(&hs->lock, flags); | |
771 | ret = s3c_hsotg_ep_queue(ep, req, gfp_flags); | |
772 | spin_unlock_irqrestore(&hs->lock, flags); | |
773 | ||
774 | return ret; | |
775 | } | |
776 | ||
5b7d70c6 BD |
777 | static void s3c_hsotg_ep_free_request(struct usb_ep *ep, |
778 | struct usb_request *req) | |
779 | { | |
780 | struct s3c_hsotg_req *hs_req = our_req(req); | |
781 | ||
782 | kfree(hs_req); | |
783 | } | |
784 | ||
785 | /** | |
786 | * s3c_hsotg_complete_oursetup - setup completion callback | |
787 | * @ep: The endpoint the request was on. | |
788 | * @req: The request completed. | |
789 | * | |
790 | * Called on completion of any requests the driver itself | |
791 | * submitted that need cleaning up. | |
792 | */ | |
793 | static void s3c_hsotg_complete_oursetup(struct usb_ep *ep, | |
794 | struct usb_request *req) | |
795 | { | |
796 | struct s3c_hsotg_ep *hs_ep = our_ep(ep); | |
941fcce4 | 797 | struct dwc2_hsotg *hsotg = hs_ep->parent; |
5b7d70c6 BD |
798 | |
799 | dev_dbg(hsotg->dev, "%s: ep %p, req %p\n", __func__, ep, req); | |
800 | ||
801 | s3c_hsotg_ep_free_request(ep, req); | |
802 | } | |
803 | ||
804 | /** | |
805 | * ep_from_windex - convert control wIndex value to endpoint | |
806 | * @hsotg: The driver state. | |
807 | * @windex: The control request wIndex field (in host order). | |
808 | * | |
809 | * Convert the given wIndex into a pointer to an driver endpoint | |
810 | * structure, or return NULL if it is not a valid endpoint. | |
8b9bc460 | 811 | */ |
941fcce4 | 812 | static struct s3c_hsotg_ep *ep_from_windex(struct dwc2_hsotg *hsotg, |
5b7d70c6 BD |
813 | u32 windex) |
814 | { | |
c6f5c050 | 815 | struct s3c_hsotg_ep *ep; |
5b7d70c6 BD |
816 | int dir = (windex & USB_DIR_IN) ? 1 : 0; |
817 | int idx = windex & 0x7F; | |
818 | ||
819 | if (windex >= 0x100) | |
820 | return NULL; | |
821 | ||
b3f489b2 | 822 | if (idx > hsotg->num_of_eps) |
5b7d70c6 BD |
823 | return NULL; |
824 | ||
c6f5c050 MYK |
825 | ep = index_to_ep(hsotg, idx, dir); |
826 | ||
5b7d70c6 BD |
827 | if (idx && ep->dir_in != dir) |
828 | return NULL; | |
829 | ||
830 | return ep; | |
831 | } | |
832 | ||
9e14d0a5 GH |
833 | /** |
834 | * s3c_hsotg_set_test_mode - Enable usb Test Modes | |
835 | * @hsotg: The driver state. | |
836 | * @testmode: requested usb test mode | |
837 | * Enable usb Test Mode requested by the Host. | |
838 | */ | |
839 | static int s3c_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode) | |
840 | { | |
841 | int dctl = readl(hsotg->regs + DCTL); | |
842 | ||
843 | dctl &= ~DCTL_TSTCTL_MASK; | |
844 | switch (testmode) { | |
845 | case TEST_J: | |
846 | case TEST_K: | |
847 | case TEST_SE0_NAK: | |
848 | case TEST_PACKET: | |
849 | case TEST_FORCE_EN: | |
850 | dctl |= testmode << DCTL_TSTCTL_SHIFT; | |
851 | break; | |
852 | default: | |
853 | return -EINVAL; | |
854 | } | |
855 | writel(dctl, hsotg->regs + DCTL); | |
856 | return 0; | |
857 | } | |
858 | ||
5b7d70c6 BD |
859 | /** |
860 | * s3c_hsotg_send_reply - send reply to control request | |
861 | * @hsotg: The device state | |
862 | * @ep: Endpoint 0 | |
863 | * @buff: Buffer for request | |
864 | * @length: Length of reply. | |
865 | * | |
866 | * Create a request and queue it on the given endpoint. This is useful as | |
867 | * an internal method of sending replies to certain control requests, etc. | |
868 | */ | |
941fcce4 | 869 | static int s3c_hsotg_send_reply(struct dwc2_hsotg *hsotg, |
5b7d70c6 BD |
870 | struct s3c_hsotg_ep *ep, |
871 | void *buff, | |
872 | int length) | |
873 | { | |
874 | struct usb_request *req; | |
875 | int ret; | |
876 | ||
877 | dev_dbg(hsotg->dev, "%s: buff %p, len %d\n", __func__, buff, length); | |
878 | ||
879 | req = s3c_hsotg_ep_alloc_request(&ep->ep, GFP_ATOMIC); | |
880 | hsotg->ep0_reply = req; | |
881 | if (!req) { | |
882 | dev_warn(hsotg->dev, "%s: cannot alloc req\n", __func__); | |
883 | return -ENOMEM; | |
884 | } | |
885 | ||
886 | req->buf = hsotg->ep0_buff; | |
887 | req->length = length; | |
f71b5e25 MYK |
888 | /* |
889 | * zero flag is for sending zlp in DATA IN stage. It has no impact on | |
890 | * STATUS stage. | |
891 | */ | |
892 | req->zero = 0; | |
5b7d70c6 BD |
893 | req->complete = s3c_hsotg_complete_oursetup; |
894 | ||
895 | if (length) | |
896 | memcpy(req->buf, buff, length); | |
5b7d70c6 BD |
897 | |
898 | ret = s3c_hsotg_ep_queue(&ep->ep, req, GFP_ATOMIC); | |
899 | if (ret) { | |
900 | dev_warn(hsotg->dev, "%s: cannot queue req\n", __func__); | |
901 | return ret; | |
902 | } | |
903 | ||
904 | return 0; | |
905 | } | |
906 | ||
907 | /** | |
908 | * s3c_hsotg_process_req_status - process request GET_STATUS | |
909 | * @hsotg: The device state | |
910 | * @ctrl: USB control request | |
911 | */ | |
941fcce4 | 912 | static int s3c_hsotg_process_req_status(struct dwc2_hsotg *hsotg, |
5b7d70c6 BD |
913 | struct usb_ctrlrequest *ctrl) |
914 | { | |
c6f5c050 | 915 | struct s3c_hsotg_ep *ep0 = hsotg->eps_out[0]; |
5b7d70c6 BD |
916 | struct s3c_hsotg_ep *ep; |
917 | __le16 reply; | |
918 | int ret; | |
919 | ||
920 | dev_dbg(hsotg->dev, "%s: USB_REQ_GET_STATUS\n", __func__); | |
921 | ||
922 | if (!ep0->dir_in) { | |
923 | dev_warn(hsotg->dev, "%s: direction out?\n", __func__); | |
924 | return -EINVAL; | |
925 | } | |
926 | ||
927 | switch (ctrl->bRequestType & USB_RECIP_MASK) { | |
928 | case USB_RECIP_DEVICE: | |
929 | reply = cpu_to_le16(0); /* bit 0 => self powered, | |
930 | * bit 1 => remote wakeup */ | |
931 | break; | |
932 | ||
933 | case USB_RECIP_INTERFACE: | |
934 | /* currently, the data result should be zero */ | |
935 | reply = cpu_to_le16(0); | |
936 | break; | |
937 | ||
938 | case USB_RECIP_ENDPOINT: | |
939 | ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex)); | |
940 | if (!ep) | |
941 | return -ENOENT; | |
942 | ||
943 | reply = cpu_to_le16(ep->halted ? 1 : 0); | |
944 | break; | |
945 | ||
946 | default: | |
947 | return 0; | |
948 | } | |
949 | ||
950 | if (le16_to_cpu(ctrl->wLength) != 2) | |
951 | return -EINVAL; | |
952 | ||
953 | ret = s3c_hsotg_send_reply(hsotg, ep0, &reply, 2); | |
954 | if (ret) { | |
955 | dev_err(hsotg->dev, "%s: failed to send reply\n", __func__); | |
956 | return ret; | |
957 | } | |
958 | ||
959 | return 1; | |
960 | } | |
961 | ||
962 | static int s3c_hsotg_ep_sethalt(struct usb_ep *ep, int value); | |
963 | ||
9c39ddc6 AT |
964 | /** |
965 | * get_ep_head - return the first request on the endpoint | |
966 | * @hs_ep: The controller endpoint to get | |
967 | * | |
968 | * Get the first request on the endpoint. | |
969 | */ | |
970 | static struct s3c_hsotg_req *get_ep_head(struct s3c_hsotg_ep *hs_ep) | |
971 | { | |
972 | if (list_empty(&hs_ep->queue)) | |
973 | return NULL; | |
974 | ||
975 | return list_first_entry(&hs_ep->queue, struct s3c_hsotg_req, queue); | |
976 | } | |
977 | ||
5b7d70c6 | 978 | /** |
58f7c43e | 979 | * s3c_hsotg_process_req_feature - process request {SET,CLEAR}_FEATURE |
5b7d70c6 BD |
980 | * @hsotg: The device state |
981 | * @ctrl: USB control request | |
982 | */ | |
941fcce4 | 983 | static int s3c_hsotg_process_req_feature(struct dwc2_hsotg *hsotg, |
5b7d70c6 BD |
984 | struct usb_ctrlrequest *ctrl) |
985 | { | |
c6f5c050 | 986 | struct s3c_hsotg_ep *ep0 = hsotg->eps_out[0]; |
9c39ddc6 AT |
987 | struct s3c_hsotg_req *hs_req; |
988 | bool restart; | |
5b7d70c6 BD |
989 | bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE); |
990 | struct s3c_hsotg_ep *ep; | |
26ab3d0c | 991 | int ret; |
bd9ef7bf | 992 | bool halted; |
9e14d0a5 GH |
993 | u32 recip; |
994 | u32 wValue; | |
995 | u32 wIndex; | |
5b7d70c6 BD |
996 | |
997 | dev_dbg(hsotg->dev, "%s: %s_FEATURE\n", | |
998 | __func__, set ? "SET" : "CLEAR"); | |
999 | ||
9e14d0a5 GH |
1000 | wValue = le16_to_cpu(ctrl->wValue); |
1001 | wIndex = le16_to_cpu(ctrl->wIndex); | |
1002 | recip = ctrl->bRequestType & USB_RECIP_MASK; | |
1003 | ||
1004 | switch (recip) { | |
1005 | case USB_RECIP_DEVICE: | |
1006 | switch (wValue) { | |
1007 | case USB_DEVICE_TEST_MODE: | |
1008 | if ((wIndex & 0xff) != 0) | |
1009 | return -EINVAL; | |
1010 | if (!set) | |
1011 | return -EINVAL; | |
1012 | ||
1013 | hsotg->test_mode = wIndex >> 8; | |
1014 | ret = s3c_hsotg_send_reply(hsotg, ep0, NULL, 0); | |
1015 | if (ret) { | |
1016 | dev_err(hsotg->dev, | |
1017 | "%s: failed to send reply\n", __func__); | |
1018 | return ret; | |
1019 | } | |
1020 | break; | |
1021 | default: | |
1022 | return -ENOENT; | |
1023 | } | |
1024 | break; | |
1025 | ||
1026 | case USB_RECIP_ENDPOINT: | |
1027 | ep = ep_from_windex(hsotg, wIndex); | |
5b7d70c6 BD |
1028 | if (!ep) { |
1029 | dev_dbg(hsotg->dev, "%s: no endpoint for 0x%04x\n", | |
9e14d0a5 | 1030 | __func__, wIndex); |
5b7d70c6 BD |
1031 | return -ENOENT; |
1032 | } | |
1033 | ||
9e14d0a5 | 1034 | switch (wValue) { |
5b7d70c6 | 1035 | case USB_ENDPOINT_HALT: |
bd9ef7bf RB |
1036 | halted = ep->halted; |
1037 | ||
5b7d70c6 | 1038 | s3c_hsotg_ep_sethalt(&ep->ep, set); |
26ab3d0c AT |
1039 | |
1040 | ret = s3c_hsotg_send_reply(hsotg, ep0, NULL, 0); | |
1041 | if (ret) { | |
1042 | dev_err(hsotg->dev, | |
1043 | "%s: failed to send reply\n", __func__); | |
1044 | return ret; | |
1045 | } | |
9c39ddc6 | 1046 | |
bd9ef7bf RB |
1047 | /* |
1048 | * we have to complete all requests for ep if it was | |
1049 | * halted, and the halt was cleared by CLEAR_FEATURE | |
1050 | */ | |
1051 | ||
1052 | if (!set && halted) { | |
9c39ddc6 AT |
1053 | /* |
1054 | * If we have request in progress, | |
1055 | * then complete it | |
1056 | */ | |
1057 | if (ep->req) { | |
1058 | hs_req = ep->req; | |
1059 | ep->req = NULL; | |
1060 | list_del_init(&hs_req->queue); | |
c00dd4a6 GH |
1061 | if (hs_req->req.complete) { |
1062 | spin_unlock(&hsotg->lock); | |
1063 | usb_gadget_giveback_request( | |
1064 | &ep->ep, &hs_req->req); | |
1065 | spin_lock(&hsotg->lock); | |
1066 | } | |
9c39ddc6 AT |
1067 | } |
1068 | ||
1069 | /* If we have pending request, then start it */ | |
c00dd4a6 GH |
1070 | if (!ep->req) { |
1071 | restart = !list_empty(&ep->queue); | |
1072 | if (restart) { | |
1073 | hs_req = get_ep_head(ep); | |
1074 | s3c_hsotg_start_req(hsotg, ep, | |
1075 | hs_req, false); | |
1076 | } | |
9c39ddc6 AT |
1077 | } |
1078 | } | |
1079 | ||
5b7d70c6 BD |
1080 | break; |
1081 | ||
1082 | default: | |
1083 | return -ENOENT; | |
1084 | } | |
9e14d0a5 GH |
1085 | break; |
1086 | default: | |
1087 | return -ENOENT; | |
1088 | } | |
5b7d70c6 BD |
1089 | return 1; |
1090 | } | |
1091 | ||
941fcce4 | 1092 | static void s3c_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg); |
ab93e014 | 1093 | |
c9f721b2 RB |
1094 | /** |
1095 | * s3c_hsotg_stall_ep0 - stall ep0 | |
1096 | * @hsotg: The device state | |
1097 | * | |
1098 | * Set stall for ep0 as response for setup request. | |
1099 | */ | |
941fcce4 | 1100 | static void s3c_hsotg_stall_ep0(struct dwc2_hsotg *hsotg) |
e9ebe7c3 | 1101 | { |
c6f5c050 | 1102 | struct s3c_hsotg_ep *ep0 = hsotg->eps_out[0]; |
c9f721b2 RB |
1103 | u32 reg; |
1104 | u32 ctrl; | |
1105 | ||
1106 | dev_dbg(hsotg->dev, "ep0 stall (dir=%d)\n", ep0->dir_in); | |
1107 | reg = (ep0->dir_in) ? DIEPCTL0 : DOEPCTL0; | |
1108 | ||
1109 | /* | |
1110 | * DxEPCTL_Stall will be cleared by EP once it has | |
1111 | * taken effect, so no need to clear later. | |
1112 | */ | |
1113 | ||
1114 | ctrl = readl(hsotg->regs + reg); | |
47a1685f DN |
1115 | ctrl |= DXEPCTL_STALL; |
1116 | ctrl |= DXEPCTL_CNAK; | |
c9f721b2 RB |
1117 | writel(ctrl, hsotg->regs + reg); |
1118 | ||
1119 | dev_dbg(hsotg->dev, | |
47a1685f | 1120 | "written DXEPCTL=0x%08x to %08x (DXEPCTL=0x%08x)\n", |
c9f721b2 RB |
1121 | ctrl, reg, readl(hsotg->regs + reg)); |
1122 | ||
1123 | /* | |
1124 | * complete won't be called, so we enqueue | |
1125 | * setup request here | |
1126 | */ | |
1127 | s3c_hsotg_enqueue_setup(hsotg); | |
1128 | } | |
1129 | ||
5b7d70c6 BD |
1130 | /** |
1131 | * s3c_hsotg_process_control - process a control request | |
1132 | * @hsotg: The device state | |
1133 | * @ctrl: The control request received | |
1134 | * | |
1135 | * The controller has received the SETUP phase of a control request, and | |
1136 | * needs to work out what to do next (and whether to pass it on to the | |
1137 | * gadget driver). | |
1138 | */ | |
941fcce4 | 1139 | static void s3c_hsotg_process_control(struct dwc2_hsotg *hsotg, |
5b7d70c6 BD |
1140 | struct usb_ctrlrequest *ctrl) |
1141 | { | |
c6f5c050 | 1142 | struct s3c_hsotg_ep *ep0 = hsotg->eps_out[0]; |
5b7d70c6 BD |
1143 | int ret = 0; |
1144 | u32 dcfg; | |
1145 | ||
5b7d70c6 BD |
1146 | dev_dbg(hsotg->dev, "ctrl Req=%02x, Type=%02x, V=%04x, L=%04x\n", |
1147 | ctrl->bRequest, ctrl->bRequestType, | |
1148 | ctrl->wValue, ctrl->wLength); | |
1149 | ||
fe0b94ab MYK |
1150 | if (ctrl->wLength == 0) { |
1151 | ep0->dir_in = 1; | |
1152 | hsotg->ep0_state = DWC2_EP0_STATUS_IN; | |
1153 | } else if (ctrl->bRequestType & USB_DIR_IN) { | |
5b7d70c6 | 1154 | ep0->dir_in = 1; |
fe0b94ab MYK |
1155 | hsotg->ep0_state = DWC2_EP0_DATA_IN; |
1156 | } else { | |
1157 | ep0->dir_in = 0; | |
1158 | hsotg->ep0_state = DWC2_EP0_DATA_OUT; | |
1159 | } | |
5b7d70c6 BD |
1160 | |
1161 | if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) { | |
1162 | switch (ctrl->bRequest) { | |
1163 | case USB_REQ_SET_ADDRESS: | |
6d713c15 | 1164 | hsotg->connected = 1; |
94cb8fd6 | 1165 | dcfg = readl(hsotg->regs + DCFG); |
47a1685f | 1166 | dcfg &= ~DCFG_DEVADDR_MASK; |
d5dbd3f7 PZ |
1167 | dcfg |= (le16_to_cpu(ctrl->wValue) << |
1168 | DCFG_DEVADDR_SHIFT) & DCFG_DEVADDR_MASK; | |
94cb8fd6 | 1169 | writel(dcfg, hsotg->regs + DCFG); |
5b7d70c6 BD |
1170 | |
1171 | dev_info(hsotg->dev, "new address %d\n", ctrl->wValue); | |
1172 | ||
1173 | ret = s3c_hsotg_send_reply(hsotg, ep0, NULL, 0); | |
1174 | return; | |
1175 | ||
1176 | case USB_REQ_GET_STATUS: | |
1177 | ret = s3c_hsotg_process_req_status(hsotg, ctrl); | |
1178 | break; | |
1179 | ||
1180 | case USB_REQ_CLEAR_FEATURE: | |
1181 | case USB_REQ_SET_FEATURE: | |
1182 | ret = s3c_hsotg_process_req_feature(hsotg, ctrl); | |
1183 | break; | |
1184 | } | |
1185 | } | |
1186 | ||
1187 | /* as a fallback, try delivering it to the driver to deal with */ | |
1188 | ||
1189 | if (ret == 0 && hsotg->driver) { | |
93f599f2 | 1190 | spin_unlock(&hsotg->lock); |
5b7d70c6 | 1191 | ret = hsotg->driver->setup(&hsotg->gadget, ctrl); |
93f599f2 | 1192 | spin_lock(&hsotg->lock); |
5b7d70c6 BD |
1193 | if (ret < 0) |
1194 | dev_dbg(hsotg->dev, "driver->setup() ret %d\n", ret); | |
1195 | } | |
1196 | ||
8b9bc460 LM |
1197 | /* |
1198 | * the request is either unhandlable, or is not formatted correctly | |
5b7d70c6 BD |
1199 | * so respond with a STALL for the status stage to indicate failure. |
1200 | */ | |
1201 | ||
c9f721b2 RB |
1202 | if (ret < 0) |
1203 | s3c_hsotg_stall_ep0(hsotg); | |
5b7d70c6 BD |
1204 | } |
1205 | ||
5b7d70c6 BD |
1206 | /** |
1207 | * s3c_hsotg_complete_setup - completion of a setup transfer | |
1208 | * @ep: The endpoint the request was on. | |
1209 | * @req: The request completed. | |
1210 | * | |
1211 | * Called on completion of any requests the driver itself submitted for | |
1212 | * EP0 setup packets | |
1213 | */ | |
1214 | static void s3c_hsotg_complete_setup(struct usb_ep *ep, | |
1215 | struct usb_request *req) | |
1216 | { | |
1217 | struct s3c_hsotg_ep *hs_ep = our_ep(ep); | |
941fcce4 | 1218 | struct dwc2_hsotg *hsotg = hs_ep->parent; |
5b7d70c6 BD |
1219 | |
1220 | if (req->status < 0) { | |
1221 | dev_dbg(hsotg->dev, "%s: failed %d\n", __func__, req->status); | |
1222 | return; | |
1223 | } | |
1224 | ||
93f599f2 | 1225 | spin_lock(&hsotg->lock); |
5b7d70c6 BD |
1226 | if (req->actual == 0) |
1227 | s3c_hsotg_enqueue_setup(hsotg); | |
1228 | else | |
1229 | s3c_hsotg_process_control(hsotg, req->buf); | |
93f599f2 | 1230 | spin_unlock(&hsotg->lock); |
5b7d70c6 BD |
1231 | } |
1232 | ||
1233 | /** | |
1234 | * s3c_hsotg_enqueue_setup - start a request for EP0 packets | |
1235 | * @hsotg: The device state. | |
1236 | * | |
1237 | * Enqueue a request on EP0 if necessary to received any SETUP packets | |
1238 | * received from the host. | |
1239 | */ | |
941fcce4 | 1240 | static void s3c_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg) |
5b7d70c6 BD |
1241 | { |
1242 | struct usb_request *req = hsotg->ctrl_req; | |
1243 | struct s3c_hsotg_req *hs_req = our_req(req); | |
1244 | int ret; | |
1245 | ||
1246 | dev_dbg(hsotg->dev, "%s: queueing setup request\n", __func__); | |
1247 | ||
1248 | req->zero = 0; | |
1249 | req->length = 8; | |
1250 | req->buf = hsotg->ctrl_buff; | |
1251 | req->complete = s3c_hsotg_complete_setup; | |
1252 | ||
1253 | if (!list_empty(&hs_req->queue)) { | |
1254 | dev_dbg(hsotg->dev, "%s already queued???\n", __func__); | |
1255 | return; | |
1256 | } | |
1257 | ||
c6f5c050 | 1258 | hsotg->eps_out[0]->dir_in = 0; |
8a20fa45 | 1259 | hsotg->eps_out[0]->send_zlp = 0; |
fe0b94ab | 1260 | hsotg->ep0_state = DWC2_EP0_SETUP; |
5b7d70c6 | 1261 | |
c6f5c050 | 1262 | ret = s3c_hsotg_ep_queue(&hsotg->eps_out[0]->ep, req, GFP_ATOMIC); |
5b7d70c6 BD |
1263 | if (ret < 0) { |
1264 | dev_err(hsotg->dev, "%s: failed queue (%d)\n", __func__, ret); | |
8b9bc460 LM |
1265 | /* |
1266 | * Don't think there's much we can do other than watch the | |
1267 | * driver fail. | |
1268 | */ | |
5b7d70c6 BD |
1269 | } |
1270 | } | |
1271 | ||
fe0b94ab MYK |
1272 | static void s3c_hsotg_program_zlp(struct dwc2_hsotg *hsotg, |
1273 | struct s3c_hsotg_ep *hs_ep) | |
1274 | { | |
1275 | u32 ctrl; | |
1276 | u8 index = hs_ep->index; | |
1277 | u32 epctl_reg = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index); | |
1278 | u32 epsiz_reg = hs_ep->dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index); | |
1279 | ||
1280 | dev_dbg(hsotg->dev, "Sending zero-length packet on ep%d\n", index); | |
1281 | ||
1282 | writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) | | |
1283 | DXEPTSIZ_XFERSIZE(0), hsotg->regs + | |
1284 | epsiz_reg); | |
1285 | ||
1286 | ctrl = readl(hsotg->regs + epctl_reg); | |
1287 | ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */ | |
1288 | ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */ | |
1289 | ctrl |= DXEPCTL_USBACTEP; | |
1290 | writel(ctrl, hsotg->regs + epctl_reg); | |
1291 | } | |
1292 | ||
5b7d70c6 BD |
1293 | /** |
1294 | * s3c_hsotg_complete_request - complete a request given to us | |
1295 | * @hsotg: The device state. | |
1296 | * @hs_ep: The endpoint the request was on. | |
1297 | * @hs_req: The request to complete. | |
1298 | * @result: The result code (0 => Ok, otherwise errno) | |
1299 | * | |
1300 | * The given request has finished, so call the necessary completion | |
1301 | * if it has one and then look to see if we can start a new request | |
1302 | * on the endpoint. | |
1303 | * | |
1304 | * Note, expects the ep to already be locked as appropriate. | |
8b9bc460 | 1305 | */ |
941fcce4 | 1306 | static void s3c_hsotg_complete_request(struct dwc2_hsotg *hsotg, |
5b7d70c6 BD |
1307 | struct s3c_hsotg_ep *hs_ep, |
1308 | struct s3c_hsotg_req *hs_req, | |
1309 | int result) | |
1310 | { | |
1311 | bool restart; | |
1312 | ||
1313 | if (!hs_req) { | |
1314 | dev_dbg(hsotg->dev, "%s: nothing to complete?\n", __func__); | |
1315 | return; | |
1316 | } | |
1317 | ||
1318 | dev_dbg(hsotg->dev, "complete: ep %p %s, req %p, %d => %p\n", | |
1319 | hs_ep, hs_ep->ep.name, hs_req, result, hs_req->req.complete); | |
1320 | ||
8b9bc460 LM |
1321 | /* |
1322 | * only replace the status if we've not already set an error | |
1323 | * from a previous transaction | |
1324 | */ | |
5b7d70c6 BD |
1325 | |
1326 | if (hs_req->req.status == -EINPROGRESS) | |
1327 | hs_req->req.status = result; | |
1328 | ||
1329 | hs_ep->req = NULL; | |
1330 | list_del_init(&hs_req->queue); | |
1331 | ||
1332 | if (using_dma(hsotg)) | |
1333 | s3c_hsotg_unmap_dma(hsotg, hs_ep, hs_req); | |
1334 | ||
8b9bc460 LM |
1335 | /* |
1336 | * call the complete request with the locks off, just in case the | |
1337 | * request tries to queue more work for this endpoint. | |
1338 | */ | |
5b7d70c6 BD |
1339 | |
1340 | if (hs_req->req.complete) { | |
22258f49 | 1341 | spin_unlock(&hsotg->lock); |
304f7e5e | 1342 | usb_gadget_giveback_request(&hs_ep->ep, &hs_req->req); |
22258f49 | 1343 | spin_lock(&hsotg->lock); |
5b7d70c6 BD |
1344 | } |
1345 | ||
8b9bc460 LM |
1346 | /* |
1347 | * Look to see if there is anything else to do. Note, the completion | |
5b7d70c6 | 1348 | * of the previous request may have caused a new request to be started |
8b9bc460 LM |
1349 | * so be careful when doing this. |
1350 | */ | |
5b7d70c6 BD |
1351 | |
1352 | if (!hs_ep->req && result >= 0) { | |
1353 | restart = !list_empty(&hs_ep->queue); | |
1354 | if (restart) { | |
1355 | hs_req = get_ep_head(hs_ep); | |
1356 | s3c_hsotg_start_req(hsotg, hs_ep, hs_req, false); | |
1357 | } | |
1358 | } | |
1359 | } | |
1360 | ||
5b7d70c6 BD |
1361 | /** |
1362 | * s3c_hsotg_rx_data - receive data from the FIFO for an endpoint | |
1363 | * @hsotg: The device state. | |
1364 | * @ep_idx: The endpoint index for the data | |
1365 | * @size: The size of data in the fifo, in bytes | |
1366 | * | |
1367 | * The FIFO status shows there is data to read from the FIFO for a given | |
1368 | * endpoint, so sort out whether we need to read the data into a request | |
1369 | * that has been made for that endpoint. | |
1370 | */ | |
941fcce4 | 1371 | static void s3c_hsotg_rx_data(struct dwc2_hsotg *hsotg, int ep_idx, int size) |
5b7d70c6 | 1372 | { |
c6f5c050 | 1373 | struct s3c_hsotg_ep *hs_ep = hsotg->eps_out[ep_idx]; |
5b7d70c6 | 1374 | struct s3c_hsotg_req *hs_req = hs_ep->req; |
94cb8fd6 | 1375 | void __iomem *fifo = hsotg->regs + EPFIFO(ep_idx); |
5b7d70c6 BD |
1376 | int to_read; |
1377 | int max_req; | |
1378 | int read_ptr; | |
1379 | ||
22258f49 | 1380 | |
5b7d70c6 | 1381 | if (!hs_req) { |
94cb8fd6 | 1382 | u32 epctl = readl(hsotg->regs + DOEPCTL(ep_idx)); |
5b7d70c6 BD |
1383 | int ptr; |
1384 | ||
6b448af4 | 1385 | dev_dbg(hsotg->dev, |
47a1685f | 1386 | "%s: FIFO %d bytes on ep%d but no req (DXEPCTl=0x%08x)\n", |
5b7d70c6 BD |
1387 | __func__, size, ep_idx, epctl); |
1388 | ||
1389 | /* dump the data from the FIFO, we've nothing we can do */ | |
1390 | for (ptr = 0; ptr < size; ptr += 4) | |
1391 | (void)readl(fifo); | |
1392 | ||
1393 | return; | |
1394 | } | |
1395 | ||
5b7d70c6 BD |
1396 | to_read = size; |
1397 | read_ptr = hs_req->req.actual; | |
1398 | max_req = hs_req->req.length - read_ptr; | |
1399 | ||
a33e7136 BD |
1400 | dev_dbg(hsotg->dev, "%s: read %d/%d, done %d/%d\n", |
1401 | __func__, to_read, max_req, read_ptr, hs_req->req.length); | |
1402 | ||
5b7d70c6 | 1403 | if (to_read > max_req) { |
8b9bc460 LM |
1404 | /* |
1405 | * more data appeared than we where willing | |
5b7d70c6 BD |
1406 | * to deal with in this request. |
1407 | */ | |
1408 | ||
1409 | /* currently we don't deal this */ | |
1410 | WARN_ON_ONCE(1); | |
1411 | } | |
1412 | ||
5b7d70c6 BD |
1413 | hs_ep->total_data += to_read; |
1414 | hs_req->req.actual += to_read; | |
1415 | to_read = DIV_ROUND_UP(to_read, 4); | |
1416 | ||
8b9bc460 LM |
1417 | /* |
1418 | * note, we might over-write the buffer end by 3 bytes depending on | |
1419 | * alignment of the data. | |
1420 | */ | |
1a7ed5be | 1421 | ioread32_rep(fifo, hs_req->req.buf + read_ptr, to_read); |
5b7d70c6 BD |
1422 | } |
1423 | ||
1424 | /** | |
fe0b94ab | 1425 | * s3c_hsotg_ep0_zlp - send/receive zero-length packet on control endpoint |
5b7d70c6 | 1426 | * @hsotg: The device instance |
fe0b94ab | 1427 | * @dir_in: If IN zlp |
5b7d70c6 BD |
1428 | * |
1429 | * Generate a zero-length IN packet request for terminating a SETUP | |
1430 | * transaction. | |
1431 | * | |
1432 | * Note, since we don't write any data to the TxFIFO, then it is | |
25985edc | 1433 | * currently believed that we do not need to wait for any space in |
5b7d70c6 BD |
1434 | * the TxFIFO. |
1435 | */ | |
fe0b94ab | 1436 | static void s3c_hsotg_ep0_zlp(struct dwc2_hsotg *hsotg, bool dir_in) |
5b7d70c6 | 1437 | { |
c6f5c050 | 1438 | /* eps_out[0] is used in both directions */ |
fe0b94ab MYK |
1439 | hsotg->eps_out[0]->dir_in = dir_in; |
1440 | hsotg->ep0_state = dir_in ? DWC2_EP0_STATUS_IN : DWC2_EP0_STATUS_OUT; | |
5b7d70c6 | 1441 | |
fe0b94ab | 1442 | s3c_hsotg_program_zlp(hsotg, hsotg->eps_out[0]); |
5b7d70c6 BD |
1443 | } |
1444 | ||
1445 | /** | |
1446 | * s3c_hsotg_handle_outdone - handle receiving OutDone/SetupDone from RXFIFO | |
1447 | * @hsotg: The device instance | |
1448 | * @epnum: The endpoint received from | |
5b7d70c6 BD |
1449 | * |
1450 | * The RXFIFO has delivered an OutDone event, which means that the data | |
1451 | * transfer for an OUT endpoint has been completed, either by a short | |
1452 | * packet or by the finish of a transfer. | |
8b9bc460 | 1453 | */ |
fe0b94ab | 1454 | static void s3c_hsotg_handle_outdone(struct dwc2_hsotg *hsotg, int epnum) |
5b7d70c6 | 1455 | { |
94cb8fd6 | 1456 | u32 epsize = readl(hsotg->regs + DOEPTSIZ(epnum)); |
c6f5c050 | 1457 | struct s3c_hsotg_ep *hs_ep = hsotg->eps_out[epnum]; |
5b7d70c6 BD |
1458 | struct s3c_hsotg_req *hs_req = hs_ep->req; |
1459 | struct usb_request *req = &hs_req->req; | |
47a1685f | 1460 | unsigned size_left = DXEPTSIZ_XFERSIZE_GET(epsize); |
5b7d70c6 BD |
1461 | int result = 0; |
1462 | ||
1463 | if (!hs_req) { | |
1464 | dev_dbg(hsotg->dev, "%s: no request active\n", __func__); | |
1465 | return; | |
1466 | } | |
1467 | ||
fe0b94ab MYK |
1468 | if (epnum == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_OUT) { |
1469 | dev_dbg(hsotg->dev, "zlp packet received\n"); | |
1470 | s3c_hsotg_complete_request(hsotg, hs_ep, hs_req, 0); | |
1471 | s3c_hsotg_enqueue_setup(hsotg); | |
1472 | return; | |
1473 | } | |
1474 | ||
5b7d70c6 | 1475 | if (using_dma(hsotg)) { |
5b7d70c6 | 1476 | unsigned size_done; |
5b7d70c6 | 1477 | |
8b9bc460 LM |
1478 | /* |
1479 | * Calculate the size of the transfer by checking how much | |
5b7d70c6 BD |
1480 | * is left in the endpoint size register and then working it |
1481 | * out from the amount we loaded for the transfer. | |
1482 | * | |
1483 | * We need to do this as DMA pointers are always 32bit aligned | |
1484 | * so may overshoot/undershoot the transfer. | |
1485 | */ | |
1486 | ||
5b7d70c6 BD |
1487 | size_done = hs_ep->size_loaded - size_left; |
1488 | size_done += hs_ep->last_load; | |
1489 | ||
1490 | req->actual = size_done; | |
1491 | } | |
1492 | ||
a33e7136 BD |
1493 | /* if there is more request to do, schedule new transfer */ |
1494 | if (req->actual < req->length && size_left == 0) { | |
1495 | s3c_hsotg_start_req(hsotg, hs_ep, hs_req, true); | |
1496 | return; | |
1497 | } | |
1498 | ||
5b7d70c6 BD |
1499 | if (req->actual < req->length && req->short_not_ok) { |
1500 | dev_dbg(hsotg->dev, "%s: got %d/%d (short not ok) => error\n", | |
1501 | __func__, req->actual, req->length); | |
1502 | ||
8b9bc460 LM |
1503 | /* |
1504 | * todo - what should we return here? there's no one else | |
1505 | * even bothering to check the status. | |
1506 | */ | |
5b7d70c6 BD |
1507 | } |
1508 | ||
fe0b94ab MYK |
1509 | if (epnum == 0 && hsotg->ep0_state == DWC2_EP0_DATA_OUT) { |
1510 | /* Move to STATUS IN */ | |
1511 | s3c_hsotg_ep0_zlp(hsotg, true); | |
1512 | return; | |
5b7d70c6 BD |
1513 | } |
1514 | ||
5ad1d316 | 1515 | s3c_hsotg_complete_request(hsotg, hs_ep, hs_req, result); |
5b7d70c6 BD |
1516 | } |
1517 | ||
1518 | /** | |
1519 | * s3c_hsotg_read_frameno - read current frame number | |
1520 | * @hsotg: The device instance | |
1521 | * | |
1522 | * Return the current frame number | |
8b9bc460 | 1523 | */ |
941fcce4 | 1524 | static u32 s3c_hsotg_read_frameno(struct dwc2_hsotg *hsotg) |
5b7d70c6 BD |
1525 | { |
1526 | u32 dsts; | |
1527 | ||
94cb8fd6 LM |
1528 | dsts = readl(hsotg->regs + DSTS); |
1529 | dsts &= DSTS_SOFFN_MASK; | |
1530 | dsts >>= DSTS_SOFFN_SHIFT; | |
5b7d70c6 BD |
1531 | |
1532 | return dsts; | |
1533 | } | |
1534 | ||
1535 | /** | |
1536 | * s3c_hsotg_handle_rx - RX FIFO has data | |
1537 | * @hsotg: The device instance | |
1538 | * | |
1539 | * The IRQ handler has detected that the RX FIFO has some data in it | |
1540 | * that requires processing, so find out what is in there and do the | |
1541 | * appropriate read. | |
1542 | * | |
25985edc | 1543 | * The RXFIFO is a true FIFO, the packets coming out are still in packet |
5b7d70c6 BD |
1544 | * chunks, so if you have x packets received on an endpoint you'll get x |
1545 | * FIFO events delivered, each with a packet's worth of data in it. | |
1546 | * | |
1547 | * When using DMA, we should not be processing events from the RXFIFO | |
1548 | * as the actual data should be sent to the memory directly and we turn | |
1549 | * on the completion interrupts to get notifications of transfer completion. | |
1550 | */ | |
941fcce4 | 1551 | static void s3c_hsotg_handle_rx(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 1552 | { |
94cb8fd6 | 1553 | u32 grxstsr = readl(hsotg->regs + GRXSTSP); |
5b7d70c6 BD |
1554 | u32 epnum, status, size; |
1555 | ||
1556 | WARN_ON(using_dma(hsotg)); | |
1557 | ||
47a1685f DN |
1558 | epnum = grxstsr & GRXSTS_EPNUM_MASK; |
1559 | status = grxstsr & GRXSTS_PKTSTS_MASK; | |
5b7d70c6 | 1560 | |
47a1685f DN |
1561 | size = grxstsr & GRXSTS_BYTECNT_MASK; |
1562 | size >>= GRXSTS_BYTECNT_SHIFT; | |
5b7d70c6 | 1563 | |
d7c747c5 | 1564 | dev_dbg(hsotg->dev, "%s: GRXSTSP=0x%08x (%d@%d)\n", |
5b7d70c6 BD |
1565 | __func__, grxstsr, size, epnum); |
1566 | ||
47a1685f DN |
1567 | switch ((status & GRXSTS_PKTSTS_MASK) >> GRXSTS_PKTSTS_SHIFT) { |
1568 | case GRXSTS_PKTSTS_GLOBALOUTNAK: | |
1569 | dev_dbg(hsotg->dev, "GLOBALOUTNAK\n"); | |
5b7d70c6 BD |
1570 | break; |
1571 | ||
47a1685f | 1572 | case GRXSTS_PKTSTS_OUTDONE: |
5b7d70c6 BD |
1573 | dev_dbg(hsotg->dev, "OutDone (Frame=0x%08x)\n", |
1574 | s3c_hsotg_read_frameno(hsotg)); | |
1575 | ||
1576 | if (!using_dma(hsotg)) | |
fe0b94ab | 1577 | s3c_hsotg_handle_outdone(hsotg, epnum); |
5b7d70c6 BD |
1578 | break; |
1579 | ||
47a1685f | 1580 | case GRXSTS_PKTSTS_SETUPDONE: |
5b7d70c6 BD |
1581 | dev_dbg(hsotg->dev, |
1582 | "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n", | |
1583 | s3c_hsotg_read_frameno(hsotg), | |
94cb8fd6 | 1584 | readl(hsotg->regs + DOEPCTL(0))); |
fe0b94ab MYK |
1585 | /* |
1586 | * Call s3c_hsotg_handle_outdone here if it was not called from | |
1587 | * GRXSTS_PKTSTS_OUTDONE. That is, if the core didn't | |
1588 | * generate GRXSTS_PKTSTS_OUTDONE for setup packet. | |
1589 | */ | |
1590 | if (hsotg->ep0_state == DWC2_EP0_SETUP) | |
1591 | s3c_hsotg_handle_outdone(hsotg, epnum); | |
5b7d70c6 BD |
1592 | break; |
1593 | ||
47a1685f | 1594 | case GRXSTS_PKTSTS_OUTRX: |
5b7d70c6 BD |
1595 | s3c_hsotg_rx_data(hsotg, epnum, size); |
1596 | break; | |
1597 | ||
47a1685f | 1598 | case GRXSTS_PKTSTS_SETUPRX: |
5b7d70c6 BD |
1599 | dev_dbg(hsotg->dev, |
1600 | "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n", | |
1601 | s3c_hsotg_read_frameno(hsotg), | |
94cb8fd6 | 1602 | readl(hsotg->regs + DOEPCTL(0))); |
5b7d70c6 | 1603 | |
fe0b94ab MYK |
1604 | WARN_ON(hsotg->ep0_state != DWC2_EP0_SETUP); |
1605 | ||
5b7d70c6 BD |
1606 | s3c_hsotg_rx_data(hsotg, epnum, size); |
1607 | break; | |
1608 | ||
1609 | default: | |
1610 | dev_warn(hsotg->dev, "%s: unknown status %08x\n", | |
1611 | __func__, grxstsr); | |
1612 | ||
1613 | s3c_hsotg_dump(hsotg); | |
1614 | break; | |
1615 | } | |
1616 | } | |
1617 | ||
1618 | /** | |
1619 | * s3c_hsotg_ep0_mps - turn max packet size into register setting | |
1620 | * @mps: The maximum packet size in bytes. | |
8b9bc460 | 1621 | */ |
5b7d70c6 BD |
1622 | static u32 s3c_hsotg_ep0_mps(unsigned int mps) |
1623 | { | |
1624 | switch (mps) { | |
1625 | case 64: | |
94cb8fd6 | 1626 | return D0EPCTL_MPS_64; |
5b7d70c6 | 1627 | case 32: |
94cb8fd6 | 1628 | return D0EPCTL_MPS_32; |
5b7d70c6 | 1629 | case 16: |
94cb8fd6 | 1630 | return D0EPCTL_MPS_16; |
5b7d70c6 | 1631 | case 8: |
94cb8fd6 | 1632 | return D0EPCTL_MPS_8; |
5b7d70c6 BD |
1633 | } |
1634 | ||
1635 | /* bad max packet size, warn and return invalid result */ | |
1636 | WARN_ON(1); | |
1637 | return (u32)-1; | |
1638 | } | |
1639 | ||
1640 | /** | |
1641 | * s3c_hsotg_set_ep_maxpacket - set endpoint's max-packet field | |
1642 | * @hsotg: The driver state. | |
1643 | * @ep: The index number of the endpoint | |
1644 | * @mps: The maximum packet size in bytes | |
1645 | * | |
1646 | * Configure the maximum packet size for the given endpoint, updating | |
1647 | * the hardware control registers to reflect this. | |
1648 | */ | |
941fcce4 | 1649 | static void s3c_hsotg_set_ep_maxpacket(struct dwc2_hsotg *hsotg, |
c6f5c050 | 1650 | unsigned int ep, unsigned int mps, unsigned int dir_in) |
5b7d70c6 | 1651 | { |
c6f5c050 | 1652 | struct s3c_hsotg_ep *hs_ep; |
5b7d70c6 BD |
1653 | void __iomem *regs = hsotg->regs; |
1654 | u32 mpsval; | |
4fca54aa | 1655 | u32 mcval; |
5b7d70c6 BD |
1656 | u32 reg; |
1657 | ||
c6f5c050 MYK |
1658 | hs_ep = index_to_ep(hsotg, ep, dir_in); |
1659 | if (!hs_ep) | |
1660 | return; | |
1661 | ||
5b7d70c6 BD |
1662 | if (ep == 0) { |
1663 | /* EP0 is a special case */ | |
1664 | mpsval = s3c_hsotg_ep0_mps(mps); | |
1665 | if (mpsval > 3) | |
1666 | goto bad_mps; | |
e9edd199 | 1667 | hs_ep->ep.maxpacket = mps; |
4fca54aa | 1668 | hs_ep->mc = 1; |
5b7d70c6 | 1669 | } else { |
47a1685f | 1670 | mpsval = mps & DXEPCTL_MPS_MASK; |
e9edd199 | 1671 | if (mpsval > 1024) |
5b7d70c6 | 1672 | goto bad_mps; |
4fca54aa RB |
1673 | mcval = ((mps >> 11) & 0x3) + 1; |
1674 | hs_ep->mc = mcval; | |
1675 | if (mcval > 3) | |
1676 | goto bad_mps; | |
e9edd199 | 1677 | hs_ep->ep.maxpacket = mpsval; |
5b7d70c6 BD |
1678 | } |
1679 | ||
c6f5c050 MYK |
1680 | if (dir_in) { |
1681 | reg = readl(regs + DIEPCTL(ep)); | |
1682 | reg &= ~DXEPCTL_MPS_MASK; | |
1683 | reg |= mpsval; | |
1684 | writel(reg, regs + DIEPCTL(ep)); | |
1685 | } else { | |
94cb8fd6 | 1686 | reg = readl(regs + DOEPCTL(ep)); |
47a1685f | 1687 | reg &= ~DXEPCTL_MPS_MASK; |
659ad60c | 1688 | reg |= mpsval; |
94cb8fd6 | 1689 | writel(reg, regs + DOEPCTL(ep)); |
659ad60c | 1690 | } |
5b7d70c6 BD |
1691 | |
1692 | return; | |
1693 | ||
1694 | bad_mps: | |
1695 | dev_err(hsotg->dev, "ep%d: bad mps of %d\n", ep, mps); | |
1696 | } | |
1697 | ||
9c39ddc6 AT |
1698 | /** |
1699 | * s3c_hsotg_txfifo_flush - flush Tx FIFO | |
1700 | * @hsotg: The driver state | |
1701 | * @idx: The index for the endpoint (0..15) | |
1702 | */ | |
941fcce4 | 1703 | static void s3c_hsotg_txfifo_flush(struct dwc2_hsotg *hsotg, unsigned int idx) |
9c39ddc6 AT |
1704 | { |
1705 | int timeout; | |
1706 | int val; | |
1707 | ||
47a1685f | 1708 | writel(GRSTCTL_TXFNUM(idx) | GRSTCTL_TXFFLSH, |
94cb8fd6 | 1709 | hsotg->regs + GRSTCTL); |
9c39ddc6 AT |
1710 | |
1711 | /* wait until the fifo is flushed */ | |
1712 | timeout = 100; | |
1713 | ||
1714 | while (1) { | |
94cb8fd6 | 1715 | val = readl(hsotg->regs + GRSTCTL); |
9c39ddc6 | 1716 | |
47a1685f | 1717 | if ((val & (GRSTCTL_TXFFLSH)) == 0) |
9c39ddc6 AT |
1718 | break; |
1719 | ||
1720 | if (--timeout == 0) { | |
1721 | dev_err(hsotg->dev, | |
1722 | "%s: timeout flushing fifo (GRSTCTL=%08x)\n", | |
1723 | __func__, val); | |
e0cbe595 | 1724 | break; |
9c39ddc6 AT |
1725 | } |
1726 | ||
1727 | udelay(1); | |
1728 | } | |
1729 | } | |
5b7d70c6 BD |
1730 | |
1731 | /** | |
1732 | * s3c_hsotg_trytx - check to see if anything needs transmitting | |
1733 | * @hsotg: The driver state | |
1734 | * @hs_ep: The driver endpoint to check. | |
1735 | * | |
1736 | * Check to see if there is a request that has data to send, and if so | |
1737 | * make an attempt to write data into the FIFO. | |
1738 | */ | |
941fcce4 | 1739 | static int s3c_hsotg_trytx(struct dwc2_hsotg *hsotg, |
5b7d70c6 BD |
1740 | struct s3c_hsotg_ep *hs_ep) |
1741 | { | |
1742 | struct s3c_hsotg_req *hs_req = hs_ep->req; | |
1743 | ||
afcf4169 RB |
1744 | if (!hs_ep->dir_in || !hs_req) { |
1745 | /** | |
1746 | * if request is not enqueued, we disable interrupts | |
1747 | * for endpoints, excepting ep0 | |
1748 | */ | |
1749 | if (hs_ep->index != 0) | |
1750 | s3c_hsotg_ctrl_epint(hsotg, hs_ep->index, | |
1751 | hs_ep->dir_in, 0); | |
5b7d70c6 | 1752 | return 0; |
afcf4169 | 1753 | } |
5b7d70c6 BD |
1754 | |
1755 | if (hs_req->req.actual < hs_req->req.length) { | |
1756 | dev_dbg(hsotg->dev, "trying to write more for ep%d\n", | |
1757 | hs_ep->index); | |
1758 | return s3c_hsotg_write_fifo(hsotg, hs_ep, hs_req); | |
1759 | } | |
1760 | ||
1761 | return 0; | |
1762 | } | |
1763 | ||
1764 | /** | |
1765 | * s3c_hsotg_complete_in - complete IN transfer | |
1766 | * @hsotg: The device state. | |
1767 | * @hs_ep: The endpoint that has just completed. | |
1768 | * | |
1769 | * An IN transfer has been completed, update the transfer's state and then | |
1770 | * call the relevant completion routines. | |
1771 | */ | |
941fcce4 | 1772 | static void s3c_hsotg_complete_in(struct dwc2_hsotg *hsotg, |
5b7d70c6 BD |
1773 | struct s3c_hsotg_ep *hs_ep) |
1774 | { | |
1775 | struct s3c_hsotg_req *hs_req = hs_ep->req; | |
94cb8fd6 | 1776 | u32 epsize = readl(hsotg->regs + DIEPTSIZ(hs_ep->index)); |
5b7d70c6 BD |
1777 | int size_left, size_done; |
1778 | ||
1779 | if (!hs_req) { | |
1780 | dev_dbg(hsotg->dev, "XferCompl but no req\n"); | |
1781 | return; | |
1782 | } | |
1783 | ||
d3ca0259 | 1784 | /* Finish ZLP handling for IN EP0 transactions */ |
fe0b94ab MYK |
1785 | if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_IN) { |
1786 | dev_dbg(hsotg->dev, "zlp packet sent\n"); | |
5ad1d316 | 1787 | s3c_hsotg_complete_request(hsotg, hs_ep, hs_req, 0); |
9e14d0a5 GH |
1788 | if (hsotg->test_mode) { |
1789 | int ret; | |
1790 | ||
1791 | ret = s3c_hsotg_set_test_mode(hsotg, hsotg->test_mode); | |
1792 | if (ret < 0) { | |
1793 | dev_dbg(hsotg->dev, "Invalid Test #%d\n", | |
1794 | hsotg->test_mode); | |
1795 | s3c_hsotg_stall_ep0(hsotg); | |
1796 | return; | |
1797 | } | |
1798 | } | |
fe0b94ab | 1799 | s3c_hsotg_enqueue_setup(hsotg); |
d3ca0259 LM |
1800 | return; |
1801 | } | |
1802 | ||
8b9bc460 LM |
1803 | /* |
1804 | * Calculate the size of the transfer by checking how much is left | |
5b7d70c6 BD |
1805 | * in the endpoint size register and then working it out from |
1806 | * the amount we loaded for the transfer. | |
1807 | * | |
1808 | * We do this even for DMA, as the transfer may have incremented | |
1809 | * past the end of the buffer (DMA transfers are always 32bit | |
1810 | * aligned). | |
1811 | */ | |
1812 | ||
47a1685f | 1813 | size_left = DXEPTSIZ_XFERSIZE_GET(epsize); |
5b7d70c6 BD |
1814 | |
1815 | size_done = hs_ep->size_loaded - size_left; | |
1816 | size_done += hs_ep->last_load; | |
1817 | ||
1818 | if (hs_req->req.actual != size_done) | |
1819 | dev_dbg(hsotg->dev, "%s: adjusting size done %d => %d\n", | |
1820 | __func__, hs_req->req.actual, size_done); | |
1821 | ||
1822 | hs_req->req.actual = size_done; | |
d3ca0259 LM |
1823 | dev_dbg(hsotg->dev, "req->length:%d req->actual:%d req->zero:%d\n", |
1824 | hs_req->req.length, hs_req->req.actual, hs_req->req.zero); | |
1825 | ||
5b7d70c6 BD |
1826 | if (!size_left && hs_req->req.actual < hs_req->req.length) { |
1827 | dev_dbg(hsotg->dev, "%s trying more for req...\n", __func__); | |
1828 | s3c_hsotg_start_req(hsotg, hs_ep, hs_req, true); | |
fe0b94ab MYK |
1829 | return; |
1830 | } | |
1831 | ||
f71b5e25 | 1832 | /* Zlp for all endpoints, for ep0 only in DATA IN stage */ |
8a20fa45 | 1833 | if (hs_ep->send_zlp) { |
f71b5e25 | 1834 | s3c_hsotg_program_zlp(hsotg, hs_ep); |
8a20fa45 | 1835 | hs_ep->send_zlp = 0; |
f71b5e25 MYK |
1836 | /* transfer will be completed on next complete interrupt */ |
1837 | return; | |
1838 | } | |
1839 | ||
fe0b94ab MYK |
1840 | if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_DATA_IN) { |
1841 | /* Move to STATUS OUT */ | |
1842 | s3c_hsotg_ep0_zlp(hsotg, false); | |
1843 | return; | |
1844 | } | |
1845 | ||
1846 | s3c_hsotg_complete_request(hsotg, hs_ep, hs_req, 0); | |
5b7d70c6 BD |
1847 | } |
1848 | ||
1849 | /** | |
1850 | * s3c_hsotg_epint - handle an in/out endpoint interrupt | |
1851 | * @hsotg: The driver state | |
1852 | * @idx: The index for the endpoint (0..15) | |
1853 | * @dir_in: Set if this is an IN endpoint | |
1854 | * | |
1855 | * Process and clear any interrupt pending for an individual endpoint | |
8b9bc460 | 1856 | */ |
941fcce4 | 1857 | static void s3c_hsotg_epint(struct dwc2_hsotg *hsotg, unsigned int idx, |
5b7d70c6 BD |
1858 | int dir_in) |
1859 | { | |
c6f5c050 | 1860 | struct s3c_hsotg_ep *hs_ep = index_to_ep(hsotg, idx, dir_in); |
94cb8fd6 LM |
1861 | u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx); |
1862 | u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx); | |
1863 | u32 epsiz_reg = dir_in ? DIEPTSIZ(idx) : DOEPTSIZ(idx); | |
5b7d70c6 | 1864 | u32 ints; |
1479e841 | 1865 | u32 ctrl; |
5b7d70c6 BD |
1866 | |
1867 | ints = readl(hsotg->regs + epint_reg); | |
1479e841 | 1868 | ctrl = readl(hsotg->regs + epctl_reg); |
5b7d70c6 | 1869 | |
a3395f0d AT |
1870 | /* Clear endpoint interrupts */ |
1871 | writel(ints, hsotg->regs + epint_reg); | |
1872 | ||
c6f5c050 MYK |
1873 | if (!hs_ep) { |
1874 | dev_err(hsotg->dev, "%s:Interrupt for unconfigured ep%d(%s)\n", | |
1875 | __func__, idx, dir_in ? "in" : "out"); | |
1876 | return; | |
1877 | } | |
1878 | ||
5b7d70c6 BD |
1879 | dev_dbg(hsotg->dev, "%s: ep%d(%s) DxEPINT=0x%08x\n", |
1880 | __func__, idx, dir_in ? "in" : "out", ints); | |
1881 | ||
b787d755 MYK |
1882 | /* Don't process XferCompl interrupt if it is a setup packet */ |
1883 | if (idx == 0 && (ints & (DXEPINT_SETUP | DXEPINT_SETUP_RCVD))) | |
1884 | ints &= ~DXEPINT_XFERCOMPL; | |
1885 | ||
47a1685f | 1886 | if (ints & DXEPINT_XFERCOMPL) { |
1479e841 | 1887 | if (hs_ep->isochronous && hs_ep->interval == 1) { |
47a1685f DN |
1888 | if (ctrl & DXEPCTL_EOFRNUM) |
1889 | ctrl |= DXEPCTL_SETEVENFR; | |
1479e841 | 1890 | else |
47a1685f | 1891 | ctrl |= DXEPCTL_SETODDFR; |
1479e841 RB |
1892 | writel(ctrl, hsotg->regs + epctl_reg); |
1893 | } | |
1894 | ||
5b7d70c6 | 1895 | dev_dbg(hsotg->dev, |
47a1685f | 1896 | "%s: XferCompl: DxEPCTL=0x%08x, DXEPTSIZ=%08x\n", |
5b7d70c6 BD |
1897 | __func__, readl(hsotg->regs + epctl_reg), |
1898 | readl(hsotg->regs + epsiz_reg)); | |
1899 | ||
8b9bc460 LM |
1900 | /* |
1901 | * we get OutDone from the FIFO, so we only need to look | |
1902 | * at completing IN requests here | |
1903 | */ | |
5b7d70c6 BD |
1904 | if (dir_in) { |
1905 | s3c_hsotg_complete_in(hsotg, hs_ep); | |
1906 | ||
c9a64ea8 | 1907 | if (idx == 0 && !hs_ep->req) |
5b7d70c6 BD |
1908 | s3c_hsotg_enqueue_setup(hsotg); |
1909 | } else if (using_dma(hsotg)) { | |
8b9bc460 LM |
1910 | /* |
1911 | * We're using DMA, we need to fire an OutDone here | |
1912 | * as we ignore the RXFIFO. | |
1913 | */ | |
5b7d70c6 | 1914 | |
fe0b94ab | 1915 | s3c_hsotg_handle_outdone(hsotg, idx); |
5b7d70c6 | 1916 | } |
5b7d70c6 BD |
1917 | } |
1918 | ||
47a1685f | 1919 | if (ints & DXEPINT_EPDISBLD) { |
5b7d70c6 | 1920 | dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__); |
5b7d70c6 | 1921 | |
9c39ddc6 AT |
1922 | if (dir_in) { |
1923 | int epctl = readl(hsotg->regs + epctl_reg); | |
1924 | ||
b203d0a2 | 1925 | s3c_hsotg_txfifo_flush(hsotg, hs_ep->fifo_index); |
9c39ddc6 | 1926 | |
47a1685f DN |
1927 | if ((epctl & DXEPCTL_STALL) && |
1928 | (epctl & DXEPCTL_EPTYPE_BULK)) { | |
94cb8fd6 | 1929 | int dctl = readl(hsotg->regs + DCTL); |
9c39ddc6 | 1930 | |
47a1685f | 1931 | dctl |= DCTL_CGNPINNAK; |
94cb8fd6 | 1932 | writel(dctl, hsotg->regs + DCTL); |
9c39ddc6 AT |
1933 | } |
1934 | } | |
1935 | } | |
1936 | ||
47a1685f | 1937 | if (ints & DXEPINT_AHBERR) |
5b7d70c6 | 1938 | dev_dbg(hsotg->dev, "%s: AHBErr\n", __func__); |
5b7d70c6 | 1939 | |
47a1685f | 1940 | if (ints & DXEPINT_SETUP) { /* Setup or Timeout */ |
5b7d70c6 BD |
1941 | dev_dbg(hsotg->dev, "%s: Setup/Timeout\n", __func__); |
1942 | ||
1943 | if (using_dma(hsotg) && idx == 0) { | |
8b9bc460 LM |
1944 | /* |
1945 | * this is the notification we've received a | |
5b7d70c6 BD |
1946 | * setup packet. In non-DMA mode we'd get this |
1947 | * from the RXFIFO, instead we need to process | |
8b9bc460 LM |
1948 | * the setup here. |
1949 | */ | |
5b7d70c6 BD |
1950 | |
1951 | if (dir_in) | |
1952 | WARN_ON_ONCE(1); | |
1953 | else | |
fe0b94ab | 1954 | s3c_hsotg_handle_outdone(hsotg, 0); |
5b7d70c6 | 1955 | } |
5b7d70c6 BD |
1956 | } |
1957 | ||
47a1685f | 1958 | if (ints & DXEPINT_BACK2BACKSETUP) |
5b7d70c6 | 1959 | dev_dbg(hsotg->dev, "%s: B2BSetup/INEPNakEff\n", __func__); |
5b7d70c6 | 1960 | |
1479e841 | 1961 | if (dir_in && !hs_ep->isochronous) { |
8b9bc460 | 1962 | /* not sure if this is important, but we'll clear it anyway */ |
47a1685f | 1963 | if (ints & DIEPMSK_INTKNTXFEMPMSK) { |
5b7d70c6 BD |
1964 | dev_dbg(hsotg->dev, "%s: ep%d: INTknTXFEmpMsk\n", |
1965 | __func__, idx); | |
5b7d70c6 BD |
1966 | } |
1967 | ||
1968 | /* this probably means something bad is happening */ | |
47a1685f | 1969 | if (ints & DIEPMSK_INTKNEPMISMSK) { |
5b7d70c6 BD |
1970 | dev_warn(hsotg->dev, "%s: ep%d: INTknEP\n", |
1971 | __func__, idx); | |
5b7d70c6 | 1972 | } |
10aebc77 BD |
1973 | |
1974 | /* FIFO has space or is empty (see GAHBCFG) */ | |
1975 | if (hsotg->dedicated_fifos && | |
47a1685f | 1976 | ints & DIEPMSK_TXFIFOEMPTY) { |
10aebc77 BD |
1977 | dev_dbg(hsotg->dev, "%s: ep%d: TxFIFOEmpty\n", |
1978 | __func__, idx); | |
70fa030f AT |
1979 | if (!using_dma(hsotg)) |
1980 | s3c_hsotg_trytx(hsotg, hs_ep); | |
10aebc77 | 1981 | } |
5b7d70c6 | 1982 | } |
5b7d70c6 BD |
1983 | } |
1984 | ||
1985 | /** | |
1986 | * s3c_hsotg_irq_enumdone - Handle EnumDone interrupt (enumeration done) | |
1987 | * @hsotg: The device state. | |
1988 | * | |
1989 | * Handle updating the device settings after the enumeration phase has | |
1990 | * been completed. | |
8b9bc460 | 1991 | */ |
941fcce4 | 1992 | static void s3c_hsotg_irq_enumdone(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 1993 | { |
94cb8fd6 | 1994 | u32 dsts = readl(hsotg->regs + DSTS); |
9b2667f1 | 1995 | int ep0_mps = 0, ep_mps = 8; |
5b7d70c6 | 1996 | |
8b9bc460 LM |
1997 | /* |
1998 | * This should signal the finish of the enumeration phase | |
5b7d70c6 | 1999 | * of the USB handshaking, so we should now know what rate |
8b9bc460 LM |
2000 | * we connected at. |
2001 | */ | |
5b7d70c6 BD |
2002 | |
2003 | dev_dbg(hsotg->dev, "EnumDone (DSTS=0x%08x)\n", dsts); | |
2004 | ||
8b9bc460 LM |
2005 | /* |
2006 | * note, since we're limited by the size of transfer on EP0, and | |
5b7d70c6 | 2007 | * it seems IN transfers must be a even number of packets we do |
8b9bc460 LM |
2008 | * not advertise a 64byte MPS on EP0. |
2009 | */ | |
5b7d70c6 BD |
2010 | |
2011 | /* catch both EnumSpd_FS and EnumSpd_FS48 */ | |
47a1685f DN |
2012 | switch (dsts & DSTS_ENUMSPD_MASK) { |
2013 | case DSTS_ENUMSPD_FS: | |
2014 | case DSTS_ENUMSPD_FS48: | |
5b7d70c6 | 2015 | hsotg->gadget.speed = USB_SPEED_FULL; |
5b7d70c6 | 2016 | ep0_mps = EP0_MPS_LIMIT; |
295538ff | 2017 | ep_mps = 1023; |
5b7d70c6 BD |
2018 | break; |
2019 | ||
47a1685f | 2020 | case DSTS_ENUMSPD_HS: |
5b7d70c6 | 2021 | hsotg->gadget.speed = USB_SPEED_HIGH; |
5b7d70c6 | 2022 | ep0_mps = EP0_MPS_LIMIT; |
295538ff | 2023 | ep_mps = 1024; |
5b7d70c6 BD |
2024 | break; |
2025 | ||
47a1685f | 2026 | case DSTS_ENUMSPD_LS: |
5b7d70c6 | 2027 | hsotg->gadget.speed = USB_SPEED_LOW; |
8b9bc460 LM |
2028 | /* |
2029 | * note, we don't actually support LS in this driver at the | |
5b7d70c6 BD |
2030 | * moment, and the documentation seems to imply that it isn't |
2031 | * supported by the PHYs on some of the devices. | |
2032 | */ | |
2033 | break; | |
2034 | } | |
e538dfda MN |
2035 | dev_info(hsotg->dev, "new device is %s\n", |
2036 | usb_speed_string(hsotg->gadget.speed)); | |
5b7d70c6 | 2037 | |
8b9bc460 LM |
2038 | /* |
2039 | * we should now know the maximum packet size for an | |
2040 | * endpoint, so set the endpoints to a default value. | |
2041 | */ | |
5b7d70c6 BD |
2042 | |
2043 | if (ep0_mps) { | |
2044 | int i; | |
c6f5c050 MYK |
2045 | /* Initialize ep0 for both in and out directions */ |
2046 | s3c_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 1); | |
2047 | s3c_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 0); | |
2048 | for (i = 1; i < hsotg->num_of_eps; i++) { | |
2049 | if (hsotg->eps_in[i]) | |
2050 | s3c_hsotg_set_ep_maxpacket(hsotg, i, ep_mps, 1); | |
2051 | if (hsotg->eps_out[i]) | |
2052 | s3c_hsotg_set_ep_maxpacket(hsotg, i, ep_mps, 0); | |
2053 | } | |
5b7d70c6 BD |
2054 | } |
2055 | ||
2056 | /* ensure after enumeration our EP0 is active */ | |
2057 | ||
2058 | s3c_hsotg_enqueue_setup(hsotg); | |
2059 | ||
2060 | dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n", | |
94cb8fd6 LM |
2061 | readl(hsotg->regs + DIEPCTL0), |
2062 | readl(hsotg->regs + DOEPCTL0)); | |
5b7d70c6 BD |
2063 | } |
2064 | ||
2065 | /** | |
2066 | * kill_all_requests - remove all requests from the endpoint's queue | |
2067 | * @hsotg: The device state. | |
2068 | * @ep: The endpoint the requests may be on. | |
2069 | * @result: The result code to use. | |
5b7d70c6 BD |
2070 | * |
2071 | * Go through the requests on the given endpoint and mark them | |
2072 | * completed with the given result code. | |
2073 | */ | |
941fcce4 | 2074 | static void kill_all_requests(struct dwc2_hsotg *hsotg, |
5b7d70c6 | 2075 | struct s3c_hsotg_ep *ep, |
6b448af4 | 2076 | int result) |
5b7d70c6 BD |
2077 | { |
2078 | struct s3c_hsotg_req *req, *treq; | |
b203d0a2 | 2079 | unsigned size; |
5b7d70c6 | 2080 | |
6b448af4 | 2081 | ep->req = NULL; |
5b7d70c6 | 2082 | |
6b448af4 | 2083 | list_for_each_entry_safe(req, treq, &ep->queue, queue) |
5b7d70c6 BD |
2084 | s3c_hsotg_complete_request(hsotg, ep, req, |
2085 | result); | |
6b448af4 | 2086 | |
b203d0a2 RB |
2087 | if (!hsotg->dedicated_fifos) |
2088 | return; | |
2089 | size = (readl(hsotg->regs + DTXFSTS(ep->index)) & 0xffff) * 4; | |
2090 | if (size < ep->fifo_size) | |
2091 | s3c_hsotg_txfifo_flush(hsotg, ep->fifo_index); | |
5b7d70c6 BD |
2092 | } |
2093 | ||
5b7d70c6 | 2094 | /** |
5e891342 | 2095 | * s3c_hsotg_disconnect - disconnect service |
5b7d70c6 BD |
2096 | * @hsotg: The device state. |
2097 | * | |
5e891342 LM |
2098 | * The device has been disconnected. Remove all current |
2099 | * transactions and signal the gadget driver that this | |
2100 | * has happened. | |
8b9bc460 | 2101 | */ |
4ace06e8 | 2102 | void s3c_hsotg_disconnect(struct dwc2_hsotg *hsotg) |
5b7d70c6 BD |
2103 | { |
2104 | unsigned ep; | |
2105 | ||
4ace06e8 MS |
2106 | if (!hsotg->connected) |
2107 | return; | |
2108 | ||
2109 | hsotg->connected = 0; | |
9e14d0a5 | 2110 | hsotg->test_mode = 0; |
c6f5c050 MYK |
2111 | |
2112 | for (ep = 0; ep < hsotg->num_of_eps; ep++) { | |
2113 | if (hsotg->eps_in[ep]) | |
2114 | kill_all_requests(hsotg, hsotg->eps_in[ep], | |
2115 | -ESHUTDOWN); | |
2116 | if (hsotg->eps_out[ep]) | |
2117 | kill_all_requests(hsotg, hsotg->eps_out[ep], | |
2118 | -ESHUTDOWN); | |
2119 | } | |
5b7d70c6 BD |
2120 | |
2121 | call_gadget(hsotg, disconnect); | |
2122 | } | |
4ace06e8 | 2123 | EXPORT_SYMBOL_GPL(s3c_hsotg_disconnect); |
5b7d70c6 BD |
2124 | |
2125 | /** | |
2126 | * s3c_hsotg_irq_fifoempty - TX FIFO empty interrupt handler | |
2127 | * @hsotg: The device state: | |
2128 | * @periodic: True if this is a periodic FIFO interrupt | |
2129 | */ | |
941fcce4 | 2130 | static void s3c_hsotg_irq_fifoempty(struct dwc2_hsotg *hsotg, bool periodic) |
5b7d70c6 BD |
2131 | { |
2132 | struct s3c_hsotg_ep *ep; | |
2133 | int epno, ret; | |
2134 | ||
2135 | /* look through for any more data to transmit */ | |
b3f489b2 | 2136 | for (epno = 0; epno < hsotg->num_of_eps; epno++) { |
c6f5c050 MYK |
2137 | ep = index_to_ep(hsotg, epno, 1); |
2138 | ||
2139 | if (!ep) | |
2140 | continue; | |
5b7d70c6 BD |
2141 | |
2142 | if (!ep->dir_in) | |
2143 | continue; | |
2144 | ||
2145 | if ((periodic && !ep->periodic) || | |
2146 | (!periodic && ep->periodic)) | |
2147 | continue; | |
2148 | ||
2149 | ret = s3c_hsotg_trytx(hsotg, ep); | |
2150 | if (ret < 0) | |
2151 | break; | |
2152 | } | |
2153 | } | |
2154 | ||
5b7d70c6 | 2155 | /* IRQ flags which will trigger a retry around the IRQ loop */ |
47a1685f DN |
2156 | #define IRQ_RETRY_MASK (GINTSTS_NPTXFEMP | \ |
2157 | GINTSTS_PTXFEMP | \ | |
2158 | GINTSTS_RXFLVL) | |
5b7d70c6 | 2159 | |
308d734e LM |
2160 | /** |
2161 | * s3c_hsotg_corereset - issue softreset to the core | |
2162 | * @hsotg: The device state | |
2163 | * | |
2164 | * Issue a soft reset to the core, and await the core finishing it. | |
8b9bc460 | 2165 | */ |
941fcce4 | 2166 | static int s3c_hsotg_corereset(struct dwc2_hsotg *hsotg) |
308d734e LM |
2167 | { |
2168 | int timeout; | |
2169 | u32 grstctl; | |
2170 | ||
2171 | dev_dbg(hsotg->dev, "resetting core\n"); | |
2172 | ||
2173 | /* issue soft reset */ | |
47a1685f | 2174 | writel(GRSTCTL_CSFTRST, hsotg->regs + GRSTCTL); |
308d734e | 2175 | |
2868fea2 | 2176 | timeout = 10000; |
308d734e | 2177 | do { |
94cb8fd6 | 2178 | grstctl = readl(hsotg->regs + GRSTCTL); |
47a1685f | 2179 | } while ((grstctl & GRSTCTL_CSFTRST) && timeout-- > 0); |
308d734e | 2180 | |
47a1685f | 2181 | if (grstctl & GRSTCTL_CSFTRST) { |
308d734e LM |
2182 | dev_err(hsotg->dev, "Failed to get CSftRst asserted\n"); |
2183 | return -EINVAL; | |
2184 | } | |
2185 | ||
2868fea2 | 2186 | timeout = 10000; |
308d734e LM |
2187 | |
2188 | while (1) { | |
94cb8fd6 | 2189 | u32 grstctl = readl(hsotg->regs + GRSTCTL); |
308d734e LM |
2190 | |
2191 | if (timeout-- < 0) { | |
2192 | dev_info(hsotg->dev, | |
2193 | "%s: reset failed, GRSTCTL=%08x\n", | |
2194 | __func__, grstctl); | |
2195 | return -ETIMEDOUT; | |
2196 | } | |
2197 | ||
47a1685f | 2198 | if (!(grstctl & GRSTCTL_AHBIDLE)) |
308d734e LM |
2199 | continue; |
2200 | ||
2201 | break; /* reset done */ | |
2202 | } | |
2203 | ||
2204 | dev_dbg(hsotg->dev, "reset successful\n"); | |
2205 | return 0; | |
2206 | } | |
2207 | ||
8b9bc460 LM |
2208 | /** |
2209 | * s3c_hsotg_core_init - issue softreset to the core | |
2210 | * @hsotg: The device state | |
2211 | * | |
2212 | * Issue a soft reset to the core, and await the core finishing it. | |
2213 | */ | |
510ffaa4 | 2214 | void s3c_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg) |
308d734e LM |
2215 | { |
2216 | s3c_hsotg_corereset(hsotg); | |
2217 | ||
2218 | /* | |
2219 | * we must now enable ep0 ready for host detection and then | |
2220 | * set configuration. | |
2221 | */ | |
2222 | ||
2223 | /* set the PLL on, remove the HNP/SRP and set the PHY */ | |
47a1685f | 2224 | writel(hsotg->phyif | GUSBCFG_TOUTCAL(7) | |
94cb8fd6 | 2225 | (0x5 << 10), hsotg->regs + GUSBCFG); |
308d734e LM |
2226 | |
2227 | s3c_hsotg_init_fifo(hsotg); | |
2228 | ||
47a1685f | 2229 | __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON); |
308d734e | 2230 | |
47a1685f | 2231 | writel(1 << 18 | DCFG_DEVSPD_HS, hsotg->regs + DCFG); |
308d734e LM |
2232 | |
2233 | /* Clear any pending OTG interrupts */ | |
94cb8fd6 | 2234 | writel(0xffffffff, hsotg->regs + GOTGINT); |
308d734e LM |
2235 | |
2236 | /* Clear any pending interrupts */ | |
94cb8fd6 | 2237 | writel(0xffffffff, hsotg->regs + GINTSTS); |
308d734e | 2238 | |
47a1685f DN |
2239 | writel(GINTSTS_ERLYSUSP | GINTSTS_SESSREQINT | |
2240 | GINTSTS_GOUTNAKEFF | GINTSTS_GINNAKEFF | | |
2241 | GINTSTS_CONIDSTSCHNG | GINTSTS_USBRST | | |
2242 | GINTSTS_ENUMDONE | GINTSTS_OTGINT | | |
2243 | GINTSTS_USBSUSP | GINTSTS_WKUPINT, | |
2244 | hsotg->regs + GINTMSK); | |
308d734e LM |
2245 | |
2246 | if (using_dma(hsotg)) | |
47a1685f | 2247 | writel(GAHBCFG_GLBL_INTR_EN | GAHBCFG_DMA_EN | |
5f05048e | 2248 | (GAHBCFG_HBSTLEN_INCR4 << GAHBCFG_HBSTLEN_SHIFT), |
94cb8fd6 | 2249 | hsotg->regs + GAHBCFG); |
308d734e | 2250 | else |
47a1685f DN |
2251 | writel(((hsotg->dedicated_fifos) ? (GAHBCFG_NP_TXF_EMP_LVL | |
2252 | GAHBCFG_P_TXF_EMP_LVL) : 0) | | |
2253 | GAHBCFG_GLBL_INTR_EN, | |
8acc8296 | 2254 | hsotg->regs + GAHBCFG); |
308d734e LM |
2255 | |
2256 | /* | |
8acc8296 RB |
2257 | * If INTknTXFEmpMsk is enabled, it's important to disable ep interrupts |
2258 | * when we have no data to transfer. Otherwise we get being flooded by | |
2259 | * interrupts. | |
308d734e LM |
2260 | */ |
2261 | ||
6ff2e832 MYK |
2262 | writel(((hsotg->dedicated_fifos && !using_dma(hsotg)) ? |
2263 | DIEPMSK_TXFIFOEMPTY | DIEPMSK_INTKNTXFEMPMSK : 0) | | |
47a1685f DN |
2264 | DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK | |
2265 | DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK | | |
2266 | DIEPMSK_INTKNEPMISMSK, | |
2267 | hsotg->regs + DIEPMSK); | |
308d734e LM |
2268 | |
2269 | /* | |
2270 | * don't need XferCompl, we get that from RXFIFO in slave mode. In | |
2271 | * DMA mode we may need this. | |
2272 | */ | |
47a1685f DN |
2273 | writel((using_dma(hsotg) ? (DIEPMSK_XFERCOMPLMSK | |
2274 | DIEPMSK_TIMEOUTMSK) : 0) | | |
2275 | DOEPMSK_EPDISBLDMSK | DOEPMSK_AHBERRMSK | | |
2276 | DOEPMSK_SETUPMSK, | |
2277 | hsotg->regs + DOEPMSK); | |
308d734e | 2278 | |
94cb8fd6 | 2279 | writel(0, hsotg->regs + DAINTMSK); |
308d734e LM |
2280 | |
2281 | dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n", | |
94cb8fd6 LM |
2282 | readl(hsotg->regs + DIEPCTL0), |
2283 | readl(hsotg->regs + DOEPCTL0)); | |
308d734e LM |
2284 | |
2285 | /* enable in and out endpoint interrupts */ | |
47a1685f | 2286 | s3c_hsotg_en_gsint(hsotg, GINTSTS_OEPINT | GINTSTS_IEPINT); |
308d734e LM |
2287 | |
2288 | /* | |
2289 | * Enable the RXFIFO when in slave mode, as this is how we collect | |
2290 | * the data. In DMA mode, we get events from the FIFO but also | |
2291 | * things we cannot process, so do not use it. | |
2292 | */ | |
2293 | if (!using_dma(hsotg)) | |
47a1685f | 2294 | s3c_hsotg_en_gsint(hsotg, GINTSTS_RXFLVL); |
308d734e LM |
2295 | |
2296 | /* Enable interrupts for EP0 in and out */ | |
2297 | s3c_hsotg_ctrl_epint(hsotg, 0, 0, 1); | |
2298 | s3c_hsotg_ctrl_epint(hsotg, 0, 1, 1); | |
2299 | ||
47a1685f | 2300 | __orr32(hsotg->regs + DCTL, DCTL_PWRONPRGDONE); |
308d734e | 2301 | udelay(10); /* see openiboot */ |
47a1685f | 2302 | __bic32(hsotg->regs + DCTL, DCTL_PWRONPRGDONE); |
308d734e | 2303 | |
94cb8fd6 | 2304 | dev_dbg(hsotg->dev, "DCTL=0x%08x\n", readl(hsotg->regs + DCTL)); |
308d734e LM |
2305 | |
2306 | /* | |
94cb8fd6 | 2307 | * DxEPCTL_USBActEp says RO in manual, but seems to be set by |
308d734e LM |
2308 | * writing to the EPCTL register.. |
2309 | */ | |
2310 | ||
2311 | /* set to read 1 8byte packet */ | |
47a1685f DN |
2312 | writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) | |
2313 | DXEPTSIZ_XFERSIZE(8), hsotg->regs + DOEPTSIZ0); | |
308d734e | 2314 | |
c6f5c050 | 2315 | writel(s3c_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) | |
47a1685f DN |
2316 | DXEPCTL_CNAK | DXEPCTL_EPENA | |
2317 | DXEPCTL_USBACTEP, | |
94cb8fd6 | 2318 | hsotg->regs + DOEPCTL0); |
308d734e LM |
2319 | |
2320 | /* enable, but don't activate EP0in */ | |
c6f5c050 | 2321 | writel(s3c_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) | |
47a1685f | 2322 | DXEPCTL_USBACTEP, hsotg->regs + DIEPCTL0); |
308d734e LM |
2323 | |
2324 | s3c_hsotg_enqueue_setup(hsotg); | |
2325 | ||
2326 | dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n", | |
94cb8fd6 LM |
2327 | readl(hsotg->regs + DIEPCTL0), |
2328 | readl(hsotg->regs + DOEPCTL0)); | |
308d734e LM |
2329 | |
2330 | /* clear global NAKs */ | |
ad38dc5d | 2331 | writel(DCTL_CGOUTNAK | DCTL_CGNPINNAK | DCTL_SFTDISCON, |
94cb8fd6 | 2332 | hsotg->regs + DCTL); |
308d734e LM |
2333 | |
2334 | /* must be at-least 3ms to allow bus to see disconnect */ | |
2335 | mdelay(3); | |
2336 | ||
ac3c81f3 | 2337 | hsotg->last_rst = jiffies; |
ad38dc5d MS |
2338 | } |
2339 | ||
941fcce4 | 2340 | static void s3c_hsotg_core_disconnect(struct dwc2_hsotg *hsotg) |
ad38dc5d MS |
2341 | { |
2342 | /* set the soft-disconnect bit */ | |
2343 | __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON); | |
2344 | } | |
ac3c81f3 | 2345 | |
510ffaa4 | 2346 | void s3c_hsotg_core_connect(struct dwc2_hsotg *hsotg) |
ad38dc5d | 2347 | { |
308d734e | 2348 | /* remove the soft-disconnect and let's go */ |
47a1685f | 2349 | __bic32(hsotg->regs + DCTL, DCTL_SFTDISCON); |
308d734e LM |
2350 | } |
2351 | ||
5b7d70c6 BD |
2352 | /** |
2353 | * s3c_hsotg_irq - handle device interrupt | |
2354 | * @irq: The IRQ number triggered | |
2355 | * @pw: The pw value when registered the handler. | |
2356 | */ | |
2357 | static irqreturn_t s3c_hsotg_irq(int irq, void *pw) | |
2358 | { | |
941fcce4 | 2359 | struct dwc2_hsotg *hsotg = pw; |
5b7d70c6 BD |
2360 | int retry_count = 8; |
2361 | u32 gintsts; | |
2362 | u32 gintmsk; | |
2363 | ||
5ad1d316 | 2364 | spin_lock(&hsotg->lock); |
5b7d70c6 | 2365 | irq_retry: |
94cb8fd6 LM |
2366 | gintsts = readl(hsotg->regs + GINTSTS); |
2367 | gintmsk = readl(hsotg->regs + GINTMSK); | |
5b7d70c6 BD |
2368 | |
2369 | dev_dbg(hsotg->dev, "%s: %08x %08x (%08x) retry %d\n", | |
2370 | __func__, gintsts, gintsts & gintmsk, gintmsk, retry_count); | |
2371 | ||
2372 | gintsts &= gintmsk; | |
2373 | ||
47a1685f DN |
2374 | if (gintsts & GINTSTS_ENUMDONE) { |
2375 | writel(GINTSTS_ENUMDONE, hsotg->regs + GINTSTS); | |
a3395f0d AT |
2376 | |
2377 | s3c_hsotg_irq_enumdone(hsotg); | |
5b7d70c6 BD |
2378 | } |
2379 | ||
47a1685f | 2380 | if (gintsts & (GINTSTS_OEPINT | GINTSTS_IEPINT)) { |
94cb8fd6 | 2381 | u32 daint = readl(hsotg->regs + DAINT); |
7e804650 RB |
2382 | u32 daintmsk = readl(hsotg->regs + DAINTMSK); |
2383 | u32 daint_out, daint_in; | |
5b7d70c6 BD |
2384 | int ep; |
2385 | ||
7e804650 | 2386 | daint &= daintmsk; |
47a1685f DN |
2387 | daint_out = daint >> DAINT_OUTEP_SHIFT; |
2388 | daint_in = daint & ~(daint_out << DAINT_OUTEP_SHIFT); | |
7e804650 | 2389 | |
5b7d70c6 BD |
2390 | dev_dbg(hsotg->dev, "%s: daint=%08x\n", __func__, daint); |
2391 | ||
cec87f1d MYK |
2392 | for (ep = 0; ep < hsotg->num_of_eps && daint_out; |
2393 | ep++, daint_out >>= 1) { | |
5b7d70c6 BD |
2394 | if (daint_out & 1) |
2395 | s3c_hsotg_epint(hsotg, ep, 0); | |
2396 | } | |
2397 | ||
cec87f1d MYK |
2398 | for (ep = 0; ep < hsotg->num_of_eps && daint_in; |
2399 | ep++, daint_in >>= 1) { | |
5b7d70c6 BD |
2400 | if (daint_in & 1) |
2401 | s3c_hsotg_epint(hsotg, ep, 1); | |
2402 | } | |
5b7d70c6 BD |
2403 | } |
2404 | ||
47a1685f | 2405 | if (gintsts & GINTSTS_USBRST) { |
12a1f4dc | 2406 | |
94cb8fd6 | 2407 | u32 usb_status = readl(hsotg->regs + GOTGCTL); |
12a1f4dc | 2408 | |
9599815d | 2409 | dev_dbg(hsotg->dev, "%s: USBRst\n", __func__); |
5b7d70c6 | 2410 | dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n", |
94cb8fd6 | 2411 | readl(hsotg->regs + GNPTXSTS)); |
5b7d70c6 | 2412 | |
47a1685f | 2413 | writel(GINTSTS_USBRST, hsotg->regs + GINTSTS); |
a3395f0d | 2414 | |
6d713c15 MYK |
2415 | /* Report disconnection if it is not already done. */ |
2416 | s3c_hsotg_disconnect(hsotg); | |
2417 | ||
94cb8fd6 | 2418 | if (usb_status & GOTGCTL_BSESVLD) { |
12a1f4dc LM |
2419 | if (time_after(jiffies, hsotg->last_rst + |
2420 | msecs_to_jiffies(200))) { | |
5b7d70c6 | 2421 | |
c6f5c050 | 2422 | kill_all_requests(hsotg, hsotg->eps_out[0], |
6b448af4 | 2423 | -ECONNRESET); |
5b7d70c6 | 2424 | |
ad38dc5d MS |
2425 | s3c_hsotg_core_init_disconnected(hsotg); |
2426 | s3c_hsotg_core_connect(hsotg); | |
12a1f4dc LM |
2427 | } |
2428 | } | |
5b7d70c6 BD |
2429 | } |
2430 | ||
2431 | /* check both FIFOs */ | |
2432 | ||
47a1685f | 2433 | if (gintsts & GINTSTS_NPTXFEMP) { |
5b7d70c6 BD |
2434 | dev_dbg(hsotg->dev, "NPTxFEmp\n"); |
2435 | ||
8b9bc460 LM |
2436 | /* |
2437 | * Disable the interrupt to stop it happening again | |
5b7d70c6 | 2438 | * unless one of these endpoint routines decides that |
8b9bc460 LM |
2439 | * it needs re-enabling |
2440 | */ | |
5b7d70c6 | 2441 | |
47a1685f | 2442 | s3c_hsotg_disable_gsint(hsotg, GINTSTS_NPTXFEMP); |
5b7d70c6 | 2443 | s3c_hsotg_irq_fifoempty(hsotg, false); |
5b7d70c6 BD |
2444 | } |
2445 | ||
47a1685f | 2446 | if (gintsts & GINTSTS_PTXFEMP) { |
5b7d70c6 BD |
2447 | dev_dbg(hsotg->dev, "PTxFEmp\n"); |
2448 | ||
94cb8fd6 | 2449 | /* See note in GINTSTS_NPTxFEmp */ |
5b7d70c6 | 2450 | |
47a1685f | 2451 | s3c_hsotg_disable_gsint(hsotg, GINTSTS_PTXFEMP); |
5b7d70c6 | 2452 | s3c_hsotg_irq_fifoempty(hsotg, true); |
5b7d70c6 BD |
2453 | } |
2454 | ||
47a1685f | 2455 | if (gintsts & GINTSTS_RXFLVL) { |
8b9bc460 LM |
2456 | /* |
2457 | * note, since GINTSTS_RxFLvl doubles as FIFO-not-empty, | |
5b7d70c6 | 2458 | * we need to retry s3c_hsotg_handle_rx if this is still |
8b9bc460 LM |
2459 | * set. |
2460 | */ | |
5b7d70c6 BD |
2461 | |
2462 | s3c_hsotg_handle_rx(hsotg); | |
5b7d70c6 BD |
2463 | } |
2464 | ||
47a1685f | 2465 | if (gintsts & GINTSTS_ERLYSUSP) { |
94cb8fd6 | 2466 | dev_dbg(hsotg->dev, "GINTSTS_ErlySusp\n"); |
47a1685f | 2467 | writel(GINTSTS_ERLYSUSP, hsotg->regs + GINTSTS); |
5b7d70c6 BD |
2468 | } |
2469 | ||
8b9bc460 LM |
2470 | /* |
2471 | * these next two seem to crop-up occasionally causing the core | |
5b7d70c6 | 2472 | * to shutdown the USB transfer, so try clearing them and logging |
8b9bc460 LM |
2473 | * the occurrence. |
2474 | */ | |
5b7d70c6 | 2475 | |
47a1685f | 2476 | if (gintsts & GINTSTS_GOUTNAKEFF) { |
5b7d70c6 BD |
2477 | dev_info(hsotg->dev, "GOUTNakEff triggered\n"); |
2478 | ||
47a1685f | 2479 | writel(DCTL_CGOUTNAK, hsotg->regs + DCTL); |
a3395f0d AT |
2480 | |
2481 | s3c_hsotg_dump(hsotg); | |
5b7d70c6 BD |
2482 | } |
2483 | ||
47a1685f | 2484 | if (gintsts & GINTSTS_GINNAKEFF) { |
5b7d70c6 BD |
2485 | dev_info(hsotg->dev, "GINNakEff triggered\n"); |
2486 | ||
47a1685f | 2487 | writel(DCTL_CGNPINNAK, hsotg->regs + DCTL); |
a3395f0d AT |
2488 | |
2489 | s3c_hsotg_dump(hsotg); | |
5b7d70c6 BD |
2490 | } |
2491 | ||
8b9bc460 LM |
2492 | /* |
2493 | * if we've had fifo events, we should try and go around the | |
2494 | * loop again to see if there's any point in returning yet. | |
2495 | */ | |
5b7d70c6 BD |
2496 | |
2497 | if (gintsts & IRQ_RETRY_MASK && --retry_count > 0) | |
2498 | goto irq_retry; | |
2499 | ||
5ad1d316 LM |
2500 | spin_unlock(&hsotg->lock); |
2501 | ||
5b7d70c6 BD |
2502 | return IRQ_HANDLED; |
2503 | } | |
2504 | ||
2505 | /** | |
2506 | * s3c_hsotg_ep_enable - enable the given endpoint | |
2507 | * @ep: The USB endpint to configure | |
2508 | * @desc: The USB endpoint descriptor to configure with. | |
2509 | * | |
2510 | * This is called from the USB gadget code's usb_ep_enable(). | |
8b9bc460 | 2511 | */ |
5b7d70c6 BD |
2512 | static int s3c_hsotg_ep_enable(struct usb_ep *ep, |
2513 | const struct usb_endpoint_descriptor *desc) | |
2514 | { | |
2515 | struct s3c_hsotg_ep *hs_ep = our_ep(ep); | |
941fcce4 | 2516 | struct dwc2_hsotg *hsotg = hs_ep->parent; |
5b7d70c6 | 2517 | unsigned long flags; |
ca4c55ad | 2518 | unsigned int index = hs_ep->index; |
5b7d70c6 BD |
2519 | u32 epctrl_reg; |
2520 | u32 epctrl; | |
2521 | u32 mps; | |
ca4c55ad MYK |
2522 | unsigned int dir_in; |
2523 | unsigned int i, val, size; | |
19c190f9 | 2524 | int ret = 0; |
5b7d70c6 BD |
2525 | |
2526 | dev_dbg(hsotg->dev, | |
2527 | "%s: ep %s: a 0x%02x, attr 0x%02x, mps 0x%04x, intr %d\n", | |
2528 | __func__, ep->name, desc->bEndpointAddress, desc->bmAttributes, | |
2529 | desc->wMaxPacketSize, desc->bInterval); | |
2530 | ||
2531 | /* not to be called for EP0 */ | |
2532 | WARN_ON(index == 0); | |
2533 | ||
2534 | dir_in = (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) ? 1 : 0; | |
2535 | if (dir_in != hs_ep->dir_in) { | |
2536 | dev_err(hsotg->dev, "%s: direction mismatch!\n", __func__); | |
2537 | return -EINVAL; | |
2538 | } | |
2539 | ||
29cc8897 | 2540 | mps = usb_endpoint_maxp(desc); |
5b7d70c6 BD |
2541 | |
2542 | /* note, we handle this here instead of s3c_hsotg_set_ep_maxpacket */ | |
2543 | ||
94cb8fd6 | 2544 | epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index); |
5b7d70c6 BD |
2545 | epctrl = readl(hsotg->regs + epctrl_reg); |
2546 | ||
2547 | dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x from 0x%08x\n", | |
2548 | __func__, epctrl, epctrl_reg); | |
2549 | ||
22258f49 | 2550 | spin_lock_irqsave(&hsotg->lock, flags); |
5b7d70c6 | 2551 | |
47a1685f DN |
2552 | epctrl &= ~(DXEPCTL_EPTYPE_MASK | DXEPCTL_MPS_MASK); |
2553 | epctrl |= DXEPCTL_MPS(mps); | |
5b7d70c6 | 2554 | |
8b9bc460 LM |
2555 | /* |
2556 | * mark the endpoint as active, otherwise the core may ignore | |
2557 | * transactions entirely for this endpoint | |
2558 | */ | |
47a1685f | 2559 | epctrl |= DXEPCTL_USBACTEP; |
5b7d70c6 | 2560 | |
8b9bc460 LM |
2561 | /* |
2562 | * set the NAK status on the endpoint, otherwise we might try and | |
5b7d70c6 BD |
2563 | * do something with data that we've yet got a request to process |
2564 | * since the RXFIFO will take data for an endpoint even if the | |
2565 | * size register hasn't been set. | |
2566 | */ | |
2567 | ||
47a1685f | 2568 | epctrl |= DXEPCTL_SNAK; |
5b7d70c6 BD |
2569 | |
2570 | /* update the endpoint state */ | |
c6f5c050 | 2571 | s3c_hsotg_set_ep_maxpacket(hsotg, hs_ep->index, mps, dir_in); |
5b7d70c6 BD |
2572 | |
2573 | /* default, set to non-periodic */ | |
1479e841 | 2574 | hs_ep->isochronous = 0; |
5b7d70c6 | 2575 | hs_ep->periodic = 0; |
a18ed7b0 | 2576 | hs_ep->halted = 0; |
1479e841 | 2577 | hs_ep->interval = desc->bInterval; |
5b7d70c6 | 2578 | |
4fca54aa RB |
2579 | if (hs_ep->interval > 1 && hs_ep->mc > 1) |
2580 | dev_err(hsotg->dev, "MC > 1 when interval is not 1\n"); | |
2581 | ||
5b7d70c6 BD |
2582 | switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) { |
2583 | case USB_ENDPOINT_XFER_ISOC: | |
47a1685f DN |
2584 | epctrl |= DXEPCTL_EPTYPE_ISO; |
2585 | epctrl |= DXEPCTL_SETEVENFR; | |
1479e841 RB |
2586 | hs_ep->isochronous = 1; |
2587 | if (dir_in) | |
2588 | hs_ep->periodic = 1; | |
2589 | break; | |
5b7d70c6 BD |
2590 | |
2591 | case USB_ENDPOINT_XFER_BULK: | |
47a1685f | 2592 | epctrl |= DXEPCTL_EPTYPE_BULK; |
5b7d70c6 BD |
2593 | break; |
2594 | ||
2595 | case USB_ENDPOINT_XFER_INT: | |
b203d0a2 | 2596 | if (dir_in) |
5b7d70c6 | 2597 | hs_ep->periodic = 1; |
5b7d70c6 | 2598 | |
47a1685f | 2599 | epctrl |= DXEPCTL_EPTYPE_INTERRUPT; |
5b7d70c6 BD |
2600 | break; |
2601 | ||
2602 | case USB_ENDPOINT_XFER_CONTROL: | |
47a1685f | 2603 | epctrl |= DXEPCTL_EPTYPE_CONTROL; |
5b7d70c6 BD |
2604 | break; |
2605 | } | |
2606 | ||
4556e12c MYK |
2607 | /* If fifo is already allocated for this ep */ |
2608 | if (hs_ep->fifo_index) { | |
2609 | size = hs_ep->ep.maxpacket * hs_ep->mc; | |
2610 | /* If bigger fifo is required deallocate current one */ | |
2611 | if (size > hs_ep->fifo_size) { | |
2612 | hsotg->fifo_map &= ~(1 << hs_ep->fifo_index); | |
2613 | hs_ep->fifo_index = 0; | |
2614 | hs_ep->fifo_size = 0; | |
2615 | } | |
2616 | } | |
2617 | ||
8b9bc460 LM |
2618 | /* |
2619 | * if the hardware has dedicated fifos, we must give each IN EP | |
10aebc77 BD |
2620 | * a unique tx-fifo even if it is non-periodic. |
2621 | */ | |
4556e12c | 2622 | if (dir_in && hsotg->dedicated_fifos && !hs_ep->fifo_index) { |
ca4c55ad MYK |
2623 | u32 fifo_index = 0; |
2624 | u32 fifo_size = UINT_MAX; | |
b203d0a2 | 2625 | size = hs_ep->ep.maxpacket*hs_ep->mc; |
5f2196bd | 2626 | for (i = 1; i < hsotg->num_of_eps; ++i) { |
b203d0a2 RB |
2627 | if (hsotg->fifo_map & (1<<i)) |
2628 | continue; | |
2629 | val = readl(hsotg->regs + DPTXFSIZN(i)); | |
2630 | val = (val >> FIFOSIZE_DEPTH_SHIFT)*4; | |
2631 | if (val < size) | |
2632 | continue; | |
ca4c55ad MYK |
2633 | /* Search for smallest acceptable fifo */ |
2634 | if (val < fifo_size) { | |
2635 | fifo_size = val; | |
2636 | fifo_index = i; | |
2637 | } | |
b203d0a2 | 2638 | } |
ca4c55ad | 2639 | if (!fifo_index) { |
5f2196bd MYK |
2640 | dev_err(hsotg->dev, |
2641 | "%s: No suitable fifo found\n", __func__); | |
b585a48b SM |
2642 | ret = -ENOMEM; |
2643 | goto error; | |
2644 | } | |
ca4c55ad MYK |
2645 | hsotg->fifo_map |= 1 << fifo_index; |
2646 | epctrl |= DXEPCTL_TXFNUM(fifo_index); | |
2647 | hs_ep->fifo_index = fifo_index; | |
2648 | hs_ep->fifo_size = fifo_size; | |
b203d0a2 | 2649 | } |
10aebc77 | 2650 | |
5b7d70c6 BD |
2651 | /* for non control endpoints, set PID to D0 */ |
2652 | if (index) | |
47a1685f | 2653 | epctrl |= DXEPCTL_SETD0PID; |
5b7d70c6 BD |
2654 | |
2655 | dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n", | |
2656 | __func__, epctrl); | |
2657 | ||
2658 | writel(epctrl, hsotg->regs + epctrl_reg); | |
2659 | dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x\n", | |
2660 | __func__, readl(hsotg->regs + epctrl_reg)); | |
2661 | ||
2662 | /* enable the endpoint interrupt */ | |
2663 | s3c_hsotg_ctrl_epint(hsotg, index, dir_in, 1); | |
2664 | ||
b585a48b | 2665 | error: |
22258f49 | 2666 | spin_unlock_irqrestore(&hsotg->lock, flags); |
19c190f9 | 2667 | return ret; |
5b7d70c6 BD |
2668 | } |
2669 | ||
8b9bc460 LM |
2670 | /** |
2671 | * s3c_hsotg_ep_disable - disable given endpoint | |
2672 | * @ep: The endpoint to disable. | |
2673 | */ | |
62f4f065 | 2674 | static int s3c_hsotg_ep_disable_force(struct usb_ep *ep, bool force) |
5b7d70c6 BD |
2675 | { |
2676 | struct s3c_hsotg_ep *hs_ep = our_ep(ep); | |
941fcce4 | 2677 | struct dwc2_hsotg *hsotg = hs_ep->parent; |
5b7d70c6 BD |
2678 | int dir_in = hs_ep->dir_in; |
2679 | int index = hs_ep->index; | |
2680 | unsigned long flags; | |
2681 | u32 epctrl_reg; | |
2682 | u32 ctrl; | |
2683 | ||
1e011293 | 2684 | dev_dbg(hsotg->dev, "%s(ep %p)\n", __func__, ep); |
5b7d70c6 | 2685 | |
c6f5c050 | 2686 | if (ep == &hsotg->eps_out[0]->ep) { |
5b7d70c6 BD |
2687 | dev_err(hsotg->dev, "%s: called for ep0\n", __func__); |
2688 | return -EINVAL; | |
2689 | } | |
2690 | ||
94cb8fd6 | 2691 | epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index); |
5b7d70c6 | 2692 | |
5ad1d316 | 2693 | spin_lock_irqsave(&hsotg->lock, flags); |
5b7d70c6 | 2694 | |
b203d0a2 RB |
2695 | hsotg->fifo_map &= ~(1<<hs_ep->fifo_index); |
2696 | hs_ep->fifo_index = 0; | |
2697 | hs_ep->fifo_size = 0; | |
5b7d70c6 BD |
2698 | |
2699 | ctrl = readl(hsotg->regs + epctrl_reg); | |
47a1685f DN |
2700 | ctrl &= ~DXEPCTL_EPENA; |
2701 | ctrl &= ~DXEPCTL_USBACTEP; | |
2702 | ctrl |= DXEPCTL_SNAK; | |
5b7d70c6 BD |
2703 | |
2704 | dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl); | |
2705 | writel(ctrl, hsotg->regs + epctrl_reg); | |
2706 | ||
2707 | /* disable endpoint interrupts */ | |
2708 | s3c_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 0); | |
2709 | ||
1141ea01 MYK |
2710 | /* terminate all requests with shutdown */ |
2711 | kill_all_requests(hsotg, hs_ep, -ESHUTDOWN); | |
2712 | ||
22258f49 | 2713 | spin_unlock_irqrestore(&hsotg->lock, flags); |
5b7d70c6 BD |
2714 | return 0; |
2715 | } | |
2716 | ||
62f4f065 RB |
2717 | static int s3c_hsotg_ep_disable(struct usb_ep *ep) |
2718 | { | |
2719 | return s3c_hsotg_ep_disable_force(ep, false); | |
2720 | } | |
5b7d70c6 BD |
2721 | /** |
2722 | * on_list - check request is on the given endpoint | |
2723 | * @ep: The endpoint to check. | |
2724 | * @test: The request to test if it is on the endpoint. | |
8b9bc460 | 2725 | */ |
5b7d70c6 BD |
2726 | static bool on_list(struct s3c_hsotg_ep *ep, struct s3c_hsotg_req *test) |
2727 | { | |
2728 | struct s3c_hsotg_req *req, *treq; | |
2729 | ||
2730 | list_for_each_entry_safe(req, treq, &ep->queue, queue) { | |
2731 | if (req == test) | |
2732 | return true; | |
2733 | } | |
2734 | ||
2735 | return false; | |
2736 | } | |
2737 | ||
8b9bc460 LM |
2738 | /** |
2739 | * s3c_hsotg_ep_dequeue - dequeue given endpoint | |
2740 | * @ep: The endpoint to dequeue. | |
2741 | * @req: The request to be removed from a queue. | |
2742 | */ | |
5b7d70c6 BD |
2743 | static int s3c_hsotg_ep_dequeue(struct usb_ep *ep, struct usb_request *req) |
2744 | { | |
2745 | struct s3c_hsotg_req *hs_req = our_req(req); | |
2746 | struct s3c_hsotg_ep *hs_ep = our_ep(ep); | |
941fcce4 | 2747 | struct dwc2_hsotg *hs = hs_ep->parent; |
5b7d70c6 BD |
2748 | unsigned long flags; |
2749 | ||
1e011293 | 2750 | dev_dbg(hs->dev, "ep_dequeue(%p,%p)\n", ep, req); |
5b7d70c6 | 2751 | |
22258f49 | 2752 | spin_lock_irqsave(&hs->lock, flags); |
5b7d70c6 BD |
2753 | |
2754 | if (!on_list(hs_ep, hs_req)) { | |
22258f49 | 2755 | spin_unlock_irqrestore(&hs->lock, flags); |
5b7d70c6 BD |
2756 | return -EINVAL; |
2757 | } | |
2758 | ||
2759 | s3c_hsotg_complete_request(hs, hs_ep, hs_req, -ECONNRESET); | |
22258f49 | 2760 | spin_unlock_irqrestore(&hs->lock, flags); |
5b7d70c6 BD |
2761 | |
2762 | return 0; | |
2763 | } | |
2764 | ||
8b9bc460 LM |
2765 | /** |
2766 | * s3c_hsotg_ep_sethalt - set halt on a given endpoint | |
2767 | * @ep: The endpoint to set halt. | |
2768 | * @value: Set or unset the halt. | |
2769 | */ | |
5b7d70c6 BD |
2770 | static int s3c_hsotg_ep_sethalt(struct usb_ep *ep, int value) |
2771 | { | |
2772 | struct s3c_hsotg_ep *hs_ep = our_ep(ep); | |
941fcce4 | 2773 | struct dwc2_hsotg *hs = hs_ep->parent; |
5b7d70c6 | 2774 | int index = hs_ep->index; |
5b7d70c6 BD |
2775 | u32 epreg; |
2776 | u32 epctl; | |
9c39ddc6 | 2777 | u32 xfertype; |
5b7d70c6 BD |
2778 | |
2779 | dev_info(hs->dev, "%s(ep %p %s, %d)\n", __func__, ep, ep->name, value); | |
2780 | ||
c9f721b2 RB |
2781 | if (index == 0) { |
2782 | if (value) | |
2783 | s3c_hsotg_stall_ep0(hs); | |
2784 | else | |
2785 | dev_warn(hs->dev, | |
2786 | "%s: can't clear halt on ep0\n", __func__); | |
2787 | return 0; | |
2788 | } | |
2789 | ||
c6f5c050 MYK |
2790 | if (hs_ep->dir_in) { |
2791 | epreg = DIEPCTL(index); | |
2792 | epctl = readl(hs->regs + epreg); | |
2793 | ||
2794 | if (value) { | |
2795 | epctl |= DXEPCTL_STALL + DXEPCTL_SNAK; | |
2796 | if (epctl & DXEPCTL_EPENA) | |
2797 | epctl |= DXEPCTL_EPDIS; | |
2798 | } else { | |
2799 | epctl &= ~DXEPCTL_STALL; | |
2800 | xfertype = epctl & DXEPCTL_EPTYPE_MASK; | |
2801 | if (xfertype == DXEPCTL_EPTYPE_BULK || | |
2802 | xfertype == DXEPCTL_EPTYPE_INTERRUPT) | |
2803 | epctl |= DXEPCTL_SETD0PID; | |
2804 | } | |
2805 | writel(epctl, hs->regs + epreg); | |
9c39ddc6 | 2806 | } else { |
5b7d70c6 | 2807 | |
c6f5c050 MYK |
2808 | epreg = DOEPCTL(index); |
2809 | epctl = readl(hs->regs + epreg); | |
5b7d70c6 | 2810 | |
c6f5c050 MYK |
2811 | if (value) |
2812 | epctl |= DXEPCTL_STALL; | |
2813 | else { | |
2814 | epctl &= ~DXEPCTL_STALL; | |
2815 | xfertype = epctl & DXEPCTL_EPTYPE_MASK; | |
2816 | if (xfertype == DXEPCTL_EPTYPE_BULK || | |
2817 | xfertype == DXEPCTL_EPTYPE_INTERRUPT) | |
2818 | epctl |= DXEPCTL_SETD0PID; | |
2819 | } | |
2820 | writel(epctl, hs->regs + epreg); | |
9c39ddc6 | 2821 | } |
5b7d70c6 | 2822 | |
a18ed7b0 RB |
2823 | hs_ep->halted = value; |
2824 | ||
5b7d70c6 BD |
2825 | return 0; |
2826 | } | |
2827 | ||
5ad1d316 LM |
2828 | /** |
2829 | * s3c_hsotg_ep_sethalt_lock - set halt on a given endpoint with lock held | |
2830 | * @ep: The endpoint to set halt. | |
2831 | * @value: Set or unset the halt. | |
2832 | */ | |
2833 | static int s3c_hsotg_ep_sethalt_lock(struct usb_ep *ep, int value) | |
2834 | { | |
2835 | struct s3c_hsotg_ep *hs_ep = our_ep(ep); | |
941fcce4 | 2836 | struct dwc2_hsotg *hs = hs_ep->parent; |
5ad1d316 LM |
2837 | unsigned long flags = 0; |
2838 | int ret = 0; | |
2839 | ||
2840 | spin_lock_irqsave(&hs->lock, flags); | |
2841 | ret = s3c_hsotg_ep_sethalt(ep, value); | |
2842 | spin_unlock_irqrestore(&hs->lock, flags); | |
2843 | ||
2844 | return ret; | |
2845 | } | |
2846 | ||
5b7d70c6 BD |
2847 | static struct usb_ep_ops s3c_hsotg_ep_ops = { |
2848 | .enable = s3c_hsotg_ep_enable, | |
2849 | .disable = s3c_hsotg_ep_disable, | |
2850 | .alloc_request = s3c_hsotg_ep_alloc_request, | |
2851 | .free_request = s3c_hsotg_ep_free_request, | |
5ad1d316 | 2852 | .queue = s3c_hsotg_ep_queue_lock, |
5b7d70c6 | 2853 | .dequeue = s3c_hsotg_ep_dequeue, |
5ad1d316 | 2854 | .set_halt = s3c_hsotg_ep_sethalt_lock, |
25985edc | 2855 | /* note, don't believe we have any call for the fifo routines */ |
5b7d70c6 BD |
2856 | }; |
2857 | ||
41188786 LM |
2858 | /** |
2859 | * s3c_hsotg_phy_enable - enable platform phy dev | |
8b9bc460 | 2860 | * @hsotg: The driver state |
41188786 LM |
2861 | * |
2862 | * A wrapper for platform code responsible for controlling | |
2863 | * low-level USB code | |
2864 | */ | |
941fcce4 | 2865 | static void s3c_hsotg_phy_enable(struct dwc2_hsotg *hsotg) |
41188786 LM |
2866 | { |
2867 | struct platform_device *pdev = to_platform_device(hsotg->dev); | |
2868 | ||
2869 | dev_dbg(hsotg->dev, "pdev 0x%p\n", pdev); | |
b2e587db | 2870 | |
ca2c5ba8 | 2871 | if (hsotg->uphy) |
74084844 | 2872 | usb_phy_init(hsotg->uphy); |
ca2c5ba8 | 2873 | else if (hsotg->plat && hsotg->plat->phy_init) |
41188786 | 2874 | hsotg->plat->phy_init(pdev, hsotg->plat->phy_type); |
ca2c5ba8 KD |
2875 | else { |
2876 | phy_init(hsotg->phy); | |
2877 | phy_power_on(hsotg->phy); | |
2878 | } | |
41188786 LM |
2879 | } |
2880 | ||
2881 | /** | |
2882 | * s3c_hsotg_phy_disable - disable platform phy dev | |
8b9bc460 | 2883 | * @hsotg: The driver state |
41188786 LM |
2884 | * |
2885 | * A wrapper for platform code responsible for controlling | |
2886 | * low-level USB code | |
2887 | */ | |
941fcce4 | 2888 | static void s3c_hsotg_phy_disable(struct dwc2_hsotg *hsotg) |
41188786 LM |
2889 | { |
2890 | struct platform_device *pdev = to_platform_device(hsotg->dev); | |
2891 | ||
ca2c5ba8 | 2892 | if (hsotg->uphy) |
74084844 | 2893 | usb_phy_shutdown(hsotg->uphy); |
ca2c5ba8 | 2894 | else if (hsotg->plat && hsotg->plat->phy_exit) |
41188786 | 2895 | hsotg->plat->phy_exit(pdev, hsotg->plat->phy_type); |
ca2c5ba8 KD |
2896 | else { |
2897 | phy_power_off(hsotg->phy); | |
2898 | phy_exit(hsotg->phy); | |
2899 | } | |
41188786 LM |
2900 | } |
2901 | ||
8b9bc460 LM |
2902 | /** |
2903 | * s3c_hsotg_init - initalize the usb core | |
2904 | * @hsotg: The driver state | |
2905 | */ | |
941fcce4 | 2906 | static void s3c_hsotg_init(struct dwc2_hsotg *hsotg) |
b3f489b2 LM |
2907 | { |
2908 | /* unmask subset of endpoint interrupts */ | |
2909 | ||
47a1685f DN |
2910 | writel(DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK | |
2911 | DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK, | |
2912 | hsotg->regs + DIEPMSK); | |
b3f489b2 | 2913 | |
47a1685f DN |
2914 | writel(DOEPMSK_SETUPMSK | DOEPMSK_AHBERRMSK | |
2915 | DOEPMSK_EPDISBLDMSK | DOEPMSK_XFERCOMPLMSK, | |
2916 | hsotg->regs + DOEPMSK); | |
b3f489b2 | 2917 | |
94cb8fd6 | 2918 | writel(0, hsotg->regs + DAINTMSK); |
b3f489b2 LM |
2919 | |
2920 | /* Be in disconnected state until gadget is registered */ | |
47a1685f | 2921 | __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON); |
b3f489b2 | 2922 | |
b3f489b2 LM |
2923 | /* setup fifos */ |
2924 | ||
2925 | dev_dbg(hsotg->dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n", | |
94cb8fd6 LM |
2926 | readl(hsotg->regs + GRXFSIZ), |
2927 | readl(hsotg->regs + GNPTXFSIZ)); | |
b3f489b2 LM |
2928 | |
2929 | s3c_hsotg_init_fifo(hsotg); | |
2930 | ||
2931 | /* set the PLL on, remove the HNP/SRP and set the PHY */ | |
47a1685f | 2932 | writel(GUSBCFG_PHYIF16 | GUSBCFG_TOUTCAL(7) | (0x5 << 10), |
94cb8fd6 | 2933 | hsotg->regs + GUSBCFG); |
b3f489b2 | 2934 | |
f5090044 GH |
2935 | if (using_dma(hsotg)) |
2936 | __orr32(hsotg->regs + GAHBCFG, GAHBCFG_DMA_EN); | |
b3f489b2 LM |
2937 | } |
2938 | ||
8b9bc460 LM |
2939 | /** |
2940 | * s3c_hsotg_udc_start - prepare the udc for work | |
2941 | * @gadget: The usb gadget state | |
2942 | * @driver: The usb gadget driver | |
2943 | * | |
2944 | * Perform initialization to prepare udc device and driver | |
2945 | * to work. | |
2946 | */ | |
f65f0f10 LM |
2947 | static int s3c_hsotg_udc_start(struct usb_gadget *gadget, |
2948 | struct usb_gadget_driver *driver) | |
5b7d70c6 | 2949 | { |
941fcce4 | 2950 | struct dwc2_hsotg *hsotg = to_hsotg(gadget); |
5b9451f8 | 2951 | unsigned long flags; |
5b7d70c6 BD |
2952 | int ret; |
2953 | ||
2954 | if (!hsotg) { | |
a023da33 | 2955 | pr_err("%s: called with no device\n", __func__); |
5b7d70c6 BD |
2956 | return -ENODEV; |
2957 | } | |
2958 | ||
2959 | if (!driver) { | |
2960 | dev_err(hsotg->dev, "%s: no driver\n", __func__); | |
2961 | return -EINVAL; | |
2962 | } | |
2963 | ||
7177aed4 | 2964 | if (driver->max_speed < USB_SPEED_FULL) |
5b7d70c6 | 2965 | dev_err(hsotg->dev, "%s: bad speed\n", __func__); |
5b7d70c6 | 2966 | |
f65f0f10 | 2967 | if (!driver->setup) { |
5b7d70c6 BD |
2968 | dev_err(hsotg->dev, "%s: missing entry points\n", __func__); |
2969 | return -EINVAL; | |
2970 | } | |
2971 | ||
7ad8096e | 2972 | mutex_lock(&hsotg->init_mutex); |
5b7d70c6 BD |
2973 | WARN_ON(hsotg->driver); |
2974 | ||
2975 | driver->driver.bus = NULL; | |
2976 | hsotg->driver = driver; | |
7d7b2292 | 2977 | hsotg->gadget.dev.of_node = hsotg->dev->of_node; |
5b7d70c6 BD |
2978 | hsotg->gadget.speed = USB_SPEED_UNKNOWN; |
2979 | ||
d00b4142 RB |
2980 | clk_enable(hsotg->clk); |
2981 | ||
f65f0f10 LM |
2982 | ret = regulator_bulk_enable(ARRAY_SIZE(hsotg->supplies), |
2983 | hsotg->supplies); | |
5b7d70c6 | 2984 | if (ret) { |
f65f0f10 | 2985 | dev_err(hsotg->dev, "failed to enable supplies: %d\n", ret); |
5b7d70c6 BD |
2986 | goto err; |
2987 | } | |
2988 | ||
c816c47f | 2989 | s3c_hsotg_phy_enable(hsotg); |
f6c01592 GH |
2990 | if (!IS_ERR_OR_NULL(hsotg->uphy)) |
2991 | otg_set_peripheral(hsotg->uphy->otg, &hsotg->gadget); | |
c816c47f | 2992 | |
5b9451f8 MS |
2993 | spin_lock_irqsave(&hsotg->lock, flags); |
2994 | s3c_hsotg_init(hsotg); | |
2995 | s3c_hsotg_core_init_disconnected(hsotg); | |
dc6e69e6 | 2996 | hsotg->enabled = 0; |
5b9451f8 MS |
2997 | spin_unlock_irqrestore(&hsotg->lock, flags); |
2998 | ||
5b7d70c6 | 2999 | dev_info(hsotg->dev, "bound driver %s\n", driver->driver.name); |
5b9451f8 | 3000 | |
7ad8096e MS |
3001 | mutex_unlock(&hsotg->init_mutex); |
3002 | ||
5b7d70c6 BD |
3003 | return 0; |
3004 | ||
3005 | err: | |
7ad8096e | 3006 | mutex_unlock(&hsotg->init_mutex); |
5b7d70c6 | 3007 | hsotg->driver = NULL; |
5b7d70c6 BD |
3008 | return ret; |
3009 | } | |
3010 | ||
8b9bc460 LM |
3011 | /** |
3012 | * s3c_hsotg_udc_stop - stop the udc | |
3013 | * @gadget: The usb gadget state | |
3014 | * @driver: The usb gadget driver | |
3015 | * | |
3016 | * Stop udc hw block and stay tunned for future transmissions | |
3017 | */ | |
22835b80 | 3018 | static int s3c_hsotg_udc_stop(struct usb_gadget *gadget) |
5b7d70c6 | 3019 | { |
941fcce4 | 3020 | struct dwc2_hsotg *hsotg = to_hsotg(gadget); |
2b19a52c | 3021 | unsigned long flags = 0; |
5b7d70c6 BD |
3022 | int ep; |
3023 | ||
3024 | if (!hsotg) | |
3025 | return -ENODEV; | |
3026 | ||
7ad8096e MS |
3027 | mutex_lock(&hsotg->init_mutex); |
3028 | ||
5b7d70c6 | 3029 | /* all endpoints should be shutdown */ |
c6f5c050 MYK |
3030 | for (ep = 1; ep < hsotg->num_of_eps; ep++) { |
3031 | if (hsotg->eps_in[ep]) | |
3032 | s3c_hsotg_ep_disable(&hsotg->eps_in[ep]->ep); | |
3033 | if (hsotg->eps_out[ep]) | |
3034 | s3c_hsotg_ep_disable(&hsotg->eps_out[ep]->ep); | |
3035 | } | |
5b7d70c6 | 3036 | |
2b19a52c LM |
3037 | spin_lock_irqsave(&hsotg->lock, flags); |
3038 | ||
32805c35 | 3039 | hsotg->driver = NULL; |
5b7d70c6 | 3040 | hsotg->gadget.speed = USB_SPEED_UNKNOWN; |
dc6e69e6 | 3041 | hsotg->enabled = 0; |
5b7d70c6 | 3042 | |
2b19a52c LM |
3043 | spin_unlock_irqrestore(&hsotg->lock, flags); |
3044 | ||
f6c01592 GH |
3045 | if (!IS_ERR_OR_NULL(hsotg->uphy)) |
3046 | otg_set_peripheral(hsotg->uphy->otg, NULL); | |
c816c47f MS |
3047 | s3c_hsotg_phy_disable(hsotg); |
3048 | ||
c8c10253 | 3049 | regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies), hsotg->supplies); |
5b7d70c6 | 3050 | |
d00b4142 RB |
3051 | clk_disable(hsotg->clk); |
3052 | ||
7ad8096e MS |
3053 | mutex_unlock(&hsotg->init_mutex); |
3054 | ||
5b7d70c6 BD |
3055 | return 0; |
3056 | } | |
5b7d70c6 | 3057 | |
8b9bc460 LM |
3058 | /** |
3059 | * s3c_hsotg_gadget_getframe - read the frame number | |
3060 | * @gadget: The usb gadget state | |
3061 | * | |
3062 | * Read the {micro} frame number | |
3063 | */ | |
5b7d70c6 BD |
3064 | static int s3c_hsotg_gadget_getframe(struct usb_gadget *gadget) |
3065 | { | |
3066 | return s3c_hsotg_read_frameno(to_hsotg(gadget)); | |
3067 | } | |
3068 | ||
a188b689 LM |
3069 | /** |
3070 | * s3c_hsotg_pullup - connect/disconnect the USB PHY | |
3071 | * @gadget: The usb gadget state | |
3072 | * @is_on: Current state of the USB PHY | |
3073 | * | |
3074 | * Connect/Disconnect the USB PHY pullup | |
3075 | */ | |
3076 | static int s3c_hsotg_pullup(struct usb_gadget *gadget, int is_on) | |
3077 | { | |
941fcce4 | 3078 | struct dwc2_hsotg *hsotg = to_hsotg(gadget); |
a188b689 LM |
3079 | unsigned long flags = 0; |
3080 | ||
d784f1e5 | 3081 | dev_dbg(hsotg->dev, "%s: is_on: %d\n", __func__, is_on); |
a188b689 | 3082 | |
7ad8096e | 3083 | mutex_lock(&hsotg->init_mutex); |
a188b689 LM |
3084 | spin_lock_irqsave(&hsotg->lock, flags); |
3085 | if (is_on) { | |
d00b4142 | 3086 | clk_enable(hsotg->clk); |
dc6e69e6 | 3087 | hsotg->enabled = 1; |
ad38dc5d | 3088 | s3c_hsotg_core_connect(hsotg); |
a188b689 | 3089 | } else { |
5b9451f8 | 3090 | s3c_hsotg_core_disconnect(hsotg); |
6d13673e | 3091 | s3c_hsotg_disconnect(hsotg); |
dc6e69e6 | 3092 | hsotg->enabled = 0; |
d00b4142 | 3093 | clk_disable(hsotg->clk); |
a188b689 LM |
3094 | } |
3095 | ||
3096 | hsotg->gadget.speed = USB_SPEED_UNKNOWN; | |
3097 | spin_unlock_irqrestore(&hsotg->lock, flags); | |
7ad8096e | 3098 | mutex_unlock(&hsotg->init_mutex); |
a188b689 LM |
3099 | |
3100 | return 0; | |
3101 | } | |
3102 | ||
83d98223 GH |
3103 | static int s3c_hsotg_vbus_session(struct usb_gadget *gadget, int is_active) |
3104 | { | |
3105 | struct dwc2_hsotg *hsotg = to_hsotg(gadget); | |
3106 | unsigned long flags; | |
3107 | ||
3108 | dev_dbg(hsotg->dev, "%s: is_active: %d\n", __func__, is_active); | |
3109 | spin_lock_irqsave(&hsotg->lock, flags); | |
3110 | ||
3111 | if (is_active) { | |
3112 | /* Kill any ep0 requests as controller will be reinitialized */ | |
3113 | kill_all_requests(hsotg, hsotg->eps_out[0], -ECONNRESET); | |
3114 | s3c_hsotg_core_init_disconnected(hsotg); | |
3115 | if (hsotg->enabled) | |
3116 | s3c_hsotg_core_connect(hsotg); | |
3117 | } else { | |
3118 | s3c_hsotg_core_disconnect(hsotg); | |
3119 | s3c_hsotg_disconnect(hsotg); | |
3120 | } | |
3121 | ||
3122 | spin_unlock_irqrestore(&hsotg->lock, flags); | |
3123 | return 0; | |
3124 | } | |
3125 | ||
596d696a GH |
3126 | /** |
3127 | * s3c_hsotg_vbus_draw - report bMaxPower field | |
3128 | * @gadget: The usb gadget state | |
3129 | * @mA: Amount of current | |
3130 | * | |
3131 | * Report how much power the device may consume to the phy. | |
3132 | */ | |
3133 | static int s3c_hsotg_vbus_draw(struct usb_gadget *gadget, unsigned mA) | |
3134 | { | |
3135 | struct dwc2_hsotg *hsotg = to_hsotg(gadget); | |
3136 | ||
3137 | if (IS_ERR_OR_NULL(hsotg->uphy)) | |
3138 | return -ENOTSUPP; | |
3139 | return usb_phy_set_power(hsotg->uphy, mA); | |
3140 | } | |
3141 | ||
eeef4587 | 3142 | static const struct usb_gadget_ops s3c_hsotg_gadget_ops = { |
5b7d70c6 | 3143 | .get_frame = s3c_hsotg_gadget_getframe, |
f65f0f10 LM |
3144 | .udc_start = s3c_hsotg_udc_start, |
3145 | .udc_stop = s3c_hsotg_udc_stop, | |
a188b689 | 3146 | .pullup = s3c_hsotg_pullup, |
83d98223 | 3147 | .vbus_session = s3c_hsotg_vbus_session, |
596d696a | 3148 | .vbus_draw = s3c_hsotg_vbus_draw, |
5b7d70c6 BD |
3149 | }; |
3150 | ||
3151 | /** | |
3152 | * s3c_hsotg_initep - initialise a single endpoint | |
3153 | * @hsotg: The device state. | |
3154 | * @hs_ep: The endpoint to be initialised. | |
3155 | * @epnum: The endpoint number | |
3156 | * | |
3157 | * Initialise the given endpoint (as part of the probe and device state | |
3158 | * creation) to give to the gadget driver. Setup the endpoint name, any | |
3159 | * direction information and other state that may be required. | |
3160 | */ | |
941fcce4 | 3161 | static void s3c_hsotg_initep(struct dwc2_hsotg *hsotg, |
5b7d70c6 | 3162 | struct s3c_hsotg_ep *hs_ep, |
c6f5c050 MYK |
3163 | int epnum, |
3164 | bool dir_in) | |
5b7d70c6 | 3165 | { |
5b7d70c6 BD |
3166 | char *dir; |
3167 | ||
3168 | if (epnum == 0) | |
3169 | dir = ""; | |
c6f5c050 | 3170 | else if (dir_in) |
5b7d70c6 | 3171 | dir = "in"; |
c6f5c050 MYK |
3172 | else |
3173 | dir = "out"; | |
5b7d70c6 | 3174 | |
c6f5c050 | 3175 | hs_ep->dir_in = dir_in; |
5b7d70c6 BD |
3176 | hs_ep->index = epnum; |
3177 | ||
3178 | snprintf(hs_ep->name, sizeof(hs_ep->name), "ep%d%s", epnum, dir); | |
3179 | ||
3180 | INIT_LIST_HEAD(&hs_ep->queue); | |
3181 | INIT_LIST_HEAD(&hs_ep->ep.ep_list); | |
3182 | ||
5b7d70c6 BD |
3183 | /* add to the list of endpoints known by the gadget driver */ |
3184 | if (epnum) | |
3185 | list_add_tail(&hs_ep->ep.ep_list, &hsotg->gadget.ep_list); | |
3186 | ||
3187 | hs_ep->parent = hsotg; | |
3188 | hs_ep->ep.name = hs_ep->name; | |
e117e742 | 3189 | usb_ep_set_maxpacket_limit(&hs_ep->ep, epnum ? 1024 : EP0_MPS_LIMIT); |
5b7d70c6 BD |
3190 | hs_ep->ep.ops = &s3c_hsotg_ep_ops; |
3191 | ||
8b9bc460 LM |
3192 | /* |
3193 | * if we're using dma, we need to set the next-endpoint pointer | |
5b7d70c6 BD |
3194 | * to be something valid. |
3195 | */ | |
3196 | ||
3197 | if (using_dma(hsotg)) { | |
47a1685f | 3198 | u32 next = DXEPCTL_NEXTEP((epnum + 1) % 15); |
c6f5c050 MYK |
3199 | if (dir_in) |
3200 | writel(next, hsotg->regs + DIEPCTL(epnum)); | |
3201 | else | |
3202 | writel(next, hsotg->regs + DOEPCTL(epnum)); | |
5b7d70c6 BD |
3203 | } |
3204 | } | |
3205 | ||
b3f489b2 LM |
3206 | /** |
3207 | * s3c_hsotg_hw_cfg - read HW configuration registers | |
3208 | * @param: The device state | |
3209 | * | |
3210 | * Read the USB core HW configuration registers | |
3211 | */ | |
c6f5c050 | 3212 | static int s3c_hsotg_hw_cfg(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 3213 | { |
c6f5c050 MYK |
3214 | u32 cfg; |
3215 | u32 ep_type; | |
3216 | u32 i; | |
3217 | ||
b3f489b2 | 3218 | /* check hardware configuration */ |
5b7d70c6 | 3219 | |
c6f5c050 MYK |
3220 | cfg = readl(hsotg->regs + GHWCFG2); |
3221 | hsotg->num_of_eps = (cfg >> 10) & 0xF; | |
3222 | /* Add ep0 */ | |
3223 | hsotg->num_of_eps++; | |
10aebc77 | 3224 | |
c6f5c050 MYK |
3225 | hsotg->eps_in[0] = devm_kzalloc(hsotg->dev, sizeof(struct s3c_hsotg_ep), |
3226 | GFP_KERNEL); | |
3227 | if (!hsotg->eps_in[0]) | |
3228 | return -ENOMEM; | |
3229 | /* Same s3c_hsotg_ep is used in both directions for ep0 */ | |
3230 | hsotg->eps_out[0] = hsotg->eps_in[0]; | |
3231 | ||
3232 | cfg = readl(hsotg->regs + GHWCFG1); | |
3233 | for (i = 1; i < hsotg->num_of_eps; i++, cfg >>= 2) { | |
3234 | ep_type = cfg & 3; | |
3235 | /* Direction in or both */ | |
3236 | if (!(ep_type & 2)) { | |
3237 | hsotg->eps_in[i] = devm_kzalloc(hsotg->dev, | |
3238 | sizeof(struct s3c_hsotg_ep), GFP_KERNEL); | |
3239 | if (!hsotg->eps_in[i]) | |
3240 | return -ENOMEM; | |
3241 | } | |
3242 | /* Direction out or both */ | |
3243 | if (!(ep_type & 1)) { | |
3244 | hsotg->eps_out[i] = devm_kzalloc(hsotg->dev, | |
3245 | sizeof(struct s3c_hsotg_ep), GFP_KERNEL); | |
3246 | if (!hsotg->eps_out[i]) | |
3247 | return -ENOMEM; | |
3248 | } | |
3249 | } | |
3250 | ||
3251 | cfg = readl(hsotg->regs + GHWCFG3); | |
3252 | hsotg->fifo_mem = (cfg >> 16); | |
10aebc77 | 3253 | |
c6f5c050 MYK |
3254 | cfg = readl(hsotg->regs + GHWCFG4); |
3255 | hsotg->dedicated_fifos = (cfg >> 25) & 1; | |
10aebc77 | 3256 | |
cff9eb75 MS |
3257 | dev_info(hsotg->dev, "EPs: %d, %s fifos, %d entries in SPRAM\n", |
3258 | hsotg->num_of_eps, | |
3259 | hsotg->dedicated_fifos ? "dedicated" : "shared", | |
3260 | hsotg->fifo_mem); | |
c6f5c050 | 3261 | return 0; |
5b7d70c6 BD |
3262 | } |
3263 | ||
8b9bc460 LM |
3264 | /** |
3265 | * s3c_hsotg_dump - dump state of the udc | |
3266 | * @param: The device state | |
3267 | */ | |
941fcce4 | 3268 | static void s3c_hsotg_dump(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 3269 | { |
83a01804 | 3270 | #ifdef DEBUG |
5b7d70c6 BD |
3271 | struct device *dev = hsotg->dev; |
3272 | void __iomem *regs = hsotg->regs; | |
3273 | u32 val; | |
3274 | int idx; | |
3275 | ||
3276 | dev_info(dev, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n", | |
94cb8fd6 LM |
3277 | readl(regs + DCFG), readl(regs + DCTL), |
3278 | readl(regs + DIEPMSK)); | |
5b7d70c6 BD |
3279 | |
3280 | dev_info(dev, "GAHBCFG=0x%08x, 0x44=0x%08x\n", | |
94cb8fd6 | 3281 | readl(regs + GAHBCFG), readl(regs + 0x44)); |
5b7d70c6 BD |
3282 | |
3283 | dev_info(dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n", | |
94cb8fd6 | 3284 | readl(regs + GRXFSIZ), readl(regs + GNPTXFSIZ)); |
5b7d70c6 BD |
3285 | |
3286 | /* show periodic fifo settings */ | |
3287 | ||
364f8e93 | 3288 | for (idx = 1; idx < hsotg->num_of_eps; idx++) { |
47a1685f | 3289 | val = readl(regs + DPTXFSIZN(idx)); |
5b7d70c6 | 3290 | dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx, |
47a1685f DN |
3291 | val >> FIFOSIZE_DEPTH_SHIFT, |
3292 | val & FIFOSIZE_STARTADDR_MASK); | |
5b7d70c6 BD |
3293 | } |
3294 | ||
364f8e93 | 3295 | for (idx = 0; idx < hsotg->num_of_eps; idx++) { |
5b7d70c6 BD |
3296 | dev_info(dev, |
3297 | "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx, | |
94cb8fd6 LM |
3298 | readl(regs + DIEPCTL(idx)), |
3299 | readl(regs + DIEPTSIZ(idx)), | |
3300 | readl(regs + DIEPDMA(idx))); | |
5b7d70c6 | 3301 | |
94cb8fd6 | 3302 | val = readl(regs + DOEPCTL(idx)); |
5b7d70c6 BD |
3303 | dev_info(dev, |
3304 | "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", | |
94cb8fd6 LM |
3305 | idx, readl(regs + DOEPCTL(idx)), |
3306 | readl(regs + DOEPTSIZ(idx)), | |
3307 | readl(regs + DOEPDMA(idx))); | |
5b7d70c6 BD |
3308 | |
3309 | } | |
3310 | ||
3311 | dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n", | |
94cb8fd6 | 3312 | readl(regs + DVBUSDIS), readl(regs + DVBUSPULSE)); |
83a01804 | 3313 | #endif |
5b7d70c6 BD |
3314 | } |
3315 | ||
9e14d0a5 GH |
3316 | /** |
3317 | * testmode_write - debugfs: change usb test mode | |
3318 | * @seq: The seq file to write to. | |
3319 | * @v: Unused parameter. | |
3320 | * | |
3321 | * This debugfs entry modify the current usb test mode. | |
3322 | */ | |
3323 | static ssize_t testmode_write(struct file *file, const char __user *ubuf, size_t | |
3324 | count, loff_t *ppos) | |
3325 | { | |
3326 | struct seq_file *s = file->private_data; | |
3327 | struct dwc2_hsotg *hsotg = s->private; | |
3328 | unsigned long flags; | |
3329 | u32 testmode = 0; | |
3330 | char buf[32]; | |
3331 | ||
3332 | if (copy_from_user(&buf, ubuf, min_t(size_t, sizeof(buf) - 1, count))) | |
3333 | return -EFAULT; | |
3334 | ||
3335 | if (!strncmp(buf, "test_j", 6)) | |
3336 | testmode = TEST_J; | |
3337 | else if (!strncmp(buf, "test_k", 6)) | |
3338 | testmode = TEST_K; | |
3339 | else if (!strncmp(buf, "test_se0_nak", 12)) | |
3340 | testmode = TEST_SE0_NAK; | |
3341 | else if (!strncmp(buf, "test_packet", 11)) | |
3342 | testmode = TEST_PACKET; | |
3343 | else if (!strncmp(buf, "test_force_enable", 17)) | |
3344 | testmode = TEST_FORCE_EN; | |
3345 | else | |
3346 | testmode = 0; | |
3347 | ||
3348 | spin_lock_irqsave(&hsotg->lock, flags); | |
3349 | s3c_hsotg_set_test_mode(hsotg, testmode); | |
3350 | spin_unlock_irqrestore(&hsotg->lock, flags); | |
3351 | return count; | |
3352 | } | |
3353 | ||
3354 | /** | |
3355 | * testmode_show - debugfs: show usb test mode state | |
3356 | * @seq: The seq file to write to. | |
3357 | * @v: Unused parameter. | |
3358 | * | |
3359 | * This debugfs entry shows which usb test mode is currently enabled. | |
3360 | */ | |
3361 | static int testmode_show(struct seq_file *s, void *unused) | |
3362 | { | |
3363 | struct dwc2_hsotg *hsotg = s->private; | |
3364 | unsigned long flags; | |
3365 | int dctl; | |
3366 | ||
3367 | spin_lock_irqsave(&hsotg->lock, flags); | |
3368 | dctl = readl(hsotg->regs + DCTL); | |
3369 | dctl &= DCTL_TSTCTL_MASK; | |
3370 | dctl >>= DCTL_TSTCTL_SHIFT; | |
3371 | spin_unlock_irqrestore(&hsotg->lock, flags); | |
3372 | ||
3373 | switch (dctl) { | |
3374 | case 0: | |
3375 | seq_puts(s, "no test\n"); | |
3376 | break; | |
3377 | case TEST_J: | |
3378 | seq_puts(s, "test_j\n"); | |
3379 | break; | |
3380 | case TEST_K: | |
3381 | seq_puts(s, "test_k\n"); | |
3382 | break; | |
3383 | case TEST_SE0_NAK: | |
3384 | seq_puts(s, "test_se0_nak\n"); | |
3385 | break; | |
3386 | case TEST_PACKET: | |
3387 | seq_puts(s, "test_packet\n"); | |
3388 | break; | |
3389 | case TEST_FORCE_EN: | |
3390 | seq_puts(s, "test_force_enable\n"); | |
3391 | break; | |
3392 | default: | |
3393 | seq_printf(s, "UNKNOWN %d\n", dctl); | |
3394 | } | |
3395 | ||
3396 | return 0; | |
3397 | } | |
3398 | ||
3399 | static int testmode_open(struct inode *inode, struct file *file) | |
3400 | { | |
3401 | return single_open(file, testmode_show, inode->i_private); | |
3402 | } | |
3403 | ||
3404 | static const struct file_operations testmode_fops = { | |
3405 | .owner = THIS_MODULE, | |
3406 | .open = testmode_open, | |
3407 | .write = testmode_write, | |
3408 | .read = seq_read, | |
3409 | .llseek = seq_lseek, | |
3410 | .release = single_release, | |
3411 | }; | |
3412 | ||
5b7d70c6 BD |
3413 | /** |
3414 | * state_show - debugfs: show overall driver and device state. | |
3415 | * @seq: The seq file to write to. | |
3416 | * @v: Unused parameter. | |
3417 | * | |
3418 | * This debugfs entry shows the overall state of the hardware and | |
3419 | * some general information about each of the endpoints available | |
3420 | * to the system. | |
3421 | */ | |
3422 | static int state_show(struct seq_file *seq, void *v) | |
3423 | { | |
941fcce4 | 3424 | struct dwc2_hsotg *hsotg = seq->private; |
5b7d70c6 BD |
3425 | void __iomem *regs = hsotg->regs; |
3426 | int idx; | |
3427 | ||
3428 | seq_printf(seq, "DCFG=0x%08x, DCTL=0x%08x, DSTS=0x%08x\n", | |
94cb8fd6 LM |
3429 | readl(regs + DCFG), |
3430 | readl(regs + DCTL), | |
3431 | readl(regs + DSTS)); | |
5b7d70c6 BD |
3432 | |
3433 | seq_printf(seq, "DIEPMSK=0x%08x, DOEPMASK=0x%08x\n", | |
94cb8fd6 | 3434 | readl(regs + DIEPMSK), readl(regs + DOEPMSK)); |
5b7d70c6 BD |
3435 | |
3436 | seq_printf(seq, "GINTMSK=0x%08x, GINTSTS=0x%08x\n", | |
94cb8fd6 LM |
3437 | readl(regs + GINTMSK), |
3438 | readl(regs + GINTSTS)); | |
5b7d70c6 BD |
3439 | |
3440 | seq_printf(seq, "DAINTMSK=0x%08x, DAINT=0x%08x\n", | |
94cb8fd6 LM |
3441 | readl(regs + DAINTMSK), |
3442 | readl(regs + DAINT)); | |
5b7d70c6 BD |
3443 | |
3444 | seq_printf(seq, "GNPTXSTS=0x%08x, GRXSTSR=%08x\n", | |
94cb8fd6 LM |
3445 | readl(regs + GNPTXSTS), |
3446 | readl(regs + GRXSTSR)); | |
5b7d70c6 | 3447 | |
a023da33 | 3448 | seq_puts(seq, "\nEndpoint status:\n"); |
5b7d70c6 | 3449 | |
364f8e93 | 3450 | for (idx = 0; idx < hsotg->num_of_eps; idx++) { |
5b7d70c6 BD |
3451 | u32 in, out; |
3452 | ||
94cb8fd6 LM |
3453 | in = readl(regs + DIEPCTL(idx)); |
3454 | out = readl(regs + DOEPCTL(idx)); | |
5b7d70c6 BD |
3455 | |
3456 | seq_printf(seq, "ep%d: DIEPCTL=0x%08x, DOEPCTL=0x%08x", | |
3457 | idx, in, out); | |
3458 | ||
94cb8fd6 LM |
3459 | in = readl(regs + DIEPTSIZ(idx)); |
3460 | out = readl(regs + DOEPTSIZ(idx)); | |
5b7d70c6 BD |
3461 | |
3462 | seq_printf(seq, ", DIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x", | |
3463 | in, out); | |
3464 | ||
a023da33 | 3465 | seq_puts(seq, "\n"); |
5b7d70c6 BD |
3466 | } |
3467 | ||
3468 | return 0; | |
3469 | } | |
3470 | ||
3471 | static int state_open(struct inode *inode, struct file *file) | |
3472 | { | |
3473 | return single_open(file, state_show, inode->i_private); | |
3474 | } | |
3475 | ||
3476 | static const struct file_operations state_fops = { | |
3477 | .owner = THIS_MODULE, | |
3478 | .open = state_open, | |
3479 | .read = seq_read, | |
3480 | .llseek = seq_lseek, | |
3481 | .release = single_release, | |
3482 | }; | |
3483 | ||
3484 | /** | |
3485 | * fifo_show - debugfs: show the fifo information | |
3486 | * @seq: The seq_file to write data to. | |
3487 | * @v: Unused parameter. | |
3488 | * | |
3489 | * Show the FIFO information for the overall fifo and all the | |
3490 | * periodic transmission FIFOs. | |
8b9bc460 | 3491 | */ |
5b7d70c6 BD |
3492 | static int fifo_show(struct seq_file *seq, void *v) |
3493 | { | |
941fcce4 | 3494 | struct dwc2_hsotg *hsotg = seq->private; |
5b7d70c6 BD |
3495 | void __iomem *regs = hsotg->regs; |
3496 | u32 val; | |
3497 | int idx; | |
3498 | ||
a023da33 | 3499 | seq_puts(seq, "Non-periodic FIFOs:\n"); |
94cb8fd6 | 3500 | seq_printf(seq, "RXFIFO: Size %d\n", readl(regs + GRXFSIZ)); |
5b7d70c6 | 3501 | |
94cb8fd6 | 3502 | val = readl(regs + GNPTXFSIZ); |
5b7d70c6 | 3503 | seq_printf(seq, "NPTXFIFO: Size %d, Start 0x%08x\n", |
47a1685f DN |
3504 | val >> FIFOSIZE_DEPTH_SHIFT, |
3505 | val & FIFOSIZE_DEPTH_MASK); | |
5b7d70c6 | 3506 | |
a023da33 | 3507 | seq_puts(seq, "\nPeriodic TXFIFOs:\n"); |
5b7d70c6 | 3508 | |
364f8e93 | 3509 | for (idx = 1; idx < hsotg->num_of_eps; idx++) { |
47a1685f | 3510 | val = readl(regs + DPTXFSIZN(idx)); |
5b7d70c6 BD |
3511 | |
3512 | seq_printf(seq, "\tDPTXFIFO%2d: Size %d, Start 0x%08x\n", idx, | |
47a1685f DN |
3513 | val >> FIFOSIZE_DEPTH_SHIFT, |
3514 | val & FIFOSIZE_STARTADDR_MASK); | |
5b7d70c6 BD |
3515 | } |
3516 | ||
3517 | return 0; | |
3518 | } | |
3519 | ||
3520 | static int fifo_open(struct inode *inode, struct file *file) | |
3521 | { | |
3522 | return single_open(file, fifo_show, inode->i_private); | |
3523 | } | |
3524 | ||
3525 | static const struct file_operations fifo_fops = { | |
3526 | .owner = THIS_MODULE, | |
3527 | .open = fifo_open, | |
3528 | .read = seq_read, | |
3529 | .llseek = seq_lseek, | |
3530 | .release = single_release, | |
3531 | }; | |
3532 | ||
3533 | ||
3534 | static const char *decode_direction(int is_in) | |
3535 | { | |
3536 | return is_in ? "in" : "out"; | |
3537 | } | |
3538 | ||
3539 | /** | |
3540 | * ep_show - debugfs: show the state of an endpoint. | |
3541 | * @seq: The seq_file to write data to. | |
3542 | * @v: Unused parameter. | |
3543 | * | |
3544 | * This debugfs entry shows the state of the given endpoint (one is | |
3545 | * registered for each available). | |
8b9bc460 | 3546 | */ |
5b7d70c6 BD |
3547 | static int ep_show(struct seq_file *seq, void *v) |
3548 | { | |
3549 | struct s3c_hsotg_ep *ep = seq->private; | |
941fcce4 | 3550 | struct dwc2_hsotg *hsotg = ep->parent; |
5b7d70c6 BD |
3551 | struct s3c_hsotg_req *req; |
3552 | void __iomem *regs = hsotg->regs; | |
3553 | int index = ep->index; | |
3554 | int show_limit = 15; | |
3555 | unsigned long flags; | |
3556 | ||
3557 | seq_printf(seq, "Endpoint index %d, named %s, dir %s:\n", | |
3558 | ep->index, ep->ep.name, decode_direction(ep->dir_in)); | |
3559 | ||
3560 | /* first show the register state */ | |
3561 | ||
3562 | seq_printf(seq, "\tDIEPCTL=0x%08x, DOEPCTL=0x%08x\n", | |
94cb8fd6 LM |
3563 | readl(regs + DIEPCTL(index)), |
3564 | readl(regs + DOEPCTL(index))); | |
5b7d70c6 BD |
3565 | |
3566 | seq_printf(seq, "\tDIEPDMA=0x%08x, DOEPDMA=0x%08x\n", | |
94cb8fd6 LM |
3567 | readl(regs + DIEPDMA(index)), |
3568 | readl(regs + DOEPDMA(index))); | |
5b7d70c6 BD |
3569 | |
3570 | seq_printf(seq, "\tDIEPINT=0x%08x, DOEPINT=0x%08x\n", | |
94cb8fd6 LM |
3571 | readl(regs + DIEPINT(index)), |
3572 | readl(regs + DOEPINT(index))); | |
5b7d70c6 BD |
3573 | |
3574 | seq_printf(seq, "\tDIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x\n", | |
94cb8fd6 LM |
3575 | readl(regs + DIEPTSIZ(index)), |
3576 | readl(regs + DOEPTSIZ(index))); | |
5b7d70c6 | 3577 | |
a023da33 | 3578 | seq_puts(seq, "\n"); |
5b7d70c6 BD |
3579 | seq_printf(seq, "mps %d\n", ep->ep.maxpacket); |
3580 | seq_printf(seq, "total_data=%ld\n", ep->total_data); | |
3581 | ||
3582 | seq_printf(seq, "request list (%p,%p):\n", | |
3583 | ep->queue.next, ep->queue.prev); | |
3584 | ||
22258f49 | 3585 | spin_lock_irqsave(&hsotg->lock, flags); |
5b7d70c6 BD |
3586 | |
3587 | list_for_each_entry(req, &ep->queue, queue) { | |
3588 | if (--show_limit < 0) { | |
a023da33 | 3589 | seq_puts(seq, "not showing more requests...\n"); |
5b7d70c6 BD |
3590 | break; |
3591 | } | |
3592 | ||
3593 | seq_printf(seq, "%c req %p: %d bytes @%p, ", | |
3594 | req == ep->req ? '*' : ' ', | |
3595 | req, req->req.length, req->req.buf); | |
3596 | seq_printf(seq, "%d done, res %d\n", | |
3597 | req->req.actual, req->req.status); | |
3598 | } | |
3599 | ||
22258f49 | 3600 | spin_unlock_irqrestore(&hsotg->lock, flags); |
5b7d70c6 BD |
3601 | |
3602 | return 0; | |
3603 | } | |
3604 | ||
3605 | static int ep_open(struct inode *inode, struct file *file) | |
3606 | { | |
3607 | return single_open(file, ep_show, inode->i_private); | |
3608 | } | |
3609 | ||
3610 | static const struct file_operations ep_fops = { | |
3611 | .owner = THIS_MODULE, | |
3612 | .open = ep_open, | |
3613 | .read = seq_read, | |
3614 | .llseek = seq_lseek, | |
3615 | .release = single_release, | |
3616 | }; | |
3617 | ||
3618 | /** | |
3619 | * s3c_hsotg_create_debug - create debugfs directory and files | |
3620 | * @hsotg: The driver state | |
3621 | * | |
3622 | * Create the debugfs files to allow the user to get information | |
3623 | * about the state of the system. The directory name is created | |
3624 | * with the same name as the device itself, in case we end up | |
3625 | * with multiple blocks in future systems. | |
8b9bc460 | 3626 | */ |
941fcce4 | 3627 | static void s3c_hsotg_create_debug(struct dwc2_hsotg *hsotg) |
5b7d70c6 BD |
3628 | { |
3629 | struct dentry *root; | |
3630 | unsigned epidx; | |
3631 | ||
3632 | root = debugfs_create_dir(dev_name(hsotg->dev), NULL); | |
3633 | hsotg->debug_root = root; | |
3634 | if (IS_ERR(root)) { | |
3635 | dev_err(hsotg->dev, "cannot create debug root\n"); | |
3636 | return; | |
3637 | } | |
3638 | ||
3639 | /* create general state file */ | |
3640 | ||
3641 | hsotg->debug_file = debugfs_create_file("state", 0444, root, | |
3642 | hsotg, &state_fops); | |
3643 | ||
3644 | if (IS_ERR(hsotg->debug_file)) | |
3645 | dev_err(hsotg->dev, "%s: failed to create state\n", __func__); | |
3646 | ||
9e14d0a5 GH |
3647 | hsotg->debug_testmode = debugfs_create_file("testmode", |
3648 | S_IRUGO | S_IWUSR, root, | |
3649 | hsotg, &testmode_fops); | |
3650 | ||
3651 | if (IS_ERR(hsotg->debug_testmode)) | |
3652 | dev_err(hsotg->dev, "%s: failed to create testmode\n", | |
3653 | __func__); | |
3654 | ||
5b7d70c6 BD |
3655 | hsotg->debug_fifo = debugfs_create_file("fifo", 0444, root, |
3656 | hsotg, &fifo_fops); | |
3657 | ||
3658 | if (IS_ERR(hsotg->debug_fifo)) | |
3659 | dev_err(hsotg->dev, "%s: failed to create fifo\n", __func__); | |
3660 | ||
c6f5c050 | 3661 | /* Create one file for each out endpoint */ |
b3f489b2 | 3662 | for (epidx = 0; epidx < hsotg->num_of_eps; epidx++) { |
c6f5c050 | 3663 | struct s3c_hsotg_ep *ep; |
5b7d70c6 | 3664 | |
c6f5c050 MYK |
3665 | ep = hsotg->eps_out[epidx]; |
3666 | if (ep) { | |
3667 | ep->debugfs = debugfs_create_file(ep->name, 0444, | |
3668 | root, ep, &ep_fops); | |
5b7d70c6 | 3669 | |
c6f5c050 MYK |
3670 | if (IS_ERR(ep->debugfs)) |
3671 | dev_err(hsotg->dev, "failed to create %s debug file\n", | |
3672 | ep->name); | |
3673 | } | |
3674 | } | |
3675 | /* Create one file for each in endpoint. EP0 is handled with out eps */ | |
3676 | for (epidx = 1; epidx < hsotg->num_of_eps; epidx++) { | |
3677 | struct s3c_hsotg_ep *ep; | |
3678 | ||
3679 | ep = hsotg->eps_in[epidx]; | |
3680 | if (ep) { | |
3681 | ep->debugfs = debugfs_create_file(ep->name, 0444, | |
3682 | root, ep, &ep_fops); | |
3683 | ||
3684 | if (IS_ERR(ep->debugfs)) | |
3685 | dev_err(hsotg->dev, "failed to create %s debug file\n", | |
3686 | ep->name); | |
3687 | } | |
5b7d70c6 BD |
3688 | } |
3689 | } | |
3690 | ||
3691 | /** | |
3692 | * s3c_hsotg_delete_debug - cleanup debugfs entries | |
3693 | * @hsotg: The driver state | |
3694 | * | |
3695 | * Cleanup (remove) the debugfs files for use on module exit. | |
8b9bc460 | 3696 | */ |
941fcce4 | 3697 | static void s3c_hsotg_delete_debug(struct dwc2_hsotg *hsotg) |
5b7d70c6 BD |
3698 | { |
3699 | unsigned epidx; | |
3700 | ||
b3f489b2 | 3701 | for (epidx = 0; epidx < hsotg->num_of_eps; epidx++) { |
c6f5c050 MYK |
3702 | if (hsotg->eps_in[epidx]) |
3703 | debugfs_remove(hsotg->eps_in[epidx]->debugfs); | |
3704 | if (hsotg->eps_out[epidx]) | |
3705 | debugfs_remove(hsotg->eps_out[epidx]->debugfs); | |
5b7d70c6 BD |
3706 | } |
3707 | ||
3708 | debugfs_remove(hsotg->debug_file); | |
9e14d0a5 | 3709 | debugfs_remove(hsotg->debug_testmode); |
5b7d70c6 BD |
3710 | debugfs_remove(hsotg->debug_fifo); |
3711 | debugfs_remove(hsotg->debug_root); | |
3712 | } | |
3713 | ||
edd74be8 GH |
3714 | #ifdef CONFIG_OF |
3715 | static void s3c_hsotg_of_probe(struct dwc2_hsotg *hsotg) | |
3716 | { | |
3717 | struct device_node *np = hsotg->dev->of_node; | |
0a176279 GH |
3718 | u32 len = 0; |
3719 | u32 i = 0; | |
edd74be8 GH |
3720 | |
3721 | /* Enable dma if requested in device tree */ | |
3722 | hsotg->g_using_dma = of_property_read_bool(np, "g-use-dma"); | |
0a176279 GH |
3723 | |
3724 | /* | |
3725 | * Register TX periodic fifo size per endpoint. | |
3726 | * EP0 is excluded since it has no fifo configuration. | |
3727 | */ | |
3728 | if (!of_find_property(np, "g-tx-fifo-size", &len)) | |
3729 | goto rx_fifo; | |
3730 | ||
3731 | len /= sizeof(u32); | |
3732 | ||
3733 | /* Read tx fifo sizes other than ep0 */ | |
3734 | if (of_property_read_u32_array(np, "g-tx-fifo-size", | |
3735 | &hsotg->g_tx_fifo_sz[1], len)) | |
3736 | goto rx_fifo; | |
3737 | ||
3738 | /* Add ep0 */ | |
3739 | len++; | |
3740 | ||
3741 | /* Make remaining TX fifos unavailable */ | |
3742 | if (len < MAX_EPS_CHANNELS) { | |
3743 | for (i = len; i < MAX_EPS_CHANNELS; i++) | |
3744 | hsotg->g_tx_fifo_sz[i] = 0; | |
3745 | } | |
3746 | ||
3747 | rx_fifo: | |
3748 | /* Register RX fifo size */ | |
3749 | of_property_read_u32(np, "g-rx-fifo-size", &hsotg->g_rx_fifo_sz); | |
3750 | ||
3751 | /* Register NPTX fifo size */ | |
3752 | of_property_read_u32(np, "g-np-tx-fifo-size", | |
3753 | &hsotg->g_np_g_tx_fifo_sz); | |
edd74be8 GH |
3754 | } |
3755 | #else | |
3756 | static inline void s3c_hsotg_of_probe(struct dwc2_hsotg *hsotg) { } | |
3757 | #endif | |
3758 | ||
8b9bc460 | 3759 | /** |
117777b2 DN |
3760 | * dwc2_gadget_init - init function for gadget |
3761 | * @dwc2: The data structure for the DWC2 driver. | |
3762 | * @irq: The IRQ number for the controller. | |
8b9bc460 | 3763 | */ |
117777b2 | 3764 | int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq) |
5b7d70c6 | 3765 | { |
117777b2 DN |
3766 | struct device *dev = hsotg->dev; |
3767 | struct s3c_hsotg_plat *plat = dev->platform_data; | |
5b7d70c6 BD |
3768 | int epnum; |
3769 | int ret; | |
fc9a731e | 3770 | int i; |
0a176279 | 3771 | u32 p_tx_fifo[] = DWC2_G_P_LEGACY_TX_FIFO_SIZE; |
5b7d70c6 | 3772 | |
1b59fc7e KD |
3773 | /* Set default UTMI width */ |
3774 | hsotg->phyif = GUSBCFG_PHYIF16; | |
3775 | ||
edd74be8 GH |
3776 | s3c_hsotg_of_probe(hsotg); |
3777 | ||
0a176279 GH |
3778 | /* Initialize to legacy fifo configuration values */ |
3779 | hsotg->g_rx_fifo_sz = 2048; | |
3780 | hsotg->g_np_g_tx_fifo_sz = 1024; | |
3781 | memcpy(&hsotg->g_tx_fifo_sz[1], p_tx_fifo, sizeof(p_tx_fifo)); | |
3782 | /* Device tree specific probe */ | |
3783 | s3c_hsotg_of_probe(hsotg); | |
3784 | /* Dump fifo information */ | |
3785 | dev_dbg(dev, "NonPeriodic TXFIFO size: %d\n", | |
3786 | hsotg->g_np_g_tx_fifo_sz); | |
3787 | dev_dbg(dev, "RXFIFO size: %d\n", hsotg->g_rx_fifo_sz); | |
3788 | for (i = 0; i < MAX_EPS_CHANNELS; i++) | |
3789 | dev_dbg(dev, "Periodic TXFIFO%2d size: %d\n", i, | |
3790 | hsotg->g_tx_fifo_sz[i]); | |
74084844 | 3791 | /* |
135b3c43 YL |
3792 | * If platform probe couldn't find a generic PHY or an old style |
3793 | * USB PHY, fall back to pdata | |
74084844 | 3794 | */ |
135b3c43 YL |
3795 | if (IS_ERR_OR_NULL(hsotg->phy) && IS_ERR_OR_NULL(hsotg->uphy)) { |
3796 | plat = dev_get_platdata(dev); | |
3797 | if (!plat) { | |
3798 | dev_err(dev, | |
3799 | "no platform data or transceiver defined\n"); | |
3800 | return -EPROBE_DEFER; | |
3801 | } | |
3802 | hsotg->plat = plat; | |
3803 | } else if (hsotg->phy) { | |
1b59fc7e KD |
3804 | /* |
3805 | * If using the generic PHY framework, check if the PHY bus | |
3806 | * width is 8-bit and set the phyif appropriately. | |
3807 | */ | |
135b3c43 | 3808 | if (phy_get_bus_width(hsotg->phy) == 8) |
1b59fc7e KD |
3809 | hsotg->phyif = GUSBCFG_PHYIF8; |
3810 | } | |
b2e587db | 3811 | |
117777b2 | 3812 | hsotg->clk = devm_clk_get(dev, "otg"); |
31ee04de | 3813 | if (IS_ERR(hsotg->clk)) { |
8d736d8a | 3814 | hsotg->clk = NULL; |
f415fbd1 | 3815 | dev_dbg(dev, "cannot get otg clock\n"); |
5b7d70c6 BD |
3816 | } |
3817 | ||
d327ab5b | 3818 | hsotg->gadget.max_speed = USB_SPEED_HIGH; |
5b7d70c6 BD |
3819 | hsotg->gadget.ops = &s3c_hsotg_gadget_ops; |
3820 | hsotg->gadget.name = dev_name(dev); | |
5b7d70c6 | 3821 | |
5b7d70c6 BD |
3822 | /* reset the system */ |
3823 | ||
f415fbd1 DN |
3824 | ret = clk_prepare_enable(hsotg->clk); |
3825 | if (ret) { | |
3826 | dev_err(dev, "failed to enable otg clk\n"); | |
3827 | goto err_clk; | |
3828 | } | |
3829 | ||
31ee04de | 3830 | |
fc9a731e LM |
3831 | /* regulators */ |
3832 | ||
3833 | for (i = 0; i < ARRAY_SIZE(hsotg->supplies); i++) | |
3834 | hsotg->supplies[i].supply = s3c_hsotg_supply_names[i]; | |
3835 | ||
cd76213e | 3836 | ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(hsotg->supplies), |
fc9a731e LM |
3837 | hsotg->supplies); |
3838 | if (ret) { | |
3839 | dev_err(dev, "failed to request supplies: %d\n", ret); | |
338edabc | 3840 | goto err_clk; |
fc9a731e LM |
3841 | } |
3842 | ||
3843 | ret = regulator_bulk_enable(ARRAY_SIZE(hsotg->supplies), | |
3844 | hsotg->supplies); | |
3845 | ||
3846 | if (ret) { | |
941fcce4 | 3847 | dev_err(dev, "failed to enable supplies: %d\n", ret); |
c139ec27 | 3848 | goto err_clk; |
fc9a731e LM |
3849 | } |
3850 | ||
41188786 LM |
3851 | /* usb phy enable */ |
3852 | s3c_hsotg_phy_enable(hsotg); | |
5b7d70c6 | 3853 | |
1b7a66b4 GH |
3854 | /* |
3855 | * Force Device mode before initialization. | |
3856 | * This allows correctly configuring fifo for device mode. | |
3857 | */ | |
3858 | __bic32(hsotg->regs + GUSBCFG, GUSBCFG_FORCEHOSTMODE); | |
3859 | __orr32(hsotg->regs + GUSBCFG, GUSBCFG_FORCEDEVMODE); | |
3860 | ||
3861 | /* | |
3862 | * According to Synopsys databook, this sleep is needed for the force | |
3863 | * device mode to take effect. | |
3864 | */ | |
3865 | msleep(25); | |
3866 | ||
5b7d70c6 | 3867 | s3c_hsotg_corereset(hsotg); |
c6f5c050 MYK |
3868 | ret = s3c_hsotg_hw_cfg(hsotg); |
3869 | if (ret) { | |
3870 | dev_err(hsotg->dev, "Hardware configuration failed: %d\n", ret); | |
3871 | goto err_clk; | |
3872 | } | |
3873 | ||
cff9eb75 | 3874 | s3c_hsotg_init(hsotg); |
b3f489b2 | 3875 | |
1b7a66b4 GH |
3876 | /* Switch back to default configuration */ |
3877 | __bic32(hsotg->regs + GUSBCFG, GUSBCFG_FORCEDEVMODE); | |
3878 | ||
3f95001d MYK |
3879 | hsotg->ctrl_buff = devm_kzalloc(hsotg->dev, |
3880 | DWC2_CTRL_BUFF_SIZE, GFP_KERNEL); | |
3881 | if (!hsotg->ctrl_buff) { | |
3882 | dev_err(dev, "failed to allocate ctrl request buff\n"); | |
3883 | ret = -ENOMEM; | |
3884 | goto err_supplies; | |
3885 | } | |
3886 | ||
3887 | hsotg->ep0_buff = devm_kzalloc(hsotg->dev, | |
3888 | DWC2_CTRL_BUFF_SIZE, GFP_KERNEL); | |
3889 | if (!hsotg->ep0_buff) { | |
3890 | dev_err(dev, "failed to allocate ctrl reply buff\n"); | |
3891 | ret = -ENOMEM; | |
3892 | goto err_supplies; | |
3893 | } | |
3894 | ||
db8178c3 DN |
3895 | ret = devm_request_irq(hsotg->dev, irq, s3c_hsotg_irq, IRQF_SHARED, |
3896 | dev_name(hsotg->dev), hsotg); | |
eb3c56c5 MS |
3897 | if (ret < 0) { |
3898 | s3c_hsotg_phy_disable(hsotg); | |
3899 | clk_disable_unprepare(hsotg->clk); | |
3900 | regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies), | |
3901 | hsotg->supplies); | |
db8178c3 | 3902 | dev_err(dev, "cannot claim IRQ for gadget\n"); |
c139ec27 | 3903 | goto err_supplies; |
eb3c56c5 MS |
3904 | } |
3905 | ||
b3f489b2 LM |
3906 | /* hsotg->num_of_eps holds number of EPs other than ep0 */ |
3907 | ||
3908 | if (hsotg->num_of_eps == 0) { | |
3909 | dev_err(dev, "wrong number of EPs (zero)\n"); | |
dfdda5a0 | 3910 | ret = -EINVAL; |
b3f489b2 LM |
3911 | goto err_supplies; |
3912 | } | |
3913 | ||
b3f489b2 LM |
3914 | /* setup endpoint information */ |
3915 | ||
3916 | INIT_LIST_HEAD(&hsotg->gadget.ep_list); | |
c6f5c050 | 3917 | hsotg->gadget.ep0 = &hsotg->eps_out[0]->ep; |
b3f489b2 LM |
3918 | |
3919 | /* allocate EP0 request */ | |
3920 | ||
c6f5c050 | 3921 | hsotg->ctrl_req = s3c_hsotg_ep_alloc_request(&hsotg->eps_out[0]->ep, |
b3f489b2 LM |
3922 | GFP_KERNEL); |
3923 | if (!hsotg->ctrl_req) { | |
3924 | dev_err(dev, "failed to allocate ctrl req\n"); | |
dfdda5a0 | 3925 | ret = -ENOMEM; |
c6f5c050 | 3926 | goto err_supplies; |
b3f489b2 | 3927 | } |
5b7d70c6 BD |
3928 | |
3929 | /* initialise the endpoints now the core has been initialised */ | |
c6f5c050 MYK |
3930 | for (epnum = 0; epnum < hsotg->num_of_eps; epnum++) { |
3931 | if (hsotg->eps_in[epnum]) | |
3932 | s3c_hsotg_initep(hsotg, hsotg->eps_in[epnum], | |
3933 | epnum, 1); | |
3934 | if (hsotg->eps_out[epnum]) | |
3935 | s3c_hsotg_initep(hsotg, hsotg->eps_out[epnum], | |
3936 | epnum, 0); | |
3937 | } | |
5b7d70c6 | 3938 | |
f65f0f10 | 3939 | /* disable power and clock */ |
3a8146aa | 3940 | s3c_hsotg_phy_disable(hsotg); |
f65f0f10 LM |
3941 | |
3942 | ret = regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies), | |
3943 | hsotg->supplies); | |
3944 | if (ret) { | |
117777b2 | 3945 | dev_err(dev, "failed to disable supplies: %d\n", ret); |
c6f5c050 | 3946 | goto err_supplies; |
f65f0f10 LM |
3947 | } |
3948 | ||
117777b2 | 3949 | ret = usb_add_gadget_udc(dev, &hsotg->gadget); |
0f91349b | 3950 | if (ret) |
c6f5c050 | 3951 | goto err_supplies; |
0f91349b | 3952 | |
5b7d70c6 BD |
3953 | s3c_hsotg_create_debug(hsotg); |
3954 | ||
3955 | s3c_hsotg_dump(hsotg); | |
3956 | ||
5b7d70c6 BD |
3957 | return 0; |
3958 | ||
fc9a731e | 3959 | err_supplies: |
41188786 | 3960 | s3c_hsotg_phy_disable(hsotg); |
31ee04de | 3961 | err_clk: |
1d144c67 | 3962 | clk_disable_unprepare(hsotg->clk); |
338edabc | 3963 | |
5b7d70c6 BD |
3964 | return ret; |
3965 | } | |
117777b2 | 3966 | EXPORT_SYMBOL_GPL(dwc2_gadget_init); |
5b7d70c6 | 3967 | |
8b9bc460 LM |
3968 | /** |
3969 | * s3c_hsotg_remove - remove function for hsotg driver | |
3970 | * @pdev: The platform information for the driver | |
3971 | */ | |
117777b2 | 3972 | int s3c_hsotg_remove(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 3973 | { |
0f91349b | 3974 | usb_del_gadget_udc(&hsotg->gadget); |
5b7d70c6 | 3975 | s3c_hsotg_delete_debug(hsotg); |
04b4a0fc | 3976 | clk_disable_unprepare(hsotg->clk); |
31ee04de | 3977 | |
5b7d70c6 BD |
3978 | return 0; |
3979 | } | |
117777b2 | 3980 | EXPORT_SYMBOL_GPL(s3c_hsotg_remove); |
5b7d70c6 | 3981 | |
117777b2 | 3982 | int s3c_hsotg_suspend(struct dwc2_hsotg *hsotg) |
b83e333a | 3983 | { |
b83e333a MS |
3984 | unsigned long flags; |
3985 | int ret = 0; | |
3986 | ||
7ad8096e MS |
3987 | mutex_lock(&hsotg->init_mutex); |
3988 | ||
dc6e69e6 MS |
3989 | if (hsotg->driver) { |
3990 | int ep; | |
3991 | ||
b83e333a MS |
3992 | dev_info(hsotg->dev, "suspending usb gadget %s\n", |
3993 | hsotg->driver->driver.name); | |
3994 | ||
dc6e69e6 MS |
3995 | spin_lock_irqsave(&hsotg->lock, flags); |
3996 | if (hsotg->enabled) | |
3997 | s3c_hsotg_core_disconnect(hsotg); | |
3998 | s3c_hsotg_disconnect(hsotg); | |
3999 | hsotg->gadget.speed = USB_SPEED_UNKNOWN; | |
4000 | spin_unlock_irqrestore(&hsotg->lock, flags); | |
b83e333a | 4001 | |
dc6e69e6 | 4002 | s3c_hsotg_phy_disable(hsotg); |
b83e333a | 4003 | |
c6f5c050 MYK |
4004 | for (ep = 0; ep < hsotg->num_of_eps; ep++) { |
4005 | if (hsotg->eps_in[ep]) | |
4006 | s3c_hsotg_ep_disable(&hsotg->eps_in[ep]->ep); | |
4007 | if (hsotg->eps_out[ep]) | |
4008 | s3c_hsotg_ep_disable(&hsotg->eps_out[ep]->ep); | |
4009 | } | |
b83e333a MS |
4010 | |
4011 | ret = regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies), | |
4012 | hsotg->supplies); | |
d00b4142 | 4013 | clk_disable(hsotg->clk); |
b83e333a MS |
4014 | } |
4015 | ||
7ad8096e MS |
4016 | mutex_unlock(&hsotg->init_mutex); |
4017 | ||
b83e333a MS |
4018 | return ret; |
4019 | } | |
117777b2 | 4020 | EXPORT_SYMBOL_GPL(s3c_hsotg_suspend); |
b83e333a | 4021 | |
117777b2 | 4022 | int s3c_hsotg_resume(struct dwc2_hsotg *hsotg) |
b83e333a | 4023 | { |
b83e333a MS |
4024 | unsigned long flags; |
4025 | int ret = 0; | |
4026 | ||
7ad8096e MS |
4027 | mutex_lock(&hsotg->init_mutex); |
4028 | ||
b83e333a MS |
4029 | if (hsotg->driver) { |
4030 | dev_info(hsotg->dev, "resuming usb gadget %s\n", | |
4031 | hsotg->driver->driver.name); | |
d00b4142 RB |
4032 | |
4033 | clk_enable(hsotg->clk); | |
b83e333a | 4034 | ret = regulator_bulk_enable(ARRAY_SIZE(hsotg->supplies), |
dc6e69e6 | 4035 | hsotg->supplies); |
b83e333a | 4036 | |
dc6e69e6 | 4037 | s3c_hsotg_phy_enable(hsotg); |
b83e333a | 4038 | |
dc6e69e6 MS |
4039 | spin_lock_irqsave(&hsotg->lock, flags); |
4040 | s3c_hsotg_core_init_disconnected(hsotg); | |
4041 | if (hsotg->enabled) | |
4042 | s3c_hsotg_core_connect(hsotg); | |
4043 | spin_unlock_irqrestore(&hsotg->lock, flags); | |
4044 | } | |
7ad8096e | 4045 | mutex_unlock(&hsotg->init_mutex); |
b83e333a MS |
4046 | |
4047 | return ret; | |
4048 | } | |
117777b2 | 4049 | EXPORT_SYMBOL_GPL(s3c_hsotg_resume); |