Commit | Line | Data |
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5fd54ace | 1 | // SPDX-License-Identifier: GPL-2.0 |
6fb914d7 | 2 | /* |
dfbc6fa3 AT |
3 | * Copyright (c) 2011 Samsung Electronics Co., Ltd. |
4 | * http://www.samsung.com | |
5b7d70c6 BD |
5 | * |
6 | * Copyright 2008 Openmoko, Inc. | |
7 | * Copyright 2008 Simtec Electronics | |
8 | * Ben Dooks <ben@simtec.co.uk> | |
9 | * http://armlinux.simtec.co.uk/ | |
10 | * | |
11 | * S3C USB2.0 High-speed / OtG driver | |
8b9bc460 | 12 | */ |
5b7d70c6 BD |
13 | |
14 | #include <linux/kernel.h> | |
15 | #include <linux/module.h> | |
16 | #include <linux/spinlock.h> | |
17 | #include <linux/interrupt.h> | |
18 | #include <linux/platform_device.h> | |
19 | #include <linux/dma-mapping.h> | |
7ad8096e | 20 | #include <linux/mutex.h> |
5b7d70c6 BD |
21 | #include <linux/seq_file.h> |
22 | #include <linux/delay.h> | |
23 | #include <linux/io.h> | |
5a0e3ad6 | 24 | #include <linux/slab.h> |
c50f056c | 25 | #include <linux/of_platform.h> |
5b7d70c6 BD |
26 | |
27 | #include <linux/usb/ch9.h> | |
28 | #include <linux/usb/gadget.h> | |
b2e587db | 29 | #include <linux/usb/phy.h> |
5b7d70c6 | 30 | |
f7c0b143 | 31 | #include "core.h" |
941fcce4 | 32 | #include "hw.h" |
5b7d70c6 BD |
33 | |
34 | /* conversion functions */ | |
1f91b4cc | 35 | static inline struct dwc2_hsotg_req *our_req(struct usb_request *req) |
5b7d70c6 | 36 | { |
1f91b4cc | 37 | return container_of(req, struct dwc2_hsotg_req, req); |
5b7d70c6 BD |
38 | } |
39 | ||
1f91b4cc | 40 | static inline struct dwc2_hsotg_ep *our_ep(struct usb_ep *ep) |
5b7d70c6 | 41 | { |
1f91b4cc | 42 | return container_of(ep, struct dwc2_hsotg_ep, ep); |
5b7d70c6 BD |
43 | } |
44 | ||
941fcce4 | 45 | static inline struct dwc2_hsotg *to_hsotg(struct usb_gadget *gadget) |
5b7d70c6 | 46 | { |
941fcce4 | 47 | return container_of(gadget, struct dwc2_hsotg, gadget); |
5b7d70c6 BD |
48 | } |
49 | ||
f25c42b8 | 50 | static inline void dwc2_set_bit(struct dwc2_hsotg *hsotg, u32 offset, u32 val) |
5b7d70c6 | 51 | { |
f25c42b8 | 52 | dwc2_writel(hsotg, dwc2_readl(hsotg, offset) | val, offset); |
5b7d70c6 BD |
53 | } |
54 | ||
f25c42b8 | 55 | static inline void dwc2_clear_bit(struct dwc2_hsotg *hsotg, u32 offset, u32 val) |
5b7d70c6 | 56 | { |
f25c42b8 | 57 | dwc2_writel(hsotg, dwc2_readl(hsotg, offset) & ~val, offset); |
5b7d70c6 BD |
58 | } |
59 | ||
1f91b4cc | 60 | static inline struct dwc2_hsotg_ep *index_to_ep(struct dwc2_hsotg *hsotg, |
c6f5c050 MYK |
61 | u32 ep_index, u32 dir_in) |
62 | { | |
63 | if (dir_in) | |
64 | return hsotg->eps_in[ep_index]; | |
65 | else | |
66 | return hsotg->eps_out[ep_index]; | |
67 | } | |
68 | ||
997f4f81 | 69 | /* forward declaration of functions */ |
1f91b4cc | 70 | static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg); |
5b7d70c6 BD |
71 | |
72 | /** | |
73 | * using_dma - return the DMA status of the driver. | |
74 | * @hsotg: The driver state. | |
75 | * | |
76 | * Return true if we're using DMA. | |
77 | * | |
78 | * Currently, we have the DMA support code worked into everywhere | |
79 | * that needs it, but the AMBA DMA implementation in the hardware can | |
80 | * only DMA from 32bit aligned addresses. This means that gadgets such | |
81 | * as the CDC Ethernet cannot work as they often pass packets which are | |
82 | * not 32bit aligned. | |
83 | * | |
84 | * Unfortunately the choice to use DMA or not is global to the controller | |
85 | * and seems to be only settable when the controller is being put through | |
86 | * a core reset. This means we either need to fix the gadgets to take | |
87 | * account of DMA alignment, or add bounce buffers (yuerk). | |
88 | * | |
edd74be8 | 89 | * g_using_dma is set depending on dts flag. |
5b7d70c6 | 90 | */ |
941fcce4 | 91 | static inline bool using_dma(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 92 | { |
05ee799f | 93 | return hsotg->params.g_dma; |
5b7d70c6 BD |
94 | } |
95 | ||
dec4b556 VA |
96 | /* |
97 | * using_desc_dma - return the descriptor DMA status of the driver. | |
98 | * @hsotg: The driver state. | |
99 | * | |
100 | * Return true if we're using descriptor DMA. | |
101 | */ | |
102 | static inline bool using_desc_dma(struct dwc2_hsotg *hsotg) | |
103 | { | |
104 | return hsotg->params.g_dma_desc; | |
105 | } | |
106 | ||
92d1635d VM |
107 | /** |
108 | * dwc2_gadget_incr_frame_num - Increments the targeted frame number. | |
109 | * @hs_ep: The endpoint | |
92d1635d VM |
110 | * |
111 | * This function will also check if the frame number overruns DSTS_SOFFN_LIMIT. | |
112 | * If an overrun occurs it will wrap the value and set the frame_overrun flag. | |
113 | */ | |
114 | static inline void dwc2_gadget_incr_frame_num(struct dwc2_hsotg_ep *hs_ep) | |
115 | { | |
116 | hs_ep->target_frame += hs_ep->interval; | |
117 | if (hs_ep->target_frame > DSTS_SOFFN_LIMIT) { | |
c1d5df69 | 118 | hs_ep->frame_overrun = true; |
92d1635d VM |
119 | hs_ep->target_frame &= DSTS_SOFFN_LIMIT; |
120 | } else { | |
c1d5df69 | 121 | hs_ep->frame_overrun = false; |
92d1635d VM |
122 | } |
123 | } | |
124 | ||
9d630b9c GT |
125 | /** |
126 | * dwc2_gadget_dec_frame_num_by_one - Decrements the targeted frame number | |
127 | * by one. | |
128 | * @hs_ep: The endpoint. | |
129 | * | |
130 | * This function used in service interval based scheduling flow to calculate | |
131 | * descriptor frame number filed value. For service interval mode frame | |
132 | * number in descriptor should point to last (u)frame in the interval. | |
133 | * | |
134 | */ | |
135 | static inline void dwc2_gadget_dec_frame_num_by_one(struct dwc2_hsotg_ep *hs_ep) | |
136 | { | |
137 | if (hs_ep->target_frame) | |
138 | hs_ep->target_frame -= 1; | |
139 | else | |
140 | hs_ep->target_frame = DSTS_SOFFN_LIMIT; | |
141 | } | |
142 | ||
5b7d70c6 | 143 | /** |
1f91b4cc | 144 | * dwc2_hsotg_en_gsint - enable one or more of the general interrupt |
5b7d70c6 BD |
145 | * @hsotg: The device state |
146 | * @ints: A bitmask of the interrupts to enable | |
147 | */ | |
1f91b4cc | 148 | static void dwc2_hsotg_en_gsint(struct dwc2_hsotg *hsotg, u32 ints) |
5b7d70c6 | 149 | { |
f25c42b8 | 150 | u32 gsintmsk = dwc2_readl(hsotg, GINTMSK); |
5b7d70c6 BD |
151 | u32 new_gsintmsk; |
152 | ||
153 | new_gsintmsk = gsintmsk | ints; | |
154 | ||
155 | if (new_gsintmsk != gsintmsk) { | |
156 | dev_dbg(hsotg->dev, "gsintmsk now 0x%08x\n", new_gsintmsk); | |
f25c42b8 | 157 | dwc2_writel(hsotg, new_gsintmsk, GINTMSK); |
5b7d70c6 BD |
158 | } |
159 | } | |
160 | ||
161 | /** | |
1f91b4cc | 162 | * dwc2_hsotg_disable_gsint - disable one or more of the general interrupt |
5b7d70c6 BD |
163 | * @hsotg: The device state |
164 | * @ints: A bitmask of the interrupts to enable | |
165 | */ | |
1f91b4cc | 166 | static void dwc2_hsotg_disable_gsint(struct dwc2_hsotg *hsotg, u32 ints) |
5b7d70c6 | 167 | { |
f25c42b8 | 168 | u32 gsintmsk = dwc2_readl(hsotg, GINTMSK); |
5b7d70c6 BD |
169 | u32 new_gsintmsk; |
170 | ||
171 | new_gsintmsk = gsintmsk & ~ints; | |
172 | ||
173 | if (new_gsintmsk != gsintmsk) | |
f25c42b8 | 174 | dwc2_writel(hsotg, new_gsintmsk, GINTMSK); |
5b7d70c6 BD |
175 | } |
176 | ||
177 | /** | |
1f91b4cc | 178 | * dwc2_hsotg_ctrl_epint - enable/disable an endpoint irq |
5b7d70c6 BD |
179 | * @hsotg: The device state |
180 | * @ep: The endpoint index | |
181 | * @dir_in: True if direction is in. | |
182 | * @en: The enable value, true to enable | |
183 | * | |
184 | * Set or clear the mask for an individual endpoint's interrupt | |
185 | * request. | |
186 | */ | |
1f91b4cc | 187 | static void dwc2_hsotg_ctrl_epint(struct dwc2_hsotg *hsotg, |
9da51974 | 188 | unsigned int ep, unsigned int dir_in, |
5b7d70c6 BD |
189 | unsigned int en) |
190 | { | |
191 | unsigned long flags; | |
192 | u32 bit = 1 << ep; | |
193 | u32 daint; | |
194 | ||
195 | if (!dir_in) | |
196 | bit <<= 16; | |
197 | ||
198 | local_irq_save(flags); | |
f25c42b8 | 199 | daint = dwc2_readl(hsotg, DAINTMSK); |
5b7d70c6 BD |
200 | if (en) |
201 | daint |= bit; | |
202 | else | |
203 | daint &= ~bit; | |
f25c42b8 | 204 | dwc2_writel(hsotg, daint, DAINTMSK); |
5b7d70c6 BD |
205 | local_irq_restore(flags); |
206 | } | |
207 | ||
c138ecfa SA |
208 | /** |
209 | * dwc2_hsotg_tx_fifo_count - return count of TX FIFOs in device mode | |
6fb914d7 GT |
210 | * |
211 | * @hsotg: Programming view of the DWC_otg controller | |
c138ecfa SA |
212 | */ |
213 | int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg *hsotg) | |
214 | { | |
215 | if (hsotg->hw_params.en_multiple_tx_fifo) | |
216 | /* In dedicated FIFO mode we need count of IN EPs */ | |
9273083a | 217 | return hsotg->hw_params.num_dev_in_eps; |
c138ecfa SA |
218 | else |
219 | /* In shared FIFO mode we need count of Periodic IN EPs */ | |
220 | return hsotg->hw_params.num_dev_perio_in_ep; | |
221 | } | |
222 | ||
c138ecfa SA |
223 | /** |
224 | * dwc2_hsotg_tx_fifo_total_depth - return total FIFO depth available for | |
225 | * device mode TX FIFOs | |
6fb914d7 GT |
226 | * |
227 | * @hsotg: Programming view of the DWC_otg controller | |
c138ecfa SA |
228 | */ |
229 | int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg) | |
230 | { | |
c138ecfa SA |
231 | int addr; |
232 | int tx_addr_max; | |
233 | u32 np_tx_fifo_size; | |
234 | ||
235 | np_tx_fifo_size = min_t(u32, hsotg->hw_params.dev_nperio_tx_fifo_size, | |
236 | hsotg->params.g_np_tx_fifo_size); | |
237 | ||
238 | /* Get Endpoint Info Control block size in DWORDs. */ | |
9273083a | 239 | tx_addr_max = hsotg->hw_params.total_fifo_size; |
c138ecfa SA |
240 | |
241 | addr = hsotg->params.g_rx_fifo_size + np_tx_fifo_size; | |
242 | if (tx_addr_max <= addr) | |
243 | return 0; | |
244 | ||
245 | return tx_addr_max - addr; | |
246 | } | |
247 | ||
187c5298 GT |
248 | /** |
249 | * dwc2_gadget_wkup_alert_handler - Handler for WKUP_ALERT interrupt | |
250 | * | |
251 | * @hsotg: Programming view of the DWC_otg controller | |
252 | * | |
253 | */ | |
254 | static void dwc2_gadget_wkup_alert_handler(struct dwc2_hsotg *hsotg) | |
255 | { | |
256 | u32 gintsts2; | |
257 | u32 gintmsk2; | |
258 | ||
259 | gintsts2 = dwc2_readl(hsotg, GINTSTS2); | |
260 | gintmsk2 = dwc2_readl(hsotg, GINTMSK2); | |
261 | ||
262 | if (gintsts2 & GINTSTS2_WKUP_ALERT_INT) { | |
263 | dev_dbg(hsotg->dev, "%s: Wkup_Alert_Int\n", __func__); | |
87b6d2c5 | 264 | dwc2_set_bit(hsotg, GINTSTS2, GINTSTS2_WKUP_ALERT_INT); |
d64bc8ee | 265 | dwc2_set_bit(hsotg, DCTL, DCTL_RMTWKUPSIG); |
187c5298 GT |
266 | } |
267 | } | |
268 | ||
c138ecfa SA |
269 | /** |
270 | * dwc2_hsotg_tx_fifo_average_depth - returns average depth of device mode | |
271 | * TX FIFOs | |
6fb914d7 GT |
272 | * |
273 | * @hsotg: Programming view of the DWC_otg controller | |
c138ecfa SA |
274 | */ |
275 | int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg *hsotg) | |
276 | { | |
277 | int tx_fifo_count; | |
278 | int tx_fifo_depth; | |
279 | ||
280 | tx_fifo_depth = dwc2_hsotg_tx_fifo_total_depth(hsotg); | |
281 | ||
282 | tx_fifo_count = dwc2_hsotg_tx_fifo_count(hsotg); | |
283 | ||
284 | if (!tx_fifo_count) | |
285 | return tx_fifo_depth; | |
286 | else | |
287 | return tx_fifo_depth / tx_fifo_count; | |
288 | } | |
289 | ||
5b7d70c6 | 290 | /** |
1f91b4cc | 291 | * dwc2_hsotg_init_fifo - initialise non-periodic FIFOs |
5b7d70c6 BD |
292 | * @hsotg: The device instance. |
293 | */ | |
1f91b4cc | 294 | static void dwc2_hsotg_init_fifo(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 295 | { |
2317eacd | 296 | unsigned int ep; |
0f002d20 | 297 | unsigned int addr; |
1703a6d3 | 298 | int timeout; |
79d6b8c5 | 299 | |
0f002d20 | 300 | u32 val; |
05ee799f | 301 | u32 *txfsz = hsotg->params.g_tx_fifo_size; |
0f002d20 | 302 | |
7fcbc95c GH |
303 | /* Reset fifo map if not correctly cleared during previous session */ |
304 | WARN_ON(hsotg->fifo_map); | |
305 | hsotg->fifo_map = 0; | |
306 | ||
0a176279 | 307 | /* set RX/NPTX FIFO sizes */ |
f25c42b8 GS |
308 | dwc2_writel(hsotg, hsotg->params.g_rx_fifo_size, GRXFSIZ); |
309 | dwc2_writel(hsotg, (hsotg->params.g_rx_fifo_size << | |
310 | FIFOSIZE_STARTADDR_SHIFT) | | |
05ee799f | 311 | (hsotg->params.g_np_tx_fifo_size << FIFOSIZE_DEPTH_SHIFT), |
f25c42b8 | 312 | GNPTXFSIZ); |
0f002d20 | 313 | |
8b9bc460 LM |
314 | /* |
315 | * arange all the rest of the TX FIFOs, as some versions of this | |
0f002d20 BD |
316 | * block have overlapping default addresses. This also ensures |
317 | * that if the settings have been changed, then they are set to | |
8b9bc460 LM |
318 | * known values. |
319 | */ | |
0f002d20 BD |
320 | |
321 | /* start at the end of the GNPTXFSIZ, rounded up */ | |
05ee799f | 322 | addr = hsotg->params.g_rx_fifo_size + hsotg->params.g_np_tx_fifo_size; |
0f002d20 | 323 | |
8b9bc460 | 324 | /* |
0a176279 | 325 | * Configure fifos sizes from provided configuration and assign |
b203d0a2 RB |
326 | * them to endpoints dynamically according to maxpacket size value of |
327 | * given endpoint. | |
8b9bc460 | 328 | */ |
2317eacd | 329 | for (ep = 1; ep < MAX_EPS_CHANNELS; ep++) { |
05ee799f | 330 | if (!txfsz[ep]) |
3fa95385 JY |
331 | continue; |
332 | val = addr; | |
05ee799f JY |
333 | val |= txfsz[ep] << FIFOSIZE_DEPTH_SHIFT; |
334 | WARN_ONCE(addr + txfsz[ep] > hsotg->fifo_mem, | |
3fa95385 | 335 | "insufficient fifo memory"); |
05ee799f | 336 | addr += txfsz[ep]; |
0f002d20 | 337 | |
f25c42b8 GS |
338 | dwc2_writel(hsotg, val, DPTXFSIZN(ep)); |
339 | val = dwc2_readl(hsotg, DPTXFSIZN(ep)); | |
0f002d20 | 340 | } |
1703a6d3 | 341 | |
f25c42b8 | 342 | dwc2_writel(hsotg, hsotg->hw_params.total_fifo_size | |
f87c842f | 343 | addr << GDFIFOCFG_EPINFOBASE_SHIFT, |
f25c42b8 | 344 | GDFIFOCFG); |
8b9bc460 LM |
345 | /* |
346 | * according to p428 of the design guide, we need to ensure that | |
347 | * all fifos are flushed before continuing | |
348 | */ | |
1703a6d3 | 349 | |
f25c42b8 GS |
350 | dwc2_writel(hsotg, GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH | |
351 | GRSTCTL_RXFFLSH, GRSTCTL); | |
1703a6d3 BD |
352 | |
353 | /* wait until the fifos are both flushed */ | |
354 | timeout = 100; | |
355 | while (1) { | |
f25c42b8 | 356 | val = dwc2_readl(hsotg, GRSTCTL); |
1703a6d3 | 357 | |
47a1685f | 358 | if ((val & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH)) == 0) |
1703a6d3 BD |
359 | break; |
360 | ||
361 | if (--timeout == 0) { | |
362 | dev_err(hsotg->dev, | |
363 | "%s: timeout flushing fifos (GRSTCTL=%08x)\n", | |
364 | __func__, val); | |
48b20bcb | 365 | break; |
1703a6d3 BD |
366 | } |
367 | ||
368 | udelay(1); | |
369 | } | |
370 | ||
371 | dev_dbg(hsotg->dev, "FIFOs reset, timeout at %d\n", timeout); | |
5b7d70c6 BD |
372 | } |
373 | ||
374 | /** | |
6fb914d7 | 375 | * dwc2_hsotg_ep_alloc_request - allocate USB rerequest structure |
5b7d70c6 BD |
376 | * @ep: USB endpoint to allocate request for. |
377 | * @flags: Allocation flags | |
378 | * | |
379 | * Allocate a new USB request structure appropriate for the specified endpoint | |
380 | */ | |
1f91b4cc | 381 | static struct usb_request *dwc2_hsotg_ep_alloc_request(struct usb_ep *ep, |
9da51974 | 382 | gfp_t flags) |
5b7d70c6 | 383 | { |
1f91b4cc | 384 | struct dwc2_hsotg_req *req; |
5b7d70c6 | 385 | |
ec33efe2 | 386 | req = kzalloc(sizeof(*req), flags); |
5b7d70c6 BD |
387 | if (!req) |
388 | return NULL; | |
389 | ||
390 | INIT_LIST_HEAD(&req->queue); | |
391 | ||
5b7d70c6 BD |
392 | return &req->req; |
393 | } | |
394 | ||
395 | /** | |
396 | * is_ep_periodic - return true if the endpoint is in periodic mode. | |
397 | * @hs_ep: The endpoint to query. | |
398 | * | |
399 | * Returns true if the endpoint is in periodic mode, meaning it is being | |
400 | * used for an Interrupt or ISO transfer. | |
401 | */ | |
1f91b4cc | 402 | static inline int is_ep_periodic(struct dwc2_hsotg_ep *hs_ep) |
5b7d70c6 BD |
403 | { |
404 | return hs_ep->periodic; | |
405 | } | |
406 | ||
407 | /** | |
1f91b4cc | 408 | * dwc2_hsotg_unmap_dma - unmap the DMA memory being used for the request |
5b7d70c6 BD |
409 | * @hsotg: The device state. |
410 | * @hs_ep: The endpoint for the request | |
411 | * @hs_req: The request being processed. | |
412 | * | |
1f91b4cc | 413 | * This is the reverse of dwc2_hsotg_map_dma(), called for the completion |
5b7d70c6 | 414 | * of a request to ensure the buffer is ready for access by the caller. |
8b9bc460 | 415 | */ |
1f91b4cc | 416 | static void dwc2_hsotg_unmap_dma(struct dwc2_hsotg *hsotg, |
9da51974 | 417 | struct dwc2_hsotg_ep *hs_ep, |
1f91b4cc | 418 | struct dwc2_hsotg_req *hs_req) |
5b7d70c6 BD |
419 | { |
420 | struct usb_request *req = &hs_req->req; | |
9da51974 | 421 | |
17d966a3 | 422 | usb_gadget_unmap_request(&hsotg->gadget, req, hs_ep->dir_in); |
5b7d70c6 BD |
423 | } |
424 | ||
0f6b80c0 VA |
425 | /* |
426 | * dwc2_gadget_alloc_ctrl_desc_chains - allocate DMA descriptor chains | |
427 | * for Control endpoint | |
428 | * @hsotg: The device state. | |
429 | * | |
430 | * This function will allocate 4 descriptor chains for EP 0: 2 for | |
431 | * Setup stage, per one for IN and OUT data/status transactions. | |
432 | */ | |
433 | static int dwc2_gadget_alloc_ctrl_desc_chains(struct dwc2_hsotg *hsotg) | |
434 | { | |
435 | hsotg->setup_desc[0] = | |
436 | dmam_alloc_coherent(hsotg->dev, | |
437 | sizeof(struct dwc2_dma_desc), | |
438 | &hsotg->setup_desc_dma[0], | |
439 | GFP_KERNEL); | |
440 | if (!hsotg->setup_desc[0]) | |
441 | goto fail; | |
442 | ||
443 | hsotg->setup_desc[1] = | |
444 | dmam_alloc_coherent(hsotg->dev, | |
445 | sizeof(struct dwc2_dma_desc), | |
446 | &hsotg->setup_desc_dma[1], | |
447 | GFP_KERNEL); | |
448 | if (!hsotg->setup_desc[1]) | |
449 | goto fail; | |
450 | ||
451 | hsotg->ctrl_in_desc = | |
452 | dmam_alloc_coherent(hsotg->dev, | |
453 | sizeof(struct dwc2_dma_desc), | |
454 | &hsotg->ctrl_in_desc_dma, | |
455 | GFP_KERNEL); | |
456 | if (!hsotg->ctrl_in_desc) | |
457 | goto fail; | |
458 | ||
459 | hsotg->ctrl_out_desc = | |
460 | dmam_alloc_coherent(hsotg->dev, | |
461 | sizeof(struct dwc2_dma_desc), | |
462 | &hsotg->ctrl_out_desc_dma, | |
463 | GFP_KERNEL); | |
464 | if (!hsotg->ctrl_out_desc) | |
465 | goto fail; | |
466 | ||
467 | return 0; | |
468 | ||
469 | fail: | |
470 | return -ENOMEM; | |
471 | } | |
472 | ||
5b7d70c6 | 473 | /** |
1f91b4cc | 474 | * dwc2_hsotg_write_fifo - write packet Data to the TxFIFO |
5b7d70c6 BD |
475 | * @hsotg: The controller state. |
476 | * @hs_ep: The endpoint we're going to write for. | |
477 | * @hs_req: The request to write data for. | |
478 | * | |
479 | * This is called when the TxFIFO has some space in it to hold a new | |
480 | * transmission and we have something to give it. The actual setup of | |
481 | * the data size is done elsewhere, so all we have to do is to actually | |
482 | * write the data. | |
483 | * | |
484 | * The return value is zero if there is more space (or nothing was done) | |
485 | * otherwise -ENOSPC is returned if the FIFO space was used up. | |
486 | * | |
487 | * This routine is only needed for PIO | |
8b9bc460 | 488 | */ |
1f91b4cc | 489 | static int dwc2_hsotg_write_fifo(struct dwc2_hsotg *hsotg, |
9da51974 | 490 | struct dwc2_hsotg_ep *hs_ep, |
1f91b4cc | 491 | struct dwc2_hsotg_req *hs_req) |
5b7d70c6 BD |
492 | { |
493 | bool periodic = is_ep_periodic(hs_ep); | |
f25c42b8 | 494 | u32 gnptxsts = dwc2_readl(hsotg, GNPTXSTS); |
5b7d70c6 BD |
495 | int buf_pos = hs_req->req.actual; |
496 | int to_write = hs_ep->size_loaded; | |
497 | void *data; | |
498 | int can_write; | |
499 | int pkt_round; | |
4fca54aa | 500 | int max_transfer; |
5b7d70c6 BD |
501 | |
502 | to_write -= (buf_pos - hs_ep->last_load); | |
503 | ||
504 | /* if there's nothing to write, get out early */ | |
505 | if (to_write == 0) | |
506 | return 0; | |
507 | ||
10aebc77 | 508 | if (periodic && !hsotg->dedicated_fifos) { |
f25c42b8 | 509 | u32 epsize = dwc2_readl(hsotg, DIEPTSIZ(hs_ep->index)); |
5b7d70c6 BD |
510 | int size_left; |
511 | int size_done; | |
512 | ||
8b9bc460 LM |
513 | /* |
514 | * work out how much data was loaded so we can calculate | |
515 | * how much data is left in the fifo. | |
516 | */ | |
5b7d70c6 | 517 | |
47a1685f | 518 | size_left = DXEPTSIZ_XFERSIZE_GET(epsize); |
5b7d70c6 | 519 | |
8b9bc460 LM |
520 | /* |
521 | * if shared fifo, we cannot write anything until the | |
e7a9ff54 BD |
522 | * previous data has been completely sent. |
523 | */ | |
524 | if (hs_ep->fifo_load != 0) { | |
1f91b4cc | 525 | dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP); |
e7a9ff54 BD |
526 | return -ENOSPC; |
527 | } | |
528 | ||
5b7d70c6 BD |
529 | dev_dbg(hsotg->dev, "%s: left=%d, load=%d, fifo=%d, size %d\n", |
530 | __func__, size_left, | |
531 | hs_ep->size_loaded, hs_ep->fifo_load, hs_ep->fifo_size); | |
532 | ||
533 | /* how much of the data has moved */ | |
534 | size_done = hs_ep->size_loaded - size_left; | |
535 | ||
536 | /* how much data is left in the fifo */ | |
537 | can_write = hs_ep->fifo_load - size_done; | |
538 | dev_dbg(hsotg->dev, "%s: => can_write1=%d\n", | |
539 | __func__, can_write); | |
540 | ||
541 | can_write = hs_ep->fifo_size - can_write; | |
542 | dev_dbg(hsotg->dev, "%s: => can_write2=%d\n", | |
543 | __func__, can_write); | |
544 | ||
545 | if (can_write <= 0) { | |
1f91b4cc | 546 | dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP); |
5b7d70c6 BD |
547 | return -ENOSPC; |
548 | } | |
10aebc77 | 549 | } else if (hsotg->dedicated_fifos && hs_ep->index != 0) { |
f25c42b8 GS |
550 | can_write = dwc2_readl(hsotg, |
551 | DTXFSTS(hs_ep->fifo_index)); | |
10aebc77 BD |
552 | |
553 | can_write &= 0xffff; | |
554 | can_write *= 4; | |
5b7d70c6 | 555 | } else { |
47a1685f | 556 | if (GNPTXSTS_NP_TXQ_SPC_AVAIL_GET(gnptxsts) == 0) { |
5b7d70c6 BD |
557 | dev_dbg(hsotg->dev, |
558 | "%s: no queue slots available (0x%08x)\n", | |
559 | __func__, gnptxsts); | |
560 | ||
1f91b4cc | 561 | dwc2_hsotg_en_gsint(hsotg, GINTSTS_NPTXFEMP); |
5b7d70c6 BD |
562 | return -ENOSPC; |
563 | } | |
564 | ||
47a1685f | 565 | can_write = GNPTXSTS_NP_TXF_SPC_AVAIL_GET(gnptxsts); |
679f9b7c | 566 | can_write *= 4; /* fifo size is in 32bit quantities. */ |
5b7d70c6 BD |
567 | } |
568 | ||
4fca54aa RB |
569 | max_transfer = hs_ep->ep.maxpacket * hs_ep->mc; |
570 | ||
571 | dev_dbg(hsotg->dev, "%s: GNPTXSTS=%08x, can=%d, to=%d, max_transfer %d\n", | |
9da51974 | 572 | __func__, gnptxsts, can_write, to_write, max_transfer); |
5b7d70c6 | 573 | |
8b9bc460 LM |
574 | /* |
575 | * limit to 512 bytes of data, it seems at least on the non-periodic | |
5b7d70c6 BD |
576 | * FIFO, requests of >512 cause the endpoint to get stuck with a |
577 | * fragment of the end of the transfer in it. | |
578 | */ | |
811f3303 | 579 | if (can_write > 512 && !periodic) |
5b7d70c6 BD |
580 | can_write = 512; |
581 | ||
8b9bc460 LM |
582 | /* |
583 | * limit the write to one max-packet size worth of data, but allow | |
03e10e5a | 584 | * the transfer to return that it did not run out of fifo space |
8b9bc460 LM |
585 | * doing it. |
586 | */ | |
4fca54aa RB |
587 | if (to_write > max_transfer) { |
588 | to_write = max_transfer; | |
03e10e5a | 589 | |
5cb2ff0c RB |
590 | /* it's needed only when we do not use dedicated fifos */ |
591 | if (!hsotg->dedicated_fifos) | |
1f91b4cc | 592 | dwc2_hsotg_en_gsint(hsotg, |
9da51974 | 593 | periodic ? GINTSTS_PTXFEMP : |
47a1685f | 594 | GINTSTS_NPTXFEMP); |
03e10e5a BD |
595 | } |
596 | ||
5b7d70c6 BD |
597 | /* see if we can write data */ |
598 | ||
599 | if (to_write > can_write) { | |
600 | to_write = can_write; | |
4fca54aa | 601 | pkt_round = to_write % max_transfer; |
5b7d70c6 | 602 | |
8b9bc460 LM |
603 | /* |
604 | * Round the write down to an | |
5b7d70c6 BD |
605 | * exact number of packets. |
606 | * | |
607 | * Note, we do not currently check to see if we can ever | |
608 | * write a full packet or not to the FIFO. | |
609 | */ | |
610 | ||
611 | if (pkt_round) | |
612 | to_write -= pkt_round; | |
613 | ||
8b9bc460 LM |
614 | /* |
615 | * enable correct FIFO interrupt to alert us when there | |
616 | * is more room left. | |
617 | */ | |
5b7d70c6 | 618 | |
5cb2ff0c RB |
619 | /* it's needed only when we do not use dedicated fifos */ |
620 | if (!hsotg->dedicated_fifos) | |
1f91b4cc | 621 | dwc2_hsotg_en_gsint(hsotg, |
9da51974 | 622 | periodic ? GINTSTS_PTXFEMP : |
47a1685f | 623 | GINTSTS_NPTXFEMP); |
5b7d70c6 BD |
624 | } |
625 | ||
626 | dev_dbg(hsotg->dev, "write %d/%d, can_write %d, done %d\n", | |
9da51974 | 627 | to_write, hs_req->req.length, can_write, buf_pos); |
5b7d70c6 BD |
628 | |
629 | if (to_write <= 0) | |
630 | return -ENOSPC; | |
631 | ||
632 | hs_req->req.actual = buf_pos + to_write; | |
633 | hs_ep->total_data += to_write; | |
634 | ||
635 | if (periodic) | |
636 | hs_ep->fifo_load += to_write; | |
637 | ||
638 | to_write = DIV_ROUND_UP(to_write, 4); | |
639 | data = hs_req->req.buf + buf_pos; | |
640 | ||
342ccce1 | 641 | dwc2_writel_rep(hsotg, EPFIFO(hs_ep->index), data, to_write); |
5b7d70c6 BD |
642 | |
643 | return (to_write >= can_write) ? -ENOSPC : 0; | |
644 | } | |
645 | ||
646 | /** | |
647 | * get_ep_limit - get the maximum data legnth for this endpoint | |
648 | * @hs_ep: The endpoint | |
649 | * | |
650 | * Return the maximum data that can be queued in one go on a given endpoint | |
651 | * so that transfers that are too long can be split. | |
652 | */ | |
9da51974 | 653 | static unsigned int get_ep_limit(struct dwc2_hsotg_ep *hs_ep) |
5b7d70c6 BD |
654 | { |
655 | int index = hs_ep->index; | |
9da51974 JY |
656 | unsigned int maxsize; |
657 | unsigned int maxpkt; | |
5b7d70c6 BD |
658 | |
659 | if (index != 0) { | |
47a1685f DN |
660 | maxsize = DXEPTSIZ_XFERSIZE_LIMIT + 1; |
661 | maxpkt = DXEPTSIZ_PKTCNT_LIMIT + 1; | |
5b7d70c6 | 662 | } else { |
9da51974 | 663 | maxsize = 64 + 64; |
66e5c643 | 664 | if (hs_ep->dir_in) |
47a1685f | 665 | maxpkt = DIEPTSIZ0_PKTCNT_LIMIT + 1; |
66e5c643 | 666 | else |
5b7d70c6 | 667 | maxpkt = 2; |
5b7d70c6 BD |
668 | } |
669 | ||
670 | /* we made the constant loading easier above by using +1 */ | |
671 | maxpkt--; | |
672 | maxsize--; | |
673 | ||
8b9bc460 LM |
674 | /* |
675 | * constrain by packet count if maxpkts*pktsize is greater | |
676 | * than the length register size. | |
677 | */ | |
5b7d70c6 BD |
678 | |
679 | if ((maxpkt * hs_ep->ep.maxpacket) < maxsize) | |
680 | maxsize = maxpkt * hs_ep->ep.maxpacket; | |
681 | ||
682 | return maxsize; | |
683 | } | |
684 | ||
381fc8f8 | 685 | /** |
38beaec6 JY |
686 | * dwc2_hsotg_read_frameno - read current frame number |
687 | * @hsotg: The device instance | |
688 | * | |
689 | * Return the current frame number | |
690 | */ | |
381fc8f8 VM |
691 | static u32 dwc2_hsotg_read_frameno(struct dwc2_hsotg *hsotg) |
692 | { | |
693 | u32 dsts; | |
694 | ||
f25c42b8 | 695 | dsts = dwc2_readl(hsotg, DSTS); |
381fc8f8 VM |
696 | dsts &= DSTS_SOFFN_MASK; |
697 | dsts >>= DSTS_SOFFN_SHIFT; | |
698 | ||
699 | return dsts; | |
700 | } | |
701 | ||
cf77b5fb VA |
702 | /** |
703 | * dwc2_gadget_get_chain_limit - get the maximum data payload value of the | |
704 | * DMA descriptor chain prepared for specific endpoint | |
705 | * @hs_ep: The endpoint | |
706 | * | |
707 | * Return the maximum data that can be queued in one go on a given endpoint | |
708 | * depending on its descriptor chain capacity so that transfers that | |
709 | * are too long can be split. | |
710 | */ | |
711 | static unsigned int dwc2_gadget_get_chain_limit(struct dwc2_hsotg_ep *hs_ep) | |
712 | { | |
713 | int is_isoc = hs_ep->isochronous; | |
714 | unsigned int maxsize; | |
715 | ||
716 | if (is_isoc) | |
717 | maxsize = hs_ep->dir_in ? DEV_DMA_ISOC_TX_NBYTES_LIMIT : | |
718 | DEV_DMA_ISOC_RX_NBYTES_LIMIT; | |
719 | else | |
720 | maxsize = DEV_DMA_NBYTES_LIMIT; | |
721 | ||
722 | /* Above size of one descriptor was chosen, multiple it */ | |
723 | maxsize *= MAX_DMA_DESC_NUM_GENERIC; | |
724 | ||
725 | return maxsize; | |
726 | } | |
727 | ||
e02f9aa6 VA |
728 | /* |
729 | * dwc2_gadget_get_desc_params - get DMA descriptor parameters. | |
730 | * @hs_ep: The endpoint | |
731 | * @mask: RX/TX bytes mask to be defined | |
732 | * | |
733 | * Returns maximum data payload for one descriptor after analyzing endpoint | |
734 | * characteristics. | |
735 | * DMA descriptor transfer bytes limit depends on EP type: | |
736 | * Control out - MPS, | |
737 | * Isochronous - descriptor rx/tx bytes bitfield limit, | |
738 | * Control In/Bulk/Interrupt - multiple of mps. This will allow to not | |
739 | * have concatenations from various descriptors within one packet. | |
740 | * | |
741 | * Selects corresponding mask for RX/TX bytes as well. | |
742 | */ | |
743 | static u32 dwc2_gadget_get_desc_params(struct dwc2_hsotg_ep *hs_ep, u32 *mask) | |
744 | { | |
745 | u32 mps = hs_ep->ep.maxpacket; | |
746 | int dir_in = hs_ep->dir_in; | |
747 | u32 desc_size = 0; | |
748 | ||
749 | if (!hs_ep->index && !dir_in) { | |
750 | desc_size = mps; | |
751 | *mask = DEV_DMA_NBYTES_MASK; | |
752 | } else if (hs_ep->isochronous) { | |
753 | if (dir_in) { | |
754 | desc_size = DEV_DMA_ISOC_TX_NBYTES_LIMIT; | |
755 | *mask = DEV_DMA_ISOC_TX_NBYTES_MASK; | |
756 | } else { | |
757 | desc_size = DEV_DMA_ISOC_RX_NBYTES_LIMIT; | |
758 | *mask = DEV_DMA_ISOC_RX_NBYTES_MASK; | |
759 | } | |
760 | } else { | |
761 | desc_size = DEV_DMA_NBYTES_LIMIT; | |
762 | *mask = DEV_DMA_NBYTES_MASK; | |
763 | ||
764 | /* Round down desc_size to be mps multiple */ | |
765 | desc_size -= desc_size % mps; | |
766 | } | |
767 | ||
768 | return desc_size; | |
769 | } | |
770 | ||
10209abe AP |
771 | static void dwc2_gadget_fill_nonisoc_xfer_ddma_one(struct dwc2_hsotg_ep *hs_ep, |
772 | struct dwc2_dma_desc **desc, | |
e02f9aa6 | 773 | dma_addr_t dma_buff, |
10209abe AP |
774 | unsigned int len, |
775 | bool true_last) | |
e02f9aa6 | 776 | { |
e02f9aa6 | 777 | int dir_in = hs_ep->dir_in; |
e02f9aa6 VA |
778 | u32 mps = hs_ep->ep.maxpacket; |
779 | u32 maxsize = 0; | |
780 | u32 offset = 0; | |
781 | u32 mask = 0; | |
782 | int i; | |
783 | ||
784 | maxsize = dwc2_gadget_get_desc_params(hs_ep, &mask); | |
785 | ||
786 | hs_ep->desc_count = (len / maxsize) + | |
787 | ((len % maxsize) ? 1 : 0); | |
788 | if (len == 0) | |
789 | hs_ep->desc_count = 1; | |
790 | ||
791 | for (i = 0; i < hs_ep->desc_count; ++i) { | |
10209abe AP |
792 | (*desc)->status = 0; |
793 | (*desc)->status |= (DEV_DMA_BUFF_STS_HBUSY | |
e02f9aa6 VA |
794 | << DEV_DMA_BUFF_STS_SHIFT); |
795 | ||
796 | if (len > maxsize) { | |
797 | if (!hs_ep->index && !dir_in) | |
10209abe | 798 | (*desc)->status |= (DEV_DMA_L | DEV_DMA_IOC); |
e02f9aa6 | 799 | |
10209abe AP |
800 | (*desc)->status |= |
801 | maxsize << DEV_DMA_NBYTES_SHIFT & mask; | |
802 | (*desc)->buf = dma_buff + offset; | |
e02f9aa6 VA |
803 | |
804 | len -= maxsize; | |
805 | offset += maxsize; | |
806 | } else { | |
10209abe AP |
807 | if (true_last) |
808 | (*desc)->status |= (DEV_DMA_L | DEV_DMA_IOC); | |
e02f9aa6 VA |
809 | |
810 | if (dir_in) | |
10209abe AP |
811 | (*desc)->status |= (len % mps) ? DEV_DMA_SHORT : |
812 | ((hs_ep->send_zlp && true_last) ? | |
813 | DEV_DMA_SHORT : 0); | |
e02f9aa6 | 814 | |
10209abe | 815 | (*desc)->status |= |
e02f9aa6 | 816 | len << DEV_DMA_NBYTES_SHIFT & mask; |
10209abe | 817 | (*desc)->buf = dma_buff + offset; |
e02f9aa6 VA |
818 | } |
819 | ||
10209abe AP |
820 | (*desc)->status &= ~DEV_DMA_BUFF_STS_MASK; |
821 | (*desc)->status |= (DEV_DMA_BUFF_STS_HREADY | |
e02f9aa6 | 822 | << DEV_DMA_BUFF_STS_SHIFT); |
10209abe AP |
823 | (*desc)++; |
824 | } | |
825 | } | |
826 | ||
827 | /* | |
828 | * dwc2_gadget_config_nonisoc_xfer_ddma - prepare non ISOC DMA desc chain. | |
829 | * @hs_ep: The endpoint | |
830 | * @ureq: Request to transfer | |
831 | * @offset: offset in bytes | |
832 | * @len: Length of the transfer | |
833 | * | |
834 | * This function will iterate over descriptor chain and fill its entries | |
835 | * with corresponding information based on transfer data. | |
836 | */ | |
837 | static void dwc2_gadget_config_nonisoc_xfer_ddma(struct dwc2_hsotg_ep *hs_ep, | |
838 | struct usb_request *ureq, | |
839 | unsigned int offset, | |
840 | unsigned int len) | |
841 | { | |
842 | struct dwc2_dma_desc *desc = hs_ep->desc_list; | |
843 | struct scatterlist *sg; | |
844 | int i; | |
845 | u8 desc_count = 0; | |
846 | ||
847 | /* non-DMA sg buffer */ | |
848 | if (!ureq->num_sgs) { | |
849 | dwc2_gadget_fill_nonisoc_xfer_ddma_one(hs_ep, &desc, | |
850 | ureq->dma + offset, len, true); | |
851 | return; | |
e02f9aa6 | 852 | } |
10209abe AP |
853 | |
854 | /* DMA sg buffer */ | |
855 | for_each_sg(ureq->sg, sg, ureq->num_sgs, i) { | |
856 | dwc2_gadget_fill_nonisoc_xfer_ddma_one(hs_ep, &desc, | |
857 | sg_dma_address(sg) + sg->offset, sg_dma_len(sg), | |
858 | sg_is_last(sg)); | |
859 | desc_count += hs_ep->desc_count; | |
860 | } | |
861 | ||
862 | hs_ep->desc_count = desc_count; | |
e02f9aa6 VA |
863 | } |
864 | ||
540ccba0 VA |
865 | /* |
866 | * dwc2_gadget_fill_isoc_desc - fills next isochronous descriptor in chain. | |
867 | * @hs_ep: The isochronous endpoint. | |
868 | * @dma_buff: usb requests dma buffer. | |
869 | * @len: usb request transfer length. | |
870 | * | |
729cac69 | 871 | * Fills next free descriptor with the data of the arrived usb request, |
540ccba0 VA |
872 | * frame info, sets Last and IOC bits increments next_desc. If filled |
873 | * descriptor is not the first one, removes L bit from the previous descriptor | |
874 | * status. | |
875 | */ | |
876 | static int dwc2_gadget_fill_isoc_desc(struct dwc2_hsotg_ep *hs_ep, | |
877 | dma_addr_t dma_buff, unsigned int len) | |
878 | { | |
879 | struct dwc2_dma_desc *desc; | |
880 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
881 | u32 index; | |
882 | u32 maxsize = 0; | |
883 | u32 mask = 0; | |
1d8e5c00 | 884 | u8 pid = 0; |
540ccba0 VA |
885 | |
886 | maxsize = dwc2_gadget_get_desc_params(hs_ep, &mask); | |
540ccba0 | 887 | |
729cac69 MH |
888 | index = hs_ep->next_desc; |
889 | desc = &hs_ep->desc_list[index]; | |
540ccba0 | 890 | |
729cac69 MH |
891 | /* Check if descriptor chain full */ |
892 | if ((desc->status >> DEV_DMA_BUFF_STS_SHIFT) == | |
893 | DEV_DMA_BUFF_STS_HREADY) { | |
894 | dev_dbg(hsotg->dev, "%s: desc chain full\n", __func__); | |
895 | return 1; | |
540ccba0 VA |
896 | } |
897 | ||
540ccba0 VA |
898 | /* Clear L bit of previous desc if more than one entries in the chain */ |
899 | if (hs_ep->next_desc) | |
900 | hs_ep->desc_list[index - 1].status &= ~DEV_DMA_L; | |
901 | ||
902 | dev_dbg(hsotg->dev, "%s: Filling ep %d, dir %s isoc desc # %d\n", | |
903 | __func__, hs_ep->index, hs_ep->dir_in ? "in" : "out", index); | |
904 | ||
905 | desc->status = 0; | |
906 | desc->status |= (DEV_DMA_BUFF_STS_HBUSY << DEV_DMA_BUFF_STS_SHIFT); | |
907 | ||
908 | desc->buf = dma_buff; | |
909 | desc->status |= (DEV_DMA_L | DEV_DMA_IOC | | |
910 | ((len << DEV_DMA_NBYTES_SHIFT) & mask)); | |
911 | ||
912 | if (hs_ep->dir_in) { | |
1d8e5c00 MH |
913 | if (len) |
914 | pid = DIV_ROUND_UP(len, hs_ep->ep.maxpacket); | |
915 | else | |
916 | pid = 1; | |
917 | desc->status |= ((pid << DEV_DMA_ISOC_PID_SHIFT) & | |
540ccba0 VA |
918 | DEV_DMA_ISOC_PID_MASK) | |
919 | ((len % hs_ep->ep.maxpacket) ? | |
920 | DEV_DMA_SHORT : 0) | | |
921 | ((hs_ep->target_frame << | |
922 | DEV_DMA_ISOC_FRNUM_SHIFT) & | |
923 | DEV_DMA_ISOC_FRNUM_MASK); | |
924 | } | |
925 | ||
926 | desc->status &= ~DEV_DMA_BUFF_STS_MASK; | |
927 | desc->status |= (DEV_DMA_BUFF_STS_HREADY << DEV_DMA_BUFF_STS_SHIFT); | |
928 | ||
729cac69 MH |
929 | /* Increment frame number by interval for IN */ |
930 | if (hs_ep->dir_in) | |
931 | dwc2_gadget_incr_frame_num(hs_ep); | |
932 | ||
540ccba0 VA |
933 | /* Update index of last configured entry in the chain */ |
934 | hs_ep->next_desc++; | |
729cac69 MH |
935 | if (hs_ep->next_desc >= MAX_DMA_DESC_NUM_GENERIC) |
936 | hs_ep->next_desc = 0; | |
540ccba0 VA |
937 | |
938 | return 0; | |
939 | } | |
940 | ||
941 | /* | |
942 | * dwc2_gadget_start_isoc_ddma - start isochronous transfer in DDMA | |
943 | * @hs_ep: The isochronous endpoint. | |
944 | * | |
729cac69 | 945 | * Prepare descriptor chain for isochronous endpoints. Afterwards |
540ccba0 | 946 | * write DMA address to HW and enable the endpoint. |
540ccba0 VA |
947 | */ |
948 | static void dwc2_gadget_start_isoc_ddma(struct dwc2_hsotg_ep *hs_ep) | |
949 | { | |
950 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
951 | struct dwc2_hsotg_req *hs_req, *treq; | |
952 | int index = hs_ep->index; | |
953 | int ret; | |
729cac69 | 954 | int i; |
540ccba0 VA |
955 | u32 dma_reg; |
956 | u32 depctl; | |
957 | u32 ctrl; | |
729cac69 | 958 | struct dwc2_dma_desc *desc; |
540ccba0 VA |
959 | |
960 | if (list_empty(&hs_ep->queue)) { | |
1ffba905 | 961 | hs_ep->target_frame = TARGET_FRAME_INITIAL; |
540ccba0 VA |
962 | dev_dbg(hsotg->dev, "%s: No requests in queue\n", __func__); |
963 | return; | |
964 | } | |
965 | ||
729cac69 MH |
966 | /* Initialize descriptor chain by Host Busy status */ |
967 | for (i = 0; i < MAX_DMA_DESC_NUM_GENERIC; i++) { | |
968 | desc = &hs_ep->desc_list[i]; | |
969 | desc->status = 0; | |
970 | desc->status |= (DEV_DMA_BUFF_STS_HBUSY | |
971 | << DEV_DMA_BUFF_STS_SHIFT); | |
972 | } | |
973 | ||
974 | hs_ep->next_desc = 0; | |
540ccba0 | 975 | list_for_each_entry_safe(hs_req, treq, &hs_ep->queue, queue) { |
10209abe AP |
976 | dma_addr_t dma_addr = hs_req->req.dma; |
977 | ||
978 | if (hs_req->req.num_sgs) { | |
979 | WARN_ON(hs_req->req.num_sgs > 1); | |
980 | dma_addr = sg_dma_address(hs_req->req.sg); | |
981 | } | |
982 | ret = dwc2_gadget_fill_isoc_desc(hs_ep, dma_addr, | |
540ccba0 | 983 | hs_req->req.length); |
729cac69 | 984 | if (ret) |
540ccba0 | 985 | break; |
540ccba0 VA |
986 | } |
987 | ||
729cac69 | 988 | hs_ep->compl_desc = 0; |
540ccba0 VA |
989 | depctl = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index); |
990 | dma_reg = hs_ep->dir_in ? DIEPDMA(index) : DOEPDMA(index); | |
991 | ||
992 | /* write descriptor chain address to control register */ | |
f25c42b8 | 993 | dwc2_writel(hsotg, hs_ep->desc_list_dma, dma_reg); |
540ccba0 | 994 | |
f25c42b8 | 995 | ctrl = dwc2_readl(hsotg, depctl); |
540ccba0 | 996 | ctrl |= DXEPCTL_EPENA | DXEPCTL_CNAK; |
f25c42b8 | 997 | dwc2_writel(hsotg, ctrl, depctl); |
540ccba0 VA |
998 | } |
999 | ||
5b7d70c6 | 1000 | /** |
1f91b4cc | 1001 | * dwc2_hsotg_start_req - start a USB request from an endpoint's queue |
5b7d70c6 BD |
1002 | * @hsotg: The controller state. |
1003 | * @hs_ep: The endpoint to process a request for | |
1004 | * @hs_req: The request to start. | |
1005 | * @continuing: True if we are doing more for the current request. | |
1006 | * | |
1007 | * Start the given request running by setting the endpoint registers | |
1008 | * appropriately, and writing any data to the FIFOs. | |
1009 | */ | |
1f91b4cc | 1010 | static void dwc2_hsotg_start_req(struct dwc2_hsotg *hsotg, |
9da51974 | 1011 | struct dwc2_hsotg_ep *hs_ep, |
1f91b4cc | 1012 | struct dwc2_hsotg_req *hs_req, |
5b7d70c6 BD |
1013 | bool continuing) |
1014 | { | |
1015 | struct usb_request *ureq = &hs_req->req; | |
1016 | int index = hs_ep->index; | |
1017 | int dir_in = hs_ep->dir_in; | |
1018 | u32 epctrl_reg; | |
1019 | u32 epsize_reg; | |
1020 | u32 epsize; | |
1021 | u32 ctrl; | |
9da51974 JY |
1022 | unsigned int length; |
1023 | unsigned int packets; | |
1024 | unsigned int maxreq; | |
aa3e8bc8 | 1025 | unsigned int dma_reg; |
5b7d70c6 BD |
1026 | |
1027 | if (index != 0) { | |
1028 | if (hs_ep->req && !continuing) { | |
1029 | dev_err(hsotg->dev, "%s: active request\n", __func__); | |
1030 | WARN_ON(1); | |
1031 | return; | |
1032 | } else if (hs_ep->req != hs_req && continuing) { | |
1033 | dev_err(hsotg->dev, | |
1034 | "%s: continue different req\n", __func__); | |
1035 | WARN_ON(1); | |
1036 | return; | |
1037 | } | |
1038 | } | |
1039 | ||
aa3e8bc8 | 1040 | dma_reg = dir_in ? DIEPDMA(index) : DOEPDMA(index); |
94cb8fd6 LM |
1041 | epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index); |
1042 | epsize_reg = dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index); | |
5b7d70c6 BD |
1043 | |
1044 | dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n", | |
f25c42b8 | 1045 | __func__, dwc2_readl(hsotg, epctrl_reg), index, |
5b7d70c6 BD |
1046 | hs_ep->dir_in ? "in" : "out"); |
1047 | ||
9c39ddc6 | 1048 | /* If endpoint is stalled, we will restart request later */ |
f25c42b8 | 1049 | ctrl = dwc2_readl(hsotg, epctrl_reg); |
9c39ddc6 | 1050 | |
b2d4c54e | 1051 | if (index && ctrl & DXEPCTL_STALL) { |
9c39ddc6 AT |
1052 | dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index); |
1053 | return; | |
1054 | } | |
1055 | ||
5b7d70c6 | 1056 | length = ureq->length - ureq->actual; |
71225bee LM |
1057 | dev_dbg(hsotg->dev, "ureq->length:%d ureq->actual:%d\n", |
1058 | ureq->length, ureq->actual); | |
5b7d70c6 | 1059 | |
cf77b5fb VA |
1060 | if (!using_desc_dma(hsotg)) |
1061 | maxreq = get_ep_limit(hs_ep); | |
1062 | else | |
1063 | maxreq = dwc2_gadget_get_chain_limit(hs_ep); | |
1064 | ||
5b7d70c6 BD |
1065 | if (length > maxreq) { |
1066 | int round = maxreq % hs_ep->ep.maxpacket; | |
1067 | ||
1068 | dev_dbg(hsotg->dev, "%s: length %d, max-req %d, r %d\n", | |
1069 | __func__, length, maxreq, round); | |
1070 | ||
1071 | /* round down to multiple of packets */ | |
1072 | if (round) | |
1073 | maxreq -= round; | |
1074 | ||
1075 | length = maxreq; | |
1076 | } | |
1077 | ||
1078 | if (length) | |
1079 | packets = DIV_ROUND_UP(length, hs_ep->ep.maxpacket); | |
1080 | else | |
1081 | packets = 1; /* send one packet if length is zero. */ | |
1082 | ||
4fca54aa RB |
1083 | if (hs_ep->isochronous && length > (hs_ep->mc * hs_ep->ep.maxpacket)) { |
1084 | dev_err(hsotg->dev, "req length > maxpacket*mc\n"); | |
1085 | return; | |
1086 | } | |
1087 | ||
5b7d70c6 | 1088 | if (dir_in && index != 0) |
4fca54aa | 1089 | if (hs_ep->isochronous) |
47a1685f | 1090 | epsize = DXEPTSIZ_MC(packets); |
4fca54aa | 1091 | else |
47a1685f | 1092 | epsize = DXEPTSIZ_MC(1); |
5b7d70c6 BD |
1093 | else |
1094 | epsize = 0; | |
1095 | ||
f71b5e25 MYK |
1096 | /* |
1097 | * zero length packet should be programmed on its own and should not | |
1098 | * be counted in DIEPTSIZ.PktCnt with other packets. | |
1099 | */ | |
1100 | if (dir_in && ureq->zero && !continuing) { | |
1101 | /* Test if zlp is actually required. */ | |
1102 | if ((ureq->length >= hs_ep->ep.maxpacket) && | |
9da51974 | 1103 | !(ureq->length % hs_ep->ep.maxpacket)) |
8a20fa45 | 1104 | hs_ep->send_zlp = 1; |
5b7d70c6 BD |
1105 | } |
1106 | ||
47a1685f DN |
1107 | epsize |= DXEPTSIZ_PKTCNT(packets); |
1108 | epsize |= DXEPTSIZ_XFERSIZE(length); | |
5b7d70c6 BD |
1109 | |
1110 | dev_dbg(hsotg->dev, "%s: %d@%d/%d, 0x%08x => 0x%08x\n", | |
1111 | __func__, packets, length, ureq->length, epsize, epsize_reg); | |
1112 | ||
1113 | /* store the request as the current one we're doing */ | |
1114 | hs_ep->req = hs_req; | |
1115 | ||
aa3e8bc8 VA |
1116 | if (using_desc_dma(hsotg)) { |
1117 | u32 offset = 0; | |
1118 | u32 mps = hs_ep->ep.maxpacket; | |
1119 | ||
1120 | /* Adjust length: EP0 - MPS, other OUT EPs - multiple of MPS */ | |
1121 | if (!dir_in) { | |
1122 | if (!index) | |
1123 | length = mps; | |
1124 | else if (length % mps) | |
1125 | length += (mps - (length % mps)); | |
1126 | } | |
5b7d70c6 | 1127 | |
8b9bc460 | 1128 | /* |
aa3e8bc8 VA |
1129 | * If more data to send, adjust DMA for EP0 out data stage. |
1130 | * ureq->dma stays unchanged, hence increment it by already | |
1131 | * passed passed data count before starting new transaction. | |
8b9bc460 | 1132 | */ |
aa3e8bc8 VA |
1133 | if (!index && hsotg->ep0_state == DWC2_EP0_DATA_OUT && |
1134 | continuing) | |
1135 | offset = ureq->actual; | |
1136 | ||
1137 | /* Fill DDMA chain entries */ | |
10209abe | 1138 | dwc2_gadget_config_nonisoc_xfer_ddma(hs_ep, ureq, offset, |
aa3e8bc8 VA |
1139 | length); |
1140 | ||
1141 | /* write descriptor chain address to control register */ | |
f25c42b8 | 1142 | dwc2_writel(hsotg, hs_ep->desc_list_dma, dma_reg); |
5b7d70c6 | 1143 | |
aa3e8bc8 VA |
1144 | dev_dbg(hsotg->dev, "%s: %08x pad => 0x%08x\n", |
1145 | __func__, (u32)hs_ep->desc_list_dma, dma_reg); | |
1146 | } else { | |
1147 | /* write size / packets */ | |
f25c42b8 | 1148 | dwc2_writel(hsotg, epsize, epsize_reg); |
aa3e8bc8 | 1149 | |
729e6574 | 1150 | if (using_dma(hsotg) && !continuing && (length != 0)) { |
aa3e8bc8 VA |
1151 | /* |
1152 | * write DMA address to control register, buffer | |
1153 | * already synced by dwc2_hsotg_ep_queue(). | |
1154 | */ | |
5b7d70c6 | 1155 | |
f25c42b8 | 1156 | dwc2_writel(hsotg, ureq->dma, dma_reg); |
aa3e8bc8 VA |
1157 | |
1158 | dev_dbg(hsotg->dev, "%s: %pad => 0x%08x\n", | |
1159 | __func__, &ureq->dma, dma_reg); | |
1160 | } | |
5b7d70c6 BD |
1161 | } |
1162 | ||
837e9f00 VM |
1163 | if (hs_ep->isochronous && hs_ep->interval == 1) { |
1164 | hs_ep->target_frame = dwc2_hsotg_read_frameno(hsotg); | |
1165 | dwc2_gadget_incr_frame_num(hs_ep); | |
1166 | ||
1167 | if (hs_ep->target_frame & 0x1) | |
1168 | ctrl |= DXEPCTL_SETODDFR; | |
1169 | else | |
1170 | ctrl |= DXEPCTL_SETEVENFR; | |
1171 | } | |
1172 | ||
47a1685f | 1173 | ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */ |
71225bee | 1174 | |
fe0b94ab | 1175 | dev_dbg(hsotg->dev, "ep0 state:%d\n", hsotg->ep0_state); |
71225bee LM |
1176 | |
1177 | /* For Setup request do not clear NAK */ | |
fe0b94ab | 1178 | if (!(index == 0 && hsotg->ep0_state == DWC2_EP0_SETUP)) |
47a1685f | 1179 | ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */ |
71225bee | 1180 | |
5b7d70c6 | 1181 | dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl); |
f25c42b8 | 1182 | dwc2_writel(hsotg, ctrl, epctrl_reg); |
5b7d70c6 | 1183 | |
8b9bc460 LM |
1184 | /* |
1185 | * set these, it seems that DMA support increments past the end | |
5b7d70c6 | 1186 | * of the packet buffer so we need to calculate the length from |
8b9bc460 LM |
1187 | * this information. |
1188 | */ | |
5b7d70c6 BD |
1189 | hs_ep->size_loaded = length; |
1190 | hs_ep->last_load = ureq->actual; | |
1191 | ||
1192 | if (dir_in && !using_dma(hsotg)) { | |
1193 | /* set these anyway, we may need them for non-periodic in */ | |
1194 | hs_ep->fifo_load = 0; | |
1195 | ||
1f91b4cc | 1196 | dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req); |
5b7d70c6 BD |
1197 | } |
1198 | ||
8b9bc460 LM |
1199 | /* |
1200 | * Note, trying to clear the NAK here causes problems with transmit | |
1201 | * on the S3C6400 ending up with the TXFIFO becoming full. | |
1202 | */ | |
5b7d70c6 BD |
1203 | |
1204 | /* check ep is enabled */ | |
f25c42b8 | 1205 | if (!(dwc2_readl(hsotg, epctrl_reg) & DXEPCTL_EPENA)) |
1a0ed863 | 1206 | dev_dbg(hsotg->dev, |
9da51974 | 1207 | "ep%d: failed to become enabled (DXEPCTL=0x%08x)?\n", |
f25c42b8 | 1208 | index, dwc2_readl(hsotg, epctrl_reg)); |
5b7d70c6 | 1209 | |
47a1685f | 1210 | dev_dbg(hsotg->dev, "%s: DXEPCTL=0x%08x\n", |
f25c42b8 | 1211 | __func__, dwc2_readl(hsotg, epctrl_reg)); |
afcf4169 RB |
1212 | |
1213 | /* enable ep interrupts */ | |
1f91b4cc | 1214 | dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 1); |
5b7d70c6 BD |
1215 | } |
1216 | ||
1217 | /** | |
1f91b4cc | 1218 | * dwc2_hsotg_map_dma - map the DMA memory being used for the request |
5b7d70c6 BD |
1219 | * @hsotg: The device state. |
1220 | * @hs_ep: The endpoint the request is on. | |
1221 | * @req: The request being processed. | |
1222 | * | |
1223 | * We've been asked to queue a request, so ensure that the memory buffer | |
1224 | * is correctly setup for DMA. If we've been passed an extant DMA address | |
1225 | * then ensure the buffer has been synced to memory. If our buffer has no | |
1226 | * DMA memory, then we map the memory and mark our request to allow us to | |
1227 | * cleanup on completion. | |
8b9bc460 | 1228 | */ |
1f91b4cc | 1229 | static int dwc2_hsotg_map_dma(struct dwc2_hsotg *hsotg, |
9da51974 | 1230 | struct dwc2_hsotg_ep *hs_ep, |
5b7d70c6 BD |
1231 | struct usb_request *req) |
1232 | { | |
e58ebcd1 | 1233 | int ret; |
5b7d70c6 | 1234 | |
e58ebcd1 FB |
1235 | ret = usb_gadget_map_request(&hsotg->gadget, req, hs_ep->dir_in); |
1236 | if (ret) | |
1237 | goto dma_error; | |
5b7d70c6 BD |
1238 | |
1239 | return 0; | |
1240 | ||
1241 | dma_error: | |
1242 | dev_err(hsotg->dev, "%s: failed to map buffer %p, %d bytes\n", | |
1243 | __func__, req->buf, req->length); | |
1244 | ||
1245 | return -EIO; | |
1246 | } | |
1247 | ||
1f91b4cc | 1248 | static int dwc2_hsotg_handle_unaligned_buf_start(struct dwc2_hsotg *hsotg, |
b98866c2 JY |
1249 | struct dwc2_hsotg_ep *hs_ep, |
1250 | struct dwc2_hsotg_req *hs_req) | |
7d24c1b5 MYK |
1251 | { |
1252 | void *req_buf = hs_req->req.buf; | |
1253 | ||
1254 | /* If dma is not being used or buffer is aligned */ | |
1255 | if (!using_dma(hsotg) || !((long)req_buf & 3)) | |
1256 | return 0; | |
1257 | ||
1258 | WARN_ON(hs_req->saved_req_buf); | |
1259 | ||
1260 | dev_dbg(hsotg->dev, "%s: %s: buf=%p length=%d\n", __func__, | |
9da51974 | 1261 | hs_ep->ep.name, req_buf, hs_req->req.length); |
7d24c1b5 MYK |
1262 | |
1263 | hs_req->req.buf = kmalloc(hs_req->req.length, GFP_ATOMIC); | |
1264 | if (!hs_req->req.buf) { | |
1265 | hs_req->req.buf = req_buf; | |
1266 | dev_err(hsotg->dev, | |
1267 | "%s: unable to allocate memory for bounce buffer\n", | |
1268 | __func__); | |
1269 | return -ENOMEM; | |
1270 | } | |
1271 | ||
1272 | /* Save actual buffer */ | |
1273 | hs_req->saved_req_buf = req_buf; | |
1274 | ||
1275 | if (hs_ep->dir_in) | |
1276 | memcpy(hs_req->req.buf, req_buf, hs_req->req.length); | |
1277 | return 0; | |
1278 | } | |
1279 | ||
b98866c2 JY |
1280 | static void |
1281 | dwc2_hsotg_handle_unaligned_buf_complete(struct dwc2_hsotg *hsotg, | |
1282 | struct dwc2_hsotg_ep *hs_ep, | |
1283 | struct dwc2_hsotg_req *hs_req) | |
7d24c1b5 MYK |
1284 | { |
1285 | /* If dma is not being used or buffer was aligned */ | |
1286 | if (!using_dma(hsotg) || !hs_req->saved_req_buf) | |
1287 | return; | |
1288 | ||
1289 | dev_dbg(hsotg->dev, "%s: %s: status=%d actual-length=%d\n", __func__, | |
1290 | hs_ep->ep.name, hs_req->req.status, hs_req->req.actual); | |
1291 | ||
1292 | /* Copy data from bounce buffer on successful out transfer */ | |
1293 | if (!hs_ep->dir_in && !hs_req->req.status) | |
1294 | memcpy(hs_req->saved_req_buf, hs_req->req.buf, | |
9da51974 | 1295 | hs_req->req.actual); |
7d24c1b5 MYK |
1296 | |
1297 | /* Free bounce buffer */ | |
1298 | kfree(hs_req->req.buf); | |
1299 | ||
1300 | hs_req->req.buf = hs_req->saved_req_buf; | |
1301 | hs_req->saved_req_buf = NULL; | |
1302 | } | |
1303 | ||
381fc8f8 VM |
1304 | /** |
1305 | * dwc2_gadget_target_frame_elapsed - Checks target frame | |
1306 | * @hs_ep: The driver endpoint to check | |
1307 | * | |
1308 | * Returns 1 if targeted frame elapsed. If returned 1 then we need to drop | |
1309 | * corresponding transfer. | |
1310 | */ | |
1311 | static bool dwc2_gadget_target_frame_elapsed(struct dwc2_hsotg_ep *hs_ep) | |
1312 | { | |
1313 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
1314 | u32 target_frame = hs_ep->target_frame; | |
c7c24e7a | 1315 | u32 current_frame = hsotg->frame_number; |
381fc8f8 VM |
1316 | bool frame_overrun = hs_ep->frame_overrun; |
1317 | ||
1318 | if (!frame_overrun && current_frame >= target_frame) | |
1319 | return true; | |
1320 | ||
1321 | if (frame_overrun && current_frame >= target_frame && | |
1322 | ((current_frame - target_frame) < DSTS_SOFFN_LIMIT / 2)) | |
1323 | return true; | |
1324 | ||
1325 | return false; | |
1326 | } | |
1327 | ||
e02f9aa6 VA |
1328 | /* |
1329 | * dwc2_gadget_set_ep0_desc_chain - Set EP's desc chain pointers | |
1330 | * @hsotg: The driver state | |
1331 | * @hs_ep: the ep descriptor chain is for | |
1332 | * | |
1333 | * Called to update EP0 structure's pointers depend on stage of | |
1334 | * control transfer. | |
1335 | */ | |
1336 | static int dwc2_gadget_set_ep0_desc_chain(struct dwc2_hsotg *hsotg, | |
1337 | struct dwc2_hsotg_ep *hs_ep) | |
1338 | { | |
1339 | switch (hsotg->ep0_state) { | |
1340 | case DWC2_EP0_SETUP: | |
1341 | case DWC2_EP0_STATUS_OUT: | |
1342 | hs_ep->desc_list = hsotg->setup_desc[0]; | |
1343 | hs_ep->desc_list_dma = hsotg->setup_desc_dma[0]; | |
1344 | break; | |
1345 | case DWC2_EP0_DATA_IN: | |
1346 | case DWC2_EP0_STATUS_IN: | |
1347 | hs_ep->desc_list = hsotg->ctrl_in_desc; | |
1348 | hs_ep->desc_list_dma = hsotg->ctrl_in_desc_dma; | |
1349 | break; | |
1350 | case DWC2_EP0_DATA_OUT: | |
1351 | hs_ep->desc_list = hsotg->ctrl_out_desc; | |
1352 | hs_ep->desc_list_dma = hsotg->ctrl_out_desc_dma; | |
1353 | break; | |
1354 | default: | |
1355 | dev_err(hsotg->dev, "invalid EP 0 state in queue %d\n", | |
1356 | hsotg->ep0_state); | |
1357 | return -EINVAL; | |
1358 | } | |
1359 | ||
1360 | return 0; | |
1361 | } | |
1362 | ||
1f91b4cc | 1363 | static int dwc2_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req, |
9da51974 | 1364 | gfp_t gfp_flags) |
5b7d70c6 | 1365 | { |
1f91b4cc FB |
1366 | struct dwc2_hsotg_req *hs_req = our_req(req); |
1367 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); | |
941fcce4 | 1368 | struct dwc2_hsotg *hs = hs_ep->parent; |
5b7d70c6 | 1369 | bool first; |
7d24c1b5 | 1370 | int ret; |
729cac69 MH |
1371 | u32 maxsize = 0; |
1372 | u32 mask = 0; | |
1373 | ||
5b7d70c6 BD |
1374 | |
1375 | dev_dbg(hs->dev, "%s: req %p: %d@%p, noi=%d, zero=%d, snok=%d\n", | |
1376 | ep->name, req, req->length, req->buf, req->no_interrupt, | |
1377 | req->zero, req->short_not_ok); | |
1378 | ||
7ababa92 | 1379 | /* Prevent new request submission when controller is suspended */ |
88b02f2c GT |
1380 | if (hs->lx_state != DWC2_L0) { |
1381 | dev_dbg(hs->dev, "%s: submit request only in active state\n", | |
9da51974 | 1382 | __func__); |
7ababa92 GH |
1383 | return -EAGAIN; |
1384 | } | |
1385 | ||
5b7d70c6 BD |
1386 | /* initialise status of the request */ |
1387 | INIT_LIST_HEAD(&hs_req->queue); | |
1388 | req->actual = 0; | |
1389 | req->status = -EINPROGRESS; | |
1390 | ||
729cac69 MH |
1391 | /* In DDMA mode for ISOC's don't queue request if length greater |
1392 | * than descriptor limits. | |
1393 | */ | |
1394 | if (using_desc_dma(hs) && hs_ep->isochronous) { | |
1395 | maxsize = dwc2_gadget_get_desc_params(hs_ep, &mask); | |
1396 | if (hs_ep->dir_in && req->length > maxsize) { | |
1397 | dev_err(hs->dev, "wrong length %d (maxsize=%d)\n", | |
1398 | req->length, maxsize); | |
1399 | return -EINVAL; | |
1400 | } | |
1401 | ||
1402 | if (!hs_ep->dir_in && req->length > hs_ep->ep.maxpacket) { | |
1403 | dev_err(hs->dev, "ISOC OUT: wrong length %d (mps=%d)\n", | |
1404 | req->length, hs_ep->ep.maxpacket); | |
1405 | return -EINVAL; | |
1406 | } | |
1407 | } | |
1408 | ||
1f91b4cc | 1409 | ret = dwc2_hsotg_handle_unaligned_buf_start(hs, hs_ep, hs_req); |
7d24c1b5 MYK |
1410 | if (ret) |
1411 | return ret; | |
1412 | ||
5b7d70c6 BD |
1413 | /* if we're using DMA, sync the buffers as necessary */ |
1414 | if (using_dma(hs)) { | |
1f91b4cc | 1415 | ret = dwc2_hsotg_map_dma(hs, hs_ep, req); |
5b7d70c6 BD |
1416 | if (ret) |
1417 | return ret; | |
1418 | } | |
e02f9aa6 VA |
1419 | /* If using descriptor DMA configure EP0 descriptor chain pointers */ |
1420 | if (using_desc_dma(hs) && !hs_ep->index) { | |
1421 | ret = dwc2_gadget_set_ep0_desc_chain(hs, hs_ep); | |
1422 | if (ret) | |
1423 | return ret; | |
1424 | } | |
5b7d70c6 | 1425 | |
5b7d70c6 BD |
1426 | first = list_empty(&hs_ep->queue); |
1427 | list_add_tail(&hs_req->queue, &hs_ep->queue); | |
1428 | ||
540ccba0 VA |
1429 | /* |
1430 | * Handle DDMA isochronous transfers separately - just add new entry | |
729cac69 | 1431 | * to the descriptor chain. |
540ccba0 VA |
1432 | * Transfer will be started once SW gets either one of NAK or |
1433 | * OutTknEpDis interrupts. | |
1434 | */ | |
729cac69 MH |
1435 | if (using_desc_dma(hs) && hs_ep->isochronous) { |
1436 | if (hs_ep->target_frame != TARGET_FRAME_INITIAL) { | |
10209abe AP |
1437 | dma_addr_t dma_addr = hs_req->req.dma; |
1438 | ||
1439 | if (hs_req->req.num_sgs) { | |
1440 | WARN_ON(hs_req->req.num_sgs > 1); | |
1441 | dma_addr = sg_dma_address(hs_req->req.sg); | |
1442 | } | |
1443 | dwc2_gadget_fill_isoc_desc(hs_ep, dma_addr, | |
729cac69 MH |
1444 | hs_req->req.length); |
1445 | } | |
540ccba0 VA |
1446 | return 0; |
1447 | } | |
1448 | ||
837e9f00 VM |
1449 | if (first) { |
1450 | if (!hs_ep->isochronous) { | |
1451 | dwc2_hsotg_start_req(hs, hs_ep, hs_req, false); | |
1452 | return 0; | |
1453 | } | |
1454 | ||
c7c24e7a AP |
1455 | /* Update current frame number value. */ |
1456 | hs->frame_number = dwc2_hsotg_read_frameno(hs); | |
1457 | while (dwc2_gadget_target_frame_elapsed(hs_ep)) { | |
837e9f00 | 1458 | dwc2_gadget_incr_frame_num(hs_ep); |
c7c24e7a AP |
1459 | /* Update current frame number value once more as it |
1460 | * changes here. | |
1461 | */ | |
1462 | hs->frame_number = dwc2_hsotg_read_frameno(hs); | |
1463 | } | |
5b7d70c6 | 1464 | |
837e9f00 VM |
1465 | if (hs_ep->target_frame != TARGET_FRAME_INITIAL) |
1466 | dwc2_hsotg_start_req(hs, hs_ep, hs_req, false); | |
1467 | } | |
5b7d70c6 BD |
1468 | return 0; |
1469 | } | |
1470 | ||
1f91b4cc | 1471 | static int dwc2_hsotg_ep_queue_lock(struct usb_ep *ep, struct usb_request *req, |
9da51974 | 1472 | gfp_t gfp_flags) |
5ad1d316 | 1473 | { |
1f91b4cc | 1474 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 1475 | struct dwc2_hsotg *hs = hs_ep->parent; |
5ad1d316 LM |
1476 | unsigned long flags = 0; |
1477 | int ret = 0; | |
1478 | ||
1479 | spin_lock_irqsave(&hs->lock, flags); | |
1f91b4cc | 1480 | ret = dwc2_hsotg_ep_queue(ep, req, gfp_flags); |
5ad1d316 LM |
1481 | spin_unlock_irqrestore(&hs->lock, flags); |
1482 | ||
1483 | return ret; | |
1484 | } | |
1485 | ||
1f91b4cc | 1486 | static void dwc2_hsotg_ep_free_request(struct usb_ep *ep, |
9da51974 | 1487 | struct usb_request *req) |
5b7d70c6 | 1488 | { |
1f91b4cc | 1489 | struct dwc2_hsotg_req *hs_req = our_req(req); |
5b7d70c6 BD |
1490 | |
1491 | kfree(hs_req); | |
1492 | } | |
1493 | ||
1494 | /** | |
1f91b4cc | 1495 | * dwc2_hsotg_complete_oursetup - setup completion callback |
5b7d70c6 BD |
1496 | * @ep: The endpoint the request was on. |
1497 | * @req: The request completed. | |
1498 | * | |
1499 | * Called on completion of any requests the driver itself | |
1500 | * submitted that need cleaning up. | |
1501 | */ | |
1f91b4cc | 1502 | static void dwc2_hsotg_complete_oursetup(struct usb_ep *ep, |
9da51974 | 1503 | struct usb_request *req) |
5b7d70c6 | 1504 | { |
1f91b4cc | 1505 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 1506 | struct dwc2_hsotg *hsotg = hs_ep->parent; |
5b7d70c6 BD |
1507 | |
1508 | dev_dbg(hsotg->dev, "%s: ep %p, req %p\n", __func__, ep, req); | |
1509 | ||
1f91b4cc | 1510 | dwc2_hsotg_ep_free_request(ep, req); |
5b7d70c6 BD |
1511 | } |
1512 | ||
1513 | /** | |
1514 | * ep_from_windex - convert control wIndex value to endpoint | |
1515 | * @hsotg: The driver state. | |
1516 | * @windex: The control request wIndex field (in host order). | |
1517 | * | |
1518 | * Convert the given wIndex into a pointer to an driver endpoint | |
1519 | * structure, or return NULL if it is not a valid endpoint. | |
8b9bc460 | 1520 | */ |
1f91b4cc | 1521 | static struct dwc2_hsotg_ep *ep_from_windex(struct dwc2_hsotg *hsotg, |
9da51974 | 1522 | u32 windex) |
5b7d70c6 | 1523 | { |
1f91b4cc | 1524 | struct dwc2_hsotg_ep *ep; |
5b7d70c6 BD |
1525 | int dir = (windex & USB_DIR_IN) ? 1 : 0; |
1526 | int idx = windex & 0x7F; | |
1527 | ||
1528 | if (windex >= 0x100) | |
1529 | return NULL; | |
1530 | ||
b3f489b2 | 1531 | if (idx > hsotg->num_of_eps) |
5b7d70c6 BD |
1532 | return NULL; |
1533 | ||
c6f5c050 MYK |
1534 | ep = index_to_ep(hsotg, idx, dir); |
1535 | ||
5b7d70c6 BD |
1536 | if (idx && ep->dir_in != dir) |
1537 | return NULL; | |
1538 | ||
1539 | return ep; | |
1540 | } | |
1541 | ||
9e14d0a5 | 1542 | /** |
1f91b4cc | 1543 | * dwc2_hsotg_set_test_mode - Enable usb Test Modes |
9e14d0a5 GH |
1544 | * @hsotg: The driver state. |
1545 | * @testmode: requested usb test mode | |
1546 | * Enable usb Test Mode requested by the Host. | |
1547 | */ | |
1f91b4cc | 1548 | int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode) |
9e14d0a5 | 1549 | { |
f25c42b8 | 1550 | int dctl = dwc2_readl(hsotg, DCTL); |
9e14d0a5 GH |
1551 | |
1552 | dctl &= ~DCTL_TSTCTL_MASK; | |
1553 | switch (testmode) { | |
1554 | case TEST_J: | |
1555 | case TEST_K: | |
1556 | case TEST_SE0_NAK: | |
1557 | case TEST_PACKET: | |
1558 | case TEST_FORCE_EN: | |
1559 | dctl |= testmode << DCTL_TSTCTL_SHIFT; | |
1560 | break; | |
1561 | default: | |
1562 | return -EINVAL; | |
1563 | } | |
f25c42b8 | 1564 | dwc2_writel(hsotg, dctl, DCTL); |
9e14d0a5 GH |
1565 | return 0; |
1566 | } | |
1567 | ||
5b7d70c6 | 1568 | /** |
1f91b4cc | 1569 | * dwc2_hsotg_send_reply - send reply to control request |
5b7d70c6 BD |
1570 | * @hsotg: The device state |
1571 | * @ep: Endpoint 0 | |
1572 | * @buff: Buffer for request | |
1573 | * @length: Length of reply. | |
1574 | * | |
1575 | * Create a request and queue it on the given endpoint. This is useful as | |
1576 | * an internal method of sending replies to certain control requests, etc. | |
1577 | */ | |
1f91b4cc | 1578 | static int dwc2_hsotg_send_reply(struct dwc2_hsotg *hsotg, |
9da51974 | 1579 | struct dwc2_hsotg_ep *ep, |
5b7d70c6 BD |
1580 | void *buff, |
1581 | int length) | |
1582 | { | |
1583 | struct usb_request *req; | |
1584 | int ret; | |
1585 | ||
1586 | dev_dbg(hsotg->dev, "%s: buff %p, len %d\n", __func__, buff, length); | |
1587 | ||
1f91b4cc | 1588 | req = dwc2_hsotg_ep_alloc_request(&ep->ep, GFP_ATOMIC); |
5b7d70c6 BD |
1589 | hsotg->ep0_reply = req; |
1590 | if (!req) { | |
1591 | dev_warn(hsotg->dev, "%s: cannot alloc req\n", __func__); | |
1592 | return -ENOMEM; | |
1593 | } | |
1594 | ||
1595 | req->buf = hsotg->ep0_buff; | |
1596 | req->length = length; | |
f71b5e25 MYK |
1597 | /* |
1598 | * zero flag is for sending zlp in DATA IN stage. It has no impact on | |
1599 | * STATUS stage. | |
1600 | */ | |
1601 | req->zero = 0; | |
1f91b4cc | 1602 | req->complete = dwc2_hsotg_complete_oursetup; |
5b7d70c6 BD |
1603 | |
1604 | if (length) | |
1605 | memcpy(req->buf, buff, length); | |
5b7d70c6 | 1606 | |
1f91b4cc | 1607 | ret = dwc2_hsotg_ep_queue(&ep->ep, req, GFP_ATOMIC); |
5b7d70c6 BD |
1608 | if (ret) { |
1609 | dev_warn(hsotg->dev, "%s: cannot queue req\n", __func__); | |
1610 | return ret; | |
1611 | } | |
1612 | ||
1613 | return 0; | |
1614 | } | |
1615 | ||
1616 | /** | |
1f91b4cc | 1617 | * dwc2_hsotg_process_req_status - process request GET_STATUS |
5b7d70c6 BD |
1618 | * @hsotg: The device state |
1619 | * @ctrl: USB control request | |
1620 | */ | |
1f91b4cc | 1621 | static int dwc2_hsotg_process_req_status(struct dwc2_hsotg *hsotg, |
9da51974 | 1622 | struct usb_ctrlrequest *ctrl) |
5b7d70c6 | 1623 | { |
1f91b4cc FB |
1624 | struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0]; |
1625 | struct dwc2_hsotg_ep *ep; | |
5b7d70c6 BD |
1626 | __le16 reply; |
1627 | int ret; | |
1628 | ||
1629 | dev_dbg(hsotg->dev, "%s: USB_REQ_GET_STATUS\n", __func__); | |
1630 | ||
1631 | if (!ep0->dir_in) { | |
1632 | dev_warn(hsotg->dev, "%s: direction out?\n", __func__); | |
1633 | return -EINVAL; | |
1634 | } | |
1635 | ||
1636 | switch (ctrl->bRequestType & USB_RECIP_MASK) { | |
1637 | case USB_RECIP_DEVICE: | |
38beaec6 JY |
1638 | /* |
1639 | * bit 0 => self powered | |
1640 | * bit 1 => remote wakeup | |
1641 | */ | |
1642 | reply = cpu_to_le16(0); | |
5b7d70c6 BD |
1643 | break; |
1644 | ||
1645 | case USB_RECIP_INTERFACE: | |
1646 | /* currently, the data result should be zero */ | |
1647 | reply = cpu_to_le16(0); | |
1648 | break; | |
1649 | ||
1650 | case USB_RECIP_ENDPOINT: | |
1651 | ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex)); | |
1652 | if (!ep) | |
1653 | return -ENOENT; | |
1654 | ||
1655 | reply = cpu_to_le16(ep->halted ? 1 : 0); | |
1656 | break; | |
1657 | ||
1658 | default: | |
1659 | return 0; | |
1660 | } | |
1661 | ||
1662 | if (le16_to_cpu(ctrl->wLength) != 2) | |
1663 | return -EINVAL; | |
1664 | ||
1f91b4cc | 1665 | ret = dwc2_hsotg_send_reply(hsotg, ep0, &reply, 2); |
5b7d70c6 BD |
1666 | if (ret) { |
1667 | dev_err(hsotg->dev, "%s: failed to send reply\n", __func__); | |
1668 | return ret; | |
1669 | } | |
1670 | ||
1671 | return 1; | |
1672 | } | |
1673 | ||
51da43b5 | 1674 | static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now); |
5b7d70c6 | 1675 | |
9c39ddc6 AT |
1676 | /** |
1677 | * get_ep_head - return the first request on the endpoint | |
1678 | * @hs_ep: The controller endpoint to get | |
1679 | * | |
1680 | * Get the first request on the endpoint. | |
1681 | */ | |
1f91b4cc | 1682 | static struct dwc2_hsotg_req *get_ep_head(struct dwc2_hsotg_ep *hs_ep) |
9c39ddc6 | 1683 | { |
ffc4b406 MY |
1684 | return list_first_entry_or_null(&hs_ep->queue, struct dwc2_hsotg_req, |
1685 | queue); | |
9c39ddc6 AT |
1686 | } |
1687 | ||
41cc4cd2 VM |
1688 | /** |
1689 | * dwc2_gadget_start_next_request - Starts next request from ep queue | |
1690 | * @hs_ep: Endpoint structure | |
1691 | * | |
1692 | * If queue is empty and EP is ISOC-OUT - unmasks OUTTKNEPDIS which is masked | |
1693 | * in its handler. Hence we need to unmask it here to be able to do | |
1694 | * resynchronization. | |
1695 | */ | |
1696 | static void dwc2_gadget_start_next_request(struct dwc2_hsotg_ep *hs_ep) | |
1697 | { | |
1698 | u32 mask; | |
1699 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
1700 | int dir_in = hs_ep->dir_in; | |
1701 | struct dwc2_hsotg_req *hs_req; | |
1702 | u32 epmsk_reg = dir_in ? DIEPMSK : DOEPMSK; | |
1703 | ||
1704 | if (!list_empty(&hs_ep->queue)) { | |
1705 | hs_req = get_ep_head(hs_ep); | |
1706 | dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, false); | |
1707 | return; | |
1708 | } | |
1709 | if (!hs_ep->isochronous) | |
1710 | return; | |
1711 | ||
1712 | if (dir_in) { | |
1713 | dev_dbg(hsotg->dev, "%s: No more ISOC-IN requests\n", | |
1714 | __func__); | |
1715 | } else { | |
1716 | dev_dbg(hsotg->dev, "%s: No more ISOC-OUT requests\n", | |
1717 | __func__); | |
f25c42b8 | 1718 | mask = dwc2_readl(hsotg, epmsk_reg); |
41cc4cd2 | 1719 | mask |= DOEPMSK_OUTTKNEPDISMSK; |
f25c42b8 | 1720 | dwc2_writel(hsotg, mask, epmsk_reg); |
41cc4cd2 VM |
1721 | } |
1722 | } | |
1723 | ||
5b7d70c6 | 1724 | /** |
1f91b4cc | 1725 | * dwc2_hsotg_process_req_feature - process request {SET,CLEAR}_FEATURE |
5b7d70c6 BD |
1726 | * @hsotg: The device state |
1727 | * @ctrl: USB control request | |
1728 | */ | |
1f91b4cc | 1729 | static int dwc2_hsotg_process_req_feature(struct dwc2_hsotg *hsotg, |
9da51974 | 1730 | struct usb_ctrlrequest *ctrl) |
5b7d70c6 | 1731 | { |
1f91b4cc FB |
1732 | struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0]; |
1733 | struct dwc2_hsotg_req *hs_req; | |
5b7d70c6 | 1734 | bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE); |
1f91b4cc | 1735 | struct dwc2_hsotg_ep *ep; |
26ab3d0c | 1736 | int ret; |
bd9ef7bf | 1737 | bool halted; |
9e14d0a5 GH |
1738 | u32 recip; |
1739 | u32 wValue; | |
1740 | u32 wIndex; | |
5b7d70c6 BD |
1741 | |
1742 | dev_dbg(hsotg->dev, "%s: %s_FEATURE\n", | |
1743 | __func__, set ? "SET" : "CLEAR"); | |
1744 | ||
9e14d0a5 GH |
1745 | wValue = le16_to_cpu(ctrl->wValue); |
1746 | wIndex = le16_to_cpu(ctrl->wIndex); | |
1747 | recip = ctrl->bRequestType & USB_RECIP_MASK; | |
1748 | ||
1749 | switch (recip) { | |
1750 | case USB_RECIP_DEVICE: | |
1751 | switch (wValue) { | |
fa389a6d VM |
1752 | case USB_DEVICE_REMOTE_WAKEUP: |
1753 | hsotg->remote_wakeup_allowed = 1; | |
1754 | break; | |
1755 | ||
9e14d0a5 GH |
1756 | case USB_DEVICE_TEST_MODE: |
1757 | if ((wIndex & 0xff) != 0) | |
1758 | return -EINVAL; | |
1759 | if (!set) | |
1760 | return -EINVAL; | |
1761 | ||
1762 | hsotg->test_mode = wIndex >> 8; | |
1f91b4cc | 1763 | ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0); |
9e14d0a5 GH |
1764 | if (ret) { |
1765 | dev_err(hsotg->dev, | |
1766 | "%s: failed to send reply\n", __func__); | |
1767 | return ret; | |
1768 | } | |
1769 | break; | |
1770 | default: | |
1771 | return -ENOENT; | |
1772 | } | |
1773 | break; | |
1774 | ||
1775 | case USB_RECIP_ENDPOINT: | |
1776 | ep = ep_from_windex(hsotg, wIndex); | |
5b7d70c6 BD |
1777 | if (!ep) { |
1778 | dev_dbg(hsotg->dev, "%s: no endpoint for 0x%04x\n", | |
9e14d0a5 | 1779 | __func__, wIndex); |
5b7d70c6 BD |
1780 | return -ENOENT; |
1781 | } | |
1782 | ||
9e14d0a5 | 1783 | switch (wValue) { |
5b7d70c6 | 1784 | case USB_ENDPOINT_HALT: |
bd9ef7bf RB |
1785 | halted = ep->halted; |
1786 | ||
51da43b5 | 1787 | dwc2_hsotg_ep_sethalt(&ep->ep, set, true); |
26ab3d0c | 1788 | |
1f91b4cc | 1789 | ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0); |
26ab3d0c AT |
1790 | if (ret) { |
1791 | dev_err(hsotg->dev, | |
1792 | "%s: failed to send reply\n", __func__); | |
1793 | return ret; | |
1794 | } | |
9c39ddc6 | 1795 | |
bd9ef7bf RB |
1796 | /* |
1797 | * we have to complete all requests for ep if it was | |
1798 | * halted, and the halt was cleared by CLEAR_FEATURE | |
1799 | */ | |
1800 | ||
1801 | if (!set && halted) { | |
9c39ddc6 AT |
1802 | /* |
1803 | * If we have request in progress, | |
1804 | * then complete it | |
1805 | */ | |
1806 | if (ep->req) { | |
1807 | hs_req = ep->req; | |
1808 | ep->req = NULL; | |
1809 | list_del_init(&hs_req->queue); | |
c00dd4a6 GH |
1810 | if (hs_req->req.complete) { |
1811 | spin_unlock(&hsotg->lock); | |
1812 | usb_gadget_giveback_request( | |
1813 | &ep->ep, &hs_req->req); | |
1814 | spin_lock(&hsotg->lock); | |
1815 | } | |
9c39ddc6 AT |
1816 | } |
1817 | ||
1818 | /* If we have pending request, then start it */ | |
34c0887f | 1819 | if (!ep->req) |
41cc4cd2 | 1820 | dwc2_gadget_start_next_request(ep); |
9c39ddc6 AT |
1821 | } |
1822 | ||
5b7d70c6 BD |
1823 | break; |
1824 | ||
1825 | default: | |
1826 | return -ENOENT; | |
1827 | } | |
9e14d0a5 GH |
1828 | break; |
1829 | default: | |
1830 | return -ENOENT; | |
1831 | } | |
5b7d70c6 BD |
1832 | return 1; |
1833 | } | |
1834 | ||
1f91b4cc | 1835 | static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg); |
ab93e014 | 1836 | |
c9f721b2 | 1837 | /** |
1f91b4cc | 1838 | * dwc2_hsotg_stall_ep0 - stall ep0 |
c9f721b2 RB |
1839 | * @hsotg: The device state |
1840 | * | |
1841 | * Set stall for ep0 as response for setup request. | |
1842 | */ | |
1f91b4cc | 1843 | static void dwc2_hsotg_stall_ep0(struct dwc2_hsotg *hsotg) |
e9ebe7c3 | 1844 | { |
1f91b4cc | 1845 | struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0]; |
c9f721b2 RB |
1846 | u32 reg; |
1847 | u32 ctrl; | |
1848 | ||
1849 | dev_dbg(hsotg->dev, "ep0 stall (dir=%d)\n", ep0->dir_in); | |
1850 | reg = (ep0->dir_in) ? DIEPCTL0 : DOEPCTL0; | |
1851 | ||
1852 | /* | |
1853 | * DxEPCTL_Stall will be cleared by EP once it has | |
1854 | * taken effect, so no need to clear later. | |
1855 | */ | |
1856 | ||
f25c42b8 | 1857 | ctrl = dwc2_readl(hsotg, reg); |
47a1685f DN |
1858 | ctrl |= DXEPCTL_STALL; |
1859 | ctrl |= DXEPCTL_CNAK; | |
f25c42b8 | 1860 | dwc2_writel(hsotg, ctrl, reg); |
c9f721b2 RB |
1861 | |
1862 | dev_dbg(hsotg->dev, | |
47a1685f | 1863 | "written DXEPCTL=0x%08x to %08x (DXEPCTL=0x%08x)\n", |
f25c42b8 | 1864 | ctrl, reg, dwc2_readl(hsotg, reg)); |
c9f721b2 RB |
1865 | |
1866 | /* | |
1867 | * complete won't be called, so we enqueue | |
1868 | * setup request here | |
1869 | */ | |
1f91b4cc | 1870 | dwc2_hsotg_enqueue_setup(hsotg); |
c9f721b2 RB |
1871 | } |
1872 | ||
5b7d70c6 | 1873 | /** |
1f91b4cc | 1874 | * dwc2_hsotg_process_control - process a control request |
5b7d70c6 BD |
1875 | * @hsotg: The device state |
1876 | * @ctrl: The control request received | |
1877 | * | |
1878 | * The controller has received the SETUP phase of a control request, and | |
1879 | * needs to work out what to do next (and whether to pass it on to the | |
1880 | * gadget driver). | |
1881 | */ | |
1f91b4cc | 1882 | static void dwc2_hsotg_process_control(struct dwc2_hsotg *hsotg, |
9da51974 | 1883 | struct usb_ctrlrequest *ctrl) |
5b7d70c6 | 1884 | { |
1f91b4cc | 1885 | struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0]; |
5b7d70c6 BD |
1886 | int ret = 0; |
1887 | u32 dcfg; | |
1888 | ||
e525e743 MYK |
1889 | dev_dbg(hsotg->dev, |
1890 | "ctrl Type=%02x, Req=%02x, V=%04x, I=%04x, L=%04x\n", | |
1891 | ctrl->bRequestType, ctrl->bRequest, ctrl->wValue, | |
1892 | ctrl->wIndex, ctrl->wLength); | |
5b7d70c6 | 1893 | |
fe0b94ab MYK |
1894 | if (ctrl->wLength == 0) { |
1895 | ep0->dir_in = 1; | |
1896 | hsotg->ep0_state = DWC2_EP0_STATUS_IN; | |
1897 | } else if (ctrl->bRequestType & USB_DIR_IN) { | |
5b7d70c6 | 1898 | ep0->dir_in = 1; |
fe0b94ab MYK |
1899 | hsotg->ep0_state = DWC2_EP0_DATA_IN; |
1900 | } else { | |
1901 | ep0->dir_in = 0; | |
1902 | hsotg->ep0_state = DWC2_EP0_DATA_OUT; | |
1903 | } | |
5b7d70c6 BD |
1904 | |
1905 | if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) { | |
1906 | switch (ctrl->bRequest) { | |
1907 | case USB_REQ_SET_ADDRESS: | |
6d713c15 | 1908 | hsotg->connected = 1; |
f25c42b8 | 1909 | dcfg = dwc2_readl(hsotg, DCFG); |
47a1685f | 1910 | dcfg &= ~DCFG_DEVADDR_MASK; |
d5dbd3f7 PZ |
1911 | dcfg |= (le16_to_cpu(ctrl->wValue) << |
1912 | DCFG_DEVADDR_SHIFT) & DCFG_DEVADDR_MASK; | |
f25c42b8 | 1913 | dwc2_writel(hsotg, dcfg, DCFG); |
5b7d70c6 BD |
1914 | |
1915 | dev_info(hsotg->dev, "new address %d\n", ctrl->wValue); | |
1916 | ||
1f91b4cc | 1917 | ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0); |
5b7d70c6 BD |
1918 | return; |
1919 | ||
1920 | case USB_REQ_GET_STATUS: | |
1f91b4cc | 1921 | ret = dwc2_hsotg_process_req_status(hsotg, ctrl); |
5b7d70c6 BD |
1922 | break; |
1923 | ||
1924 | case USB_REQ_CLEAR_FEATURE: | |
1925 | case USB_REQ_SET_FEATURE: | |
1f91b4cc | 1926 | ret = dwc2_hsotg_process_req_feature(hsotg, ctrl); |
5b7d70c6 BD |
1927 | break; |
1928 | } | |
1929 | } | |
1930 | ||
1931 | /* as a fallback, try delivering it to the driver to deal with */ | |
1932 | ||
1933 | if (ret == 0 && hsotg->driver) { | |
93f599f2 | 1934 | spin_unlock(&hsotg->lock); |
5b7d70c6 | 1935 | ret = hsotg->driver->setup(&hsotg->gadget, ctrl); |
93f599f2 | 1936 | spin_lock(&hsotg->lock); |
5b7d70c6 BD |
1937 | if (ret < 0) |
1938 | dev_dbg(hsotg->dev, "driver->setup() ret %d\n", ret); | |
1939 | } | |
1940 | ||
8b9bc460 LM |
1941 | /* |
1942 | * the request is either unhandlable, or is not formatted correctly | |
5b7d70c6 BD |
1943 | * so respond with a STALL for the status stage to indicate failure. |
1944 | */ | |
1945 | ||
c9f721b2 | 1946 | if (ret < 0) |
1f91b4cc | 1947 | dwc2_hsotg_stall_ep0(hsotg); |
5b7d70c6 BD |
1948 | } |
1949 | ||
5b7d70c6 | 1950 | /** |
1f91b4cc | 1951 | * dwc2_hsotg_complete_setup - completion of a setup transfer |
5b7d70c6 BD |
1952 | * @ep: The endpoint the request was on. |
1953 | * @req: The request completed. | |
1954 | * | |
1955 | * Called on completion of any requests the driver itself submitted for | |
1956 | * EP0 setup packets | |
1957 | */ | |
1f91b4cc | 1958 | static void dwc2_hsotg_complete_setup(struct usb_ep *ep, |
9da51974 | 1959 | struct usb_request *req) |
5b7d70c6 | 1960 | { |
1f91b4cc | 1961 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 1962 | struct dwc2_hsotg *hsotg = hs_ep->parent; |
5b7d70c6 BD |
1963 | |
1964 | if (req->status < 0) { | |
1965 | dev_dbg(hsotg->dev, "%s: failed %d\n", __func__, req->status); | |
1966 | return; | |
1967 | } | |
1968 | ||
93f599f2 | 1969 | spin_lock(&hsotg->lock); |
5b7d70c6 | 1970 | if (req->actual == 0) |
1f91b4cc | 1971 | dwc2_hsotg_enqueue_setup(hsotg); |
5b7d70c6 | 1972 | else |
1f91b4cc | 1973 | dwc2_hsotg_process_control(hsotg, req->buf); |
93f599f2 | 1974 | spin_unlock(&hsotg->lock); |
5b7d70c6 BD |
1975 | } |
1976 | ||
1977 | /** | |
1f91b4cc | 1978 | * dwc2_hsotg_enqueue_setup - start a request for EP0 packets |
5b7d70c6 BD |
1979 | * @hsotg: The device state. |
1980 | * | |
1981 | * Enqueue a request on EP0 if necessary to received any SETUP packets | |
1982 | * received from the host. | |
1983 | */ | |
1f91b4cc | 1984 | static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg) |
5b7d70c6 BD |
1985 | { |
1986 | struct usb_request *req = hsotg->ctrl_req; | |
1f91b4cc | 1987 | struct dwc2_hsotg_req *hs_req = our_req(req); |
5b7d70c6 BD |
1988 | int ret; |
1989 | ||
1990 | dev_dbg(hsotg->dev, "%s: queueing setup request\n", __func__); | |
1991 | ||
1992 | req->zero = 0; | |
1993 | req->length = 8; | |
1994 | req->buf = hsotg->ctrl_buff; | |
1f91b4cc | 1995 | req->complete = dwc2_hsotg_complete_setup; |
5b7d70c6 BD |
1996 | |
1997 | if (!list_empty(&hs_req->queue)) { | |
1998 | dev_dbg(hsotg->dev, "%s already queued???\n", __func__); | |
1999 | return; | |
2000 | } | |
2001 | ||
c6f5c050 | 2002 | hsotg->eps_out[0]->dir_in = 0; |
8a20fa45 | 2003 | hsotg->eps_out[0]->send_zlp = 0; |
fe0b94ab | 2004 | hsotg->ep0_state = DWC2_EP0_SETUP; |
5b7d70c6 | 2005 | |
1f91b4cc | 2006 | ret = dwc2_hsotg_ep_queue(&hsotg->eps_out[0]->ep, req, GFP_ATOMIC); |
5b7d70c6 BD |
2007 | if (ret < 0) { |
2008 | dev_err(hsotg->dev, "%s: failed queue (%d)\n", __func__, ret); | |
8b9bc460 LM |
2009 | /* |
2010 | * Don't think there's much we can do other than watch the | |
2011 | * driver fail. | |
2012 | */ | |
5b7d70c6 BD |
2013 | } |
2014 | } | |
2015 | ||
1f91b4cc | 2016 | static void dwc2_hsotg_program_zlp(struct dwc2_hsotg *hsotg, |
9da51974 | 2017 | struct dwc2_hsotg_ep *hs_ep) |
fe0b94ab MYK |
2018 | { |
2019 | u32 ctrl; | |
2020 | u8 index = hs_ep->index; | |
2021 | u32 epctl_reg = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index); | |
2022 | u32 epsiz_reg = hs_ep->dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index); | |
2023 | ||
ccb34a91 MYK |
2024 | if (hs_ep->dir_in) |
2025 | dev_dbg(hsotg->dev, "Sending zero-length packet on ep%d\n", | |
e02f9aa6 | 2026 | index); |
ccb34a91 MYK |
2027 | else |
2028 | dev_dbg(hsotg->dev, "Receiving zero-length packet on ep%d\n", | |
e02f9aa6 VA |
2029 | index); |
2030 | if (using_desc_dma(hsotg)) { | |
201ec568 MH |
2031 | if (!index) |
2032 | dwc2_gadget_set_ep0_desc_chain(hsotg, hs_ep); | |
2033 | ||
10209abe AP |
2034 | /* Not specific buffer needed for ep0 ZLP */ |
2035 | dwc2_gadget_fill_nonisoc_xfer_ddma_one(hs_ep, &hs_ep->desc_list, | |
2036 | hs_ep->desc_list_dma, 0, true); | |
e02f9aa6 | 2037 | } else { |
f25c42b8 GS |
2038 | dwc2_writel(hsotg, DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) | |
2039 | DXEPTSIZ_XFERSIZE(0), | |
e02f9aa6 VA |
2040 | epsiz_reg); |
2041 | } | |
fe0b94ab | 2042 | |
f25c42b8 | 2043 | ctrl = dwc2_readl(hsotg, epctl_reg); |
fe0b94ab MYK |
2044 | ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */ |
2045 | ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */ | |
2046 | ctrl |= DXEPCTL_USBACTEP; | |
f25c42b8 | 2047 | dwc2_writel(hsotg, ctrl, epctl_reg); |
fe0b94ab MYK |
2048 | } |
2049 | ||
5b7d70c6 | 2050 | /** |
1f91b4cc | 2051 | * dwc2_hsotg_complete_request - complete a request given to us |
5b7d70c6 BD |
2052 | * @hsotg: The device state. |
2053 | * @hs_ep: The endpoint the request was on. | |
2054 | * @hs_req: The request to complete. | |
2055 | * @result: The result code (0 => Ok, otherwise errno) | |
2056 | * | |
2057 | * The given request has finished, so call the necessary completion | |
2058 | * if it has one and then look to see if we can start a new request | |
2059 | * on the endpoint. | |
2060 | * | |
2061 | * Note, expects the ep to already be locked as appropriate. | |
8b9bc460 | 2062 | */ |
1f91b4cc | 2063 | static void dwc2_hsotg_complete_request(struct dwc2_hsotg *hsotg, |
9da51974 | 2064 | struct dwc2_hsotg_ep *hs_ep, |
1f91b4cc | 2065 | struct dwc2_hsotg_req *hs_req, |
5b7d70c6 BD |
2066 | int result) |
2067 | { | |
5b7d70c6 BD |
2068 | if (!hs_req) { |
2069 | dev_dbg(hsotg->dev, "%s: nothing to complete?\n", __func__); | |
2070 | return; | |
2071 | } | |
2072 | ||
2073 | dev_dbg(hsotg->dev, "complete: ep %p %s, req %p, %d => %p\n", | |
2074 | hs_ep, hs_ep->ep.name, hs_req, result, hs_req->req.complete); | |
2075 | ||
8b9bc460 LM |
2076 | /* |
2077 | * only replace the status if we've not already set an error | |
2078 | * from a previous transaction | |
2079 | */ | |
5b7d70c6 BD |
2080 | |
2081 | if (hs_req->req.status == -EINPROGRESS) | |
2082 | hs_req->req.status = result; | |
2083 | ||
44583fec YL |
2084 | if (using_dma(hsotg)) |
2085 | dwc2_hsotg_unmap_dma(hsotg, hs_ep, hs_req); | |
2086 | ||
1f91b4cc | 2087 | dwc2_hsotg_handle_unaligned_buf_complete(hsotg, hs_ep, hs_req); |
7d24c1b5 | 2088 | |
5b7d70c6 BD |
2089 | hs_ep->req = NULL; |
2090 | list_del_init(&hs_req->queue); | |
2091 | ||
8b9bc460 LM |
2092 | /* |
2093 | * call the complete request with the locks off, just in case the | |
2094 | * request tries to queue more work for this endpoint. | |
2095 | */ | |
5b7d70c6 BD |
2096 | |
2097 | if (hs_req->req.complete) { | |
22258f49 | 2098 | spin_unlock(&hsotg->lock); |
304f7e5e | 2099 | usb_gadget_giveback_request(&hs_ep->ep, &hs_req->req); |
22258f49 | 2100 | spin_lock(&hsotg->lock); |
5b7d70c6 BD |
2101 | } |
2102 | ||
540ccba0 VA |
2103 | /* In DDMA don't need to proceed to starting of next ISOC request */ |
2104 | if (using_desc_dma(hsotg) && hs_ep->isochronous) | |
2105 | return; | |
2106 | ||
8b9bc460 LM |
2107 | /* |
2108 | * Look to see if there is anything else to do. Note, the completion | |
5b7d70c6 | 2109 | * of the previous request may have caused a new request to be started |
8b9bc460 LM |
2110 | * so be careful when doing this. |
2111 | */ | |
5b7d70c6 | 2112 | |
34c0887f | 2113 | if (!hs_ep->req && result >= 0) |
41cc4cd2 | 2114 | dwc2_gadget_start_next_request(hs_ep); |
5b7d70c6 BD |
2115 | } |
2116 | ||
540ccba0 VA |
2117 | /* |
2118 | * dwc2_gadget_complete_isoc_request_ddma - complete an isoc request in DDMA | |
2119 | * @hs_ep: The endpoint the request was on. | |
2120 | * | |
2121 | * Get first request from the ep queue, determine descriptor on which complete | |
729cac69 MH |
2122 | * happened. SW discovers which descriptor currently in use by HW, adjusts |
2123 | * dma_address and calculates index of completed descriptor based on the value | |
2124 | * of DEPDMA register. Update actual length of request, giveback to gadget. | |
540ccba0 VA |
2125 | */ |
2126 | static void dwc2_gadget_complete_isoc_request_ddma(struct dwc2_hsotg_ep *hs_ep) | |
2127 | { | |
2128 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
2129 | struct dwc2_hsotg_req *hs_req; | |
2130 | struct usb_request *ureq; | |
540ccba0 VA |
2131 | u32 desc_sts; |
2132 | u32 mask; | |
2133 | ||
729cac69 | 2134 | desc_sts = hs_ep->desc_list[hs_ep->compl_desc].status; |
540ccba0 | 2135 | |
729cac69 MH |
2136 | /* Process only descriptors with buffer status set to DMA done */ |
2137 | while ((desc_sts & DEV_DMA_BUFF_STS_MASK) >> | |
2138 | DEV_DMA_BUFF_STS_SHIFT == DEV_DMA_BUFF_STS_DMADONE) { | |
540ccba0 | 2139 | |
729cac69 MH |
2140 | hs_req = get_ep_head(hs_ep); |
2141 | if (!hs_req) { | |
2142 | dev_warn(hsotg->dev, "%s: ISOC EP queue empty\n", __func__); | |
2143 | return; | |
2144 | } | |
2145 | ureq = &hs_req->req; | |
2146 | ||
2147 | /* Check completion status */ | |
2148 | if ((desc_sts & DEV_DMA_STS_MASK) >> DEV_DMA_STS_SHIFT == | |
2149 | DEV_DMA_STS_SUCC) { | |
2150 | mask = hs_ep->dir_in ? DEV_DMA_ISOC_TX_NBYTES_MASK : | |
2151 | DEV_DMA_ISOC_RX_NBYTES_MASK; | |
2152 | ureq->actual = ureq->length - ((desc_sts & mask) >> | |
2153 | DEV_DMA_ISOC_NBYTES_SHIFT); | |
2154 | ||
2155 | /* Adjust actual len for ISOC Out if len is | |
2156 | * not align of 4 | |
2157 | */ | |
2158 | if (!hs_ep->dir_in && ureq->length & 0x3) | |
2159 | ureq->actual += 4 - (ureq->length & 0x3); | |
2160 | } | |
540ccba0 | 2161 | |
729cac69 | 2162 | dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0); |
95d2b037 | 2163 | |
729cac69 MH |
2164 | hs_ep->compl_desc++; |
2165 | if (hs_ep->compl_desc > (MAX_DMA_DESC_NUM_GENERIC - 1)) | |
2166 | hs_ep->compl_desc = 0; | |
2167 | desc_sts = hs_ep->desc_list[hs_ep->compl_desc].status; | |
2168 | } | |
540ccba0 VA |
2169 | } |
2170 | ||
2171 | /* | |
729cac69 MH |
2172 | * dwc2_gadget_handle_isoc_bna - handle BNA interrupt for ISOC. |
2173 | * @hs_ep: The isochronous endpoint. | |
540ccba0 | 2174 | * |
729cac69 MH |
2175 | * If EP ISOC OUT then need to flush RX FIFO to remove source of BNA |
2176 | * interrupt. Reset target frame and next_desc to allow to start | |
2177 | * ISOC's on NAK interrupt for IN direction or on OUTTKNEPDIS | |
2178 | * interrupt for OUT direction. | |
540ccba0 | 2179 | */ |
729cac69 | 2180 | static void dwc2_gadget_handle_isoc_bna(struct dwc2_hsotg_ep *hs_ep) |
540ccba0 VA |
2181 | { |
2182 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
540ccba0 | 2183 | |
729cac69 MH |
2184 | if (!hs_ep->dir_in) |
2185 | dwc2_flush_rx_fifo(hsotg); | |
2186 | dwc2_hsotg_complete_request(hsotg, hs_ep, get_ep_head(hs_ep), 0); | |
540ccba0 | 2187 | |
729cac69 MH |
2188 | hs_ep->target_frame = TARGET_FRAME_INITIAL; |
2189 | hs_ep->next_desc = 0; | |
2190 | hs_ep->compl_desc = 0; | |
540ccba0 VA |
2191 | } |
2192 | ||
5b7d70c6 | 2193 | /** |
1f91b4cc | 2194 | * dwc2_hsotg_rx_data - receive data from the FIFO for an endpoint |
5b7d70c6 BD |
2195 | * @hsotg: The device state. |
2196 | * @ep_idx: The endpoint index for the data | |
2197 | * @size: The size of data in the fifo, in bytes | |
2198 | * | |
2199 | * The FIFO status shows there is data to read from the FIFO for a given | |
2200 | * endpoint, so sort out whether we need to read the data into a request | |
2201 | * that has been made for that endpoint. | |
2202 | */ | |
1f91b4cc | 2203 | static void dwc2_hsotg_rx_data(struct dwc2_hsotg *hsotg, int ep_idx, int size) |
5b7d70c6 | 2204 | { |
1f91b4cc FB |
2205 | struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[ep_idx]; |
2206 | struct dwc2_hsotg_req *hs_req = hs_ep->req; | |
5b7d70c6 BD |
2207 | int to_read; |
2208 | int max_req; | |
2209 | int read_ptr; | |
2210 | ||
2211 | if (!hs_req) { | |
f25c42b8 | 2212 | u32 epctl = dwc2_readl(hsotg, DOEPCTL(ep_idx)); |
5b7d70c6 BD |
2213 | int ptr; |
2214 | ||
6b448af4 | 2215 | dev_dbg(hsotg->dev, |
9da51974 | 2216 | "%s: FIFO %d bytes on ep%d but no req (DXEPCTl=0x%08x)\n", |
5b7d70c6 BD |
2217 | __func__, size, ep_idx, epctl); |
2218 | ||
2219 | /* dump the data from the FIFO, we've nothing we can do */ | |
2220 | for (ptr = 0; ptr < size; ptr += 4) | |
f25c42b8 | 2221 | (void)dwc2_readl(hsotg, EPFIFO(ep_idx)); |
5b7d70c6 BD |
2222 | |
2223 | return; | |
2224 | } | |
2225 | ||
5b7d70c6 BD |
2226 | to_read = size; |
2227 | read_ptr = hs_req->req.actual; | |
2228 | max_req = hs_req->req.length - read_ptr; | |
2229 | ||
a33e7136 BD |
2230 | dev_dbg(hsotg->dev, "%s: read %d/%d, done %d/%d\n", |
2231 | __func__, to_read, max_req, read_ptr, hs_req->req.length); | |
2232 | ||
5b7d70c6 | 2233 | if (to_read > max_req) { |
8b9bc460 LM |
2234 | /* |
2235 | * more data appeared than we where willing | |
5b7d70c6 BD |
2236 | * to deal with in this request. |
2237 | */ | |
2238 | ||
2239 | /* currently we don't deal this */ | |
2240 | WARN_ON_ONCE(1); | |
2241 | } | |
2242 | ||
5b7d70c6 BD |
2243 | hs_ep->total_data += to_read; |
2244 | hs_req->req.actual += to_read; | |
2245 | to_read = DIV_ROUND_UP(to_read, 4); | |
2246 | ||
8b9bc460 LM |
2247 | /* |
2248 | * note, we might over-write the buffer end by 3 bytes depending on | |
2249 | * alignment of the data. | |
2250 | */ | |
342ccce1 GS |
2251 | dwc2_readl_rep(hsotg, EPFIFO(ep_idx), |
2252 | hs_req->req.buf + read_ptr, to_read); | |
5b7d70c6 BD |
2253 | } |
2254 | ||
2255 | /** | |
1f91b4cc | 2256 | * dwc2_hsotg_ep0_zlp - send/receive zero-length packet on control endpoint |
5b7d70c6 | 2257 | * @hsotg: The device instance |
fe0b94ab | 2258 | * @dir_in: If IN zlp |
5b7d70c6 BD |
2259 | * |
2260 | * Generate a zero-length IN packet request for terminating a SETUP | |
2261 | * transaction. | |
2262 | * | |
2263 | * Note, since we don't write any data to the TxFIFO, then it is | |
25985edc | 2264 | * currently believed that we do not need to wait for any space in |
5b7d70c6 BD |
2265 | * the TxFIFO. |
2266 | */ | |
1f91b4cc | 2267 | static void dwc2_hsotg_ep0_zlp(struct dwc2_hsotg *hsotg, bool dir_in) |
5b7d70c6 | 2268 | { |
c6f5c050 | 2269 | /* eps_out[0] is used in both directions */ |
fe0b94ab MYK |
2270 | hsotg->eps_out[0]->dir_in = dir_in; |
2271 | hsotg->ep0_state = dir_in ? DWC2_EP0_STATUS_IN : DWC2_EP0_STATUS_OUT; | |
5b7d70c6 | 2272 | |
1f91b4cc | 2273 | dwc2_hsotg_program_zlp(hsotg, hsotg->eps_out[0]); |
5b7d70c6 BD |
2274 | } |
2275 | ||
ec1f9d9f | 2276 | static void dwc2_hsotg_change_ep_iso_parity(struct dwc2_hsotg *hsotg, |
9da51974 | 2277 | u32 epctl_reg) |
ec1f9d9f RB |
2278 | { |
2279 | u32 ctrl; | |
2280 | ||
f25c42b8 | 2281 | ctrl = dwc2_readl(hsotg, epctl_reg); |
ec1f9d9f RB |
2282 | if (ctrl & DXEPCTL_EOFRNUM) |
2283 | ctrl |= DXEPCTL_SETEVENFR; | |
2284 | else | |
2285 | ctrl |= DXEPCTL_SETODDFR; | |
f25c42b8 | 2286 | dwc2_writel(hsotg, ctrl, epctl_reg); |
ec1f9d9f RB |
2287 | } |
2288 | ||
aa3e8bc8 VA |
2289 | /* |
2290 | * dwc2_gadget_get_xfersize_ddma - get transferred bytes amount from desc | |
2291 | * @hs_ep - The endpoint on which transfer went | |
2292 | * | |
2293 | * Iterate over endpoints descriptor chain and get info on bytes remained | |
2294 | * in DMA descriptors after transfer has completed. Used for non isoc EPs. | |
2295 | */ | |
2296 | static unsigned int dwc2_gadget_get_xfersize_ddma(struct dwc2_hsotg_ep *hs_ep) | |
2297 | { | |
2298 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
2299 | unsigned int bytes_rem = 0; | |
2300 | struct dwc2_dma_desc *desc = hs_ep->desc_list; | |
2301 | int i; | |
2302 | u32 status; | |
2303 | ||
2304 | if (!desc) | |
2305 | return -EINVAL; | |
2306 | ||
2307 | for (i = 0; i < hs_ep->desc_count; ++i) { | |
2308 | status = desc->status; | |
2309 | bytes_rem += status & DEV_DMA_NBYTES_MASK; | |
2310 | ||
2311 | if (status & DEV_DMA_STS_MASK) | |
2312 | dev_err(hsotg->dev, "descriptor %d closed with %x\n", | |
2313 | i, status & DEV_DMA_STS_MASK); | |
2314 | } | |
2315 | ||
2316 | return bytes_rem; | |
2317 | } | |
2318 | ||
5b7d70c6 | 2319 | /** |
1f91b4cc | 2320 | * dwc2_hsotg_handle_outdone - handle receiving OutDone/SetupDone from RXFIFO |
5b7d70c6 BD |
2321 | * @hsotg: The device instance |
2322 | * @epnum: The endpoint received from | |
5b7d70c6 BD |
2323 | * |
2324 | * The RXFIFO has delivered an OutDone event, which means that the data | |
2325 | * transfer for an OUT endpoint has been completed, either by a short | |
2326 | * packet or by the finish of a transfer. | |
8b9bc460 | 2327 | */ |
1f91b4cc | 2328 | static void dwc2_hsotg_handle_outdone(struct dwc2_hsotg *hsotg, int epnum) |
5b7d70c6 | 2329 | { |
f25c42b8 | 2330 | u32 epsize = dwc2_readl(hsotg, DOEPTSIZ(epnum)); |
1f91b4cc FB |
2331 | struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[epnum]; |
2332 | struct dwc2_hsotg_req *hs_req = hs_ep->req; | |
5b7d70c6 | 2333 | struct usb_request *req = &hs_req->req; |
9da51974 | 2334 | unsigned int size_left = DXEPTSIZ_XFERSIZE_GET(epsize); |
5b7d70c6 BD |
2335 | int result = 0; |
2336 | ||
2337 | if (!hs_req) { | |
2338 | dev_dbg(hsotg->dev, "%s: no request active\n", __func__); | |
2339 | return; | |
2340 | } | |
2341 | ||
fe0b94ab MYK |
2342 | if (epnum == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_OUT) { |
2343 | dev_dbg(hsotg->dev, "zlp packet received\n"); | |
1f91b4cc FB |
2344 | dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0); |
2345 | dwc2_hsotg_enqueue_setup(hsotg); | |
fe0b94ab MYK |
2346 | return; |
2347 | } | |
2348 | ||
aa3e8bc8 VA |
2349 | if (using_desc_dma(hsotg)) |
2350 | size_left = dwc2_gadget_get_xfersize_ddma(hs_ep); | |
2351 | ||
5b7d70c6 | 2352 | if (using_dma(hsotg)) { |
9da51974 | 2353 | unsigned int size_done; |
5b7d70c6 | 2354 | |
8b9bc460 LM |
2355 | /* |
2356 | * Calculate the size of the transfer by checking how much | |
5b7d70c6 BD |
2357 | * is left in the endpoint size register and then working it |
2358 | * out from the amount we loaded for the transfer. | |
2359 | * | |
2360 | * We need to do this as DMA pointers are always 32bit aligned | |
2361 | * so may overshoot/undershoot the transfer. | |
2362 | */ | |
2363 | ||
5b7d70c6 BD |
2364 | size_done = hs_ep->size_loaded - size_left; |
2365 | size_done += hs_ep->last_load; | |
2366 | ||
2367 | req->actual = size_done; | |
2368 | } | |
2369 | ||
a33e7136 BD |
2370 | /* if there is more request to do, schedule new transfer */ |
2371 | if (req->actual < req->length && size_left == 0) { | |
1f91b4cc | 2372 | dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true); |
a33e7136 BD |
2373 | return; |
2374 | } | |
2375 | ||
5b7d70c6 BD |
2376 | if (req->actual < req->length && req->short_not_ok) { |
2377 | dev_dbg(hsotg->dev, "%s: got %d/%d (short not ok) => error\n", | |
2378 | __func__, req->actual, req->length); | |
2379 | ||
8b9bc460 LM |
2380 | /* |
2381 | * todo - what should we return here? there's no one else | |
2382 | * even bothering to check the status. | |
2383 | */ | |
5b7d70c6 BD |
2384 | } |
2385 | ||
ef750c71 VA |
2386 | /* DDMA IN status phase will start from StsPhseRcvd interrupt */ |
2387 | if (!using_desc_dma(hsotg) && epnum == 0 && | |
2388 | hsotg->ep0_state == DWC2_EP0_DATA_OUT) { | |
fe0b94ab | 2389 | /* Move to STATUS IN */ |
1f91b4cc | 2390 | dwc2_hsotg_ep0_zlp(hsotg, true); |
fe0b94ab | 2391 | return; |
5b7d70c6 BD |
2392 | } |
2393 | ||
ec1f9d9f RB |
2394 | /* |
2395 | * Slave mode OUT transfers do not go through XferComplete so | |
2396 | * adjust the ISOC parity here. | |
2397 | */ | |
2398 | if (!using_dma(hsotg)) { | |
ec1f9d9f RB |
2399 | if (hs_ep->isochronous && hs_ep->interval == 1) |
2400 | dwc2_hsotg_change_ep_iso_parity(hsotg, DOEPCTL(epnum)); | |
837e9f00 VM |
2401 | else if (hs_ep->isochronous && hs_ep->interval > 1) |
2402 | dwc2_gadget_incr_frame_num(hs_ep); | |
ec1f9d9f RB |
2403 | } |
2404 | ||
1f91b4cc | 2405 | dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, result); |
5b7d70c6 BD |
2406 | } |
2407 | ||
5b7d70c6 | 2408 | /** |
1f91b4cc | 2409 | * dwc2_hsotg_handle_rx - RX FIFO has data |
5b7d70c6 BD |
2410 | * @hsotg: The device instance |
2411 | * | |
2412 | * The IRQ handler has detected that the RX FIFO has some data in it | |
2413 | * that requires processing, so find out what is in there and do the | |
2414 | * appropriate read. | |
2415 | * | |
25985edc | 2416 | * The RXFIFO is a true FIFO, the packets coming out are still in packet |
5b7d70c6 BD |
2417 | * chunks, so if you have x packets received on an endpoint you'll get x |
2418 | * FIFO events delivered, each with a packet's worth of data in it. | |
2419 | * | |
2420 | * When using DMA, we should not be processing events from the RXFIFO | |
2421 | * as the actual data should be sent to the memory directly and we turn | |
2422 | * on the completion interrupts to get notifications of transfer completion. | |
2423 | */ | |
1f91b4cc | 2424 | static void dwc2_hsotg_handle_rx(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 2425 | { |
f25c42b8 | 2426 | u32 grxstsr = dwc2_readl(hsotg, GRXSTSP); |
5b7d70c6 BD |
2427 | u32 epnum, status, size; |
2428 | ||
2429 | WARN_ON(using_dma(hsotg)); | |
2430 | ||
47a1685f DN |
2431 | epnum = grxstsr & GRXSTS_EPNUM_MASK; |
2432 | status = grxstsr & GRXSTS_PKTSTS_MASK; | |
5b7d70c6 | 2433 | |
47a1685f DN |
2434 | size = grxstsr & GRXSTS_BYTECNT_MASK; |
2435 | size >>= GRXSTS_BYTECNT_SHIFT; | |
5b7d70c6 | 2436 | |
d7c747c5 | 2437 | dev_dbg(hsotg->dev, "%s: GRXSTSP=0x%08x (%d@%d)\n", |
9da51974 | 2438 | __func__, grxstsr, size, epnum); |
5b7d70c6 | 2439 | |
47a1685f DN |
2440 | switch ((status & GRXSTS_PKTSTS_MASK) >> GRXSTS_PKTSTS_SHIFT) { |
2441 | case GRXSTS_PKTSTS_GLOBALOUTNAK: | |
2442 | dev_dbg(hsotg->dev, "GLOBALOUTNAK\n"); | |
5b7d70c6 BD |
2443 | break; |
2444 | ||
47a1685f | 2445 | case GRXSTS_PKTSTS_OUTDONE: |
5b7d70c6 | 2446 | dev_dbg(hsotg->dev, "OutDone (Frame=0x%08x)\n", |
1f91b4cc | 2447 | dwc2_hsotg_read_frameno(hsotg)); |
5b7d70c6 BD |
2448 | |
2449 | if (!using_dma(hsotg)) | |
1f91b4cc | 2450 | dwc2_hsotg_handle_outdone(hsotg, epnum); |
5b7d70c6 BD |
2451 | break; |
2452 | ||
47a1685f | 2453 | case GRXSTS_PKTSTS_SETUPDONE: |
5b7d70c6 BD |
2454 | dev_dbg(hsotg->dev, |
2455 | "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n", | |
1f91b4cc | 2456 | dwc2_hsotg_read_frameno(hsotg), |
f25c42b8 | 2457 | dwc2_readl(hsotg, DOEPCTL(0))); |
fe0b94ab | 2458 | /* |
1f91b4cc | 2459 | * Call dwc2_hsotg_handle_outdone here if it was not called from |
fe0b94ab MYK |
2460 | * GRXSTS_PKTSTS_OUTDONE. That is, if the core didn't |
2461 | * generate GRXSTS_PKTSTS_OUTDONE for setup packet. | |
2462 | */ | |
2463 | if (hsotg->ep0_state == DWC2_EP0_SETUP) | |
1f91b4cc | 2464 | dwc2_hsotg_handle_outdone(hsotg, epnum); |
5b7d70c6 BD |
2465 | break; |
2466 | ||
47a1685f | 2467 | case GRXSTS_PKTSTS_OUTRX: |
1f91b4cc | 2468 | dwc2_hsotg_rx_data(hsotg, epnum, size); |
5b7d70c6 BD |
2469 | break; |
2470 | ||
47a1685f | 2471 | case GRXSTS_PKTSTS_SETUPRX: |
5b7d70c6 BD |
2472 | dev_dbg(hsotg->dev, |
2473 | "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n", | |
1f91b4cc | 2474 | dwc2_hsotg_read_frameno(hsotg), |
f25c42b8 | 2475 | dwc2_readl(hsotg, DOEPCTL(0))); |
5b7d70c6 | 2476 | |
fe0b94ab MYK |
2477 | WARN_ON(hsotg->ep0_state != DWC2_EP0_SETUP); |
2478 | ||
1f91b4cc | 2479 | dwc2_hsotg_rx_data(hsotg, epnum, size); |
5b7d70c6 BD |
2480 | break; |
2481 | ||
2482 | default: | |
2483 | dev_warn(hsotg->dev, "%s: unknown status %08x\n", | |
2484 | __func__, grxstsr); | |
2485 | ||
1f91b4cc | 2486 | dwc2_hsotg_dump(hsotg); |
5b7d70c6 BD |
2487 | break; |
2488 | } | |
2489 | } | |
2490 | ||
2491 | /** | |
1f91b4cc | 2492 | * dwc2_hsotg_ep0_mps - turn max packet size into register setting |
5b7d70c6 | 2493 | * @mps: The maximum packet size in bytes. |
8b9bc460 | 2494 | */ |
1f91b4cc | 2495 | static u32 dwc2_hsotg_ep0_mps(unsigned int mps) |
5b7d70c6 BD |
2496 | { |
2497 | switch (mps) { | |
2498 | case 64: | |
94cb8fd6 | 2499 | return D0EPCTL_MPS_64; |
5b7d70c6 | 2500 | case 32: |
94cb8fd6 | 2501 | return D0EPCTL_MPS_32; |
5b7d70c6 | 2502 | case 16: |
94cb8fd6 | 2503 | return D0EPCTL_MPS_16; |
5b7d70c6 | 2504 | case 8: |
94cb8fd6 | 2505 | return D0EPCTL_MPS_8; |
5b7d70c6 BD |
2506 | } |
2507 | ||
2508 | /* bad max packet size, warn and return invalid result */ | |
2509 | WARN_ON(1); | |
2510 | return (u32)-1; | |
2511 | } | |
2512 | ||
2513 | /** | |
1f91b4cc | 2514 | * dwc2_hsotg_set_ep_maxpacket - set endpoint's max-packet field |
5b7d70c6 BD |
2515 | * @hsotg: The driver state. |
2516 | * @ep: The index number of the endpoint | |
2517 | * @mps: The maximum packet size in bytes | |
ee2c40de | 2518 | * @mc: The multicount value |
6fb914d7 | 2519 | * @dir_in: True if direction is in. |
5b7d70c6 BD |
2520 | * |
2521 | * Configure the maximum packet size for the given endpoint, updating | |
2522 | * the hardware control registers to reflect this. | |
2523 | */ | |
1f91b4cc | 2524 | static void dwc2_hsotg_set_ep_maxpacket(struct dwc2_hsotg *hsotg, |
ee2c40de VM |
2525 | unsigned int ep, unsigned int mps, |
2526 | unsigned int mc, unsigned int dir_in) | |
5b7d70c6 | 2527 | { |
1f91b4cc | 2528 | struct dwc2_hsotg_ep *hs_ep; |
5b7d70c6 BD |
2529 | u32 reg; |
2530 | ||
c6f5c050 MYK |
2531 | hs_ep = index_to_ep(hsotg, ep, dir_in); |
2532 | if (!hs_ep) | |
2533 | return; | |
2534 | ||
5b7d70c6 | 2535 | if (ep == 0) { |
ee2c40de VM |
2536 | u32 mps_bytes = mps; |
2537 | ||
5b7d70c6 | 2538 | /* EP0 is a special case */ |
ee2c40de VM |
2539 | mps = dwc2_hsotg_ep0_mps(mps_bytes); |
2540 | if (mps > 3) | |
5b7d70c6 | 2541 | goto bad_mps; |
ee2c40de | 2542 | hs_ep->ep.maxpacket = mps_bytes; |
4fca54aa | 2543 | hs_ep->mc = 1; |
5b7d70c6 | 2544 | } else { |
ee2c40de | 2545 | if (mps > 1024) |
5b7d70c6 | 2546 | goto bad_mps; |
ee2c40de VM |
2547 | hs_ep->mc = mc; |
2548 | if (mc > 3) | |
4fca54aa | 2549 | goto bad_mps; |
ee2c40de | 2550 | hs_ep->ep.maxpacket = mps; |
5b7d70c6 BD |
2551 | } |
2552 | ||
c6f5c050 | 2553 | if (dir_in) { |
f25c42b8 | 2554 | reg = dwc2_readl(hsotg, DIEPCTL(ep)); |
c6f5c050 | 2555 | reg &= ~DXEPCTL_MPS_MASK; |
ee2c40de | 2556 | reg |= mps; |
f25c42b8 | 2557 | dwc2_writel(hsotg, reg, DIEPCTL(ep)); |
c6f5c050 | 2558 | } else { |
f25c42b8 | 2559 | reg = dwc2_readl(hsotg, DOEPCTL(ep)); |
47a1685f | 2560 | reg &= ~DXEPCTL_MPS_MASK; |
ee2c40de | 2561 | reg |= mps; |
f25c42b8 | 2562 | dwc2_writel(hsotg, reg, DOEPCTL(ep)); |
659ad60c | 2563 | } |
5b7d70c6 BD |
2564 | |
2565 | return; | |
2566 | ||
2567 | bad_mps: | |
2568 | dev_err(hsotg->dev, "ep%d: bad mps of %d\n", ep, mps); | |
2569 | } | |
2570 | ||
9c39ddc6 | 2571 | /** |
1f91b4cc | 2572 | * dwc2_hsotg_txfifo_flush - flush Tx FIFO |
9c39ddc6 AT |
2573 | * @hsotg: The driver state |
2574 | * @idx: The index for the endpoint (0..15) | |
2575 | */ | |
1f91b4cc | 2576 | static void dwc2_hsotg_txfifo_flush(struct dwc2_hsotg *hsotg, unsigned int idx) |
9c39ddc6 | 2577 | { |
f25c42b8 GS |
2578 | dwc2_writel(hsotg, GRSTCTL_TXFNUM(idx) | GRSTCTL_TXFFLSH, |
2579 | GRSTCTL); | |
9c39ddc6 AT |
2580 | |
2581 | /* wait until the fifo is flushed */ | |
79d6b8c5 SA |
2582 | if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL, GRSTCTL_TXFFLSH, 100)) |
2583 | dev_warn(hsotg->dev, "%s: timeout flushing fifo GRSTCTL_TXFFLSH\n", | |
2584 | __func__); | |
9c39ddc6 | 2585 | } |
5b7d70c6 BD |
2586 | |
2587 | /** | |
1f91b4cc | 2588 | * dwc2_hsotg_trytx - check to see if anything needs transmitting |
5b7d70c6 BD |
2589 | * @hsotg: The driver state |
2590 | * @hs_ep: The driver endpoint to check. | |
2591 | * | |
2592 | * Check to see if there is a request that has data to send, and if so | |
2593 | * make an attempt to write data into the FIFO. | |
2594 | */ | |
1f91b4cc | 2595 | static int dwc2_hsotg_trytx(struct dwc2_hsotg *hsotg, |
9da51974 | 2596 | struct dwc2_hsotg_ep *hs_ep) |
5b7d70c6 | 2597 | { |
1f91b4cc | 2598 | struct dwc2_hsotg_req *hs_req = hs_ep->req; |
5b7d70c6 | 2599 | |
afcf4169 RB |
2600 | if (!hs_ep->dir_in || !hs_req) { |
2601 | /** | |
2602 | * if request is not enqueued, we disable interrupts | |
2603 | * for endpoints, excepting ep0 | |
2604 | */ | |
2605 | if (hs_ep->index != 0) | |
1f91b4cc | 2606 | dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, |
9da51974 | 2607 | hs_ep->dir_in, 0); |
5b7d70c6 | 2608 | return 0; |
afcf4169 | 2609 | } |
5b7d70c6 BD |
2610 | |
2611 | if (hs_req->req.actual < hs_req->req.length) { | |
2612 | dev_dbg(hsotg->dev, "trying to write more for ep%d\n", | |
2613 | hs_ep->index); | |
1f91b4cc | 2614 | return dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req); |
5b7d70c6 BD |
2615 | } |
2616 | ||
2617 | return 0; | |
2618 | } | |
2619 | ||
2620 | /** | |
1f91b4cc | 2621 | * dwc2_hsotg_complete_in - complete IN transfer |
5b7d70c6 BD |
2622 | * @hsotg: The device state. |
2623 | * @hs_ep: The endpoint that has just completed. | |
2624 | * | |
2625 | * An IN transfer has been completed, update the transfer's state and then | |
2626 | * call the relevant completion routines. | |
2627 | */ | |
1f91b4cc | 2628 | static void dwc2_hsotg_complete_in(struct dwc2_hsotg *hsotg, |
9da51974 | 2629 | struct dwc2_hsotg_ep *hs_ep) |
5b7d70c6 | 2630 | { |
1f91b4cc | 2631 | struct dwc2_hsotg_req *hs_req = hs_ep->req; |
f25c42b8 | 2632 | u32 epsize = dwc2_readl(hsotg, DIEPTSIZ(hs_ep->index)); |
5b7d70c6 BD |
2633 | int size_left, size_done; |
2634 | ||
2635 | if (!hs_req) { | |
2636 | dev_dbg(hsotg->dev, "XferCompl but no req\n"); | |
2637 | return; | |
2638 | } | |
2639 | ||
d3ca0259 | 2640 | /* Finish ZLP handling for IN EP0 transactions */ |
fe0b94ab MYK |
2641 | if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_IN) { |
2642 | dev_dbg(hsotg->dev, "zlp packet sent\n"); | |
c3b22fe2 RK |
2643 | |
2644 | /* | |
2645 | * While send zlp for DWC2_EP0_STATUS_IN EP direction was | |
2646 | * changed to IN. Change back to complete OUT transfer request | |
2647 | */ | |
2648 | hs_ep->dir_in = 0; | |
2649 | ||
1f91b4cc | 2650 | dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0); |
9e14d0a5 GH |
2651 | if (hsotg->test_mode) { |
2652 | int ret; | |
2653 | ||
1f91b4cc | 2654 | ret = dwc2_hsotg_set_test_mode(hsotg, hsotg->test_mode); |
9e14d0a5 GH |
2655 | if (ret < 0) { |
2656 | dev_dbg(hsotg->dev, "Invalid Test #%d\n", | |
9da51974 | 2657 | hsotg->test_mode); |
1f91b4cc | 2658 | dwc2_hsotg_stall_ep0(hsotg); |
9e14d0a5 GH |
2659 | return; |
2660 | } | |
2661 | } | |
1f91b4cc | 2662 | dwc2_hsotg_enqueue_setup(hsotg); |
d3ca0259 LM |
2663 | return; |
2664 | } | |
2665 | ||
8b9bc460 LM |
2666 | /* |
2667 | * Calculate the size of the transfer by checking how much is left | |
5b7d70c6 BD |
2668 | * in the endpoint size register and then working it out from |
2669 | * the amount we loaded for the transfer. | |
2670 | * | |
2671 | * We do this even for DMA, as the transfer may have incremented | |
2672 | * past the end of the buffer (DMA transfers are always 32bit | |
2673 | * aligned). | |
2674 | */ | |
aa3e8bc8 VA |
2675 | if (using_desc_dma(hsotg)) { |
2676 | size_left = dwc2_gadget_get_xfersize_ddma(hs_ep); | |
2677 | if (size_left < 0) | |
2678 | dev_err(hsotg->dev, "error parsing DDMA results %d\n", | |
2679 | size_left); | |
2680 | } else { | |
2681 | size_left = DXEPTSIZ_XFERSIZE_GET(epsize); | |
2682 | } | |
5b7d70c6 BD |
2683 | |
2684 | size_done = hs_ep->size_loaded - size_left; | |
2685 | size_done += hs_ep->last_load; | |
2686 | ||
2687 | if (hs_req->req.actual != size_done) | |
2688 | dev_dbg(hsotg->dev, "%s: adjusting size done %d => %d\n", | |
2689 | __func__, hs_req->req.actual, size_done); | |
2690 | ||
2691 | hs_req->req.actual = size_done; | |
d3ca0259 LM |
2692 | dev_dbg(hsotg->dev, "req->length:%d req->actual:%d req->zero:%d\n", |
2693 | hs_req->req.length, hs_req->req.actual, hs_req->req.zero); | |
2694 | ||
5b7d70c6 BD |
2695 | if (!size_left && hs_req->req.actual < hs_req->req.length) { |
2696 | dev_dbg(hsotg->dev, "%s trying more for req...\n", __func__); | |
1f91b4cc | 2697 | dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true); |
fe0b94ab MYK |
2698 | return; |
2699 | } | |
2700 | ||
f71b5e25 | 2701 | /* Zlp for all endpoints, for ep0 only in DATA IN stage */ |
8a20fa45 | 2702 | if (hs_ep->send_zlp) { |
1f91b4cc | 2703 | dwc2_hsotg_program_zlp(hsotg, hs_ep); |
8a20fa45 | 2704 | hs_ep->send_zlp = 0; |
f71b5e25 MYK |
2705 | /* transfer will be completed on next complete interrupt */ |
2706 | return; | |
2707 | } | |
2708 | ||
fe0b94ab MYK |
2709 | if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_DATA_IN) { |
2710 | /* Move to STATUS OUT */ | |
1f91b4cc | 2711 | dwc2_hsotg_ep0_zlp(hsotg, false); |
fe0b94ab MYK |
2712 | return; |
2713 | } | |
2714 | ||
1f91b4cc | 2715 | dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0); |
5b7d70c6 BD |
2716 | } |
2717 | ||
32601588 VM |
2718 | /** |
2719 | * dwc2_gadget_read_ep_interrupts - reads interrupts for given ep | |
2720 | * @hsotg: The device state. | |
2721 | * @idx: Index of ep. | |
2722 | * @dir_in: Endpoint direction 1-in 0-out. | |
2723 | * | |
2724 | * Reads for endpoint with given index and direction, by masking | |
2725 | * epint_reg with coresponding mask. | |
2726 | */ | |
2727 | static u32 dwc2_gadget_read_ep_interrupts(struct dwc2_hsotg *hsotg, | |
2728 | unsigned int idx, int dir_in) | |
2729 | { | |
2730 | u32 epmsk_reg = dir_in ? DIEPMSK : DOEPMSK; | |
2731 | u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx); | |
2732 | u32 ints; | |
2733 | u32 mask; | |
2734 | u32 diepempmsk; | |
2735 | ||
f25c42b8 GS |
2736 | mask = dwc2_readl(hsotg, epmsk_reg); |
2737 | diepempmsk = dwc2_readl(hsotg, DIEPEMPMSK); | |
32601588 VM |
2738 | mask |= ((diepempmsk >> idx) & 0x1) ? DIEPMSK_TXFIFOEMPTY : 0; |
2739 | mask |= DXEPINT_SETUP_RCVD; | |
2740 | ||
f25c42b8 | 2741 | ints = dwc2_readl(hsotg, epint_reg); |
32601588 VM |
2742 | ints &= mask; |
2743 | return ints; | |
2744 | } | |
2745 | ||
bd9971f0 VM |
2746 | /** |
2747 | * dwc2_gadget_handle_ep_disabled - handle DXEPINT_EPDISBLD | |
2748 | * @hs_ep: The endpoint on which interrupt is asserted. | |
2749 | * | |
2750 | * This interrupt indicates that the endpoint has been disabled per the | |
2751 | * application's request. | |
2752 | * | |
2753 | * For IN endpoints flushes txfifo, in case of BULK clears DCTL_CGNPINNAK, | |
2754 | * in case of ISOC completes current request. | |
2755 | * | |
2756 | * For ISOC-OUT endpoints completes expired requests. If there is remaining | |
2757 | * request starts it. | |
2758 | */ | |
2759 | static void dwc2_gadget_handle_ep_disabled(struct dwc2_hsotg_ep *hs_ep) | |
2760 | { | |
2761 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
2762 | struct dwc2_hsotg_req *hs_req; | |
2763 | unsigned char idx = hs_ep->index; | |
2764 | int dir_in = hs_ep->dir_in; | |
2765 | u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx); | |
f25c42b8 | 2766 | int dctl = dwc2_readl(hsotg, DCTL); |
bd9971f0 VM |
2767 | |
2768 | dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__); | |
2769 | ||
2770 | if (dir_in) { | |
f25c42b8 | 2771 | int epctl = dwc2_readl(hsotg, epctl_reg); |
bd9971f0 VM |
2772 | |
2773 | dwc2_hsotg_txfifo_flush(hsotg, hs_ep->fifo_index); | |
2774 | ||
2775 | if (hs_ep->isochronous) { | |
2776 | dwc2_hsotg_complete_in(hsotg, hs_ep); | |
2777 | return; | |
2778 | } | |
2779 | ||
2780 | if ((epctl & DXEPCTL_STALL) && (epctl & DXEPCTL_EPTYPE_BULK)) { | |
f25c42b8 | 2781 | int dctl = dwc2_readl(hsotg, DCTL); |
bd9971f0 VM |
2782 | |
2783 | dctl |= DCTL_CGNPINNAK; | |
f25c42b8 | 2784 | dwc2_writel(hsotg, dctl, DCTL); |
bd9971f0 VM |
2785 | } |
2786 | return; | |
2787 | } | |
2788 | ||
2789 | if (dctl & DCTL_GOUTNAKSTS) { | |
2790 | dctl |= DCTL_CGOUTNAK; | |
f25c42b8 | 2791 | dwc2_writel(hsotg, dctl, DCTL); |
bd9971f0 VM |
2792 | } |
2793 | ||
2794 | if (!hs_ep->isochronous) | |
2795 | return; | |
2796 | ||
2797 | if (list_empty(&hs_ep->queue)) { | |
2798 | dev_dbg(hsotg->dev, "%s: complete_ep 0x%p, ep->queue empty!\n", | |
2799 | __func__, hs_ep); | |
2800 | return; | |
2801 | } | |
2802 | ||
2803 | do { | |
2804 | hs_req = get_ep_head(hs_ep); | |
2805 | if (hs_req) | |
2806 | dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, | |
2807 | -ENODATA); | |
2808 | dwc2_gadget_incr_frame_num(hs_ep); | |
c7c24e7a AP |
2809 | /* Update current frame number value. */ |
2810 | hsotg->frame_number = dwc2_hsotg_read_frameno(hsotg); | |
bd9971f0 VM |
2811 | } while (dwc2_gadget_target_frame_elapsed(hs_ep)); |
2812 | ||
2813 | dwc2_gadget_start_next_request(hs_ep); | |
2814 | } | |
2815 | ||
5321922c VM |
2816 | /** |
2817 | * dwc2_gadget_handle_out_token_ep_disabled - handle DXEPINT_OUTTKNEPDIS | |
6fb914d7 | 2818 | * @ep: The endpoint on which interrupt is asserted. |
5321922c VM |
2819 | * |
2820 | * This is starting point for ISOC-OUT transfer, synchronization done with | |
2821 | * first out token received from host while corresponding EP is disabled. | |
2822 | * | |
2823 | * Device does not know initial frame in which out token will come. For this | |
2824 | * HW generates OUTTKNEPDIS - out token is received while EP is disabled. Upon | |
2825 | * getting this interrupt SW starts calculation for next transfer frame. | |
2826 | */ | |
2827 | static void dwc2_gadget_handle_out_token_ep_disabled(struct dwc2_hsotg_ep *ep) | |
2828 | { | |
2829 | struct dwc2_hsotg *hsotg = ep->parent; | |
2830 | int dir_in = ep->dir_in; | |
2831 | u32 doepmsk; | |
2832 | ||
2833 | if (dir_in || !ep->isochronous) | |
2834 | return; | |
2835 | ||
540ccba0 VA |
2836 | if (using_desc_dma(hsotg)) { |
2837 | if (ep->target_frame == TARGET_FRAME_INITIAL) { | |
2838 | /* Start first ISO Out */ | |
4d4f1e79 | 2839 | ep->target_frame = hsotg->frame_number; |
540ccba0 VA |
2840 | dwc2_gadget_start_isoc_ddma(ep); |
2841 | } | |
2842 | return; | |
2843 | } | |
2844 | ||
5321922c VM |
2845 | if (ep->interval > 1 && |
2846 | ep->target_frame == TARGET_FRAME_INITIAL) { | |
5321922c VM |
2847 | u32 ctrl; |
2848 | ||
4d4f1e79 | 2849 | ep->target_frame = hsotg->frame_number; |
5321922c VM |
2850 | dwc2_gadget_incr_frame_num(ep); |
2851 | ||
f25c42b8 | 2852 | ctrl = dwc2_readl(hsotg, DOEPCTL(ep->index)); |
5321922c VM |
2853 | if (ep->target_frame & 0x1) |
2854 | ctrl |= DXEPCTL_SETODDFR; | |
2855 | else | |
2856 | ctrl |= DXEPCTL_SETEVENFR; | |
2857 | ||
f25c42b8 | 2858 | dwc2_writel(hsotg, ctrl, DOEPCTL(ep->index)); |
5321922c VM |
2859 | } |
2860 | ||
2861 | dwc2_gadget_start_next_request(ep); | |
f25c42b8 | 2862 | doepmsk = dwc2_readl(hsotg, DOEPMSK); |
5321922c | 2863 | doepmsk &= ~DOEPMSK_OUTTKNEPDISMSK; |
f25c42b8 | 2864 | dwc2_writel(hsotg, doepmsk, DOEPMSK); |
5321922c VM |
2865 | } |
2866 | ||
2867 | /** | |
38beaec6 JY |
2868 | * dwc2_gadget_handle_nak - handle NAK interrupt |
2869 | * @hs_ep: The endpoint on which interrupt is asserted. | |
2870 | * | |
2871 | * This is starting point for ISOC-IN transfer, synchronization done with | |
2872 | * first IN token received from host while corresponding EP is disabled. | |
2873 | * | |
2874 | * Device does not know when first one token will arrive from host. On first | |
2875 | * token arrival HW generates 2 interrupts: 'in token received while FIFO empty' | |
2876 | * and 'NAK'. NAK interrupt for ISOC-IN means that token has arrived and ZLP was | |
2877 | * sent in response to that as there was no data in FIFO. SW is basing on this | |
2878 | * interrupt to obtain frame in which token has come and then based on the | |
2879 | * interval calculates next frame for transfer. | |
2880 | */ | |
5321922c VM |
2881 | static void dwc2_gadget_handle_nak(struct dwc2_hsotg_ep *hs_ep) |
2882 | { | |
2883 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
2884 | int dir_in = hs_ep->dir_in; | |
2885 | ||
2886 | if (!dir_in || !hs_ep->isochronous) | |
2887 | return; | |
2888 | ||
2889 | if (hs_ep->target_frame == TARGET_FRAME_INITIAL) { | |
540ccba0 VA |
2890 | |
2891 | if (using_desc_dma(hsotg)) { | |
4d4f1e79 | 2892 | hs_ep->target_frame = hsotg->frame_number; |
729cac69 | 2893 | dwc2_gadget_incr_frame_num(hs_ep); |
48dac4e4 GT |
2894 | |
2895 | /* In service interval mode target_frame must | |
2896 | * be set to last (u)frame of the service interval. | |
2897 | */ | |
2898 | if (hsotg->params.service_interval) { | |
2899 | /* Set target_frame to the first (u)frame of | |
2900 | * the service interval | |
2901 | */ | |
2902 | hs_ep->target_frame &= ~hs_ep->interval + 1; | |
2903 | ||
2904 | /* Set target_frame to the last (u)frame of | |
2905 | * the service interval | |
2906 | */ | |
2907 | dwc2_gadget_incr_frame_num(hs_ep); | |
2908 | dwc2_gadget_dec_frame_num_by_one(hs_ep); | |
2909 | } | |
2910 | ||
540ccba0 VA |
2911 | dwc2_gadget_start_isoc_ddma(hs_ep); |
2912 | return; | |
2913 | } | |
2914 | ||
4d4f1e79 | 2915 | hs_ep->target_frame = hsotg->frame_number; |
5321922c | 2916 | if (hs_ep->interval > 1) { |
f25c42b8 | 2917 | u32 ctrl = dwc2_readl(hsotg, |
5321922c VM |
2918 | DIEPCTL(hs_ep->index)); |
2919 | if (hs_ep->target_frame & 0x1) | |
2920 | ctrl |= DXEPCTL_SETODDFR; | |
2921 | else | |
2922 | ctrl |= DXEPCTL_SETEVENFR; | |
2923 | ||
f25c42b8 | 2924 | dwc2_writel(hsotg, ctrl, DIEPCTL(hs_ep->index)); |
5321922c VM |
2925 | } |
2926 | ||
2927 | dwc2_hsotg_complete_request(hsotg, hs_ep, | |
2928 | get_ep_head(hs_ep), 0); | |
2929 | } | |
2930 | ||
729cac69 MH |
2931 | if (!using_desc_dma(hsotg)) |
2932 | dwc2_gadget_incr_frame_num(hs_ep); | |
5321922c VM |
2933 | } |
2934 | ||
5b7d70c6 | 2935 | /** |
1f91b4cc | 2936 | * dwc2_hsotg_epint - handle an in/out endpoint interrupt |
5b7d70c6 BD |
2937 | * @hsotg: The driver state |
2938 | * @idx: The index for the endpoint (0..15) | |
2939 | * @dir_in: Set if this is an IN endpoint | |
2940 | * | |
2941 | * Process and clear any interrupt pending for an individual endpoint | |
8b9bc460 | 2942 | */ |
1f91b4cc | 2943 | static void dwc2_hsotg_epint(struct dwc2_hsotg *hsotg, unsigned int idx, |
9da51974 | 2944 | int dir_in) |
5b7d70c6 | 2945 | { |
1f91b4cc | 2946 | struct dwc2_hsotg_ep *hs_ep = index_to_ep(hsotg, idx, dir_in); |
94cb8fd6 LM |
2947 | u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx); |
2948 | u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx); | |
2949 | u32 epsiz_reg = dir_in ? DIEPTSIZ(idx) : DOEPTSIZ(idx); | |
5b7d70c6 | 2950 | u32 ints; |
1479e841 | 2951 | u32 ctrl; |
5b7d70c6 | 2952 | |
32601588 | 2953 | ints = dwc2_gadget_read_ep_interrupts(hsotg, idx, dir_in); |
f25c42b8 | 2954 | ctrl = dwc2_readl(hsotg, epctl_reg); |
5b7d70c6 | 2955 | |
a3395f0d | 2956 | /* Clear endpoint interrupts */ |
f25c42b8 | 2957 | dwc2_writel(hsotg, ints, epint_reg); |
a3395f0d | 2958 | |
c6f5c050 MYK |
2959 | if (!hs_ep) { |
2960 | dev_err(hsotg->dev, "%s:Interrupt for unconfigured ep%d(%s)\n", | |
9da51974 | 2961 | __func__, idx, dir_in ? "in" : "out"); |
c6f5c050 MYK |
2962 | return; |
2963 | } | |
2964 | ||
5b7d70c6 BD |
2965 | dev_dbg(hsotg->dev, "%s: ep%d(%s) DxEPINT=0x%08x\n", |
2966 | __func__, idx, dir_in ? "in" : "out", ints); | |
2967 | ||
b787d755 MYK |
2968 | /* Don't process XferCompl interrupt if it is a setup packet */ |
2969 | if (idx == 0 && (ints & (DXEPINT_SETUP | DXEPINT_SETUP_RCVD))) | |
2970 | ints &= ~DXEPINT_XFERCOMPL; | |
2971 | ||
f0afdb42 VA |
2972 | /* |
2973 | * Don't process XferCompl interrupt in DDMA if EP0 is still in SETUP | |
2974 | * stage and xfercomplete was generated without SETUP phase done | |
2975 | * interrupt. SW should parse received setup packet only after host's | |
2976 | * exit from setup phase of control transfer. | |
2977 | */ | |
2978 | if (using_desc_dma(hsotg) && idx == 0 && !hs_ep->dir_in && | |
2979 | hsotg->ep0_state == DWC2_EP0_SETUP && !(ints & DXEPINT_SETUP)) | |
2980 | ints &= ~DXEPINT_XFERCOMPL; | |
2981 | ||
837e9f00 | 2982 | if (ints & DXEPINT_XFERCOMPL) { |
5b7d70c6 | 2983 | dev_dbg(hsotg->dev, |
47a1685f | 2984 | "%s: XferCompl: DxEPCTL=0x%08x, DXEPTSIZ=%08x\n", |
f25c42b8 GS |
2985 | __func__, dwc2_readl(hsotg, epctl_reg), |
2986 | dwc2_readl(hsotg, epsiz_reg)); | |
5b7d70c6 | 2987 | |
540ccba0 VA |
2988 | /* In DDMA handle isochronous requests separately */ |
2989 | if (using_desc_dma(hsotg) && hs_ep->isochronous) { | |
729cac69 MH |
2990 | /* XferCompl set along with BNA */ |
2991 | if (!(ints & DXEPINT_BNAINTR)) | |
2992 | dwc2_gadget_complete_isoc_request_ddma(hs_ep); | |
540ccba0 VA |
2993 | } else if (dir_in) { |
2994 | /* | |
2995 | * We get OutDone from the FIFO, so we only | |
2996 | * need to look at completing IN requests here | |
2997 | * if operating slave mode | |
2998 | */ | |
837e9f00 VM |
2999 | if (hs_ep->isochronous && hs_ep->interval > 1) |
3000 | dwc2_gadget_incr_frame_num(hs_ep); | |
3001 | ||
1f91b4cc | 3002 | dwc2_hsotg_complete_in(hsotg, hs_ep); |
837e9f00 VM |
3003 | if (ints & DXEPINT_NAKINTRPT) |
3004 | ints &= ~DXEPINT_NAKINTRPT; | |
5b7d70c6 | 3005 | |
c9a64ea8 | 3006 | if (idx == 0 && !hs_ep->req) |
1f91b4cc | 3007 | dwc2_hsotg_enqueue_setup(hsotg); |
5b7d70c6 | 3008 | } else if (using_dma(hsotg)) { |
8b9bc460 LM |
3009 | /* |
3010 | * We're using DMA, we need to fire an OutDone here | |
3011 | * as we ignore the RXFIFO. | |
3012 | */ | |
837e9f00 VM |
3013 | if (hs_ep->isochronous && hs_ep->interval > 1) |
3014 | dwc2_gadget_incr_frame_num(hs_ep); | |
5b7d70c6 | 3015 | |
1f91b4cc | 3016 | dwc2_hsotg_handle_outdone(hsotg, idx); |
5b7d70c6 | 3017 | } |
5b7d70c6 BD |
3018 | } |
3019 | ||
bd9971f0 VM |
3020 | if (ints & DXEPINT_EPDISBLD) |
3021 | dwc2_gadget_handle_ep_disabled(hs_ep); | |
9c39ddc6 | 3022 | |
5321922c VM |
3023 | if (ints & DXEPINT_OUTTKNEPDIS) |
3024 | dwc2_gadget_handle_out_token_ep_disabled(hs_ep); | |
3025 | ||
3026 | if (ints & DXEPINT_NAKINTRPT) | |
3027 | dwc2_gadget_handle_nak(hs_ep); | |
3028 | ||
47a1685f | 3029 | if (ints & DXEPINT_AHBERR) |
5b7d70c6 | 3030 | dev_dbg(hsotg->dev, "%s: AHBErr\n", __func__); |
5b7d70c6 | 3031 | |
47a1685f | 3032 | if (ints & DXEPINT_SETUP) { /* Setup or Timeout */ |
5b7d70c6 BD |
3033 | dev_dbg(hsotg->dev, "%s: Setup/Timeout\n", __func__); |
3034 | ||
3035 | if (using_dma(hsotg) && idx == 0) { | |
8b9bc460 LM |
3036 | /* |
3037 | * this is the notification we've received a | |
5b7d70c6 BD |
3038 | * setup packet. In non-DMA mode we'd get this |
3039 | * from the RXFIFO, instead we need to process | |
8b9bc460 LM |
3040 | * the setup here. |
3041 | */ | |
5b7d70c6 BD |
3042 | |
3043 | if (dir_in) | |
3044 | WARN_ON_ONCE(1); | |
3045 | else | |
1f91b4cc | 3046 | dwc2_hsotg_handle_outdone(hsotg, 0); |
5b7d70c6 | 3047 | } |
5b7d70c6 BD |
3048 | } |
3049 | ||
ef750c71 | 3050 | if (ints & DXEPINT_STSPHSERCVD) { |
9d9a6b07 VA |
3051 | dev_dbg(hsotg->dev, "%s: StsPhseRcvd\n", __func__); |
3052 | ||
9e95a66c MH |
3053 | /* Safety check EP0 state when STSPHSERCVD asserted */ |
3054 | if (hsotg->ep0_state == DWC2_EP0_DATA_OUT) { | |
3055 | /* Move to STATUS IN for DDMA */ | |
3056 | if (using_desc_dma(hsotg)) | |
3057 | dwc2_hsotg_ep0_zlp(hsotg, true); | |
3058 | } | |
3059 | ||
ef750c71 VA |
3060 | } |
3061 | ||
47a1685f | 3062 | if (ints & DXEPINT_BACK2BACKSETUP) |
5b7d70c6 | 3063 | dev_dbg(hsotg->dev, "%s: B2BSetup/INEPNakEff\n", __func__); |
5b7d70c6 | 3064 | |
540ccba0 VA |
3065 | if (ints & DXEPINT_BNAINTR) { |
3066 | dev_dbg(hsotg->dev, "%s: BNA interrupt\n", __func__); | |
540ccba0 | 3067 | if (hs_ep->isochronous) |
729cac69 | 3068 | dwc2_gadget_handle_isoc_bna(hs_ep); |
540ccba0 VA |
3069 | } |
3070 | ||
1479e841 | 3071 | if (dir_in && !hs_ep->isochronous) { |
8b9bc460 | 3072 | /* not sure if this is important, but we'll clear it anyway */ |
26ddef5d | 3073 | if (ints & DXEPINT_INTKNTXFEMP) { |
5b7d70c6 BD |
3074 | dev_dbg(hsotg->dev, "%s: ep%d: INTknTXFEmpMsk\n", |
3075 | __func__, idx); | |
5b7d70c6 BD |
3076 | } |
3077 | ||
3078 | /* this probably means something bad is happening */ | |
26ddef5d | 3079 | if (ints & DXEPINT_INTKNEPMIS) { |
5b7d70c6 BD |
3080 | dev_warn(hsotg->dev, "%s: ep%d: INTknEP\n", |
3081 | __func__, idx); | |
5b7d70c6 | 3082 | } |
10aebc77 BD |
3083 | |
3084 | /* FIFO has space or is empty (see GAHBCFG) */ | |
3085 | if (hsotg->dedicated_fifos && | |
26ddef5d | 3086 | ints & DXEPINT_TXFEMP) { |
10aebc77 BD |
3087 | dev_dbg(hsotg->dev, "%s: ep%d: TxFIFOEmpty\n", |
3088 | __func__, idx); | |
70fa030f | 3089 | if (!using_dma(hsotg)) |
1f91b4cc | 3090 | dwc2_hsotg_trytx(hsotg, hs_ep); |
10aebc77 | 3091 | } |
5b7d70c6 | 3092 | } |
5b7d70c6 BD |
3093 | } |
3094 | ||
3095 | /** | |
1f91b4cc | 3096 | * dwc2_hsotg_irq_enumdone - Handle EnumDone interrupt (enumeration done) |
5b7d70c6 BD |
3097 | * @hsotg: The device state. |
3098 | * | |
3099 | * Handle updating the device settings after the enumeration phase has | |
3100 | * been completed. | |
8b9bc460 | 3101 | */ |
1f91b4cc | 3102 | static void dwc2_hsotg_irq_enumdone(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 3103 | { |
f25c42b8 | 3104 | u32 dsts = dwc2_readl(hsotg, DSTS); |
9b2667f1 | 3105 | int ep0_mps = 0, ep_mps = 8; |
5b7d70c6 | 3106 | |
8b9bc460 LM |
3107 | /* |
3108 | * This should signal the finish of the enumeration phase | |
5b7d70c6 | 3109 | * of the USB handshaking, so we should now know what rate |
8b9bc460 LM |
3110 | * we connected at. |
3111 | */ | |
5b7d70c6 BD |
3112 | |
3113 | dev_dbg(hsotg->dev, "EnumDone (DSTS=0x%08x)\n", dsts); | |
3114 | ||
8b9bc460 LM |
3115 | /* |
3116 | * note, since we're limited by the size of transfer on EP0, and | |
5b7d70c6 | 3117 | * it seems IN transfers must be a even number of packets we do |
8b9bc460 LM |
3118 | * not advertise a 64byte MPS on EP0. |
3119 | */ | |
5b7d70c6 BD |
3120 | |
3121 | /* catch both EnumSpd_FS and EnumSpd_FS48 */ | |
6d76c92c | 3122 | switch ((dsts & DSTS_ENUMSPD_MASK) >> DSTS_ENUMSPD_SHIFT) { |
47a1685f DN |
3123 | case DSTS_ENUMSPD_FS: |
3124 | case DSTS_ENUMSPD_FS48: | |
5b7d70c6 | 3125 | hsotg->gadget.speed = USB_SPEED_FULL; |
5b7d70c6 | 3126 | ep0_mps = EP0_MPS_LIMIT; |
295538ff | 3127 | ep_mps = 1023; |
5b7d70c6 BD |
3128 | break; |
3129 | ||
47a1685f | 3130 | case DSTS_ENUMSPD_HS: |
5b7d70c6 | 3131 | hsotg->gadget.speed = USB_SPEED_HIGH; |
5b7d70c6 | 3132 | ep0_mps = EP0_MPS_LIMIT; |
295538ff | 3133 | ep_mps = 1024; |
5b7d70c6 BD |
3134 | break; |
3135 | ||
47a1685f | 3136 | case DSTS_ENUMSPD_LS: |
5b7d70c6 | 3137 | hsotg->gadget.speed = USB_SPEED_LOW; |
552d940f VM |
3138 | ep0_mps = 8; |
3139 | ep_mps = 8; | |
8b9bc460 LM |
3140 | /* |
3141 | * note, we don't actually support LS in this driver at the | |
5b7d70c6 BD |
3142 | * moment, and the documentation seems to imply that it isn't |
3143 | * supported by the PHYs on some of the devices. | |
3144 | */ | |
3145 | break; | |
3146 | } | |
e538dfda MN |
3147 | dev_info(hsotg->dev, "new device is %s\n", |
3148 | usb_speed_string(hsotg->gadget.speed)); | |
5b7d70c6 | 3149 | |
8b9bc460 LM |
3150 | /* |
3151 | * we should now know the maximum packet size for an | |
3152 | * endpoint, so set the endpoints to a default value. | |
3153 | */ | |
5b7d70c6 BD |
3154 | |
3155 | if (ep0_mps) { | |
3156 | int i; | |
c6f5c050 | 3157 | /* Initialize ep0 for both in and out directions */ |
ee2c40de VM |
3158 | dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 0, 1); |
3159 | dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 0, 0); | |
c6f5c050 MYK |
3160 | for (i = 1; i < hsotg->num_of_eps; i++) { |
3161 | if (hsotg->eps_in[i]) | |
ee2c40de VM |
3162 | dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps, |
3163 | 0, 1); | |
c6f5c050 | 3164 | if (hsotg->eps_out[i]) |
ee2c40de VM |
3165 | dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps, |
3166 | 0, 0); | |
c6f5c050 | 3167 | } |
5b7d70c6 BD |
3168 | } |
3169 | ||
3170 | /* ensure after enumeration our EP0 is active */ | |
3171 | ||
1f91b4cc | 3172 | dwc2_hsotg_enqueue_setup(hsotg); |
5b7d70c6 BD |
3173 | |
3174 | dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n", | |
f25c42b8 GS |
3175 | dwc2_readl(hsotg, DIEPCTL0), |
3176 | dwc2_readl(hsotg, DOEPCTL0)); | |
5b7d70c6 BD |
3177 | } |
3178 | ||
3179 | /** | |
3180 | * kill_all_requests - remove all requests from the endpoint's queue | |
3181 | * @hsotg: The device state. | |
3182 | * @ep: The endpoint the requests may be on. | |
3183 | * @result: The result code to use. | |
5b7d70c6 BD |
3184 | * |
3185 | * Go through the requests on the given endpoint and mark them | |
3186 | * completed with the given result code. | |
3187 | */ | |
941fcce4 | 3188 | static void kill_all_requests(struct dwc2_hsotg *hsotg, |
1f91b4cc | 3189 | struct dwc2_hsotg_ep *ep, |
6b448af4 | 3190 | int result) |
5b7d70c6 | 3191 | { |
1f91b4cc | 3192 | struct dwc2_hsotg_req *req, *treq; |
9da51974 | 3193 | unsigned int size; |
5b7d70c6 | 3194 | |
6b448af4 | 3195 | ep->req = NULL; |
5b7d70c6 | 3196 | |
6b448af4 | 3197 | list_for_each_entry_safe(req, treq, &ep->queue, queue) |
1f91b4cc | 3198 | dwc2_hsotg_complete_request(hsotg, ep, req, |
9da51974 | 3199 | result); |
6b448af4 | 3200 | |
b203d0a2 RB |
3201 | if (!hsotg->dedicated_fifos) |
3202 | return; | |
f25c42b8 | 3203 | size = (dwc2_readl(hsotg, DTXFSTS(ep->fifo_index)) & 0xffff) * 4; |
b203d0a2 | 3204 | if (size < ep->fifo_size) |
1f91b4cc | 3205 | dwc2_hsotg_txfifo_flush(hsotg, ep->fifo_index); |
5b7d70c6 BD |
3206 | } |
3207 | ||
5b7d70c6 | 3208 | /** |
1f91b4cc | 3209 | * dwc2_hsotg_disconnect - disconnect service |
5b7d70c6 BD |
3210 | * @hsotg: The device state. |
3211 | * | |
5e891342 LM |
3212 | * The device has been disconnected. Remove all current |
3213 | * transactions and signal the gadget driver that this | |
3214 | * has happened. | |
8b9bc460 | 3215 | */ |
1f91b4cc | 3216 | void dwc2_hsotg_disconnect(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 3217 | { |
9da51974 | 3218 | unsigned int ep; |
5b7d70c6 | 3219 | |
4ace06e8 MS |
3220 | if (!hsotg->connected) |
3221 | return; | |
3222 | ||
3223 | hsotg->connected = 0; | |
9e14d0a5 | 3224 | hsotg->test_mode = 0; |
c6f5c050 | 3225 | |
dccf1bad | 3226 | /* all endpoints should be shutdown */ |
c6f5c050 MYK |
3227 | for (ep = 0; ep < hsotg->num_of_eps; ep++) { |
3228 | if (hsotg->eps_in[ep]) | |
4fe4f9fe MH |
3229 | kill_all_requests(hsotg, hsotg->eps_in[ep], |
3230 | -ESHUTDOWN); | |
c6f5c050 | 3231 | if (hsotg->eps_out[ep]) |
4fe4f9fe MH |
3232 | kill_all_requests(hsotg, hsotg->eps_out[ep], |
3233 | -ESHUTDOWN); | |
c6f5c050 | 3234 | } |
5b7d70c6 BD |
3235 | |
3236 | call_gadget(hsotg, disconnect); | |
065d3931 | 3237 | hsotg->lx_state = DWC2_L3; |
ce2b21a4 JS |
3238 | |
3239 | usb_gadget_set_state(&hsotg->gadget, USB_STATE_NOTATTACHED); | |
5b7d70c6 BD |
3240 | } |
3241 | ||
3242 | /** | |
1f91b4cc | 3243 | * dwc2_hsotg_irq_fifoempty - TX FIFO empty interrupt handler |
5b7d70c6 BD |
3244 | * @hsotg: The device state: |
3245 | * @periodic: True if this is a periodic FIFO interrupt | |
3246 | */ | |
1f91b4cc | 3247 | static void dwc2_hsotg_irq_fifoempty(struct dwc2_hsotg *hsotg, bool periodic) |
5b7d70c6 | 3248 | { |
1f91b4cc | 3249 | struct dwc2_hsotg_ep *ep; |
5b7d70c6 BD |
3250 | int epno, ret; |
3251 | ||
3252 | /* look through for any more data to transmit */ | |
b3f489b2 | 3253 | for (epno = 0; epno < hsotg->num_of_eps; epno++) { |
c6f5c050 MYK |
3254 | ep = index_to_ep(hsotg, epno, 1); |
3255 | ||
3256 | if (!ep) | |
3257 | continue; | |
5b7d70c6 BD |
3258 | |
3259 | if (!ep->dir_in) | |
3260 | continue; | |
3261 | ||
3262 | if ((periodic && !ep->periodic) || | |
3263 | (!periodic && ep->periodic)) | |
3264 | continue; | |
3265 | ||
1f91b4cc | 3266 | ret = dwc2_hsotg_trytx(hsotg, ep); |
5b7d70c6 BD |
3267 | if (ret < 0) |
3268 | break; | |
3269 | } | |
3270 | } | |
3271 | ||
5b7d70c6 | 3272 | /* IRQ flags which will trigger a retry around the IRQ loop */ |
47a1685f DN |
3273 | #define IRQ_RETRY_MASK (GINTSTS_NPTXFEMP | \ |
3274 | GINTSTS_PTXFEMP | \ | |
3275 | GINTSTS_RXFLVL) | |
5b7d70c6 | 3276 | |
4fe4f9fe | 3277 | static int dwc2_hsotg_ep_disable(struct usb_ep *ep); |
8b9bc460 | 3278 | /** |
1f91b4cc | 3279 | * dwc2_hsotg_core_init - issue softreset to the core |
8b9bc460 | 3280 | * @hsotg: The device state |
6fb914d7 | 3281 | * @is_usb_reset: Usb resetting flag |
8b9bc460 LM |
3282 | * |
3283 | * Issue a soft reset to the core, and await the core finishing it. | |
3284 | */ | |
1f91b4cc | 3285 | void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg, |
9da51974 | 3286 | bool is_usb_reset) |
308d734e | 3287 | { |
1ee6903b | 3288 | u32 intmsk; |
643cc4de | 3289 | u32 val; |
ecd9a7ad | 3290 | u32 usbcfg; |
79c3b5bb | 3291 | u32 dcfg = 0; |
dccf1bad | 3292 | int ep; |
643cc4de | 3293 | |
5390d438 MYK |
3294 | /* Kill any ep0 requests as controller will be reinitialized */ |
3295 | kill_all_requests(hsotg, hsotg->eps_out[0], -ECONNRESET); | |
3296 | ||
dccf1bad | 3297 | if (!is_usb_reset) { |
6e6360b6 | 3298 | if (dwc2_core_reset(hsotg, true)) |
86de4895 | 3299 | return; |
dccf1bad MH |
3300 | } else { |
3301 | /* all endpoints should be shutdown */ | |
3302 | for (ep = 1; ep < hsotg->num_of_eps; ep++) { | |
3303 | if (hsotg->eps_in[ep]) | |
3304 | dwc2_hsotg_ep_disable(&hsotg->eps_in[ep]->ep); | |
3305 | if (hsotg->eps_out[ep]) | |
3306 | dwc2_hsotg_ep_disable(&hsotg->eps_out[ep]->ep); | |
3307 | } | |
3308 | } | |
308d734e LM |
3309 | |
3310 | /* | |
3311 | * we must now enable ep0 ready for host detection and then | |
3312 | * set configuration. | |
3313 | */ | |
3314 | ||
ecd9a7ad | 3315 | /* keep other bits untouched (so e.g. forced modes are not lost) */ |
f25c42b8 | 3316 | usbcfg = dwc2_readl(hsotg, GUSBCFG); |
1e868545 | 3317 | usbcfg &= ~GUSBCFG_TOUTCAL_MASK; |
707d80f0 | 3318 | usbcfg |= GUSBCFG_TOUTCAL(7); |
ecd9a7ad | 3319 | |
1e868545 JM |
3320 | /* remove the HNP/SRP and set the PHY */ |
3321 | usbcfg &= ~(GUSBCFG_SRPCAP | GUSBCFG_HNPCAP); | |
3322 | dwc2_writel(hsotg, usbcfg, GUSBCFG); | |
707d80f0 | 3323 | |
1e868545 | 3324 | dwc2_phy_init(hsotg, true); |
308d734e | 3325 | |
1f91b4cc | 3326 | dwc2_hsotg_init_fifo(hsotg); |
308d734e | 3327 | |
643cc4de | 3328 | if (!is_usb_reset) |
f25c42b8 | 3329 | dwc2_set_bit(hsotg, DCTL, DCTL_SFTDISCON); |
308d734e | 3330 | |
79c3b5bb | 3331 | dcfg |= DCFG_EPMISCNT(1); |
38e9002b VM |
3332 | |
3333 | switch (hsotg->params.speed) { | |
3334 | case DWC2_SPEED_PARAM_LOW: | |
3335 | dcfg |= DCFG_DEVSPD_LS; | |
3336 | break; | |
3337 | case DWC2_SPEED_PARAM_FULL: | |
79c3b5bb VA |
3338 | if (hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS) |
3339 | dcfg |= DCFG_DEVSPD_FS48; | |
3340 | else | |
3341 | dcfg |= DCFG_DEVSPD_FS; | |
38e9002b VM |
3342 | break; |
3343 | default: | |
79c3b5bb VA |
3344 | dcfg |= DCFG_DEVSPD_HS; |
3345 | } | |
38e9002b | 3346 | |
b43ebc96 GT |
3347 | if (hsotg->params.ipg_isoc_en) |
3348 | dcfg |= DCFG_IPG_ISOC_SUPPORDED; | |
3349 | ||
f25c42b8 | 3350 | dwc2_writel(hsotg, dcfg, DCFG); |
308d734e LM |
3351 | |
3352 | /* Clear any pending OTG interrupts */ | |
f25c42b8 | 3353 | dwc2_writel(hsotg, 0xffffffff, GOTGINT); |
308d734e LM |
3354 | |
3355 | /* Clear any pending interrupts */ | |
f25c42b8 | 3356 | dwc2_writel(hsotg, 0xffffffff, GINTSTS); |
1ee6903b | 3357 | intmsk = GINTSTS_ERLYSUSP | GINTSTS_SESSREQINT | |
47a1685f | 3358 | GINTSTS_GOUTNAKEFF | GINTSTS_GINNAKEFF | |
1ee6903b GH |
3359 | GINTSTS_USBRST | GINTSTS_RESETDET | |
3360 | GINTSTS_ENUMDONE | GINTSTS_OTGINT | | |
376f0401 SA |
3361 | GINTSTS_USBSUSP | GINTSTS_WKUPINT | |
3362 | GINTSTS_LPMTRANRCVD; | |
f4736701 VA |
3363 | |
3364 | if (!using_desc_dma(hsotg)) | |
3365 | intmsk |= GINTSTS_INCOMPL_SOIN | GINTSTS_INCOMPL_SOOUT; | |
1ee6903b | 3366 | |
95832c00 | 3367 | if (!hsotg->params.external_id_pin_ctl) |
1ee6903b GH |
3368 | intmsk |= GINTSTS_CONIDSTSCHNG; |
3369 | ||
f25c42b8 | 3370 | dwc2_writel(hsotg, intmsk, GINTMSK); |
308d734e | 3371 | |
a5c18f11 | 3372 | if (using_dma(hsotg)) { |
f25c42b8 | 3373 | dwc2_writel(hsotg, GAHBCFG_GLBL_INTR_EN | GAHBCFG_DMA_EN | |
d1ac8c80 | 3374 | hsotg->params.ahbcfg, |
f25c42b8 | 3375 | GAHBCFG); |
a5c18f11 VA |
3376 | |
3377 | /* Set DDMA mode support in the core if needed */ | |
3378 | if (using_desc_dma(hsotg)) | |
f25c42b8 | 3379 | dwc2_set_bit(hsotg, DCFG, DCFG_DESCDMA_EN); |
a5c18f11 VA |
3380 | |
3381 | } else { | |
f25c42b8 | 3382 | dwc2_writel(hsotg, ((hsotg->dedicated_fifos) ? |
95c8bc36 AS |
3383 | (GAHBCFG_NP_TXF_EMP_LVL | |
3384 | GAHBCFG_P_TXF_EMP_LVL) : 0) | | |
f25c42b8 | 3385 | GAHBCFG_GLBL_INTR_EN, GAHBCFG); |
a5c18f11 | 3386 | } |
308d734e LM |
3387 | |
3388 | /* | |
8acc8296 RB |
3389 | * If INTknTXFEmpMsk is enabled, it's important to disable ep interrupts |
3390 | * when we have no data to transfer. Otherwise we get being flooded by | |
3391 | * interrupts. | |
308d734e LM |
3392 | */ |
3393 | ||
f25c42b8 | 3394 | dwc2_writel(hsotg, ((hsotg->dedicated_fifos && !using_dma(hsotg)) ? |
6ff2e832 | 3395 | DIEPMSK_TXFIFOEMPTY | DIEPMSK_INTKNTXFEMPMSK : 0) | |
47a1685f | 3396 | DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK | |
837e9f00 | 3397 | DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK, |
f25c42b8 | 3398 | DIEPMSK); |
308d734e LM |
3399 | |
3400 | /* | |
3401 | * don't need XferCompl, we get that from RXFIFO in slave mode. In | |
9d9a6b07 | 3402 | * DMA mode we may need this and StsPhseRcvd. |
308d734e | 3403 | */ |
f25c42b8 | 3404 | dwc2_writel(hsotg, (using_dma(hsotg) ? (DIEPMSK_XFERCOMPLMSK | |
9d9a6b07 | 3405 | DOEPMSK_STSPHSERCVDMSK) : 0) | |
47a1685f | 3406 | DOEPMSK_EPDISBLDMSK | DOEPMSK_AHBERRMSK | |
9d9a6b07 | 3407 | DOEPMSK_SETUPMSK, |
f25c42b8 | 3408 | DOEPMSK); |
308d734e | 3409 | |
ec01f0b2 | 3410 | /* Enable BNA interrupt for DDMA */ |
37981e00 | 3411 | if (using_desc_dma(hsotg)) { |
f25c42b8 GS |
3412 | dwc2_set_bit(hsotg, DOEPMSK, DOEPMSK_BNAMSK); |
3413 | dwc2_set_bit(hsotg, DIEPMSK, DIEPMSK_BNAININTRMSK); | |
37981e00 | 3414 | } |
ec01f0b2 | 3415 | |
ca531bc2 GT |
3416 | /* Enable Service Interval mode if supported */ |
3417 | if (using_desc_dma(hsotg) && hsotg->params.service_interval) | |
3418 | dwc2_set_bit(hsotg, DCTL, DCTL_SERVICE_INTERVAL_SUPPORTED); | |
3419 | ||
f25c42b8 | 3420 | dwc2_writel(hsotg, 0, DAINTMSK); |
308d734e LM |
3421 | |
3422 | dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n", | |
f25c42b8 GS |
3423 | dwc2_readl(hsotg, DIEPCTL0), |
3424 | dwc2_readl(hsotg, DOEPCTL0)); | |
308d734e LM |
3425 | |
3426 | /* enable in and out endpoint interrupts */ | |
1f91b4cc | 3427 | dwc2_hsotg_en_gsint(hsotg, GINTSTS_OEPINT | GINTSTS_IEPINT); |
308d734e LM |
3428 | |
3429 | /* | |
3430 | * Enable the RXFIFO when in slave mode, as this is how we collect | |
3431 | * the data. In DMA mode, we get events from the FIFO but also | |
3432 | * things we cannot process, so do not use it. | |
3433 | */ | |
3434 | if (!using_dma(hsotg)) | |
1f91b4cc | 3435 | dwc2_hsotg_en_gsint(hsotg, GINTSTS_RXFLVL); |
308d734e LM |
3436 | |
3437 | /* Enable interrupts for EP0 in and out */ | |
1f91b4cc FB |
3438 | dwc2_hsotg_ctrl_epint(hsotg, 0, 0, 1); |
3439 | dwc2_hsotg_ctrl_epint(hsotg, 0, 1, 1); | |
308d734e | 3440 | |
643cc4de | 3441 | if (!is_usb_reset) { |
f25c42b8 | 3442 | dwc2_set_bit(hsotg, DCTL, DCTL_PWRONPRGDONE); |
643cc4de | 3443 | udelay(10); /* see openiboot */ |
f25c42b8 | 3444 | dwc2_clear_bit(hsotg, DCTL, DCTL_PWRONPRGDONE); |
643cc4de | 3445 | } |
308d734e | 3446 | |
f25c42b8 | 3447 | dev_dbg(hsotg->dev, "DCTL=0x%08x\n", dwc2_readl(hsotg, DCTL)); |
308d734e LM |
3448 | |
3449 | /* | |
94cb8fd6 | 3450 | * DxEPCTL_USBActEp says RO in manual, but seems to be set by |
308d734e LM |
3451 | * writing to the EPCTL register.. |
3452 | */ | |
3453 | ||
3454 | /* set to read 1 8byte packet */ | |
f25c42b8 GS |
3455 | dwc2_writel(hsotg, DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) | |
3456 | DXEPTSIZ_XFERSIZE(8), DOEPTSIZ0); | |
308d734e | 3457 | |
f25c42b8 | 3458 | dwc2_writel(hsotg, dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) | |
47a1685f DN |
3459 | DXEPCTL_CNAK | DXEPCTL_EPENA | |
3460 | DXEPCTL_USBACTEP, | |
f25c42b8 | 3461 | DOEPCTL0); |
308d734e LM |
3462 | |
3463 | /* enable, but don't activate EP0in */ | |
f25c42b8 GS |
3464 | dwc2_writel(hsotg, dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) | |
3465 | DXEPCTL_USBACTEP, DIEPCTL0); | |
308d734e | 3466 | |
308d734e | 3467 | /* clear global NAKs */ |
643cc4de GH |
3468 | val = DCTL_CGOUTNAK | DCTL_CGNPINNAK; |
3469 | if (!is_usb_reset) | |
3470 | val |= DCTL_SFTDISCON; | |
f25c42b8 | 3471 | dwc2_set_bit(hsotg, DCTL, val); |
308d734e | 3472 | |
21b03405 SA |
3473 | /* configure the core to support LPM */ |
3474 | dwc2_gadget_init_lpm(hsotg); | |
3475 | ||
15d9dbf8 GT |
3476 | /* program GREFCLK register if needed */ |
3477 | if (using_desc_dma(hsotg) && hsotg->params.service_interval) | |
3478 | dwc2_gadget_program_ref_clk(hsotg); | |
3479 | ||
308d734e LM |
3480 | /* must be at-least 3ms to allow bus to see disconnect */ |
3481 | mdelay(3); | |
3482 | ||
065d3931 | 3483 | hsotg->lx_state = DWC2_L0; |
755d7395 VM |
3484 | |
3485 | dwc2_hsotg_enqueue_setup(hsotg); | |
3486 | ||
3487 | dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n", | |
f25c42b8 GS |
3488 | dwc2_readl(hsotg, DIEPCTL0), |
3489 | dwc2_readl(hsotg, DOEPCTL0)); | |
ad38dc5d MS |
3490 | } |
3491 | ||
1f91b4cc | 3492 | static void dwc2_hsotg_core_disconnect(struct dwc2_hsotg *hsotg) |
ad38dc5d MS |
3493 | { |
3494 | /* set the soft-disconnect bit */ | |
f25c42b8 | 3495 | dwc2_set_bit(hsotg, DCTL, DCTL_SFTDISCON); |
ad38dc5d | 3496 | } |
ac3c81f3 | 3497 | |
1f91b4cc | 3498 | void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg) |
ad38dc5d | 3499 | { |
308d734e | 3500 | /* remove the soft-disconnect and let's go */ |
f25c42b8 | 3501 | dwc2_clear_bit(hsotg, DCTL, DCTL_SFTDISCON); |
308d734e LM |
3502 | } |
3503 | ||
381fc8f8 VM |
3504 | /** |
3505 | * dwc2_gadget_handle_incomplete_isoc_in - handle incomplete ISO IN Interrupt. | |
3506 | * @hsotg: The device state: | |
3507 | * | |
3508 | * This interrupt indicates one of the following conditions occurred while | |
3509 | * transmitting an ISOC transaction. | |
3510 | * - Corrupted IN Token for ISOC EP. | |
3511 | * - Packet not complete in FIFO. | |
3512 | * | |
3513 | * The following actions will be taken: | |
3514 | * - Determine the EP | |
3515 | * - Disable EP; when 'Endpoint Disabled' interrupt is received Flush FIFO | |
3516 | */ | |
3517 | static void dwc2_gadget_handle_incomplete_isoc_in(struct dwc2_hsotg *hsotg) | |
3518 | { | |
3519 | struct dwc2_hsotg_ep *hs_ep; | |
3520 | u32 epctrl; | |
1b4977c7 | 3521 | u32 daintmsk; |
381fc8f8 VM |
3522 | u32 idx; |
3523 | ||
3524 | dev_dbg(hsotg->dev, "Incomplete isoc in interrupt received:\n"); | |
3525 | ||
f25c42b8 | 3526 | daintmsk = dwc2_readl(hsotg, DAINTMSK); |
1b4977c7 | 3527 | |
d5d5f079 | 3528 | for (idx = 1; idx < hsotg->num_of_eps; idx++) { |
381fc8f8 | 3529 | hs_ep = hsotg->eps_in[idx]; |
1b4977c7 | 3530 | /* Proceed only unmasked ISOC EPs */ |
89066b36 | 3531 | if ((BIT(idx) & ~daintmsk) || !hs_ep->isochronous) |
1b4977c7 RK |
3532 | continue; |
3533 | ||
f25c42b8 | 3534 | epctrl = dwc2_readl(hsotg, DIEPCTL(idx)); |
1b4977c7 | 3535 | if ((epctrl & DXEPCTL_EPENA) && |
381fc8f8 VM |
3536 | dwc2_gadget_target_frame_elapsed(hs_ep)) { |
3537 | epctrl |= DXEPCTL_SNAK; | |
3538 | epctrl |= DXEPCTL_EPDIS; | |
f25c42b8 | 3539 | dwc2_writel(hsotg, epctrl, DIEPCTL(idx)); |
381fc8f8 VM |
3540 | } |
3541 | } | |
3542 | ||
3543 | /* Clear interrupt */ | |
f25c42b8 | 3544 | dwc2_writel(hsotg, GINTSTS_INCOMPL_SOIN, GINTSTS); |
381fc8f8 VM |
3545 | } |
3546 | ||
3547 | /** | |
3548 | * dwc2_gadget_handle_incomplete_isoc_out - handle incomplete ISO OUT Interrupt | |
3549 | * @hsotg: The device state: | |
3550 | * | |
3551 | * This interrupt indicates one of the following conditions occurred while | |
3552 | * transmitting an ISOC transaction. | |
3553 | * - Corrupted OUT Token for ISOC EP. | |
3554 | * - Packet not complete in FIFO. | |
3555 | * | |
3556 | * The following actions will be taken: | |
3557 | * - Determine the EP | |
3558 | * - Set DCTL_SGOUTNAK and unmask GOUTNAKEFF if target frame elapsed. | |
3559 | */ | |
3560 | static void dwc2_gadget_handle_incomplete_isoc_out(struct dwc2_hsotg *hsotg) | |
3561 | { | |
3562 | u32 gintsts; | |
3563 | u32 gintmsk; | |
689efb26 | 3564 | u32 daintmsk; |
381fc8f8 VM |
3565 | u32 epctrl; |
3566 | struct dwc2_hsotg_ep *hs_ep; | |
3567 | int idx; | |
3568 | ||
3569 | dev_dbg(hsotg->dev, "%s: GINTSTS_INCOMPL_SOOUT\n", __func__); | |
3570 | ||
f25c42b8 | 3571 | daintmsk = dwc2_readl(hsotg, DAINTMSK); |
689efb26 RK |
3572 | daintmsk >>= DAINT_OUTEP_SHIFT; |
3573 | ||
d5d5f079 | 3574 | for (idx = 1; idx < hsotg->num_of_eps; idx++) { |
381fc8f8 | 3575 | hs_ep = hsotg->eps_out[idx]; |
689efb26 | 3576 | /* Proceed only unmasked ISOC EPs */ |
89066b36 | 3577 | if ((BIT(idx) & ~daintmsk) || !hs_ep->isochronous) |
689efb26 RK |
3578 | continue; |
3579 | ||
f25c42b8 | 3580 | epctrl = dwc2_readl(hsotg, DOEPCTL(idx)); |
689efb26 | 3581 | if ((epctrl & DXEPCTL_EPENA) && |
381fc8f8 VM |
3582 | dwc2_gadget_target_frame_elapsed(hs_ep)) { |
3583 | /* Unmask GOUTNAKEFF interrupt */ | |
f25c42b8 | 3584 | gintmsk = dwc2_readl(hsotg, GINTMSK); |
381fc8f8 | 3585 | gintmsk |= GINTSTS_GOUTNAKEFF; |
f25c42b8 | 3586 | dwc2_writel(hsotg, gintmsk, GINTMSK); |
381fc8f8 | 3587 | |
f25c42b8 | 3588 | gintsts = dwc2_readl(hsotg, GINTSTS); |
689efb26 | 3589 | if (!(gintsts & GINTSTS_GOUTNAKEFF)) { |
f25c42b8 | 3590 | dwc2_set_bit(hsotg, DCTL, DCTL_SGOUTNAK); |
689efb26 RK |
3591 | break; |
3592 | } | |
381fc8f8 VM |
3593 | } |
3594 | } | |
3595 | ||
3596 | /* Clear interrupt */ | |
f25c42b8 | 3597 | dwc2_writel(hsotg, GINTSTS_INCOMPL_SOOUT, GINTSTS); |
381fc8f8 VM |
3598 | } |
3599 | ||
5b7d70c6 | 3600 | /** |
1f91b4cc | 3601 | * dwc2_hsotg_irq - handle device interrupt |
5b7d70c6 BD |
3602 | * @irq: The IRQ number triggered |
3603 | * @pw: The pw value when registered the handler. | |
3604 | */ | |
1f91b4cc | 3605 | static irqreturn_t dwc2_hsotg_irq(int irq, void *pw) |
5b7d70c6 | 3606 | { |
941fcce4 | 3607 | struct dwc2_hsotg *hsotg = pw; |
5b7d70c6 BD |
3608 | int retry_count = 8; |
3609 | u32 gintsts; | |
3610 | u32 gintmsk; | |
3611 | ||
ee3de8d7 VM |
3612 | if (!dwc2_is_device_mode(hsotg)) |
3613 | return IRQ_NONE; | |
3614 | ||
5ad1d316 | 3615 | spin_lock(&hsotg->lock); |
5b7d70c6 | 3616 | irq_retry: |
f25c42b8 GS |
3617 | gintsts = dwc2_readl(hsotg, GINTSTS); |
3618 | gintmsk = dwc2_readl(hsotg, GINTMSK); | |
5b7d70c6 BD |
3619 | |
3620 | dev_dbg(hsotg->dev, "%s: %08x %08x (%08x) retry %d\n", | |
3621 | __func__, gintsts, gintsts & gintmsk, gintmsk, retry_count); | |
3622 | ||
3623 | gintsts &= gintmsk; | |
3624 | ||
8fc37b82 MYK |
3625 | if (gintsts & GINTSTS_RESETDET) { |
3626 | dev_dbg(hsotg->dev, "%s: USBRstDet\n", __func__); | |
3627 | ||
f25c42b8 | 3628 | dwc2_writel(hsotg, GINTSTS_RESETDET, GINTSTS); |
8fc37b82 MYK |
3629 | |
3630 | /* This event must be used only if controller is suspended */ | |
3631 | if (hsotg->lx_state == DWC2_L2) { | |
41ba9b9b | 3632 | dwc2_exit_partial_power_down(hsotg, true); |
8fc37b82 MYK |
3633 | hsotg->lx_state = DWC2_L0; |
3634 | } | |
3635 | } | |
3636 | ||
3637 | if (gintsts & (GINTSTS_USBRST | GINTSTS_RESETDET)) { | |
f25c42b8 | 3638 | u32 usb_status = dwc2_readl(hsotg, GOTGCTL); |
8fc37b82 MYK |
3639 | u32 connected = hsotg->connected; |
3640 | ||
3641 | dev_dbg(hsotg->dev, "%s: USBRst\n", __func__); | |
3642 | dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n", | |
f25c42b8 | 3643 | dwc2_readl(hsotg, GNPTXSTS)); |
8fc37b82 | 3644 | |
f25c42b8 | 3645 | dwc2_writel(hsotg, GINTSTS_USBRST, GINTSTS); |
8fc37b82 MYK |
3646 | |
3647 | /* Report disconnection if it is not already done. */ | |
3648 | dwc2_hsotg_disconnect(hsotg); | |
3649 | ||
307bc11f | 3650 | /* Reset device address to zero */ |
f25c42b8 | 3651 | dwc2_clear_bit(hsotg, DCFG, DCFG_DEVADDR_MASK); |
307bc11f | 3652 | |
8fc37b82 MYK |
3653 | if (usb_status & GOTGCTL_BSESVLD && connected) |
3654 | dwc2_hsotg_core_init_disconnected(hsotg, true); | |
3655 | } | |
3656 | ||
47a1685f | 3657 | if (gintsts & GINTSTS_ENUMDONE) { |
f25c42b8 | 3658 | dwc2_writel(hsotg, GINTSTS_ENUMDONE, GINTSTS); |
a3395f0d | 3659 | |
1f91b4cc | 3660 | dwc2_hsotg_irq_enumdone(hsotg); |
5b7d70c6 BD |
3661 | } |
3662 | ||
47a1685f | 3663 | if (gintsts & (GINTSTS_OEPINT | GINTSTS_IEPINT)) { |
f25c42b8 GS |
3664 | u32 daint = dwc2_readl(hsotg, DAINT); |
3665 | u32 daintmsk = dwc2_readl(hsotg, DAINTMSK); | |
7e804650 | 3666 | u32 daint_out, daint_in; |
5b7d70c6 BD |
3667 | int ep; |
3668 | ||
7e804650 | 3669 | daint &= daintmsk; |
47a1685f DN |
3670 | daint_out = daint >> DAINT_OUTEP_SHIFT; |
3671 | daint_in = daint & ~(daint_out << DAINT_OUTEP_SHIFT); | |
7e804650 | 3672 | |
5b7d70c6 BD |
3673 | dev_dbg(hsotg->dev, "%s: daint=%08x\n", __func__, daint); |
3674 | ||
cec87f1d MYK |
3675 | for (ep = 0; ep < hsotg->num_of_eps && daint_out; |
3676 | ep++, daint_out >>= 1) { | |
5b7d70c6 | 3677 | if (daint_out & 1) |
1f91b4cc | 3678 | dwc2_hsotg_epint(hsotg, ep, 0); |
5b7d70c6 BD |
3679 | } |
3680 | ||
cec87f1d MYK |
3681 | for (ep = 0; ep < hsotg->num_of_eps && daint_in; |
3682 | ep++, daint_in >>= 1) { | |
5b7d70c6 | 3683 | if (daint_in & 1) |
1f91b4cc | 3684 | dwc2_hsotg_epint(hsotg, ep, 1); |
5b7d70c6 | 3685 | } |
5b7d70c6 BD |
3686 | } |
3687 | ||
5b7d70c6 BD |
3688 | /* check both FIFOs */ |
3689 | ||
47a1685f | 3690 | if (gintsts & GINTSTS_NPTXFEMP) { |
5b7d70c6 BD |
3691 | dev_dbg(hsotg->dev, "NPTxFEmp\n"); |
3692 | ||
8b9bc460 LM |
3693 | /* |
3694 | * Disable the interrupt to stop it happening again | |
5b7d70c6 | 3695 | * unless one of these endpoint routines decides that |
8b9bc460 LM |
3696 | * it needs re-enabling |
3697 | */ | |
5b7d70c6 | 3698 | |
1f91b4cc FB |
3699 | dwc2_hsotg_disable_gsint(hsotg, GINTSTS_NPTXFEMP); |
3700 | dwc2_hsotg_irq_fifoempty(hsotg, false); | |
5b7d70c6 BD |
3701 | } |
3702 | ||
47a1685f | 3703 | if (gintsts & GINTSTS_PTXFEMP) { |
5b7d70c6 BD |
3704 | dev_dbg(hsotg->dev, "PTxFEmp\n"); |
3705 | ||
94cb8fd6 | 3706 | /* See note in GINTSTS_NPTxFEmp */ |
5b7d70c6 | 3707 | |
1f91b4cc FB |
3708 | dwc2_hsotg_disable_gsint(hsotg, GINTSTS_PTXFEMP); |
3709 | dwc2_hsotg_irq_fifoempty(hsotg, true); | |
5b7d70c6 BD |
3710 | } |
3711 | ||
47a1685f | 3712 | if (gintsts & GINTSTS_RXFLVL) { |
8b9bc460 LM |
3713 | /* |
3714 | * note, since GINTSTS_RxFLvl doubles as FIFO-not-empty, | |
1f91b4cc | 3715 | * we need to retry dwc2_hsotg_handle_rx if this is still |
8b9bc460 LM |
3716 | * set. |
3717 | */ | |
5b7d70c6 | 3718 | |
1f91b4cc | 3719 | dwc2_hsotg_handle_rx(hsotg); |
5b7d70c6 BD |
3720 | } |
3721 | ||
47a1685f | 3722 | if (gintsts & GINTSTS_ERLYSUSP) { |
94cb8fd6 | 3723 | dev_dbg(hsotg->dev, "GINTSTS_ErlySusp\n"); |
f25c42b8 | 3724 | dwc2_writel(hsotg, GINTSTS_ERLYSUSP, GINTSTS); |
5b7d70c6 BD |
3725 | } |
3726 | ||
8b9bc460 LM |
3727 | /* |
3728 | * these next two seem to crop-up occasionally causing the core | |
5b7d70c6 | 3729 | * to shutdown the USB transfer, so try clearing them and logging |
8b9bc460 LM |
3730 | * the occurrence. |
3731 | */ | |
5b7d70c6 | 3732 | |
47a1685f | 3733 | if (gintsts & GINTSTS_GOUTNAKEFF) { |
837e9f00 VM |
3734 | u8 idx; |
3735 | u32 epctrl; | |
3736 | u32 gintmsk; | |
d8484552 | 3737 | u32 daintmsk; |
837e9f00 VM |
3738 | struct dwc2_hsotg_ep *hs_ep; |
3739 | ||
f25c42b8 | 3740 | daintmsk = dwc2_readl(hsotg, DAINTMSK); |
d8484552 | 3741 | daintmsk >>= DAINT_OUTEP_SHIFT; |
837e9f00 | 3742 | /* Mask this interrupt */ |
f25c42b8 | 3743 | gintmsk = dwc2_readl(hsotg, GINTMSK); |
837e9f00 | 3744 | gintmsk &= ~GINTSTS_GOUTNAKEFF; |
f25c42b8 | 3745 | dwc2_writel(hsotg, gintmsk, GINTMSK); |
837e9f00 VM |
3746 | |
3747 | dev_dbg(hsotg->dev, "GOUTNakEff triggered\n"); | |
d5d5f079 | 3748 | for (idx = 1; idx < hsotg->num_of_eps; idx++) { |
837e9f00 | 3749 | hs_ep = hsotg->eps_out[idx]; |
d8484552 | 3750 | /* Proceed only unmasked ISOC EPs */ |
89066b36 | 3751 | if ((BIT(idx) & ~daintmsk) || !hs_ep->isochronous) |
d8484552 RK |
3752 | continue; |
3753 | ||
f25c42b8 | 3754 | epctrl = dwc2_readl(hsotg, DOEPCTL(idx)); |
837e9f00 | 3755 | |
d8484552 | 3756 | if (epctrl & DXEPCTL_EPENA) { |
837e9f00 VM |
3757 | epctrl |= DXEPCTL_SNAK; |
3758 | epctrl |= DXEPCTL_EPDIS; | |
f25c42b8 | 3759 | dwc2_writel(hsotg, epctrl, DOEPCTL(idx)); |
837e9f00 VM |
3760 | } |
3761 | } | |
a3395f0d | 3762 | |
837e9f00 | 3763 | /* This interrupt bit is cleared in DXEPINT_EPDISBLD handler */ |
5b7d70c6 BD |
3764 | } |
3765 | ||
47a1685f | 3766 | if (gintsts & GINTSTS_GINNAKEFF) { |
5b7d70c6 BD |
3767 | dev_info(hsotg->dev, "GINNakEff triggered\n"); |
3768 | ||
f25c42b8 | 3769 | dwc2_set_bit(hsotg, DCTL, DCTL_CGNPINNAK); |
a3395f0d | 3770 | |
1f91b4cc | 3771 | dwc2_hsotg_dump(hsotg); |
5b7d70c6 BD |
3772 | } |
3773 | ||
381fc8f8 VM |
3774 | if (gintsts & GINTSTS_INCOMPL_SOIN) |
3775 | dwc2_gadget_handle_incomplete_isoc_in(hsotg); | |
ec1f9d9f | 3776 | |
381fc8f8 VM |
3777 | if (gintsts & GINTSTS_INCOMPL_SOOUT) |
3778 | dwc2_gadget_handle_incomplete_isoc_out(hsotg); | |
ec1f9d9f | 3779 | |
8b9bc460 LM |
3780 | /* |
3781 | * if we've had fifo events, we should try and go around the | |
3782 | * loop again to see if there's any point in returning yet. | |
3783 | */ | |
5b7d70c6 BD |
3784 | |
3785 | if (gintsts & IRQ_RETRY_MASK && --retry_count > 0) | |
77b6200e | 3786 | goto irq_retry; |
5b7d70c6 | 3787 | |
187c5298 GT |
3788 | /* Check WKUP_ALERT interrupt*/ |
3789 | if (hsotg->params.service_interval) | |
3790 | dwc2_gadget_wkup_alert_handler(hsotg); | |
3791 | ||
5ad1d316 LM |
3792 | spin_unlock(&hsotg->lock); |
3793 | ||
5b7d70c6 BD |
3794 | return IRQ_HANDLED; |
3795 | } | |
3796 | ||
a4f82771 VA |
3797 | static void dwc2_hsotg_ep_stop_xfr(struct dwc2_hsotg *hsotg, |
3798 | struct dwc2_hsotg_ep *hs_ep) | |
3799 | { | |
3800 | u32 epctrl_reg; | |
3801 | u32 epint_reg; | |
3802 | ||
3803 | epctrl_reg = hs_ep->dir_in ? DIEPCTL(hs_ep->index) : | |
3804 | DOEPCTL(hs_ep->index); | |
3805 | epint_reg = hs_ep->dir_in ? DIEPINT(hs_ep->index) : | |
3806 | DOEPINT(hs_ep->index); | |
3807 | ||
3808 | dev_dbg(hsotg->dev, "%s: stopping transfer on %s\n", __func__, | |
3809 | hs_ep->name); | |
3810 | ||
3811 | if (hs_ep->dir_in) { | |
3812 | if (hsotg->dedicated_fifos || hs_ep->periodic) { | |
f25c42b8 | 3813 | dwc2_set_bit(hsotg, epctrl_reg, DXEPCTL_SNAK); |
a4f82771 VA |
3814 | /* Wait for Nak effect */ |
3815 | if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg, | |
3816 | DXEPINT_INEPNAKEFF, 100)) | |
3817 | dev_warn(hsotg->dev, | |
3818 | "%s: timeout DIEPINT.NAKEFF\n", | |
3819 | __func__); | |
3820 | } else { | |
f25c42b8 | 3821 | dwc2_set_bit(hsotg, DCTL, DCTL_SGNPINNAK); |
a4f82771 VA |
3822 | /* Wait for Nak effect */ |
3823 | if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS, | |
3824 | GINTSTS_GINNAKEFF, 100)) | |
3825 | dev_warn(hsotg->dev, | |
3826 | "%s: timeout GINTSTS.GINNAKEFF\n", | |
3827 | __func__); | |
3828 | } | |
3829 | } else { | |
f25c42b8 GS |
3830 | if (!(dwc2_readl(hsotg, GINTSTS) & GINTSTS_GOUTNAKEFF)) |
3831 | dwc2_set_bit(hsotg, DCTL, DCTL_SGOUTNAK); | |
a4f82771 VA |
3832 | |
3833 | /* Wait for global nak to take effect */ | |
3834 | if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS, | |
3835 | GINTSTS_GOUTNAKEFF, 100)) | |
3836 | dev_warn(hsotg->dev, "%s: timeout GINTSTS.GOUTNAKEFF\n", | |
3837 | __func__); | |
3838 | } | |
3839 | ||
3840 | /* Disable ep */ | |
f25c42b8 | 3841 | dwc2_set_bit(hsotg, epctrl_reg, DXEPCTL_EPDIS | DXEPCTL_SNAK); |
a4f82771 VA |
3842 | |
3843 | /* Wait for ep to be disabled */ | |
3844 | if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg, DXEPINT_EPDISBLD, 100)) | |
3845 | dev_warn(hsotg->dev, | |
3846 | "%s: timeout DOEPCTL.EPDisable\n", __func__); | |
3847 | ||
3848 | /* Clear EPDISBLD interrupt */ | |
f25c42b8 | 3849 | dwc2_set_bit(hsotg, epint_reg, DXEPINT_EPDISBLD); |
a4f82771 VA |
3850 | |
3851 | if (hs_ep->dir_in) { | |
3852 | unsigned short fifo_index; | |
3853 | ||
3854 | if (hsotg->dedicated_fifos || hs_ep->periodic) | |
3855 | fifo_index = hs_ep->fifo_index; | |
3856 | else | |
3857 | fifo_index = 0; | |
3858 | ||
3859 | /* Flush TX FIFO */ | |
3860 | dwc2_flush_tx_fifo(hsotg, fifo_index); | |
3861 | ||
3862 | /* Clear Global In NP NAK in Shared FIFO for non periodic ep */ | |
3863 | if (!hsotg->dedicated_fifos && !hs_ep->periodic) | |
f25c42b8 | 3864 | dwc2_set_bit(hsotg, DCTL, DCTL_CGNPINNAK); |
a4f82771 VA |
3865 | |
3866 | } else { | |
3867 | /* Remove global NAKs */ | |
f25c42b8 | 3868 | dwc2_set_bit(hsotg, DCTL, DCTL_CGOUTNAK); |
a4f82771 VA |
3869 | } |
3870 | } | |
3871 | ||
5b7d70c6 | 3872 | /** |
1f91b4cc | 3873 | * dwc2_hsotg_ep_enable - enable the given endpoint |
5b7d70c6 BD |
3874 | * @ep: The USB endpint to configure |
3875 | * @desc: The USB endpoint descriptor to configure with. | |
3876 | * | |
3877 | * This is called from the USB gadget code's usb_ep_enable(). | |
8b9bc460 | 3878 | */ |
1f91b4cc | 3879 | static int dwc2_hsotg_ep_enable(struct usb_ep *ep, |
9da51974 | 3880 | const struct usb_endpoint_descriptor *desc) |
5b7d70c6 | 3881 | { |
1f91b4cc | 3882 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 3883 | struct dwc2_hsotg *hsotg = hs_ep->parent; |
5b7d70c6 | 3884 | unsigned long flags; |
ca4c55ad | 3885 | unsigned int index = hs_ep->index; |
5b7d70c6 BD |
3886 | u32 epctrl_reg; |
3887 | u32 epctrl; | |
3888 | u32 mps; | |
ee2c40de | 3889 | u32 mc; |
837e9f00 | 3890 | u32 mask; |
ca4c55ad MYK |
3891 | unsigned int dir_in; |
3892 | unsigned int i, val, size; | |
19c190f9 | 3893 | int ret = 0; |
729cac69 | 3894 | unsigned char ep_type; |
5b7d70c6 BD |
3895 | |
3896 | dev_dbg(hsotg->dev, | |
3897 | "%s: ep %s: a 0x%02x, attr 0x%02x, mps 0x%04x, intr %d\n", | |
3898 | __func__, ep->name, desc->bEndpointAddress, desc->bmAttributes, | |
3899 | desc->wMaxPacketSize, desc->bInterval); | |
3900 | ||
3901 | /* not to be called for EP0 */ | |
8c3d6092 VA |
3902 | if (index == 0) { |
3903 | dev_err(hsotg->dev, "%s: called for EP 0\n", __func__); | |
3904 | return -EINVAL; | |
3905 | } | |
5b7d70c6 BD |
3906 | |
3907 | dir_in = (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) ? 1 : 0; | |
3908 | if (dir_in != hs_ep->dir_in) { | |
3909 | dev_err(hsotg->dev, "%s: direction mismatch!\n", __func__); | |
3910 | return -EINVAL; | |
3911 | } | |
3912 | ||
729cac69 | 3913 | ep_type = desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK; |
29cc8897 | 3914 | mps = usb_endpoint_maxp(desc); |
ee2c40de | 3915 | mc = usb_endpoint_maxp_mult(desc); |
5b7d70c6 | 3916 | |
729cac69 MH |
3917 | /* ISOC IN in DDMA supported bInterval up to 10 */ |
3918 | if (using_desc_dma(hsotg) && ep_type == USB_ENDPOINT_XFER_ISOC && | |
3919 | dir_in && desc->bInterval > 10) { | |
3920 | dev_err(hsotg->dev, | |
3921 | "%s: ISOC IN, DDMA: bInterval>10 not supported!\n", __func__); | |
3922 | return -EINVAL; | |
3923 | } | |
3924 | ||
3925 | /* High bandwidth ISOC OUT in DDMA not supported */ | |
3926 | if (using_desc_dma(hsotg) && ep_type == USB_ENDPOINT_XFER_ISOC && | |
3927 | !dir_in && mc > 1) { | |
3928 | dev_err(hsotg->dev, | |
3929 | "%s: ISOC OUT, DDMA: HB not supported!\n", __func__); | |
3930 | return -EINVAL; | |
3931 | } | |
3932 | ||
1f91b4cc | 3933 | /* note, we handle this here instead of dwc2_hsotg_set_ep_maxpacket */ |
5b7d70c6 | 3934 | |
94cb8fd6 | 3935 | epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index); |
f25c42b8 | 3936 | epctrl = dwc2_readl(hsotg, epctrl_reg); |
5b7d70c6 BD |
3937 | |
3938 | dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x from 0x%08x\n", | |
3939 | __func__, epctrl, epctrl_reg); | |
3940 | ||
5f54c54b | 3941 | /* Allocate DMA descriptor chain for non-ctrl endpoints */ |
9383e084 VM |
3942 | if (using_desc_dma(hsotg) && !hs_ep->desc_list) { |
3943 | hs_ep->desc_list = dmam_alloc_coherent(hsotg->dev, | |
5f54c54b VA |
3944 | MAX_DMA_DESC_NUM_GENERIC * |
3945 | sizeof(struct dwc2_dma_desc), | |
86e881e7 | 3946 | &hs_ep->desc_list_dma, GFP_ATOMIC); |
5f54c54b VA |
3947 | if (!hs_ep->desc_list) { |
3948 | ret = -ENOMEM; | |
3949 | goto error2; | |
3950 | } | |
3951 | } | |
3952 | ||
22258f49 | 3953 | spin_lock_irqsave(&hsotg->lock, flags); |
5b7d70c6 | 3954 | |
47a1685f DN |
3955 | epctrl &= ~(DXEPCTL_EPTYPE_MASK | DXEPCTL_MPS_MASK); |
3956 | epctrl |= DXEPCTL_MPS(mps); | |
5b7d70c6 | 3957 | |
8b9bc460 LM |
3958 | /* |
3959 | * mark the endpoint as active, otherwise the core may ignore | |
3960 | * transactions entirely for this endpoint | |
3961 | */ | |
47a1685f | 3962 | epctrl |= DXEPCTL_USBACTEP; |
5b7d70c6 | 3963 | |
5b7d70c6 | 3964 | /* update the endpoint state */ |
ee2c40de | 3965 | dwc2_hsotg_set_ep_maxpacket(hsotg, hs_ep->index, mps, mc, dir_in); |
5b7d70c6 BD |
3966 | |
3967 | /* default, set to non-periodic */ | |
1479e841 | 3968 | hs_ep->isochronous = 0; |
5b7d70c6 | 3969 | hs_ep->periodic = 0; |
a18ed7b0 | 3970 | hs_ep->halted = 0; |
1479e841 | 3971 | hs_ep->interval = desc->bInterval; |
4fca54aa | 3972 | |
729cac69 | 3973 | switch (ep_type) { |
5b7d70c6 | 3974 | case USB_ENDPOINT_XFER_ISOC: |
47a1685f DN |
3975 | epctrl |= DXEPCTL_EPTYPE_ISO; |
3976 | epctrl |= DXEPCTL_SETEVENFR; | |
1479e841 | 3977 | hs_ep->isochronous = 1; |
142bd33f | 3978 | hs_ep->interval = 1 << (desc->bInterval - 1); |
837e9f00 | 3979 | hs_ep->target_frame = TARGET_FRAME_INITIAL; |
ab7d2192 | 3980 | hs_ep->next_desc = 0; |
729cac69 | 3981 | hs_ep->compl_desc = 0; |
837e9f00 | 3982 | if (dir_in) { |
1479e841 | 3983 | hs_ep->periodic = 1; |
f25c42b8 | 3984 | mask = dwc2_readl(hsotg, DIEPMSK); |
837e9f00 | 3985 | mask |= DIEPMSK_NAKMSK; |
f25c42b8 | 3986 | dwc2_writel(hsotg, mask, DIEPMSK); |
837e9f00 | 3987 | } else { |
f25c42b8 | 3988 | mask = dwc2_readl(hsotg, DOEPMSK); |
837e9f00 | 3989 | mask |= DOEPMSK_OUTTKNEPDISMSK; |
f25c42b8 | 3990 | dwc2_writel(hsotg, mask, DOEPMSK); |
837e9f00 | 3991 | } |
1479e841 | 3992 | break; |
5b7d70c6 BD |
3993 | |
3994 | case USB_ENDPOINT_XFER_BULK: | |
47a1685f | 3995 | epctrl |= DXEPCTL_EPTYPE_BULK; |
5b7d70c6 BD |
3996 | break; |
3997 | ||
3998 | case USB_ENDPOINT_XFER_INT: | |
b203d0a2 | 3999 | if (dir_in) |
5b7d70c6 | 4000 | hs_ep->periodic = 1; |
5b7d70c6 | 4001 | |
142bd33f VM |
4002 | if (hsotg->gadget.speed == USB_SPEED_HIGH) |
4003 | hs_ep->interval = 1 << (desc->bInterval - 1); | |
4004 | ||
47a1685f | 4005 | epctrl |= DXEPCTL_EPTYPE_INTERRUPT; |
5b7d70c6 BD |
4006 | break; |
4007 | ||
4008 | case USB_ENDPOINT_XFER_CONTROL: | |
47a1685f | 4009 | epctrl |= DXEPCTL_EPTYPE_CONTROL; |
5b7d70c6 BD |
4010 | break; |
4011 | } | |
4012 | ||
8b9bc460 LM |
4013 | /* |
4014 | * if the hardware has dedicated fifos, we must give each IN EP | |
10aebc77 BD |
4015 | * a unique tx-fifo even if it is non-periodic. |
4016 | */ | |
21f3bb52 | 4017 | if (dir_in && hsotg->dedicated_fifos) { |
ca4c55ad MYK |
4018 | u32 fifo_index = 0; |
4019 | u32 fifo_size = UINT_MAX; | |
9da51974 JY |
4020 | |
4021 | size = hs_ep->ep.maxpacket * hs_ep->mc; | |
5f2196bd | 4022 | for (i = 1; i < hsotg->num_of_eps; ++i) { |
9da51974 | 4023 | if (hsotg->fifo_map & (1 << i)) |
b203d0a2 | 4024 | continue; |
f25c42b8 | 4025 | val = dwc2_readl(hsotg, DPTXFSIZN(i)); |
9da51974 | 4026 | val = (val >> FIFOSIZE_DEPTH_SHIFT) * 4; |
b203d0a2 RB |
4027 | if (val < size) |
4028 | continue; | |
ca4c55ad MYK |
4029 | /* Search for smallest acceptable fifo */ |
4030 | if (val < fifo_size) { | |
4031 | fifo_size = val; | |
4032 | fifo_index = i; | |
4033 | } | |
b203d0a2 | 4034 | } |
ca4c55ad | 4035 | if (!fifo_index) { |
5f2196bd MYK |
4036 | dev_err(hsotg->dev, |
4037 | "%s: No suitable fifo found\n", __func__); | |
b585a48b | 4038 | ret = -ENOMEM; |
5f54c54b | 4039 | goto error1; |
b585a48b | 4040 | } |
97311c8f | 4041 | epctrl &= ~(DXEPCTL_TXFNUM_LIMIT << DXEPCTL_TXFNUM_SHIFT); |
ca4c55ad MYK |
4042 | hsotg->fifo_map |= 1 << fifo_index; |
4043 | epctrl |= DXEPCTL_TXFNUM(fifo_index); | |
4044 | hs_ep->fifo_index = fifo_index; | |
4045 | hs_ep->fifo_size = fifo_size; | |
b203d0a2 | 4046 | } |
10aebc77 | 4047 | |
5b7d70c6 | 4048 | /* for non control endpoints, set PID to D0 */ |
837e9f00 | 4049 | if (index && !hs_ep->isochronous) |
47a1685f | 4050 | epctrl |= DXEPCTL_SETD0PID; |
5b7d70c6 | 4051 | |
5295322a AP |
4052 | /* WA for Full speed ISOC IN in DDMA mode. |
4053 | * By Clear NAK status of EP, core will send ZLP | |
4054 | * to IN token and assert NAK interrupt relying | |
4055 | * on TxFIFO status only | |
4056 | */ | |
4057 | ||
4058 | if (hsotg->gadget.speed == USB_SPEED_FULL && | |
4059 | hs_ep->isochronous && dir_in) { | |
4060 | /* The WA applies only to core versions from 2.72a | |
4061 | * to 4.00a (including both). Also for FS_IOT_1.00a | |
4062 | * and HS_IOT_1.00a. | |
4063 | */ | |
f25c42b8 | 4064 | u32 gsnpsid = dwc2_readl(hsotg, GSNPSID); |
5295322a AP |
4065 | |
4066 | if ((gsnpsid >= DWC2_CORE_REV_2_72a && | |
4067 | gsnpsid <= DWC2_CORE_REV_4_00a) || | |
4068 | gsnpsid == DWC2_FS_IOT_REV_1_00a || | |
4069 | gsnpsid == DWC2_HS_IOT_REV_1_00a) | |
4070 | epctrl |= DXEPCTL_CNAK; | |
4071 | } | |
4072 | ||
5b7d70c6 BD |
4073 | dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n", |
4074 | __func__, epctrl); | |
4075 | ||
f25c42b8 | 4076 | dwc2_writel(hsotg, epctrl, epctrl_reg); |
5b7d70c6 | 4077 | dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x\n", |
f25c42b8 | 4078 | __func__, dwc2_readl(hsotg, epctrl_reg)); |
5b7d70c6 BD |
4079 | |
4080 | /* enable the endpoint interrupt */ | |
1f91b4cc | 4081 | dwc2_hsotg_ctrl_epint(hsotg, index, dir_in, 1); |
5b7d70c6 | 4082 | |
5f54c54b | 4083 | error1: |
22258f49 | 4084 | spin_unlock_irqrestore(&hsotg->lock, flags); |
5f54c54b VA |
4085 | |
4086 | error2: | |
4087 | if (ret && using_desc_dma(hsotg) && hs_ep->desc_list) { | |
9383e084 | 4088 | dmam_free_coherent(hsotg->dev, MAX_DMA_DESC_NUM_GENERIC * |
5f54c54b VA |
4089 | sizeof(struct dwc2_dma_desc), |
4090 | hs_ep->desc_list, hs_ep->desc_list_dma); | |
4091 | hs_ep->desc_list = NULL; | |
4092 | } | |
4093 | ||
19c190f9 | 4094 | return ret; |
5b7d70c6 BD |
4095 | } |
4096 | ||
8b9bc460 | 4097 | /** |
1f91b4cc | 4098 | * dwc2_hsotg_ep_disable - disable given endpoint |
8b9bc460 LM |
4099 | * @ep: The endpoint to disable. |
4100 | */ | |
1f91b4cc | 4101 | static int dwc2_hsotg_ep_disable(struct usb_ep *ep) |
5b7d70c6 | 4102 | { |
1f91b4cc | 4103 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 4104 | struct dwc2_hsotg *hsotg = hs_ep->parent; |
5b7d70c6 BD |
4105 | int dir_in = hs_ep->dir_in; |
4106 | int index = hs_ep->index; | |
5b7d70c6 BD |
4107 | u32 epctrl_reg; |
4108 | u32 ctrl; | |
4109 | ||
1e011293 | 4110 | dev_dbg(hsotg->dev, "%s(ep %p)\n", __func__, ep); |
5b7d70c6 | 4111 | |
c6f5c050 | 4112 | if (ep == &hsotg->eps_out[0]->ep) { |
5b7d70c6 BD |
4113 | dev_err(hsotg->dev, "%s: called for ep0\n", __func__); |
4114 | return -EINVAL; | |
9b481092 JS |
4115 | } |
4116 | ||
4117 | if (hsotg->op_state != OTG_STATE_B_PERIPHERAL) { | |
4118 | dev_err(hsotg->dev, "%s: called in host mode?\n", __func__); | |
4119 | return -EINVAL; | |
5b7d70c6 BD |
4120 | } |
4121 | ||
94cb8fd6 | 4122 | epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index); |
5b7d70c6 | 4123 | |
f25c42b8 | 4124 | ctrl = dwc2_readl(hsotg, epctrl_reg); |
a4f82771 VA |
4125 | |
4126 | if (ctrl & DXEPCTL_EPENA) | |
4127 | dwc2_hsotg_ep_stop_xfr(hsotg, hs_ep); | |
4128 | ||
47a1685f DN |
4129 | ctrl &= ~DXEPCTL_EPENA; |
4130 | ctrl &= ~DXEPCTL_USBACTEP; | |
4131 | ctrl |= DXEPCTL_SNAK; | |
5b7d70c6 BD |
4132 | |
4133 | dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl); | |
f25c42b8 | 4134 | dwc2_writel(hsotg, ctrl, epctrl_reg); |
5b7d70c6 BD |
4135 | |
4136 | /* disable endpoint interrupts */ | |
1f91b4cc | 4137 | dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 0); |
5b7d70c6 | 4138 | |
1141ea01 MYK |
4139 | /* terminate all requests with shutdown */ |
4140 | kill_all_requests(hsotg, hs_ep, -ESHUTDOWN); | |
4141 | ||
1c07b20e RB |
4142 | hsotg->fifo_map &= ~(1 << hs_ep->fifo_index); |
4143 | hs_ep->fifo_index = 0; | |
4144 | hs_ep->fifo_size = 0; | |
4145 | ||
5b7d70c6 BD |
4146 | return 0; |
4147 | } | |
4148 | ||
4fe4f9fe MH |
4149 | static int dwc2_hsotg_ep_disable_lock(struct usb_ep *ep) |
4150 | { | |
4151 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); | |
4152 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
4153 | unsigned long flags; | |
4154 | int ret; | |
4155 | ||
4156 | spin_lock_irqsave(&hsotg->lock, flags); | |
4157 | ret = dwc2_hsotg_ep_disable(ep); | |
4158 | spin_unlock_irqrestore(&hsotg->lock, flags); | |
4159 | return ret; | |
4160 | } | |
4161 | ||
5b7d70c6 BD |
4162 | /** |
4163 | * on_list - check request is on the given endpoint | |
4164 | * @ep: The endpoint to check. | |
4165 | * @test: The request to test if it is on the endpoint. | |
8b9bc460 | 4166 | */ |
1f91b4cc | 4167 | static bool on_list(struct dwc2_hsotg_ep *ep, struct dwc2_hsotg_req *test) |
5b7d70c6 | 4168 | { |
1f91b4cc | 4169 | struct dwc2_hsotg_req *req, *treq; |
5b7d70c6 BD |
4170 | |
4171 | list_for_each_entry_safe(req, treq, &ep->queue, queue) { | |
4172 | if (req == test) | |
4173 | return true; | |
4174 | } | |
4175 | ||
4176 | return false; | |
4177 | } | |
4178 | ||
8b9bc460 | 4179 | /** |
1f91b4cc | 4180 | * dwc2_hsotg_ep_dequeue - dequeue given endpoint |
8b9bc460 LM |
4181 | * @ep: The endpoint to dequeue. |
4182 | * @req: The request to be removed from a queue. | |
4183 | */ | |
1f91b4cc | 4184 | static int dwc2_hsotg_ep_dequeue(struct usb_ep *ep, struct usb_request *req) |
5b7d70c6 | 4185 | { |
1f91b4cc FB |
4186 | struct dwc2_hsotg_req *hs_req = our_req(req); |
4187 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); | |
941fcce4 | 4188 | struct dwc2_hsotg *hs = hs_ep->parent; |
5b7d70c6 BD |
4189 | unsigned long flags; |
4190 | ||
1e011293 | 4191 | dev_dbg(hs->dev, "ep_dequeue(%p,%p)\n", ep, req); |
5b7d70c6 | 4192 | |
22258f49 | 4193 | spin_lock_irqsave(&hs->lock, flags); |
5b7d70c6 BD |
4194 | |
4195 | if (!on_list(hs_ep, hs_req)) { | |
22258f49 | 4196 | spin_unlock_irqrestore(&hs->lock, flags); |
5b7d70c6 BD |
4197 | return -EINVAL; |
4198 | } | |
4199 | ||
c524dd5f MYK |
4200 | /* Dequeue already started request */ |
4201 | if (req == &hs_ep->req->req) | |
4202 | dwc2_hsotg_ep_stop_xfr(hs, hs_ep); | |
4203 | ||
1f91b4cc | 4204 | dwc2_hsotg_complete_request(hs, hs_ep, hs_req, -ECONNRESET); |
22258f49 | 4205 | spin_unlock_irqrestore(&hs->lock, flags); |
5b7d70c6 BD |
4206 | |
4207 | return 0; | |
4208 | } | |
4209 | ||
8b9bc460 | 4210 | /** |
1f91b4cc | 4211 | * dwc2_hsotg_ep_sethalt - set halt on a given endpoint |
8b9bc460 LM |
4212 | * @ep: The endpoint to set halt. |
4213 | * @value: Set or unset the halt. | |
51da43b5 VA |
4214 | * @now: If true, stall the endpoint now. Otherwise return -EAGAIN if |
4215 | * the endpoint is busy processing requests. | |
4216 | * | |
4217 | * We need to stall the endpoint immediately if request comes from set_feature | |
4218 | * protocol command handler. | |
8b9bc460 | 4219 | */ |
51da43b5 | 4220 | static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now) |
5b7d70c6 | 4221 | { |
1f91b4cc | 4222 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 4223 | struct dwc2_hsotg *hs = hs_ep->parent; |
5b7d70c6 | 4224 | int index = hs_ep->index; |
5b7d70c6 BD |
4225 | u32 epreg; |
4226 | u32 epctl; | |
9c39ddc6 | 4227 | u32 xfertype; |
5b7d70c6 BD |
4228 | |
4229 | dev_info(hs->dev, "%s(ep %p %s, %d)\n", __func__, ep, ep->name, value); | |
4230 | ||
c9f721b2 RB |
4231 | if (index == 0) { |
4232 | if (value) | |
1f91b4cc | 4233 | dwc2_hsotg_stall_ep0(hs); |
c9f721b2 RB |
4234 | else |
4235 | dev_warn(hs->dev, | |
4236 | "%s: can't clear halt on ep0\n", __func__); | |
4237 | return 0; | |
4238 | } | |
4239 | ||
15186f10 VA |
4240 | if (hs_ep->isochronous) { |
4241 | dev_err(hs->dev, "%s is Isochronous Endpoint\n", ep->name); | |
4242 | return -EINVAL; | |
4243 | } | |
4244 | ||
51da43b5 VA |
4245 | if (!now && value && !list_empty(&hs_ep->queue)) { |
4246 | dev_dbg(hs->dev, "%s request is pending, cannot halt\n", | |
4247 | ep->name); | |
4248 | return -EAGAIN; | |
4249 | } | |
4250 | ||
c6f5c050 MYK |
4251 | if (hs_ep->dir_in) { |
4252 | epreg = DIEPCTL(index); | |
f25c42b8 | 4253 | epctl = dwc2_readl(hs, epreg); |
c6f5c050 MYK |
4254 | |
4255 | if (value) { | |
5a350d53 | 4256 | epctl |= DXEPCTL_STALL | DXEPCTL_SNAK; |
c6f5c050 MYK |
4257 | if (epctl & DXEPCTL_EPENA) |
4258 | epctl |= DXEPCTL_EPDIS; | |
4259 | } else { | |
4260 | epctl &= ~DXEPCTL_STALL; | |
4261 | xfertype = epctl & DXEPCTL_EPTYPE_MASK; | |
4262 | if (xfertype == DXEPCTL_EPTYPE_BULK || | |
9da51974 | 4263 | xfertype == DXEPCTL_EPTYPE_INTERRUPT) |
77b6200e | 4264 | epctl |= DXEPCTL_SETD0PID; |
c6f5c050 | 4265 | } |
f25c42b8 | 4266 | dwc2_writel(hs, epctl, epreg); |
9c39ddc6 | 4267 | } else { |
c6f5c050 | 4268 | epreg = DOEPCTL(index); |
f25c42b8 | 4269 | epctl = dwc2_readl(hs, epreg); |
5b7d70c6 | 4270 | |
34c0887f | 4271 | if (value) { |
c6f5c050 | 4272 | epctl |= DXEPCTL_STALL; |
34c0887f | 4273 | } else { |
c6f5c050 MYK |
4274 | epctl &= ~DXEPCTL_STALL; |
4275 | xfertype = epctl & DXEPCTL_EPTYPE_MASK; | |
4276 | if (xfertype == DXEPCTL_EPTYPE_BULK || | |
9da51974 | 4277 | xfertype == DXEPCTL_EPTYPE_INTERRUPT) |
77b6200e | 4278 | epctl |= DXEPCTL_SETD0PID; |
c6f5c050 | 4279 | } |
f25c42b8 | 4280 | dwc2_writel(hs, epctl, epreg); |
9c39ddc6 | 4281 | } |
5b7d70c6 | 4282 | |
a18ed7b0 RB |
4283 | hs_ep->halted = value; |
4284 | ||
5b7d70c6 BD |
4285 | return 0; |
4286 | } | |
4287 | ||
5ad1d316 | 4288 | /** |
1f91b4cc | 4289 | * dwc2_hsotg_ep_sethalt_lock - set halt on a given endpoint with lock held |
5ad1d316 LM |
4290 | * @ep: The endpoint to set halt. |
4291 | * @value: Set or unset the halt. | |
4292 | */ | |
1f91b4cc | 4293 | static int dwc2_hsotg_ep_sethalt_lock(struct usb_ep *ep, int value) |
5ad1d316 | 4294 | { |
1f91b4cc | 4295 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 4296 | struct dwc2_hsotg *hs = hs_ep->parent; |
5ad1d316 LM |
4297 | unsigned long flags = 0; |
4298 | int ret = 0; | |
4299 | ||
4300 | spin_lock_irqsave(&hs->lock, flags); | |
51da43b5 | 4301 | ret = dwc2_hsotg_ep_sethalt(ep, value, false); |
5ad1d316 LM |
4302 | spin_unlock_irqrestore(&hs->lock, flags); |
4303 | ||
4304 | return ret; | |
4305 | } | |
4306 | ||
ebce561a | 4307 | static const struct usb_ep_ops dwc2_hsotg_ep_ops = { |
1f91b4cc | 4308 | .enable = dwc2_hsotg_ep_enable, |
4fe4f9fe | 4309 | .disable = dwc2_hsotg_ep_disable_lock, |
1f91b4cc FB |
4310 | .alloc_request = dwc2_hsotg_ep_alloc_request, |
4311 | .free_request = dwc2_hsotg_ep_free_request, | |
4312 | .queue = dwc2_hsotg_ep_queue_lock, | |
4313 | .dequeue = dwc2_hsotg_ep_dequeue, | |
4314 | .set_halt = dwc2_hsotg_ep_sethalt_lock, | |
25985edc | 4315 | /* note, don't believe we have any call for the fifo routines */ |
5b7d70c6 BD |
4316 | }; |
4317 | ||
8b9bc460 | 4318 | /** |
9da51974 | 4319 | * dwc2_hsotg_init - initialize the usb core |
8b9bc460 LM |
4320 | * @hsotg: The driver state |
4321 | */ | |
1f91b4cc | 4322 | static void dwc2_hsotg_init(struct dwc2_hsotg *hsotg) |
b3f489b2 LM |
4323 | { |
4324 | /* unmask subset of endpoint interrupts */ | |
4325 | ||
f25c42b8 | 4326 | dwc2_writel(hsotg, DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK | |
95c8bc36 | 4327 | DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK, |
f25c42b8 | 4328 | DIEPMSK); |
b3f489b2 | 4329 | |
f25c42b8 | 4330 | dwc2_writel(hsotg, DOEPMSK_SETUPMSK | DOEPMSK_AHBERRMSK | |
95c8bc36 | 4331 | DOEPMSK_EPDISBLDMSK | DOEPMSK_XFERCOMPLMSK, |
f25c42b8 | 4332 | DOEPMSK); |
b3f489b2 | 4333 | |
f25c42b8 | 4334 | dwc2_writel(hsotg, 0, DAINTMSK); |
b3f489b2 LM |
4335 | |
4336 | /* Be in disconnected state until gadget is registered */ | |
f25c42b8 | 4337 | dwc2_set_bit(hsotg, DCTL, DCTL_SFTDISCON); |
b3f489b2 | 4338 | |
b3f489b2 LM |
4339 | /* setup fifos */ |
4340 | ||
4341 | dev_dbg(hsotg->dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n", | |
f25c42b8 GS |
4342 | dwc2_readl(hsotg, GRXFSIZ), |
4343 | dwc2_readl(hsotg, GNPTXFSIZ)); | |
b3f489b2 | 4344 | |
1f91b4cc | 4345 | dwc2_hsotg_init_fifo(hsotg); |
b3f489b2 | 4346 | |
f5090044 | 4347 | if (using_dma(hsotg)) |
f25c42b8 | 4348 | dwc2_set_bit(hsotg, GAHBCFG, GAHBCFG_DMA_EN); |
b3f489b2 LM |
4349 | } |
4350 | ||
8b9bc460 | 4351 | /** |
1f91b4cc | 4352 | * dwc2_hsotg_udc_start - prepare the udc for work |
8b9bc460 LM |
4353 | * @gadget: The usb gadget state |
4354 | * @driver: The usb gadget driver | |
4355 | * | |
4356 | * Perform initialization to prepare udc device and driver | |
4357 | * to work. | |
4358 | */ | |
1f91b4cc | 4359 | static int dwc2_hsotg_udc_start(struct usb_gadget *gadget, |
9da51974 | 4360 | struct usb_gadget_driver *driver) |
5b7d70c6 | 4361 | { |
941fcce4 | 4362 | struct dwc2_hsotg *hsotg = to_hsotg(gadget); |
5b9451f8 | 4363 | unsigned long flags; |
5b7d70c6 BD |
4364 | int ret; |
4365 | ||
4366 | if (!hsotg) { | |
a023da33 | 4367 | pr_err("%s: called with no device\n", __func__); |
5b7d70c6 BD |
4368 | return -ENODEV; |
4369 | } | |
4370 | ||
4371 | if (!driver) { | |
4372 | dev_err(hsotg->dev, "%s: no driver\n", __func__); | |
4373 | return -EINVAL; | |
4374 | } | |
4375 | ||
7177aed4 | 4376 | if (driver->max_speed < USB_SPEED_FULL) |
5b7d70c6 | 4377 | dev_err(hsotg->dev, "%s: bad speed\n", __func__); |
5b7d70c6 | 4378 | |
f65f0f10 | 4379 | if (!driver->setup) { |
5b7d70c6 BD |
4380 | dev_err(hsotg->dev, "%s: missing entry points\n", __func__); |
4381 | return -EINVAL; | |
4382 | } | |
4383 | ||
4384 | WARN_ON(hsotg->driver); | |
4385 | ||
4386 | driver->driver.bus = NULL; | |
4387 | hsotg->driver = driver; | |
7d7b2292 | 4388 | hsotg->gadget.dev.of_node = hsotg->dev->of_node; |
5b7d70c6 BD |
4389 | hsotg->gadget.speed = USB_SPEED_UNKNOWN; |
4390 | ||
09a75e85 MS |
4391 | if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) { |
4392 | ret = dwc2_lowlevel_hw_enable(hsotg); | |
4393 | if (ret) | |
4394 | goto err; | |
5b7d70c6 BD |
4395 | } |
4396 | ||
f6c01592 GH |
4397 | if (!IS_ERR_OR_NULL(hsotg->uphy)) |
4398 | otg_set_peripheral(hsotg->uphy->otg, &hsotg->gadget); | |
c816c47f | 4399 | |
5b9451f8 | 4400 | spin_lock_irqsave(&hsotg->lock, flags); |
d0f0ac56 JY |
4401 | if (dwc2_hw_is_device(hsotg)) { |
4402 | dwc2_hsotg_init(hsotg); | |
4403 | dwc2_hsotg_core_init_disconnected(hsotg, false); | |
4404 | } | |
4405 | ||
dc6e69e6 | 4406 | hsotg->enabled = 0; |
5b9451f8 MS |
4407 | spin_unlock_irqrestore(&hsotg->lock, flags); |
4408 | ||
10209abe | 4409 | gadget->sg_supported = using_desc_dma(hsotg); |
5b7d70c6 | 4410 | dev_info(hsotg->dev, "bound driver %s\n", driver->driver.name); |
5b9451f8 | 4411 | |
5b7d70c6 BD |
4412 | return 0; |
4413 | ||
4414 | err: | |
4415 | hsotg->driver = NULL; | |
5b7d70c6 BD |
4416 | return ret; |
4417 | } | |
4418 | ||
8b9bc460 | 4419 | /** |
1f91b4cc | 4420 | * dwc2_hsotg_udc_stop - stop the udc |
8b9bc460 | 4421 | * @gadget: The usb gadget state |
8b9bc460 LM |
4422 | * |
4423 | * Stop udc hw block and stay tunned for future transmissions | |
4424 | */ | |
1f91b4cc | 4425 | static int dwc2_hsotg_udc_stop(struct usb_gadget *gadget) |
5b7d70c6 | 4426 | { |
941fcce4 | 4427 | struct dwc2_hsotg *hsotg = to_hsotg(gadget); |
2b19a52c | 4428 | unsigned long flags = 0; |
5b7d70c6 BD |
4429 | int ep; |
4430 | ||
4431 | if (!hsotg) | |
4432 | return -ENODEV; | |
4433 | ||
5b7d70c6 | 4434 | /* all endpoints should be shutdown */ |
c6f5c050 MYK |
4435 | for (ep = 1; ep < hsotg->num_of_eps; ep++) { |
4436 | if (hsotg->eps_in[ep]) | |
4fe4f9fe | 4437 | dwc2_hsotg_ep_disable_lock(&hsotg->eps_in[ep]->ep); |
c6f5c050 | 4438 | if (hsotg->eps_out[ep]) |
4fe4f9fe | 4439 | dwc2_hsotg_ep_disable_lock(&hsotg->eps_out[ep]->ep); |
c6f5c050 | 4440 | } |
5b7d70c6 | 4441 | |
2b19a52c LM |
4442 | spin_lock_irqsave(&hsotg->lock, flags); |
4443 | ||
32805c35 | 4444 | hsotg->driver = NULL; |
5b7d70c6 | 4445 | hsotg->gadget.speed = USB_SPEED_UNKNOWN; |
dc6e69e6 | 4446 | hsotg->enabled = 0; |
5b7d70c6 | 4447 | |
2b19a52c LM |
4448 | spin_unlock_irqrestore(&hsotg->lock, flags); |
4449 | ||
f6c01592 GH |
4450 | if (!IS_ERR_OR_NULL(hsotg->uphy)) |
4451 | otg_set_peripheral(hsotg->uphy->otg, NULL); | |
c816c47f | 4452 | |
09a75e85 MS |
4453 | if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) |
4454 | dwc2_lowlevel_hw_disable(hsotg); | |
5b7d70c6 BD |
4455 | |
4456 | return 0; | |
4457 | } | |
5b7d70c6 | 4458 | |
8b9bc460 | 4459 | /** |
1f91b4cc | 4460 | * dwc2_hsotg_gadget_getframe - read the frame number |
8b9bc460 LM |
4461 | * @gadget: The usb gadget state |
4462 | * | |
4463 | * Read the {micro} frame number | |
4464 | */ | |
1f91b4cc | 4465 | static int dwc2_hsotg_gadget_getframe(struct usb_gadget *gadget) |
5b7d70c6 | 4466 | { |
1f91b4cc | 4467 | return dwc2_hsotg_read_frameno(to_hsotg(gadget)); |
5b7d70c6 BD |
4468 | } |
4469 | ||
a188b689 | 4470 | /** |
1f91b4cc | 4471 | * dwc2_hsotg_pullup - connect/disconnect the USB PHY |
a188b689 LM |
4472 | * @gadget: The usb gadget state |
4473 | * @is_on: Current state of the USB PHY | |
4474 | * | |
4475 | * Connect/Disconnect the USB PHY pullup | |
4476 | */ | |
1f91b4cc | 4477 | static int dwc2_hsotg_pullup(struct usb_gadget *gadget, int is_on) |
a188b689 | 4478 | { |
941fcce4 | 4479 | struct dwc2_hsotg *hsotg = to_hsotg(gadget); |
a188b689 LM |
4480 | unsigned long flags = 0; |
4481 | ||
77ba9119 | 4482 | dev_dbg(hsotg->dev, "%s: is_on: %d op_state: %d\n", __func__, is_on, |
9da51974 | 4483 | hsotg->op_state); |
77ba9119 GH |
4484 | |
4485 | /* Don't modify pullup state while in host mode */ | |
4486 | if (hsotg->op_state != OTG_STATE_B_PERIPHERAL) { | |
4487 | hsotg->enabled = is_on; | |
4488 | return 0; | |
4489 | } | |
a188b689 LM |
4490 | |
4491 | spin_lock_irqsave(&hsotg->lock, flags); | |
4492 | if (is_on) { | |
dc6e69e6 | 4493 | hsotg->enabled = 1; |
1f91b4cc | 4494 | dwc2_hsotg_core_init_disconnected(hsotg, false); |
66e77a24 RK |
4495 | /* Enable ACG feature in device mode,if supported */ |
4496 | dwc2_enable_acg(hsotg); | |
1f91b4cc | 4497 | dwc2_hsotg_core_connect(hsotg); |
a188b689 | 4498 | } else { |
1f91b4cc FB |
4499 | dwc2_hsotg_core_disconnect(hsotg); |
4500 | dwc2_hsotg_disconnect(hsotg); | |
dc6e69e6 | 4501 | hsotg->enabled = 0; |
a188b689 LM |
4502 | } |
4503 | ||
4504 | hsotg->gadget.speed = USB_SPEED_UNKNOWN; | |
4505 | spin_unlock_irqrestore(&hsotg->lock, flags); | |
4506 | ||
4507 | return 0; | |
4508 | } | |
4509 | ||
1f91b4cc | 4510 | static int dwc2_hsotg_vbus_session(struct usb_gadget *gadget, int is_active) |
83d98223 GH |
4511 | { |
4512 | struct dwc2_hsotg *hsotg = to_hsotg(gadget); | |
4513 | unsigned long flags; | |
4514 | ||
4515 | dev_dbg(hsotg->dev, "%s: is_active: %d\n", __func__, is_active); | |
4516 | spin_lock_irqsave(&hsotg->lock, flags); | |
4517 | ||
61f7223b | 4518 | /* |
41ba9b9b | 4519 | * If controller is hibernated, it must exit from power_down |
61f7223b GH |
4520 | * before being initialized / de-initialized |
4521 | */ | |
4522 | if (hsotg->lx_state == DWC2_L2) | |
41ba9b9b | 4523 | dwc2_exit_partial_power_down(hsotg, false); |
61f7223b | 4524 | |
83d98223 | 4525 | if (is_active) { |
cd0e641c | 4526 | hsotg->op_state = OTG_STATE_B_PERIPHERAL; |
065d3931 | 4527 | |
1f91b4cc | 4528 | dwc2_hsotg_core_init_disconnected(hsotg, false); |
66e77a24 RK |
4529 | if (hsotg->enabled) { |
4530 | /* Enable ACG feature in device mode,if supported */ | |
4531 | dwc2_enable_acg(hsotg); | |
1f91b4cc | 4532 | dwc2_hsotg_core_connect(hsotg); |
66e77a24 | 4533 | } |
83d98223 | 4534 | } else { |
1f91b4cc FB |
4535 | dwc2_hsotg_core_disconnect(hsotg); |
4536 | dwc2_hsotg_disconnect(hsotg); | |
83d98223 GH |
4537 | } |
4538 | ||
4539 | spin_unlock_irqrestore(&hsotg->lock, flags); | |
4540 | return 0; | |
4541 | } | |
4542 | ||
596d696a | 4543 | /** |
1f91b4cc | 4544 | * dwc2_hsotg_vbus_draw - report bMaxPower field |
596d696a GH |
4545 | * @gadget: The usb gadget state |
4546 | * @mA: Amount of current | |
4547 | * | |
4548 | * Report how much power the device may consume to the phy. | |
4549 | */ | |
9da51974 | 4550 | static int dwc2_hsotg_vbus_draw(struct usb_gadget *gadget, unsigned int mA) |
596d696a GH |
4551 | { |
4552 | struct dwc2_hsotg *hsotg = to_hsotg(gadget); | |
4553 | ||
4554 | if (IS_ERR_OR_NULL(hsotg->uphy)) | |
4555 | return -ENOTSUPP; | |
4556 | return usb_phy_set_power(hsotg->uphy, mA); | |
4557 | } | |
4558 | ||
1f91b4cc FB |
4559 | static const struct usb_gadget_ops dwc2_hsotg_gadget_ops = { |
4560 | .get_frame = dwc2_hsotg_gadget_getframe, | |
4561 | .udc_start = dwc2_hsotg_udc_start, | |
4562 | .udc_stop = dwc2_hsotg_udc_stop, | |
4563 | .pullup = dwc2_hsotg_pullup, | |
4564 | .vbus_session = dwc2_hsotg_vbus_session, | |
4565 | .vbus_draw = dwc2_hsotg_vbus_draw, | |
5b7d70c6 BD |
4566 | }; |
4567 | ||
4568 | /** | |
1f91b4cc | 4569 | * dwc2_hsotg_initep - initialise a single endpoint |
5b7d70c6 BD |
4570 | * @hsotg: The device state. |
4571 | * @hs_ep: The endpoint to be initialised. | |
4572 | * @epnum: The endpoint number | |
6fb914d7 | 4573 | * @dir_in: True if direction is in. |
5b7d70c6 BD |
4574 | * |
4575 | * Initialise the given endpoint (as part of the probe and device state | |
4576 | * creation) to give to the gadget driver. Setup the endpoint name, any | |
4577 | * direction information and other state that may be required. | |
4578 | */ | |
1f91b4cc | 4579 | static void dwc2_hsotg_initep(struct dwc2_hsotg *hsotg, |
9da51974 | 4580 | struct dwc2_hsotg_ep *hs_ep, |
c6f5c050 MYK |
4581 | int epnum, |
4582 | bool dir_in) | |
5b7d70c6 | 4583 | { |
5b7d70c6 BD |
4584 | char *dir; |
4585 | ||
4586 | if (epnum == 0) | |
4587 | dir = ""; | |
c6f5c050 | 4588 | else if (dir_in) |
5b7d70c6 | 4589 | dir = "in"; |
c6f5c050 MYK |
4590 | else |
4591 | dir = "out"; | |
5b7d70c6 | 4592 | |
c6f5c050 | 4593 | hs_ep->dir_in = dir_in; |
5b7d70c6 BD |
4594 | hs_ep->index = epnum; |
4595 | ||
4596 | snprintf(hs_ep->name, sizeof(hs_ep->name), "ep%d%s", epnum, dir); | |
4597 | ||
4598 | INIT_LIST_HEAD(&hs_ep->queue); | |
4599 | INIT_LIST_HEAD(&hs_ep->ep.ep_list); | |
4600 | ||
5b7d70c6 BD |
4601 | /* add to the list of endpoints known by the gadget driver */ |
4602 | if (epnum) | |
4603 | list_add_tail(&hs_ep->ep.ep_list, &hsotg->gadget.ep_list); | |
4604 | ||
4605 | hs_ep->parent = hsotg; | |
4606 | hs_ep->ep.name = hs_ep->name; | |
38e9002b VM |
4607 | |
4608 | if (hsotg->params.speed == DWC2_SPEED_PARAM_LOW) | |
4609 | usb_ep_set_maxpacket_limit(&hs_ep->ep, 8); | |
4610 | else | |
4611 | usb_ep_set_maxpacket_limit(&hs_ep->ep, | |
4612 | epnum ? 1024 : EP0_MPS_LIMIT); | |
1f91b4cc | 4613 | hs_ep->ep.ops = &dwc2_hsotg_ep_ops; |
5b7d70c6 | 4614 | |
2954522f RB |
4615 | if (epnum == 0) { |
4616 | hs_ep->ep.caps.type_control = true; | |
4617 | } else { | |
38e9002b VM |
4618 | if (hsotg->params.speed != DWC2_SPEED_PARAM_LOW) { |
4619 | hs_ep->ep.caps.type_iso = true; | |
4620 | hs_ep->ep.caps.type_bulk = true; | |
4621 | } | |
2954522f RB |
4622 | hs_ep->ep.caps.type_int = true; |
4623 | } | |
4624 | ||
4625 | if (dir_in) | |
4626 | hs_ep->ep.caps.dir_in = true; | |
4627 | else | |
4628 | hs_ep->ep.caps.dir_out = true; | |
4629 | ||
8b9bc460 LM |
4630 | /* |
4631 | * if we're using dma, we need to set the next-endpoint pointer | |
5b7d70c6 BD |
4632 | * to be something valid. |
4633 | */ | |
4634 | ||
4635 | if (using_dma(hsotg)) { | |
47a1685f | 4636 | u32 next = DXEPCTL_NEXTEP((epnum + 1) % 15); |
9da51974 | 4637 | |
c6f5c050 | 4638 | if (dir_in) |
f25c42b8 | 4639 | dwc2_writel(hsotg, next, DIEPCTL(epnum)); |
c6f5c050 | 4640 | else |
f25c42b8 | 4641 | dwc2_writel(hsotg, next, DOEPCTL(epnum)); |
5b7d70c6 BD |
4642 | } |
4643 | } | |
4644 | ||
b3f489b2 | 4645 | /** |
1f91b4cc | 4646 | * dwc2_hsotg_hw_cfg - read HW configuration registers |
6fb914d7 | 4647 | * @hsotg: Programming view of the DWC_otg controller |
b3f489b2 LM |
4648 | * |
4649 | * Read the USB core HW configuration registers | |
4650 | */ | |
1f91b4cc | 4651 | static int dwc2_hsotg_hw_cfg(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 4652 | { |
c6f5c050 MYK |
4653 | u32 cfg; |
4654 | u32 ep_type; | |
4655 | u32 i; | |
4656 | ||
b3f489b2 | 4657 | /* check hardware configuration */ |
5b7d70c6 | 4658 | |
43e90349 JY |
4659 | hsotg->num_of_eps = hsotg->hw_params.num_dev_ep; |
4660 | ||
c6f5c050 MYK |
4661 | /* Add ep0 */ |
4662 | hsotg->num_of_eps++; | |
10aebc77 | 4663 | |
b98866c2 JY |
4664 | hsotg->eps_in[0] = devm_kzalloc(hsotg->dev, |
4665 | sizeof(struct dwc2_hsotg_ep), | |
4666 | GFP_KERNEL); | |
c6f5c050 MYK |
4667 | if (!hsotg->eps_in[0]) |
4668 | return -ENOMEM; | |
1f91b4cc | 4669 | /* Same dwc2_hsotg_ep is used in both directions for ep0 */ |
c6f5c050 MYK |
4670 | hsotg->eps_out[0] = hsotg->eps_in[0]; |
4671 | ||
43e90349 | 4672 | cfg = hsotg->hw_params.dev_ep_dirs; |
251a17f5 | 4673 | for (i = 1, cfg >>= 2; i < hsotg->num_of_eps; i++, cfg >>= 2) { |
c6f5c050 MYK |
4674 | ep_type = cfg & 3; |
4675 | /* Direction in or both */ | |
4676 | if (!(ep_type & 2)) { | |
4677 | hsotg->eps_in[i] = devm_kzalloc(hsotg->dev, | |
1f91b4cc | 4678 | sizeof(struct dwc2_hsotg_ep), GFP_KERNEL); |
c6f5c050 MYK |
4679 | if (!hsotg->eps_in[i]) |
4680 | return -ENOMEM; | |
4681 | } | |
4682 | /* Direction out or both */ | |
4683 | if (!(ep_type & 1)) { | |
4684 | hsotg->eps_out[i] = devm_kzalloc(hsotg->dev, | |
1f91b4cc | 4685 | sizeof(struct dwc2_hsotg_ep), GFP_KERNEL); |
c6f5c050 MYK |
4686 | if (!hsotg->eps_out[i]) |
4687 | return -ENOMEM; | |
4688 | } | |
4689 | } | |
4690 | ||
43e90349 JY |
4691 | hsotg->fifo_mem = hsotg->hw_params.total_fifo_size; |
4692 | hsotg->dedicated_fifos = hsotg->hw_params.en_multiple_tx_fifo; | |
10aebc77 | 4693 | |
cff9eb75 MS |
4694 | dev_info(hsotg->dev, "EPs: %d, %s fifos, %d entries in SPRAM\n", |
4695 | hsotg->num_of_eps, | |
4696 | hsotg->dedicated_fifos ? "dedicated" : "shared", | |
4697 | hsotg->fifo_mem); | |
c6f5c050 | 4698 | return 0; |
5b7d70c6 BD |
4699 | } |
4700 | ||
8b9bc460 | 4701 | /** |
1f91b4cc | 4702 | * dwc2_hsotg_dump - dump state of the udc |
6fb914d7 GT |
4703 | * @hsotg: Programming view of the DWC_otg controller |
4704 | * | |
8b9bc460 | 4705 | */ |
1f91b4cc | 4706 | static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 4707 | { |
83a01804 | 4708 | #ifdef DEBUG |
5b7d70c6 | 4709 | struct device *dev = hsotg->dev; |
5b7d70c6 BD |
4710 | u32 val; |
4711 | int idx; | |
4712 | ||
4713 | dev_info(dev, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n", | |
f25c42b8 GS |
4714 | dwc2_readl(hsotg, DCFG), dwc2_readl(hsotg, DCTL), |
4715 | dwc2_readl(hsotg, DIEPMSK)); | |
5b7d70c6 | 4716 | |
f889f23d | 4717 | dev_info(dev, "GAHBCFG=0x%08x, GHWCFG1=0x%08x\n", |
f25c42b8 | 4718 | dwc2_readl(hsotg, GAHBCFG), dwc2_readl(hsotg, GHWCFG1)); |
5b7d70c6 BD |
4719 | |
4720 | dev_info(dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n", | |
f25c42b8 | 4721 | dwc2_readl(hsotg, GRXFSIZ), dwc2_readl(hsotg, GNPTXFSIZ)); |
5b7d70c6 BD |
4722 | |
4723 | /* show periodic fifo settings */ | |
4724 | ||
364f8e93 | 4725 | for (idx = 1; idx < hsotg->num_of_eps; idx++) { |
f25c42b8 | 4726 | val = dwc2_readl(hsotg, DPTXFSIZN(idx)); |
5b7d70c6 | 4727 | dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx, |
47a1685f DN |
4728 | val >> FIFOSIZE_DEPTH_SHIFT, |
4729 | val & FIFOSIZE_STARTADDR_MASK); | |
5b7d70c6 BD |
4730 | } |
4731 | ||
364f8e93 | 4732 | for (idx = 0; idx < hsotg->num_of_eps; idx++) { |
5b7d70c6 BD |
4733 | dev_info(dev, |
4734 | "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx, | |
f25c42b8 GS |
4735 | dwc2_readl(hsotg, DIEPCTL(idx)), |
4736 | dwc2_readl(hsotg, DIEPTSIZ(idx)), | |
4737 | dwc2_readl(hsotg, DIEPDMA(idx))); | |
5b7d70c6 | 4738 | |
f25c42b8 | 4739 | val = dwc2_readl(hsotg, DOEPCTL(idx)); |
5b7d70c6 BD |
4740 | dev_info(dev, |
4741 | "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", | |
f25c42b8 GS |
4742 | idx, dwc2_readl(hsotg, DOEPCTL(idx)), |
4743 | dwc2_readl(hsotg, DOEPTSIZ(idx)), | |
4744 | dwc2_readl(hsotg, DOEPDMA(idx))); | |
5b7d70c6 BD |
4745 | } |
4746 | ||
4747 | dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n", | |
f25c42b8 | 4748 | dwc2_readl(hsotg, DVBUSDIS), dwc2_readl(hsotg, DVBUSPULSE)); |
83a01804 | 4749 | #endif |
5b7d70c6 BD |
4750 | } |
4751 | ||
8b9bc460 | 4752 | /** |
117777b2 | 4753 | * dwc2_gadget_init - init function for gadget |
6fb914d7 GT |
4754 | * @hsotg: Programming view of the DWC_otg controller |
4755 | * | |
8b9bc460 | 4756 | */ |
f3768997 | 4757 | int dwc2_gadget_init(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 4758 | { |
117777b2 | 4759 | struct device *dev = hsotg->dev; |
5b7d70c6 BD |
4760 | int epnum; |
4761 | int ret; | |
43e90349 | 4762 | |
0a176279 GH |
4763 | /* Dump fifo information */ |
4764 | dev_dbg(dev, "NonPeriodic TXFIFO size: %d\n", | |
05ee799f JY |
4765 | hsotg->params.g_np_tx_fifo_size); |
4766 | dev_dbg(dev, "RXFIFO size: %d\n", hsotg->params.g_rx_fifo_size); | |
5b7d70c6 | 4767 | |
d327ab5b | 4768 | hsotg->gadget.max_speed = USB_SPEED_HIGH; |
1f91b4cc | 4769 | hsotg->gadget.ops = &dwc2_hsotg_gadget_ops; |
5b7d70c6 | 4770 | hsotg->gadget.name = dev_name(dev); |
fa389a6d | 4771 | hsotg->remote_wakeup_allowed = 0; |
7455f8b7 JY |
4772 | |
4773 | if (hsotg->params.lpm) | |
4774 | hsotg->gadget.lpm_capable = true; | |
4775 | ||
097ee662 GH |
4776 | if (hsotg->dr_mode == USB_DR_MODE_OTG) |
4777 | hsotg->gadget.is_otg = 1; | |
ec4cc657 MYK |
4778 | else if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) |
4779 | hsotg->op_state = OTG_STATE_B_PERIPHERAL; | |
5b7d70c6 | 4780 | |
1f91b4cc | 4781 | ret = dwc2_hsotg_hw_cfg(hsotg); |
c6f5c050 MYK |
4782 | if (ret) { |
4783 | dev_err(hsotg->dev, "Hardware configuration failed: %d\n", ret); | |
09a75e85 | 4784 | return ret; |
c6f5c050 MYK |
4785 | } |
4786 | ||
3f95001d MYK |
4787 | hsotg->ctrl_buff = devm_kzalloc(hsotg->dev, |
4788 | DWC2_CTRL_BUFF_SIZE, GFP_KERNEL); | |
8bae0f8c | 4789 | if (!hsotg->ctrl_buff) |
09a75e85 | 4790 | return -ENOMEM; |
3f95001d MYK |
4791 | |
4792 | hsotg->ep0_buff = devm_kzalloc(hsotg->dev, | |
4793 | DWC2_CTRL_BUFF_SIZE, GFP_KERNEL); | |
8bae0f8c | 4794 | if (!hsotg->ep0_buff) |
09a75e85 | 4795 | return -ENOMEM; |
3f95001d | 4796 | |
0f6b80c0 VA |
4797 | if (using_desc_dma(hsotg)) { |
4798 | ret = dwc2_gadget_alloc_ctrl_desc_chains(hsotg); | |
4799 | if (ret < 0) | |
4800 | return ret; | |
4801 | } | |
4802 | ||
f3768997 VM |
4803 | ret = devm_request_irq(hsotg->dev, hsotg->irq, dwc2_hsotg_irq, |
4804 | IRQF_SHARED, dev_name(hsotg->dev), hsotg); | |
eb3c56c5 | 4805 | if (ret < 0) { |
db8178c3 | 4806 | dev_err(dev, "cannot claim IRQ for gadget\n"); |
09a75e85 | 4807 | return ret; |
eb3c56c5 MS |
4808 | } |
4809 | ||
b3f489b2 LM |
4810 | /* hsotg->num_of_eps holds number of EPs other than ep0 */ |
4811 | ||
4812 | if (hsotg->num_of_eps == 0) { | |
4813 | dev_err(dev, "wrong number of EPs (zero)\n"); | |
09a75e85 | 4814 | return -EINVAL; |
b3f489b2 LM |
4815 | } |
4816 | ||
b3f489b2 LM |
4817 | /* setup endpoint information */ |
4818 | ||
4819 | INIT_LIST_HEAD(&hsotg->gadget.ep_list); | |
c6f5c050 | 4820 | hsotg->gadget.ep0 = &hsotg->eps_out[0]->ep; |
b3f489b2 LM |
4821 | |
4822 | /* allocate EP0 request */ | |
4823 | ||
1f91b4cc | 4824 | hsotg->ctrl_req = dwc2_hsotg_ep_alloc_request(&hsotg->eps_out[0]->ep, |
b3f489b2 LM |
4825 | GFP_KERNEL); |
4826 | if (!hsotg->ctrl_req) { | |
4827 | dev_err(dev, "failed to allocate ctrl req\n"); | |
09a75e85 | 4828 | return -ENOMEM; |
b3f489b2 | 4829 | } |
5b7d70c6 BD |
4830 | |
4831 | /* initialise the endpoints now the core has been initialised */ | |
c6f5c050 MYK |
4832 | for (epnum = 0; epnum < hsotg->num_of_eps; epnum++) { |
4833 | if (hsotg->eps_in[epnum]) | |
1f91b4cc | 4834 | dwc2_hsotg_initep(hsotg, hsotg->eps_in[epnum], |
9da51974 | 4835 | epnum, 1); |
c6f5c050 | 4836 | if (hsotg->eps_out[epnum]) |
1f91b4cc | 4837 | dwc2_hsotg_initep(hsotg, hsotg->eps_out[epnum], |
9da51974 | 4838 | epnum, 0); |
c6f5c050 | 4839 | } |
5b7d70c6 | 4840 | |
117777b2 | 4841 | ret = usb_add_gadget_udc(dev, &hsotg->gadget); |
9bb073a0 GT |
4842 | if (ret) { |
4843 | dwc2_hsotg_ep_free_request(&hsotg->eps_out[0]->ep, | |
4844 | hsotg->ctrl_req); | |
09a75e85 | 4845 | return ret; |
9bb073a0 | 4846 | } |
1f91b4cc | 4847 | dwc2_hsotg_dump(hsotg); |
5b7d70c6 | 4848 | |
5b7d70c6 | 4849 | return 0; |
5b7d70c6 BD |
4850 | } |
4851 | ||
8b9bc460 | 4852 | /** |
1f91b4cc | 4853 | * dwc2_hsotg_remove - remove function for hsotg driver |
6fb914d7 GT |
4854 | * @hsotg: Programming view of the DWC_otg controller |
4855 | * | |
8b9bc460 | 4856 | */ |
1f91b4cc | 4857 | int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 4858 | { |
0f91349b | 4859 | usb_del_gadget_udc(&hsotg->gadget); |
9bb073a0 | 4860 | dwc2_hsotg_ep_free_request(&hsotg->eps_out[0]->ep, hsotg->ctrl_req); |
31ee04de | 4861 | |
5b7d70c6 BD |
4862 | return 0; |
4863 | } | |
4864 | ||
1f91b4cc | 4865 | int dwc2_hsotg_suspend(struct dwc2_hsotg *hsotg) |
b83e333a | 4866 | { |
b83e333a | 4867 | unsigned long flags; |
b83e333a | 4868 | |
9e779778 | 4869 | if (hsotg->lx_state != DWC2_L0) |
09a75e85 | 4870 | return 0; |
9e779778 | 4871 | |
dc6e69e6 MS |
4872 | if (hsotg->driver) { |
4873 | int ep; | |
4874 | ||
b83e333a MS |
4875 | dev_info(hsotg->dev, "suspending usb gadget %s\n", |
4876 | hsotg->driver->driver.name); | |
4877 | ||
dc6e69e6 MS |
4878 | spin_lock_irqsave(&hsotg->lock, flags); |
4879 | if (hsotg->enabled) | |
1f91b4cc FB |
4880 | dwc2_hsotg_core_disconnect(hsotg); |
4881 | dwc2_hsotg_disconnect(hsotg); | |
dc6e69e6 MS |
4882 | hsotg->gadget.speed = USB_SPEED_UNKNOWN; |
4883 | spin_unlock_irqrestore(&hsotg->lock, flags); | |
b83e333a | 4884 | |
c6f5c050 MYK |
4885 | for (ep = 0; ep < hsotg->num_of_eps; ep++) { |
4886 | if (hsotg->eps_in[ep]) | |
4fe4f9fe | 4887 | dwc2_hsotg_ep_disable_lock(&hsotg->eps_in[ep]->ep); |
c6f5c050 | 4888 | if (hsotg->eps_out[ep]) |
4fe4f9fe | 4889 | dwc2_hsotg_ep_disable_lock(&hsotg->eps_out[ep]->ep); |
c6f5c050 | 4890 | } |
b83e333a MS |
4891 | } |
4892 | ||
09a75e85 | 4893 | return 0; |
b83e333a MS |
4894 | } |
4895 | ||
1f91b4cc | 4896 | int dwc2_hsotg_resume(struct dwc2_hsotg *hsotg) |
b83e333a | 4897 | { |
b83e333a | 4898 | unsigned long flags; |
b83e333a | 4899 | |
9e779778 | 4900 | if (hsotg->lx_state == DWC2_L2) |
09a75e85 | 4901 | return 0; |
9e779778 | 4902 | |
b83e333a MS |
4903 | if (hsotg->driver) { |
4904 | dev_info(hsotg->dev, "resuming usb gadget %s\n", | |
4905 | hsotg->driver->driver.name); | |
d00b4142 | 4906 | |
dc6e69e6 | 4907 | spin_lock_irqsave(&hsotg->lock, flags); |
1f91b4cc | 4908 | dwc2_hsotg_core_init_disconnected(hsotg, false); |
66e77a24 RK |
4909 | if (hsotg->enabled) { |
4910 | /* Enable ACG feature in device mode,if supported */ | |
4911 | dwc2_enable_acg(hsotg); | |
1f91b4cc | 4912 | dwc2_hsotg_core_connect(hsotg); |
66e77a24 | 4913 | } |
dc6e69e6 MS |
4914 | spin_unlock_irqrestore(&hsotg->lock, flags); |
4915 | } | |
b83e333a | 4916 | |
09a75e85 | 4917 | return 0; |
b83e333a | 4918 | } |
58e52ff6 JY |
4919 | |
4920 | /** | |
4921 | * dwc2_backup_device_registers() - Backup controller device registers. | |
4922 | * When suspending usb bus, registers needs to be backuped | |
4923 | * if controller power is disabled once suspended. | |
4924 | * | |
4925 | * @hsotg: Programming view of the DWC_otg controller | |
4926 | */ | |
4927 | int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg) | |
4928 | { | |
4929 | struct dwc2_dregs_backup *dr; | |
4930 | int i; | |
4931 | ||
4932 | dev_dbg(hsotg->dev, "%s\n", __func__); | |
4933 | ||
4934 | /* Backup dev regs */ | |
4935 | dr = &hsotg->dr_backup; | |
4936 | ||
f25c42b8 GS |
4937 | dr->dcfg = dwc2_readl(hsotg, DCFG); |
4938 | dr->dctl = dwc2_readl(hsotg, DCTL); | |
4939 | dr->daintmsk = dwc2_readl(hsotg, DAINTMSK); | |
4940 | dr->diepmsk = dwc2_readl(hsotg, DIEPMSK); | |
4941 | dr->doepmsk = dwc2_readl(hsotg, DOEPMSK); | |
58e52ff6 JY |
4942 | |
4943 | for (i = 0; i < hsotg->num_of_eps; i++) { | |
4944 | /* Backup IN EPs */ | |
f25c42b8 | 4945 | dr->diepctl[i] = dwc2_readl(hsotg, DIEPCTL(i)); |
58e52ff6 JY |
4946 | |
4947 | /* Ensure DATA PID is correctly configured */ | |
4948 | if (dr->diepctl[i] & DXEPCTL_DPID) | |
4949 | dr->diepctl[i] |= DXEPCTL_SETD1PID; | |
4950 | else | |
4951 | dr->diepctl[i] |= DXEPCTL_SETD0PID; | |
4952 | ||
f25c42b8 GS |
4953 | dr->dieptsiz[i] = dwc2_readl(hsotg, DIEPTSIZ(i)); |
4954 | dr->diepdma[i] = dwc2_readl(hsotg, DIEPDMA(i)); | |
58e52ff6 JY |
4955 | |
4956 | /* Backup OUT EPs */ | |
f25c42b8 | 4957 | dr->doepctl[i] = dwc2_readl(hsotg, DOEPCTL(i)); |
58e52ff6 JY |
4958 | |
4959 | /* Ensure DATA PID is correctly configured */ | |
4960 | if (dr->doepctl[i] & DXEPCTL_DPID) | |
4961 | dr->doepctl[i] |= DXEPCTL_SETD1PID; | |
4962 | else | |
4963 | dr->doepctl[i] |= DXEPCTL_SETD0PID; | |
4964 | ||
f25c42b8 GS |
4965 | dr->doeptsiz[i] = dwc2_readl(hsotg, DOEPTSIZ(i)); |
4966 | dr->doepdma[i] = dwc2_readl(hsotg, DOEPDMA(i)); | |
4967 | dr->dtxfsiz[i] = dwc2_readl(hsotg, DPTXFSIZN(i)); | |
58e52ff6 JY |
4968 | } |
4969 | dr->valid = true; | |
4970 | return 0; | |
4971 | } | |
4972 | ||
4973 | /** | |
4974 | * dwc2_restore_device_registers() - Restore controller device registers. | |
4975 | * When resuming usb bus, device registers needs to be restored | |
4976 | * if controller power were disabled. | |
4977 | * | |
4978 | * @hsotg: Programming view of the DWC_otg controller | |
9a5d2816 VM |
4979 | * @remote_wakeup: Indicates whether resume is initiated by Device or Host. |
4980 | * | |
4981 | * Return: 0 if successful, negative error code otherwise | |
58e52ff6 | 4982 | */ |
9a5d2816 | 4983 | int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg, int remote_wakeup) |
58e52ff6 JY |
4984 | { |
4985 | struct dwc2_dregs_backup *dr; | |
58e52ff6 JY |
4986 | int i; |
4987 | ||
4988 | dev_dbg(hsotg->dev, "%s\n", __func__); | |
4989 | ||
4990 | /* Restore dev regs */ | |
4991 | dr = &hsotg->dr_backup; | |
4992 | if (!dr->valid) { | |
4993 | dev_err(hsotg->dev, "%s: no device registers to restore\n", | |
4994 | __func__); | |
4995 | return -EINVAL; | |
4996 | } | |
4997 | dr->valid = false; | |
4998 | ||
9a5d2816 | 4999 | if (!remote_wakeup) |
f25c42b8 | 5000 | dwc2_writel(hsotg, dr->dctl, DCTL); |
9a5d2816 | 5001 | |
f25c42b8 GS |
5002 | dwc2_writel(hsotg, dr->daintmsk, DAINTMSK); |
5003 | dwc2_writel(hsotg, dr->diepmsk, DIEPMSK); | |
5004 | dwc2_writel(hsotg, dr->doepmsk, DOEPMSK); | |
58e52ff6 JY |
5005 | |
5006 | for (i = 0; i < hsotg->num_of_eps; i++) { | |
5007 | /* Restore IN EPs */ | |
f25c42b8 GS |
5008 | dwc2_writel(hsotg, dr->dieptsiz[i], DIEPTSIZ(i)); |
5009 | dwc2_writel(hsotg, dr->diepdma[i], DIEPDMA(i)); | |
5010 | dwc2_writel(hsotg, dr->doeptsiz[i], DOEPTSIZ(i)); | |
9a5d2816 VM |
5011 | /** WA for enabled EPx's IN in DDMA mode. On entering to |
5012 | * hibernation wrong value read and saved from DIEPDMAx, | |
5013 | * as result BNA interrupt asserted on hibernation exit | |
5014 | * by restoring from saved area. | |
5015 | */ | |
5016 | if (hsotg->params.g_dma_desc && | |
5017 | (dr->diepctl[i] & DXEPCTL_EPENA)) | |
5018 | dr->diepdma[i] = hsotg->eps_in[i]->desc_list_dma; | |
f25c42b8 GS |
5019 | dwc2_writel(hsotg, dr->dtxfsiz[i], DPTXFSIZN(i)); |
5020 | dwc2_writel(hsotg, dr->diepctl[i], DIEPCTL(i)); | |
58e52ff6 | 5021 | /* Restore OUT EPs */ |
f25c42b8 | 5022 | dwc2_writel(hsotg, dr->doeptsiz[i], DOEPTSIZ(i)); |
9a5d2816 VM |
5023 | /* WA for enabled EPx's OUT in DDMA mode. On entering to |
5024 | * hibernation wrong value read and saved from DOEPDMAx, | |
5025 | * as result BNA interrupt asserted on hibernation exit | |
5026 | * by restoring from saved area. | |
5027 | */ | |
5028 | if (hsotg->params.g_dma_desc && | |
5029 | (dr->doepctl[i] & DXEPCTL_EPENA)) | |
5030 | dr->doepdma[i] = hsotg->eps_out[i]->desc_list_dma; | |
f25c42b8 GS |
5031 | dwc2_writel(hsotg, dr->doepdma[i], DOEPDMA(i)); |
5032 | dwc2_writel(hsotg, dr->doepctl[i], DOEPCTL(i)); | |
58e52ff6 JY |
5033 | } |
5034 | ||
58e52ff6 JY |
5035 | return 0; |
5036 | } | |
21b03405 SA |
5037 | |
5038 | /** | |
5039 | * dwc2_gadget_init_lpm - Configure the core to support LPM in device mode | |
5040 | * | |
5041 | * @hsotg: Programming view of DWC_otg controller | |
5042 | * | |
5043 | */ | |
5044 | void dwc2_gadget_init_lpm(struct dwc2_hsotg *hsotg) | |
5045 | { | |
5046 | u32 val; | |
5047 | ||
5048 | if (!hsotg->params.lpm) | |
5049 | return; | |
5050 | ||
5051 | val = GLPMCFG_LPMCAP | GLPMCFG_APPL1RES; | |
5052 | val |= hsotg->params.hird_threshold_en ? GLPMCFG_HIRD_THRES_EN : 0; | |
5053 | val |= hsotg->params.lpm_clock_gating ? GLPMCFG_ENBLSLPM : 0; | |
5054 | val |= hsotg->params.hird_threshold << GLPMCFG_HIRD_THRES_SHIFT; | |
5055 | val |= hsotg->params.besl ? GLPMCFG_ENBESL : 0; | |
46637565 | 5056 | val |= GLPMCFG_LPM_REJECT_CTRL_CONTROL; |
9aed8c08 | 5057 | val |= GLPMCFG_LPM_ACCEPT_CTRL_ISOC; |
f25c42b8 GS |
5058 | dwc2_writel(hsotg, val, GLPMCFG); |
5059 | dev_dbg(hsotg->dev, "GLPMCFG=0x%08x\n", dwc2_readl(hsotg, GLPMCFG)); | |
4abe4537 GT |
5060 | |
5061 | /* Unmask WKUP_ALERT Interrupt */ | |
5062 | if (hsotg->params.service_interval) | |
5063 | dwc2_set_bit(hsotg, GINTMSK2, GINTMSK2_WKUP_ALERT_INT_MSK); | |
21b03405 | 5064 | } |
c5c403dc | 5065 | |
15d9dbf8 GT |
5066 | /** |
5067 | * dwc2_gadget_program_ref_clk - Program GREFCLK register in device mode | |
5068 | * | |
5069 | * @hsotg: Programming view of DWC_otg controller | |
5070 | * | |
5071 | */ | |
5072 | void dwc2_gadget_program_ref_clk(struct dwc2_hsotg *hsotg) | |
5073 | { | |
5074 | u32 val = 0; | |
5075 | ||
5076 | val |= GREFCLK_REF_CLK_MODE; | |
5077 | val |= hsotg->params.ref_clk_per << GREFCLK_REFCLKPER_SHIFT; | |
5078 | val |= hsotg->params.sof_cnt_wkup_alert << | |
5079 | GREFCLK_SOF_CNT_WKUP_ALERT_SHIFT; | |
5080 | ||
5081 | dwc2_writel(hsotg, val, GREFCLK); | |
5082 | dev_dbg(hsotg->dev, "GREFCLK=0x%08x\n", dwc2_readl(hsotg, GREFCLK)); | |
5083 | } | |
5084 | ||
c5c403dc VM |
5085 | /** |
5086 | * dwc2_gadget_enter_hibernation() - Put controller in Hibernation. | |
5087 | * | |
5088 | * @hsotg: Programming view of the DWC_otg controller | |
5089 | * | |
5090 | * Return non-zero if failed to enter to hibernation. | |
5091 | */ | |
5092 | int dwc2_gadget_enter_hibernation(struct dwc2_hsotg *hsotg) | |
5093 | { | |
5094 | u32 gpwrdn; | |
5095 | int ret = 0; | |
5096 | ||
5097 | /* Change to L2(suspend) state */ | |
5098 | hsotg->lx_state = DWC2_L2; | |
5099 | dev_dbg(hsotg->dev, "Start of hibernation completed\n"); | |
5100 | ret = dwc2_backup_global_registers(hsotg); | |
5101 | if (ret) { | |
5102 | dev_err(hsotg->dev, "%s: failed to backup global registers\n", | |
5103 | __func__); | |
5104 | return ret; | |
5105 | } | |
5106 | ret = dwc2_backup_device_registers(hsotg); | |
5107 | if (ret) { | |
5108 | dev_err(hsotg->dev, "%s: failed to backup device registers\n", | |
5109 | __func__); | |
5110 | return ret; | |
5111 | } | |
5112 | ||
5113 | gpwrdn = GPWRDN_PWRDNRSTN; | |
5114 | gpwrdn |= GPWRDN_PMUACTV; | |
f25c42b8 | 5115 | dwc2_writel(hsotg, gpwrdn, GPWRDN); |
c5c403dc VM |
5116 | udelay(10); |
5117 | ||
5118 | /* Set flag to indicate that we are in hibernation */ | |
5119 | hsotg->hibernated = 1; | |
5120 | ||
5121 | /* Enable interrupts from wake up logic */ | |
f25c42b8 | 5122 | gpwrdn = dwc2_readl(hsotg, GPWRDN); |
c5c403dc | 5123 | gpwrdn |= GPWRDN_PMUINTSEL; |
f25c42b8 | 5124 | dwc2_writel(hsotg, gpwrdn, GPWRDN); |
c5c403dc VM |
5125 | udelay(10); |
5126 | ||
5127 | /* Unmask device mode interrupts in GPWRDN */ | |
f25c42b8 | 5128 | gpwrdn = dwc2_readl(hsotg, GPWRDN); |
c5c403dc VM |
5129 | gpwrdn |= GPWRDN_RST_DET_MSK; |
5130 | gpwrdn |= GPWRDN_LNSTSCHG_MSK; | |
5131 | gpwrdn |= GPWRDN_STS_CHGINT_MSK; | |
f25c42b8 | 5132 | dwc2_writel(hsotg, gpwrdn, GPWRDN); |
c5c403dc VM |
5133 | udelay(10); |
5134 | ||
5135 | /* Enable Power Down Clamp */ | |
f25c42b8 | 5136 | gpwrdn = dwc2_readl(hsotg, GPWRDN); |
c5c403dc | 5137 | gpwrdn |= GPWRDN_PWRDNCLMP; |
f25c42b8 | 5138 | dwc2_writel(hsotg, gpwrdn, GPWRDN); |
c5c403dc VM |
5139 | udelay(10); |
5140 | ||
5141 | /* Switch off VDD */ | |
f25c42b8 | 5142 | gpwrdn = dwc2_readl(hsotg, GPWRDN); |
c5c403dc | 5143 | gpwrdn |= GPWRDN_PWRDNSWTCH; |
f25c42b8 | 5144 | dwc2_writel(hsotg, gpwrdn, GPWRDN); |
c5c403dc VM |
5145 | udelay(10); |
5146 | ||
5147 | /* Save gpwrdn register for further usage if stschng interrupt */ | |
f25c42b8 | 5148 | hsotg->gr_backup.gpwrdn = dwc2_readl(hsotg, GPWRDN); |
c5c403dc VM |
5149 | dev_dbg(hsotg->dev, "Hibernation completed\n"); |
5150 | ||
5151 | return ret; | |
5152 | } | |
5153 | ||
5154 | /** | |
5155 | * dwc2_gadget_exit_hibernation() | |
5156 | * This function is for exiting from Device mode hibernation by host initiated | |
5157 | * resume/reset and device initiated remote-wakeup. | |
5158 | * | |
5159 | * @hsotg: Programming view of the DWC_otg controller | |
5160 | * @rem_wakeup: indicates whether resume is initiated by Device or Host. | |
6fb914d7 | 5161 | * @reset: indicates whether resume is initiated by Reset. |
c5c403dc VM |
5162 | * |
5163 | * Return non-zero if failed to exit from hibernation. | |
5164 | */ | |
5165 | int dwc2_gadget_exit_hibernation(struct dwc2_hsotg *hsotg, | |
5166 | int rem_wakeup, int reset) | |
5167 | { | |
5168 | u32 pcgcctl; | |
5169 | u32 gpwrdn; | |
5170 | u32 dctl; | |
5171 | int ret = 0; | |
5172 | struct dwc2_gregs_backup *gr; | |
5173 | struct dwc2_dregs_backup *dr; | |
5174 | ||
5175 | gr = &hsotg->gr_backup; | |
5176 | dr = &hsotg->dr_backup; | |
5177 | ||
5178 | if (!hsotg->hibernated) { | |
5179 | dev_dbg(hsotg->dev, "Already exited from Hibernation\n"); | |
5180 | return 1; | |
5181 | } | |
5182 | dev_dbg(hsotg->dev, | |
5183 | "%s: called with rem_wakeup = %d reset = %d\n", | |
5184 | __func__, rem_wakeup, reset); | |
5185 | ||
5186 | dwc2_hib_restore_common(hsotg, rem_wakeup, 0); | |
5187 | ||
5188 | if (!reset) { | |
5189 | /* Clear all pending interupts */ | |
f25c42b8 | 5190 | dwc2_writel(hsotg, 0xffffffff, GINTSTS); |
c5c403dc VM |
5191 | } |
5192 | ||
5193 | /* De-assert Restore */ | |
f25c42b8 | 5194 | gpwrdn = dwc2_readl(hsotg, GPWRDN); |
c5c403dc | 5195 | gpwrdn &= ~GPWRDN_RESTORE; |
f25c42b8 | 5196 | dwc2_writel(hsotg, gpwrdn, GPWRDN); |
c5c403dc VM |
5197 | udelay(10); |
5198 | ||
5199 | if (!rem_wakeup) { | |
f25c42b8 | 5200 | pcgcctl = dwc2_readl(hsotg, PCGCTL); |
c5c403dc | 5201 | pcgcctl &= ~PCGCTL_RSTPDWNMODULE; |
f25c42b8 | 5202 | dwc2_writel(hsotg, pcgcctl, PCGCTL); |
c5c403dc VM |
5203 | } |
5204 | ||
5205 | /* Restore GUSBCFG, DCFG and DCTL */ | |
f25c42b8 GS |
5206 | dwc2_writel(hsotg, gr->gusbcfg, GUSBCFG); |
5207 | dwc2_writel(hsotg, dr->dcfg, DCFG); | |
5208 | dwc2_writel(hsotg, dr->dctl, DCTL); | |
c5c403dc VM |
5209 | |
5210 | /* De-assert Wakeup Logic */ | |
f25c42b8 | 5211 | gpwrdn = dwc2_readl(hsotg, GPWRDN); |
c5c403dc | 5212 | gpwrdn &= ~GPWRDN_PMUACTV; |
f25c42b8 | 5213 | dwc2_writel(hsotg, gpwrdn, GPWRDN); |
c5c403dc VM |
5214 | |
5215 | if (rem_wakeup) { | |
5216 | udelay(10); | |
5217 | /* Start Remote Wakeup Signaling */ | |
f25c42b8 | 5218 | dwc2_writel(hsotg, dr->dctl | DCTL_RMTWKUPSIG, DCTL); |
c5c403dc VM |
5219 | } else { |
5220 | udelay(50); | |
5221 | /* Set Device programming done bit */ | |
f25c42b8 | 5222 | dctl = dwc2_readl(hsotg, DCTL); |
c5c403dc | 5223 | dctl |= DCTL_PWRONPRGDONE; |
f25c42b8 | 5224 | dwc2_writel(hsotg, dctl, DCTL); |
c5c403dc VM |
5225 | } |
5226 | /* Wait for interrupts which must be cleared */ | |
5227 | mdelay(2); | |
5228 | /* Clear all pending interupts */ | |
f25c42b8 | 5229 | dwc2_writel(hsotg, 0xffffffff, GINTSTS); |
c5c403dc VM |
5230 | |
5231 | /* Restore global registers */ | |
5232 | ret = dwc2_restore_global_registers(hsotg); | |
5233 | if (ret) { | |
5234 | dev_err(hsotg->dev, "%s: failed to restore registers\n", | |
5235 | __func__); | |
5236 | return ret; | |
5237 | } | |
5238 | ||
5239 | /* Restore device registers */ | |
5240 | ret = dwc2_restore_device_registers(hsotg, rem_wakeup); | |
5241 | if (ret) { | |
5242 | dev_err(hsotg->dev, "%s: failed to restore device registers\n", | |
5243 | __func__); | |
5244 | return ret; | |
5245 | } | |
5246 | ||
5247 | if (rem_wakeup) { | |
5248 | mdelay(10); | |
f25c42b8 | 5249 | dctl = dwc2_readl(hsotg, DCTL); |
c5c403dc | 5250 | dctl &= ~DCTL_RMTWKUPSIG; |
f25c42b8 | 5251 | dwc2_writel(hsotg, dctl, DCTL); |
c5c403dc VM |
5252 | } |
5253 | ||
5254 | hsotg->hibernated = 0; | |
5255 | hsotg->lx_state = DWC2_L0; | |
5256 | dev_dbg(hsotg->dev, "Hibernation recovery completes here\n"); | |
5257 | ||
5258 | return ret; | |
5259 | } |