Commit | Line | Data |
---|---|---|
8b9bc460 | 1 | /** |
dfbc6fa3 AT |
2 | * Copyright (c) 2011 Samsung Electronics Co., Ltd. |
3 | * http://www.samsung.com | |
5b7d70c6 BD |
4 | * |
5 | * Copyright 2008 Openmoko, Inc. | |
6 | * Copyright 2008 Simtec Electronics | |
7 | * Ben Dooks <ben@simtec.co.uk> | |
8 | * http://armlinux.simtec.co.uk/ | |
9 | * | |
10 | * S3C USB2.0 High-speed / OtG driver | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License version 2 as | |
14 | * published by the Free Software Foundation. | |
8b9bc460 | 15 | */ |
5b7d70c6 BD |
16 | |
17 | #include <linux/kernel.h> | |
18 | #include <linux/module.h> | |
19 | #include <linux/spinlock.h> | |
20 | #include <linux/interrupt.h> | |
21 | #include <linux/platform_device.h> | |
22 | #include <linux/dma-mapping.h> | |
7ad8096e | 23 | #include <linux/mutex.h> |
5b7d70c6 BD |
24 | #include <linux/seq_file.h> |
25 | #include <linux/delay.h> | |
26 | #include <linux/io.h> | |
5a0e3ad6 | 27 | #include <linux/slab.h> |
c50f056c | 28 | #include <linux/of_platform.h> |
5b7d70c6 BD |
29 | |
30 | #include <linux/usb/ch9.h> | |
31 | #include <linux/usb/gadget.h> | |
b2e587db | 32 | #include <linux/usb/phy.h> |
5b7d70c6 | 33 | |
f7c0b143 | 34 | #include "core.h" |
941fcce4 | 35 | #include "hw.h" |
5b7d70c6 BD |
36 | |
37 | /* conversion functions */ | |
1f91b4cc | 38 | static inline struct dwc2_hsotg_req *our_req(struct usb_request *req) |
5b7d70c6 | 39 | { |
1f91b4cc | 40 | return container_of(req, struct dwc2_hsotg_req, req); |
5b7d70c6 BD |
41 | } |
42 | ||
1f91b4cc | 43 | static inline struct dwc2_hsotg_ep *our_ep(struct usb_ep *ep) |
5b7d70c6 | 44 | { |
1f91b4cc | 45 | return container_of(ep, struct dwc2_hsotg_ep, ep); |
5b7d70c6 BD |
46 | } |
47 | ||
941fcce4 | 48 | static inline struct dwc2_hsotg *to_hsotg(struct usb_gadget *gadget) |
5b7d70c6 | 49 | { |
941fcce4 | 50 | return container_of(gadget, struct dwc2_hsotg, gadget); |
5b7d70c6 BD |
51 | } |
52 | ||
53 | static inline void __orr32(void __iomem *ptr, u32 val) | |
54 | { | |
95c8bc36 | 55 | dwc2_writel(dwc2_readl(ptr) | val, ptr); |
5b7d70c6 BD |
56 | } |
57 | ||
58 | static inline void __bic32(void __iomem *ptr, u32 val) | |
59 | { | |
95c8bc36 | 60 | dwc2_writel(dwc2_readl(ptr) & ~val, ptr); |
5b7d70c6 BD |
61 | } |
62 | ||
1f91b4cc | 63 | static inline struct dwc2_hsotg_ep *index_to_ep(struct dwc2_hsotg *hsotg, |
c6f5c050 MYK |
64 | u32 ep_index, u32 dir_in) |
65 | { | |
66 | if (dir_in) | |
67 | return hsotg->eps_in[ep_index]; | |
68 | else | |
69 | return hsotg->eps_out[ep_index]; | |
70 | } | |
71 | ||
997f4f81 | 72 | /* forward declaration of functions */ |
1f91b4cc | 73 | static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg); |
5b7d70c6 BD |
74 | |
75 | /** | |
76 | * using_dma - return the DMA status of the driver. | |
77 | * @hsotg: The driver state. | |
78 | * | |
79 | * Return true if we're using DMA. | |
80 | * | |
81 | * Currently, we have the DMA support code worked into everywhere | |
82 | * that needs it, but the AMBA DMA implementation in the hardware can | |
83 | * only DMA from 32bit aligned addresses. This means that gadgets such | |
84 | * as the CDC Ethernet cannot work as they often pass packets which are | |
85 | * not 32bit aligned. | |
86 | * | |
87 | * Unfortunately the choice to use DMA or not is global to the controller | |
88 | * and seems to be only settable when the controller is being put through | |
89 | * a core reset. This means we either need to fix the gadgets to take | |
90 | * account of DMA alignment, or add bounce buffers (yuerk). | |
91 | * | |
edd74be8 | 92 | * g_using_dma is set depending on dts flag. |
5b7d70c6 | 93 | */ |
941fcce4 | 94 | static inline bool using_dma(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 95 | { |
edd74be8 | 96 | return hsotg->g_using_dma; |
5b7d70c6 BD |
97 | } |
98 | ||
92d1635d VM |
99 | /** |
100 | * dwc2_gadget_incr_frame_num - Increments the targeted frame number. | |
101 | * @hs_ep: The endpoint | |
102 | * @increment: The value to increment by | |
103 | * | |
104 | * This function will also check if the frame number overruns DSTS_SOFFN_LIMIT. | |
105 | * If an overrun occurs it will wrap the value and set the frame_overrun flag. | |
106 | */ | |
107 | static inline void dwc2_gadget_incr_frame_num(struct dwc2_hsotg_ep *hs_ep) | |
108 | { | |
109 | hs_ep->target_frame += hs_ep->interval; | |
110 | if (hs_ep->target_frame > DSTS_SOFFN_LIMIT) { | |
111 | hs_ep->frame_overrun = 1; | |
112 | hs_ep->target_frame &= DSTS_SOFFN_LIMIT; | |
113 | } else { | |
114 | hs_ep->frame_overrun = 0; | |
115 | } | |
116 | } | |
117 | ||
5b7d70c6 | 118 | /** |
1f91b4cc | 119 | * dwc2_hsotg_en_gsint - enable one or more of the general interrupt |
5b7d70c6 BD |
120 | * @hsotg: The device state |
121 | * @ints: A bitmask of the interrupts to enable | |
122 | */ | |
1f91b4cc | 123 | static void dwc2_hsotg_en_gsint(struct dwc2_hsotg *hsotg, u32 ints) |
5b7d70c6 | 124 | { |
95c8bc36 | 125 | u32 gsintmsk = dwc2_readl(hsotg->regs + GINTMSK); |
5b7d70c6 BD |
126 | u32 new_gsintmsk; |
127 | ||
128 | new_gsintmsk = gsintmsk | ints; | |
129 | ||
130 | if (new_gsintmsk != gsintmsk) { | |
131 | dev_dbg(hsotg->dev, "gsintmsk now 0x%08x\n", new_gsintmsk); | |
95c8bc36 | 132 | dwc2_writel(new_gsintmsk, hsotg->regs + GINTMSK); |
5b7d70c6 BD |
133 | } |
134 | } | |
135 | ||
136 | /** | |
1f91b4cc | 137 | * dwc2_hsotg_disable_gsint - disable one or more of the general interrupt |
5b7d70c6 BD |
138 | * @hsotg: The device state |
139 | * @ints: A bitmask of the interrupts to enable | |
140 | */ | |
1f91b4cc | 141 | static void dwc2_hsotg_disable_gsint(struct dwc2_hsotg *hsotg, u32 ints) |
5b7d70c6 | 142 | { |
95c8bc36 | 143 | u32 gsintmsk = dwc2_readl(hsotg->regs + GINTMSK); |
5b7d70c6 BD |
144 | u32 new_gsintmsk; |
145 | ||
146 | new_gsintmsk = gsintmsk & ~ints; | |
147 | ||
148 | if (new_gsintmsk != gsintmsk) | |
95c8bc36 | 149 | dwc2_writel(new_gsintmsk, hsotg->regs + GINTMSK); |
5b7d70c6 BD |
150 | } |
151 | ||
152 | /** | |
1f91b4cc | 153 | * dwc2_hsotg_ctrl_epint - enable/disable an endpoint irq |
5b7d70c6 BD |
154 | * @hsotg: The device state |
155 | * @ep: The endpoint index | |
156 | * @dir_in: True if direction is in. | |
157 | * @en: The enable value, true to enable | |
158 | * | |
159 | * Set or clear the mask for an individual endpoint's interrupt | |
160 | * request. | |
161 | */ | |
1f91b4cc | 162 | static void dwc2_hsotg_ctrl_epint(struct dwc2_hsotg *hsotg, |
5b7d70c6 BD |
163 | unsigned int ep, unsigned int dir_in, |
164 | unsigned int en) | |
165 | { | |
166 | unsigned long flags; | |
167 | u32 bit = 1 << ep; | |
168 | u32 daint; | |
169 | ||
170 | if (!dir_in) | |
171 | bit <<= 16; | |
172 | ||
173 | local_irq_save(flags); | |
95c8bc36 | 174 | daint = dwc2_readl(hsotg->regs + DAINTMSK); |
5b7d70c6 BD |
175 | if (en) |
176 | daint |= bit; | |
177 | else | |
178 | daint &= ~bit; | |
95c8bc36 | 179 | dwc2_writel(daint, hsotg->regs + DAINTMSK); |
5b7d70c6 BD |
180 | local_irq_restore(flags); |
181 | } | |
182 | ||
183 | /** | |
1f91b4cc | 184 | * dwc2_hsotg_init_fifo - initialise non-periodic FIFOs |
5b7d70c6 BD |
185 | * @hsotg: The device instance. |
186 | */ | |
1f91b4cc | 187 | static void dwc2_hsotg_init_fifo(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 188 | { |
ba48eab8 | 189 | unsigned int fifo; |
0f002d20 | 190 | unsigned int addr; |
1703a6d3 | 191 | int timeout; |
aa381a72 | 192 | u32 dptxfsizn; |
0f002d20 BD |
193 | u32 val; |
194 | ||
7fcbc95c GH |
195 | /* Reset fifo map if not correctly cleared during previous session */ |
196 | WARN_ON(hsotg->fifo_map); | |
197 | hsotg->fifo_map = 0; | |
198 | ||
0a176279 | 199 | /* set RX/NPTX FIFO sizes */ |
95c8bc36 AS |
200 | dwc2_writel(hsotg->g_rx_fifo_sz, hsotg->regs + GRXFSIZ); |
201 | dwc2_writel((hsotg->g_rx_fifo_sz << FIFOSIZE_STARTADDR_SHIFT) | | |
0a176279 GH |
202 | (hsotg->g_np_g_tx_fifo_sz << FIFOSIZE_DEPTH_SHIFT), |
203 | hsotg->regs + GNPTXFSIZ); | |
0f002d20 | 204 | |
8b9bc460 LM |
205 | /* |
206 | * arange all the rest of the TX FIFOs, as some versions of this | |
0f002d20 BD |
207 | * block have overlapping default addresses. This also ensures |
208 | * that if the settings have been changed, then they are set to | |
8b9bc460 LM |
209 | * known values. |
210 | */ | |
0f002d20 BD |
211 | |
212 | /* start at the end of the GNPTXFSIZ, rounded up */ | |
0a176279 | 213 | addr = hsotg->g_rx_fifo_sz + hsotg->g_np_g_tx_fifo_sz; |
0f002d20 | 214 | |
8b9bc460 | 215 | /* |
0a176279 | 216 | * Configure fifos sizes from provided configuration and assign |
b203d0a2 RB |
217 | * them to endpoints dynamically according to maxpacket size value of |
218 | * given endpoint. | |
8b9bc460 | 219 | */ |
ba48eab8 RB |
220 | for (fifo = 1; fifo < MAX_EPS_CHANNELS; fifo++) { |
221 | dptxfsizn = dwc2_readl(hsotg->regs + DPTXFSIZN(fifo)); | |
aa381a72 RB |
222 | |
223 | val = (dptxfsizn & FIFOSIZE_DEPTH_MASK) | addr; | |
224 | addr += dptxfsizn >> FIFOSIZE_DEPTH_SHIFT; | |
225 | ||
226 | if (addr > hsotg->fifo_mem) | |
227 | break; | |
0f002d20 | 228 | |
ba48eab8 | 229 | dwc2_writel(val, hsotg->regs + DPTXFSIZN(fifo)); |
0f002d20 | 230 | } |
1703a6d3 | 231 | |
8b9bc460 LM |
232 | /* |
233 | * according to p428 of the design guide, we need to ensure that | |
234 | * all fifos are flushed before continuing | |
235 | */ | |
1703a6d3 | 236 | |
95c8bc36 | 237 | dwc2_writel(GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH | |
47a1685f | 238 | GRSTCTL_RXFFLSH, hsotg->regs + GRSTCTL); |
1703a6d3 BD |
239 | |
240 | /* wait until the fifos are both flushed */ | |
241 | timeout = 100; | |
242 | while (1) { | |
95c8bc36 | 243 | val = dwc2_readl(hsotg->regs + GRSTCTL); |
1703a6d3 | 244 | |
47a1685f | 245 | if ((val & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH)) == 0) |
1703a6d3 BD |
246 | break; |
247 | ||
248 | if (--timeout == 0) { | |
249 | dev_err(hsotg->dev, | |
250 | "%s: timeout flushing fifos (GRSTCTL=%08x)\n", | |
251 | __func__, val); | |
48b20bcb | 252 | break; |
1703a6d3 BD |
253 | } |
254 | ||
255 | udelay(1); | |
256 | } | |
257 | ||
258 | dev_dbg(hsotg->dev, "FIFOs reset, timeout at %d\n", timeout); | |
5b7d70c6 BD |
259 | } |
260 | ||
261 | /** | |
262 | * @ep: USB endpoint to allocate request for. | |
263 | * @flags: Allocation flags | |
264 | * | |
265 | * Allocate a new USB request structure appropriate for the specified endpoint | |
266 | */ | |
1f91b4cc | 267 | static struct usb_request *dwc2_hsotg_ep_alloc_request(struct usb_ep *ep, |
0978f8c5 | 268 | gfp_t flags) |
5b7d70c6 | 269 | { |
1f91b4cc | 270 | struct dwc2_hsotg_req *req; |
5b7d70c6 | 271 | |
1f91b4cc | 272 | req = kzalloc(sizeof(struct dwc2_hsotg_req), flags); |
5b7d70c6 BD |
273 | if (!req) |
274 | return NULL; | |
275 | ||
276 | INIT_LIST_HEAD(&req->queue); | |
277 | ||
5b7d70c6 BD |
278 | return &req->req; |
279 | } | |
280 | ||
281 | /** | |
282 | * is_ep_periodic - return true if the endpoint is in periodic mode. | |
283 | * @hs_ep: The endpoint to query. | |
284 | * | |
285 | * Returns true if the endpoint is in periodic mode, meaning it is being | |
286 | * used for an Interrupt or ISO transfer. | |
287 | */ | |
1f91b4cc | 288 | static inline int is_ep_periodic(struct dwc2_hsotg_ep *hs_ep) |
5b7d70c6 BD |
289 | { |
290 | return hs_ep->periodic; | |
291 | } | |
292 | ||
293 | /** | |
1f91b4cc | 294 | * dwc2_hsotg_unmap_dma - unmap the DMA memory being used for the request |
5b7d70c6 BD |
295 | * @hsotg: The device state. |
296 | * @hs_ep: The endpoint for the request | |
297 | * @hs_req: The request being processed. | |
298 | * | |
1f91b4cc | 299 | * This is the reverse of dwc2_hsotg_map_dma(), called for the completion |
5b7d70c6 | 300 | * of a request to ensure the buffer is ready for access by the caller. |
8b9bc460 | 301 | */ |
1f91b4cc FB |
302 | static void dwc2_hsotg_unmap_dma(struct dwc2_hsotg *hsotg, |
303 | struct dwc2_hsotg_ep *hs_ep, | |
304 | struct dwc2_hsotg_req *hs_req) | |
5b7d70c6 BD |
305 | { |
306 | struct usb_request *req = &hs_req->req; | |
5b7d70c6 BD |
307 | |
308 | /* ignore this if we're not moving any data */ | |
309 | if (hs_req->req.length == 0) | |
310 | return; | |
311 | ||
17d966a3 | 312 | usb_gadget_unmap_request(&hsotg->gadget, req, hs_ep->dir_in); |
5b7d70c6 BD |
313 | } |
314 | ||
315 | /** | |
1f91b4cc | 316 | * dwc2_hsotg_write_fifo - write packet Data to the TxFIFO |
5b7d70c6 BD |
317 | * @hsotg: The controller state. |
318 | * @hs_ep: The endpoint we're going to write for. | |
319 | * @hs_req: The request to write data for. | |
320 | * | |
321 | * This is called when the TxFIFO has some space in it to hold a new | |
322 | * transmission and we have something to give it. The actual setup of | |
323 | * the data size is done elsewhere, so all we have to do is to actually | |
324 | * write the data. | |
325 | * | |
326 | * The return value is zero if there is more space (or nothing was done) | |
327 | * otherwise -ENOSPC is returned if the FIFO space was used up. | |
328 | * | |
329 | * This routine is only needed for PIO | |
8b9bc460 | 330 | */ |
1f91b4cc FB |
331 | static int dwc2_hsotg_write_fifo(struct dwc2_hsotg *hsotg, |
332 | struct dwc2_hsotg_ep *hs_ep, | |
333 | struct dwc2_hsotg_req *hs_req) | |
5b7d70c6 BD |
334 | { |
335 | bool periodic = is_ep_periodic(hs_ep); | |
95c8bc36 | 336 | u32 gnptxsts = dwc2_readl(hsotg->regs + GNPTXSTS); |
5b7d70c6 BD |
337 | int buf_pos = hs_req->req.actual; |
338 | int to_write = hs_ep->size_loaded; | |
339 | void *data; | |
340 | int can_write; | |
341 | int pkt_round; | |
4fca54aa | 342 | int max_transfer; |
5b7d70c6 BD |
343 | |
344 | to_write -= (buf_pos - hs_ep->last_load); | |
345 | ||
346 | /* if there's nothing to write, get out early */ | |
347 | if (to_write == 0) | |
348 | return 0; | |
349 | ||
10aebc77 | 350 | if (periodic && !hsotg->dedicated_fifos) { |
95c8bc36 | 351 | u32 epsize = dwc2_readl(hsotg->regs + DIEPTSIZ(hs_ep->index)); |
5b7d70c6 BD |
352 | int size_left; |
353 | int size_done; | |
354 | ||
8b9bc460 LM |
355 | /* |
356 | * work out how much data was loaded so we can calculate | |
357 | * how much data is left in the fifo. | |
358 | */ | |
5b7d70c6 | 359 | |
47a1685f | 360 | size_left = DXEPTSIZ_XFERSIZE_GET(epsize); |
5b7d70c6 | 361 | |
8b9bc460 LM |
362 | /* |
363 | * if shared fifo, we cannot write anything until the | |
e7a9ff54 BD |
364 | * previous data has been completely sent. |
365 | */ | |
366 | if (hs_ep->fifo_load != 0) { | |
1f91b4cc | 367 | dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP); |
e7a9ff54 BD |
368 | return -ENOSPC; |
369 | } | |
370 | ||
5b7d70c6 BD |
371 | dev_dbg(hsotg->dev, "%s: left=%d, load=%d, fifo=%d, size %d\n", |
372 | __func__, size_left, | |
373 | hs_ep->size_loaded, hs_ep->fifo_load, hs_ep->fifo_size); | |
374 | ||
375 | /* how much of the data has moved */ | |
376 | size_done = hs_ep->size_loaded - size_left; | |
377 | ||
378 | /* how much data is left in the fifo */ | |
379 | can_write = hs_ep->fifo_load - size_done; | |
380 | dev_dbg(hsotg->dev, "%s: => can_write1=%d\n", | |
381 | __func__, can_write); | |
382 | ||
383 | can_write = hs_ep->fifo_size - can_write; | |
384 | dev_dbg(hsotg->dev, "%s: => can_write2=%d\n", | |
385 | __func__, can_write); | |
386 | ||
387 | if (can_write <= 0) { | |
1f91b4cc | 388 | dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP); |
5b7d70c6 BD |
389 | return -ENOSPC; |
390 | } | |
10aebc77 | 391 | } else if (hsotg->dedicated_fifos && hs_ep->index != 0) { |
ad674a15 RB |
392 | can_write = dwc2_readl(hsotg->regs + |
393 | DTXFSTS(hs_ep->fifo_index)); | |
10aebc77 BD |
394 | |
395 | can_write &= 0xffff; | |
396 | can_write *= 4; | |
5b7d70c6 | 397 | } else { |
47a1685f | 398 | if (GNPTXSTS_NP_TXQ_SPC_AVAIL_GET(gnptxsts) == 0) { |
5b7d70c6 BD |
399 | dev_dbg(hsotg->dev, |
400 | "%s: no queue slots available (0x%08x)\n", | |
401 | __func__, gnptxsts); | |
402 | ||
1f91b4cc | 403 | dwc2_hsotg_en_gsint(hsotg, GINTSTS_NPTXFEMP); |
5b7d70c6 BD |
404 | return -ENOSPC; |
405 | } | |
406 | ||
47a1685f | 407 | can_write = GNPTXSTS_NP_TXF_SPC_AVAIL_GET(gnptxsts); |
679f9b7c | 408 | can_write *= 4; /* fifo size is in 32bit quantities. */ |
5b7d70c6 BD |
409 | } |
410 | ||
4fca54aa RB |
411 | max_transfer = hs_ep->ep.maxpacket * hs_ep->mc; |
412 | ||
413 | dev_dbg(hsotg->dev, "%s: GNPTXSTS=%08x, can=%d, to=%d, max_transfer %d\n", | |
414 | __func__, gnptxsts, can_write, to_write, max_transfer); | |
5b7d70c6 | 415 | |
8b9bc460 LM |
416 | /* |
417 | * limit to 512 bytes of data, it seems at least on the non-periodic | |
5b7d70c6 BD |
418 | * FIFO, requests of >512 cause the endpoint to get stuck with a |
419 | * fragment of the end of the transfer in it. | |
420 | */ | |
811f3303 | 421 | if (can_write > 512 && !periodic) |
5b7d70c6 BD |
422 | can_write = 512; |
423 | ||
8b9bc460 LM |
424 | /* |
425 | * limit the write to one max-packet size worth of data, but allow | |
03e10e5a | 426 | * the transfer to return that it did not run out of fifo space |
8b9bc460 LM |
427 | * doing it. |
428 | */ | |
4fca54aa RB |
429 | if (to_write > max_transfer) { |
430 | to_write = max_transfer; | |
03e10e5a | 431 | |
5cb2ff0c RB |
432 | /* it's needed only when we do not use dedicated fifos */ |
433 | if (!hsotg->dedicated_fifos) | |
1f91b4cc | 434 | dwc2_hsotg_en_gsint(hsotg, |
47a1685f DN |
435 | periodic ? GINTSTS_PTXFEMP : |
436 | GINTSTS_NPTXFEMP); | |
03e10e5a BD |
437 | } |
438 | ||
5b7d70c6 BD |
439 | /* see if we can write data */ |
440 | ||
441 | if (to_write > can_write) { | |
442 | to_write = can_write; | |
4fca54aa | 443 | pkt_round = to_write % max_transfer; |
5b7d70c6 | 444 | |
8b9bc460 LM |
445 | /* |
446 | * Round the write down to an | |
5b7d70c6 BD |
447 | * exact number of packets. |
448 | * | |
449 | * Note, we do not currently check to see if we can ever | |
450 | * write a full packet or not to the FIFO. | |
451 | */ | |
452 | ||
453 | if (pkt_round) | |
454 | to_write -= pkt_round; | |
455 | ||
8b9bc460 LM |
456 | /* |
457 | * enable correct FIFO interrupt to alert us when there | |
458 | * is more room left. | |
459 | */ | |
5b7d70c6 | 460 | |
5cb2ff0c RB |
461 | /* it's needed only when we do not use dedicated fifos */ |
462 | if (!hsotg->dedicated_fifos) | |
1f91b4cc | 463 | dwc2_hsotg_en_gsint(hsotg, |
47a1685f DN |
464 | periodic ? GINTSTS_PTXFEMP : |
465 | GINTSTS_NPTXFEMP); | |
5b7d70c6 BD |
466 | } |
467 | ||
468 | dev_dbg(hsotg->dev, "write %d/%d, can_write %d, done %d\n", | |
469 | to_write, hs_req->req.length, can_write, buf_pos); | |
470 | ||
471 | if (to_write <= 0) | |
472 | return -ENOSPC; | |
473 | ||
474 | hs_req->req.actual = buf_pos + to_write; | |
475 | hs_ep->total_data += to_write; | |
476 | ||
477 | if (periodic) | |
478 | hs_ep->fifo_load += to_write; | |
479 | ||
480 | to_write = DIV_ROUND_UP(to_write, 4); | |
481 | data = hs_req->req.buf + buf_pos; | |
482 | ||
1a7ed5be | 483 | iowrite32_rep(hsotg->regs + EPFIFO(hs_ep->index), data, to_write); |
5b7d70c6 BD |
484 | |
485 | return (to_write >= can_write) ? -ENOSPC : 0; | |
486 | } | |
487 | ||
488 | /** | |
489 | * get_ep_limit - get the maximum data legnth for this endpoint | |
490 | * @hs_ep: The endpoint | |
491 | * | |
492 | * Return the maximum data that can be queued in one go on a given endpoint | |
493 | * so that transfers that are too long can be split. | |
494 | */ | |
1f91b4cc | 495 | static unsigned get_ep_limit(struct dwc2_hsotg_ep *hs_ep) |
5b7d70c6 BD |
496 | { |
497 | int index = hs_ep->index; | |
498 | unsigned maxsize; | |
499 | unsigned maxpkt; | |
500 | ||
501 | if (index != 0) { | |
47a1685f DN |
502 | maxsize = DXEPTSIZ_XFERSIZE_LIMIT + 1; |
503 | maxpkt = DXEPTSIZ_PKTCNT_LIMIT + 1; | |
5b7d70c6 | 504 | } else { |
b05ca580 | 505 | maxsize = 64+64; |
66e5c643 | 506 | if (hs_ep->dir_in) |
47a1685f | 507 | maxpkt = DIEPTSIZ0_PKTCNT_LIMIT + 1; |
66e5c643 | 508 | else |
5b7d70c6 | 509 | maxpkt = 2; |
5b7d70c6 BD |
510 | } |
511 | ||
512 | /* we made the constant loading easier above by using +1 */ | |
513 | maxpkt--; | |
514 | maxsize--; | |
515 | ||
8b9bc460 LM |
516 | /* |
517 | * constrain by packet count if maxpkts*pktsize is greater | |
518 | * than the length register size. | |
519 | */ | |
5b7d70c6 BD |
520 | |
521 | if ((maxpkt * hs_ep->ep.maxpacket) < maxsize) | |
522 | maxsize = maxpkt * hs_ep->ep.maxpacket; | |
523 | ||
524 | return maxsize; | |
525 | } | |
526 | ||
381fc8f8 VM |
527 | /** |
528 | * dwc2_hsotg_read_frameno - read current frame number | |
529 | * @hsotg: The device instance | |
530 | * | |
531 | * Return the current frame number | |
532 | */ | |
533 | static u32 dwc2_hsotg_read_frameno(struct dwc2_hsotg *hsotg) | |
534 | { | |
535 | u32 dsts; | |
536 | ||
537 | dsts = dwc2_readl(hsotg->regs + DSTS); | |
538 | dsts &= DSTS_SOFFN_MASK; | |
539 | dsts >>= DSTS_SOFFN_SHIFT; | |
540 | ||
541 | return dsts; | |
542 | } | |
543 | ||
5b7d70c6 | 544 | /** |
1f91b4cc | 545 | * dwc2_hsotg_start_req - start a USB request from an endpoint's queue |
5b7d70c6 BD |
546 | * @hsotg: The controller state. |
547 | * @hs_ep: The endpoint to process a request for | |
548 | * @hs_req: The request to start. | |
549 | * @continuing: True if we are doing more for the current request. | |
550 | * | |
551 | * Start the given request running by setting the endpoint registers | |
552 | * appropriately, and writing any data to the FIFOs. | |
553 | */ | |
1f91b4cc FB |
554 | static void dwc2_hsotg_start_req(struct dwc2_hsotg *hsotg, |
555 | struct dwc2_hsotg_ep *hs_ep, | |
556 | struct dwc2_hsotg_req *hs_req, | |
5b7d70c6 BD |
557 | bool continuing) |
558 | { | |
559 | struct usb_request *ureq = &hs_req->req; | |
560 | int index = hs_ep->index; | |
561 | int dir_in = hs_ep->dir_in; | |
562 | u32 epctrl_reg; | |
563 | u32 epsize_reg; | |
564 | u32 epsize; | |
565 | u32 ctrl; | |
566 | unsigned length; | |
567 | unsigned packets; | |
568 | unsigned maxreq; | |
569 | ||
570 | if (index != 0) { | |
571 | if (hs_ep->req && !continuing) { | |
572 | dev_err(hsotg->dev, "%s: active request\n", __func__); | |
573 | WARN_ON(1); | |
574 | return; | |
575 | } else if (hs_ep->req != hs_req && continuing) { | |
576 | dev_err(hsotg->dev, | |
577 | "%s: continue different req\n", __func__); | |
578 | WARN_ON(1); | |
579 | return; | |
580 | } | |
581 | } | |
582 | ||
94cb8fd6 LM |
583 | epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index); |
584 | epsize_reg = dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index); | |
5b7d70c6 BD |
585 | |
586 | dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n", | |
95c8bc36 | 587 | __func__, dwc2_readl(hsotg->regs + epctrl_reg), index, |
5b7d70c6 BD |
588 | hs_ep->dir_in ? "in" : "out"); |
589 | ||
9c39ddc6 | 590 | /* If endpoint is stalled, we will restart request later */ |
95c8bc36 | 591 | ctrl = dwc2_readl(hsotg->regs + epctrl_reg); |
9c39ddc6 | 592 | |
b2d4c54e | 593 | if (index && ctrl & DXEPCTL_STALL) { |
9c39ddc6 AT |
594 | dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index); |
595 | return; | |
596 | } | |
597 | ||
5b7d70c6 | 598 | length = ureq->length - ureq->actual; |
71225bee LM |
599 | dev_dbg(hsotg->dev, "ureq->length:%d ureq->actual:%d\n", |
600 | ureq->length, ureq->actual); | |
5b7d70c6 BD |
601 | |
602 | maxreq = get_ep_limit(hs_ep); | |
603 | if (length > maxreq) { | |
604 | int round = maxreq % hs_ep->ep.maxpacket; | |
605 | ||
606 | dev_dbg(hsotg->dev, "%s: length %d, max-req %d, r %d\n", | |
607 | __func__, length, maxreq, round); | |
608 | ||
609 | /* round down to multiple of packets */ | |
610 | if (round) | |
611 | maxreq -= round; | |
612 | ||
613 | length = maxreq; | |
614 | } | |
615 | ||
616 | if (length) | |
617 | packets = DIV_ROUND_UP(length, hs_ep->ep.maxpacket); | |
618 | else | |
619 | packets = 1; /* send one packet if length is zero. */ | |
620 | ||
4fca54aa RB |
621 | if (hs_ep->isochronous && length > (hs_ep->mc * hs_ep->ep.maxpacket)) { |
622 | dev_err(hsotg->dev, "req length > maxpacket*mc\n"); | |
623 | return; | |
624 | } | |
625 | ||
5b7d70c6 | 626 | if (dir_in && index != 0) |
4fca54aa | 627 | if (hs_ep->isochronous) |
47a1685f | 628 | epsize = DXEPTSIZ_MC(packets); |
4fca54aa | 629 | else |
47a1685f | 630 | epsize = DXEPTSIZ_MC(1); |
5b7d70c6 BD |
631 | else |
632 | epsize = 0; | |
633 | ||
f71b5e25 MYK |
634 | /* |
635 | * zero length packet should be programmed on its own and should not | |
636 | * be counted in DIEPTSIZ.PktCnt with other packets. | |
637 | */ | |
638 | if (dir_in && ureq->zero && !continuing) { | |
639 | /* Test if zlp is actually required. */ | |
640 | if ((ureq->length >= hs_ep->ep.maxpacket) && | |
641 | !(ureq->length % hs_ep->ep.maxpacket)) | |
8a20fa45 | 642 | hs_ep->send_zlp = 1; |
5b7d70c6 BD |
643 | } |
644 | ||
47a1685f DN |
645 | epsize |= DXEPTSIZ_PKTCNT(packets); |
646 | epsize |= DXEPTSIZ_XFERSIZE(length); | |
5b7d70c6 BD |
647 | |
648 | dev_dbg(hsotg->dev, "%s: %d@%d/%d, 0x%08x => 0x%08x\n", | |
649 | __func__, packets, length, ureq->length, epsize, epsize_reg); | |
650 | ||
651 | /* store the request as the current one we're doing */ | |
652 | hs_ep->req = hs_req; | |
653 | ||
654 | /* write size / packets */ | |
95c8bc36 | 655 | dwc2_writel(epsize, hsotg->regs + epsize_reg); |
5b7d70c6 | 656 | |
db1d8ba3 | 657 | if (using_dma(hsotg) && !continuing) { |
5b7d70c6 BD |
658 | unsigned int dma_reg; |
659 | ||
8b9bc460 LM |
660 | /* |
661 | * write DMA address to control register, buffer already | |
1f91b4cc | 662 | * synced by dwc2_hsotg_ep_queue(). |
8b9bc460 | 663 | */ |
5b7d70c6 | 664 | |
94cb8fd6 | 665 | dma_reg = dir_in ? DIEPDMA(index) : DOEPDMA(index); |
95c8bc36 | 666 | dwc2_writel(ureq->dma, hsotg->regs + dma_reg); |
5b7d70c6 | 667 | |
0cc4cf6f | 668 | dev_dbg(hsotg->dev, "%s: %pad => 0x%08x\n", |
8b3bc14f | 669 | __func__, &ureq->dma, dma_reg); |
5b7d70c6 BD |
670 | } |
671 | ||
837e9f00 VM |
672 | if (hs_ep->isochronous && hs_ep->interval == 1) { |
673 | hs_ep->target_frame = dwc2_hsotg_read_frameno(hsotg); | |
674 | dwc2_gadget_incr_frame_num(hs_ep); | |
675 | ||
676 | if (hs_ep->target_frame & 0x1) | |
677 | ctrl |= DXEPCTL_SETODDFR; | |
678 | else | |
679 | ctrl |= DXEPCTL_SETEVENFR; | |
680 | } | |
681 | ||
47a1685f | 682 | ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */ |
71225bee | 683 | |
fe0b94ab | 684 | dev_dbg(hsotg->dev, "ep0 state:%d\n", hsotg->ep0_state); |
71225bee LM |
685 | |
686 | /* For Setup request do not clear NAK */ | |
fe0b94ab | 687 | if (!(index == 0 && hsotg->ep0_state == DWC2_EP0_SETUP)) |
47a1685f | 688 | ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */ |
71225bee | 689 | |
5b7d70c6 | 690 | dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl); |
95c8bc36 | 691 | dwc2_writel(ctrl, hsotg->regs + epctrl_reg); |
5b7d70c6 | 692 | |
8b9bc460 LM |
693 | /* |
694 | * set these, it seems that DMA support increments past the end | |
5b7d70c6 | 695 | * of the packet buffer so we need to calculate the length from |
8b9bc460 LM |
696 | * this information. |
697 | */ | |
5b7d70c6 BD |
698 | hs_ep->size_loaded = length; |
699 | hs_ep->last_load = ureq->actual; | |
700 | ||
701 | if (dir_in && !using_dma(hsotg)) { | |
702 | /* set these anyway, we may need them for non-periodic in */ | |
703 | hs_ep->fifo_load = 0; | |
704 | ||
1f91b4cc | 705 | dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req); |
5b7d70c6 BD |
706 | } |
707 | ||
8b9bc460 LM |
708 | /* |
709 | * Note, trying to clear the NAK here causes problems with transmit | |
710 | * on the S3C6400 ending up with the TXFIFO becoming full. | |
711 | */ | |
5b7d70c6 BD |
712 | |
713 | /* check ep is enabled */ | |
95c8bc36 | 714 | if (!(dwc2_readl(hsotg->regs + epctrl_reg) & DXEPCTL_EPENA)) |
1a0ed863 | 715 | dev_dbg(hsotg->dev, |
47a1685f | 716 | "ep%d: failed to become enabled (DXEPCTL=0x%08x)?\n", |
95c8bc36 | 717 | index, dwc2_readl(hsotg->regs + epctrl_reg)); |
5b7d70c6 | 718 | |
47a1685f | 719 | dev_dbg(hsotg->dev, "%s: DXEPCTL=0x%08x\n", |
95c8bc36 | 720 | __func__, dwc2_readl(hsotg->regs + epctrl_reg)); |
afcf4169 RB |
721 | |
722 | /* enable ep interrupts */ | |
1f91b4cc | 723 | dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 1); |
5b7d70c6 BD |
724 | } |
725 | ||
726 | /** | |
1f91b4cc | 727 | * dwc2_hsotg_map_dma - map the DMA memory being used for the request |
5b7d70c6 BD |
728 | * @hsotg: The device state. |
729 | * @hs_ep: The endpoint the request is on. | |
730 | * @req: The request being processed. | |
731 | * | |
732 | * We've been asked to queue a request, so ensure that the memory buffer | |
733 | * is correctly setup for DMA. If we've been passed an extant DMA address | |
734 | * then ensure the buffer has been synced to memory. If our buffer has no | |
735 | * DMA memory, then we map the memory and mark our request to allow us to | |
736 | * cleanup on completion. | |
8b9bc460 | 737 | */ |
1f91b4cc FB |
738 | static int dwc2_hsotg_map_dma(struct dwc2_hsotg *hsotg, |
739 | struct dwc2_hsotg_ep *hs_ep, | |
5b7d70c6 BD |
740 | struct usb_request *req) |
741 | { | |
1f91b4cc | 742 | struct dwc2_hsotg_req *hs_req = our_req(req); |
e58ebcd1 | 743 | int ret; |
5b7d70c6 BD |
744 | |
745 | /* if the length is zero, ignore the DMA data */ | |
746 | if (hs_req->req.length == 0) | |
747 | return 0; | |
748 | ||
e58ebcd1 FB |
749 | ret = usb_gadget_map_request(&hsotg->gadget, req, hs_ep->dir_in); |
750 | if (ret) | |
751 | goto dma_error; | |
5b7d70c6 BD |
752 | |
753 | return 0; | |
754 | ||
755 | dma_error: | |
756 | dev_err(hsotg->dev, "%s: failed to map buffer %p, %d bytes\n", | |
757 | __func__, req->buf, req->length); | |
758 | ||
759 | return -EIO; | |
760 | } | |
761 | ||
1f91b4cc FB |
762 | static int dwc2_hsotg_handle_unaligned_buf_start(struct dwc2_hsotg *hsotg, |
763 | struct dwc2_hsotg_ep *hs_ep, struct dwc2_hsotg_req *hs_req) | |
7d24c1b5 MYK |
764 | { |
765 | void *req_buf = hs_req->req.buf; | |
766 | ||
767 | /* If dma is not being used or buffer is aligned */ | |
768 | if (!using_dma(hsotg) || !((long)req_buf & 3)) | |
769 | return 0; | |
770 | ||
771 | WARN_ON(hs_req->saved_req_buf); | |
772 | ||
773 | dev_dbg(hsotg->dev, "%s: %s: buf=%p length=%d\n", __func__, | |
774 | hs_ep->ep.name, req_buf, hs_req->req.length); | |
775 | ||
776 | hs_req->req.buf = kmalloc(hs_req->req.length, GFP_ATOMIC); | |
777 | if (!hs_req->req.buf) { | |
778 | hs_req->req.buf = req_buf; | |
779 | dev_err(hsotg->dev, | |
780 | "%s: unable to allocate memory for bounce buffer\n", | |
781 | __func__); | |
782 | return -ENOMEM; | |
783 | } | |
784 | ||
785 | /* Save actual buffer */ | |
786 | hs_req->saved_req_buf = req_buf; | |
787 | ||
788 | if (hs_ep->dir_in) | |
789 | memcpy(hs_req->req.buf, req_buf, hs_req->req.length); | |
790 | return 0; | |
791 | } | |
792 | ||
1f91b4cc FB |
793 | static void dwc2_hsotg_handle_unaligned_buf_complete(struct dwc2_hsotg *hsotg, |
794 | struct dwc2_hsotg_ep *hs_ep, struct dwc2_hsotg_req *hs_req) | |
7d24c1b5 MYK |
795 | { |
796 | /* If dma is not being used or buffer was aligned */ | |
797 | if (!using_dma(hsotg) || !hs_req->saved_req_buf) | |
798 | return; | |
799 | ||
800 | dev_dbg(hsotg->dev, "%s: %s: status=%d actual-length=%d\n", __func__, | |
801 | hs_ep->ep.name, hs_req->req.status, hs_req->req.actual); | |
802 | ||
803 | /* Copy data from bounce buffer on successful out transfer */ | |
804 | if (!hs_ep->dir_in && !hs_req->req.status) | |
805 | memcpy(hs_req->saved_req_buf, hs_req->req.buf, | |
806 | hs_req->req.actual); | |
807 | ||
808 | /* Free bounce buffer */ | |
809 | kfree(hs_req->req.buf); | |
810 | ||
811 | hs_req->req.buf = hs_req->saved_req_buf; | |
812 | hs_req->saved_req_buf = NULL; | |
813 | } | |
814 | ||
381fc8f8 VM |
815 | /** |
816 | * dwc2_gadget_target_frame_elapsed - Checks target frame | |
817 | * @hs_ep: The driver endpoint to check | |
818 | * | |
819 | * Returns 1 if targeted frame elapsed. If returned 1 then we need to drop | |
820 | * corresponding transfer. | |
821 | */ | |
822 | static bool dwc2_gadget_target_frame_elapsed(struct dwc2_hsotg_ep *hs_ep) | |
823 | { | |
824 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
825 | u32 target_frame = hs_ep->target_frame; | |
826 | u32 current_frame = dwc2_hsotg_read_frameno(hsotg); | |
827 | bool frame_overrun = hs_ep->frame_overrun; | |
828 | ||
829 | if (!frame_overrun && current_frame >= target_frame) | |
830 | return true; | |
831 | ||
832 | if (frame_overrun && current_frame >= target_frame && | |
833 | ((current_frame - target_frame) < DSTS_SOFFN_LIMIT / 2)) | |
834 | return true; | |
835 | ||
836 | return false; | |
837 | } | |
838 | ||
1f91b4cc | 839 | static int dwc2_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req, |
5b7d70c6 BD |
840 | gfp_t gfp_flags) |
841 | { | |
1f91b4cc FB |
842 | struct dwc2_hsotg_req *hs_req = our_req(req); |
843 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); | |
941fcce4 | 844 | struct dwc2_hsotg *hs = hs_ep->parent; |
5b7d70c6 | 845 | bool first; |
7d24c1b5 | 846 | int ret; |
5b7d70c6 BD |
847 | |
848 | dev_dbg(hs->dev, "%s: req %p: %d@%p, noi=%d, zero=%d, snok=%d\n", | |
849 | ep->name, req, req->length, req->buf, req->no_interrupt, | |
850 | req->zero, req->short_not_ok); | |
851 | ||
7ababa92 GH |
852 | /* Prevent new request submission when controller is suspended */ |
853 | if (hs->lx_state == DWC2_L2) { | |
854 | dev_dbg(hs->dev, "%s: don't submit request while suspended\n", | |
855 | __func__); | |
856 | return -EAGAIN; | |
857 | } | |
858 | ||
5b7d70c6 BD |
859 | /* initialise status of the request */ |
860 | INIT_LIST_HEAD(&hs_req->queue); | |
861 | req->actual = 0; | |
862 | req->status = -EINPROGRESS; | |
863 | ||
1f91b4cc | 864 | ret = dwc2_hsotg_handle_unaligned_buf_start(hs, hs_ep, hs_req); |
7d24c1b5 MYK |
865 | if (ret) |
866 | return ret; | |
867 | ||
5b7d70c6 BD |
868 | /* if we're using DMA, sync the buffers as necessary */ |
869 | if (using_dma(hs)) { | |
1f91b4cc | 870 | ret = dwc2_hsotg_map_dma(hs, hs_ep, req); |
5b7d70c6 BD |
871 | if (ret) |
872 | return ret; | |
873 | } | |
874 | ||
5b7d70c6 BD |
875 | first = list_empty(&hs_ep->queue); |
876 | list_add_tail(&hs_req->queue, &hs_ep->queue); | |
877 | ||
837e9f00 VM |
878 | if (first) { |
879 | if (!hs_ep->isochronous) { | |
880 | dwc2_hsotg_start_req(hs, hs_ep, hs_req, false); | |
881 | return 0; | |
882 | } | |
883 | ||
884 | while (dwc2_gadget_target_frame_elapsed(hs_ep)) | |
885 | dwc2_gadget_incr_frame_num(hs_ep); | |
5b7d70c6 | 886 | |
837e9f00 VM |
887 | if (hs_ep->target_frame != TARGET_FRAME_INITIAL) |
888 | dwc2_hsotg_start_req(hs, hs_ep, hs_req, false); | |
889 | } | |
5b7d70c6 BD |
890 | return 0; |
891 | } | |
892 | ||
1f91b4cc | 893 | static int dwc2_hsotg_ep_queue_lock(struct usb_ep *ep, struct usb_request *req, |
5ad1d316 LM |
894 | gfp_t gfp_flags) |
895 | { | |
1f91b4cc | 896 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 897 | struct dwc2_hsotg *hs = hs_ep->parent; |
5ad1d316 LM |
898 | unsigned long flags = 0; |
899 | int ret = 0; | |
900 | ||
901 | spin_lock_irqsave(&hs->lock, flags); | |
1f91b4cc | 902 | ret = dwc2_hsotg_ep_queue(ep, req, gfp_flags); |
5ad1d316 LM |
903 | spin_unlock_irqrestore(&hs->lock, flags); |
904 | ||
905 | return ret; | |
906 | } | |
907 | ||
1f91b4cc | 908 | static void dwc2_hsotg_ep_free_request(struct usb_ep *ep, |
5b7d70c6 BD |
909 | struct usb_request *req) |
910 | { | |
1f91b4cc | 911 | struct dwc2_hsotg_req *hs_req = our_req(req); |
5b7d70c6 BD |
912 | |
913 | kfree(hs_req); | |
914 | } | |
915 | ||
916 | /** | |
1f91b4cc | 917 | * dwc2_hsotg_complete_oursetup - setup completion callback |
5b7d70c6 BD |
918 | * @ep: The endpoint the request was on. |
919 | * @req: The request completed. | |
920 | * | |
921 | * Called on completion of any requests the driver itself | |
922 | * submitted that need cleaning up. | |
923 | */ | |
1f91b4cc | 924 | static void dwc2_hsotg_complete_oursetup(struct usb_ep *ep, |
5b7d70c6 BD |
925 | struct usb_request *req) |
926 | { | |
1f91b4cc | 927 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 928 | struct dwc2_hsotg *hsotg = hs_ep->parent; |
5b7d70c6 BD |
929 | |
930 | dev_dbg(hsotg->dev, "%s: ep %p, req %p\n", __func__, ep, req); | |
931 | ||
1f91b4cc | 932 | dwc2_hsotg_ep_free_request(ep, req); |
5b7d70c6 BD |
933 | } |
934 | ||
935 | /** | |
936 | * ep_from_windex - convert control wIndex value to endpoint | |
937 | * @hsotg: The driver state. | |
938 | * @windex: The control request wIndex field (in host order). | |
939 | * | |
940 | * Convert the given wIndex into a pointer to an driver endpoint | |
941 | * structure, or return NULL if it is not a valid endpoint. | |
8b9bc460 | 942 | */ |
1f91b4cc | 943 | static struct dwc2_hsotg_ep *ep_from_windex(struct dwc2_hsotg *hsotg, |
5b7d70c6 BD |
944 | u32 windex) |
945 | { | |
1f91b4cc | 946 | struct dwc2_hsotg_ep *ep; |
5b7d70c6 BD |
947 | int dir = (windex & USB_DIR_IN) ? 1 : 0; |
948 | int idx = windex & 0x7F; | |
949 | ||
950 | if (windex >= 0x100) | |
951 | return NULL; | |
952 | ||
b3f489b2 | 953 | if (idx > hsotg->num_of_eps) |
5b7d70c6 BD |
954 | return NULL; |
955 | ||
c6f5c050 MYK |
956 | ep = index_to_ep(hsotg, idx, dir); |
957 | ||
5b7d70c6 BD |
958 | if (idx && ep->dir_in != dir) |
959 | return NULL; | |
960 | ||
961 | return ep; | |
962 | } | |
963 | ||
9e14d0a5 | 964 | /** |
1f91b4cc | 965 | * dwc2_hsotg_set_test_mode - Enable usb Test Modes |
9e14d0a5 GH |
966 | * @hsotg: The driver state. |
967 | * @testmode: requested usb test mode | |
968 | * Enable usb Test Mode requested by the Host. | |
969 | */ | |
1f91b4cc | 970 | int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode) |
9e14d0a5 | 971 | { |
95c8bc36 | 972 | int dctl = dwc2_readl(hsotg->regs + DCTL); |
9e14d0a5 GH |
973 | |
974 | dctl &= ~DCTL_TSTCTL_MASK; | |
975 | switch (testmode) { | |
976 | case TEST_J: | |
977 | case TEST_K: | |
978 | case TEST_SE0_NAK: | |
979 | case TEST_PACKET: | |
980 | case TEST_FORCE_EN: | |
981 | dctl |= testmode << DCTL_TSTCTL_SHIFT; | |
982 | break; | |
983 | default: | |
984 | return -EINVAL; | |
985 | } | |
95c8bc36 | 986 | dwc2_writel(dctl, hsotg->regs + DCTL); |
9e14d0a5 GH |
987 | return 0; |
988 | } | |
989 | ||
5b7d70c6 | 990 | /** |
1f91b4cc | 991 | * dwc2_hsotg_send_reply - send reply to control request |
5b7d70c6 BD |
992 | * @hsotg: The device state |
993 | * @ep: Endpoint 0 | |
994 | * @buff: Buffer for request | |
995 | * @length: Length of reply. | |
996 | * | |
997 | * Create a request and queue it on the given endpoint. This is useful as | |
998 | * an internal method of sending replies to certain control requests, etc. | |
999 | */ | |
1f91b4cc FB |
1000 | static int dwc2_hsotg_send_reply(struct dwc2_hsotg *hsotg, |
1001 | struct dwc2_hsotg_ep *ep, | |
5b7d70c6 BD |
1002 | void *buff, |
1003 | int length) | |
1004 | { | |
1005 | struct usb_request *req; | |
1006 | int ret; | |
1007 | ||
1008 | dev_dbg(hsotg->dev, "%s: buff %p, len %d\n", __func__, buff, length); | |
1009 | ||
1f91b4cc | 1010 | req = dwc2_hsotg_ep_alloc_request(&ep->ep, GFP_ATOMIC); |
5b7d70c6 BD |
1011 | hsotg->ep0_reply = req; |
1012 | if (!req) { | |
1013 | dev_warn(hsotg->dev, "%s: cannot alloc req\n", __func__); | |
1014 | return -ENOMEM; | |
1015 | } | |
1016 | ||
1017 | req->buf = hsotg->ep0_buff; | |
1018 | req->length = length; | |
f71b5e25 MYK |
1019 | /* |
1020 | * zero flag is for sending zlp in DATA IN stage. It has no impact on | |
1021 | * STATUS stage. | |
1022 | */ | |
1023 | req->zero = 0; | |
1f91b4cc | 1024 | req->complete = dwc2_hsotg_complete_oursetup; |
5b7d70c6 BD |
1025 | |
1026 | if (length) | |
1027 | memcpy(req->buf, buff, length); | |
5b7d70c6 | 1028 | |
1f91b4cc | 1029 | ret = dwc2_hsotg_ep_queue(&ep->ep, req, GFP_ATOMIC); |
5b7d70c6 BD |
1030 | if (ret) { |
1031 | dev_warn(hsotg->dev, "%s: cannot queue req\n", __func__); | |
1032 | return ret; | |
1033 | } | |
1034 | ||
1035 | return 0; | |
1036 | } | |
1037 | ||
1038 | /** | |
1f91b4cc | 1039 | * dwc2_hsotg_process_req_status - process request GET_STATUS |
5b7d70c6 BD |
1040 | * @hsotg: The device state |
1041 | * @ctrl: USB control request | |
1042 | */ | |
1f91b4cc | 1043 | static int dwc2_hsotg_process_req_status(struct dwc2_hsotg *hsotg, |
5b7d70c6 BD |
1044 | struct usb_ctrlrequest *ctrl) |
1045 | { | |
1f91b4cc FB |
1046 | struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0]; |
1047 | struct dwc2_hsotg_ep *ep; | |
5b7d70c6 BD |
1048 | __le16 reply; |
1049 | int ret; | |
1050 | ||
1051 | dev_dbg(hsotg->dev, "%s: USB_REQ_GET_STATUS\n", __func__); | |
1052 | ||
1053 | if (!ep0->dir_in) { | |
1054 | dev_warn(hsotg->dev, "%s: direction out?\n", __func__); | |
1055 | return -EINVAL; | |
1056 | } | |
1057 | ||
1058 | switch (ctrl->bRequestType & USB_RECIP_MASK) { | |
1059 | case USB_RECIP_DEVICE: | |
1060 | reply = cpu_to_le16(0); /* bit 0 => self powered, | |
1061 | * bit 1 => remote wakeup */ | |
1062 | break; | |
1063 | ||
1064 | case USB_RECIP_INTERFACE: | |
1065 | /* currently, the data result should be zero */ | |
1066 | reply = cpu_to_le16(0); | |
1067 | break; | |
1068 | ||
1069 | case USB_RECIP_ENDPOINT: | |
1070 | ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex)); | |
1071 | if (!ep) | |
1072 | return -ENOENT; | |
1073 | ||
1074 | reply = cpu_to_le16(ep->halted ? 1 : 0); | |
1075 | break; | |
1076 | ||
1077 | default: | |
1078 | return 0; | |
1079 | } | |
1080 | ||
1081 | if (le16_to_cpu(ctrl->wLength) != 2) | |
1082 | return -EINVAL; | |
1083 | ||
1f91b4cc | 1084 | ret = dwc2_hsotg_send_reply(hsotg, ep0, &reply, 2); |
5b7d70c6 BD |
1085 | if (ret) { |
1086 | dev_err(hsotg->dev, "%s: failed to send reply\n", __func__); | |
1087 | return ret; | |
1088 | } | |
1089 | ||
1090 | return 1; | |
1091 | } | |
1092 | ||
51da43b5 | 1093 | static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now); |
5b7d70c6 | 1094 | |
9c39ddc6 AT |
1095 | /** |
1096 | * get_ep_head - return the first request on the endpoint | |
1097 | * @hs_ep: The controller endpoint to get | |
1098 | * | |
1099 | * Get the first request on the endpoint. | |
1100 | */ | |
1f91b4cc | 1101 | static struct dwc2_hsotg_req *get_ep_head(struct dwc2_hsotg_ep *hs_ep) |
9c39ddc6 AT |
1102 | { |
1103 | if (list_empty(&hs_ep->queue)) | |
1104 | return NULL; | |
1105 | ||
1f91b4cc | 1106 | return list_first_entry(&hs_ep->queue, struct dwc2_hsotg_req, queue); |
9c39ddc6 AT |
1107 | } |
1108 | ||
41cc4cd2 VM |
1109 | /** |
1110 | * dwc2_gadget_start_next_request - Starts next request from ep queue | |
1111 | * @hs_ep: Endpoint structure | |
1112 | * | |
1113 | * If queue is empty and EP is ISOC-OUT - unmasks OUTTKNEPDIS which is masked | |
1114 | * in its handler. Hence we need to unmask it here to be able to do | |
1115 | * resynchronization. | |
1116 | */ | |
1117 | static void dwc2_gadget_start_next_request(struct dwc2_hsotg_ep *hs_ep) | |
1118 | { | |
1119 | u32 mask; | |
1120 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
1121 | int dir_in = hs_ep->dir_in; | |
1122 | struct dwc2_hsotg_req *hs_req; | |
1123 | u32 epmsk_reg = dir_in ? DIEPMSK : DOEPMSK; | |
1124 | ||
1125 | if (!list_empty(&hs_ep->queue)) { | |
1126 | hs_req = get_ep_head(hs_ep); | |
1127 | dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, false); | |
1128 | return; | |
1129 | } | |
1130 | if (!hs_ep->isochronous) | |
1131 | return; | |
1132 | ||
1133 | if (dir_in) { | |
1134 | dev_dbg(hsotg->dev, "%s: No more ISOC-IN requests\n", | |
1135 | __func__); | |
1136 | } else { | |
1137 | dev_dbg(hsotg->dev, "%s: No more ISOC-OUT requests\n", | |
1138 | __func__); | |
1139 | mask = dwc2_readl(hsotg->regs + epmsk_reg); | |
1140 | mask |= DOEPMSK_OUTTKNEPDISMSK; | |
1141 | dwc2_writel(mask, hsotg->regs + epmsk_reg); | |
1142 | } | |
1143 | } | |
1144 | ||
5b7d70c6 | 1145 | /** |
1f91b4cc | 1146 | * dwc2_hsotg_process_req_feature - process request {SET,CLEAR}_FEATURE |
5b7d70c6 BD |
1147 | * @hsotg: The device state |
1148 | * @ctrl: USB control request | |
1149 | */ | |
1f91b4cc | 1150 | static int dwc2_hsotg_process_req_feature(struct dwc2_hsotg *hsotg, |
5b7d70c6 BD |
1151 | struct usb_ctrlrequest *ctrl) |
1152 | { | |
1f91b4cc FB |
1153 | struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0]; |
1154 | struct dwc2_hsotg_req *hs_req; | |
5b7d70c6 | 1155 | bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE); |
1f91b4cc | 1156 | struct dwc2_hsotg_ep *ep; |
26ab3d0c | 1157 | int ret; |
bd9ef7bf | 1158 | bool halted; |
9e14d0a5 GH |
1159 | u32 recip; |
1160 | u32 wValue; | |
1161 | u32 wIndex; | |
5b7d70c6 BD |
1162 | |
1163 | dev_dbg(hsotg->dev, "%s: %s_FEATURE\n", | |
1164 | __func__, set ? "SET" : "CLEAR"); | |
1165 | ||
9e14d0a5 GH |
1166 | wValue = le16_to_cpu(ctrl->wValue); |
1167 | wIndex = le16_to_cpu(ctrl->wIndex); | |
1168 | recip = ctrl->bRequestType & USB_RECIP_MASK; | |
1169 | ||
1170 | switch (recip) { | |
1171 | case USB_RECIP_DEVICE: | |
1172 | switch (wValue) { | |
1173 | case USB_DEVICE_TEST_MODE: | |
1174 | if ((wIndex & 0xff) != 0) | |
1175 | return -EINVAL; | |
1176 | if (!set) | |
1177 | return -EINVAL; | |
1178 | ||
1179 | hsotg->test_mode = wIndex >> 8; | |
1f91b4cc | 1180 | ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0); |
9e14d0a5 GH |
1181 | if (ret) { |
1182 | dev_err(hsotg->dev, | |
1183 | "%s: failed to send reply\n", __func__); | |
1184 | return ret; | |
1185 | } | |
1186 | break; | |
1187 | default: | |
1188 | return -ENOENT; | |
1189 | } | |
1190 | break; | |
1191 | ||
1192 | case USB_RECIP_ENDPOINT: | |
1193 | ep = ep_from_windex(hsotg, wIndex); | |
5b7d70c6 BD |
1194 | if (!ep) { |
1195 | dev_dbg(hsotg->dev, "%s: no endpoint for 0x%04x\n", | |
9e14d0a5 | 1196 | __func__, wIndex); |
5b7d70c6 BD |
1197 | return -ENOENT; |
1198 | } | |
1199 | ||
9e14d0a5 | 1200 | switch (wValue) { |
5b7d70c6 | 1201 | case USB_ENDPOINT_HALT: |
bd9ef7bf RB |
1202 | halted = ep->halted; |
1203 | ||
51da43b5 | 1204 | dwc2_hsotg_ep_sethalt(&ep->ep, set, true); |
26ab3d0c | 1205 | |
1f91b4cc | 1206 | ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0); |
26ab3d0c AT |
1207 | if (ret) { |
1208 | dev_err(hsotg->dev, | |
1209 | "%s: failed to send reply\n", __func__); | |
1210 | return ret; | |
1211 | } | |
9c39ddc6 | 1212 | |
bd9ef7bf RB |
1213 | /* |
1214 | * we have to complete all requests for ep if it was | |
1215 | * halted, and the halt was cleared by CLEAR_FEATURE | |
1216 | */ | |
1217 | ||
1218 | if (!set && halted) { | |
9c39ddc6 AT |
1219 | /* |
1220 | * If we have request in progress, | |
1221 | * then complete it | |
1222 | */ | |
1223 | if (ep->req) { | |
1224 | hs_req = ep->req; | |
1225 | ep->req = NULL; | |
1226 | list_del_init(&hs_req->queue); | |
c00dd4a6 GH |
1227 | if (hs_req->req.complete) { |
1228 | spin_unlock(&hsotg->lock); | |
1229 | usb_gadget_giveback_request( | |
1230 | &ep->ep, &hs_req->req); | |
1231 | spin_lock(&hsotg->lock); | |
1232 | } | |
9c39ddc6 AT |
1233 | } |
1234 | ||
1235 | /* If we have pending request, then start it */ | |
c00dd4a6 | 1236 | if (!ep->req) { |
41cc4cd2 | 1237 | dwc2_gadget_start_next_request(ep); |
9c39ddc6 AT |
1238 | } |
1239 | } | |
1240 | ||
5b7d70c6 BD |
1241 | break; |
1242 | ||
1243 | default: | |
1244 | return -ENOENT; | |
1245 | } | |
9e14d0a5 GH |
1246 | break; |
1247 | default: | |
1248 | return -ENOENT; | |
1249 | } | |
5b7d70c6 BD |
1250 | return 1; |
1251 | } | |
1252 | ||
1f91b4cc | 1253 | static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg); |
ab93e014 | 1254 | |
c9f721b2 | 1255 | /** |
1f91b4cc | 1256 | * dwc2_hsotg_stall_ep0 - stall ep0 |
c9f721b2 RB |
1257 | * @hsotg: The device state |
1258 | * | |
1259 | * Set stall for ep0 as response for setup request. | |
1260 | */ | |
1f91b4cc | 1261 | static void dwc2_hsotg_stall_ep0(struct dwc2_hsotg *hsotg) |
e9ebe7c3 | 1262 | { |
1f91b4cc | 1263 | struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0]; |
c9f721b2 RB |
1264 | u32 reg; |
1265 | u32 ctrl; | |
1266 | ||
1267 | dev_dbg(hsotg->dev, "ep0 stall (dir=%d)\n", ep0->dir_in); | |
1268 | reg = (ep0->dir_in) ? DIEPCTL0 : DOEPCTL0; | |
1269 | ||
1270 | /* | |
1271 | * DxEPCTL_Stall will be cleared by EP once it has | |
1272 | * taken effect, so no need to clear later. | |
1273 | */ | |
1274 | ||
95c8bc36 | 1275 | ctrl = dwc2_readl(hsotg->regs + reg); |
47a1685f DN |
1276 | ctrl |= DXEPCTL_STALL; |
1277 | ctrl |= DXEPCTL_CNAK; | |
95c8bc36 | 1278 | dwc2_writel(ctrl, hsotg->regs + reg); |
c9f721b2 RB |
1279 | |
1280 | dev_dbg(hsotg->dev, | |
47a1685f | 1281 | "written DXEPCTL=0x%08x to %08x (DXEPCTL=0x%08x)\n", |
95c8bc36 | 1282 | ctrl, reg, dwc2_readl(hsotg->regs + reg)); |
c9f721b2 RB |
1283 | |
1284 | /* | |
1285 | * complete won't be called, so we enqueue | |
1286 | * setup request here | |
1287 | */ | |
1f91b4cc | 1288 | dwc2_hsotg_enqueue_setup(hsotg); |
c9f721b2 RB |
1289 | } |
1290 | ||
5b7d70c6 | 1291 | /** |
1f91b4cc | 1292 | * dwc2_hsotg_process_control - process a control request |
5b7d70c6 BD |
1293 | * @hsotg: The device state |
1294 | * @ctrl: The control request received | |
1295 | * | |
1296 | * The controller has received the SETUP phase of a control request, and | |
1297 | * needs to work out what to do next (and whether to pass it on to the | |
1298 | * gadget driver). | |
1299 | */ | |
1f91b4cc | 1300 | static void dwc2_hsotg_process_control(struct dwc2_hsotg *hsotg, |
5b7d70c6 BD |
1301 | struct usb_ctrlrequest *ctrl) |
1302 | { | |
1f91b4cc | 1303 | struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0]; |
5b7d70c6 BD |
1304 | int ret = 0; |
1305 | u32 dcfg; | |
1306 | ||
e525e743 MYK |
1307 | dev_dbg(hsotg->dev, |
1308 | "ctrl Type=%02x, Req=%02x, V=%04x, I=%04x, L=%04x\n", | |
1309 | ctrl->bRequestType, ctrl->bRequest, ctrl->wValue, | |
1310 | ctrl->wIndex, ctrl->wLength); | |
5b7d70c6 | 1311 | |
fe0b94ab MYK |
1312 | if (ctrl->wLength == 0) { |
1313 | ep0->dir_in = 1; | |
1314 | hsotg->ep0_state = DWC2_EP0_STATUS_IN; | |
1315 | } else if (ctrl->bRequestType & USB_DIR_IN) { | |
5b7d70c6 | 1316 | ep0->dir_in = 1; |
fe0b94ab MYK |
1317 | hsotg->ep0_state = DWC2_EP0_DATA_IN; |
1318 | } else { | |
1319 | ep0->dir_in = 0; | |
1320 | hsotg->ep0_state = DWC2_EP0_DATA_OUT; | |
1321 | } | |
5b7d70c6 BD |
1322 | |
1323 | if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) { | |
1324 | switch (ctrl->bRequest) { | |
1325 | case USB_REQ_SET_ADDRESS: | |
6d713c15 | 1326 | hsotg->connected = 1; |
95c8bc36 | 1327 | dcfg = dwc2_readl(hsotg->regs + DCFG); |
47a1685f | 1328 | dcfg &= ~DCFG_DEVADDR_MASK; |
d5dbd3f7 PZ |
1329 | dcfg |= (le16_to_cpu(ctrl->wValue) << |
1330 | DCFG_DEVADDR_SHIFT) & DCFG_DEVADDR_MASK; | |
95c8bc36 | 1331 | dwc2_writel(dcfg, hsotg->regs + DCFG); |
5b7d70c6 BD |
1332 | |
1333 | dev_info(hsotg->dev, "new address %d\n", ctrl->wValue); | |
1334 | ||
1f91b4cc | 1335 | ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0); |
5b7d70c6 BD |
1336 | return; |
1337 | ||
1338 | case USB_REQ_GET_STATUS: | |
1f91b4cc | 1339 | ret = dwc2_hsotg_process_req_status(hsotg, ctrl); |
5b7d70c6 BD |
1340 | break; |
1341 | ||
1342 | case USB_REQ_CLEAR_FEATURE: | |
1343 | case USB_REQ_SET_FEATURE: | |
1f91b4cc | 1344 | ret = dwc2_hsotg_process_req_feature(hsotg, ctrl); |
5b7d70c6 BD |
1345 | break; |
1346 | } | |
1347 | } | |
1348 | ||
1349 | /* as a fallback, try delivering it to the driver to deal with */ | |
1350 | ||
1351 | if (ret == 0 && hsotg->driver) { | |
93f599f2 | 1352 | spin_unlock(&hsotg->lock); |
5b7d70c6 | 1353 | ret = hsotg->driver->setup(&hsotg->gadget, ctrl); |
93f599f2 | 1354 | spin_lock(&hsotg->lock); |
5b7d70c6 BD |
1355 | if (ret < 0) |
1356 | dev_dbg(hsotg->dev, "driver->setup() ret %d\n", ret); | |
1357 | } | |
1358 | ||
8b9bc460 LM |
1359 | /* |
1360 | * the request is either unhandlable, or is not formatted correctly | |
5b7d70c6 BD |
1361 | * so respond with a STALL for the status stage to indicate failure. |
1362 | */ | |
1363 | ||
c9f721b2 | 1364 | if (ret < 0) |
1f91b4cc | 1365 | dwc2_hsotg_stall_ep0(hsotg); |
5b7d70c6 BD |
1366 | } |
1367 | ||
5b7d70c6 | 1368 | /** |
1f91b4cc | 1369 | * dwc2_hsotg_complete_setup - completion of a setup transfer |
5b7d70c6 BD |
1370 | * @ep: The endpoint the request was on. |
1371 | * @req: The request completed. | |
1372 | * | |
1373 | * Called on completion of any requests the driver itself submitted for | |
1374 | * EP0 setup packets | |
1375 | */ | |
1f91b4cc | 1376 | static void dwc2_hsotg_complete_setup(struct usb_ep *ep, |
5b7d70c6 BD |
1377 | struct usb_request *req) |
1378 | { | |
1f91b4cc | 1379 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 1380 | struct dwc2_hsotg *hsotg = hs_ep->parent; |
5b7d70c6 BD |
1381 | |
1382 | if (req->status < 0) { | |
1383 | dev_dbg(hsotg->dev, "%s: failed %d\n", __func__, req->status); | |
1384 | return; | |
1385 | } | |
1386 | ||
93f599f2 | 1387 | spin_lock(&hsotg->lock); |
5b7d70c6 | 1388 | if (req->actual == 0) |
1f91b4cc | 1389 | dwc2_hsotg_enqueue_setup(hsotg); |
5b7d70c6 | 1390 | else |
1f91b4cc | 1391 | dwc2_hsotg_process_control(hsotg, req->buf); |
93f599f2 | 1392 | spin_unlock(&hsotg->lock); |
5b7d70c6 BD |
1393 | } |
1394 | ||
1395 | /** | |
1f91b4cc | 1396 | * dwc2_hsotg_enqueue_setup - start a request for EP0 packets |
5b7d70c6 BD |
1397 | * @hsotg: The device state. |
1398 | * | |
1399 | * Enqueue a request on EP0 if necessary to received any SETUP packets | |
1400 | * received from the host. | |
1401 | */ | |
1f91b4cc | 1402 | static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg) |
5b7d70c6 BD |
1403 | { |
1404 | struct usb_request *req = hsotg->ctrl_req; | |
1f91b4cc | 1405 | struct dwc2_hsotg_req *hs_req = our_req(req); |
5b7d70c6 BD |
1406 | int ret; |
1407 | ||
1408 | dev_dbg(hsotg->dev, "%s: queueing setup request\n", __func__); | |
1409 | ||
1410 | req->zero = 0; | |
1411 | req->length = 8; | |
1412 | req->buf = hsotg->ctrl_buff; | |
1f91b4cc | 1413 | req->complete = dwc2_hsotg_complete_setup; |
5b7d70c6 BD |
1414 | |
1415 | if (!list_empty(&hs_req->queue)) { | |
1416 | dev_dbg(hsotg->dev, "%s already queued???\n", __func__); | |
1417 | return; | |
1418 | } | |
1419 | ||
c6f5c050 | 1420 | hsotg->eps_out[0]->dir_in = 0; |
8a20fa45 | 1421 | hsotg->eps_out[0]->send_zlp = 0; |
fe0b94ab | 1422 | hsotg->ep0_state = DWC2_EP0_SETUP; |
5b7d70c6 | 1423 | |
1f91b4cc | 1424 | ret = dwc2_hsotg_ep_queue(&hsotg->eps_out[0]->ep, req, GFP_ATOMIC); |
5b7d70c6 BD |
1425 | if (ret < 0) { |
1426 | dev_err(hsotg->dev, "%s: failed queue (%d)\n", __func__, ret); | |
8b9bc460 LM |
1427 | /* |
1428 | * Don't think there's much we can do other than watch the | |
1429 | * driver fail. | |
1430 | */ | |
5b7d70c6 BD |
1431 | } |
1432 | } | |
1433 | ||
1f91b4cc FB |
1434 | static void dwc2_hsotg_program_zlp(struct dwc2_hsotg *hsotg, |
1435 | struct dwc2_hsotg_ep *hs_ep) | |
fe0b94ab MYK |
1436 | { |
1437 | u32 ctrl; | |
1438 | u8 index = hs_ep->index; | |
1439 | u32 epctl_reg = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index); | |
1440 | u32 epsiz_reg = hs_ep->dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index); | |
1441 | ||
ccb34a91 MYK |
1442 | if (hs_ep->dir_in) |
1443 | dev_dbg(hsotg->dev, "Sending zero-length packet on ep%d\n", | |
1444 | index); | |
1445 | else | |
1446 | dev_dbg(hsotg->dev, "Receiving zero-length packet on ep%d\n", | |
1447 | index); | |
fe0b94ab | 1448 | |
95c8bc36 AS |
1449 | dwc2_writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) | |
1450 | DXEPTSIZ_XFERSIZE(0), hsotg->regs + | |
1451 | epsiz_reg); | |
fe0b94ab | 1452 | |
95c8bc36 | 1453 | ctrl = dwc2_readl(hsotg->regs + epctl_reg); |
fe0b94ab MYK |
1454 | ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */ |
1455 | ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */ | |
1456 | ctrl |= DXEPCTL_USBACTEP; | |
95c8bc36 | 1457 | dwc2_writel(ctrl, hsotg->regs + epctl_reg); |
fe0b94ab MYK |
1458 | } |
1459 | ||
5b7d70c6 | 1460 | /** |
1f91b4cc | 1461 | * dwc2_hsotg_complete_request - complete a request given to us |
5b7d70c6 BD |
1462 | * @hsotg: The device state. |
1463 | * @hs_ep: The endpoint the request was on. | |
1464 | * @hs_req: The request to complete. | |
1465 | * @result: The result code (0 => Ok, otherwise errno) | |
1466 | * | |
1467 | * The given request has finished, so call the necessary completion | |
1468 | * if it has one and then look to see if we can start a new request | |
1469 | * on the endpoint. | |
1470 | * | |
1471 | * Note, expects the ep to already be locked as appropriate. | |
8b9bc460 | 1472 | */ |
1f91b4cc FB |
1473 | static void dwc2_hsotg_complete_request(struct dwc2_hsotg *hsotg, |
1474 | struct dwc2_hsotg_ep *hs_ep, | |
1475 | struct dwc2_hsotg_req *hs_req, | |
5b7d70c6 BD |
1476 | int result) |
1477 | { | |
5b7d70c6 BD |
1478 | |
1479 | if (!hs_req) { | |
1480 | dev_dbg(hsotg->dev, "%s: nothing to complete?\n", __func__); | |
1481 | return; | |
1482 | } | |
1483 | ||
1484 | dev_dbg(hsotg->dev, "complete: ep %p %s, req %p, %d => %p\n", | |
1485 | hs_ep, hs_ep->ep.name, hs_req, result, hs_req->req.complete); | |
1486 | ||
8b9bc460 LM |
1487 | /* |
1488 | * only replace the status if we've not already set an error | |
1489 | * from a previous transaction | |
1490 | */ | |
5b7d70c6 BD |
1491 | |
1492 | if (hs_req->req.status == -EINPROGRESS) | |
1493 | hs_req->req.status = result; | |
1494 | ||
44583fec YL |
1495 | if (using_dma(hsotg)) |
1496 | dwc2_hsotg_unmap_dma(hsotg, hs_ep, hs_req); | |
1497 | ||
1f91b4cc | 1498 | dwc2_hsotg_handle_unaligned_buf_complete(hsotg, hs_ep, hs_req); |
7d24c1b5 | 1499 | |
5b7d70c6 BD |
1500 | hs_ep->req = NULL; |
1501 | list_del_init(&hs_req->queue); | |
1502 | ||
8b9bc460 LM |
1503 | /* |
1504 | * call the complete request with the locks off, just in case the | |
1505 | * request tries to queue more work for this endpoint. | |
1506 | */ | |
5b7d70c6 BD |
1507 | |
1508 | if (hs_req->req.complete) { | |
22258f49 | 1509 | spin_unlock(&hsotg->lock); |
304f7e5e | 1510 | usb_gadget_giveback_request(&hs_ep->ep, &hs_req->req); |
22258f49 | 1511 | spin_lock(&hsotg->lock); |
5b7d70c6 BD |
1512 | } |
1513 | ||
8b9bc460 LM |
1514 | /* |
1515 | * Look to see if there is anything else to do. Note, the completion | |
5b7d70c6 | 1516 | * of the previous request may have caused a new request to be started |
8b9bc460 LM |
1517 | * so be careful when doing this. |
1518 | */ | |
5b7d70c6 BD |
1519 | |
1520 | if (!hs_ep->req && result >= 0) { | |
41cc4cd2 | 1521 | dwc2_gadget_start_next_request(hs_ep); |
5b7d70c6 BD |
1522 | } |
1523 | } | |
1524 | ||
5b7d70c6 | 1525 | /** |
1f91b4cc | 1526 | * dwc2_hsotg_rx_data - receive data from the FIFO for an endpoint |
5b7d70c6 BD |
1527 | * @hsotg: The device state. |
1528 | * @ep_idx: The endpoint index for the data | |
1529 | * @size: The size of data in the fifo, in bytes | |
1530 | * | |
1531 | * The FIFO status shows there is data to read from the FIFO for a given | |
1532 | * endpoint, so sort out whether we need to read the data into a request | |
1533 | * that has been made for that endpoint. | |
1534 | */ | |
1f91b4cc | 1535 | static void dwc2_hsotg_rx_data(struct dwc2_hsotg *hsotg, int ep_idx, int size) |
5b7d70c6 | 1536 | { |
1f91b4cc FB |
1537 | struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[ep_idx]; |
1538 | struct dwc2_hsotg_req *hs_req = hs_ep->req; | |
94cb8fd6 | 1539 | void __iomem *fifo = hsotg->regs + EPFIFO(ep_idx); |
5b7d70c6 BD |
1540 | int to_read; |
1541 | int max_req; | |
1542 | int read_ptr; | |
1543 | ||
22258f49 | 1544 | |
5b7d70c6 | 1545 | if (!hs_req) { |
95c8bc36 | 1546 | u32 epctl = dwc2_readl(hsotg->regs + DOEPCTL(ep_idx)); |
5b7d70c6 BD |
1547 | int ptr; |
1548 | ||
6b448af4 | 1549 | dev_dbg(hsotg->dev, |
47a1685f | 1550 | "%s: FIFO %d bytes on ep%d but no req (DXEPCTl=0x%08x)\n", |
5b7d70c6 BD |
1551 | __func__, size, ep_idx, epctl); |
1552 | ||
1553 | /* dump the data from the FIFO, we've nothing we can do */ | |
1554 | for (ptr = 0; ptr < size; ptr += 4) | |
95c8bc36 | 1555 | (void)dwc2_readl(fifo); |
5b7d70c6 BD |
1556 | |
1557 | return; | |
1558 | } | |
1559 | ||
5b7d70c6 BD |
1560 | to_read = size; |
1561 | read_ptr = hs_req->req.actual; | |
1562 | max_req = hs_req->req.length - read_ptr; | |
1563 | ||
a33e7136 BD |
1564 | dev_dbg(hsotg->dev, "%s: read %d/%d, done %d/%d\n", |
1565 | __func__, to_read, max_req, read_ptr, hs_req->req.length); | |
1566 | ||
5b7d70c6 | 1567 | if (to_read > max_req) { |
8b9bc460 LM |
1568 | /* |
1569 | * more data appeared than we where willing | |
5b7d70c6 BD |
1570 | * to deal with in this request. |
1571 | */ | |
1572 | ||
1573 | /* currently we don't deal this */ | |
1574 | WARN_ON_ONCE(1); | |
1575 | } | |
1576 | ||
5b7d70c6 BD |
1577 | hs_ep->total_data += to_read; |
1578 | hs_req->req.actual += to_read; | |
1579 | to_read = DIV_ROUND_UP(to_read, 4); | |
1580 | ||
8b9bc460 LM |
1581 | /* |
1582 | * note, we might over-write the buffer end by 3 bytes depending on | |
1583 | * alignment of the data. | |
1584 | */ | |
1a7ed5be | 1585 | ioread32_rep(fifo, hs_req->req.buf + read_ptr, to_read); |
5b7d70c6 BD |
1586 | } |
1587 | ||
1588 | /** | |
1f91b4cc | 1589 | * dwc2_hsotg_ep0_zlp - send/receive zero-length packet on control endpoint |
5b7d70c6 | 1590 | * @hsotg: The device instance |
fe0b94ab | 1591 | * @dir_in: If IN zlp |
5b7d70c6 BD |
1592 | * |
1593 | * Generate a zero-length IN packet request for terminating a SETUP | |
1594 | * transaction. | |
1595 | * | |
1596 | * Note, since we don't write any data to the TxFIFO, then it is | |
25985edc | 1597 | * currently believed that we do not need to wait for any space in |
5b7d70c6 BD |
1598 | * the TxFIFO. |
1599 | */ | |
1f91b4cc | 1600 | static void dwc2_hsotg_ep0_zlp(struct dwc2_hsotg *hsotg, bool dir_in) |
5b7d70c6 | 1601 | { |
c6f5c050 | 1602 | /* eps_out[0] is used in both directions */ |
fe0b94ab MYK |
1603 | hsotg->eps_out[0]->dir_in = dir_in; |
1604 | hsotg->ep0_state = dir_in ? DWC2_EP0_STATUS_IN : DWC2_EP0_STATUS_OUT; | |
5b7d70c6 | 1605 | |
1f91b4cc | 1606 | dwc2_hsotg_program_zlp(hsotg, hsotg->eps_out[0]); |
5b7d70c6 BD |
1607 | } |
1608 | ||
ec1f9d9f RB |
1609 | static void dwc2_hsotg_change_ep_iso_parity(struct dwc2_hsotg *hsotg, |
1610 | u32 epctl_reg) | |
1611 | { | |
1612 | u32 ctrl; | |
1613 | ||
1614 | ctrl = dwc2_readl(hsotg->regs + epctl_reg); | |
1615 | if (ctrl & DXEPCTL_EOFRNUM) | |
1616 | ctrl |= DXEPCTL_SETEVENFR; | |
1617 | else | |
1618 | ctrl |= DXEPCTL_SETODDFR; | |
1619 | dwc2_writel(ctrl, hsotg->regs + epctl_reg); | |
1620 | } | |
1621 | ||
5b7d70c6 | 1622 | /** |
1f91b4cc | 1623 | * dwc2_hsotg_handle_outdone - handle receiving OutDone/SetupDone from RXFIFO |
5b7d70c6 BD |
1624 | * @hsotg: The device instance |
1625 | * @epnum: The endpoint received from | |
5b7d70c6 BD |
1626 | * |
1627 | * The RXFIFO has delivered an OutDone event, which means that the data | |
1628 | * transfer for an OUT endpoint has been completed, either by a short | |
1629 | * packet or by the finish of a transfer. | |
8b9bc460 | 1630 | */ |
1f91b4cc | 1631 | static void dwc2_hsotg_handle_outdone(struct dwc2_hsotg *hsotg, int epnum) |
5b7d70c6 | 1632 | { |
95c8bc36 | 1633 | u32 epsize = dwc2_readl(hsotg->regs + DOEPTSIZ(epnum)); |
1f91b4cc FB |
1634 | struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[epnum]; |
1635 | struct dwc2_hsotg_req *hs_req = hs_ep->req; | |
5b7d70c6 | 1636 | struct usb_request *req = &hs_req->req; |
47a1685f | 1637 | unsigned size_left = DXEPTSIZ_XFERSIZE_GET(epsize); |
5b7d70c6 BD |
1638 | int result = 0; |
1639 | ||
1640 | if (!hs_req) { | |
1641 | dev_dbg(hsotg->dev, "%s: no request active\n", __func__); | |
1642 | return; | |
1643 | } | |
1644 | ||
fe0b94ab MYK |
1645 | if (epnum == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_OUT) { |
1646 | dev_dbg(hsotg->dev, "zlp packet received\n"); | |
1f91b4cc FB |
1647 | dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0); |
1648 | dwc2_hsotg_enqueue_setup(hsotg); | |
fe0b94ab MYK |
1649 | return; |
1650 | } | |
1651 | ||
5b7d70c6 | 1652 | if (using_dma(hsotg)) { |
5b7d70c6 | 1653 | unsigned size_done; |
5b7d70c6 | 1654 | |
8b9bc460 LM |
1655 | /* |
1656 | * Calculate the size of the transfer by checking how much | |
5b7d70c6 BD |
1657 | * is left in the endpoint size register and then working it |
1658 | * out from the amount we loaded for the transfer. | |
1659 | * | |
1660 | * We need to do this as DMA pointers are always 32bit aligned | |
1661 | * so may overshoot/undershoot the transfer. | |
1662 | */ | |
1663 | ||
5b7d70c6 BD |
1664 | size_done = hs_ep->size_loaded - size_left; |
1665 | size_done += hs_ep->last_load; | |
1666 | ||
1667 | req->actual = size_done; | |
1668 | } | |
1669 | ||
a33e7136 BD |
1670 | /* if there is more request to do, schedule new transfer */ |
1671 | if (req->actual < req->length && size_left == 0) { | |
1f91b4cc | 1672 | dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true); |
a33e7136 BD |
1673 | return; |
1674 | } | |
1675 | ||
5b7d70c6 BD |
1676 | if (req->actual < req->length && req->short_not_ok) { |
1677 | dev_dbg(hsotg->dev, "%s: got %d/%d (short not ok) => error\n", | |
1678 | __func__, req->actual, req->length); | |
1679 | ||
8b9bc460 LM |
1680 | /* |
1681 | * todo - what should we return here? there's no one else | |
1682 | * even bothering to check the status. | |
1683 | */ | |
5b7d70c6 BD |
1684 | } |
1685 | ||
fe0b94ab MYK |
1686 | if (epnum == 0 && hsotg->ep0_state == DWC2_EP0_DATA_OUT) { |
1687 | /* Move to STATUS IN */ | |
1f91b4cc | 1688 | dwc2_hsotg_ep0_zlp(hsotg, true); |
fe0b94ab | 1689 | return; |
5b7d70c6 BD |
1690 | } |
1691 | ||
ec1f9d9f RB |
1692 | /* |
1693 | * Slave mode OUT transfers do not go through XferComplete so | |
1694 | * adjust the ISOC parity here. | |
1695 | */ | |
1696 | if (!using_dma(hsotg)) { | |
ec1f9d9f RB |
1697 | if (hs_ep->isochronous && hs_ep->interval == 1) |
1698 | dwc2_hsotg_change_ep_iso_parity(hsotg, DOEPCTL(epnum)); | |
837e9f00 VM |
1699 | else if (hs_ep->isochronous && hs_ep->interval > 1) |
1700 | dwc2_gadget_incr_frame_num(hs_ep); | |
ec1f9d9f RB |
1701 | } |
1702 | ||
1f91b4cc | 1703 | dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, result); |
5b7d70c6 BD |
1704 | } |
1705 | ||
5b7d70c6 | 1706 | /** |
1f91b4cc | 1707 | * dwc2_hsotg_handle_rx - RX FIFO has data |
5b7d70c6 BD |
1708 | * @hsotg: The device instance |
1709 | * | |
1710 | * The IRQ handler has detected that the RX FIFO has some data in it | |
1711 | * that requires processing, so find out what is in there and do the | |
1712 | * appropriate read. | |
1713 | * | |
25985edc | 1714 | * The RXFIFO is a true FIFO, the packets coming out are still in packet |
5b7d70c6 BD |
1715 | * chunks, so if you have x packets received on an endpoint you'll get x |
1716 | * FIFO events delivered, each with a packet's worth of data in it. | |
1717 | * | |
1718 | * When using DMA, we should not be processing events from the RXFIFO | |
1719 | * as the actual data should be sent to the memory directly and we turn | |
1720 | * on the completion interrupts to get notifications of transfer completion. | |
1721 | */ | |
1f91b4cc | 1722 | static void dwc2_hsotg_handle_rx(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 1723 | { |
95c8bc36 | 1724 | u32 grxstsr = dwc2_readl(hsotg->regs + GRXSTSP); |
5b7d70c6 BD |
1725 | u32 epnum, status, size; |
1726 | ||
1727 | WARN_ON(using_dma(hsotg)); | |
1728 | ||
47a1685f DN |
1729 | epnum = grxstsr & GRXSTS_EPNUM_MASK; |
1730 | status = grxstsr & GRXSTS_PKTSTS_MASK; | |
5b7d70c6 | 1731 | |
47a1685f DN |
1732 | size = grxstsr & GRXSTS_BYTECNT_MASK; |
1733 | size >>= GRXSTS_BYTECNT_SHIFT; | |
5b7d70c6 | 1734 | |
d7c747c5 | 1735 | dev_dbg(hsotg->dev, "%s: GRXSTSP=0x%08x (%d@%d)\n", |
5b7d70c6 BD |
1736 | __func__, grxstsr, size, epnum); |
1737 | ||
47a1685f DN |
1738 | switch ((status & GRXSTS_PKTSTS_MASK) >> GRXSTS_PKTSTS_SHIFT) { |
1739 | case GRXSTS_PKTSTS_GLOBALOUTNAK: | |
1740 | dev_dbg(hsotg->dev, "GLOBALOUTNAK\n"); | |
5b7d70c6 BD |
1741 | break; |
1742 | ||
47a1685f | 1743 | case GRXSTS_PKTSTS_OUTDONE: |
5b7d70c6 | 1744 | dev_dbg(hsotg->dev, "OutDone (Frame=0x%08x)\n", |
1f91b4cc | 1745 | dwc2_hsotg_read_frameno(hsotg)); |
5b7d70c6 BD |
1746 | |
1747 | if (!using_dma(hsotg)) | |
1f91b4cc | 1748 | dwc2_hsotg_handle_outdone(hsotg, epnum); |
5b7d70c6 BD |
1749 | break; |
1750 | ||
47a1685f | 1751 | case GRXSTS_PKTSTS_SETUPDONE: |
5b7d70c6 BD |
1752 | dev_dbg(hsotg->dev, |
1753 | "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n", | |
1f91b4cc | 1754 | dwc2_hsotg_read_frameno(hsotg), |
95c8bc36 | 1755 | dwc2_readl(hsotg->regs + DOEPCTL(0))); |
fe0b94ab | 1756 | /* |
1f91b4cc | 1757 | * Call dwc2_hsotg_handle_outdone here if it was not called from |
fe0b94ab MYK |
1758 | * GRXSTS_PKTSTS_OUTDONE. That is, if the core didn't |
1759 | * generate GRXSTS_PKTSTS_OUTDONE for setup packet. | |
1760 | */ | |
1761 | if (hsotg->ep0_state == DWC2_EP0_SETUP) | |
1f91b4cc | 1762 | dwc2_hsotg_handle_outdone(hsotg, epnum); |
5b7d70c6 BD |
1763 | break; |
1764 | ||
47a1685f | 1765 | case GRXSTS_PKTSTS_OUTRX: |
1f91b4cc | 1766 | dwc2_hsotg_rx_data(hsotg, epnum, size); |
5b7d70c6 BD |
1767 | break; |
1768 | ||
47a1685f | 1769 | case GRXSTS_PKTSTS_SETUPRX: |
5b7d70c6 BD |
1770 | dev_dbg(hsotg->dev, |
1771 | "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n", | |
1f91b4cc | 1772 | dwc2_hsotg_read_frameno(hsotg), |
95c8bc36 | 1773 | dwc2_readl(hsotg->regs + DOEPCTL(0))); |
5b7d70c6 | 1774 | |
fe0b94ab MYK |
1775 | WARN_ON(hsotg->ep0_state != DWC2_EP0_SETUP); |
1776 | ||
1f91b4cc | 1777 | dwc2_hsotg_rx_data(hsotg, epnum, size); |
5b7d70c6 BD |
1778 | break; |
1779 | ||
1780 | default: | |
1781 | dev_warn(hsotg->dev, "%s: unknown status %08x\n", | |
1782 | __func__, grxstsr); | |
1783 | ||
1f91b4cc | 1784 | dwc2_hsotg_dump(hsotg); |
5b7d70c6 BD |
1785 | break; |
1786 | } | |
1787 | } | |
1788 | ||
1789 | /** | |
1f91b4cc | 1790 | * dwc2_hsotg_ep0_mps - turn max packet size into register setting |
5b7d70c6 | 1791 | * @mps: The maximum packet size in bytes. |
8b9bc460 | 1792 | */ |
1f91b4cc | 1793 | static u32 dwc2_hsotg_ep0_mps(unsigned int mps) |
5b7d70c6 BD |
1794 | { |
1795 | switch (mps) { | |
1796 | case 64: | |
94cb8fd6 | 1797 | return D0EPCTL_MPS_64; |
5b7d70c6 | 1798 | case 32: |
94cb8fd6 | 1799 | return D0EPCTL_MPS_32; |
5b7d70c6 | 1800 | case 16: |
94cb8fd6 | 1801 | return D0EPCTL_MPS_16; |
5b7d70c6 | 1802 | case 8: |
94cb8fd6 | 1803 | return D0EPCTL_MPS_8; |
5b7d70c6 BD |
1804 | } |
1805 | ||
1806 | /* bad max packet size, warn and return invalid result */ | |
1807 | WARN_ON(1); | |
1808 | return (u32)-1; | |
1809 | } | |
1810 | ||
1811 | /** | |
1f91b4cc | 1812 | * dwc2_hsotg_set_ep_maxpacket - set endpoint's max-packet field |
5b7d70c6 BD |
1813 | * @hsotg: The driver state. |
1814 | * @ep: The index number of the endpoint | |
1815 | * @mps: The maximum packet size in bytes | |
1816 | * | |
1817 | * Configure the maximum packet size for the given endpoint, updating | |
1818 | * the hardware control registers to reflect this. | |
1819 | */ | |
1f91b4cc | 1820 | static void dwc2_hsotg_set_ep_maxpacket(struct dwc2_hsotg *hsotg, |
c6f5c050 | 1821 | unsigned int ep, unsigned int mps, unsigned int dir_in) |
5b7d70c6 | 1822 | { |
1f91b4cc | 1823 | struct dwc2_hsotg_ep *hs_ep; |
5b7d70c6 BD |
1824 | void __iomem *regs = hsotg->regs; |
1825 | u32 mpsval; | |
4fca54aa | 1826 | u32 mcval; |
5b7d70c6 BD |
1827 | u32 reg; |
1828 | ||
c6f5c050 MYK |
1829 | hs_ep = index_to_ep(hsotg, ep, dir_in); |
1830 | if (!hs_ep) | |
1831 | return; | |
1832 | ||
5b7d70c6 BD |
1833 | if (ep == 0) { |
1834 | /* EP0 is a special case */ | |
1f91b4cc | 1835 | mpsval = dwc2_hsotg_ep0_mps(mps); |
5b7d70c6 BD |
1836 | if (mpsval > 3) |
1837 | goto bad_mps; | |
e9edd199 | 1838 | hs_ep->ep.maxpacket = mps; |
4fca54aa | 1839 | hs_ep->mc = 1; |
5b7d70c6 | 1840 | } else { |
47a1685f | 1841 | mpsval = mps & DXEPCTL_MPS_MASK; |
e9edd199 | 1842 | if (mpsval > 1024) |
5b7d70c6 | 1843 | goto bad_mps; |
4fca54aa RB |
1844 | mcval = ((mps >> 11) & 0x3) + 1; |
1845 | hs_ep->mc = mcval; | |
1846 | if (mcval > 3) | |
1847 | goto bad_mps; | |
e9edd199 | 1848 | hs_ep->ep.maxpacket = mpsval; |
5b7d70c6 BD |
1849 | } |
1850 | ||
c6f5c050 | 1851 | if (dir_in) { |
95c8bc36 | 1852 | reg = dwc2_readl(regs + DIEPCTL(ep)); |
c6f5c050 MYK |
1853 | reg &= ~DXEPCTL_MPS_MASK; |
1854 | reg |= mpsval; | |
95c8bc36 | 1855 | dwc2_writel(reg, regs + DIEPCTL(ep)); |
c6f5c050 | 1856 | } else { |
95c8bc36 | 1857 | reg = dwc2_readl(regs + DOEPCTL(ep)); |
47a1685f | 1858 | reg &= ~DXEPCTL_MPS_MASK; |
659ad60c | 1859 | reg |= mpsval; |
95c8bc36 | 1860 | dwc2_writel(reg, regs + DOEPCTL(ep)); |
659ad60c | 1861 | } |
5b7d70c6 BD |
1862 | |
1863 | return; | |
1864 | ||
1865 | bad_mps: | |
1866 | dev_err(hsotg->dev, "ep%d: bad mps of %d\n", ep, mps); | |
1867 | } | |
1868 | ||
9c39ddc6 | 1869 | /** |
1f91b4cc | 1870 | * dwc2_hsotg_txfifo_flush - flush Tx FIFO |
9c39ddc6 AT |
1871 | * @hsotg: The driver state |
1872 | * @idx: The index for the endpoint (0..15) | |
1873 | */ | |
1f91b4cc | 1874 | static void dwc2_hsotg_txfifo_flush(struct dwc2_hsotg *hsotg, unsigned int idx) |
9c39ddc6 AT |
1875 | { |
1876 | int timeout; | |
1877 | int val; | |
1878 | ||
95c8bc36 AS |
1879 | dwc2_writel(GRSTCTL_TXFNUM(idx) | GRSTCTL_TXFFLSH, |
1880 | hsotg->regs + GRSTCTL); | |
9c39ddc6 AT |
1881 | |
1882 | /* wait until the fifo is flushed */ | |
1883 | timeout = 100; | |
1884 | ||
1885 | while (1) { | |
95c8bc36 | 1886 | val = dwc2_readl(hsotg->regs + GRSTCTL); |
9c39ddc6 | 1887 | |
47a1685f | 1888 | if ((val & (GRSTCTL_TXFFLSH)) == 0) |
9c39ddc6 AT |
1889 | break; |
1890 | ||
1891 | if (--timeout == 0) { | |
1892 | dev_err(hsotg->dev, | |
1893 | "%s: timeout flushing fifo (GRSTCTL=%08x)\n", | |
1894 | __func__, val); | |
e0cbe595 | 1895 | break; |
9c39ddc6 AT |
1896 | } |
1897 | ||
1898 | udelay(1); | |
1899 | } | |
1900 | } | |
5b7d70c6 BD |
1901 | |
1902 | /** | |
1f91b4cc | 1903 | * dwc2_hsotg_trytx - check to see if anything needs transmitting |
5b7d70c6 BD |
1904 | * @hsotg: The driver state |
1905 | * @hs_ep: The driver endpoint to check. | |
1906 | * | |
1907 | * Check to see if there is a request that has data to send, and if so | |
1908 | * make an attempt to write data into the FIFO. | |
1909 | */ | |
1f91b4cc FB |
1910 | static int dwc2_hsotg_trytx(struct dwc2_hsotg *hsotg, |
1911 | struct dwc2_hsotg_ep *hs_ep) | |
5b7d70c6 | 1912 | { |
1f91b4cc | 1913 | struct dwc2_hsotg_req *hs_req = hs_ep->req; |
5b7d70c6 | 1914 | |
afcf4169 RB |
1915 | if (!hs_ep->dir_in || !hs_req) { |
1916 | /** | |
1917 | * if request is not enqueued, we disable interrupts | |
1918 | * for endpoints, excepting ep0 | |
1919 | */ | |
1920 | if (hs_ep->index != 0) | |
1f91b4cc | 1921 | dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, |
afcf4169 | 1922 | hs_ep->dir_in, 0); |
5b7d70c6 | 1923 | return 0; |
afcf4169 | 1924 | } |
5b7d70c6 BD |
1925 | |
1926 | if (hs_req->req.actual < hs_req->req.length) { | |
1927 | dev_dbg(hsotg->dev, "trying to write more for ep%d\n", | |
1928 | hs_ep->index); | |
1f91b4cc | 1929 | return dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req); |
5b7d70c6 BD |
1930 | } |
1931 | ||
1932 | return 0; | |
1933 | } | |
1934 | ||
1935 | /** | |
1f91b4cc | 1936 | * dwc2_hsotg_complete_in - complete IN transfer |
5b7d70c6 BD |
1937 | * @hsotg: The device state. |
1938 | * @hs_ep: The endpoint that has just completed. | |
1939 | * | |
1940 | * An IN transfer has been completed, update the transfer's state and then | |
1941 | * call the relevant completion routines. | |
1942 | */ | |
1f91b4cc FB |
1943 | static void dwc2_hsotg_complete_in(struct dwc2_hsotg *hsotg, |
1944 | struct dwc2_hsotg_ep *hs_ep) | |
5b7d70c6 | 1945 | { |
1f91b4cc | 1946 | struct dwc2_hsotg_req *hs_req = hs_ep->req; |
95c8bc36 | 1947 | u32 epsize = dwc2_readl(hsotg->regs + DIEPTSIZ(hs_ep->index)); |
5b7d70c6 BD |
1948 | int size_left, size_done; |
1949 | ||
1950 | if (!hs_req) { | |
1951 | dev_dbg(hsotg->dev, "XferCompl but no req\n"); | |
1952 | return; | |
1953 | } | |
1954 | ||
d3ca0259 | 1955 | /* Finish ZLP handling for IN EP0 transactions */ |
fe0b94ab MYK |
1956 | if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_IN) { |
1957 | dev_dbg(hsotg->dev, "zlp packet sent\n"); | |
1f91b4cc | 1958 | dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0); |
9e14d0a5 GH |
1959 | if (hsotg->test_mode) { |
1960 | int ret; | |
1961 | ||
1f91b4cc | 1962 | ret = dwc2_hsotg_set_test_mode(hsotg, hsotg->test_mode); |
9e14d0a5 GH |
1963 | if (ret < 0) { |
1964 | dev_dbg(hsotg->dev, "Invalid Test #%d\n", | |
1965 | hsotg->test_mode); | |
1f91b4cc | 1966 | dwc2_hsotg_stall_ep0(hsotg); |
9e14d0a5 GH |
1967 | return; |
1968 | } | |
1969 | } | |
1f91b4cc | 1970 | dwc2_hsotg_enqueue_setup(hsotg); |
d3ca0259 LM |
1971 | return; |
1972 | } | |
1973 | ||
8b9bc460 LM |
1974 | /* |
1975 | * Calculate the size of the transfer by checking how much is left | |
5b7d70c6 BD |
1976 | * in the endpoint size register and then working it out from |
1977 | * the amount we loaded for the transfer. | |
1978 | * | |
1979 | * We do this even for DMA, as the transfer may have incremented | |
1980 | * past the end of the buffer (DMA transfers are always 32bit | |
1981 | * aligned). | |
1982 | */ | |
1983 | ||
47a1685f | 1984 | size_left = DXEPTSIZ_XFERSIZE_GET(epsize); |
5b7d70c6 BD |
1985 | |
1986 | size_done = hs_ep->size_loaded - size_left; | |
1987 | size_done += hs_ep->last_load; | |
1988 | ||
1989 | if (hs_req->req.actual != size_done) | |
1990 | dev_dbg(hsotg->dev, "%s: adjusting size done %d => %d\n", | |
1991 | __func__, hs_req->req.actual, size_done); | |
1992 | ||
1993 | hs_req->req.actual = size_done; | |
d3ca0259 LM |
1994 | dev_dbg(hsotg->dev, "req->length:%d req->actual:%d req->zero:%d\n", |
1995 | hs_req->req.length, hs_req->req.actual, hs_req->req.zero); | |
1996 | ||
5b7d70c6 BD |
1997 | if (!size_left && hs_req->req.actual < hs_req->req.length) { |
1998 | dev_dbg(hsotg->dev, "%s trying more for req...\n", __func__); | |
1f91b4cc | 1999 | dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true); |
fe0b94ab MYK |
2000 | return; |
2001 | } | |
2002 | ||
f71b5e25 | 2003 | /* Zlp for all endpoints, for ep0 only in DATA IN stage */ |
8a20fa45 | 2004 | if (hs_ep->send_zlp) { |
1f91b4cc | 2005 | dwc2_hsotg_program_zlp(hsotg, hs_ep); |
8a20fa45 | 2006 | hs_ep->send_zlp = 0; |
f71b5e25 MYK |
2007 | /* transfer will be completed on next complete interrupt */ |
2008 | return; | |
2009 | } | |
2010 | ||
fe0b94ab MYK |
2011 | if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_DATA_IN) { |
2012 | /* Move to STATUS OUT */ | |
1f91b4cc | 2013 | dwc2_hsotg_ep0_zlp(hsotg, false); |
fe0b94ab MYK |
2014 | return; |
2015 | } | |
2016 | ||
1f91b4cc | 2017 | dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0); |
5b7d70c6 BD |
2018 | } |
2019 | ||
32601588 VM |
2020 | /** |
2021 | * dwc2_gadget_read_ep_interrupts - reads interrupts for given ep | |
2022 | * @hsotg: The device state. | |
2023 | * @idx: Index of ep. | |
2024 | * @dir_in: Endpoint direction 1-in 0-out. | |
2025 | * | |
2026 | * Reads for endpoint with given index and direction, by masking | |
2027 | * epint_reg with coresponding mask. | |
2028 | */ | |
2029 | static u32 dwc2_gadget_read_ep_interrupts(struct dwc2_hsotg *hsotg, | |
2030 | unsigned int idx, int dir_in) | |
2031 | { | |
2032 | u32 epmsk_reg = dir_in ? DIEPMSK : DOEPMSK; | |
2033 | u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx); | |
2034 | u32 ints; | |
2035 | u32 mask; | |
2036 | u32 diepempmsk; | |
2037 | ||
2038 | mask = dwc2_readl(hsotg->regs + epmsk_reg); | |
2039 | diepempmsk = dwc2_readl(hsotg->regs + DIEPEMPMSK); | |
2040 | mask |= ((diepempmsk >> idx) & 0x1) ? DIEPMSK_TXFIFOEMPTY : 0; | |
2041 | mask |= DXEPINT_SETUP_RCVD; | |
2042 | ||
2043 | ints = dwc2_readl(hsotg->regs + epint_reg); | |
2044 | ints &= mask; | |
2045 | return ints; | |
2046 | } | |
2047 | ||
bd9971f0 VM |
2048 | /** |
2049 | * dwc2_gadget_handle_ep_disabled - handle DXEPINT_EPDISBLD | |
2050 | * @hs_ep: The endpoint on which interrupt is asserted. | |
2051 | * | |
2052 | * This interrupt indicates that the endpoint has been disabled per the | |
2053 | * application's request. | |
2054 | * | |
2055 | * For IN endpoints flushes txfifo, in case of BULK clears DCTL_CGNPINNAK, | |
2056 | * in case of ISOC completes current request. | |
2057 | * | |
2058 | * For ISOC-OUT endpoints completes expired requests. If there is remaining | |
2059 | * request starts it. | |
2060 | */ | |
2061 | static void dwc2_gadget_handle_ep_disabled(struct dwc2_hsotg_ep *hs_ep) | |
2062 | { | |
2063 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
2064 | struct dwc2_hsotg_req *hs_req; | |
2065 | unsigned char idx = hs_ep->index; | |
2066 | int dir_in = hs_ep->dir_in; | |
2067 | u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx); | |
2068 | int dctl = dwc2_readl(hsotg->regs + DCTL); | |
2069 | ||
2070 | dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__); | |
2071 | ||
2072 | if (dir_in) { | |
2073 | int epctl = dwc2_readl(hsotg->regs + epctl_reg); | |
2074 | ||
2075 | dwc2_hsotg_txfifo_flush(hsotg, hs_ep->fifo_index); | |
2076 | ||
2077 | if (hs_ep->isochronous) { | |
2078 | dwc2_hsotg_complete_in(hsotg, hs_ep); | |
2079 | return; | |
2080 | } | |
2081 | ||
2082 | if ((epctl & DXEPCTL_STALL) && (epctl & DXEPCTL_EPTYPE_BULK)) { | |
2083 | int dctl = dwc2_readl(hsotg->regs + DCTL); | |
2084 | ||
2085 | dctl |= DCTL_CGNPINNAK; | |
2086 | dwc2_writel(dctl, hsotg->regs + DCTL); | |
2087 | } | |
2088 | return; | |
2089 | } | |
2090 | ||
2091 | if (dctl & DCTL_GOUTNAKSTS) { | |
2092 | dctl |= DCTL_CGOUTNAK; | |
2093 | dwc2_writel(dctl, hsotg->regs + DCTL); | |
2094 | } | |
2095 | ||
2096 | if (!hs_ep->isochronous) | |
2097 | return; | |
2098 | ||
2099 | if (list_empty(&hs_ep->queue)) { | |
2100 | dev_dbg(hsotg->dev, "%s: complete_ep 0x%p, ep->queue empty!\n", | |
2101 | __func__, hs_ep); | |
2102 | return; | |
2103 | } | |
2104 | ||
2105 | do { | |
2106 | hs_req = get_ep_head(hs_ep); | |
2107 | if (hs_req) | |
2108 | dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, | |
2109 | -ENODATA); | |
2110 | dwc2_gadget_incr_frame_num(hs_ep); | |
2111 | } while (dwc2_gadget_target_frame_elapsed(hs_ep)); | |
2112 | ||
2113 | dwc2_gadget_start_next_request(hs_ep); | |
2114 | } | |
2115 | ||
5321922c VM |
2116 | /** |
2117 | * dwc2_gadget_handle_out_token_ep_disabled - handle DXEPINT_OUTTKNEPDIS | |
2118 | * @hs_ep: The endpoint on which interrupt is asserted. | |
2119 | * | |
2120 | * This is starting point for ISOC-OUT transfer, synchronization done with | |
2121 | * first out token received from host while corresponding EP is disabled. | |
2122 | * | |
2123 | * Device does not know initial frame in which out token will come. For this | |
2124 | * HW generates OUTTKNEPDIS - out token is received while EP is disabled. Upon | |
2125 | * getting this interrupt SW starts calculation for next transfer frame. | |
2126 | */ | |
2127 | static void dwc2_gadget_handle_out_token_ep_disabled(struct dwc2_hsotg_ep *ep) | |
2128 | { | |
2129 | struct dwc2_hsotg *hsotg = ep->parent; | |
2130 | int dir_in = ep->dir_in; | |
2131 | u32 doepmsk; | |
2132 | ||
2133 | if (dir_in || !ep->isochronous) | |
2134 | return; | |
2135 | ||
2136 | dwc2_hsotg_complete_request(hsotg, ep, get_ep_head(ep), -ENODATA); | |
2137 | ||
2138 | if (ep->interval > 1 && | |
2139 | ep->target_frame == TARGET_FRAME_INITIAL) { | |
2140 | u32 dsts; | |
2141 | u32 ctrl; | |
2142 | ||
2143 | dsts = dwc2_readl(hsotg->regs + DSTS); | |
2144 | ep->target_frame = dwc2_hsotg_read_frameno(hsotg); | |
2145 | dwc2_gadget_incr_frame_num(ep); | |
2146 | ||
2147 | ctrl = dwc2_readl(hsotg->regs + DOEPCTL(ep->index)); | |
2148 | if (ep->target_frame & 0x1) | |
2149 | ctrl |= DXEPCTL_SETODDFR; | |
2150 | else | |
2151 | ctrl |= DXEPCTL_SETEVENFR; | |
2152 | ||
2153 | dwc2_writel(ctrl, hsotg->regs + DOEPCTL(ep->index)); | |
2154 | } | |
2155 | ||
2156 | dwc2_gadget_start_next_request(ep); | |
2157 | doepmsk = dwc2_readl(hsotg->regs + DOEPMSK); | |
2158 | doepmsk &= ~DOEPMSK_OUTTKNEPDISMSK; | |
2159 | dwc2_writel(doepmsk, hsotg->regs + DOEPMSK); | |
2160 | } | |
2161 | ||
2162 | /** | |
2163 | * dwc2_gadget_handle_nak - handle NAK interrupt | |
2164 | * @hs_ep: The endpoint on which interrupt is asserted. | |
2165 | * | |
2166 | * This is starting point for ISOC-IN transfer, synchronization done with | |
2167 | * first IN token received from host while corresponding EP is disabled. | |
2168 | * | |
2169 | * Device does not know when first one token will arrive from host. On first | |
2170 | * token arrival HW generates 2 interrupts: 'in token received while FIFO empty' | |
2171 | * and 'NAK'. NAK interrupt for ISOC-IN means that token has arrived and ZLP was | |
2172 | * sent in response to that as there was no data in FIFO. SW is basing on this | |
2173 | * interrupt to obtain frame in which token has come and then based on the | |
2174 | * interval calculates next frame for transfer. | |
2175 | */ | |
2176 | static void dwc2_gadget_handle_nak(struct dwc2_hsotg_ep *hs_ep) | |
2177 | { | |
2178 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
2179 | int dir_in = hs_ep->dir_in; | |
2180 | ||
2181 | if (!dir_in || !hs_ep->isochronous) | |
2182 | return; | |
2183 | ||
2184 | if (hs_ep->target_frame == TARGET_FRAME_INITIAL) { | |
2185 | hs_ep->target_frame = dwc2_hsotg_read_frameno(hsotg); | |
2186 | if (hs_ep->interval > 1) { | |
2187 | u32 ctrl = dwc2_readl(hsotg->regs + | |
2188 | DIEPCTL(hs_ep->index)); | |
2189 | if (hs_ep->target_frame & 0x1) | |
2190 | ctrl |= DXEPCTL_SETODDFR; | |
2191 | else | |
2192 | ctrl |= DXEPCTL_SETEVENFR; | |
2193 | ||
2194 | dwc2_writel(ctrl, hsotg->regs + DIEPCTL(hs_ep->index)); | |
2195 | } | |
2196 | ||
2197 | dwc2_hsotg_complete_request(hsotg, hs_ep, | |
2198 | get_ep_head(hs_ep), 0); | |
2199 | } | |
2200 | ||
2201 | dwc2_gadget_incr_frame_num(hs_ep); | |
2202 | } | |
2203 | ||
5b7d70c6 | 2204 | /** |
1f91b4cc | 2205 | * dwc2_hsotg_epint - handle an in/out endpoint interrupt |
5b7d70c6 BD |
2206 | * @hsotg: The driver state |
2207 | * @idx: The index for the endpoint (0..15) | |
2208 | * @dir_in: Set if this is an IN endpoint | |
2209 | * | |
2210 | * Process and clear any interrupt pending for an individual endpoint | |
8b9bc460 | 2211 | */ |
1f91b4cc | 2212 | static void dwc2_hsotg_epint(struct dwc2_hsotg *hsotg, unsigned int idx, |
5b7d70c6 BD |
2213 | int dir_in) |
2214 | { | |
1f91b4cc | 2215 | struct dwc2_hsotg_ep *hs_ep = index_to_ep(hsotg, idx, dir_in); |
94cb8fd6 LM |
2216 | u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx); |
2217 | u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx); | |
2218 | u32 epsiz_reg = dir_in ? DIEPTSIZ(idx) : DOEPTSIZ(idx); | |
5b7d70c6 | 2219 | u32 ints; |
1479e841 | 2220 | u32 ctrl; |
5b7d70c6 | 2221 | |
32601588 | 2222 | ints = dwc2_gadget_read_ep_interrupts(hsotg, idx, dir_in); |
95c8bc36 | 2223 | ctrl = dwc2_readl(hsotg->regs + epctl_reg); |
5b7d70c6 | 2224 | |
a3395f0d | 2225 | /* Clear endpoint interrupts */ |
95c8bc36 | 2226 | dwc2_writel(ints, hsotg->regs + epint_reg); |
a3395f0d | 2227 | |
c6f5c050 MYK |
2228 | if (!hs_ep) { |
2229 | dev_err(hsotg->dev, "%s:Interrupt for unconfigured ep%d(%s)\n", | |
2230 | __func__, idx, dir_in ? "in" : "out"); | |
2231 | return; | |
2232 | } | |
2233 | ||
5b7d70c6 BD |
2234 | dev_dbg(hsotg->dev, "%s: ep%d(%s) DxEPINT=0x%08x\n", |
2235 | __func__, idx, dir_in ? "in" : "out", ints); | |
2236 | ||
b787d755 MYK |
2237 | /* Don't process XferCompl interrupt if it is a setup packet */ |
2238 | if (idx == 0 && (ints & (DXEPINT_SETUP | DXEPINT_SETUP_RCVD))) | |
2239 | ints &= ~DXEPINT_XFERCOMPL; | |
2240 | ||
837e9f00 VM |
2241 | if (ints & DXEPINT_STSPHSERCVD) |
2242 | dev_dbg(hsotg->dev, "%s: StsPhseRcvd asserted\n", __func__); | |
1479e841 | 2243 | |
837e9f00 | 2244 | if (ints & DXEPINT_XFERCOMPL) { |
5b7d70c6 | 2245 | dev_dbg(hsotg->dev, |
47a1685f | 2246 | "%s: XferCompl: DxEPCTL=0x%08x, DXEPTSIZ=%08x\n", |
95c8bc36 AS |
2247 | __func__, dwc2_readl(hsotg->regs + epctl_reg), |
2248 | dwc2_readl(hsotg->regs + epsiz_reg)); | |
5b7d70c6 | 2249 | |
8b9bc460 LM |
2250 | /* |
2251 | * we get OutDone from the FIFO, so we only need to look | |
2252 | * at completing IN requests here | |
2253 | */ | |
5b7d70c6 | 2254 | if (dir_in) { |
837e9f00 VM |
2255 | if (hs_ep->isochronous && hs_ep->interval > 1) |
2256 | dwc2_gadget_incr_frame_num(hs_ep); | |
2257 | ||
1f91b4cc | 2258 | dwc2_hsotg_complete_in(hsotg, hs_ep); |
837e9f00 VM |
2259 | if (ints & DXEPINT_NAKINTRPT) |
2260 | ints &= ~DXEPINT_NAKINTRPT; | |
5b7d70c6 | 2261 | |
c9a64ea8 | 2262 | if (idx == 0 && !hs_ep->req) |
1f91b4cc | 2263 | dwc2_hsotg_enqueue_setup(hsotg); |
5b7d70c6 | 2264 | } else if (using_dma(hsotg)) { |
8b9bc460 LM |
2265 | /* |
2266 | * We're using DMA, we need to fire an OutDone here | |
2267 | * as we ignore the RXFIFO. | |
2268 | */ | |
837e9f00 VM |
2269 | if (hs_ep->isochronous && hs_ep->interval > 1) |
2270 | dwc2_gadget_incr_frame_num(hs_ep); | |
5b7d70c6 | 2271 | |
1f91b4cc | 2272 | dwc2_hsotg_handle_outdone(hsotg, idx); |
5b7d70c6 | 2273 | } |
5b7d70c6 BD |
2274 | } |
2275 | ||
bd9971f0 VM |
2276 | if (ints & DXEPINT_EPDISBLD) |
2277 | dwc2_gadget_handle_ep_disabled(hs_ep); | |
9c39ddc6 | 2278 | |
5321922c VM |
2279 | if (ints & DXEPINT_OUTTKNEPDIS) |
2280 | dwc2_gadget_handle_out_token_ep_disabled(hs_ep); | |
2281 | ||
2282 | if (ints & DXEPINT_NAKINTRPT) | |
2283 | dwc2_gadget_handle_nak(hs_ep); | |
2284 | ||
47a1685f | 2285 | if (ints & DXEPINT_AHBERR) |
5b7d70c6 | 2286 | dev_dbg(hsotg->dev, "%s: AHBErr\n", __func__); |
5b7d70c6 | 2287 | |
47a1685f | 2288 | if (ints & DXEPINT_SETUP) { /* Setup or Timeout */ |
5b7d70c6 BD |
2289 | dev_dbg(hsotg->dev, "%s: Setup/Timeout\n", __func__); |
2290 | ||
2291 | if (using_dma(hsotg) && idx == 0) { | |
8b9bc460 LM |
2292 | /* |
2293 | * this is the notification we've received a | |
5b7d70c6 BD |
2294 | * setup packet. In non-DMA mode we'd get this |
2295 | * from the RXFIFO, instead we need to process | |
8b9bc460 LM |
2296 | * the setup here. |
2297 | */ | |
5b7d70c6 BD |
2298 | |
2299 | if (dir_in) | |
2300 | WARN_ON_ONCE(1); | |
2301 | else | |
1f91b4cc | 2302 | dwc2_hsotg_handle_outdone(hsotg, 0); |
5b7d70c6 | 2303 | } |
5b7d70c6 BD |
2304 | } |
2305 | ||
47a1685f | 2306 | if (ints & DXEPINT_BACK2BACKSETUP) |
5b7d70c6 | 2307 | dev_dbg(hsotg->dev, "%s: B2BSetup/INEPNakEff\n", __func__); |
5b7d70c6 | 2308 | |
1479e841 | 2309 | if (dir_in && !hs_ep->isochronous) { |
8b9bc460 | 2310 | /* not sure if this is important, but we'll clear it anyway */ |
26ddef5d | 2311 | if (ints & DXEPINT_INTKNTXFEMP) { |
5b7d70c6 BD |
2312 | dev_dbg(hsotg->dev, "%s: ep%d: INTknTXFEmpMsk\n", |
2313 | __func__, idx); | |
5b7d70c6 BD |
2314 | } |
2315 | ||
2316 | /* this probably means something bad is happening */ | |
26ddef5d | 2317 | if (ints & DXEPINT_INTKNEPMIS) { |
5b7d70c6 BD |
2318 | dev_warn(hsotg->dev, "%s: ep%d: INTknEP\n", |
2319 | __func__, idx); | |
5b7d70c6 | 2320 | } |
10aebc77 BD |
2321 | |
2322 | /* FIFO has space or is empty (see GAHBCFG) */ | |
2323 | if (hsotg->dedicated_fifos && | |
26ddef5d | 2324 | ints & DXEPINT_TXFEMP) { |
10aebc77 BD |
2325 | dev_dbg(hsotg->dev, "%s: ep%d: TxFIFOEmpty\n", |
2326 | __func__, idx); | |
70fa030f | 2327 | if (!using_dma(hsotg)) |
1f91b4cc | 2328 | dwc2_hsotg_trytx(hsotg, hs_ep); |
10aebc77 | 2329 | } |
5b7d70c6 | 2330 | } |
5b7d70c6 BD |
2331 | } |
2332 | ||
2333 | /** | |
1f91b4cc | 2334 | * dwc2_hsotg_irq_enumdone - Handle EnumDone interrupt (enumeration done) |
5b7d70c6 BD |
2335 | * @hsotg: The device state. |
2336 | * | |
2337 | * Handle updating the device settings after the enumeration phase has | |
2338 | * been completed. | |
8b9bc460 | 2339 | */ |
1f91b4cc | 2340 | static void dwc2_hsotg_irq_enumdone(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 2341 | { |
95c8bc36 | 2342 | u32 dsts = dwc2_readl(hsotg->regs + DSTS); |
9b2667f1 | 2343 | int ep0_mps = 0, ep_mps = 8; |
5b7d70c6 | 2344 | |
8b9bc460 LM |
2345 | /* |
2346 | * This should signal the finish of the enumeration phase | |
5b7d70c6 | 2347 | * of the USB handshaking, so we should now know what rate |
8b9bc460 LM |
2348 | * we connected at. |
2349 | */ | |
5b7d70c6 BD |
2350 | |
2351 | dev_dbg(hsotg->dev, "EnumDone (DSTS=0x%08x)\n", dsts); | |
2352 | ||
8b9bc460 LM |
2353 | /* |
2354 | * note, since we're limited by the size of transfer on EP0, and | |
5b7d70c6 | 2355 | * it seems IN transfers must be a even number of packets we do |
8b9bc460 LM |
2356 | * not advertise a 64byte MPS on EP0. |
2357 | */ | |
5b7d70c6 BD |
2358 | |
2359 | /* catch both EnumSpd_FS and EnumSpd_FS48 */ | |
6d76c92c | 2360 | switch ((dsts & DSTS_ENUMSPD_MASK) >> DSTS_ENUMSPD_SHIFT) { |
47a1685f DN |
2361 | case DSTS_ENUMSPD_FS: |
2362 | case DSTS_ENUMSPD_FS48: | |
5b7d70c6 | 2363 | hsotg->gadget.speed = USB_SPEED_FULL; |
5b7d70c6 | 2364 | ep0_mps = EP0_MPS_LIMIT; |
295538ff | 2365 | ep_mps = 1023; |
5b7d70c6 BD |
2366 | break; |
2367 | ||
47a1685f | 2368 | case DSTS_ENUMSPD_HS: |
5b7d70c6 | 2369 | hsotg->gadget.speed = USB_SPEED_HIGH; |
5b7d70c6 | 2370 | ep0_mps = EP0_MPS_LIMIT; |
295538ff | 2371 | ep_mps = 1024; |
5b7d70c6 BD |
2372 | break; |
2373 | ||
47a1685f | 2374 | case DSTS_ENUMSPD_LS: |
5b7d70c6 | 2375 | hsotg->gadget.speed = USB_SPEED_LOW; |
8b9bc460 LM |
2376 | /* |
2377 | * note, we don't actually support LS in this driver at the | |
5b7d70c6 BD |
2378 | * moment, and the documentation seems to imply that it isn't |
2379 | * supported by the PHYs on some of the devices. | |
2380 | */ | |
2381 | break; | |
2382 | } | |
e538dfda MN |
2383 | dev_info(hsotg->dev, "new device is %s\n", |
2384 | usb_speed_string(hsotg->gadget.speed)); | |
5b7d70c6 | 2385 | |
8b9bc460 LM |
2386 | /* |
2387 | * we should now know the maximum packet size for an | |
2388 | * endpoint, so set the endpoints to a default value. | |
2389 | */ | |
5b7d70c6 BD |
2390 | |
2391 | if (ep0_mps) { | |
2392 | int i; | |
c6f5c050 | 2393 | /* Initialize ep0 for both in and out directions */ |
1f91b4cc FB |
2394 | dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 1); |
2395 | dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 0); | |
c6f5c050 MYK |
2396 | for (i = 1; i < hsotg->num_of_eps; i++) { |
2397 | if (hsotg->eps_in[i]) | |
1f91b4cc | 2398 | dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps, 1); |
c6f5c050 | 2399 | if (hsotg->eps_out[i]) |
1f91b4cc | 2400 | dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps, 0); |
c6f5c050 | 2401 | } |
5b7d70c6 BD |
2402 | } |
2403 | ||
2404 | /* ensure after enumeration our EP0 is active */ | |
2405 | ||
1f91b4cc | 2406 | dwc2_hsotg_enqueue_setup(hsotg); |
5b7d70c6 BD |
2407 | |
2408 | dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n", | |
95c8bc36 AS |
2409 | dwc2_readl(hsotg->regs + DIEPCTL0), |
2410 | dwc2_readl(hsotg->regs + DOEPCTL0)); | |
5b7d70c6 BD |
2411 | } |
2412 | ||
2413 | /** | |
2414 | * kill_all_requests - remove all requests from the endpoint's queue | |
2415 | * @hsotg: The device state. | |
2416 | * @ep: The endpoint the requests may be on. | |
2417 | * @result: The result code to use. | |
5b7d70c6 BD |
2418 | * |
2419 | * Go through the requests on the given endpoint and mark them | |
2420 | * completed with the given result code. | |
2421 | */ | |
941fcce4 | 2422 | static void kill_all_requests(struct dwc2_hsotg *hsotg, |
1f91b4cc | 2423 | struct dwc2_hsotg_ep *ep, |
6b448af4 | 2424 | int result) |
5b7d70c6 | 2425 | { |
1f91b4cc | 2426 | struct dwc2_hsotg_req *req, *treq; |
b203d0a2 | 2427 | unsigned size; |
5b7d70c6 | 2428 | |
6b448af4 | 2429 | ep->req = NULL; |
5b7d70c6 | 2430 | |
6b448af4 | 2431 | list_for_each_entry_safe(req, treq, &ep->queue, queue) |
1f91b4cc | 2432 | dwc2_hsotg_complete_request(hsotg, ep, req, |
5b7d70c6 | 2433 | result); |
6b448af4 | 2434 | |
b203d0a2 RB |
2435 | if (!hsotg->dedicated_fifos) |
2436 | return; | |
ad674a15 | 2437 | size = (dwc2_readl(hsotg->regs + DTXFSTS(ep->fifo_index)) & 0xffff) * 4; |
b203d0a2 | 2438 | if (size < ep->fifo_size) |
1f91b4cc | 2439 | dwc2_hsotg_txfifo_flush(hsotg, ep->fifo_index); |
5b7d70c6 BD |
2440 | } |
2441 | ||
5b7d70c6 | 2442 | /** |
1f91b4cc | 2443 | * dwc2_hsotg_disconnect - disconnect service |
5b7d70c6 BD |
2444 | * @hsotg: The device state. |
2445 | * | |
5e891342 LM |
2446 | * The device has been disconnected. Remove all current |
2447 | * transactions and signal the gadget driver that this | |
2448 | * has happened. | |
8b9bc460 | 2449 | */ |
1f91b4cc | 2450 | void dwc2_hsotg_disconnect(struct dwc2_hsotg *hsotg) |
5b7d70c6 BD |
2451 | { |
2452 | unsigned ep; | |
2453 | ||
4ace06e8 MS |
2454 | if (!hsotg->connected) |
2455 | return; | |
2456 | ||
2457 | hsotg->connected = 0; | |
9e14d0a5 | 2458 | hsotg->test_mode = 0; |
c6f5c050 MYK |
2459 | |
2460 | for (ep = 0; ep < hsotg->num_of_eps; ep++) { | |
2461 | if (hsotg->eps_in[ep]) | |
2462 | kill_all_requests(hsotg, hsotg->eps_in[ep], | |
2463 | -ESHUTDOWN); | |
2464 | if (hsotg->eps_out[ep]) | |
2465 | kill_all_requests(hsotg, hsotg->eps_out[ep], | |
2466 | -ESHUTDOWN); | |
2467 | } | |
5b7d70c6 BD |
2468 | |
2469 | call_gadget(hsotg, disconnect); | |
065d3931 | 2470 | hsotg->lx_state = DWC2_L3; |
5b7d70c6 BD |
2471 | } |
2472 | ||
2473 | /** | |
1f91b4cc | 2474 | * dwc2_hsotg_irq_fifoempty - TX FIFO empty interrupt handler |
5b7d70c6 BD |
2475 | * @hsotg: The device state: |
2476 | * @periodic: True if this is a periodic FIFO interrupt | |
2477 | */ | |
1f91b4cc | 2478 | static void dwc2_hsotg_irq_fifoempty(struct dwc2_hsotg *hsotg, bool periodic) |
5b7d70c6 | 2479 | { |
1f91b4cc | 2480 | struct dwc2_hsotg_ep *ep; |
5b7d70c6 BD |
2481 | int epno, ret; |
2482 | ||
2483 | /* look through for any more data to transmit */ | |
b3f489b2 | 2484 | for (epno = 0; epno < hsotg->num_of_eps; epno++) { |
c6f5c050 MYK |
2485 | ep = index_to_ep(hsotg, epno, 1); |
2486 | ||
2487 | if (!ep) | |
2488 | continue; | |
5b7d70c6 BD |
2489 | |
2490 | if (!ep->dir_in) | |
2491 | continue; | |
2492 | ||
2493 | if ((periodic && !ep->periodic) || | |
2494 | (!periodic && ep->periodic)) | |
2495 | continue; | |
2496 | ||
1f91b4cc | 2497 | ret = dwc2_hsotg_trytx(hsotg, ep); |
5b7d70c6 BD |
2498 | if (ret < 0) |
2499 | break; | |
2500 | } | |
2501 | } | |
2502 | ||
5b7d70c6 | 2503 | /* IRQ flags which will trigger a retry around the IRQ loop */ |
47a1685f DN |
2504 | #define IRQ_RETRY_MASK (GINTSTS_NPTXFEMP | \ |
2505 | GINTSTS_PTXFEMP | \ | |
2506 | GINTSTS_RXFLVL) | |
5b7d70c6 | 2507 | |
8b9bc460 | 2508 | /** |
1f91b4cc | 2509 | * dwc2_hsotg_core_init - issue softreset to the core |
8b9bc460 LM |
2510 | * @hsotg: The device state |
2511 | * | |
2512 | * Issue a soft reset to the core, and await the core finishing it. | |
2513 | */ | |
1f91b4cc | 2514 | void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg, |
643cc4de | 2515 | bool is_usb_reset) |
308d734e | 2516 | { |
1ee6903b | 2517 | u32 intmsk; |
643cc4de | 2518 | u32 val; |
ecd9a7ad | 2519 | u32 usbcfg; |
643cc4de | 2520 | |
5390d438 MYK |
2521 | /* Kill any ep0 requests as controller will be reinitialized */ |
2522 | kill_all_requests(hsotg, hsotg->eps_out[0], -ECONNRESET); | |
2523 | ||
643cc4de | 2524 | if (!is_usb_reset) |
241729ba | 2525 | if (dwc2_core_reset(hsotg)) |
86de4895 | 2526 | return; |
308d734e LM |
2527 | |
2528 | /* | |
2529 | * we must now enable ep0 ready for host detection and then | |
2530 | * set configuration. | |
2531 | */ | |
2532 | ||
ecd9a7ad PR |
2533 | /* keep other bits untouched (so e.g. forced modes are not lost) */ |
2534 | usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); | |
2535 | usbcfg &= ~(GUSBCFG_TOUTCAL_MASK | GUSBCFG_PHYIF16 | GUSBCFG_SRPCAP | | |
2536 | GUSBCFG_HNPCAP); | |
2537 | ||
308d734e | 2538 | /* set the PLL on, remove the HNP/SRP and set the PHY */ |
fa4a8d72 | 2539 | val = (hsotg->phyif == GUSBCFG_PHYIF8) ? 9 : 5; |
ecd9a7ad PR |
2540 | usbcfg |= hsotg->phyif | GUSBCFG_TOUTCAL(7) | |
2541 | (val << GUSBCFG_USBTRDTIM_SHIFT); | |
2542 | dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); | |
308d734e | 2543 | |
1f91b4cc | 2544 | dwc2_hsotg_init_fifo(hsotg); |
308d734e | 2545 | |
643cc4de GH |
2546 | if (!is_usb_reset) |
2547 | __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON); | |
308d734e | 2548 | |
95c8bc36 | 2549 | dwc2_writel(DCFG_EPMISCNT(1) | DCFG_DEVSPD_HS, hsotg->regs + DCFG); |
308d734e LM |
2550 | |
2551 | /* Clear any pending OTG interrupts */ | |
95c8bc36 | 2552 | dwc2_writel(0xffffffff, hsotg->regs + GOTGINT); |
308d734e LM |
2553 | |
2554 | /* Clear any pending interrupts */ | |
95c8bc36 | 2555 | dwc2_writel(0xffffffff, hsotg->regs + GINTSTS); |
1ee6903b | 2556 | intmsk = GINTSTS_ERLYSUSP | GINTSTS_SESSREQINT | |
47a1685f | 2557 | GINTSTS_GOUTNAKEFF | GINTSTS_GINNAKEFF | |
1ee6903b GH |
2558 | GINTSTS_USBRST | GINTSTS_RESETDET | |
2559 | GINTSTS_ENUMDONE | GINTSTS_OTGINT | | |
ec1f9d9f RB |
2560 | GINTSTS_USBSUSP | GINTSTS_WKUPINT | |
2561 | GINTSTS_INCOMPL_SOIN | GINTSTS_INCOMPL_SOOUT; | |
1ee6903b GH |
2562 | |
2563 | if (hsotg->core_params->external_id_pin_ctl <= 0) | |
2564 | intmsk |= GINTSTS_CONIDSTSCHNG; | |
2565 | ||
2566 | dwc2_writel(intmsk, hsotg->regs + GINTMSK); | |
308d734e LM |
2567 | |
2568 | if (using_dma(hsotg)) | |
95c8bc36 AS |
2569 | dwc2_writel(GAHBCFG_GLBL_INTR_EN | GAHBCFG_DMA_EN | |
2570 | (GAHBCFG_HBSTLEN_INCR4 << GAHBCFG_HBSTLEN_SHIFT), | |
2571 | hsotg->regs + GAHBCFG); | |
308d734e | 2572 | else |
95c8bc36 AS |
2573 | dwc2_writel(((hsotg->dedicated_fifos) ? |
2574 | (GAHBCFG_NP_TXF_EMP_LVL | | |
2575 | GAHBCFG_P_TXF_EMP_LVL) : 0) | | |
2576 | GAHBCFG_GLBL_INTR_EN, hsotg->regs + GAHBCFG); | |
308d734e LM |
2577 | |
2578 | /* | |
8acc8296 RB |
2579 | * If INTknTXFEmpMsk is enabled, it's important to disable ep interrupts |
2580 | * when we have no data to transfer. Otherwise we get being flooded by | |
2581 | * interrupts. | |
308d734e LM |
2582 | */ |
2583 | ||
95c8bc36 | 2584 | dwc2_writel(((hsotg->dedicated_fifos && !using_dma(hsotg)) ? |
6ff2e832 | 2585 | DIEPMSK_TXFIFOEMPTY | DIEPMSK_INTKNTXFEMPMSK : 0) | |
47a1685f | 2586 | DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK | |
837e9f00 | 2587 | DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK, |
47a1685f | 2588 | hsotg->regs + DIEPMSK); |
308d734e LM |
2589 | |
2590 | /* | |
2591 | * don't need XferCompl, we get that from RXFIFO in slave mode. In | |
2592 | * DMA mode we may need this. | |
2593 | */ | |
837e9f00 | 2594 | dwc2_writel((using_dma(hsotg) ? (DIEPMSK_XFERCOMPLMSK) : 0) | |
47a1685f | 2595 | DOEPMSK_EPDISBLDMSK | DOEPMSK_AHBERRMSK | |
837e9f00 | 2596 | DOEPMSK_SETUPMSK | DOEPMSK_STSPHSERCVDMSK, |
47a1685f | 2597 | hsotg->regs + DOEPMSK); |
308d734e | 2598 | |
95c8bc36 | 2599 | dwc2_writel(0, hsotg->regs + DAINTMSK); |
308d734e LM |
2600 | |
2601 | dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n", | |
95c8bc36 AS |
2602 | dwc2_readl(hsotg->regs + DIEPCTL0), |
2603 | dwc2_readl(hsotg->regs + DOEPCTL0)); | |
308d734e LM |
2604 | |
2605 | /* enable in and out endpoint interrupts */ | |
1f91b4cc | 2606 | dwc2_hsotg_en_gsint(hsotg, GINTSTS_OEPINT | GINTSTS_IEPINT); |
308d734e LM |
2607 | |
2608 | /* | |
2609 | * Enable the RXFIFO when in slave mode, as this is how we collect | |
2610 | * the data. In DMA mode, we get events from the FIFO but also | |
2611 | * things we cannot process, so do not use it. | |
2612 | */ | |
2613 | if (!using_dma(hsotg)) | |
1f91b4cc | 2614 | dwc2_hsotg_en_gsint(hsotg, GINTSTS_RXFLVL); |
308d734e LM |
2615 | |
2616 | /* Enable interrupts for EP0 in and out */ | |
1f91b4cc FB |
2617 | dwc2_hsotg_ctrl_epint(hsotg, 0, 0, 1); |
2618 | dwc2_hsotg_ctrl_epint(hsotg, 0, 1, 1); | |
308d734e | 2619 | |
643cc4de GH |
2620 | if (!is_usb_reset) { |
2621 | __orr32(hsotg->regs + DCTL, DCTL_PWRONPRGDONE); | |
2622 | udelay(10); /* see openiboot */ | |
2623 | __bic32(hsotg->regs + DCTL, DCTL_PWRONPRGDONE); | |
2624 | } | |
308d734e | 2625 | |
95c8bc36 | 2626 | dev_dbg(hsotg->dev, "DCTL=0x%08x\n", dwc2_readl(hsotg->regs + DCTL)); |
308d734e LM |
2627 | |
2628 | /* | |
94cb8fd6 | 2629 | * DxEPCTL_USBActEp says RO in manual, but seems to be set by |
308d734e LM |
2630 | * writing to the EPCTL register.. |
2631 | */ | |
2632 | ||
2633 | /* set to read 1 8byte packet */ | |
95c8bc36 | 2634 | dwc2_writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) | |
47a1685f | 2635 | DXEPTSIZ_XFERSIZE(8), hsotg->regs + DOEPTSIZ0); |
308d734e | 2636 | |
95c8bc36 | 2637 | dwc2_writel(dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) | |
47a1685f DN |
2638 | DXEPCTL_CNAK | DXEPCTL_EPENA | |
2639 | DXEPCTL_USBACTEP, | |
94cb8fd6 | 2640 | hsotg->regs + DOEPCTL0); |
308d734e LM |
2641 | |
2642 | /* enable, but don't activate EP0in */ | |
95c8bc36 | 2643 | dwc2_writel(dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) | |
47a1685f | 2644 | DXEPCTL_USBACTEP, hsotg->regs + DIEPCTL0); |
308d734e | 2645 | |
1f91b4cc | 2646 | dwc2_hsotg_enqueue_setup(hsotg); |
308d734e LM |
2647 | |
2648 | dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n", | |
95c8bc36 AS |
2649 | dwc2_readl(hsotg->regs + DIEPCTL0), |
2650 | dwc2_readl(hsotg->regs + DOEPCTL0)); | |
308d734e LM |
2651 | |
2652 | /* clear global NAKs */ | |
643cc4de GH |
2653 | val = DCTL_CGOUTNAK | DCTL_CGNPINNAK; |
2654 | if (!is_usb_reset) | |
2655 | val |= DCTL_SFTDISCON; | |
2656 | __orr32(hsotg->regs + DCTL, val); | |
308d734e LM |
2657 | |
2658 | /* must be at-least 3ms to allow bus to see disconnect */ | |
2659 | mdelay(3); | |
2660 | ||
065d3931 | 2661 | hsotg->lx_state = DWC2_L0; |
ad38dc5d MS |
2662 | } |
2663 | ||
1f91b4cc | 2664 | static void dwc2_hsotg_core_disconnect(struct dwc2_hsotg *hsotg) |
ad38dc5d MS |
2665 | { |
2666 | /* set the soft-disconnect bit */ | |
2667 | __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON); | |
2668 | } | |
ac3c81f3 | 2669 | |
1f91b4cc | 2670 | void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg) |
ad38dc5d | 2671 | { |
308d734e | 2672 | /* remove the soft-disconnect and let's go */ |
47a1685f | 2673 | __bic32(hsotg->regs + DCTL, DCTL_SFTDISCON); |
308d734e LM |
2674 | } |
2675 | ||
381fc8f8 VM |
2676 | /** |
2677 | * dwc2_gadget_handle_incomplete_isoc_in - handle incomplete ISO IN Interrupt. | |
2678 | * @hsotg: The device state: | |
2679 | * | |
2680 | * This interrupt indicates one of the following conditions occurred while | |
2681 | * transmitting an ISOC transaction. | |
2682 | * - Corrupted IN Token for ISOC EP. | |
2683 | * - Packet not complete in FIFO. | |
2684 | * | |
2685 | * The following actions will be taken: | |
2686 | * - Determine the EP | |
2687 | * - Disable EP; when 'Endpoint Disabled' interrupt is received Flush FIFO | |
2688 | */ | |
2689 | static void dwc2_gadget_handle_incomplete_isoc_in(struct dwc2_hsotg *hsotg) | |
2690 | { | |
2691 | struct dwc2_hsotg_ep *hs_ep; | |
2692 | u32 epctrl; | |
2693 | u32 idx; | |
2694 | ||
2695 | dev_dbg(hsotg->dev, "Incomplete isoc in interrupt received:\n"); | |
2696 | ||
2697 | for (idx = 1; idx <= hsotg->num_of_eps; idx++) { | |
2698 | hs_ep = hsotg->eps_in[idx]; | |
2699 | epctrl = dwc2_readl(hsotg->regs + DIEPCTL(idx)); | |
2700 | if ((epctrl & DXEPCTL_EPENA) && hs_ep->isochronous && | |
2701 | dwc2_gadget_target_frame_elapsed(hs_ep)) { | |
2702 | epctrl |= DXEPCTL_SNAK; | |
2703 | epctrl |= DXEPCTL_EPDIS; | |
2704 | dwc2_writel(epctrl, hsotg->regs + DIEPCTL(idx)); | |
2705 | } | |
2706 | } | |
2707 | ||
2708 | /* Clear interrupt */ | |
2709 | dwc2_writel(GINTSTS_INCOMPL_SOIN, hsotg->regs + GINTSTS); | |
2710 | } | |
2711 | ||
2712 | /** | |
2713 | * dwc2_gadget_handle_incomplete_isoc_out - handle incomplete ISO OUT Interrupt | |
2714 | * @hsotg: The device state: | |
2715 | * | |
2716 | * This interrupt indicates one of the following conditions occurred while | |
2717 | * transmitting an ISOC transaction. | |
2718 | * - Corrupted OUT Token for ISOC EP. | |
2719 | * - Packet not complete in FIFO. | |
2720 | * | |
2721 | * The following actions will be taken: | |
2722 | * - Determine the EP | |
2723 | * - Set DCTL_SGOUTNAK and unmask GOUTNAKEFF if target frame elapsed. | |
2724 | */ | |
2725 | static void dwc2_gadget_handle_incomplete_isoc_out(struct dwc2_hsotg *hsotg) | |
2726 | { | |
2727 | u32 gintsts; | |
2728 | u32 gintmsk; | |
2729 | u32 epctrl; | |
2730 | struct dwc2_hsotg_ep *hs_ep; | |
2731 | int idx; | |
2732 | ||
2733 | dev_dbg(hsotg->dev, "%s: GINTSTS_INCOMPL_SOOUT\n", __func__); | |
2734 | ||
2735 | for (idx = 1; idx <= hsotg->num_of_eps; idx++) { | |
2736 | hs_ep = hsotg->eps_out[idx]; | |
2737 | epctrl = dwc2_readl(hsotg->regs + DOEPCTL(idx)); | |
2738 | if ((epctrl & DXEPCTL_EPENA) && hs_ep->isochronous && | |
2739 | dwc2_gadget_target_frame_elapsed(hs_ep)) { | |
2740 | /* Unmask GOUTNAKEFF interrupt */ | |
2741 | gintmsk = dwc2_readl(hsotg->regs + GINTMSK); | |
2742 | gintmsk |= GINTSTS_GOUTNAKEFF; | |
2743 | dwc2_writel(gintmsk, hsotg->regs + GINTMSK); | |
2744 | ||
2745 | gintsts = dwc2_readl(hsotg->regs + GINTSTS); | |
2746 | if (!(gintsts & GINTSTS_GOUTNAKEFF)) | |
2747 | __orr32(hsotg->regs + DCTL, DCTL_SGOUTNAK); | |
2748 | } | |
2749 | } | |
2750 | ||
2751 | /* Clear interrupt */ | |
2752 | dwc2_writel(GINTSTS_INCOMPL_SOOUT, hsotg->regs + GINTSTS); | |
2753 | } | |
2754 | ||
5b7d70c6 | 2755 | /** |
1f91b4cc | 2756 | * dwc2_hsotg_irq - handle device interrupt |
5b7d70c6 BD |
2757 | * @irq: The IRQ number triggered |
2758 | * @pw: The pw value when registered the handler. | |
2759 | */ | |
1f91b4cc | 2760 | static irqreturn_t dwc2_hsotg_irq(int irq, void *pw) |
5b7d70c6 | 2761 | { |
941fcce4 | 2762 | struct dwc2_hsotg *hsotg = pw; |
5b7d70c6 BD |
2763 | int retry_count = 8; |
2764 | u32 gintsts; | |
2765 | u32 gintmsk; | |
2766 | ||
ee3de8d7 VM |
2767 | if (!dwc2_is_device_mode(hsotg)) |
2768 | return IRQ_NONE; | |
2769 | ||
5ad1d316 | 2770 | spin_lock(&hsotg->lock); |
5b7d70c6 | 2771 | irq_retry: |
95c8bc36 AS |
2772 | gintsts = dwc2_readl(hsotg->regs + GINTSTS); |
2773 | gintmsk = dwc2_readl(hsotg->regs + GINTMSK); | |
5b7d70c6 BD |
2774 | |
2775 | dev_dbg(hsotg->dev, "%s: %08x %08x (%08x) retry %d\n", | |
2776 | __func__, gintsts, gintsts & gintmsk, gintmsk, retry_count); | |
2777 | ||
2778 | gintsts &= gintmsk; | |
2779 | ||
8fc37b82 MYK |
2780 | if (gintsts & GINTSTS_RESETDET) { |
2781 | dev_dbg(hsotg->dev, "%s: USBRstDet\n", __func__); | |
2782 | ||
2783 | dwc2_writel(GINTSTS_RESETDET, hsotg->regs + GINTSTS); | |
2784 | ||
2785 | /* This event must be used only if controller is suspended */ | |
2786 | if (hsotg->lx_state == DWC2_L2) { | |
2787 | dwc2_exit_hibernation(hsotg, true); | |
2788 | hsotg->lx_state = DWC2_L0; | |
2789 | } | |
2790 | } | |
2791 | ||
2792 | if (gintsts & (GINTSTS_USBRST | GINTSTS_RESETDET)) { | |
2793 | ||
2794 | u32 usb_status = dwc2_readl(hsotg->regs + GOTGCTL); | |
2795 | u32 connected = hsotg->connected; | |
2796 | ||
2797 | dev_dbg(hsotg->dev, "%s: USBRst\n", __func__); | |
2798 | dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n", | |
2799 | dwc2_readl(hsotg->regs + GNPTXSTS)); | |
2800 | ||
2801 | dwc2_writel(GINTSTS_USBRST, hsotg->regs + GINTSTS); | |
2802 | ||
2803 | /* Report disconnection if it is not already done. */ | |
2804 | dwc2_hsotg_disconnect(hsotg); | |
2805 | ||
2806 | if (usb_status & GOTGCTL_BSESVLD && connected) | |
2807 | dwc2_hsotg_core_init_disconnected(hsotg, true); | |
2808 | } | |
2809 | ||
47a1685f | 2810 | if (gintsts & GINTSTS_ENUMDONE) { |
95c8bc36 | 2811 | dwc2_writel(GINTSTS_ENUMDONE, hsotg->regs + GINTSTS); |
a3395f0d | 2812 | |
1f91b4cc | 2813 | dwc2_hsotg_irq_enumdone(hsotg); |
5b7d70c6 BD |
2814 | } |
2815 | ||
47a1685f | 2816 | if (gintsts & (GINTSTS_OEPINT | GINTSTS_IEPINT)) { |
95c8bc36 AS |
2817 | u32 daint = dwc2_readl(hsotg->regs + DAINT); |
2818 | u32 daintmsk = dwc2_readl(hsotg->regs + DAINTMSK); | |
7e804650 | 2819 | u32 daint_out, daint_in; |
5b7d70c6 BD |
2820 | int ep; |
2821 | ||
7e804650 | 2822 | daint &= daintmsk; |
47a1685f DN |
2823 | daint_out = daint >> DAINT_OUTEP_SHIFT; |
2824 | daint_in = daint & ~(daint_out << DAINT_OUTEP_SHIFT); | |
7e804650 | 2825 | |
5b7d70c6 BD |
2826 | dev_dbg(hsotg->dev, "%s: daint=%08x\n", __func__, daint); |
2827 | ||
cec87f1d MYK |
2828 | for (ep = 0; ep < hsotg->num_of_eps && daint_out; |
2829 | ep++, daint_out >>= 1) { | |
5b7d70c6 | 2830 | if (daint_out & 1) |
1f91b4cc | 2831 | dwc2_hsotg_epint(hsotg, ep, 0); |
5b7d70c6 BD |
2832 | } |
2833 | ||
cec87f1d MYK |
2834 | for (ep = 0; ep < hsotg->num_of_eps && daint_in; |
2835 | ep++, daint_in >>= 1) { | |
5b7d70c6 | 2836 | if (daint_in & 1) |
1f91b4cc | 2837 | dwc2_hsotg_epint(hsotg, ep, 1); |
5b7d70c6 | 2838 | } |
5b7d70c6 BD |
2839 | } |
2840 | ||
5b7d70c6 BD |
2841 | /* check both FIFOs */ |
2842 | ||
47a1685f | 2843 | if (gintsts & GINTSTS_NPTXFEMP) { |
5b7d70c6 BD |
2844 | dev_dbg(hsotg->dev, "NPTxFEmp\n"); |
2845 | ||
8b9bc460 LM |
2846 | /* |
2847 | * Disable the interrupt to stop it happening again | |
5b7d70c6 | 2848 | * unless one of these endpoint routines decides that |
8b9bc460 LM |
2849 | * it needs re-enabling |
2850 | */ | |
5b7d70c6 | 2851 | |
1f91b4cc FB |
2852 | dwc2_hsotg_disable_gsint(hsotg, GINTSTS_NPTXFEMP); |
2853 | dwc2_hsotg_irq_fifoempty(hsotg, false); | |
5b7d70c6 BD |
2854 | } |
2855 | ||
47a1685f | 2856 | if (gintsts & GINTSTS_PTXFEMP) { |
5b7d70c6 BD |
2857 | dev_dbg(hsotg->dev, "PTxFEmp\n"); |
2858 | ||
94cb8fd6 | 2859 | /* See note in GINTSTS_NPTxFEmp */ |
5b7d70c6 | 2860 | |
1f91b4cc FB |
2861 | dwc2_hsotg_disable_gsint(hsotg, GINTSTS_PTXFEMP); |
2862 | dwc2_hsotg_irq_fifoempty(hsotg, true); | |
5b7d70c6 BD |
2863 | } |
2864 | ||
47a1685f | 2865 | if (gintsts & GINTSTS_RXFLVL) { |
8b9bc460 LM |
2866 | /* |
2867 | * note, since GINTSTS_RxFLvl doubles as FIFO-not-empty, | |
1f91b4cc | 2868 | * we need to retry dwc2_hsotg_handle_rx if this is still |
8b9bc460 LM |
2869 | * set. |
2870 | */ | |
5b7d70c6 | 2871 | |
1f91b4cc | 2872 | dwc2_hsotg_handle_rx(hsotg); |
5b7d70c6 BD |
2873 | } |
2874 | ||
47a1685f | 2875 | if (gintsts & GINTSTS_ERLYSUSP) { |
94cb8fd6 | 2876 | dev_dbg(hsotg->dev, "GINTSTS_ErlySusp\n"); |
95c8bc36 | 2877 | dwc2_writel(GINTSTS_ERLYSUSP, hsotg->regs + GINTSTS); |
5b7d70c6 BD |
2878 | } |
2879 | ||
8b9bc460 LM |
2880 | /* |
2881 | * these next two seem to crop-up occasionally causing the core | |
5b7d70c6 | 2882 | * to shutdown the USB transfer, so try clearing them and logging |
8b9bc460 LM |
2883 | * the occurrence. |
2884 | */ | |
5b7d70c6 | 2885 | |
47a1685f | 2886 | if (gintsts & GINTSTS_GOUTNAKEFF) { |
837e9f00 VM |
2887 | u8 idx; |
2888 | u32 epctrl; | |
2889 | u32 gintmsk; | |
2890 | struct dwc2_hsotg_ep *hs_ep; | |
2891 | ||
2892 | /* Mask this interrupt */ | |
2893 | gintmsk = dwc2_readl(hsotg->regs + GINTMSK); | |
2894 | gintmsk &= ~GINTSTS_GOUTNAKEFF; | |
2895 | dwc2_writel(gintmsk, hsotg->regs + GINTMSK); | |
2896 | ||
2897 | dev_dbg(hsotg->dev, "GOUTNakEff triggered\n"); | |
2898 | for (idx = 1; idx <= hsotg->num_of_eps; idx++) { | |
2899 | hs_ep = hsotg->eps_out[idx]; | |
2900 | epctrl = dwc2_readl(hsotg->regs + DOEPCTL(idx)); | |
2901 | ||
2902 | if ((epctrl & DXEPCTL_EPENA) && hs_ep->isochronous) { | |
2903 | epctrl |= DXEPCTL_SNAK; | |
2904 | epctrl |= DXEPCTL_EPDIS; | |
2905 | dwc2_writel(epctrl, hsotg->regs + DOEPCTL(idx)); | |
2906 | } | |
2907 | } | |
a3395f0d | 2908 | |
837e9f00 | 2909 | /* This interrupt bit is cleared in DXEPINT_EPDISBLD handler */ |
5b7d70c6 BD |
2910 | } |
2911 | ||
47a1685f | 2912 | if (gintsts & GINTSTS_GINNAKEFF) { |
5b7d70c6 BD |
2913 | dev_info(hsotg->dev, "GINNakEff triggered\n"); |
2914 | ||
3be99cd0 | 2915 | __orr32(hsotg->regs + DCTL, DCTL_CGNPINNAK); |
a3395f0d | 2916 | |
1f91b4cc | 2917 | dwc2_hsotg_dump(hsotg); |
5b7d70c6 BD |
2918 | } |
2919 | ||
381fc8f8 VM |
2920 | if (gintsts & GINTSTS_INCOMPL_SOIN) |
2921 | dwc2_gadget_handle_incomplete_isoc_in(hsotg); | |
ec1f9d9f | 2922 | |
381fc8f8 VM |
2923 | if (gintsts & GINTSTS_INCOMPL_SOOUT) |
2924 | dwc2_gadget_handle_incomplete_isoc_out(hsotg); | |
ec1f9d9f | 2925 | |
8b9bc460 LM |
2926 | /* |
2927 | * if we've had fifo events, we should try and go around the | |
2928 | * loop again to see if there's any point in returning yet. | |
2929 | */ | |
5b7d70c6 BD |
2930 | |
2931 | if (gintsts & IRQ_RETRY_MASK && --retry_count > 0) | |
2932 | goto irq_retry; | |
2933 | ||
5ad1d316 LM |
2934 | spin_unlock(&hsotg->lock); |
2935 | ||
5b7d70c6 BD |
2936 | return IRQ_HANDLED; |
2937 | } | |
2938 | ||
2939 | /** | |
1f91b4cc | 2940 | * dwc2_hsotg_ep_enable - enable the given endpoint |
5b7d70c6 BD |
2941 | * @ep: The USB endpint to configure |
2942 | * @desc: The USB endpoint descriptor to configure with. | |
2943 | * | |
2944 | * This is called from the USB gadget code's usb_ep_enable(). | |
8b9bc460 | 2945 | */ |
1f91b4cc | 2946 | static int dwc2_hsotg_ep_enable(struct usb_ep *ep, |
5b7d70c6 BD |
2947 | const struct usb_endpoint_descriptor *desc) |
2948 | { | |
1f91b4cc | 2949 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 2950 | struct dwc2_hsotg *hsotg = hs_ep->parent; |
5b7d70c6 | 2951 | unsigned long flags; |
ca4c55ad | 2952 | unsigned int index = hs_ep->index; |
5b7d70c6 BD |
2953 | u32 epctrl_reg; |
2954 | u32 epctrl; | |
2955 | u32 mps; | |
837e9f00 | 2956 | u32 mask; |
ca4c55ad MYK |
2957 | unsigned int dir_in; |
2958 | unsigned int i, val, size; | |
19c190f9 | 2959 | int ret = 0; |
5b7d70c6 BD |
2960 | |
2961 | dev_dbg(hsotg->dev, | |
2962 | "%s: ep %s: a 0x%02x, attr 0x%02x, mps 0x%04x, intr %d\n", | |
2963 | __func__, ep->name, desc->bEndpointAddress, desc->bmAttributes, | |
2964 | desc->wMaxPacketSize, desc->bInterval); | |
2965 | ||
2966 | /* not to be called for EP0 */ | |
8c3d6092 VA |
2967 | if (index == 0) { |
2968 | dev_err(hsotg->dev, "%s: called for EP 0\n", __func__); | |
2969 | return -EINVAL; | |
2970 | } | |
5b7d70c6 BD |
2971 | |
2972 | dir_in = (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) ? 1 : 0; | |
2973 | if (dir_in != hs_ep->dir_in) { | |
2974 | dev_err(hsotg->dev, "%s: direction mismatch!\n", __func__); | |
2975 | return -EINVAL; | |
2976 | } | |
2977 | ||
29cc8897 | 2978 | mps = usb_endpoint_maxp(desc); |
5b7d70c6 | 2979 | |
1f91b4cc | 2980 | /* note, we handle this here instead of dwc2_hsotg_set_ep_maxpacket */ |
5b7d70c6 | 2981 | |
94cb8fd6 | 2982 | epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index); |
95c8bc36 | 2983 | epctrl = dwc2_readl(hsotg->regs + epctrl_reg); |
5b7d70c6 BD |
2984 | |
2985 | dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x from 0x%08x\n", | |
2986 | __func__, epctrl, epctrl_reg); | |
2987 | ||
22258f49 | 2988 | spin_lock_irqsave(&hsotg->lock, flags); |
5b7d70c6 | 2989 | |
47a1685f DN |
2990 | epctrl &= ~(DXEPCTL_EPTYPE_MASK | DXEPCTL_MPS_MASK); |
2991 | epctrl |= DXEPCTL_MPS(mps); | |
5b7d70c6 | 2992 | |
8b9bc460 LM |
2993 | /* |
2994 | * mark the endpoint as active, otherwise the core may ignore | |
2995 | * transactions entirely for this endpoint | |
2996 | */ | |
47a1685f | 2997 | epctrl |= DXEPCTL_USBACTEP; |
5b7d70c6 | 2998 | |
5b7d70c6 | 2999 | /* update the endpoint state */ |
1f91b4cc | 3000 | dwc2_hsotg_set_ep_maxpacket(hsotg, hs_ep->index, mps, dir_in); |
5b7d70c6 BD |
3001 | |
3002 | /* default, set to non-periodic */ | |
1479e841 | 3003 | hs_ep->isochronous = 0; |
5b7d70c6 | 3004 | hs_ep->periodic = 0; |
a18ed7b0 | 3005 | hs_ep->halted = 0; |
1479e841 | 3006 | hs_ep->interval = desc->bInterval; |
4fca54aa | 3007 | |
5b7d70c6 BD |
3008 | switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) { |
3009 | case USB_ENDPOINT_XFER_ISOC: | |
47a1685f DN |
3010 | epctrl |= DXEPCTL_EPTYPE_ISO; |
3011 | epctrl |= DXEPCTL_SETEVENFR; | |
1479e841 | 3012 | hs_ep->isochronous = 1; |
142bd33f | 3013 | hs_ep->interval = 1 << (desc->bInterval - 1); |
837e9f00 VM |
3014 | hs_ep->target_frame = TARGET_FRAME_INITIAL; |
3015 | if (dir_in) { | |
1479e841 | 3016 | hs_ep->periodic = 1; |
837e9f00 VM |
3017 | mask = dwc2_readl(hsotg->regs + DIEPMSK); |
3018 | mask |= DIEPMSK_NAKMSK; | |
3019 | dwc2_writel(mask, hsotg->regs + DIEPMSK); | |
3020 | } else { | |
3021 | mask = dwc2_readl(hsotg->regs + DOEPMSK); | |
3022 | mask |= DOEPMSK_OUTTKNEPDISMSK; | |
3023 | dwc2_writel(mask, hsotg->regs + DOEPMSK); | |
3024 | } | |
1479e841 | 3025 | break; |
5b7d70c6 BD |
3026 | |
3027 | case USB_ENDPOINT_XFER_BULK: | |
47a1685f | 3028 | epctrl |= DXEPCTL_EPTYPE_BULK; |
5b7d70c6 BD |
3029 | break; |
3030 | ||
3031 | case USB_ENDPOINT_XFER_INT: | |
b203d0a2 | 3032 | if (dir_in) |
5b7d70c6 | 3033 | hs_ep->periodic = 1; |
5b7d70c6 | 3034 | |
142bd33f VM |
3035 | if (hsotg->gadget.speed == USB_SPEED_HIGH) |
3036 | hs_ep->interval = 1 << (desc->bInterval - 1); | |
3037 | ||
47a1685f | 3038 | epctrl |= DXEPCTL_EPTYPE_INTERRUPT; |
5b7d70c6 BD |
3039 | break; |
3040 | ||
3041 | case USB_ENDPOINT_XFER_CONTROL: | |
47a1685f | 3042 | epctrl |= DXEPCTL_EPTYPE_CONTROL; |
5b7d70c6 BD |
3043 | break; |
3044 | } | |
3045 | ||
4556e12c MYK |
3046 | /* If fifo is already allocated for this ep */ |
3047 | if (hs_ep->fifo_index) { | |
3048 | size = hs_ep->ep.maxpacket * hs_ep->mc; | |
3049 | /* If bigger fifo is required deallocate current one */ | |
3050 | if (size > hs_ep->fifo_size) { | |
3051 | hsotg->fifo_map &= ~(1 << hs_ep->fifo_index); | |
3052 | hs_ep->fifo_index = 0; | |
3053 | hs_ep->fifo_size = 0; | |
3054 | } | |
3055 | } | |
3056 | ||
8b9bc460 LM |
3057 | /* |
3058 | * if the hardware has dedicated fifos, we must give each IN EP | |
10aebc77 BD |
3059 | * a unique tx-fifo even if it is non-periodic. |
3060 | */ | |
4556e12c | 3061 | if (dir_in && hsotg->dedicated_fifos && !hs_ep->fifo_index) { |
ca4c55ad MYK |
3062 | u32 fifo_index = 0; |
3063 | u32 fifo_size = UINT_MAX; | |
b203d0a2 | 3064 | size = hs_ep->ep.maxpacket*hs_ep->mc; |
5f2196bd | 3065 | for (i = 1; i < hsotg->num_of_eps; ++i) { |
b203d0a2 RB |
3066 | if (hsotg->fifo_map & (1<<i)) |
3067 | continue; | |
95c8bc36 | 3068 | val = dwc2_readl(hsotg->regs + DPTXFSIZN(i)); |
b203d0a2 RB |
3069 | val = (val >> FIFOSIZE_DEPTH_SHIFT)*4; |
3070 | if (val < size) | |
3071 | continue; | |
ca4c55ad MYK |
3072 | /* Search for smallest acceptable fifo */ |
3073 | if (val < fifo_size) { | |
3074 | fifo_size = val; | |
3075 | fifo_index = i; | |
3076 | } | |
b203d0a2 | 3077 | } |
ca4c55ad | 3078 | if (!fifo_index) { |
5f2196bd MYK |
3079 | dev_err(hsotg->dev, |
3080 | "%s: No suitable fifo found\n", __func__); | |
b585a48b SM |
3081 | ret = -ENOMEM; |
3082 | goto error; | |
3083 | } | |
ca4c55ad MYK |
3084 | hsotg->fifo_map |= 1 << fifo_index; |
3085 | epctrl |= DXEPCTL_TXFNUM(fifo_index); | |
3086 | hs_ep->fifo_index = fifo_index; | |
3087 | hs_ep->fifo_size = fifo_size; | |
b203d0a2 | 3088 | } |
10aebc77 | 3089 | |
5b7d70c6 | 3090 | /* for non control endpoints, set PID to D0 */ |
837e9f00 | 3091 | if (index && !hs_ep->isochronous) |
47a1685f | 3092 | epctrl |= DXEPCTL_SETD0PID; |
5b7d70c6 BD |
3093 | |
3094 | dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n", | |
3095 | __func__, epctrl); | |
3096 | ||
95c8bc36 | 3097 | dwc2_writel(epctrl, hsotg->regs + epctrl_reg); |
5b7d70c6 | 3098 | dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x\n", |
95c8bc36 | 3099 | __func__, dwc2_readl(hsotg->regs + epctrl_reg)); |
5b7d70c6 BD |
3100 | |
3101 | /* enable the endpoint interrupt */ | |
1f91b4cc | 3102 | dwc2_hsotg_ctrl_epint(hsotg, index, dir_in, 1); |
5b7d70c6 | 3103 | |
b585a48b | 3104 | error: |
22258f49 | 3105 | spin_unlock_irqrestore(&hsotg->lock, flags); |
19c190f9 | 3106 | return ret; |
5b7d70c6 BD |
3107 | } |
3108 | ||
8b9bc460 | 3109 | /** |
1f91b4cc | 3110 | * dwc2_hsotg_ep_disable - disable given endpoint |
8b9bc460 LM |
3111 | * @ep: The endpoint to disable. |
3112 | */ | |
1f91b4cc | 3113 | static int dwc2_hsotg_ep_disable(struct usb_ep *ep) |
5b7d70c6 | 3114 | { |
1f91b4cc | 3115 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 3116 | struct dwc2_hsotg *hsotg = hs_ep->parent; |
5b7d70c6 BD |
3117 | int dir_in = hs_ep->dir_in; |
3118 | int index = hs_ep->index; | |
3119 | unsigned long flags; | |
3120 | u32 epctrl_reg; | |
3121 | u32 ctrl; | |
3122 | ||
1e011293 | 3123 | dev_dbg(hsotg->dev, "%s(ep %p)\n", __func__, ep); |
5b7d70c6 | 3124 | |
c6f5c050 | 3125 | if (ep == &hsotg->eps_out[0]->ep) { |
5b7d70c6 BD |
3126 | dev_err(hsotg->dev, "%s: called for ep0\n", __func__); |
3127 | return -EINVAL; | |
3128 | } | |
3129 | ||
94cb8fd6 | 3130 | epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index); |
5b7d70c6 | 3131 | |
5ad1d316 | 3132 | spin_lock_irqsave(&hsotg->lock, flags); |
5b7d70c6 | 3133 | |
b203d0a2 RB |
3134 | hsotg->fifo_map &= ~(1<<hs_ep->fifo_index); |
3135 | hs_ep->fifo_index = 0; | |
3136 | hs_ep->fifo_size = 0; | |
5b7d70c6 | 3137 | |
95c8bc36 | 3138 | ctrl = dwc2_readl(hsotg->regs + epctrl_reg); |
47a1685f DN |
3139 | ctrl &= ~DXEPCTL_EPENA; |
3140 | ctrl &= ~DXEPCTL_USBACTEP; | |
3141 | ctrl |= DXEPCTL_SNAK; | |
5b7d70c6 BD |
3142 | |
3143 | dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl); | |
95c8bc36 | 3144 | dwc2_writel(ctrl, hsotg->regs + epctrl_reg); |
5b7d70c6 BD |
3145 | |
3146 | /* disable endpoint interrupts */ | |
1f91b4cc | 3147 | dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 0); |
5b7d70c6 | 3148 | |
1141ea01 MYK |
3149 | /* terminate all requests with shutdown */ |
3150 | kill_all_requests(hsotg, hs_ep, -ESHUTDOWN); | |
3151 | ||
22258f49 | 3152 | spin_unlock_irqrestore(&hsotg->lock, flags); |
5b7d70c6 BD |
3153 | return 0; |
3154 | } | |
3155 | ||
3156 | /** | |
3157 | * on_list - check request is on the given endpoint | |
3158 | * @ep: The endpoint to check. | |
3159 | * @test: The request to test if it is on the endpoint. | |
8b9bc460 | 3160 | */ |
1f91b4cc | 3161 | static bool on_list(struct dwc2_hsotg_ep *ep, struct dwc2_hsotg_req *test) |
5b7d70c6 | 3162 | { |
1f91b4cc | 3163 | struct dwc2_hsotg_req *req, *treq; |
5b7d70c6 BD |
3164 | |
3165 | list_for_each_entry_safe(req, treq, &ep->queue, queue) { | |
3166 | if (req == test) | |
3167 | return true; | |
3168 | } | |
3169 | ||
3170 | return false; | |
3171 | } | |
3172 | ||
c524dd5f MYK |
3173 | static int dwc2_hsotg_wait_bit_set(struct dwc2_hsotg *hs_otg, u32 reg, |
3174 | u32 bit, u32 timeout) | |
3175 | { | |
3176 | u32 i; | |
3177 | ||
3178 | for (i = 0; i < timeout; i++) { | |
3179 | if (dwc2_readl(hs_otg->regs + reg) & bit) | |
3180 | return 0; | |
3181 | udelay(1); | |
3182 | } | |
3183 | ||
3184 | return -ETIMEDOUT; | |
3185 | } | |
3186 | ||
3187 | static void dwc2_hsotg_ep_stop_xfr(struct dwc2_hsotg *hsotg, | |
3188 | struct dwc2_hsotg_ep *hs_ep) | |
3189 | { | |
3190 | u32 epctrl_reg; | |
3191 | u32 epint_reg; | |
3192 | ||
3193 | epctrl_reg = hs_ep->dir_in ? DIEPCTL(hs_ep->index) : | |
3194 | DOEPCTL(hs_ep->index); | |
3195 | epint_reg = hs_ep->dir_in ? DIEPINT(hs_ep->index) : | |
3196 | DOEPINT(hs_ep->index); | |
3197 | ||
3198 | dev_dbg(hsotg->dev, "%s: stopping transfer on %s\n", __func__, | |
3199 | hs_ep->name); | |
3200 | if (hs_ep->dir_in) { | |
3201 | __orr32(hsotg->regs + epctrl_reg, DXEPCTL_SNAK); | |
3202 | /* Wait for Nak effect */ | |
3203 | if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg, | |
3204 | DXEPINT_INEPNAKEFF, 100)) | |
3205 | dev_warn(hsotg->dev, | |
3206 | "%s: timeout DIEPINT.NAKEFF\n", __func__); | |
3207 | } else { | |
6b58cb07 VM |
3208 | if (!(dwc2_readl(hsotg->regs + GINTSTS) & GINTSTS_GOUTNAKEFF)) |
3209 | __orr32(hsotg->regs + DCTL, DCTL_SGOUTNAK); | |
c524dd5f MYK |
3210 | |
3211 | /* Wait for global nak to take effect */ | |
3212 | if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS, | |
0676c7e7 | 3213 | GINTSTS_GOUTNAKEFF, 100)) |
c524dd5f | 3214 | dev_warn(hsotg->dev, |
0676c7e7 | 3215 | "%s: timeout GINTSTS.GOUTNAKEFF\n", __func__); |
c524dd5f MYK |
3216 | } |
3217 | ||
3218 | /* Disable ep */ | |
3219 | __orr32(hsotg->regs + epctrl_reg, DXEPCTL_EPDIS | DXEPCTL_SNAK); | |
3220 | ||
3221 | /* Wait for ep to be disabled */ | |
3222 | if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg, DXEPINT_EPDISBLD, 100)) | |
3223 | dev_warn(hsotg->dev, | |
3224 | "%s: timeout DOEPCTL.EPDisable\n", __func__); | |
3225 | ||
3226 | if (hs_ep->dir_in) { | |
3227 | if (hsotg->dedicated_fifos) { | |
3228 | dwc2_writel(GRSTCTL_TXFNUM(hs_ep->fifo_index) | | |
3229 | GRSTCTL_TXFFLSH, hsotg->regs + GRSTCTL); | |
3230 | /* Wait for fifo flush */ | |
3231 | if (dwc2_hsotg_wait_bit_set(hsotg, GRSTCTL, | |
3232 | GRSTCTL_TXFFLSH, 100)) | |
3233 | dev_warn(hsotg->dev, | |
3234 | "%s: timeout flushing fifos\n", | |
3235 | __func__); | |
3236 | } | |
3237 | /* TODO: Flush shared tx fifo */ | |
3238 | } else { | |
3239 | /* Remove global NAKs */ | |
0676c7e7 | 3240 | __bic32(hsotg->regs + DCTL, DCTL_SGOUTNAK); |
c524dd5f MYK |
3241 | } |
3242 | } | |
3243 | ||
8b9bc460 | 3244 | /** |
1f91b4cc | 3245 | * dwc2_hsotg_ep_dequeue - dequeue given endpoint |
8b9bc460 LM |
3246 | * @ep: The endpoint to dequeue. |
3247 | * @req: The request to be removed from a queue. | |
3248 | */ | |
1f91b4cc | 3249 | static int dwc2_hsotg_ep_dequeue(struct usb_ep *ep, struct usb_request *req) |
5b7d70c6 | 3250 | { |
1f91b4cc FB |
3251 | struct dwc2_hsotg_req *hs_req = our_req(req); |
3252 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); | |
941fcce4 | 3253 | struct dwc2_hsotg *hs = hs_ep->parent; |
5b7d70c6 BD |
3254 | unsigned long flags; |
3255 | ||
1e011293 | 3256 | dev_dbg(hs->dev, "ep_dequeue(%p,%p)\n", ep, req); |
5b7d70c6 | 3257 | |
22258f49 | 3258 | spin_lock_irqsave(&hs->lock, flags); |
5b7d70c6 BD |
3259 | |
3260 | if (!on_list(hs_ep, hs_req)) { | |
22258f49 | 3261 | spin_unlock_irqrestore(&hs->lock, flags); |
5b7d70c6 BD |
3262 | return -EINVAL; |
3263 | } | |
3264 | ||
c524dd5f MYK |
3265 | /* Dequeue already started request */ |
3266 | if (req == &hs_ep->req->req) | |
3267 | dwc2_hsotg_ep_stop_xfr(hs, hs_ep); | |
3268 | ||
1f91b4cc | 3269 | dwc2_hsotg_complete_request(hs, hs_ep, hs_req, -ECONNRESET); |
22258f49 | 3270 | spin_unlock_irqrestore(&hs->lock, flags); |
5b7d70c6 BD |
3271 | |
3272 | return 0; | |
3273 | } | |
3274 | ||
8b9bc460 | 3275 | /** |
1f91b4cc | 3276 | * dwc2_hsotg_ep_sethalt - set halt on a given endpoint |
8b9bc460 LM |
3277 | * @ep: The endpoint to set halt. |
3278 | * @value: Set or unset the halt. | |
51da43b5 VA |
3279 | * @now: If true, stall the endpoint now. Otherwise return -EAGAIN if |
3280 | * the endpoint is busy processing requests. | |
3281 | * | |
3282 | * We need to stall the endpoint immediately if request comes from set_feature | |
3283 | * protocol command handler. | |
8b9bc460 | 3284 | */ |
51da43b5 | 3285 | static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now) |
5b7d70c6 | 3286 | { |
1f91b4cc | 3287 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 3288 | struct dwc2_hsotg *hs = hs_ep->parent; |
5b7d70c6 | 3289 | int index = hs_ep->index; |
5b7d70c6 BD |
3290 | u32 epreg; |
3291 | u32 epctl; | |
9c39ddc6 | 3292 | u32 xfertype; |
5b7d70c6 BD |
3293 | |
3294 | dev_info(hs->dev, "%s(ep %p %s, %d)\n", __func__, ep, ep->name, value); | |
3295 | ||
c9f721b2 RB |
3296 | if (index == 0) { |
3297 | if (value) | |
1f91b4cc | 3298 | dwc2_hsotg_stall_ep0(hs); |
c9f721b2 RB |
3299 | else |
3300 | dev_warn(hs->dev, | |
3301 | "%s: can't clear halt on ep0\n", __func__); | |
3302 | return 0; | |
3303 | } | |
3304 | ||
15186f10 VA |
3305 | if (hs_ep->isochronous) { |
3306 | dev_err(hs->dev, "%s is Isochronous Endpoint\n", ep->name); | |
3307 | return -EINVAL; | |
3308 | } | |
3309 | ||
51da43b5 VA |
3310 | if (!now && value && !list_empty(&hs_ep->queue)) { |
3311 | dev_dbg(hs->dev, "%s request is pending, cannot halt\n", | |
3312 | ep->name); | |
3313 | return -EAGAIN; | |
3314 | } | |
3315 | ||
c6f5c050 MYK |
3316 | if (hs_ep->dir_in) { |
3317 | epreg = DIEPCTL(index); | |
95c8bc36 | 3318 | epctl = dwc2_readl(hs->regs + epreg); |
c6f5c050 MYK |
3319 | |
3320 | if (value) { | |
5a350d53 | 3321 | epctl |= DXEPCTL_STALL | DXEPCTL_SNAK; |
c6f5c050 MYK |
3322 | if (epctl & DXEPCTL_EPENA) |
3323 | epctl |= DXEPCTL_EPDIS; | |
3324 | } else { | |
3325 | epctl &= ~DXEPCTL_STALL; | |
3326 | xfertype = epctl & DXEPCTL_EPTYPE_MASK; | |
3327 | if (xfertype == DXEPCTL_EPTYPE_BULK || | |
3328 | xfertype == DXEPCTL_EPTYPE_INTERRUPT) | |
3329 | epctl |= DXEPCTL_SETD0PID; | |
3330 | } | |
95c8bc36 | 3331 | dwc2_writel(epctl, hs->regs + epreg); |
9c39ddc6 | 3332 | } else { |
5b7d70c6 | 3333 | |
c6f5c050 | 3334 | epreg = DOEPCTL(index); |
95c8bc36 | 3335 | epctl = dwc2_readl(hs->regs + epreg); |
5b7d70c6 | 3336 | |
c6f5c050 MYK |
3337 | if (value) |
3338 | epctl |= DXEPCTL_STALL; | |
3339 | else { | |
3340 | epctl &= ~DXEPCTL_STALL; | |
3341 | xfertype = epctl & DXEPCTL_EPTYPE_MASK; | |
3342 | if (xfertype == DXEPCTL_EPTYPE_BULK || | |
3343 | xfertype == DXEPCTL_EPTYPE_INTERRUPT) | |
3344 | epctl |= DXEPCTL_SETD0PID; | |
3345 | } | |
95c8bc36 | 3346 | dwc2_writel(epctl, hs->regs + epreg); |
9c39ddc6 | 3347 | } |
5b7d70c6 | 3348 | |
a18ed7b0 RB |
3349 | hs_ep->halted = value; |
3350 | ||
5b7d70c6 BD |
3351 | return 0; |
3352 | } | |
3353 | ||
5ad1d316 | 3354 | /** |
1f91b4cc | 3355 | * dwc2_hsotg_ep_sethalt_lock - set halt on a given endpoint with lock held |
5ad1d316 LM |
3356 | * @ep: The endpoint to set halt. |
3357 | * @value: Set or unset the halt. | |
3358 | */ | |
1f91b4cc | 3359 | static int dwc2_hsotg_ep_sethalt_lock(struct usb_ep *ep, int value) |
5ad1d316 | 3360 | { |
1f91b4cc | 3361 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 3362 | struct dwc2_hsotg *hs = hs_ep->parent; |
5ad1d316 LM |
3363 | unsigned long flags = 0; |
3364 | int ret = 0; | |
3365 | ||
3366 | spin_lock_irqsave(&hs->lock, flags); | |
51da43b5 | 3367 | ret = dwc2_hsotg_ep_sethalt(ep, value, false); |
5ad1d316 LM |
3368 | spin_unlock_irqrestore(&hs->lock, flags); |
3369 | ||
3370 | return ret; | |
3371 | } | |
3372 | ||
1f91b4cc FB |
3373 | static struct usb_ep_ops dwc2_hsotg_ep_ops = { |
3374 | .enable = dwc2_hsotg_ep_enable, | |
3375 | .disable = dwc2_hsotg_ep_disable, | |
3376 | .alloc_request = dwc2_hsotg_ep_alloc_request, | |
3377 | .free_request = dwc2_hsotg_ep_free_request, | |
3378 | .queue = dwc2_hsotg_ep_queue_lock, | |
3379 | .dequeue = dwc2_hsotg_ep_dequeue, | |
3380 | .set_halt = dwc2_hsotg_ep_sethalt_lock, | |
25985edc | 3381 | /* note, don't believe we have any call for the fifo routines */ |
5b7d70c6 BD |
3382 | }; |
3383 | ||
8b9bc460 | 3384 | /** |
1f91b4cc | 3385 | * dwc2_hsotg_init - initalize the usb core |
8b9bc460 LM |
3386 | * @hsotg: The driver state |
3387 | */ | |
1f91b4cc | 3388 | static void dwc2_hsotg_init(struct dwc2_hsotg *hsotg) |
b3f489b2 | 3389 | { |
fa4a8d72 | 3390 | u32 trdtim; |
ecd9a7ad | 3391 | u32 usbcfg; |
b3f489b2 LM |
3392 | /* unmask subset of endpoint interrupts */ |
3393 | ||
95c8bc36 AS |
3394 | dwc2_writel(DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK | |
3395 | DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK, | |
3396 | hsotg->regs + DIEPMSK); | |
b3f489b2 | 3397 | |
95c8bc36 AS |
3398 | dwc2_writel(DOEPMSK_SETUPMSK | DOEPMSK_AHBERRMSK | |
3399 | DOEPMSK_EPDISBLDMSK | DOEPMSK_XFERCOMPLMSK, | |
3400 | hsotg->regs + DOEPMSK); | |
b3f489b2 | 3401 | |
95c8bc36 | 3402 | dwc2_writel(0, hsotg->regs + DAINTMSK); |
b3f489b2 LM |
3403 | |
3404 | /* Be in disconnected state until gadget is registered */ | |
47a1685f | 3405 | __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON); |
b3f489b2 | 3406 | |
b3f489b2 LM |
3407 | /* setup fifos */ |
3408 | ||
3409 | dev_dbg(hsotg->dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n", | |
95c8bc36 AS |
3410 | dwc2_readl(hsotg->regs + GRXFSIZ), |
3411 | dwc2_readl(hsotg->regs + GNPTXFSIZ)); | |
b3f489b2 | 3412 | |
1f91b4cc | 3413 | dwc2_hsotg_init_fifo(hsotg); |
b3f489b2 | 3414 | |
ecd9a7ad PR |
3415 | /* keep other bits untouched (so e.g. forced modes are not lost) */ |
3416 | usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); | |
3417 | usbcfg &= ~(GUSBCFG_TOUTCAL_MASK | GUSBCFG_PHYIF16 | GUSBCFG_SRPCAP | | |
3418 | GUSBCFG_HNPCAP); | |
3419 | ||
b3f489b2 | 3420 | /* set the PLL on, remove the HNP/SRP and set the PHY */ |
fa4a8d72 | 3421 | trdtim = (hsotg->phyif == GUSBCFG_PHYIF8) ? 9 : 5; |
ecd9a7ad PR |
3422 | usbcfg |= hsotg->phyif | GUSBCFG_TOUTCAL(7) | |
3423 | (trdtim << GUSBCFG_USBTRDTIM_SHIFT); | |
3424 | dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); | |
b3f489b2 | 3425 | |
f5090044 GH |
3426 | if (using_dma(hsotg)) |
3427 | __orr32(hsotg->regs + GAHBCFG, GAHBCFG_DMA_EN); | |
b3f489b2 LM |
3428 | } |
3429 | ||
8b9bc460 | 3430 | /** |
1f91b4cc | 3431 | * dwc2_hsotg_udc_start - prepare the udc for work |
8b9bc460 LM |
3432 | * @gadget: The usb gadget state |
3433 | * @driver: The usb gadget driver | |
3434 | * | |
3435 | * Perform initialization to prepare udc device and driver | |
3436 | * to work. | |
3437 | */ | |
1f91b4cc | 3438 | static int dwc2_hsotg_udc_start(struct usb_gadget *gadget, |
f65f0f10 | 3439 | struct usb_gadget_driver *driver) |
5b7d70c6 | 3440 | { |
941fcce4 | 3441 | struct dwc2_hsotg *hsotg = to_hsotg(gadget); |
5b9451f8 | 3442 | unsigned long flags; |
5b7d70c6 BD |
3443 | int ret; |
3444 | ||
3445 | if (!hsotg) { | |
a023da33 | 3446 | pr_err("%s: called with no device\n", __func__); |
5b7d70c6 BD |
3447 | return -ENODEV; |
3448 | } | |
3449 | ||
3450 | if (!driver) { | |
3451 | dev_err(hsotg->dev, "%s: no driver\n", __func__); | |
3452 | return -EINVAL; | |
3453 | } | |
3454 | ||
7177aed4 | 3455 | if (driver->max_speed < USB_SPEED_FULL) |
5b7d70c6 | 3456 | dev_err(hsotg->dev, "%s: bad speed\n", __func__); |
5b7d70c6 | 3457 | |
f65f0f10 | 3458 | if (!driver->setup) { |
5b7d70c6 BD |
3459 | dev_err(hsotg->dev, "%s: missing entry points\n", __func__); |
3460 | return -EINVAL; | |
3461 | } | |
3462 | ||
3463 | WARN_ON(hsotg->driver); | |
3464 | ||
3465 | driver->driver.bus = NULL; | |
3466 | hsotg->driver = driver; | |
7d7b2292 | 3467 | hsotg->gadget.dev.of_node = hsotg->dev->of_node; |
5b7d70c6 BD |
3468 | hsotg->gadget.speed = USB_SPEED_UNKNOWN; |
3469 | ||
09a75e85 MS |
3470 | if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) { |
3471 | ret = dwc2_lowlevel_hw_enable(hsotg); | |
3472 | if (ret) | |
3473 | goto err; | |
5b7d70c6 BD |
3474 | } |
3475 | ||
f6c01592 GH |
3476 | if (!IS_ERR_OR_NULL(hsotg->uphy)) |
3477 | otg_set_peripheral(hsotg->uphy->otg, &hsotg->gadget); | |
c816c47f | 3478 | |
5b9451f8 | 3479 | spin_lock_irqsave(&hsotg->lock, flags); |
1f91b4cc FB |
3480 | dwc2_hsotg_init(hsotg); |
3481 | dwc2_hsotg_core_init_disconnected(hsotg, false); | |
dc6e69e6 | 3482 | hsotg->enabled = 0; |
5b9451f8 MS |
3483 | spin_unlock_irqrestore(&hsotg->lock, flags); |
3484 | ||
5b7d70c6 | 3485 | dev_info(hsotg->dev, "bound driver %s\n", driver->driver.name); |
5b9451f8 | 3486 | |
5b7d70c6 BD |
3487 | return 0; |
3488 | ||
3489 | err: | |
3490 | hsotg->driver = NULL; | |
5b7d70c6 BD |
3491 | return ret; |
3492 | } | |
3493 | ||
8b9bc460 | 3494 | /** |
1f91b4cc | 3495 | * dwc2_hsotg_udc_stop - stop the udc |
8b9bc460 LM |
3496 | * @gadget: The usb gadget state |
3497 | * @driver: The usb gadget driver | |
3498 | * | |
3499 | * Stop udc hw block and stay tunned for future transmissions | |
3500 | */ | |
1f91b4cc | 3501 | static int dwc2_hsotg_udc_stop(struct usb_gadget *gadget) |
5b7d70c6 | 3502 | { |
941fcce4 | 3503 | struct dwc2_hsotg *hsotg = to_hsotg(gadget); |
2b19a52c | 3504 | unsigned long flags = 0; |
5b7d70c6 BD |
3505 | int ep; |
3506 | ||
3507 | if (!hsotg) | |
3508 | return -ENODEV; | |
3509 | ||
5b7d70c6 | 3510 | /* all endpoints should be shutdown */ |
c6f5c050 MYK |
3511 | for (ep = 1; ep < hsotg->num_of_eps; ep++) { |
3512 | if (hsotg->eps_in[ep]) | |
1f91b4cc | 3513 | dwc2_hsotg_ep_disable(&hsotg->eps_in[ep]->ep); |
c6f5c050 | 3514 | if (hsotg->eps_out[ep]) |
1f91b4cc | 3515 | dwc2_hsotg_ep_disable(&hsotg->eps_out[ep]->ep); |
c6f5c050 | 3516 | } |
5b7d70c6 | 3517 | |
2b19a52c LM |
3518 | spin_lock_irqsave(&hsotg->lock, flags); |
3519 | ||
32805c35 | 3520 | hsotg->driver = NULL; |
5b7d70c6 | 3521 | hsotg->gadget.speed = USB_SPEED_UNKNOWN; |
dc6e69e6 | 3522 | hsotg->enabled = 0; |
5b7d70c6 | 3523 | |
2b19a52c LM |
3524 | spin_unlock_irqrestore(&hsotg->lock, flags); |
3525 | ||
f6c01592 GH |
3526 | if (!IS_ERR_OR_NULL(hsotg->uphy)) |
3527 | otg_set_peripheral(hsotg->uphy->otg, NULL); | |
c816c47f | 3528 | |
09a75e85 MS |
3529 | if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) |
3530 | dwc2_lowlevel_hw_disable(hsotg); | |
5b7d70c6 BD |
3531 | |
3532 | return 0; | |
3533 | } | |
5b7d70c6 | 3534 | |
8b9bc460 | 3535 | /** |
1f91b4cc | 3536 | * dwc2_hsotg_gadget_getframe - read the frame number |
8b9bc460 LM |
3537 | * @gadget: The usb gadget state |
3538 | * | |
3539 | * Read the {micro} frame number | |
3540 | */ | |
1f91b4cc | 3541 | static int dwc2_hsotg_gadget_getframe(struct usb_gadget *gadget) |
5b7d70c6 | 3542 | { |
1f91b4cc | 3543 | return dwc2_hsotg_read_frameno(to_hsotg(gadget)); |
5b7d70c6 BD |
3544 | } |
3545 | ||
a188b689 | 3546 | /** |
1f91b4cc | 3547 | * dwc2_hsotg_pullup - connect/disconnect the USB PHY |
a188b689 LM |
3548 | * @gadget: The usb gadget state |
3549 | * @is_on: Current state of the USB PHY | |
3550 | * | |
3551 | * Connect/Disconnect the USB PHY pullup | |
3552 | */ | |
1f91b4cc | 3553 | static int dwc2_hsotg_pullup(struct usb_gadget *gadget, int is_on) |
a188b689 | 3554 | { |
941fcce4 | 3555 | struct dwc2_hsotg *hsotg = to_hsotg(gadget); |
a188b689 LM |
3556 | unsigned long flags = 0; |
3557 | ||
77ba9119 GH |
3558 | dev_dbg(hsotg->dev, "%s: is_on: %d op_state: %d\n", __func__, is_on, |
3559 | hsotg->op_state); | |
3560 | ||
3561 | /* Don't modify pullup state while in host mode */ | |
3562 | if (hsotg->op_state != OTG_STATE_B_PERIPHERAL) { | |
3563 | hsotg->enabled = is_on; | |
3564 | return 0; | |
3565 | } | |
a188b689 LM |
3566 | |
3567 | spin_lock_irqsave(&hsotg->lock, flags); | |
3568 | if (is_on) { | |
dc6e69e6 | 3569 | hsotg->enabled = 1; |
1f91b4cc FB |
3570 | dwc2_hsotg_core_init_disconnected(hsotg, false); |
3571 | dwc2_hsotg_core_connect(hsotg); | |
a188b689 | 3572 | } else { |
1f91b4cc FB |
3573 | dwc2_hsotg_core_disconnect(hsotg); |
3574 | dwc2_hsotg_disconnect(hsotg); | |
dc6e69e6 | 3575 | hsotg->enabled = 0; |
a188b689 LM |
3576 | } |
3577 | ||
3578 | hsotg->gadget.speed = USB_SPEED_UNKNOWN; | |
3579 | spin_unlock_irqrestore(&hsotg->lock, flags); | |
3580 | ||
3581 | return 0; | |
3582 | } | |
3583 | ||
1f91b4cc | 3584 | static int dwc2_hsotg_vbus_session(struct usb_gadget *gadget, int is_active) |
83d98223 GH |
3585 | { |
3586 | struct dwc2_hsotg *hsotg = to_hsotg(gadget); | |
3587 | unsigned long flags; | |
3588 | ||
3589 | dev_dbg(hsotg->dev, "%s: is_active: %d\n", __func__, is_active); | |
3590 | spin_lock_irqsave(&hsotg->lock, flags); | |
3591 | ||
61f7223b GH |
3592 | /* |
3593 | * If controller is hibernated, it must exit from hibernation | |
3594 | * before being initialized / de-initialized | |
3595 | */ | |
3596 | if (hsotg->lx_state == DWC2_L2) | |
3597 | dwc2_exit_hibernation(hsotg, false); | |
3598 | ||
83d98223 | 3599 | if (is_active) { |
cd0e641c | 3600 | hsotg->op_state = OTG_STATE_B_PERIPHERAL; |
065d3931 | 3601 | |
1f91b4cc | 3602 | dwc2_hsotg_core_init_disconnected(hsotg, false); |
83d98223 | 3603 | if (hsotg->enabled) |
1f91b4cc | 3604 | dwc2_hsotg_core_connect(hsotg); |
83d98223 | 3605 | } else { |
1f91b4cc FB |
3606 | dwc2_hsotg_core_disconnect(hsotg); |
3607 | dwc2_hsotg_disconnect(hsotg); | |
83d98223 GH |
3608 | } |
3609 | ||
3610 | spin_unlock_irqrestore(&hsotg->lock, flags); | |
3611 | return 0; | |
3612 | } | |
3613 | ||
596d696a | 3614 | /** |
1f91b4cc | 3615 | * dwc2_hsotg_vbus_draw - report bMaxPower field |
596d696a GH |
3616 | * @gadget: The usb gadget state |
3617 | * @mA: Amount of current | |
3618 | * | |
3619 | * Report how much power the device may consume to the phy. | |
3620 | */ | |
1f91b4cc | 3621 | static int dwc2_hsotg_vbus_draw(struct usb_gadget *gadget, unsigned mA) |
596d696a GH |
3622 | { |
3623 | struct dwc2_hsotg *hsotg = to_hsotg(gadget); | |
3624 | ||
3625 | if (IS_ERR_OR_NULL(hsotg->uphy)) | |
3626 | return -ENOTSUPP; | |
3627 | return usb_phy_set_power(hsotg->uphy, mA); | |
3628 | } | |
3629 | ||
1f91b4cc FB |
3630 | static const struct usb_gadget_ops dwc2_hsotg_gadget_ops = { |
3631 | .get_frame = dwc2_hsotg_gadget_getframe, | |
3632 | .udc_start = dwc2_hsotg_udc_start, | |
3633 | .udc_stop = dwc2_hsotg_udc_stop, | |
3634 | .pullup = dwc2_hsotg_pullup, | |
3635 | .vbus_session = dwc2_hsotg_vbus_session, | |
3636 | .vbus_draw = dwc2_hsotg_vbus_draw, | |
5b7d70c6 BD |
3637 | }; |
3638 | ||
3639 | /** | |
1f91b4cc | 3640 | * dwc2_hsotg_initep - initialise a single endpoint |
5b7d70c6 BD |
3641 | * @hsotg: The device state. |
3642 | * @hs_ep: The endpoint to be initialised. | |
3643 | * @epnum: The endpoint number | |
3644 | * | |
3645 | * Initialise the given endpoint (as part of the probe and device state | |
3646 | * creation) to give to the gadget driver. Setup the endpoint name, any | |
3647 | * direction information and other state that may be required. | |
3648 | */ | |
1f91b4cc FB |
3649 | static void dwc2_hsotg_initep(struct dwc2_hsotg *hsotg, |
3650 | struct dwc2_hsotg_ep *hs_ep, | |
c6f5c050 MYK |
3651 | int epnum, |
3652 | bool dir_in) | |
5b7d70c6 | 3653 | { |
5b7d70c6 BD |
3654 | char *dir; |
3655 | ||
3656 | if (epnum == 0) | |
3657 | dir = ""; | |
c6f5c050 | 3658 | else if (dir_in) |
5b7d70c6 | 3659 | dir = "in"; |
c6f5c050 MYK |
3660 | else |
3661 | dir = "out"; | |
5b7d70c6 | 3662 | |
c6f5c050 | 3663 | hs_ep->dir_in = dir_in; |
5b7d70c6 BD |
3664 | hs_ep->index = epnum; |
3665 | ||
3666 | snprintf(hs_ep->name, sizeof(hs_ep->name), "ep%d%s", epnum, dir); | |
3667 | ||
3668 | INIT_LIST_HEAD(&hs_ep->queue); | |
3669 | INIT_LIST_HEAD(&hs_ep->ep.ep_list); | |
3670 | ||
5b7d70c6 BD |
3671 | /* add to the list of endpoints known by the gadget driver */ |
3672 | if (epnum) | |
3673 | list_add_tail(&hs_ep->ep.ep_list, &hsotg->gadget.ep_list); | |
3674 | ||
3675 | hs_ep->parent = hsotg; | |
3676 | hs_ep->ep.name = hs_ep->name; | |
e117e742 | 3677 | usb_ep_set_maxpacket_limit(&hs_ep->ep, epnum ? 1024 : EP0_MPS_LIMIT); |
1f91b4cc | 3678 | hs_ep->ep.ops = &dwc2_hsotg_ep_ops; |
5b7d70c6 | 3679 | |
2954522f RB |
3680 | if (epnum == 0) { |
3681 | hs_ep->ep.caps.type_control = true; | |
3682 | } else { | |
3683 | hs_ep->ep.caps.type_iso = true; | |
3684 | hs_ep->ep.caps.type_bulk = true; | |
3685 | hs_ep->ep.caps.type_int = true; | |
3686 | } | |
3687 | ||
3688 | if (dir_in) | |
3689 | hs_ep->ep.caps.dir_in = true; | |
3690 | else | |
3691 | hs_ep->ep.caps.dir_out = true; | |
3692 | ||
8b9bc460 LM |
3693 | /* |
3694 | * if we're using dma, we need to set the next-endpoint pointer | |
5b7d70c6 BD |
3695 | * to be something valid. |
3696 | */ | |
3697 | ||
3698 | if (using_dma(hsotg)) { | |
47a1685f | 3699 | u32 next = DXEPCTL_NEXTEP((epnum + 1) % 15); |
c6f5c050 | 3700 | if (dir_in) |
95c8bc36 | 3701 | dwc2_writel(next, hsotg->regs + DIEPCTL(epnum)); |
c6f5c050 | 3702 | else |
95c8bc36 | 3703 | dwc2_writel(next, hsotg->regs + DOEPCTL(epnum)); |
5b7d70c6 BD |
3704 | } |
3705 | } | |
3706 | ||
b3f489b2 | 3707 | /** |
1f91b4cc | 3708 | * dwc2_hsotg_hw_cfg - read HW configuration registers |
b3f489b2 LM |
3709 | * @param: The device state |
3710 | * | |
3711 | * Read the USB core HW configuration registers | |
3712 | */ | |
1f91b4cc | 3713 | static int dwc2_hsotg_hw_cfg(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 3714 | { |
c6f5c050 MYK |
3715 | u32 cfg; |
3716 | u32 ep_type; | |
3717 | u32 i; | |
3718 | ||
b3f489b2 | 3719 | /* check hardware configuration */ |
5b7d70c6 | 3720 | |
43e90349 JY |
3721 | hsotg->num_of_eps = hsotg->hw_params.num_dev_ep; |
3722 | ||
c6f5c050 MYK |
3723 | /* Add ep0 */ |
3724 | hsotg->num_of_eps++; | |
10aebc77 | 3725 | |
1f91b4cc | 3726 | hsotg->eps_in[0] = devm_kzalloc(hsotg->dev, sizeof(struct dwc2_hsotg_ep), |
c6f5c050 MYK |
3727 | GFP_KERNEL); |
3728 | if (!hsotg->eps_in[0]) | |
3729 | return -ENOMEM; | |
1f91b4cc | 3730 | /* Same dwc2_hsotg_ep is used in both directions for ep0 */ |
c6f5c050 MYK |
3731 | hsotg->eps_out[0] = hsotg->eps_in[0]; |
3732 | ||
43e90349 | 3733 | cfg = hsotg->hw_params.dev_ep_dirs; |
251a17f5 | 3734 | for (i = 1, cfg >>= 2; i < hsotg->num_of_eps; i++, cfg >>= 2) { |
c6f5c050 MYK |
3735 | ep_type = cfg & 3; |
3736 | /* Direction in or both */ | |
3737 | if (!(ep_type & 2)) { | |
3738 | hsotg->eps_in[i] = devm_kzalloc(hsotg->dev, | |
1f91b4cc | 3739 | sizeof(struct dwc2_hsotg_ep), GFP_KERNEL); |
c6f5c050 MYK |
3740 | if (!hsotg->eps_in[i]) |
3741 | return -ENOMEM; | |
3742 | } | |
3743 | /* Direction out or both */ | |
3744 | if (!(ep_type & 1)) { | |
3745 | hsotg->eps_out[i] = devm_kzalloc(hsotg->dev, | |
1f91b4cc | 3746 | sizeof(struct dwc2_hsotg_ep), GFP_KERNEL); |
c6f5c050 MYK |
3747 | if (!hsotg->eps_out[i]) |
3748 | return -ENOMEM; | |
3749 | } | |
3750 | } | |
3751 | ||
43e90349 JY |
3752 | hsotg->fifo_mem = hsotg->hw_params.total_fifo_size; |
3753 | hsotg->dedicated_fifos = hsotg->hw_params.en_multiple_tx_fifo; | |
10aebc77 | 3754 | |
cff9eb75 MS |
3755 | dev_info(hsotg->dev, "EPs: %d, %s fifos, %d entries in SPRAM\n", |
3756 | hsotg->num_of_eps, | |
3757 | hsotg->dedicated_fifos ? "dedicated" : "shared", | |
3758 | hsotg->fifo_mem); | |
c6f5c050 | 3759 | return 0; |
5b7d70c6 BD |
3760 | } |
3761 | ||
8b9bc460 | 3762 | /** |
1f91b4cc | 3763 | * dwc2_hsotg_dump - dump state of the udc |
8b9bc460 LM |
3764 | * @param: The device state |
3765 | */ | |
1f91b4cc | 3766 | static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 3767 | { |
83a01804 | 3768 | #ifdef DEBUG |
5b7d70c6 BD |
3769 | struct device *dev = hsotg->dev; |
3770 | void __iomem *regs = hsotg->regs; | |
3771 | u32 val; | |
3772 | int idx; | |
3773 | ||
3774 | dev_info(dev, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n", | |
95c8bc36 AS |
3775 | dwc2_readl(regs + DCFG), dwc2_readl(regs + DCTL), |
3776 | dwc2_readl(regs + DIEPMSK)); | |
5b7d70c6 | 3777 | |
f889f23d | 3778 | dev_info(dev, "GAHBCFG=0x%08x, GHWCFG1=0x%08x\n", |
95c8bc36 | 3779 | dwc2_readl(regs + GAHBCFG), dwc2_readl(regs + GHWCFG1)); |
5b7d70c6 BD |
3780 | |
3781 | dev_info(dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n", | |
95c8bc36 | 3782 | dwc2_readl(regs + GRXFSIZ), dwc2_readl(regs + GNPTXFSIZ)); |
5b7d70c6 BD |
3783 | |
3784 | /* show periodic fifo settings */ | |
3785 | ||
364f8e93 | 3786 | for (idx = 1; idx < hsotg->num_of_eps; idx++) { |
95c8bc36 | 3787 | val = dwc2_readl(regs + DPTXFSIZN(idx)); |
5b7d70c6 | 3788 | dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx, |
47a1685f DN |
3789 | val >> FIFOSIZE_DEPTH_SHIFT, |
3790 | val & FIFOSIZE_STARTADDR_MASK); | |
5b7d70c6 BD |
3791 | } |
3792 | ||
364f8e93 | 3793 | for (idx = 0; idx < hsotg->num_of_eps; idx++) { |
5b7d70c6 BD |
3794 | dev_info(dev, |
3795 | "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx, | |
95c8bc36 AS |
3796 | dwc2_readl(regs + DIEPCTL(idx)), |
3797 | dwc2_readl(regs + DIEPTSIZ(idx)), | |
3798 | dwc2_readl(regs + DIEPDMA(idx))); | |
5b7d70c6 | 3799 | |
95c8bc36 | 3800 | val = dwc2_readl(regs + DOEPCTL(idx)); |
5b7d70c6 BD |
3801 | dev_info(dev, |
3802 | "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", | |
95c8bc36 AS |
3803 | idx, dwc2_readl(regs + DOEPCTL(idx)), |
3804 | dwc2_readl(regs + DOEPTSIZ(idx)), | |
3805 | dwc2_readl(regs + DOEPDMA(idx))); | |
5b7d70c6 BD |
3806 | |
3807 | } | |
3808 | ||
3809 | dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n", | |
95c8bc36 | 3810 | dwc2_readl(regs + DVBUSDIS), dwc2_readl(regs + DVBUSPULSE)); |
83a01804 | 3811 | #endif |
5b7d70c6 BD |
3812 | } |
3813 | ||
edd74be8 | 3814 | #ifdef CONFIG_OF |
1f91b4cc | 3815 | static void dwc2_hsotg_of_probe(struct dwc2_hsotg *hsotg) |
edd74be8 GH |
3816 | { |
3817 | struct device_node *np = hsotg->dev->of_node; | |
3818 | ||
3819 | /* Enable dma if requested in device tree */ | |
3820 | hsotg->g_using_dma = of_property_read_bool(np, "g-use-dma"); | |
0a176279 | 3821 | |
0a176279 GH |
3822 | /* Register RX fifo size */ |
3823 | of_property_read_u32(np, "g-rx-fifo-size", &hsotg->g_rx_fifo_sz); | |
3824 | ||
3825 | /* Register NPTX fifo size */ | |
3826 | of_property_read_u32(np, "g-np-tx-fifo-size", | |
3827 | &hsotg->g_np_g_tx_fifo_sz); | |
edd74be8 GH |
3828 | } |
3829 | #else | |
1f91b4cc | 3830 | static inline void dwc2_hsotg_of_probe(struct dwc2_hsotg *hsotg) { } |
edd74be8 GH |
3831 | #endif |
3832 | ||
8b9bc460 | 3833 | /** |
117777b2 DN |
3834 | * dwc2_gadget_init - init function for gadget |
3835 | * @dwc2: The data structure for the DWC2 driver. | |
3836 | * @irq: The IRQ number for the controller. | |
8b9bc460 | 3837 | */ |
117777b2 | 3838 | int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq) |
5b7d70c6 | 3839 | { |
117777b2 | 3840 | struct device *dev = hsotg->dev; |
5b7d70c6 BD |
3841 | int epnum; |
3842 | int ret; | |
3843 | ||
0a176279 GH |
3844 | /* Initialize to legacy fifo configuration values */ |
3845 | hsotg->g_rx_fifo_sz = 2048; | |
3846 | hsotg->g_np_g_tx_fifo_sz = 1024; | |
0a176279 | 3847 | /* Device tree specific probe */ |
1f91b4cc | 3848 | dwc2_hsotg_of_probe(hsotg); |
43e90349 JY |
3849 | |
3850 | /* Check against largest possible value. */ | |
3851 | if (hsotg->g_np_g_tx_fifo_sz > | |
3852 | hsotg->hw_params.dev_nperio_tx_fifo_size) { | |
3853 | dev_warn(dev, "Specified GNPTXFDEP=%d > %d\n", | |
3854 | hsotg->g_np_g_tx_fifo_sz, | |
3855 | hsotg->hw_params.dev_nperio_tx_fifo_size); | |
3856 | hsotg->g_np_g_tx_fifo_sz = | |
3857 | hsotg->hw_params.dev_nperio_tx_fifo_size; | |
3858 | } | |
3859 | ||
0a176279 GH |
3860 | /* Dump fifo information */ |
3861 | dev_dbg(dev, "NonPeriodic TXFIFO size: %d\n", | |
3862 | hsotg->g_np_g_tx_fifo_sz); | |
3863 | dev_dbg(dev, "RXFIFO size: %d\n", hsotg->g_rx_fifo_sz); | |
5b7d70c6 | 3864 | |
d327ab5b | 3865 | hsotg->gadget.max_speed = USB_SPEED_HIGH; |
1f91b4cc | 3866 | hsotg->gadget.ops = &dwc2_hsotg_gadget_ops; |
5b7d70c6 | 3867 | hsotg->gadget.name = dev_name(dev); |
097ee662 GH |
3868 | if (hsotg->dr_mode == USB_DR_MODE_OTG) |
3869 | hsotg->gadget.is_otg = 1; | |
ec4cc657 MYK |
3870 | else if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) |
3871 | hsotg->op_state = OTG_STATE_B_PERIPHERAL; | |
5b7d70c6 | 3872 | |
1f91b4cc | 3873 | ret = dwc2_hsotg_hw_cfg(hsotg); |
c6f5c050 MYK |
3874 | if (ret) { |
3875 | dev_err(hsotg->dev, "Hardware configuration failed: %d\n", ret); | |
09a75e85 | 3876 | return ret; |
c6f5c050 MYK |
3877 | } |
3878 | ||
3f95001d MYK |
3879 | hsotg->ctrl_buff = devm_kzalloc(hsotg->dev, |
3880 | DWC2_CTRL_BUFF_SIZE, GFP_KERNEL); | |
8bae0f8c | 3881 | if (!hsotg->ctrl_buff) |
09a75e85 | 3882 | return -ENOMEM; |
3f95001d MYK |
3883 | |
3884 | hsotg->ep0_buff = devm_kzalloc(hsotg->dev, | |
3885 | DWC2_CTRL_BUFF_SIZE, GFP_KERNEL); | |
8bae0f8c | 3886 | if (!hsotg->ep0_buff) |
09a75e85 | 3887 | return -ENOMEM; |
3f95001d | 3888 | |
1f91b4cc | 3889 | ret = devm_request_irq(hsotg->dev, irq, dwc2_hsotg_irq, IRQF_SHARED, |
db8178c3 | 3890 | dev_name(hsotg->dev), hsotg); |
eb3c56c5 | 3891 | if (ret < 0) { |
db8178c3 | 3892 | dev_err(dev, "cannot claim IRQ for gadget\n"); |
09a75e85 | 3893 | return ret; |
eb3c56c5 MS |
3894 | } |
3895 | ||
b3f489b2 LM |
3896 | /* hsotg->num_of_eps holds number of EPs other than ep0 */ |
3897 | ||
3898 | if (hsotg->num_of_eps == 0) { | |
3899 | dev_err(dev, "wrong number of EPs (zero)\n"); | |
09a75e85 | 3900 | return -EINVAL; |
b3f489b2 LM |
3901 | } |
3902 | ||
b3f489b2 LM |
3903 | /* setup endpoint information */ |
3904 | ||
3905 | INIT_LIST_HEAD(&hsotg->gadget.ep_list); | |
c6f5c050 | 3906 | hsotg->gadget.ep0 = &hsotg->eps_out[0]->ep; |
b3f489b2 LM |
3907 | |
3908 | /* allocate EP0 request */ | |
3909 | ||
1f91b4cc | 3910 | hsotg->ctrl_req = dwc2_hsotg_ep_alloc_request(&hsotg->eps_out[0]->ep, |
b3f489b2 LM |
3911 | GFP_KERNEL); |
3912 | if (!hsotg->ctrl_req) { | |
3913 | dev_err(dev, "failed to allocate ctrl req\n"); | |
09a75e85 | 3914 | return -ENOMEM; |
b3f489b2 | 3915 | } |
5b7d70c6 BD |
3916 | |
3917 | /* initialise the endpoints now the core has been initialised */ | |
c6f5c050 MYK |
3918 | for (epnum = 0; epnum < hsotg->num_of_eps; epnum++) { |
3919 | if (hsotg->eps_in[epnum]) | |
1f91b4cc | 3920 | dwc2_hsotg_initep(hsotg, hsotg->eps_in[epnum], |
c6f5c050 MYK |
3921 | epnum, 1); |
3922 | if (hsotg->eps_out[epnum]) | |
1f91b4cc | 3923 | dwc2_hsotg_initep(hsotg, hsotg->eps_out[epnum], |
c6f5c050 MYK |
3924 | epnum, 0); |
3925 | } | |
5b7d70c6 | 3926 | |
117777b2 | 3927 | ret = usb_add_gadget_udc(dev, &hsotg->gadget); |
0f91349b | 3928 | if (ret) |
09a75e85 | 3929 | return ret; |
0f91349b | 3930 | |
1f91b4cc | 3931 | dwc2_hsotg_dump(hsotg); |
5b7d70c6 | 3932 | |
5b7d70c6 | 3933 | return 0; |
5b7d70c6 BD |
3934 | } |
3935 | ||
8b9bc460 | 3936 | /** |
1f91b4cc | 3937 | * dwc2_hsotg_remove - remove function for hsotg driver |
8b9bc460 LM |
3938 | * @pdev: The platform information for the driver |
3939 | */ | |
1f91b4cc | 3940 | int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 3941 | { |
0f91349b | 3942 | usb_del_gadget_udc(&hsotg->gadget); |
31ee04de | 3943 | |
5b7d70c6 BD |
3944 | return 0; |
3945 | } | |
3946 | ||
1f91b4cc | 3947 | int dwc2_hsotg_suspend(struct dwc2_hsotg *hsotg) |
b83e333a | 3948 | { |
b83e333a | 3949 | unsigned long flags; |
b83e333a | 3950 | |
9e779778 | 3951 | if (hsotg->lx_state != DWC2_L0) |
09a75e85 | 3952 | return 0; |
9e779778 | 3953 | |
dc6e69e6 MS |
3954 | if (hsotg->driver) { |
3955 | int ep; | |
3956 | ||
b83e333a MS |
3957 | dev_info(hsotg->dev, "suspending usb gadget %s\n", |
3958 | hsotg->driver->driver.name); | |
3959 | ||
dc6e69e6 MS |
3960 | spin_lock_irqsave(&hsotg->lock, flags); |
3961 | if (hsotg->enabled) | |
1f91b4cc FB |
3962 | dwc2_hsotg_core_disconnect(hsotg); |
3963 | dwc2_hsotg_disconnect(hsotg); | |
dc6e69e6 MS |
3964 | hsotg->gadget.speed = USB_SPEED_UNKNOWN; |
3965 | spin_unlock_irqrestore(&hsotg->lock, flags); | |
b83e333a | 3966 | |
c6f5c050 MYK |
3967 | for (ep = 0; ep < hsotg->num_of_eps; ep++) { |
3968 | if (hsotg->eps_in[ep]) | |
1f91b4cc | 3969 | dwc2_hsotg_ep_disable(&hsotg->eps_in[ep]->ep); |
c6f5c050 | 3970 | if (hsotg->eps_out[ep]) |
1f91b4cc | 3971 | dwc2_hsotg_ep_disable(&hsotg->eps_out[ep]->ep); |
c6f5c050 | 3972 | } |
b83e333a MS |
3973 | } |
3974 | ||
09a75e85 | 3975 | return 0; |
b83e333a MS |
3976 | } |
3977 | ||
1f91b4cc | 3978 | int dwc2_hsotg_resume(struct dwc2_hsotg *hsotg) |
b83e333a | 3979 | { |
b83e333a | 3980 | unsigned long flags; |
b83e333a | 3981 | |
9e779778 | 3982 | if (hsotg->lx_state == DWC2_L2) |
09a75e85 | 3983 | return 0; |
9e779778 | 3984 | |
b83e333a MS |
3985 | if (hsotg->driver) { |
3986 | dev_info(hsotg->dev, "resuming usb gadget %s\n", | |
3987 | hsotg->driver->driver.name); | |
d00b4142 | 3988 | |
dc6e69e6 | 3989 | spin_lock_irqsave(&hsotg->lock, flags); |
1f91b4cc | 3990 | dwc2_hsotg_core_init_disconnected(hsotg, false); |
dc6e69e6 | 3991 | if (hsotg->enabled) |
1f91b4cc | 3992 | dwc2_hsotg_core_connect(hsotg); |
dc6e69e6 MS |
3993 | spin_unlock_irqrestore(&hsotg->lock, flags); |
3994 | } | |
b83e333a | 3995 | |
09a75e85 | 3996 | return 0; |
b83e333a | 3997 | } |
58e52ff6 JY |
3998 | |
3999 | /** | |
4000 | * dwc2_backup_device_registers() - Backup controller device registers. | |
4001 | * When suspending usb bus, registers needs to be backuped | |
4002 | * if controller power is disabled once suspended. | |
4003 | * | |
4004 | * @hsotg: Programming view of the DWC_otg controller | |
4005 | */ | |
4006 | int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg) | |
4007 | { | |
4008 | struct dwc2_dregs_backup *dr; | |
4009 | int i; | |
4010 | ||
4011 | dev_dbg(hsotg->dev, "%s\n", __func__); | |
4012 | ||
4013 | /* Backup dev regs */ | |
4014 | dr = &hsotg->dr_backup; | |
4015 | ||
4016 | dr->dcfg = dwc2_readl(hsotg->regs + DCFG); | |
4017 | dr->dctl = dwc2_readl(hsotg->regs + DCTL); | |
4018 | dr->daintmsk = dwc2_readl(hsotg->regs + DAINTMSK); | |
4019 | dr->diepmsk = dwc2_readl(hsotg->regs + DIEPMSK); | |
4020 | dr->doepmsk = dwc2_readl(hsotg->regs + DOEPMSK); | |
4021 | ||
4022 | for (i = 0; i < hsotg->num_of_eps; i++) { | |
4023 | /* Backup IN EPs */ | |
4024 | dr->diepctl[i] = dwc2_readl(hsotg->regs + DIEPCTL(i)); | |
4025 | ||
4026 | /* Ensure DATA PID is correctly configured */ | |
4027 | if (dr->diepctl[i] & DXEPCTL_DPID) | |
4028 | dr->diepctl[i] |= DXEPCTL_SETD1PID; | |
4029 | else | |
4030 | dr->diepctl[i] |= DXEPCTL_SETD0PID; | |
4031 | ||
4032 | dr->dieptsiz[i] = dwc2_readl(hsotg->regs + DIEPTSIZ(i)); | |
4033 | dr->diepdma[i] = dwc2_readl(hsotg->regs + DIEPDMA(i)); | |
4034 | ||
4035 | /* Backup OUT EPs */ | |
4036 | dr->doepctl[i] = dwc2_readl(hsotg->regs + DOEPCTL(i)); | |
4037 | ||
4038 | /* Ensure DATA PID is correctly configured */ | |
4039 | if (dr->doepctl[i] & DXEPCTL_DPID) | |
4040 | dr->doepctl[i] |= DXEPCTL_SETD1PID; | |
4041 | else | |
4042 | dr->doepctl[i] |= DXEPCTL_SETD0PID; | |
4043 | ||
4044 | dr->doeptsiz[i] = dwc2_readl(hsotg->regs + DOEPTSIZ(i)); | |
4045 | dr->doepdma[i] = dwc2_readl(hsotg->regs + DOEPDMA(i)); | |
4046 | } | |
4047 | dr->valid = true; | |
4048 | return 0; | |
4049 | } | |
4050 | ||
4051 | /** | |
4052 | * dwc2_restore_device_registers() - Restore controller device registers. | |
4053 | * When resuming usb bus, device registers needs to be restored | |
4054 | * if controller power were disabled. | |
4055 | * | |
4056 | * @hsotg: Programming view of the DWC_otg controller | |
4057 | */ | |
4058 | int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg) | |
4059 | { | |
4060 | struct dwc2_dregs_backup *dr; | |
4061 | u32 dctl; | |
4062 | int i; | |
4063 | ||
4064 | dev_dbg(hsotg->dev, "%s\n", __func__); | |
4065 | ||
4066 | /* Restore dev regs */ | |
4067 | dr = &hsotg->dr_backup; | |
4068 | if (!dr->valid) { | |
4069 | dev_err(hsotg->dev, "%s: no device registers to restore\n", | |
4070 | __func__); | |
4071 | return -EINVAL; | |
4072 | } | |
4073 | dr->valid = false; | |
4074 | ||
4075 | dwc2_writel(dr->dcfg, hsotg->regs + DCFG); | |
4076 | dwc2_writel(dr->dctl, hsotg->regs + DCTL); | |
4077 | dwc2_writel(dr->daintmsk, hsotg->regs + DAINTMSK); | |
4078 | dwc2_writel(dr->diepmsk, hsotg->regs + DIEPMSK); | |
4079 | dwc2_writel(dr->doepmsk, hsotg->regs + DOEPMSK); | |
4080 | ||
4081 | for (i = 0; i < hsotg->num_of_eps; i++) { | |
4082 | /* Restore IN EPs */ | |
4083 | dwc2_writel(dr->diepctl[i], hsotg->regs + DIEPCTL(i)); | |
4084 | dwc2_writel(dr->dieptsiz[i], hsotg->regs + DIEPTSIZ(i)); | |
4085 | dwc2_writel(dr->diepdma[i], hsotg->regs + DIEPDMA(i)); | |
4086 | ||
4087 | /* Restore OUT EPs */ | |
4088 | dwc2_writel(dr->doepctl[i], hsotg->regs + DOEPCTL(i)); | |
4089 | dwc2_writel(dr->doeptsiz[i], hsotg->regs + DOEPTSIZ(i)); | |
4090 | dwc2_writel(dr->doepdma[i], hsotg->regs + DOEPDMA(i)); | |
4091 | } | |
4092 | ||
4093 | /* Set the Power-On Programming done bit */ | |
4094 | dctl = dwc2_readl(hsotg->regs + DCTL); | |
4095 | dctl |= DCTL_PWRONPRGDONE; | |
4096 | dwc2_writel(dctl, hsotg->regs + DCTL); | |
4097 | ||
4098 | return 0; | |
4099 | } |