Commit | Line | Data |
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5fd54ace | 1 | // SPDX-License-Identifier: GPL-2.0 |
6fb914d7 | 2 | /* |
dfbc6fa3 AT |
3 | * Copyright (c) 2011 Samsung Electronics Co., Ltd. |
4 | * http://www.samsung.com | |
5b7d70c6 BD |
5 | * |
6 | * Copyright 2008 Openmoko, Inc. | |
7 | * Copyright 2008 Simtec Electronics | |
8 | * Ben Dooks <ben@simtec.co.uk> | |
9 | * http://armlinux.simtec.co.uk/ | |
10 | * | |
11 | * S3C USB2.0 High-speed / OtG driver | |
8b9bc460 | 12 | */ |
5b7d70c6 BD |
13 | |
14 | #include <linux/kernel.h> | |
15 | #include <linux/module.h> | |
16 | #include <linux/spinlock.h> | |
17 | #include <linux/interrupt.h> | |
18 | #include <linux/platform_device.h> | |
19 | #include <linux/dma-mapping.h> | |
7ad8096e | 20 | #include <linux/mutex.h> |
5b7d70c6 BD |
21 | #include <linux/seq_file.h> |
22 | #include <linux/delay.h> | |
23 | #include <linux/io.h> | |
5a0e3ad6 | 24 | #include <linux/slab.h> |
c50f056c | 25 | #include <linux/of_platform.h> |
5b7d70c6 BD |
26 | |
27 | #include <linux/usb/ch9.h> | |
28 | #include <linux/usb/gadget.h> | |
b2e587db | 29 | #include <linux/usb/phy.h> |
5b7d70c6 | 30 | |
f7c0b143 | 31 | #include "core.h" |
941fcce4 | 32 | #include "hw.h" |
5b7d70c6 BD |
33 | |
34 | /* conversion functions */ | |
1f91b4cc | 35 | static inline struct dwc2_hsotg_req *our_req(struct usb_request *req) |
5b7d70c6 | 36 | { |
1f91b4cc | 37 | return container_of(req, struct dwc2_hsotg_req, req); |
5b7d70c6 BD |
38 | } |
39 | ||
1f91b4cc | 40 | static inline struct dwc2_hsotg_ep *our_ep(struct usb_ep *ep) |
5b7d70c6 | 41 | { |
1f91b4cc | 42 | return container_of(ep, struct dwc2_hsotg_ep, ep); |
5b7d70c6 BD |
43 | } |
44 | ||
941fcce4 | 45 | static inline struct dwc2_hsotg *to_hsotg(struct usb_gadget *gadget) |
5b7d70c6 | 46 | { |
941fcce4 | 47 | return container_of(gadget, struct dwc2_hsotg, gadget); |
5b7d70c6 BD |
48 | } |
49 | ||
abd064a1 | 50 | static inline void dwc2_set_bit(void __iomem *ptr, u32 val) |
5b7d70c6 | 51 | { |
95c8bc36 | 52 | dwc2_writel(dwc2_readl(ptr) | val, ptr); |
5b7d70c6 BD |
53 | } |
54 | ||
abd064a1 | 55 | static inline void dwc2_clear_bit(void __iomem *ptr, u32 val) |
5b7d70c6 | 56 | { |
95c8bc36 | 57 | dwc2_writel(dwc2_readl(ptr) & ~val, ptr); |
5b7d70c6 BD |
58 | } |
59 | ||
1f91b4cc | 60 | static inline struct dwc2_hsotg_ep *index_to_ep(struct dwc2_hsotg *hsotg, |
c6f5c050 MYK |
61 | u32 ep_index, u32 dir_in) |
62 | { | |
63 | if (dir_in) | |
64 | return hsotg->eps_in[ep_index]; | |
65 | else | |
66 | return hsotg->eps_out[ep_index]; | |
67 | } | |
68 | ||
997f4f81 | 69 | /* forward declaration of functions */ |
1f91b4cc | 70 | static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg); |
5b7d70c6 BD |
71 | |
72 | /** | |
73 | * using_dma - return the DMA status of the driver. | |
74 | * @hsotg: The driver state. | |
75 | * | |
76 | * Return true if we're using DMA. | |
77 | * | |
78 | * Currently, we have the DMA support code worked into everywhere | |
79 | * that needs it, but the AMBA DMA implementation in the hardware can | |
80 | * only DMA from 32bit aligned addresses. This means that gadgets such | |
81 | * as the CDC Ethernet cannot work as they often pass packets which are | |
82 | * not 32bit aligned. | |
83 | * | |
84 | * Unfortunately the choice to use DMA or not is global to the controller | |
85 | * and seems to be only settable when the controller is being put through | |
86 | * a core reset. This means we either need to fix the gadgets to take | |
87 | * account of DMA alignment, or add bounce buffers (yuerk). | |
88 | * | |
edd74be8 | 89 | * g_using_dma is set depending on dts flag. |
5b7d70c6 | 90 | */ |
941fcce4 | 91 | static inline bool using_dma(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 92 | { |
05ee799f | 93 | return hsotg->params.g_dma; |
5b7d70c6 BD |
94 | } |
95 | ||
dec4b556 VA |
96 | /* |
97 | * using_desc_dma - return the descriptor DMA status of the driver. | |
98 | * @hsotg: The driver state. | |
99 | * | |
100 | * Return true if we're using descriptor DMA. | |
101 | */ | |
102 | static inline bool using_desc_dma(struct dwc2_hsotg *hsotg) | |
103 | { | |
104 | return hsotg->params.g_dma_desc; | |
105 | } | |
106 | ||
92d1635d VM |
107 | /** |
108 | * dwc2_gadget_incr_frame_num - Increments the targeted frame number. | |
109 | * @hs_ep: The endpoint | |
92d1635d VM |
110 | * |
111 | * This function will also check if the frame number overruns DSTS_SOFFN_LIMIT. | |
112 | * If an overrun occurs it will wrap the value and set the frame_overrun flag. | |
113 | */ | |
114 | static inline void dwc2_gadget_incr_frame_num(struct dwc2_hsotg_ep *hs_ep) | |
115 | { | |
116 | hs_ep->target_frame += hs_ep->interval; | |
117 | if (hs_ep->target_frame > DSTS_SOFFN_LIMIT) { | |
c1d5df69 | 118 | hs_ep->frame_overrun = true; |
92d1635d VM |
119 | hs_ep->target_frame &= DSTS_SOFFN_LIMIT; |
120 | } else { | |
c1d5df69 | 121 | hs_ep->frame_overrun = false; |
92d1635d VM |
122 | } |
123 | } | |
124 | ||
5b7d70c6 | 125 | /** |
1f91b4cc | 126 | * dwc2_hsotg_en_gsint - enable one or more of the general interrupt |
5b7d70c6 BD |
127 | * @hsotg: The device state |
128 | * @ints: A bitmask of the interrupts to enable | |
129 | */ | |
1f91b4cc | 130 | static void dwc2_hsotg_en_gsint(struct dwc2_hsotg *hsotg, u32 ints) |
5b7d70c6 | 131 | { |
95c8bc36 | 132 | u32 gsintmsk = dwc2_readl(hsotg->regs + GINTMSK); |
5b7d70c6 BD |
133 | u32 new_gsintmsk; |
134 | ||
135 | new_gsintmsk = gsintmsk | ints; | |
136 | ||
137 | if (new_gsintmsk != gsintmsk) { | |
138 | dev_dbg(hsotg->dev, "gsintmsk now 0x%08x\n", new_gsintmsk); | |
95c8bc36 | 139 | dwc2_writel(new_gsintmsk, hsotg->regs + GINTMSK); |
5b7d70c6 BD |
140 | } |
141 | } | |
142 | ||
143 | /** | |
1f91b4cc | 144 | * dwc2_hsotg_disable_gsint - disable one or more of the general interrupt |
5b7d70c6 BD |
145 | * @hsotg: The device state |
146 | * @ints: A bitmask of the interrupts to enable | |
147 | */ | |
1f91b4cc | 148 | static void dwc2_hsotg_disable_gsint(struct dwc2_hsotg *hsotg, u32 ints) |
5b7d70c6 | 149 | { |
95c8bc36 | 150 | u32 gsintmsk = dwc2_readl(hsotg->regs + GINTMSK); |
5b7d70c6 BD |
151 | u32 new_gsintmsk; |
152 | ||
153 | new_gsintmsk = gsintmsk & ~ints; | |
154 | ||
155 | if (new_gsintmsk != gsintmsk) | |
95c8bc36 | 156 | dwc2_writel(new_gsintmsk, hsotg->regs + GINTMSK); |
5b7d70c6 BD |
157 | } |
158 | ||
159 | /** | |
1f91b4cc | 160 | * dwc2_hsotg_ctrl_epint - enable/disable an endpoint irq |
5b7d70c6 BD |
161 | * @hsotg: The device state |
162 | * @ep: The endpoint index | |
163 | * @dir_in: True if direction is in. | |
164 | * @en: The enable value, true to enable | |
165 | * | |
166 | * Set or clear the mask for an individual endpoint's interrupt | |
167 | * request. | |
168 | */ | |
1f91b4cc | 169 | static void dwc2_hsotg_ctrl_epint(struct dwc2_hsotg *hsotg, |
9da51974 | 170 | unsigned int ep, unsigned int dir_in, |
5b7d70c6 BD |
171 | unsigned int en) |
172 | { | |
173 | unsigned long flags; | |
174 | u32 bit = 1 << ep; | |
175 | u32 daint; | |
176 | ||
177 | if (!dir_in) | |
178 | bit <<= 16; | |
179 | ||
180 | local_irq_save(flags); | |
95c8bc36 | 181 | daint = dwc2_readl(hsotg->regs + DAINTMSK); |
5b7d70c6 BD |
182 | if (en) |
183 | daint |= bit; | |
184 | else | |
185 | daint &= ~bit; | |
95c8bc36 | 186 | dwc2_writel(daint, hsotg->regs + DAINTMSK); |
5b7d70c6 BD |
187 | local_irq_restore(flags); |
188 | } | |
189 | ||
c138ecfa SA |
190 | /** |
191 | * dwc2_hsotg_tx_fifo_count - return count of TX FIFOs in device mode | |
6fb914d7 GT |
192 | * |
193 | * @hsotg: Programming view of the DWC_otg controller | |
c138ecfa SA |
194 | */ |
195 | int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg *hsotg) | |
196 | { | |
197 | if (hsotg->hw_params.en_multiple_tx_fifo) | |
198 | /* In dedicated FIFO mode we need count of IN EPs */ | |
9273083a | 199 | return hsotg->hw_params.num_dev_in_eps; |
c138ecfa SA |
200 | else |
201 | /* In shared FIFO mode we need count of Periodic IN EPs */ | |
202 | return hsotg->hw_params.num_dev_perio_in_ep; | |
203 | } | |
204 | ||
c138ecfa SA |
205 | /** |
206 | * dwc2_hsotg_tx_fifo_total_depth - return total FIFO depth available for | |
207 | * device mode TX FIFOs | |
6fb914d7 GT |
208 | * |
209 | * @hsotg: Programming view of the DWC_otg controller | |
c138ecfa SA |
210 | */ |
211 | int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg) | |
212 | { | |
c138ecfa SA |
213 | int addr; |
214 | int tx_addr_max; | |
215 | u32 np_tx_fifo_size; | |
216 | ||
217 | np_tx_fifo_size = min_t(u32, hsotg->hw_params.dev_nperio_tx_fifo_size, | |
218 | hsotg->params.g_np_tx_fifo_size); | |
219 | ||
220 | /* Get Endpoint Info Control block size in DWORDs. */ | |
9273083a | 221 | tx_addr_max = hsotg->hw_params.total_fifo_size; |
c138ecfa SA |
222 | |
223 | addr = hsotg->params.g_rx_fifo_size + np_tx_fifo_size; | |
224 | if (tx_addr_max <= addr) | |
225 | return 0; | |
226 | ||
227 | return tx_addr_max - addr; | |
228 | } | |
229 | ||
230 | /** | |
231 | * dwc2_hsotg_tx_fifo_average_depth - returns average depth of device mode | |
232 | * TX FIFOs | |
6fb914d7 GT |
233 | * |
234 | * @hsotg: Programming view of the DWC_otg controller | |
c138ecfa SA |
235 | */ |
236 | int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg *hsotg) | |
237 | { | |
238 | int tx_fifo_count; | |
239 | int tx_fifo_depth; | |
240 | ||
241 | tx_fifo_depth = dwc2_hsotg_tx_fifo_total_depth(hsotg); | |
242 | ||
243 | tx_fifo_count = dwc2_hsotg_tx_fifo_count(hsotg); | |
244 | ||
245 | if (!tx_fifo_count) | |
246 | return tx_fifo_depth; | |
247 | else | |
248 | return tx_fifo_depth / tx_fifo_count; | |
249 | } | |
250 | ||
5b7d70c6 | 251 | /** |
1f91b4cc | 252 | * dwc2_hsotg_init_fifo - initialise non-periodic FIFOs |
5b7d70c6 BD |
253 | * @hsotg: The device instance. |
254 | */ | |
1f91b4cc | 255 | static void dwc2_hsotg_init_fifo(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 256 | { |
2317eacd | 257 | unsigned int ep; |
0f002d20 | 258 | unsigned int addr; |
1703a6d3 | 259 | int timeout; |
79d6b8c5 | 260 | |
0f002d20 | 261 | u32 val; |
05ee799f | 262 | u32 *txfsz = hsotg->params.g_tx_fifo_size; |
0f002d20 | 263 | |
7fcbc95c GH |
264 | /* Reset fifo map if not correctly cleared during previous session */ |
265 | WARN_ON(hsotg->fifo_map); | |
266 | hsotg->fifo_map = 0; | |
267 | ||
0a176279 | 268 | /* set RX/NPTX FIFO sizes */ |
05ee799f JY |
269 | dwc2_writel(hsotg->params.g_rx_fifo_size, hsotg->regs + GRXFSIZ); |
270 | dwc2_writel((hsotg->params.g_rx_fifo_size << FIFOSIZE_STARTADDR_SHIFT) | | |
271 | (hsotg->params.g_np_tx_fifo_size << FIFOSIZE_DEPTH_SHIFT), | |
272 | hsotg->regs + GNPTXFSIZ); | |
0f002d20 | 273 | |
8b9bc460 LM |
274 | /* |
275 | * arange all the rest of the TX FIFOs, as some versions of this | |
0f002d20 BD |
276 | * block have overlapping default addresses. This also ensures |
277 | * that if the settings have been changed, then they are set to | |
8b9bc460 LM |
278 | * known values. |
279 | */ | |
0f002d20 BD |
280 | |
281 | /* start at the end of the GNPTXFSIZ, rounded up */ | |
05ee799f | 282 | addr = hsotg->params.g_rx_fifo_size + hsotg->params.g_np_tx_fifo_size; |
0f002d20 | 283 | |
8b9bc460 | 284 | /* |
0a176279 | 285 | * Configure fifos sizes from provided configuration and assign |
b203d0a2 RB |
286 | * them to endpoints dynamically according to maxpacket size value of |
287 | * given endpoint. | |
8b9bc460 | 288 | */ |
2317eacd | 289 | for (ep = 1; ep < MAX_EPS_CHANNELS; ep++) { |
05ee799f | 290 | if (!txfsz[ep]) |
3fa95385 JY |
291 | continue; |
292 | val = addr; | |
05ee799f JY |
293 | val |= txfsz[ep] << FIFOSIZE_DEPTH_SHIFT; |
294 | WARN_ONCE(addr + txfsz[ep] > hsotg->fifo_mem, | |
3fa95385 | 295 | "insufficient fifo memory"); |
05ee799f | 296 | addr += txfsz[ep]; |
0f002d20 | 297 | |
2317eacd | 298 | dwc2_writel(val, hsotg->regs + DPTXFSIZN(ep)); |
05ee799f | 299 | val = dwc2_readl(hsotg->regs + DPTXFSIZN(ep)); |
0f002d20 | 300 | } |
1703a6d3 | 301 | |
f87c842f SA |
302 | dwc2_writel(hsotg->hw_params.total_fifo_size | |
303 | addr << GDFIFOCFG_EPINFOBASE_SHIFT, | |
304 | hsotg->regs + GDFIFOCFG); | |
8b9bc460 LM |
305 | /* |
306 | * according to p428 of the design guide, we need to ensure that | |
307 | * all fifos are flushed before continuing | |
308 | */ | |
1703a6d3 | 309 | |
95c8bc36 | 310 | dwc2_writel(GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH | |
47a1685f | 311 | GRSTCTL_RXFFLSH, hsotg->regs + GRSTCTL); |
1703a6d3 BD |
312 | |
313 | /* wait until the fifos are both flushed */ | |
314 | timeout = 100; | |
315 | while (1) { | |
95c8bc36 | 316 | val = dwc2_readl(hsotg->regs + GRSTCTL); |
1703a6d3 | 317 | |
47a1685f | 318 | if ((val & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH)) == 0) |
1703a6d3 BD |
319 | break; |
320 | ||
321 | if (--timeout == 0) { | |
322 | dev_err(hsotg->dev, | |
323 | "%s: timeout flushing fifos (GRSTCTL=%08x)\n", | |
324 | __func__, val); | |
48b20bcb | 325 | break; |
1703a6d3 BD |
326 | } |
327 | ||
328 | udelay(1); | |
329 | } | |
330 | ||
331 | dev_dbg(hsotg->dev, "FIFOs reset, timeout at %d\n", timeout); | |
5b7d70c6 BD |
332 | } |
333 | ||
334 | /** | |
6fb914d7 | 335 | * dwc2_hsotg_ep_alloc_request - allocate USB rerequest structure |
5b7d70c6 BD |
336 | * @ep: USB endpoint to allocate request for. |
337 | * @flags: Allocation flags | |
338 | * | |
339 | * Allocate a new USB request structure appropriate for the specified endpoint | |
340 | */ | |
1f91b4cc | 341 | static struct usb_request *dwc2_hsotg_ep_alloc_request(struct usb_ep *ep, |
9da51974 | 342 | gfp_t flags) |
5b7d70c6 | 343 | { |
1f91b4cc | 344 | struct dwc2_hsotg_req *req; |
5b7d70c6 | 345 | |
ec33efe2 | 346 | req = kzalloc(sizeof(*req), flags); |
5b7d70c6 BD |
347 | if (!req) |
348 | return NULL; | |
349 | ||
350 | INIT_LIST_HEAD(&req->queue); | |
351 | ||
5b7d70c6 BD |
352 | return &req->req; |
353 | } | |
354 | ||
355 | /** | |
356 | * is_ep_periodic - return true if the endpoint is in periodic mode. | |
357 | * @hs_ep: The endpoint to query. | |
358 | * | |
359 | * Returns true if the endpoint is in periodic mode, meaning it is being | |
360 | * used for an Interrupt or ISO transfer. | |
361 | */ | |
1f91b4cc | 362 | static inline int is_ep_periodic(struct dwc2_hsotg_ep *hs_ep) |
5b7d70c6 BD |
363 | { |
364 | return hs_ep->periodic; | |
365 | } | |
366 | ||
367 | /** | |
1f91b4cc | 368 | * dwc2_hsotg_unmap_dma - unmap the DMA memory being used for the request |
5b7d70c6 BD |
369 | * @hsotg: The device state. |
370 | * @hs_ep: The endpoint for the request | |
371 | * @hs_req: The request being processed. | |
372 | * | |
1f91b4cc | 373 | * This is the reverse of dwc2_hsotg_map_dma(), called for the completion |
5b7d70c6 | 374 | * of a request to ensure the buffer is ready for access by the caller. |
8b9bc460 | 375 | */ |
1f91b4cc | 376 | static void dwc2_hsotg_unmap_dma(struct dwc2_hsotg *hsotg, |
9da51974 | 377 | struct dwc2_hsotg_ep *hs_ep, |
1f91b4cc | 378 | struct dwc2_hsotg_req *hs_req) |
5b7d70c6 BD |
379 | { |
380 | struct usb_request *req = &hs_req->req; | |
9da51974 | 381 | |
17d966a3 | 382 | usb_gadget_unmap_request(&hsotg->gadget, req, hs_ep->dir_in); |
5b7d70c6 BD |
383 | } |
384 | ||
0f6b80c0 VA |
385 | /* |
386 | * dwc2_gadget_alloc_ctrl_desc_chains - allocate DMA descriptor chains | |
387 | * for Control endpoint | |
388 | * @hsotg: The device state. | |
389 | * | |
390 | * This function will allocate 4 descriptor chains for EP 0: 2 for | |
391 | * Setup stage, per one for IN and OUT data/status transactions. | |
392 | */ | |
393 | static int dwc2_gadget_alloc_ctrl_desc_chains(struct dwc2_hsotg *hsotg) | |
394 | { | |
395 | hsotg->setup_desc[0] = | |
396 | dmam_alloc_coherent(hsotg->dev, | |
397 | sizeof(struct dwc2_dma_desc), | |
398 | &hsotg->setup_desc_dma[0], | |
399 | GFP_KERNEL); | |
400 | if (!hsotg->setup_desc[0]) | |
401 | goto fail; | |
402 | ||
403 | hsotg->setup_desc[1] = | |
404 | dmam_alloc_coherent(hsotg->dev, | |
405 | sizeof(struct dwc2_dma_desc), | |
406 | &hsotg->setup_desc_dma[1], | |
407 | GFP_KERNEL); | |
408 | if (!hsotg->setup_desc[1]) | |
409 | goto fail; | |
410 | ||
411 | hsotg->ctrl_in_desc = | |
412 | dmam_alloc_coherent(hsotg->dev, | |
413 | sizeof(struct dwc2_dma_desc), | |
414 | &hsotg->ctrl_in_desc_dma, | |
415 | GFP_KERNEL); | |
416 | if (!hsotg->ctrl_in_desc) | |
417 | goto fail; | |
418 | ||
419 | hsotg->ctrl_out_desc = | |
420 | dmam_alloc_coherent(hsotg->dev, | |
421 | sizeof(struct dwc2_dma_desc), | |
422 | &hsotg->ctrl_out_desc_dma, | |
423 | GFP_KERNEL); | |
424 | if (!hsotg->ctrl_out_desc) | |
425 | goto fail; | |
426 | ||
427 | return 0; | |
428 | ||
429 | fail: | |
430 | return -ENOMEM; | |
431 | } | |
432 | ||
5b7d70c6 | 433 | /** |
1f91b4cc | 434 | * dwc2_hsotg_write_fifo - write packet Data to the TxFIFO |
5b7d70c6 BD |
435 | * @hsotg: The controller state. |
436 | * @hs_ep: The endpoint we're going to write for. | |
437 | * @hs_req: The request to write data for. | |
438 | * | |
439 | * This is called when the TxFIFO has some space in it to hold a new | |
440 | * transmission and we have something to give it. The actual setup of | |
441 | * the data size is done elsewhere, so all we have to do is to actually | |
442 | * write the data. | |
443 | * | |
444 | * The return value is zero if there is more space (or nothing was done) | |
445 | * otherwise -ENOSPC is returned if the FIFO space was used up. | |
446 | * | |
447 | * This routine is only needed for PIO | |
8b9bc460 | 448 | */ |
1f91b4cc | 449 | static int dwc2_hsotg_write_fifo(struct dwc2_hsotg *hsotg, |
9da51974 | 450 | struct dwc2_hsotg_ep *hs_ep, |
1f91b4cc | 451 | struct dwc2_hsotg_req *hs_req) |
5b7d70c6 BD |
452 | { |
453 | bool periodic = is_ep_periodic(hs_ep); | |
95c8bc36 | 454 | u32 gnptxsts = dwc2_readl(hsotg->regs + GNPTXSTS); |
5b7d70c6 BD |
455 | int buf_pos = hs_req->req.actual; |
456 | int to_write = hs_ep->size_loaded; | |
457 | void *data; | |
458 | int can_write; | |
459 | int pkt_round; | |
4fca54aa | 460 | int max_transfer; |
5b7d70c6 BD |
461 | |
462 | to_write -= (buf_pos - hs_ep->last_load); | |
463 | ||
464 | /* if there's nothing to write, get out early */ | |
465 | if (to_write == 0) | |
466 | return 0; | |
467 | ||
10aebc77 | 468 | if (periodic && !hsotg->dedicated_fifos) { |
95c8bc36 | 469 | u32 epsize = dwc2_readl(hsotg->regs + DIEPTSIZ(hs_ep->index)); |
5b7d70c6 BD |
470 | int size_left; |
471 | int size_done; | |
472 | ||
8b9bc460 LM |
473 | /* |
474 | * work out how much data was loaded so we can calculate | |
475 | * how much data is left in the fifo. | |
476 | */ | |
5b7d70c6 | 477 | |
47a1685f | 478 | size_left = DXEPTSIZ_XFERSIZE_GET(epsize); |
5b7d70c6 | 479 | |
8b9bc460 LM |
480 | /* |
481 | * if shared fifo, we cannot write anything until the | |
e7a9ff54 BD |
482 | * previous data has been completely sent. |
483 | */ | |
484 | if (hs_ep->fifo_load != 0) { | |
1f91b4cc | 485 | dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP); |
e7a9ff54 BD |
486 | return -ENOSPC; |
487 | } | |
488 | ||
5b7d70c6 BD |
489 | dev_dbg(hsotg->dev, "%s: left=%d, load=%d, fifo=%d, size %d\n", |
490 | __func__, size_left, | |
491 | hs_ep->size_loaded, hs_ep->fifo_load, hs_ep->fifo_size); | |
492 | ||
493 | /* how much of the data has moved */ | |
494 | size_done = hs_ep->size_loaded - size_left; | |
495 | ||
496 | /* how much data is left in the fifo */ | |
497 | can_write = hs_ep->fifo_load - size_done; | |
498 | dev_dbg(hsotg->dev, "%s: => can_write1=%d\n", | |
499 | __func__, can_write); | |
500 | ||
501 | can_write = hs_ep->fifo_size - can_write; | |
502 | dev_dbg(hsotg->dev, "%s: => can_write2=%d\n", | |
503 | __func__, can_write); | |
504 | ||
505 | if (can_write <= 0) { | |
1f91b4cc | 506 | dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP); |
5b7d70c6 BD |
507 | return -ENOSPC; |
508 | } | |
10aebc77 | 509 | } else if (hsotg->dedicated_fifos && hs_ep->index != 0) { |
ad674a15 RB |
510 | can_write = dwc2_readl(hsotg->regs + |
511 | DTXFSTS(hs_ep->fifo_index)); | |
10aebc77 BD |
512 | |
513 | can_write &= 0xffff; | |
514 | can_write *= 4; | |
5b7d70c6 | 515 | } else { |
47a1685f | 516 | if (GNPTXSTS_NP_TXQ_SPC_AVAIL_GET(gnptxsts) == 0) { |
5b7d70c6 BD |
517 | dev_dbg(hsotg->dev, |
518 | "%s: no queue slots available (0x%08x)\n", | |
519 | __func__, gnptxsts); | |
520 | ||
1f91b4cc | 521 | dwc2_hsotg_en_gsint(hsotg, GINTSTS_NPTXFEMP); |
5b7d70c6 BD |
522 | return -ENOSPC; |
523 | } | |
524 | ||
47a1685f | 525 | can_write = GNPTXSTS_NP_TXF_SPC_AVAIL_GET(gnptxsts); |
679f9b7c | 526 | can_write *= 4; /* fifo size is in 32bit quantities. */ |
5b7d70c6 BD |
527 | } |
528 | ||
4fca54aa RB |
529 | max_transfer = hs_ep->ep.maxpacket * hs_ep->mc; |
530 | ||
531 | dev_dbg(hsotg->dev, "%s: GNPTXSTS=%08x, can=%d, to=%d, max_transfer %d\n", | |
9da51974 | 532 | __func__, gnptxsts, can_write, to_write, max_transfer); |
5b7d70c6 | 533 | |
8b9bc460 LM |
534 | /* |
535 | * limit to 512 bytes of data, it seems at least on the non-periodic | |
5b7d70c6 BD |
536 | * FIFO, requests of >512 cause the endpoint to get stuck with a |
537 | * fragment of the end of the transfer in it. | |
538 | */ | |
811f3303 | 539 | if (can_write > 512 && !periodic) |
5b7d70c6 BD |
540 | can_write = 512; |
541 | ||
8b9bc460 LM |
542 | /* |
543 | * limit the write to one max-packet size worth of data, but allow | |
03e10e5a | 544 | * the transfer to return that it did not run out of fifo space |
8b9bc460 LM |
545 | * doing it. |
546 | */ | |
4fca54aa RB |
547 | if (to_write > max_transfer) { |
548 | to_write = max_transfer; | |
03e10e5a | 549 | |
5cb2ff0c RB |
550 | /* it's needed only when we do not use dedicated fifos */ |
551 | if (!hsotg->dedicated_fifos) | |
1f91b4cc | 552 | dwc2_hsotg_en_gsint(hsotg, |
9da51974 | 553 | periodic ? GINTSTS_PTXFEMP : |
47a1685f | 554 | GINTSTS_NPTXFEMP); |
03e10e5a BD |
555 | } |
556 | ||
5b7d70c6 BD |
557 | /* see if we can write data */ |
558 | ||
559 | if (to_write > can_write) { | |
560 | to_write = can_write; | |
4fca54aa | 561 | pkt_round = to_write % max_transfer; |
5b7d70c6 | 562 | |
8b9bc460 LM |
563 | /* |
564 | * Round the write down to an | |
5b7d70c6 BD |
565 | * exact number of packets. |
566 | * | |
567 | * Note, we do not currently check to see if we can ever | |
568 | * write a full packet or not to the FIFO. | |
569 | */ | |
570 | ||
571 | if (pkt_round) | |
572 | to_write -= pkt_round; | |
573 | ||
8b9bc460 LM |
574 | /* |
575 | * enable correct FIFO interrupt to alert us when there | |
576 | * is more room left. | |
577 | */ | |
5b7d70c6 | 578 | |
5cb2ff0c RB |
579 | /* it's needed only when we do not use dedicated fifos */ |
580 | if (!hsotg->dedicated_fifos) | |
1f91b4cc | 581 | dwc2_hsotg_en_gsint(hsotg, |
9da51974 | 582 | periodic ? GINTSTS_PTXFEMP : |
47a1685f | 583 | GINTSTS_NPTXFEMP); |
5b7d70c6 BD |
584 | } |
585 | ||
586 | dev_dbg(hsotg->dev, "write %d/%d, can_write %d, done %d\n", | |
9da51974 | 587 | to_write, hs_req->req.length, can_write, buf_pos); |
5b7d70c6 BD |
588 | |
589 | if (to_write <= 0) | |
590 | return -ENOSPC; | |
591 | ||
592 | hs_req->req.actual = buf_pos + to_write; | |
593 | hs_ep->total_data += to_write; | |
594 | ||
595 | if (periodic) | |
596 | hs_ep->fifo_load += to_write; | |
597 | ||
598 | to_write = DIV_ROUND_UP(to_write, 4); | |
599 | data = hs_req->req.buf + buf_pos; | |
600 | ||
1a7ed5be | 601 | iowrite32_rep(hsotg->regs + EPFIFO(hs_ep->index), data, to_write); |
5b7d70c6 BD |
602 | |
603 | return (to_write >= can_write) ? -ENOSPC : 0; | |
604 | } | |
605 | ||
606 | /** | |
607 | * get_ep_limit - get the maximum data legnth for this endpoint | |
608 | * @hs_ep: The endpoint | |
609 | * | |
610 | * Return the maximum data that can be queued in one go on a given endpoint | |
611 | * so that transfers that are too long can be split. | |
612 | */ | |
9da51974 | 613 | static unsigned int get_ep_limit(struct dwc2_hsotg_ep *hs_ep) |
5b7d70c6 BD |
614 | { |
615 | int index = hs_ep->index; | |
9da51974 JY |
616 | unsigned int maxsize; |
617 | unsigned int maxpkt; | |
5b7d70c6 BD |
618 | |
619 | if (index != 0) { | |
47a1685f DN |
620 | maxsize = DXEPTSIZ_XFERSIZE_LIMIT + 1; |
621 | maxpkt = DXEPTSIZ_PKTCNT_LIMIT + 1; | |
5b7d70c6 | 622 | } else { |
9da51974 | 623 | maxsize = 64 + 64; |
66e5c643 | 624 | if (hs_ep->dir_in) |
47a1685f | 625 | maxpkt = DIEPTSIZ0_PKTCNT_LIMIT + 1; |
66e5c643 | 626 | else |
5b7d70c6 | 627 | maxpkt = 2; |
5b7d70c6 BD |
628 | } |
629 | ||
630 | /* we made the constant loading easier above by using +1 */ | |
631 | maxpkt--; | |
632 | maxsize--; | |
633 | ||
8b9bc460 LM |
634 | /* |
635 | * constrain by packet count if maxpkts*pktsize is greater | |
636 | * than the length register size. | |
637 | */ | |
5b7d70c6 BD |
638 | |
639 | if ((maxpkt * hs_ep->ep.maxpacket) < maxsize) | |
640 | maxsize = maxpkt * hs_ep->ep.maxpacket; | |
641 | ||
642 | return maxsize; | |
643 | } | |
644 | ||
381fc8f8 | 645 | /** |
38beaec6 JY |
646 | * dwc2_hsotg_read_frameno - read current frame number |
647 | * @hsotg: The device instance | |
648 | * | |
649 | * Return the current frame number | |
650 | */ | |
381fc8f8 VM |
651 | static u32 dwc2_hsotg_read_frameno(struct dwc2_hsotg *hsotg) |
652 | { | |
653 | u32 dsts; | |
654 | ||
655 | dsts = dwc2_readl(hsotg->regs + DSTS); | |
656 | dsts &= DSTS_SOFFN_MASK; | |
657 | dsts >>= DSTS_SOFFN_SHIFT; | |
658 | ||
659 | return dsts; | |
660 | } | |
661 | ||
cf77b5fb VA |
662 | /** |
663 | * dwc2_gadget_get_chain_limit - get the maximum data payload value of the | |
664 | * DMA descriptor chain prepared for specific endpoint | |
665 | * @hs_ep: The endpoint | |
666 | * | |
667 | * Return the maximum data that can be queued in one go on a given endpoint | |
668 | * depending on its descriptor chain capacity so that transfers that | |
669 | * are too long can be split. | |
670 | */ | |
671 | static unsigned int dwc2_gadget_get_chain_limit(struct dwc2_hsotg_ep *hs_ep) | |
672 | { | |
673 | int is_isoc = hs_ep->isochronous; | |
674 | unsigned int maxsize; | |
675 | ||
676 | if (is_isoc) | |
677 | maxsize = hs_ep->dir_in ? DEV_DMA_ISOC_TX_NBYTES_LIMIT : | |
678 | DEV_DMA_ISOC_RX_NBYTES_LIMIT; | |
679 | else | |
680 | maxsize = DEV_DMA_NBYTES_LIMIT; | |
681 | ||
682 | /* Above size of one descriptor was chosen, multiple it */ | |
683 | maxsize *= MAX_DMA_DESC_NUM_GENERIC; | |
684 | ||
685 | return maxsize; | |
686 | } | |
687 | ||
e02f9aa6 VA |
688 | /* |
689 | * dwc2_gadget_get_desc_params - get DMA descriptor parameters. | |
690 | * @hs_ep: The endpoint | |
691 | * @mask: RX/TX bytes mask to be defined | |
692 | * | |
693 | * Returns maximum data payload for one descriptor after analyzing endpoint | |
694 | * characteristics. | |
695 | * DMA descriptor transfer bytes limit depends on EP type: | |
696 | * Control out - MPS, | |
697 | * Isochronous - descriptor rx/tx bytes bitfield limit, | |
698 | * Control In/Bulk/Interrupt - multiple of mps. This will allow to not | |
699 | * have concatenations from various descriptors within one packet. | |
700 | * | |
701 | * Selects corresponding mask for RX/TX bytes as well. | |
702 | */ | |
703 | static u32 dwc2_gadget_get_desc_params(struct dwc2_hsotg_ep *hs_ep, u32 *mask) | |
704 | { | |
705 | u32 mps = hs_ep->ep.maxpacket; | |
706 | int dir_in = hs_ep->dir_in; | |
707 | u32 desc_size = 0; | |
708 | ||
709 | if (!hs_ep->index && !dir_in) { | |
710 | desc_size = mps; | |
711 | *mask = DEV_DMA_NBYTES_MASK; | |
712 | } else if (hs_ep->isochronous) { | |
713 | if (dir_in) { | |
714 | desc_size = DEV_DMA_ISOC_TX_NBYTES_LIMIT; | |
715 | *mask = DEV_DMA_ISOC_TX_NBYTES_MASK; | |
716 | } else { | |
717 | desc_size = DEV_DMA_ISOC_RX_NBYTES_LIMIT; | |
718 | *mask = DEV_DMA_ISOC_RX_NBYTES_MASK; | |
719 | } | |
720 | } else { | |
721 | desc_size = DEV_DMA_NBYTES_LIMIT; | |
722 | *mask = DEV_DMA_NBYTES_MASK; | |
723 | ||
724 | /* Round down desc_size to be mps multiple */ | |
725 | desc_size -= desc_size % mps; | |
726 | } | |
727 | ||
728 | return desc_size; | |
729 | } | |
730 | ||
731 | /* | |
732 | * dwc2_gadget_config_nonisoc_xfer_ddma - prepare non ISOC DMA desc chain. | |
733 | * @hs_ep: The endpoint | |
734 | * @dma_buff: DMA address to use | |
735 | * @len: Length of the transfer | |
736 | * | |
737 | * This function will iterate over descriptor chain and fill its entries | |
738 | * with corresponding information based on transfer data. | |
739 | */ | |
740 | static void dwc2_gadget_config_nonisoc_xfer_ddma(struct dwc2_hsotg_ep *hs_ep, | |
741 | dma_addr_t dma_buff, | |
742 | unsigned int len) | |
743 | { | |
744 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
745 | int dir_in = hs_ep->dir_in; | |
746 | struct dwc2_dma_desc *desc = hs_ep->desc_list; | |
747 | u32 mps = hs_ep->ep.maxpacket; | |
748 | u32 maxsize = 0; | |
749 | u32 offset = 0; | |
750 | u32 mask = 0; | |
751 | int i; | |
752 | ||
753 | maxsize = dwc2_gadget_get_desc_params(hs_ep, &mask); | |
754 | ||
755 | hs_ep->desc_count = (len / maxsize) + | |
756 | ((len % maxsize) ? 1 : 0); | |
757 | if (len == 0) | |
758 | hs_ep->desc_count = 1; | |
759 | ||
760 | for (i = 0; i < hs_ep->desc_count; ++i) { | |
761 | desc->status = 0; | |
762 | desc->status |= (DEV_DMA_BUFF_STS_HBUSY | |
763 | << DEV_DMA_BUFF_STS_SHIFT); | |
764 | ||
765 | if (len > maxsize) { | |
766 | if (!hs_ep->index && !dir_in) | |
767 | desc->status |= (DEV_DMA_L | DEV_DMA_IOC); | |
768 | ||
769 | desc->status |= (maxsize << | |
770 | DEV_DMA_NBYTES_SHIFT & mask); | |
771 | desc->buf = dma_buff + offset; | |
772 | ||
773 | len -= maxsize; | |
774 | offset += maxsize; | |
775 | } else { | |
776 | desc->status |= (DEV_DMA_L | DEV_DMA_IOC); | |
777 | ||
778 | if (dir_in) | |
779 | desc->status |= (len % mps) ? DEV_DMA_SHORT : | |
780 | ((hs_ep->send_zlp) ? DEV_DMA_SHORT : 0); | |
781 | if (len > maxsize) | |
782 | dev_err(hsotg->dev, "wrong len %d\n", len); | |
783 | ||
784 | desc->status |= | |
785 | len << DEV_DMA_NBYTES_SHIFT & mask; | |
786 | desc->buf = dma_buff + offset; | |
787 | } | |
788 | ||
789 | desc->status &= ~DEV_DMA_BUFF_STS_MASK; | |
790 | desc->status |= (DEV_DMA_BUFF_STS_HREADY | |
791 | << DEV_DMA_BUFF_STS_SHIFT); | |
792 | desc++; | |
793 | } | |
794 | } | |
795 | ||
540ccba0 VA |
796 | /* |
797 | * dwc2_gadget_fill_isoc_desc - fills next isochronous descriptor in chain. | |
798 | * @hs_ep: The isochronous endpoint. | |
799 | * @dma_buff: usb requests dma buffer. | |
800 | * @len: usb request transfer length. | |
801 | * | |
729cac69 | 802 | * Fills next free descriptor with the data of the arrived usb request, |
540ccba0 VA |
803 | * frame info, sets Last and IOC bits increments next_desc. If filled |
804 | * descriptor is not the first one, removes L bit from the previous descriptor | |
805 | * status. | |
806 | */ | |
807 | static int dwc2_gadget_fill_isoc_desc(struct dwc2_hsotg_ep *hs_ep, | |
808 | dma_addr_t dma_buff, unsigned int len) | |
809 | { | |
810 | struct dwc2_dma_desc *desc; | |
811 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
812 | u32 index; | |
813 | u32 maxsize = 0; | |
814 | u32 mask = 0; | |
1d8e5c00 | 815 | u8 pid = 0; |
540ccba0 VA |
816 | |
817 | maxsize = dwc2_gadget_get_desc_params(hs_ep, &mask); | |
540ccba0 | 818 | |
729cac69 MH |
819 | index = hs_ep->next_desc; |
820 | desc = &hs_ep->desc_list[index]; | |
540ccba0 | 821 | |
729cac69 MH |
822 | /* Check if descriptor chain full */ |
823 | if ((desc->status >> DEV_DMA_BUFF_STS_SHIFT) == | |
824 | DEV_DMA_BUFF_STS_HREADY) { | |
825 | dev_dbg(hsotg->dev, "%s: desc chain full\n", __func__); | |
826 | return 1; | |
540ccba0 VA |
827 | } |
828 | ||
540ccba0 VA |
829 | /* Clear L bit of previous desc if more than one entries in the chain */ |
830 | if (hs_ep->next_desc) | |
831 | hs_ep->desc_list[index - 1].status &= ~DEV_DMA_L; | |
832 | ||
833 | dev_dbg(hsotg->dev, "%s: Filling ep %d, dir %s isoc desc # %d\n", | |
834 | __func__, hs_ep->index, hs_ep->dir_in ? "in" : "out", index); | |
835 | ||
836 | desc->status = 0; | |
837 | desc->status |= (DEV_DMA_BUFF_STS_HBUSY << DEV_DMA_BUFF_STS_SHIFT); | |
838 | ||
839 | desc->buf = dma_buff; | |
840 | desc->status |= (DEV_DMA_L | DEV_DMA_IOC | | |
841 | ((len << DEV_DMA_NBYTES_SHIFT) & mask)); | |
842 | ||
843 | if (hs_ep->dir_in) { | |
1d8e5c00 MH |
844 | if (len) |
845 | pid = DIV_ROUND_UP(len, hs_ep->ep.maxpacket); | |
846 | else | |
847 | pid = 1; | |
848 | desc->status |= ((pid << DEV_DMA_ISOC_PID_SHIFT) & | |
540ccba0 VA |
849 | DEV_DMA_ISOC_PID_MASK) | |
850 | ((len % hs_ep->ep.maxpacket) ? | |
851 | DEV_DMA_SHORT : 0) | | |
852 | ((hs_ep->target_frame << | |
853 | DEV_DMA_ISOC_FRNUM_SHIFT) & | |
854 | DEV_DMA_ISOC_FRNUM_MASK); | |
855 | } | |
856 | ||
857 | desc->status &= ~DEV_DMA_BUFF_STS_MASK; | |
858 | desc->status |= (DEV_DMA_BUFF_STS_HREADY << DEV_DMA_BUFF_STS_SHIFT); | |
859 | ||
729cac69 MH |
860 | /* Increment frame number by interval for IN */ |
861 | if (hs_ep->dir_in) | |
862 | dwc2_gadget_incr_frame_num(hs_ep); | |
863 | ||
540ccba0 VA |
864 | /* Update index of last configured entry in the chain */ |
865 | hs_ep->next_desc++; | |
729cac69 MH |
866 | if (hs_ep->next_desc >= MAX_DMA_DESC_NUM_GENERIC) |
867 | hs_ep->next_desc = 0; | |
540ccba0 VA |
868 | |
869 | return 0; | |
870 | } | |
871 | ||
872 | /* | |
873 | * dwc2_gadget_start_isoc_ddma - start isochronous transfer in DDMA | |
874 | * @hs_ep: The isochronous endpoint. | |
875 | * | |
729cac69 | 876 | * Prepare descriptor chain for isochronous endpoints. Afterwards |
540ccba0 | 877 | * write DMA address to HW and enable the endpoint. |
540ccba0 VA |
878 | */ |
879 | static void dwc2_gadget_start_isoc_ddma(struct dwc2_hsotg_ep *hs_ep) | |
880 | { | |
881 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
882 | struct dwc2_hsotg_req *hs_req, *treq; | |
883 | int index = hs_ep->index; | |
884 | int ret; | |
729cac69 | 885 | int i; |
540ccba0 VA |
886 | u32 dma_reg; |
887 | u32 depctl; | |
888 | u32 ctrl; | |
729cac69 | 889 | struct dwc2_dma_desc *desc; |
540ccba0 VA |
890 | |
891 | if (list_empty(&hs_ep->queue)) { | |
1ffba905 | 892 | hs_ep->target_frame = TARGET_FRAME_INITIAL; |
540ccba0 VA |
893 | dev_dbg(hsotg->dev, "%s: No requests in queue\n", __func__); |
894 | return; | |
895 | } | |
896 | ||
729cac69 MH |
897 | /* Initialize descriptor chain by Host Busy status */ |
898 | for (i = 0; i < MAX_DMA_DESC_NUM_GENERIC; i++) { | |
899 | desc = &hs_ep->desc_list[i]; | |
900 | desc->status = 0; | |
901 | desc->status |= (DEV_DMA_BUFF_STS_HBUSY | |
902 | << DEV_DMA_BUFF_STS_SHIFT); | |
903 | } | |
904 | ||
905 | hs_ep->next_desc = 0; | |
540ccba0 VA |
906 | list_for_each_entry_safe(hs_req, treq, &hs_ep->queue, queue) { |
907 | ret = dwc2_gadget_fill_isoc_desc(hs_ep, hs_req->req.dma, | |
908 | hs_req->req.length); | |
729cac69 | 909 | if (ret) |
540ccba0 | 910 | break; |
540ccba0 VA |
911 | } |
912 | ||
729cac69 | 913 | hs_ep->compl_desc = 0; |
540ccba0 VA |
914 | depctl = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index); |
915 | dma_reg = hs_ep->dir_in ? DIEPDMA(index) : DOEPDMA(index); | |
916 | ||
917 | /* write descriptor chain address to control register */ | |
918 | dwc2_writel(hs_ep->desc_list_dma, hsotg->regs + dma_reg); | |
919 | ||
920 | ctrl = dwc2_readl(hsotg->regs + depctl); | |
921 | ctrl |= DXEPCTL_EPENA | DXEPCTL_CNAK; | |
922 | dwc2_writel(ctrl, hsotg->regs + depctl); | |
540ccba0 VA |
923 | } |
924 | ||
5b7d70c6 | 925 | /** |
1f91b4cc | 926 | * dwc2_hsotg_start_req - start a USB request from an endpoint's queue |
5b7d70c6 BD |
927 | * @hsotg: The controller state. |
928 | * @hs_ep: The endpoint to process a request for | |
929 | * @hs_req: The request to start. | |
930 | * @continuing: True if we are doing more for the current request. | |
931 | * | |
932 | * Start the given request running by setting the endpoint registers | |
933 | * appropriately, and writing any data to the FIFOs. | |
934 | */ | |
1f91b4cc | 935 | static void dwc2_hsotg_start_req(struct dwc2_hsotg *hsotg, |
9da51974 | 936 | struct dwc2_hsotg_ep *hs_ep, |
1f91b4cc | 937 | struct dwc2_hsotg_req *hs_req, |
5b7d70c6 BD |
938 | bool continuing) |
939 | { | |
940 | struct usb_request *ureq = &hs_req->req; | |
941 | int index = hs_ep->index; | |
942 | int dir_in = hs_ep->dir_in; | |
943 | u32 epctrl_reg; | |
944 | u32 epsize_reg; | |
945 | u32 epsize; | |
946 | u32 ctrl; | |
9da51974 JY |
947 | unsigned int length; |
948 | unsigned int packets; | |
949 | unsigned int maxreq; | |
aa3e8bc8 | 950 | unsigned int dma_reg; |
5b7d70c6 BD |
951 | |
952 | if (index != 0) { | |
953 | if (hs_ep->req && !continuing) { | |
954 | dev_err(hsotg->dev, "%s: active request\n", __func__); | |
955 | WARN_ON(1); | |
956 | return; | |
957 | } else if (hs_ep->req != hs_req && continuing) { | |
958 | dev_err(hsotg->dev, | |
959 | "%s: continue different req\n", __func__); | |
960 | WARN_ON(1); | |
961 | return; | |
962 | } | |
963 | } | |
964 | ||
aa3e8bc8 | 965 | dma_reg = dir_in ? DIEPDMA(index) : DOEPDMA(index); |
94cb8fd6 LM |
966 | epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index); |
967 | epsize_reg = dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index); | |
5b7d70c6 BD |
968 | |
969 | dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n", | |
95c8bc36 | 970 | __func__, dwc2_readl(hsotg->regs + epctrl_reg), index, |
5b7d70c6 BD |
971 | hs_ep->dir_in ? "in" : "out"); |
972 | ||
9c39ddc6 | 973 | /* If endpoint is stalled, we will restart request later */ |
95c8bc36 | 974 | ctrl = dwc2_readl(hsotg->regs + epctrl_reg); |
9c39ddc6 | 975 | |
b2d4c54e | 976 | if (index && ctrl & DXEPCTL_STALL) { |
9c39ddc6 AT |
977 | dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index); |
978 | return; | |
979 | } | |
980 | ||
5b7d70c6 | 981 | length = ureq->length - ureq->actual; |
71225bee LM |
982 | dev_dbg(hsotg->dev, "ureq->length:%d ureq->actual:%d\n", |
983 | ureq->length, ureq->actual); | |
5b7d70c6 | 984 | |
cf77b5fb VA |
985 | if (!using_desc_dma(hsotg)) |
986 | maxreq = get_ep_limit(hs_ep); | |
987 | else | |
988 | maxreq = dwc2_gadget_get_chain_limit(hs_ep); | |
989 | ||
5b7d70c6 BD |
990 | if (length > maxreq) { |
991 | int round = maxreq % hs_ep->ep.maxpacket; | |
992 | ||
993 | dev_dbg(hsotg->dev, "%s: length %d, max-req %d, r %d\n", | |
994 | __func__, length, maxreq, round); | |
995 | ||
996 | /* round down to multiple of packets */ | |
997 | if (round) | |
998 | maxreq -= round; | |
999 | ||
1000 | length = maxreq; | |
1001 | } | |
1002 | ||
1003 | if (length) | |
1004 | packets = DIV_ROUND_UP(length, hs_ep->ep.maxpacket); | |
1005 | else | |
1006 | packets = 1; /* send one packet if length is zero. */ | |
1007 | ||
4fca54aa RB |
1008 | if (hs_ep->isochronous && length > (hs_ep->mc * hs_ep->ep.maxpacket)) { |
1009 | dev_err(hsotg->dev, "req length > maxpacket*mc\n"); | |
1010 | return; | |
1011 | } | |
1012 | ||
5b7d70c6 | 1013 | if (dir_in && index != 0) |
4fca54aa | 1014 | if (hs_ep->isochronous) |
47a1685f | 1015 | epsize = DXEPTSIZ_MC(packets); |
4fca54aa | 1016 | else |
47a1685f | 1017 | epsize = DXEPTSIZ_MC(1); |
5b7d70c6 BD |
1018 | else |
1019 | epsize = 0; | |
1020 | ||
f71b5e25 MYK |
1021 | /* |
1022 | * zero length packet should be programmed on its own and should not | |
1023 | * be counted in DIEPTSIZ.PktCnt with other packets. | |
1024 | */ | |
1025 | if (dir_in && ureq->zero && !continuing) { | |
1026 | /* Test if zlp is actually required. */ | |
1027 | if ((ureq->length >= hs_ep->ep.maxpacket) && | |
9da51974 | 1028 | !(ureq->length % hs_ep->ep.maxpacket)) |
8a20fa45 | 1029 | hs_ep->send_zlp = 1; |
5b7d70c6 BD |
1030 | } |
1031 | ||
47a1685f DN |
1032 | epsize |= DXEPTSIZ_PKTCNT(packets); |
1033 | epsize |= DXEPTSIZ_XFERSIZE(length); | |
5b7d70c6 BD |
1034 | |
1035 | dev_dbg(hsotg->dev, "%s: %d@%d/%d, 0x%08x => 0x%08x\n", | |
1036 | __func__, packets, length, ureq->length, epsize, epsize_reg); | |
1037 | ||
1038 | /* store the request as the current one we're doing */ | |
1039 | hs_ep->req = hs_req; | |
1040 | ||
aa3e8bc8 VA |
1041 | if (using_desc_dma(hsotg)) { |
1042 | u32 offset = 0; | |
1043 | u32 mps = hs_ep->ep.maxpacket; | |
1044 | ||
1045 | /* Adjust length: EP0 - MPS, other OUT EPs - multiple of MPS */ | |
1046 | if (!dir_in) { | |
1047 | if (!index) | |
1048 | length = mps; | |
1049 | else if (length % mps) | |
1050 | length += (mps - (length % mps)); | |
1051 | } | |
5b7d70c6 | 1052 | |
8b9bc460 | 1053 | /* |
aa3e8bc8 VA |
1054 | * If more data to send, adjust DMA for EP0 out data stage. |
1055 | * ureq->dma stays unchanged, hence increment it by already | |
1056 | * passed passed data count before starting new transaction. | |
8b9bc460 | 1057 | */ |
aa3e8bc8 VA |
1058 | if (!index && hsotg->ep0_state == DWC2_EP0_DATA_OUT && |
1059 | continuing) | |
1060 | offset = ureq->actual; | |
1061 | ||
1062 | /* Fill DDMA chain entries */ | |
1063 | dwc2_gadget_config_nonisoc_xfer_ddma(hs_ep, ureq->dma + offset, | |
1064 | length); | |
1065 | ||
1066 | /* write descriptor chain address to control register */ | |
1067 | dwc2_writel(hs_ep->desc_list_dma, hsotg->regs + dma_reg); | |
5b7d70c6 | 1068 | |
aa3e8bc8 VA |
1069 | dev_dbg(hsotg->dev, "%s: %08x pad => 0x%08x\n", |
1070 | __func__, (u32)hs_ep->desc_list_dma, dma_reg); | |
1071 | } else { | |
1072 | /* write size / packets */ | |
1073 | dwc2_writel(epsize, hsotg->regs + epsize_reg); | |
1074 | ||
729e6574 | 1075 | if (using_dma(hsotg) && !continuing && (length != 0)) { |
aa3e8bc8 VA |
1076 | /* |
1077 | * write DMA address to control register, buffer | |
1078 | * already synced by dwc2_hsotg_ep_queue(). | |
1079 | */ | |
5b7d70c6 | 1080 | |
aa3e8bc8 VA |
1081 | dwc2_writel(ureq->dma, hsotg->regs + dma_reg); |
1082 | ||
1083 | dev_dbg(hsotg->dev, "%s: %pad => 0x%08x\n", | |
1084 | __func__, &ureq->dma, dma_reg); | |
1085 | } | |
5b7d70c6 BD |
1086 | } |
1087 | ||
837e9f00 VM |
1088 | if (hs_ep->isochronous && hs_ep->interval == 1) { |
1089 | hs_ep->target_frame = dwc2_hsotg_read_frameno(hsotg); | |
1090 | dwc2_gadget_incr_frame_num(hs_ep); | |
1091 | ||
1092 | if (hs_ep->target_frame & 0x1) | |
1093 | ctrl |= DXEPCTL_SETODDFR; | |
1094 | else | |
1095 | ctrl |= DXEPCTL_SETEVENFR; | |
1096 | } | |
1097 | ||
47a1685f | 1098 | ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */ |
71225bee | 1099 | |
fe0b94ab | 1100 | dev_dbg(hsotg->dev, "ep0 state:%d\n", hsotg->ep0_state); |
71225bee LM |
1101 | |
1102 | /* For Setup request do not clear NAK */ | |
fe0b94ab | 1103 | if (!(index == 0 && hsotg->ep0_state == DWC2_EP0_SETUP)) |
47a1685f | 1104 | ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */ |
71225bee | 1105 | |
5b7d70c6 | 1106 | dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl); |
95c8bc36 | 1107 | dwc2_writel(ctrl, hsotg->regs + epctrl_reg); |
5b7d70c6 | 1108 | |
8b9bc460 LM |
1109 | /* |
1110 | * set these, it seems that DMA support increments past the end | |
5b7d70c6 | 1111 | * of the packet buffer so we need to calculate the length from |
8b9bc460 LM |
1112 | * this information. |
1113 | */ | |
5b7d70c6 BD |
1114 | hs_ep->size_loaded = length; |
1115 | hs_ep->last_load = ureq->actual; | |
1116 | ||
1117 | if (dir_in && !using_dma(hsotg)) { | |
1118 | /* set these anyway, we may need them for non-periodic in */ | |
1119 | hs_ep->fifo_load = 0; | |
1120 | ||
1f91b4cc | 1121 | dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req); |
5b7d70c6 BD |
1122 | } |
1123 | ||
8b9bc460 LM |
1124 | /* |
1125 | * Note, trying to clear the NAK here causes problems with transmit | |
1126 | * on the S3C6400 ending up with the TXFIFO becoming full. | |
1127 | */ | |
5b7d70c6 BD |
1128 | |
1129 | /* check ep is enabled */ | |
95c8bc36 | 1130 | if (!(dwc2_readl(hsotg->regs + epctrl_reg) & DXEPCTL_EPENA)) |
1a0ed863 | 1131 | dev_dbg(hsotg->dev, |
9da51974 | 1132 | "ep%d: failed to become enabled (DXEPCTL=0x%08x)?\n", |
95c8bc36 | 1133 | index, dwc2_readl(hsotg->regs + epctrl_reg)); |
5b7d70c6 | 1134 | |
47a1685f | 1135 | dev_dbg(hsotg->dev, "%s: DXEPCTL=0x%08x\n", |
95c8bc36 | 1136 | __func__, dwc2_readl(hsotg->regs + epctrl_reg)); |
afcf4169 RB |
1137 | |
1138 | /* enable ep interrupts */ | |
1f91b4cc | 1139 | dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 1); |
5b7d70c6 BD |
1140 | } |
1141 | ||
1142 | /** | |
1f91b4cc | 1143 | * dwc2_hsotg_map_dma - map the DMA memory being used for the request |
5b7d70c6 BD |
1144 | * @hsotg: The device state. |
1145 | * @hs_ep: The endpoint the request is on. | |
1146 | * @req: The request being processed. | |
1147 | * | |
1148 | * We've been asked to queue a request, so ensure that the memory buffer | |
1149 | * is correctly setup for DMA. If we've been passed an extant DMA address | |
1150 | * then ensure the buffer has been synced to memory. If our buffer has no | |
1151 | * DMA memory, then we map the memory and mark our request to allow us to | |
1152 | * cleanup on completion. | |
8b9bc460 | 1153 | */ |
1f91b4cc | 1154 | static int dwc2_hsotg_map_dma(struct dwc2_hsotg *hsotg, |
9da51974 | 1155 | struct dwc2_hsotg_ep *hs_ep, |
5b7d70c6 BD |
1156 | struct usb_request *req) |
1157 | { | |
e58ebcd1 | 1158 | int ret; |
5b7d70c6 | 1159 | |
e58ebcd1 FB |
1160 | ret = usb_gadget_map_request(&hsotg->gadget, req, hs_ep->dir_in); |
1161 | if (ret) | |
1162 | goto dma_error; | |
5b7d70c6 BD |
1163 | |
1164 | return 0; | |
1165 | ||
1166 | dma_error: | |
1167 | dev_err(hsotg->dev, "%s: failed to map buffer %p, %d bytes\n", | |
1168 | __func__, req->buf, req->length); | |
1169 | ||
1170 | return -EIO; | |
1171 | } | |
1172 | ||
1f91b4cc | 1173 | static int dwc2_hsotg_handle_unaligned_buf_start(struct dwc2_hsotg *hsotg, |
b98866c2 JY |
1174 | struct dwc2_hsotg_ep *hs_ep, |
1175 | struct dwc2_hsotg_req *hs_req) | |
7d24c1b5 MYK |
1176 | { |
1177 | void *req_buf = hs_req->req.buf; | |
1178 | ||
1179 | /* If dma is not being used or buffer is aligned */ | |
1180 | if (!using_dma(hsotg) || !((long)req_buf & 3)) | |
1181 | return 0; | |
1182 | ||
1183 | WARN_ON(hs_req->saved_req_buf); | |
1184 | ||
1185 | dev_dbg(hsotg->dev, "%s: %s: buf=%p length=%d\n", __func__, | |
9da51974 | 1186 | hs_ep->ep.name, req_buf, hs_req->req.length); |
7d24c1b5 MYK |
1187 | |
1188 | hs_req->req.buf = kmalloc(hs_req->req.length, GFP_ATOMIC); | |
1189 | if (!hs_req->req.buf) { | |
1190 | hs_req->req.buf = req_buf; | |
1191 | dev_err(hsotg->dev, | |
1192 | "%s: unable to allocate memory for bounce buffer\n", | |
1193 | __func__); | |
1194 | return -ENOMEM; | |
1195 | } | |
1196 | ||
1197 | /* Save actual buffer */ | |
1198 | hs_req->saved_req_buf = req_buf; | |
1199 | ||
1200 | if (hs_ep->dir_in) | |
1201 | memcpy(hs_req->req.buf, req_buf, hs_req->req.length); | |
1202 | return 0; | |
1203 | } | |
1204 | ||
b98866c2 JY |
1205 | static void |
1206 | dwc2_hsotg_handle_unaligned_buf_complete(struct dwc2_hsotg *hsotg, | |
1207 | struct dwc2_hsotg_ep *hs_ep, | |
1208 | struct dwc2_hsotg_req *hs_req) | |
7d24c1b5 MYK |
1209 | { |
1210 | /* If dma is not being used or buffer was aligned */ | |
1211 | if (!using_dma(hsotg) || !hs_req->saved_req_buf) | |
1212 | return; | |
1213 | ||
1214 | dev_dbg(hsotg->dev, "%s: %s: status=%d actual-length=%d\n", __func__, | |
1215 | hs_ep->ep.name, hs_req->req.status, hs_req->req.actual); | |
1216 | ||
1217 | /* Copy data from bounce buffer on successful out transfer */ | |
1218 | if (!hs_ep->dir_in && !hs_req->req.status) | |
1219 | memcpy(hs_req->saved_req_buf, hs_req->req.buf, | |
9da51974 | 1220 | hs_req->req.actual); |
7d24c1b5 MYK |
1221 | |
1222 | /* Free bounce buffer */ | |
1223 | kfree(hs_req->req.buf); | |
1224 | ||
1225 | hs_req->req.buf = hs_req->saved_req_buf; | |
1226 | hs_req->saved_req_buf = NULL; | |
1227 | } | |
1228 | ||
381fc8f8 VM |
1229 | /** |
1230 | * dwc2_gadget_target_frame_elapsed - Checks target frame | |
1231 | * @hs_ep: The driver endpoint to check | |
1232 | * | |
1233 | * Returns 1 if targeted frame elapsed. If returned 1 then we need to drop | |
1234 | * corresponding transfer. | |
1235 | */ | |
1236 | static bool dwc2_gadget_target_frame_elapsed(struct dwc2_hsotg_ep *hs_ep) | |
1237 | { | |
1238 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
1239 | u32 target_frame = hs_ep->target_frame; | |
c7c24e7a | 1240 | u32 current_frame = hsotg->frame_number; |
381fc8f8 VM |
1241 | bool frame_overrun = hs_ep->frame_overrun; |
1242 | ||
1243 | if (!frame_overrun && current_frame >= target_frame) | |
1244 | return true; | |
1245 | ||
1246 | if (frame_overrun && current_frame >= target_frame && | |
1247 | ((current_frame - target_frame) < DSTS_SOFFN_LIMIT / 2)) | |
1248 | return true; | |
1249 | ||
1250 | return false; | |
1251 | } | |
1252 | ||
e02f9aa6 VA |
1253 | /* |
1254 | * dwc2_gadget_set_ep0_desc_chain - Set EP's desc chain pointers | |
1255 | * @hsotg: The driver state | |
1256 | * @hs_ep: the ep descriptor chain is for | |
1257 | * | |
1258 | * Called to update EP0 structure's pointers depend on stage of | |
1259 | * control transfer. | |
1260 | */ | |
1261 | static int dwc2_gadget_set_ep0_desc_chain(struct dwc2_hsotg *hsotg, | |
1262 | struct dwc2_hsotg_ep *hs_ep) | |
1263 | { | |
1264 | switch (hsotg->ep0_state) { | |
1265 | case DWC2_EP0_SETUP: | |
1266 | case DWC2_EP0_STATUS_OUT: | |
1267 | hs_ep->desc_list = hsotg->setup_desc[0]; | |
1268 | hs_ep->desc_list_dma = hsotg->setup_desc_dma[0]; | |
1269 | break; | |
1270 | case DWC2_EP0_DATA_IN: | |
1271 | case DWC2_EP0_STATUS_IN: | |
1272 | hs_ep->desc_list = hsotg->ctrl_in_desc; | |
1273 | hs_ep->desc_list_dma = hsotg->ctrl_in_desc_dma; | |
1274 | break; | |
1275 | case DWC2_EP0_DATA_OUT: | |
1276 | hs_ep->desc_list = hsotg->ctrl_out_desc; | |
1277 | hs_ep->desc_list_dma = hsotg->ctrl_out_desc_dma; | |
1278 | break; | |
1279 | default: | |
1280 | dev_err(hsotg->dev, "invalid EP 0 state in queue %d\n", | |
1281 | hsotg->ep0_state); | |
1282 | return -EINVAL; | |
1283 | } | |
1284 | ||
1285 | return 0; | |
1286 | } | |
1287 | ||
1f91b4cc | 1288 | static int dwc2_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req, |
9da51974 | 1289 | gfp_t gfp_flags) |
5b7d70c6 | 1290 | { |
1f91b4cc FB |
1291 | struct dwc2_hsotg_req *hs_req = our_req(req); |
1292 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); | |
941fcce4 | 1293 | struct dwc2_hsotg *hs = hs_ep->parent; |
5b7d70c6 | 1294 | bool first; |
7d24c1b5 | 1295 | int ret; |
729cac69 MH |
1296 | u32 maxsize = 0; |
1297 | u32 mask = 0; | |
1298 | ||
5b7d70c6 BD |
1299 | |
1300 | dev_dbg(hs->dev, "%s: req %p: %d@%p, noi=%d, zero=%d, snok=%d\n", | |
1301 | ep->name, req, req->length, req->buf, req->no_interrupt, | |
1302 | req->zero, req->short_not_ok); | |
1303 | ||
7ababa92 | 1304 | /* Prevent new request submission when controller is suspended */ |
88b02f2c GT |
1305 | if (hs->lx_state != DWC2_L0) { |
1306 | dev_dbg(hs->dev, "%s: submit request only in active state\n", | |
9da51974 | 1307 | __func__); |
7ababa92 GH |
1308 | return -EAGAIN; |
1309 | } | |
1310 | ||
5b7d70c6 BD |
1311 | /* initialise status of the request */ |
1312 | INIT_LIST_HEAD(&hs_req->queue); | |
1313 | req->actual = 0; | |
1314 | req->status = -EINPROGRESS; | |
1315 | ||
729cac69 MH |
1316 | /* In DDMA mode for ISOC's don't queue request if length greater |
1317 | * than descriptor limits. | |
1318 | */ | |
1319 | if (using_desc_dma(hs) && hs_ep->isochronous) { | |
1320 | maxsize = dwc2_gadget_get_desc_params(hs_ep, &mask); | |
1321 | if (hs_ep->dir_in && req->length > maxsize) { | |
1322 | dev_err(hs->dev, "wrong length %d (maxsize=%d)\n", | |
1323 | req->length, maxsize); | |
1324 | return -EINVAL; | |
1325 | } | |
1326 | ||
1327 | if (!hs_ep->dir_in && req->length > hs_ep->ep.maxpacket) { | |
1328 | dev_err(hs->dev, "ISOC OUT: wrong length %d (mps=%d)\n", | |
1329 | req->length, hs_ep->ep.maxpacket); | |
1330 | return -EINVAL; | |
1331 | } | |
1332 | } | |
1333 | ||
1f91b4cc | 1334 | ret = dwc2_hsotg_handle_unaligned_buf_start(hs, hs_ep, hs_req); |
7d24c1b5 MYK |
1335 | if (ret) |
1336 | return ret; | |
1337 | ||
5b7d70c6 BD |
1338 | /* if we're using DMA, sync the buffers as necessary */ |
1339 | if (using_dma(hs)) { | |
1f91b4cc | 1340 | ret = dwc2_hsotg_map_dma(hs, hs_ep, req); |
5b7d70c6 BD |
1341 | if (ret) |
1342 | return ret; | |
1343 | } | |
e02f9aa6 VA |
1344 | /* If using descriptor DMA configure EP0 descriptor chain pointers */ |
1345 | if (using_desc_dma(hs) && !hs_ep->index) { | |
1346 | ret = dwc2_gadget_set_ep0_desc_chain(hs, hs_ep); | |
1347 | if (ret) | |
1348 | return ret; | |
1349 | } | |
5b7d70c6 | 1350 | |
5b7d70c6 BD |
1351 | first = list_empty(&hs_ep->queue); |
1352 | list_add_tail(&hs_req->queue, &hs_ep->queue); | |
1353 | ||
540ccba0 VA |
1354 | /* |
1355 | * Handle DDMA isochronous transfers separately - just add new entry | |
729cac69 | 1356 | * to the descriptor chain. |
540ccba0 VA |
1357 | * Transfer will be started once SW gets either one of NAK or |
1358 | * OutTknEpDis interrupts. | |
1359 | */ | |
729cac69 MH |
1360 | if (using_desc_dma(hs) && hs_ep->isochronous) { |
1361 | if (hs_ep->target_frame != TARGET_FRAME_INITIAL) { | |
1362 | dwc2_gadget_fill_isoc_desc(hs_ep, hs_req->req.dma, | |
1363 | hs_req->req.length); | |
1364 | } | |
540ccba0 VA |
1365 | return 0; |
1366 | } | |
1367 | ||
837e9f00 VM |
1368 | if (first) { |
1369 | if (!hs_ep->isochronous) { | |
1370 | dwc2_hsotg_start_req(hs, hs_ep, hs_req, false); | |
1371 | return 0; | |
1372 | } | |
1373 | ||
c7c24e7a AP |
1374 | /* Update current frame number value. */ |
1375 | hs->frame_number = dwc2_hsotg_read_frameno(hs); | |
1376 | while (dwc2_gadget_target_frame_elapsed(hs_ep)) { | |
837e9f00 | 1377 | dwc2_gadget_incr_frame_num(hs_ep); |
c7c24e7a AP |
1378 | /* Update current frame number value once more as it |
1379 | * changes here. | |
1380 | */ | |
1381 | hs->frame_number = dwc2_hsotg_read_frameno(hs); | |
1382 | } | |
5b7d70c6 | 1383 | |
837e9f00 VM |
1384 | if (hs_ep->target_frame != TARGET_FRAME_INITIAL) |
1385 | dwc2_hsotg_start_req(hs, hs_ep, hs_req, false); | |
1386 | } | |
5b7d70c6 BD |
1387 | return 0; |
1388 | } | |
1389 | ||
1f91b4cc | 1390 | static int dwc2_hsotg_ep_queue_lock(struct usb_ep *ep, struct usb_request *req, |
9da51974 | 1391 | gfp_t gfp_flags) |
5ad1d316 | 1392 | { |
1f91b4cc | 1393 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 1394 | struct dwc2_hsotg *hs = hs_ep->parent; |
5ad1d316 LM |
1395 | unsigned long flags = 0; |
1396 | int ret = 0; | |
1397 | ||
1398 | spin_lock_irqsave(&hs->lock, flags); | |
1f91b4cc | 1399 | ret = dwc2_hsotg_ep_queue(ep, req, gfp_flags); |
5ad1d316 LM |
1400 | spin_unlock_irqrestore(&hs->lock, flags); |
1401 | ||
1402 | return ret; | |
1403 | } | |
1404 | ||
1f91b4cc | 1405 | static void dwc2_hsotg_ep_free_request(struct usb_ep *ep, |
9da51974 | 1406 | struct usb_request *req) |
5b7d70c6 | 1407 | { |
1f91b4cc | 1408 | struct dwc2_hsotg_req *hs_req = our_req(req); |
5b7d70c6 BD |
1409 | |
1410 | kfree(hs_req); | |
1411 | } | |
1412 | ||
1413 | /** | |
1f91b4cc | 1414 | * dwc2_hsotg_complete_oursetup - setup completion callback |
5b7d70c6 BD |
1415 | * @ep: The endpoint the request was on. |
1416 | * @req: The request completed. | |
1417 | * | |
1418 | * Called on completion of any requests the driver itself | |
1419 | * submitted that need cleaning up. | |
1420 | */ | |
1f91b4cc | 1421 | static void dwc2_hsotg_complete_oursetup(struct usb_ep *ep, |
9da51974 | 1422 | struct usb_request *req) |
5b7d70c6 | 1423 | { |
1f91b4cc | 1424 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 1425 | struct dwc2_hsotg *hsotg = hs_ep->parent; |
5b7d70c6 BD |
1426 | |
1427 | dev_dbg(hsotg->dev, "%s: ep %p, req %p\n", __func__, ep, req); | |
1428 | ||
1f91b4cc | 1429 | dwc2_hsotg_ep_free_request(ep, req); |
5b7d70c6 BD |
1430 | } |
1431 | ||
1432 | /** | |
1433 | * ep_from_windex - convert control wIndex value to endpoint | |
1434 | * @hsotg: The driver state. | |
1435 | * @windex: The control request wIndex field (in host order). | |
1436 | * | |
1437 | * Convert the given wIndex into a pointer to an driver endpoint | |
1438 | * structure, or return NULL if it is not a valid endpoint. | |
8b9bc460 | 1439 | */ |
1f91b4cc | 1440 | static struct dwc2_hsotg_ep *ep_from_windex(struct dwc2_hsotg *hsotg, |
9da51974 | 1441 | u32 windex) |
5b7d70c6 | 1442 | { |
1f91b4cc | 1443 | struct dwc2_hsotg_ep *ep; |
5b7d70c6 BD |
1444 | int dir = (windex & USB_DIR_IN) ? 1 : 0; |
1445 | int idx = windex & 0x7F; | |
1446 | ||
1447 | if (windex >= 0x100) | |
1448 | return NULL; | |
1449 | ||
b3f489b2 | 1450 | if (idx > hsotg->num_of_eps) |
5b7d70c6 BD |
1451 | return NULL; |
1452 | ||
c6f5c050 MYK |
1453 | ep = index_to_ep(hsotg, idx, dir); |
1454 | ||
5b7d70c6 BD |
1455 | if (idx && ep->dir_in != dir) |
1456 | return NULL; | |
1457 | ||
1458 | return ep; | |
1459 | } | |
1460 | ||
9e14d0a5 | 1461 | /** |
1f91b4cc | 1462 | * dwc2_hsotg_set_test_mode - Enable usb Test Modes |
9e14d0a5 GH |
1463 | * @hsotg: The driver state. |
1464 | * @testmode: requested usb test mode | |
1465 | * Enable usb Test Mode requested by the Host. | |
1466 | */ | |
1f91b4cc | 1467 | int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode) |
9e14d0a5 | 1468 | { |
95c8bc36 | 1469 | int dctl = dwc2_readl(hsotg->regs + DCTL); |
9e14d0a5 GH |
1470 | |
1471 | dctl &= ~DCTL_TSTCTL_MASK; | |
1472 | switch (testmode) { | |
1473 | case TEST_J: | |
1474 | case TEST_K: | |
1475 | case TEST_SE0_NAK: | |
1476 | case TEST_PACKET: | |
1477 | case TEST_FORCE_EN: | |
1478 | dctl |= testmode << DCTL_TSTCTL_SHIFT; | |
1479 | break; | |
1480 | default: | |
1481 | return -EINVAL; | |
1482 | } | |
95c8bc36 | 1483 | dwc2_writel(dctl, hsotg->regs + DCTL); |
9e14d0a5 GH |
1484 | return 0; |
1485 | } | |
1486 | ||
5b7d70c6 | 1487 | /** |
1f91b4cc | 1488 | * dwc2_hsotg_send_reply - send reply to control request |
5b7d70c6 BD |
1489 | * @hsotg: The device state |
1490 | * @ep: Endpoint 0 | |
1491 | * @buff: Buffer for request | |
1492 | * @length: Length of reply. | |
1493 | * | |
1494 | * Create a request and queue it on the given endpoint. This is useful as | |
1495 | * an internal method of sending replies to certain control requests, etc. | |
1496 | */ | |
1f91b4cc | 1497 | static int dwc2_hsotg_send_reply(struct dwc2_hsotg *hsotg, |
9da51974 | 1498 | struct dwc2_hsotg_ep *ep, |
5b7d70c6 BD |
1499 | void *buff, |
1500 | int length) | |
1501 | { | |
1502 | struct usb_request *req; | |
1503 | int ret; | |
1504 | ||
1505 | dev_dbg(hsotg->dev, "%s: buff %p, len %d\n", __func__, buff, length); | |
1506 | ||
1f91b4cc | 1507 | req = dwc2_hsotg_ep_alloc_request(&ep->ep, GFP_ATOMIC); |
5b7d70c6 BD |
1508 | hsotg->ep0_reply = req; |
1509 | if (!req) { | |
1510 | dev_warn(hsotg->dev, "%s: cannot alloc req\n", __func__); | |
1511 | return -ENOMEM; | |
1512 | } | |
1513 | ||
1514 | req->buf = hsotg->ep0_buff; | |
1515 | req->length = length; | |
f71b5e25 MYK |
1516 | /* |
1517 | * zero flag is for sending zlp in DATA IN stage. It has no impact on | |
1518 | * STATUS stage. | |
1519 | */ | |
1520 | req->zero = 0; | |
1f91b4cc | 1521 | req->complete = dwc2_hsotg_complete_oursetup; |
5b7d70c6 BD |
1522 | |
1523 | if (length) | |
1524 | memcpy(req->buf, buff, length); | |
5b7d70c6 | 1525 | |
1f91b4cc | 1526 | ret = dwc2_hsotg_ep_queue(&ep->ep, req, GFP_ATOMIC); |
5b7d70c6 BD |
1527 | if (ret) { |
1528 | dev_warn(hsotg->dev, "%s: cannot queue req\n", __func__); | |
1529 | return ret; | |
1530 | } | |
1531 | ||
1532 | return 0; | |
1533 | } | |
1534 | ||
1535 | /** | |
1f91b4cc | 1536 | * dwc2_hsotg_process_req_status - process request GET_STATUS |
5b7d70c6 BD |
1537 | * @hsotg: The device state |
1538 | * @ctrl: USB control request | |
1539 | */ | |
1f91b4cc | 1540 | static int dwc2_hsotg_process_req_status(struct dwc2_hsotg *hsotg, |
9da51974 | 1541 | struct usb_ctrlrequest *ctrl) |
5b7d70c6 | 1542 | { |
1f91b4cc FB |
1543 | struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0]; |
1544 | struct dwc2_hsotg_ep *ep; | |
5b7d70c6 BD |
1545 | __le16 reply; |
1546 | int ret; | |
1547 | ||
1548 | dev_dbg(hsotg->dev, "%s: USB_REQ_GET_STATUS\n", __func__); | |
1549 | ||
1550 | if (!ep0->dir_in) { | |
1551 | dev_warn(hsotg->dev, "%s: direction out?\n", __func__); | |
1552 | return -EINVAL; | |
1553 | } | |
1554 | ||
1555 | switch (ctrl->bRequestType & USB_RECIP_MASK) { | |
1556 | case USB_RECIP_DEVICE: | |
38beaec6 JY |
1557 | /* |
1558 | * bit 0 => self powered | |
1559 | * bit 1 => remote wakeup | |
1560 | */ | |
1561 | reply = cpu_to_le16(0); | |
5b7d70c6 BD |
1562 | break; |
1563 | ||
1564 | case USB_RECIP_INTERFACE: | |
1565 | /* currently, the data result should be zero */ | |
1566 | reply = cpu_to_le16(0); | |
1567 | break; | |
1568 | ||
1569 | case USB_RECIP_ENDPOINT: | |
1570 | ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex)); | |
1571 | if (!ep) | |
1572 | return -ENOENT; | |
1573 | ||
1574 | reply = cpu_to_le16(ep->halted ? 1 : 0); | |
1575 | break; | |
1576 | ||
1577 | default: | |
1578 | return 0; | |
1579 | } | |
1580 | ||
1581 | if (le16_to_cpu(ctrl->wLength) != 2) | |
1582 | return -EINVAL; | |
1583 | ||
1f91b4cc | 1584 | ret = dwc2_hsotg_send_reply(hsotg, ep0, &reply, 2); |
5b7d70c6 BD |
1585 | if (ret) { |
1586 | dev_err(hsotg->dev, "%s: failed to send reply\n", __func__); | |
1587 | return ret; | |
1588 | } | |
1589 | ||
1590 | return 1; | |
1591 | } | |
1592 | ||
51da43b5 | 1593 | static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now); |
5b7d70c6 | 1594 | |
9c39ddc6 AT |
1595 | /** |
1596 | * get_ep_head - return the first request on the endpoint | |
1597 | * @hs_ep: The controller endpoint to get | |
1598 | * | |
1599 | * Get the first request on the endpoint. | |
1600 | */ | |
1f91b4cc | 1601 | static struct dwc2_hsotg_req *get_ep_head(struct dwc2_hsotg_ep *hs_ep) |
9c39ddc6 | 1602 | { |
ffc4b406 MY |
1603 | return list_first_entry_or_null(&hs_ep->queue, struct dwc2_hsotg_req, |
1604 | queue); | |
9c39ddc6 AT |
1605 | } |
1606 | ||
41cc4cd2 VM |
1607 | /** |
1608 | * dwc2_gadget_start_next_request - Starts next request from ep queue | |
1609 | * @hs_ep: Endpoint structure | |
1610 | * | |
1611 | * If queue is empty and EP is ISOC-OUT - unmasks OUTTKNEPDIS which is masked | |
1612 | * in its handler. Hence we need to unmask it here to be able to do | |
1613 | * resynchronization. | |
1614 | */ | |
1615 | static void dwc2_gadget_start_next_request(struct dwc2_hsotg_ep *hs_ep) | |
1616 | { | |
1617 | u32 mask; | |
1618 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
1619 | int dir_in = hs_ep->dir_in; | |
1620 | struct dwc2_hsotg_req *hs_req; | |
1621 | u32 epmsk_reg = dir_in ? DIEPMSK : DOEPMSK; | |
1622 | ||
1623 | if (!list_empty(&hs_ep->queue)) { | |
1624 | hs_req = get_ep_head(hs_ep); | |
1625 | dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, false); | |
1626 | return; | |
1627 | } | |
1628 | if (!hs_ep->isochronous) | |
1629 | return; | |
1630 | ||
1631 | if (dir_in) { | |
1632 | dev_dbg(hsotg->dev, "%s: No more ISOC-IN requests\n", | |
1633 | __func__); | |
1634 | } else { | |
1635 | dev_dbg(hsotg->dev, "%s: No more ISOC-OUT requests\n", | |
1636 | __func__); | |
1637 | mask = dwc2_readl(hsotg->regs + epmsk_reg); | |
1638 | mask |= DOEPMSK_OUTTKNEPDISMSK; | |
1639 | dwc2_writel(mask, hsotg->regs + epmsk_reg); | |
1640 | } | |
1641 | } | |
1642 | ||
5b7d70c6 | 1643 | /** |
1f91b4cc | 1644 | * dwc2_hsotg_process_req_feature - process request {SET,CLEAR}_FEATURE |
5b7d70c6 BD |
1645 | * @hsotg: The device state |
1646 | * @ctrl: USB control request | |
1647 | */ | |
1f91b4cc | 1648 | static int dwc2_hsotg_process_req_feature(struct dwc2_hsotg *hsotg, |
9da51974 | 1649 | struct usb_ctrlrequest *ctrl) |
5b7d70c6 | 1650 | { |
1f91b4cc FB |
1651 | struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0]; |
1652 | struct dwc2_hsotg_req *hs_req; | |
5b7d70c6 | 1653 | bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE); |
1f91b4cc | 1654 | struct dwc2_hsotg_ep *ep; |
26ab3d0c | 1655 | int ret; |
bd9ef7bf | 1656 | bool halted; |
9e14d0a5 GH |
1657 | u32 recip; |
1658 | u32 wValue; | |
1659 | u32 wIndex; | |
5b7d70c6 BD |
1660 | |
1661 | dev_dbg(hsotg->dev, "%s: %s_FEATURE\n", | |
1662 | __func__, set ? "SET" : "CLEAR"); | |
1663 | ||
9e14d0a5 GH |
1664 | wValue = le16_to_cpu(ctrl->wValue); |
1665 | wIndex = le16_to_cpu(ctrl->wIndex); | |
1666 | recip = ctrl->bRequestType & USB_RECIP_MASK; | |
1667 | ||
1668 | switch (recip) { | |
1669 | case USB_RECIP_DEVICE: | |
1670 | switch (wValue) { | |
fa389a6d VM |
1671 | case USB_DEVICE_REMOTE_WAKEUP: |
1672 | hsotg->remote_wakeup_allowed = 1; | |
1673 | break; | |
1674 | ||
9e14d0a5 GH |
1675 | case USB_DEVICE_TEST_MODE: |
1676 | if ((wIndex & 0xff) != 0) | |
1677 | return -EINVAL; | |
1678 | if (!set) | |
1679 | return -EINVAL; | |
1680 | ||
1681 | hsotg->test_mode = wIndex >> 8; | |
1f91b4cc | 1682 | ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0); |
9e14d0a5 GH |
1683 | if (ret) { |
1684 | dev_err(hsotg->dev, | |
1685 | "%s: failed to send reply\n", __func__); | |
1686 | return ret; | |
1687 | } | |
1688 | break; | |
1689 | default: | |
1690 | return -ENOENT; | |
1691 | } | |
1692 | break; | |
1693 | ||
1694 | case USB_RECIP_ENDPOINT: | |
1695 | ep = ep_from_windex(hsotg, wIndex); | |
5b7d70c6 BD |
1696 | if (!ep) { |
1697 | dev_dbg(hsotg->dev, "%s: no endpoint for 0x%04x\n", | |
9e14d0a5 | 1698 | __func__, wIndex); |
5b7d70c6 BD |
1699 | return -ENOENT; |
1700 | } | |
1701 | ||
9e14d0a5 | 1702 | switch (wValue) { |
5b7d70c6 | 1703 | case USB_ENDPOINT_HALT: |
bd9ef7bf RB |
1704 | halted = ep->halted; |
1705 | ||
51da43b5 | 1706 | dwc2_hsotg_ep_sethalt(&ep->ep, set, true); |
26ab3d0c | 1707 | |
1f91b4cc | 1708 | ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0); |
26ab3d0c AT |
1709 | if (ret) { |
1710 | dev_err(hsotg->dev, | |
1711 | "%s: failed to send reply\n", __func__); | |
1712 | return ret; | |
1713 | } | |
9c39ddc6 | 1714 | |
bd9ef7bf RB |
1715 | /* |
1716 | * we have to complete all requests for ep if it was | |
1717 | * halted, and the halt was cleared by CLEAR_FEATURE | |
1718 | */ | |
1719 | ||
1720 | if (!set && halted) { | |
9c39ddc6 AT |
1721 | /* |
1722 | * If we have request in progress, | |
1723 | * then complete it | |
1724 | */ | |
1725 | if (ep->req) { | |
1726 | hs_req = ep->req; | |
1727 | ep->req = NULL; | |
1728 | list_del_init(&hs_req->queue); | |
c00dd4a6 GH |
1729 | if (hs_req->req.complete) { |
1730 | spin_unlock(&hsotg->lock); | |
1731 | usb_gadget_giveback_request( | |
1732 | &ep->ep, &hs_req->req); | |
1733 | spin_lock(&hsotg->lock); | |
1734 | } | |
9c39ddc6 AT |
1735 | } |
1736 | ||
1737 | /* If we have pending request, then start it */ | |
34c0887f | 1738 | if (!ep->req) |
41cc4cd2 | 1739 | dwc2_gadget_start_next_request(ep); |
9c39ddc6 AT |
1740 | } |
1741 | ||
5b7d70c6 BD |
1742 | break; |
1743 | ||
1744 | default: | |
1745 | return -ENOENT; | |
1746 | } | |
9e14d0a5 GH |
1747 | break; |
1748 | default: | |
1749 | return -ENOENT; | |
1750 | } | |
5b7d70c6 BD |
1751 | return 1; |
1752 | } | |
1753 | ||
1f91b4cc | 1754 | static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg); |
ab93e014 | 1755 | |
c9f721b2 | 1756 | /** |
1f91b4cc | 1757 | * dwc2_hsotg_stall_ep0 - stall ep0 |
c9f721b2 RB |
1758 | * @hsotg: The device state |
1759 | * | |
1760 | * Set stall for ep0 as response for setup request. | |
1761 | */ | |
1f91b4cc | 1762 | static void dwc2_hsotg_stall_ep0(struct dwc2_hsotg *hsotg) |
e9ebe7c3 | 1763 | { |
1f91b4cc | 1764 | struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0]; |
c9f721b2 RB |
1765 | u32 reg; |
1766 | u32 ctrl; | |
1767 | ||
1768 | dev_dbg(hsotg->dev, "ep0 stall (dir=%d)\n", ep0->dir_in); | |
1769 | reg = (ep0->dir_in) ? DIEPCTL0 : DOEPCTL0; | |
1770 | ||
1771 | /* | |
1772 | * DxEPCTL_Stall will be cleared by EP once it has | |
1773 | * taken effect, so no need to clear later. | |
1774 | */ | |
1775 | ||
95c8bc36 | 1776 | ctrl = dwc2_readl(hsotg->regs + reg); |
47a1685f DN |
1777 | ctrl |= DXEPCTL_STALL; |
1778 | ctrl |= DXEPCTL_CNAK; | |
95c8bc36 | 1779 | dwc2_writel(ctrl, hsotg->regs + reg); |
c9f721b2 RB |
1780 | |
1781 | dev_dbg(hsotg->dev, | |
47a1685f | 1782 | "written DXEPCTL=0x%08x to %08x (DXEPCTL=0x%08x)\n", |
95c8bc36 | 1783 | ctrl, reg, dwc2_readl(hsotg->regs + reg)); |
c9f721b2 RB |
1784 | |
1785 | /* | |
1786 | * complete won't be called, so we enqueue | |
1787 | * setup request here | |
1788 | */ | |
1f91b4cc | 1789 | dwc2_hsotg_enqueue_setup(hsotg); |
c9f721b2 RB |
1790 | } |
1791 | ||
5b7d70c6 | 1792 | /** |
1f91b4cc | 1793 | * dwc2_hsotg_process_control - process a control request |
5b7d70c6 BD |
1794 | * @hsotg: The device state |
1795 | * @ctrl: The control request received | |
1796 | * | |
1797 | * The controller has received the SETUP phase of a control request, and | |
1798 | * needs to work out what to do next (and whether to pass it on to the | |
1799 | * gadget driver). | |
1800 | */ | |
1f91b4cc | 1801 | static void dwc2_hsotg_process_control(struct dwc2_hsotg *hsotg, |
9da51974 | 1802 | struct usb_ctrlrequest *ctrl) |
5b7d70c6 | 1803 | { |
1f91b4cc | 1804 | struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0]; |
5b7d70c6 BD |
1805 | int ret = 0; |
1806 | u32 dcfg; | |
1807 | ||
e525e743 MYK |
1808 | dev_dbg(hsotg->dev, |
1809 | "ctrl Type=%02x, Req=%02x, V=%04x, I=%04x, L=%04x\n", | |
1810 | ctrl->bRequestType, ctrl->bRequest, ctrl->wValue, | |
1811 | ctrl->wIndex, ctrl->wLength); | |
5b7d70c6 | 1812 | |
fe0b94ab MYK |
1813 | if (ctrl->wLength == 0) { |
1814 | ep0->dir_in = 1; | |
1815 | hsotg->ep0_state = DWC2_EP0_STATUS_IN; | |
1816 | } else if (ctrl->bRequestType & USB_DIR_IN) { | |
5b7d70c6 | 1817 | ep0->dir_in = 1; |
fe0b94ab MYK |
1818 | hsotg->ep0_state = DWC2_EP0_DATA_IN; |
1819 | } else { | |
1820 | ep0->dir_in = 0; | |
1821 | hsotg->ep0_state = DWC2_EP0_DATA_OUT; | |
1822 | } | |
5b7d70c6 BD |
1823 | |
1824 | if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) { | |
1825 | switch (ctrl->bRequest) { | |
1826 | case USB_REQ_SET_ADDRESS: | |
6d713c15 | 1827 | hsotg->connected = 1; |
95c8bc36 | 1828 | dcfg = dwc2_readl(hsotg->regs + DCFG); |
47a1685f | 1829 | dcfg &= ~DCFG_DEVADDR_MASK; |
d5dbd3f7 PZ |
1830 | dcfg |= (le16_to_cpu(ctrl->wValue) << |
1831 | DCFG_DEVADDR_SHIFT) & DCFG_DEVADDR_MASK; | |
95c8bc36 | 1832 | dwc2_writel(dcfg, hsotg->regs + DCFG); |
5b7d70c6 BD |
1833 | |
1834 | dev_info(hsotg->dev, "new address %d\n", ctrl->wValue); | |
1835 | ||
1f91b4cc | 1836 | ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0); |
5b7d70c6 BD |
1837 | return; |
1838 | ||
1839 | case USB_REQ_GET_STATUS: | |
1f91b4cc | 1840 | ret = dwc2_hsotg_process_req_status(hsotg, ctrl); |
5b7d70c6 BD |
1841 | break; |
1842 | ||
1843 | case USB_REQ_CLEAR_FEATURE: | |
1844 | case USB_REQ_SET_FEATURE: | |
1f91b4cc | 1845 | ret = dwc2_hsotg_process_req_feature(hsotg, ctrl); |
5b7d70c6 BD |
1846 | break; |
1847 | } | |
1848 | } | |
1849 | ||
1850 | /* as a fallback, try delivering it to the driver to deal with */ | |
1851 | ||
1852 | if (ret == 0 && hsotg->driver) { | |
93f599f2 | 1853 | spin_unlock(&hsotg->lock); |
5b7d70c6 | 1854 | ret = hsotg->driver->setup(&hsotg->gadget, ctrl); |
93f599f2 | 1855 | spin_lock(&hsotg->lock); |
5b7d70c6 BD |
1856 | if (ret < 0) |
1857 | dev_dbg(hsotg->dev, "driver->setup() ret %d\n", ret); | |
1858 | } | |
1859 | ||
8b9bc460 LM |
1860 | /* |
1861 | * the request is either unhandlable, or is not formatted correctly | |
5b7d70c6 BD |
1862 | * so respond with a STALL for the status stage to indicate failure. |
1863 | */ | |
1864 | ||
c9f721b2 | 1865 | if (ret < 0) |
1f91b4cc | 1866 | dwc2_hsotg_stall_ep0(hsotg); |
5b7d70c6 BD |
1867 | } |
1868 | ||
5b7d70c6 | 1869 | /** |
1f91b4cc | 1870 | * dwc2_hsotg_complete_setup - completion of a setup transfer |
5b7d70c6 BD |
1871 | * @ep: The endpoint the request was on. |
1872 | * @req: The request completed. | |
1873 | * | |
1874 | * Called on completion of any requests the driver itself submitted for | |
1875 | * EP0 setup packets | |
1876 | */ | |
1f91b4cc | 1877 | static void dwc2_hsotg_complete_setup(struct usb_ep *ep, |
9da51974 | 1878 | struct usb_request *req) |
5b7d70c6 | 1879 | { |
1f91b4cc | 1880 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 1881 | struct dwc2_hsotg *hsotg = hs_ep->parent; |
5b7d70c6 BD |
1882 | |
1883 | if (req->status < 0) { | |
1884 | dev_dbg(hsotg->dev, "%s: failed %d\n", __func__, req->status); | |
1885 | return; | |
1886 | } | |
1887 | ||
93f599f2 | 1888 | spin_lock(&hsotg->lock); |
5b7d70c6 | 1889 | if (req->actual == 0) |
1f91b4cc | 1890 | dwc2_hsotg_enqueue_setup(hsotg); |
5b7d70c6 | 1891 | else |
1f91b4cc | 1892 | dwc2_hsotg_process_control(hsotg, req->buf); |
93f599f2 | 1893 | spin_unlock(&hsotg->lock); |
5b7d70c6 BD |
1894 | } |
1895 | ||
1896 | /** | |
1f91b4cc | 1897 | * dwc2_hsotg_enqueue_setup - start a request for EP0 packets |
5b7d70c6 BD |
1898 | * @hsotg: The device state. |
1899 | * | |
1900 | * Enqueue a request on EP0 if necessary to received any SETUP packets | |
1901 | * received from the host. | |
1902 | */ | |
1f91b4cc | 1903 | static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg) |
5b7d70c6 BD |
1904 | { |
1905 | struct usb_request *req = hsotg->ctrl_req; | |
1f91b4cc | 1906 | struct dwc2_hsotg_req *hs_req = our_req(req); |
5b7d70c6 BD |
1907 | int ret; |
1908 | ||
1909 | dev_dbg(hsotg->dev, "%s: queueing setup request\n", __func__); | |
1910 | ||
1911 | req->zero = 0; | |
1912 | req->length = 8; | |
1913 | req->buf = hsotg->ctrl_buff; | |
1f91b4cc | 1914 | req->complete = dwc2_hsotg_complete_setup; |
5b7d70c6 BD |
1915 | |
1916 | if (!list_empty(&hs_req->queue)) { | |
1917 | dev_dbg(hsotg->dev, "%s already queued???\n", __func__); | |
1918 | return; | |
1919 | } | |
1920 | ||
c6f5c050 | 1921 | hsotg->eps_out[0]->dir_in = 0; |
8a20fa45 | 1922 | hsotg->eps_out[0]->send_zlp = 0; |
fe0b94ab | 1923 | hsotg->ep0_state = DWC2_EP0_SETUP; |
5b7d70c6 | 1924 | |
1f91b4cc | 1925 | ret = dwc2_hsotg_ep_queue(&hsotg->eps_out[0]->ep, req, GFP_ATOMIC); |
5b7d70c6 BD |
1926 | if (ret < 0) { |
1927 | dev_err(hsotg->dev, "%s: failed queue (%d)\n", __func__, ret); | |
8b9bc460 LM |
1928 | /* |
1929 | * Don't think there's much we can do other than watch the | |
1930 | * driver fail. | |
1931 | */ | |
5b7d70c6 BD |
1932 | } |
1933 | } | |
1934 | ||
1f91b4cc | 1935 | static void dwc2_hsotg_program_zlp(struct dwc2_hsotg *hsotg, |
9da51974 | 1936 | struct dwc2_hsotg_ep *hs_ep) |
fe0b94ab MYK |
1937 | { |
1938 | u32 ctrl; | |
1939 | u8 index = hs_ep->index; | |
1940 | u32 epctl_reg = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index); | |
1941 | u32 epsiz_reg = hs_ep->dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index); | |
1942 | ||
ccb34a91 MYK |
1943 | if (hs_ep->dir_in) |
1944 | dev_dbg(hsotg->dev, "Sending zero-length packet on ep%d\n", | |
e02f9aa6 | 1945 | index); |
ccb34a91 MYK |
1946 | else |
1947 | dev_dbg(hsotg->dev, "Receiving zero-length packet on ep%d\n", | |
e02f9aa6 VA |
1948 | index); |
1949 | if (using_desc_dma(hsotg)) { | |
1950 | /* Not specific buffer needed for ep0 ZLP */ | |
1951 | dma_addr_t dma = hs_ep->desc_list_dma; | |
fe0b94ab | 1952 | |
201ec568 MH |
1953 | if (!index) |
1954 | dwc2_gadget_set_ep0_desc_chain(hsotg, hs_ep); | |
1955 | ||
e02f9aa6 VA |
1956 | dwc2_gadget_config_nonisoc_xfer_ddma(hs_ep, dma, 0); |
1957 | } else { | |
1958 | dwc2_writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) | | |
1959 | DXEPTSIZ_XFERSIZE(0), hsotg->regs + | |
1960 | epsiz_reg); | |
1961 | } | |
fe0b94ab | 1962 | |
95c8bc36 | 1963 | ctrl = dwc2_readl(hsotg->regs + epctl_reg); |
fe0b94ab MYK |
1964 | ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */ |
1965 | ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */ | |
1966 | ctrl |= DXEPCTL_USBACTEP; | |
95c8bc36 | 1967 | dwc2_writel(ctrl, hsotg->regs + epctl_reg); |
fe0b94ab MYK |
1968 | } |
1969 | ||
5b7d70c6 | 1970 | /** |
1f91b4cc | 1971 | * dwc2_hsotg_complete_request - complete a request given to us |
5b7d70c6 BD |
1972 | * @hsotg: The device state. |
1973 | * @hs_ep: The endpoint the request was on. | |
1974 | * @hs_req: The request to complete. | |
1975 | * @result: The result code (0 => Ok, otherwise errno) | |
1976 | * | |
1977 | * The given request has finished, so call the necessary completion | |
1978 | * if it has one and then look to see if we can start a new request | |
1979 | * on the endpoint. | |
1980 | * | |
1981 | * Note, expects the ep to already be locked as appropriate. | |
8b9bc460 | 1982 | */ |
1f91b4cc | 1983 | static void dwc2_hsotg_complete_request(struct dwc2_hsotg *hsotg, |
9da51974 | 1984 | struct dwc2_hsotg_ep *hs_ep, |
1f91b4cc | 1985 | struct dwc2_hsotg_req *hs_req, |
5b7d70c6 BD |
1986 | int result) |
1987 | { | |
5b7d70c6 BD |
1988 | if (!hs_req) { |
1989 | dev_dbg(hsotg->dev, "%s: nothing to complete?\n", __func__); | |
1990 | return; | |
1991 | } | |
1992 | ||
1993 | dev_dbg(hsotg->dev, "complete: ep %p %s, req %p, %d => %p\n", | |
1994 | hs_ep, hs_ep->ep.name, hs_req, result, hs_req->req.complete); | |
1995 | ||
8b9bc460 LM |
1996 | /* |
1997 | * only replace the status if we've not already set an error | |
1998 | * from a previous transaction | |
1999 | */ | |
5b7d70c6 BD |
2000 | |
2001 | if (hs_req->req.status == -EINPROGRESS) | |
2002 | hs_req->req.status = result; | |
2003 | ||
44583fec YL |
2004 | if (using_dma(hsotg)) |
2005 | dwc2_hsotg_unmap_dma(hsotg, hs_ep, hs_req); | |
2006 | ||
1f91b4cc | 2007 | dwc2_hsotg_handle_unaligned_buf_complete(hsotg, hs_ep, hs_req); |
7d24c1b5 | 2008 | |
5b7d70c6 BD |
2009 | hs_ep->req = NULL; |
2010 | list_del_init(&hs_req->queue); | |
2011 | ||
8b9bc460 LM |
2012 | /* |
2013 | * call the complete request with the locks off, just in case the | |
2014 | * request tries to queue more work for this endpoint. | |
2015 | */ | |
5b7d70c6 BD |
2016 | |
2017 | if (hs_req->req.complete) { | |
22258f49 | 2018 | spin_unlock(&hsotg->lock); |
304f7e5e | 2019 | usb_gadget_giveback_request(&hs_ep->ep, &hs_req->req); |
22258f49 | 2020 | spin_lock(&hsotg->lock); |
5b7d70c6 BD |
2021 | } |
2022 | ||
540ccba0 VA |
2023 | /* In DDMA don't need to proceed to starting of next ISOC request */ |
2024 | if (using_desc_dma(hsotg) && hs_ep->isochronous) | |
2025 | return; | |
2026 | ||
8b9bc460 LM |
2027 | /* |
2028 | * Look to see if there is anything else to do. Note, the completion | |
5b7d70c6 | 2029 | * of the previous request may have caused a new request to be started |
8b9bc460 LM |
2030 | * so be careful when doing this. |
2031 | */ | |
5b7d70c6 | 2032 | |
34c0887f | 2033 | if (!hs_ep->req && result >= 0) |
41cc4cd2 | 2034 | dwc2_gadget_start_next_request(hs_ep); |
5b7d70c6 BD |
2035 | } |
2036 | ||
540ccba0 VA |
2037 | /* |
2038 | * dwc2_gadget_complete_isoc_request_ddma - complete an isoc request in DDMA | |
2039 | * @hs_ep: The endpoint the request was on. | |
2040 | * | |
2041 | * Get first request from the ep queue, determine descriptor on which complete | |
729cac69 MH |
2042 | * happened. SW discovers which descriptor currently in use by HW, adjusts |
2043 | * dma_address and calculates index of completed descriptor based on the value | |
2044 | * of DEPDMA register. Update actual length of request, giveback to gadget. | |
540ccba0 VA |
2045 | */ |
2046 | static void dwc2_gadget_complete_isoc_request_ddma(struct dwc2_hsotg_ep *hs_ep) | |
2047 | { | |
2048 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
2049 | struct dwc2_hsotg_req *hs_req; | |
2050 | struct usb_request *ureq; | |
540ccba0 VA |
2051 | u32 desc_sts; |
2052 | u32 mask; | |
2053 | ||
729cac69 | 2054 | desc_sts = hs_ep->desc_list[hs_ep->compl_desc].status; |
540ccba0 | 2055 | |
729cac69 MH |
2056 | /* Process only descriptors with buffer status set to DMA done */ |
2057 | while ((desc_sts & DEV_DMA_BUFF_STS_MASK) >> | |
2058 | DEV_DMA_BUFF_STS_SHIFT == DEV_DMA_BUFF_STS_DMADONE) { | |
540ccba0 | 2059 | |
729cac69 MH |
2060 | hs_req = get_ep_head(hs_ep); |
2061 | if (!hs_req) { | |
2062 | dev_warn(hsotg->dev, "%s: ISOC EP queue empty\n", __func__); | |
2063 | return; | |
2064 | } | |
2065 | ureq = &hs_req->req; | |
2066 | ||
2067 | /* Check completion status */ | |
2068 | if ((desc_sts & DEV_DMA_STS_MASK) >> DEV_DMA_STS_SHIFT == | |
2069 | DEV_DMA_STS_SUCC) { | |
2070 | mask = hs_ep->dir_in ? DEV_DMA_ISOC_TX_NBYTES_MASK : | |
2071 | DEV_DMA_ISOC_RX_NBYTES_MASK; | |
2072 | ureq->actual = ureq->length - ((desc_sts & mask) >> | |
2073 | DEV_DMA_ISOC_NBYTES_SHIFT); | |
2074 | ||
2075 | /* Adjust actual len for ISOC Out if len is | |
2076 | * not align of 4 | |
2077 | */ | |
2078 | if (!hs_ep->dir_in && ureq->length & 0x3) | |
2079 | ureq->actual += 4 - (ureq->length & 0x3); | |
2080 | } | |
540ccba0 | 2081 | |
729cac69 | 2082 | dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0); |
95d2b037 | 2083 | |
729cac69 MH |
2084 | hs_ep->compl_desc++; |
2085 | if (hs_ep->compl_desc > (MAX_DMA_DESC_NUM_GENERIC - 1)) | |
2086 | hs_ep->compl_desc = 0; | |
2087 | desc_sts = hs_ep->desc_list[hs_ep->compl_desc].status; | |
2088 | } | |
540ccba0 VA |
2089 | } |
2090 | ||
2091 | /* | |
729cac69 MH |
2092 | * dwc2_gadget_handle_isoc_bna - handle BNA interrupt for ISOC. |
2093 | * @hs_ep: The isochronous endpoint. | |
540ccba0 | 2094 | * |
729cac69 MH |
2095 | * If EP ISOC OUT then need to flush RX FIFO to remove source of BNA |
2096 | * interrupt. Reset target frame and next_desc to allow to start | |
2097 | * ISOC's on NAK interrupt for IN direction or on OUTTKNEPDIS | |
2098 | * interrupt for OUT direction. | |
540ccba0 | 2099 | */ |
729cac69 | 2100 | static void dwc2_gadget_handle_isoc_bna(struct dwc2_hsotg_ep *hs_ep) |
540ccba0 VA |
2101 | { |
2102 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
540ccba0 | 2103 | |
729cac69 MH |
2104 | if (!hs_ep->dir_in) |
2105 | dwc2_flush_rx_fifo(hsotg); | |
2106 | dwc2_hsotg_complete_request(hsotg, hs_ep, get_ep_head(hs_ep), 0); | |
540ccba0 | 2107 | |
729cac69 MH |
2108 | hs_ep->target_frame = TARGET_FRAME_INITIAL; |
2109 | hs_ep->next_desc = 0; | |
2110 | hs_ep->compl_desc = 0; | |
540ccba0 VA |
2111 | } |
2112 | ||
5b7d70c6 | 2113 | /** |
1f91b4cc | 2114 | * dwc2_hsotg_rx_data - receive data from the FIFO for an endpoint |
5b7d70c6 BD |
2115 | * @hsotg: The device state. |
2116 | * @ep_idx: The endpoint index for the data | |
2117 | * @size: The size of data in the fifo, in bytes | |
2118 | * | |
2119 | * The FIFO status shows there is data to read from the FIFO for a given | |
2120 | * endpoint, so sort out whether we need to read the data into a request | |
2121 | * that has been made for that endpoint. | |
2122 | */ | |
1f91b4cc | 2123 | static void dwc2_hsotg_rx_data(struct dwc2_hsotg *hsotg, int ep_idx, int size) |
5b7d70c6 | 2124 | { |
1f91b4cc FB |
2125 | struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[ep_idx]; |
2126 | struct dwc2_hsotg_req *hs_req = hs_ep->req; | |
94cb8fd6 | 2127 | void __iomem *fifo = hsotg->regs + EPFIFO(ep_idx); |
5b7d70c6 BD |
2128 | int to_read; |
2129 | int max_req; | |
2130 | int read_ptr; | |
2131 | ||
2132 | if (!hs_req) { | |
95c8bc36 | 2133 | u32 epctl = dwc2_readl(hsotg->regs + DOEPCTL(ep_idx)); |
5b7d70c6 BD |
2134 | int ptr; |
2135 | ||
6b448af4 | 2136 | dev_dbg(hsotg->dev, |
9da51974 | 2137 | "%s: FIFO %d bytes on ep%d but no req (DXEPCTl=0x%08x)\n", |
5b7d70c6 BD |
2138 | __func__, size, ep_idx, epctl); |
2139 | ||
2140 | /* dump the data from the FIFO, we've nothing we can do */ | |
2141 | for (ptr = 0; ptr < size; ptr += 4) | |
95c8bc36 | 2142 | (void)dwc2_readl(fifo); |
5b7d70c6 BD |
2143 | |
2144 | return; | |
2145 | } | |
2146 | ||
5b7d70c6 BD |
2147 | to_read = size; |
2148 | read_ptr = hs_req->req.actual; | |
2149 | max_req = hs_req->req.length - read_ptr; | |
2150 | ||
a33e7136 BD |
2151 | dev_dbg(hsotg->dev, "%s: read %d/%d, done %d/%d\n", |
2152 | __func__, to_read, max_req, read_ptr, hs_req->req.length); | |
2153 | ||
5b7d70c6 | 2154 | if (to_read > max_req) { |
8b9bc460 LM |
2155 | /* |
2156 | * more data appeared than we where willing | |
5b7d70c6 BD |
2157 | * to deal with in this request. |
2158 | */ | |
2159 | ||
2160 | /* currently we don't deal this */ | |
2161 | WARN_ON_ONCE(1); | |
2162 | } | |
2163 | ||
5b7d70c6 BD |
2164 | hs_ep->total_data += to_read; |
2165 | hs_req->req.actual += to_read; | |
2166 | to_read = DIV_ROUND_UP(to_read, 4); | |
2167 | ||
8b9bc460 LM |
2168 | /* |
2169 | * note, we might over-write the buffer end by 3 bytes depending on | |
2170 | * alignment of the data. | |
2171 | */ | |
1a7ed5be | 2172 | ioread32_rep(fifo, hs_req->req.buf + read_ptr, to_read); |
5b7d70c6 BD |
2173 | } |
2174 | ||
2175 | /** | |
1f91b4cc | 2176 | * dwc2_hsotg_ep0_zlp - send/receive zero-length packet on control endpoint |
5b7d70c6 | 2177 | * @hsotg: The device instance |
fe0b94ab | 2178 | * @dir_in: If IN zlp |
5b7d70c6 BD |
2179 | * |
2180 | * Generate a zero-length IN packet request for terminating a SETUP | |
2181 | * transaction. | |
2182 | * | |
2183 | * Note, since we don't write any data to the TxFIFO, then it is | |
25985edc | 2184 | * currently believed that we do not need to wait for any space in |
5b7d70c6 BD |
2185 | * the TxFIFO. |
2186 | */ | |
1f91b4cc | 2187 | static void dwc2_hsotg_ep0_zlp(struct dwc2_hsotg *hsotg, bool dir_in) |
5b7d70c6 | 2188 | { |
c6f5c050 | 2189 | /* eps_out[0] is used in both directions */ |
fe0b94ab MYK |
2190 | hsotg->eps_out[0]->dir_in = dir_in; |
2191 | hsotg->ep0_state = dir_in ? DWC2_EP0_STATUS_IN : DWC2_EP0_STATUS_OUT; | |
5b7d70c6 | 2192 | |
1f91b4cc | 2193 | dwc2_hsotg_program_zlp(hsotg, hsotg->eps_out[0]); |
5b7d70c6 BD |
2194 | } |
2195 | ||
ec1f9d9f | 2196 | static void dwc2_hsotg_change_ep_iso_parity(struct dwc2_hsotg *hsotg, |
9da51974 | 2197 | u32 epctl_reg) |
ec1f9d9f RB |
2198 | { |
2199 | u32 ctrl; | |
2200 | ||
2201 | ctrl = dwc2_readl(hsotg->regs + epctl_reg); | |
2202 | if (ctrl & DXEPCTL_EOFRNUM) | |
2203 | ctrl |= DXEPCTL_SETEVENFR; | |
2204 | else | |
2205 | ctrl |= DXEPCTL_SETODDFR; | |
2206 | dwc2_writel(ctrl, hsotg->regs + epctl_reg); | |
2207 | } | |
2208 | ||
aa3e8bc8 VA |
2209 | /* |
2210 | * dwc2_gadget_get_xfersize_ddma - get transferred bytes amount from desc | |
2211 | * @hs_ep - The endpoint on which transfer went | |
2212 | * | |
2213 | * Iterate over endpoints descriptor chain and get info on bytes remained | |
2214 | * in DMA descriptors after transfer has completed. Used for non isoc EPs. | |
2215 | */ | |
2216 | static unsigned int dwc2_gadget_get_xfersize_ddma(struct dwc2_hsotg_ep *hs_ep) | |
2217 | { | |
2218 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
2219 | unsigned int bytes_rem = 0; | |
2220 | struct dwc2_dma_desc *desc = hs_ep->desc_list; | |
2221 | int i; | |
2222 | u32 status; | |
2223 | ||
2224 | if (!desc) | |
2225 | return -EINVAL; | |
2226 | ||
2227 | for (i = 0; i < hs_ep->desc_count; ++i) { | |
2228 | status = desc->status; | |
2229 | bytes_rem += status & DEV_DMA_NBYTES_MASK; | |
2230 | ||
2231 | if (status & DEV_DMA_STS_MASK) | |
2232 | dev_err(hsotg->dev, "descriptor %d closed with %x\n", | |
2233 | i, status & DEV_DMA_STS_MASK); | |
2234 | } | |
2235 | ||
2236 | return bytes_rem; | |
2237 | } | |
2238 | ||
5b7d70c6 | 2239 | /** |
1f91b4cc | 2240 | * dwc2_hsotg_handle_outdone - handle receiving OutDone/SetupDone from RXFIFO |
5b7d70c6 BD |
2241 | * @hsotg: The device instance |
2242 | * @epnum: The endpoint received from | |
5b7d70c6 BD |
2243 | * |
2244 | * The RXFIFO has delivered an OutDone event, which means that the data | |
2245 | * transfer for an OUT endpoint has been completed, either by a short | |
2246 | * packet or by the finish of a transfer. | |
8b9bc460 | 2247 | */ |
1f91b4cc | 2248 | static void dwc2_hsotg_handle_outdone(struct dwc2_hsotg *hsotg, int epnum) |
5b7d70c6 | 2249 | { |
95c8bc36 | 2250 | u32 epsize = dwc2_readl(hsotg->regs + DOEPTSIZ(epnum)); |
1f91b4cc FB |
2251 | struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[epnum]; |
2252 | struct dwc2_hsotg_req *hs_req = hs_ep->req; | |
5b7d70c6 | 2253 | struct usb_request *req = &hs_req->req; |
9da51974 | 2254 | unsigned int size_left = DXEPTSIZ_XFERSIZE_GET(epsize); |
5b7d70c6 BD |
2255 | int result = 0; |
2256 | ||
2257 | if (!hs_req) { | |
2258 | dev_dbg(hsotg->dev, "%s: no request active\n", __func__); | |
2259 | return; | |
2260 | } | |
2261 | ||
fe0b94ab MYK |
2262 | if (epnum == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_OUT) { |
2263 | dev_dbg(hsotg->dev, "zlp packet received\n"); | |
1f91b4cc FB |
2264 | dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0); |
2265 | dwc2_hsotg_enqueue_setup(hsotg); | |
fe0b94ab MYK |
2266 | return; |
2267 | } | |
2268 | ||
aa3e8bc8 VA |
2269 | if (using_desc_dma(hsotg)) |
2270 | size_left = dwc2_gadget_get_xfersize_ddma(hs_ep); | |
2271 | ||
5b7d70c6 | 2272 | if (using_dma(hsotg)) { |
9da51974 | 2273 | unsigned int size_done; |
5b7d70c6 | 2274 | |
8b9bc460 LM |
2275 | /* |
2276 | * Calculate the size of the transfer by checking how much | |
5b7d70c6 BD |
2277 | * is left in the endpoint size register and then working it |
2278 | * out from the amount we loaded for the transfer. | |
2279 | * | |
2280 | * We need to do this as DMA pointers are always 32bit aligned | |
2281 | * so may overshoot/undershoot the transfer. | |
2282 | */ | |
2283 | ||
5b7d70c6 BD |
2284 | size_done = hs_ep->size_loaded - size_left; |
2285 | size_done += hs_ep->last_load; | |
2286 | ||
2287 | req->actual = size_done; | |
2288 | } | |
2289 | ||
a33e7136 BD |
2290 | /* if there is more request to do, schedule new transfer */ |
2291 | if (req->actual < req->length && size_left == 0) { | |
1f91b4cc | 2292 | dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true); |
a33e7136 BD |
2293 | return; |
2294 | } | |
2295 | ||
5b7d70c6 BD |
2296 | if (req->actual < req->length && req->short_not_ok) { |
2297 | dev_dbg(hsotg->dev, "%s: got %d/%d (short not ok) => error\n", | |
2298 | __func__, req->actual, req->length); | |
2299 | ||
8b9bc460 LM |
2300 | /* |
2301 | * todo - what should we return here? there's no one else | |
2302 | * even bothering to check the status. | |
2303 | */ | |
5b7d70c6 BD |
2304 | } |
2305 | ||
ef750c71 VA |
2306 | /* DDMA IN status phase will start from StsPhseRcvd interrupt */ |
2307 | if (!using_desc_dma(hsotg) && epnum == 0 && | |
2308 | hsotg->ep0_state == DWC2_EP0_DATA_OUT) { | |
fe0b94ab | 2309 | /* Move to STATUS IN */ |
1f91b4cc | 2310 | dwc2_hsotg_ep0_zlp(hsotg, true); |
fe0b94ab | 2311 | return; |
5b7d70c6 BD |
2312 | } |
2313 | ||
ec1f9d9f RB |
2314 | /* |
2315 | * Slave mode OUT transfers do not go through XferComplete so | |
2316 | * adjust the ISOC parity here. | |
2317 | */ | |
2318 | if (!using_dma(hsotg)) { | |
ec1f9d9f RB |
2319 | if (hs_ep->isochronous && hs_ep->interval == 1) |
2320 | dwc2_hsotg_change_ep_iso_parity(hsotg, DOEPCTL(epnum)); | |
837e9f00 VM |
2321 | else if (hs_ep->isochronous && hs_ep->interval > 1) |
2322 | dwc2_gadget_incr_frame_num(hs_ep); | |
ec1f9d9f RB |
2323 | } |
2324 | ||
1f91b4cc | 2325 | dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, result); |
5b7d70c6 BD |
2326 | } |
2327 | ||
5b7d70c6 | 2328 | /** |
1f91b4cc | 2329 | * dwc2_hsotg_handle_rx - RX FIFO has data |
5b7d70c6 BD |
2330 | * @hsotg: The device instance |
2331 | * | |
2332 | * The IRQ handler has detected that the RX FIFO has some data in it | |
2333 | * that requires processing, so find out what is in there and do the | |
2334 | * appropriate read. | |
2335 | * | |
25985edc | 2336 | * The RXFIFO is a true FIFO, the packets coming out are still in packet |
5b7d70c6 BD |
2337 | * chunks, so if you have x packets received on an endpoint you'll get x |
2338 | * FIFO events delivered, each with a packet's worth of data in it. | |
2339 | * | |
2340 | * When using DMA, we should not be processing events from the RXFIFO | |
2341 | * as the actual data should be sent to the memory directly and we turn | |
2342 | * on the completion interrupts to get notifications of transfer completion. | |
2343 | */ | |
1f91b4cc | 2344 | static void dwc2_hsotg_handle_rx(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 2345 | { |
95c8bc36 | 2346 | u32 grxstsr = dwc2_readl(hsotg->regs + GRXSTSP); |
5b7d70c6 BD |
2347 | u32 epnum, status, size; |
2348 | ||
2349 | WARN_ON(using_dma(hsotg)); | |
2350 | ||
47a1685f DN |
2351 | epnum = grxstsr & GRXSTS_EPNUM_MASK; |
2352 | status = grxstsr & GRXSTS_PKTSTS_MASK; | |
5b7d70c6 | 2353 | |
47a1685f DN |
2354 | size = grxstsr & GRXSTS_BYTECNT_MASK; |
2355 | size >>= GRXSTS_BYTECNT_SHIFT; | |
5b7d70c6 | 2356 | |
d7c747c5 | 2357 | dev_dbg(hsotg->dev, "%s: GRXSTSP=0x%08x (%d@%d)\n", |
9da51974 | 2358 | __func__, grxstsr, size, epnum); |
5b7d70c6 | 2359 | |
47a1685f DN |
2360 | switch ((status & GRXSTS_PKTSTS_MASK) >> GRXSTS_PKTSTS_SHIFT) { |
2361 | case GRXSTS_PKTSTS_GLOBALOUTNAK: | |
2362 | dev_dbg(hsotg->dev, "GLOBALOUTNAK\n"); | |
5b7d70c6 BD |
2363 | break; |
2364 | ||
47a1685f | 2365 | case GRXSTS_PKTSTS_OUTDONE: |
5b7d70c6 | 2366 | dev_dbg(hsotg->dev, "OutDone (Frame=0x%08x)\n", |
1f91b4cc | 2367 | dwc2_hsotg_read_frameno(hsotg)); |
5b7d70c6 BD |
2368 | |
2369 | if (!using_dma(hsotg)) | |
1f91b4cc | 2370 | dwc2_hsotg_handle_outdone(hsotg, epnum); |
5b7d70c6 BD |
2371 | break; |
2372 | ||
47a1685f | 2373 | case GRXSTS_PKTSTS_SETUPDONE: |
5b7d70c6 BD |
2374 | dev_dbg(hsotg->dev, |
2375 | "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n", | |
1f91b4cc | 2376 | dwc2_hsotg_read_frameno(hsotg), |
95c8bc36 | 2377 | dwc2_readl(hsotg->regs + DOEPCTL(0))); |
fe0b94ab | 2378 | /* |
1f91b4cc | 2379 | * Call dwc2_hsotg_handle_outdone here if it was not called from |
fe0b94ab MYK |
2380 | * GRXSTS_PKTSTS_OUTDONE. That is, if the core didn't |
2381 | * generate GRXSTS_PKTSTS_OUTDONE for setup packet. | |
2382 | */ | |
2383 | if (hsotg->ep0_state == DWC2_EP0_SETUP) | |
1f91b4cc | 2384 | dwc2_hsotg_handle_outdone(hsotg, epnum); |
5b7d70c6 BD |
2385 | break; |
2386 | ||
47a1685f | 2387 | case GRXSTS_PKTSTS_OUTRX: |
1f91b4cc | 2388 | dwc2_hsotg_rx_data(hsotg, epnum, size); |
5b7d70c6 BD |
2389 | break; |
2390 | ||
47a1685f | 2391 | case GRXSTS_PKTSTS_SETUPRX: |
5b7d70c6 BD |
2392 | dev_dbg(hsotg->dev, |
2393 | "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n", | |
1f91b4cc | 2394 | dwc2_hsotg_read_frameno(hsotg), |
95c8bc36 | 2395 | dwc2_readl(hsotg->regs + DOEPCTL(0))); |
5b7d70c6 | 2396 | |
fe0b94ab MYK |
2397 | WARN_ON(hsotg->ep0_state != DWC2_EP0_SETUP); |
2398 | ||
1f91b4cc | 2399 | dwc2_hsotg_rx_data(hsotg, epnum, size); |
5b7d70c6 BD |
2400 | break; |
2401 | ||
2402 | default: | |
2403 | dev_warn(hsotg->dev, "%s: unknown status %08x\n", | |
2404 | __func__, grxstsr); | |
2405 | ||
1f91b4cc | 2406 | dwc2_hsotg_dump(hsotg); |
5b7d70c6 BD |
2407 | break; |
2408 | } | |
2409 | } | |
2410 | ||
2411 | /** | |
1f91b4cc | 2412 | * dwc2_hsotg_ep0_mps - turn max packet size into register setting |
5b7d70c6 | 2413 | * @mps: The maximum packet size in bytes. |
8b9bc460 | 2414 | */ |
1f91b4cc | 2415 | static u32 dwc2_hsotg_ep0_mps(unsigned int mps) |
5b7d70c6 BD |
2416 | { |
2417 | switch (mps) { | |
2418 | case 64: | |
94cb8fd6 | 2419 | return D0EPCTL_MPS_64; |
5b7d70c6 | 2420 | case 32: |
94cb8fd6 | 2421 | return D0EPCTL_MPS_32; |
5b7d70c6 | 2422 | case 16: |
94cb8fd6 | 2423 | return D0EPCTL_MPS_16; |
5b7d70c6 | 2424 | case 8: |
94cb8fd6 | 2425 | return D0EPCTL_MPS_8; |
5b7d70c6 BD |
2426 | } |
2427 | ||
2428 | /* bad max packet size, warn and return invalid result */ | |
2429 | WARN_ON(1); | |
2430 | return (u32)-1; | |
2431 | } | |
2432 | ||
2433 | /** | |
1f91b4cc | 2434 | * dwc2_hsotg_set_ep_maxpacket - set endpoint's max-packet field |
5b7d70c6 BD |
2435 | * @hsotg: The driver state. |
2436 | * @ep: The index number of the endpoint | |
2437 | * @mps: The maximum packet size in bytes | |
ee2c40de | 2438 | * @mc: The multicount value |
6fb914d7 | 2439 | * @dir_in: True if direction is in. |
5b7d70c6 BD |
2440 | * |
2441 | * Configure the maximum packet size for the given endpoint, updating | |
2442 | * the hardware control registers to reflect this. | |
2443 | */ | |
1f91b4cc | 2444 | static void dwc2_hsotg_set_ep_maxpacket(struct dwc2_hsotg *hsotg, |
ee2c40de VM |
2445 | unsigned int ep, unsigned int mps, |
2446 | unsigned int mc, unsigned int dir_in) | |
5b7d70c6 | 2447 | { |
1f91b4cc | 2448 | struct dwc2_hsotg_ep *hs_ep; |
5b7d70c6 | 2449 | void __iomem *regs = hsotg->regs; |
5b7d70c6 BD |
2450 | u32 reg; |
2451 | ||
c6f5c050 MYK |
2452 | hs_ep = index_to_ep(hsotg, ep, dir_in); |
2453 | if (!hs_ep) | |
2454 | return; | |
2455 | ||
5b7d70c6 | 2456 | if (ep == 0) { |
ee2c40de VM |
2457 | u32 mps_bytes = mps; |
2458 | ||
5b7d70c6 | 2459 | /* EP0 is a special case */ |
ee2c40de VM |
2460 | mps = dwc2_hsotg_ep0_mps(mps_bytes); |
2461 | if (mps > 3) | |
5b7d70c6 | 2462 | goto bad_mps; |
ee2c40de | 2463 | hs_ep->ep.maxpacket = mps_bytes; |
4fca54aa | 2464 | hs_ep->mc = 1; |
5b7d70c6 | 2465 | } else { |
ee2c40de | 2466 | if (mps > 1024) |
5b7d70c6 | 2467 | goto bad_mps; |
ee2c40de VM |
2468 | hs_ep->mc = mc; |
2469 | if (mc > 3) | |
4fca54aa | 2470 | goto bad_mps; |
ee2c40de | 2471 | hs_ep->ep.maxpacket = mps; |
5b7d70c6 BD |
2472 | } |
2473 | ||
c6f5c050 | 2474 | if (dir_in) { |
95c8bc36 | 2475 | reg = dwc2_readl(regs + DIEPCTL(ep)); |
c6f5c050 | 2476 | reg &= ~DXEPCTL_MPS_MASK; |
ee2c40de | 2477 | reg |= mps; |
95c8bc36 | 2478 | dwc2_writel(reg, regs + DIEPCTL(ep)); |
c6f5c050 | 2479 | } else { |
95c8bc36 | 2480 | reg = dwc2_readl(regs + DOEPCTL(ep)); |
47a1685f | 2481 | reg &= ~DXEPCTL_MPS_MASK; |
ee2c40de | 2482 | reg |= mps; |
95c8bc36 | 2483 | dwc2_writel(reg, regs + DOEPCTL(ep)); |
659ad60c | 2484 | } |
5b7d70c6 BD |
2485 | |
2486 | return; | |
2487 | ||
2488 | bad_mps: | |
2489 | dev_err(hsotg->dev, "ep%d: bad mps of %d\n", ep, mps); | |
2490 | } | |
2491 | ||
9c39ddc6 | 2492 | /** |
1f91b4cc | 2493 | * dwc2_hsotg_txfifo_flush - flush Tx FIFO |
9c39ddc6 AT |
2494 | * @hsotg: The driver state |
2495 | * @idx: The index for the endpoint (0..15) | |
2496 | */ | |
1f91b4cc | 2497 | static void dwc2_hsotg_txfifo_flush(struct dwc2_hsotg *hsotg, unsigned int idx) |
9c39ddc6 | 2498 | { |
95c8bc36 AS |
2499 | dwc2_writel(GRSTCTL_TXFNUM(idx) | GRSTCTL_TXFFLSH, |
2500 | hsotg->regs + GRSTCTL); | |
9c39ddc6 AT |
2501 | |
2502 | /* wait until the fifo is flushed */ | |
79d6b8c5 SA |
2503 | if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL, GRSTCTL_TXFFLSH, 100)) |
2504 | dev_warn(hsotg->dev, "%s: timeout flushing fifo GRSTCTL_TXFFLSH\n", | |
2505 | __func__); | |
9c39ddc6 | 2506 | } |
5b7d70c6 BD |
2507 | |
2508 | /** | |
1f91b4cc | 2509 | * dwc2_hsotg_trytx - check to see if anything needs transmitting |
5b7d70c6 BD |
2510 | * @hsotg: The driver state |
2511 | * @hs_ep: The driver endpoint to check. | |
2512 | * | |
2513 | * Check to see if there is a request that has data to send, and if so | |
2514 | * make an attempt to write data into the FIFO. | |
2515 | */ | |
1f91b4cc | 2516 | static int dwc2_hsotg_trytx(struct dwc2_hsotg *hsotg, |
9da51974 | 2517 | struct dwc2_hsotg_ep *hs_ep) |
5b7d70c6 | 2518 | { |
1f91b4cc | 2519 | struct dwc2_hsotg_req *hs_req = hs_ep->req; |
5b7d70c6 | 2520 | |
afcf4169 RB |
2521 | if (!hs_ep->dir_in || !hs_req) { |
2522 | /** | |
2523 | * if request is not enqueued, we disable interrupts | |
2524 | * for endpoints, excepting ep0 | |
2525 | */ | |
2526 | if (hs_ep->index != 0) | |
1f91b4cc | 2527 | dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, |
9da51974 | 2528 | hs_ep->dir_in, 0); |
5b7d70c6 | 2529 | return 0; |
afcf4169 | 2530 | } |
5b7d70c6 BD |
2531 | |
2532 | if (hs_req->req.actual < hs_req->req.length) { | |
2533 | dev_dbg(hsotg->dev, "trying to write more for ep%d\n", | |
2534 | hs_ep->index); | |
1f91b4cc | 2535 | return dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req); |
5b7d70c6 BD |
2536 | } |
2537 | ||
2538 | return 0; | |
2539 | } | |
2540 | ||
2541 | /** | |
1f91b4cc | 2542 | * dwc2_hsotg_complete_in - complete IN transfer |
5b7d70c6 BD |
2543 | * @hsotg: The device state. |
2544 | * @hs_ep: The endpoint that has just completed. | |
2545 | * | |
2546 | * An IN transfer has been completed, update the transfer's state and then | |
2547 | * call the relevant completion routines. | |
2548 | */ | |
1f91b4cc | 2549 | static void dwc2_hsotg_complete_in(struct dwc2_hsotg *hsotg, |
9da51974 | 2550 | struct dwc2_hsotg_ep *hs_ep) |
5b7d70c6 | 2551 | { |
1f91b4cc | 2552 | struct dwc2_hsotg_req *hs_req = hs_ep->req; |
95c8bc36 | 2553 | u32 epsize = dwc2_readl(hsotg->regs + DIEPTSIZ(hs_ep->index)); |
5b7d70c6 BD |
2554 | int size_left, size_done; |
2555 | ||
2556 | if (!hs_req) { | |
2557 | dev_dbg(hsotg->dev, "XferCompl but no req\n"); | |
2558 | return; | |
2559 | } | |
2560 | ||
d3ca0259 | 2561 | /* Finish ZLP handling for IN EP0 transactions */ |
fe0b94ab MYK |
2562 | if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_IN) { |
2563 | dev_dbg(hsotg->dev, "zlp packet sent\n"); | |
c3b22fe2 RK |
2564 | |
2565 | /* | |
2566 | * While send zlp for DWC2_EP0_STATUS_IN EP direction was | |
2567 | * changed to IN. Change back to complete OUT transfer request | |
2568 | */ | |
2569 | hs_ep->dir_in = 0; | |
2570 | ||
1f91b4cc | 2571 | dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0); |
9e14d0a5 GH |
2572 | if (hsotg->test_mode) { |
2573 | int ret; | |
2574 | ||
1f91b4cc | 2575 | ret = dwc2_hsotg_set_test_mode(hsotg, hsotg->test_mode); |
9e14d0a5 GH |
2576 | if (ret < 0) { |
2577 | dev_dbg(hsotg->dev, "Invalid Test #%d\n", | |
9da51974 | 2578 | hsotg->test_mode); |
1f91b4cc | 2579 | dwc2_hsotg_stall_ep0(hsotg); |
9e14d0a5 GH |
2580 | return; |
2581 | } | |
2582 | } | |
1f91b4cc | 2583 | dwc2_hsotg_enqueue_setup(hsotg); |
d3ca0259 LM |
2584 | return; |
2585 | } | |
2586 | ||
8b9bc460 LM |
2587 | /* |
2588 | * Calculate the size of the transfer by checking how much is left | |
5b7d70c6 BD |
2589 | * in the endpoint size register and then working it out from |
2590 | * the amount we loaded for the transfer. | |
2591 | * | |
2592 | * We do this even for DMA, as the transfer may have incremented | |
2593 | * past the end of the buffer (DMA transfers are always 32bit | |
2594 | * aligned). | |
2595 | */ | |
aa3e8bc8 VA |
2596 | if (using_desc_dma(hsotg)) { |
2597 | size_left = dwc2_gadget_get_xfersize_ddma(hs_ep); | |
2598 | if (size_left < 0) | |
2599 | dev_err(hsotg->dev, "error parsing DDMA results %d\n", | |
2600 | size_left); | |
2601 | } else { | |
2602 | size_left = DXEPTSIZ_XFERSIZE_GET(epsize); | |
2603 | } | |
5b7d70c6 BD |
2604 | |
2605 | size_done = hs_ep->size_loaded - size_left; | |
2606 | size_done += hs_ep->last_load; | |
2607 | ||
2608 | if (hs_req->req.actual != size_done) | |
2609 | dev_dbg(hsotg->dev, "%s: adjusting size done %d => %d\n", | |
2610 | __func__, hs_req->req.actual, size_done); | |
2611 | ||
2612 | hs_req->req.actual = size_done; | |
d3ca0259 LM |
2613 | dev_dbg(hsotg->dev, "req->length:%d req->actual:%d req->zero:%d\n", |
2614 | hs_req->req.length, hs_req->req.actual, hs_req->req.zero); | |
2615 | ||
5b7d70c6 BD |
2616 | if (!size_left && hs_req->req.actual < hs_req->req.length) { |
2617 | dev_dbg(hsotg->dev, "%s trying more for req...\n", __func__); | |
1f91b4cc | 2618 | dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true); |
fe0b94ab MYK |
2619 | return; |
2620 | } | |
2621 | ||
f71b5e25 | 2622 | /* Zlp for all endpoints, for ep0 only in DATA IN stage */ |
8a20fa45 | 2623 | if (hs_ep->send_zlp) { |
1f91b4cc | 2624 | dwc2_hsotg_program_zlp(hsotg, hs_ep); |
8a20fa45 | 2625 | hs_ep->send_zlp = 0; |
f71b5e25 MYK |
2626 | /* transfer will be completed on next complete interrupt */ |
2627 | return; | |
2628 | } | |
2629 | ||
fe0b94ab MYK |
2630 | if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_DATA_IN) { |
2631 | /* Move to STATUS OUT */ | |
1f91b4cc | 2632 | dwc2_hsotg_ep0_zlp(hsotg, false); |
fe0b94ab MYK |
2633 | return; |
2634 | } | |
2635 | ||
1f91b4cc | 2636 | dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0); |
5b7d70c6 BD |
2637 | } |
2638 | ||
32601588 VM |
2639 | /** |
2640 | * dwc2_gadget_read_ep_interrupts - reads interrupts for given ep | |
2641 | * @hsotg: The device state. | |
2642 | * @idx: Index of ep. | |
2643 | * @dir_in: Endpoint direction 1-in 0-out. | |
2644 | * | |
2645 | * Reads for endpoint with given index and direction, by masking | |
2646 | * epint_reg with coresponding mask. | |
2647 | */ | |
2648 | static u32 dwc2_gadget_read_ep_interrupts(struct dwc2_hsotg *hsotg, | |
2649 | unsigned int idx, int dir_in) | |
2650 | { | |
2651 | u32 epmsk_reg = dir_in ? DIEPMSK : DOEPMSK; | |
2652 | u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx); | |
2653 | u32 ints; | |
2654 | u32 mask; | |
2655 | u32 diepempmsk; | |
2656 | ||
2657 | mask = dwc2_readl(hsotg->regs + epmsk_reg); | |
2658 | diepempmsk = dwc2_readl(hsotg->regs + DIEPEMPMSK); | |
2659 | mask |= ((diepempmsk >> idx) & 0x1) ? DIEPMSK_TXFIFOEMPTY : 0; | |
2660 | mask |= DXEPINT_SETUP_RCVD; | |
2661 | ||
2662 | ints = dwc2_readl(hsotg->regs + epint_reg); | |
2663 | ints &= mask; | |
2664 | return ints; | |
2665 | } | |
2666 | ||
bd9971f0 VM |
2667 | /** |
2668 | * dwc2_gadget_handle_ep_disabled - handle DXEPINT_EPDISBLD | |
2669 | * @hs_ep: The endpoint on which interrupt is asserted. | |
2670 | * | |
2671 | * This interrupt indicates that the endpoint has been disabled per the | |
2672 | * application's request. | |
2673 | * | |
2674 | * For IN endpoints flushes txfifo, in case of BULK clears DCTL_CGNPINNAK, | |
2675 | * in case of ISOC completes current request. | |
2676 | * | |
2677 | * For ISOC-OUT endpoints completes expired requests. If there is remaining | |
2678 | * request starts it. | |
2679 | */ | |
2680 | static void dwc2_gadget_handle_ep_disabled(struct dwc2_hsotg_ep *hs_ep) | |
2681 | { | |
2682 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
2683 | struct dwc2_hsotg_req *hs_req; | |
2684 | unsigned char idx = hs_ep->index; | |
2685 | int dir_in = hs_ep->dir_in; | |
2686 | u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx); | |
2687 | int dctl = dwc2_readl(hsotg->regs + DCTL); | |
2688 | ||
2689 | dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__); | |
2690 | ||
2691 | if (dir_in) { | |
2692 | int epctl = dwc2_readl(hsotg->regs + epctl_reg); | |
2693 | ||
2694 | dwc2_hsotg_txfifo_flush(hsotg, hs_ep->fifo_index); | |
2695 | ||
2696 | if (hs_ep->isochronous) { | |
2697 | dwc2_hsotg_complete_in(hsotg, hs_ep); | |
2698 | return; | |
2699 | } | |
2700 | ||
2701 | if ((epctl & DXEPCTL_STALL) && (epctl & DXEPCTL_EPTYPE_BULK)) { | |
2702 | int dctl = dwc2_readl(hsotg->regs + DCTL); | |
2703 | ||
2704 | dctl |= DCTL_CGNPINNAK; | |
2705 | dwc2_writel(dctl, hsotg->regs + DCTL); | |
2706 | } | |
2707 | return; | |
2708 | } | |
2709 | ||
2710 | if (dctl & DCTL_GOUTNAKSTS) { | |
2711 | dctl |= DCTL_CGOUTNAK; | |
2712 | dwc2_writel(dctl, hsotg->regs + DCTL); | |
2713 | } | |
2714 | ||
2715 | if (!hs_ep->isochronous) | |
2716 | return; | |
2717 | ||
2718 | if (list_empty(&hs_ep->queue)) { | |
2719 | dev_dbg(hsotg->dev, "%s: complete_ep 0x%p, ep->queue empty!\n", | |
2720 | __func__, hs_ep); | |
2721 | return; | |
2722 | } | |
2723 | ||
2724 | do { | |
2725 | hs_req = get_ep_head(hs_ep); | |
2726 | if (hs_req) | |
2727 | dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, | |
2728 | -ENODATA); | |
2729 | dwc2_gadget_incr_frame_num(hs_ep); | |
c7c24e7a AP |
2730 | /* Update current frame number value. */ |
2731 | hsotg->frame_number = dwc2_hsotg_read_frameno(hsotg); | |
bd9971f0 VM |
2732 | } while (dwc2_gadget_target_frame_elapsed(hs_ep)); |
2733 | ||
2734 | dwc2_gadget_start_next_request(hs_ep); | |
2735 | } | |
2736 | ||
5321922c VM |
2737 | /** |
2738 | * dwc2_gadget_handle_out_token_ep_disabled - handle DXEPINT_OUTTKNEPDIS | |
6fb914d7 | 2739 | * @ep: The endpoint on which interrupt is asserted. |
5321922c VM |
2740 | * |
2741 | * This is starting point for ISOC-OUT transfer, synchronization done with | |
2742 | * first out token received from host while corresponding EP is disabled. | |
2743 | * | |
2744 | * Device does not know initial frame in which out token will come. For this | |
2745 | * HW generates OUTTKNEPDIS - out token is received while EP is disabled. Upon | |
2746 | * getting this interrupt SW starts calculation for next transfer frame. | |
2747 | */ | |
2748 | static void dwc2_gadget_handle_out_token_ep_disabled(struct dwc2_hsotg_ep *ep) | |
2749 | { | |
2750 | struct dwc2_hsotg *hsotg = ep->parent; | |
2751 | int dir_in = ep->dir_in; | |
2752 | u32 doepmsk; | |
540ccba0 | 2753 | u32 tmp; |
5321922c VM |
2754 | |
2755 | if (dir_in || !ep->isochronous) | |
2756 | return; | |
2757 | ||
540ccba0 VA |
2758 | /* |
2759 | * Store frame in which irq was asserted here, as | |
2760 | * it can change while completing request below. | |
2761 | */ | |
2762 | tmp = dwc2_hsotg_read_frameno(hsotg); | |
2763 | ||
540ccba0 VA |
2764 | if (using_desc_dma(hsotg)) { |
2765 | if (ep->target_frame == TARGET_FRAME_INITIAL) { | |
2766 | /* Start first ISO Out */ | |
2767 | ep->target_frame = tmp; | |
2768 | dwc2_gadget_start_isoc_ddma(ep); | |
2769 | } | |
2770 | return; | |
2771 | } | |
2772 | ||
5321922c VM |
2773 | if (ep->interval > 1 && |
2774 | ep->target_frame == TARGET_FRAME_INITIAL) { | |
2775 | u32 dsts; | |
2776 | u32 ctrl; | |
2777 | ||
2778 | dsts = dwc2_readl(hsotg->regs + DSTS); | |
2779 | ep->target_frame = dwc2_hsotg_read_frameno(hsotg); | |
2780 | dwc2_gadget_incr_frame_num(ep); | |
2781 | ||
2782 | ctrl = dwc2_readl(hsotg->regs + DOEPCTL(ep->index)); | |
2783 | if (ep->target_frame & 0x1) | |
2784 | ctrl |= DXEPCTL_SETODDFR; | |
2785 | else | |
2786 | ctrl |= DXEPCTL_SETEVENFR; | |
2787 | ||
2788 | dwc2_writel(ctrl, hsotg->regs + DOEPCTL(ep->index)); | |
2789 | } | |
2790 | ||
2791 | dwc2_gadget_start_next_request(ep); | |
2792 | doepmsk = dwc2_readl(hsotg->regs + DOEPMSK); | |
2793 | doepmsk &= ~DOEPMSK_OUTTKNEPDISMSK; | |
2794 | dwc2_writel(doepmsk, hsotg->regs + DOEPMSK); | |
2795 | } | |
2796 | ||
2797 | /** | |
38beaec6 JY |
2798 | * dwc2_gadget_handle_nak - handle NAK interrupt |
2799 | * @hs_ep: The endpoint on which interrupt is asserted. | |
2800 | * | |
2801 | * This is starting point for ISOC-IN transfer, synchronization done with | |
2802 | * first IN token received from host while corresponding EP is disabled. | |
2803 | * | |
2804 | * Device does not know when first one token will arrive from host. On first | |
2805 | * token arrival HW generates 2 interrupts: 'in token received while FIFO empty' | |
2806 | * and 'NAK'. NAK interrupt for ISOC-IN means that token has arrived and ZLP was | |
2807 | * sent in response to that as there was no data in FIFO. SW is basing on this | |
2808 | * interrupt to obtain frame in which token has come and then based on the | |
2809 | * interval calculates next frame for transfer. | |
2810 | */ | |
5321922c VM |
2811 | static void dwc2_gadget_handle_nak(struct dwc2_hsotg_ep *hs_ep) |
2812 | { | |
2813 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
2814 | int dir_in = hs_ep->dir_in; | |
729cac69 | 2815 | u32 tmp; |
5321922c VM |
2816 | |
2817 | if (!dir_in || !hs_ep->isochronous) | |
2818 | return; | |
2819 | ||
2820 | if (hs_ep->target_frame == TARGET_FRAME_INITIAL) { | |
540ccba0 | 2821 | |
729cac69 | 2822 | tmp = dwc2_hsotg_read_frameno(hsotg); |
540ccba0 | 2823 | if (using_desc_dma(hsotg)) { |
729cac69 MH |
2824 | hs_ep->target_frame = tmp; |
2825 | dwc2_gadget_incr_frame_num(hs_ep); | |
540ccba0 VA |
2826 | dwc2_gadget_start_isoc_ddma(hs_ep); |
2827 | return; | |
2828 | } | |
2829 | ||
729cac69 | 2830 | hs_ep->target_frame = tmp; |
5321922c VM |
2831 | if (hs_ep->interval > 1) { |
2832 | u32 ctrl = dwc2_readl(hsotg->regs + | |
2833 | DIEPCTL(hs_ep->index)); | |
2834 | if (hs_ep->target_frame & 0x1) | |
2835 | ctrl |= DXEPCTL_SETODDFR; | |
2836 | else | |
2837 | ctrl |= DXEPCTL_SETEVENFR; | |
2838 | ||
2839 | dwc2_writel(ctrl, hsotg->regs + DIEPCTL(hs_ep->index)); | |
2840 | } | |
2841 | ||
2842 | dwc2_hsotg_complete_request(hsotg, hs_ep, | |
2843 | get_ep_head(hs_ep), 0); | |
2844 | } | |
2845 | ||
729cac69 MH |
2846 | if (!using_desc_dma(hsotg)) |
2847 | dwc2_gadget_incr_frame_num(hs_ep); | |
5321922c VM |
2848 | } |
2849 | ||
5b7d70c6 | 2850 | /** |
1f91b4cc | 2851 | * dwc2_hsotg_epint - handle an in/out endpoint interrupt |
5b7d70c6 BD |
2852 | * @hsotg: The driver state |
2853 | * @idx: The index for the endpoint (0..15) | |
2854 | * @dir_in: Set if this is an IN endpoint | |
2855 | * | |
2856 | * Process and clear any interrupt pending for an individual endpoint | |
8b9bc460 | 2857 | */ |
1f91b4cc | 2858 | static void dwc2_hsotg_epint(struct dwc2_hsotg *hsotg, unsigned int idx, |
9da51974 | 2859 | int dir_in) |
5b7d70c6 | 2860 | { |
1f91b4cc | 2861 | struct dwc2_hsotg_ep *hs_ep = index_to_ep(hsotg, idx, dir_in); |
94cb8fd6 LM |
2862 | u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx); |
2863 | u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx); | |
2864 | u32 epsiz_reg = dir_in ? DIEPTSIZ(idx) : DOEPTSIZ(idx); | |
5b7d70c6 | 2865 | u32 ints; |
1479e841 | 2866 | u32 ctrl; |
5b7d70c6 | 2867 | |
32601588 | 2868 | ints = dwc2_gadget_read_ep_interrupts(hsotg, idx, dir_in); |
95c8bc36 | 2869 | ctrl = dwc2_readl(hsotg->regs + epctl_reg); |
5b7d70c6 | 2870 | |
a3395f0d | 2871 | /* Clear endpoint interrupts */ |
95c8bc36 | 2872 | dwc2_writel(ints, hsotg->regs + epint_reg); |
a3395f0d | 2873 | |
c6f5c050 MYK |
2874 | if (!hs_ep) { |
2875 | dev_err(hsotg->dev, "%s:Interrupt for unconfigured ep%d(%s)\n", | |
9da51974 | 2876 | __func__, idx, dir_in ? "in" : "out"); |
c6f5c050 MYK |
2877 | return; |
2878 | } | |
2879 | ||
5b7d70c6 BD |
2880 | dev_dbg(hsotg->dev, "%s: ep%d(%s) DxEPINT=0x%08x\n", |
2881 | __func__, idx, dir_in ? "in" : "out", ints); | |
2882 | ||
b787d755 MYK |
2883 | /* Don't process XferCompl interrupt if it is a setup packet */ |
2884 | if (idx == 0 && (ints & (DXEPINT_SETUP | DXEPINT_SETUP_RCVD))) | |
2885 | ints &= ~DXEPINT_XFERCOMPL; | |
2886 | ||
f0afdb42 VA |
2887 | /* |
2888 | * Don't process XferCompl interrupt in DDMA if EP0 is still in SETUP | |
2889 | * stage and xfercomplete was generated without SETUP phase done | |
2890 | * interrupt. SW should parse received setup packet only after host's | |
2891 | * exit from setup phase of control transfer. | |
2892 | */ | |
2893 | if (using_desc_dma(hsotg) && idx == 0 && !hs_ep->dir_in && | |
2894 | hsotg->ep0_state == DWC2_EP0_SETUP && !(ints & DXEPINT_SETUP)) | |
2895 | ints &= ~DXEPINT_XFERCOMPL; | |
2896 | ||
837e9f00 | 2897 | if (ints & DXEPINT_XFERCOMPL) { |
5b7d70c6 | 2898 | dev_dbg(hsotg->dev, |
47a1685f | 2899 | "%s: XferCompl: DxEPCTL=0x%08x, DXEPTSIZ=%08x\n", |
95c8bc36 AS |
2900 | __func__, dwc2_readl(hsotg->regs + epctl_reg), |
2901 | dwc2_readl(hsotg->regs + epsiz_reg)); | |
5b7d70c6 | 2902 | |
540ccba0 VA |
2903 | /* In DDMA handle isochronous requests separately */ |
2904 | if (using_desc_dma(hsotg) && hs_ep->isochronous) { | |
729cac69 MH |
2905 | /* XferCompl set along with BNA */ |
2906 | if (!(ints & DXEPINT_BNAINTR)) | |
2907 | dwc2_gadget_complete_isoc_request_ddma(hs_ep); | |
540ccba0 VA |
2908 | } else if (dir_in) { |
2909 | /* | |
2910 | * We get OutDone from the FIFO, so we only | |
2911 | * need to look at completing IN requests here | |
2912 | * if operating slave mode | |
2913 | */ | |
837e9f00 VM |
2914 | if (hs_ep->isochronous && hs_ep->interval > 1) |
2915 | dwc2_gadget_incr_frame_num(hs_ep); | |
2916 | ||
1f91b4cc | 2917 | dwc2_hsotg_complete_in(hsotg, hs_ep); |
837e9f00 VM |
2918 | if (ints & DXEPINT_NAKINTRPT) |
2919 | ints &= ~DXEPINT_NAKINTRPT; | |
5b7d70c6 | 2920 | |
c9a64ea8 | 2921 | if (idx == 0 && !hs_ep->req) |
1f91b4cc | 2922 | dwc2_hsotg_enqueue_setup(hsotg); |
5b7d70c6 | 2923 | } else if (using_dma(hsotg)) { |
8b9bc460 LM |
2924 | /* |
2925 | * We're using DMA, we need to fire an OutDone here | |
2926 | * as we ignore the RXFIFO. | |
2927 | */ | |
837e9f00 VM |
2928 | if (hs_ep->isochronous && hs_ep->interval > 1) |
2929 | dwc2_gadget_incr_frame_num(hs_ep); | |
5b7d70c6 | 2930 | |
1f91b4cc | 2931 | dwc2_hsotg_handle_outdone(hsotg, idx); |
5b7d70c6 | 2932 | } |
5b7d70c6 BD |
2933 | } |
2934 | ||
bd9971f0 VM |
2935 | if (ints & DXEPINT_EPDISBLD) |
2936 | dwc2_gadget_handle_ep_disabled(hs_ep); | |
9c39ddc6 | 2937 | |
5321922c VM |
2938 | if (ints & DXEPINT_OUTTKNEPDIS) |
2939 | dwc2_gadget_handle_out_token_ep_disabled(hs_ep); | |
2940 | ||
2941 | if (ints & DXEPINT_NAKINTRPT) | |
2942 | dwc2_gadget_handle_nak(hs_ep); | |
2943 | ||
47a1685f | 2944 | if (ints & DXEPINT_AHBERR) |
5b7d70c6 | 2945 | dev_dbg(hsotg->dev, "%s: AHBErr\n", __func__); |
5b7d70c6 | 2946 | |
47a1685f | 2947 | if (ints & DXEPINT_SETUP) { /* Setup or Timeout */ |
5b7d70c6 BD |
2948 | dev_dbg(hsotg->dev, "%s: Setup/Timeout\n", __func__); |
2949 | ||
2950 | if (using_dma(hsotg) && idx == 0) { | |
8b9bc460 LM |
2951 | /* |
2952 | * this is the notification we've received a | |
5b7d70c6 BD |
2953 | * setup packet. In non-DMA mode we'd get this |
2954 | * from the RXFIFO, instead we need to process | |
8b9bc460 LM |
2955 | * the setup here. |
2956 | */ | |
5b7d70c6 BD |
2957 | |
2958 | if (dir_in) | |
2959 | WARN_ON_ONCE(1); | |
2960 | else | |
1f91b4cc | 2961 | dwc2_hsotg_handle_outdone(hsotg, 0); |
5b7d70c6 | 2962 | } |
5b7d70c6 BD |
2963 | } |
2964 | ||
ef750c71 | 2965 | if (ints & DXEPINT_STSPHSERCVD) { |
9d9a6b07 VA |
2966 | dev_dbg(hsotg->dev, "%s: StsPhseRcvd\n", __func__); |
2967 | ||
9e95a66c MH |
2968 | /* Safety check EP0 state when STSPHSERCVD asserted */ |
2969 | if (hsotg->ep0_state == DWC2_EP0_DATA_OUT) { | |
2970 | /* Move to STATUS IN for DDMA */ | |
2971 | if (using_desc_dma(hsotg)) | |
2972 | dwc2_hsotg_ep0_zlp(hsotg, true); | |
2973 | } | |
2974 | ||
ef750c71 VA |
2975 | } |
2976 | ||
47a1685f | 2977 | if (ints & DXEPINT_BACK2BACKSETUP) |
5b7d70c6 | 2978 | dev_dbg(hsotg->dev, "%s: B2BSetup/INEPNakEff\n", __func__); |
5b7d70c6 | 2979 | |
540ccba0 VA |
2980 | if (ints & DXEPINT_BNAINTR) { |
2981 | dev_dbg(hsotg->dev, "%s: BNA interrupt\n", __func__); | |
540ccba0 | 2982 | if (hs_ep->isochronous) |
729cac69 | 2983 | dwc2_gadget_handle_isoc_bna(hs_ep); |
540ccba0 VA |
2984 | } |
2985 | ||
1479e841 | 2986 | if (dir_in && !hs_ep->isochronous) { |
8b9bc460 | 2987 | /* not sure if this is important, but we'll clear it anyway */ |
26ddef5d | 2988 | if (ints & DXEPINT_INTKNTXFEMP) { |
5b7d70c6 BD |
2989 | dev_dbg(hsotg->dev, "%s: ep%d: INTknTXFEmpMsk\n", |
2990 | __func__, idx); | |
5b7d70c6 BD |
2991 | } |
2992 | ||
2993 | /* this probably means something bad is happening */ | |
26ddef5d | 2994 | if (ints & DXEPINT_INTKNEPMIS) { |
5b7d70c6 BD |
2995 | dev_warn(hsotg->dev, "%s: ep%d: INTknEP\n", |
2996 | __func__, idx); | |
5b7d70c6 | 2997 | } |
10aebc77 BD |
2998 | |
2999 | /* FIFO has space or is empty (see GAHBCFG) */ | |
3000 | if (hsotg->dedicated_fifos && | |
26ddef5d | 3001 | ints & DXEPINT_TXFEMP) { |
10aebc77 BD |
3002 | dev_dbg(hsotg->dev, "%s: ep%d: TxFIFOEmpty\n", |
3003 | __func__, idx); | |
70fa030f | 3004 | if (!using_dma(hsotg)) |
1f91b4cc | 3005 | dwc2_hsotg_trytx(hsotg, hs_ep); |
10aebc77 | 3006 | } |
5b7d70c6 | 3007 | } |
5b7d70c6 BD |
3008 | } |
3009 | ||
3010 | /** | |
1f91b4cc | 3011 | * dwc2_hsotg_irq_enumdone - Handle EnumDone interrupt (enumeration done) |
5b7d70c6 BD |
3012 | * @hsotg: The device state. |
3013 | * | |
3014 | * Handle updating the device settings after the enumeration phase has | |
3015 | * been completed. | |
8b9bc460 | 3016 | */ |
1f91b4cc | 3017 | static void dwc2_hsotg_irq_enumdone(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 3018 | { |
95c8bc36 | 3019 | u32 dsts = dwc2_readl(hsotg->regs + DSTS); |
9b2667f1 | 3020 | int ep0_mps = 0, ep_mps = 8; |
5b7d70c6 | 3021 | |
8b9bc460 LM |
3022 | /* |
3023 | * This should signal the finish of the enumeration phase | |
5b7d70c6 | 3024 | * of the USB handshaking, so we should now know what rate |
8b9bc460 LM |
3025 | * we connected at. |
3026 | */ | |
5b7d70c6 BD |
3027 | |
3028 | dev_dbg(hsotg->dev, "EnumDone (DSTS=0x%08x)\n", dsts); | |
3029 | ||
8b9bc460 LM |
3030 | /* |
3031 | * note, since we're limited by the size of transfer on EP0, and | |
5b7d70c6 | 3032 | * it seems IN transfers must be a even number of packets we do |
8b9bc460 LM |
3033 | * not advertise a 64byte MPS on EP0. |
3034 | */ | |
5b7d70c6 BD |
3035 | |
3036 | /* catch both EnumSpd_FS and EnumSpd_FS48 */ | |
6d76c92c | 3037 | switch ((dsts & DSTS_ENUMSPD_MASK) >> DSTS_ENUMSPD_SHIFT) { |
47a1685f DN |
3038 | case DSTS_ENUMSPD_FS: |
3039 | case DSTS_ENUMSPD_FS48: | |
5b7d70c6 | 3040 | hsotg->gadget.speed = USB_SPEED_FULL; |
5b7d70c6 | 3041 | ep0_mps = EP0_MPS_LIMIT; |
295538ff | 3042 | ep_mps = 1023; |
5b7d70c6 BD |
3043 | break; |
3044 | ||
47a1685f | 3045 | case DSTS_ENUMSPD_HS: |
5b7d70c6 | 3046 | hsotg->gadget.speed = USB_SPEED_HIGH; |
5b7d70c6 | 3047 | ep0_mps = EP0_MPS_LIMIT; |
295538ff | 3048 | ep_mps = 1024; |
5b7d70c6 BD |
3049 | break; |
3050 | ||
47a1685f | 3051 | case DSTS_ENUMSPD_LS: |
5b7d70c6 | 3052 | hsotg->gadget.speed = USB_SPEED_LOW; |
552d940f VM |
3053 | ep0_mps = 8; |
3054 | ep_mps = 8; | |
8b9bc460 LM |
3055 | /* |
3056 | * note, we don't actually support LS in this driver at the | |
5b7d70c6 BD |
3057 | * moment, and the documentation seems to imply that it isn't |
3058 | * supported by the PHYs on some of the devices. | |
3059 | */ | |
3060 | break; | |
3061 | } | |
e538dfda MN |
3062 | dev_info(hsotg->dev, "new device is %s\n", |
3063 | usb_speed_string(hsotg->gadget.speed)); | |
5b7d70c6 | 3064 | |
8b9bc460 LM |
3065 | /* |
3066 | * we should now know the maximum packet size for an | |
3067 | * endpoint, so set the endpoints to a default value. | |
3068 | */ | |
5b7d70c6 BD |
3069 | |
3070 | if (ep0_mps) { | |
3071 | int i; | |
c6f5c050 | 3072 | /* Initialize ep0 for both in and out directions */ |
ee2c40de VM |
3073 | dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 0, 1); |
3074 | dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 0, 0); | |
c6f5c050 MYK |
3075 | for (i = 1; i < hsotg->num_of_eps; i++) { |
3076 | if (hsotg->eps_in[i]) | |
ee2c40de VM |
3077 | dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps, |
3078 | 0, 1); | |
c6f5c050 | 3079 | if (hsotg->eps_out[i]) |
ee2c40de VM |
3080 | dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps, |
3081 | 0, 0); | |
c6f5c050 | 3082 | } |
5b7d70c6 BD |
3083 | } |
3084 | ||
3085 | /* ensure after enumeration our EP0 is active */ | |
3086 | ||
1f91b4cc | 3087 | dwc2_hsotg_enqueue_setup(hsotg); |
5b7d70c6 BD |
3088 | |
3089 | dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n", | |
95c8bc36 AS |
3090 | dwc2_readl(hsotg->regs + DIEPCTL0), |
3091 | dwc2_readl(hsotg->regs + DOEPCTL0)); | |
5b7d70c6 BD |
3092 | } |
3093 | ||
3094 | /** | |
3095 | * kill_all_requests - remove all requests from the endpoint's queue | |
3096 | * @hsotg: The device state. | |
3097 | * @ep: The endpoint the requests may be on. | |
3098 | * @result: The result code to use. | |
5b7d70c6 BD |
3099 | * |
3100 | * Go through the requests on the given endpoint and mark them | |
3101 | * completed with the given result code. | |
3102 | */ | |
941fcce4 | 3103 | static void kill_all_requests(struct dwc2_hsotg *hsotg, |
1f91b4cc | 3104 | struct dwc2_hsotg_ep *ep, |
6b448af4 | 3105 | int result) |
5b7d70c6 | 3106 | { |
1f91b4cc | 3107 | struct dwc2_hsotg_req *req, *treq; |
9da51974 | 3108 | unsigned int size; |
5b7d70c6 | 3109 | |
6b448af4 | 3110 | ep->req = NULL; |
5b7d70c6 | 3111 | |
6b448af4 | 3112 | list_for_each_entry_safe(req, treq, &ep->queue, queue) |
1f91b4cc | 3113 | dwc2_hsotg_complete_request(hsotg, ep, req, |
9da51974 | 3114 | result); |
6b448af4 | 3115 | |
b203d0a2 RB |
3116 | if (!hsotg->dedicated_fifos) |
3117 | return; | |
ad674a15 | 3118 | size = (dwc2_readl(hsotg->regs + DTXFSTS(ep->fifo_index)) & 0xffff) * 4; |
b203d0a2 | 3119 | if (size < ep->fifo_size) |
1f91b4cc | 3120 | dwc2_hsotg_txfifo_flush(hsotg, ep->fifo_index); |
5b7d70c6 BD |
3121 | } |
3122 | ||
5b7d70c6 | 3123 | /** |
1f91b4cc | 3124 | * dwc2_hsotg_disconnect - disconnect service |
5b7d70c6 BD |
3125 | * @hsotg: The device state. |
3126 | * | |
5e891342 LM |
3127 | * The device has been disconnected. Remove all current |
3128 | * transactions and signal the gadget driver that this | |
3129 | * has happened. | |
8b9bc460 | 3130 | */ |
1f91b4cc | 3131 | void dwc2_hsotg_disconnect(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 3132 | { |
9da51974 | 3133 | unsigned int ep; |
5b7d70c6 | 3134 | |
4ace06e8 MS |
3135 | if (!hsotg->connected) |
3136 | return; | |
3137 | ||
3138 | hsotg->connected = 0; | |
9e14d0a5 | 3139 | hsotg->test_mode = 0; |
c6f5c050 MYK |
3140 | |
3141 | for (ep = 0; ep < hsotg->num_of_eps; ep++) { | |
3142 | if (hsotg->eps_in[ep]) | |
3143 | kill_all_requests(hsotg, hsotg->eps_in[ep], | |
9da51974 | 3144 | -ESHUTDOWN); |
c6f5c050 MYK |
3145 | if (hsotg->eps_out[ep]) |
3146 | kill_all_requests(hsotg, hsotg->eps_out[ep], | |
9da51974 | 3147 | -ESHUTDOWN); |
c6f5c050 | 3148 | } |
5b7d70c6 BD |
3149 | |
3150 | call_gadget(hsotg, disconnect); | |
065d3931 | 3151 | hsotg->lx_state = DWC2_L3; |
ce2b21a4 JS |
3152 | |
3153 | usb_gadget_set_state(&hsotg->gadget, USB_STATE_NOTATTACHED); | |
5b7d70c6 BD |
3154 | } |
3155 | ||
3156 | /** | |
1f91b4cc | 3157 | * dwc2_hsotg_irq_fifoempty - TX FIFO empty interrupt handler |
5b7d70c6 BD |
3158 | * @hsotg: The device state: |
3159 | * @periodic: True if this is a periodic FIFO interrupt | |
3160 | */ | |
1f91b4cc | 3161 | static void dwc2_hsotg_irq_fifoempty(struct dwc2_hsotg *hsotg, bool periodic) |
5b7d70c6 | 3162 | { |
1f91b4cc | 3163 | struct dwc2_hsotg_ep *ep; |
5b7d70c6 BD |
3164 | int epno, ret; |
3165 | ||
3166 | /* look through for any more data to transmit */ | |
b3f489b2 | 3167 | for (epno = 0; epno < hsotg->num_of_eps; epno++) { |
c6f5c050 MYK |
3168 | ep = index_to_ep(hsotg, epno, 1); |
3169 | ||
3170 | if (!ep) | |
3171 | continue; | |
5b7d70c6 BD |
3172 | |
3173 | if (!ep->dir_in) | |
3174 | continue; | |
3175 | ||
3176 | if ((periodic && !ep->periodic) || | |
3177 | (!periodic && ep->periodic)) | |
3178 | continue; | |
3179 | ||
1f91b4cc | 3180 | ret = dwc2_hsotg_trytx(hsotg, ep); |
5b7d70c6 BD |
3181 | if (ret < 0) |
3182 | break; | |
3183 | } | |
3184 | } | |
3185 | ||
5b7d70c6 | 3186 | /* IRQ flags which will trigger a retry around the IRQ loop */ |
47a1685f DN |
3187 | #define IRQ_RETRY_MASK (GINTSTS_NPTXFEMP | \ |
3188 | GINTSTS_PTXFEMP | \ | |
3189 | GINTSTS_RXFLVL) | |
5b7d70c6 | 3190 | |
8b9bc460 | 3191 | /** |
1f91b4cc | 3192 | * dwc2_hsotg_core_init - issue softreset to the core |
8b9bc460 | 3193 | * @hsotg: The device state |
6fb914d7 | 3194 | * @is_usb_reset: Usb resetting flag |
8b9bc460 LM |
3195 | * |
3196 | * Issue a soft reset to the core, and await the core finishing it. | |
3197 | */ | |
1f91b4cc | 3198 | void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg, |
9da51974 | 3199 | bool is_usb_reset) |
308d734e | 3200 | { |
1ee6903b | 3201 | u32 intmsk; |
643cc4de | 3202 | u32 val; |
ecd9a7ad | 3203 | u32 usbcfg; |
79c3b5bb | 3204 | u32 dcfg = 0; |
643cc4de | 3205 | |
5390d438 MYK |
3206 | /* Kill any ep0 requests as controller will be reinitialized */ |
3207 | kill_all_requests(hsotg, hsotg->eps_out[0], -ECONNRESET); | |
3208 | ||
643cc4de | 3209 | if (!is_usb_reset) |
6e6360b6 | 3210 | if (dwc2_core_reset(hsotg, true)) |
86de4895 | 3211 | return; |
308d734e LM |
3212 | |
3213 | /* | |
3214 | * we must now enable ep0 ready for host detection and then | |
3215 | * set configuration. | |
3216 | */ | |
3217 | ||
ecd9a7ad PR |
3218 | /* keep other bits untouched (so e.g. forced modes are not lost) */ |
3219 | usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); | |
3220 | usbcfg &= ~(GUSBCFG_TOUTCAL_MASK | GUSBCFG_PHYIF16 | GUSBCFG_SRPCAP | | |
ca02954a | 3221 | GUSBCFG_HNPCAP | GUSBCFG_USBTRDTIM_MASK); |
ecd9a7ad | 3222 | |
79c3b5bb | 3223 | if (hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS && |
38e9002b VM |
3224 | (hsotg->params.speed == DWC2_SPEED_PARAM_FULL || |
3225 | hsotg->params.speed == DWC2_SPEED_PARAM_LOW)) { | |
79c3b5bb VA |
3226 | /* FS/LS Dedicated Transceiver Interface */ |
3227 | usbcfg |= GUSBCFG_PHYSEL; | |
3228 | } else { | |
3229 | /* set the PLL on, remove the HNP/SRP and set the PHY */ | |
3230 | val = (hsotg->phyif == GUSBCFG_PHYIF8) ? 9 : 5; | |
3231 | usbcfg |= hsotg->phyif | GUSBCFG_TOUTCAL(7) | | |
3232 | (val << GUSBCFG_USBTRDTIM_SHIFT); | |
3233 | } | |
ecd9a7ad | 3234 | dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); |
308d734e | 3235 | |
1f91b4cc | 3236 | dwc2_hsotg_init_fifo(hsotg); |
308d734e | 3237 | |
643cc4de | 3238 | if (!is_usb_reset) |
abd064a1 | 3239 | dwc2_set_bit(hsotg->regs + DCTL, DCTL_SFTDISCON); |
308d734e | 3240 | |
79c3b5bb | 3241 | dcfg |= DCFG_EPMISCNT(1); |
38e9002b VM |
3242 | |
3243 | switch (hsotg->params.speed) { | |
3244 | case DWC2_SPEED_PARAM_LOW: | |
3245 | dcfg |= DCFG_DEVSPD_LS; | |
3246 | break; | |
3247 | case DWC2_SPEED_PARAM_FULL: | |
79c3b5bb VA |
3248 | if (hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS) |
3249 | dcfg |= DCFG_DEVSPD_FS48; | |
3250 | else | |
3251 | dcfg |= DCFG_DEVSPD_FS; | |
38e9002b VM |
3252 | break; |
3253 | default: | |
79c3b5bb VA |
3254 | dcfg |= DCFG_DEVSPD_HS; |
3255 | } | |
38e9002b | 3256 | |
b43ebc96 GT |
3257 | if (hsotg->params.ipg_isoc_en) |
3258 | dcfg |= DCFG_IPG_ISOC_SUPPORDED; | |
3259 | ||
79c3b5bb | 3260 | dwc2_writel(dcfg, hsotg->regs + DCFG); |
308d734e LM |
3261 | |
3262 | /* Clear any pending OTG interrupts */ | |
95c8bc36 | 3263 | dwc2_writel(0xffffffff, hsotg->regs + GOTGINT); |
308d734e LM |
3264 | |
3265 | /* Clear any pending interrupts */ | |
95c8bc36 | 3266 | dwc2_writel(0xffffffff, hsotg->regs + GINTSTS); |
1ee6903b | 3267 | intmsk = GINTSTS_ERLYSUSP | GINTSTS_SESSREQINT | |
47a1685f | 3268 | GINTSTS_GOUTNAKEFF | GINTSTS_GINNAKEFF | |
1ee6903b GH |
3269 | GINTSTS_USBRST | GINTSTS_RESETDET | |
3270 | GINTSTS_ENUMDONE | GINTSTS_OTGINT | | |
376f0401 SA |
3271 | GINTSTS_USBSUSP | GINTSTS_WKUPINT | |
3272 | GINTSTS_LPMTRANRCVD; | |
f4736701 VA |
3273 | |
3274 | if (!using_desc_dma(hsotg)) | |
3275 | intmsk |= GINTSTS_INCOMPL_SOIN | GINTSTS_INCOMPL_SOOUT; | |
1ee6903b | 3276 | |
95832c00 | 3277 | if (!hsotg->params.external_id_pin_ctl) |
1ee6903b GH |
3278 | intmsk |= GINTSTS_CONIDSTSCHNG; |
3279 | ||
3280 | dwc2_writel(intmsk, hsotg->regs + GINTMSK); | |
308d734e | 3281 | |
a5c18f11 | 3282 | if (using_dma(hsotg)) { |
95c8bc36 | 3283 | dwc2_writel(GAHBCFG_GLBL_INTR_EN | GAHBCFG_DMA_EN | |
d1ac8c80 | 3284 | hsotg->params.ahbcfg, |
95c8bc36 | 3285 | hsotg->regs + GAHBCFG); |
a5c18f11 VA |
3286 | |
3287 | /* Set DDMA mode support in the core if needed */ | |
3288 | if (using_desc_dma(hsotg)) | |
abd064a1 | 3289 | dwc2_set_bit(hsotg->regs + DCFG, DCFG_DESCDMA_EN); |
a5c18f11 VA |
3290 | |
3291 | } else { | |
95c8bc36 AS |
3292 | dwc2_writel(((hsotg->dedicated_fifos) ? |
3293 | (GAHBCFG_NP_TXF_EMP_LVL | | |
3294 | GAHBCFG_P_TXF_EMP_LVL) : 0) | | |
3295 | GAHBCFG_GLBL_INTR_EN, hsotg->regs + GAHBCFG); | |
a5c18f11 | 3296 | } |
308d734e LM |
3297 | |
3298 | /* | |
8acc8296 RB |
3299 | * If INTknTXFEmpMsk is enabled, it's important to disable ep interrupts |
3300 | * when we have no data to transfer. Otherwise we get being flooded by | |
3301 | * interrupts. | |
308d734e LM |
3302 | */ |
3303 | ||
95c8bc36 | 3304 | dwc2_writel(((hsotg->dedicated_fifos && !using_dma(hsotg)) ? |
6ff2e832 | 3305 | DIEPMSK_TXFIFOEMPTY | DIEPMSK_INTKNTXFEMPMSK : 0) | |
47a1685f | 3306 | DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK | |
837e9f00 | 3307 | DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK, |
47a1685f | 3308 | hsotg->regs + DIEPMSK); |
308d734e LM |
3309 | |
3310 | /* | |
3311 | * don't need XferCompl, we get that from RXFIFO in slave mode. In | |
9d9a6b07 | 3312 | * DMA mode we may need this and StsPhseRcvd. |
308d734e | 3313 | */ |
9d9a6b07 VA |
3314 | dwc2_writel((using_dma(hsotg) ? (DIEPMSK_XFERCOMPLMSK | |
3315 | DOEPMSK_STSPHSERCVDMSK) : 0) | | |
47a1685f | 3316 | DOEPMSK_EPDISBLDMSK | DOEPMSK_AHBERRMSK | |
9d9a6b07 | 3317 | DOEPMSK_SETUPMSK, |
47a1685f | 3318 | hsotg->regs + DOEPMSK); |
308d734e | 3319 | |
ec01f0b2 | 3320 | /* Enable BNA interrupt for DDMA */ |
37981e00 | 3321 | if (using_desc_dma(hsotg)) { |
abd064a1 | 3322 | dwc2_set_bit(hsotg->regs + DOEPMSK, DOEPMSK_BNAMSK); |
37981e00 MH |
3323 | dwc2_set_bit(hsotg->regs + DIEPMSK, DIEPMSK_BNAININTRMSK); |
3324 | } | |
ec01f0b2 | 3325 | |
95c8bc36 | 3326 | dwc2_writel(0, hsotg->regs + DAINTMSK); |
308d734e LM |
3327 | |
3328 | dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n", | |
95c8bc36 AS |
3329 | dwc2_readl(hsotg->regs + DIEPCTL0), |
3330 | dwc2_readl(hsotg->regs + DOEPCTL0)); | |
308d734e LM |
3331 | |
3332 | /* enable in and out endpoint interrupts */ | |
1f91b4cc | 3333 | dwc2_hsotg_en_gsint(hsotg, GINTSTS_OEPINT | GINTSTS_IEPINT); |
308d734e LM |
3334 | |
3335 | /* | |
3336 | * Enable the RXFIFO when in slave mode, as this is how we collect | |
3337 | * the data. In DMA mode, we get events from the FIFO but also | |
3338 | * things we cannot process, so do not use it. | |
3339 | */ | |
3340 | if (!using_dma(hsotg)) | |
1f91b4cc | 3341 | dwc2_hsotg_en_gsint(hsotg, GINTSTS_RXFLVL); |
308d734e LM |
3342 | |
3343 | /* Enable interrupts for EP0 in and out */ | |
1f91b4cc FB |
3344 | dwc2_hsotg_ctrl_epint(hsotg, 0, 0, 1); |
3345 | dwc2_hsotg_ctrl_epint(hsotg, 0, 1, 1); | |
308d734e | 3346 | |
643cc4de | 3347 | if (!is_usb_reset) { |
abd064a1 | 3348 | dwc2_set_bit(hsotg->regs + DCTL, DCTL_PWRONPRGDONE); |
643cc4de | 3349 | udelay(10); /* see openiboot */ |
abd064a1 | 3350 | dwc2_clear_bit(hsotg->regs + DCTL, DCTL_PWRONPRGDONE); |
643cc4de | 3351 | } |
308d734e | 3352 | |
95c8bc36 | 3353 | dev_dbg(hsotg->dev, "DCTL=0x%08x\n", dwc2_readl(hsotg->regs + DCTL)); |
308d734e LM |
3354 | |
3355 | /* | |
94cb8fd6 | 3356 | * DxEPCTL_USBActEp says RO in manual, but seems to be set by |
308d734e LM |
3357 | * writing to the EPCTL register.. |
3358 | */ | |
3359 | ||
3360 | /* set to read 1 8byte packet */ | |
95c8bc36 | 3361 | dwc2_writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) | |
47a1685f | 3362 | DXEPTSIZ_XFERSIZE(8), hsotg->regs + DOEPTSIZ0); |
308d734e | 3363 | |
95c8bc36 | 3364 | dwc2_writel(dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) | |
47a1685f DN |
3365 | DXEPCTL_CNAK | DXEPCTL_EPENA | |
3366 | DXEPCTL_USBACTEP, | |
94cb8fd6 | 3367 | hsotg->regs + DOEPCTL0); |
308d734e LM |
3368 | |
3369 | /* enable, but don't activate EP0in */ | |
95c8bc36 | 3370 | dwc2_writel(dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) | |
47a1685f | 3371 | DXEPCTL_USBACTEP, hsotg->regs + DIEPCTL0); |
308d734e | 3372 | |
308d734e | 3373 | /* clear global NAKs */ |
643cc4de GH |
3374 | val = DCTL_CGOUTNAK | DCTL_CGNPINNAK; |
3375 | if (!is_usb_reset) | |
3376 | val |= DCTL_SFTDISCON; | |
abd064a1 | 3377 | dwc2_set_bit(hsotg->regs + DCTL, val); |
308d734e | 3378 | |
21b03405 SA |
3379 | /* configure the core to support LPM */ |
3380 | dwc2_gadget_init_lpm(hsotg); | |
3381 | ||
308d734e LM |
3382 | /* must be at-least 3ms to allow bus to see disconnect */ |
3383 | mdelay(3); | |
3384 | ||
065d3931 | 3385 | hsotg->lx_state = DWC2_L0; |
755d7395 VM |
3386 | |
3387 | dwc2_hsotg_enqueue_setup(hsotg); | |
3388 | ||
3389 | dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n", | |
3390 | dwc2_readl(hsotg->regs + DIEPCTL0), | |
3391 | dwc2_readl(hsotg->regs + DOEPCTL0)); | |
ad38dc5d MS |
3392 | } |
3393 | ||
1f91b4cc | 3394 | static void dwc2_hsotg_core_disconnect(struct dwc2_hsotg *hsotg) |
ad38dc5d MS |
3395 | { |
3396 | /* set the soft-disconnect bit */ | |
abd064a1 | 3397 | dwc2_set_bit(hsotg->regs + DCTL, DCTL_SFTDISCON); |
ad38dc5d | 3398 | } |
ac3c81f3 | 3399 | |
1f91b4cc | 3400 | void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg) |
ad38dc5d | 3401 | { |
308d734e | 3402 | /* remove the soft-disconnect and let's go */ |
abd064a1 | 3403 | dwc2_clear_bit(hsotg->regs + DCTL, DCTL_SFTDISCON); |
308d734e LM |
3404 | } |
3405 | ||
381fc8f8 VM |
3406 | /** |
3407 | * dwc2_gadget_handle_incomplete_isoc_in - handle incomplete ISO IN Interrupt. | |
3408 | * @hsotg: The device state: | |
3409 | * | |
3410 | * This interrupt indicates one of the following conditions occurred while | |
3411 | * transmitting an ISOC transaction. | |
3412 | * - Corrupted IN Token for ISOC EP. | |
3413 | * - Packet not complete in FIFO. | |
3414 | * | |
3415 | * The following actions will be taken: | |
3416 | * - Determine the EP | |
3417 | * - Disable EP; when 'Endpoint Disabled' interrupt is received Flush FIFO | |
3418 | */ | |
3419 | static void dwc2_gadget_handle_incomplete_isoc_in(struct dwc2_hsotg *hsotg) | |
3420 | { | |
3421 | struct dwc2_hsotg_ep *hs_ep; | |
3422 | u32 epctrl; | |
1b4977c7 | 3423 | u32 daintmsk; |
381fc8f8 VM |
3424 | u32 idx; |
3425 | ||
3426 | dev_dbg(hsotg->dev, "Incomplete isoc in interrupt received:\n"); | |
3427 | ||
1b4977c7 RK |
3428 | daintmsk = dwc2_readl(hsotg->regs + DAINTMSK); |
3429 | ||
d5d5f079 | 3430 | for (idx = 1; idx < hsotg->num_of_eps; idx++) { |
381fc8f8 | 3431 | hs_ep = hsotg->eps_in[idx]; |
1b4977c7 RK |
3432 | /* Proceed only unmasked ISOC EPs */ |
3433 | if (!hs_ep->isochronous || (BIT(idx) & ~daintmsk)) | |
3434 | continue; | |
3435 | ||
381fc8f8 | 3436 | epctrl = dwc2_readl(hsotg->regs + DIEPCTL(idx)); |
1b4977c7 | 3437 | if ((epctrl & DXEPCTL_EPENA) && |
381fc8f8 VM |
3438 | dwc2_gadget_target_frame_elapsed(hs_ep)) { |
3439 | epctrl |= DXEPCTL_SNAK; | |
3440 | epctrl |= DXEPCTL_EPDIS; | |
3441 | dwc2_writel(epctrl, hsotg->regs + DIEPCTL(idx)); | |
3442 | } | |
3443 | } | |
3444 | ||
3445 | /* Clear interrupt */ | |
3446 | dwc2_writel(GINTSTS_INCOMPL_SOIN, hsotg->regs + GINTSTS); | |
3447 | } | |
3448 | ||
3449 | /** | |
3450 | * dwc2_gadget_handle_incomplete_isoc_out - handle incomplete ISO OUT Interrupt | |
3451 | * @hsotg: The device state: | |
3452 | * | |
3453 | * This interrupt indicates one of the following conditions occurred while | |
3454 | * transmitting an ISOC transaction. | |
3455 | * - Corrupted OUT Token for ISOC EP. | |
3456 | * - Packet not complete in FIFO. | |
3457 | * | |
3458 | * The following actions will be taken: | |
3459 | * - Determine the EP | |
3460 | * - Set DCTL_SGOUTNAK and unmask GOUTNAKEFF if target frame elapsed. | |
3461 | */ | |
3462 | static void dwc2_gadget_handle_incomplete_isoc_out(struct dwc2_hsotg *hsotg) | |
3463 | { | |
3464 | u32 gintsts; | |
3465 | u32 gintmsk; | |
689efb26 | 3466 | u32 daintmsk; |
381fc8f8 VM |
3467 | u32 epctrl; |
3468 | struct dwc2_hsotg_ep *hs_ep; | |
3469 | int idx; | |
3470 | ||
3471 | dev_dbg(hsotg->dev, "%s: GINTSTS_INCOMPL_SOOUT\n", __func__); | |
3472 | ||
689efb26 RK |
3473 | daintmsk = dwc2_readl(hsotg->regs + DAINTMSK); |
3474 | daintmsk >>= DAINT_OUTEP_SHIFT; | |
3475 | ||
d5d5f079 | 3476 | for (idx = 1; idx < hsotg->num_of_eps; idx++) { |
381fc8f8 | 3477 | hs_ep = hsotg->eps_out[idx]; |
689efb26 RK |
3478 | /* Proceed only unmasked ISOC EPs */ |
3479 | if (!hs_ep->isochronous || (BIT(idx) & ~daintmsk)) | |
3480 | continue; | |
3481 | ||
381fc8f8 | 3482 | epctrl = dwc2_readl(hsotg->regs + DOEPCTL(idx)); |
689efb26 | 3483 | if ((epctrl & DXEPCTL_EPENA) && |
381fc8f8 VM |
3484 | dwc2_gadget_target_frame_elapsed(hs_ep)) { |
3485 | /* Unmask GOUTNAKEFF interrupt */ | |
3486 | gintmsk = dwc2_readl(hsotg->regs + GINTMSK); | |
3487 | gintmsk |= GINTSTS_GOUTNAKEFF; | |
3488 | dwc2_writel(gintmsk, hsotg->regs + GINTMSK); | |
3489 | ||
3490 | gintsts = dwc2_readl(hsotg->regs + GINTSTS); | |
689efb26 | 3491 | if (!(gintsts & GINTSTS_GOUTNAKEFF)) { |
abd064a1 | 3492 | dwc2_set_bit(hsotg->regs + DCTL, DCTL_SGOUTNAK); |
689efb26 RK |
3493 | break; |
3494 | } | |
381fc8f8 VM |
3495 | } |
3496 | } | |
3497 | ||
3498 | /* Clear interrupt */ | |
3499 | dwc2_writel(GINTSTS_INCOMPL_SOOUT, hsotg->regs + GINTSTS); | |
3500 | } | |
3501 | ||
5b7d70c6 | 3502 | /** |
1f91b4cc | 3503 | * dwc2_hsotg_irq - handle device interrupt |
5b7d70c6 BD |
3504 | * @irq: The IRQ number triggered |
3505 | * @pw: The pw value when registered the handler. | |
3506 | */ | |
1f91b4cc | 3507 | static irqreturn_t dwc2_hsotg_irq(int irq, void *pw) |
5b7d70c6 | 3508 | { |
941fcce4 | 3509 | struct dwc2_hsotg *hsotg = pw; |
5b7d70c6 BD |
3510 | int retry_count = 8; |
3511 | u32 gintsts; | |
3512 | u32 gintmsk; | |
3513 | ||
ee3de8d7 VM |
3514 | if (!dwc2_is_device_mode(hsotg)) |
3515 | return IRQ_NONE; | |
3516 | ||
5ad1d316 | 3517 | spin_lock(&hsotg->lock); |
5b7d70c6 | 3518 | irq_retry: |
95c8bc36 AS |
3519 | gintsts = dwc2_readl(hsotg->regs + GINTSTS); |
3520 | gintmsk = dwc2_readl(hsotg->regs + GINTMSK); | |
5b7d70c6 BD |
3521 | |
3522 | dev_dbg(hsotg->dev, "%s: %08x %08x (%08x) retry %d\n", | |
3523 | __func__, gintsts, gintsts & gintmsk, gintmsk, retry_count); | |
3524 | ||
3525 | gintsts &= gintmsk; | |
3526 | ||
8fc37b82 MYK |
3527 | if (gintsts & GINTSTS_RESETDET) { |
3528 | dev_dbg(hsotg->dev, "%s: USBRstDet\n", __func__); | |
3529 | ||
3530 | dwc2_writel(GINTSTS_RESETDET, hsotg->regs + GINTSTS); | |
3531 | ||
3532 | /* This event must be used only if controller is suspended */ | |
3533 | if (hsotg->lx_state == DWC2_L2) { | |
41ba9b9b | 3534 | dwc2_exit_partial_power_down(hsotg, true); |
8fc37b82 MYK |
3535 | hsotg->lx_state = DWC2_L0; |
3536 | } | |
3537 | } | |
3538 | ||
3539 | if (gintsts & (GINTSTS_USBRST | GINTSTS_RESETDET)) { | |
8fc37b82 MYK |
3540 | u32 usb_status = dwc2_readl(hsotg->regs + GOTGCTL); |
3541 | u32 connected = hsotg->connected; | |
3542 | ||
3543 | dev_dbg(hsotg->dev, "%s: USBRst\n", __func__); | |
3544 | dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n", | |
3545 | dwc2_readl(hsotg->regs + GNPTXSTS)); | |
3546 | ||
3547 | dwc2_writel(GINTSTS_USBRST, hsotg->regs + GINTSTS); | |
3548 | ||
3549 | /* Report disconnection if it is not already done. */ | |
3550 | dwc2_hsotg_disconnect(hsotg); | |
3551 | ||
307bc11f | 3552 | /* Reset device address to zero */ |
abd064a1 | 3553 | dwc2_clear_bit(hsotg->regs + DCFG, DCFG_DEVADDR_MASK); |
307bc11f | 3554 | |
8fc37b82 MYK |
3555 | if (usb_status & GOTGCTL_BSESVLD && connected) |
3556 | dwc2_hsotg_core_init_disconnected(hsotg, true); | |
3557 | } | |
3558 | ||
47a1685f | 3559 | if (gintsts & GINTSTS_ENUMDONE) { |
95c8bc36 | 3560 | dwc2_writel(GINTSTS_ENUMDONE, hsotg->regs + GINTSTS); |
a3395f0d | 3561 | |
1f91b4cc | 3562 | dwc2_hsotg_irq_enumdone(hsotg); |
5b7d70c6 BD |
3563 | } |
3564 | ||
47a1685f | 3565 | if (gintsts & (GINTSTS_OEPINT | GINTSTS_IEPINT)) { |
95c8bc36 AS |
3566 | u32 daint = dwc2_readl(hsotg->regs + DAINT); |
3567 | u32 daintmsk = dwc2_readl(hsotg->regs + DAINTMSK); | |
7e804650 | 3568 | u32 daint_out, daint_in; |
5b7d70c6 BD |
3569 | int ep; |
3570 | ||
7e804650 | 3571 | daint &= daintmsk; |
47a1685f DN |
3572 | daint_out = daint >> DAINT_OUTEP_SHIFT; |
3573 | daint_in = daint & ~(daint_out << DAINT_OUTEP_SHIFT); | |
7e804650 | 3574 | |
5b7d70c6 BD |
3575 | dev_dbg(hsotg->dev, "%s: daint=%08x\n", __func__, daint); |
3576 | ||
cec87f1d MYK |
3577 | for (ep = 0; ep < hsotg->num_of_eps && daint_out; |
3578 | ep++, daint_out >>= 1) { | |
5b7d70c6 | 3579 | if (daint_out & 1) |
1f91b4cc | 3580 | dwc2_hsotg_epint(hsotg, ep, 0); |
5b7d70c6 BD |
3581 | } |
3582 | ||
cec87f1d MYK |
3583 | for (ep = 0; ep < hsotg->num_of_eps && daint_in; |
3584 | ep++, daint_in >>= 1) { | |
5b7d70c6 | 3585 | if (daint_in & 1) |
1f91b4cc | 3586 | dwc2_hsotg_epint(hsotg, ep, 1); |
5b7d70c6 | 3587 | } |
5b7d70c6 BD |
3588 | } |
3589 | ||
5b7d70c6 BD |
3590 | /* check both FIFOs */ |
3591 | ||
47a1685f | 3592 | if (gintsts & GINTSTS_NPTXFEMP) { |
5b7d70c6 BD |
3593 | dev_dbg(hsotg->dev, "NPTxFEmp\n"); |
3594 | ||
8b9bc460 LM |
3595 | /* |
3596 | * Disable the interrupt to stop it happening again | |
5b7d70c6 | 3597 | * unless one of these endpoint routines decides that |
8b9bc460 LM |
3598 | * it needs re-enabling |
3599 | */ | |
5b7d70c6 | 3600 | |
1f91b4cc FB |
3601 | dwc2_hsotg_disable_gsint(hsotg, GINTSTS_NPTXFEMP); |
3602 | dwc2_hsotg_irq_fifoempty(hsotg, false); | |
5b7d70c6 BD |
3603 | } |
3604 | ||
47a1685f | 3605 | if (gintsts & GINTSTS_PTXFEMP) { |
5b7d70c6 BD |
3606 | dev_dbg(hsotg->dev, "PTxFEmp\n"); |
3607 | ||
94cb8fd6 | 3608 | /* See note in GINTSTS_NPTxFEmp */ |
5b7d70c6 | 3609 | |
1f91b4cc FB |
3610 | dwc2_hsotg_disable_gsint(hsotg, GINTSTS_PTXFEMP); |
3611 | dwc2_hsotg_irq_fifoempty(hsotg, true); | |
5b7d70c6 BD |
3612 | } |
3613 | ||
47a1685f | 3614 | if (gintsts & GINTSTS_RXFLVL) { |
8b9bc460 LM |
3615 | /* |
3616 | * note, since GINTSTS_RxFLvl doubles as FIFO-not-empty, | |
1f91b4cc | 3617 | * we need to retry dwc2_hsotg_handle_rx if this is still |
8b9bc460 LM |
3618 | * set. |
3619 | */ | |
5b7d70c6 | 3620 | |
1f91b4cc | 3621 | dwc2_hsotg_handle_rx(hsotg); |
5b7d70c6 BD |
3622 | } |
3623 | ||
47a1685f | 3624 | if (gintsts & GINTSTS_ERLYSUSP) { |
94cb8fd6 | 3625 | dev_dbg(hsotg->dev, "GINTSTS_ErlySusp\n"); |
95c8bc36 | 3626 | dwc2_writel(GINTSTS_ERLYSUSP, hsotg->regs + GINTSTS); |
5b7d70c6 BD |
3627 | } |
3628 | ||
8b9bc460 LM |
3629 | /* |
3630 | * these next two seem to crop-up occasionally causing the core | |
5b7d70c6 | 3631 | * to shutdown the USB transfer, so try clearing them and logging |
8b9bc460 LM |
3632 | * the occurrence. |
3633 | */ | |
5b7d70c6 | 3634 | |
47a1685f | 3635 | if (gintsts & GINTSTS_GOUTNAKEFF) { |
837e9f00 VM |
3636 | u8 idx; |
3637 | u32 epctrl; | |
3638 | u32 gintmsk; | |
d8484552 | 3639 | u32 daintmsk; |
837e9f00 VM |
3640 | struct dwc2_hsotg_ep *hs_ep; |
3641 | ||
d8484552 RK |
3642 | daintmsk = dwc2_readl(hsotg->regs + DAINTMSK); |
3643 | daintmsk >>= DAINT_OUTEP_SHIFT; | |
837e9f00 VM |
3644 | /* Mask this interrupt */ |
3645 | gintmsk = dwc2_readl(hsotg->regs + GINTMSK); | |
3646 | gintmsk &= ~GINTSTS_GOUTNAKEFF; | |
3647 | dwc2_writel(gintmsk, hsotg->regs + GINTMSK); | |
3648 | ||
3649 | dev_dbg(hsotg->dev, "GOUTNakEff triggered\n"); | |
d5d5f079 | 3650 | for (idx = 1; idx < hsotg->num_of_eps; idx++) { |
837e9f00 | 3651 | hs_ep = hsotg->eps_out[idx]; |
d8484552 RK |
3652 | /* Proceed only unmasked ISOC EPs */ |
3653 | if (!hs_ep->isochronous || (BIT(idx) & ~daintmsk)) | |
3654 | continue; | |
3655 | ||
837e9f00 VM |
3656 | epctrl = dwc2_readl(hsotg->regs + DOEPCTL(idx)); |
3657 | ||
d8484552 | 3658 | if (epctrl & DXEPCTL_EPENA) { |
837e9f00 VM |
3659 | epctrl |= DXEPCTL_SNAK; |
3660 | epctrl |= DXEPCTL_EPDIS; | |
3661 | dwc2_writel(epctrl, hsotg->regs + DOEPCTL(idx)); | |
3662 | } | |
3663 | } | |
a3395f0d | 3664 | |
837e9f00 | 3665 | /* This interrupt bit is cleared in DXEPINT_EPDISBLD handler */ |
5b7d70c6 BD |
3666 | } |
3667 | ||
47a1685f | 3668 | if (gintsts & GINTSTS_GINNAKEFF) { |
5b7d70c6 BD |
3669 | dev_info(hsotg->dev, "GINNakEff triggered\n"); |
3670 | ||
abd064a1 | 3671 | dwc2_set_bit(hsotg->regs + DCTL, DCTL_CGNPINNAK); |
a3395f0d | 3672 | |
1f91b4cc | 3673 | dwc2_hsotg_dump(hsotg); |
5b7d70c6 BD |
3674 | } |
3675 | ||
381fc8f8 VM |
3676 | if (gintsts & GINTSTS_INCOMPL_SOIN) |
3677 | dwc2_gadget_handle_incomplete_isoc_in(hsotg); | |
ec1f9d9f | 3678 | |
381fc8f8 VM |
3679 | if (gintsts & GINTSTS_INCOMPL_SOOUT) |
3680 | dwc2_gadget_handle_incomplete_isoc_out(hsotg); | |
ec1f9d9f | 3681 | |
8b9bc460 LM |
3682 | /* |
3683 | * if we've had fifo events, we should try and go around the | |
3684 | * loop again to see if there's any point in returning yet. | |
3685 | */ | |
5b7d70c6 BD |
3686 | |
3687 | if (gintsts & IRQ_RETRY_MASK && --retry_count > 0) | |
77b6200e | 3688 | goto irq_retry; |
5b7d70c6 | 3689 | |
5ad1d316 LM |
3690 | spin_unlock(&hsotg->lock); |
3691 | ||
5b7d70c6 BD |
3692 | return IRQ_HANDLED; |
3693 | } | |
3694 | ||
a4f82771 VA |
3695 | static void dwc2_hsotg_ep_stop_xfr(struct dwc2_hsotg *hsotg, |
3696 | struct dwc2_hsotg_ep *hs_ep) | |
3697 | { | |
3698 | u32 epctrl_reg; | |
3699 | u32 epint_reg; | |
3700 | ||
3701 | epctrl_reg = hs_ep->dir_in ? DIEPCTL(hs_ep->index) : | |
3702 | DOEPCTL(hs_ep->index); | |
3703 | epint_reg = hs_ep->dir_in ? DIEPINT(hs_ep->index) : | |
3704 | DOEPINT(hs_ep->index); | |
3705 | ||
3706 | dev_dbg(hsotg->dev, "%s: stopping transfer on %s\n", __func__, | |
3707 | hs_ep->name); | |
3708 | ||
3709 | if (hs_ep->dir_in) { | |
3710 | if (hsotg->dedicated_fifos || hs_ep->periodic) { | |
abd064a1 | 3711 | dwc2_set_bit(hsotg->regs + epctrl_reg, DXEPCTL_SNAK); |
a4f82771 VA |
3712 | /* Wait for Nak effect */ |
3713 | if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg, | |
3714 | DXEPINT_INEPNAKEFF, 100)) | |
3715 | dev_warn(hsotg->dev, | |
3716 | "%s: timeout DIEPINT.NAKEFF\n", | |
3717 | __func__); | |
3718 | } else { | |
abd064a1 | 3719 | dwc2_set_bit(hsotg->regs + DCTL, DCTL_SGNPINNAK); |
a4f82771 VA |
3720 | /* Wait for Nak effect */ |
3721 | if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS, | |
3722 | GINTSTS_GINNAKEFF, 100)) | |
3723 | dev_warn(hsotg->dev, | |
3724 | "%s: timeout GINTSTS.GINNAKEFF\n", | |
3725 | __func__); | |
3726 | } | |
3727 | } else { | |
3728 | if (!(dwc2_readl(hsotg->regs + GINTSTS) & GINTSTS_GOUTNAKEFF)) | |
abd064a1 | 3729 | dwc2_set_bit(hsotg->regs + DCTL, DCTL_SGOUTNAK); |
a4f82771 VA |
3730 | |
3731 | /* Wait for global nak to take effect */ | |
3732 | if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS, | |
3733 | GINTSTS_GOUTNAKEFF, 100)) | |
3734 | dev_warn(hsotg->dev, "%s: timeout GINTSTS.GOUTNAKEFF\n", | |
3735 | __func__); | |
3736 | } | |
3737 | ||
3738 | /* Disable ep */ | |
abd064a1 | 3739 | dwc2_set_bit(hsotg->regs + epctrl_reg, DXEPCTL_EPDIS | DXEPCTL_SNAK); |
a4f82771 VA |
3740 | |
3741 | /* Wait for ep to be disabled */ | |
3742 | if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg, DXEPINT_EPDISBLD, 100)) | |
3743 | dev_warn(hsotg->dev, | |
3744 | "%s: timeout DOEPCTL.EPDisable\n", __func__); | |
3745 | ||
3746 | /* Clear EPDISBLD interrupt */ | |
abd064a1 | 3747 | dwc2_set_bit(hsotg->regs + epint_reg, DXEPINT_EPDISBLD); |
a4f82771 VA |
3748 | |
3749 | if (hs_ep->dir_in) { | |
3750 | unsigned short fifo_index; | |
3751 | ||
3752 | if (hsotg->dedicated_fifos || hs_ep->periodic) | |
3753 | fifo_index = hs_ep->fifo_index; | |
3754 | else | |
3755 | fifo_index = 0; | |
3756 | ||
3757 | /* Flush TX FIFO */ | |
3758 | dwc2_flush_tx_fifo(hsotg, fifo_index); | |
3759 | ||
3760 | /* Clear Global In NP NAK in Shared FIFO for non periodic ep */ | |
3761 | if (!hsotg->dedicated_fifos && !hs_ep->periodic) | |
abd064a1 | 3762 | dwc2_set_bit(hsotg->regs + DCTL, DCTL_CGNPINNAK); |
a4f82771 VA |
3763 | |
3764 | } else { | |
3765 | /* Remove global NAKs */ | |
abd064a1 | 3766 | dwc2_set_bit(hsotg->regs + DCTL, DCTL_CGOUTNAK); |
a4f82771 VA |
3767 | } |
3768 | } | |
3769 | ||
5b7d70c6 | 3770 | /** |
1f91b4cc | 3771 | * dwc2_hsotg_ep_enable - enable the given endpoint |
5b7d70c6 BD |
3772 | * @ep: The USB endpint to configure |
3773 | * @desc: The USB endpoint descriptor to configure with. | |
3774 | * | |
3775 | * This is called from the USB gadget code's usb_ep_enable(). | |
8b9bc460 | 3776 | */ |
1f91b4cc | 3777 | static int dwc2_hsotg_ep_enable(struct usb_ep *ep, |
9da51974 | 3778 | const struct usb_endpoint_descriptor *desc) |
5b7d70c6 | 3779 | { |
1f91b4cc | 3780 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 3781 | struct dwc2_hsotg *hsotg = hs_ep->parent; |
5b7d70c6 | 3782 | unsigned long flags; |
ca4c55ad | 3783 | unsigned int index = hs_ep->index; |
5b7d70c6 BD |
3784 | u32 epctrl_reg; |
3785 | u32 epctrl; | |
3786 | u32 mps; | |
ee2c40de | 3787 | u32 mc; |
837e9f00 | 3788 | u32 mask; |
ca4c55ad MYK |
3789 | unsigned int dir_in; |
3790 | unsigned int i, val, size; | |
19c190f9 | 3791 | int ret = 0; |
729cac69 | 3792 | unsigned char ep_type; |
5b7d70c6 BD |
3793 | |
3794 | dev_dbg(hsotg->dev, | |
3795 | "%s: ep %s: a 0x%02x, attr 0x%02x, mps 0x%04x, intr %d\n", | |
3796 | __func__, ep->name, desc->bEndpointAddress, desc->bmAttributes, | |
3797 | desc->wMaxPacketSize, desc->bInterval); | |
3798 | ||
3799 | /* not to be called for EP0 */ | |
8c3d6092 VA |
3800 | if (index == 0) { |
3801 | dev_err(hsotg->dev, "%s: called for EP 0\n", __func__); | |
3802 | return -EINVAL; | |
3803 | } | |
5b7d70c6 BD |
3804 | |
3805 | dir_in = (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) ? 1 : 0; | |
3806 | if (dir_in != hs_ep->dir_in) { | |
3807 | dev_err(hsotg->dev, "%s: direction mismatch!\n", __func__); | |
3808 | return -EINVAL; | |
3809 | } | |
3810 | ||
729cac69 | 3811 | ep_type = desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK; |
29cc8897 | 3812 | mps = usb_endpoint_maxp(desc); |
ee2c40de | 3813 | mc = usb_endpoint_maxp_mult(desc); |
5b7d70c6 | 3814 | |
729cac69 MH |
3815 | /* ISOC IN in DDMA supported bInterval up to 10 */ |
3816 | if (using_desc_dma(hsotg) && ep_type == USB_ENDPOINT_XFER_ISOC && | |
3817 | dir_in && desc->bInterval > 10) { | |
3818 | dev_err(hsotg->dev, | |
3819 | "%s: ISOC IN, DDMA: bInterval>10 not supported!\n", __func__); | |
3820 | return -EINVAL; | |
3821 | } | |
3822 | ||
3823 | /* High bandwidth ISOC OUT in DDMA not supported */ | |
3824 | if (using_desc_dma(hsotg) && ep_type == USB_ENDPOINT_XFER_ISOC && | |
3825 | !dir_in && mc > 1) { | |
3826 | dev_err(hsotg->dev, | |
3827 | "%s: ISOC OUT, DDMA: HB not supported!\n", __func__); | |
3828 | return -EINVAL; | |
3829 | } | |
3830 | ||
1f91b4cc | 3831 | /* note, we handle this here instead of dwc2_hsotg_set_ep_maxpacket */ |
5b7d70c6 | 3832 | |
94cb8fd6 | 3833 | epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index); |
95c8bc36 | 3834 | epctrl = dwc2_readl(hsotg->regs + epctrl_reg); |
5b7d70c6 BD |
3835 | |
3836 | dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x from 0x%08x\n", | |
3837 | __func__, epctrl, epctrl_reg); | |
3838 | ||
5f54c54b | 3839 | /* Allocate DMA descriptor chain for non-ctrl endpoints */ |
9383e084 VM |
3840 | if (using_desc_dma(hsotg) && !hs_ep->desc_list) { |
3841 | hs_ep->desc_list = dmam_alloc_coherent(hsotg->dev, | |
5f54c54b VA |
3842 | MAX_DMA_DESC_NUM_GENERIC * |
3843 | sizeof(struct dwc2_dma_desc), | |
86e881e7 | 3844 | &hs_ep->desc_list_dma, GFP_ATOMIC); |
5f54c54b VA |
3845 | if (!hs_ep->desc_list) { |
3846 | ret = -ENOMEM; | |
3847 | goto error2; | |
3848 | } | |
3849 | } | |
3850 | ||
22258f49 | 3851 | spin_lock_irqsave(&hsotg->lock, flags); |
5b7d70c6 | 3852 | |
47a1685f DN |
3853 | epctrl &= ~(DXEPCTL_EPTYPE_MASK | DXEPCTL_MPS_MASK); |
3854 | epctrl |= DXEPCTL_MPS(mps); | |
5b7d70c6 | 3855 | |
8b9bc460 LM |
3856 | /* |
3857 | * mark the endpoint as active, otherwise the core may ignore | |
3858 | * transactions entirely for this endpoint | |
3859 | */ | |
47a1685f | 3860 | epctrl |= DXEPCTL_USBACTEP; |
5b7d70c6 | 3861 | |
5b7d70c6 | 3862 | /* update the endpoint state */ |
ee2c40de | 3863 | dwc2_hsotg_set_ep_maxpacket(hsotg, hs_ep->index, mps, mc, dir_in); |
5b7d70c6 BD |
3864 | |
3865 | /* default, set to non-periodic */ | |
1479e841 | 3866 | hs_ep->isochronous = 0; |
5b7d70c6 | 3867 | hs_ep->periodic = 0; |
a18ed7b0 | 3868 | hs_ep->halted = 0; |
1479e841 | 3869 | hs_ep->interval = desc->bInterval; |
4fca54aa | 3870 | |
729cac69 | 3871 | switch (ep_type) { |
5b7d70c6 | 3872 | case USB_ENDPOINT_XFER_ISOC: |
47a1685f DN |
3873 | epctrl |= DXEPCTL_EPTYPE_ISO; |
3874 | epctrl |= DXEPCTL_SETEVENFR; | |
1479e841 | 3875 | hs_ep->isochronous = 1; |
142bd33f | 3876 | hs_ep->interval = 1 << (desc->bInterval - 1); |
837e9f00 | 3877 | hs_ep->target_frame = TARGET_FRAME_INITIAL; |
ab7d2192 | 3878 | hs_ep->next_desc = 0; |
729cac69 | 3879 | hs_ep->compl_desc = 0; |
837e9f00 | 3880 | if (dir_in) { |
1479e841 | 3881 | hs_ep->periodic = 1; |
837e9f00 VM |
3882 | mask = dwc2_readl(hsotg->regs + DIEPMSK); |
3883 | mask |= DIEPMSK_NAKMSK; | |
3884 | dwc2_writel(mask, hsotg->regs + DIEPMSK); | |
3885 | } else { | |
3886 | mask = dwc2_readl(hsotg->regs + DOEPMSK); | |
3887 | mask |= DOEPMSK_OUTTKNEPDISMSK; | |
3888 | dwc2_writel(mask, hsotg->regs + DOEPMSK); | |
3889 | } | |
1479e841 | 3890 | break; |
5b7d70c6 BD |
3891 | |
3892 | case USB_ENDPOINT_XFER_BULK: | |
47a1685f | 3893 | epctrl |= DXEPCTL_EPTYPE_BULK; |
5b7d70c6 BD |
3894 | break; |
3895 | ||
3896 | case USB_ENDPOINT_XFER_INT: | |
b203d0a2 | 3897 | if (dir_in) |
5b7d70c6 | 3898 | hs_ep->periodic = 1; |
5b7d70c6 | 3899 | |
142bd33f VM |
3900 | if (hsotg->gadget.speed == USB_SPEED_HIGH) |
3901 | hs_ep->interval = 1 << (desc->bInterval - 1); | |
3902 | ||
47a1685f | 3903 | epctrl |= DXEPCTL_EPTYPE_INTERRUPT; |
5b7d70c6 BD |
3904 | break; |
3905 | ||
3906 | case USB_ENDPOINT_XFER_CONTROL: | |
47a1685f | 3907 | epctrl |= DXEPCTL_EPTYPE_CONTROL; |
5b7d70c6 BD |
3908 | break; |
3909 | } | |
3910 | ||
8b9bc460 LM |
3911 | /* |
3912 | * if the hardware has dedicated fifos, we must give each IN EP | |
10aebc77 BD |
3913 | * a unique tx-fifo even if it is non-periodic. |
3914 | */ | |
21f3bb52 | 3915 | if (dir_in && hsotg->dedicated_fifos) { |
ca4c55ad MYK |
3916 | u32 fifo_index = 0; |
3917 | u32 fifo_size = UINT_MAX; | |
9da51974 JY |
3918 | |
3919 | size = hs_ep->ep.maxpacket * hs_ep->mc; | |
5f2196bd | 3920 | for (i = 1; i < hsotg->num_of_eps; ++i) { |
9da51974 | 3921 | if (hsotg->fifo_map & (1 << i)) |
b203d0a2 | 3922 | continue; |
95c8bc36 | 3923 | val = dwc2_readl(hsotg->regs + DPTXFSIZN(i)); |
9da51974 | 3924 | val = (val >> FIFOSIZE_DEPTH_SHIFT) * 4; |
b203d0a2 RB |
3925 | if (val < size) |
3926 | continue; | |
ca4c55ad MYK |
3927 | /* Search for smallest acceptable fifo */ |
3928 | if (val < fifo_size) { | |
3929 | fifo_size = val; | |
3930 | fifo_index = i; | |
3931 | } | |
b203d0a2 | 3932 | } |
ca4c55ad | 3933 | if (!fifo_index) { |
5f2196bd MYK |
3934 | dev_err(hsotg->dev, |
3935 | "%s: No suitable fifo found\n", __func__); | |
b585a48b | 3936 | ret = -ENOMEM; |
5f54c54b | 3937 | goto error1; |
b585a48b | 3938 | } |
ca4c55ad MYK |
3939 | hsotg->fifo_map |= 1 << fifo_index; |
3940 | epctrl |= DXEPCTL_TXFNUM(fifo_index); | |
3941 | hs_ep->fifo_index = fifo_index; | |
3942 | hs_ep->fifo_size = fifo_size; | |
b203d0a2 | 3943 | } |
10aebc77 | 3944 | |
5b7d70c6 | 3945 | /* for non control endpoints, set PID to D0 */ |
837e9f00 | 3946 | if (index && !hs_ep->isochronous) |
47a1685f | 3947 | epctrl |= DXEPCTL_SETD0PID; |
5b7d70c6 | 3948 | |
5295322a AP |
3949 | /* WA for Full speed ISOC IN in DDMA mode. |
3950 | * By Clear NAK status of EP, core will send ZLP | |
3951 | * to IN token and assert NAK interrupt relying | |
3952 | * on TxFIFO status only | |
3953 | */ | |
3954 | ||
3955 | if (hsotg->gadget.speed == USB_SPEED_FULL && | |
3956 | hs_ep->isochronous && dir_in) { | |
3957 | /* The WA applies only to core versions from 2.72a | |
3958 | * to 4.00a (including both). Also for FS_IOT_1.00a | |
3959 | * and HS_IOT_1.00a. | |
3960 | */ | |
3961 | u32 gsnpsid = dwc2_readl(hsotg->regs + GSNPSID); | |
3962 | ||
3963 | if ((gsnpsid >= DWC2_CORE_REV_2_72a && | |
3964 | gsnpsid <= DWC2_CORE_REV_4_00a) || | |
3965 | gsnpsid == DWC2_FS_IOT_REV_1_00a || | |
3966 | gsnpsid == DWC2_HS_IOT_REV_1_00a) | |
3967 | epctrl |= DXEPCTL_CNAK; | |
3968 | } | |
3969 | ||
5b7d70c6 BD |
3970 | dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n", |
3971 | __func__, epctrl); | |
3972 | ||
95c8bc36 | 3973 | dwc2_writel(epctrl, hsotg->regs + epctrl_reg); |
5b7d70c6 | 3974 | dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x\n", |
95c8bc36 | 3975 | __func__, dwc2_readl(hsotg->regs + epctrl_reg)); |
5b7d70c6 BD |
3976 | |
3977 | /* enable the endpoint interrupt */ | |
1f91b4cc | 3978 | dwc2_hsotg_ctrl_epint(hsotg, index, dir_in, 1); |
5b7d70c6 | 3979 | |
5f54c54b | 3980 | error1: |
22258f49 | 3981 | spin_unlock_irqrestore(&hsotg->lock, flags); |
5f54c54b VA |
3982 | |
3983 | error2: | |
3984 | if (ret && using_desc_dma(hsotg) && hs_ep->desc_list) { | |
9383e084 | 3985 | dmam_free_coherent(hsotg->dev, MAX_DMA_DESC_NUM_GENERIC * |
5f54c54b VA |
3986 | sizeof(struct dwc2_dma_desc), |
3987 | hs_ep->desc_list, hs_ep->desc_list_dma); | |
3988 | hs_ep->desc_list = NULL; | |
3989 | } | |
3990 | ||
19c190f9 | 3991 | return ret; |
5b7d70c6 BD |
3992 | } |
3993 | ||
8b9bc460 | 3994 | /** |
1f91b4cc | 3995 | * dwc2_hsotg_ep_disable - disable given endpoint |
8b9bc460 LM |
3996 | * @ep: The endpoint to disable. |
3997 | */ | |
1f91b4cc | 3998 | static int dwc2_hsotg_ep_disable(struct usb_ep *ep) |
5b7d70c6 | 3999 | { |
1f91b4cc | 4000 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 4001 | struct dwc2_hsotg *hsotg = hs_ep->parent; |
5b7d70c6 BD |
4002 | int dir_in = hs_ep->dir_in; |
4003 | int index = hs_ep->index; | |
4004 | unsigned long flags; | |
4005 | u32 epctrl_reg; | |
4006 | u32 ctrl; | |
4007 | ||
1e011293 | 4008 | dev_dbg(hsotg->dev, "%s(ep %p)\n", __func__, ep); |
5b7d70c6 | 4009 | |
c6f5c050 | 4010 | if (ep == &hsotg->eps_out[0]->ep) { |
5b7d70c6 BD |
4011 | dev_err(hsotg->dev, "%s: called for ep0\n", __func__); |
4012 | return -EINVAL; | |
9b481092 JS |
4013 | } |
4014 | ||
4015 | if (hsotg->op_state != OTG_STATE_B_PERIPHERAL) { | |
4016 | dev_err(hsotg->dev, "%s: called in host mode?\n", __func__); | |
4017 | return -EINVAL; | |
5b7d70c6 BD |
4018 | } |
4019 | ||
94cb8fd6 | 4020 | epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index); |
5b7d70c6 | 4021 | |
5ad1d316 | 4022 | spin_lock_irqsave(&hsotg->lock, flags); |
5b7d70c6 | 4023 | |
95c8bc36 | 4024 | ctrl = dwc2_readl(hsotg->regs + epctrl_reg); |
a4f82771 VA |
4025 | |
4026 | if (ctrl & DXEPCTL_EPENA) | |
4027 | dwc2_hsotg_ep_stop_xfr(hsotg, hs_ep); | |
4028 | ||
47a1685f DN |
4029 | ctrl &= ~DXEPCTL_EPENA; |
4030 | ctrl &= ~DXEPCTL_USBACTEP; | |
4031 | ctrl |= DXEPCTL_SNAK; | |
5b7d70c6 BD |
4032 | |
4033 | dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl); | |
95c8bc36 | 4034 | dwc2_writel(ctrl, hsotg->regs + epctrl_reg); |
5b7d70c6 BD |
4035 | |
4036 | /* disable endpoint interrupts */ | |
1f91b4cc | 4037 | dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 0); |
5b7d70c6 | 4038 | |
1141ea01 MYK |
4039 | /* terminate all requests with shutdown */ |
4040 | kill_all_requests(hsotg, hs_ep, -ESHUTDOWN); | |
4041 | ||
1c07b20e RB |
4042 | hsotg->fifo_map &= ~(1 << hs_ep->fifo_index); |
4043 | hs_ep->fifo_index = 0; | |
4044 | hs_ep->fifo_size = 0; | |
4045 | ||
22258f49 | 4046 | spin_unlock_irqrestore(&hsotg->lock, flags); |
5b7d70c6 BD |
4047 | return 0; |
4048 | } | |
4049 | ||
4050 | /** | |
4051 | * on_list - check request is on the given endpoint | |
4052 | * @ep: The endpoint to check. | |
4053 | * @test: The request to test if it is on the endpoint. | |
8b9bc460 | 4054 | */ |
1f91b4cc | 4055 | static bool on_list(struct dwc2_hsotg_ep *ep, struct dwc2_hsotg_req *test) |
5b7d70c6 | 4056 | { |
1f91b4cc | 4057 | struct dwc2_hsotg_req *req, *treq; |
5b7d70c6 BD |
4058 | |
4059 | list_for_each_entry_safe(req, treq, &ep->queue, queue) { | |
4060 | if (req == test) | |
4061 | return true; | |
4062 | } | |
4063 | ||
4064 | return false; | |
4065 | } | |
4066 | ||
8b9bc460 | 4067 | /** |
1f91b4cc | 4068 | * dwc2_hsotg_ep_dequeue - dequeue given endpoint |
8b9bc460 LM |
4069 | * @ep: The endpoint to dequeue. |
4070 | * @req: The request to be removed from a queue. | |
4071 | */ | |
1f91b4cc | 4072 | static int dwc2_hsotg_ep_dequeue(struct usb_ep *ep, struct usb_request *req) |
5b7d70c6 | 4073 | { |
1f91b4cc FB |
4074 | struct dwc2_hsotg_req *hs_req = our_req(req); |
4075 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); | |
941fcce4 | 4076 | struct dwc2_hsotg *hs = hs_ep->parent; |
5b7d70c6 BD |
4077 | unsigned long flags; |
4078 | ||
1e011293 | 4079 | dev_dbg(hs->dev, "ep_dequeue(%p,%p)\n", ep, req); |
5b7d70c6 | 4080 | |
22258f49 | 4081 | spin_lock_irqsave(&hs->lock, flags); |
5b7d70c6 BD |
4082 | |
4083 | if (!on_list(hs_ep, hs_req)) { | |
22258f49 | 4084 | spin_unlock_irqrestore(&hs->lock, flags); |
5b7d70c6 BD |
4085 | return -EINVAL; |
4086 | } | |
4087 | ||
c524dd5f MYK |
4088 | /* Dequeue already started request */ |
4089 | if (req == &hs_ep->req->req) | |
4090 | dwc2_hsotg_ep_stop_xfr(hs, hs_ep); | |
4091 | ||
1f91b4cc | 4092 | dwc2_hsotg_complete_request(hs, hs_ep, hs_req, -ECONNRESET); |
22258f49 | 4093 | spin_unlock_irqrestore(&hs->lock, flags); |
5b7d70c6 BD |
4094 | |
4095 | return 0; | |
4096 | } | |
4097 | ||
8b9bc460 | 4098 | /** |
1f91b4cc | 4099 | * dwc2_hsotg_ep_sethalt - set halt on a given endpoint |
8b9bc460 LM |
4100 | * @ep: The endpoint to set halt. |
4101 | * @value: Set or unset the halt. | |
51da43b5 VA |
4102 | * @now: If true, stall the endpoint now. Otherwise return -EAGAIN if |
4103 | * the endpoint is busy processing requests. | |
4104 | * | |
4105 | * We need to stall the endpoint immediately if request comes from set_feature | |
4106 | * protocol command handler. | |
8b9bc460 | 4107 | */ |
51da43b5 | 4108 | static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now) |
5b7d70c6 | 4109 | { |
1f91b4cc | 4110 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 4111 | struct dwc2_hsotg *hs = hs_ep->parent; |
5b7d70c6 | 4112 | int index = hs_ep->index; |
5b7d70c6 BD |
4113 | u32 epreg; |
4114 | u32 epctl; | |
9c39ddc6 | 4115 | u32 xfertype; |
5b7d70c6 BD |
4116 | |
4117 | dev_info(hs->dev, "%s(ep %p %s, %d)\n", __func__, ep, ep->name, value); | |
4118 | ||
c9f721b2 RB |
4119 | if (index == 0) { |
4120 | if (value) | |
1f91b4cc | 4121 | dwc2_hsotg_stall_ep0(hs); |
c9f721b2 RB |
4122 | else |
4123 | dev_warn(hs->dev, | |
4124 | "%s: can't clear halt on ep0\n", __func__); | |
4125 | return 0; | |
4126 | } | |
4127 | ||
15186f10 VA |
4128 | if (hs_ep->isochronous) { |
4129 | dev_err(hs->dev, "%s is Isochronous Endpoint\n", ep->name); | |
4130 | return -EINVAL; | |
4131 | } | |
4132 | ||
51da43b5 VA |
4133 | if (!now && value && !list_empty(&hs_ep->queue)) { |
4134 | dev_dbg(hs->dev, "%s request is pending, cannot halt\n", | |
4135 | ep->name); | |
4136 | return -EAGAIN; | |
4137 | } | |
4138 | ||
c6f5c050 MYK |
4139 | if (hs_ep->dir_in) { |
4140 | epreg = DIEPCTL(index); | |
95c8bc36 | 4141 | epctl = dwc2_readl(hs->regs + epreg); |
c6f5c050 MYK |
4142 | |
4143 | if (value) { | |
5a350d53 | 4144 | epctl |= DXEPCTL_STALL | DXEPCTL_SNAK; |
c6f5c050 MYK |
4145 | if (epctl & DXEPCTL_EPENA) |
4146 | epctl |= DXEPCTL_EPDIS; | |
4147 | } else { | |
4148 | epctl &= ~DXEPCTL_STALL; | |
4149 | xfertype = epctl & DXEPCTL_EPTYPE_MASK; | |
4150 | if (xfertype == DXEPCTL_EPTYPE_BULK || | |
9da51974 | 4151 | xfertype == DXEPCTL_EPTYPE_INTERRUPT) |
77b6200e | 4152 | epctl |= DXEPCTL_SETD0PID; |
c6f5c050 | 4153 | } |
95c8bc36 | 4154 | dwc2_writel(epctl, hs->regs + epreg); |
9c39ddc6 | 4155 | } else { |
c6f5c050 | 4156 | epreg = DOEPCTL(index); |
95c8bc36 | 4157 | epctl = dwc2_readl(hs->regs + epreg); |
5b7d70c6 | 4158 | |
34c0887f | 4159 | if (value) { |
c6f5c050 | 4160 | epctl |= DXEPCTL_STALL; |
34c0887f | 4161 | } else { |
c6f5c050 MYK |
4162 | epctl &= ~DXEPCTL_STALL; |
4163 | xfertype = epctl & DXEPCTL_EPTYPE_MASK; | |
4164 | if (xfertype == DXEPCTL_EPTYPE_BULK || | |
9da51974 | 4165 | xfertype == DXEPCTL_EPTYPE_INTERRUPT) |
77b6200e | 4166 | epctl |= DXEPCTL_SETD0PID; |
c6f5c050 | 4167 | } |
95c8bc36 | 4168 | dwc2_writel(epctl, hs->regs + epreg); |
9c39ddc6 | 4169 | } |
5b7d70c6 | 4170 | |
a18ed7b0 RB |
4171 | hs_ep->halted = value; |
4172 | ||
5b7d70c6 BD |
4173 | return 0; |
4174 | } | |
4175 | ||
5ad1d316 | 4176 | /** |
1f91b4cc | 4177 | * dwc2_hsotg_ep_sethalt_lock - set halt on a given endpoint with lock held |
5ad1d316 LM |
4178 | * @ep: The endpoint to set halt. |
4179 | * @value: Set or unset the halt. | |
4180 | */ | |
1f91b4cc | 4181 | static int dwc2_hsotg_ep_sethalt_lock(struct usb_ep *ep, int value) |
5ad1d316 | 4182 | { |
1f91b4cc | 4183 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 4184 | struct dwc2_hsotg *hs = hs_ep->parent; |
5ad1d316 LM |
4185 | unsigned long flags = 0; |
4186 | int ret = 0; | |
4187 | ||
4188 | spin_lock_irqsave(&hs->lock, flags); | |
51da43b5 | 4189 | ret = dwc2_hsotg_ep_sethalt(ep, value, false); |
5ad1d316 LM |
4190 | spin_unlock_irqrestore(&hs->lock, flags); |
4191 | ||
4192 | return ret; | |
4193 | } | |
4194 | ||
ebce561a | 4195 | static const struct usb_ep_ops dwc2_hsotg_ep_ops = { |
1f91b4cc FB |
4196 | .enable = dwc2_hsotg_ep_enable, |
4197 | .disable = dwc2_hsotg_ep_disable, | |
4198 | .alloc_request = dwc2_hsotg_ep_alloc_request, | |
4199 | .free_request = dwc2_hsotg_ep_free_request, | |
4200 | .queue = dwc2_hsotg_ep_queue_lock, | |
4201 | .dequeue = dwc2_hsotg_ep_dequeue, | |
4202 | .set_halt = dwc2_hsotg_ep_sethalt_lock, | |
25985edc | 4203 | /* note, don't believe we have any call for the fifo routines */ |
5b7d70c6 BD |
4204 | }; |
4205 | ||
8b9bc460 | 4206 | /** |
9da51974 | 4207 | * dwc2_hsotg_init - initialize the usb core |
8b9bc460 LM |
4208 | * @hsotg: The driver state |
4209 | */ | |
1f91b4cc | 4210 | static void dwc2_hsotg_init(struct dwc2_hsotg *hsotg) |
b3f489b2 | 4211 | { |
fa4a8d72 | 4212 | u32 trdtim; |
ecd9a7ad | 4213 | u32 usbcfg; |
b3f489b2 LM |
4214 | /* unmask subset of endpoint interrupts */ |
4215 | ||
95c8bc36 AS |
4216 | dwc2_writel(DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK | |
4217 | DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK, | |
4218 | hsotg->regs + DIEPMSK); | |
b3f489b2 | 4219 | |
95c8bc36 AS |
4220 | dwc2_writel(DOEPMSK_SETUPMSK | DOEPMSK_AHBERRMSK | |
4221 | DOEPMSK_EPDISBLDMSK | DOEPMSK_XFERCOMPLMSK, | |
4222 | hsotg->regs + DOEPMSK); | |
b3f489b2 | 4223 | |
95c8bc36 | 4224 | dwc2_writel(0, hsotg->regs + DAINTMSK); |
b3f489b2 LM |
4225 | |
4226 | /* Be in disconnected state until gadget is registered */ | |
abd064a1 | 4227 | dwc2_set_bit(hsotg->regs + DCTL, DCTL_SFTDISCON); |
b3f489b2 | 4228 | |
b3f489b2 LM |
4229 | /* setup fifos */ |
4230 | ||
4231 | dev_dbg(hsotg->dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n", | |
95c8bc36 AS |
4232 | dwc2_readl(hsotg->regs + GRXFSIZ), |
4233 | dwc2_readl(hsotg->regs + GNPTXFSIZ)); | |
b3f489b2 | 4234 | |
1f91b4cc | 4235 | dwc2_hsotg_init_fifo(hsotg); |
b3f489b2 | 4236 | |
ecd9a7ad PR |
4237 | /* keep other bits untouched (so e.g. forced modes are not lost) */ |
4238 | usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); | |
4239 | usbcfg &= ~(GUSBCFG_TOUTCAL_MASK | GUSBCFG_PHYIF16 | GUSBCFG_SRPCAP | | |
ca02954a | 4240 | GUSBCFG_HNPCAP | GUSBCFG_USBTRDTIM_MASK); |
ecd9a7ad | 4241 | |
b3f489b2 | 4242 | /* set the PLL on, remove the HNP/SRP and set the PHY */ |
fa4a8d72 | 4243 | trdtim = (hsotg->phyif == GUSBCFG_PHYIF8) ? 9 : 5; |
ecd9a7ad PR |
4244 | usbcfg |= hsotg->phyif | GUSBCFG_TOUTCAL(7) | |
4245 | (trdtim << GUSBCFG_USBTRDTIM_SHIFT); | |
4246 | dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); | |
b3f489b2 | 4247 | |
f5090044 | 4248 | if (using_dma(hsotg)) |
abd064a1 | 4249 | dwc2_set_bit(hsotg->regs + GAHBCFG, GAHBCFG_DMA_EN); |
b3f489b2 LM |
4250 | } |
4251 | ||
8b9bc460 | 4252 | /** |
1f91b4cc | 4253 | * dwc2_hsotg_udc_start - prepare the udc for work |
8b9bc460 LM |
4254 | * @gadget: The usb gadget state |
4255 | * @driver: The usb gadget driver | |
4256 | * | |
4257 | * Perform initialization to prepare udc device and driver | |
4258 | * to work. | |
4259 | */ | |
1f91b4cc | 4260 | static int dwc2_hsotg_udc_start(struct usb_gadget *gadget, |
9da51974 | 4261 | struct usb_gadget_driver *driver) |
5b7d70c6 | 4262 | { |
941fcce4 | 4263 | struct dwc2_hsotg *hsotg = to_hsotg(gadget); |
5b9451f8 | 4264 | unsigned long flags; |
5b7d70c6 BD |
4265 | int ret; |
4266 | ||
4267 | if (!hsotg) { | |
a023da33 | 4268 | pr_err("%s: called with no device\n", __func__); |
5b7d70c6 BD |
4269 | return -ENODEV; |
4270 | } | |
4271 | ||
4272 | if (!driver) { | |
4273 | dev_err(hsotg->dev, "%s: no driver\n", __func__); | |
4274 | return -EINVAL; | |
4275 | } | |
4276 | ||
7177aed4 | 4277 | if (driver->max_speed < USB_SPEED_FULL) |
5b7d70c6 | 4278 | dev_err(hsotg->dev, "%s: bad speed\n", __func__); |
5b7d70c6 | 4279 | |
f65f0f10 | 4280 | if (!driver->setup) { |
5b7d70c6 BD |
4281 | dev_err(hsotg->dev, "%s: missing entry points\n", __func__); |
4282 | return -EINVAL; | |
4283 | } | |
4284 | ||
4285 | WARN_ON(hsotg->driver); | |
4286 | ||
4287 | driver->driver.bus = NULL; | |
4288 | hsotg->driver = driver; | |
7d7b2292 | 4289 | hsotg->gadget.dev.of_node = hsotg->dev->of_node; |
5b7d70c6 BD |
4290 | hsotg->gadget.speed = USB_SPEED_UNKNOWN; |
4291 | ||
09a75e85 MS |
4292 | if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) { |
4293 | ret = dwc2_lowlevel_hw_enable(hsotg); | |
4294 | if (ret) | |
4295 | goto err; | |
5b7d70c6 BD |
4296 | } |
4297 | ||
f6c01592 GH |
4298 | if (!IS_ERR_OR_NULL(hsotg->uphy)) |
4299 | otg_set_peripheral(hsotg->uphy->otg, &hsotg->gadget); | |
c816c47f | 4300 | |
5b9451f8 | 4301 | spin_lock_irqsave(&hsotg->lock, flags); |
d0f0ac56 JY |
4302 | if (dwc2_hw_is_device(hsotg)) { |
4303 | dwc2_hsotg_init(hsotg); | |
4304 | dwc2_hsotg_core_init_disconnected(hsotg, false); | |
4305 | } | |
4306 | ||
dc6e69e6 | 4307 | hsotg->enabled = 0; |
5b9451f8 MS |
4308 | spin_unlock_irqrestore(&hsotg->lock, flags); |
4309 | ||
5b7d70c6 | 4310 | dev_info(hsotg->dev, "bound driver %s\n", driver->driver.name); |
5b9451f8 | 4311 | |
5b7d70c6 BD |
4312 | return 0; |
4313 | ||
4314 | err: | |
4315 | hsotg->driver = NULL; | |
5b7d70c6 BD |
4316 | return ret; |
4317 | } | |
4318 | ||
8b9bc460 | 4319 | /** |
1f91b4cc | 4320 | * dwc2_hsotg_udc_stop - stop the udc |
8b9bc460 | 4321 | * @gadget: The usb gadget state |
8b9bc460 LM |
4322 | * |
4323 | * Stop udc hw block and stay tunned for future transmissions | |
4324 | */ | |
1f91b4cc | 4325 | static int dwc2_hsotg_udc_stop(struct usb_gadget *gadget) |
5b7d70c6 | 4326 | { |
941fcce4 | 4327 | struct dwc2_hsotg *hsotg = to_hsotg(gadget); |
2b19a52c | 4328 | unsigned long flags = 0; |
5b7d70c6 BD |
4329 | int ep; |
4330 | ||
4331 | if (!hsotg) | |
4332 | return -ENODEV; | |
4333 | ||
5b7d70c6 | 4334 | /* all endpoints should be shutdown */ |
c6f5c050 MYK |
4335 | for (ep = 1; ep < hsotg->num_of_eps; ep++) { |
4336 | if (hsotg->eps_in[ep]) | |
1f91b4cc | 4337 | dwc2_hsotg_ep_disable(&hsotg->eps_in[ep]->ep); |
c6f5c050 | 4338 | if (hsotg->eps_out[ep]) |
1f91b4cc | 4339 | dwc2_hsotg_ep_disable(&hsotg->eps_out[ep]->ep); |
c6f5c050 | 4340 | } |
5b7d70c6 | 4341 | |
2b19a52c LM |
4342 | spin_lock_irqsave(&hsotg->lock, flags); |
4343 | ||
32805c35 | 4344 | hsotg->driver = NULL; |
5b7d70c6 | 4345 | hsotg->gadget.speed = USB_SPEED_UNKNOWN; |
dc6e69e6 | 4346 | hsotg->enabled = 0; |
5b7d70c6 | 4347 | |
2b19a52c LM |
4348 | spin_unlock_irqrestore(&hsotg->lock, flags); |
4349 | ||
f6c01592 GH |
4350 | if (!IS_ERR_OR_NULL(hsotg->uphy)) |
4351 | otg_set_peripheral(hsotg->uphy->otg, NULL); | |
c816c47f | 4352 | |
09a75e85 MS |
4353 | if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) |
4354 | dwc2_lowlevel_hw_disable(hsotg); | |
5b7d70c6 BD |
4355 | |
4356 | return 0; | |
4357 | } | |
5b7d70c6 | 4358 | |
8b9bc460 | 4359 | /** |
1f91b4cc | 4360 | * dwc2_hsotg_gadget_getframe - read the frame number |
8b9bc460 LM |
4361 | * @gadget: The usb gadget state |
4362 | * | |
4363 | * Read the {micro} frame number | |
4364 | */ | |
1f91b4cc | 4365 | static int dwc2_hsotg_gadget_getframe(struct usb_gadget *gadget) |
5b7d70c6 | 4366 | { |
1f91b4cc | 4367 | return dwc2_hsotg_read_frameno(to_hsotg(gadget)); |
5b7d70c6 BD |
4368 | } |
4369 | ||
a188b689 | 4370 | /** |
1f91b4cc | 4371 | * dwc2_hsotg_pullup - connect/disconnect the USB PHY |
a188b689 LM |
4372 | * @gadget: The usb gadget state |
4373 | * @is_on: Current state of the USB PHY | |
4374 | * | |
4375 | * Connect/Disconnect the USB PHY pullup | |
4376 | */ | |
1f91b4cc | 4377 | static int dwc2_hsotg_pullup(struct usb_gadget *gadget, int is_on) |
a188b689 | 4378 | { |
941fcce4 | 4379 | struct dwc2_hsotg *hsotg = to_hsotg(gadget); |
a188b689 LM |
4380 | unsigned long flags = 0; |
4381 | ||
77ba9119 | 4382 | dev_dbg(hsotg->dev, "%s: is_on: %d op_state: %d\n", __func__, is_on, |
9da51974 | 4383 | hsotg->op_state); |
77ba9119 GH |
4384 | |
4385 | /* Don't modify pullup state while in host mode */ | |
4386 | if (hsotg->op_state != OTG_STATE_B_PERIPHERAL) { | |
4387 | hsotg->enabled = is_on; | |
4388 | return 0; | |
4389 | } | |
a188b689 LM |
4390 | |
4391 | spin_lock_irqsave(&hsotg->lock, flags); | |
4392 | if (is_on) { | |
dc6e69e6 | 4393 | hsotg->enabled = 1; |
1f91b4cc | 4394 | dwc2_hsotg_core_init_disconnected(hsotg, false); |
66e77a24 RK |
4395 | /* Enable ACG feature in device mode,if supported */ |
4396 | dwc2_enable_acg(hsotg); | |
1f91b4cc | 4397 | dwc2_hsotg_core_connect(hsotg); |
a188b689 | 4398 | } else { |
1f91b4cc FB |
4399 | dwc2_hsotg_core_disconnect(hsotg); |
4400 | dwc2_hsotg_disconnect(hsotg); | |
dc6e69e6 | 4401 | hsotg->enabled = 0; |
a188b689 LM |
4402 | } |
4403 | ||
4404 | hsotg->gadget.speed = USB_SPEED_UNKNOWN; | |
4405 | spin_unlock_irqrestore(&hsotg->lock, flags); | |
4406 | ||
4407 | return 0; | |
4408 | } | |
4409 | ||
1f91b4cc | 4410 | static int dwc2_hsotg_vbus_session(struct usb_gadget *gadget, int is_active) |
83d98223 GH |
4411 | { |
4412 | struct dwc2_hsotg *hsotg = to_hsotg(gadget); | |
4413 | unsigned long flags; | |
4414 | ||
4415 | dev_dbg(hsotg->dev, "%s: is_active: %d\n", __func__, is_active); | |
4416 | spin_lock_irqsave(&hsotg->lock, flags); | |
4417 | ||
61f7223b | 4418 | /* |
41ba9b9b | 4419 | * If controller is hibernated, it must exit from power_down |
61f7223b GH |
4420 | * before being initialized / de-initialized |
4421 | */ | |
4422 | if (hsotg->lx_state == DWC2_L2) | |
41ba9b9b | 4423 | dwc2_exit_partial_power_down(hsotg, false); |
61f7223b | 4424 | |
83d98223 | 4425 | if (is_active) { |
cd0e641c | 4426 | hsotg->op_state = OTG_STATE_B_PERIPHERAL; |
065d3931 | 4427 | |
1f91b4cc | 4428 | dwc2_hsotg_core_init_disconnected(hsotg, false); |
66e77a24 RK |
4429 | if (hsotg->enabled) { |
4430 | /* Enable ACG feature in device mode,if supported */ | |
4431 | dwc2_enable_acg(hsotg); | |
1f91b4cc | 4432 | dwc2_hsotg_core_connect(hsotg); |
66e77a24 | 4433 | } |
83d98223 | 4434 | } else { |
1f91b4cc FB |
4435 | dwc2_hsotg_core_disconnect(hsotg); |
4436 | dwc2_hsotg_disconnect(hsotg); | |
83d98223 GH |
4437 | } |
4438 | ||
4439 | spin_unlock_irqrestore(&hsotg->lock, flags); | |
4440 | return 0; | |
4441 | } | |
4442 | ||
596d696a | 4443 | /** |
1f91b4cc | 4444 | * dwc2_hsotg_vbus_draw - report bMaxPower field |
596d696a GH |
4445 | * @gadget: The usb gadget state |
4446 | * @mA: Amount of current | |
4447 | * | |
4448 | * Report how much power the device may consume to the phy. | |
4449 | */ | |
9da51974 | 4450 | static int dwc2_hsotg_vbus_draw(struct usb_gadget *gadget, unsigned int mA) |
596d696a GH |
4451 | { |
4452 | struct dwc2_hsotg *hsotg = to_hsotg(gadget); | |
4453 | ||
4454 | if (IS_ERR_OR_NULL(hsotg->uphy)) | |
4455 | return -ENOTSUPP; | |
4456 | return usb_phy_set_power(hsotg->uphy, mA); | |
4457 | } | |
4458 | ||
1f91b4cc FB |
4459 | static const struct usb_gadget_ops dwc2_hsotg_gadget_ops = { |
4460 | .get_frame = dwc2_hsotg_gadget_getframe, | |
4461 | .udc_start = dwc2_hsotg_udc_start, | |
4462 | .udc_stop = dwc2_hsotg_udc_stop, | |
4463 | .pullup = dwc2_hsotg_pullup, | |
4464 | .vbus_session = dwc2_hsotg_vbus_session, | |
4465 | .vbus_draw = dwc2_hsotg_vbus_draw, | |
5b7d70c6 BD |
4466 | }; |
4467 | ||
4468 | /** | |
1f91b4cc | 4469 | * dwc2_hsotg_initep - initialise a single endpoint |
5b7d70c6 BD |
4470 | * @hsotg: The device state. |
4471 | * @hs_ep: The endpoint to be initialised. | |
4472 | * @epnum: The endpoint number | |
6fb914d7 | 4473 | * @dir_in: True if direction is in. |
5b7d70c6 BD |
4474 | * |
4475 | * Initialise the given endpoint (as part of the probe and device state | |
4476 | * creation) to give to the gadget driver. Setup the endpoint name, any | |
4477 | * direction information and other state that may be required. | |
4478 | */ | |
1f91b4cc | 4479 | static void dwc2_hsotg_initep(struct dwc2_hsotg *hsotg, |
9da51974 | 4480 | struct dwc2_hsotg_ep *hs_ep, |
c6f5c050 MYK |
4481 | int epnum, |
4482 | bool dir_in) | |
5b7d70c6 | 4483 | { |
5b7d70c6 BD |
4484 | char *dir; |
4485 | ||
4486 | if (epnum == 0) | |
4487 | dir = ""; | |
c6f5c050 | 4488 | else if (dir_in) |
5b7d70c6 | 4489 | dir = "in"; |
c6f5c050 MYK |
4490 | else |
4491 | dir = "out"; | |
5b7d70c6 | 4492 | |
c6f5c050 | 4493 | hs_ep->dir_in = dir_in; |
5b7d70c6 BD |
4494 | hs_ep->index = epnum; |
4495 | ||
4496 | snprintf(hs_ep->name, sizeof(hs_ep->name), "ep%d%s", epnum, dir); | |
4497 | ||
4498 | INIT_LIST_HEAD(&hs_ep->queue); | |
4499 | INIT_LIST_HEAD(&hs_ep->ep.ep_list); | |
4500 | ||
5b7d70c6 BD |
4501 | /* add to the list of endpoints known by the gadget driver */ |
4502 | if (epnum) | |
4503 | list_add_tail(&hs_ep->ep.ep_list, &hsotg->gadget.ep_list); | |
4504 | ||
4505 | hs_ep->parent = hsotg; | |
4506 | hs_ep->ep.name = hs_ep->name; | |
38e9002b VM |
4507 | |
4508 | if (hsotg->params.speed == DWC2_SPEED_PARAM_LOW) | |
4509 | usb_ep_set_maxpacket_limit(&hs_ep->ep, 8); | |
4510 | else | |
4511 | usb_ep_set_maxpacket_limit(&hs_ep->ep, | |
4512 | epnum ? 1024 : EP0_MPS_LIMIT); | |
1f91b4cc | 4513 | hs_ep->ep.ops = &dwc2_hsotg_ep_ops; |
5b7d70c6 | 4514 | |
2954522f RB |
4515 | if (epnum == 0) { |
4516 | hs_ep->ep.caps.type_control = true; | |
4517 | } else { | |
38e9002b VM |
4518 | if (hsotg->params.speed != DWC2_SPEED_PARAM_LOW) { |
4519 | hs_ep->ep.caps.type_iso = true; | |
4520 | hs_ep->ep.caps.type_bulk = true; | |
4521 | } | |
2954522f RB |
4522 | hs_ep->ep.caps.type_int = true; |
4523 | } | |
4524 | ||
4525 | if (dir_in) | |
4526 | hs_ep->ep.caps.dir_in = true; | |
4527 | else | |
4528 | hs_ep->ep.caps.dir_out = true; | |
4529 | ||
8b9bc460 LM |
4530 | /* |
4531 | * if we're using dma, we need to set the next-endpoint pointer | |
5b7d70c6 BD |
4532 | * to be something valid. |
4533 | */ | |
4534 | ||
4535 | if (using_dma(hsotg)) { | |
47a1685f | 4536 | u32 next = DXEPCTL_NEXTEP((epnum + 1) % 15); |
9da51974 | 4537 | |
c6f5c050 | 4538 | if (dir_in) |
95c8bc36 | 4539 | dwc2_writel(next, hsotg->regs + DIEPCTL(epnum)); |
c6f5c050 | 4540 | else |
95c8bc36 | 4541 | dwc2_writel(next, hsotg->regs + DOEPCTL(epnum)); |
5b7d70c6 BD |
4542 | } |
4543 | } | |
4544 | ||
b3f489b2 | 4545 | /** |
1f91b4cc | 4546 | * dwc2_hsotg_hw_cfg - read HW configuration registers |
6fb914d7 | 4547 | * @hsotg: Programming view of the DWC_otg controller |
b3f489b2 LM |
4548 | * |
4549 | * Read the USB core HW configuration registers | |
4550 | */ | |
1f91b4cc | 4551 | static int dwc2_hsotg_hw_cfg(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 4552 | { |
c6f5c050 MYK |
4553 | u32 cfg; |
4554 | u32 ep_type; | |
4555 | u32 i; | |
4556 | ||
b3f489b2 | 4557 | /* check hardware configuration */ |
5b7d70c6 | 4558 | |
43e90349 JY |
4559 | hsotg->num_of_eps = hsotg->hw_params.num_dev_ep; |
4560 | ||
c6f5c050 MYK |
4561 | /* Add ep0 */ |
4562 | hsotg->num_of_eps++; | |
10aebc77 | 4563 | |
b98866c2 JY |
4564 | hsotg->eps_in[0] = devm_kzalloc(hsotg->dev, |
4565 | sizeof(struct dwc2_hsotg_ep), | |
4566 | GFP_KERNEL); | |
c6f5c050 MYK |
4567 | if (!hsotg->eps_in[0]) |
4568 | return -ENOMEM; | |
1f91b4cc | 4569 | /* Same dwc2_hsotg_ep is used in both directions for ep0 */ |
c6f5c050 MYK |
4570 | hsotg->eps_out[0] = hsotg->eps_in[0]; |
4571 | ||
43e90349 | 4572 | cfg = hsotg->hw_params.dev_ep_dirs; |
251a17f5 | 4573 | for (i = 1, cfg >>= 2; i < hsotg->num_of_eps; i++, cfg >>= 2) { |
c6f5c050 MYK |
4574 | ep_type = cfg & 3; |
4575 | /* Direction in or both */ | |
4576 | if (!(ep_type & 2)) { | |
4577 | hsotg->eps_in[i] = devm_kzalloc(hsotg->dev, | |
1f91b4cc | 4578 | sizeof(struct dwc2_hsotg_ep), GFP_KERNEL); |
c6f5c050 MYK |
4579 | if (!hsotg->eps_in[i]) |
4580 | return -ENOMEM; | |
4581 | } | |
4582 | /* Direction out or both */ | |
4583 | if (!(ep_type & 1)) { | |
4584 | hsotg->eps_out[i] = devm_kzalloc(hsotg->dev, | |
1f91b4cc | 4585 | sizeof(struct dwc2_hsotg_ep), GFP_KERNEL); |
c6f5c050 MYK |
4586 | if (!hsotg->eps_out[i]) |
4587 | return -ENOMEM; | |
4588 | } | |
4589 | } | |
4590 | ||
43e90349 JY |
4591 | hsotg->fifo_mem = hsotg->hw_params.total_fifo_size; |
4592 | hsotg->dedicated_fifos = hsotg->hw_params.en_multiple_tx_fifo; | |
10aebc77 | 4593 | |
cff9eb75 MS |
4594 | dev_info(hsotg->dev, "EPs: %d, %s fifos, %d entries in SPRAM\n", |
4595 | hsotg->num_of_eps, | |
4596 | hsotg->dedicated_fifos ? "dedicated" : "shared", | |
4597 | hsotg->fifo_mem); | |
c6f5c050 | 4598 | return 0; |
5b7d70c6 BD |
4599 | } |
4600 | ||
8b9bc460 | 4601 | /** |
1f91b4cc | 4602 | * dwc2_hsotg_dump - dump state of the udc |
6fb914d7 GT |
4603 | * @hsotg: Programming view of the DWC_otg controller |
4604 | * | |
8b9bc460 | 4605 | */ |
1f91b4cc | 4606 | static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 4607 | { |
83a01804 | 4608 | #ifdef DEBUG |
5b7d70c6 BD |
4609 | struct device *dev = hsotg->dev; |
4610 | void __iomem *regs = hsotg->regs; | |
4611 | u32 val; | |
4612 | int idx; | |
4613 | ||
4614 | dev_info(dev, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n", | |
95c8bc36 AS |
4615 | dwc2_readl(regs + DCFG), dwc2_readl(regs + DCTL), |
4616 | dwc2_readl(regs + DIEPMSK)); | |
5b7d70c6 | 4617 | |
f889f23d | 4618 | dev_info(dev, "GAHBCFG=0x%08x, GHWCFG1=0x%08x\n", |
95c8bc36 | 4619 | dwc2_readl(regs + GAHBCFG), dwc2_readl(regs + GHWCFG1)); |
5b7d70c6 BD |
4620 | |
4621 | dev_info(dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n", | |
95c8bc36 | 4622 | dwc2_readl(regs + GRXFSIZ), dwc2_readl(regs + GNPTXFSIZ)); |
5b7d70c6 BD |
4623 | |
4624 | /* show periodic fifo settings */ | |
4625 | ||
364f8e93 | 4626 | for (idx = 1; idx < hsotg->num_of_eps; idx++) { |
95c8bc36 | 4627 | val = dwc2_readl(regs + DPTXFSIZN(idx)); |
5b7d70c6 | 4628 | dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx, |
47a1685f DN |
4629 | val >> FIFOSIZE_DEPTH_SHIFT, |
4630 | val & FIFOSIZE_STARTADDR_MASK); | |
5b7d70c6 BD |
4631 | } |
4632 | ||
364f8e93 | 4633 | for (idx = 0; idx < hsotg->num_of_eps; idx++) { |
5b7d70c6 BD |
4634 | dev_info(dev, |
4635 | "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx, | |
95c8bc36 AS |
4636 | dwc2_readl(regs + DIEPCTL(idx)), |
4637 | dwc2_readl(regs + DIEPTSIZ(idx)), | |
4638 | dwc2_readl(regs + DIEPDMA(idx))); | |
5b7d70c6 | 4639 | |
95c8bc36 | 4640 | val = dwc2_readl(regs + DOEPCTL(idx)); |
5b7d70c6 BD |
4641 | dev_info(dev, |
4642 | "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", | |
95c8bc36 AS |
4643 | idx, dwc2_readl(regs + DOEPCTL(idx)), |
4644 | dwc2_readl(regs + DOEPTSIZ(idx)), | |
4645 | dwc2_readl(regs + DOEPDMA(idx))); | |
5b7d70c6 BD |
4646 | } |
4647 | ||
4648 | dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n", | |
95c8bc36 | 4649 | dwc2_readl(regs + DVBUSDIS), dwc2_readl(regs + DVBUSPULSE)); |
83a01804 | 4650 | #endif |
5b7d70c6 BD |
4651 | } |
4652 | ||
8b9bc460 | 4653 | /** |
117777b2 | 4654 | * dwc2_gadget_init - init function for gadget |
6fb914d7 GT |
4655 | * @hsotg: Programming view of the DWC_otg controller |
4656 | * | |
8b9bc460 | 4657 | */ |
f3768997 | 4658 | int dwc2_gadget_init(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 4659 | { |
117777b2 | 4660 | struct device *dev = hsotg->dev; |
5b7d70c6 BD |
4661 | int epnum; |
4662 | int ret; | |
43e90349 | 4663 | |
0a176279 GH |
4664 | /* Dump fifo information */ |
4665 | dev_dbg(dev, "NonPeriodic TXFIFO size: %d\n", | |
05ee799f JY |
4666 | hsotg->params.g_np_tx_fifo_size); |
4667 | dev_dbg(dev, "RXFIFO size: %d\n", hsotg->params.g_rx_fifo_size); | |
5b7d70c6 | 4668 | |
d327ab5b | 4669 | hsotg->gadget.max_speed = USB_SPEED_HIGH; |
1f91b4cc | 4670 | hsotg->gadget.ops = &dwc2_hsotg_gadget_ops; |
5b7d70c6 | 4671 | hsotg->gadget.name = dev_name(dev); |
fa389a6d | 4672 | hsotg->remote_wakeup_allowed = 0; |
7455f8b7 JY |
4673 | |
4674 | if (hsotg->params.lpm) | |
4675 | hsotg->gadget.lpm_capable = true; | |
4676 | ||
097ee662 GH |
4677 | if (hsotg->dr_mode == USB_DR_MODE_OTG) |
4678 | hsotg->gadget.is_otg = 1; | |
ec4cc657 MYK |
4679 | else if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) |
4680 | hsotg->op_state = OTG_STATE_B_PERIPHERAL; | |
5b7d70c6 | 4681 | |
1f91b4cc | 4682 | ret = dwc2_hsotg_hw_cfg(hsotg); |
c6f5c050 MYK |
4683 | if (ret) { |
4684 | dev_err(hsotg->dev, "Hardware configuration failed: %d\n", ret); | |
09a75e85 | 4685 | return ret; |
c6f5c050 MYK |
4686 | } |
4687 | ||
3f95001d MYK |
4688 | hsotg->ctrl_buff = devm_kzalloc(hsotg->dev, |
4689 | DWC2_CTRL_BUFF_SIZE, GFP_KERNEL); | |
8bae0f8c | 4690 | if (!hsotg->ctrl_buff) |
09a75e85 | 4691 | return -ENOMEM; |
3f95001d MYK |
4692 | |
4693 | hsotg->ep0_buff = devm_kzalloc(hsotg->dev, | |
4694 | DWC2_CTRL_BUFF_SIZE, GFP_KERNEL); | |
8bae0f8c | 4695 | if (!hsotg->ep0_buff) |
09a75e85 | 4696 | return -ENOMEM; |
3f95001d | 4697 | |
0f6b80c0 VA |
4698 | if (using_desc_dma(hsotg)) { |
4699 | ret = dwc2_gadget_alloc_ctrl_desc_chains(hsotg); | |
4700 | if (ret < 0) | |
4701 | return ret; | |
4702 | } | |
4703 | ||
f3768997 VM |
4704 | ret = devm_request_irq(hsotg->dev, hsotg->irq, dwc2_hsotg_irq, |
4705 | IRQF_SHARED, dev_name(hsotg->dev), hsotg); | |
eb3c56c5 | 4706 | if (ret < 0) { |
db8178c3 | 4707 | dev_err(dev, "cannot claim IRQ for gadget\n"); |
09a75e85 | 4708 | return ret; |
eb3c56c5 MS |
4709 | } |
4710 | ||
b3f489b2 LM |
4711 | /* hsotg->num_of_eps holds number of EPs other than ep0 */ |
4712 | ||
4713 | if (hsotg->num_of_eps == 0) { | |
4714 | dev_err(dev, "wrong number of EPs (zero)\n"); | |
09a75e85 | 4715 | return -EINVAL; |
b3f489b2 LM |
4716 | } |
4717 | ||
b3f489b2 LM |
4718 | /* setup endpoint information */ |
4719 | ||
4720 | INIT_LIST_HEAD(&hsotg->gadget.ep_list); | |
c6f5c050 | 4721 | hsotg->gadget.ep0 = &hsotg->eps_out[0]->ep; |
b3f489b2 LM |
4722 | |
4723 | /* allocate EP0 request */ | |
4724 | ||
1f91b4cc | 4725 | hsotg->ctrl_req = dwc2_hsotg_ep_alloc_request(&hsotg->eps_out[0]->ep, |
b3f489b2 LM |
4726 | GFP_KERNEL); |
4727 | if (!hsotg->ctrl_req) { | |
4728 | dev_err(dev, "failed to allocate ctrl req\n"); | |
09a75e85 | 4729 | return -ENOMEM; |
b3f489b2 | 4730 | } |
5b7d70c6 BD |
4731 | |
4732 | /* initialise the endpoints now the core has been initialised */ | |
c6f5c050 MYK |
4733 | for (epnum = 0; epnum < hsotg->num_of_eps; epnum++) { |
4734 | if (hsotg->eps_in[epnum]) | |
1f91b4cc | 4735 | dwc2_hsotg_initep(hsotg, hsotg->eps_in[epnum], |
9da51974 | 4736 | epnum, 1); |
c6f5c050 | 4737 | if (hsotg->eps_out[epnum]) |
1f91b4cc | 4738 | dwc2_hsotg_initep(hsotg, hsotg->eps_out[epnum], |
9da51974 | 4739 | epnum, 0); |
c6f5c050 | 4740 | } |
5b7d70c6 | 4741 | |
117777b2 | 4742 | ret = usb_add_gadget_udc(dev, &hsotg->gadget); |
9bb073a0 GT |
4743 | if (ret) { |
4744 | dwc2_hsotg_ep_free_request(&hsotg->eps_out[0]->ep, | |
4745 | hsotg->ctrl_req); | |
09a75e85 | 4746 | return ret; |
9bb073a0 | 4747 | } |
1f91b4cc | 4748 | dwc2_hsotg_dump(hsotg); |
5b7d70c6 | 4749 | |
5b7d70c6 | 4750 | return 0; |
5b7d70c6 BD |
4751 | } |
4752 | ||
8b9bc460 | 4753 | /** |
1f91b4cc | 4754 | * dwc2_hsotg_remove - remove function for hsotg driver |
6fb914d7 GT |
4755 | * @hsotg: Programming view of the DWC_otg controller |
4756 | * | |
8b9bc460 | 4757 | */ |
1f91b4cc | 4758 | int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 4759 | { |
0f91349b | 4760 | usb_del_gadget_udc(&hsotg->gadget); |
9bb073a0 | 4761 | dwc2_hsotg_ep_free_request(&hsotg->eps_out[0]->ep, hsotg->ctrl_req); |
31ee04de | 4762 | |
5b7d70c6 BD |
4763 | return 0; |
4764 | } | |
4765 | ||
1f91b4cc | 4766 | int dwc2_hsotg_suspend(struct dwc2_hsotg *hsotg) |
b83e333a | 4767 | { |
b83e333a | 4768 | unsigned long flags; |
b83e333a | 4769 | |
9e779778 | 4770 | if (hsotg->lx_state != DWC2_L0) |
09a75e85 | 4771 | return 0; |
9e779778 | 4772 | |
dc6e69e6 MS |
4773 | if (hsotg->driver) { |
4774 | int ep; | |
4775 | ||
b83e333a MS |
4776 | dev_info(hsotg->dev, "suspending usb gadget %s\n", |
4777 | hsotg->driver->driver.name); | |
4778 | ||
dc6e69e6 MS |
4779 | spin_lock_irqsave(&hsotg->lock, flags); |
4780 | if (hsotg->enabled) | |
1f91b4cc FB |
4781 | dwc2_hsotg_core_disconnect(hsotg); |
4782 | dwc2_hsotg_disconnect(hsotg); | |
dc6e69e6 MS |
4783 | hsotg->gadget.speed = USB_SPEED_UNKNOWN; |
4784 | spin_unlock_irqrestore(&hsotg->lock, flags); | |
b83e333a | 4785 | |
c6f5c050 MYK |
4786 | for (ep = 0; ep < hsotg->num_of_eps; ep++) { |
4787 | if (hsotg->eps_in[ep]) | |
1f91b4cc | 4788 | dwc2_hsotg_ep_disable(&hsotg->eps_in[ep]->ep); |
c6f5c050 | 4789 | if (hsotg->eps_out[ep]) |
1f91b4cc | 4790 | dwc2_hsotg_ep_disable(&hsotg->eps_out[ep]->ep); |
c6f5c050 | 4791 | } |
b83e333a MS |
4792 | } |
4793 | ||
09a75e85 | 4794 | return 0; |
b83e333a MS |
4795 | } |
4796 | ||
1f91b4cc | 4797 | int dwc2_hsotg_resume(struct dwc2_hsotg *hsotg) |
b83e333a | 4798 | { |
b83e333a | 4799 | unsigned long flags; |
b83e333a | 4800 | |
9e779778 | 4801 | if (hsotg->lx_state == DWC2_L2) |
09a75e85 | 4802 | return 0; |
9e779778 | 4803 | |
b83e333a MS |
4804 | if (hsotg->driver) { |
4805 | dev_info(hsotg->dev, "resuming usb gadget %s\n", | |
4806 | hsotg->driver->driver.name); | |
d00b4142 | 4807 | |
dc6e69e6 | 4808 | spin_lock_irqsave(&hsotg->lock, flags); |
1f91b4cc | 4809 | dwc2_hsotg_core_init_disconnected(hsotg, false); |
66e77a24 RK |
4810 | if (hsotg->enabled) { |
4811 | /* Enable ACG feature in device mode,if supported */ | |
4812 | dwc2_enable_acg(hsotg); | |
1f91b4cc | 4813 | dwc2_hsotg_core_connect(hsotg); |
66e77a24 | 4814 | } |
dc6e69e6 MS |
4815 | spin_unlock_irqrestore(&hsotg->lock, flags); |
4816 | } | |
b83e333a | 4817 | |
09a75e85 | 4818 | return 0; |
b83e333a | 4819 | } |
58e52ff6 JY |
4820 | |
4821 | /** | |
4822 | * dwc2_backup_device_registers() - Backup controller device registers. | |
4823 | * When suspending usb bus, registers needs to be backuped | |
4824 | * if controller power is disabled once suspended. | |
4825 | * | |
4826 | * @hsotg: Programming view of the DWC_otg controller | |
4827 | */ | |
4828 | int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg) | |
4829 | { | |
4830 | struct dwc2_dregs_backup *dr; | |
4831 | int i; | |
4832 | ||
4833 | dev_dbg(hsotg->dev, "%s\n", __func__); | |
4834 | ||
4835 | /* Backup dev regs */ | |
4836 | dr = &hsotg->dr_backup; | |
4837 | ||
4838 | dr->dcfg = dwc2_readl(hsotg->regs + DCFG); | |
4839 | dr->dctl = dwc2_readl(hsotg->regs + DCTL); | |
4840 | dr->daintmsk = dwc2_readl(hsotg->regs + DAINTMSK); | |
4841 | dr->diepmsk = dwc2_readl(hsotg->regs + DIEPMSK); | |
4842 | dr->doepmsk = dwc2_readl(hsotg->regs + DOEPMSK); | |
4843 | ||
4844 | for (i = 0; i < hsotg->num_of_eps; i++) { | |
4845 | /* Backup IN EPs */ | |
4846 | dr->diepctl[i] = dwc2_readl(hsotg->regs + DIEPCTL(i)); | |
4847 | ||
4848 | /* Ensure DATA PID is correctly configured */ | |
4849 | if (dr->diepctl[i] & DXEPCTL_DPID) | |
4850 | dr->diepctl[i] |= DXEPCTL_SETD1PID; | |
4851 | else | |
4852 | dr->diepctl[i] |= DXEPCTL_SETD0PID; | |
4853 | ||
4854 | dr->dieptsiz[i] = dwc2_readl(hsotg->regs + DIEPTSIZ(i)); | |
4855 | dr->diepdma[i] = dwc2_readl(hsotg->regs + DIEPDMA(i)); | |
4856 | ||
4857 | /* Backup OUT EPs */ | |
4858 | dr->doepctl[i] = dwc2_readl(hsotg->regs + DOEPCTL(i)); | |
4859 | ||
4860 | /* Ensure DATA PID is correctly configured */ | |
4861 | if (dr->doepctl[i] & DXEPCTL_DPID) | |
4862 | dr->doepctl[i] |= DXEPCTL_SETD1PID; | |
4863 | else | |
4864 | dr->doepctl[i] |= DXEPCTL_SETD0PID; | |
4865 | ||
4866 | dr->doeptsiz[i] = dwc2_readl(hsotg->regs + DOEPTSIZ(i)); | |
4867 | dr->doepdma[i] = dwc2_readl(hsotg->regs + DOEPDMA(i)); | |
af7c2bd3 | 4868 | dr->dtxfsiz[i] = dwc2_readl(hsotg->regs + DPTXFSIZN(i)); |
58e52ff6 JY |
4869 | } |
4870 | dr->valid = true; | |
4871 | return 0; | |
4872 | } | |
4873 | ||
4874 | /** | |
4875 | * dwc2_restore_device_registers() - Restore controller device registers. | |
4876 | * When resuming usb bus, device registers needs to be restored | |
4877 | * if controller power were disabled. | |
4878 | * | |
4879 | * @hsotg: Programming view of the DWC_otg controller | |
9a5d2816 VM |
4880 | * @remote_wakeup: Indicates whether resume is initiated by Device or Host. |
4881 | * | |
4882 | * Return: 0 if successful, negative error code otherwise | |
58e52ff6 | 4883 | */ |
9a5d2816 | 4884 | int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg, int remote_wakeup) |
58e52ff6 JY |
4885 | { |
4886 | struct dwc2_dregs_backup *dr; | |
58e52ff6 JY |
4887 | int i; |
4888 | ||
4889 | dev_dbg(hsotg->dev, "%s\n", __func__); | |
4890 | ||
4891 | /* Restore dev regs */ | |
4892 | dr = &hsotg->dr_backup; | |
4893 | if (!dr->valid) { | |
4894 | dev_err(hsotg->dev, "%s: no device registers to restore\n", | |
4895 | __func__); | |
4896 | return -EINVAL; | |
4897 | } | |
4898 | dr->valid = false; | |
4899 | ||
9a5d2816 VM |
4900 | if (!remote_wakeup) |
4901 | dwc2_writel(dr->dctl, hsotg->regs + DCTL); | |
4902 | ||
58e52ff6 JY |
4903 | dwc2_writel(dr->daintmsk, hsotg->regs + DAINTMSK); |
4904 | dwc2_writel(dr->diepmsk, hsotg->regs + DIEPMSK); | |
4905 | dwc2_writel(dr->doepmsk, hsotg->regs + DOEPMSK); | |
4906 | ||
4907 | for (i = 0; i < hsotg->num_of_eps; i++) { | |
4908 | /* Restore IN EPs */ | |
58e52ff6 JY |
4909 | dwc2_writel(dr->dieptsiz[i], hsotg->regs + DIEPTSIZ(i)); |
4910 | dwc2_writel(dr->diepdma[i], hsotg->regs + DIEPDMA(i)); | |
9a5d2816 VM |
4911 | dwc2_writel(dr->doeptsiz[i], hsotg->regs + DOEPTSIZ(i)); |
4912 | /** WA for enabled EPx's IN in DDMA mode. On entering to | |
4913 | * hibernation wrong value read and saved from DIEPDMAx, | |
4914 | * as result BNA interrupt asserted on hibernation exit | |
4915 | * by restoring from saved area. | |
4916 | */ | |
4917 | if (hsotg->params.g_dma_desc && | |
4918 | (dr->diepctl[i] & DXEPCTL_EPENA)) | |
4919 | dr->diepdma[i] = hsotg->eps_in[i]->desc_list_dma; | |
af7c2bd3 | 4920 | dwc2_writel(dr->dtxfsiz[i], hsotg->regs + DPTXFSIZN(i)); |
9a5d2816 | 4921 | dwc2_writel(dr->diepctl[i], hsotg->regs + DIEPCTL(i)); |
58e52ff6 | 4922 | /* Restore OUT EPs */ |
58e52ff6 | 4923 | dwc2_writel(dr->doeptsiz[i], hsotg->regs + DOEPTSIZ(i)); |
9a5d2816 VM |
4924 | /* WA for enabled EPx's OUT in DDMA mode. On entering to |
4925 | * hibernation wrong value read and saved from DOEPDMAx, | |
4926 | * as result BNA interrupt asserted on hibernation exit | |
4927 | * by restoring from saved area. | |
4928 | */ | |
4929 | if (hsotg->params.g_dma_desc && | |
4930 | (dr->doepctl[i] & DXEPCTL_EPENA)) | |
4931 | dr->doepdma[i] = hsotg->eps_out[i]->desc_list_dma; | |
58e52ff6 | 4932 | dwc2_writel(dr->doepdma[i], hsotg->regs + DOEPDMA(i)); |
9a5d2816 | 4933 | dwc2_writel(dr->doepctl[i], hsotg->regs + DOEPCTL(i)); |
58e52ff6 JY |
4934 | } |
4935 | ||
58e52ff6 JY |
4936 | return 0; |
4937 | } | |
21b03405 SA |
4938 | |
4939 | /** | |
4940 | * dwc2_gadget_init_lpm - Configure the core to support LPM in device mode | |
4941 | * | |
4942 | * @hsotg: Programming view of DWC_otg controller | |
4943 | * | |
4944 | */ | |
4945 | void dwc2_gadget_init_lpm(struct dwc2_hsotg *hsotg) | |
4946 | { | |
4947 | u32 val; | |
4948 | ||
4949 | if (!hsotg->params.lpm) | |
4950 | return; | |
4951 | ||
4952 | val = GLPMCFG_LPMCAP | GLPMCFG_APPL1RES; | |
4953 | val |= hsotg->params.hird_threshold_en ? GLPMCFG_HIRD_THRES_EN : 0; | |
4954 | val |= hsotg->params.lpm_clock_gating ? GLPMCFG_ENBLSLPM : 0; | |
4955 | val |= hsotg->params.hird_threshold << GLPMCFG_HIRD_THRES_SHIFT; | |
4956 | val |= hsotg->params.besl ? GLPMCFG_ENBESL : 0; | |
4957 | dwc2_writel(val, hsotg->regs + GLPMCFG); | |
4958 | dev_dbg(hsotg->dev, "GLPMCFG=0x%08x\n", dwc2_readl(hsotg->regs | |
4959 | + GLPMCFG)); | |
4960 | } | |
c5c403dc VM |
4961 | |
4962 | /** | |
4963 | * dwc2_gadget_enter_hibernation() - Put controller in Hibernation. | |
4964 | * | |
4965 | * @hsotg: Programming view of the DWC_otg controller | |
4966 | * | |
4967 | * Return non-zero if failed to enter to hibernation. | |
4968 | */ | |
4969 | int dwc2_gadget_enter_hibernation(struct dwc2_hsotg *hsotg) | |
4970 | { | |
4971 | u32 gpwrdn; | |
4972 | int ret = 0; | |
4973 | ||
4974 | /* Change to L2(suspend) state */ | |
4975 | hsotg->lx_state = DWC2_L2; | |
4976 | dev_dbg(hsotg->dev, "Start of hibernation completed\n"); | |
4977 | ret = dwc2_backup_global_registers(hsotg); | |
4978 | if (ret) { | |
4979 | dev_err(hsotg->dev, "%s: failed to backup global registers\n", | |
4980 | __func__); | |
4981 | return ret; | |
4982 | } | |
4983 | ret = dwc2_backup_device_registers(hsotg); | |
4984 | if (ret) { | |
4985 | dev_err(hsotg->dev, "%s: failed to backup device registers\n", | |
4986 | __func__); | |
4987 | return ret; | |
4988 | } | |
4989 | ||
4990 | gpwrdn = GPWRDN_PWRDNRSTN; | |
4991 | gpwrdn |= GPWRDN_PMUACTV; | |
4992 | dwc2_writel(gpwrdn, hsotg->regs + GPWRDN); | |
4993 | udelay(10); | |
4994 | ||
4995 | /* Set flag to indicate that we are in hibernation */ | |
4996 | hsotg->hibernated = 1; | |
4997 | ||
4998 | /* Enable interrupts from wake up logic */ | |
4999 | gpwrdn = dwc2_readl(hsotg->regs + GPWRDN); | |
5000 | gpwrdn |= GPWRDN_PMUINTSEL; | |
5001 | dwc2_writel(gpwrdn, hsotg->regs + GPWRDN); | |
5002 | udelay(10); | |
5003 | ||
5004 | /* Unmask device mode interrupts in GPWRDN */ | |
5005 | gpwrdn = dwc2_readl(hsotg->regs + GPWRDN); | |
5006 | gpwrdn |= GPWRDN_RST_DET_MSK; | |
5007 | gpwrdn |= GPWRDN_LNSTSCHG_MSK; | |
5008 | gpwrdn |= GPWRDN_STS_CHGINT_MSK; | |
5009 | dwc2_writel(gpwrdn, hsotg->regs + GPWRDN); | |
5010 | udelay(10); | |
5011 | ||
5012 | /* Enable Power Down Clamp */ | |
5013 | gpwrdn = dwc2_readl(hsotg->regs + GPWRDN); | |
5014 | gpwrdn |= GPWRDN_PWRDNCLMP; | |
5015 | dwc2_writel(gpwrdn, hsotg->regs + GPWRDN); | |
5016 | udelay(10); | |
5017 | ||
5018 | /* Switch off VDD */ | |
5019 | gpwrdn = dwc2_readl(hsotg->regs + GPWRDN); | |
5020 | gpwrdn |= GPWRDN_PWRDNSWTCH; | |
5021 | dwc2_writel(gpwrdn, hsotg->regs + GPWRDN); | |
5022 | udelay(10); | |
5023 | ||
5024 | /* Save gpwrdn register for further usage if stschng interrupt */ | |
5025 | hsotg->gr_backup.gpwrdn = dwc2_readl(hsotg->regs + GPWRDN); | |
5026 | dev_dbg(hsotg->dev, "Hibernation completed\n"); | |
5027 | ||
5028 | return ret; | |
5029 | } | |
5030 | ||
5031 | /** | |
5032 | * dwc2_gadget_exit_hibernation() | |
5033 | * This function is for exiting from Device mode hibernation by host initiated | |
5034 | * resume/reset and device initiated remote-wakeup. | |
5035 | * | |
5036 | * @hsotg: Programming view of the DWC_otg controller | |
5037 | * @rem_wakeup: indicates whether resume is initiated by Device or Host. | |
6fb914d7 | 5038 | * @reset: indicates whether resume is initiated by Reset. |
c5c403dc VM |
5039 | * |
5040 | * Return non-zero if failed to exit from hibernation. | |
5041 | */ | |
5042 | int dwc2_gadget_exit_hibernation(struct dwc2_hsotg *hsotg, | |
5043 | int rem_wakeup, int reset) | |
5044 | { | |
5045 | u32 pcgcctl; | |
5046 | u32 gpwrdn; | |
5047 | u32 dctl; | |
5048 | int ret = 0; | |
5049 | struct dwc2_gregs_backup *gr; | |
5050 | struct dwc2_dregs_backup *dr; | |
5051 | ||
5052 | gr = &hsotg->gr_backup; | |
5053 | dr = &hsotg->dr_backup; | |
5054 | ||
5055 | if (!hsotg->hibernated) { | |
5056 | dev_dbg(hsotg->dev, "Already exited from Hibernation\n"); | |
5057 | return 1; | |
5058 | } | |
5059 | dev_dbg(hsotg->dev, | |
5060 | "%s: called with rem_wakeup = %d reset = %d\n", | |
5061 | __func__, rem_wakeup, reset); | |
5062 | ||
5063 | dwc2_hib_restore_common(hsotg, rem_wakeup, 0); | |
5064 | ||
5065 | if (!reset) { | |
5066 | /* Clear all pending interupts */ | |
5067 | dwc2_writel(0xffffffff, hsotg->regs + GINTSTS); | |
5068 | } | |
5069 | ||
5070 | /* De-assert Restore */ | |
5071 | gpwrdn = dwc2_readl(hsotg->regs + GPWRDN); | |
5072 | gpwrdn &= ~GPWRDN_RESTORE; | |
5073 | dwc2_writel(gpwrdn, hsotg->regs + GPWRDN); | |
5074 | udelay(10); | |
5075 | ||
5076 | if (!rem_wakeup) { | |
5077 | pcgcctl = dwc2_readl(hsotg->regs + PCGCTL); | |
5078 | pcgcctl &= ~PCGCTL_RSTPDWNMODULE; | |
5079 | dwc2_writel(pcgcctl, hsotg->regs + PCGCTL); | |
5080 | } | |
5081 | ||
5082 | /* Restore GUSBCFG, DCFG and DCTL */ | |
5083 | dwc2_writel(gr->gusbcfg, hsotg->regs + GUSBCFG); | |
5084 | dwc2_writel(dr->dcfg, hsotg->regs + DCFG); | |
5085 | dwc2_writel(dr->dctl, hsotg->regs + DCTL); | |
5086 | ||
5087 | /* De-assert Wakeup Logic */ | |
5088 | gpwrdn = dwc2_readl(hsotg->regs + GPWRDN); | |
5089 | gpwrdn &= ~GPWRDN_PMUACTV; | |
5090 | dwc2_writel(gpwrdn, hsotg->regs + GPWRDN); | |
5091 | ||
5092 | if (rem_wakeup) { | |
5093 | udelay(10); | |
5094 | /* Start Remote Wakeup Signaling */ | |
5095 | dwc2_writel(dr->dctl | DCTL_RMTWKUPSIG, hsotg->regs + DCTL); | |
5096 | } else { | |
5097 | udelay(50); | |
5098 | /* Set Device programming done bit */ | |
5099 | dctl = dwc2_readl(hsotg->regs + DCTL); | |
5100 | dctl |= DCTL_PWRONPRGDONE; | |
5101 | dwc2_writel(dctl, hsotg->regs + DCTL); | |
5102 | } | |
5103 | /* Wait for interrupts which must be cleared */ | |
5104 | mdelay(2); | |
5105 | /* Clear all pending interupts */ | |
5106 | dwc2_writel(0xffffffff, hsotg->regs + GINTSTS); | |
5107 | ||
5108 | /* Restore global registers */ | |
5109 | ret = dwc2_restore_global_registers(hsotg); | |
5110 | if (ret) { | |
5111 | dev_err(hsotg->dev, "%s: failed to restore registers\n", | |
5112 | __func__); | |
5113 | return ret; | |
5114 | } | |
5115 | ||
5116 | /* Restore device registers */ | |
5117 | ret = dwc2_restore_device_registers(hsotg, rem_wakeup); | |
5118 | if (ret) { | |
5119 | dev_err(hsotg->dev, "%s: failed to restore device registers\n", | |
5120 | __func__); | |
5121 | return ret; | |
5122 | } | |
5123 | ||
5124 | if (rem_wakeup) { | |
5125 | mdelay(10); | |
5126 | dctl = dwc2_readl(hsotg->regs + DCTL); | |
5127 | dctl &= ~DCTL_RMTWKUPSIG; | |
5128 | dwc2_writel(dctl, hsotg->regs + DCTL); | |
5129 | } | |
5130 | ||
5131 | hsotg->hibernated = 0; | |
5132 | hsotg->lx_state = DWC2_L0; | |
5133 | dev_dbg(hsotg->dev, "Hibernation recovery completes here\n"); | |
5134 | ||
5135 | return ret; | |
5136 | } |