Commit | Line | Data |
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5fd54ace | 1 | // SPDX-License-Identifier: GPL-2.0 |
6fb914d7 | 2 | /* |
dfbc6fa3 AT |
3 | * Copyright (c) 2011 Samsung Electronics Co., Ltd. |
4 | * http://www.samsung.com | |
5b7d70c6 BD |
5 | * |
6 | * Copyright 2008 Openmoko, Inc. | |
7 | * Copyright 2008 Simtec Electronics | |
8 | * Ben Dooks <ben@simtec.co.uk> | |
9 | * http://armlinux.simtec.co.uk/ | |
10 | * | |
11 | * S3C USB2.0 High-speed / OtG driver | |
8b9bc460 | 12 | */ |
5b7d70c6 BD |
13 | |
14 | #include <linux/kernel.h> | |
15 | #include <linux/module.h> | |
16 | #include <linux/spinlock.h> | |
17 | #include <linux/interrupt.h> | |
18 | #include <linux/platform_device.h> | |
19 | #include <linux/dma-mapping.h> | |
7ad8096e | 20 | #include <linux/mutex.h> |
5b7d70c6 BD |
21 | #include <linux/seq_file.h> |
22 | #include <linux/delay.h> | |
23 | #include <linux/io.h> | |
5a0e3ad6 | 24 | #include <linux/slab.h> |
c50f056c | 25 | #include <linux/of_platform.h> |
5b7d70c6 BD |
26 | |
27 | #include <linux/usb/ch9.h> | |
28 | #include <linux/usb/gadget.h> | |
b2e587db | 29 | #include <linux/usb/phy.h> |
5b7d70c6 | 30 | |
f7c0b143 | 31 | #include "core.h" |
941fcce4 | 32 | #include "hw.h" |
5b7d70c6 BD |
33 | |
34 | /* conversion functions */ | |
1f91b4cc | 35 | static inline struct dwc2_hsotg_req *our_req(struct usb_request *req) |
5b7d70c6 | 36 | { |
1f91b4cc | 37 | return container_of(req, struct dwc2_hsotg_req, req); |
5b7d70c6 BD |
38 | } |
39 | ||
1f91b4cc | 40 | static inline struct dwc2_hsotg_ep *our_ep(struct usb_ep *ep) |
5b7d70c6 | 41 | { |
1f91b4cc | 42 | return container_of(ep, struct dwc2_hsotg_ep, ep); |
5b7d70c6 BD |
43 | } |
44 | ||
941fcce4 | 45 | static inline struct dwc2_hsotg *to_hsotg(struct usb_gadget *gadget) |
5b7d70c6 | 46 | { |
941fcce4 | 47 | return container_of(gadget, struct dwc2_hsotg, gadget); |
5b7d70c6 BD |
48 | } |
49 | ||
f25c42b8 | 50 | static inline void dwc2_set_bit(struct dwc2_hsotg *hsotg, u32 offset, u32 val) |
5b7d70c6 | 51 | { |
f25c42b8 | 52 | dwc2_writel(hsotg, dwc2_readl(hsotg, offset) | val, offset); |
5b7d70c6 BD |
53 | } |
54 | ||
f25c42b8 | 55 | static inline void dwc2_clear_bit(struct dwc2_hsotg *hsotg, u32 offset, u32 val) |
5b7d70c6 | 56 | { |
f25c42b8 | 57 | dwc2_writel(hsotg, dwc2_readl(hsotg, offset) & ~val, offset); |
5b7d70c6 BD |
58 | } |
59 | ||
1f91b4cc | 60 | static inline struct dwc2_hsotg_ep *index_to_ep(struct dwc2_hsotg *hsotg, |
c6f5c050 MYK |
61 | u32 ep_index, u32 dir_in) |
62 | { | |
63 | if (dir_in) | |
64 | return hsotg->eps_in[ep_index]; | |
65 | else | |
66 | return hsotg->eps_out[ep_index]; | |
67 | } | |
68 | ||
997f4f81 | 69 | /* forward declaration of functions */ |
1f91b4cc | 70 | static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg); |
5b7d70c6 BD |
71 | |
72 | /** | |
73 | * using_dma - return the DMA status of the driver. | |
74 | * @hsotg: The driver state. | |
75 | * | |
76 | * Return true if we're using DMA. | |
77 | * | |
78 | * Currently, we have the DMA support code worked into everywhere | |
79 | * that needs it, but the AMBA DMA implementation in the hardware can | |
80 | * only DMA from 32bit aligned addresses. This means that gadgets such | |
81 | * as the CDC Ethernet cannot work as they often pass packets which are | |
82 | * not 32bit aligned. | |
83 | * | |
84 | * Unfortunately the choice to use DMA or not is global to the controller | |
85 | * and seems to be only settable when the controller is being put through | |
86 | * a core reset. This means we either need to fix the gadgets to take | |
87 | * account of DMA alignment, or add bounce buffers (yuerk). | |
88 | * | |
edd74be8 | 89 | * g_using_dma is set depending on dts flag. |
5b7d70c6 | 90 | */ |
941fcce4 | 91 | static inline bool using_dma(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 92 | { |
05ee799f | 93 | return hsotg->params.g_dma; |
5b7d70c6 BD |
94 | } |
95 | ||
dec4b556 VA |
96 | /* |
97 | * using_desc_dma - return the descriptor DMA status of the driver. | |
98 | * @hsotg: The driver state. | |
99 | * | |
100 | * Return true if we're using descriptor DMA. | |
101 | */ | |
102 | static inline bool using_desc_dma(struct dwc2_hsotg *hsotg) | |
103 | { | |
104 | return hsotg->params.g_dma_desc; | |
105 | } | |
106 | ||
92d1635d VM |
107 | /** |
108 | * dwc2_gadget_incr_frame_num - Increments the targeted frame number. | |
109 | * @hs_ep: The endpoint | |
92d1635d VM |
110 | * |
111 | * This function will also check if the frame number overruns DSTS_SOFFN_LIMIT. | |
112 | * If an overrun occurs it will wrap the value and set the frame_overrun flag. | |
113 | */ | |
114 | static inline void dwc2_gadget_incr_frame_num(struct dwc2_hsotg_ep *hs_ep) | |
115 | { | |
116 | hs_ep->target_frame += hs_ep->interval; | |
117 | if (hs_ep->target_frame > DSTS_SOFFN_LIMIT) { | |
c1d5df69 | 118 | hs_ep->frame_overrun = true; |
92d1635d VM |
119 | hs_ep->target_frame &= DSTS_SOFFN_LIMIT; |
120 | } else { | |
c1d5df69 | 121 | hs_ep->frame_overrun = false; |
92d1635d VM |
122 | } |
123 | } | |
124 | ||
9d630b9c GT |
125 | /** |
126 | * dwc2_gadget_dec_frame_num_by_one - Decrements the targeted frame number | |
127 | * by one. | |
128 | * @hs_ep: The endpoint. | |
129 | * | |
130 | * This function used in service interval based scheduling flow to calculate | |
131 | * descriptor frame number filed value. For service interval mode frame | |
132 | * number in descriptor should point to last (u)frame in the interval. | |
133 | * | |
134 | */ | |
135 | static inline void dwc2_gadget_dec_frame_num_by_one(struct dwc2_hsotg_ep *hs_ep) | |
136 | { | |
137 | if (hs_ep->target_frame) | |
138 | hs_ep->target_frame -= 1; | |
139 | else | |
140 | hs_ep->target_frame = DSTS_SOFFN_LIMIT; | |
141 | } | |
142 | ||
5b7d70c6 | 143 | /** |
1f91b4cc | 144 | * dwc2_hsotg_en_gsint - enable one or more of the general interrupt |
5b7d70c6 BD |
145 | * @hsotg: The device state |
146 | * @ints: A bitmask of the interrupts to enable | |
147 | */ | |
1f91b4cc | 148 | static void dwc2_hsotg_en_gsint(struct dwc2_hsotg *hsotg, u32 ints) |
5b7d70c6 | 149 | { |
f25c42b8 | 150 | u32 gsintmsk = dwc2_readl(hsotg, GINTMSK); |
5b7d70c6 BD |
151 | u32 new_gsintmsk; |
152 | ||
153 | new_gsintmsk = gsintmsk | ints; | |
154 | ||
155 | if (new_gsintmsk != gsintmsk) { | |
156 | dev_dbg(hsotg->dev, "gsintmsk now 0x%08x\n", new_gsintmsk); | |
f25c42b8 | 157 | dwc2_writel(hsotg, new_gsintmsk, GINTMSK); |
5b7d70c6 BD |
158 | } |
159 | } | |
160 | ||
161 | /** | |
1f91b4cc | 162 | * dwc2_hsotg_disable_gsint - disable one or more of the general interrupt |
5b7d70c6 BD |
163 | * @hsotg: The device state |
164 | * @ints: A bitmask of the interrupts to enable | |
165 | */ | |
1f91b4cc | 166 | static void dwc2_hsotg_disable_gsint(struct dwc2_hsotg *hsotg, u32 ints) |
5b7d70c6 | 167 | { |
f25c42b8 | 168 | u32 gsintmsk = dwc2_readl(hsotg, GINTMSK); |
5b7d70c6 BD |
169 | u32 new_gsintmsk; |
170 | ||
171 | new_gsintmsk = gsintmsk & ~ints; | |
172 | ||
173 | if (new_gsintmsk != gsintmsk) | |
f25c42b8 | 174 | dwc2_writel(hsotg, new_gsintmsk, GINTMSK); |
5b7d70c6 BD |
175 | } |
176 | ||
177 | /** | |
1f91b4cc | 178 | * dwc2_hsotg_ctrl_epint - enable/disable an endpoint irq |
5b7d70c6 BD |
179 | * @hsotg: The device state |
180 | * @ep: The endpoint index | |
181 | * @dir_in: True if direction is in. | |
182 | * @en: The enable value, true to enable | |
183 | * | |
184 | * Set or clear the mask for an individual endpoint's interrupt | |
185 | * request. | |
186 | */ | |
1f91b4cc | 187 | static void dwc2_hsotg_ctrl_epint(struct dwc2_hsotg *hsotg, |
9da51974 | 188 | unsigned int ep, unsigned int dir_in, |
5b7d70c6 BD |
189 | unsigned int en) |
190 | { | |
191 | unsigned long flags; | |
192 | u32 bit = 1 << ep; | |
193 | u32 daint; | |
194 | ||
195 | if (!dir_in) | |
196 | bit <<= 16; | |
197 | ||
198 | local_irq_save(flags); | |
f25c42b8 | 199 | daint = dwc2_readl(hsotg, DAINTMSK); |
5b7d70c6 BD |
200 | if (en) |
201 | daint |= bit; | |
202 | else | |
203 | daint &= ~bit; | |
f25c42b8 | 204 | dwc2_writel(hsotg, daint, DAINTMSK); |
5b7d70c6 BD |
205 | local_irq_restore(flags); |
206 | } | |
207 | ||
c138ecfa SA |
208 | /** |
209 | * dwc2_hsotg_tx_fifo_count - return count of TX FIFOs in device mode | |
6fb914d7 GT |
210 | * |
211 | * @hsotg: Programming view of the DWC_otg controller | |
c138ecfa SA |
212 | */ |
213 | int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg *hsotg) | |
214 | { | |
215 | if (hsotg->hw_params.en_multiple_tx_fifo) | |
216 | /* In dedicated FIFO mode we need count of IN EPs */ | |
9273083a | 217 | return hsotg->hw_params.num_dev_in_eps; |
c138ecfa SA |
218 | else |
219 | /* In shared FIFO mode we need count of Periodic IN EPs */ | |
220 | return hsotg->hw_params.num_dev_perio_in_ep; | |
221 | } | |
222 | ||
c138ecfa SA |
223 | /** |
224 | * dwc2_hsotg_tx_fifo_total_depth - return total FIFO depth available for | |
225 | * device mode TX FIFOs | |
6fb914d7 GT |
226 | * |
227 | * @hsotg: Programming view of the DWC_otg controller | |
c138ecfa SA |
228 | */ |
229 | int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg) | |
230 | { | |
c138ecfa SA |
231 | int addr; |
232 | int tx_addr_max; | |
233 | u32 np_tx_fifo_size; | |
234 | ||
235 | np_tx_fifo_size = min_t(u32, hsotg->hw_params.dev_nperio_tx_fifo_size, | |
236 | hsotg->params.g_np_tx_fifo_size); | |
237 | ||
238 | /* Get Endpoint Info Control block size in DWORDs. */ | |
9273083a | 239 | tx_addr_max = hsotg->hw_params.total_fifo_size; |
c138ecfa SA |
240 | |
241 | addr = hsotg->params.g_rx_fifo_size + np_tx_fifo_size; | |
242 | if (tx_addr_max <= addr) | |
243 | return 0; | |
244 | ||
245 | return tx_addr_max - addr; | |
246 | } | |
247 | ||
248 | /** | |
249 | * dwc2_hsotg_tx_fifo_average_depth - returns average depth of device mode | |
250 | * TX FIFOs | |
6fb914d7 GT |
251 | * |
252 | * @hsotg: Programming view of the DWC_otg controller | |
c138ecfa SA |
253 | */ |
254 | int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg *hsotg) | |
255 | { | |
256 | int tx_fifo_count; | |
257 | int tx_fifo_depth; | |
258 | ||
259 | tx_fifo_depth = dwc2_hsotg_tx_fifo_total_depth(hsotg); | |
260 | ||
261 | tx_fifo_count = dwc2_hsotg_tx_fifo_count(hsotg); | |
262 | ||
263 | if (!tx_fifo_count) | |
264 | return tx_fifo_depth; | |
265 | else | |
266 | return tx_fifo_depth / tx_fifo_count; | |
267 | } | |
268 | ||
5b7d70c6 | 269 | /** |
1f91b4cc | 270 | * dwc2_hsotg_init_fifo - initialise non-periodic FIFOs |
5b7d70c6 BD |
271 | * @hsotg: The device instance. |
272 | */ | |
1f91b4cc | 273 | static void dwc2_hsotg_init_fifo(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 274 | { |
2317eacd | 275 | unsigned int ep; |
0f002d20 | 276 | unsigned int addr; |
1703a6d3 | 277 | int timeout; |
79d6b8c5 | 278 | |
0f002d20 | 279 | u32 val; |
05ee799f | 280 | u32 *txfsz = hsotg->params.g_tx_fifo_size; |
0f002d20 | 281 | |
7fcbc95c GH |
282 | /* Reset fifo map if not correctly cleared during previous session */ |
283 | WARN_ON(hsotg->fifo_map); | |
284 | hsotg->fifo_map = 0; | |
285 | ||
0a176279 | 286 | /* set RX/NPTX FIFO sizes */ |
f25c42b8 GS |
287 | dwc2_writel(hsotg, hsotg->params.g_rx_fifo_size, GRXFSIZ); |
288 | dwc2_writel(hsotg, (hsotg->params.g_rx_fifo_size << | |
289 | FIFOSIZE_STARTADDR_SHIFT) | | |
05ee799f | 290 | (hsotg->params.g_np_tx_fifo_size << FIFOSIZE_DEPTH_SHIFT), |
f25c42b8 | 291 | GNPTXFSIZ); |
0f002d20 | 292 | |
8b9bc460 LM |
293 | /* |
294 | * arange all the rest of the TX FIFOs, as some versions of this | |
0f002d20 BD |
295 | * block have overlapping default addresses. This also ensures |
296 | * that if the settings have been changed, then they are set to | |
8b9bc460 LM |
297 | * known values. |
298 | */ | |
0f002d20 BD |
299 | |
300 | /* start at the end of the GNPTXFSIZ, rounded up */ | |
05ee799f | 301 | addr = hsotg->params.g_rx_fifo_size + hsotg->params.g_np_tx_fifo_size; |
0f002d20 | 302 | |
8b9bc460 | 303 | /* |
0a176279 | 304 | * Configure fifos sizes from provided configuration and assign |
b203d0a2 RB |
305 | * them to endpoints dynamically according to maxpacket size value of |
306 | * given endpoint. | |
8b9bc460 | 307 | */ |
2317eacd | 308 | for (ep = 1; ep < MAX_EPS_CHANNELS; ep++) { |
05ee799f | 309 | if (!txfsz[ep]) |
3fa95385 JY |
310 | continue; |
311 | val = addr; | |
05ee799f JY |
312 | val |= txfsz[ep] << FIFOSIZE_DEPTH_SHIFT; |
313 | WARN_ONCE(addr + txfsz[ep] > hsotg->fifo_mem, | |
3fa95385 | 314 | "insufficient fifo memory"); |
05ee799f | 315 | addr += txfsz[ep]; |
0f002d20 | 316 | |
f25c42b8 GS |
317 | dwc2_writel(hsotg, val, DPTXFSIZN(ep)); |
318 | val = dwc2_readl(hsotg, DPTXFSIZN(ep)); | |
0f002d20 | 319 | } |
1703a6d3 | 320 | |
f25c42b8 | 321 | dwc2_writel(hsotg, hsotg->hw_params.total_fifo_size | |
f87c842f | 322 | addr << GDFIFOCFG_EPINFOBASE_SHIFT, |
f25c42b8 | 323 | GDFIFOCFG); |
8b9bc460 LM |
324 | /* |
325 | * according to p428 of the design guide, we need to ensure that | |
326 | * all fifos are flushed before continuing | |
327 | */ | |
1703a6d3 | 328 | |
f25c42b8 GS |
329 | dwc2_writel(hsotg, GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH | |
330 | GRSTCTL_RXFFLSH, GRSTCTL); | |
1703a6d3 BD |
331 | |
332 | /* wait until the fifos are both flushed */ | |
333 | timeout = 100; | |
334 | while (1) { | |
f25c42b8 | 335 | val = dwc2_readl(hsotg, GRSTCTL); |
1703a6d3 | 336 | |
47a1685f | 337 | if ((val & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH)) == 0) |
1703a6d3 BD |
338 | break; |
339 | ||
340 | if (--timeout == 0) { | |
341 | dev_err(hsotg->dev, | |
342 | "%s: timeout flushing fifos (GRSTCTL=%08x)\n", | |
343 | __func__, val); | |
48b20bcb | 344 | break; |
1703a6d3 BD |
345 | } |
346 | ||
347 | udelay(1); | |
348 | } | |
349 | ||
350 | dev_dbg(hsotg->dev, "FIFOs reset, timeout at %d\n", timeout); | |
5b7d70c6 BD |
351 | } |
352 | ||
353 | /** | |
6fb914d7 | 354 | * dwc2_hsotg_ep_alloc_request - allocate USB rerequest structure |
5b7d70c6 BD |
355 | * @ep: USB endpoint to allocate request for. |
356 | * @flags: Allocation flags | |
357 | * | |
358 | * Allocate a new USB request structure appropriate for the specified endpoint | |
359 | */ | |
1f91b4cc | 360 | static struct usb_request *dwc2_hsotg_ep_alloc_request(struct usb_ep *ep, |
9da51974 | 361 | gfp_t flags) |
5b7d70c6 | 362 | { |
1f91b4cc | 363 | struct dwc2_hsotg_req *req; |
5b7d70c6 | 364 | |
ec33efe2 | 365 | req = kzalloc(sizeof(*req), flags); |
5b7d70c6 BD |
366 | if (!req) |
367 | return NULL; | |
368 | ||
369 | INIT_LIST_HEAD(&req->queue); | |
370 | ||
5b7d70c6 BD |
371 | return &req->req; |
372 | } | |
373 | ||
374 | /** | |
375 | * is_ep_periodic - return true if the endpoint is in periodic mode. | |
376 | * @hs_ep: The endpoint to query. | |
377 | * | |
378 | * Returns true if the endpoint is in periodic mode, meaning it is being | |
379 | * used for an Interrupt or ISO transfer. | |
380 | */ | |
1f91b4cc | 381 | static inline int is_ep_periodic(struct dwc2_hsotg_ep *hs_ep) |
5b7d70c6 BD |
382 | { |
383 | return hs_ep->periodic; | |
384 | } | |
385 | ||
386 | /** | |
1f91b4cc | 387 | * dwc2_hsotg_unmap_dma - unmap the DMA memory being used for the request |
5b7d70c6 BD |
388 | * @hsotg: The device state. |
389 | * @hs_ep: The endpoint for the request | |
390 | * @hs_req: The request being processed. | |
391 | * | |
1f91b4cc | 392 | * This is the reverse of dwc2_hsotg_map_dma(), called for the completion |
5b7d70c6 | 393 | * of a request to ensure the buffer is ready for access by the caller. |
8b9bc460 | 394 | */ |
1f91b4cc | 395 | static void dwc2_hsotg_unmap_dma(struct dwc2_hsotg *hsotg, |
9da51974 | 396 | struct dwc2_hsotg_ep *hs_ep, |
1f91b4cc | 397 | struct dwc2_hsotg_req *hs_req) |
5b7d70c6 BD |
398 | { |
399 | struct usb_request *req = &hs_req->req; | |
9da51974 | 400 | |
17d966a3 | 401 | usb_gadget_unmap_request(&hsotg->gadget, req, hs_ep->dir_in); |
5b7d70c6 BD |
402 | } |
403 | ||
0f6b80c0 VA |
404 | /* |
405 | * dwc2_gadget_alloc_ctrl_desc_chains - allocate DMA descriptor chains | |
406 | * for Control endpoint | |
407 | * @hsotg: The device state. | |
408 | * | |
409 | * This function will allocate 4 descriptor chains for EP 0: 2 for | |
410 | * Setup stage, per one for IN and OUT data/status transactions. | |
411 | */ | |
412 | static int dwc2_gadget_alloc_ctrl_desc_chains(struct dwc2_hsotg *hsotg) | |
413 | { | |
414 | hsotg->setup_desc[0] = | |
415 | dmam_alloc_coherent(hsotg->dev, | |
416 | sizeof(struct dwc2_dma_desc), | |
417 | &hsotg->setup_desc_dma[0], | |
418 | GFP_KERNEL); | |
419 | if (!hsotg->setup_desc[0]) | |
420 | goto fail; | |
421 | ||
422 | hsotg->setup_desc[1] = | |
423 | dmam_alloc_coherent(hsotg->dev, | |
424 | sizeof(struct dwc2_dma_desc), | |
425 | &hsotg->setup_desc_dma[1], | |
426 | GFP_KERNEL); | |
427 | if (!hsotg->setup_desc[1]) | |
428 | goto fail; | |
429 | ||
430 | hsotg->ctrl_in_desc = | |
431 | dmam_alloc_coherent(hsotg->dev, | |
432 | sizeof(struct dwc2_dma_desc), | |
433 | &hsotg->ctrl_in_desc_dma, | |
434 | GFP_KERNEL); | |
435 | if (!hsotg->ctrl_in_desc) | |
436 | goto fail; | |
437 | ||
438 | hsotg->ctrl_out_desc = | |
439 | dmam_alloc_coherent(hsotg->dev, | |
440 | sizeof(struct dwc2_dma_desc), | |
441 | &hsotg->ctrl_out_desc_dma, | |
442 | GFP_KERNEL); | |
443 | if (!hsotg->ctrl_out_desc) | |
444 | goto fail; | |
445 | ||
446 | return 0; | |
447 | ||
448 | fail: | |
449 | return -ENOMEM; | |
450 | } | |
451 | ||
5b7d70c6 | 452 | /** |
1f91b4cc | 453 | * dwc2_hsotg_write_fifo - write packet Data to the TxFIFO |
5b7d70c6 BD |
454 | * @hsotg: The controller state. |
455 | * @hs_ep: The endpoint we're going to write for. | |
456 | * @hs_req: The request to write data for. | |
457 | * | |
458 | * This is called when the TxFIFO has some space in it to hold a new | |
459 | * transmission and we have something to give it. The actual setup of | |
460 | * the data size is done elsewhere, so all we have to do is to actually | |
461 | * write the data. | |
462 | * | |
463 | * The return value is zero if there is more space (or nothing was done) | |
464 | * otherwise -ENOSPC is returned if the FIFO space was used up. | |
465 | * | |
466 | * This routine is only needed for PIO | |
8b9bc460 | 467 | */ |
1f91b4cc | 468 | static int dwc2_hsotg_write_fifo(struct dwc2_hsotg *hsotg, |
9da51974 | 469 | struct dwc2_hsotg_ep *hs_ep, |
1f91b4cc | 470 | struct dwc2_hsotg_req *hs_req) |
5b7d70c6 BD |
471 | { |
472 | bool periodic = is_ep_periodic(hs_ep); | |
f25c42b8 | 473 | u32 gnptxsts = dwc2_readl(hsotg, GNPTXSTS); |
5b7d70c6 BD |
474 | int buf_pos = hs_req->req.actual; |
475 | int to_write = hs_ep->size_loaded; | |
476 | void *data; | |
477 | int can_write; | |
478 | int pkt_round; | |
4fca54aa | 479 | int max_transfer; |
5b7d70c6 BD |
480 | |
481 | to_write -= (buf_pos - hs_ep->last_load); | |
482 | ||
483 | /* if there's nothing to write, get out early */ | |
484 | if (to_write == 0) | |
485 | return 0; | |
486 | ||
10aebc77 | 487 | if (periodic && !hsotg->dedicated_fifos) { |
f25c42b8 | 488 | u32 epsize = dwc2_readl(hsotg, DIEPTSIZ(hs_ep->index)); |
5b7d70c6 BD |
489 | int size_left; |
490 | int size_done; | |
491 | ||
8b9bc460 LM |
492 | /* |
493 | * work out how much data was loaded so we can calculate | |
494 | * how much data is left in the fifo. | |
495 | */ | |
5b7d70c6 | 496 | |
47a1685f | 497 | size_left = DXEPTSIZ_XFERSIZE_GET(epsize); |
5b7d70c6 | 498 | |
8b9bc460 LM |
499 | /* |
500 | * if shared fifo, we cannot write anything until the | |
e7a9ff54 BD |
501 | * previous data has been completely sent. |
502 | */ | |
503 | if (hs_ep->fifo_load != 0) { | |
1f91b4cc | 504 | dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP); |
e7a9ff54 BD |
505 | return -ENOSPC; |
506 | } | |
507 | ||
5b7d70c6 BD |
508 | dev_dbg(hsotg->dev, "%s: left=%d, load=%d, fifo=%d, size %d\n", |
509 | __func__, size_left, | |
510 | hs_ep->size_loaded, hs_ep->fifo_load, hs_ep->fifo_size); | |
511 | ||
512 | /* how much of the data has moved */ | |
513 | size_done = hs_ep->size_loaded - size_left; | |
514 | ||
515 | /* how much data is left in the fifo */ | |
516 | can_write = hs_ep->fifo_load - size_done; | |
517 | dev_dbg(hsotg->dev, "%s: => can_write1=%d\n", | |
518 | __func__, can_write); | |
519 | ||
520 | can_write = hs_ep->fifo_size - can_write; | |
521 | dev_dbg(hsotg->dev, "%s: => can_write2=%d\n", | |
522 | __func__, can_write); | |
523 | ||
524 | if (can_write <= 0) { | |
1f91b4cc | 525 | dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP); |
5b7d70c6 BD |
526 | return -ENOSPC; |
527 | } | |
10aebc77 | 528 | } else if (hsotg->dedicated_fifos && hs_ep->index != 0) { |
f25c42b8 GS |
529 | can_write = dwc2_readl(hsotg, |
530 | DTXFSTS(hs_ep->fifo_index)); | |
10aebc77 BD |
531 | |
532 | can_write &= 0xffff; | |
533 | can_write *= 4; | |
5b7d70c6 | 534 | } else { |
47a1685f | 535 | if (GNPTXSTS_NP_TXQ_SPC_AVAIL_GET(gnptxsts) == 0) { |
5b7d70c6 BD |
536 | dev_dbg(hsotg->dev, |
537 | "%s: no queue slots available (0x%08x)\n", | |
538 | __func__, gnptxsts); | |
539 | ||
1f91b4cc | 540 | dwc2_hsotg_en_gsint(hsotg, GINTSTS_NPTXFEMP); |
5b7d70c6 BD |
541 | return -ENOSPC; |
542 | } | |
543 | ||
47a1685f | 544 | can_write = GNPTXSTS_NP_TXF_SPC_AVAIL_GET(gnptxsts); |
679f9b7c | 545 | can_write *= 4; /* fifo size is in 32bit quantities. */ |
5b7d70c6 BD |
546 | } |
547 | ||
4fca54aa RB |
548 | max_transfer = hs_ep->ep.maxpacket * hs_ep->mc; |
549 | ||
550 | dev_dbg(hsotg->dev, "%s: GNPTXSTS=%08x, can=%d, to=%d, max_transfer %d\n", | |
9da51974 | 551 | __func__, gnptxsts, can_write, to_write, max_transfer); |
5b7d70c6 | 552 | |
8b9bc460 LM |
553 | /* |
554 | * limit to 512 bytes of data, it seems at least on the non-periodic | |
5b7d70c6 BD |
555 | * FIFO, requests of >512 cause the endpoint to get stuck with a |
556 | * fragment of the end of the transfer in it. | |
557 | */ | |
811f3303 | 558 | if (can_write > 512 && !periodic) |
5b7d70c6 BD |
559 | can_write = 512; |
560 | ||
8b9bc460 LM |
561 | /* |
562 | * limit the write to one max-packet size worth of data, but allow | |
03e10e5a | 563 | * the transfer to return that it did not run out of fifo space |
8b9bc460 LM |
564 | * doing it. |
565 | */ | |
4fca54aa RB |
566 | if (to_write > max_transfer) { |
567 | to_write = max_transfer; | |
03e10e5a | 568 | |
5cb2ff0c RB |
569 | /* it's needed only when we do not use dedicated fifos */ |
570 | if (!hsotg->dedicated_fifos) | |
1f91b4cc | 571 | dwc2_hsotg_en_gsint(hsotg, |
9da51974 | 572 | periodic ? GINTSTS_PTXFEMP : |
47a1685f | 573 | GINTSTS_NPTXFEMP); |
03e10e5a BD |
574 | } |
575 | ||
5b7d70c6 BD |
576 | /* see if we can write data */ |
577 | ||
578 | if (to_write > can_write) { | |
579 | to_write = can_write; | |
4fca54aa | 580 | pkt_round = to_write % max_transfer; |
5b7d70c6 | 581 | |
8b9bc460 LM |
582 | /* |
583 | * Round the write down to an | |
5b7d70c6 BD |
584 | * exact number of packets. |
585 | * | |
586 | * Note, we do not currently check to see if we can ever | |
587 | * write a full packet or not to the FIFO. | |
588 | */ | |
589 | ||
590 | if (pkt_round) | |
591 | to_write -= pkt_round; | |
592 | ||
8b9bc460 LM |
593 | /* |
594 | * enable correct FIFO interrupt to alert us when there | |
595 | * is more room left. | |
596 | */ | |
5b7d70c6 | 597 | |
5cb2ff0c RB |
598 | /* it's needed only when we do not use dedicated fifos */ |
599 | if (!hsotg->dedicated_fifos) | |
1f91b4cc | 600 | dwc2_hsotg_en_gsint(hsotg, |
9da51974 | 601 | periodic ? GINTSTS_PTXFEMP : |
47a1685f | 602 | GINTSTS_NPTXFEMP); |
5b7d70c6 BD |
603 | } |
604 | ||
605 | dev_dbg(hsotg->dev, "write %d/%d, can_write %d, done %d\n", | |
9da51974 | 606 | to_write, hs_req->req.length, can_write, buf_pos); |
5b7d70c6 BD |
607 | |
608 | if (to_write <= 0) | |
609 | return -ENOSPC; | |
610 | ||
611 | hs_req->req.actual = buf_pos + to_write; | |
612 | hs_ep->total_data += to_write; | |
613 | ||
614 | if (periodic) | |
615 | hs_ep->fifo_load += to_write; | |
616 | ||
617 | to_write = DIV_ROUND_UP(to_write, 4); | |
618 | data = hs_req->req.buf + buf_pos; | |
619 | ||
342ccce1 | 620 | dwc2_writel_rep(hsotg, EPFIFO(hs_ep->index), data, to_write); |
5b7d70c6 BD |
621 | |
622 | return (to_write >= can_write) ? -ENOSPC : 0; | |
623 | } | |
624 | ||
625 | /** | |
626 | * get_ep_limit - get the maximum data legnth for this endpoint | |
627 | * @hs_ep: The endpoint | |
628 | * | |
629 | * Return the maximum data that can be queued in one go on a given endpoint | |
630 | * so that transfers that are too long can be split. | |
631 | */ | |
9da51974 | 632 | static unsigned int get_ep_limit(struct dwc2_hsotg_ep *hs_ep) |
5b7d70c6 BD |
633 | { |
634 | int index = hs_ep->index; | |
9da51974 JY |
635 | unsigned int maxsize; |
636 | unsigned int maxpkt; | |
5b7d70c6 BD |
637 | |
638 | if (index != 0) { | |
47a1685f DN |
639 | maxsize = DXEPTSIZ_XFERSIZE_LIMIT + 1; |
640 | maxpkt = DXEPTSIZ_PKTCNT_LIMIT + 1; | |
5b7d70c6 | 641 | } else { |
9da51974 | 642 | maxsize = 64 + 64; |
66e5c643 | 643 | if (hs_ep->dir_in) |
47a1685f | 644 | maxpkt = DIEPTSIZ0_PKTCNT_LIMIT + 1; |
66e5c643 | 645 | else |
5b7d70c6 | 646 | maxpkt = 2; |
5b7d70c6 BD |
647 | } |
648 | ||
649 | /* we made the constant loading easier above by using +1 */ | |
650 | maxpkt--; | |
651 | maxsize--; | |
652 | ||
8b9bc460 LM |
653 | /* |
654 | * constrain by packet count if maxpkts*pktsize is greater | |
655 | * than the length register size. | |
656 | */ | |
5b7d70c6 BD |
657 | |
658 | if ((maxpkt * hs_ep->ep.maxpacket) < maxsize) | |
659 | maxsize = maxpkt * hs_ep->ep.maxpacket; | |
660 | ||
661 | return maxsize; | |
662 | } | |
663 | ||
381fc8f8 | 664 | /** |
38beaec6 JY |
665 | * dwc2_hsotg_read_frameno - read current frame number |
666 | * @hsotg: The device instance | |
667 | * | |
668 | * Return the current frame number | |
669 | */ | |
381fc8f8 VM |
670 | static u32 dwc2_hsotg_read_frameno(struct dwc2_hsotg *hsotg) |
671 | { | |
672 | u32 dsts; | |
673 | ||
f25c42b8 | 674 | dsts = dwc2_readl(hsotg, DSTS); |
381fc8f8 VM |
675 | dsts &= DSTS_SOFFN_MASK; |
676 | dsts >>= DSTS_SOFFN_SHIFT; | |
677 | ||
678 | return dsts; | |
679 | } | |
680 | ||
cf77b5fb VA |
681 | /** |
682 | * dwc2_gadget_get_chain_limit - get the maximum data payload value of the | |
683 | * DMA descriptor chain prepared for specific endpoint | |
684 | * @hs_ep: The endpoint | |
685 | * | |
686 | * Return the maximum data that can be queued in one go on a given endpoint | |
687 | * depending on its descriptor chain capacity so that transfers that | |
688 | * are too long can be split. | |
689 | */ | |
690 | static unsigned int dwc2_gadget_get_chain_limit(struct dwc2_hsotg_ep *hs_ep) | |
691 | { | |
692 | int is_isoc = hs_ep->isochronous; | |
693 | unsigned int maxsize; | |
694 | ||
695 | if (is_isoc) | |
696 | maxsize = hs_ep->dir_in ? DEV_DMA_ISOC_TX_NBYTES_LIMIT : | |
697 | DEV_DMA_ISOC_RX_NBYTES_LIMIT; | |
698 | else | |
699 | maxsize = DEV_DMA_NBYTES_LIMIT; | |
700 | ||
701 | /* Above size of one descriptor was chosen, multiple it */ | |
702 | maxsize *= MAX_DMA_DESC_NUM_GENERIC; | |
703 | ||
704 | return maxsize; | |
705 | } | |
706 | ||
e02f9aa6 VA |
707 | /* |
708 | * dwc2_gadget_get_desc_params - get DMA descriptor parameters. | |
709 | * @hs_ep: The endpoint | |
710 | * @mask: RX/TX bytes mask to be defined | |
711 | * | |
712 | * Returns maximum data payload for one descriptor after analyzing endpoint | |
713 | * characteristics. | |
714 | * DMA descriptor transfer bytes limit depends on EP type: | |
715 | * Control out - MPS, | |
716 | * Isochronous - descriptor rx/tx bytes bitfield limit, | |
717 | * Control In/Bulk/Interrupt - multiple of mps. This will allow to not | |
718 | * have concatenations from various descriptors within one packet. | |
719 | * | |
720 | * Selects corresponding mask for RX/TX bytes as well. | |
721 | */ | |
722 | static u32 dwc2_gadget_get_desc_params(struct dwc2_hsotg_ep *hs_ep, u32 *mask) | |
723 | { | |
724 | u32 mps = hs_ep->ep.maxpacket; | |
725 | int dir_in = hs_ep->dir_in; | |
726 | u32 desc_size = 0; | |
727 | ||
728 | if (!hs_ep->index && !dir_in) { | |
729 | desc_size = mps; | |
730 | *mask = DEV_DMA_NBYTES_MASK; | |
731 | } else if (hs_ep->isochronous) { | |
732 | if (dir_in) { | |
733 | desc_size = DEV_DMA_ISOC_TX_NBYTES_LIMIT; | |
734 | *mask = DEV_DMA_ISOC_TX_NBYTES_MASK; | |
735 | } else { | |
736 | desc_size = DEV_DMA_ISOC_RX_NBYTES_LIMIT; | |
737 | *mask = DEV_DMA_ISOC_RX_NBYTES_MASK; | |
738 | } | |
739 | } else { | |
740 | desc_size = DEV_DMA_NBYTES_LIMIT; | |
741 | *mask = DEV_DMA_NBYTES_MASK; | |
742 | ||
743 | /* Round down desc_size to be mps multiple */ | |
744 | desc_size -= desc_size % mps; | |
745 | } | |
746 | ||
747 | return desc_size; | |
748 | } | |
749 | ||
750 | /* | |
751 | * dwc2_gadget_config_nonisoc_xfer_ddma - prepare non ISOC DMA desc chain. | |
752 | * @hs_ep: The endpoint | |
753 | * @dma_buff: DMA address to use | |
754 | * @len: Length of the transfer | |
755 | * | |
756 | * This function will iterate over descriptor chain and fill its entries | |
757 | * with corresponding information based on transfer data. | |
758 | */ | |
759 | static void dwc2_gadget_config_nonisoc_xfer_ddma(struct dwc2_hsotg_ep *hs_ep, | |
760 | dma_addr_t dma_buff, | |
761 | unsigned int len) | |
762 | { | |
763 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
764 | int dir_in = hs_ep->dir_in; | |
765 | struct dwc2_dma_desc *desc = hs_ep->desc_list; | |
766 | u32 mps = hs_ep->ep.maxpacket; | |
767 | u32 maxsize = 0; | |
768 | u32 offset = 0; | |
769 | u32 mask = 0; | |
770 | int i; | |
771 | ||
772 | maxsize = dwc2_gadget_get_desc_params(hs_ep, &mask); | |
773 | ||
774 | hs_ep->desc_count = (len / maxsize) + | |
775 | ((len % maxsize) ? 1 : 0); | |
776 | if (len == 0) | |
777 | hs_ep->desc_count = 1; | |
778 | ||
779 | for (i = 0; i < hs_ep->desc_count; ++i) { | |
780 | desc->status = 0; | |
781 | desc->status |= (DEV_DMA_BUFF_STS_HBUSY | |
782 | << DEV_DMA_BUFF_STS_SHIFT); | |
783 | ||
784 | if (len > maxsize) { | |
785 | if (!hs_ep->index && !dir_in) | |
786 | desc->status |= (DEV_DMA_L | DEV_DMA_IOC); | |
787 | ||
788 | desc->status |= (maxsize << | |
789 | DEV_DMA_NBYTES_SHIFT & mask); | |
790 | desc->buf = dma_buff + offset; | |
791 | ||
792 | len -= maxsize; | |
793 | offset += maxsize; | |
794 | } else { | |
795 | desc->status |= (DEV_DMA_L | DEV_DMA_IOC); | |
796 | ||
797 | if (dir_in) | |
798 | desc->status |= (len % mps) ? DEV_DMA_SHORT : | |
799 | ((hs_ep->send_zlp) ? DEV_DMA_SHORT : 0); | |
800 | if (len > maxsize) | |
801 | dev_err(hsotg->dev, "wrong len %d\n", len); | |
802 | ||
803 | desc->status |= | |
804 | len << DEV_DMA_NBYTES_SHIFT & mask; | |
805 | desc->buf = dma_buff + offset; | |
806 | } | |
807 | ||
808 | desc->status &= ~DEV_DMA_BUFF_STS_MASK; | |
809 | desc->status |= (DEV_DMA_BUFF_STS_HREADY | |
810 | << DEV_DMA_BUFF_STS_SHIFT); | |
811 | desc++; | |
812 | } | |
813 | } | |
814 | ||
540ccba0 VA |
815 | /* |
816 | * dwc2_gadget_fill_isoc_desc - fills next isochronous descriptor in chain. | |
817 | * @hs_ep: The isochronous endpoint. | |
818 | * @dma_buff: usb requests dma buffer. | |
819 | * @len: usb request transfer length. | |
820 | * | |
729cac69 | 821 | * Fills next free descriptor with the data of the arrived usb request, |
540ccba0 VA |
822 | * frame info, sets Last and IOC bits increments next_desc. If filled |
823 | * descriptor is not the first one, removes L bit from the previous descriptor | |
824 | * status. | |
825 | */ | |
826 | static int dwc2_gadget_fill_isoc_desc(struct dwc2_hsotg_ep *hs_ep, | |
827 | dma_addr_t dma_buff, unsigned int len) | |
828 | { | |
829 | struct dwc2_dma_desc *desc; | |
830 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
831 | u32 index; | |
832 | u32 maxsize = 0; | |
833 | u32 mask = 0; | |
1d8e5c00 | 834 | u8 pid = 0; |
540ccba0 VA |
835 | |
836 | maxsize = dwc2_gadget_get_desc_params(hs_ep, &mask); | |
540ccba0 | 837 | |
729cac69 MH |
838 | index = hs_ep->next_desc; |
839 | desc = &hs_ep->desc_list[index]; | |
540ccba0 | 840 | |
729cac69 MH |
841 | /* Check if descriptor chain full */ |
842 | if ((desc->status >> DEV_DMA_BUFF_STS_SHIFT) == | |
843 | DEV_DMA_BUFF_STS_HREADY) { | |
844 | dev_dbg(hsotg->dev, "%s: desc chain full\n", __func__); | |
845 | return 1; | |
540ccba0 VA |
846 | } |
847 | ||
540ccba0 VA |
848 | /* Clear L bit of previous desc if more than one entries in the chain */ |
849 | if (hs_ep->next_desc) | |
850 | hs_ep->desc_list[index - 1].status &= ~DEV_DMA_L; | |
851 | ||
852 | dev_dbg(hsotg->dev, "%s: Filling ep %d, dir %s isoc desc # %d\n", | |
853 | __func__, hs_ep->index, hs_ep->dir_in ? "in" : "out", index); | |
854 | ||
855 | desc->status = 0; | |
856 | desc->status |= (DEV_DMA_BUFF_STS_HBUSY << DEV_DMA_BUFF_STS_SHIFT); | |
857 | ||
858 | desc->buf = dma_buff; | |
859 | desc->status |= (DEV_DMA_L | DEV_DMA_IOC | | |
860 | ((len << DEV_DMA_NBYTES_SHIFT) & mask)); | |
861 | ||
862 | if (hs_ep->dir_in) { | |
1d8e5c00 MH |
863 | if (len) |
864 | pid = DIV_ROUND_UP(len, hs_ep->ep.maxpacket); | |
865 | else | |
866 | pid = 1; | |
867 | desc->status |= ((pid << DEV_DMA_ISOC_PID_SHIFT) & | |
540ccba0 VA |
868 | DEV_DMA_ISOC_PID_MASK) | |
869 | ((len % hs_ep->ep.maxpacket) ? | |
870 | DEV_DMA_SHORT : 0) | | |
871 | ((hs_ep->target_frame << | |
872 | DEV_DMA_ISOC_FRNUM_SHIFT) & | |
873 | DEV_DMA_ISOC_FRNUM_MASK); | |
874 | } | |
875 | ||
876 | desc->status &= ~DEV_DMA_BUFF_STS_MASK; | |
877 | desc->status |= (DEV_DMA_BUFF_STS_HREADY << DEV_DMA_BUFF_STS_SHIFT); | |
878 | ||
729cac69 MH |
879 | /* Increment frame number by interval for IN */ |
880 | if (hs_ep->dir_in) | |
881 | dwc2_gadget_incr_frame_num(hs_ep); | |
882 | ||
540ccba0 VA |
883 | /* Update index of last configured entry in the chain */ |
884 | hs_ep->next_desc++; | |
729cac69 MH |
885 | if (hs_ep->next_desc >= MAX_DMA_DESC_NUM_GENERIC) |
886 | hs_ep->next_desc = 0; | |
540ccba0 VA |
887 | |
888 | return 0; | |
889 | } | |
890 | ||
891 | /* | |
892 | * dwc2_gadget_start_isoc_ddma - start isochronous transfer in DDMA | |
893 | * @hs_ep: The isochronous endpoint. | |
894 | * | |
729cac69 | 895 | * Prepare descriptor chain for isochronous endpoints. Afterwards |
540ccba0 | 896 | * write DMA address to HW and enable the endpoint. |
540ccba0 VA |
897 | */ |
898 | static void dwc2_gadget_start_isoc_ddma(struct dwc2_hsotg_ep *hs_ep) | |
899 | { | |
900 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
901 | struct dwc2_hsotg_req *hs_req, *treq; | |
902 | int index = hs_ep->index; | |
903 | int ret; | |
729cac69 | 904 | int i; |
540ccba0 VA |
905 | u32 dma_reg; |
906 | u32 depctl; | |
907 | u32 ctrl; | |
729cac69 | 908 | struct dwc2_dma_desc *desc; |
540ccba0 VA |
909 | |
910 | if (list_empty(&hs_ep->queue)) { | |
1ffba905 | 911 | hs_ep->target_frame = TARGET_FRAME_INITIAL; |
540ccba0 VA |
912 | dev_dbg(hsotg->dev, "%s: No requests in queue\n", __func__); |
913 | return; | |
914 | } | |
915 | ||
729cac69 MH |
916 | /* Initialize descriptor chain by Host Busy status */ |
917 | for (i = 0; i < MAX_DMA_DESC_NUM_GENERIC; i++) { | |
918 | desc = &hs_ep->desc_list[i]; | |
919 | desc->status = 0; | |
920 | desc->status |= (DEV_DMA_BUFF_STS_HBUSY | |
921 | << DEV_DMA_BUFF_STS_SHIFT); | |
922 | } | |
923 | ||
924 | hs_ep->next_desc = 0; | |
540ccba0 VA |
925 | list_for_each_entry_safe(hs_req, treq, &hs_ep->queue, queue) { |
926 | ret = dwc2_gadget_fill_isoc_desc(hs_ep, hs_req->req.dma, | |
927 | hs_req->req.length); | |
729cac69 | 928 | if (ret) |
540ccba0 | 929 | break; |
540ccba0 VA |
930 | } |
931 | ||
729cac69 | 932 | hs_ep->compl_desc = 0; |
540ccba0 VA |
933 | depctl = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index); |
934 | dma_reg = hs_ep->dir_in ? DIEPDMA(index) : DOEPDMA(index); | |
935 | ||
936 | /* write descriptor chain address to control register */ | |
f25c42b8 | 937 | dwc2_writel(hsotg, hs_ep->desc_list_dma, dma_reg); |
540ccba0 | 938 | |
f25c42b8 | 939 | ctrl = dwc2_readl(hsotg, depctl); |
540ccba0 | 940 | ctrl |= DXEPCTL_EPENA | DXEPCTL_CNAK; |
f25c42b8 | 941 | dwc2_writel(hsotg, ctrl, depctl); |
540ccba0 VA |
942 | } |
943 | ||
5b7d70c6 | 944 | /** |
1f91b4cc | 945 | * dwc2_hsotg_start_req - start a USB request from an endpoint's queue |
5b7d70c6 BD |
946 | * @hsotg: The controller state. |
947 | * @hs_ep: The endpoint to process a request for | |
948 | * @hs_req: The request to start. | |
949 | * @continuing: True if we are doing more for the current request. | |
950 | * | |
951 | * Start the given request running by setting the endpoint registers | |
952 | * appropriately, and writing any data to the FIFOs. | |
953 | */ | |
1f91b4cc | 954 | static void dwc2_hsotg_start_req(struct dwc2_hsotg *hsotg, |
9da51974 | 955 | struct dwc2_hsotg_ep *hs_ep, |
1f91b4cc | 956 | struct dwc2_hsotg_req *hs_req, |
5b7d70c6 BD |
957 | bool continuing) |
958 | { | |
959 | struct usb_request *ureq = &hs_req->req; | |
960 | int index = hs_ep->index; | |
961 | int dir_in = hs_ep->dir_in; | |
962 | u32 epctrl_reg; | |
963 | u32 epsize_reg; | |
964 | u32 epsize; | |
965 | u32 ctrl; | |
9da51974 JY |
966 | unsigned int length; |
967 | unsigned int packets; | |
968 | unsigned int maxreq; | |
aa3e8bc8 | 969 | unsigned int dma_reg; |
5b7d70c6 BD |
970 | |
971 | if (index != 0) { | |
972 | if (hs_ep->req && !continuing) { | |
973 | dev_err(hsotg->dev, "%s: active request\n", __func__); | |
974 | WARN_ON(1); | |
975 | return; | |
976 | } else if (hs_ep->req != hs_req && continuing) { | |
977 | dev_err(hsotg->dev, | |
978 | "%s: continue different req\n", __func__); | |
979 | WARN_ON(1); | |
980 | return; | |
981 | } | |
982 | } | |
983 | ||
aa3e8bc8 | 984 | dma_reg = dir_in ? DIEPDMA(index) : DOEPDMA(index); |
94cb8fd6 LM |
985 | epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index); |
986 | epsize_reg = dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index); | |
5b7d70c6 BD |
987 | |
988 | dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n", | |
f25c42b8 | 989 | __func__, dwc2_readl(hsotg, epctrl_reg), index, |
5b7d70c6 BD |
990 | hs_ep->dir_in ? "in" : "out"); |
991 | ||
9c39ddc6 | 992 | /* If endpoint is stalled, we will restart request later */ |
f25c42b8 | 993 | ctrl = dwc2_readl(hsotg, epctrl_reg); |
9c39ddc6 | 994 | |
b2d4c54e | 995 | if (index && ctrl & DXEPCTL_STALL) { |
9c39ddc6 AT |
996 | dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index); |
997 | return; | |
998 | } | |
999 | ||
5b7d70c6 | 1000 | length = ureq->length - ureq->actual; |
71225bee LM |
1001 | dev_dbg(hsotg->dev, "ureq->length:%d ureq->actual:%d\n", |
1002 | ureq->length, ureq->actual); | |
5b7d70c6 | 1003 | |
cf77b5fb VA |
1004 | if (!using_desc_dma(hsotg)) |
1005 | maxreq = get_ep_limit(hs_ep); | |
1006 | else | |
1007 | maxreq = dwc2_gadget_get_chain_limit(hs_ep); | |
1008 | ||
5b7d70c6 BD |
1009 | if (length > maxreq) { |
1010 | int round = maxreq % hs_ep->ep.maxpacket; | |
1011 | ||
1012 | dev_dbg(hsotg->dev, "%s: length %d, max-req %d, r %d\n", | |
1013 | __func__, length, maxreq, round); | |
1014 | ||
1015 | /* round down to multiple of packets */ | |
1016 | if (round) | |
1017 | maxreq -= round; | |
1018 | ||
1019 | length = maxreq; | |
1020 | } | |
1021 | ||
1022 | if (length) | |
1023 | packets = DIV_ROUND_UP(length, hs_ep->ep.maxpacket); | |
1024 | else | |
1025 | packets = 1; /* send one packet if length is zero. */ | |
1026 | ||
4fca54aa RB |
1027 | if (hs_ep->isochronous && length > (hs_ep->mc * hs_ep->ep.maxpacket)) { |
1028 | dev_err(hsotg->dev, "req length > maxpacket*mc\n"); | |
1029 | return; | |
1030 | } | |
1031 | ||
5b7d70c6 | 1032 | if (dir_in && index != 0) |
4fca54aa | 1033 | if (hs_ep->isochronous) |
47a1685f | 1034 | epsize = DXEPTSIZ_MC(packets); |
4fca54aa | 1035 | else |
47a1685f | 1036 | epsize = DXEPTSIZ_MC(1); |
5b7d70c6 BD |
1037 | else |
1038 | epsize = 0; | |
1039 | ||
f71b5e25 MYK |
1040 | /* |
1041 | * zero length packet should be programmed on its own and should not | |
1042 | * be counted in DIEPTSIZ.PktCnt with other packets. | |
1043 | */ | |
1044 | if (dir_in && ureq->zero && !continuing) { | |
1045 | /* Test if zlp is actually required. */ | |
1046 | if ((ureq->length >= hs_ep->ep.maxpacket) && | |
9da51974 | 1047 | !(ureq->length % hs_ep->ep.maxpacket)) |
8a20fa45 | 1048 | hs_ep->send_zlp = 1; |
5b7d70c6 BD |
1049 | } |
1050 | ||
47a1685f DN |
1051 | epsize |= DXEPTSIZ_PKTCNT(packets); |
1052 | epsize |= DXEPTSIZ_XFERSIZE(length); | |
5b7d70c6 BD |
1053 | |
1054 | dev_dbg(hsotg->dev, "%s: %d@%d/%d, 0x%08x => 0x%08x\n", | |
1055 | __func__, packets, length, ureq->length, epsize, epsize_reg); | |
1056 | ||
1057 | /* store the request as the current one we're doing */ | |
1058 | hs_ep->req = hs_req; | |
1059 | ||
aa3e8bc8 VA |
1060 | if (using_desc_dma(hsotg)) { |
1061 | u32 offset = 0; | |
1062 | u32 mps = hs_ep->ep.maxpacket; | |
1063 | ||
1064 | /* Adjust length: EP0 - MPS, other OUT EPs - multiple of MPS */ | |
1065 | if (!dir_in) { | |
1066 | if (!index) | |
1067 | length = mps; | |
1068 | else if (length % mps) | |
1069 | length += (mps - (length % mps)); | |
1070 | } | |
5b7d70c6 | 1071 | |
8b9bc460 | 1072 | /* |
aa3e8bc8 VA |
1073 | * If more data to send, adjust DMA for EP0 out data stage. |
1074 | * ureq->dma stays unchanged, hence increment it by already | |
1075 | * passed passed data count before starting new transaction. | |
8b9bc460 | 1076 | */ |
aa3e8bc8 VA |
1077 | if (!index && hsotg->ep0_state == DWC2_EP0_DATA_OUT && |
1078 | continuing) | |
1079 | offset = ureq->actual; | |
1080 | ||
1081 | /* Fill DDMA chain entries */ | |
1082 | dwc2_gadget_config_nonisoc_xfer_ddma(hs_ep, ureq->dma + offset, | |
1083 | length); | |
1084 | ||
1085 | /* write descriptor chain address to control register */ | |
f25c42b8 | 1086 | dwc2_writel(hsotg, hs_ep->desc_list_dma, dma_reg); |
5b7d70c6 | 1087 | |
aa3e8bc8 VA |
1088 | dev_dbg(hsotg->dev, "%s: %08x pad => 0x%08x\n", |
1089 | __func__, (u32)hs_ep->desc_list_dma, dma_reg); | |
1090 | } else { | |
1091 | /* write size / packets */ | |
f25c42b8 | 1092 | dwc2_writel(hsotg, epsize, epsize_reg); |
aa3e8bc8 | 1093 | |
729e6574 | 1094 | if (using_dma(hsotg) && !continuing && (length != 0)) { |
aa3e8bc8 VA |
1095 | /* |
1096 | * write DMA address to control register, buffer | |
1097 | * already synced by dwc2_hsotg_ep_queue(). | |
1098 | */ | |
5b7d70c6 | 1099 | |
f25c42b8 | 1100 | dwc2_writel(hsotg, ureq->dma, dma_reg); |
aa3e8bc8 VA |
1101 | |
1102 | dev_dbg(hsotg->dev, "%s: %pad => 0x%08x\n", | |
1103 | __func__, &ureq->dma, dma_reg); | |
1104 | } | |
5b7d70c6 BD |
1105 | } |
1106 | ||
837e9f00 VM |
1107 | if (hs_ep->isochronous && hs_ep->interval == 1) { |
1108 | hs_ep->target_frame = dwc2_hsotg_read_frameno(hsotg); | |
1109 | dwc2_gadget_incr_frame_num(hs_ep); | |
1110 | ||
1111 | if (hs_ep->target_frame & 0x1) | |
1112 | ctrl |= DXEPCTL_SETODDFR; | |
1113 | else | |
1114 | ctrl |= DXEPCTL_SETEVENFR; | |
1115 | } | |
1116 | ||
47a1685f | 1117 | ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */ |
71225bee | 1118 | |
fe0b94ab | 1119 | dev_dbg(hsotg->dev, "ep0 state:%d\n", hsotg->ep0_state); |
71225bee LM |
1120 | |
1121 | /* For Setup request do not clear NAK */ | |
fe0b94ab | 1122 | if (!(index == 0 && hsotg->ep0_state == DWC2_EP0_SETUP)) |
47a1685f | 1123 | ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */ |
71225bee | 1124 | |
5b7d70c6 | 1125 | dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl); |
f25c42b8 | 1126 | dwc2_writel(hsotg, ctrl, epctrl_reg); |
5b7d70c6 | 1127 | |
8b9bc460 LM |
1128 | /* |
1129 | * set these, it seems that DMA support increments past the end | |
5b7d70c6 | 1130 | * of the packet buffer so we need to calculate the length from |
8b9bc460 LM |
1131 | * this information. |
1132 | */ | |
5b7d70c6 BD |
1133 | hs_ep->size_loaded = length; |
1134 | hs_ep->last_load = ureq->actual; | |
1135 | ||
1136 | if (dir_in && !using_dma(hsotg)) { | |
1137 | /* set these anyway, we may need them for non-periodic in */ | |
1138 | hs_ep->fifo_load = 0; | |
1139 | ||
1f91b4cc | 1140 | dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req); |
5b7d70c6 BD |
1141 | } |
1142 | ||
8b9bc460 LM |
1143 | /* |
1144 | * Note, trying to clear the NAK here causes problems with transmit | |
1145 | * on the S3C6400 ending up with the TXFIFO becoming full. | |
1146 | */ | |
5b7d70c6 BD |
1147 | |
1148 | /* check ep is enabled */ | |
f25c42b8 | 1149 | if (!(dwc2_readl(hsotg, epctrl_reg) & DXEPCTL_EPENA)) |
1a0ed863 | 1150 | dev_dbg(hsotg->dev, |
9da51974 | 1151 | "ep%d: failed to become enabled (DXEPCTL=0x%08x)?\n", |
f25c42b8 | 1152 | index, dwc2_readl(hsotg, epctrl_reg)); |
5b7d70c6 | 1153 | |
47a1685f | 1154 | dev_dbg(hsotg->dev, "%s: DXEPCTL=0x%08x\n", |
f25c42b8 | 1155 | __func__, dwc2_readl(hsotg, epctrl_reg)); |
afcf4169 RB |
1156 | |
1157 | /* enable ep interrupts */ | |
1f91b4cc | 1158 | dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 1); |
5b7d70c6 BD |
1159 | } |
1160 | ||
1161 | /** | |
1f91b4cc | 1162 | * dwc2_hsotg_map_dma - map the DMA memory being used for the request |
5b7d70c6 BD |
1163 | * @hsotg: The device state. |
1164 | * @hs_ep: The endpoint the request is on. | |
1165 | * @req: The request being processed. | |
1166 | * | |
1167 | * We've been asked to queue a request, so ensure that the memory buffer | |
1168 | * is correctly setup for DMA. If we've been passed an extant DMA address | |
1169 | * then ensure the buffer has been synced to memory. If our buffer has no | |
1170 | * DMA memory, then we map the memory and mark our request to allow us to | |
1171 | * cleanup on completion. | |
8b9bc460 | 1172 | */ |
1f91b4cc | 1173 | static int dwc2_hsotg_map_dma(struct dwc2_hsotg *hsotg, |
9da51974 | 1174 | struct dwc2_hsotg_ep *hs_ep, |
5b7d70c6 BD |
1175 | struct usb_request *req) |
1176 | { | |
e58ebcd1 | 1177 | int ret; |
5b7d70c6 | 1178 | |
e58ebcd1 FB |
1179 | ret = usb_gadget_map_request(&hsotg->gadget, req, hs_ep->dir_in); |
1180 | if (ret) | |
1181 | goto dma_error; | |
5b7d70c6 BD |
1182 | |
1183 | return 0; | |
1184 | ||
1185 | dma_error: | |
1186 | dev_err(hsotg->dev, "%s: failed to map buffer %p, %d bytes\n", | |
1187 | __func__, req->buf, req->length); | |
1188 | ||
1189 | return -EIO; | |
1190 | } | |
1191 | ||
1f91b4cc | 1192 | static int dwc2_hsotg_handle_unaligned_buf_start(struct dwc2_hsotg *hsotg, |
b98866c2 JY |
1193 | struct dwc2_hsotg_ep *hs_ep, |
1194 | struct dwc2_hsotg_req *hs_req) | |
7d24c1b5 MYK |
1195 | { |
1196 | void *req_buf = hs_req->req.buf; | |
1197 | ||
1198 | /* If dma is not being used or buffer is aligned */ | |
1199 | if (!using_dma(hsotg) || !((long)req_buf & 3)) | |
1200 | return 0; | |
1201 | ||
1202 | WARN_ON(hs_req->saved_req_buf); | |
1203 | ||
1204 | dev_dbg(hsotg->dev, "%s: %s: buf=%p length=%d\n", __func__, | |
9da51974 | 1205 | hs_ep->ep.name, req_buf, hs_req->req.length); |
7d24c1b5 MYK |
1206 | |
1207 | hs_req->req.buf = kmalloc(hs_req->req.length, GFP_ATOMIC); | |
1208 | if (!hs_req->req.buf) { | |
1209 | hs_req->req.buf = req_buf; | |
1210 | dev_err(hsotg->dev, | |
1211 | "%s: unable to allocate memory for bounce buffer\n", | |
1212 | __func__); | |
1213 | return -ENOMEM; | |
1214 | } | |
1215 | ||
1216 | /* Save actual buffer */ | |
1217 | hs_req->saved_req_buf = req_buf; | |
1218 | ||
1219 | if (hs_ep->dir_in) | |
1220 | memcpy(hs_req->req.buf, req_buf, hs_req->req.length); | |
1221 | return 0; | |
1222 | } | |
1223 | ||
b98866c2 JY |
1224 | static void |
1225 | dwc2_hsotg_handle_unaligned_buf_complete(struct dwc2_hsotg *hsotg, | |
1226 | struct dwc2_hsotg_ep *hs_ep, | |
1227 | struct dwc2_hsotg_req *hs_req) | |
7d24c1b5 MYK |
1228 | { |
1229 | /* If dma is not being used or buffer was aligned */ | |
1230 | if (!using_dma(hsotg) || !hs_req->saved_req_buf) | |
1231 | return; | |
1232 | ||
1233 | dev_dbg(hsotg->dev, "%s: %s: status=%d actual-length=%d\n", __func__, | |
1234 | hs_ep->ep.name, hs_req->req.status, hs_req->req.actual); | |
1235 | ||
1236 | /* Copy data from bounce buffer on successful out transfer */ | |
1237 | if (!hs_ep->dir_in && !hs_req->req.status) | |
1238 | memcpy(hs_req->saved_req_buf, hs_req->req.buf, | |
9da51974 | 1239 | hs_req->req.actual); |
7d24c1b5 MYK |
1240 | |
1241 | /* Free bounce buffer */ | |
1242 | kfree(hs_req->req.buf); | |
1243 | ||
1244 | hs_req->req.buf = hs_req->saved_req_buf; | |
1245 | hs_req->saved_req_buf = NULL; | |
1246 | } | |
1247 | ||
381fc8f8 VM |
1248 | /** |
1249 | * dwc2_gadget_target_frame_elapsed - Checks target frame | |
1250 | * @hs_ep: The driver endpoint to check | |
1251 | * | |
1252 | * Returns 1 if targeted frame elapsed. If returned 1 then we need to drop | |
1253 | * corresponding transfer. | |
1254 | */ | |
1255 | static bool dwc2_gadget_target_frame_elapsed(struct dwc2_hsotg_ep *hs_ep) | |
1256 | { | |
1257 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
1258 | u32 target_frame = hs_ep->target_frame; | |
c7c24e7a | 1259 | u32 current_frame = hsotg->frame_number; |
381fc8f8 VM |
1260 | bool frame_overrun = hs_ep->frame_overrun; |
1261 | ||
1262 | if (!frame_overrun && current_frame >= target_frame) | |
1263 | return true; | |
1264 | ||
1265 | if (frame_overrun && current_frame >= target_frame && | |
1266 | ((current_frame - target_frame) < DSTS_SOFFN_LIMIT / 2)) | |
1267 | return true; | |
1268 | ||
1269 | return false; | |
1270 | } | |
1271 | ||
e02f9aa6 VA |
1272 | /* |
1273 | * dwc2_gadget_set_ep0_desc_chain - Set EP's desc chain pointers | |
1274 | * @hsotg: The driver state | |
1275 | * @hs_ep: the ep descriptor chain is for | |
1276 | * | |
1277 | * Called to update EP0 structure's pointers depend on stage of | |
1278 | * control transfer. | |
1279 | */ | |
1280 | static int dwc2_gadget_set_ep0_desc_chain(struct dwc2_hsotg *hsotg, | |
1281 | struct dwc2_hsotg_ep *hs_ep) | |
1282 | { | |
1283 | switch (hsotg->ep0_state) { | |
1284 | case DWC2_EP0_SETUP: | |
1285 | case DWC2_EP0_STATUS_OUT: | |
1286 | hs_ep->desc_list = hsotg->setup_desc[0]; | |
1287 | hs_ep->desc_list_dma = hsotg->setup_desc_dma[0]; | |
1288 | break; | |
1289 | case DWC2_EP0_DATA_IN: | |
1290 | case DWC2_EP0_STATUS_IN: | |
1291 | hs_ep->desc_list = hsotg->ctrl_in_desc; | |
1292 | hs_ep->desc_list_dma = hsotg->ctrl_in_desc_dma; | |
1293 | break; | |
1294 | case DWC2_EP0_DATA_OUT: | |
1295 | hs_ep->desc_list = hsotg->ctrl_out_desc; | |
1296 | hs_ep->desc_list_dma = hsotg->ctrl_out_desc_dma; | |
1297 | break; | |
1298 | default: | |
1299 | dev_err(hsotg->dev, "invalid EP 0 state in queue %d\n", | |
1300 | hsotg->ep0_state); | |
1301 | return -EINVAL; | |
1302 | } | |
1303 | ||
1304 | return 0; | |
1305 | } | |
1306 | ||
1f91b4cc | 1307 | static int dwc2_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req, |
9da51974 | 1308 | gfp_t gfp_flags) |
5b7d70c6 | 1309 | { |
1f91b4cc FB |
1310 | struct dwc2_hsotg_req *hs_req = our_req(req); |
1311 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); | |
941fcce4 | 1312 | struct dwc2_hsotg *hs = hs_ep->parent; |
5b7d70c6 | 1313 | bool first; |
7d24c1b5 | 1314 | int ret; |
729cac69 MH |
1315 | u32 maxsize = 0; |
1316 | u32 mask = 0; | |
1317 | ||
5b7d70c6 BD |
1318 | |
1319 | dev_dbg(hs->dev, "%s: req %p: %d@%p, noi=%d, zero=%d, snok=%d\n", | |
1320 | ep->name, req, req->length, req->buf, req->no_interrupt, | |
1321 | req->zero, req->short_not_ok); | |
1322 | ||
7ababa92 | 1323 | /* Prevent new request submission when controller is suspended */ |
88b02f2c GT |
1324 | if (hs->lx_state != DWC2_L0) { |
1325 | dev_dbg(hs->dev, "%s: submit request only in active state\n", | |
9da51974 | 1326 | __func__); |
7ababa92 GH |
1327 | return -EAGAIN; |
1328 | } | |
1329 | ||
5b7d70c6 BD |
1330 | /* initialise status of the request */ |
1331 | INIT_LIST_HEAD(&hs_req->queue); | |
1332 | req->actual = 0; | |
1333 | req->status = -EINPROGRESS; | |
1334 | ||
729cac69 MH |
1335 | /* In DDMA mode for ISOC's don't queue request if length greater |
1336 | * than descriptor limits. | |
1337 | */ | |
1338 | if (using_desc_dma(hs) && hs_ep->isochronous) { | |
1339 | maxsize = dwc2_gadget_get_desc_params(hs_ep, &mask); | |
1340 | if (hs_ep->dir_in && req->length > maxsize) { | |
1341 | dev_err(hs->dev, "wrong length %d (maxsize=%d)\n", | |
1342 | req->length, maxsize); | |
1343 | return -EINVAL; | |
1344 | } | |
1345 | ||
1346 | if (!hs_ep->dir_in && req->length > hs_ep->ep.maxpacket) { | |
1347 | dev_err(hs->dev, "ISOC OUT: wrong length %d (mps=%d)\n", | |
1348 | req->length, hs_ep->ep.maxpacket); | |
1349 | return -EINVAL; | |
1350 | } | |
1351 | } | |
1352 | ||
1f91b4cc | 1353 | ret = dwc2_hsotg_handle_unaligned_buf_start(hs, hs_ep, hs_req); |
7d24c1b5 MYK |
1354 | if (ret) |
1355 | return ret; | |
1356 | ||
5b7d70c6 BD |
1357 | /* if we're using DMA, sync the buffers as necessary */ |
1358 | if (using_dma(hs)) { | |
1f91b4cc | 1359 | ret = dwc2_hsotg_map_dma(hs, hs_ep, req); |
5b7d70c6 BD |
1360 | if (ret) |
1361 | return ret; | |
1362 | } | |
e02f9aa6 VA |
1363 | /* If using descriptor DMA configure EP0 descriptor chain pointers */ |
1364 | if (using_desc_dma(hs) && !hs_ep->index) { | |
1365 | ret = dwc2_gadget_set_ep0_desc_chain(hs, hs_ep); | |
1366 | if (ret) | |
1367 | return ret; | |
1368 | } | |
5b7d70c6 | 1369 | |
5b7d70c6 BD |
1370 | first = list_empty(&hs_ep->queue); |
1371 | list_add_tail(&hs_req->queue, &hs_ep->queue); | |
1372 | ||
540ccba0 VA |
1373 | /* |
1374 | * Handle DDMA isochronous transfers separately - just add new entry | |
729cac69 | 1375 | * to the descriptor chain. |
540ccba0 VA |
1376 | * Transfer will be started once SW gets either one of NAK or |
1377 | * OutTknEpDis interrupts. | |
1378 | */ | |
729cac69 MH |
1379 | if (using_desc_dma(hs) && hs_ep->isochronous) { |
1380 | if (hs_ep->target_frame != TARGET_FRAME_INITIAL) { | |
1381 | dwc2_gadget_fill_isoc_desc(hs_ep, hs_req->req.dma, | |
1382 | hs_req->req.length); | |
1383 | } | |
540ccba0 VA |
1384 | return 0; |
1385 | } | |
1386 | ||
837e9f00 VM |
1387 | if (first) { |
1388 | if (!hs_ep->isochronous) { | |
1389 | dwc2_hsotg_start_req(hs, hs_ep, hs_req, false); | |
1390 | return 0; | |
1391 | } | |
1392 | ||
c7c24e7a AP |
1393 | /* Update current frame number value. */ |
1394 | hs->frame_number = dwc2_hsotg_read_frameno(hs); | |
1395 | while (dwc2_gadget_target_frame_elapsed(hs_ep)) { | |
837e9f00 | 1396 | dwc2_gadget_incr_frame_num(hs_ep); |
c7c24e7a AP |
1397 | /* Update current frame number value once more as it |
1398 | * changes here. | |
1399 | */ | |
1400 | hs->frame_number = dwc2_hsotg_read_frameno(hs); | |
1401 | } | |
5b7d70c6 | 1402 | |
837e9f00 VM |
1403 | if (hs_ep->target_frame != TARGET_FRAME_INITIAL) |
1404 | dwc2_hsotg_start_req(hs, hs_ep, hs_req, false); | |
1405 | } | |
5b7d70c6 BD |
1406 | return 0; |
1407 | } | |
1408 | ||
1f91b4cc | 1409 | static int dwc2_hsotg_ep_queue_lock(struct usb_ep *ep, struct usb_request *req, |
9da51974 | 1410 | gfp_t gfp_flags) |
5ad1d316 | 1411 | { |
1f91b4cc | 1412 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 1413 | struct dwc2_hsotg *hs = hs_ep->parent; |
5ad1d316 LM |
1414 | unsigned long flags = 0; |
1415 | int ret = 0; | |
1416 | ||
1417 | spin_lock_irqsave(&hs->lock, flags); | |
1f91b4cc | 1418 | ret = dwc2_hsotg_ep_queue(ep, req, gfp_flags); |
5ad1d316 LM |
1419 | spin_unlock_irqrestore(&hs->lock, flags); |
1420 | ||
1421 | return ret; | |
1422 | } | |
1423 | ||
1f91b4cc | 1424 | static void dwc2_hsotg_ep_free_request(struct usb_ep *ep, |
9da51974 | 1425 | struct usb_request *req) |
5b7d70c6 | 1426 | { |
1f91b4cc | 1427 | struct dwc2_hsotg_req *hs_req = our_req(req); |
5b7d70c6 BD |
1428 | |
1429 | kfree(hs_req); | |
1430 | } | |
1431 | ||
1432 | /** | |
1f91b4cc | 1433 | * dwc2_hsotg_complete_oursetup - setup completion callback |
5b7d70c6 BD |
1434 | * @ep: The endpoint the request was on. |
1435 | * @req: The request completed. | |
1436 | * | |
1437 | * Called on completion of any requests the driver itself | |
1438 | * submitted that need cleaning up. | |
1439 | */ | |
1f91b4cc | 1440 | static void dwc2_hsotg_complete_oursetup(struct usb_ep *ep, |
9da51974 | 1441 | struct usb_request *req) |
5b7d70c6 | 1442 | { |
1f91b4cc | 1443 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 1444 | struct dwc2_hsotg *hsotg = hs_ep->parent; |
5b7d70c6 BD |
1445 | |
1446 | dev_dbg(hsotg->dev, "%s: ep %p, req %p\n", __func__, ep, req); | |
1447 | ||
1f91b4cc | 1448 | dwc2_hsotg_ep_free_request(ep, req); |
5b7d70c6 BD |
1449 | } |
1450 | ||
1451 | /** | |
1452 | * ep_from_windex - convert control wIndex value to endpoint | |
1453 | * @hsotg: The driver state. | |
1454 | * @windex: The control request wIndex field (in host order). | |
1455 | * | |
1456 | * Convert the given wIndex into a pointer to an driver endpoint | |
1457 | * structure, or return NULL if it is not a valid endpoint. | |
8b9bc460 | 1458 | */ |
1f91b4cc | 1459 | static struct dwc2_hsotg_ep *ep_from_windex(struct dwc2_hsotg *hsotg, |
9da51974 | 1460 | u32 windex) |
5b7d70c6 | 1461 | { |
1f91b4cc | 1462 | struct dwc2_hsotg_ep *ep; |
5b7d70c6 BD |
1463 | int dir = (windex & USB_DIR_IN) ? 1 : 0; |
1464 | int idx = windex & 0x7F; | |
1465 | ||
1466 | if (windex >= 0x100) | |
1467 | return NULL; | |
1468 | ||
b3f489b2 | 1469 | if (idx > hsotg->num_of_eps) |
5b7d70c6 BD |
1470 | return NULL; |
1471 | ||
c6f5c050 MYK |
1472 | ep = index_to_ep(hsotg, idx, dir); |
1473 | ||
5b7d70c6 BD |
1474 | if (idx && ep->dir_in != dir) |
1475 | return NULL; | |
1476 | ||
1477 | return ep; | |
1478 | } | |
1479 | ||
9e14d0a5 | 1480 | /** |
1f91b4cc | 1481 | * dwc2_hsotg_set_test_mode - Enable usb Test Modes |
9e14d0a5 GH |
1482 | * @hsotg: The driver state. |
1483 | * @testmode: requested usb test mode | |
1484 | * Enable usb Test Mode requested by the Host. | |
1485 | */ | |
1f91b4cc | 1486 | int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode) |
9e14d0a5 | 1487 | { |
f25c42b8 | 1488 | int dctl = dwc2_readl(hsotg, DCTL); |
9e14d0a5 GH |
1489 | |
1490 | dctl &= ~DCTL_TSTCTL_MASK; | |
1491 | switch (testmode) { | |
1492 | case TEST_J: | |
1493 | case TEST_K: | |
1494 | case TEST_SE0_NAK: | |
1495 | case TEST_PACKET: | |
1496 | case TEST_FORCE_EN: | |
1497 | dctl |= testmode << DCTL_TSTCTL_SHIFT; | |
1498 | break; | |
1499 | default: | |
1500 | return -EINVAL; | |
1501 | } | |
f25c42b8 | 1502 | dwc2_writel(hsotg, dctl, DCTL); |
9e14d0a5 GH |
1503 | return 0; |
1504 | } | |
1505 | ||
5b7d70c6 | 1506 | /** |
1f91b4cc | 1507 | * dwc2_hsotg_send_reply - send reply to control request |
5b7d70c6 BD |
1508 | * @hsotg: The device state |
1509 | * @ep: Endpoint 0 | |
1510 | * @buff: Buffer for request | |
1511 | * @length: Length of reply. | |
1512 | * | |
1513 | * Create a request and queue it on the given endpoint. This is useful as | |
1514 | * an internal method of sending replies to certain control requests, etc. | |
1515 | */ | |
1f91b4cc | 1516 | static int dwc2_hsotg_send_reply(struct dwc2_hsotg *hsotg, |
9da51974 | 1517 | struct dwc2_hsotg_ep *ep, |
5b7d70c6 BD |
1518 | void *buff, |
1519 | int length) | |
1520 | { | |
1521 | struct usb_request *req; | |
1522 | int ret; | |
1523 | ||
1524 | dev_dbg(hsotg->dev, "%s: buff %p, len %d\n", __func__, buff, length); | |
1525 | ||
1f91b4cc | 1526 | req = dwc2_hsotg_ep_alloc_request(&ep->ep, GFP_ATOMIC); |
5b7d70c6 BD |
1527 | hsotg->ep0_reply = req; |
1528 | if (!req) { | |
1529 | dev_warn(hsotg->dev, "%s: cannot alloc req\n", __func__); | |
1530 | return -ENOMEM; | |
1531 | } | |
1532 | ||
1533 | req->buf = hsotg->ep0_buff; | |
1534 | req->length = length; | |
f71b5e25 MYK |
1535 | /* |
1536 | * zero flag is for sending zlp in DATA IN stage. It has no impact on | |
1537 | * STATUS stage. | |
1538 | */ | |
1539 | req->zero = 0; | |
1f91b4cc | 1540 | req->complete = dwc2_hsotg_complete_oursetup; |
5b7d70c6 BD |
1541 | |
1542 | if (length) | |
1543 | memcpy(req->buf, buff, length); | |
5b7d70c6 | 1544 | |
1f91b4cc | 1545 | ret = dwc2_hsotg_ep_queue(&ep->ep, req, GFP_ATOMIC); |
5b7d70c6 BD |
1546 | if (ret) { |
1547 | dev_warn(hsotg->dev, "%s: cannot queue req\n", __func__); | |
1548 | return ret; | |
1549 | } | |
1550 | ||
1551 | return 0; | |
1552 | } | |
1553 | ||
1554 | /** | |
1f91b4cc | 1555 | * dwc2_hsotg_process_req_status - process request GET_STATUS |
5b7d70c6 BD |
1556 | * @hsotg: The device state |
1557 | * @ctrl: USB control request | |
1558 | */ | |
1f91b4cc | 1559 | static int dwc2_hsotg_process_req_status(struct dwc2_hsotg *hsotg, |
9da51974 | 1560 | struct usb_ctrlrequest *ctrl) |
5b7d70c6 | 1561 | { |
1f91b4cc FB |
1562 | struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0]; |
1563 | struct dwc2_hsotg_ep *ep; | |
5b7d70c6 BD |
1564 | __le16 reply; |
1565 | int ret; | |
1566 | ||
1567 | dev_dbg(hsotg->dev, "%s: USB_REQ_GET_STATUS\n", __func__); | |
1568 | ||
1569 | if (!ep0->dir_in) { | |
1570 | dev_warn(hsotg->dev, "%s: direction out?\n", __func__); | |
1571 | return -EINVAL; | |
1572 | } | |
1573 | ||
1574 | switch (ctrl->bRequestType & USB_RECIP_MASK) { | |
1575 | case USB_RECIP_DEVICE: | |
38beaec6 JY |
1576 | /* |
1577 | * bit 0 => self powered | |
1578 | * bit 1 => remote wakeup | |
1579 | */ | |
1580 | reply = cpu_to_le16(0); | |
5b7d70c6 BD |
1581 | break; |
1582 | ||
1583 | case USB_RECIP_INTERFACE: | |
1584 | /* currently, the data result should be zero */ | |
1585 | reply = cpu_to_le16(0); | |
1586 | break; | |
1587 | ||
1588 | case USB_RECIP_ENDPOINT: | |
1589 | ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex)); | |
1590 | if (!ep) | |
1591 | return -ENOENT; | |
1592 | ||
1593 | reply = cpu_to_le16(ep->halted ? 1 : 0); | |
1594 | break; | |
1595 | ||
1596 | default: | |
1597 | return 0; | |
1598 | } | |
1599 | ||
1600 | if (le16_to_cpu(ctrl->wLength) != 2) | |
1601 | return -EINVAL; | |
1602 | ||
1f91b4cc | 1603 | ret = dwc2_hsotg_send_reply(hsotg, ep0, &reply, 2); |
5b7d70c6 BD |
1604 | if (ret) { |
1605 | dev_err(hsotg->dev, "%s: failed to send reply\n", __func__); | |
1606 | return ret; | |
1607 | } | |
1608 | ||
1609 | return 1; | |
1610 | } | |
1611 | ||
51da43b5 | 1612 | static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now); |
5b7d70c6 | 1613 | |
9c39ddc6 AT |
1614 | /** |
1615 | * get_ep_head - return the first request on the endpoint | |
1616 | * @hs_ep: The controller endpoint to get | |
1617 | * | |
1618 | * Get the first request on the endpoint. | |
1619 | */ | |
1f91b4cc | 1620 | static struct dwc2_hsotg_req *get_ep_head(struct dwc2_hsotg_ep *hs_ep) |
9c39ddc6 | 1621 | { |
ffc4b406 MY |
1622 | return list_first_entry_or_null(&hs_ep->queue, struct dwc2_hsotg_req, |
1623 | queue); | |
9c39ddc6 AT |
1624 | } |
1625 | ||
41cc4cd2 VM |
1626 | /** |
1627 | * dwc2_gadget_start_next_request - Starts next request from ep queue | |
1628 | * @hs_ep: Endpoint structure | |
1629 | * | |
1630 | * If queue is empty and EP is ISOC-OUT - unmasks OUTTKNEPDIS which is masked | |
1631 | * in its handler. Hence we need to unmask it here to be able to do | |
1632 | * resynchronization. | |
1633 | */ | |
1634 | static void dwc2_gadget_start_next_request(struct dwc2_hsotg_ep *hs_ep) | |
1635 | { | |
1636 | u32 mask; | |
1637 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
1638 | int dir_in = hs_ep->dir_in; | |
1639 | struct dwc2_hsotg_req *hs_req; | |
1640 | u32 epmsk_reg = dir_in ? DIEPMSK : DOEPMSK; | |
1641 | ||
1642 | if (!list_empty(&hs_ep->queue)) { | |
1643 | hs_req = get_ep_head(hs_ep); | |
1644 | dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, false); | |
1645 | return; | |
1646 | } | |
1647 | if (!hs_ep->isochronous) | |
1648 | return; | |
1649 | ||
1650 | if (dir_in) { | |
1651 | dev_dbg(hsotg->dev, "%s: No more ISOC-IN requests\n", | |
1652 | __func__); | |
1653 | } else { | |
1654 | dev_dbg(hsotg->dev, "%s: No more ISOC-OUT requests\n", | |
1655 | __func__); | |
f25c42b8 | 1656 | mask = dwc2_readl(hsotg, epmsk_reg); |
41cc4cd2 | 1657 | mask |= DOEPMSK_OUTTKNEPDISMSK; |
f25c42b8 | 1658 | dwc2_writel(hsotg, mask, epmsk_reg); |
41cc4cd2 VM |
1659 | } |
1660 | } | |
1661 | ||
5b7d70c6 | 1662 | /** |
1f91b4cc | 1663 | * dwc2_hsotg_process_req_feature - process request {SET,CLEAR}_FEATURE |
5b7d70c6 BD |
1664 | * @hsotg: The device state |
1665 | * @ctrl: USB control request | |
1666 | */ | |
1f91b4cc | 1667 | static int dwc2_hsotg_process_req_feature(struct dwc2_hsotg *hsotg, |
9da51974 | 1668 | struct usb_ctrlrequest *ctrl) |
5b7d70c6 | 1669 | { |
1f91b4cc FB |
1670 | struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0]; |
1671 | struct dwc2_hsotg_req *hs_req; | |
5b7d70c6 | 1672 | bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE); |
1f91b4cc | 1673 | struct dwc2_hsotg_ep *ep; |
26ab3d0c | 1674 | int ret; |
bd9ef7bf | 1675 | bool halted; |
9e14d0a5 GH |
1676 | u32 recip; |
1677 | u32 wValue; | |
1678 | u32 wIndex; | |
5b7d70c6 BD |
1679 | |
1680 | dev_dbg(hsotg->dev, "%s: %s_FEATURE\n", | |
1681 | __func__, set ? "SET" : "CLEAR"); | |
1682 | ||
9e14d0a5 GH |
1683 | wValue = le16_to_cpu(ctrl->wValue); |
1684 | wIndex = le16_to_cpu(ctrl->wIndex); | |
1685 | recip = ctrl->bRequestType & USB_RECIP_MASK; | |
1686 | ||
1687 | switch (recip) { | |
1688 | case USB_RECIP_DEVICE: | |
1689 | switch (wValue) { | |
fa389a6d VM |
1690 | case USB_DEVICE_REMOTE_WAKEUP: |
1691 | hsotg->remote_wakeup_allowed = 1; | |
1692 | break; | |
1693 | ||
9e14d0a5 GH |
1694 | case USB_DEVICE_TEST_MODE: |
1695 | if ((wIndex & 0xff) != 0) | |
1696 | return -EINVAL; | |
1697 | if (!set) | |
1698 | return -EINVAL; | |
1699 | ||
1700 | hsotg->test_mode = wIndex >> 8; | |
1f91b4cc | 1701 | ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0); |
9e14d0a5 GH |
1702 | if (ret) { |
1703 | dev_err(hsotg->dev, | |
1704 | "%s: failed to send reply\n", __func__); | |
1705 | return ret; | |
1706 | } | |
1707 | break; | |
1708 | default: | |
1709 | return -ENOENT; | |
1710 | } | |
1711 | break; | |
1712 | ||
1713 | case USB_RECIP_ENDPOINT: | |
1714 | ep = ep_from_windex(hsotg, wIndex); | |
5b7d70c6 BD |
1715 | if (!ep) { |
1716 | dev_dbg(hsotg->dev, "%s: no endpoint for 0x%04x\n", | |
9e14d0a5 | 1717 | __func__, wIndex); |
5b7d70c6 BD |
1718 | return -ENOENT; |
1719 | } | |
1720 | ||
9e14d0a5 | 1721 | switch (wValue) { |
5b7d70c6 | 1722 | case USB_ENDPOINT_HALT: |
bd9ef7bf RB |
1723 | halted = ep->halted; |
1724 | ||
51da43b5 | 1725 | dwc2_hsotg_ep_sethalt(&ep->ep, set, true); |
26ab3d0c | 1726 | |
1f91b4cc | 1727 | ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0); |
26ab3d0c AT |
1728 | if (ret) { |
1729 | dev_err(hsotg->dev, | |
1730 | "%s: failed to send reply\n", __func__); | |
1731 | return ret; | |
1732 | } | |
9c39ddc6 | 1733 | |
bd9ef7bf RB |
1734 | /* |
1735 | * we have to complete all requests for ep if it was | |
1736 | * halted, and the halt was cleared by CLEAR_FEATURE | |
1737 | */ | |
1738 | ||
1739 | if (!set && halted) { | |
9c39ddc6 AT |
1740 | /* |
1741 | * If we have request in progress, | |
1742 | * then complete it | |
1743 | */ | |
1744 | if (ep->req) { | |
1745 | hs_req = ep->req; | |
1746 | ep->req = NULL; | |
1747 | list_del_init(&hs_req->queue); | |
c00dd4a6 GH |
1748 | if (hs_req->req.complete) { |
1749 | spin_unlock(&hsotg->lock); | |
1750 | usb_gadget_giveback_request( | |
1751 | &ep->ep, &hs_req->req); | |
1752 | spin_lock(&hsotg->lock); | |
1753 | } | |
9c39ddc6 AT |
1754 | } |
1755 | ||
1756 | /* If we have pending request, then start it */ | |
34c0887f | 1757 | if (!ep->req) |
41cc4cd2 | 1758 | dwc2_gadget_start_next_request(ep); |
9c39ddc6 AT |
1759 | } |
1760 | ||
5b7d70c6 BD |
1761 | break; |
1762 | ||
1763 | default: | |
1764 | return -ENOENT; | |
1765 | } | |
9e14d0a5 GH |
1766 | break; |
1767 | default: | |
1768 | return -ENOENT; | |
1769 | } | |
5b7d70c6 BD |
1770 | return 1; |
1771 | } | |
1772 | ||
1f91b4cc | 1773 | static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg); |
ab93e014 | 1774 | |
c9f721b2 | 1775 | /** |
1f91b4cc | 1776 | * dwc2_hsotg_stall_ep0 - stall ep0 |
c9f721b2 RB |
1777 | * @hsotg: The device state |
1778 | * | |
1779 | * Set stall for ep0 as response for setup request. | |
1780 | */ | |
1f91b4cc | 1781 | static void dwc2_hsotg_stall_ep0(struct dwc2_hsotg *hsotg) |
e9ebe7c3 | 1782 | { |
1f91b4cc | 1783 | struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0]; |
c9f721b2 RB |
1784 | u32 reg; |
1785 | u32 ctrl; | |
1786 | ||
1787 | dev_dbg(hsotg->dev, "ep0 stall (dir=%d)\n", ep0->dir_in); | |
1788 | reg = (ep0->dir_in) ? DIEPCTL0 : DOEPCTL0; | |
1789 | ||
1790 | /* | |
1791 | * DxEPCTL_Stall will be cleared by EP once it has | |
1792 | * taken effect, so no need to clear later. | |
1793 | */ | |
1794 | ||
f25c42b8 | 1795 | ctrl = dwc2_readl(hsotg, reg); |
47a1685f DN |
1796 | ctrl |= DXEPCTL_STALL; |
1797 | ctrl |= DXEPCTL_CNAK; | |
f25c42b8 | 1798 | dwc2_writel(hsotg, ctrl, reg); |
c9f721b2 RB |
1799 | |
1800 | dev_dbg(hsotg->dev, | |
47a1685f | 1801 | "written DXEPCTL=0x%08x to %08x (DXEPCTL=0x%08x)\n", |
f25c42b8 | 1802 | ctrl, reg, dwc2_readl(hsotg, reg)); |
c9f721b2 RB |
1803 | |
1804 | /* | |
1805 | * complete won't be called, so we enqueue | |
1806 | * setup request here | |
1807 | */ | |
1f91b4cc | 1808 | dwc2_hsotg_enqueue_setup(hsotg); |
c9f721b2 RB |
1809 | } |
1810 | ||
5b7d70c6 | 1811 | /** |
1f91b4cc | 1812 | * dwc2_hsotg_process_control - process a control request |
5b7d70c6 BD |
1813 | * @hsotg: The device state |
1814 | * @ctrl: The control request received | |
1815 | * | |
1816 | * The controller has received the SETUP phase of a control request, and | |
1817 | * needs to work out what to do next (and whether to pass it on to the | |
1818 | * gadget driver). | |
1819 | */ | |
1f91b4cc | 1820 | static void dwc2_hsotg_process_control(struct dwc2_hsotg *hsotg, |
9da51974 | 1821 | struct usb_ctrlrequest *ctrl) |
5b7d70c6 | 1822 | { |
1f91b4cc | 1823 | struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0]; |
5b7d70c6 BD |
1824 | int ret = 0; |
1825 | u32 dcfg; | |
1826 | ||
e525e743 MYK |
1827 | dev_dbg(hsotg->dev, |
1828 | "ctrl Type=%02x, Req=%02x, V=%04x, I=%04x, L=%04x\n", | |
1829 | ctrl->bRequestType, ctrl->bRequest, ctrl->wValue, | |
1830 | ctrl->wIndex, ctrl->wLength); | |
5b7d70c6 | 1831 | |
fe0b94ab MYK |
1832 | if (ctrl->wLength == 0) { |
1833 | ep0->dir_in = 1; | |
1834 | hsotg->ep0_state = DWC2_EP0_STATUS_IN; | |
1835 | } else if (ctrl->bRequestType & USB_DIR_IN) { | |
5b7d70c6 | 1836 | ep0->dir_in = 1; |
fe0b94ab MYK |
1837 | hsotg->ep0_state = DWC2_EP0_DATA_IN; |
1838 | } else { | |
1839 | ep0->dir_in = 0; | |
1840 | hsotg->ep0_state = DWC2_EP0_DATA_OUT; | |
1841 | } | |
5b7d70c6 BD |
1842 | |
1843 | if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) { | |
1844 | switch (ctrl->bRequest) { | |
1845 | case USB_REQ_SET_ADDRESS: | |
6d713c15 | 1846 | hsotg->connected = 1; |
f25c42b8 | 1847 | dcfg = dwc2_readl(hsotg, DCFG); |
47a1685f | 1848 | dcfg &= ~DCFG_DEVADDR_MASK; |
d5dbd3f7 PZ |
1849 | dcfg |= (le16_to_cpu(ctrl->wValue) << |
1850 | DCFG_DEVADDR_SHIFT) & DCFG_DEVADDR_MASK; | |
f25c42b8 | 1851 | dwc2_writel(hsotg, dcfg, DCFG); |
5b7d70c6 BD |
1852 | |
1853 | dev_info(hsotg->dev, "new address %d\n", ctrl->wValue); | |
1854 | ||
1f91b4cc | 1855 | ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0); |
5b7d70c6 BD |
1856 | return; |
1857 | ||
1858 | case USB_REQ_GET_STATUS: | |
1f91b4cc | 1859 | ret = dwc2_hsotg_process_req_status(hsotg, ctrl); |
5b7d70c6 BD |
1860 | break; |
1861 | ||
1862 | case USB_REQ_CLEAR_FEATURE: | |
1863 | case USB_REQ_SET_FEATURE: | |
1f91b4cc | 1864 | ret = dwc2_hsotg_process_req_feature(hsotg, ctrl); |
5b7d70c6 BD |
1865 | break; |
1866 | } | |
1867 | } | |
1868 | ||
1869 | /* as a fallback, try delivering it to the driver to deal with */ | |
1870 | ||
1871 | if (ret == 0 && hsotg->driver) { | |
93f599f2 | 1872 | spin_unlock(&hsotg->lock); |
5b7d70c6 | 1873 | ret = hsotg->driver->setup(&hsotg->gadget, ctrl); |
93f599f2 | 1874 | spin_lock(&hsotg->lock); |
5b7d70c6 BD |
1875 | if (ret < 0) |
1876 | dev_dbg(hsotg->dev, "driver->setup() ret %d\n", ret); | |
1877 | } | |
1878 | ||
8b9bc460 LM |
1879 | /* |
1880 | * the request is either unhandlable, or is not formatted correctly | |
5b7d70c6 BD |
1881 | * so respond with a STALL for the status stage to indicate failure. |
1882 | */ | |
1883 | ||
c9f721b2 | 1884 | if (ret < 0) |
1f91b4cc | 1885 | dwc2_hsotg_stall_ep0(hsotg); |
5b7d70c6 BD |
1886 | } |
1887 | ||
5b7d70c6 | 1888 | /** |
1f91b4cc | 1889 | * dwc2_hsotg_complete_setup - completion of a setup transfer |
5b7d70c6 BD |
1890 | * @ep: The endpoint the request was on. |
1891 | * @req: The request completed. | |
1892 | * | |
1893 | * Called on completion of any requests the driver itself submitted for | |
1894 | * EP0 setup packets | |
1895 | */ | |
1f91b4cc | 1896 | static void dwc2_hsotg_complete_setup(struct usb_ep *ep, |
9da51974 | 1897 | struct usb_request *req) |
5b7d70c6 | 1898 | { |
1f91b4cc | 1899 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 1900 | struct dwc2_hsotg *hsotg = hs_ep->parent; |
5b7d70c6 BD |
1901 | |
1902 | if (req->status < 0) { | |
1903 | dev_dbg(hsotg->dev, "%s: failed %d\n", __func__, req->status); | |
1904 | return; | |
1905 | } | |
1906 | ||
93f599f2 | 1907 | spin_lock(&hsotg->lock); |
5b7d70c6 | 1908 | if (req->actual == 0) |
1f91b4cc | 1909 | dwc2_hsotg_enqueue_setup(hsotg); |
5b7d70c6 | 1910 | else |
1f91b4cc | 1911 | dwc2_hsotg_process_control(hsotg, req->buf); |
93f599f2 | 1912 | spin_unlock(&hsotg->lock); |
5b7d70c6 BD |
1913 | } |
1914 | ||
1915 | /** | |
1f91b4cc | 1916 | * dwc2_hsotg_enqueue_setup - start a request for EP0 packets |
5b7d70c6 BD |
1917 | * @hsotg: The device state. |
1918 | * | |
1919 | * Enqueue a request on EP0 if necessary to received any SETUP packets | |
1920 | * received from the host. | |
1921 | */ | |
1f91b4cc | 1922 | static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg) |
5b7d70c6 BD |
1923 | { |
1924 | struct usb_request *req = hsotg->ctrl_req; | |
1f91b4cc | 1925 | struct dwc2_hsotg_req *hs_req = our_req(req); |
5b7d70c6 BD |
1926 | int ret; |
1927 | ||
1928 | dev_dbg(hsotg->dev, "%s: queueing setup request\n", __func__); | |
1929 | ||
1930 | req->zero = 0; | |
1931 | req->length = 8; | |
1932 | req->buf = hsotg->ctrl_buff; | |
1f91b4cc | 1933 | req->complete = dwc2_hsotg_complete_setup; |
5b7d70c6 BD |
1934 | |
1935 | if (!list_empty(&hs_req->queue)) { | |
1936 | dev_dbg(hsotg->dev, "%s already queued???\n", __func__); | |
1937 | return; | |
1938 | } | |
1939 | ||
c6f5c050 | 1940 | hsotg->eps_out[0]->dir_in = 0; |
8a20fa45 | 1941 | hsotg->eps_out[0]->send_zlp = 0; |
fe0b94ab | 1942 | hsotg->ep0_state = DWC2_EP0_SETUP; |
5b7d70c6 | 1943 | |
1f91b4cc | 1944 | ret = dwc2_hsotg_ep_queue(&hsotg->eps_out[0]->ep, req, GFP_ATOMIC); |
5b7d70c6 BD |
1945 | if (ret < 0) { |
1946 | dev_err(hsotg->dev, "%s: failed queue (%d)\n", __func__, ret); | |
8b9bc460 LM |
1947 | /* |
1948 | * Don't think there's much we can do other than watch the | |
1949 | * driver fail. | |
1950 | */ | |
5b7d70c6 BD |
1951 | } |
1952 | } | |
1953 | ||
1f91b4cc | 1954 | static void dwc2_hsotg_program_zlp(struct dwc2_hsotg *hsotg, |
9da51974 | 1955 | struct dwc2_hsotg_ep *hs_ep) |
fe0b94ab MYK |
1956 | { |
1957 | u32 ctrl; | |
1958 | u8 index = hs_ep->index; | |
1959 | u32 epctl_reg = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index); | |
1960 | u32 epsiz_reg = hs_ep->dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index); | |
1961 | ||
ccb34a91 MYK |
1962 | if (hs_ep->dir_in) |
1963 | dev_dbg(hsotg->dev, "Sending zero-length packet on ep%d\n", | |
e02f9aa6 | 1964 | index); |
ccb34a91 MYK |
1965 | else |
1966 | dev_dbg(hsotg->dev, "Receiving zero-length packet on ep%d\n", | |
e02f9aa6 VA |
1967 | index); |
1968 | if (using_desc_dma(hsotg)) { | |
1969 | /* Not specific buffer needed for ep0 ZLP */ | |
1970 | dma_addr_t dma = hs_ep->desc_list_dma; | |
fe0b94ab | 1971 | |
201ec568 MH |
1972 | if (!index) |
1973 | dwc2_gadget_set_ep0_desc_chain(hsotg, hs_ep); | |
1974 | ||
e02f9aa6 VA |
1975 | dwc2_gadget_config_nonisoc_xfer_ddma(hs_ep, dma, 0); |
1976 | } else { | |
f25c42b8 GS |
1977 | dwc2_writel(hsotg, DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) | |
1978 | DXEPTSIZ_XFERSIZE(0), | |
e02f9aa6 VA |
1979 | epsiz_reg); |
1980 | } | |
fe0b94ab | 1981 | |
f25c42b8 | 1982 | ctrl = dwc2_readl(hsotg, epctl_reg); |
fe0b94ab MYK |
1983 | ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */ |
1984 | ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */ | |
1985 | ctrl |= DXEPCTL_USBACTEP; | |
f25c42b8 | 1986 | dwc2_writel(hsotg, ctrl, epctl_reg); |
fe0b94ab MYK |
1987 | } |
1988 | ||
5b7d70c6 | 1989 | /** |
1f91b4cc | 1990 | * dwc2_hsotg_complete_request - complete a request given to us |
5b7d70c6 BD |
1991 | * @hsotg: The device state. |
1992 | * @hs_ep: The endpoint the request was on. | |
1993 | * @hs_req: The request to complete. | |
1994 | * @result: The result code (0 => Ok, otherwise errno) | |
1995 | * | |
1996 | * The given request has finished, so call the necessary completion | |
1997 | * if it has one and then look to see if we can start a new request | |
1998 | * on the endpoint. | |
1999 | * | |
2000 | * Note, expects the ep to already be locked as appropriate. | |
8b9bc460 | 2001 | */ |
1f91b4cc | 2002 | static void dwc2_hsotg_complete_request(struct dwc2_hsotg *hsotg, |
9da51974 | 2003 | struct dwc2_hsotg_ep *hs_ep, |
1f91b4cc | 2004 | struct dwc2_hsotg_req *hs_req, |
5b7d70c6 BD |
2005 | int result) |
2006 | { | |
5b7d70c6 BD |
2007 | if (!hs_req) { |
2008 | dev_dbg(hsotg->dev, "%s: nothing to complete?\n", __func__); | |
2009 | return; | |
2010 | } | |
2011 | ||
2012 | dev_dbg(hsotg->dev, "complete: ep %p %s, req %p, %d => %p\n", | |
2013 | hs_ep, hs_ep->ep.name, hs_req, result, hs_req->req.complete); | |
2014 | ||
8b9bc460 LM |
2015 | /* |
2016 | * only replace the status if we've not already set an error | |
2017 | * from a previous transaction | |
2018 | */ | |
5b7d70c6 BD |
2019 | |
2020 | if (hs_req->req.status == -EINPROGRESS) | |
2021 | hs_req->req.status = result; | |
2022 | ||
44583fec YL |
2023 | if (using_dma(hsotg)) |
2024 | dwc2_hsotg_unmap_dma(hsotg, hs_ep, hs_req); | |
2025 | ||
1f91b4cc | 2026 | dwc2_hsotg_handle_unaligned_buf_complete(hsotg, hs_ep, hs_req); |
7d24c1b5 | 2027 | |
5b7d70c6 BD |
2028 | hs_ep->req = NULL; |
2029 | list_del_init(&hs_req->queue); | |
2030 | ||
8b9bc460 LM |
2031 | /* |
2032 | * call the complete request with the locks off, just in case the | |
2033 | * request tries to queue more work for this endpoint. | |
2034 | */ | |
5b7d70c6 BD |
2035 | |
2036 | if (hs_req->req.complete) { | |
22258f49 | 2037 | spin_unlock(&hsotg->lock); |
304f7e5e | 2038 | usb_gadget_giveback_request(&hs_ep->ep, &hs_req->req); |
22258f49 | 2039 | spin_lock(&hsotg->lock); |
5b7d70c6 BD |
2040 | } |
2041 | ||
540ccba0 VA |
2042 | /* In DDMA don't need to proceed to starting of next ISOC request */ |
2043 | if (using_desc_dma(hsotg) && hs_ep->isochronous) | |
2044 | return; | |
2045 | ||
8b9bc460 LM |
2046 | /* |
2047 | * Look to see if there is anything else to do. Note, the completion | |
5b7d70c6 | 2048 | * of the previous request may have caused a new request to be started |
8b9bc460 LM |
2049 | * so be careful when doing this. |
2050 | */ | |
5b7d70c6 | 2051 | |
34c0887f | 2052 | if (!hs_ep->req && result >= 0) |
41cc4cd2 | 2053 | dwc2_gadget_start_next_request(hs_ep); |
5b7d70c6 BD |
2054 | } |
2055 | ||
540ccba0 VA |
2056 | /* |
2057 | * dwc2_gadget_complete_isoc_request_ddma - complete an isoc request in DDMA | |
2058 | * @hs_ep: The endpoint the request was on. | |
2059 | * | |
2060 | * Get first request from the ep queue, determine descriptor on which complete | |
729cac69 MH |
2061 | * happened. SW discovers which descriptor currently in use by HW, adjusts |
2062 | * dma_address and calculates index of completed descriptor based on the value | |
2063 | * of DEPDMA register. Update actual length of request, giveback to gadget. | |
540ccba0 VA |
2064 | */ |
2065 | static void dwc2_gadget_complete_isoc_request_ddma(struct dwc2_hsotg_ep *hs_ep) | |
2066 | { | |
2067 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
2068 | struct dwc2_hsotg_req *hs_req; | |
2069 | struct usb_request *ureq; | |
540ccba0 VA |
2070 | u32 desc_sts; |
2071 | u32 mask; | |
2072 | ||
729cac69 | 2073 | desc_sts = hs_ep->desc_list[hs_ep->compl_desc].status; |
540ccba0 | 2074 | |
729cac69 MH |
2075 | /* Process only descriptors with buffer status set to DMA done */ |
2076 | while ((desc_sts & DEV_DMA_BUFF_STS_MASK) >> | |
2077 | DEV_DMA_BUFF_STS_SHIFT == DEV_DMA_BUFF_STS_DMADONE) { | |
540ccba0 | 2078 | |
729cac69 MH |
2079 | hs_req = get_ep_head(hs_ep); |
2080 | if (!hs_req) { | |
2081 | dev_warn(hsotg->dev, "%s: ISOC EP queue empty\n", __func__); | |
2082 | return; | |
2083 | } | |
2084 | ureq = &hs_req->req; | |
2085 | ||
2086 | /* Check completion status */ | |
2087 | if ((desc_sts & DEV_DMA_STS_MASK) >> DEV_DMA_STS_SHIFT == | |
2088 | DEV_DMA_STS_SUCC) { | |
2089 | mask = hs_ep->dir_in ? DEV_DMA_ISOC_TX_NBYTES_MASK : | |
2090 | DEV_DMA_ISOC_RX_NBYTES_MASK; | |
2091 | ureq->actual = ureq->length - ((desc_sts & mask) >> | |
2092 | DEV_DMA_ISOC_NBYTES_SHIFT); | |
2093 | ||
2094 | /* Adjust actual len for ISOC Out if len is | |
2095 | * not align of 4 | |
2096 | */ | |
2097 | if (!hs_ep->dir_in && ureq->length & 0x3) | |
2098 | ureq->actual += 4 - (ureq->length & 0x3); | |
2099 | } | |
540ccba0 | 2100 | |
729cac69 | 2101 | dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0); |
95d2b037 | 2102 | |
729cac69 MH |
2103 | hs_ep->compl_desc++; |
2104 | if (hs_ep->compl_desc > (MAX_DMA_DESC_NUM_GENERIC - 1)) | |
2105 | hs_ep->compl_desc = 0; | |
2106 | desc_sts = hs_ep->desc_list[hs_ep->compl_desc].status; | |
2107 | } | |
540ccba0 VA |
2108 | } |
2109 | ||
2110 | /* | |
729cac69 MH |
2111 | * dwc2_gadget_handle_isoc_bna - handle BNA interrupt for ISOC. |
2112 | * @hs_ep: The isochronous endpoint. | |
540ccba0 | 2113 | * |
729cac69 MH |
2114 | * If EP ISOC OUT then need to flush RX FIFO to remove source of BNA |
2115 | * interrupt. Reset target frame and next_desc to allow to start | |
2116 | * ISOC's on NAK interrupt for IN direction or on OUTTKNEPDIS | |
2117 | * interrupt for OUT direction. | |
540ccba0 | 2118 | */ |
729cac69 | 2119 | static void dwc2_gadget_handle_isoc_bna(struct dwc2_hsotg_ep *hs_ep) |
540ccba0 VA |
2120 | { |
2121 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
540ccba0 | 2122 | |
729cac69 MH |
2123 | if (!hs_ep->dir_in) |
2124 | dwc2_flush_rx_fifo(hsotg); | |
2125 | dwc2_hsotg_complete_request(hsotg, hs_ep, get_ep_head(hs_ep), 0); | |
540ccba0 | 2126 | |
729cac69 MH |
2127 | hs_ep->target_frame = TARGET_FRAME_INITIAL; |
2128 | hs_ep->next_desc = 0; | |
2129 | hs_ep->compl_desc = 0; | |
540ccba0 VA |
2130 | } |
2131 | ||
5b7d70c6 | 2132 | /** |
1f91b4cc | 2133 | * dwc2_hsotg_rx_data - receive data from the FIFO for an endpoint |
5b7d70c6 BD |
2134 | * @hsotg: The device state. |
2135 | * @ep_idx: The endpoint index for the data | |
2136 | * @size: The size of data in the fifo, in bytes | |
2137 | * | |
2138 | * The FIFO status shows there is data to read from the FIFO for a given | |
2139 | * endpoint, so sort out whether we need to read the data into a request | |
2140 | * that has been made for that endpoint. | |
2141 | */ | |
1f91b4cc | 2142 | static void dwc2_hsotg_rx_data(struct dwc2_hsotg *hsotg, int ep_idx, int size) |
5b7d70c6 | 2143 | { |
1f91b4cc FB |
2144 | struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[ep_idx]; |
2145 | struct dwc2_hsotg_req *hs_req = hs_ep->req; | |
5b7d70c6 BD |
2146 | int to_read; |
2147 | int max_req; | |
2148 | int read_ptr; | |
2149 | ||
2150 | if (!hs_req) { | |
f25c42b8 | 2151 | u32 epctl = dwc2_readl(hsotg, DOEPCTL(ep_idx)); |
5b7d70c6 BD |
2152 | int ptr; |
2153 | ||
6b448af4 | 2154 | dev_dbg(hsotg->dev, |
9da51974 | 2155 | "%s: FIFO %d bytes on ep%d but no req (DXEPCTl=0x%08x)\n", |
5b7d70c6 BD |
2156 | __func__, size, ep_idx, epctl); |
2157 | ||
2158 | /* dump the data from the FIFO, we've nothing we can do */ | |
2159 | for (ptr = 0; ptr < size; ptr += 4) | |
f25c42b8 | 2160 | (void)dwc2_readl(hsotg, EPFIFO(ep_idx)); |
5b7d70c6 BD |
2161 | |
2162 | return; | |
2163 | } | |
2164 | ||
5b7d70c6 BD |
2165 | to_read = size; |
2166 | read_ptr = hs_req->req.actual; | |
2167 | max_req = hs_req->req.length - read_ptr; | |
2168 | ||
a33e7136 BD |
2169 | dev_dbg(hsotg->dev, "%s: read %d/%d, done %d/%d\n", |
2170 | __func__, to_read, max_req, read_ptr, hs_req->req.length); | |
2171 | ||
5b7d70c6 | 2172 | if (to_read > max_req) { |
8b9bc460 LM |
2173 | /* |
2174 | * more data appeared than we where willing | |
5b7d70c6 BD |
2175 | * to deal with in this request. |
2176 | */ | |
2177 | ||
2178 | /* currently we don't deal this */ | |
2179 | WARN_ON_ONCE(1); | |
2180 | } | |
2181 | ||
5b7d70c6 BD |
2182 | hs_ep->total_data += to_read; |
2183 | hs_req->req.actual += to_read; | |
2184 | to_read = DIV_ROUND_UP(to_read, 4); | |
2185 | ||
8b9bc460 LM |
2186 | /* |
2187 | * note, we might over-write the buffer end by 3 bytes depending on | |
2188 | * alignment of the data. | |
2189 | */ | |
342ccce1 GS |
2190 | dwc2_readl_rep(hsotg, EPFIFO(ep_idx), |
2191 | hs_req->req.buf + read_ptr, to_read); | |
5b7d70c6 BD |
2192 | } |
2193 | ||
2194 | /** | |
1f91b4cc | 2195 | * dwc2_hsotg_ep0_zlp - send/receive zero-length packet on control endpoint |
5b7d70c6 | 2196 | * @hsotg: The device instance |
fe0b94ab | 2197 | * @dir_in: If IN zlp |
5b7d70c6 BD |
2198 | * |
2199 | * Generate a zero-length IN packet request for terminating a SETUP | |
2200 | * transaction. | |
2201 | * | |
2202 | * Note, since we don't write any data to the TxFIFO, then it is | |
25985edc | 2203 | * currently believed that we do not need to wait for any space in |
5b7d70c6 BD |
2204 | * the TxFIFO. |
2205 | */ | |
1f91b4cc | 2206 | static void dwc2_hsotg_ep0_zlp(struct dwc2_hsotg *hsotg, bool dir_in) |
5b7d70c6 | 2207 | { |
c6f5c050 | 2208 | /* eps_out[0] is used in both directions */ |
fe0b94ab MYK |
2209 | hsotg->eps_out[0]->dir_in = dir_in; |
2210 | hsotg->ep0_state = dir_in ? DWC2_EP0_STATUS_IN : DWC2_EP0_STATUS_OUT; | |
5b7d70c6 | 2211 | |
1f91b4cc | 2212 | dwc2_hsotg_program_zlp(hsotg, hsotg->eps_out[0]); |
5b7d70c6 BD |
2213 | } |
2214 | ||
ec1f9d9f | 2215 | static void dwc2_hsotg_change_ep_iso_parity(struct dwc2_hsotg *hsotg, |
9da51974 | 2216 | u32 epctl_reg) |
ec1f9d9f RB |
2217 | { |
2218 | u32 ctrl; | |
2219 | ||
f25c42b8 | 2220 | ctrl = dwc2_readl(hsotg, epctl_reg); |
ec1f9d9f RB |
2221 | if (ctrl & DXEPCTL_EOFRNUM) |
2222 | ctrl |= DXEPCTL_SETEVENFR; | |
2223 | else | |
2224 | ctrl |= DXEPCTL_SETODDFR; | |
f25c42b8 | 2225 | dwc2_writel(hsotg, ctrl, epctl_reg); |
ec1f9d9f RB |
2226 | } |
2227 | ||
aa3e8bc8 VA |
2228 | /* |
2229 | * dwc2_gadget_get_xfersize_ddma - get transferred bytes amount from desc | |
2230 | * @hs_ep - The endpoint on which transfer went | |
2231 | * | |
2232 | * Iterate over endpoints descriptor chain and get info on bytes remained | |
2233 | * in DMA descriptors after transfer has completed. Used for non isoc EPs. | |
2234 | */ | |
2235 | static unsigned int dwc2_gadget_get_xfersize_ddma(struct dwc2_hsotg_ep *hs_ep) | |
2236 | { | |
2237 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
2238 | unsigned int bytes_rem = 0; | |
2239 | struct dwc2_dma_desc *desc = hs_ep->desc_list; | |
2240 | int i; | |
2241 | u32 status; | |
2242 | ||
2243 | if (!desc) | |
2244 | return -EINVAL; | |
2245 | ||
2246 | for (i = 0; i < hs_ep->desc_count; ++i) { | |
2247 | status = desc->status; | |
2248 | bytes_rem += status & DEV_DMA_NBYTES_MASK; | |
2249 | ||
2250 | if (status & DEV_DMA_STS_MASK) | |
2251 | dev_err(hsotg->dev, "descriptor %d closed with %x\n", | |
2252 | i, status & DEV_DMA_STS_MASK); | |
2253 | } | |
2254 | ||
2255 | return bytes_rem; | |
2256 | } | |
2257 | ||
5b7d70c6 | 2258 | /** |
1f91b4cc | 2259 | * dwc2_hsotg_handle_outdone - handle receiving OutDone/SetupDone from RXFIFO |
5b7d70c6 BD |
2260 | * @hsotg: The device instance |
2261 | * @epnum: The endpoint received from | |
5b7d70c6 BD |
2262 | * |
2263 | * The RXFIFO has delivered an OutDone event, which means that the data | |
2264 | * transfer for an OUT endpoint has been completed, either by a short | |
2265 | * packet or by the finish of a transfer. | |
8b9bc460 | 2266 | */ |
1f91b4cc | 2267 | static void dwc2_hsotg_handle_outdone(struct dwc2_hsotg *hsotg, int epnum) |
5b7d70c6 | 2268 | { |
f25c42b8 | 2269 | u32 epsize = dwc2_readl(hsotg, DOEPTSIZ(epnum)); |
1f91b4cc FB |
2270 | struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[epnum]; |
2271 | struct dwc2_hsotg_req *hs_req = hs_ep->req; | |
5b7d70c6 | 2272 | struct usb_request *req = &hs_req->req; |
9da51974 | 2273 | unsigned int size_left = DXEPTSIZ_XFERSIZE_GET(epsize); |
5b7d70c6 BD |
2274 | int result = 0; |
2275 | ||
2276 | if (!hs_req) { | |
2277 | dev_dbg(hsotg->dev, "%s: no request active\n", __func__); | |
2278 | return; | |
2279 | } | |
2280 | ||
fe0b94ab MYK |
2281 | if (epnum == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_OUT) { |
2282 | dev_dbg(hsotg->dev, "zlp packet received\n"); | |
1f91b4cc FB |
2283 | dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0); |
2284 | dwc2_hsotg_enqueue_setup(hsotg); | |
fe0b94ab MYK |
2285 | return; |
2286 | } | |
2287 | ||
aa3e8bc8 VA |
2288 | if (using_desc_dma(hsotg)) |
2289 | size_left = dwc2_gadget_get_xfersize_ddma(hs_ep); | |
2290 | ||
5b7d70c6 | 2291 | if (using_dma(hsotg)) { |
9da51974 | 2292 | unsigned int size_done; |
5b7d70c6 | 2293 | |
8b9bc460 LM |
2294 | /* |
2295 | * Calculate the size of the transfer by checking how much | |
5b7d70c6 BD |
2296 | * is left in the endpoint size register and then working it |
2297 | * out from the amount we loaded for the transfer. | |
2298 | * | |
2299 | * We need to do this as DMA pointers are always 32bit aligned | |
2300 | * so may overshoot/undershoot the transfer. | |
2301 | */ | |
2302 | ||
5b7d70c6 BD |
2303 | size_done = hs_ep->size_loaded - size_left; |
2304 | size_done += hs_ep->last_load; | |
2305 | ||
2306 | req->actual = size_done; | |
2307 | } | |
2308 | ||
a33e7136 BD |
2309 | /* if there is more request to do, schedule new transfer */ |
2310 | if (req->actual < req->length && size_left == 0) { | |
1f91b4cc | 2311 | dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true); |
a33e7136 BD |
2312 | return; |
2313 | } | |
2314 | ||
5b7d70c6 BD |
2315 | if (req->actual < req->length && req->short_not_ok) { |
2316 | dev_dbg(hsotg->dev, "%s: got %d/%d (short not ok) => error\n", | |
2317 | __func__, req->actual, req->length); | |
2318 | ||
8b9bc460 LM |
2319 | /* |
2320 | * todo - what should we return here? there's no one else | |
2321 | * even bothering to check the status. | |
2322 | */ | |
5b7d70c6 BD |
2323 | } |
2324 | ||
ef750c71 VA |
2325 | /* DDMA IN status phase will start from StsPhseRcvd interrupt */ |
2326 | if (!using_desc_dma(hsotg) && epnum == 0 && | |
2327 | hsotg->ep0_state == DWC2_EP0_DATA_OUT) { | |
fe0b94ab | 2328 | /* Move to STATUS IN */ |
1f91b4cc | 2329 | dwc2_hsotg_ep0_zlp(hsotg, true); |
fe0b94ab | 2330 | return; |
5b7d70c6 BD |
2331 | } |
2332 | ||
ec1f9d9f RB |
2333 | /* |
2334 | * Slave mode OUT transfers do not go through XferComplete so | |
2335 | * adjust the ISOC parity here. | |
2336 | */ | |
2337 | if (!using_dma(hsotg)) { | |
ec1f9d9f RB |
2338 | if (hs_ep->isochronous && hs_ep->interval == 1) |
2339 | dwc2_hsotg_change_ep_iso_parity(hsotg, DOEPCTL(epnum)); | |
837e9f00 VM |
2340 | else if (hs_ep->isochronous && hs_ep->interval > 1) |
2341 | dwc2_gadget_incr_frame_num(hs_ep); | |
ec1f9d9f RB |
2342 | } |
2343 | ||
1f91b4cc | 2344 | dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, result); |
5b7d70c6 BD |
2345 | } |
2346 | ||
5b7d70c6 | 2347 | /** |
1f91b4cc | 2348 | * dwc2_hsotg_handle_rx - RX FIFO has data |
5b7d70c6 BD |
2349 | * @hsotg: The device instance |
2350 | * | |
2351 | * The IRQ handler has detected that the RX FIFO has some data in it | |
2352 | * that requires processing, so find out what is in there and do the | |
2353 | * appropriate read. | |
2354 | * | |
25985edc | 2355 | * The RXFIFO is a true FIFO, the packets coming out are still in packet |
5b7d70c6 BD |
2356 | * chunks, so if you have x packets received on an endpoint you'll get x |
2357 | * FIFO events delivered, each with a packet's worth of data in it. | |
2358 | * | |
2359 | * When using DMA, we should not be processing events from the RXFIFO | |
2360 | * as the actual data should be sent to the memory directly and we turn | |
2361 | * on the completion interrupts to get notifications of transfer completion. | |
2362 | */ | |
1f91b4cc | 2363 | static void dwc2_hsotg_handle_rx(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 2364 | { |
f25c42b8 | 2365 | u32 grxstsr = dwc2_readl(hsotg, GRXSTSP); |
5b7d70c6 BD |
2366 | u32 epnum, status, size; |
2367 | ||
2368 | WARN_ON(using_dma(hsotg)); | |
2369 | ||
47a1685f DN |
2370 | epnum = grxstsr & GRXSTS_EPNUM_MASK; |
2371 | status = grxstsr & GRXSTS_PKTSTS_MASK; | |
5b7d70c6 | 2372 | |
47a1685f DN |
2373 | size = grxstsr & GRXSTS_BYTECNT_MASK; |
2374 | size >>= GRXSTS_BYTECNT_SHIFT; | |
5b7d70c6 | 2375 | |
d7c747c5 | 2376 | dev_dbg(hsotg->dev, "%s: GRXSTSP=0x%08x (%d@%d)\n", |
9da51974 | 2377 | __func__, grxstsr, size, epnum); |
5b7d70c6 | 2378 | |
47a1685f DN |
2379 | switch ((status & GRXSTS_PKTSTS_MASK) >> GRXSTS_PKTSTS_SHIFT) { |
2380 | case GRXSTS_PKTSTS_GLOBALOUTNAK: | |
2381 | dev_dbg(hsotg->dev, "GLOBALOUTNAK\n"); | |
5b7d70c6 BD |
2382 | break; |
2383 | ||
47a1685f | 2384 | case GRXSTS_PKTSTS_OUTDONE: |
5b7d70c6 | 2385 | dev_dbg(hsotg->dev, "OutDone (Frame=0x%08x)\n", |
1f91b4cc | 2386 | dwc2_hsotg_read_frameno(hsotg)); |
5b7d70c6 BD |
2387 | |
2388 | if (!using_dma(hsotg)) | |
1f91b4cc | 2389 | dwc2_hsotg_handle_outdone(hsotg, epnum); |
5b7d70c6 BD |
2390 | break; |
2391 | ||
47a1685f | 2392 | case GRXSTS_PKTSTS_SETUPDONE: |
5b7d70c6 BD |
2393 | dev_dbg(hsotg->dev, |
2394 | "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n", | |
1f91b4cc | 2395 | dwc2_hsotg_read_frameno(hsotg), |
f25c42b8 | 2396 | dwc2_readl(hsotg, DOEPCTL(0))); |
fe0b94ab | 2397 | /* |
1f91b4cc | 2398 | * Call dwc2_hsotg_handle_outdone here if it was not called from |
fe0b94ab MYK |
2399 | * GRXSTS_PKTSTS_OUTDONE. That is, if the core didn't |
2400 | * generate GRXSTS_PKTSTS_OUTDONE for setup packet. | |
2401 | */ | |
2402 | if (hsotg->ep0_state == DWC2_EP0_SETUP) | |
1f91b4cc | 2403 | dwc2_hsotg_handle_outdone(hsotg, epnum); |
5b7d70c6 BD |
2404 | break; |
2405 | ||
47a1685f | 2406 | case GRXSTS_PKTSTS_OUTRX: |
1f91b4cc | 2407 | dwc2_hsotg_rx_data(hsotg, epnum, size); |
5b7d70c6 BD |
2408 | break; |
2409 | ||
47a1685f | 2410 | case GRXSTS_PKTSTS_SETUPRX: |
5b7d70c6 BD |
2411 | dev_dbg(hsotg->dev, |
2412 | "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n", | |
1f91b4cc | 2413 | dwc2_hsotg_read_frameno(hsotg), |
f25c42b8 | 2414 | dwc2_readl(hsotg, DOEPCTL(0))); |
5b7d70c6 | 2415 | |
fe0b94ab MYK |
2416 | WARN_ON(hsotg->ep0_state != DWC2_EP0_SETUP); |
2417 | ||
1f91b4cc | 2418 | dwc2_hsotg_rx_data(hsotg, epnum, size); |
5b7d70c6 BD |
2419 | break; |
2420 | ||
2421 | default: | |
2422 | dev_warn(hsotg->dev, "%s: unknown status %08x\n", | |
2423 | __func__, grxstsr); | |
2424 | ||
1f91b4cc | 2425 | dwc2_hsotg_dump(hsotg); |
5b7d70c6 BD |
2426 | break; |
2427 | } | |
2428 | } | |
2429 | ||
2430 | /** | |
1f91b4cc | 2431 | * dwc2_hsotg_ep0_mps - turn max packet size into register setting |
5b7d70c6 | 2432 | * @mps: The maximum packet size in bytes. |
8b9bc460 | 2433 | */ |
1f91b4cc | 2434 | static u32 dwc2_hsotg_ep0_mps(unsigned int mps) |
5b7d70c6 BD |
2435 | { |
2436 | switch (mps) { | |
2437 | case 64: | |
94cb8fd6 | 2438 | return D0EPCTL_MPS_64; |
5b7d70c6 | 2439 | case 32: |
94cb8fd6 | 2440 | return D0EPCTL_MPS_32; |
5b7d70c6 | 2441 | case 16: |
94cb8fd6 | 2442 | return D0EPCTL_MPS_16; |
5b7d70c6 | 2443 | case 8: |
94cb8fd6 | 2444 | return D0EPCTL_MPS_8; |
5b7d70c6 BD |
2445 | } |
2446 | ||
2447 | /* bad max packet size, warn and return invalid result */ | |
2448 | WARN_ON(1); | |
2449 | return (u32)-1; | |
2450 | } | |
2451 | ||
2452 | /** | |
1f91b4cc | 2453 | * dwc2_hsotg_set_ep_maxpacket - set endpoint's max-packet field |
5b7d70c6 BD |
2454 | * @hsotg: The driver state. |
2455 | * @ep: The index number of the endpoint | |
2456 | * @mps: The maximum packet size in bytes | |
ee2c40de | 2457 | * @mc: The multicount value |
6fb914d7 | 2458 | * @dir_in: True if direction is in. |
5b7d70c6 BD |
2459 | * |
2460 | * Configure the maximum packet size for the given endpoint, updating | |
2461 | * the hardware control registers to reflect this. | |
2462 | */ | |
1f91b4cc | 2463 | static void dwc2_hsotg_set_ep_maxpacket(struct dwc2_hsotg *hsotg, |
ee2c40de VM |
2464 | unsigned int ep, unsigned int mps, |
2465 | unsigned int mc, unsigned int dir_in) | |
5b7d70c6 | 2466 | { |
1f91b4cc | 2467 | struct dwc2_hsotg_ep *hs_ep; |
5b7d70c6 BD |
2468 | u32 reg; |
2469 | ||
c6f5c050 MYK |
2470 | hs_ep = index_to_ep(hsotg, ep, dir_in); |
2471 | if (!hs_ep) | |
2472 | return; | |
2473 | ||
5b7d70c6 | 2474 | if (ep == 0) { |
ee2c40de VM |
2475 | u32 mps_bytes = mps; |
2476 | ||
5b7d70c6 | 2477 | /* EP0 is a special case */ |
ee2c40de VM |
2478 | mps = dwc2_hsotg_ep0_mps(mps_bytes); |
2479 | if (mps > 3) | |
5b7d70c6 | 2480 | goto bad_mps; |
ee2c40de | 2481 | hs_ep->ep.maxpacket = mps_bytes; |
4fca54aa | 2482 | hs_ep->mc = 1; |
5b7d70c6 | 2483 | } else { |
ee2c40de | 2484 | if (mps > 1024) |
5b7d70c6 | 2485 | goto bad_mps; |
ee2c40de VM |
2486 | hs_ep->mc = mc; |
2487 | if (mc > 3) | |
4fca54aa | 2488 | goto bad_mps; |
ee2c40de | 2489 | hs_ep->ep.maxpacket = mps; |
5b7d70c6 BD |
2490 | } |
2491 | ||
c6f5c050 | 2492 | if (dir_in) { |
f25c42b8 | 2493 | reg = dwc2_readl(hsotg, DIEPCTL(ep)); |
c6f5c050 | 2494 | reg &= ~DXEPCTL_MPS_MASK; |
ee2c40de | 2495 | reg |= mps; |
f25c42b8 | 2496 | dwc2_writel(hsotg, reg, DIEPCTL(ep)); |
c6f5c050 | 2497 | } else { |
f25c42b8 | 2498 | reg = dwc2_readl(hsotg, DOEPCTL(ep)); |
47a1685f | 2499 | reg &= ~DXEPCTL_MPS_MASK; |
ee2c40de | 2500 | reg |= mps; |
f25c42b8 | 2501 | dwc2_writel(hsotg, reg, DOEPCTL(ep)); |
659ad60c | 2502 | } |
5b7d70c6 BD |
2503 | |
2504 | return; | |
2505 | ||
2506 | bad_mps: | |
2507 | dev_err(hsotg->dev, "ep%d: bad mps of %d\n", ep, mps); | |
2508 | } | |
2509 | ||
9c39ddc6 | 2510 | /** |
1f91b4cc | 2511 | * dwc2_hsotg_txfifo_flush - flush Tx FIFO |
9c39ddc6 AT |
2512 | * @hsotg: The driver state |
2513 | * @idx: The index for the endpoint (0..15) | |
2514 | */ | |
1f91b4cc | 2515 | static void dwc2_hsotg_txfifo_flush(struct dwc2_hsotg *hsotg, unsigned int idx) |
9c39ddc6 | 2516 | { |
f25c42b8 GS |
2517 | dwc2_writel(hsotg, GRSTCTL_TXFNUM(idx) | GRSTCTL_TXFFLSH, |
2518 | GRSTCTL); | |
9c39ddc6 AT |
2519 | |
2520 | /* wait until the fifo is flushed */ | |
79d6b8c5 SA |
2521 | if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL, GRSTCTL_TXFFLSH, 100)) |
2522 | dev_warn(hsotg->dev, "%s: timeout flushing fifo GRSTCTL_TXFFLSH\n", | |
2523 | __func__); | |
9c39ddc6 | 2524 | } |
5b7d70c6 BD |
2525 | |
2526 | /** | |
1f91b4cc | 2527 | * dwc2_hsotg_trytx - check to see if anything needs transmitting |
5b7d70c6 BD |
2528 | * @hsotg: The driver state |
2529 | * @hs_ep: The driver endpoint to check. | |
2530 | * | |
2531 | * Check to see if there is a request that has data to send, and if so | |
2532 | * make an attempt to write data into the FIFO. | |
2533 | */ | |
1f91b4cc | 2534 | static int dwc2_hsotg_trytx(struct dwc2_hsotg *hsotg, |
9da51974 | 2535 | struct dwc2_hsotg_ep *hs_ep) |
5b7d70c6 | 2536 | { |
1f91b4cc | 2537 | struct dwc2_hsotg_req *hs_req = hs_ep->req; |
5b7d70c6 | 2538 | |
afcf4169 RB |
2539 | if (!hs_ep->dir_in || !hs_req) { |
2540 | /** | |
2541 | * if request is not enqueued, we disable interrupts | |
2542 | * for endpoints, excepting ep0 | |
2543 | */ | |
2544 | if (hs_ep->index != 0) | |
1f91b4cc | 2545 | dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, |
9da51974 | 2546 | hs_ep->dir_in, 0); |
5b7d70c6 | 2547 | return 0; |
afcf4169 | 2548 | } |
5b7d70c6 BD |
2549 | |
2550 | if (hs_req->req.actual < hs_req->req.length) { | |
2551 | dev_dbg(hsotg->dev, "trying to write more for ep%d\n", | |
2552 | hs_ep->index); | |
1f91b4cc | 2553 | return dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req); |
5b7d70c6 BD |
2554 | } |
2555 | ||
2556 | return 0; | |
2557 | } | |
2558 | ||
2559 | /** | |
1f91b4cc | 2560 | * dwc2_hsotg_complete_in - complete IN transfer |
5b7d70c6 BD |
2561 | * @hsotg: The device state. |
2562 | * @hs_ep: The endpoint that has just completed. | |
2563 | * | |
2564 | * An IN transfer has been completed, update the transfer's state and then | |
2565 | * call the relevant completion routines. | |
2566 | */ | |
1f91b4cc | 2567 | static void dwc2_hsotg_complete_in(struct dwc2_hsotg *hsotg, |
9da51974 | 2568 | struct dwc2_hsotg_ep *hs_ep) |
5b7d70c6 | 2569 | { |
1f91b4cc | 2570 | struct dwc2_hsotg_req *hs_req = hs_ep->req; |
f25c42b8 | 2571 | u32 epsize = dwc2_readl(hsotg, DIEPTSIZ(hs_ep->index)); |
5b7d70c6 BD |
2572 | int size_left, size_done; |
2573 | ||
2574 | if (!hs_req) { | |
2575 | dev_dbg(hsotg->dev, "XferCompl but no req\n"); | |
2576 | return; | |
2577 | } | |
2578 | ||
d3ca0259 | 2579 | /* Finish ZLP handling for IN EP0 transactions */ |
fe0b94ab MYK |
2580 | if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_IN) { |
2581 | dev_dbg(hsotg->dev, "zlp packet sent\n"); | |
c3b22fe2 RK |
2582 | |
2583 | /* | |
2584 | * While send zlp for DWC2_EP0_STATUS_IN EP direction was | |
2585 | * changed to IN. Change back to complete OUT transfer request | |
2586 | */ | |
2587 | hs_ep->dir_in = 0; | |
2588 | ||
1f91b4cc | 2589 | dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0); |
9e14d0a5 GH |
2590 | if (hsotg->test_mode) { |
2591 | int ret; | |
2592 | ||
1f91b4cc | 2593 | ret = dwc2_hsotg_set_test_mode(hsotg, hsotg->test_mode); |
9e14d0a5 GH |
2594 | if (ret < 0) { |
2595 | dev_dbg(hsotg->dev, "Invalid Test #%d\n", | |
9da51974 | 2596 | hsotg->test_mode); |
1f91b4cc | 2597 | dwc2_hsotg_stall_ep0(hsotg); |
9e14d0a5 GH |
2598 | return; |
2599 | } | |
2600 | } | |
1f91b4cc | 2601 | dwc2_hsotg_enqueue_setup(hsotg); |
d3ca0259 LM |
2602 | return; |
2603 | } | |
2604 | ||
8b9bc460 LM |
2605 | /* |
2606 | * Calculate the size of the transfer by checking how much is left | |
5b7d70c6 BD |
2607 | * in the endpoint size register and then working it out from |
2608 | * the amount we loaded for the transfer. | |
2609 | * | |
2610 | * We do this even for DMA, as the transfer may have incremented | |
2611 | * past the end of the buffer (DMA transfers are always 32bit | |
2612 | * aligned). | |
2613 | */ | |
aa3e8bc8 VA |
2614 | if (using_desc_dma(hsotg)) { |
2615 | size_left = dwc2_gadget_get_xfersize_ddma(hs_ep); | |
2616 | if (size_left < 0) | |
2617 | dev_err(hsotg->dev, "error parsing DDMA results %d\n", | |
2618 | size_left); | |
2619 | } else { | |
2620 | size_left = DXEPTSIZ_XFERSIZE_GET(epsize); | |
2621 | } | |
5b7d70c6 BD |
2622 | |
2623 | size_done = hs_ep->size_loaded - size_left; | |
2624 | size_done += hs_ep->last_load; | |
2625 | ||
2626 | if (hs_req->req.actual != size_done) | |
2627 | dev_dbg(hsotg->dev, "%s: adjusting size done %d => %d\n", | |
2628 | __func__, hs_req->req.actual, size_done); | |
2629 | ||
2630 | hs_req->req.actual = size_done; | |
d3ca0259 LM |
2631 | dev_dbg(hsotg->dev, "req->length:%d req->actual:%d req->zero:%d\n", |
2632 | hs_req->req.length, hs_req->req.actual, hs_req->req.zero); | |
2633 | ||
5b7d70c6 BD |
2634 | if (!size_left && hs_req->req.actual < hs_req->req.length) { |
2635 | dev_dbg(hsotg->dev, "%s trying more for req...\n", __func__); | |
1f91b4cc | 2636 | dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true); |
fe0b94ab MYK |
2637 | return; |
2638 | } | |
2639 | ||
f71b5e25 | 2640 | /* Zlp for all endpoints, for ep0 only in DATA IN stage */ |
8a20fa45 | 2641 | if (hs_ep->send_zlp) { |
1f91b4cc | 2642 | dwc2_hsotg_program_zlp(hsotg, hs_ep); |
8a20fa45 | 2643 | hs_ep->send_zlp = 0; |
f71b5e25 MYK |
2644 | /* transfer will be completed on next complete interrupt */ |
2645 | return; | |
2646 | } | |
2647 | ||
fe0b94ab MYK |
2648 | if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_DATA_IN) { |
2649 | /* Move to STATUS OUT */ | |
1f91b4cc | 2650 | dwc2_hsotg_ep0_zlp(hsotg, false); |
fe0b94ab MYK |
2651 | return; |
2652 | } | |
2653 | ||
1f91b4cc | 2654 | dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0); |
5b7d70c6 BD |
2655 | } |
2656 | ||
32601588 VM |
2657 | /** |
2658 | * dwc2_gadget_read_ep_interrupts - reads interrupts for given ep | |
2659 | * @hsotg: The device state. | |
2660 | * @idx: Index of ep. | |
2661 | * @dir_in: Endpoint direction 1-in 0-out. | |
2662 | * | |
2663 | * Reads for endpoint with given index and direction, by masking | |
2664 | * epint_reg with coresponding mask. | |
2665 | */ | |
2666 | static u32 dwc2_gadget_read_ep_interrupts(struct dwc2_hsotg *hsotg, | |
2667 | unsigned int idx, int dir_in) | |
2668 | { | |
2669 | u32 epmsk_reg = dir_in ? DIEPMSK : DOEPMSK; | |
2670 | u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx); | |
2671 | u32 ints; | |
2672 | u32 mask; | |
2673 | u32 diepempmsk; | |
2674 | ||
f25c42b8 GS |
2675 | mask = dwc2_readl(hsotg, epmsk_reg); |
2676 | diepempmsk = dwc2_readl(hsotg, DIEPEMPMSK); | |
32601588 VM |
2677 | mask |= ((diepempmsk >> idx) & 0x1) ? DIEPMSK_TXFIFOEMPTY : 0; |
2678 | mask |= DXEPINT_SETUP_RCVD; | |
2679 | ||
f25c42b8 | 2680 | ints = dwc2_readl(hsotg, epint_reg); |
32601588 VM |
2681 | ints &= mask; |
2682 | return ints; | |
2683 | } | |
2684 | ||
bd9971f0 VM |
2685 | /** |
2686 | * dwc2_gadget_handle_ep_disabled - handle DXEPINT_EPDISBLD | |
2687 | * @hs_ep: The endpoint on which interrupt is asserted. | |
2688 | * | |
2689 | * This interrupt indicates that the endpoint has been disabled per the | |
2690 | * application's request. | |
2691 | * | |
2692 | * For IN endpoints flushes txfifo, in case of BULK clears DCTL_CGNPINNAK, | |
2693 | * in case of ISOC completes current request. | |
2694 | * | |
2695 | * For ISOC-OUT endpoints completes expired requests. If there is remaining | |
2696 | * request starts it. | |
2697 | */ | |
2698 | static void dwc2_gadget_handle_ep_disabled(struct dwc2_hsotg_ep *hs_ep) | |
2699 | { | |
2700 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
2701 | struct dwc2_hsotg_req *hs_req; | |
2702 | unsigned char idx = hs_ep->index; | |
2703 | int dir_in = hs_ep->dir_in; | |
2704 | u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx); | |
f25c42b8 | 2705 | int dctl = dwc2_readl(hsotg, DCTL); |
bd9971f0 VM |
2706 | |
2707 | dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__); | |
2708 | ||
2709 | if (dir_in) { | |
f25c42b8 | 2710 | int epctl = dwc2_readl(hsotg, epctl_reg); |
bd9971f0 VM |
2711 | |
2712 | dwc2_hsotg_txfifo_flush(hsotg, hs_ep->fifo_index); | |
2713 | ||
2714 | if (hs_ep->isochronous) { | |
2715 | dwc2_hsotg_complete_in(hsotg, hs_ep); | |
2716 | return; | |
2717 | } | |
2718 | ||
2719 | if ((epctl & DXEPCTL_STALL) && (epctl & DXEPCTL_EPTYPE_BULK)) { | |
f25c42b8 | 2720 | int dctl = dwc2_readl(hsotg, DCTL); |
bd9971f0 VM |
2721 | |
2722 | dctl |= DCTL_CGNPINNAK; | |
f25c42b8 | 2723 | dwc2_writel(hsotg, dctl, DCTL); |
bd9971f0 VM |
2724 | } |
2725 | return; | |
2726 | } | |
2727 | ||
2728 | if (dctl & DCTL_GOUTNAKSTS) { | |
2729 | dctl |= DCTL_CGOUTNAK; | |
f25c42b8 | 2730 | dwc2_writel(hsotg, dctl, DCTL); |
bd9971f0 VM |
2731 | } |
2732 | ||
2733 | if (!hs_ep->isochronous) | |
2734 | return; | |
2735 | ||
2736 | if (list_empty(&hs_ep->queue)) { | |
2737 | dev_dbg(hsotg->dev, "%s: complete_ep 0x%p, ep->queue empty!\n", | |
2738 | __func__, hs_ep); | |
2739 | return; | |
2740 | } | |
2741 | ||
2742 | do { | |
2743 | hs_req = get_ep_head(hs_ep); | |
2744 | if (hs_req) | |
2745 | dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, | |
2746 | -ENODATA); | |
2747 | dwc2_gadget_incr_frame_num(hs_ep); | |
c7c24e7a AP |
2748 | /* Update current frame number value. */ |
2749 | hsotg->frame_number = dwc2_hsotg_read_frameno(hsotg); | |
bd9971f0 VM |
2750 | } while (dwc2_gadget_target_frame_elapsed(hs_ep)); |
2751 | ||
2752 | dwc2_gadget_start_next_request(hs_ep); | |
2753 | } | |
2754 | ||
5321922c VM |
2755 | /** |
2756 | * dwc2_gadget_handle_out_token_ep_disabled - handle DXEPINT_OUTTKNEPDIS | |
6fb914d7 | 2757 | * @ep: The endpoint on which interrupt is asserted. |
5321922c VM |
2758 | * |
2759 | * This is starting point for ISOC-OUT transfer, synchronization done with | |
2760 | * first out token received from host while corresponding EP is disabled. | |
2761 | * | |
2762 | * Device does not know initial frame in which out token will come. For this | |
2763 | * HW generates OUTTKNEPDIS - out token is received while EP is disabled. Upon | |
2764 | * getting this interrupt SW starts calculation for next transfer frame. | |
2765 | */ | |
2766 | static void dwc2_gadget_handle_out_token_ep_disabled(struct dwc2_hsotg_ep *ep) | |
2767 | { | |
2768 | struct dwc2_hsotg *hsotg = ep->parent; | |
2769 | int dir_in = ep->dir_in; | |
2770 | u32 doepmsk; | |
2771 | ||
2772 | if (dir_in || !ep->isochronous) | |
2773 | return; | |
2774 | ||
540ccba0 VA |
2775 | if (using_desc_dma(hsotg)) { |
2776 | if (ep->target_frame == TARGET_FRAME_INITIAL) { | |
2777 | /* Start first ISO Out */ | |
4d4f1e79 | 2778 | ep->target_frame = hsotg->frame_number; |
540ccba0 VA |
2779 | dwc2_gadget_start_isoc_ddma(ep); |
2780 | } | |
2781 | return; | |
2782 | } | |
2783 | ||
5321922c VM |
2784 | if (ep->interval > 1 && |
2785 | ep->target_frame == TARGET_FRAME_INITIAL) { | |
5321922c VM |
2786 | u32 ctrl; |
2787 | ||
4d4f1e79 | 2788 | ep->target_frame = hsotg->frame_number; |
5321922c VM |
2789 | dwc2_gadget_incr_frame_num(ep); |
2790 | ||
f25c42b8 | 2791 | ctrl = dwc2_readl(hsotg, DOEPCTL(ep->index)); |
5321922c VM |
2792 | if (ep->target_frame & 0x1) |
2793 | ctrl |= DXEPCTL_SETODDFR; | |
2794 | else | |
2795 | ctrl |= DXEPCTL_SETEVENFR; | |
2796 | ||
f25c42b8 | 2797 | dwc2_writel(hsotg, ctrl, DOEPCTL(ep->index)); |
5321922c VM |
2798 | } |
2799 | ||
2800 | dwc2_gadget_start_next_request(ep); | |
f25c42b8 | 2801 | doepmsk = dwc2_readl(hsotg, DOEPMSK); |
5321922c | 2802 | doepmsk &= ~DOEPMSK_OUTTKNEPDISMSK; |
f25c42b8 | 2803 | dwc2_writel(hsotg, doepmsk, DOEPMSK); |
5321922c VM |
2804 | } |
2805 | ||
2806 | /** | |
38beaec6 JY |
2807 | * dwc2_gadget_handle_nak - handle NAK interrupt |
2808 | * @hs_ep: The endpoint on which interrupt is asserted. | |
2809 | * | |
2810 | * This is starting point for ISOC-IN transfer, synchronization done with | |
2811 | * first IN token received from host while corresponding EP is disabled. | |
2812 | * | |
2813 | * Device does not know when first one token will arrive from host. On first | |
2814 | * token arrival HW generates 2 interrupts: 'in token received while FIFO empty' | |
2815 | * and 'NAK'. NAK interrupt for ISOC-IN means that token has arrived and ZLP was | |
2816 | * sent in response to that as there was no data in FIFO. SW is basing on this | |
2817 | * interrupt to obtain frame in which token has come and then based on the | |
2818 | * interval calculates next frame for transfer. | |
2819 | */ | |
5321922c VM |
2820 | static void dwc2_gadget_handle_nak(struct dwc2_hsotg_ep *hs_ep) |
2821 | { | |
2822 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
2823 | int dir_in = hs_ep->dir_in; | |
2824 | ||
2825 | if (!dir_in || !hs_ep->isochronous) | |
2826 | return; | |
2827 | ||
2828 | if (hs_ep->target_frame == TARGET_FRAME_INITIAL) { | |
540ccba0 VA |
2829 | |
2830 | if (using_desc_dma(hsotg)) { | |
4d4f1e79 | 2831 | hs_ep->target_frame = hsotg->frame_number; |
729cac69 | 2832 | dwc2_gadget_incr_frame_num(hs_ep); |
540ccba0 VA |
2833 | dwc2_gadget_start_isoc_ddma(hs_ep); |
2834 | return; | |
2835 | } | |
2836 | ||
4d4f1e79 | 2837 | hs_ep->target_frame = hsotg->frame_number; |
5321922c | 2838 | if (hs_ep->interval > 1) { |
f25c42b8 | 2839 | u32 ctrl = dwc2_readl(hsotg, |
5321922c VM |
2840 | DIEPCTL(hs_ep->index)); |
2841 | if (hs_ep->target_frame & 0x1) | |
2842 | ctrl |= DXEPCTL_SETODDFR; | |
2843 | else | |
2844 | ctrl |= DXEPCTL_SETEVENFR; | |
2845 | ||
f25c42b8 | 2846 | dwc2_writel(hsotg, ctrl, DIEPCTL(hs_ep->index)); |
5321922c VM |
2847 | } |
2848 | ||
2849 | dwc2_hsotg_complete_request(hsotg, hs_ep, | |
2850 | get_ep_head(hs_ep), 0); | |
2851 | } | |
2852 | ||
729cac69 MH |
2853 | if (!using_desc_dma(hsotg)) |
2854 | dwc2_gadget_incr_frame_num(hs_ep); | |
5321922c VM |
2855 | } |
2856 | ||
5b7d70c6 | 2857 | /** |
1f91b4cc | 2858 | * dwc2_hsotg_epint - handle an in/out endpoint interrupt |
5b7d70c6 BD |
2859 | * @hsotg: The driver state |
2860 | * @idx: The index for the endpoint (0..15) | |
2861 | * @dir_in: Set if this is an IN endpoint | |
2862 | * | |
2863 | * Process and clear any interrupt pending for an individual endpoint | |
8b9bc460 | 2864 | */ |
1f91b4cc | 2865 | static void dwc2_hsotg_epint(struct dwc2_hsotg *hsotg, unsigned int idx, |
9da51974 | 2866 | int dir_in) |
5b7d70c6 | 2867 | { |
1f91b4cc | 2868 | struct dwc2_hsotg_ep *hs_ep = index_to_ep(hsotg, idx, dir_in); |
94cb8fd6 LM |
2869 | u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx); |
2870 | u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx); | |
2871 | u32 epsiz_reg = dir_in ? DIEPTSIZ(idx) : DOEPTSIZ(idx); | |
5b7d70c6 | 2872 | u32 ints; |
1479e841 | 2873 | u32 ctrl; |
5b7d70c6 | 2874 | |
32601588 | 2875 | ints = dwc2_gadget_read_ep_interrupts(hsotg, idx, dir_in); |
f25c42b8 | 2876 | ctrl = dwc2_readl(hsotg, epctl_reg); |
5b7d70c6 | 2877 | |
a3395f0d | 2878 | /* Clear endpoint interrupts */ |
f25c42b8 | 2879 | dwc2_writel(hsotg, ints, epint_reg); |
a3395f0d | 2880 | |
c6f5c050 MYK |
2881 | if (!hs_ep) { |
2882 | dev_err(hsotg->dev, "%s:Interrupt for unconfigured ep%d(%s)\n", | |
9da51974 | 2883 | __func__, idx, dir_in ? "in" : "out"); |
c6f5c050 MYK |
2884 | return; |
2885 | } | |
2886 | ||
5b7d70c6 BD |
2887 | dev_dbg(hsotg->dev, "%s: ep%d(%s) DxEPINT=0x%08x\n", |
2888 | __func__, idx, dir_in ? "in" : "out", ints); | |
2889 | ||
b787d755 MYK |
2890 | /* Don't process XferCompl interrupt if it is a setup packet */ |
2891 | if (idx == 0 && (ints & (DXEPINT_SETUP | DXEPINT_SETUP_RCVD))) | |
2892 | ints &= ~DXEPINT_XFERCOMPL; | |
2893 | ||
f0afdb42 VA |
2894 | /* |
2895 | * Don't process XferCompl interrupt in DDMA if EP0 is still in SETUP | |
2896 | * stage and xfercomplete was generated without SETUP phase done | |
2897 | * interrupt. SW should parse received setup packet only after host's | |
2898 | * exit from setup phase of control transfer. | |
2899 | */ | |
2900 | if (using_desc_dma(hsotg) && idx == 0 && !hs_ep->dir_in && | |
2901 | hsotg->ep0_state == DWC2_EP0_SETUP && !(ints & DXEPINT_SETUP)) | |
2902 | ints &= ~DXEPINT_XFERCOMPL; | |
2903 | ||
837e9f00 | 2904 | if (ints & DXEPINT_XFERCOMPL) { |
5b7d70c6 | 2905 | dev_dbg(hsotg->dev, |
47a1685f | 2906 | "%s: XferCompl: DxEPCTL=0x%08x, DXEPTSIZ=%08x\n", |
f25c42b8 GS |
2907 | __func__, dwc2_readl(hsotg, epctl_reg), |
2908 | dwc2_readl(hsotg, epsiz_reg)); | |
5b7d70c6 | 2909 | |
540ccba0 VA |
2910 | /* In DDMA handle isochronous requests separately */ |
2911 | if (using_desc_dma(hsotg) && hs_ep->isochronous) { | |
729cac69 MH |
2912 | /* XferCompl set along with BNA */ |
2913 | if (!(ints & DXEPINT_BNAINTR)) | |
2914 | dwc2_gadget_complete_isoc_request_ddma(hs_ep); | |
540ccba0 VA |
2915 | } else if (dir_in) { |
2916 | /* | |
2917 | * We get OutDone from the FIFO, so we only | |
2918 | * need to look at completing IN requests here | |
2919 | * if operating slave mode | |
2920 | */ | |
837e9f00 VM |
2921 | if (hs_ep->isochronous && hs_ep->interval > 1) |
2922 | dwc2_gadget_incr_frame_num(hs_ep); | |
2923 | ||
1f91b4cc | 2924 | dwc2_hsotg_complete_in(hsotg, hs_ep); |
837e9f00 VM |
2925 | if (ints & DXEPINT_NAKINTRPT) |
2926 | ints &= ~DXEPINT_NAKINTRPT; | |
5b7d70c6 | 2927 | |
c9a64ea8 | 2928 | if (idx == 0 && !hs_ep->req) |
1f91b4cc | 2929 | dwc2_hsotg_enqueue_setup(hsotg); |
5b7d70c6 | 2930 | } else if (using_dma(hsotg)) { |
8b9bc460 LM |
2931 | /* |
2932 | * We're using DMA, we need to fire an OutDone here | |
2933 | * as we ignore the RXFIFO. | |
2934 | */ | |
837e9f00 VM |
2935 | if (hs_ep->isochronous && hs_ep->interval > 1) |
2936 | dwc2_gadget_incr_frame_num(hs_ep); | |
5b7d70c6 | 2937 | |
1f91b4cc | 2938 | dwc2_hsotg_handle_outdone(hsotg, idx); |
5b7d70c6 | 2939 | } |
5b7d70c6 BD |
2940 | } |
2941 | ||
bd9971f0 VM |
2942 | if (ints & DXEPINT_EPDISBLD) |
2943 | dwc2_gadget_handle_ep_disabled(hs_ep); | |
9c39ddc6 | 2944 | |
5321922c VM |
2945 | if (ints & DXEPINT_OUTTKNEPDIS) |
2946 | dwc2_gadget_handle_out_token_ep_disabled(hs_ep); | |
2947 | ||
2948 | if (ints & DXEPINT_NAKINTRPT) | |
2949 | dwc2_gadget_handle_nak(hs_ep); | |
2950 | ||
47a1685f | 2951 | if (ints & DXEPINT_AHBERR) |
5b7d70c6 | 2952 | dev_dbg(hsotg->dev, "%s: AHBErr\n", __func__); |
5b7d70c6 | 2953 | |
47a1685f | 2954 | if (ints & DXEPINT_SETUP) { /* Setup or Timeout */ |
5b7d70c6 BD |
2955 | dev_dbg(hsotg->dev, "%s: Setup/Timeout\n", __func__); |
2956 | ||
2957 | if (using_dma(hsotg) && idx == 0) { | |
8b9bc460 LM |
2958 | /* |
2959 | * this is the notification we've received a | |
5b7d70c6 BD |
2960 | * setup packet. In non-DMA mode we'd get this |
2961 | * from the RXFIFO, instead we need to process | |
8b9bc460 LM |
2962 | * the setup here. |
2963 | */ | |
5b7d70c6 BD |
2964 | |
2965 | if (dir_in) | |
2966 | WARN_ON_ONCE(1); | |
2967 | else | |
1f91b4cc | 2968 | dwc2_hsotg_handle_outdone(hsotg, 0); |
5b7d70c6 | 2969 | } |
5b7d70c6 BD |
2970 | } |
2971 | ||
ef750c71 | 2972 | if (ints & DXEPINT_STSPHSERCVD) { |
9d9a6b07 VA |
2973 | dev_dbg(hsotg->dev, "%s: StsPhseRcvd\n", __func__); |
2974 | ||
9e95a66c MH |
2975 | /* Safety check EP0 state when STSPHSERCVD asserted */ |
2976 | if (hsotg->ep0_state == DWC2_EP0_DATA_OUT) { | |
2977 | /* Move to STATUS IN for DDMA */ | |
2978 | if (using_desc_dma(hsotg)) | |
2979 | dwc2_hsotg_ep0_zlp(hsotg, true); | |
2980 | } | |
2981 | ||
ef750c71 VA |
2982 | } |
2983 | ||
47a1685f | 2984 | if (ints & DXEPINT_BACK2BACKSETUP) |
5b7d70c6 | 2985 | dev_dbg(hsotg->dev, "%s: B2BSetup/INEPNakEff\n", __func__); |
5b7d70c6 | 2986 | |
540ccba0 VA |
2987 | if (ints & DXEPINT_BNAINTR) { |
2988 | dev_dbg(hsotg->dev, "%s: BNA interrupt\n", __func__); | |
540ccba0 | 2989 | if (hs_ep->isochronous) |
729cac69 | 2990 | dwc2_gadget_handle_isoc_bna(hs_ep); |
540ccba0 VA |
2991 | } |
2992 | ||
1479e841 | 2993 | if (dir_in && !hs_ep->isochronous) { |
8b9bc460 | 2994 | /* not sure if this is important, but we'll clear it anyway */ |
26ddef5d | 2995 | if (ints & DXEPINT_INTKNTXFEMP) { |
5b7d70c6 BD |
2996 | dev_dbg(hsotg->dev, "%s: ep%d: INTknTXFEmpMsk\n", |
2997 | __func__, idx); | |
5b7d70c6 BD |
2998 | } |
2999 | ||
3000 | /* this probably means something bad is happening */ | |
26ddef5d | 3001 | if (ints & DXEPINT_INTKNEPMIS) { |
5b7d70c6 BD |
3002 | dev_warn(hsotg->dev, "%s: ep%d: INTknEP\n", |
3003 | __func__, idx); | |
5b7d70c6 | 3004 | } |
10aebc77 BD |
3005 | |
3006 | /* FIFO has space or is empty (see GAHBCFG) */ | |
3007 | if (hsotg->dedicated_fifos && | |
26ddef5d | 3008 | ints & DXEPINT_TXFEMP) { |
10aebc77 BD |
3009 | dev_dbg(hsotg->dev, "%s: ep%d: TxFIFOEmpty\n", |
3010 | __func__, idx); | |
70fa030f | 3011 | if (!using_dma(hsotg)) |
1f91b4cc | 3012 | dwc2_hsotg_trytx(hsotg, hs_ep); |
10aebc77 | 3013 | } |
5b7d70c6 | 3014 | } |
5b7d70c6 BD |
3015 | } |
3016 | ||
3017 | /** | |
1f91b4cc | 3018 | * dwc2_hsotg_irq_enumdone - Handle EnumDone interrupt (enumeration done) |
5b7d70c6 BD |
3019 | * @hsotg: The device state. |
3020 | * | |
3021 | * Handle updating the device settings after the enumeration phase has | |
3022 | * been completed. | |
8b9bc460 | 3023 | */ |
1f91b4cc | 3024 | static void dwc2_hsotg_irq_enumdone(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 3025 | { |
f25c42b8 | 3026 | u32 dsts = dwc2_readl(hsotg, DSTS); |
9b2667f1 | 3027 | int ep0_mps = 0, ep_mps = 8; |
5b7d70c6 | 3028 | |
8b9bc460 LM |
3029 | /* |
3030 | * This should signal the finish of the enumeration phase | |
5b7d70c6 | 3031 | * of the USB handshaking, so we should now know what rate |
8b9bc460 LM |
3032 | * we connected at. |
3033 | */ | |
5b7d70c6 BD |
3034 | |
3035 | dev_dbg(hsotg->dev, "EnumDone (DSTS=0x%08x)\n", dsts); | |
3036 | ||
8b9bc460 LM |
3037 | /* |
3038 | * note, since we're limited by the size of transfer on EP0, and | |
5b7d70c6 | 3039 | * it seems IN transfers must be a even number of packets we do |
8b9bc460 LM |
3040 | * not advertise a 64byte MPS on EP0. |
3041 | */ | |
5b7d70c6 BD |
3042 | |
3043 | /* catch both EnumSpd_FS and EnumSpd_FS48 */ | |
6d76c92c | 3044 | switch ((dsts & DSTS_ENUMSPD_MASK) >> DSTS_ENUMSPD_SHIFT) { |
47a1685f DN |
3045 | case DSTS_ENUMSPD_FS: |
3046 | case DSTS_ENUMSPD_FS48: | |
5b7d70c6 | 3047 | hsotg->gadget.speed = USB_SPEED_FULL; |
5b7d70c6 | 3048 | ep0_mps = EP0_MPS_LIMIT; |
295538ff | 3049 | ep_mps = 1023; |
5b7d70c6 BD |
3050 | break; |
3051 | ||
47a1685f | 3052 | case DSTS_ENUMSPD_HS: |
5b7d70c6 | 3053 | hsotg->gadget.speed = USB_SPEED_HIGH; |
5b7d70c6 | 3054 | ep0_mps = EP0_MPS_LIMIT; |
295538ff | 3055 | ep_mps = 1024; |
5b7d70c6 BD |
3056 | break; |
3057 | ||
47a1685f | 3058 | case DSTS_ENUMSPD_LS: |
5b7d70c6 | 3059 | hsotg->gadget.speed = USB_SPEED_LOW; |
552d940f VM |
3060 | ep0_mps = 8; |
3061 | ep_mps = 8; | |
8b9bc460 LM |
3062 | /* |
3063 | * note, we don't actually support LS in this driver at the | |
5b7d70c6 BD |
3064 | * moment, and the documentation seems to imply that it isn't |
3065 | * supported by the PHYs on some of the devices. | |
3066 | */ | |
3067 | break; | |
3068 | } | |
e538dfda MN |
3069 | dev_info(hsotg->dev, "new device is %s\n", |
3070 | usb_speed_string(hsotg->gadget.speed)); | |
5b7d70c6 | 3071 | |
8b9bc460 LM |
3072 | /* |
3073 | * we should now know the maximum packet size for an | |
3074 | * endpoint, so set the endpoints to a default value. | |
3075 | */ | |
5b7d70c6 BD |
3076 | |
3077 | if (ep0_mps) { | |
3078 | int i; | |
c6f5c050 | 3079 | /* Initialize ep0 for both in and out directions */ |
ee2c40de VM |
3080 | dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 0, 1); |
3081 | dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 0, 0); | |
c6f5c050 MYK |
3082 | for (i = 1; i < hsotg->num_of_eps; i++) { |
3083 | if (hsotg->eps_in[i]) | |
ee2c40de VM |
3084 | dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps, |
3085 | 0, 1); | |
c6f5c050 | 3086 | if (hsotg->eps_out[i]) |
ee2c40de VM |
3087 | dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps, |
3088 | 0, 0); | |
c6f5c050 | 3089 | } |
5b7d70c6 BD |
3090 | } |
3091 | ||
3092 | /* ensure after enumeration our EP0 is active */ | |
3093 | ||
1f91b4cc | 3094 | dwc2_hsotg_enqueue_setup(hsotg); |
5b7d70c6 BD |
3095 | |
3096 | dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n", | |
f25c42b8 GS |
3097 | dwc2_readl(hsotg, DIEPCTL0), |
3098 | dwc2_readl(hsotg, DOEPCTL0)); | |
5b7d70c6 BD |
3099 | } |
3100 | ||
3101 | /** | |
3102 | * kill_all_requests - remove all requests from the endpoint's queue | |
3103 | * @hsotg: The device state. | |
3104 | * @ep: The endpoint the requests may be on. | |
3105 | * @result: The result code to use. | |
5b7d70c6 BD |
3106 | * |
3107 | * Go through the requests on the given endpoint and mark them | |
3108 | * completed with the given result code. | |
3109 | */ | |
941fcce4 | 3110 | static void kill_all_requests(struct dwc2_hsotg *hsotg, |
1f91b4cc | 3111 | struct dwc2_hsotg_ep *ep, |
6b448af4 | 3112 | int result) |
5b7d70c6 | 3113 | { |
1f91b4cc | 3114 | struct dwc2_hsotg_req *req, *treq; |
9da51974 | 3115 | unsigned int size; |
5b7d70c6 | 3116 | |
6b448af4 | 3117 | ep->req = NULL; |
5b7d70c6 | 3118 | |
6b448af4 | 3119 | list_for_each_entry_safe(req, treq, &ep->queue, queue) |
1f91b4cc | 3120 | dwc2_hsotg_complete_request(hsotg, ep, req, |
9da51974 | 3121 | result); |
6b448af4 | 3122 | |
b203d0a2 RB |
3123 | if (!hsotg->dedicated_fifos) |
3124 | return; | |
f25c42b8 | 3125 | size = (dwc2_readl(hsotg, DTXFSTS(ep->fifo_index)) & 0xffff) * 4; |
b203d0a2 | 3126 | if (size < ep->fifo_size) |
1f91b4cc | 3127 | dwc2_hsotg_txfifo_flush(hsotg, ep->fifo_index); |
5b7d70c6 BD |
3128 | } |
3129 | ||
dccf1bad MH |
3130 | static int dwc2_hsotg_ep_disable(struct usb_ep *ep); |
3131 | ||
5b7d70c6 | 3132 | /** |
1f91b4cc | 3133 | * dwc2_hsotg_disconnect - disconnect service |
5b7d70c6 BD |
3134 | * @hsotg: The device state. |
3135 | * | |
5e891342 LM |
3136 | * The device has been disconnected. Remove all current |
3137 | * transactions and signal the gadget driver that this | |
3138 | * has happened. | |
8b9bc460 | 3139 | */ |
1f91b4cc | 3140 | void dwc2_hsotg_disconnect(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 3141 | { |
9da51974 | 3142 | unsigned int ep; |
5b7d70c6 | 3143 | |
4ace06e8 MS |
3144 | if (!hsotg->connected) |
3145 | return; | |
3146 | ||
3147 | hsotg->connected = 0; | |
9e14d0a5 | 3148 | hsotg->test_mode = 0; |
c6f5c050 | 3149 | |
dccf1bad | 3150 | /* all endpoints should be shutdown */ |
c6f5c050 MYK |
3151 | for (ep = 0; ep < hsotg->num_of_eps; ep++) { |
3152 | if (hsotg->eps_in[ep]) | |
dccf1bad | 3153 | dwc2_hsotg_ep_disable(&hsotg->eps_in[ep]->ep); |
c6f5c050 | 3154 | if (hsotg->eps_out[ep]) |
dccf1bad | 3155 | dwc2_hsotg_ep_disable(&hsotg->eps_out[ep]->ep); |
c6f5c050 | 3156 | } |
5b7d70c6 BD |
3157 | |
3158 | call_gadget(hsotg, disconnect); | |
065d3931 | 3159 | hsotg->lx_state = DWC2_L3; |
ce2b21a4 JS |
3160 | |
3161 | usb_gadget_set_state(&hsotg->gadget, USB_STATE_NOTATTACHED); | |
5b7d70c6 BD |
3162 | } |
3163 | ||
3164 | /** | |
1f91b4cc | 3165 | * dwc2_hsotg_irq_fifoempty - TX FIFO empty interrupt handler |
5b7d70c6 BD |
3166 | * @hsotg: The device state: |
3167 | * @periodic: True if this is a periodic FIFO interrupt | |
3168 | */ | |
1f91b4cc | 3169 | static void dwc2_hsotg_irq_fifoempty(struct dwc2_hsotg *hsotg, bool periodic) |
5b7d70c6 | 3170 | { |
1f91b4cc | 3171 | struct dwc2_hsotg_ep *ep; |
5b7d70c6 BD |
3172 | int epno, ret; |
3173 | ||
3174 | /* look through for any more data to transmit */ | |
b3f489b2 | 3175 | for (epno = 0; epno < hsotg->num_of_eps; epno++) { |
c6f5c050 MYK |
3176 | ep = index_to_ep(hsotg, epno, 1); |
3177 | ||
3178 | if (!ep) | |
3179 | continue; | |
5b7d70c6 BD |
3180 | |
3181 | if (!ep->dir_in) | |
3182 | continue; | |
3183 | ||
3184 | if ((periodic && !ep->periodic) || | |
3185 | (!periodic && ep->periodic)) | |
3186 | continue; | |
3187 | ||
1f91b4cc | 3188 | ret = dwc2_hsotg_trytx(hsotg, ep); |
5b7d70c6 BD |
3189 | if (ret < 0) |
3190 | break; | |
3191 | } | |
3192 | } | |
3193 | ||
5b7d70c6 | 3194 | /* IRQ flags which will trigger a retry around the IRQ loop */ |
47a1685f DN |
3195 | #define IRQ_RETRY_MASK (GINTSTS_NPTXFEMP | \ |
3196 | GINTSTS_PTXFEMP | \ | |
3197 | GINTSTS_RXFLVL) | |
5b7d70c6 | 3198 | |
8b9bc460 | 3199 | /** |
1f91b4cc | 3200 | * dwc2_hsotg_core_init - issue softreset to the core |
8b9bc460 | 3201 | * @hsotg: The device state |
6fb914d7 | 3202 | * @is_usb_reset: Usb resetting flag |
8b9bc460 LM |
3203 | * |
3204 | * Issue a soft reset to the core, and await the core finishing it. | |
3205 | */ | |
1f91b4cc | 3206 | void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg, |
9da51974 | 3207 | bool is_usb_reset) |
308d734e | 3208 | { |
1ee6903b | 3209 | u32 intmsk; |
643cc4de | 3210 | u32 val; |
ecd9a7ad | 3211 | u32 usbcfg; |
79c3b5bb | 3212 | u32 dcfg = 0; |
dccf1bad | 3213 | int ep; |
643cc4de | 3214 | |
5390d438 MYK |
3215 | /* Kill any ep0 requests as controller will be reinitialized */ |
3216 | kill_all_requests(hsotg, hsotg->eps_out[0], -ECONNRESET); | |
3217 | ||
dccf1bad | 3218 | if (!is_usb_reset) { |
6e6360b6 | 3219 | if (dwc2_core_reset(hsotg, true)) |
86de4895 | 3220 | return; |
dccf1bad MH |
3221 | } else { |
3222 | /* all endpoints should be shutdown */ | |
3223 | for (ep = 1; ep < hsotg->num_of_eps; ep++) { | |
3224 | if (hsotg->eps_in[ep]) | |
3225 | dwc2_hsotg_ep_disable(&hsotg->eps_in[ep]->ep); | |
3226 | if (hsotg->eps_out[ep]) | |
3227 | dwc2_hsotg_ep_disable(&hsotg->eps_out[ep]->ep); | |
3228 | } | |
3229 | } | |
308d734e LM |
3230 | |
3231 | /* | |
3232 | * we must now enable ep0 ready for host detection and then | |
3233 | * set configuration. | |
3234 | */ | |
3235 | ||
ecd9a7ad | 3236 | /* keep other bits untouched (so e.g. forced modes are not lost) */ |
f25c42b8 | 3237 | usbcfg = dwc2_readl(hsotg, GUSBCFG); |
ecd9a7ad | 3238 | usbcfg &= ~(GUSBCFG_TOUTCAL_MASK | GUSBCFG_PHYIF16 | GUSBCFG_SRPCAP | |
ca02954a | 3239 | GUSBCFG_HNPCAP | GUSBCFG_USBTRDTIM_MASK); |
ecd9a7ad | 3240 | |
79c3b5bb | 3241 | if (hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS && |
38e9002b VM |
3242 | (hsotg->params.speed == DWC2_SPEED_PARAM_FULL || |
3243 | hsotg->params.speed == DWC2_SPEED_PARAM_LOW)) { | |
79c3b5bb VA |
3244 | /* FS/LS Dedicated Transceiver Interface */ |
3245 | usbcfg |= GUSBCFG_PHYSEL; | |
3246 | } else { | |
3247 | /* set the PLL on, remove the HNP/SRP and set the PHY */ | |
3248 | val = (hsotg->phyif == GUSBCFG_PHYIF8) ? 9 : 5; | |
3249 | usbcfg |= hsotg->phyif | GUSBCFG_TOUTCAL(7) | | |
3250 | (val << GUSBCFG_USBTRDTIM_SHIFT); | |
3251 | } | |
f25c42b8 | 3252 | dwc2_writel(hsotg, usbcfg, GUSBCFG); |
308d734e | 3253 | |
1f91b4cc | 3254 | dwc2_hsotg_init_fifo(hsotg); |
308d734e | 3255 | |
643cc4de | 3256 | if (!is_usb_reset) |
f25c42b8 | 3257 | dwc2_set_bit(hsotg, DCTL, DCTL_SFTDISCON); |
308d734e | 3258 | |
79c3b5bb | 3259 | dcfg |= DCFG_EPMISCNT(1); |
38e9002b VM |
3260 | |
3261 | switch (hsotg->params.speed) { | |
3262 | case DWC2_SPEED_PARAM_LOW: | |
3263 | dcfg |= DCFG_DEVSPD_LS; | |
3264 | break; | |
3265 | case DWC2_SPEED_PARAM_FULL: | |
79c3b5bb VA |
3266 | if (hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS) |
3267 | dcfg |= DCFG_DEVSPD_FS48; | |
3268 | else | |
3269 | dcfg |= DCFG_DEVSPD_FS; | |
38e9002b VM |
3270 | break; |
3271 | default: | |
79c3b5bb VA |
3272 | dcfg |= DCFG_DEVSPD_HS; |
3273 | } | |
38e9002b | 3274 | |
b43ebc96 GT |
3275 | if (hsotg->params.ipg_isoc_en) |
3276 | dcfg |= DCFG_IPG_ISOC_SUPPORDED; | |
3277 | ||
f25c42b8 | 3278 | dwc2_writel(hsotg, dcfg, DCFG); |
308d734e LM |
3279 | |
3280 | /* Clear any pending OTG interrupts */ | |
f25c42b8 | 3281 | dwc2_writel(hsotg, 0xffffffff, GOTGINT); |
308d734e LM |
3282 | |
3283 | /* Clear any pending interrupts */ | |
f25c42b8 | 3284 | dwc2_writel(hsotg, 0xffffffff, GINTSTS); |
1ee6903b | 3285 | intmsk = GINTSTS_ERLYSUSP | GINTSTS_SESSREQINT | |
47a1685f | 3286 | GINTSTS_GOUTNAKEFF | GINTSTS_GINNAKEFF | |
1ee6903b GH |
3287 | GINTSTS_USBRST | GINTSTS_RESETDET | |
3288 | GINTSTS_ENUMDONE | GINTSTS_OTGINT | | |
376f0401 SA |
3289 | GINTSTS_USBSUSP | GINTSTS_WKUPINT | |
3290 | GINTSTS_LPMTRANRCVD; | |
f4736701 VA |
3291 | |
3292 | if (!using_desc_dma(hsotg)) | |
3293 | intmsk |= GINTSTS_INCOMPL_SOIN | GINTSTS_INCOMPL_SOOUT; | |
1ee6903b | 3294 | |
95832c00 | 3295 | if (!hsotg->params.external_id_pin_ctl) |
1ee6903b GH |
3296 | intmsk |= GINTSTS_CONIDSTSCHNG; |
3297 | ||
f25c42b8 | 3298 | dwc2_writel(hsotg, intmsk, GINTMSK); |
308d734e | 3299 | |
a5c18f11 | 3300 | if (using_dma(hsotg)) { |
f25c42b8 | 3301 | dwc2_writel(hsotg, GAHBCFG_GLBL_INTR_EN | GAHBCFG_DMA_EN | |
d1ac8c80 | 3302 | hsotg->params.ahbcfg, |
f25c42b8 | 3303 | GAHBCFG); |
a5c18f11 VA |
3304 | |
3305 | /* Set DDMA mode support in the core if needed */ | |
3306 | if (using_desc_dma(hsotg)) | |
f25c42b8 | 3307 | dwc2_set_bit(hsotg, DCFG, DCFG_DESCDMA_EN); |
a5c18f11 VA |
3308 | |
3309 | } else { | |
f25c42b8 | 3310 | dwc2_writel(hsotg, ((hsotg->dedicated_fifos) ? |
95c8bc36 AS |
3311 | (GAHBCFG_NP_TXF_EMP_LVL | |
3312 | GAHBCFG_P_TXF_EMP_LVL) : 0) | | |
f25c42b8 | 3313 | GAHBCFG_GLBL_INTR_EN, GAHBCFG); |
a5c18f11 | 3314 | } |
308d734e LM |
3315 | |
3316 | /* | |
8acc8296 RB |
3317 | * If INTknTXFEmpMsk is enabled, it's important to disable ep interrupts |
3318 | * when we have no data to transfer. Otherwise we get being flooded by | |
3319 | * interrupts. | |
308d734e LM |
3320 | */ |
3321 | ||
f25c42b8 | 3322 | dwc2_writel(hsotg, ((hsotg->dedicated_fifos && !using_dma(hsotg)) ? |
6ff2e832 | 3323 | DIEPMSK_TXFIFOEMPTY | DIEPMSK_INTKNTXFEMPMSK : 0) | |
47a1685f | 3324 | DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK | |
837e9f00 | 3325 | DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK, |
f25c42b8 | 3326 | DIEPMSK); |
308d734e LM |
3327 | |
3328 | /* | |
3329 | * don't need XferCompl, we get that from RXFIFO in slave mode. In | |
9d9a6b07 | 3330 | * DMA mode we may need this and StsPhseRcvd. |
308d734e | 3331 | */ |
f25c42b8 | 3332 | dwc2_writel(hsotg, (using_dma(hsotg) ? (DIEPMSK_XFERCOMPLMSK | |
9d9a6b07 | 3333 | DOEPMSK_STSPHSERCVDMSK) : 0) | |
47a1685f | 3334 | DOEPMSK_EPDISBLDMSK | DOEPMSK_AHBERRMSK | |
9d9a6b07 | 3335 | DOEPMSK_SETUPMSK, |
f25c42b8 | 3336 | DOEPMSK); |
308d734e | 3337 | |
ec01f0b2 | 3338 | /* Enable BNA interrupt for DDMA */ |
37981e00 | 3339 | if (using_desc_dma(hsotg)) { |
f25c42b8 GS |
3340 | dwc2_set_bit(hsotg, DOEPMSK, DOEPMSK_BNAMSK); |
3341 | dwc2_set_bit(hsotg, DIEPMSK, DIEPMSK_BNAININTRMSK); | |
37981e00 | 3342 | } |
ec01f0b2 | 3343 | |
ca531bc2 GT |
3344 | /* Enable Service Interval mode if supported */ |
3345 | if (using_desc_dma(hsotg) && hsotg->params.service_interval) | |
3346 | dwc2_set_bit(hsotg, DCTL, DCTL_SERVICE_INTERVAL_SUPPORTED); | |
3347 | ||
f25c42b8 | 3348 | dwc2_writel(hsotg, 0, DAINTMSK); |
308d734e LM |
3349 | |
3350 | dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n", | |
f25c42b8 GS |
3351 | dwc2_readl(hsotg, DIEPCTL0), |
3352 | dwc2_readl(hsotg, DOEPCTL0)); | |
308d734e LM |
3353 | |
3354 | /* enable in and out endpoint interrupts */ | |
1f91b4cc | 3355 | dwc2_hsotg_en_gsint(hsotg, GINTSTS_OEPINT | GINTSTS_IEPINT); |
308d734e LM |
3356 | |
3357 | /* | |
3358 | * Enable the RXFIFO when in slave mode, as this is how we collect | |
3359 | * the data. In DMA mode, we get events from the FIFO but also | |
3360 | * things we cannot process, so do not use it. | |
3361 | */ | |
3362 | if (!using_dma(hsotg)) | |
1f91b4cc | 3363 | dwc2_hsotg_en_gsint(hsotg, GINTSTS_RXFLVL); |
308d734e LM |
3364 | |
3365 | /* Enable interrupts for EP0 in and out */ | |
1f91b4cc FB |
3366 | dwc2_hsotg_ctrl_epint(hsotg, 0, 0, 1); |
3367 | dwc2_hsotg_ctrl_epint(hsotg, 0, 1, 1); | |
308d734e | 3368 | |
643cc4de | 3369 | if (!is_usb_reset) { |
f25c42b8 | 3370 | dwc2_set_bit(hsotg, DCTL, DCTL_PWRONPRGDONE); |
643cc4de | 3371 | udelay(10); /* see openiboot */ |
f25c42b8 | 3372 | dwc2_clear_bit(hsotg, DCTL, DCTL_PWRONPRGDONE); |
643cc4de | 3373 | } |
308d734e | 3374 | |
f25c42b8 | 3375 | dev_dbg(hsotg->dev, "DCTL=0x%08x\n", dwc2_readl(hsotg, DCTL)); |
308d734e LM |
3376 | |
3377 | /* | |
94cb8fd6 | 3378 | * DxEPCTL_USBActEp says RO in manual, but seems to be set by |
308d734e LM |
3379 | * writing to the EPCTL register.. |
3380 | */ | |
3381 | ||
3382 | /* set to read 1 8byte packet */ | |
f25c42b8 GS |
3383 | dwc2_writel(hsotg, DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) | |
3384 | DXEPTSIZ_XFERSIZE(8), DOEPTSIZ0); | |
308d734e | 3385 | |
f25c42b8 | 3386 | dwc2_writel(hsotg, dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) | |
47a1685f DN |
3387 | DXEPCTL_CNAK | DXEPCTL_EPENA | |
3388 | DXEPCTL_USBACTEP, | |
f25c42b8 | 3389 | DOEPCTL0); |
308d734e LM |
3390 | |
3391 | /* enable, but don't activate EP0in */ | |
f25c42b8 GS |
3392 | dwc2_writel(hsotg, dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) | |
3393 | DXEPCTL_USBACTEP, DIEPCTL0); | |
308d734e | 3394 | |
308d734e | 3395 | /* clear global NAKs */ |
643cc4de GH |
3396 | val = DCTL_CGOUTNAK | DCTL_CGNPINNAK; |
3397 | if (!is_usb_reset) | |
3398 | val |= DCTL_SFTDISCON; | |
f25c42b8 | 3399 | dwc2_set_bit(hsotg, DCTL, val); |
308d734e | 3400 | |
21b03405 SA |
3401 | /* configure the core to support LPM */ |
3402 | dwc2_gadget_init_lpm(hsotg); | |
3403 | ||
308d734e LM |
3404 | /* must be at-least 3ms to allow bus to see disconnect */ |
3405 | mdelay(3); | |
3406 | ||
065d3931 | 3407 | hsotg->lx_state = DWC2_L0; |
755d7395 VM |
3408 | |
3409 | dwc2_hsotg_enqueue_setup(hsotg); | |
3410 | ||
3411 | dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n", | |
f25c42b8 GS |
3412 | dwc2_readl(hsotg, DIEPCTL0), |
3413 | dwc2_readl(hsotg, DOEPCTL0)); | |
ad38dc5d MS |
3414 | } |
3415 | ||
1f91b4cc | 3416 | static void dwc2_hsotg_core_disconnect(struct dwc2_hsotg *hsotg) |
ad38dc5d MS |
3417 | { |
3418 | /* set the soft-disconnect bit */ | |
f25c42b8 | 3419 | dwc2_set_bit(hsotg, DCTL, DCTL_SFTDISCON); |
ad38dc5d | 3420 | } |
ac3c81f3 | 3421 | |
1f91b4cc | 3422 | void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg) |
ad38dc5d | 3423 | { |
308d734e | 3424 | /* remove the soft-disconnect and let's go */ |
f25c42b8 | 3425 | dwc2_clear_bit(hsotg, DCTL, DCTL_SFTDISCON); |
308d734e LM |
3426 | } |
3427 | ||
381fc8f8 VM |
3428 | /** |
3429 | * dwc2_gadget_handle_incomplete_isoc_in - handle incomplete ISO IN Interrupt. | |
3430 | * @hsotg: The device state: | |
3431 | * | |
3432 | * This interrupt indicates one of the following conditions occurred while | |
3433 | * transmitting an ISOC transaction. | |
3434 | * - Corrupted IN Token for ISOC EP. | |
3435 | * - Packet not complete in FIFO. | |
3436 | * | |
3437 | * The following actions will be taken: | |
3438 | * - Determine the EP | |
3439 | * - Disable EP; when 'Endpoint Disabled' interrupt is received Flush FIFO | |
3440 | */ | |
3441 | static void dwc2_gadget_handle_incomplete_isoc_in(struct dwc2_hsotg *hsotg) | |
3442 | { | |
3443 | struct dwc2_hsotg_ep *hs_ep; | |
3444 | u32 epctrl; | |
1b4977c7 | 3445 | u32 daintmsk; |
381fc8f8 VM |
3446 | u32 idx; |
3447 | ||
3448 | dev_dbg(hsotg->dev, "Incomplete isoc in interrupt received:\n"); | |
3449 | ||
f25c42b8 | 3450 | daintmsk = dwc2_readl(hsotg, DAINTMSK); |
1b4977c7 | 3451 | |
d5d5f079 | 3452 | for (idx = 1; idx < hsotg->num_of_eps; idx++) { |
381fc8f8 | 3453 | hs_ep = hsotg->eps_in[idx]; |
1b4977c7 | 3454 | /* Proceed only unmasked ISOC EPs */ |
89066b36 | 3455 | if ((BIT(idx) & ~daintmsk) || !hs_ep->isochronous) |
1b4977c7 RK |
3456 | continue; |
3457 | ||
f25c42b8 | 3458 | epctrl = dwc2_readl(hsotg, DIEPCTL(idx)); |
1b4977c7 | 3459 | if ((epctrl & DXEPCTL_EPENA) && |
381fc8f8 VM |
3460 | dwc2_gadget_target_frame_elapsed(hs_ep)) { |
3461 | epctrl |= DXEPCTL_SNAK; | |
3462 | epctrl |= DXEPCTL_EPDIS; | |
f25c42b8 | 3463 | dwc2_writel(hsotg, epctrl, DIEPCTL(idx)); |
381fc8f8 VM |
3464 | } |
3465 | } | |
3466 | ||
3467 | /* Clear interrupt */ | |
f25c42b8 | 3468 | dwc2_writel(hsotg, GINTSTS_INCOMPL_SOIN, GINTSTS); |
381fc8f8 VM |
3469 | } |
3470 | ||
3471 | /** | |
3472 | * dwc2_gadget_handle_incomplete_isoc_out - handle incomplete ISO OUT Interrupt | |
3473 | * @hsotg: The device state: | |
3474 | * | |
3475 | * This interrupt indicates one of the following conditions occurred while | |
3476 | * transmitting an ISOC transaction. | |
3477 | * - Corrupted OUT Token for ISOC EP. | |
3478 | * - Packet not complete in FIFO. | |
3479 | * | |
3480 | * The following actions will be taken: | |
3481 | * - Determine the EP | |
3482 | * - Set DCTL_SGOUTNAK and unmask GOUTNAKEFF if target frame elapsed. | |
3483 | */ | |
3484 | static void dwc2_gadget_handle_incomplete_isoc_out(struct dwc2_hsotg *hsotg) | |
3485 | { | |
3486 | u32 gintsts; | |
3487 | u32 gintmsk; | |
689efb26 | 3488 | u32 daintmsk; |
381fc8f8 VM |
3489 | u32 epctrl; |
3490 | struct dwc2_hsotg_ep *hs_ep; | |
3491 | int idx; | |
3492 | ||
3493 | dev_dbg(hsotg->dev, "%s: GINTSTS_INCOMPL_SOOUT\n", __func__); | |
3494 | ||
f25c42b8 | 3495 | daintmsk = dwc2_readl(hsotg, DAINTMSK); |
689efb26 RK |
3496 | daintmsk >>= DAINT_OUTEP_SHIFT; |
3497 | ||
d5d5f079 | 3498 | for (idx = 1; idx < hsotg->num_of_eps; idx++) { |
381fc8f8 | 3499 | hs_ep = hsotg->eps_out[idx]; |
689efb26 | 3500 | /* Proceed only unmasked ISOC EPs */ |
89066b36 | 3501 | if ((BIT(idx) & ~daintmsk) || !hs_ep->isochronous) |
689efb26 RK |
3502 | continue; |
3503 | ||
f25c42b8 | 3504 | epctrl = dwc2_readl(hsotg, DOEPCTL(idx)); |
689efb26 | 3505 | if ((epctrl & DXEPCTL_EPENA) && |
381fc8f8 VM |
3506 | dwc2_gadget_target_frame_elapsed(hs_ep)) { |
3507 | /* Unmask GOUTNAKEFF interrupt */ | |
f25c42b8 | 3508 | gintmsk = dwc2_readl(hsotg, GINTMSK); |
381fc8f8 | 3509 | gintmsk |= GINTSTS_GOUTNAKEFF; |
f25c42b8 | 3510 | dwc2_writel(hsotg, gintmsk, GINTMSK); |
381fc8f8 | 3511 | |
f25c42b8 | 3512 | gintsts = dwc2_readl(hsotg, GINTSTS); |
689efb26 | 3513 | if (!(gintsts & GINTSTS_GOUTNAKEFF)) { |
f25c42b8 | 3514 | dwc2_set_bit(hsotg, DCTL, DCTL_SGOUTNAK); |
689efb26 RK |
3515 | break; |
3516 | } | |
381fc8f8 VM |
3517 | } |
3518 | } | |
3519 | ||
3520 | /* Clear interrupt */ | |
f25c42b8 | 3521 | dwc2_writel(hsotg, GINTSTS_INCOMPL_SOOUT, GINTSTS); |
381fc8f8 VM |
3522 | } |
3523 | ||
5b7d70c6 | 3524 | /** |
1f91b4cc | 3525 | * dwc2_hsotg_irq - handle device interrupt |
5b7d70c6 BD |
3526 | * @irq: The IRQ number triggered |
3527 | * @pw: The pw value when registered the handler. | |
3528 | */ | |
1f91b4cc | 3529 | static irqreturn_t dwc2_hsotg_irq(int irq, void *pw) |
5b7d70c6 | 3530 | { |
941fcce4 | 3531 | struct dwc2_hsotg *hsotg = pw; |
5b7d70c6 BD |
3532 | int retry_count = 8; |
3533 | u32 gintsts; | |
3534 | u32 gintmsk; | |
3535 | ||
ee3de8d7 VM |
3536 | if (!dwc2_is_device_mode(hsotg)) |
3537 | return IRQ_NONE; | |
3538 | ||
5ad1d316 | 3539 | spin_lock(&hsotg->lock); |
5b7d70c6 | 3540 | irq_retry: |
f25c42b8 GS |
3541 | gintsts = dwc2_readl(hsotg, GINTSTS); |
3542 | gintmsk = dwc2_readl(hsotg, GINTMSK); | |
5b7d70c6 BD |
3543 | |
3544 | dev_dbg(hsotg->dev, "%s: %08x %08x (%08x) retry %d\n", | |
3545 | __func__, gintsts, gintsts & gintmsk, gintmsk, retry_count); | |
3546 | ||
3547 | gintsts &= gintmsk; | |
3548 | ||
8fc37b82 MYK |
3549 | if (gintsts & GINTSTS_RESETDET) { |
3550 | dev_dbg(hsotg->dev, "%s: USBRstDet\n", __func__); | |
3551 | ||
f25c42b8 | 3552 | dwc2_writel(hsotg, GINTSTS_RESETDET, GINTSTS); |
8fc37b82 MYK |
3553 | |
3554 | /* This event must be used only if controller is suspended */ | |
3555 | if (hsotg->lx_state == DWC2_L2) { | |
41ba9b9b | 3556 | dwc2_exit_partial_power_down(hsotg, true); |
8fc37b82 MYK |
3557 | hsotg->lx_state = DWC2_L0; |
3558 | } | |
3559 | } | |
3560 | ||
3561 | if (gintsts & (GINTSTS_USBRST | GINTSTS_RESETDET)) { | |
f25c42b8 | 3562 | u32 usb_status = dwc2_readl(hsotg, GOTGCTL); |
8fc37b82 MYK |
3563 | u32 connected = hsotg->connected; |
3564 | ||
3565 | dev_dbg(hsotg->dev, "%s: USBRst\n", __func__); | |
3566 | dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n", | |
f25c42b8 | 3567 | dwc2_readl(hsotg, GNPTXSTS)); |
8fc37b82 | 3568 | |
f25c42b8 | 3569 | dwc2_writel(hsotg, GINTSTS_USBRST, GINTSTS); |
8fc37b82 MYK |
3570 | |
3571 | /* Report disconnection if it is not already done. */ | |
3572 | dwc2_hsotg_disconnect(hsotg); | |
3573 | ||
307bc11f | 3574 | /* Reset device address to zero */ |
f25c42b8 | 3575 | dwc2_clear_bit(hsotg, DCFG, DCFG_DEVADDR_MASK); |
307bc11f | 3576 | |
8fc37b82 MYK |
3577 | if (usb_status & GOTGCTL_BSESVLD && connected) |
3578 | dwc2_hsotg_core_init_disconnected(hsotg, true); | |
3579 | } | |
3580 | ||
47a1685f | 3581 | if (gintsts & GINTSTS_ENUMDONE) { |
f25c42b8 | 3582 | dwc2_writel(hsotg, GINTSTS_ENUMDONE, GINTSTS); |
a3395f0d | 3583 | |
1f91b4cc | 3584 | dwc2_hsotg_irq_enumdone(hsotg); |
5b7d70c6 BD |
3585 | } |
3586 | ||
47a1685f | 3587 | if (gintsts & (GINTSTS_OEPINT | GINTSTS_IEPINT)) { |
f25c42b8 GS |
3588 | u32 daint = dwc2_readl(hsotg, DAINT); |
3589 | u32 daintmsk = dwc2_readl(hsotg, DAINTMSK); | |
7e804650 | 3590 | u32 daint_out, daint_in; |
5b7d70c6 BD |
3591 | int ep; |
3592 | ||
7e804650 | 3593 | daint &= daintmsk; |
47a1685f DN |
3594 | daint_out = daint >> DAINT_OUTEP_SHIFT; |
3595 | daint_in = daint & ~(daint_out << DAINT_OUTEP_SHIFT); | |
7e804650 | 3596 | |
5b7d70c6 BD |
3597 | dev_dbg(hsotg->dev, "%s: daint=%08x\n", __func__, daint); |
3598 | ||
cec87f1d MYK |
3599 | for (ep = 0; ep < hsotg->num_of_eps && daint_out; |
3600 | ep++, daint_out >>= 1) { | |
5b7d70c6 | 3601 | if (daint_out & 1) |
1f91b4cc | 3602 | dwc2_hsotg_epint(hsotg, ep, 0); |
5b7d70c6 BD |
3603 | } |
3604 | ||
cec87f1d MYK |
3605 | for (ep = 0; ep < hsotg->num_of_eps && daint_in; |
3606 | ep++, daint_in >>= 1) { | |
5b7d70c6 | 3607 | if (daint_in & 1) |
1f91b4cc | 3608 | dwc2_hsotg_epint(hsotg, ep, 1); |
5b7d70c6 | 3609 | } |
5b7d70c6 BD |
3610 | } |
3611 | ||
5b7d70c6 BD |
3612 | /* check both FIFOs */ |
3613 | ||
47a1685f | 3614 | if (gintsts & GINTSTS_NPTXFEMP) { |
5b7d70c6 BD |
3615 | dev_dbg(hsotg->dev, "NPTxFEmp\n"); |
3616 | ||
8b9bc460 LM |
3617 | /* |
3618 | * Disable the interrupt to stop it happening again | |
5b7d70c6 | 3619 | * unless one of these endpoint routines decides that |
8b9bc460 LM |
3620 | * it needs re-enabling |
3621 | */ | |
5b7d70c6 | 3622 | |
1f91b4cc FB |
3623 | dwc2_hsotg_disable_gsint(hsotg, GINTSTS_NPTXFEMP); |
3624 | dwc2_hsotg_irq_fifoempty(hsotg, false); | |
5b7d70c6 BD |
3625 | } |
3626 | ||
47a1685f | 3627 | if (gintsts & GINTSTS_PTXFEMP) { |
5b7d70c6 BD |
3628 | dev_dbg(hsotg->dev, "PTxFEmp\n"); |
3629 | ||
94cb8fd6 | 3630 | /* See note in GINTSTS_NPTxFEmp */ |
5b7d70c6 | 3631 | |
1f91b4cc FB |
3632 | dwc2_hsotg_disable_gsint(hsotg, GINTSTS_PTXFEMP); |
3633 | dwc2_hsotg_irq_fifoempty(hsotg, true); | |
5b7d70c6 BD |
3634 | } |
3635 | ||
47a1685f | 3636 | if (gintsts & GINTSTS_RXFLVL) { |
8b9bc460 LM |
3637 | /* |
3638 | * note, since GINTSTS_RxFLvl doubles as FIFO-not-empty, | |
1f91b4cc | 3639 | * we need to retry dwc2_hsotg_handle_rx if this is still |
8b9bc460 LM |
3640 | * set. |
3641 | */ | |
5b7d70c6 | 3642 | |
1f91b4cc | 3643 | dwc2_hsotg_handle_rx(hsotg); |
5b7d70c6 BD |
3644 | } |
3645 | ||
47a1685f | 3646 | if (gintsts & GINTSTS_ERLYSUSP) { |
94cb8fd6 | 3647 | dev_dbg(hsotg->dev, "GINTSTS_ErlySusp\n"); |
f25c42b8 | 3648 | dwc2_writel(hsotg, GINTSTS_ERLYSUSP, GINTSTS); |
5b7d70c6 BD |
3649 | } |
3650 | ||
8b9bc460 LM |
3651 | /* |
3652 | * these next two seem to crop-up occasionally causing the core | |
5b7d70c6 | 3653 | * to shutdown the USB transfer, so try clearing them and logging |
8b9bc460 LM |
3654 | * the occurrence. |
3655 | */ | |
5b7d70c6 | 3656 | |
47a1685f | 3657 | if (gintsts & GINTSTS_GOUTNAKEFF) { |
837e9f00 VM |
3658 | u8 idx; |
3659 | u32 epctrl; | |
3660 | u32 gintmsk; | |
d8484552 | 3661 | u32 daintmsk; |
837e9f00 VM |
3662 | struct dwc2_hsotg_ep *hs_ep; |
3663 | ||
f25c42b8 | 3664 | daintmsk = dwc2_readl(hsotg, DAINTMSK); |
d8484552 | 3665 | daintmsk >>= DAINT_OUTEP_SHIFT; |
837e9f00 | 3666 | /* Mask this interrupt */ |
f25c42b8 | 3667 | gintmsk = dwc2_readl(hsotg, GINTMSK); |
837e9f00 | 3668 | gintmsk &= ~GINTSTS_GOUTNAKEFF; |
f25c42b8 | 3669 | dwc2_writel(hsotg, gintmsk, GINTMSK); |
837e9f00 VM |
3670 | |
3671 | dev_dbg(hsotg->dev, "GOUTNakEff triggered\n"); | |
d5d5f079 | 3672 | for (idx = 1; idx < hsotg->num_of_eps; idx++) { |
837e9f00 | 3673 | hs_ep = hsotg->eps_out[idx]; |
d8484552 | 3674 | /* Proceed only unmasked ISOC EPs */ |
89066b36 | 3675 | if ((BIT(idx) & ~daintmsk) || !hs_ep->isochronous) |
d8484552 RK |
3676 | continue; |
3677 | ||
f25c42b8 | 3678 | epctrl = dwc2_readl(hsotg, DOEPCTL(idx)); |
837e9f00 | 3679 | |
d8484552 | 3680 | if (epctrl & DXEPCTL_EPENA) { |
837e9f00 VM |
3681 | epctrl |= DXEPCTL_SNAK; |
3682 | epctrl |= DXEPCTL_EPDIS; | |
f25c42b8 | 3683 | dwc2_writel(hsotg, epctrl, DOEPCTL(idx)); |
837e9f00 VM |
3684 | } |
3685 | } | |
a3395f0d | 3686 | |
837e9f00 | 3687 | /* This interrupt bit is cleared in DXEPINT_EPDISBLD handler */ |
5b7d70c6 BD |
3688 | } |
3689 | ||
47a1685f | 3690 | if (gintsts & GINTSTS_GINNAKEFF) { |
5b7d70c6 BD |
3691 | dev_info(hsotg->dev, "GINNakEff triggered\n"); |
3692 | ||
f25c42b8 | 3693 | dwc2_set_bit(hsotg, DCTL, DCTL_CGNPINNAK); |
a3395f0d | 3694 | |
1f91b4cc | 3695 | dwc2_hsotg_dump(hsotg); |
5b7d70c6 BD |
3696 | } |
3697 | ||
381fc8f8 VM |
3698 | if (gintsts & GINTSTS_INCOMPL_SOIN) |
3699 | dwc2_gadget_handle_incomplete_isoc_in(hsotg); | |
ec1f9d9f | 3700 | |
381fc8f8 VM |
3701 | if (gintsts & GINTSTS_INCOMPL_SOOUT) |
3702 | dwc2_gadget_handle_incomplete_isoc_out(hsotg); | |
ec1f9d9f | 3703 | |
8b9bc460 LM |
3704 | /* |
3705 | * if we've had fifo events, we should try and go around the | |
3706 | * loop again to see if there's any point in returning yet. | |
3707 | */ | |
5b7d70c6 BD |
3708 | |
3709 | if (gintsts & IRQ_RETRY_MASK && --retry_count > 0) | |
77b6200e | 3710 | goto irq_retry; |
5b7d70c6 | 3711 | |
5ad1d316 LM |
3712 | spin_unlock(&hsotg->lock); |
3713 | ||
5b7d70c6 BD |
3714 | return IRQ_HANDLED; |
3715 | } | |
3716 | ||
a4f82771 VA |
3717 | static void dwc2_hsotg_ep_stop_xfr(struct dwc2_hsotg *hsotg, |
3718 | struct dwc2_hsotg_ep *hs_ep) | |
3719 | { | |
3720 | u32 epctrl_reg; | |
3721 | u32 epint_reg; | |
3722 | ||
3723 | epctrl_reg = hs_ep->dir_in ? DIEPCTL(hs_ep->index) : | |
3724 | DOEPCTL(hs_ep->index); | |
3725 | epint_reg = hs_ep->dir_in ? DIEPINT(hs_ep->index) : | |
3726 | DOEPINT(hs_ep->index); | |
3727 | ||
3728 | dev_dbg(hsotg->dev, "%s: stopping transfer on %s\n", __func__, | |
3729 | hs_ep->name); | |
3730 | ||
3731 | if (hs_ep->dir_in) { | |
3732 | if (hsotg->dedicated_fifos || hs_ep->periodic) { | |
f25c42b8 | 3733 | dwc2_set_bit(hsotg, epctrl_reg, DXEPCTL_SNAK); |
a4f82771 VA |
3734 | /* Wait for Nak effect */ |
3735 | if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg, | |
3736 | DXEPINT_INEPNAKEFF, 100)) | |
3737 | dev_warn(hsotg->dev, | |
3738 | "%s: timeout DIEPINT.NAKEFF\n", | |
3739 | __func__); | |
3740 | } else { | |
f25c42b8 | 3741 | dwc2_set_bit(hsotg, DCTL, DCTL_SGNPINNAK); |
a4f82771 VA |
3742 | /* Wait for Nak effect */ |
3743 | if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS, | |
3744 | GINTSTS_GINNAKEFF, 100)) | |
3745 | dev_warn(hsotg->dev, | |
3746 | "%s: timeout GINTSTS.GINNAKEFF\n", | |
3747 | __func__); | |
3748 | } | |
3749 | } else { | |
f25c42b8 GS |
3750 | if (!(dwc2_readl(hsotg, GINTSTS) & GINTSTS_GOUTNAKEFF)) |
3751 | dwc2_set_bit(hsotg, DCTL, DCTL_SGOUTNAK); | |
a4f82771 VA |
3752 | |
3753 | /* Wait for global nak to take effect */ | |
3754 | if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS, | |
3755 | GINTSTS_GOUTNAKEFF, 100)) | |
3756 | dev_warn(hsotg->dev, "%s: timeout GINTSTS.GOUTNAKEFF\n", | |
3757 | __func__); | |
3758 | } | |
3759 | ||
3760 | /* Disable ep */ | |
f25c42b8 | 3761 | dwc2_set_bit(hsotg, epctrl_reg, DXEPCTL_EPDIS | DXEPCTL_SNAK); |
a4f82771 VA |
3762 | |
3763 | /* Wait for ep to be disabled */ | |
3764 | if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg, DXEPINT_EPDISBLD, 100)) | |
3765 | dev_warn(hsotg->dev, | |
3766 | "%s: timeout DOEPCTL.EPDisable\n", __func__); | |
3767 | ||
3768 | /* Clear EPDISBLD interrupt */ | |
f25c42b8 | 3769 | dwc2_set_bit(hsotg, epint_reg, DXEPINT_EPDISBLD); |
a4f82771 VA |
3770 | |
3771 | if (hs_ep->dir_in) { | |
3772 | unsigned short fifo_index; | |
3773 | ||
3774 | if (hsotg->dedicated_fifos || hs_ep->periodic) | |
3775 | fifo_index = hs_ep->fifo_index; | |
3776 | else | |
3777 | fifo_index = 0; | |
3778 | ||
3779 | /* Flush TX FIFO */ | |
3780 | dwc2_flush_tx_fifo(hsotg, fifo_index); | |
3781 | ||
3782 | /* Clear Global In NP NAK in Shared FIFO for non periodic ep */ | |
3783 | if (!hsotg->dedicated_fifos && !hs_ep->periodic) | |
f25c42b8 | 3784 | dwc2_set_bit(hsotg, DCTL, DCTL_CGNPINNAK); |
a4f82771 VA |
3785 | |
3786 | } else { | |
3787 | /* Remove global NAKs */ | |
f25c42b8 | 3788 | dwc2_set_bit(hsotg, DCTL, DCTL_CGOUTNAK); |
a4f82771 VA |
3789 | } |
3790 | } | |
3791 | ||
5b7d70c6 | 3792 | /** |
1f91b4cc | 3793 | * dwc2_hsotg_ep_enable - enable the given endpoint |
5b7d70c6 BD |
3794 | * @ep: The USB endpint to configure |
3795 | * @desc: The USB endpoint descriptor to configure with. | |
3796 | * | |
3797 | * This is called from the USB gadget code's usb_ep_enable(). | |
8b9bc460 | 3798 | */ |
1f91b4cc | 3799 | static int dwc2_hsotg_ep_enable(struct usb_ep *ep, |
9da51974 | 3800 | const struct usb_endpoint_descriptor *desc) |
5b7d70c6 | 3801 | { |
1f91b4cc | 3802 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 3803 | struct dwc2_hsotg *hsotg = hs_ep->parent; |
5b7d70c6 | 3804 | unsigned long flags; |
ca4c55ad | 3805 | unsigned int index = hs_ep->index; |
5b7d70c6 BD |
3806 | u32 epctrl_reg; |
3807 | u32 epctrl; | |
3808 | u32 mps; | |
ee2c40de | 3809 | u32 mc; |
837e9f00 | 3810 | u32 mask; |
ca4c55ad MYK |
3811 | unsigned int dir_in; |
3812 | unsigned int i, val, size; | |
19c190f9 | 3813 | int ret = 0; |
729cac69 | 3814 | unsigned char ep_type; |
5b7d70c6 BD |
3815 | |
3816 | dev_dbg(hsotg->dev, | |
3817 | "%s: ep %s: a 0x%02x, attr 0x%02x, mps 0x%04x, intr %d\n", | |
3818 | __func__, ep->name, desc->bEndpointAddress, desc->bmAttributes, | |
3819 | desc->wMaxPacketSize, desc->bInterval); | |
3820 | ||
3821 | /* not to be called for EP0 */ | |
8c3d6092 VA |
3822 | if (index == 0) { |
3823 | dev_err(hsotg->dev, "%s: called for EP 0\n", __func__); | |
3824 | return -EINVAL; | |
3825 | } | |
5b7d70c6 BD |
3826 | |
3827 | dir_in = (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) ? 1 : 0; | |
3828 | if (dir_in != hs_ep->dir_in) { | |
3829 | dev_err(hsotg->dev, "%s: direction mismatch!\n", __func__); | |
3830 | return -EINVAL; | |
3831 | } | |
3832 | ||
729cac69 | 3833 | ep_type = desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK; |
29cc8897 | 3834 | mps = usb_endpoint_maxp(desc); |
ee2c40de | 3835 | mc = usb_endpoint_maxp_mult(desc); |
5b7d70c6 | 3836 | |
729cac69 MH |
3837 | /* ISOC IN in DDMA supported bInterval up to 10 */ |
3838 | if (using_desc_dma(hsotg) && ep_type == USB_ENDPOINT_XFER_ISOC && | |
3839 | dir_in && desc->bInterval > 10) { | |
3840 | dev_err(hsotg->dev, | |
3841 | "%s: ISOC IN, DDMA: bInterval>10 not supported!\n", __func__); | |
3842 | return -EINVAL; | |
3843 | } | |
3844 | ||
3845 | /* High bandwidth ISOC OUT in DDMA not supported */ | |
3846 | if (using_desc_dma(hsotg) && ep_type == USB_ENDPOINT_XFER_ISOC && | |
3847 | !dir_in && mc > 1) { | |
3848 | dev_err(hsotg->dev, | |
3849 | "%s: ISOC OUT, DDMA: HB not supported!\n", __func__); | |
3850 | return -EINVAL; | |
3851 | } | |
3852 | ||
1f91b4cc | 3853 | /* note, we handle this here instead of dwc2_hsotg_set_ep_maxpacket */ |
5b7d70c6 | 3854 | |
94cb8fd6 | 3855 | epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index); |
f25c42b8 | 3856 | epctrl = dwc2_readl(hsotg, epctrl_reg); |
5b7d70c6 BD |
3857 | |
3858 | dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x from 0x%08x\n", | |
3859 | __func__, epctrl, epctrl_reg); | |
3860 | ||
5f54c54b | 3861 | /* Allocate DMA descriptor chain for non-ctrl endpoints */ |
9383e084 VM |
3862 | if (using_desc_dma(hsotg) && !hs_ep->desc_list) { |
3863 | hs_ep->desc_list = dmam_alloc_coherent(hsotg->dev, | |
5f54c54b VA |
3864 | MAX_DMA_DESC_NUM_GENERIC * |
3865 | sizeof(struct dwc2_dma_desc), | |
86e881e7 | 3866 | &hs_ep->desc_list_dma, GFP_ATOMIC); |
5f54c54b VA |
3867 | if (!hs_ep->desc_list) { |
3868 | ret = -ENOMEM; | |
3869 | goto error2; | |
3870 | } | |
3871 | } | |
3872 | ||
22258f49 | 3873 | spin_lock_irqsave(&hsotg->lock, flags); |
5b7d70c6 | 3874 | |
47a1685f DN |
3875 | epctrl &= ~(DXEPCTL_EPTYPE_MASK | DXEPCTL_MPS_MASK); |
3876 | epctrl |= DXEPCTL_MPS(mps); | |
5b7d70c6 | 3877 | |
8b9bc460 LM |
3878 | /* |
3879 | * mark the endpoint as active, otherwise the core may ignore | |
3880 | * transactions entirely for this endpoint | |
3881 | */ | |
47a1685f | 3882 | epctrl |= DXEPCTL_USBACTEP; |
5b7d70c6 | 3883 | |
5b7d70c6 | 3884 | /* update the endpoint state */ |
ee2c40de | 3885 | dwc2_hsotg_set_ep_maxpacket(hsotg, hs_ep->index, mps, mc, dir_in); |
5b7d70c6 BD |
3886 | |
3887 | /* default, set to non-periodic */ | |
1479e841 | 3888 | hs_ep->isochronous = 0; |
5b7d70c6 | 3889 | hs_ep->periodic = 0; |
a18ed7b0 | 3890 | hs_ep->halted = 0; |
1479e841 | 3891 | hs_ep->interval = desc->bInterval; |
4fca54aa | 3892 | |
729cac69 | 3893 | switch (ep_type) { |
5b7d70c6 | 3894 | case USB_ENDPOINT_XFER_ISOC: |
47a1685f DN |
3895 | epctrl |= DXEPCTL_EPTYPE_ISO; |
3896 | epctrl |= DXEPCTL_SETEVENFR; | |
1479e841 | 3897 | hs_ep->isochronous = 1; |
142bd33f | 3898 | hs_ep->interval = 1 << (desc->bInterval - 1); |
837e9f00 | 3899 | hs_ep->target_frame = TARGET_FRAME_INITIAL; |
ab7d2192 | 3900 | hs_ep->next_desc = 0; |
729cac69 | 3901 | hs_ep->compl_desc = 0; |
837e9f00 | 3902 | if (dir_in) { |
1479e841 | 3903 | hs_ep->periodic = 1; |
f25c42b8 | 3904 | mask = dwc2_readl(hsotg, DIEPMSK); |
837e9f00 | 3905 | mask |= DIEPMSK_NAKMSK; |
f25c42b8 | 3906 | dwc2_writel(hsotg, mask, DIEPMSK); |
837e9f00 | 3907 | } else { |
f25c42b8 | 3908 | mask = dwc2_readl(hsotg, DOEPMSK); |
837e9f00 | 3909 | mask |= DOEPMSK_OUTTKNEPDISMSK; |
f25c42b8 | 3910 | dwc2_writel(hsotg, mask, DOEPMSK); |
837e9f00 | 3911 | } |
1479e841 | 3912 | break; |
5b7d70c6 BD |
3913 | |
3914 | case USB_ENDPOINT_XFER_BULK: | |
47a1685f | 3915 | epctrl |= DXEPCTL_EPTYPE_BULK; |
5b7d70c6 BD |
3916 | break; |
3917 | ||
3918 | case USB_ENDPOINT_XFER_INT: | |
b203d0a2 | 3919 | if (dir_in) |
5b7d70c6 | 3920 | hs_ep->periodic = 1; |
5b7d70c6 | 3921 | |
142bd33f VM |
3922 | if (hsotg->gadget.speed == USB_SPEED_HIGH) |
3923 | hs_ep->interval = 1 << (desc->bInterval - 1); | |
3924 | ||
47a1685f | 3925 | epctrl |= DXEPCTL_EPTYPE_INTERRUPT; |
5b7d70c6 BD |
3926 | break; |
3927 | ||
3928 | case USB_ENDPOINT_XFER_CONTROL: | |
47a1685f | 3929 | epctrl |= DXEPCTL_EPTYPE_CONTROL; |
5b7d70c6 BD |
3930 | break; |
3931 | } | |
3932 | ||
8b9bc460 LM |
3933 | /* |
3934 | * if the hardware has dedicated fifos, we must give each IN EP | |
10aebc77 BD |
3935 | * a unique tx-fifo even if it is non-periodic. |
3936 | */ | |
21f3bb52 | 3937 | if (dir_in && hsotg->dedicated_fifos) { |
ca4c55ad MYK |
3938 | u32 fifo_index = 0; |
3939 | u32 fifo_size = UINT_MAX; | |
9da51974 JY |
3940 | |
3941 | size = hs_ep->ep.maxpacket * hs_ep->mc; | |
5f2196bd | 3942 | for (i = 1; i < hsotg->num_of_eps; ++i) { |
9da51974 | 3943 | if (hsotg->fifo_map & (1 << i)) |
b203d0a2 | 3944 | continue; |
f25c42b8 | 3945 | val = dwc2_readl(hsotg, DPTXFSIZN(i)); |
9da51974 | 3946 | val = (val >> FIFOSIZE_DEPTH_SHIFT) * 4; |
b203d0a2 RB |
3947 | if (val < size) |
3948 | continue; | |
ca4c55ad MYK |
3949 | /* Search for smallest acceptable fifo */ |
3950 | if (val < fifo_size) { | |
3951 | fifo_size = val; | |
3952 | fifo_index = i; | |
3953 | } | |
b203d0a2 | 3954 | } |
ca4c55ad | 3955 | if (!fifo_index) { |
5f2196bd MYK |
3956 | dev_err(hsotg->dev, |
3957 | "%s: No suitable fifo found\n", __func__); | |
b585a48b | 3958 | ret = -ENOMEM; |
5f54c54b | 3959 | goto error1; |
b585a48b | 3960 | } |
ca4c55ad MYK |
3961 | hsotg->fifo_map |= 1 << fifo_index; |
3962 | epctrl |= DXEPCTL_TXFNUM(fifo_index); | |
3963 | hs_ep->fifo_index = fifo_index; | |
3964 | hs_ep->fifo_size = fifo_size; | |
b203d0a2 | 3965 | } |
10aebc77 | 3966 | |
5b7d70c6 | 3967 | /* for non control endpoints, set PID to D0 */ |
837e9f00 | 3968 | if (index && !hs_ep->isochronous) |
47a1685f | 3969 | epctrl |= DXEPCTL_SETD0PID; |
5b7d70c6 | 3970 | |
5295322a AP |
3971 | /* WA for Full speed ISOC IN in DDMA mode. |
3972 | * By Clear NAK status of EP, core will send ZLP | |
3973 | * to IN token and assert NAK interrupt relying | |
3974 | * on TxFIFO status only | |
3975 | */ | |
3976 | ||
3977 | if (hsotg->gadget.speed == USB_SPEED_FULL && | |
3978 | hs_ep->isochronous && dir_in) { | |
3979 | /* The WA applies only to core versions from 2.72a | |
3980 | * to 4.00a (including both). Also for FS_IOT_1.00a | |
3981 | * and HS_IOT_1.00a. | |
3982 | */ | |
f25c42b8 | 3983 | u32 gsnpsid = dwc2_readl(hsotg, GSNPSID); |
5295322a AP |
3984 | |
3985 | if ((gsnpsid >= DWC2_CORE_REV_2_72a && | |
3986 | gsnpsid <= DWC2_CORE_REV_4_00a) || | |
3987 | gsnpsid == DWC2_FS_IOT_REV_1_00a || | |
3988 | gsnpsid == DWC2_HS_IOT_REV_1_00a) | |
3989 | epctrl |= DXEPCTL_CNAK; | |
3990 | } | |
3991 | ||
5b7d70c6 BD |
3992 | dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n", |
3993 | __func__, epctrl); | |
3994 | ||
f25c42b8 | 3995 | dwc2_writel(hsotg, epctrl, epctrl_reg); |
5b7d70c6 | 3996 | dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x\n", |
f25c42b8 | 3997 | __func__, dwc2_readl(hsotg, epctrl_reg)); |
5b7d70c6 BD |
3998 | |
3999 | /* enable the endpoint interrupt */ | |
1f91b4cc | 4000 | dwc2_hsotg_ctrl_epint(hsotg, index, dir_in, 1); |
5b7d70c6 | 4001 | |
5f54c54b | 4002 | error1: |
22258f49 | 4003 | spin_unlock_irqrestore(&hsotg->lock, flags); |
5f54c54b VA |
4004 | |
4005 | error2: | |
4006 | if (ret && using_desc_dma(hsotg) && hs_ep->desc_list) { | |
9383e084 | 4007 | dmam_free_coherent(hsotg->dev, MAX_DMA_DESC_NUM_GENERIC * |
5f54c54b VA |
4008 | sizeof(struct dwc2_dma_desc), |
4009 | hs_ep->desc_list, hs_ep->desc_list_dma); | |
4010 | hs_ep->desc_list = NULL; | |
4011 | } | |
4012 | ||
19c190f9 | 4013 | return ret; |
5b7d70c6 BD |
4014 | } |
4015 | ||
8b9bc460 | 4016 | /** |
1f91b4cc | 4017 | * dwc2_hsotg_ep_disable - disable given endpoint |
8b9bc460 LM |
4018 | * @ep: The endpoint to disable. |
4019 | */ | |
1f91b4cc | 4020 | static int dwc2_hsotg_ep_disable(struct usb_ep *ep) |
5b7d70c6 | 4021 | { |
1f91b4cc | 4022 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 4023 | struct dwc2_hsotg *hsotg = hs_ep->parent; |
5b7d70c6 BD |
4024 | int dir_in = hs_ep->dir_in; |
4025 | int index = hs_ep->index; | |
4026 | unsigned long flags; | |
4027 | u32 epctrl_reg; | |
4028 | u32 ctrl; | |
dccf1bad | 4029 | int locked; |
5b7d70c6 | 4030 | |
1e011293 | 4031 | dev_dbg(hsotg->dev, "%s(ep %p)\n", __func__, ep); |
5b7d70c6 | 4032 | |
c6f5c050 | 4033 | if (ep == &hsotg->eps_out[0]->ep) { |
5b7d70c6 BD |
4034 | dev_err(hsotg->dev, "%s: called for ep0\n", __func__); |
4035 | return -EINVAL; | |
9b481092 JS |
4036 | } |
4037 | ||
4038 | if (hsotg->op_state != OTG_STATE_B_PERIPHERAL) { | |
4039 | dev_err(hsotg->dev, "%s: called in host mode?\n", __func__); | |
4040 | return -EINVAL; | |
5b7d70c6 BD |
4041 | } |
4042 | ||
94cb8fd6 | 4043 | epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index); |
5b7d70c6 | 4044 | |
dccf1bad MH |
4045 | locked = spin_is_locked(&hsotg->lock); |
4046 | if (!locked) | |
4047 | spin_lock_irqsave(&hsotg->lock, flags); | |
5b7d70c6 | 4048 | |
f25c42b8 | 4049 | ctrl = dwc2_readl(hsotg, epctrl_reg); |
a4f82771 VA |
4050 | |
4051 | if (ctrl & DXEPCTL_EPENA) | |
4052 | dwc2_hsotg_ep_stop_xfr(hsotg, hs_ep); | |
4053 | ||
47a1685f DN |
4054 | ctrl &= ~DXEPCTL_EPENA; |
4055 | ctrl &= ~DXEPCTL_USBACTEP; | |
4056 | ctrl |= DXEPCTL_SNAK; | |
5b7d70c6 BD |
4057 | |
4058 | dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl); | |
f25c42b8 | 4059 | dwc2_writel(hsotg, ctrl, epctrl_reg); |
5b7d70c6 BD |
4060 | |
4061 | /* disable endpoint interrupts */ | |
1f91b4cc | 4062 | dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 0); |
5b7d70c6 | 4063 | |
1141ea01 MYK |
4064 | /* terminate all requests with shutdown */ |
4065 | kill_all_requests(hsotg, hs_ep, -ESHUTDOWN); | |
4066 | ||
1c07b20e RB |
4067 | hsotg->fifo_map &= ~(1 << hs_ep->fifo_index); |
4068 | hs_ep->fifo_index = 0; | |
4069 | hs_ep->fifo_size = 0; | |
4070 | ||
dccf1bad MH |
4071 | if (!locked) |
4072 | spin_unlock_irqrestore(&hsotg->lock, flags); | |
4073 | ||
5b7d70c6 BD |
4074 | return 0; |
4075 | } | |
4076 | ||
4077 | /** | |
4078 | * on_list - check request is on the given endpoint | |
4079 | * @ep: The endpoint to check. | |
4080 | * @test: The request to test if it is on the endpoint. | |
8b9bc460 | 4081 | */ |
1f91b4cc | 4082 | static bool on_list(struct dwc2_hsotg_ep *ep, struct dwc2_hsotg_req *test) |
5b7d70c6 | 4083 | { |
1f91b4cc | 4084 | struct dwc2_hsotg_req *req, *treq; |
5b7d70c6 BD |
4085 | |
4086 | list_for_each_entry_safe(req, treq, &ep->queue, queue) { | |
4087 | if (req == test) | |
4088 | return true; | |
4089 | } | |
4090 | ||
4091 | return false; | |
4092 | } | |
4093 | ||
8b9bc460 | 4094 | /** |
1f91b4cc | 4095 | * dwc2_hsotg_ep_dequeue - dequeue given endpoint |
8b9bc460 LM |
4096 | * @ep: The endpoint to dequeue. |
4097 | * @req: The request to be removed from a queue. | |
4098 | */ | |
1f91b4cc | 4099 | static int dwc2_hsotg_ep_dequeue(struct usb_ep *ep, struct usb_request *req) |
5b7d70c6 | 4100 | { |
1f91b4cc FB |
4101 | struct dwc2_hsotg_req *hs_req = our_req(req); |
4102 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); | |
941fcce4 | 4103 | struct dwc2_hsotg *hs = hs_ep->parent; |
5b7d70c6 BD |
4104 | unsigned long flags; |
4105 | ||
1e011293 | 4106 | dev_dbg(hs->dev, "ep_dequeue(%p,%p)\n", ep, req); |
5b7d70c6 | 4107 | |
22258f49 | 4108 | spin_lock_irqsave(&hs->lock, flags); |
5b7d70c6 BD |
4109 | |
4110 | if (!on_list(hs_ep, hs_req)) { | |
22258f49 | 4111 | spin_unlock_irqrestore(&hs->lock, flags); |
5b7d70c6 BD |
4112 | return -EINVAL; |
4113 | } | |
4114 | ||
c524dd5f MYK |
4115 | /* Dequeue already started request */ |
4116 | if (req == &hs_ep->req->req) | |
4117 | dwc2_hsotg_ep_stop_xfr(hs, hs_ep); | |
4118 | ||
1f91b4cc | 4119 | dwc2_hsotg_complete_request(hs, hs_ep, hs_req, -ECONNRESET); |
22258f49 | 4120 | spin_unlock_irqrestore(&hs->lock, flags); |
5b7d70c6 BD |
4121 | |
4122 | return 0; | |
4123 | } | |
4124 | ||
8b9bc460 | 4125 | /** |
1f91b4cc | 4126 | * dwc2_hsotg_ep_sethalt - set halt on a given endpoint |
8b9bc460 LM |
4127 | * @ep: The endpoint to set halt. |
4128 | * @value: Set or unset the halt. | |
51da43b5 VA |
4129 | * @now: If true, stall the endpoint now. Otherwise return -EAGAIN if |
4130 | * the endpoint is busy processing requests. | |
4131 | * | |
4132 | * We need to stall the endpoint immediately if request comes from set_feature | |
4133 | * protocol command handler. | |
8b9bc460 | 4134 | */ |
51da43b5 | 4135 | static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now) |
5b7d70c6 | 4136 | { |
1f91b4cc | 4137 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 4138 | struct dwc2_hsotg *hs = hs_ep->parent; |
5b7d70c6 | 4139 | int index = hs_ep->index; |
5b7d70c6 BD |
4140 | u32 epreg; |
4141 | u32 epctl; | |
9c39ddc6 | 4142 | u32 xfertype; |
5b7d70c6 BD |
4143 | |
4144 | dev_info(hs->dev, "%s(ep %p %s, %d)\n", __func__, ep, ep->name, value); | |
4145 | ||
c9f721b2 RB |
4146 | if (index == 0) { |
4147 | if (value) | |
1f91b4cc | 4148 | dwc2_hsotg_stall_ep0(hs); |
c9f721b2 RB |
4149 | else |
4150 | dev_warn(hs->dev, | |
4151 | "%s: can't clear halt on ep0\n", __func__); | |
4152 | return 0; | |
4153 | } | |
4154 | ||
15186f10 VA |
4155 | if (hs_ep->isochronous) { |
4156 | dev_err(hs->dev, "%s is Isochronous Endpoint\n", ep->name); | |
4157 | return -EINVAL; | |
4158 | } | |
4159 | ||
51da43b5 VA |
4160 | if (!now && value && !list_empty(&hs_ep->queue)) { |
4161 | dev_dbg(hs->dev, "%s request is pending, cannot halt\n", | |
4162 | ep->name); | |
4163 | return -EAGAIN; | |
4164 | } | |
4165 | ||
c6f5c050 MYK |
4166 | if (hs_ep->dir_in) { |
4167 | epreg = DIEPCTL(index); | |
f25c42b8 | 4168 | epctl = dwc2_readl(hs, epreg); |
c6f5c050 MYK |
4169 | |
4170 | if (value) { | |
5a350d53 | 4171 | epctl |= DXEPCTL_STALL | DXEPCTL_SNAK; |
c6f5c050 MYK |
4172 | if (epctl & DXEPCTL_EPENA) |
4173 | epctl |= DXEPCTL_EPDIS; | |
4174 | } else { | |
4175 | epctl &= ~DXEPCTL_STALL; | |
4176 | xfertype = epctl & DXEPCTL_EPTYPE_MASK; | |
4177 | if (xfertype == DXEPCTL_EPTYPE_BULK || | |
9da51974 | 4178 | xfertype == DXEPCTL_EPTYPE_INTERRUPT) |
77b6200e | 4179 | epctl |= DXEPCTL_SETD0PID; |
c6f5c050 | 4180 | } |
f25c42b8 | 4181 | dwc2_writel(hs, epctl, epreg); |
9c39ddc6 | 4182 | } else { |
c6f5c050 | 4183 | epreg = DOEPCTL(index); |
f25c42b8 | 4184 | epctl = dwc2_readl(hs, epreg); |
5b7d70c6 | 4185 | |
34c0887f | 4186 | if (value) { |
c6f5c050 | 4187 | epctl |= DXEPCTL_STALL; |
34c0887f | 4188 | } else { |
c6f5c050 MYK |
4189 | epctl &= ~DXEPCTL_STALL; |
4190 | xfertype = epctl & DXEPCTL_EPTYPE_MASK; | |
4191 | if (xfertype == DXEPCTL_EPTYPE_BULK || | |
9da51974 | 4192 | xfertype == DXEPCTL_EPTYPE_INTERRUPT) |
77b6200e | 4193 | epctl |= DXEPCTL_SETD0PID; |
c6f5c050 | 4194 | } |
f25c42b8 | 4195 | dwc2_writel(hs, epctl, epreg); |
9c39ddc6 | 4196 | } |
5b7d70c6 | 4197 | |
a18ed7b0 RB |
4198 | hs_ep->halted = value; |
4199 | ||
5b7d70c6 BD |
4200 | return 0; |
4201 | } | |
4202 | ||
5ad1d316 | 4203 | /** |
1f91b4cc | 4204 | * dwc2_hsotg_ep_sethalt_lock - set halt on a given endpoint with lock held |
5ad1d316 LM |
4205 | * @ep: The endpoint to set halt. |
4206 | * @value: Set or unset the halt. | |
4207 | */ | |
1f91b4cc | 4208 | static int dwc2_hsotg_ep_sethalt_lock(struct usb_ep *ep, int value) |
5ad1d316 | 4209 | { |
1f91b4cc | 4210 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 4211 | struct dwc2_hsotg *hs = hs_ep->parent; |
5ad1d316 LM |
4212 | unsigned long flags = 0; |
4213 | int ret = 0; | |
4214 | ||
4215 | spin_lock_irqsave(&hs->lock, flags); | |
51da43b5 | 4216 | ret = dwc2_hsotg_ep_sethalt(ep, value, false); |
5ad1d316 LM |
4217 | spin_unlock_irqrestore(&hs->lock, flags); |
4218 | ||
4219 | return ret; | |
4220 | } | |
4221 | ||
ebce561a | 4222 | static const struct usb_ep_ops dwc2_hsotg_ep_ops = { |
1f91b4cc FB |
4223 | .enable = dwc2_hsotg_ep_enable, |
4224 | .disable = dwc2_hsotg_ep_disable, | |
4225 | .alloc_request = dwc2_hsotg_ep_alloc_request, | |
4226 | .free_request = dwc2_hsotg_ep_free_request, | |
4227 | .queue = dwc2_hsotg_ep_queue_lock, | |
4228 | .dequeue = dwc2_hsotg_ep_dequeue, | |
4229 | .set_halt = dwc2_hsotg_ep_sethalt_lock, | |
25985edc | 4230 | /* note, don't believe we have any call for the fifo routines */ |
5b7d70c6 BD |
4231 | }; |
4232 | ||
8b9bc460 | 4233 | /** |
9da51974 | 4234 | * dwc2_hsotg_init - initialize the usb core |
8b9bc460 LM |
4235 | * @hsotg: The driver state |
4236 | */ | |
1f91b4cc | 4237 | static void dwc2_hsotg_init(struct dwc2_hsotg *hsotg) |
b3f489b2 | 4238 | { |
fa4a8d72 | 4239 | u32 trdtim; |
ecd9a7ad | 4240 | u32 usbcfg; |
b3f489b2 LM |
4241 | /* unmask subset of endpoint interrupts */ |
4242 | ||
f25c42b8 | 4243 | dwc2_writel(hsotg, DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK | |
95c8bc36 | 4244 | DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK, |
f25c42b8 | 4245 | DIEPMSK); |
b3f489b2 | 4246 | |
f25c42b8 | 4247 | dwc2_writel(hsotg, DOEPMSK_SETUPMSK | DOEPMSK_AHBERRMSK | |
95c8bc36 | 4248 | DOEPMSK_EPDISBLDMSK | DOEPMSK_XFERCOMPLMSK, |
f25c42b8 | 4249 | DOEPMSK); |
b3f489b2 | 4250 | |
f25c42b8 | 4251 | dwc2_writel(hsotg, 0, DAINTMSK); |
b3f489b2 LM |
4252 | |
4253 | /* Be in disconnected state until gadget is registered */ | |
f25c42b8 | 4254 | dwc2_set_bit(hsotg, DCTL, DCTL_SFTDISCON); |
b3f489b2 | 4255 | |
b3f489b2 LM |
4256 | /* setup fifos */ |
4257 | ||
4258 | dev_dbg(hsotg->dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n", | |
f25c42b8 GS |
4259 | dwc2_readl(hsotg, GRXFSIZ), |
4260 | dwc2_readl(hsotg, GNPTXFSIZ)); | |
b3f489b2 | 4261 | |
1f91b4cc | 4262 | dwc2_hsotg_init_fifo(hsotg); |
b3f489b2 | 4263 | |
ecd9a7ad | 4264 | /* keep other bits untouched (so e.g. forced modes are not lost) */ |
f25c42b8 | 4265 | usbcfg = dwc2_readl(hsotg, GUSBCFG); |
ecd9a7ad | 4266 | usbcfg &= ~(GUSBCFG_TOUTCAL_MASK | GUSBCFG_PHYIF16 | GUSBCFG_SRPCAP | |
ca02954a | 4267 | GUSBCFG_HNPCAP | GUSBCFG_USBTRDTIM_MASK); |
ecd9a7ad | 4268 | |
b3f489b2 | 4269 | /* set the PLL on, remove the HNP/SRP and set the PHY */ |
fa4a8d72 | 4270 | trdtim = (hsotg->phyif == GUSBCFG_PHYIF8) ? 9 : 5; |
ecd9a7ad PR |
4271 | usbcfg |= hsotg->phyif | GUSBCFG_TOUTCAL(7) | |
4272 | (trdtim << GUSBCFG_USBTRDTIM_SHIFT); | |
f25c42b8 | 4273 | dwc2_writel(hsotg, usbcfg, GUSBCFG); |
b3f489b2 | 4274 | |
f5090044 | 4275 | if (using_dma(hsotg)) |
f25c42b8 | 4276 | dwc2_set_bit(hsotg, GAHBCFG, GAHBCFG_DMA_EN); |
b3f489b2 LM |
4277 | } |
4278 | ||
8b9bc460 | 4279 | /** |
1f91b4cc | 4280 | * dwc2_hsotg_udc_start - prepare the udc for work |
8b9bc460 LM |
4281 | * @gadget: The usb gadget state |
4282 | * @driver: The usb gadget driver | |
4283 | * | |
4284 | * Perform initialization to prepare udc device and driver | |
4285 | * to work. | |
4286 | */ | |
1f91b4cc | 4287 | static int dwc2_hsotg_udc_start(struct usb_gadget *gadget, |
9da51974 | 4288 | struct usb_gadget_driver *driver) |
5b7d70c6 | 4289 | { |
941fcce4 | 4290 | struct dwc2_hsotg *hsotg = to_hsotg(gadget); |
5b9451f8 | 4291 | unsigned long flags; |
5b7d70c6 BD |
4292 | int ret; |
4293 | ||
4294 | if (!hsotg) { | |
a023da33 | 4295 | pr_err("%s: called with no device\n", __func__); |
5b7d70c6 BD |
4296 | return -ENODEV; |
4297 | } | |
4298 | ||
4299 | if (!driver) { | |
4300 | dev_err(hsotg->dev, "%s: no driver\n", __func__); | |
4301 | return -EINVAL; | |
4302 | } | |
4303 | ||
7177aed4 | 4304 | if (driver->max_speed < USB_SPEED_FULL) |
5b7d70c6 | 4305 | dev_err(hsotg->dev, "%s: bad speed\n", __func__); |
5b7d70c6 | 4306 | |
f65f0f10 | 4307 | if (!driver->setup) { |
5b7d70c6 BD |
4308 | dev_err(hsotg->dev, "%s: missing entry points\n", __func__); |
4309 | return -EINVAL; | |
4310 | } | |
4311 | ||
4312 | WARN_ON(hsotg->driver); | |
4313 | ||
4314 | driver->driver.bus = NULL; | |
4315 | hsotg->driver = driver; | |
7d7b2292 | 4316 | hsotg->gadget.dev.of_node = hsotg->dev->of_node; |
5b7d70c6 BD |
4317 | hsotg->gadget.speed = USB_SPEED_UNKNOWN; |
4318 | ||
09a75e85 MS |
4319 | if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) { |
4320 | ret = dwc2_lowlevel_hw_enable(hsotg); | |
4321 | if (ret) | |
4322 | goto err; | |
5b7d70c6 BD |
4323 | } |
4324 | ||
f6c01592 GH |
4325 | if (!IS_ERR_OR_NULL(hsotg->uphy)) |
4326 | otg_set_peripheral(hsotg->uphy->otg, &hsotg->gadget); | |
c816c47f | 4327 | |
5b9451f8 | 4328 | spin_lock_irqsave(&hsotg->lock, flags); |
d0f0ac56 JY |
4329 | if (dwc2_hw_is_device(hsotg)) { |
4330 | dwc2_hsotg_init(hsotg); | |
4331 | dwc2_hsotg_core_init_disconnected(hsotg, false); | |
4332 | } | |
4333 | ||
dc6e69e6 | 4334 | hsotg->enabled = 0; |
5b9451f8 MS |
4335 | spin_unlock_irqrestore(&hsotg->lock, flags); |
4336 | ||
5b7d70c6 | 4337 | dev_info(hsotg->dev, "bound driver %s\n", driver->driver.name); |
5b9451f8 | 4338 | |
5b7d70c6 BD |
4339 | return 0; |
4340 | ||
4341 | err: | |
4342 | hsotg->driver = NULL; | |
5b7d70c6 BD |
4343 | return ret; |
4344 | } | |
4345 | ||
8b9bc460 | 4346 | /** |
1f91b4cc | 4347 | * dwc2_hsotg_udc_stop - stop the udc |
8b9bc460 | 4348 | * @gadget: The usb gadget state |
8b9bc460 LM |
4349 | * |
4350 | * Stop udc hw block and stay tunned for future transmissions | |
4351 | */ | |
1f91b4cc | 4352 | static int dwc2_hsotg_udc_stop(struct usb_gadget *gadget) |
5b7d70c6 | 4353 | { |
941fcce4 | 4354 | struct dwc2_hsotg *hsotg = to_hsotg(gadget); |
2b19a52c | 4355 | unsigned long flags = 0; |
5b7d70c6 BD |
4356 | int ep; |
4357 | ||
4358 | if (!hsotg) | |
4359 | return -ENODEV; | |
4360 | ||
5b7d70c6 | 4361 | /* all endpoints should be shutdown */ |
c6f5c050 MYK |
4362 | for (ep = 1; ep < hsotg->num_of_eps; ep++) { |
4363 | if (hsotg->eps_in[ep]) | |
1f91b4cc | 4364 | dwc2_hsotg_ep_disable(&hsotg->eps_in[ep]->ep); |
c6f5c050 | 4365 | if (hsotg->eps_out[ep]) |
1f91b4cc | 4366 | dwc2_hsotg_ep_disable(&hsotg->eps_out[ep]->ep); |
c6f5c050 | 4367 | } |
5b7d70c6 | 4368 | |
2b19a52c LM |
4369 | spin_lock_irqsave(&hsotg->lock, flags); |
4370 | ||
32805c35 | 4371 | hsotg->driver = NULL; |
5b7d70c6 | 4372 | hsotg->gadget.speed = USB_SPEED_UNKNOWN; |
dc6e69e6 | 4373 | hsotg->enabled = 0; |
5b7d70c6 | 4374 | |
2b19a52c LM |
4375 | spin_unlock_irqrestore(&hsotg->lock, flags); |
4376 | ||
f6c01592 GH |
4377 | if (!IS_ERR_OR_NULL(hsotg->uphy)) |
4378 | otg_set_peripheral(hsotg->uphy->otg, NULL); | |
c816c47f | 4379 | |
09a75e85 MS |
4380 | if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) |
4381 | dwc2_lowlevel_hw_disable(hsotg); | |
5b7d70c6 BD |
4382 | |
4383 | return 0; | |
4384 | } | |
5b7d70c6 | 4385 | |
8b9bc460 | 4386 | /** |
1f91b4cc | 4387 | * dwc2_hsotg_gadget_getframe - read the frame number |
8b9bc460 LM |
4388 | * @gadget: The usb gadget state |
4389 | * | |
4390 | * Read the {micro} frame number | |
4391 | */ | |
1f91b4cc | 4392 | static int dwc2_hsotg_gadget_getframe(struct usb_gadget *gadget) |
5b7d70c6 | 4393 | { |
1f91b4cc | 4394 | return dwc2_hsotg_read_frameno(to_hsotg(gadget)); |
5b7d70c6 BD |
4395 | } |
4396 | ||
a188b689 | 4397 | /** |
1f91b4cc | 4398 | * dwc2_hsotg_pullup - connect/disconnect the USB PHY |
a188b689 LM |
4399 | * @gadget: The usb gadget state |
4400 | * @is_on: Current state of the USB PHY | |
4401 | * | |
4402 | * Connect/Disconnect the USB PHY pullup | |
4403 | */ | |
1f91b4cc | 4404 | static int dwc2_hsotg_pullup(struct usb_gadget *gadget, int is_on) |
a188b689 | 4405 | { |
941fcce4 | 4406 | struct dwc2_hsotg *hsotg = to_hsotg(gadget); |
a188b689 LM |
4407 | unsigned long flags = 0; |
4408 | ||
77ba9119 | 4409 | dev_dbg(hsotg->dev, "%s: is_on: %d op_state: %d\n", __func__, is_on, |
9da51974 | 4410 | hsotg->op_state); |
77ba9119 GH |
4411 | |
4412 | /* Don't modify pullup state while in host mode */ | |
4413 | if (hsotg->op_state != OTG_STATE_B_PERIPHERAL) { | |
4414 | hsotg->enabled = is_on; | |
4415 | return 0; | |
4416 | } | |
a188b689 LM |
4417 | |
4418 | spin_lock_irqsave(&hsotg->lock, flags); | |
4419 | if (is_on) { | |
dc6e69e6 | 4420 | hsotg->enabled = 1; |
1f91b4cc | 4421 | dwc2_hsotg_core_init_disconnected(hsotg, false); |
66e77a24 RK |
4422 | /* Enable ACG feature in device mode,if supported */ |
4423 | dwc2_enable_acg(hsotg); | |
1f91b4cc | 4424 | dwc2_hsotg_core_connect(hsotg); |
a188b689 | 4425 | } else { |
1f91b4cc FB |
4426 | dwc2_hsotg_core_disconnect(hsotg); |
4427 | dwc2_hsotg_disconnect(hsotg); | |
dc6e69e6 | 4428 | hsotg->enabled = 0; |
a188b689 LM |
4429 | } |
4430 | ||
4431 | hsotg->gadget.speed = USB_SPEED_UNKNOWN; | |
4432 | spin_unlock_irqrestore(&hsotg->lock, flags); | |
4433 | ||
4434 | return 0; | |
4435 | } | |
4436 | ||
1f91b4cc | 4437 | static int dwc2_hsotg_vbus_session(struct usb_gadget *gadget, int is_active) |
83d98223 GH |
4438 | { |
4439 | struct dwc2_hsotg *hsotg = to_hsotg(gadget); | |
4440 | unsigned long flags; | |
4441 | ||
4442 | dev_dbg(hsotg->dev, "%s: is_active: %d\n", __func__, is_active); | |
4443 | spin_lock_irqsave(&hsotg->lock, flags); | |
4444 | ||
61f7223b | 4445 | /* |
41ba9b9b | 4446 | * If controller is hibernated, it must exit from power_down |
61f7223b GH |
4447 | * before being initialized / de-initialized |
4448 | */ | |
4449 | if (hsotg->lx_state == DWC2_L2) | |
41ba9b9b | 4450 | dwc2_exit_partial_power_down(hsotg, false); |
61f7223b | 4451 | |
83d98223 | 4452 | if (is_active) { |
cd0e641c | 4453 | hsotg->op_state = OTG_STATE_B_PERIPHERAL; |
065d3931 | 4454 | |
1f91b4cc | 4455 | dwc2_hsotg_core_init_disconnected(hsotg, false); |
66e77a24 RK |
4456 | if (hsotg->enabled) { |
4457 | /* Enable ACG feature in device mode,if supported */ | |
4458 | dwc2_enable_acg(hsotg); | |
1f91b4cc | 4459 | dwc2_hsotg_core_connect(hsotg); |
66e77a24 | 4460 | } |
83d98223 | 4461 | } else { |
1f91b4cc FB |
4462 | dwc2_hsotg_core_disconnect(hsotg); |
4463 | dwc2_hsotg_disconnect(hsotg); | |
83d98223 GH |
4464 | } |
4465 | ||
4466 | spin_unlock_irqrestore(&hsotg->lock, flags); | |
4467 | return 0; | |
4468 | } | |
4469 | ||
596d696a | 4470 | /** |
1f91b4cc | 4471 | * dwc2_hsotg_vbus_draw - report bMaxPower field |
596d696a GH |
4472 | * @gadget: The usb gadget state |
4473 | * @mA: Amount of current | |
4474 | * | |
4475 | * Report how much power the device may consume to the phy. | |
4476 | */ | |
9da51974 | 4477 | static int dwc2_hsotg_vbus_draw(struct usb_gadget *gadget, unsigned int mA) |
596d696a GH |
4478 | { |
4479 | struct dwc2_hsotg *hsotg = to_hsotg(gadget); | |
4480 | ||
4481 | if (IS_ERR_OR_NULL(hsotg->uphy)) | |
4482 | return -ENOTSUPP; | |
4483 | return usb_phy_set_power(hsotg->uphy, mA); | |
4484 | } | |
4485 | ||
1f91b4cc FB |
4486 | static const struct usb_gadget_ops dwc2_hsotg_gadget_ops = { |
4487 | .get_frame = dwc2_hsotg_gadget_getframe, | |
4488 | .udc_start = dwc2_hsotg_udc_start, | |
4489 | .udc_stop = dwc2_hsotg_udc_stop, | |
4490 | .pullup = dwc2_hsotg_pullup, | |
4491 | .vbus_session = dwc2_hsotg_vbus_session, | |
4492 | .vbus_draw = dwc2_hsotg_vbus_draw, | |
5b7d70c6 BD |
4493 | }; |
4494 | ||
4495 | /** | |
1f91b4cc | 4496 | * dwc2_hsotg_initep - initialise a single endpoint |
5b7d70c6 BD |
4497 | * @hsotg: The device state. |
4498 | * @hs_ep: The endpoint to be initialised. | |
4499 | * @epnum: The endpoint number | |
6fb914d7 | 4500 | * @dir_in: True if direction is in. |
5b7d70c6 BD |
4501 | * |
4502 | * Initialise the given endpoint (as part of the probe and device state | |
4503 | * creation) to give to the gadget driver. Setup the endpoint name, any | |
4504 | * direction information and other state that may be required. | |
4505 | */ | |
1f91b4cc | 4506 | static void dwc2_hsotg_initep(struct dwc2_hsotg *hsotg, |
9da51974 | 4507 | struct dwc2_hsotg_ep *hs_ep, |
c6f5c050 MYK |
4508 | int epnum, |
4509 | bool dir_in) | |
5b7d70c6 | 4510 | { |
5b7d70c6 BD |
4511 | char *dir; |
4512 | ||
4513 | if (epnum == 0) | |
4514 | dir = ""; | |
c6f5c050 | 4515 | else if (dir_in) |
5b7d70c6 | 4516 | dir = "in"; |
c6f5c050 MYK |
4517 | else |
4518 | dir = "out"; | |
5b7d70c6 | 4519 | |
c6f5c050 | 4520 | hs_ep->dir_in = dir_in; |
5b7d70c6 BD |
4521 | hs_ep->index = epnum; |
4522 | ||
4523 | snprintf(hs_ep->name, sizeof(hs_ep->name), "ep%d%s", epnum, dir); | |
4524 | ||
4525 | INIT_LIST_HEAD(&hs_ep->queue); | |
4526 | INIT_LIST_HEAD(&hs_ep->ep.ep_list); | |
4527 | ||
5b7d70c6 BD |
4528 | /* add to the list of endpoints known by the gadget driver */ |
4529 | if (epnum) | |
4530 | list_add_tail(&hs_ep->ep.ep_list, &hsotg->gadget.ep_list); | |
4531 | ||
4532 | hs_ep->parent = hsotg; | |
4533 | hs_ep->ep.name = hs_ep->name; | |
38e9002b VM |
4534 | |
4535 | if (hsotg->params.speed == DWC2_SPEED_PARAM_LOW) | |
4536 | usb_ep_set_maxpacket_limit(&hs_ep->ep, 8); | |
4537 | else | |
4538 | usb_ep_set_maxpacket_limit(&hs_ep->ep, | |
4539 | epnum ? 1024 : EP0_MPS_LIMIT); | |
1f91b4cc | 4540 | hs_ep->ep.ops = &dwc2_hsotg_ep_ops; |
5b7d70c6 | 4541 | |
2954522f RB |
4542 | if (epnum == 0) { |
4543 | hs_ep->ep.caps.type_control = true; | |
4544 | } else { | |
38e9002b VM |
4545 | if (hsotg->params.speed != DWC2_SPEED_PARAM_LOW) { |
4546 | hs_ep->ep.caps.type_iso = true; | |
4547 | hs_ep->ep.caps.type_bulk = true; | |
4548 | } | |
2954522f RB |
4549 | hs_ep->ep.caps.type_int = true; |
4550 | } | |
4551 | ||
4552 | if (dir_in) | |
4553 | hs_ep->ep.caps.dir_in = true; | |
4554 | else | |
4555 | hs_ep->ep.caps.dir_out = true; | |
4556 | ||
8b9bc460 LM |
4557 | /* |
4558 | * if we're using dma, we need to set the next-endpoint pointer | |
5b7d70c6 BD |
4559 | * to be something valid. |
4560 | */ | |
4561 | ||
4562 | if (using_dma(hsotg)) { | |
47a1685f | 4563 | u32 next = DXEPCTL_NEXTEP((epnum + 1) % 15); |
9da51974 | 4564 | |
c6f5c050 | 4565 | if (dir_in) |
f25c42b8 | 4566 | dwc2_writel(hsotg, next, DIEPCTL(epnum)); |
c6f5c050 | 4567 | else |
f25c42b8 | 4568 | dwc2_writel(hsotg, next, DOEPCTL(epnum)); |
5b7d70c6 BD |
4569 | } |
4570 | } | |
4571 | ||
b3f489b2 | 4572 | /** |
1f91b4cc | 4573 | * dwc2_hsotg_hw_cfg - read HW configuration registers |
6fb914d7 | 4574 | * @hsotg: Programming view of the DWC_otg controller |
b3f489b2 LM |
4575 | * |
4576 | * Read the USB core HW configuration registers | |
4577 | */ | |
1f91b4cc | 4578 | static int dwc2_hsotg_hw_cfg(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 4579 | { |
c6f5c050 MYK |
4580 | u32 cfg; |
4581 | u32 ep_type; | |
4582 | u32 i; | |
4583 | ||
b3f489b2 | 4584 | /* check hardware configuration */ |
5b7d70c6 | 4585 | |
43e90349 JY |
4586 | hsotg->num_of_eps = hsotg->hw_params.num_dev_ep; |
4587 | ||
c6f5c050 MYK |
4588 | /* Add ep0 */ |
4589 | hsotg->num_of_eps++; | |
10aebc77 | 4590 | |
b98866c2 JY |
4591 | hsotg->eps_in[0] = devm_kzalloc(hsotg->dev, |
4592 | sizeof(struct dwc2_hsotg_ep), | |
4593 | GFP_KERNEL); | |
c6f5c050 MYK |
4594 | if (!hsotg->eps_in[0]) |
4595 | return -ENOMEM; | |
1f91b4cc | 4596 | /* Same dwc2_hsotg_ep is used in both directions for ep0 */ |
c6f5c050 MYK |
4597 | hsotg->eps_out[0] = hsotg->eps_in[0]; |
4598 | ||
43e90349 | 4599 | cfg = hsotg->hw_params.dev_ep_dirs; |
251a17f5 | 4600 | for (i = 1, cfg >>= 2; i < hsotg->num_of_eps; i++, cfg >>= 2) { |
c6f5c050 MYK |
4601 | ep_type = cfg & 3; |
4602 | /* Direction in or both */ | |
4603 | if (!(ep_type & 2)) { | |
4604 | hsotg->eps_in[i] = devm_kzalloc(hsotg->dev, | |
1f91b4cc | 4605 | sizeof(struct dwc2_hsotg_ep), GFP_KERNEL); |
c6f5c050 MYK |
4606 | if (!hsotg->eps_in[i]) |
4607 | return -ENOMEM; | |
4608 | } | |
4609 | /* Direction out or both */ | |
4610 | if (!(ep_type & 1)) { | |
4611 | hsotg->eps_out[i] = devm_kzalloc(hsotg->dev, | |
1f91b4cc | 4612 | sizeof(struct dwc2_hsotg_ep), GFP_KERNEL); |
c6f5c050 MYK |
4613 | if (!hsotg->eps_out[i]) |
4614 | return -ENOMEM; | |
4615 | } | |
4616 | } | |
4617 | ||
43e90349 JY |
4618 | hsotg->fifo_mem = hsotg->hw_params.total_fifo_size; |
4619 | hsotg->dedicated_fifos = hsotg->hw_params.en_multiple_tx_fifo; | |
10aebc77 | 4620 | |
cff9eb75 MS |
4621 | dev_info(hsotg->dev, "EPs: %d, %s fifos, %d entries in SPRAM\n", |
4622 | hsotg->num_of_eps, | |
4623 | hsotg->dedicated_fifos ? "dedicated" : "shared", | |
4624 | hsotg->fifo_mem); | |
c6f5c050 | 4625 | return 0; |
5b7d70c6 BD |
4626 | } |
4627 | ||
8b9bc460 | 4628 | /** |
1f91b4cc | 4629 | * dwc2_hsotg_dump - dump state of the udc |
6fb914d7 GT |
4630 | * @hsotg: Programming view of the DWC_otg controller |
4631 | * | |
8b9bc460 | 4632 | */ |
1f91b4cc | 4633 | static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 4634 | { |
83a01804 | 4635 | #ifdef DEBUG |
5b7d70c6 | 4636 | struct device *dev = hsotg->dev; |
5b7d70c6 BD |
4637 | u32 val; |
4638 | int idx; | |
4639 | ||
4640 | dev_info(dev, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n", | |
f25c42b8 GS |
4641 | dwc2_readl(hsotg, DCFG), dwc2_readl(hsotg, DCTL), |
4642 | dwc2_readl(hsotg, DIEPMSK)); | |
5b7d70c6 | 4643 | |
f889f23d | 4644 | dev_info(dev, "GAHBCFG=0x%08x, GHWCFG1=0x%08x\n", |
f25c42b8 | 4645 | dwc2_readl(hsotg, GAHBCFG), dwc2_readl(hsotg, GHWCFG1)); |
5b7d70c6 BD |
4646 | |
4647 | dev_info(dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n", | |
f25c42b8 | 4648 | dwc2_readl(hsotg, GRXFSIZ), dwc2_readl(hsotg, GNPTXFSIZ)); |
5b7d70c6 BD |
4649 | |
4650 | /* show periodic fifo settings */ | |
4651 | ||
364f8e93 | 4652 | for (idx = 1; idx < hsotg->num_of_eps; idx++) { |
f25c42b8 | 4653 | val = dwc2_readl(hsotg, DPTXFSIZN(idx)); |
5b7d70c6 | 4654 | dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx, |
47a1685f DN |
4655 | val >> FIFOSIZE_DEPTH_SHIFT, |
4656 | val & FIFOSIZE_STARTADDR_MASK); | |
5b7d70c6 BD |
4657 | } |
4658 | ||
364f8e93 | 4659 | for (idx = 0; idx < hsotg->num_of_eps; idx++) { |
5b7d70c6 BD |
4660 | dev_info(dev, |
4661 | "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx, | |
f25c42b8 GS |
4662 | dwc2_readl(hsotg, DIEPCTL(idx)), |
4663 | dwc2_readl(hsotg, DIEPTSIZ(idx)), | |
4664 | dwc2_readl(hsotg, DIEPDMA(idx))); | |
5b7d70c6 | 4665 | |
f25c42b8 | 4666 | val = dwc2_readl(hsotg, DOEPCTL(idx)); |
5b7d70c6 BD |
4667 | dev_info(dev, |
4668 | "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", | |
f25c42b8 GS |
4669 | idx, dwc2_readl(hsotg, DOEPCTL(idx)), |
4670 | dwc2_readl(hsotg, DOEPTSIZ(idx)), | |
4671 | dwc2_readl(hsotg, DOEPDMA(idx))); | |
5b7d70c6 BD |
4672 | } |
4673 | ||
4674 | dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n", | |
f25c42b8 | 4675 | dwc2_readl(hsotg, DVBUSDIS), dwc2_readl(hsotg, DVBUSPULSE)); |
83a01804 | 4676 | #endif |
5b7d70c6 BD |
4677 | } |
4678 | ||
8b9bc460 | 4679 | /** |
117777b2 | 4680 | * dwc2_gadget_init - init function for gadget |
6fb914d7 GT |
4681 | * @hsotg: Programming view of the DWC_otg controller |
4682 | * | |
8b9bc460 | 4683 | */ |
f3768997 | 4684 | int dwc2_gadget_init(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 4685 | { |
117777b2 | 4686 | struct device *dev = hsotg->dev; |
5b7d70c6 BD |
4687 | int epnum; |
4688 | int ret; | |
43e90349 | 4689 | |
0a176279 GH |
4690 | /* Dump fifo information */ |
4691 | dev_dbg(dev, "NonPeriodic TXFIFO size: %d\n", | |
05ee799f JY |
4692 | hsotg->params.g_np_tx_fifo_size); |
4693 | dev_dbg(dev, "RXFIFO size: %d\n", hsotg->params.g_rx_fifo_size); | |
5b7d70c6 | 4694 | |
d327ab5b | 4695 | hsotg->gadget.max_speed = USB_SPEED_HIGH; |
1f91b4cc | 4696 | hsotg->gadget.ops = &dwc2_hsotg_gadget_ops; |
5b7d70c6 | 4697 | hsotg->gadget.name = dev_name(dev); |
fa389a6d | 4698 | hsotg->remote_wakeup_allowed = 0; |
7455f8b7 JY |
4699 | |
4700 | if (hsotg->params.lpm) | |
4701 | hsotg->gadget.lpm_capable = true; | |
4702 | ||
097ee662 GH |
4703 | if (hsotg->dr_mode == USB_DR_MODE_OTG) |
4704 | hsotg->gadget.is_otg = 1; | |
ec4cc657 MYK |
4705 | else if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) |
4706 | hsotg->op_state = OTG_STATE_B_PERIPHERAL; | |
5b7d70c6 | 4707 | |
1f91b4cc | 4708 | ret = dwc2_hsotg_hw_cfg(hsotg); |
c6f5c050 MYK |
4709 | if (ret) { |
4710 | dev_err(hsotg->dev, "Hardware configuration failed: %d\n", ret); | |
09a75e85 | 4711 | return ret; |
c6f5c050 MYK |
4712 | } |
4713 | ||
3f95001d MYK |
4714 | hsotg->ctrl_buff = devm_kzalloc(hsotg->dev, |
4715 | DWC2_CTRL_BUFF_SIZE, GFP_KERNEL); | |
8bae0f8c | 4716 | if (!hsotg->ctrl_buff) |
09a75e85 | 4717 | return -ENOMEM; |
3f95001d MYK |
4718 | |
4719 | hsotg->ep0_buff = devm_kzalloc(hsotg->dev, | |
4720 | DWC2_CTRL_BUFF_SIZE, GFP_KERNEL); | |
8bae0f8c | 4721 | if (!hsotg->ep0_buff) |
09a75e85 | 4722 | return -ENOMEM; |
3f95001d | 4723 | |
0f6b80c0 VA |
4724 | if (using_desc_dma(hsotg)) { |
4725 | ret = dwc2_gadget_alloc_ctrl_desc_chains(hsotg); | |
4726 | if (ret < 0) | |
4727 | return ret; | |
4728 | } | |
4729 | ||
f3768997 VM |
4730 | ret = devm_request_irq(hsotg->dev, hsotg->irq, dwc2_hsotg_irq, |
4731 | IRQF_SHARED, dev_name(hsotg->dev), hsotg); | |
eb3c56c5 | 4732 | if (ret < 0) { |
db8178c3 | 4733 | dev_err(dev, "cannot claim IRQ for gadget\n"); |
09a75e85 | 4734 | return ret; |
eb3c56c5 MS |
4735 | } |
4736 | ||
b3f489b2 LM |
4737 | /* hsotg->num_of_eps holds number of EPs other than ep0 */ |
4738 | ||
4739 | if (hsotg->num_of_eps == 0) { | |
4740 | dev_err(dev, "wrong number of EPs (zero)\n"); | |
09a75e85 | 4741 | return -EINVAL; |
b3f489b2 LM |
4742 | } |
4743 | ||
b3f489b2 LM |
4744 | /* setup endpoint information */ |
4745 | ||
4746 | INIT_LIST_HEAD(&hsotg->gadget.ep_list); | |
c6f5c050 | 4747 | hsotg->gadget.ep0 = &hsotg->eps_out[0]->ep; |
b3f489b2 LM |
4748 | |
4749 | /* allocate EP0 request */ | |
4750 | ||
1f91b4cc | 4751 | hsotg->ctrl_req = dwc2_hsotg_ep_alloc_request(&hsotg->eps_out[0]->ep, |
b3f489b2 LM |
4752 | GFP_KERNEL); |
4753 | if (!hsotg->ctrl_req) { | |
4754 | dev_err(dev, "failed to allocate ctrl req\n"); | |
09a75e85 | 4755 | return -ENOMEM; |
b3f489b2 | 4756 | } |
5b7d70c6 BD |
4757 | |
4758 | /* initialise the endpoints now the core has been initialised */ | |
c6f5c050 MYK |
4759 | for (epnum = 0; epnum < hsotg->num_of_eps; epnum++) { |
4760 | if (hsotg->eps_in[epnum]) | |
1f91b4cc | 4761 | dwc2_hsotg_initep(hsotg, hsotg->eps_in[epnum], |
9da51974 | 4762 | epnum, 1); |
c6f5c050 | 4763 | if (hsotg->eps_out[epnum]) |
1f91b4cc | 4764 | dwc2_hsotg_initep(hsotg, hsotg->eps_out[epnum], |
9da51974 | 4765 | epnum, 0); |
c6f5c050 | 4766 | } |
5b7d70c6 | 4767 | |
117777b2 | 4768 | ret = usb_add_gadget_udc(dev, &hsotg->gadget); |
9bb073a0 GT |
4769 | if (ret) { |
4770 | dwc2_hsotg_ep_free_request(&hsotg->eps_out[0]->ep, | |
4771 | hsotg->ctrl_req); | |
09a75e85 | 4772 | return ret; |
9bb073a0 | 4773 | } |
1f91b4cc | 4774 | dwc2_hsotg_dump(hsotg); |
5b7d70c6 | 4775 | |
5b7d70c6 | 4776 | return 0; |
5b7d70c6 BD |
4777 | } |
4778 | ||
8b9bc460 | 4779 | /** |
1f91b4cc | 4780 | * dwc2_hsotg_remove - remove function for hsotg driver |
6fb914d7 GT |
4781 | * @hsotg: Programming view of the DWC_otg controller |
4782 | * | |
8b9bc460 | 4783 | */ |
1f91b4cc | 4784 | int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 4785 | { |
0f91349b | 4786 | usb_del_gadget_udc(&hsotg->gadget); |
9bb073a0 | 4787 | dwc2_hsotg_ep_free_request(&hsotg->eps_out[0]->ep, hsotg->ctrl_req); |
31ee04de | 4788 | |
5b7d70c6 BD |
4789 | return 0; |
4790 | } | |
4791 | ||
1f91b4cc | 4792 | int dwc2_hsotg_suspend(struct dwc2_hsotg *hsotg) |
b83e333a | 4793 | { |
b83e333a | 4794 | unsigned long flags; |
b83e333a | 4795 | |
9e779778 | 4796 | if (hsotg->lx_state != DWC2_L0) |
09a75e85 | 4797 | return 0; |
9e779778 | 4798 | |
dc6e69e6 MS |
4799 | if (hsotg->driver) { |
4800 | int ep; | |
4801 | ||
b83e333a MS |
4802 | dev_info(hsotg->dev, "suspending usb gadget %s\n", |
4803 | hsotg->driver->driver.name); | |
4804 | ||
dc6e69e6 MS |
4805 | spin_lock_irqsave(&hsotg->lock, flags); |
4806 | if (hsotg->enabled) | |
1f91b4cc FB |
4807 | dwc2_hsotg_core_disconnect(hsotg); |
4808 | dwc2_hsotg_disconnect(hsotg); | |
dc6e69e6 MS |
4809 | hsotg->gadget.speed = USB_SPEED_UNKNOWN; |
4810 | spin_unlock_irqrestore(&hsotg->lock, flags); | |
b83e333a | 4811 | |
c6f5c050 MYK |
4812 | for (ep = 0; ep < hsotg->num_of_eps; ep++) { |
4813 | if (hsotg->eps_in[ep]) | |
1f91b4cc | 4814 | dwc2_hsotg_ep_disable(&hsotg->eps_in[ep]->ep); |
c6f5c050 | 4815 | if (hsotg->eps_out[ep]) |
1f91b4cc | 4816 | dwc2_hsotg_ep_disable(&hsotg->eps_out[ep]->ep); |
c6f5c050 | 4817 | } |
b83e333a MS |
4818 | } |
4819 | ||
09a75e85 | 4820 | return 0; |
b83e333a MS |
4821 | } |
4822 | ||
1f91b4cc | 4823 | int dwc2_hsotg_resume(struct dwc2_hsotg *hsotg) |
b83e333a | 4824 | { |
b83e333a | 4825 | unsigned long flags; |
b83e333a | 4826 | |
9e779778 | 4827 | if (hsotg->lx_state == DWC2_L2) |
09a75e85 | 4828 | return 0; |
9e779778 | 4829 | |
b83e333a MS |
4830 | if (hsotg->driver) { |
4831 | dev_info(hsotg->dev, "resuming usb gadget %s\n", | |
4832 | hsotg->driver->driver.name); | |
d00b4142 | 4833 | |
dc6e69e6 | 4834 | spin_lock_irqsave(&hsotg->lock, flags); |
1f91b4cc | 4835 | dwc2_hsotg_core_init_disconnected(hsotg, false); |
66e77a24 RK |
4836 | if (hsotg->enabled) { |
4837 | /* Enable ACG feature in device mode,if supported */ | |
4838 | dwc2_enable_acg(hsotg); | |
1f91b4cc | 4839 | dwc2_hsotg_core_connect(hsotg); |
66e77a24 | 4840 | } |
dc6e69e6 MS |
4841 | spin_unlock_irqrestore(&hsotg->lock, flags); |
4842 | } | |
b83e333a | 4843 | |
09a75e85 | 4844 | return 0; |
b83e333a | 4845 | } |
58e52ff6 JY |
4846 | |
4847 | /** | |
4848 | * dwc2_backup_device_registers() - Backup controller device registers. | |
4849 | * When suspending usb bus, registers needs to be backuped | |
4850 | * if controller power is disabled once suspended. | |
4851 | * | |
4852 | * @hsotg: Programming view of the DWC_otg controller | |
4853 | */ | |
4854 | int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg) | |
4855 | { | |
4856 | struct dwc2_dregs_backup *dr; | |
4857 | int i; | |
4858 | ||
4859 | dev_dbg(hsotg->dev, "%s\n", __func__); | |
4860 | ||
4861 | /* Backup dev regs */ | |
4862 | dr = &hsotg->dr_backup; | |
4863 | ||
f25c42b8 GS |
4864 | dr->dcfg = dwc2_readl(hsotg, DCFG); |
4865 | dr->dctl = dwc2_readl(hsotg, DCTL); | |
4866 | dr->daintmsk = dwc2_readl(hsotg, DAINTMSK); | |
4867 | dr->diepmsk = dwc2_readl(hsotg, DIEPMSK); | |
4868 | dr->doepmsk = dwc2_readl(hsotg, DOEPMSK); | |
58e52ff6 JY |
4869 | |
4870 | for (i = 0; i < hsotg->num_of_eps; i++) { | |
4871 | /* Backup IN EPs */ | |
f25c42b8 | 4872 | dr->diepctl[i] = dwc2_readl(hsotg, DIEPCTL(i)); |
58e52ff6 JY |
4873 | |
4874 | /* Ensure DATA PID is correctly configured */ | |
4875 | if (dr->diepctl[i] & DXEPCTL_DPID) | |
4876 | dr->diepctl[i] |= DXEPCTL_SETD1PID; | |
4877 | else | |
4878 | dr->diepctl[i] |= DXEPCTL_SETD0PID; | |
4879 | ||
f25c42b8 GS |
4880 | dr->dieptsiz[i] = dwc2_readl(hsotg, DIEPTSIZ(i)); |
4881 | dr->diepdma[i] = dwc2_readl(hsotg, DIEPDMA(i)); | |
58e52ff6 JY |
4882 | |
4883 | /* Backup OUT EPs */ | |
f25c42b8 | 4884 | dr->doepctl[i] = dwc2_readl(hsotg, DOEPCTL(i)); |
58e52ff6 JY |
4885 | |
4886 | /* Ensure DATA PID is correctly configured */ | |
4887 | if (dr->doepctl[i] & DXEPCTL_DPID) | |
4888 | dr->doepctl[i] |= DXEPCTL_SETD1PID; | |
4889 | else | |
4890 | dr->doepctl[i] |= DXEPCTL_SETD0PID; | |
4891 | ||
f25c42b8 GS |
4892 | dr->doeptsiz[i] = dwc2_readl(hsotg, DOEPTSIZ(i)); |
4893 | dr->doepdma[i] = dwc2_readl(hsotg, DOEPDMA(i)); | |
4894 | dr->dtxfsiz[i] = dwc2_readl(hsotg, DPTXFSIZN(i)); | |
58e52ff6 JY |
4895 | } |
4896 | dr->valid = true; | |
4897 | return 0; | |
4898 | } | |
4899 | ||
4900 | /** | |
4901 | * dwc2_restore_device_registers() - Restore controller device registers. | |
4902 | * When resuming usb bus, device registers needs to be restored | |
4903 | * if controller power were disabled. | |
4904 | * | |
4905 | * @hsotg: Programming view of the DWC_otg controller | |
9a5d2816 VM |
4906 | * @remote_wakeup: Indicates whether resume is initiated by Device or Host. |
4907 | * | |
4908 | * Return: 0 if successful, negative error code otherwise | |
58e52ff6 | 4909 | */ |
9a5d2816 | 4910 | int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg, int remote_wakeup) |
58e52ff6 JY |
4911 | { |
4912 | struct dwc2_dregs_backup *dr; | |
58e52ff6 JY |
4913 | int i; |
4914 | ||
4915 | dev_dbg(hsotg->dev, "%s\n", __func__); | |
4916 | ||
4917 | /* Restore dev regs */ | |
4918 | dr = &hsotg->dr_backup; | |
4919 | if (!dr->valid) { | |
4920 | dev_err(hsotg->dev, "%s: no device registers to restore\n", | |
4921 | __func__); | |
4922 | return -EINVAL; | |
4923 | } | |
4924 | dr->valid = false; | |
4925 | ||
9a5d2816 | 4926 | if (!remote_wakeup) |
f25c42b8 | 4927 | dwc2_writel(hsotg, dr->dctl, DCTL); |
9a5d2816 | 4928 | |
f25c42b8 GS |
4929 | dwc2_writel(hsotg, dr->daintmsk, DAINTMSK); |
4930 | dwc2_writel(hsotg, dr->diepmsk, DIEPMSK); | |
4931 | dwc2_writel(hsotg, dr->doepmsk, DOEPMSK); | |
58e52ff6 JY |
4932 | |
4933 | for (i = 0; i < hsotg->num_of_eps; i++) { | |
4934 | /* Restore IN EPs */ | |
f25c42b8 GS |
4935 | dwc2_writel(hsotg, dr->dieptsiz[i], DIEPTSIZ(i)); |
4936 | dwc2_writel(hsotg, dr->diepdma[i], DIEPDMA(i)); | |
4937 | dwc2_writel(hsotg, dr->doeptsiz[i], DOEPTSIZ(i)); | |
9a5d2816 VM |
4938 | /** WA for enabled EPx's IN in DDMA mode. On entering to |
4939 | * hibernation wrong value read and saved from DIEPDMAx, | |
4940 | * as result BNA interrupt asserted on hibernation exit | |
4941 | * by restoring from saved area. | |
4942 | */ | |
4943 | if (hsotg->params.g_dma_desc && | |
4944 | (dr->diepctl[i] & DXEPCTL_EPENA)) | |
4945 | dr->diepdma[i] = hsotg->eps_in[i]->desc_list_dma; | |
f25c42b8 GS |
4946 | dwc2_writel(hsotg, dr->dtxfsiz[i], DPTXFSIZN(i)); |
4947 | dwc2_writel(hsotg, dr->diepctl[i], DIEPCTL(i)); | |
58e52ff6 | 4948 | /* Restore OUT EPs */ |
f25c42b8 | 4949 | dwc2_writel(hsotg, dr->doeptsiz[i], DOEPTSIZ(i)); |
9a5d2816 VM |
4950 | /* WA for enabled EPx's OUT in DDMA mode. On entering to |
4951 | * hibernation wrong value read and saved from DOEPDMAx, | |
4952 | * as result BNA interrupt asserted on hibernation exit | |
4953 | * by restoring from saved area. | |
4954 | */ | |
4955 | if (hsotg->params.g_dma_desc && | |
4956 | (dr->doepctl[i] & DXEPCTL_EPENA)) | |
4957 | dr->doepdma[i] = hsotg->eps_out[i]->desc_list_dma; | |
f25c42b8 GS |
4958 | dwc2_writel(hsotg, dr->doepdma[i], DOEPDMA(i)); |
4959 | dwc2_writel(hsotg, dr->doepctl[i], DOEPCTL(i)); | |
58e52ff6 JY |
4960 | } |
4961 | ||
58e52ff6 JY |
4962 | return 0; |
4963 | } | |
21b03405 SA |
4964 | |
4965 | /** | |
4966 | * dwc2_gadget_init_lpm - Configure the core to support LPM in device mode | |
4967 | * | |
4968 | * @hsotg: Programming view of DWC_otg controller | |
4969 | * | |
4970 | */ | |
4971 | void dwc2_gadget_init_lpm(struct dwc2_hsotg *hsotg) | |
4972 | { | |
4973 | u32 val; | |
4974 | ||
4975 | if (!hsotg->params.lpm) | |
4976 | return; | |
4977 | ||
4978 | val = GLPMCFG_LPMCAP | GLPMCFG_APPL1RES; | |
4979 | val |= hsotg->params.hird_threshold_en ? GLPMCFG_HIRD_THRES_EN : 0; | |
4980 | val |= hsotg->params.lpm_clock_gating ? GLPMCFG_ENBLSLPM : 0; | |
4981 | val |= hsotg->params.hird_threshold << GLPMCFG_HIRD_THRES_SHIFT; | |
4982 | val |= hsotg->params.besl ? GLPMCFG_ENBESL : 0; | |
f25c42b8 GS |
4983 | dwc2_writel(hsotg, val, GLPMCFG); |
4984 | dev_dbg(hsotg->dev, "GLPMCFG=0x%08x\n", dwc2_readl(hsotg, GLPMCFG)); | |
21b03405 | 4985 | } |
c5c403dc VM |
4986 | |
4987 | /** | |
4988 | * dwc2_gadget_enter_hibernation() - Put controller in Hibernation. | |
4989 | * | |
4990 | * @hsotg: Programming view of the DWC_otg controller | |
4991 | * | |
4992 | * Return non-zero if failed to enter to hibernation. | |
4993 | */ | |
4994 | int dwc2_gadget_enter_hibernation(struct dwc2_hsotg *hsotg) | |
4995 | { | |
4996 | u32 gpwrdn; | |
4997 | int ret = 0; | |
4998 | ||
4999 | /* Change to L2(suspend) state */ | |
5000 | hsotg->lx_state = DWC2_L2; | |
5001 | dev_dbg(hsotg->dev, "Start of hibernation completed\n"); | |
5002 | ret = dwc2_backup_global_registers(hsotg); | |
5003 | if (ret) { | |
5004 | dev_err(hsotg->dev, "%s: failed to backup global registers\n", | |
5005 | __func__); | |
5006 | return ret; | |
5007 | } | |
5008 | ret = dwc2_backup_device_registers(hsotg); | |
5009 | if (ret) { | |
5010 | dev_err(hsotg->dev, "%s: failed to backup device registers\n", | |
5011 | __func__); | |
5012 | return ret; | |
5013 | } | |
5014 | ||
5015 | gpwrdn = GPWRDN_PWRDNRSTN; | |
5016 | gpwrdn |= GPWRDN_PMUACTV; | |
f25c42b8 | 5017 | dwc2_writel(hsotg, gpwrdn, GPWRDN); |
c5c403dc VM |
5018 | udelay(10); |
5019 | ||
5020 | /* Set flag to indicate that we are in hibernation */ | |
5021 | hsotg->hibernated = 1; | |
5022 | ||
5023 | /* Enable interrupts from wake up logic */ | |
f25c42b8 | 5024 | gpwrdn = dwc2_readl(hsotg, GPWRDN); |
c5c403dc | 5025 | gpwrdn |= GPWRDN_PMUINTSEL; |
f25c42b8 | 5026 | dwc2_writel(hsotg, gpwrdn, GPWRDN); |
c5c403dc VM |
5027 | udelay(10); |
5028 | ||
5029 | /* Unmask device mode interrupts in GPWRDN */ | |
f25c42b8 | 5030 | gpwrdn = dwc2_readl(hsotg, GPWRDN); |
c5c403dc VM |
5031 | gpwrdn |= GPWRDN_RST_DET_MSK; |
5032 | gpwrdn |= GPWRDN_LNSTSCHG_MSK; | |
5033 | gpwrdn |= GPWRDN_STS_CHGINT_MSK; | |
f25c42b8 | 5034 | dwc2_writel(hsotg, gpwrdn, GPWRDN); |
c5c403dc VM |
5035 | udelay(10); |
5036 | ||
5037 | /* Enable Power Down Clamp */ | |
f25c42b8 | 5038 | gpwrdn = dwc2_readl(hsotg, GPWRDN); |
c5c403dc | 5039 | gpwrdn |= GPWRDN_PWRDNCLMP; |
f25c42b8 | 5040 | dwc2_writel(hsotg, gpwrdn, GPWRDN); |
c5c403dc VM |
5041 | udelay(10); |
5042 | ||
5043 | /* Switch off VDD */ | |
f25c42b8 | 5044 | gpwrdn = dwc2_readl(hsotg, GPWRDN); |
c5c403dc | 5045 | gpwrdn |= GPWRDN_PWRDNSWTCH; |
f25c42b8 | 5046 | dwc2_writel(hsotg, gpwrdn, GPWRDN); |
c5c403dc VM |
5047 | udelay(10); |
5048 | ||
5049 | /* Save gpwrdn register for further usage if stschng interrupt */ | |
f25c42b8 | 5050 | hsotg->gr_backup.gpwrdn = dwc2_readl(hsotg, GPWRDN); |
c5c403dc VM |
5051 | dev_dbg(hsotg->dev, "Hibernation completed\n"); |
5052 | ||
5053 | return ret; | |
5054 | } | |
5055 | ||
5056 | /** | |
5057 | * dwc2_gadget_exit_hibernation() | |
5058 | * This function is for exiting from Device mode hibernation by host initiated | |
5059 | * resume/reset and device initiated remote-wakeup. | |
5060 | * | |
5061 | * @hsotg: Programming view of the DWC_otg controller | |
5062 | * @rem_wakeup: indicates whether resume is initiated by Device or Host. | |
6fb914d7 | 5063 | * @reset: indicates whether resume is initiated by Reset. |
c5c403dc VM |
5064 | * |
5065 | * Return non-zero if failed to exit from hibernation. | |
5066 | */ | |
5067 | int dwc2_gadget_exit_hibernation(struct dwc2_hsotg *hsotg, | |
5068 | int rem_wakeup, int reset) | |
5069 | { | |
5070 | u32 pcgcctl; | |
5071 | u32 gpwrdn; | |
5072 | u32 dctl; | |
5073 | int ret = 0; | |
5074 | struct dwc2_gregs_backup *gr; | |
5075 | struct dwc2_dregs_backup *dr; | |
5076 | ||
5077 | gr = &hsotg->gr_backup; | |
5078 | dr = &hsotg->dr_backup; | |
5079 | ||
5080 | if (!hsotg->hibernated) { | |
5081 | dev_dbg(hsotg->dev, "Already exited from Hibernation\n"); | |
5082 | return 1; | |
5083 | } | |
5084 | dev_dbg(hsotg->dev, | |
5085 | "%s: called with rem_wakeup = %d reset = %d\n", | |
5086 | __func__, rem_wakeup, reset); | |
5087 | ||
5088 | dwc2_hib_restore_common(hsotg, rem_wakeup, 0); | |
5089 | ||
5090 | if (!reset) { | |
5091 | /* Clear all pending interupts */ | |
f25c42b8 | 5092 | dwc2_writel(hsotg, 0xffffffff, GINTSTS); |
c5c403dc VM |
5093 | } |
5094 | ||
5095 | /* De-assert Restore */ | |
f25c42b8 | 5096 | gpwrdn = dwc2_readl(hsotg, GPWRDN); |
c5c403dc | 5097 | gpwrdn &= ~GPWRDN_RESTORE; |
f25c42b8 | 5098 | dwc2_writel(hsotg, gpwrdn, GPWRDN); |
c5c403dc VM |
5099 | udelay(10); |
5100 | ||
5101 | if (!rem_wakeup) { | |
f25c42b8 | 5102 | pcgcctl = dwc2_readl(hsotg, PCGCTL); |
c5c403dc | 5103 | pcgcctl &= ~PCGCTL_RSTPDWNMODULE; |
f25c42b8 | 5104 | dwc2_writel(hsotg, pcgcctl, PCGCTL); |
c5c403dc VM |
5105 | } |
5106 | ||
5107 | /* Restore GUSBCFG, DCFG and DCTL */ | |
f25c42b8 GS |
5108 | dwc2_writel(hsotg, gr->gusbcfg, GUSBCFG); |
5109 | dwc2_writel(hsotg, dr->dcfg, DCFG); | |
5110 | dwc2_writel(hsotg, dr->dctl, DCTL); | |
c5c403dc VM |
5111 | |
5112 | /* De-assert Wakeup Logic */ | |
f25c42b8 | 5113 | gpwrdn = dwc2_readl(hsotg, GPWRDN); |
c5c403dc | 5114 | gpwrdn &= ~GPWRDN_PMUACTV; |
f25c42b8 | 5115 | dwc2_writel(hsotg, gpwrdn, GPWRDN); |
c5c403dc VM |
5116 | |
5117 | if (rem_wakeup) { | |
5118 | udelay(10); | |
5119 | /* Start Remote Wakeup Signaling */ | |
f25c42b8 | 5120 | dwc2_writel(hsotg, dr->dctl | DCTL_RMTWKUPSIG, DCTL); |
c5c403dc VM |
5121 | } else { |
5122 | udelay(50); | |
5123 | /* Set Device programming done bit */ | |
f25c42b8 | 5124 | dctl = dwc2_readl(hsotg, DCTL); |
c5c403dc | 5125 | dctl |= DCTL_PWRONPRGDONE; |
f25c42b8 | 5126 | dwc2_writel(hsotg, dctl, DCTL); |
c5c403dc VM |
5127 | } |
5128 | /* Wait for interrupts which must be cleared */ | |
5129 | mdelay(2); | |
5130 | /* Clear all pending interupts */ | |
f25c42b8 | 5131 | dwc2_writel(hsotg, 0xffffffff, GINTSTS); |
c5c403dc VM |
5132 | |
5133 | /* Restore global registers */ | |
5134 | ret = dwc2_restore_global_registers(hsotg); | |
5135 | if (ret) { | |
5136 | dev_err(hsotg->dev, "%s: failed to restore registers\n", | |
5137 | __func__); | |
5138 | return ret; | |
5139 | } | |
5140 | ||
5141 | /* Restore device registers */ | |
5142 | ret = dwc2_restore_device_registers(hsotg, rem_wakeup); | |
5143 | if (ret) { | |
5144 | dev_err(hsotg->dev, "%s: failed to restore device registers\n", | |
5145 | __func__); | |
5146 | return ret; | |
5147 | } | |
5148 | ||
5149 | if (rem_wakeup) { | |
5150 | mdelay(10); | |
f25c42b8 | 5151 | dctl = dwc2_readl(hsotg, DCTL); |
c5c403dc | 5152 | dctl &= ~DCTL_RMTWKUPSIG; |
f25c42b8 | 5153 | dwc2_writel(hsotg, dctl, DCTL); |
c5c403dc VM |
5154 | } |
5155 | ||
5156 | hsotg->hibernated = 0; | |
5157 | hsotg->lx_state = DWC2_L0; | |
5158 | dev_dbg(hsotg->dev, "Hibernation recovery completes here\n"); | |
5159 | ||
5160 | return ret; | |
5161 | } |