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5fd54ace | 1 | // SPDX-License-Identifier: GPL-2.0 |
6fb914d7 | 2 | /* |
dfbc6fa3 AT |
3 | * Copyright (c) 2011 Samsung Electronics Co., Ltd. |
4 | * http://www.samsung.com | |
5b7d70c6 BD |
5 | * |
6 | * Copyright 2008 Openmoko, Inc. | |
7 | * Copyright 2008 Simtec Electronics | |
8 | * Ben Dooks <ben@simtec.co.uk> | |
9 | * http://armlinux.simtec.co.uk/ | |
10 | * | |
11 | * S3C USB2.0 High-speed / OtG driver | |
8b9bc460 | 12 | */ |
5b7d70c6 BD |
13 | |
14 | #include <linux/kernel.h> | |
15 | #include <linux/module.h> | |
16 | #include <linux/spinlock.h> | |
17 | #include <linux/interrupt.h> | |
18 | #include <linux/platform_device.h> | |
19 | #include <linux/dma-mapping.h> | |
7ad8096e | 20 | #include <linux/mutex.h> |
5b7d70c6 BD |
21 | #include <linux/seq_file.h> |
22 | #include <linux/delay.h> | |
23 | #include <linux/io.h> | |
5a0e3ad6 | 24 | #include <linux/slab.h> |
c50f056c | 25 | #include <linux/of_platform.h> |
5b7d70c6 BD |
26 | |
27 | #include <linux/usb/ch9.h> | |
28 | #include <linux/usb/gadget.h> | |
b2e587db | 29 | #include <linux/usb/phy.h> |
b4c53b4a MH |
30 | #include <linux/usb/composite.h> |
31 | ||
5b7d70c6 | 32 | |
f7c0b143 | 33 | #include "core.h" |
941fcce4 | 34 | #include "hw.h" |
5b7d70c6 BD |
35 | |
36 | /* conversion functions */ | |
1f91b4cc | 37 | static inline struct dwc2_hsotg_req *our_req(struct usb_request *req) |
5b7d70c6 | 38 | { |
1f91b4cc | 39 | return container_of(req, struct dwc2_hsotg_req, req); |
5b7d70c6 BD |
40 | } |
41 | ||
1f91b4cc | 42 | static inline struct dwc2_hsotg_ep *our_ep(struct usb_ep *ep) |
5b7d70c6 | 43 | { |
1f91b4cc | 44 | return container_of(ep, struct dwc2_hsotg_ep, ep); |
5b7d70c6 BD |
45 | } |
46 | ||
941fcce4 | 47 | static inline struct dwc2_hsotg *to_hsotg(struct usb_gadget *gadget) |
5b7d70c6 | 48 | { |
941fcce4 | 49 | return container_of(gadget, struct dwc2_hsotg, gadget); |
5b7d70c6 BD |
50 | } |
51 | ||
f25c42b8 | 52 | static inline void dwc2_set_bit(struct dwc2_hsotg *hsotg, u32 offset, u32 val) |
5b7d70c6 | 53 | { |
f25c42b8 | 54 | dwc2_writel(hsotg, dwc2_readl(hsotg, offset) | val, offset); |
5b7d70c6 BD |
55 | } |
56 | ||
f25c42b8 | 57 | static inline void dwc2_clear_bit(struct dwc2_hsotg *hsotg, u32 offset, u32 val) |
5b7d70c6 | 58 | { |
f25c42b8 | 59 | dwc2_writel(hsotg, dwc2_readl(hsotg, offset) & ~val, offset); |
5b7d70c6 BD |
60 | } |
61 | ||
1f91b4cc | 62 | static inline struct dwc2_hsotg_ep *index_to_ep(struct dwc2_hsotg *hsotg, |
c6f5c050 MYK |
63 | u32 ep_index, u32 dir_in) |
64 | { | |
65 | if (dir_in) | |
66 | return hsotg->eps_in[ep_index]; | |
67 | else | |
68 | return hsotg->eps_out[ep_index]; | |
69 | } | |
70 | ||
997f4f81 | 71 | /* forward declaration of functions */ |
1f91b4cc | 72 | static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg); |
5b7d70c6 BD |
73 | |
74 | /** | |
75 | * using_dma - return the DMA status of the driver. | |
76 | * @hsotg: The driver state. | |
77 | * | |
78 | * Return true if we're using DMA. | |
79 | * | |
80 | * Currently, we have the DMA support code worked into everywhere | |
81 | * that needs it, but the AMBA DMA implementation in the hardware can | |
82 | * only DMA from 32bit aligned addresses. This means that gadgets such | |
83 | * as the CDC Ethernet cannot work as they often pass packets which are | |
84 | * not 32bit aligned. | |
85 | * | |
86 | * Unfortunately the choice to use DMA or not is global to the controller | |
87 | * and seems to be only settable when the controller is being put through | |
88 | * a core reset. This means we either need to fix the gadgets to take | |
89 | * account of DMA alignment, or add bounce buffers (yuerk). | |
90 | * | |
edd74be8 | 91 | * g_using_dma is set depending on dts flag. |
5b7d70c6 | 92 | */ |
941fcce4 | 93 | static inline bool using_dma(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 94 | { |
05ee799f | 95 | return hsotg->params.g_dma; |
5b7d70c6 BD |
96 | } |
97 | ||
dec4b556 VA |
98 | /* |
99 | * using_desc_dma - return the descriptor DMA status of the driver. | |
100 | * @hsotg: The driver state. | |
101 | * | |
102 | * Return true if we're using descriptor DMA. | |
103 | */ | |
104 | static inline bool using_desc_dma(struct dwc2_hsotg *hsotg) | |
105 | { | |
106 | return hsotg->params.g_dma_desc; | |
107 | } | |
108 | ||
92d1635d VM |
109 | /** |
110 | * dwc2_gadget_incr_frame_num - Increments the targeted frame number. | |
111 | * @hs_ep: The endpoint | |
92d1635d VM |
112 | * |
113 | * This function will also check if the frame number overruns DSTS_SOFFN_LIMIT. | |
114 | * If an overrun occurs it will wrap the value and set the frame_overrun flag. | |
115 | */ | |
116 | static inline void dwc2_gadget_incr_frame_num(struct dwc2_hsotg_ep *hs_ep) | |
117 | { | |
118 | hs_ep->target_frame += hs_ep->interval; | |
119 | if (hs_ep->target_frame > DSTS_SOFFN_LIMIT) { | |
c1d5df69 | 120 | hs_ep->frame_overrun = true; |
92d1635d VM |
121 | hs_ep->target_frame &= DSTS_SOFFN_LIMIT; |
122 | } else { | |
c1d5df69 | 123 | hs_ep->frame_overrun = false; |
92d1635d VM |
124 | } |
125 | } | |
126 | ||
9d630b9c GT |
127 | /** |
128 | * dwc2_gadget_dec_frame_num_by_one - Decrements the targeted frame number | |
129 | * by one. | |
130 | * @hs_ep: The endpoint. | |
131 | * | |
132 | * This function used in service interval based scheduling flow to calculate | |
133 | * descriptor frame number filed value. For service interval mode frame | |
134 | * number in descriptor should point to last (u)frame in the interval. | |
135 | * | |
136 | */ | |
137 | static inline void dwc2_gadget_dec_frame_num_by_one(struct dwc2_hsotg_ep *hs_ep) | |
138 | { | |
139 | if (hs_ep->target_frame) | |
140 | hs_ep->target_frame -= 1; | |
141 | else | |
142 | hs_ep->target_frame = DSTS_SOFFN_LIMIT; | |
143 | } | |
144 | ||
5b7d70c6 | 145 | /** |
1f91b4cc | 146 | * dwc2_hsotg_en_gsint - enable one or more of the general interrupt |
5b7d70c6 BD |
147 | * @hsotg: The device state |
148 | * @ints: A bitmask of the interrupts to enable | |
149 | */ | |
1f91b4cc | 150 | static void dwc2_hsotg_en_gsint(struct dwc2_hsotg *hsotg, u32 ints) |
5b7d70c6 | 151 | { |
f25c42b8 | 152 | u32 gsintmsk = dwc2_readl(hsotg, GINTMSK); |
5b7d70c6 BD |
153 | u32 new_gsintmsk; |
154 | ||
155 | new_gsintmsk = gsintmsk | ints; | |
156 | ||
157 | if (new_gsintmsk != gsintmsk) { | |
158 | dev_dbg(hsotg->dev, "gsintmsk now 0x%08x\n", new_gsintmsk); | |
f25c42b8 | 159 | dwc2_writel(hsotg, new_gsintmsk, GINTMSK); |
5b7d70c6 BD |
160 | } |
161 | } | |
162 | ||
163 | /** | |
1f91b4cc | 164 | * dwc2_hsotg_disable_gsint - disable one or more of the general interrupt |
5b7d70c6 BD |
165 | * @hsotg: The device state |
166 | * @ints: A bitmask of the interrupts to enable | |
167 | */ | |
1f91b4cc | 168 | static void dwc2_hsotg_disable_gsint(struct dwc2_hsotg *hsotg, u32 ints) |
5b7d70c6 | 169 | { |
f25c42b8 | 170 | u32 gsintmsk = dwc2_readl(hsotg, GINTMSK); |
5b7d70c6 BD |
171 | u32 new_gsintmsk; |
172 | ||
173 | new_gsintmsk = gsintmsk & ~ints; | |
174 | ||
175 | if (new_gsintmsk != gsintmsk) | |
f25c42b8 | 176 | dwc2_writel(hsotg, new_gsintmsk, GINTMSK); |
5b7d70c6 BD |
177 | } |
178 | ||
179 | /** | |
1f91b4cc | 180 | * dwc2_hsotg_ctrl_epint - enable/disable an endpoint irq |
5b7d70c6 BD |
181 | * @hsotg: The device state |
182 | * @ep: The endpoint index | |
183 | * @dir_in: True if direction is in. | |
184 | * @en: The enable value, true to enable | |
185 | * | |
186 | * Set or clear the mask for an individual endpoint's interrupt | |
187 | * request. | |
188 | */ | |
1f91b4cc | 189 | static void dwc2_hsotg_ctrl_epint(struct dwc2_hsotg *hsotg, |
9da51974 | 190 | unsigned int ep, unsigned int dir_in, |
5b7d70c6 BD |
191 | unsigned int en) |
192 | { | |
193 | unsigned long flags; | |
194 | u32 bit = 1 << ep; | |
195 | u32 daint; | |
196 | ||
197 | if (!dir_in) | |
198 | bit <<= 16; | |
199 | ||
200 | local_irq_save(flags); | |
f25c42b8 | 201 | daint = dwc2_readl(hsotg, DAINTMSK); |
5b7d70c6 BD |
202 | if (en) |
203 | daint |= bit; | |
204 | else | |
205 | daint &= ~bit; | |
f25c42b8 | 206 | dwc2_writel(hsotg, daint, DAINTMSK); |
5b7d70c6 BD |
207 | local_irq_restore(flags); |
208 | } | |
209 | ||
c138ecfa SA |
210 | /** |
211 | * dwc2_hsotg_tx_fifo_count - return count of TX FIFOs in device mode | |
6fb914d7 GT |
212 | * |
213 | * @hsotg: Programming view of the DWC_otg controller | |
c138ecfa SA |
214 | */ |
215 | int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg *hsotg) | |
216 | { | |
217 | if (hsotg->hw_params.en_multiple_tx_fifo) | |
218 | /* In dedicated FIFO mode we need count of IN EPs */ | |
9273083a | 219 | return hsotg->hw_params.num_dev_in_eps; |
c138ecfa SA |
220 | else |
221 | /* In shared FIFO mode we need count of Periodic IN EPs */ | |
222 | return hsotg->hw_params.num_dev_perio_in_ep; | |
223 | } | |
224 | ||
c138ecfa SA |
225 | /** |
226 | * dwc2_hsotg_tx_fifo_total_depth - return total FIFO depth available for | |
227 | * device mode TX FIFOs | |
6fb914d7 GT |
228 | * |
229 | * @hsotg: Programming view of the DWC_otg controller | |
c138ecfa SA |
230 | */ |
231 | int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg) | |
232 | { | |
c138ecfa SA |
233 | int addr; |
234 | int tx_addr_max; | |
235 | u32 np_tx_fifo_size; | |
236 | ||
237 | np_tx_fifo_size = min_t(u32, hsotg->hw_params.dev_nperio_tx_fifo_size, | |
238 | hsotg->params.g_np_tx_fifo_size); | |
239 | ||
240 | /* Get Endpoint Info Control block size in DWORDs. */ | |
9273083a | 241 | tx_addr_max = hsotg->hw_params.total_fifo_size; |
c138ecfa SA |
242 | |
243 | addr = hsotg->params.g_rx_fifo_size + np_tx_fifo_size; | |
244 | if (tx_addr_max <= addr) | |
245 | return 0; | |
246 | ||
247 | return tx_addr_max - addr; | |
248 | } | |
249 | ||
187c5298 GT |
250 | /** |
251 | * dwc2_gadget_wkup_alert_handler - Handler for WKUP_ALERT interrupt | |
252 | * | |
253 | * @hsotg: Programming view of the DWC_otg controller | |
254 | * | |
255 | */ | |
256 | static void dwc2_gadget_wkup_alert_handler(struct dwc2_hsotg *hsotg) | |
257 | { | |
258 | u32 gintsts2; | |
259 | u32 gintmsk2; | |
260 | ||
261 | gintsts2 = dwc2_readl(hsotg, GINTSTS2); | |
262 | gintmsk2 = dwc2_readl(hsotg, GINTMSK2); | |
9607f3cd | 263 | gintsts2 &= gintmsk2; |
187c5298 GT |
264 | |
265 | if (gintsts2 & GINTSTS2_WKUP_ALERT_INT) { | |
266 | dev_dbg(hsotg->dev, "%s: Wkup_Alert_Int\n", __func__); | |
87b6d2c5 | 267 | dwc2_set_bit(hsotg, GINTSTS2, GINTSTS2_WKUP_ALERT_INT); |
d64bc8ee | 268 | dwc2_set_bit(hsotg, DCTL, DCTL_RMTWKUPSIG); |
187c5298 GT |
269 | } |
270 | } | |
271 | ||
c138ecfa SA |
272 | /** |
273 | * dwc2_hsotg_tx_fifo_average_depth - returns average depth of device mode | |
274 | * TX FIFOs | |
6fb914d7 GT |
275 | * |
276 | * @hsotg: Programming view of the DWC_otg controller | |
c138ecfa SA |
277 | */ |
278 | int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg *hsotg) | |
279 | { | |
280 | int tx_fifo_count; | |
281 | int tx_fifo_depth; | |
282 | ||
283 | tx_fifo_depth = dwc2_hsotg_tx_fifo_total_depth(hsotg); | |
284 | ||
285 | tx_fifo_count = dwc2_hsotg_tx_fifo_count(hsotg); | |
286 | ||
287 | if (!tx_fifo_count) | |
288 | return tx_fifo_depth; | |
289 | else | |
290 | return tx_fifo_depth / tx_fifo_count; | |
291 | } | |
292 | ||
5b7d70c6 | 293 | /** |
1f91b4cc | 294 | * dwc2_hsotg_init_fifo - initialise non-periodic FIFOs |
5b7d70c6 BD |
295 | * @hsotg: The device instance. |
296 | */ | |
1f91b4cc | 297 | static void dwc2_hsotg_init_fifo(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 298 | { |
2317eacd | 299 | unsigned int ep; |
0f002d20 | 300 | unsigned int addr; |
1703a6d3 | 301 | int timeout; |
79d6b8c5 | 302 | |
0f002d20 | 303 | u32 val; |
05ee799f | 304 | u32 *txfsz = hsotg->params.g_tx_fifo_size; |
0f002d20 | 305 | |
7fcbc95c GH |
306 | /* Reset fifo map if not correctly cleared during previous session */ |
307 | WARN_ON(hsotg->fifo_map); | |
308 | hsotg->fifo_map = 0; | |
309 | ||
0a176279 | 310 | /* set RX/NPTX FIFO sizes */ |
f25c42b8 GS |
311 | dwc2_writel(hsotg, hsotg->params.g_rx_fifo_size, GRXFSIZ); |
312 | dwc2_writel(hsotg, (hsotg->params.g_rx_fifo_size << | |
313 | FIFOSIZE_STARTADDR_SHIFT) | | |
05ee799f | 314 | (hsotg->params.g_np_tx_fifo_size << FIFOSIZE_DEPTH_SHIFT), |
f25c42b8 | 315 | GNPTXFSIZ); |
0f002d20 | 316 | |
8b9bc460 LM |
317 | /* |
318 | * arange all the rest of the TX FIFOs, as some versions of this | |
0f002d20 BD |
319 | * block have overlapping default addresses. This also ensures |
320 | * that if the settings have been changed, then they are set to | |
8b9bc460 LM |
321 | * known values. |
322 | */ | |
0f002d20 BD |
323 | |
324 | /* start at the end of the GNPTXFSIZ, rounded up */ | |
05ee799f | 325 | addr = hsotg->params.g_rx_fifo_size + hsotg->params.g_np_tx_fifo_size; |
0f002d20 | 326 | |
8b9bc460 | 327 | /* |
0a176279 | 328 | * Configure fifos sizes from provided configuration and assign |
b203d0a2 RB |
329 | * them to endpoints dynamically according to maxpacket size value of |
330 | * given endpoint. | |
8b9bc460 | 331 | */ |
2317eacd | 332 | for (ep = 1; ep < MAX_EPS_CHANNELS; ep++) { |
05ee799f | 333 | if (!txfsz[ep]) |
3fa95385 JY |
334 | continue; |
335 | val = addr; | |
05ee799f JY |
336 | val |= txfsz[ep] << FIFOSIZE_DEPTH_SHIFT; |
337 | WARN_ONCE(addr + txfsz[ep] > hsotg->fifo_mem, | |
3fa95385 | 338 | "insufficient fifo memory"); |
05ee799f | 339 | addr += txfsz[ep]; |
0f002d20 | 340 | |
f25c42b8 GS |
341 | dwc2_writel(hsotg, val, DPTXFSIZN(ep)); |
342 | val = dwc2_readl(hsotg, DPTXFSIZN(ep)); | |
0f002d20 | 343 | } |
1703a6d3 | 344 | |
f25c42b8 | 345 | dwc2_writel(hsotg, hsotg->hw_params.total_fifo_size | |
f87c842f | 346 | addr << GDFIFOCFG_EPINFOBASE_SHIFT, |
f25c42b8 | 347 | GDFIFOCFG); |
8b9bc460 LM |
348 | /* |
349 | * according to p428 of the design guide, we need to ensure that | |
350 | * all fifos are flushed before continuing | |
351 | */ | |
1703a6d3 | 352 | |
f25c42b8 GS |
353 | dwc2_writel(hsotg, GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH | |
354 | GRSTCTL_RXFFLSH, GRSTCTL); | |
1703a6d3 BD |
355 | |
356 | /* wait until the fifos are both flushed */ | |
357 | timeout = 100; | |
358 | while (1) { | |
f25c42b8 | 359 | val = dwc2_readl(hsotg, GRSTCTL); |
1703a6d3 | 360 | |
47a1685f | 361 | if ((val & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH)) == 0) |
1703a6d3 BD |
362 | break; |
363 | ||
364 | if (--timeout == 0) { | |
365 | dev_err(hsotg->dev, | |
366 | "%s: timeout flushing fifos (GRSTCTL=%08x)\n", | |
367 | __func__, val); | |
48b20bcb | 368 | break; |
1703a6d3 BD |
369 | } |
370 | ||
371 | udelay(1); | |
372 | } | |
373 | ||
374 | dev_dbg(hsotg->dev, "FIFOs reset, timeout at %d\n", timeout); | |
5b7d70c6 BD |
375 | } |
376 | ||
377 | /** | |
6fb914d7 | 378 | * dwc2_hsotg_ep_alloc_request - allocate USB rerequest structure |
5b7d70c6 BD |
379 | * @ep: USB endpoint to allocate request for. |
380 | * @flags: Allocation flags | |
381 | * | |
382 | * Allocate a new USB request structure appropriate for the specified endpoint | |
383 | */ | |
1f91b4cc | 384 | static struct usb_request *dwc2_hsotg_ep_alloc_request(struct usb_ep *ep, |
9da51974 | 385 | gfp_t flags) |
5b7d70c6 | 386 | { |
1f91b4cc | 387 | struct dwc2_hsotg_req *req; |
5b7d70c6 | 388 | |
ec33efe2 | 389 | req = kzalloc(sizeof(*req), flags); |
5b7d70c6 BD |
390 | if (!req) |
391 | return NULL; | |
392 | ||
393 | INIT_LIST_HEAD(&req->queue); | |
394 | ||
5b7d70c6 BD |
395 | return &req->req; |
396 | } | |
397 | ||
398 | /** | |
399 | * is_ep_periodic - return true if the endpoint is in periodic mode. | |
400 | * @hs_ep: The endpoint to query. | |
401 | * | |
402 | * Returns true if the endpoint is in periodic mode, meaning it is being | |
403 | * used for an Interrupt or ISO transfer. | |
404 | */ | |
1f91b4cc | 405 | static inline int is_ep_periodic(struct dwc2_hsotg_ep *hs_ep) |
5b7d70c6 BD |
406 | { |
407 | return hs_ep->periodic; | |
408 | } | |
409 | ||
410 | /** | |
1f91b4cc | 411 | * dwc2_hsotg_unmap_dma - unmap the DMA memory being used for the request |
5b7d70c6 BD |
412 | * @hsotg: The device state. |
413 | * @hs_ep: The endpoint for the request | |
414 | * @hs_req: The request being processed. | |
415 | * | |
1f91b4cc | 416 | * This is the reverse of dwc2_hsotg_map_dma(), called for the completion |
5b7d70c6 | 417 | * of a request to ensure the buffer is ready for access by the caller. |
8b9bc460 | 418 | */ |
1f91b4cc | 419 | static void dwc2_hsotg_unmap_dma(struct dwc2_hsotg *hsotg, |
9da51974 | 420 | struct dwc2_hsotg_ep *hs_ep, |
1f91b4cc | 421 | struct dwc2_hsotg_req *hs_req) |
5b7d70c6 BD |
422 | { |
423 | struct usb_request *req = &hs_req->req; | |
9da51974 | 424 | |
75a41ce4 | 425 | usb_gadget_unmap_request(&hsotg->gadget, req, hs_ep->map_dir); |
5b7d70c6 BD |
426 | } |
427 | ||
0f6b80c0 VA |
428 | /* |
429 | * dwc2_gadget_alloc_ctrl_desc_chains - allocate DMA descriptor chains | |
430 | * for Control endpoint | |
431 | * @hsotg: The device state. | |
432 | * | |
433 | * This function will allocate 4 descriptor chains for EP 0: 2 for | |
434 | * Setup stage, per one for IN and OUT data/status transactions. | |
435 | */ | |
436 | static int dwc2_gadget_alloc_ctrl_desc_chains(struct dwc2_hsotg *hsotg) | |
437 | { | |
438 | hsotg->setup_desc[0] = | |
439 | dmam_alloc_coherent(hsotg->dev, | |
440 | sizeof(struct dwc2_dma_desc), | |
441 | &hsotg->setup_desc_dma[0], | |
442 | GFP_KERNEL); | |
443 | if (!hsotg->setup_desc[0]) | |
444 | goto fail; | |
445 | ||
446 | hsotg->setup_desc[1] = | |
447 | dmam_alloc_coherent(hsotg->dev, | |
448 | sizeof(struct dwc2_dma_desc), | |
449 | &hsotg->setup_desc_dma[1], | |
450 | GFP_KERNEL); | |
451 | if (!hsotg->setup_desc[1]) | |
452 | goto fail; | |
453 | ||
454 | hsotg->ctrl_in_desc = | |
455 | dmam_alloc_coherent(hsotg->dev, | |
456 | sizeof(struct dwc2_dma_desc), | |
457 | &hsotg->ctrl_in_desc_dma, | |
458 | GFP_KERNEL); | |
459 | if (!hsotg->ctrl_in_desc) | |
460 | goto fail; | |
461 | ||
462 | hsotg->ctrl_out_desc = | |
463 | dmam_alloc_coherent(hsotg->dev, | |
464 | sizeof(struct dwc2_dma_desc), | |
465 | &hsotg->ctrl_out_desc_dma, | |
466 | GFP_KERNEL); | |
467 | if (!hsotg->ctrl_out_desc) | |
468 | goto fail; | |
469 | ||
470 | return 0; | |
471 | ||
472 | fail: | |
473 | return -ENOMEM; | |
474 | } | |
475 | ||
5b7d70c6 | 476 | /** |
1f91b4cc | 477 | * dwc2_hsotg_write_fifo - write packet Data to the TxFIFO |
5b7d70c6 BD |
478 | * @hsotg: The controller state. |
479 | * @hs_ep: The endpoint we're going to write for. | |
480 | * @hs_req: The request to write data for. | |
481 | * | |
482 | * This is called when the TxFIFO has some space in it to hold a new | |
483 | * transmission and we have something to give it. The actual setup of | |
484 | * the data size is done elsewhere, so all we have to do is to actually | |
485 | * write the data. | |
486 | * | |
487 | * The return value is zero if there is more space (or nothing was done) | |
488 | * otherwise -ENOSPC is returned if the FIFO space was used up. | |
489 | * | |
490 | * This routine is only needed for PIO | |
8b9bc460 | 491 | */ |
1f91b4cc | 492 | static int dwc2_hsotg_write_fifo(struct dwc2_hsotg *hsotg, |
9da51974 | 493 | struct dwc2_hsotg_ep *hs_ep, |
1f91b4cc | 494 | struct dwc2_hsotg_req *hs_req) |
5b7d70c6 BD |
495 | { |
496 | bool periodic = is_ep_periodic(hs_ep); | |
f25c42b8 | 497 | u32 gnptxsts = dwc2_readl(hsotg, GNPTXSTS); |
5b7d70c6 BD |
498 | int buf_pos = hs_req->req.actual; |
499 | int to_write = hs_ep->size_loaded; | |
500 | void *data; | |
501 | int can_write; | |
502 | int pkt_round; | |
4fca54aa | 503 | int max_transfer; |
5b7d70c6 BD |
504 | |
505 | to_write -= (buf_pos - hs_ep->last_load); | |
506 | ||
507 | /* if there's nothing to write, get out early */ | |
508 | if (to_write == 0) | |
509 | return 0; | |
510 | ||
10aebc77 | 511 | if (periodic && !hsotg->dedicated_fifos) { |
f25c42b8 | 512 | u32 epsize = dwc2_readl(hsotg, DIEPTSIZ(hs_ep->index)); |
5b7d70c6 BD |
513 | int size_left; |
514 | int size_done; | |
515 | ||
8b9bc460 LM |
516 | /* |
517 | * work out how much data was loaded so we can calculate | |
518 | * how much data is left in the fifo. | |
519 | */ | |
5b7d70c6 | 520 | |
47a1685f | 521 | size_left = DXEPTSIZ_XFERSIZE_GET(epsize); |
5b7d70c6 | 522 | |
8b9bc460 LM |
523 | /* |
524 | * if shared fifo, we cannot write anything until the | |
e7a9ff54 BD |
525 | * previous data has been completely sent. |
526 | */ | |
527 | if (hs_ep->fifo_load != 0) { | |
1f91b4cc | 528 | dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP); |
e7a9ff54 BD |
529 | return -ENOSPC; |
530 | } | |
531 | ||
5b7d70c6 BD |
532 | dev_dbg(hsotg->dev, "%s: left=%d, load=%d, fifo=%d, size %d\n", |
533 | __func__, size_left, | |
534 | hs_ep->size_loaded, hs_ep->fifo_load, hs_ep->fifo_size); | |
535 | ||
536 | /* how much of the data has moved */ | |
537 | size_done = hs_ep->size_loaded - size_left; | |
538 | ||
539 | /* how much data is left in the fifo */ | |
540 | can_write = hs_ep->fifo_load - size_done; | |
541 | dev_dbg(hsotg->dev, "%s: => can_write1=%d\n", | |
542 | __func__, can_write); | |
543 | ||
544 | can_write = hs_ep->fifo_size - can_write; | |
545 | dev_dbg(hsotg->dev, "%s: => can_write2=%d\n", | |
546 | __func__, can_write); | |
547 | ||
548 | if (can_write <= 0) { | |
1f91b4cc | 549 | dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP); |
5b7d70c6 BD |
550 | return -ENOSPC; |
551 | } | |
10aebc77 | 552 | } else if (hsotg->dedicated_fifos && hs_ep->index != 0) { |
f25c42b8 GS |
553 | can_write = dwc2_readl(hsotg, |
554 | DTXFSTS(hs_ep->fifo_index)); | |
10aebc77 BD |
555 | |
556 | can_write &= 0xffff; | |
557 | can_write *= 4; | |
5b7d70c6 | 558 | } else { |
47a1685f | 559 | if (GNPTXSTS_NP_TXQ_SPC_AVAIL_GET(gnptxsts) == 0) { |
5b7d70c6 BD |
560 | dev_dbg(hsotg->dev, |
561 | "%s: no queue slots available (0x%08x)\n", | |
562 | __func__, gnptxsts); | |
563 | ||
1f91b4cc | 564 | dwc2_hsotg_en_gsint(hsotg, GINTSTS_NPTXFEMP); |
5b7d70c6 BD |
565 | return -ENOSPC; |
566 | } | |
567 | ||
47a1685f | 568 | can_write = GNPTXSTS_NP_TXF_SPC_AVAIL_GET(gnptxsts); |
679f9b7c | 569 | can_write *= 4; /* fifo size is in 32bit quantities. */ |
5b7d70c6 BD |
570 | } |
571 | ||
4fca54aa RB |
572 | max_transfer = hs_ep->ep.maxpacket * hs_ep->mc; |
573 | ||
574 | dev_dbg(hsotg->dev, "%s: GNPTXSTS=%08x, can=%d, to=%d, max_transfer %d\n", | |
9da51974 | 575 | __func__, gnptxsts, can_write, to_write, max_transfer); |
5b7d70c6 | 576 | |
8b9bc460 LM |
577 | /* |
578 | * limit to 512 bytes of data, it seems at least on the non-periodic | |
5b7d70c6 BD |
579 | * FIFO, requests of >512 cause the endpoint to get stuck with a |
580 | * fragment of the end of the transfer in it. | |
581 | */ | |
811f3303 | 582 | if (can_write > 512 && !periodic) |
5b7d70c6 BD |
583 | can_write = 512; |
584 | ||
8b9bc460 LM |
585 | /* |
586 | * limit the write to one max-packet size worth of data, but allow | |
03e10e5a | 587 | * the transfer to return that it did not run out of fifo space |
8b9bc460 LM |
588 | * doing it. |
589 | */ | |
4fca54aa RB |
590 | if (to_write > max_transfer) { |
591 | to_write = max_transfer; | |
03e10e5a | 592 | |
5cb2ff0c RB |
593 | /* it's needed only when we do not use dedicated fifos */ |
594 | if (!hsotg->dedicated_fifos) | |
1f91b4cc | 595 | dwc2_hsotg_en_gsint(hsotg, |
9da51974 | 596 | periodic ? GINTSTS_PTXFEMP : |
47a1685f | 597 | GINTSTS_NPTXFEMP); |
03e10e5a BD |
598 | } |
599 | ||
5b7d70c6 BD |
600 | /* see if we can write data */ |
601 | ||
602 | if (to_write > can_write) { | |
603 | to_write = can_write; | |
4fca54aa | 604 | pkt_round = to_write % max_transfer; |
5b7d70c6 | 605 | |
8b9bc460 LM |
606 | /* |
607 | * Round the write down to an | |
5b7d70c6 BD |
608 | * exact number of packets. |
609 | * | |
610 | * Note, we do not currently check to see if we can ever | |
611 | * write a full packet or not to the FIFO. | |
612 | */ | |
613 | ||
614 | if (pkt_round) | |
615 | to_write -= pkt_round; | |
616 | ||
8b9bc460 LM |
617 | /* |
618 | * enable correct FIFO interrupt to alert us when there | |
619 | * is more room left. | |
620 | */ | |
5b7d70c6 | 621 | |
5cb2ff0c RB |
622 | /* it's needed only when we do not use dedicated fifos */ |
623 | if (!hsotg->dedicated_fifos) | |
1f91b4cc | 624 | dwc2_hsotg_en_gsint(hsotg, |
9da51974 | 625 | periodic ? GINTSTS_PTXFEMP : |
47a1685f | 626 | GINTSTS_NPTXFEMP); |
5b7d70c6 BD |
627 | } |
628 | ||
629 | dev_dbg(hsotg->dev, "write %d/%d, can_write %d, done %d\n", | |
9da51974 | 630 | to_write, hs_req->req.length, can_write, buf_pos); |
5b7d70c6 BD |
631 | |
632 | if (to_write <= 0) | |
633 | return -ENOSPC; | |
634 | ||
635 | hs_req->req.actual = buf_pos + to_write; | |
636 | hs_ep->total_data += to_write; | |
637 | ||
638 | if (periodic) | |
639 | hs_ep->fifo_load += to_write; | |
640 | ||
641 | to_write = DIV_ROUND_UP(to_write, 4); | |
642 | data = hs_req->req.buf + buf_pos; | |
643 | ||
342ccce1 | 644 | dwc2_writel_rep(hsotg, EPFIFO(hs_ep->index), data, to_write); |
5b7d70c6 BD |
645 | |
646 | return (to_write >= can_write) ? -ENOSPC : 0; | |
647 | } | |
648 | ||
649 | /** | |
650 | * get_ep_limit - get the maximum data legnth for this endpoint | |
651 | * @hs_ep: The endpoint | |
652 | * | |
653 | * Return the maximum data that can be queued in one go on a given endpoint | |
654 | * so that transfers that are too long can be split. | |
655 | */ | |
9da51974 | 656 | static unsigned int get_ep_limit(struct dwc2_hsotg_ep *hs_ep) |
5b7d70c6 BD |
657 | { |
658 | int index = hs_ep->index; | |
9da51974 JY |
659 | unsigned int maxsize; |
660 | unsigned int maxpkt; | |
5b7d70c6 BD |
661 | |
662 | if (index != 0) { | |
47a1685f DN |
663 | maxsize = DXEPTSIZ_XFERSIZE_LIMIT + 1; |
664 | maxpkt = DXEPTSIZ_PKTCNT_LIMIT + 1; | |
5b7d70c6 | 665 | } else { |
9da51974 | 666 | maxsize = 64 + 64; |
66e5c643 | 667 | if (hs_ep->dir_in) |
47a1685f | 668 | maxpkt = DIEPTSIZ0_PKTCNT_LIMIT + 1; |
66e5c643 | 669 | else |
5b7d70c6 | 670 | maxpkt = 2; |
5b7d70c6 BD |
671 | } |
672 | ||
673 | /* we made the constant loading easier above by using +1 */ | |
674 | maxpkt--; | |
675 | maxsize--; | |
676 | ||
8b9bc460 LM |
677 | /* |
678 | * constrain by packet count if maxpkts*pktsize is greater | |
679 | * than the length register size. | |
680 | */ | |
5b7d70c6 BD |
681 | |
682 | if ((maxpkt * hs_ep->ep.maxpacket) < maxsize) | |
683 | maxsize = maxpkt * hs_ep->ep.maxpacket; | |
684 | ||
685 | return maxsize; | |
686 | } | |
687 | ||
381fc8f8 | 688 | /** |
38beaec6 JY |
689 | * dwc2_hsotg_read_frameno - read current frame number |
690 | * @hsotg: The device instance | |
691 | * | |
692 | * Return the current frame number | |
693 | */ | |
381fc8f8 VM |
694 | static u32 dwc2_hsotg_read_frameno(struct dwc2_hsotg *hsotg) |
695 | { | |
696 | u32 dsts; | |
697 | ||
f25c42b8 | 698 | dsts = dwc2_readl(hsotg, DSTS); |
381fc8f8 VM |
699 | dsts &= DSTS_SOFFN_MASK; |
700 | dsts >>= DSTS_SOFFN_SHIFT; | |
701 | ||
702 | return dsts; | |
703 | } | |
704 | ||
cf77b5fb VA |
705 | /** |
706 | * dwc2_gadget_get_chain_limit - get the maximum data payload value of the | |
707 | * DMA descriptor chain prepared for specific endpoint | |
708 | * @hs_ep: The endpoint | |
709 | * | |
710 | * Return the maximum data that can be queued in one go on a given endpoint | |
711 | * depending on its descriptor chain capacity so that transfers that | |
712 | * are too long can be split. | |
713 | */ | |
714 | static unsigned int dwc2_gadget_get_chain_limit(struct dwc2_hsotg_ep *hs_ep) | |
715 | { | |
b2c586eb | 716 | const struct usb_endpoint_descriptor *ep_desc = hs_ep->ep.desc; |
cf77b5fb VA |
717 | int is_isoc = hs_ep->isochronous; |
718 | unsigned int maxsize; | |
b2c586eb MH |
719 | u32 mps = hs_ep->ep.maxpacket; |
720 | int dir_in = hs_ep->dir_in; | |
cf77b5fb VA |
721 | |
722 | if (is_isoc) | |
54f37f56 MH |
723 | maxsize = (hs_ep->dir_in ? DEV_DMA_ISOC_TX_NBYTES_LIMIT : |
724 | DEV_DMA_ISOC_RX_NBYTES_LIMIT) * | |
725 | MAX_DMA_DESC_NUM_HS_ISOC; | |
cf77b5fb | 726 | else |
54f37f56 | 727 | maxsize = DEV_DMA_NBYTES_LIMIT * MAX_DMA_DESC_NUM_GENERIC; |
cf77b5fb | 728 | |
b2c586eb MH |
729 | /* Interrupt OUT EP with mps not multiple of 4 */ |
730 | if (hs_ep->index) | |
731 | if (usb_endpoint_xfer_int(ep_desc) && !dir_in && (mps % 4)) | |
732 | maxsize = mps * MAX_DMA_DESC_NUM_GENERIC; | |
733 | ||
cf77b5fb VA |
734 | return maxsize; |
735 | } | |
736 | ||
e02f9aa6 VA |
737 | /* |
738 | * dwc2_gadget_get_desc_params - get DMA descriptor parameters. | |
739 | * @hs_ep: The endpoint | |
740 | * @mask: RX/TX bytes mask to be defined | |
741 | * | |
742 | * Returns maximum data payload for one descriptor after analyzing endpoint | |
743 | * characteristics. | |
744 | * DMA descriptor transfer bytes limit depends on EP type: | |
745 | * Control out - MPS, | |
746 | * Isochronous - descriptor rx/tx bytes bitfield limit, | |
747 | * Control In/Bulk/Interrupt - multiple of mps. This will allow to not | |
748 | * have concatenations from various descriptors within one packet. | |
b2c586eb MH |
749 | * Interrupt OUT - if mps not multiple of 4 then a single packet corresponds |
750 | * to a single descriptor. | |
e02f9aa6 VA |
751 | * |
752 | * Selects corresponding mask for RX/TX bytes as well. | |
753 | */ | |
754 | static u32 dwc2_gadget_get_desc_params(struct dwc2_hsotg_ep *hs_ep, u32 *mask) | |
755 | { | |
b2c586eb | 756 | const struct usb_endpoint_descriptor *ep_desc = hs_ep->ep.desc; |
e02f9aa6 VA |
757 | u32 mps = hs_ep->ep.maxpacket; |
758 | int dir_in = hs_ep->dir_in; | |
759 | u32 desc_size = 0; | |
760 | ||
761 | if (!hs_ep->index && !dir_in) { | |
762 | desc_size = mps; | |
763 | *mask = DEV_DMA_NBYTES_MASK; | |
764 | } else if (hs_ep->isochronous) { | |
765 | if (dir_in) { | |
766 | desc_size = DEV_DMA_ISOC_TX_NBYTES_LIMIT; | |
767 | *mask = DEV_DMA_ISOC_TX_NBYTES_MASK; | |
768 | } else { | |
769 | desc_size = DEV_DMA_ISOC_RX_NBYTES_LIMIT; | |
770 | *mask = DEV_DMA_ISOC_RX_NBYTES_MASK; | |
771 | } | |
772 | } else { | |
773 | desc_size = DEV_DMA_NBYTES_LIMIT; | |
774 | *mask = DEV_DMA_NBYTES_MASK; | |
775 | ||
776 | /* Round down desc_size to be mps multiple */ | |
777 | desc_size -= desc_size % mps; | |
778 | } | |
779 | ||
b2c586eb MH |
780 | /* Interrupt OUT EP with mps not multiple of 4 */ |
781 | if (hs_ep->index) | |
782 | if (usb_endpoint_xfer_int(ep_desc) && !dir_in && (mps % 4)) { | |
783 | desc_size = mps; | |
784 | *mask = DEV_DMA_NBYTES_MASK; | |
785 | } | |
786 | ||
e02f9aa6 VA |
787 | return desc_size; |
788 | } | |
789 | ||
10209abe AP |
790 | static void dwc2_gadget_fill_nonisoc_xfer_ddma_one(struct dwc2_hsotg_ep *hs_ep, |
791 | struct dwc2_dma_desc **desc, | |
e02f9aa6 | 792 | dma_addr_t dma_buff, |
10209abe AP |
793 | unsigned int len, |
794 | bool true_last) | |
e02f9aa6 | 795 | { |
e02f9aa6 | 796 | int dir_in = hs_ep->dir_in; |
e02f9aa6 VA |
797 | u32 mps = hs_ep->ep.maxpacket; |
798 | u32 maxsize = 0; | |
799 | u32 offset = 0; | |
800 | u32 mask = 0; | |
801 | int i; | |
802 | ||
803 | maxsize = dwc2_gadget_get_desc_params(hs_ep, &mask); | |
804 | ||
805 | hs_ep->desc_count = (len / maxsize) + | |
806 | ((len % maxsize) ? 1 : 0); | |
807 | if (len == 0) | |
808 | hs_ep->desc_count = 1; | |
809 | ||
810 | for (i = 0; i < hs_ep->desc_count; ++i) { | |
10209abe AP |
811 | (*desc)->status = 0; |
812 | (*desc)->status |= (DEV_DMA_BUFF_STS_HBUSY | |
e02f9aa6 VA |
813 | << DEV_DMA_BUFF_STS_SHIFT); |
814 | ||
815 | if (len > maxsize) { | |
816 | if (!hs_ep->index && !dir_in) | |
10209abe | 817 | (*desc)->status |= (DEV_DMA_L | DEV_DMA_IOC); |
e02f9aa6 | 818 | |
10209abe AP |
819 | (*desc)->status |= |
820 | maxsize << DEV_DMA_NBYTES_SHIFT & mask; | |
821 | (*desc)->buf = dma_buff + offset; | |
e02f9aa6 VA |
822 | |
823 | len -= maxsize; | |
824 | offset += maxsize; | |
825 | } else { | |
10209abe AP |
826 | if (true_last) |
827 | (*desc)->status |= (DEV_DMA_L | DEV_DMA_IOC); | |
e02f9aa6 VA |
828 | |
829 | if (dir_in) | |
10209abe AP |
830 | (*desc)->status |= (len % mps) ? DEV_DMA_SHORT : |
831 | ((hs_ep->send_zlp && true_last) ? | |
832 | DEV_DMA_SHORT : 0); | |
e02f9aa6 | 833 | |
10209abe | 834 | (*desc)->status |= |
e02f9aa6 | 835 | len << DEV_DMA_NBYTES_SHIFT & mask; |
10209abe | 836 | (*desc)->buf = dma_buff + offset; |
e02f9aa6 VA |
837 | } |
838 | ||
10209abe AP |
839 | (*desc)->status &= ~DEV_DMA_BUFF_STS_MASK; |
840 | (*desc)->status |= (DEV_DMA_BUFF_STS_HREADY | |
e02f9aa6 | 841 | << DEV_DMA_BUFF_STS_SHIFT); |
10209abe AP |
842 | (*desc)++; |
843 | } | |
844 | } | |
845 | ||
846 | /* | |
847 | * dwc2_gadget_config_nonisoc_xfer_ddma - prepare non ISOC DMA desc chain. | |
848 | * @hs_ep: The endpoint | |
849 | * @ureq: Request to transfer | |
850 | * @offset: offset in bytes | |
851 | * @len: Length of the transfer | |
852 | * | |
853 | * This function will iterate over descriptor chain and fill its entries | |
854 | * with corresponding information based on transfer data. | |
855 | */ | |
856 | static void dwc2_gadget_config_nonisoc_xfer_ddma(struct dwc2_hsotg_ep *hs_ep, | |
066cfd07 | 857 | dma_addr_t dma_buff, |
10209abe AP |
858 | unsigned int len) |
859 | { | |
066cfd07 | 860 | struct usb_request *ureq = NULL; |
10209abe AP |
861 | struct dwc2_dma_desc *desc = hs_ep->desc_list; |
862 | struct scatterlist *sg; | |
863 | int i; | |
864 | u8 desc_count = 0; | |
865 | ||
066cfd07 AP |
866 | if (hs_ep->req) |
867 | ureq = &hs_ep->req->req; | |
868 | ||
10209abe | 869 | /* non-DMA sg buffer */ |
066cfd07 | 870 | if (!ureq || !ureq->num_sgs) { |
10209abe | 871 | dwc2_gadget_fill_nonisoc_xfer_ddma_one(hs_ep, &desc, |
066cfd07 | 872 | dma_buff, len, true); |
10209abe | 873 | return; |
e02f9aa6 | 874 | } |
10209abe AP |
875 | |
876 | /* DMA sg buffer */ | |
877 | for_each_sg(ureq->sg, sg, ureq->num_sgs, i) { | |
878 | dwc2_gadget_fill_nonisoc_xfer_ddma_one(hs_ep, &desc, | |
879 | sg_dma_address(sg) + sg->offset, sg_dma_len(sg), | |
880 | sg_is_last(sg)); | |
881 | desc_count += hs_ep->desc_count; | |
882 | } | |
883 | ||
884 | hs_ep->desc_count = desc_count; | |
e02f9aa6 VA |
885 | } |
886 | ||
540ccba0 VA |
887 | /* |
888 | * dwc2_gadget_fill_isoc_desc - fills next isochronous descriptor in chain. | |
889 | * @hs_ep: The isochronous endpoint. | |
890 | * @dma_buff: usb requests dma buffer. | |
891 | * @len: usb request transfer length. | |
892 | * | |
729cac69 | 893 | * Fills next free descriptor with the data of the arrived usb request, |
540ccba0 VA |
894 | * frame info, sets Last and IOC bits increments next_desc. If filled |
895 | * descriptor is not the first one, removes L bit from the previous descriptor | |
896 | * status. | |
897 | */ | |
898 | static int dwc2_gadget_fill_isoc_desc(struct dwc2_hsotg_ep *hs_ep, | |
899 | dma_addr_t dma_buff, unsigned int len) | |
900 | { | |
901 | struct dwc2_dma_desc *desc; | |
902 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
903 | u32 index; | |
540ccba0 | 904 | u32 mask = 0; |
1d8e5c00 | 905 | u8 pid = 0; |
540ccba0 | 906 | |
768a0741 | 907 | dwc2_gadget_get_desc_params(hs_ep, &mask); |
540ccba0 | 908 | |
729cac69 MH |
909 | index = hs_ep->next_desc; |
910 | desc = &hs_ep->desc_list[index]; | |
540ccba0 | 911 | |
729cac69 MH |
912 | /* Check if descriptor chain full */ |
913 | if ((desc->status >> DEV_DMA_BUFF_STS_SHIFT) == | |
914 | DEV_DMA_BUFF_STS_HREADY) { | |
915 | dev_dbg(hsotg->dev, "%s: desc chain full\n", __func__); | |
916 | return 1; | |
540ccba0 VA |
917 | } |
918 | ||
540ccba0 VA |
919 | /* Clear L bit of previous desc if more than one entries in the chain */ |
920 | if (hs_ep->next_desc) | |
921 | hs_ep->desc_list[index - 1].status &= ~DEV_DMA_L; | |
922 | ||
923 | dev_dbg(hsotg->dev, "%s: Filling ep %d, dir %s isoc desc # %d\n", | |
924 | __func__, hs_ep->index, hs_ep->dir_in ? "in" : "out", index); | |
925 | ||
926 | desc->status = 0; | |
927 | desc->status |= (DEV_DMA_BUFF_STS_HBUSY << DEV_DMA_BUFF_STS_SHIFT); | |
928 | ||
929 | desc->buf = dma_buff; | |
930 | desc->status |= (DEV_DMA_L | DEV_DMA_IOC | | |
931 | ((len << DEV_DMA_NBYTES_SHIFT) & mask)); | |
932 | ||
933 | if (hs_ep->dir_in) { | |
1d8e5c00 MH |
934 | if (len) |
935 | pid = DIV_ROUND_UP(len, hs_ep->ep.maxpacket); | |
936 | else | |
937 | pid = 1; | |
938 | desc->status |= ((pid << DEV_DMA_ISOC_PID_SHIFT) & | |
540ccba0 VA |
939 | DEV_DMA_ISOC_PID_MASK) | |
940 | ((len % hs_ep->ep.maxpacket) ? | |
941 | DEV_DMA_SHORT : 0) | | |
942 | ((hs_ep->target_frame << | |
943 | DEV_DMA_ISOC_FRNUM_SHIFT) & | |
944 | DEV_DMA_ISOC_FRNUM_MASK); | |
945 | } | |
946 | ||
947 | desc->status &= ~DEV_DMA_BUFF_STS_MASK; | |
948 | desc->status |= (DEV_DMA_BUFF_STS_HREADY << DEV_DMA_BUFF_STS_SHIFT); | |
949 | ||
729cac69 MH |
950 | /* Increment frame number by interval for IN */ |
951 | if (hs_ep->dir_in) | |
952 | dwc2_gadget_incr_frame_num(hs_ep); | |
953 | ||
540ccba0 VA |
954 | /* Update index of last configured entry in the chain */ |
955 | hs_ep->next_desc++; | |
54f37f56 | 956 | if (hs_ep->next_desc >= MAX_DMA_DESC_NUM_HS_ISOC) |
729cac69 | 957 | hs_ep->next_desc = 0; |
540ccba0 VA |
958 | |
959 | return 0; | |
960 | } | |
961 | ||
962 | /* | |
963 | * dwc2_gadget_start_isoc_ddma - start isochronous transfer in DDMA | |
964 | * @hs_ep: The isochronous endpoint. | |
965 | * | |
729cac69 | 966 | * Prepare descriptor chain for isochronous endpoints. Afterwards |
540ccba0 | 967 | * write DMA address to HW and enable the endpoint. |
540ccba0 VA |
968 | */ |
969 | static void dwc2_gadget_start_isoc_ddma(struct dwc2_hsotg_ep *hs_ep) | |
970 | { | |
971 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
972 | struct dwc2_hsotg_req *hs_req, *treq; | |
973 | int index = hs_ep->index; | |
974 | int ret; | |
729cac69 | 975 | int i; |
540ccba0 VA |
976 | u32 dma_reg; |
977 | u32 depctl; | |
978 | u32 ctrl; | |
729cac69 | 979 | struct dwc2_dma_desc *desc; |
540ccba0 VA |
980 | |
981 | if (list_empty(&hs_ep->queue)) { | |
1ffba905 | 982 | hs_ep->target_frame = TARGET_FRAME_INITIAL; |
540ccba0 VA |
983 | dev_dbg(hsotg->dev, "%s: No requests in queue\n", __func__); |
984 | return; | |
985 | } | |
986 | ||
729cac69 | 987 | /* Initialize descriptor chain by Host Busy status */ |
54f37f56 | 988 | for (i = 0; i < MAX_DMA_DESC_NUM_HS_ISOC; i++) { |
729cac69 MH |
989 | desc = &hs_ep->desc_list[i]; |
990 | desc->status = 0; | |
991 | desc->status |= (DEV_DMA_BUFF_STS_HBUSY | |
992 | << DEV_DMA_BUFF_STS_SHIFT); | |
993 | } | |
994 | ||
995 | hs_ep->next_desc = 0; | |
540ccba0 | 996 | list_for_each_entry_safe(hs_req, treq, &hs_ep->queue, queue) { |
10209abe AP |
997 | dma_addr_t dma_addr = hs_req->req.dma; |
998 | ||
999 | if (hs_req->req.num_sgs) { | |
1000 | WARN_ON(hs_req->req.num_sgs > 1); | |
1001 | dma_addr = sg_dma_address(hs_req->req.sg); | |
1002 | } | |
1003 | ret = dwc2_gadget_fill_isoc_desc(hs_ep, dma_addr, | |
540ccba0 | 1004 | hs_req->req.length); |
729cac69 | 1005 | if (ret) |
540ccba0 | 1006 | break; |
540ccba0 VA |
1007 | } |
1008 | ||
729cac69 | 1009 | hs_ep->compl_desc = 0; |
540ccba0 VA |
1010 | depctl = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index); |
1011 | dma_reg = hs_ep->dir_in ? DIEPDMA(index) : DOEPDMA(index); | |
1012 | ||
1013 | /* write descriptor chain address to control register */ | |
f25c42b8 | 1014 | dwc2_writel(hsotg, hs_ep->desc_list_dma, dma_reg); |
540ccba0 | 1015 | |
f25c42b8 | 1016 | ctrl = dwc2_readl(hsotg, depctl); |
540ccba0 | 1017 | ctrl |= DXEPCTL_EPENA | DXEPCTL_CNAK; |
f25c42b8 | 1018 | dwc2_writel(hsotg, ctrl, depctl); |
540ccba0 VA |
1019 | } |
1020 | ||
5b7d70c6 | 1021 | /** |
1f91b4cc | 1022 | * dwc2_hsotg_start_req - start a USB request from an endpoint's queue |
5b7d70c6 BD |
1023 | * @hsotg: The controller state. |
1024 | * @hs_ep: The endpoint to process a request for | |
1025 | * @hs_req: The request to start. | |
1026 | * @continuing: True if we are doing more for the current request. | |
1027 | * | |
1028 | * Start the given request running by setting the endpoint registers | |
1029 | * appropriately, and writing any data to the FIFOs. | |
1030 | */ | |
1f91b4cc | 1031 | static void dwc2_hsotg_start_req(struct dwc2_hsotg *hsotg, |
9da51974 | 1032 | struct dwc2_hsotg_ep *hs_ep, |
1f91b4cc | 1033 | struct dwc2_hsotg_req *hs_req, |
5b7d70c6 BD |
1034 | bool continuing) |
1035 | { | |
1036 | struct usb_request *ureq = &hs_req->req; | |
1037 | int index = hs_ep->index; | |
1038 | int dir_in = hs_ep->dir_in; | |
1039 | u32 epctrl_reg; | |
1040 | u32 epsize_reg; | |
1041 | u32 epsize; | |
1042 | u32 ctrl; | |
9da51974 JY |
1043 | unsigned int length; |
1044 | unsigned int packets; | |
1045 | unsigned int maxreq; | |
aa3e8bc8 | 1046 | unsigned int dma_reg; |
5b7d70c6 BD |
1047 | |
1048 | if (index != 0) { | |
1049 | if (hs_ep->req && !continuing) { | |
1050 | dev_err(hsotg->dev, "%s: active request\n", __func__); | |
1051 | WARN_ON(1); | |
1052 | return; | |
1053 | } else if (hs_ep->req != hs_req && continuing) { | |
1054 | dev_err(hsotg->dev, | |
1055 | "%s: continue different req\n", __func__); | |
1056 | WARN_ON(1); | |
1057 | return; | |
1058 | } | |
1059 | } | |
1060 | ||
aa3e8bc8 | 1061 | dma_reg = dir_in ? DIEPDMA(index) : DOEPDMA(index); |
94cb8fd6 LM |
1062 | epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index); |
1063 | epsize_reg = dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index); | |
5b7d70c6 BD |
1064 | |
1065 | dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n", | |
f25c42b8 | 1066 | __func__, dwc2_readl(hsotg, epctrl_reg), index, |
5b7d70c6 BD |
1067 | hs_ep->dir_in ? "in" : "out"); |
1068 | ||
9c39ddc6 | 1069 | /* If endpoint is stalled, we will restart request later */ |
f25c42b8 | 1070 | ctrl = dwc2_readl(hsotg, epctrl_reg); |
9c39ddc6 | 1071 | |
b2d4c54e | 1072 | if (index && ctrl & DXEPCTL_STALL) { |
9c39ddc6 AT |
1073 | dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index); |
1074 | return; | |
1075 | } | |
1076 | ||
5b7d70c6 | 1077 | length = ureq->length - ureq->actual; |
71225bee LM |
1078 | dev_dbg(hsotg->dev, "ureq->length:%d ureq->actual:%d\n", |
1079 | ureq->length, ureq->actual); | |
5b7d70c6 | 1080 | |
cf77b5fb VA |
1081 | if (!using_desc_dma(hsotg)) |
1082 | maxreq = get_ep_limit(hs_ep); | |
1083 | else | |
1084 | maxreq = dwc2_gadget_get_chain_limit(hs_ep); | |
1085 | ||
5b7d70c6 BD |
1086 | if (length > maxreq) { |
1087 | int round = maxreq % hs_ep->ep.maxpacket; | |
1088 | ||
1089 | dev_dbg(hsotg->dev, "%s: length %d, max-req %d, r %d\n", | |
1090 | __func__, length, maxreq, round); | |
1091 | ||
1092 | /* round down to multiple of packets */ | |
1093 | if (round) | |
1094 | maxreq -= round; | |
1095 | ||
1096 | length = maxreq; | |
1097 | } | |
1098 | ||
1099 | if (length) | |
1100 | packets = DIV_ROUND_UP(length, hs_ep->ep.maxpacket); | |
1101 | else | |
1102 | packets = 1; /* send one packet if length is zero. */ | |
1103 | ||
1104 | if (dir_in && index != 0) | |
4fca54aa | 1105 | if (hs_ep->isochronous) |
47a1685f | 1106 | epsize = DXEPTSIZ_MC(packets); |
4fca54aa | 1107 | else |
47a1685f | 1108 | epsize = DXEPTSIZ_MC(1); |
5b7d70c6 BD |
1109 | else |
1110 | epsize = 0; | |
1111 | ||
f71b5e25 MYK |
1112 | /* |
1113 | * zero length packet should be programmed on its own and should not | |
1114 | * be counted in DIEPTSIZ.PktCnt with other packets. | |
1115 | */ | |
1116 | if (dir_in && ureq->zero && !continuing) { | |
1117 | /* Test if zlp is actually required. */ | |
1118 | if ((ureq->length >= hs_ep->ep.maxpacket) && | |
9da51974 | 1119 | !(ureq->length % hs_ep->ep.maxpacket)) |
8a20fa45 | 1120 | hs_ep->send_zlp = 1; |
5b7d70c6 BD |
1121 | } |
1122 | ||
47a1685f DN |
1123 | epsize |= DXEPTSIZ_PKTCNT(packets); |
1124 | epsize |= DXEPTSIZ_XFERSIZE(length); | |
5b7d70c6 BD |
1125 | |
1126 | dev_dbg(hsotg->dev, "%s: %d@%d/%d, 0x%08x => 0x%08x\n", | |
1127 | __func__, packets, length, ureq->length, epsize, epsize_reg); | |
1128 | ||
1129 | /* store the request as the current one we're doing */ | |
1130 | hs_ep->req = hs_req; | |
1131 | ||
aa3e8bc8 VA |
1132 | if (using_desc_dma(hsotg)) { |
1133 | u32 offset = 0; | |
1134 | u32 mps = hs_ep->ep.maxpacket; | |
1135 | ||
1136 | /* Adjust length: EP0 - MPS, other OUT EPs - multiple of MPS */ | |
1137 | if (!dir_in) { | |
1138 | if (!index) | |
1139 | length = mps; | |
1140 | else if (length % mps) | |
1141 | length += (mps - (length % mps)); | |
1142 | } | |
5b7d70c6 | 1143 | |
b2c586eb | 1144 | if (continuing) |
aa3e8bc8 VA |
1145 | offset = ureq->actual; |
1146 | ||
1147 | /* Fill DDMA chain entries */ | |
066cfd07 | 1148 | dwc2_gadget_config_nonisoc_xfer_ddma(hs_ep, ureq->dma + offset, |
aa3e8bc8 VA |
1149 | length); |
1150 | ||
1151 | /* write descriptor chain address to control register */ | |
f25c42b8 | 1152 | dwc2_writel(hsotg, hs_ep->desc_list_dma, dma_reg); |
5b7d70c6 | 1153 | |
aa3e8bc8 VA |
1154 | dev_dbg(hsotg->dev, "%s: %08x pad => 0x%08x\n", |
1155 | __func__, (u32)hs_ep->desc_list_dma, dma_reg); | |
1156 | } else { | |
1157 | /* write size / packets */ | |
f25c42b8 | 1158 | dwc2_writel(hsotg, epsize, epsize_reg); |
aa3e8bc8 | 1159 | |
729e6574 | 1160 | if (using_dma(hsotg) && !continuing && (length != 0)) { |
aa3e8bc8 VA |
1161 | /* |
1162 | * write DMA address to control register, buffer | |
1163 | * already synced by dwc2_hsotg_ep_queue(). | |
1164 | */ | |
5b7d70c6 | 1165 | |
f25c42b8 | 1166 | dwc2_writel(hsotg, ureq->dma, dma_reg); |
aa3e8bc8 VA |
1167 | |
1168 | dev_dbg(hsotg->dev, "%s: %pad => 0x%08x\n", | |
1169 | __func__, &ureq->dma, dma_reg); | |
1170 | } | |
5b7d70c6 BD |
1171 | } |
1172 | ||
837e9f00 VM |
1173 | if (hs_ep->isochronous && hs_ep->interval == 1) { |
1174 | hs_ep->target_frame = dwc2_hsotg_read_frameno(hsotg); | |
1175 | dwc2_gadget_incr_frame_num(hs_ep); | |
1176 | ||
1177 | if (hs_ep->target_frame & 0x1) | |
1178 | ctrl |= DXEPCTL_SETODDFR; | |
1179 | else | |
1180 | ctrl |= DXEPCTL_SETEVENFR; | |
1181 | } | |
1182 | ||
47a1685f | 1183 | ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */ |
71225bee | 1184 | |
fe0b94ab | 1185 | dev_dbg(hsotg->dev, "ep0 state:%d\n", hsotg->ep0_state); |
71225bee LM |
1186 | |
1187 | /* For Setup request do not clear NAK */ | |
fe0b94ab | 1188 | if (!(index == 0 && hsotg->ep0_state == DWC2_EP0_SETUP)) |
47a1685f | 1189 | ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */ |
71225bee | 1190 | |
5b7d70c6 | 1191 | dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl); |
f25c42b8 | 1192 | dwc2_writel(hsotg, ctrl, epctrl_reg); |
5b7d70c6 | 1193 | |
8b9bc460 LM |
1194 | /* |
1195 | * set these, it seems that DMA support increments past the end | |
5b7d70c6 | 1196 | * of the packet buffer so we need to calculate the length from |
8b9bc460 LM |
1197 | * this information. |
1198 | */ | |
5b7d70c6 BD |
1199 | hs_ep->size_loaded = length; |
1200 | hs_ep->last_load = ureq->actual; | |
1201 | ||
1202 | if (dir_in && !using_dma(hsotg)) { | |
1203 | /* set these anyway, we may need them for non-periodic in */ | |
1204 | hs_ep->fifo_load = 0; | |
1205 | ||
1f91b4cc | 1206 | dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req); |
5b7d70c6 BD |
1207 | } |
1208 | ||
8b9bc460 LM |
1209 | /* |
1210 | * Note, trying to clear the NAK here causes problems with transmit | |
1211 | * on the S3C6400 ending up with the TXFIFO becoming full. | |
1212 | */ | |
5b7d70c6 BD |
1213 | |
1214 | /* check ep is enabled */ | |
f25c42b8 | 1215 | if (!(dwc2_readl(hsotg, epctrl_reg) & DXEPCTL_EPENA)) |
1a0ed863 | 1216 | dev_dbg(hsotg->dev, |
9da51974 | 1217 | "ep%d: failed to become enabled (DXEPCTL=0x%08x)?\n", |
f25c42b8 | 1218 | index, dwc2_readl(hsotg, epctrl_reg)); |
5b7d70c6 | 1219 | |
47a1685f | 1220 | dev_dbg(hsotg->dev, "%s: DXEPCTL=0x%08x\n", |
f25c42b8 | 1221 | __func__, dwc2_readl(hsotg, epctrl_reg)); |
afcf4169 RB |
1222 | |
1223 | /* enable ep interrupts */ | |
1f91b4cc | 1224 | dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 1); |
5b7d70c6 BD |
1225 | } |
1226 | ||
1227 | /** | |
1f91b4cc | 1228 | * dwc2_hsotg_map_dma - map the DMA memory being used for the request |
5b7d70c6 BD |
1229 | * @hsotg: The device state. |
1230 | * @hs_ep: The endpoint the request is on. | |
1231 | * @req: The request being processed. | |
1232 | * | |
1233 | * We've been asked to queue a request, so ensure that the memory buffer | |
1234 | * is correctly setup for DMA. If we've been passed an extant DMA address | |
1235 | * then ensure the buffer has been synced to memory. If our buffer has no | |
1236 | * DMA memory, then we map the memory and mark our request to allow us to | |
1237 | * cleanup on completion. | |
8b9bc460 | 1238 | */ |
1f91b4cc | 1239 | static int dwc2_hsotg_map_dma(struct dwc2_hsotg *hsotg, |
9da51974 | 1240 | struct dwc2_hsotg_ep *hs_ep, |
5b7d70c6 BD |
1241 | struct usb_request *req) |
1242 | { | |
e58ebcd1 | 1243 | int ret; |
5b7d70c6 | 1244 | |
75a41ce4 | 1245 | hs_ep->map_dir = hs_ep->dir_in; |
e58ebcd1 FB |
1246 | ret = usb_gadget_map_request(&hsotg->gadget, req, hs_ep->dir_in); |
1247 | if (ret) | |
1248 | goto dma_error; | |
5b7d70c6 BD |
1249 | |
1250 | return 0; | |
1251 | ||
1252 | dma_error: | |
1253 | dev_err(hsotg->dev, "%s: failed to map buffer %p, %d bytes\n", | |
1254 | __func__, req->buf, req->length); | |
1255 | ||
1256 | return -EIO; | |
1257 | } | |
1258 | ||
1f91b4cc | 1259 | static int dwc2_hsotg_handle_unaligned_buf_start(struct dwc2_hsotg *hsotg, |
b98866c2 JY |
1260 | struct dwc2_hsotg_ep *hs_ep, |
1261 | struct dwc2_hsotg_req *hs_req) | |
7d24c1b5 MYK |
1262 | { |
1263 | void *req_buf = hs_req->req.buf; | |
1264 | ||
1265 | /* If dma is not being used or buffer is aligned */ | |
1266 | if (!using_dma(hsotg) || !((long)req_buf & 3)) | |
1267 | return 0; | |
1268 | ||
1269 | WARN_ON(hs_req->saved_req_buf); | |
1270 | ||
1271 | dev_dbg(hsotg->dev, "%s: %s: buf=%p length=%d\n", __func__, | |
9da51974 | 1272 | hs_ep->ep.name, req_buf, hs_req->req.length); |
7d24c1b5 MYK |
1273 | |
1274 | hs_req->req.buf = kmalloc(hs_req->req.length, GFP_ATOMIC); | |
1275 | if (!hs_req->req.buf) { | |
1276 | hs_req->req.buf = req_buf; | |
1277 | dev_err(hsotg->dev, | |
1278 | "%s: unable to allocate memory for bounce buffer\n", | |
1279 | __func__); | |
1280 | return -ENOMEM; | |
1281 | } | |
1282 | ||
1283 | /* Save actual buffer */ | |
1284 | hs_req->saved_req_buf = req_buf; | |
1285 | ||
1286 | if (hs_ep->dir_in) | |
1287 | memcpy(hs_req->req.buf, req_buf, hs_req->req.length); | |
1288 | return 0; | |
1289 | } | |
1290 | ||
b98866c2 JY |
1291 | static void |
1292 | dwc2_hsotg_handle_unaligned_buf_complete(struct dwc2_hsotg *hsotg, | |
1293 | struct dwc2_hsotg_ep *hs_ep, | |
1294 | struct dwc2_hsotg_req *hs_req) | |
7d24c1b5 MYK |
1295 | { |
1296 | /* If dma is not being used or buffer was aligned */ | |
1297 | if (!using_dma(hsotg) || !hs_req->saved_req_buf) | |
1298 | return; | |
1299 | ||
1300 | dev_dbg(hsotg->dev, "%s: %s: status=%d actual-length=%d\n", __func__, | |
1301 | hs_ep->ep.name, hs_req->req.status, hs_req->req.actual); | |
1302 | ||
1303 | /* Copy data from bounce buffer on successful out transfer */ | |
1304 | if (!hs_ep->dir_in && !hs_req->req.status) | |
1305 | memcpy(hs_req->saved_req_buf, hs_req->req.buf, | |
9da51974 | 1306 | hs_req->req.actual); |
7d24c1b5 MYK |
1307 | |
1308 | /* Free bounce buffer */ | |
1309 | kfree(hs_req->req.buf); | |
1310 | ||
1311 | hs_req->req.buf = hs_req->saved_req_buf; | |
1312 | hs_req->saved_req_buf = NULL; | |
1313 | } | |
1314 | ||
381fc8f8 VM |
1315 | /** |
1316 | * dwc2_gadget_target_frame_elapsed - Checks target frame | |
1317 | * @hs_ep: The driver endpoint to check | |
1318 | * | |
1319 | * Returns 1 if targeted frame elapsed. If returned 1 then we need to drop | |
1320 | * corresponding transfer. | |
1321 | */ | |
1322 | static bool dwc2_gadget_target_frame_elapsed(struct dwc2_hsotg_ep *hs_ep) | |
1323 | { | |
1324 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
1325 | u32 target_frame = hs_ep->target_frame; | |
c7c24e7a | 1326 | u32 current_frame = hsotg->frame_number; |
381fc8f8 VM |
1327 | bool frame_overrun = hs_ep->frame_overrun; |
1328 | ||
1329 | if (!frame_overrun && current_frame >= target_frame) | |
1330 | return true; | |
1331 | ||
1332 | if (frame_overrun && current_frame >= target_frame && | |
1333 | ((current_frame - target_frame) < DSTS_SOFFN_LIMIT / 2)) | |
1334 | return true; | |
1335 | ||
1336 | return false; | |
1337 | } | |
1338 | ||
e02f9aa6 VA |
1339 | /* |
1340 | * dwc2_gadget_set_ep0_desc_chain - Set EP's desc chain pointers | |
1341 | * @hsotg: The driver state | |
1342 | * @hs_ep: the ep descriptor chain is for | |
1343 | * | |
1344 | * Called to update EP0 structure's pointers depend on stage of | |
1345 | * control transfer. | |
1346 | */ | |
1347 | static int dwc2_gadget_set_ep0_desc_chain(struct dwc2_hsotg *hsotg, | |
1348 | struct dwc2_hsotg_ep *hs_ep) | |
1349 | { | |
1350 | switch (hsotg->ep0_state) { | |
1351 | case DWC2_EP0_SETUP: | |
1352 | case DWC2_EP0_STATUS_OUT: | |
1353 | hs_ep->desc_list = hsotg->setup_desc[0]; | |
1354 | hs_ep->desc_list_dma = hsotg->setup_desc_dma[0]; | |
1355 | break; | |
1356 | case DWC2_EP0_DATA_IN: | |
1357 | case DWC2_EP0_STATUS_IN: | |
1358 | hs_ep->desc_list = hsotg->ctrl_in_desc; | |
1359 | hs_ep->desc_list_dma = hsotg->ctrl_in_desc_dma; | |
1360 | break; | |
1361 | case DWC2_EP0_DATA_OUT: | |
1362 | hs_ep->desc_list = hsotg->ctrl_out_desc; | |
1363 | hs_ep->desc_list_dma = hsotg->ctrl_out_desc_dma; | |
1364 | break; | |
1365 | default: | |
1366 | dev_err(hsotg->dev, "invalid EP 0 state in queue %d\n", | |
1367 | hsotg->ep0_state); | |
1368 | return -EINVAL; | |
1369 | } | |
1370 | ||
1371 | return 0; | |
1372 | } | |
1373 | ||
1f91b4cc | 1374 | static int dwc2_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req, |
9da51974 | 1375 | gfp_t gfp_flags) |
5b7d70c6 | 1376 | { |
1f91b4cc FB |
1377 | struct dwc2_hsotg_req *hs_req = our_req(req); |
1378 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); | |
941fcce4 | 1379 | struct dwc2_hsotg *hs = hs_ep->parent; |
5b7d70c6 | 1380 | bool first; |
7d24c1b5 | 1381 | int ret; |
729cac69 MH |
1382 | u32 maxsize = 0; |
1383 | u32 mask = 0; | |
1384 | ||
5b7d70c6 BD |
1385 | |
1386 | dev_dbg(hs->dev, "%s: req %p: %d@%p, noi=%d, zero=%d, snok=%d\n", | |
1387 | ep->name, req, req->length, req->buf, req->no_interrupt, | |
1388 | req->zero, req->short_not_ok); | |
1389 | ||
7ababa92 | 1390 | /* Prevent new request submission when controller is suspended */ |
88b02f2c GT |
1391 | if (hs->lx_state != DWC2_L0) { |
1392 | dev_dbg(hs->dev, "%s: submit request only in active state\n", | |
9da51974 | 1393 | __func__); |
7ababa92 GH |
1394 | return -EAGAIN; |
1395 | } | |
1396 | ||
5b7d70c6 BD |
1397 | /* initialise status of the request */ |
1398 | INIT_LIST_HEAD(&hs_req->queue); | |
1399 | req->actual = 0; | |
1400 | req->status = -EINPROGRESS; | |
1401 | ||
860ef6cd MH |
1402 | /* Don't queue ISOC request if length greater than mps*mc */ |
1403 | if (hs_ep->isochronous && | |
1404 | req->length > (hs_ep->mc * hs_ep->ep.maxpacket)) { | |
1405 | dev_err(hs->dev, "req length > maxpacket*mc\n"); | |
1406 | return -EINVAL; | |
1407 | } | |
1408 | ||
729cac69 MH |
1409 | /* In DDMA mode for ISOC's don't queue request if length greater |
1410 | * than descriptor limits. | |
1411 | */ | |
1412 | if (using_desc_dma(hs) && hs_ep->isochronous) { | |
1413 | maxsize = dwc2_gadget_get_desc_params(hs_ep, &mask); | |
1414 | if (hs_ep->dir_in && req->length > maxsize) { | |
1415 | dev_err(hs->dev, "wrong length %d (maxsize=%d)\n", | |
1416 | req->length, maxsize); | |
1417 | return -EINVAL; | |
1418 | } | |
1419 | ||
1420 | if (!hs_ep->dir_in && req->length > hs_ep->ep.maxpacket) { | |
1421 | dev_err(hs->dev, "ISOC OUT: wrong length %d (mps=%d)\n", | |
1422 | req->length, hs_ep->ep.maxpacket); | |
1423 | return -EINVAL; | |
1424 | } | |
1425 | } | |
1426 | ||
1f91b4cc | 1427 | ret = dwc2_hsotg_handle_unaligned_buf_start(hs, hs_ep, hs_req); |
7d24c1b5 MYK |
1428 | if (ret) |
1429 | return ret; | |
1430 | ||
5b7d70c6 BD |
1431 | /* if we're using DMA, sync the buffers as necessary */ |
1432 | if (using_dma(hs)) { | |
1f91b4cc | 1433 | ret = dwc2_hsotg_map_dma(hs, hs_ep, req); |
5b7d70c6 BD |
1434 | if (ret) |
1435 | return ret; | |
1436 | } | |
e02f9aa6 VA |
1437 | /* If using descriptor DMA configure EP0 descriptor chain pointers */ |
1438 | if (using_desc_dma(hs) && !hs_ep->index) { | |
1439 | ret = dwc2_gadget_set_ep0_desc_chain(hs, hs_ep); | |
1440 | if (ret) | |
1441 | return ret; | |
1442 | } | |
5b7d70c6 | 1443 | |
5b7d70c6 BD |
1444 | first = list_empty(&hs_ep->queue); |
1445 | list_add_tail(&hs_req->queue, &hs_ep->queue); | |
1446 | ||
540ccba0 VA |
1447 | /* |
1448 | * Handle DDMA isochronous transfers separately - just add new entry | |
729cac69 | 1449 | * to the descriptor chain. |
540ccba0 VA |
1450 | * Transfer will be started once SW gets either one of NAK or |
1451 | * OutTknEpDis interrupts. | |
1452 | */ | |
729cac69 MH |
1453 | if (using_desc_dma(hs) && hs_ep->isochronous) { |
1454 | if (hs_ep->target_frame != TARGET_FRAME_INITIAL) { | |
10209abe AP |
1455 | dma_addr_t dma_addr = hs_req->req.dma; |
1456 | ||
1457 | if (hs_req->req.num_sgs) { | |
1458 | WARN_ON(hs_req->req.num_sgs > 1); | |
1459 | dma_addr = sg_dma_address(hs_req->req.sg); | |
1460 | } | |
1461 | dwc2_gadget_fill_isoc_desc(hs_ep, dma_addr, | |
729cac69 MH |
1462 | hs_req->req.length); |
1463 | } | |
540ccba0 VA |
1464 | return 0; |
1465 | } | |
1466 | ||
b4c53b4a MH |
1467 | /* Change EP direction if status phase request is after data out */ |
1468 | if (!hs_ep->index && !req->length && !hs_ep->dir_in && | |
1469 | hs->ep0_state == DWC2_EP0_DATA_OUT) | |
1470 | hs_ep->dir_in = 1; | |
1471 | ||
837e9f00 VM |
1472 | if (first) { |
1473 | if (!hs_ep->isochronous) { | |
1474 | dwc2_hsotg_start_req(hs, hs_ep, hs_req, false); | |
1475 | return 0; | |
1476 | } | |
1477 | ||
c7c24e7a AP |
1478 | /* Update current frame number value. */ |
1479 | hs->frame_number = dwc2_hsotg_read_frameno(hs); | |
1480 | while (dwc2_gadget_target_frame_elapsed(hs_ep)) { | |
837e9f00 | 1481 | dwc2_gadget_incr_frame_num(hs_ep); |
c7c24e7a AP |
1482 | /* Update current frame number value once more as it |
1483 | * changes here. | |
1484 | */ | |
1485 | hs->frame_number = dwc2_hsotg_read_frameno(hs); | |
1486 | } | |
5b7d70c6 | 1487 | |
837e9f00 VM |
1488 | if (hs_ep->target_frame != TARGET_FRAME_INITIAL) |
1489 | dwc2_hsotg_start_req(hs, hs_ep, hs_req, false); | |
1490 | } | |
5b7d70c6 BD |
1491 | return 0; |
1492 | } | |
1493 | ||
1f91b4cc | 1494 | static int dwc2_hsotg_ep_queue_lock(struct usb_ep *ep, struct usb_request *req, |
9da51974 | 1495 | gfp_t gfp_flags) |
5ad1d316 | 1496 | { |
1f91b4cc | 1497 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 1498 | struct dwc2_hsotg *hs = hs_ep->parent; |
8879904b JH |
1499 | unsigned long flags; |
1500 | int ret; | |
5ad1d316 LM |
1501 | |
1502 | spin_lock_irqsave(&hs->lock, flags); | |
1f91b4cc | 1503 | ret = dwc2_hsotg_ep_queue(ep, req, gfp_flags); |
5ad1d316 LM |
1504 | spin_unlock_irqrestore(&hs->lock, flags); |
1505 | ||
1506 | return ret; | |
1507 | } | |
1508 | ||
1f91b4cc | 1509 | static void dwc2_hsotg_ep_free_request(struct usb_ep *ep, |
9da51974 | 1510 | struct usb_request *req) |
5b7d70c6 | 1511 | { |
1f91b4cc | 1512 | struct dwc2_hsotg_req *hs_req = our_req(req); |
5b7d70c6 BD |
1513 | |
1514 | kfree(hs_req); | |
1515 | } | |
1516 | ||
1517 | /** | |
1f91b4cc | 1518 | * dwc2_hsotg_complete_oursetup - setup completion callback |
5b7d70c6 BD |
1519 | * @ep: The endpoint the request was on. |
1520 | * @req: The request completed. | |
1521 | * | |
1522 | * Called on completion of any requests the driver itself | |
1523 | * submitted that need cleaning up. | |
1524 | */ | |
1f91b4cc | 1525 | static void dwc2_hsotg_complete_oursetup(struct usb_ep *ep, |
9da51974 | 1526 | struct usb_request *req) |
5b7d70c6 | 1527 | { |
1f91b4cc | 1528 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 1529 | struct dwc2_hsotg *hsotg = hs_ep->parent; |
5b7d70c6 BD |
1530 | |
1531 | dev_dbg(hsotg->dev, "%s: ep %p, req %p\n", __func__, ep, req); | |
1532 | ||
1f91b4cc | 1533 | dwc2_hsotg_ep_free_request(ep, req); |
5b7d70c6 BD |
1534 | } |
1535 | ||
1536 | /** | |
1537 | * ep_from_windex - convert control wIndex value to endpoint | |
1538 | * @hsotg: The driver state. | |
1539 | * @windex: The control request wIndex field (in host order). | |
1540 | * | |
1541 | * Convert the given wIndex into a pointer to an driver endpoint | |
1542 | * structure, or return NULL if it is not a valid endpoint. | |
8b9bc460 | 1543 | */ |
1f91b4cc | 1544 | static struct dwc2_hsotg_ep *ep_from_windex(struct dwc2_hsotg *hsotg, |
9da51974 | 1545 | u32 windex) |
5b7d70c6 | 1546 | { |
5b7d70c6 BD |
1547 | int dir = (windex & USB_DIR_IN) ? 1 : 0; |
1548 | int idx = windex & 0x7F; | |
1549 | ||
1550 | if (windex >= 0x100) | |
1551 | return NULL; | |
1552 | ||
b3f489b2 | 1553 | if (idx > hsotg->num_of_eps) |
5b7d70c6 BD |
1554 | return NULL; |
1555 | ||
f670e9f9 | 1556 | return index_to_ep(hsotg, idx, dir); |
5b7d70c6 BD |
1557 | } |
1558 | ||
9e14d0a5 | 1559 | /** |
1f91b4cc | 1560 | * dwc2_hsotg_set_test_mode - Enable usb Test Modes |
9e14d0a5 GH |
1561 | * @hsotg: The driver state. |
1562 | * @testmode: requested usb test mode | |
1563 | * Enable usb Test Mode requested by the Host. | |
1564 | */ | |
1f91b4cc | 1565 | int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode) |
9e14d0a5 | 1566 | { |
f25c42b8 | 1567 | int dctl = dwc2_readl(hsotg, DCTL); |
9e14d0a5 GH |
1568 | |
1569 | dctl &= ~DCTL_TSTCTL_MASK; | |
1570 | switch (testmode) { | |
62fb45d3 GKH |
1571 | case USB_TEST_J: |
1572 | case USB_TEST_K: | |
1573 | case USB_TEST_SE0_NAK: | |
1574 | case USB_TEST_PACKET: | |
1575 | case USB_TEST_FORCE_ENABLE: | |
9e14d0a5 GH |
1576 | dctl |= testmode << DCTL_TSTCTL_SHIFT; |
1577 | break; | |
1578 | default: | |
1579 | return -EINVAL; | |
1580 | } | |
f25c42b8 | 1581 | dwc2_writel(hsotg, dctl, DCTL); |
9e14d0a5 GH |
1582 | return 0; |
1583 | } | |
1584 | ||
5b7d70c6 | 1585 | /** |
1f91b4cc | 1586 | * dwc2_hsotg_send_reply - send reply to control request |
5b7d70c6 BD |
1587 | * @hsotg: The device state |
1588 | * @ep: Endpoint 0 | |
1589 | * @buff: Buffer for request | |
1590 | * @length: Length of reply. | |
1591 | * | |
1592 | * Create a request and queue it on the given endpoint. This is useful as | |
1593 | * an internal method of sending replies to certain control requests, etc. | |
1594 | */ | |
1f91b4cc | 1595 | static int dwc2_hsotg_send_reply(struct dwc2_hsotg *hsotg, |
9da51974 | 1596 | struct dwc2_hsotg_ep *ep, |
5b7d70c6 BD |
1597 | void *buff, |
1598 | int length) | |
1599 | { | |
1600 | struct usb_request *req; | |
1601 | int ret; | |
1602 | ||
1603 | dev_dbg(hsotg->dev, "%s: buff %p, len %d\n", __func__, buff, length); | |
1604 | ||
1f91b4cc | 1605 | req = dwc2_hsotg_ep_alloc_request(&ep->ep, GFP_ATOMIC); |
5b7d70c6 BD |
1606 | hsotg->ep0_reply = req; |
1607 | if (!req) { | |
1608 | dev_warn(hsotg->dev, "%s: cannot alloc req\n", __func__); | |
1609 | return -ENOMEM; | |
1610 | } | |
1611 | ||
1612 | req->buf = hsotg->ep0_buff; | |
1613 | req->length = length; | |
f71b5e25 MYK |
1614 | /* |
1615 | * zero flag is for sending zlp in DATA IN stage. It has no impact on | |
1616 | * STATUS stage. | |
1617 | */ | |
1618 | req->zero = 0; | |
1f91b4cc | 1619 | req->complete = dwc2_hsotg_complete_oursetup; |
5b7d70c6 BD |
1620 | |
1621 | if (length) | |
1622 | memcpy(req->buf, buff, length); | |
5b7d70c6 | 1623 | |
1f91b4cc | 1624 | ret = dwc2_hsotg_ep_queue(&ep->ep, req, GFP_ATOMIC); |
5b7d70c6 BD |
1625 | if (ret) { |
1626 | dev_warn(hsotg->dev, "%s: cannot queue req\n", __func__); | |
1627 | return ret; | |
1628 | } | |
1629 | ||
1630 | return 0; | |
1631 | } | |
1632 | ||
1633 | /** | |
1f91b4cc | 1634 | * dwc2_hsotg_process_req_status - process request GET_STATUS |
5b7d70c6 BD |
1635 | * @hsotg: The device state |
1636 | * @ctrl: USB control request | |
1637 | */ | |
1f91b4cc | 1638 | static int dwc2_hsotg_process_req_status(struct dwc2_hsotg *hsotg, |
9da51974 | 1639 | struct usb_ctrlrequest *ctrl) |
5b7d70c6 | 1640 | { |
1f91b4cc FB |
1641 | struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0]; |
1642 | struct dwc2_hsotg_ep *ep; | |
5b7d70c6 | 1643 | __le16 reply; |
9a0d6f7c | 1644 | u16 status; |
5b7d70c6 BD |
1645 | int ret; |
1646 | ||
1647 | dev_dbg(hsotg->dev, "%s: USB_REQ_GET_STATUS\n", __func__); | |
1648 | ||
1649 | if (!ep0->dir_in) { | |
1650 | dev_warn(hsotg->dev, "%s: direction out?\n", __func__); | |
1651 | return -EINVAL; | |
1652 | } | |
1653 | ||
1654 | switch (ctrl->bRequestType & USB_RECIP_MASK) { | |
1655 | case USB_RECIP_DEVICE: | |
1a0808cb JK |
1656 | status = hsotg->gadget.is_selfpowered << |
1657 | USB_DEVICE_SELF_POWERED; | |
9a0d6f7c MH |
1658 | status |= hsotg->remote_wakeup_allowed << |
1659 | USB_DEVICE_REMOTE_WAKEUP; | |
1660 | reply = cpu_to_le16(status); | |
5b7d70c6 BD |
1661 | break; |
1662 | ||
1663 | case USB_RECIP_INTERFACE: | |
1664 | /* currently, the data result should be zero */ | |
1665 | reply = cpu_to_le16(0); | |
1666 | break; | |
1667 | ||
1668 | case USB_RECIP_ENDPOINT: | |
1669 | ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex)); | |
1670 | if (!ep) | |
1671 | return -ENOENT; | |
1672 | ||
1673 | reply = cpu_to_le16(ep->halted ? 1 : 0); | |
1674 | break; | |
1675 | ||
1676 | default: | |
1677 | return 0; | |
1678 | } | |
1679 | ||
1680 | if (le16_to_cpu(ctrl->wLength) != 2) | |
1681 | return -EINVAL; | |
1682 | ||
1f91b4cc | 1683 | ret = dwc2_hsotg_send_reply(hsotg, ep0, &reply, 2); |
5b7d70c6 BD |
1684 | if (ret) { |
1685 | dev_err(hsotg->dev, "%s: failed to send reply\n", __func__); | |
1686 | return ret; | |
1687 | } | |
1688 | ||
1689 | return 1; | |
1690 | } | |
1691 | ||
51da43b5 | 1692 | static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now); |
5b7d70c6 | 1693 | |
9c39ddc6 AT |
1694 | /** |
1695 | * get_ep_head - return the first request on the endpoint | |
1696 | * @hs_ep: The controller endpoint to get | |
1697 | * | |
1698 | * Get the first request on the endpoint. | |
1699 | */ | |
1f91b4cc | 1700 | static struct dwc2_hsotg_req *get_ep_head(struct dwc2_hsotg_ep *hs_ep) |
9c39ddc6 | 1701 | { |
ffc4b406 MY |
1702 | return list_first_entry_or_null(&hs_ep->queue, struct dwc2_hsotg_req, |
1703 | queue); | |
9c39ddc6 AT |
1704 | } |
1705 | ||
41cc4cd2 VM |
1706 | /** |
1707 | * dwc2_gadget_start_next_request - Starts next request from ep queue | |
1708 | * @hs_ep: Endpoint structure | |
1709 | * | |
1710 | * If queue is empty and EP is ISOC-OUT - unmasks OUTTKNEPDIS which is masked | |
1711 | * in its handler. Hence we need to unmask it here to be able to do | |
1712 | * resynchronization. | |
1713 | */ | |
1714 | static void dwc2_gadget_start_next_request(struct dwc2_hsotg_ep *hs_ep) | |
1715 | { | |
1716 | u32 mask; | |
1717 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
1718 | int dir_in = hs_ep->dir_in; | |
1719 | struct dwc2_hsotg_req *hs_req; | |
1720 | u32 epmsk_reg = dir_in ? DIEPMSK : DOEPMSK; | |
1721 | ||
1722 | if (!list_empty(&hs_ep->queue)) { | |
1723 | hs_req = get_ep_head(hs_ep); | |
1724 | dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, false); | |
1725 | return; | |
1726 | } | |
1727 | if (!hs_ep->isochronous) | |
1728 | return; | |
1729 | ||
1730 | if (dir_in) { | |
1731 | dev_dbg(hsotg->dev, "%s: No more ISOC-IN requests\n", | |
1732 | __func__); | |
1733 | } else { | |
1734 | dev_dbg(hsotg->dev, "%s: No more ISOC-OUT requests\n", | |
1735 | __func__); | |
f25c42b8 | 1736 | mask = dwc2_readl(hsotg, epmsk_reg); |
41cc4cd2 | 1737 | mask |= DOEPMSK_OUTTKNEPDISMSK; |
f25c42b8 | 1738 | dwc2_writel(hsotg, mask, epmsk_reg); |
41cc4cd2 VM |
1739 | } |
1740 | } | |
1741 | ||
5b7d70c6 | 1742 | /** |
1f91b4cc | 1743 | * dwc2_hsotg_process_req_feature - process request {SET,CLEAR}_FEATURE |
5b7d70c6 BD |
1744 | * @hsotg: The device state |
1745 | * @ctrl: USB control request | |
1746 | */ | |
1f91b4cc | 1747 | static int dwc2_hsotg_process_req_feature(struct dwc2_hsotg *hsotg, |
9da51974 | 1748 | struct usb_ctrlrequest *ctrl) |
5b7d70c6 | 1749 | { |
1f91b4cc FB |
1750 | struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0]; |
1751 | struct dwc2_hsotg_req *hs_req; | |
5b7d70c6 | 1752 | bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE); |
1f91b4cc | 1753 | struct dwc2_hsotg_ep *ep; |
26ab3d0c | 1754 | int ret; |
bd9ef7bf | 1755 | bool halted; |
9e14d0a5 GH |
1756 | u32 recip; |
1757 | u32 wValue; | |
1758 | u32 wIndex; | |
5b7d70c6 BD |
1759 | |
1760 | dev_dbg(hsotg->dev, "%s: %s_FEATURE\n", | |
1761 | __func__, set ? "SET" : "CLEAR"); | |
1762 | ||
9e14d0a5 GH |
1763 | wValue = le16_to_cpu(ctrl->wValue); |
1764 | wIndex = le16_to_cpu(ctrl->wIndex); | |
1765 | recip = ctrl->bRequestType & USB_RECIP_MASK; | |
1766 | ||
1767 | switch (recip) { | |
1768 | case USB_RECIP_DEVICE: | |
1769 | switch (wValue) { | |
fa389a6d | 1770 | case USB_DEVICE_REMOTE_WAKEUP: |
9a0d6f7c MH |
1771 | if (set) |
1772 | hsotg->remote_wakeup_allowed = 1; | |
1773 | else | |
1774 | hsotg->remote_wakeup_allowed = 0; | |
fa389a6d VM |
1775 | break; |
1776 | ||
9e14d0a5 GH |
1777 | case USB_DEVICE_TEST_MODE: |
1778 | if ((wIndex & 0xff) != 0) | |
1779 | return -EINVAL; | |
1780 | if (!set) | |
1781 | return -EINVAL; | |
1782 | ||
1783 | hsotg->test_mode = wIndex >> 8; | |
9e14d0a5 GH |
1784 | break; |
1785 | default: | |
1786 | return -ENOENT; | |
1787 | } | |
9a0d6f7c MH |
1788 | |
1789 | ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0); | |
1790 | if (ret) { | |
1791 | dev_err(hsotg->dev, | |
1792 | "%s: failed to send reply\n", __func__); | |
1793 | return ret; | |
1794 | } | |
9e14d0a5 GH |
1795 | break; |
1796 | ||
1797 | case USB_RECIP_ENDPOINT: | |
1798 | ep = ep_from_windex(hsotg, wIndex); | |
5b7d70c6 BD |
1799 | if (!ep) { |
1800 | dev_dbg(hsotg->dev, "%s: no endpoint for 0x%04x\n", | |
9e14d0a5 | 1801 | __func__, wIndex); |
5b7d70c6 BD |
1802 | return -ENOENT; |
1803 | } | |
1804 | ||
9e14d0a5 | 1805 | switch (wValue) { |
5b7d70c6 | 1806 | case USB_ENDPOINT_HALT: |
bd9ef7bf RB |
1807 | halted = ep->halted; |
1808 | ||
b833ce15 MH |
1809 | if (!ep->wedged) |
1810 | dwc2_hsotg_ep_sethalt(&ep->ep, set, true); | |
26ab3d0c | 1811 | |
1f91b4cc | 1812 | ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0); |
26ab3d0c AT |
1813 | if (ret) { |
1814 | dev_err(hsotg->dev, | |
1815 | "%s: failed to send reply\n", __func__); | |
1816 | return ret; | |
1817 | } | |
9c39ddc6 | 1818 | |
bd9ef7bf RB |
1819 | /* |
1820 | * we have to complete all requests for ep if it was | |
1821 | * halted, and the halt was cleared by CLEAR_FEATURE | |
1822 | */ | |
1823 | ||
1824 | if (!set && halted) { | |
9c39ddc6 AT |
1825 | /* |
1826 | * If we have request in progress, | |
1827 | * then complete it | |
1828 | */ | |
1829 | if (ep->req) { | |
1830 | hs_req = ep->req; | |
1831 | ep->req = NULL; | |
1832 | list_del_init(&hs_req->queue); | |
c00dd4a6 GH |
1833 | if (hs_req->req.complete) { |
1834 | spin_unlock(&hsotg->lock); | |
1835 | usb_gadget_giveback_request( | |
1836 | &ep->ep, &hs_req->req); | |
1837 | spin_lock(&hsotg->lock); | |
1838 | } | |
9c39ddc6 AT |
1839 | } |
1840 | ||
1841 | /* If we have pending request, then start it */ | |
34c0887f | 1842 | if (!ep->req) |
41cc4cd2 | 1843 | dwc2_gadget_start_next_request(ep); |
9c39ddc6 AT |
1844 | } |
1845 | ||
5b7d70c6 BD |
1846 | break; |
1847 | ||
1848 | default: | |
1849 | return -ENOENT; | |
1850 | } | |
9e14d0a5 GH |
1851 | break; |
1852 | default: | |
1853 | return -ENOENT; | |
1854 | } | |
5b7d70c6 BD |
1855 | return 1; |
1856 | } | |
1857 | ||
1f91b4cc | 1858 | static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg); |
ab93e014 | 1859 | |
c9f721b2 | 1860 | /** |
1f91b4cc | 1861 | * dwc2_hsotg_stall_ep0 - stall ep0 |
c9f721b2 RB |
1862 | * @hsotg: The device state |
1863 | * | |
1864 | * Set stall for ep0 as response for setup request. | |
1865 | */ | |
1f91b4cc | 1866 | static void dwc2_hsotg_stall_ep0(struct dwc2_hsotg *hsotg) |
e9ebe7c3 | 1867 | { |
1f91b4cc | 1868 | struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0]; |
c9f721b2 RB |
1869 | u32 reg; |
1870 | u32 ctrl; | |
1871 | ||
1872 | dev_dbg(hsotg->dev, "ep0 stall (dir=%d)\n", ep0->dir_in); | |
1873 | reg = (ep0->dir_in) ? DIEPCTL0 : DOEPCTL0; | |
1874 | ||
1875 | /* | |
1876 | * DxEPCTL_Stall will be cleared by EP once it has | |
1877 | * taken effect, so no need to clear later. | |
1878 | */ | |
1879 | ||
f25c42b8 | 1880 | ctrl = dwc2_readl(hsotg, reg); |
47a1685f DN |
1881 | ctrl |= DXEPCTL_STALL; |
1882 | ctrl |= DXEPCTL_CNAK; | |
f25c42b8 | 1883 | dwc2_writel(hsotg, ctrl, reg); |
c9f721b2 RB |
1884 | |
1885 | dev_dbg(hsotg->dev, | |
47a1685f | 1886 | "written DXEPCTL=0x%08x to %08x (DXEPCTL=0x%08x)\n", |
f25c42b8 | 1887 | ctrl, reg, dwc2_readl(hsotg, reg)); |
c9f721b2 RB |
1888 | |
1889 | /* | |
1890 | * complete won't be called, so we enqueue | |
1891 | * setup request here | |
1892 | */ | |
1f91b4cc | 1893 | dwc2_hsotg_enqueue_setup(hsotg); |
c9f721b2 RB |
1894 | } |
1895 | ||
5b7d70c6 | 1896 | /** |
1f91b4cc | 1897 | * dwc2_hsotg_process_control - process a control request |
5b7d70c6 BD |
1898 | * @hsotg: The device state |
1899 | * @ctrl: The control request received | |
1900 | * | |
1901 | * The controller has received the SETUP phase of a control request, and | |
1902 | * needs to work out what to do next (and whether to pass it on to the | |
1903 | * gadget driver). | |
1904 | */ | |
1f91b4cc | 1905 | static void dwc2_hsotg_process_control(struct dwc2_hsotg *hsotg, |
9da51974 | 1906 | struct usb_ctrlrequest *ctrl) |
5b7d70c6 | 1907 | { |
1f91b4cc | 1908 | struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0]; |
5b7d70c6 BD |
1909 | int ret = 0; |
1910 | u32 dcfg; | |
1911 | ||
e525e743 MYK |
1912 | dev_dbg(hsotg->dev, |
1913 | "ctrl Type=%02x, Req=%02x, V=%04x, I=%04x, L=%04x\n", | |
1914 | ctrl->bRequestType, ctrl->bRequest, ctrl->wValue, | |
1915 | ctrl->wIndex, ctrl->wLength); | |
5b7d70c6 | 1916 | |
fe0b94ab MYK |
1917 | if (ctrl->wLength == 0) { |
1918 | ep0->dir_in = 1; | |
1919 | hsotg->ep0_state = DWC2_EP0_STATUS_IN; | |
1920 | } else if (ctrl->bRequestType & USB_DIR_IN) { | |
5b7d70c6 | 1921 | ep0->dir_in = 1; |
fe0b94ab MYK |
1922 | hsotg->ep0_state = DWC2_EP0_DATA_IN; |
1923 | } else { | |
1924 | ep0->dir_in = 0; | |
1925 | hsotg->ep0_state = DWC2_EP0_DATA_OUT; | |
1926 | } | |
5b7d70c6 BD |
1927 | |
1928 | if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) { | |
1929 | switch (ctrl->bRequest) { | |
1930 | case USB_REQ_SET_ADDRESS: | |
6d713c15 | 1931 | hsotg->connected = 1; |
f25c42b8 | 1932 | dcfg = dwc2_readl(hsotg, DCFG); |
47a1685f | 1933 | dcfg &= ~DCFG_DEVADDR_MASK; |
d5dbd3f7 PZ |
1934 | dcfg |= (le16_to_cpu(ctrl->wValue) << |
1935 | DCFG_DEVADDR_SHIFT) & DCFG_DEVADDR_MASK; | |
f25c42b8 | 1936 | dwc2_writel(hsotg, dcfg, DCFG); |
5b7d70c6 BD |
1937 | |
1938 | dev_info(hsotg->dev, "new address %d\n", ctrl->wValue); | |
1939 | ||
1f91b4cc | 1940 | ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0); |
5b7d70c6 BD |
1941 | return; |
1942 | ||
1943 | case USB_REQ_GET_STATUS: | |
1f91b4cc | 1944 | ret = dwc2_hsotg_process_req_status(hsotg, ctrl); |
5b7d70c6 BD |
1945 | break; |
1946 | ||
1947 | case USB_REQ_CLEAR_FEATURE: | |
1948 | case USB_REQ_SET_FEATURE: | |
1f91b4cc | 1949 | ret = dwc2_hsotg_process_req_feature(hsotg, ctrl); |
5b7d70c6 BD |
1950 | break; |
1951 | } | |
1952 | } | |
1953 | ||
1954 | /* as a fallback, try delivering it to the driver to deal with */ | |
1955 | ||
1956 | if (ret == 0 && hsotg->driver) { | |
93f599f2 | 1957 | spin_unlock(&hsotg->lock); |
5b7d70c6 | 1958 | ret = hsotg->driver->setup(&hsotg->gadget, ctrl); |
93f599f2 | 1959 | spin_lock(&hsotg->lock); |
5b7d70c6 BD |
1960 | if (ret < 0) |
1961 | dev_dbg(hsotg->dev, "driver->setup() ret %d\n", ret); | |
1962 | } | |
1963 | ||
b4c53b4a MH |
1964 | hsotg->delayed_status = false; |
1965 | if (ret == USB_GADGET_DELAYED_STATUS) | |
1966 | hsotg->delayed_status = true; | |
1967 | ||
8b9bc460 LM |
1968 | /* |
1969 | * the request is either unhandlable, or is not formatted correctly | |
5b7d70c6 BD |
1970 | * so respond with a STALL for the status stage to indicate failure. |
1971 | */ | |
1972 | ||
c9f721b2 | 1973 | if (ret < 0) |
1f91b4cc | 1974 | dwc2_hsotg_stall_ep0(hsotg); |
5b7d70c6 BD |
1975 | } |
1976 | ||
5b7d70c6 | 1977 | /** |
1f91b4cc | 1978 | * dwc2_hsotg_complete_setup - completion of a setup transfer |
5b7d70c6 BD |
1979 | * @ep: The endpoint the request was on. |
1980 | * @req: The request completed. | |
1981 | * | |
1982 | * Called on completion of any requests the driver itself submitted for | |
1983 | * EP0 setup packets | |
1984 | */ | |
1f91b4cc | 1985 | static void dwc2_hsotg_complete_setup(struct usb_ep *ep, |
9da51974 | 1986 | struct usb_request *req) |
5b7d70c6 | 1987 | { |
1f91b4cc | 1988 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 1989 | struct dwc2_hsotg *hsotg = hs_ep->parent; |
5b7d70c6 BD |
1990 | |
1991 | if (req->status < 0) { | |
1992 | dev_dbg(hsotg->dev, "%s: failed %d\n", __func__, req->status); | |
1993 | return; | |
1994 | } | |
1995 | ||
93f599f2 | 1996 | spin_lock(&hsotg->lock); |
5b7d70c6 | 1997 | if (req->actual == 0) |
1f91b4cc | 1998 | dwc2_hsotg_enqueue_setup(hsotg); |
5b7d70c6 | 1999 | else |
1f91b4cc | 2000 | dwc2_hsotg_process_control(hsotg, req->buf); |
93f599f2 | 2001 | spin_unlock(&hsotg->lock); |
5b7d70c6 BD |
2002 | } |
2003 | ||
2004 | /** | |
1f91b4cc | 2005 | * dwc2_hsotg_enqueue_setup - start a request for EP0 packets |
5b7d70c6 BD |
2006 | * @hsotg: The device state. |
2007 | * | |
2008 | * Enqueue a request on EP0 if necessary to received any SETUP packets | |
2009 | * received from the host. | |
2010 | */ | |
1f91b4cc | 2011 | static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg) |
5b7d70c6 BD |
2012 | { |
2013 | struct usb_request *req = hsotg->ctrl_req; | |
1f91b4cc | 2014 | struct dwc2_hsotg_req *hs_req = our_req(req); |
5b7d70c6 BD |
2015 | int ret; |
2016 | ||
2017 | dev_dbg(hsotg->dev, "%s: queueing setup request\n", __func__); | |
2018 | ||
2019 | req->zero = 0; | |
2020 | req->length = 8; | |
2021 | req->buf = hsotg->ctrl_buff; | |
1f91b4cc | 2022 | req->complete = dwc2_hsotg_complete_setup; |
5b7d70c6 BD |
2023 | |
2024 | if (!list_empty(&hs_req->queue)) { | |
2025 | dev_dbg(hsotg->dev, "%s already queued???\n", __func__); | |
2026 | return; | |
2027 | } | |
2028 | ||
c6f5c050 | 2029 | hsotg->eps_out[0]->dir_in = 0; |
8a20fa45 | 2030 | hsotg->eps_out[0]->send_zlp = 0; |
fe0b94ab | 2031 | hsotg->ep0_state = DWC2_EP0_SETUP; |
5b7d70c6 | 2032 | |
1f91b4cc | 2033 | ret = dwc2_hsotg_ep_queue(&hsotg->eps_out[0]->ep, req, GFP_ATOMIC); |
5b7d70c6 BD |
2034 | if (ret < 0) { |
2035 | dev_err(hsotg->dev, "%s: failed queue (%d)\n", __func__, ret); | |
8b9bc460 LM |
2036 | /* |
2037 | * Don't think there's much we can do other than watch the | |
2038 | * driver fail. | |
2039 | */ | |
5b7d70c6 BD |
2040 | } |
2041 | } | |
2042 | ||
1f91b4cc | 2043 | static void dwc2_hsotg_program_zlp(struct dwc2_hsotg *hsotg, |
9da51974 | 2044 | struct dwc2_hsotg_ep *hs_ep) |
fe0b94ab MYK |
2045 | { |
2046 | u32 ctrl; | |
2047 | u8 index = hs_ep->index; | |
2048 | u32 epctl_reg = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index); | |
2049 | u32 epsiz_reg = hs_ep->dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index); | |
2050 | ||
ccb34a91 MYK |
2051 | if (hs_ep->dir_in) |
2052 | dev_dbg(hsotg->dev, "Sending zero-length packet on ep%d\n", | |
e02f9aa6 | 2053 | index); |
ccb34a91 MYK |
2054 | else |
2055 | dev_dbg(hsotg->dev, "Receiving zero-length packet on ep%d\n", | |
e02f9aa6 VA |
2056 | index); |
2057 | if (using_desc_dma(hsotg)) { | |
066cfd07 AP |
2058 | /* Not specific buffer needed for ep0 ZLP */ |
2059 | dma_addr_t dma = hs_ep->desc_list_dma; | |
2060 | ||
201ec568 MH |
2061 | if (!index) |
2062 | dwc2_gadget_set_ep0_desc_chain(hsotg, hs_ep); | |
2063 | ||
066cfd07 | 2064 | dwc2_gadget_config_nonisoc_xfer_ddma(hs_ep, dma, 0); |
e02f9aa6 | 2065 | } else { |
f25c42b8 GS |
2066 | dwc2_writel(hsotg, DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) | |
2067 | DXEPTSIZ_XFERSIZE(0), | |
e02f9aa6 VA |
2068 | epsiz_reg); |
2069 | } | |
fe0b94ab | 2070 | |
f25c42b8 | 2071 | ctrl = dwc2_readl(hsotg, epctl_reg); |
fe0b94ab MYK |
2072 | ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */ |
2073 | ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */ | |
2074 | ctrl |= DXEPCTL_USBACTEP; | |
f25c42b8 | 2075 | dwc2_writel(hsotg, ctrl, epctl_reg); |
fe0b94ab MYK |
2076 | } |
2077 | ||
5b7d70c6 | 2078 | /** |
1f91b4cc | 2079 | * dwc2_hsotg_complete_request - complete a request given to us |
5b7d70c6 BD |
2080 | * @hsotg: The device state. |
2081 | * @hs_ep: The endpoint the request was on. | |
2082 | * @hs_req: The request to complete. | |
2083 | * @result: The result code (0 => Ok, otherwise errno) | |
2084 | * | |
2085 | * The given request has finished, so call the necessary completion | |
2086 | * if it has one and then look to see if we can start a new request | |
2087 | * on the endpoint. | |
2088 | * | |
2089 | * Note, expects the ep to already be locked as appropriate. | |
8b9bc460 | 2090 | */ |
1f91b4cc | 2091 | static void dwc2_hsotg_complete_request(struct dwc2_hsotg *hsotg, |
9da51974 | 2092 | struct dwc2_hsotg_ep *hs_ep, |
1f91b4cc | 2093 | struct dwc2_hsotg_req *hs_req, |
5b7d70c6 BD |
2094 | int result) |
2095 | { | |
5b7d70c6 BD |
2096 | if (!hs_req) { |
2097 | dev_dbg(hsotg->dev, "%s: nothing to complete?\n", __func__); | |
2098 | return; | |
2099 | } | |
2100 | ||
2101 | dev_dbg(hsotg->dev, "complete: ep %p %s, req %p, %d => %p\n", | |
2102 | hs_ep, hs_ep->ep.name, hs_req, result, hs_req->req.complete); | |
2103 | ||
8b9bc460 LM |
2104 | /* |
2105 | * only replace the status if we've not already set an error | |
2106 | * from a previous transaction | |
2107 | */ | |
5b7d70c6 BD |
2108 | |
2109 | if (hs_req->req.status == -EINPROGRESS) | |
2110 | hs_req->req.status = result; | |
2111 | ||
44583fec YL |
2112 | if (using_dma(hsotg)) |
2113 | dwc2_hsotg_unmap_dma(hsotg, hs_ep, hs_req); | |
2114 | ||
1f91b4cc | 2115 | dwc2_hsotg_handle_unaligned_buf_complete(hsotg, hs_ep, hs_req); |
7d24c1b5 | 2116 | |
5b7d70c6 BD |
2117 | hs_ep->req = NULL; |
2118 | list_del_init(&hs_req->queue); | |
2119 | ||
8b9bc460 LM |
2120 | /* |
2121 | * call the complete request with the locks off, just in case the | |
2122 | * request tries to queue more work for this endpoint. | |
2123 | */ | |
5b7d70c6 BD |
2124 | |
2125 | if (hs_req->req.complete) { | |
22258f49 | 2126 | spin_unlock(&hsotg->lock); |
304f7e5e | 2127 | usb_gadget_giveback_request(&hs_ep->ep, &hs_req->req); |
22258f49 | 2128 | spin_lock(&hsotg->lock); |
5b7d70c6 BD |
2129 | } |
2130 | ||
540ccba0 VA |
2131 | /* In DDMA don't need to proceed to starting of next ISOC request */ |
2132 | if (using_desc_dma(hsotg) && hs_ep->isochronous) | |
2133 | return; | |
2134 | ||
8b9bc460 LM |
2135 | /* |
2136 | * Look to see if there is anything else to do. Note, the completion | |
5b7d70c6 | 2137 | * of the previous request may have caused a new request to be started |
8b9bc460 LM |
2138 | * so be careful when doing this. |
2139 | */ | |
5b7d70c6 | 2140 | |
34c0887f | 2141 | if (!hs_ep->req && result >= 0) |
41cc4cd2 | 2142 | dwc2_gadget_start_next_request(hs_ep); |
5b7d70c6 BD |
2143 | } |
2144 | ||
540ccba0 VA |
2145 | /* |
2146 | * dwc2_gadget_complete_isoc_request_ddma - complete an isoc request in DDMA | |
2147 | * @hs_ep: The endpoint the request was on. | |
2148 | * | |
2149 | * Get first request from the ep queue, determine descriptor on which complete | |
729cac69 MH |
2150 | * happened. SW discovers which descriptor currently in use by HW, adjusts |
2151 | * dma_address and calculates index of completed descriptor based on the value | |
2152 | * of DEPDMA register. Update actual length of request, giveback to gadget. | |
540ccba0 VA |
2153 | */ |
2154 | static void dwc2_gadget_complete_isoc_request_ddma(struct dwc2_hsotg_ep *hs_ep) | |
2155 | { | |
2156 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
2157 | struct dwc2_hsotg_req *hs_req; | |
2158 | struct usb_request *ureq; | |
540ccba0 VA |
2159 | u32 desc_sts; |
2160 | u32 mask; | |
2161 | ||
729cac69 | 2162 | desc_sts = hs_ep->desc_list[hs_ep->compl_desc].status; |
540ccba0 | 2163 | |
729cac69 MH |
2164 | /* Process only descriptors with buffer status set to DMA done */ |
2165 | while ((desc_sts & DEV_DMA_BUFF_STS_MASK) >> | |
2166 | DEV_DMA_BUFF_STS_SHIFT == DEV_DMA_BUFF_STS_DMADONE) { | |
540ccba0 | 2167 | |
729cac69 MH |
2168 | hs_req = get_ep_head(hs_ep); |
2169 | if (!hs_req) { | |
2170 | dev_warn(hsotg->dev, "%s: ISOC EP queue empty\n", __func__); | |
2171 | return; | |
2172 | } | |
2173 | ureq = &hs_req->req; | |
2174 | ||
2175 | /* Check completion status */ | |
2176 | if ((desc_sts & DEV_DMA_STS_MASK) >> DEV_DMA_STS_SHIFT == | |
2177 | DEV_DMA_STS_SUCC) { | |
2178 | mask = hs_ep->dir_in ? DEV_DMA_ISOC_TX_NBYTES_MASK : | |
2179 | DEV_DMA_ISOC_RX_NBYTES_MASK; | |
2180 | ureq->actual = ureq->length - ((desc_sts & mask) >> | |
2181 | DEV_DMA_ISOC_NBYTES_SHIFT); | |
2182 | ||
2183 | /* Adjust actual len for ISOC Out if len is | |
2184 | * not align of 4 | |
2185 | */ | |
2186 | if (!hs_ep->dir_in && ureq->length & 0x3) | |
2187 | ureq->actual += 4 - (ureq->length & 0x3); | |
c8006f67 MH |
2188 | |
2189 | /* Set actual frame number for completed transfers */ | |
2190 | ureq->frame_number = | |
2191 | (desc_sts & DEV_DMA_ISOC_FRNUM_MASK) >> | |
2192 | DEV_DMA_ISOC_FRNUM_SHIFT; | |
729cac69 | 2193 | } |
540ccba0 | 2194 | |
729cac69 | 2195 | dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0); |
95d2b037 | 2196 | |
729cac69 | 2197 | hs_ep->compl_desc++; |
54f37f56 | 2198 | if (hs_ep->compl_desc > (MAX_DMA_DESC_NUM_HS_ISOC - 1)) |
729cac69 MH |
2199 | hs_ep->compl_desc = 0; |
2200 | desc_sts = hs_ep->desc_list[hs_ep->compl_desc].status; | |
2201 | } | |
540ccba0 VA |
2202 | } |
2203 | ||
2204 | /* | |
729cac69 MH |
2205 | * dwc2_gadget_handle_isoc_bna - handle BNA interrupt for ISOC. |
2206 | * @hs_ep: The isochronous endpoint. | |
540ccba0 | 2207 | * |
729cac69 MH |
2208 | * If EP ISOC OUT then need to flush RX FIFO to remove source of BNA |
2209 | * interrupt. Reset target frame and next_desc to allow to start | |
2210 | * ISOC's on NAK interrupt for IN direction or on OUTTKNEPDIS | |
2211 | * interrupt for OUT direction. | |
540ccba0 | 2212 | */ |
729cac69 | 2213 | static void dwc2_gadget_handle_isoc_bna(struct dwc2_hsotg_ep *hs_ep) |
540ccba0 VA |
2214 | { |
2215 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
540ccba0 | 2216 | |
729cac69 MH |
2217 | if (!hs_ep->dir_in) |
2218 | dwc2_flush_rx_fifo(hsotg); | |
2219 | dwc2_hsotg_complete_request(hsotg, hs_ep, get_ep_head(hs_ep), 0); | |
540ccba0 | 2220 | |
729cac69 MH |
2221 | hs_ep->target_frame = TARGET_FRAME_INITIAL; |
2222 | hs_ep->next_desc = 0; | |
2223 | hs_ep->compl_desc = 0; | |
540ccba0 VA |
2224 | } |
2225 | ||
5b7d70c6 | 2226 | /** |
1f91b4cc | 2227 | * dwc2_hsotg_rx_data - receive data from the FIFO for an endpoint |
5b7d70c6 BD |
2228 | * @hsotg: The device state. |
2229 | * @ep_idx: The endpoint index for the data | |
2230 | * @size: The size of data in the fifo, in bytes | |
2231 | * | |
2232 | * The FIFO status shows there is data to read from the FIFO for a given | |
2233 | * endpoint, so sort out whether we need to read the data into a request | |
2234 | * that has been made for that endpoint. | |
2235 | */ | |
1f91b4cc | 2236 | static void dwc2_hsotg_rx_data(struct dwc2_hsotg *hsotg, int ep_idx, int size) |
5b7d70c6 | 2237 | { |
1f91b4cc FB |
2238 | struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[ep_idx]; |
2239 | struct dwc2_hsotg_req *hs_req = hs_ep->req; | |
5b7d70c6 BD |
2240 | int to_read; |
2241 | int max_req; | |
2242 | int read_ptr; | |
2243 | ||
2244 | if (!hs_req) { | |
f25c42b8 | 2245 | u32 epctl = dwc2_readl(hsotg, DOEPCTL(ep_idx)); |
5b7d70c6 BD |
2246 | int ptr; |
2247 | ||
6b448af4 | 2248 | dev_dbg(hsotg->dev, |
9da51974 | 2249 | "%s: FIFO %d bytes on ep%d but no req (DXEPCTl=0x%08x)\n", |
5b7d70c6 BD |
2250 | __func__, size, ep_idx, epctl); |
2251 | ||
2252 | /* dump the data from the FIFO, we've nothing we can do */ | |
2253 | for (ptr = 0; ptr < size; ptr += 4) | |
f25c42b8 | 2254 | (void)dwc2_readl(hsotg, EPFIFO(ep_idx)); |
5b7d70c6 BD |
2255 | |
2256 | return; | |
2257 | } | |
2258 | ||
5b7d70c6 BD |
2259 | to_read = size; |
2260 | read_ptr = hs_req->req.actual; | |
2261 | max_req = hs_req->req.length - read_ptr; | |
2262 | ||
a33e7136 BD |
2263 | dev_dbg(hsotg->dev, "%s: read %d/%d, done %d/%d\n", |
2264 | __func__, to_read, max_req, read_ptr, hs_req->req.length); | |
2265 | ||
5b7d70c6 | 2266 | if (to_read > max_req) { |
8b9bc460 LM |
2267 | /* |
2268 | * more data appeared than we where willing | |
5b7d70c6 BD |
2269 | * to deal with in this request. |
2270 | */ | |
2271 | ||
2272 | /* currently we don't deal this */ | |
2273 | WARN_ON_ONCE(1); | |
2274 | } | |
2275 | ||
5b7d70c6 BD |
2276 | hs_ep->total_data += to_read; |
2277 | hs_req->req.actual += to_read; | |
2278 | to_read = DIV_ROUND_UP(to_read, 4); | |
2279 | ||
8b9bc460 LM |
2280 | /* |
2281 | * note, we might over-write the buffer end by 3 bytes depending on | |
2282 | * alignment of the data. | |
2283 | */ | |
342ccce1 GS |
2284 | dwc2_readl_rep(hsotg, EPFIFO(ep_idx), |
2285 | hs_req->req.buf + read_ptr, to_read); | |
5b7d70c6 BD |
2286 | } |
2287 | ||
2288 | /** | |
1f91b4cc | 2289 | * dwc2_hsotg_ep0_zlp - send/receive zero-length packet on control endpoint |
5b7d70c6 | 2290 | * @hsotg: The device instance |
fe0b94ab | 2291 | * @dir_in: If IN zlp |
5b7d70c6 BD |
2292 | * |
2293 | * Generate a zero-length IN packet request for terminating a SETUP | |
2294 | * transaction. | |
2295 | * | |
2296 | * Note, since we don't write any data to the TxFIFO, then it is | |
25985edc | 2297 | * currently believed that we do not need to wait for any space in |
5b7d70c6 BD |
2298 | * the TxFIFO. |
2299 | */ | |
1f91b4cc | 2300 | static void dwc2_hsotg_ep0_zlp(struct dwc2_hsotg *hsotg, bool dir_in) |
5b7d70c6 | 2301 | { |
c6f5c050 | 2302 | /* eps_out[0] is used in both directions */ |
fe0b94ab MYK |
2303 | hsotg->eps_out[0]->dir_in = dir_in; |
2304 | hsotg->ep0_state = dir_in ? DWC2_EP0_STATUS_IN : DWC2_EP0_STATUS_OUT; | |
5b7d70c6 | 2305 | |
1f91b4cc | 2306 | dwc2_hsotg_program_zlp(hsotg, hsotg->eps_out[0]); |
5b7d70c6 BD |
2307 | } |
2308 | ||
ec1f9d9f | 2309 | static void dwc2_hsotg_change_ep_iso_parity(struct dwc2_hsotg *hsotg, |
9da51974 | 2310 | u32 epctl_reg) |
ec1f9d9f RB |
2311 | { |
2312 | u32 ctrl; | |
2313 | ||
f25c42b8 | 2314 | ctrl = dwc2_readl(hsotg, epctl_reg); |
ec1f9d9f RB |
2315 | if (ctrl & DXEPCTL_EOFRNUM) |
2316 | ctrl |= DXEPCTL_SETEVENFR; | |
2317 | else | |
2318 | ctrl |= DXEPCTL_SETODDFR; | |
f25c42b8 | 2319 | dwc2_writel(hsotg, ctrl, epctl_reg); |
ec1f9d9f RB |
2320 | } |
2321 | ||
aa3e8bc8 VA |
2322 | /* |
2323 | * dwc2_gadget_get_xfersize_ddma - get transferred bytes amount from desc | |
2324 | * @hs_ep - The endpoint on which transfer went | |
2325 | * | |
2326 | * Iterate over endpoints descriptor chain and get info on bytes remained | |
2327 | * in DMA descriptors after transfer has completed. Used for non isoc EPs. | |
2328 | */ | |
2329 | static unsigned int dwc2_gadget_get_xfersize_ddma(struct dwc2_hsotg_ep *hs_ep) | |
2330 | { | |
b2c586eb | 2331 | const struct usb_endpoint_descriptor *ep_desc = hs_ep->ep.desc; |
aa3e8bc8 VA |
2332 | struct dwc2_hsotg *hsotg = hs_ep->parent; |
2333 | unsigned int bytes_rem = 0; | |
b2c586eb | 2334 | unsigned int bytes_rem_correction = 0; |
aa3e8bc8 VA |
2335 | struct dwc2_dma_desc *desc = hs_ep->desc_list; |
2336 | int i; | |
2337 | u32 status; | |
b2c586eb MH |
2338 | u32 mps = hs_ep->ep.maxpacket; |
2339 | int dir_in = hs_ep->dir_in; | |
aa3e8bc8 VA |
2340 | |
2341 | if (!desc) | |
2342 | return -EINVAL; | |
2343 | ||
b2c586eb MH |
2344 | /* Interrupt OUT EP with mps not multiple of 4 */ |
2345 | if (hs_ep->index) | |
2346 | if (usb_endpoint_xfer_int(ep_desc) && !dir_in && (mps % 4)) | |
2347 | bytes_rem_correction = 4 - (mps % 4); | |
2348 | ||
aa3e8bc8 VA |
2349 | for (i = 0; i < hs_ep->desc_count; ++i) { |
2350 | status = desc->status; | |
2351 | bytes_rem += status & DEV_DMA_NBYTES_MASK; | |
b2c586eb | 2352 | bytes_rem -= bytes_rem_correction; |
aa3e8bc8 VA |
2353 | |
2354 | if (status & DEV_DMA_STS_MASK) | |
2355 | dev_err(hsotg->dev, "descriptor %d closed with %x\n", | |
2356 | i, status & DEV_DMA_STS_MASK); | |
b2c586eb MH |
2357 | |
2358 | if (status & DEV_DMA_L) | |
2359 | break; | |
2360 | ||
5acb4b97 | 2361 | desc++; |
aa3e8bc8 VA |
2362 | } |
2363 | ||
2364 | return bytes_rem; | |
2365 | } | |
2366 | ||
5b7d70c6 | 2367 | /** |
1f91b4cc | 2368 | * dwc2_hsotg_handle_outdone - handle receiving OutDone/SetupDone from RXFIFO |
5b7d70c6 BD |
2369 | * @hsotg: The device instance |
2370 | * @epnum: The endpoint received from | |
5b7d70c6 BD |
2371 | * |
2372 | * The RXFIFO has delivered an OutDone event, which means that the data | |
2373 | * transfer for an OUT endpoint has been completed, either by a short | |
2374 | * packet or by the finish of a transfer. | |
8b9bc460 | 2375 | */ |
1f91b4cc | 2376 | static void dwc2_hsotg_handle_outdone(struct dwc2_hsotg *hsotg, int epnum) |
5b7d70c6 | 2377 | { |
f25c42b8 | 2378 | u32 epsize = dwc2_readl(hsotg, DOEPTSIZ(epnum)); |
1f91b4cc FB |
2379 | struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[epnum]; |
2380 | struct dwc2_hsotg_req *hs_req = hs_ep->req; | |
5b7d70c6 | 2381 | struct usb_request *req = &hs_req->req; |
9da51974 | 2382 | unsigned int size_left = DXEPTSIZ_XFERSIZE_GET(epsize); |
5b7d70c6 BD |
2383 | int result = 0; |
2384 | ||
2385 | if (!hs_req) { | |
2386 | dev_dbg(hsotg->dev, "%s: no request active\n", __func__); | |
2387 | return; | |
2388 | } | |
2389 | ||
fe0b94ab MYK |
2390 | if (epnum == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_OUT) { |
2391 | dev_dbg(hsotg->dev, "zlp packet received\n"); | |
1f91b4cc FB |
2392 | dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0); |
2393 | dwc2_hsotg_enqueue_setup(hsotg); | |
fe0b94ab MYK |
2394 | return; |
2395 | } | |
2396 | ||
aa3e8bc8 VA |
2397 | if (using_desc_dma(hsotg)) |
2398 | size_left = dwc2_gadget_get_xfersize_ddma(hs_ep); | |
2399 | ||
5b7d70c6 | 2400 | if (using_dma(hsotg)) { |
9da51974 | 2401 | unsigned int size_done; |
5b7d70c6 | 2402 | |
8b9bc460 LM |
2403 | /* |
2404 | * Calculate the size of the transfer by checking how much | |
5b7d70c6 BD |
2405 | * is left in the endpoint size register and then working it |
2406 | * out from the amount we loaded for the transfer. | |
2407 | * | |
2408 | * We need to do this as DMA pointers are always 32bit aligned | |
2409 | * so may overshoot/undershoot the transfer. | |
2410 | */ | |
2411 | ||
5b7d70c6 BD |
2412 | size_done = hs_ep->size_loaded - size_left; |
2413 | size_done += hs_ep->last_load; | |
2414 | ||
2415 | req->actual = size_done; | |
2416 | } | |
2417 | ||
a33e7136 BD |
2418 | /* if there is more request to do, schedule new transfer */ |
2419 | if (req->actual < req->length && size_left == 0) { | |
1f91b4cc | 2420 | dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true); |
a33e7136 BD |
2421 | return; |
2422 | } | |
2423 | ||
5b7d70c6 BD |
2424 | if (req->actual < req->length && req->short_not_ok) { |
2425 | dev_dbg(hsotg->dev, "%s: got %d/%d (short not ok) => error\n", | |
2426 | __func__, req->actual, req->length); | |
2427 | ||
8b9bc460 LM |
2428 | /* |
2429 | * todo - what should we return here? there's no one else | |
2430 | * even bothering to check the status. | |
2431 | */ | |
5b7d70c6 BD |
2432 | } |
2433 | ||
ef750c71 VA |
2434 | /* DDMA IN status phase will start from StsPhseRcvd interrupt */ |
2435 | if (!using_desc_dma(hsotg) && epnum == 0 && | |
2436 | hsotg->ep0_state == DWC2_EP0_DATA_OUT) { | |
fe0b94ab | 2437 | /* Move to STATUS IN */ |
b4c53b4a MH |
2438 | if (!hsotg->delayed_status) |
2439 | dwc2_hsotg_ep0_zlp(hsotg, true); | |
5b7d70c6 BD |
2440 | } |
2441 | ||
ec1f9d9f RB |
2442 | /* |
2443 | * Slave mode OUT transfers do not go through XferComplete so | |
2444 | * adjust the ISOC parity here. | |
2445 | */ | |
2446 | if (!using_dma(hsotg)) { | |
ec1f9d9f RB |
2447 | if (hs_ep->isochronous && hs_ep->interval == 1) |
2448 | dwc2_hsotg_change_ep_iso_parity(hsotg, DOEPCTL(epnum)); | |
837e9f00 VM |
2449 | else if (hs_ep->isochronous && hs_ep->interval > 1) |
2450 | dwc2_gadget_incr_frame_num(hs_ep); | |
ec1f9d9f RB |
2451 | } |
2452 | ||
4faf3b36 MH |
2453 | /* Set actual frame number for completed transfers */ |
2454 | if (!using_desc_dma(hsotg) && hs_ep->isochronous) | |
2455 | req->frame_number = hsotg->frame_number; | |
2456 | ||
1f91b4cc | 2457 | dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, result); |
5b7d70c6 BD |
2458 | } |
2459 | ||
5b7d70c6 | 2460 | /** |
1f91b4cc | 2461 | * dwc2_hsotg_handle_rx - RX FIFO has data |
5b7d70c6 BD |
2462 | * @hsotg: The device instance |
2463 | * | |
2464 | * The IRQ handler has detected that the RX FIFO has some data in it | |
2465 | * that requires processing, so find out what is in there and do the | |
2466 | * appropriate read. | |
2467 | * | |
25985edc | 2468 | * The RXFIFO is a true FIFO, the packets coming out are still in packet |
5b7d70c6 BD |
2469 | * chunks, so if you have x packets received on an endpoint you'll get x |
2470 | * FIFO events delivered, each with a packet's worth of data in it. | |
2471 | * | |
2472 | * When using DMA, we should not be processing events from the RXFIFO | |
2473 | * as the actual data should be sent to the memory directly and we turn | |
2474 | * on the completion interrupts to get notifications of transfer completion. | |
2475 | */ | |
1f91b4cc | 2476 | static void dwc2_hsotg_handle_rx(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 2477 | { |
f25c42b8 | 2478 | u32 grxstsr = dwc2_readl(hsotg, GRXSTSP); |
5b7d70c6 BD |
2479 | u32 epnum, status, size; |
2480 | ||
2481 | WARN_ON(using_dma(hsotg)); | |
2482 | ||
47a1685f DN |
2483 | epnum = grxstsr & GRXSTS_EPNUM_MASK; |
2484 | status = grxstsr & GRXSTS_PKTSTS_MASK; | |
5b7d70c6 | 2485 | |
47a1685f DN |
2486 | size = grxstsr & GRXSTS_BYTECNT_MASK; |
2487 | size >>= GRXSTS_BYTECNT_SHIFT; | |
5b7d70c6 | 2488 | |
d7c747c5 | 2489 | dev_dbg(hsotg->dev, "%s: GRXSTSP=0x%08x (%d@%d)\n", |
9da51974 | 2490 | __func__, grxstsr, size, epnum); |
5b7d70c6 | 2491 | |
47a1685f DN |
2492 | switch ((status & GRXSTS_PKTSTS_MASK) >> GRXSTS_PKTSTS_SHIFT) { |
2493 | case GRXSTS_PKTSTS_GLOBALOUTNAK: | |
2494 | dev_dbg(hsotg->dev, "GLOBALOUTNAK\n"); | |
5b7d70c6 BD |
2495 | break; |
2496 | ||
47a1685f | 2497 | case GRXSTS_PKTSTS_OUTDONE: |
5b7d70c6 | 2498 | dev_dbg(hsotg->dev, "OutDone (Frame=0x%08x)\n", |
1f91b4cc | 2499 | dwc2_hsotg_read_frameno(hsotg)); |
5b7d70c6 BD |
2500 | |
2501 | if (!using_dma(hsotg)) | |
1f91b4cc | 2502 | dwc2_hsotg_handle_outdone(hsotg, epnum); |
5b7d70c6 BD |
2503 | break; |
2504 | ||
47a1685f | 2505 | case GRXSTS_PKTSTS_SETUPDONE: |
5b7d70c6 BD |
2506 | dev_dbg(hsotg->dev, |
2507 | "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n", | |
1f91b4cc | 2508 | dwc2_hsotg_read_frameno(hsotg), |
f25c42b8 | 2509 | dwc2_readl(hsotg, DOEPCTL(0))); |
fe0b94ab | 2510 | /* |
1f91b4cc | 2511 | * Call dwc2_hsotg_handle_outdone here if it was not called from |
fe0b94ab MYK |
2512 | * GRXSTS_PKTSTS_OUTDONE. That is, if the core didn't |
2513 | * generate GRXSTS_PKTSTS_OUTDONE for setup packet. | |
2514 | */ | |
2515 | if (hsotg->ep0_state == DWC2_EP0_SETUP) | |
1f91b4cc | 2516 | dwc2_hsotg_handle_outdone(hsotg, epnum); |
5b7d70c6 BD |
2517 | break; |
2518 | ||
47a1685f | 2519 | case GRXSTS_PKTSTS_OUTRX: |
1f91b4cc | 2520 | dwc2_hsotg_rx_data(hsotg, epnum, size); |
5b7d70c6 BD |
2521 | break; |
2522 | ||
47a1685f | 2523 | case GRXSTS_PKTSTS_SETUPRX: |
5b7d70c6 BD |
2524 | dev_dbg(hsotg->dev, |
2525 | "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n", | |
1f91b4cc | 2526 | dwc2_hsotg_read_frameno(hsotg), |
f25c42b8 | 2527 | dwc2_readl(hsotg, DOEPCTL(0))); |
5b7d70c6 | 2528 | |
fe0b94ab MYK |
2529 | WARN_ON(hsotg->ep0_state != DWC2_EP0_SETUP); |
2530 | ||
1f91b4cc | 2531 | dwc2_hsotg_rx_data(hsotg, epnum, size); |
5b7d70c6 BD |
2532 | break; |
2533 | ||
2534 | default: | |
2535 | dev_warn(hsotg->dev, "%s: unknown status %08x\n", | |
2536 | __func__, grxstsr); | |
2537 | ||
1f91b4cc | 2538 | dwc2_hsotg_dump(hsotg); |
5b7d70c6 BD |
2539 | break; |
2540 | } | |
2541 | } | |
2542 | ||
2543 | /** | |
1f91b4cc | 2544 | * dwc2_hsotg_ep0_mps - turn max packet size into register setting |
5b7d70c6 | 2545 | * @mps: The maximum packet size in bytes. |
8b9bc460 | 2546 | */ |
1f91b4cc | 2547 | static u32 dwc2_hsotg_ep0_mps(unsigned int mps) |
5b7d70c6 BD |
2548 | { |
2549 | switch (mps) { | |
2550 | case 64: | |
94cb8fd6 | 2551 | return D0EPCTL_MPS_64; |
5b7d70c6 | 2552 | case 32: |
94cb8fd6 | 2553 | return D0EPCTL_MPS_32; |
5b7d70c6 | 2554 | case 16: |
94cb8fd6 | 2555 | return D0EPCTL_MPS_16; |
5b7d70c6 | 2556 | case 8: |
94cb8fd6 | 2557 | return D0EPCTL_MPS_8; |
5b7d70c6 BD |
2558 | } |
2559 | ||
2560 | /* bad max packet size, warn and return invalid result */ | |
2561 | WARN_ON(1); | |
2562 | return (u32)-1; | |
2563 | } | |
2564 | ||
2565 | /** | |
1f91b4cc | 2566 | * dwc2_hsotg_set_ep_maxpacket - set endpoint's max-packet field |
5b7d70c6 BD |
2567 | * @hsotg: The driver state. |
2568 | * @ep: The index number of the endpoint | |
2569 | * @mps: The maximum packet size in bytes | |
ee2c40de | 2570 | * @mc: The multicount value |
6fb914d7 | 2571 | * @dir_in: True if direction is in. |
5b7d70c6 BD |
2572 | * |
2573 | * Configure the maximum packet size for the given endpoint, updating | |
2574 | * the hardware control registers to reflect this. | |
2575 | */ | |
1f91b4cc | 2576 | static void dwc2_hsotg_set_ep_maxpacket(struct dwc2_hsotg *hsotg, |
ee2c40de VM |
2577 | unsigned int ep, unsigned int mps, |
2578 | unsigned int mc, unsigned int dir_in) | |
5b7d70c6 | 2579 | { |
1f91b4cc | 2580 | struct dwc2_hsotg_ep *hs_ep; |
5b7d70c6 BD |
2581 | u32 reg; |
2582 | ||
c6f5c050 MYK |
2583 | hs_ep = index_to_ep(hsotg, ep, dir_in); |
2584 | if (!hs_ep) | |
2585 | return; | |
2586 | ||
5b7d70c6 | 2587 | if (ep == 0) { |
ee2c40de VM |
2588 | u32 mps_bytes = mps; |
2589 | ||
5b7d70c6 | 2590 | /* EP0 is a special case */ |
ee2c40de VM |
2591 | mps = dwc2_hsotg_ep0_mps(mps_bytes); |
2592 | if (mps > 3) | |
5b7d70c6 | 2593 | goto bad_mps; |
ee2c40de | 2594 | hs_ep->ep.maxpacket = mps_bytes; |
4fca54aa | 2595 | hs_ep->mc = 1; |
5b7d70c6 | 2596 | } else { |
ee2c40de | 2597 | if (mps > 1024) |
5b7d70c6 | 2598 | goto bad_mps; |
ee2c40de VM |
2599 | hs_ep->mc = mc; |
2600 | if (mc > 3) | |
4fca54aa | 2601 | goto bad_mps; |
ee2c40de | 2602 | hs_ep->ep.maxpacket = mps; |
5b7d70c6 BD |
2603 | } |
2604 | ||
c6f5c050 | 2605 | if (dir_in) { |
f25c42b8 | 2606 | reg = dwc2_readl(hsotg, DIEPCTL(ep)); |
c6f5c050 | 2607 | reg &= ~DXEPCTL_MPS_MASK; |
ee2c40de | 2608 | reg |= mps; |
f25c42b8 | 2609 | dwc2_writel(hsotg, reg, DIEPCTL(ep)); |
c6f5c050 | 2610 | } else { |
f25c42b8 | 2611 | reg = dwc2_readl(hsotg, DOEPCTL(ep)); |
47a1685f | 2612 | reg &= ~DXEPCTL_MPS_MASK; |
ee2c40de | 2613 | reg |= mps; |
f25c42b8 | 2614 | dwc2_writel(hsotg, reg, DOEPCTL(ep)); |
659ad60c | 2615 | } |
5b7d70c6 BD |
2616 | |
2617 | return; | |
2618 | ||
2619 | bad_mps: | |
2620 | dev_err(hsotg->dev, "ep%d: bad mps of %d\n", ep, mps); | |
2621 | } | |
2622 | ||
9c39ddc6 | 2623 | /** |
1f91b4cc | 2624 | * dwc2_hsotg_txfifo_flush - flush Tx FIFO |
9c39ddc6 AT |
2625 | * @hsotg: The driver state |
2626 | * @idx: The index for the endpoint (0..15) | |
2627 | */ | |
1f91b4cc | 2628 | static void dwc2_hsotg_txfifo_flush(struct dwc2_hsotg *hsotg, unsigned int idx) |
9c39ddc6 | 2629 | { |
f25c42b8 GS |
2630 | dwc2_writel(hsotg, GRSTCTL_TXFNUM(idx) | GRSTCTL_TXFFLSH, |
2631 | GRSTCTL); | |
9c39ddc6 AT |
2632 | |
2633 | /* wait until the fifo is flushed */ | |
79d6b8c5 SA |
2634 | if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL, GRSTCTL_TXFFLSH, 100)) |
2635 | dev_warn(hsotg->dev, "%s: timeout flushing fifo GRSTCTL_TXFFLSH\n", | |
2636 | __func__); | |
9c39ddc6 | 2637 | } |
5b7d70c6 BD |
2638 | |
2639 | /** | |
1f91b4cc | 2640 | * dwc2_hsotg_trytx - check to see if anything needs transmitting |
5b7d70c6 BD |
2641 | * @hsotg: The driver state |
2642 | * @hs_ep: The driver endpoint to check. | |
2643 | * | |
2644 | * Check to see if there is a request that has data to send, and if so | |
2645 | * make an attempt to write data into the FIFO. | |
2646 | */ | |
1f91b4cc | 2647 | static int dwc2_hsotg_trytx(struct dwc2_hsotg *hsotg, |
9da51974 | 2648 | struct dwc2_hsotg_ep *hs_ep) |
5b7d70c6 | 2649 | { |
1f91b4cc | 2650 | struct dwc2_hsotg_req *hs_req = hs_ep->req; |
5b7d70c6 | 2651 | |
afcf4169 RB |
2652 | if (!hs_ep->dir_in || !hs_req) { |
2653 | /** | |
2654 | * if request is not enqueued, we disable interrupts | |
2655 | * for endpoints, excepting ep0 | |
2656 | */ | |
2657 | if (hs_ep->index != 0) | |
1f91b4cc | 2658 | dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, |
9da51974 | 2659 | hs_ep->dir_in, 0); |
5b7d70c6 | 2660 | return 0; |
afcf4169 | 2661 | } |
5b7d70c6 BD |
2662 | |
2663 | if (hs_req->req.actual < hs_req->req.length) { | |
2664 | dev_dbg(hsotg->dev, "trying to write more for ep%d\n", | |
2665 | hs_ep->index); | |
1f91b4cc | 2666 | return dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req); |
5b7d70c6 BD |
2667 | } |
2668 | ||
2669 | return 0; | |
2670 | } | |
2671 | ||
2672 | /** | |
1f91b4cc | 2673 | * dwc2_hsotg_complete_in - complete IN transfer |
5b7d70c6 BD |
2674 | * @hsotg: The device state. |
2675 | * @hs_ep: The endpoint that has just completed. | |
2676 | * | |
2677 | * An IN transfer has been completed, update the transfer's state and then | |
2678 | * call the relevant completion routines. | |
2679 | */ | |
1f91b4cc | 2680 | static void dwc2_hsotg_complete_in(struct dwc2_hsotg *hsotg, |
9da51974 | 2681 | struct dwc2_hsotg_ep *hs_ep) |
5b7d70c6 | 2682 | { |
1f91b4cc | 2683 | struct dwc2_hsotg_req *hs_req = hs_ep->req; |
f25c42b8 | 2684 | u32 epsize = dwc2_readl(hsotg, DIEPTSIZ(hs_ep->index)); |
5b7d70c6 BD |
2685 | int size_left, size_done; |
2686 | ||
2687 | if (!hs_req) { | |
2688 | dev_dbg(hsotg->dev, "XferCompl but no req\n"); | |
2689 | return; | |
2690 | } | |
2691 | ||
d3ca0259 | 2692 | /* Finish ZLP handling for IN EP0 transactions */ |
fe0b94ab MYK |
2693 | if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_IN) { |
2694 | dev_dbg(hsotg->dev, "zlp packet sent\n"); | |
c3b22fe2 RK |
2695 | |
2696 | /* | |
2697 | * While send zlp for DWC2_EP0_STATUS_IN EP direction was | |
2698 | * changed to IN. Change back to complete OUT transfer request | |
2699 | */ | |
2700 | hs_ep->dir_in = 0; | |
2701 | ||
1f91b4cc | 2702 | dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0); |
9e14d0a5 GH |
2703 | if (hsotg->test_mode) { |
2704 | int ret; | |
2705 | ||
1f91b4cc | 2706 | ret = dwc2_hsotg_set_test_mode(hsotg, hsotg->test_mode); |
9e14d0a5 GH |
2707 | if (ret < 0) { |
2708 | dev_dbg(hsotg->dev, "Invalid Test #%d\n", | |
9da51974 | 2709 | hsotg->test_mode); |
1f91b4cc | 2710 | dwc2_hsotg_stall_ep0(hsotg); |
9e14d0a5 GH |
2711 | return; |
2712 | } | |
2713 | } | |
1f91b4cc | 2714 | dwc2_hsotg_enqueue_setup(hsotg); |
d3ca0259 LM |
2715 | return; |
2716 | } | |
2717 | ||
8b9bc460 LM |
2718 | /* |
2719 | * Calculate the size of the transfer by checking how much is left | |
5b7d70c6 BD |
2720 | * in the endpoint size register and then working it out from |
2721 | * the amount we loaded for the transfer. | |
2722 | * | |
2723 | * We do this even for DMA, as the transfer may have incremented | |
2724 | * past the end of the buffer (DMA transfers are always 32bit | |
2725 | * aligned). | |
2726 | */ | |
aa3e8bc8 VA |
2727 | if (using_desc_dma(hsotg)) { |
2728 | size_left = dwc2_gadget_get_xfersize_ddma(hs_ep); | |
2729 | if (size_left < 0) | |
2730 | dev_err(hsotg->dev, "error parsing DDMA results %d\n", | |
2731 | size_left); | |
2732 | } else { | |
2733 | size_left = DXEPTSIZ_XFERSIZE_GET(epsize); | |
2734 | } | |
5b7d70c6 BD |
2735 | |
2736 | size_done = hs_ep->size_loaded - size_left; | |
2737 | size_done += hs_ep->last_load; | |
2738 | ||
2739 | if (hs_req->req.actual != size_done) | |
2740 | dev_dbg(hsotg->dev, "%s: adjusting size done %d => %d\n", | |
2741 | __func__, hs_req->req.actual, size_done); | |
2742 | ||
2743 | hs_req->req.actual = size_done; | |
d3ca0259 LM |
2744 | dev_dbg(hsotg->dev, "req->length:%d req->actual:%d req->zero:%d\n", |
2745 | hs_req->req.length, hs_req->req.actual, hs_req->req.zero); | |
2746 | ||
5b7d70c6 BD |
2747 | if (!size_left && hs_req->req.actual < hs_req->req.length) { |
2748 | dev_dbg(hsotg->dev, "%s trying more for req...\n", __func__); | |
1f91b4cc | 2749 | dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true); |
fe0b94ab MYK |
2750 | return; |
2751 | } | |
2752 | ||
d53dc388 | 2753 | /* Zlp for all endpoints in non DDMA, for ep0 only in DATA IN stage */ |
8a20fa45 | 2754 | if (hs_ep->send_zlp) { |
8a20fa45 | 2755 | hs_ep->send_zlp = 0; |
d53dc388 MH |
2756 | if (!using_desc_dma(hsotg)) { |
2757 | dwc2_hsotg_program_zlp(hsotg, hs_ep); | |
2758 | /* transfer will be completed on next complete interrupt */ | |
2759 | return; | |
2760 | } | |
f71b5e25 MYK |
2761 | } |
2762 | ||
fe0b94ab MYK |
2763 | if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_DATA_IN) { |
2764 | /* Move to STATUS OUT */ | |
1f91b4cc | 2765 | dwc2_hsotg_ep0_zlp(hsotg, false); |
fe0b94ab MYK |
2766 | return; |
2767 | } | |
2768 | ||
1f91b4cc | 2769 | dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0); |
5b7d70c6 BD |
2770 | } |
2771 | ||
32601588 VM |
2772 | /** |
2773 | * dwc2_gadget_read_ep_interrupts - reads interrupts for given ep | |
2774 | * @hsotg: The device state. | |
2775 | * @idx: Index of ep. | |
2776 | * @dir_in: Endpoint direction 1-in 0-out. | |
2777 | * | |
2778 | * Reads for endpoint with given index and direction, by masking | |
2779 | * epint_reg with coresponding mask. | |
2780 | */ | |
2781 | static u32 dwc2_gadget_read_ep_interrupts(struct dwc2_hsotg *hsotg, | |
2782 | unsigned int idx, int dir_in) | |
2783 | { | |
2784 | u32 epmsk_reg = dir_in ? DIEPMSK : DOEPMSK; | |
2785 | u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx); | |
2786 | u32 ints; | |
2787 | u32 mask; | |
2788 | u32 diepempmsk; | |
2789 | ||
f25c42b8 GS |
2790 | mask = dwc2_readl(hsotg, epmsk_reg); |
2791 | diepempmsk = dwc2_readl(hsotg, DIEPEMPMSK); | |
32601588 VM |
2792 | mask |= ((diepempmsk >> idx) & 0x1) ? DIEPMSK_TXFIFOEMPTY : 0; |
2793 | mask |= DXEPINT_SETUP_RCVD; | |
2794 | ||
f25c42b8 | 2795 | ints = dwc2_readl(hsotg, epint_reg); |
32601588 VM |
2796 | ints &= mask; |
2797 | return ints; | |
2798 | } | |
2799 | ||
bd9971f0 VM |
2800 | /** |
2801 | * dwc2_gadget_handle_ep_disabled - handle DXEPINT_EPDISBLD | |
2802 | * @hs_ep: The endpoint on which interrupt is asserted. | |
2803 | * | |
2804 | * This interrupt indicates that the endpoint has been disabled per the | |
2805 | * application's request. | |
2806 | * | |
2807 | * For IN endpoints flushes txfifo, in case of BULK clears DCTL_CGNPINNAK, | |
2808 | * in case of ISOC completes current request. | |
2809 | * | |
2810 | * For ISOC-OUT endpoints completes expired requests. If there is remaining | |
2811 | * request starts it. | |
2812 | */ | |
2813 | static void dwc2_gadget_handle_ep_disabled(struct dwc2_hsotg_ep *hs_ep) | |
2814 | { | |
2815 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
2816 | struct dwc2_hsotg_req *hs_req; | |
2817 | unsigned char idx = hs_ep->index; | |
2818 | int dir_in = hs_ep->dir_in; | |
2819 | u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx); | |
f25c42b8 | 2820 | int dctl = dwc2_readl(hsotg, DCTL); |
bd9971f0 VM |
2821 | |
2822 | dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__); | |
2823 | ||
2824 | if (dir_in) { | |
f25c42b8 | 2825 | int epctl = dwc2_readl(hsotg, epctl_reg); |
bd9971f0 VM |
2826 | |
2827 | dwc2_hsotg_txfifo_flush(hsotg, hs_ep->fifo_index); | |
2828 | ||
2829 | if (hs_ep->isochronous) { | |
2830 | dwc2_hsotg_complete_in(hsotg, hs_ep); | |
2831 | return; | |
2832 | } | |
2833 | ||
2834 | if ((epctl & DXEPCTL_STALL) && (epctl & DXEPCTL_EPTYPE_BULK)) { | |
f25c42b8 | 2835 | int dctl = dwc2_readl(hsotg, DCTL); |
bd9971f0 VM |
2836 | |
2837 | dctl |= DCTL_CGNPINNAK; | |
f25c42b8 | 2838 | dwc2_writel(hsotg, dctl, DCTL); |
bd9971f0 VM |
2839 | } |
2840 | return; | |
2841 | } | |
2842 | ||
2843 | if (dctl & DCTL_GOUTNAKSTS) { | |
2844 | dctl |= DCTL_CGOUTNAK; | |
f25c42b8 | 2845 | dwc2_writel(hsotg, dctl, DCTL); |
bd9971f0 VM |
2846 | } |
2847 | ||
2848 | if (!hs_ep->isochronous) | |
2849 | return; | |
2850 | ||
2851 | if (list_empty(&hs_ep->queue)) { | |
2852 | dev_dbg(hsotg->dev, "%s: complete_ep 0x%p, ep->queue empty!\n", | |
2853 | __func__, hs_ep); | |
2854 | return; | |
2855 | } | |
2856 | ||
2857 | do { | |
2858 | hs_req = get_ep_head(hs_ep); | |
2859 | if (hs_req) | |
2860 | dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, | |
2861 | -ENODATA); | |
2862 | dwc2_gadget_incr_frame_num(hs_ep); | |
c7c24e7a AP |
2863 | /* Update current frame number value. */ |
2864 | hsotg->frame_number = dwc2_hsotg_read_frameno(hsotg); | |
bd9971f0 VM |
2865 | } while (dwc2_gadget_target_frame_elapsed(hs_ep)); |
2866 | ||
2867 | dwc2_gadget_start_next_request(hs_ep); | |
2868 | } | |
2869 | ||
5321922c VM |
2870 | /** |
2871 | * dwc2_gadget_handle_out_token_ep_disabled - handle DXEPINT_OUTTKNEPDIS | |
6fb914d7 | 2872 | * @ep: The endpoint on which interrupt is asserted. |
5321922c VM |
2873 | * |
2874 | * This is starting point for ISOC-OUT transfer, synchronization done with | |
2875 | * first out token received from host while corresponding EP is disabled. | |
2876 | * | |
2877 | * Device does not know initial frame in which out token will come. For this | |
2878 | * HW generates OUTTKNEPDIS - out token is received while EP is disabled. Upon | |
2879 | * getting this interrupt SW starts calculation for next transfer frame. | |
2880 | */ | |
2881 | static void dwc2_gadget_handle_out_token_ep_disabled(struct dwc2_hsotg_ep *ep) | |
2882 | { | |
2883 | struct dwc2_hsotg *hsotg = ep->parent; | |
2884 | int dir_in = ep->dir_in; | |
2885 | u32 doepmsk; | |
2886 | ||
2887 | if (dir_in || !ep->isochronous) | |
2888 | return; | |
2889 | ||
540ccba0 VA |
2890 | if (using_desc_dma(hsotg)) { |
2891 | if (ep->target_frame == TARGET_FRAME_INITIAL) { | |
2892 | /* Start first ISO Out */ | |
4d4f1e79 | 2893 | ep->target_frame = hsotg->frame_number; |
540ccba0 VA |
2894 | dwc2_gadget_start_isoc_ddma(ep); |
2895 | } | |
2896 | return; | |
2897 | } | |
2898 | ||
5321922c VM |
2899 | if (ep->interval > 1 && |
2900 | ep->target_frame == TARGET_FRAME_INITIAL) { | |
5321922c VM |
2901 | u32 ctrl; |
2902 | ||
4d4f1e79 | 2903 | ep->target_frame = hsotg->frame_number; |
5321922c VM |
2904 | dwc2_gadget_incr_frame_num(ep); |
2905 | ||
f25c42b8 | 2906 | ctrl = dwc2_readl(hsotg, DOEPCTL(ep->index)); |
5321922c VM |
2907 | if (ep->target_frame & 0x1) |
2908 | ctrl |= DXEPCTL_SETODDFR; | |
2909 | else | |
2910 | ctrl |= DXEPCTL_SETEVENFR; | |
2911 | ||
f25c42b8 | 2912 | dwc2_writel(hsotg, ctrl, DOEPCTL(ep->index)); |
5321922c VM |
2913 | } |
2914 | ||
2915 | dwc2_gadget_start_next_request(ep); | |
f25c42b8 | 2916 | doepmsk = dwc2_readl(hsotg, DOEPMSK); |
5321922c | 2917 | doepmsk &= ~DOEPMSK_OUTTKNEPDISMSK; |
f25c42b8 | 2918 | dwc2_writel(hsotg, doepmsk, DOEPMSK); |
5321922c VM |
2919 | } |
2920 | ||
2921 | /** | |
38beaec6 JY |
2922 | * dwc2_gadget_handle_nak - handle NAK interrupt |
2923 | * @hs_ep: The endpoint on which interrupt is asserted. | |
2924 | * | |
2925 | * This is starting point for ISOC-IN transfer, synchronization done with | |
2926 | * first IN token received from host while corresponding EP is disabled. | |
2927 | * | |
2928 | * Device does not know when first one token will arrive from host. On first | |
2929 | * token arrival HW generates 2 interrupts: 'in token received while FIFO empty' | |
2930 | * and 'NAK'. NAK interrupt for ISOC-IN means that token has arrived and ZLP was | |
2931 | * sent in response to that as there was no data in FIFO. SW is basing on this | |
2932 | * interrupt to obtain frame in which token has come and then based on the | |
2933 | * interval calculates next frame for transfer. | |
2934 | */ | |
5321922c VM |
2935 | static void dwc2_gadget_handle_nak(struct dwc2_hsotg_ep *hs_ep) |
2936 | { | |
2937 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
2938 | int dir_in = hs_ep->dir_in; | |
2939 | ||
2940 | if (!dir_in || !hs_ep->isochronous) | |
2941 | return; | |
2942 | ||
2943 | if (hs_ep->target_frame == TARGET_FRAME_INITIAL) { | |
540ccba0 VA |
2944 | |
2945 | if (using_desc_dma(hsotg)) { | |
4d4f1e79 | 2946 | hs_ep->target_frame = hsotg->frame_number; |
729cac69 | 2947 | dwc2_gadget_incr_frame_num(hs_ep); |
48dac4e4 GT |
2948 | |
2949 | /* In service interval mode target_frame must | |
2950 | * be set to last (u)frame of the service interval. | |
2951 | */ | |
2952 | if (hsotg->params.service_interval) { | |
2953 | /* Set target_frame to the first (u)frame of | |
2954 | * the service interval | |
2955 | */ | |
2956 | hs_ep->target_frame &= ~hs_ep->interval + 1; | |
2957 | ||
2958 | /* Set target_frame to the last (u)frame of | |
2959 | * the service interval | |
2960 | */ | |
2961 | dwc2_gadget_incr_frame_num(hs_ep); | |
2962 | dwc2_gadget_dec_frame_num_by_one(hs_ep); | |
2963 | } | |
2964 | ||
540ccba0 VA |
2965 | dwc2_gadget_start_isoc_ddma(hs_ep); |
2966 | return; | |
2967 | } | |
2968 | ||
4d4f1e79 | 2969 | hs_ep->target_frame = hsotg->frame_number; |
5321922c | 2970 | if (hs_ep->interval > 1) { |
f25c42b8 | 2971 | u32 ctrl = dwc2_readl(hsotg, |
5321922c VM |
2972 | DIEPCTL(hs_ep->index)); |
2973 | if (hs_ep->target_frame & 0x1) | |
2974 | ctrl |= DXEPCTL_SETODDFR; | |
2975 | else | |
2976 | ctrl |= DXEPCTL_SETEVENFR; | |
2977 | ||
f25c42b8 | 2978 | dwc2_writel(hsotg, ctrl, DIEPCTL(hs_ep->index)); |
5321922c VM |
2979 | } |
2980 | ||
2981 | dwc2_hsotg_complete_request(hsotg, hs_ep, | |
2982 | get_ep_head(hs_ep), 0); | |
2983 | } | |
2984 | ||
729cac69 MH |
2985 | if (!using_desc_dma(hsotg)) |
2986 | dwc2_gadget_incr_frame_num(hs_ep); | |
5321922c VM |
2987 | } |
2988 | ||
5b7d70c6 | 2989 | /** |
1f91b4cc | 2990 | * dwc2_hsotg_epint - handle an in/out endpoint interrupt |
5b7d70c6 BD |
2991 | * @hsotg: The driver state |
2992 | * @idx: The index for the endpoint (0..15) | |
2993 | * @dir_in: Set if this is an IN endpoint | |
2994 | * | |
2995 | * Process and clear any interrupt pending for an individual endpoint | |
8b9bc460 | 2996 | */ |
1f91b4cc | 2997 | static void dwc2_hsotg_epint(struct dwc2_hsotg *hsotg, unsigned int idx, |
9da51974 | 2998 | int dir_in) |
5b7d70c6 | 2999 | { |
1f91b4cc | 3000 | struct dwc2_hsotg_ep *hs_ep = index_to_ep(hsotg, idx, dir_in); |
94cb8fd6 LM |
3001 | u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx); |
3002 | u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx); | |
3003 | u32 epsiz_reg = dir_in ? DIEPTSIZ(idx) : DOEPTSIZ(idx); | |
5b7d70c6 | 3004 | u32 ints; |
5b7d70c6 | 3005 | |
32601588 | 3006 | ints = dwc2_gadget_read_ep_interrupts(hsotg, idx, dir_in); |
5b7d70c6 | 3007 | |
a3395f0d | 3008 | /* Clear endpoint interrupts */ |
f25c42b8 | 3009 | dwc2_writel(hsotg, ints, epint_reg); |
a3395f0d | 3010 | |
c6f5c050 MYK |
3011 | if (!hs_ep) { |
3012 | dev_err(hsotg->dev, "%s:Interrupt for unconfigured ep%d(%s)\n", | |
9da51974 | 3013 | __func__, idx, dir_in ? "in" : "out"); |
c6f5c050 MYK |
3014 | return; |
3015 | } | |
3016 | ||
5b7d70c6 BD |
3017 | dev_dbg(hsotg->dev, "%s: ep%d(%s) DxEPINT=0x%08x\n", |
3018 | __func__, idx, dir_in ? "in" : "out", ints); | |
3019 | ||
b787d755 MYK |
3020 | /* Don't process XferCompl interrupt if it is a setup packet */ |
3021 | if (idx == 0 && (ints & (DXEPINT_SETUP | DXEPINT_SETUP_RCVD))) | |
3022 | ints &= ~DXEPINT_XFERCOMPL; | |
3023 | ||
f0afdb42 VA |
3024 | /* |
3025 | * Don't process XferCompl interrupt in DDMA if EP0 is still in SETUP | |
3026 | * stage and xfercomplete was generated without SETUP phase done | |
3027 | * interrupt. SW should parse received setup packet only after host's | |
3028 | * exit from setup phase of control transfer. | |
3029 | */ | |
3030 | if (using_desc_dma(hsotg) && idx == 0 && !hs_ep->dir_in && | |
3031 | hsotg->ep0_state == DWC2_EP0_SETUP && !(ints & DXEPINT_SETUP)) | |
3032 | ints &= ~DXEPINT_XFERCOMPL; | |
3033 | ||
837e9f00 | 3034 | if (ints & DXEPINT_XFERCOMPL) { |
5b7d70c6 | 3035 | dev_dbg(hsotg->dev, |
47a1685f | 3036 | "%s: XferCompl: DxEPCTL=0x%08x, DXEPTSIZ=%08x\n", |
f25c42b8 GS |
3037 | __func__, dwc2_readl(hsotg, epctl_reg), |
3038 | dwc2_readl(hsotg, epsiz_reg)); | |
5b7d70c6 | 3039 | |
540ccba0 VA |
3040 | /* In DDMA handle isochronous requests separately */ |
3041 | if (using_desc_dma(hsotg) && hs_ep->isochronous) { | |
729cac69 MH |
3042 | /* XferCompl set along with BNA */ |
3043 | if (!(ints & DXEPINT_BNAINTR)) | |
3044 | dwc2_gadget_complete_isoc_request_ddma(hs_ep); | |
540ccba0 VA |
3045 | } else if (dir_in) { |
3046 | /* | |
3047 | * We get OutDone from the FIFO, so we only | |
3048 | * need to look at completing IN requests here | |
3049 | * if operating slave mode | |
3050 | */ | |
837e9f00 VM |
3051 | if (hs_ep->isochronous && hs_ep->interval > 1) |
3052 | dwc2_gadget_incr_frame_num(hs_ep); | |
3053 | ||
1f91b4cc | 3054 | dwc2_hsotg_complete_in(hsotg, hs_ep); |
837e9f00 VM |
3055 | if (ints & DXEPINT_NAKINTRPT) |
3056 | ints &= ~DXEPINT_NAKINTRPT; | |
5b7d70c6 | 3057 | |
c9a64ea8 | 3058 | if (idx == 0 && !hs_ep->req) |
1f91b4cc | 3059 | dwc2_hsotg_enqueue_setup(hsotg); |
5b7d70c6 | 3060 | } else if (using_dma(hsotg)) { |
8b9bc460 LM |
3061 | /* |
3062 | * We're using DMA, we need to fire an OutDone here | |
3063 | * as we ignore the RXFIFO. | |
3064 | */ | |
837e9f00 VM |
3065 | if (hs_ep->isochronous && hs_ep->interval > 1) |
3066 | dwc2_gadget_incr_frame_num(hs_ep); | |
5b7d70c6 | 3067 | |
1f91b4cc | 3068 | dwc2_hsotg_handle_outdone(hsotg, idx); |
5b7d70c6 | 3069 | } |
5b7d70c6 BD |
3070 | } |
3071 | ||
bd9971f0 VM |
3072 | if (ints & DXEPINT_EPDISBLD) |
3073 | dwc2_gadget_handle_ep_disabled(hs_ep); | |
9c39ddc6 | 3074 | |
5321922c VM |
3075 | if (ints & DXEPINT_OUTTKNEPDIS) |
3076 | dwc2_gadget_handle_out_token_ep_disabled(hs_ep); | |
3077 | ||
3078 | if (ints & DXEPINT_NAKINTRPT) | |
3079 | dwc2_gadget_handle_nak(hs_ep); | |
3080 | ||
47a1685f | 3081 | if (ints & DXEPINT_AHBERR) |
5b7d70c6 | 3082 | dev_dbg(hsotg->dev, "%s: AHBErr\n", __func__); |
5b7d70c6 | 3083 | |
47a1685f | 3084 | if (ints & DXEPINT_SETUP) { /* Setup or Timeout */ |
5b7d70c6 BD |
3085 | dev_dbg(hsotg->dev, "%s: Setup/Timeout\n", __func__); |
3086 | ||
3087 | if (using_dma(hsotg) && idx == 0) { | |
8b9bc460 LM |
3088 | /* |
3089 | * this is the notification we've received a | |
5b7d70c6 BD |
3090 | * setup packet. In non-DMA mode we'd get this |
3091 | * from the RXFIFO, instead we need to process | |
8b9bc460 LM |
3092 | * the setup here. |
3093 | */ | |
5b7d70c6 BD |
3094 | |
3095 | if (dir_in) | |
3096 | WARN_ON_ONCE(1); | |
3097 | else | |
1f91b4cc | 3098 | dwc2_hsotg_handle_outdone(hsotg, 0); |
5b7d70c6 | 3099 | } |
5b7d70c6 BD |
3100 | } |
3101 | ||
ef750c71 | 3102 | if (ints & DXEPINT_STSPHSERCVD) { |
9d9a6b07 VA |
3103 | dev_dbg(hsotg->dev, "%s: StsPhseRcvd\n", __func__); |
3104 | ||
9e95a66c MH |
3105 | /* Safety check EP0 state when STSPHSERCVD asserted */ |
3106 | if (hsotg->ep0_state == DWC2_EP0_DATA_OUT) { | |
3107 | /* Move to STATUS IN for DDMA */ | |
b4c53b4a MH |
3108 | if (using_desc_dma(hsotg)) { |
3109 | if (!hsotg->delayed_status) | |
3110 | dwc2_hsotg_ep0_zlp(hsotg, true); | |
3111 | else | |
3112 | /* In case of 3 stage Control Write with delayed | |
3113 | * status, when Status IN transfer started | |
3114 | * before STSPHSERCVD asserted, NAKSTS bit not | |
3115 | * cleared by CNAK in dwc2_hsotg_start_req() | |
3116 | * function. Clear now NAKSTS to allow complete | |
3117 | * transfer. | |
3118 | */ | |
3119 | dwc2_set_bit(hsotg, DIEPCTL(0), | |
3120 | DXEPCTL_CNAK); | |
3121 | } | |
9e95a66c MH |
3122 | } |
3123 | ||
ef750c71 VA |
3124 | } |
3125 | ||
47a1685f | 3126 | if (ints & DXEPINT_BACK2BACKSETUP) |
5b7d70c6 | 3127 | dev_dbg(hsotg->dev, "%s: B2BSetup/INEPNakEff\n", __func__); |
5b7d70c6 | 3128 | |
540ccba0 VA |
3129 | if (ints & DXEPINT_BNAINTR) { |
3130 | dev_dbg(hsotg->dev, "%s: BNA interrupt\n", __func__); | |
540ccba0 | 3131 | if (hs_ep->isochronous) |
729cac69 | 3132 | dwc2_gadget_handle_isoc_bna(hs_ep); |
540ccba0 VA |
3133 | } |
3134 | ||
1479e841 | 3135 | if (dir_in && !hs_ep->isochronous) { |
8b9bc460 | 3136 | /* not sure if this is important, but we'll clear it anyway */ |
26ddef5d | 3137 | if (ints & DXEPINT_INTKNTXFEMP) { |
5b7d70c6 BD |
3138 | dev_dbg(hsotg->dev, "%s: ep%d: INTknTXFEmpMsk\n", |
3139 | __func__, idx); | |
5b7d70c6 BD |
3140 | } |
3141 | ||
3142 | /* this probably means something bad is happening */ | |
26ddef5d | 3143 | if (ints & DXEPINT_INTKNEPMIS) { |
5b7d70c6 BD |
3144 | dev_warn(hsotg->dev, "%s: ep%d: INTknEP\n", |
3145 | __func__, idx); | |
5b7d70c6 | 3146 | } |
10aebc77 BD |
3147 | |
3148 | /* FIFO has space or is empty (see GAHBCFG) */ | |
3149 | if (hsotg->dedicated_fifos && | |
26ddef5d | 3150 | ints & DXEPINT_TXFEMP) { |
10aebc77 BD |
3151 | dev_dbg(hsotg->dev, "%s: ep%d: TxFIFOEmpty\n", |
3152 | __func__, idx); | |
70fa030f | 3153 | if (!using_dma(hsotg)) |
1f91b4cc | 3154 | dwc2_hsotg_trytx(hsotg, hs_ep); |
10aebc77 | 3155 | } |
5b7d70c6 | 3156 | } |
5b7d70c6 BD |
3157 | } |
3158 | ||
3159 | /** | |
1f91b4cc | 3160 | * dwc2_hsotg_irq_enumdone - Handle EnumDone interrupt (enumeration done) |
5b7d70c6 BD |
3161 | * @hsotg: The device state. |
3162 | * | |
3163 | * Handle updating the device settings after the enumeration phase has | |
3164 | * been completed. | |
8b9bc460 | 3165 | */ |
1f91b4cc | 3166 | static void dwc2_hsotg_irq_enumdone(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 3167 | { |
f25c42b8 | 3168 | u32 dsts = dwc2_readl(hsotg, DSTS); |
9b2667f1 | 3169 | int ep0_mps = 0, ep_mps = 8; |
5b7d70c6 | 3170 | |
8b9bc460 LM |
3171 | /* |
3172 | * This should signal the finish of the enumeration phase | |
5b7d70c6 | 3173 | * of the USB handshaking, so we should now know what rate |
8b9bc460 LM |
3174 | * we connected at. |
3175 | */ | |
5b7d70c6 BD |
3176 | |
3177 | dev_dbg(hsotg->dev, "EnumDone (DSTS=0x%08x)\n", dsts); | |
3178 | ||
8b9bc460 LM |
3179 | /* |
3180 | * note, since we're limited by the size of transfer on EP0, and | |
5b7d70c6 | 3181 | * it seems IN transfers must be a even number of packets we do |
8b9bc460 LM |
3182 | * not advertise a 64byte MPS on EP0. |
3183 | */ | |
5b7d70c6 BD |
3184 | |
3185 | /* catch both EnumSpd_FS and EnumSpd_FS48 */ | |
6d76c92c | 3186 | switch ((dsts & DSTS_ENUMSPD_MASK) >> DSTS_ENUMSPD_SHIFT) { |
47a1685f DN |
3187 | case DSTS_ENUMSPD_FS: |
3188 | case DSTS_ENUMSPD_FS48: | |
5b7d70c6 | 3189 | hsotg->gadget.speed = USB_SPEED_FULL; |
5b7d70c6 | 3190 | ep0_mps = EP0_MPS_LIMIT; |
295538ff | 3191 | ep_mps = 1023; |
5b7d70c6 BD |
3192 | break; |
3193 | ||
47a1685f | 3194 | case DSTS_ENUMSPD_HS: |
5b7d70c6 | 3195 | hsotg->gadget.speed = USB_SPEED_HIGH; |
5b7d70c6 | 3196 | ep0_mps = EP0_MPS_LIMIT; |
295538ff | 3197 | ep_mps = 1024; |
5b7d70c6 BD |
3198 | break; |
3199 | ||
47a1685f | 3200 | case DSTS_ENUMSPD_LS: |
5b7d70c6 | 3201 | hsotg->gadget.speed = USB_SPEED_LOW; |
552d940f VM |
3202 | ep0_mps = 8; |
3203 | ep_mps = 8; | |
8b9bc460 LM |
3204 | /* |
3205 | * note, we don't actually support LS in this driver at the | |
5b7d70c6 BD |
3206 | * moment, and the documentation seems to imply that it isn't |
3207 | * supported by the PHYs on some of the devices. | |
3208 | */ | |
3209 | break; | |
3210 | } | |
e538dfda MN |
3211 | dev_info(hsotg->dev, "new device is %s\n", |
3212 | usb_speed_string(hsotg->gadget.speed)); | |
5b7d70c6 | 3213 | |
8b9bc460 LM |
3214 | /* |
3215 | * we should now know the maximum packet size for an | |
3216 | * endpoint, so set the endpoints to a default value. | |
3217 | */ | |
5b7d70c6 BD |
3218 | |
3219 | if (ep0_mps) { | |
3220 | int i; | |
c6f5c050 | 3221 | /* Initialize ep0 for both in and out directions */ |
ee2c40de VM |
3222 | dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 0, 1); |
3223 | dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 0, 0); | |
c6f5c050 MYK |
3224 | for (i = 1; i < hsotg->num_of_eps; i++) { |
3225 | if (hsotg->eps_in[i]) | |
ee2c40de VM |
3226 | dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps, |
3227 | 0, 1); | |
c6f5c050 | 3228 | if (hsotg->eps_out[i]) |
ee2c40de VM |
3229 | dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps, |
3230 | 0, 0); | |
c6f5c050 | 3231 | } |
5b7d70c6 BD |
3232 | } |
3233 | ||
3234 | /* ensure after enumeration our EP0 is active */ | |
3235 | ||
1f91b4cc | 3236 | dwc2_hsotg_enqueue_setup(hsotg); |
5b7d70c6 BD |
3237 | |
3238 | dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n", | |
f25c42b8 GS |
3239 | dwc2_readl(hsotg, DIEPCTL0), |
3240 | dwc2_readl(hsotg, DOEPCTL0)); | |
5b7d70c6 BD |
3241 | } |
3242 | ||
3243 | /** | |
3244 | * kill_all_requests - remove all requests from the endpoint's queue | |
3245 | * @hsotg: The device state. | |
3246 | * @ep: The endpoint the requests may be on. | |
3247 | * @result: The result code to use. | |
5b7d70c6 BD |
3248 | * |
3249 | * Go through the requests on the given endpoint and mark them | |
3250 | * completed with the given result code. | |
3251 | */ | |
941fcce4 | 3252 | static void kill_all_requests(struct dwc2_hsotg *hsotg, |
1f91b4cc | 3253 | struct dwc2_hsotg_ep *ep, |
6b448af4 | 3254 | int result) |
5b7d70c6 | 3255 | { |
9da51974 | 3256 | unsigned int size; |
5b7d70c6 | 3257 | |
6b448af4 | 3258 | ep->req = NULL; |
5b7d70c6 | 3259 | |
37bea42f JK |
3260 | while (!list_empty(&ep->queue)) { |
3261 | struct dwc2_hsotg_req *req = get_ep_head(ep); | |
3262 | ||
3263 | dwc2_hsotg_complete_request(hsotg, ep, req, result); | |
3264 | } | |
6b448af4 | 3265 | |
b203d0a2 RB |
3266 | if (!hsotg->dedicated_fifos) |
3267 | return; | |
f25c42b8 | 3268 | size = (dwc2_readl(hsotg, DTXFSTS(ep->fifo_index)) & 0xffff) * 4; |
b203d0a2 | 3269 | if (size < ep->fifo_size) |
1f91b4cc | 3270 | dwc2_hsotg_txfifo_flush(hsotg, ep->fifo_index); |
5b7d70c6 BD |
3271 | } |
3272 | ||
5b7d70c6 | 3273 | /** |
1f91b4cc | 3274 | * dwc2_hsotg_disconnect - disconnect service |
5b7d70c6 BD |
3275 | * @hsotg: The device state. |
3276 | * | |
5e891342 LM |
3277 | * The device has been disconnected. Remove all current |
3278 | * transactions and signal the gadget driver that this | |
3279 | * has happened. | |
8b9bc460 | 3280 | */ |
1f91b4cc | 3281 | void dwc2_hsotg_disconnect(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 3282 | { |
9da51974 | 3283 | unsigned int ep; |
5b7d70c6 | 3284 | |
4ace06e8 MS |
3285 | if (!hsotg->connected) |
3286 | return; | |
3287 | ||
3288 | hsotg->connected = 0; | |
9e14d0a5 | 3289 | hsotg->test_mode = 0; |
c6f5c050 | 3290 | |
dccf1bad | 3291 | /* all endpoints should be shutdown */ |
c6f5c050 MYK |
3292 | for (ep = 0; ep < hsotg->num_of_eps; ep++) { |
3293 | if (hsotg->eps_in[ep]) | |
4fe4f9fe MH |
3294 | kill_all_requests(hsotg, hsotg->eps_in[ep], |
3295 | -ESHUTDOWN); | |
c6f5c050 | 3296 | if (hsotg->eps_out[ep]) |
4fe4f9fe MH |
3297 | kill_all_requests(hsotg, hsotg->eps_out[ep], |
3298 | -ESHUTDOWN); | |
c6f5c050 | 3299 | } |
5b7d70c6 BD |
3300 | |
3301 | call_gadget(hsotg, disconnect); | |
065d3931 | 3302 | hsotg->lx_state = DWC2_L3; |
ce2b21a4 JS |
3303 | |
3304 | usb_gadget_set_state(&hsotg->gadget, USB_STATE_NOTATTACHED); | |
5b7d70c6 BD |
3305 | } |
3306 | ||
3307 | /** | |
1f91b4cc | 3308 | * dwc2_hsotg_irq_fifoempty - TX FIFO empty interrupt handler |
5b7d70c6 BD |
3309 | * @hsotg: The device state: |
3310 | * @periodic: True if this is a periodic FIFO interrupt | |
3311 | */ | |
1f91b4cc | 3312 | static void dwc2_hsotg_irq_fifoempty(struct dwc2_hsotg *hsotg, bool periodic) |
5b7d70c6 | 3313 | { |
1f91b4cc | 3314 | struct dwc2_hsotg_ep *ep; |
5b7d70c6 BD |
3315 | int epno, ret; |
3316 | ||
3317 | /* look through for any more data to transmit */ | |
b3f489b2 | 3318 | for (epno = 0; epno < hsotg->num_of_eps; epno++) { |
c6f5c050 MYK |
3319 | ep = index_to_ep(hsotg, epno, 1); |
3320 | ||
3321 | if (!ep) | |
3322 | continue; | |
5b7d70c6 BD |
3323 | |
3324 | if (!ep->dir_in) | |
3325 | continue; | |
3326 | ||
3327 | if ((periodic && !ep->periodic) || | |
3328 | (!periodic && ep->periodic)) | |
3329 | continue; | |
3330 | ||
1f91b4cc | 3331 | ret = dwc2_hsotg_trytx(hsotg, ep); |
5b7d70c6 BD |
3332 | if (ret < 0) |
3333 | break; | |
3334 | } | |
3335 | } | |
3336 | ||
5b7d70c6 | 3337 | /* IRQ flags which will trigger a retry around the IRQ loop */ |
47a1685f DN |
3338 | #define IRQ_RETRY_MASK (GINTSTS_NPTXFEMP | \ |
3339 | GINTSTS_PTXFEMP | \ | |
3340 | GINTSTS_RXFLVL) | |
5b7d70c6 | 3341 | |
4fe4f9fe | 3342 | static int dwc2_hsotg_ep_disable(struct usb_ep *ep); |
8b9bc460 | 3343 | /** |
58aff959 | 3344 | * dwc2_hsotg_core_init_disconnected - issue softreset to the core |
8b9bc460 | 3345 | * @hsotg: The device state |
6fb914d7 | 3346 | * @is_usb_reset: Usb resetting flag |
8b9bc460 LM |
3347 | * |
3348 | * Issue a soft reset to the core, and await the core finishing it. | |
3349 | */ | |
1f91b4cc | 3350 | void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg, |
9da51974 | 3351 | bool is_usb_reset) |
308d734e | 3352 | { |
1ee6903b | 3353 | u32 intmsk; |
643cc4de | 3354 | u32 val; |
ecd9a7ad | 3355 | u32 usbcfg; |
79c3b5bb | 3356 | u32 dcfg = 0; |
dccf1bad | 3357 | int ep; |
643cc4de | 3358 | |
5390d438 MYK |
3359 | /* Kill any ep0 requests as controller will be reinitialized */ |
3360 | kill_all_requests(hsotg, hsotg->eps_out[0], -ECONNRESET); | |
3361 | ||
dccf1bad | 3362 | if (!is_usb_reset) { |
6e6360b6 | 3363 | if (dwc2_core_reset(hsotg, true)) |
86de4895 | 3364 | return; |
dccf1bad MH |
3365 | } else { |
3366 | /* all endpoints should be shutdown */ | |
3367 | for (ep = 1; ep < hsotg->num_of_eps; ep++) { | |
3368 | if (hsotg->eps_in[ep]) | |
3369 | dwc2_hsotg_ep_disable(&hsotg->eps_in[ep]->ep); | |
3370 | if (hsotg->eps_out[ep]) | |
3371 | dwc2_hsotg_ep_disable(&hsotg->eps_out[ep]->ep); | |
3372 | } | |
3373 | } | |
308d734e LM |
3374 | |
3375 | /* | |
3376 | * we must now enable ep0 ready for host detection and then | |
3377 | * set configuration. | |
3378 | */ | |
3379 | ||
ecd9a7ad | 3380 | /* keep other bits untouched (so e.g. forced modes are not lost) */ |
f25c42b8 | 3381 | usbcfg = dwc2_readl(hsotg, GUSBCFG); |
1e868545 | 3382 | usbcfg &= ~GUSBCFG_TOUTCAL_MASK; |
707d80f0 | 3383 | usbcfg |= GUSBCFG_TOUTCAL(7); |
ecd9a7ad | 3384 | |
1e868545 JM |
3385 | /* remove the HNP/SRP and set the PHY */ |
3386 | usbcfg &= ~(GUSBCFG_SRPCAP | GUSBCFG_HNPCAP); | |
3387 | dwc2_writel(hsotg, usbcfg, GUSBCFG); | |
707d80f0 | 3388 | |
1e868545 | 3389 | dwc2_phy_init(hsotg, true); |
308d734e | 3390 | |
1f91b4cc | 3391 | dwc2_hsotg_init_fifo(hsotg); |
308d734e | 3392 | |
643cc4de | 3393 | if (!is_usb_reset) |
f25c42b8 | 3394 | dwc2_set_bit(hsotg, DCTL, DCTL_SFTDISCON); |
308d734e | 3395 | |
79c3b5bb | 3396 | dcfg |= DCFG_EPMISCNT(1); |
38e9002b VM |
3397 | |
3398 | switch (hsotg->params.speed) { | |
3399 | case DWC2_SPEED_PARAM_LOW: | |
3400 | dcfg |= DCFG_DEVSPD_LS; | |
3401 | break; | |
3402 | case DWC2_SPEED_PARAM_FULL: | |
79c3b5bb VA |
3403 | if (hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS) |
3404 | dcfg |= DCFG_DEVSPD_FS48; | |
3405 | else | |
3406 | dcfg |= DCFG_DEVSPD_FS; | |
38e9002b VM |
3407 | break; |
3408 | default: | |
79c3b5bb VA |
3409 | dcfg |= DCFG_DEVSPD_HS; |
3410 | } | |
38e9002b | 3411 | |
b43ebc96 GT |
3412 | if (hsotg->params.ipg_isoc_en) |
3413 | dcfg |= DCFG_IPG_ISOC_SUPPORDED; | |
3414 | ||
f25c42b8 | 3415 | dwc2_writel(hsotg, dcfg, DCFG); |
308d734e LM |
3416 | |
3417 | /* Clear any pending OTG interrupts */ | |
f25c42b8 | 3418 | dwc2_writel(hsotg, 0xffffffff, GOTGINT); |
308d734e LM |
3419 | |
3420 | /* Clear any pending interrupts */ | |
f25c42b8 | 3421 | dwc2_writel(hsotg, 0xffffffff, GINTSTS); |
1ee6903b | 3422 | intmsk = GINTSTS_ERLYSUSP | GINTSTS_SESSREQINT | |
47a1685f | 3423 | GINTSTS_GOUTNAKEFF | GINTSTS_GINNAKEFF | |
1ee6903b GH |
3424 | GINTSTS_USBRST | GINTSTS_RESETDET | |
3425 | GINTSTS_ENUMDONE | GINTSTS_OTGINT | | |
376f0401 SA |
3426 | GINTSTS_USBSUSP | GINTSTS_WKUPINT | |
3427 | GINTSTS_LPMTRANRCVD; | |
f4736701 VA |
3428 | |
3429 | if (!using_desc_dma(hsotg)) | |
3430 | intmsk |= GINTSTS_INCOMPL_SOIN | GINTSTS_INCOMPL_SOOUT; | |
1ee6903b | 3431 | |
95832c00 | 3432 | if (!hsotg->params.external_id_pin_ctl) |
1ee6903b GH |
3433 | intmsk |= GINTSTS_CONIDSTSCHNG; |
3434 | ||
f25c42b8 | 3435 | dwc2_writel(hsotg, intmsk, GINTMSK); |
308d734e | 3436 | |
a5c18f11 | 3437 | if (using_dma(hsotg)) { |
f25c42b8 | 3438 | dwc2_writel(hsotg, GAHBCFG_GLBL_INTR_EN | GAHBCFG_DMA_EN | |
d1ac8c80 | 3439 | hsotg->params.ahbcfg, |
f25c42b8 | 3440 | GAHBCFG); |
a5c18f11 VA |
3441 | |
3442 | /* Set DDMA mode support in the core if needed */ | |
3443 | if (using_desc_dma(hsotg)) | |
f25c42b8 | 3444 | dwc2_set_bit(hsotg, DCFG, DCFG_DESCDMA_EN); |
a5c18f11 VA |
3445 | |
3446 | } else { | |
f25c42b8 | 3447 | dwc2_writel(hsotg, ((hsotg->dedicated_fifos) ? |
95c8bc36 AS |
3448 | (GAHBCFG_NP_TXF_EMP_LVL | |
3449 | GAHBCFG_P_TXF_EMP_LVL) : 0) | | |
f25c42b8 | 3450 | GAHBCFG_GLBL_INTR_EN, GAHBCFG); |
a5c18f11 | 3451 | } |
308d734e LM |
3452 | |
3453 | /* | |
8acc8296 RB |
3454 | * If INTknTXFEmpMsk is enabled, it's important to disable ep interrupts |
3455 | * when we have no data to transfer. Otherwise we get being flooded by | |
3456 | * interrupts. | |
308d734e LM |
3457 | */ |
3458 | ||
f25c42b8 | 3459 | dwc2_writel(hsotg, ((hsotg->dedicated_fifos && !using_dma(hsotg)) ? |
6ff2e832 | 3460 | DIEPMSK_TXFIFOEMPTY | DIEPMSK_INTKNTXFEMPMSK : 0) | |
47a1685f | 3461 | DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK | |
837e9f00 | 3462 | DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK, |
f25c42b8 | 3463 | DIEPMSK); |
308d734e LM |
3464 | |
3465 | /* | |
3466 | * don't need XferCompl, we get that from RXFIFO in slave mode. In | |
9d9a6b07 | 3467 | * DMA mode we may need this and StsPhseRcvd. |
308d734e | 3468 | */ |
f25c42b8 | 3469 | dwc2_writel(hsotg, (using_dma(hsotg) ? (DIEPMSK_XFERCOMPLMSK | |
9d9a6b07 | 3470 | DOEPMSK_STSPHSERCVDMSK) : 0) | |
47a1685f | 3471 | DOEPMSK_EPDISBLDMSK | DOEPMSK_AHBERRMSK | |
9d9a6b07 | 3472 | DOEPMSK_SETUPMSK, |
f25c42b8 | 3473 | DOEPMSK); |
308d734e | 3474 | |
ec01f0b2 | 3475 | /* Enable BNA interrupt for DDMA */ |
37981e00 | 3476 | if (using_desc_dma(hsotg)) { |
f25c42b8 GS |
3477 | dwc2_set_bit(hsotg, DOEPMSK, DOEPMSK_BNAMSK); |
3478 | dwc2_set_bit(hsotg, DIEPMSK, DIEPMSK_BNAININTRMSK); | |
37981e00 | 3479 | } |
ec01f0b2 | 3480 | |
ca531bc2 GT |
3481 | /* Enable Service Interval mode if supported */ |
3482 | if (using_desc_dma(hsotg) && hsotg->params.service_interval) | |
3483 | dwc2_set_bit(hsotg, DCTL, DCTL_SERVICE_INTERVAL_SUPPORTED); | |
3484 | ||
f25c42b8 | 3485 | dwc2_writel(hsotg, 0, DAINTMSK); |
308d734e LM |
3486 | |
3487 | dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n", | |
f25c42b8 GS |
3488 | dwc2_readl(hsotg, DIEPCTL0), |
3489 | dwc2_readl(hsotg, DOEPCTL0)); | |
308d734e LM |
3490 | |
3491 | /* enable in and out endpoint interrupts */ | |
1f91b4cc | 3492 | dwc2_hsotg_en_gsint(hsotg, GINTSTS_OEPINT | GINTSTS_IEPINT); |
308d734e LM |
3493 | |
3494 | /* | |
3495 | * Enable the RXFIFO when in slave mode, as this is how we collect | |
3496 | * the data. In DMA mode, we get events from the FIFO but also | |
3497 | * things we cannot process, so do not use it. | |
3498 | */ | |
3499 | if (!using_dma(hsotg)) | |
1f91b4cc | 3500 | dwc2_hsotg_en_gsint(hsotg, GINTSTS_RXFLVL); |
308d734e LM |
3501 | |
3502 | /* Enable interrupts for EP0 in and out */ | |
1f91b4cc FB |
3503 | dwc2_hsotg_ctrl_epint(hsotg, 0, 0, 1); |
3504 | dwc2_hsotg_ctrl_epint(hsotg, 0, 1, 1); | |
308d734e | 3505 | |
643cc4de | 3506 | if (!is_usb_reset) { |
f25c42b8 | 3507 | dwc2_set_bit(hsotg, DCTL, DCTL_PWRONPRGDONE); |
643cc4de | 3508 | udelay(10); /* see openiboot */ |
f25c42b8 | 3509 | dwc2_clear_bit(hsotg, DCTL, DCTL_PWRONPRGDONE); |
643cc4de | 3510 | } |
308d734e | 3511 | |
f25c42b8 | 3512 | dev_dbg(hsotg->dev, "DCTL=0x%08x\n", dwc2_readl(hsotg, DCTL)); |
308d734e LM |
3513 | |
3514 | /* | |
94cb8fd6 | 3515 | * DxEPCTL_USBActEp says RO in manual, but seems to be set by |
308d734e LM |
3516 | * writing to the EPCTL register.. |
3517 | */ | |
3518 | ||
3519 | /* set to read 1 8byte packet */ | |
f25c42b8 GS |
3520 | dwc2_writel(hsotg, DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) | |
3521 | DXEPTSIZ_XFERSIZE(8), DOEPTSIZ0); | |
308d734e | 3522 | |
f25c42b8 | 3523 | dwc2_writel(hsotg, dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) | |
47a1685f DN |
3524 | DXEPCTL_CNAK | DXEPCTL_EPENA | |
3525 | DXEPCTL_USBACTEP, | |
f25c42b8 | 3526 | DOEPCTL0); |
308d734e LM |
3527 | |
3528 | /* enable, but don't activate EP0in */ | |
f25c42b8 GS |
3529 | dwc2_writel(hsotg, dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) | |
3530 | DXEPCTL_USBACTEP, DIEPCTL0); | |
308d734e | 3531 | |
308d734e | 3532 | /* clear global NAKs */ |
643cc4de GH |
3533 | val = DCTL_CGOUTNAK | DCTL_CGNPINNAK; |
3534 | if (!is_usb_reset) | |
3535 | val |= DCTL_SFTDISCON; | |
f25c42b8 | 3536 | dwc2_set_bit(hsotg, DCTL, val); |
308d734e | 3537 | |
21b03405 SA |
3538 | /* configure the core to support LPM */ |
3539 | dwc2_gadget_init_lpm(hsotg); | |
3540 | ||
15d9dbf8 GT |
3541 | /* program GREFCLK register if needed */ |
3542 | if (using_desc_dma(hsotg) && hsotg->params.service_interval) | |
3543 | dwc2_gadget_program_ref_clk(hsotg); | |
3544 | ||
308d734e LM |
3545 | /* must be at-least 3ms to allow bus to see disconnect */ |
3546 | mdelay(3); | |
3547 | ||
065d3931 | 3548 | hsotg->lx_state = DWC2_L0; |
755d7395 VM |
3549 | |
3550 | dwc2_hsotg_enqueue_setup(hsotg); | |
3551 | ||
3552 | dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n", | |
f25c42b8 GS |
3553 | dwc2_readl(hsotg, DIEPCTL0), |
3554 | dwc2_readl(hsotg, DOEPCTL0)); | |
ad38dc5d MS |
3555 | } |
3556 | ||
17f93402 | 3557 | void dwc2_hsotg_core_disconnect(struct dwc2_hsotg *hsotg) |
ad38dc5d MS |
3558 | { |
3559 | /* set the soft-disconnect bit */ | |
f25c42b8 | 3560 | dwc2_set_bit(hsotg, DCTL, DCTL_SFTDISCON); |
ad38dc5d | 3561 | } |
ac3c81f3 | 3562 | |
1f91b4cc | 3563 | void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg) |
ad38dc5d | 3564 | { |
308d734e | 3565 | /* remove the soft-disconnect and let's go */ |
f25c42b8 | 3566 | dwc2_clear_bit(hsotg, DCTL, DCTL_SFTDISCON); |
308d734e LM |
3567 | } |
3568 | ||
381fc8f8 VM |
3569 | /** |
3570 | * dwc2_gadget_handle_incomplete_isoc_in - handle incomplete ISO IN Interrupt. | |
3571 | * @hsotg: The device state: | |
3572 | * | |
3573 | * This interrupt indicates one of the following conditions occurred while | |
3574 | * transmitting an ISOC transaction. | |
3575 | * - Corrupted IN Token for ISOC EP. | |
3576 | * - Packet not complete in FIFO. | |
3577 | * | |
3578 | * The following actions will be taken: | |
3579 | * - Determine the EP | |
3580 | * - Disable EP; when 'Endpoint Disabled' interrupt is received Flush FIFO | |
3581 | */ | |
3582 | static void dwc2_gadget_handle_incomplete_isoc_in(struct dwc2_hsotg *hsotg) | |
3583 | { | |
3584 | struct dwc2_hsotg_ep *hs_ep; | |
3585 | u32 epctrl; | |
1b4977c7 | 3586 | u32 daintmsk; |
381fc8f8 VM |
3587 | u32 idx; |
3588 | ||
3589 | dev_dbg(hsotg->dev, "Incomplete isoc in interrupt received:\n"); | |
3590 | ||
f25c42b8 | 3591 | daintmsk = dwc2_readl(hsotg, DAINTMSK); |
1b4977c7 | 3592 | |
d5d5f079 | 3593 | for (idx = 1; idx < hsotg->num_of_eps; idx++) { |
381fc8f8 | 3594 | hs_ep = hsotg->eps_in[idx]; |
1b4977c7 | 3595 | /* Proceed only unmasked ISOC EPs */ |
89066b36 | 3596 | if ((BIT(idx) & ~daintmsk) || !hs_ep->isochronous) |
1b4977c7 RK |
3597 | continue; |
3598 | ||
f25c42b8 | 3599 | epctrl = dwc2_readl(hsotg, DIEPCTL(idx)); |
1b4977c7 | 3600 | if ((epctrl & DXEPCTL_EPENA) && |
381fc8f8 VM |
3601 | dwc2_gadget_target_frame_elapsed(hs_ep)) { |
3602 | epctrl |= DXEPCTL_SNAK; | |
3603 | epctrl |= DXEPCTL_EPDIS; | |
f25c42b8 | 3604 | dwc2_writel(hsotg, epctrl, DIEPCTL(idx)); |
381fc8f8 VM |
3605 | } |
3606 | } | |
3607 | ||
3608 | /* Clear interrupt */ | |
f25c42b8 | 3609 | dwc2_writel(hsotg, GINTSTS_INCOMPL_SOIN, GINTSTS); |
381fc8f8 VM |
3610 | } |
3611 | ||
3612 | /** | |
3613 | * dwc2_gadget_handle_incomplete_isoc_out - handle incomplete ISO OUT Interrupt | |
3614 | * @hsotg: The device state: | |
3615 | * | |
3616 | * This interrupt indicates one of the following conditions occurred while | |
3617 | * transmitting an ISOC transaction. | |
3618 | * - Corrupted OUT Token for ISOC EP. | |
3619 | * - Packet not complete in FIFO. | |
3620 | * | |
3621 | * The following actions will be taken: | |
3622 | * - Determine the EP | |
3623 | * - Set DCTL_SGOUTNAK and unmask GOUTNAKEFF if target frame elapsed. | |
3624 | */ | |
3625 | static void dwc2_gadget_handle_incomplete_isoc_out(struct dwc2_hsotg *hsotg) | |
3626 | { | |
3627 | u32 gintsts; | |
3628 | u32 gintmsk; | |
689efb26 | 3629 | u32 daintmsk; |
381fc8f8 VM |
3630 | u32 epctrl; |
3631 | struct dwc2_hsotg_ep *hs_ep; | |
3632 | int idx; | |
3633 | ||
3634 | dev_dbg(hsotg->dev, "%s: GINTSTS_INCOMPL_SOOUT\n", __func__); | |
3635 | ||
f25c42b8 | 3636 | daintmsk = dwc2_readl(hsotg, DAINTMSK); |
689efb26 RK |
3637 | daintmsk >>= DAINT_OUTEP_SHIFT; |
3638 | ||
d5d5f079 | 3639 | for (idx = 1; idx < hsotg->num_of_eps; idx++) { |
381fc8f8 | 3640 | hs_ep = hsotg->eps_out[idx]; |
689efb26 | 3641 | /* Proceed only unmasked ISOC EPs */ |
89066b36 | 3642 | if ((BIT(idx) & ~daintmsk) || !hs_ep->isochronous) |
689efb26 RK |
3643 | continue; |
3644 | ||
f25c42b8 | 3645 | epctrl = dwc2_readl(hsotg, DOEPCTL(idx)); |
689efb26 | 3646 | if ((epctrl & DXEPCTL_EPENA) && |
381fc8f8 VM |
3647 | dwc2_gadget_target_frame_elapsed(hs_ep)) { |
3648 | /* Unmask GOUTNAKEFF interrupt */ | |
f25c42b8 | 3649 | gintmsk = dwc2_readl(hsotg, GINTMSK); |
381fc8f8 | 3650 | gintmsk |= GINTSTS_GOUTNAKEFF; |
f25c42b8 | 3651 | dwc2_writel(hsotg, gintmsk, GINTMSK); |
381fc8f8 | 3652 | |
f25c42b8 | 3653 | gintsts = dwc2_readl(hsotg, GINTSTS); |
689efb26 | 3654 | if (!(gintsts & GINTSTS_GOUTNAKEFF)) { |
f25c42b8 | 3655 | dwc2_set_bit(hsotg, DCTL, DCTL_SGOUTNAK); |
689efb26 RK |
3656 | break; |
3657 | } | |
381fc8f8 VM |
3658 | } |
3659 | } | |
3660 | ||
3661 | /* Clear interrupt */ | |
f25c42b8 | 3662 | dwc2_writel(hsotg, GINTSTS_INCOMPL_SOOUT, GINTSTS); |
381fc8f8 VM |
3663 | } |
3664 | ||
5b7d70c6 | 3665 | /** |
1f91b4cc | 3666 | * dwc2_hsotg_irq - handle device interrupt |
5b7d70c6 BD |
3667 | * @irq: The IRQ number triggered |
3668 | * @pw: The pw value when registered the handler. | |
3669 | */ | |
1f91b4cc | 3670 | static irqreturn_t dwc2_hsotg_irq(int irq, void *pw) |
5b7d70c6 | 3671 | { |
941fcce4 | 3672 | struct dwc2_hsotg *hsotg = pw; |
5b7d70c6 BD |
3673 | int retry_count = 8; |
3674 | u32 gintsts; | |
3675 | u32 gintmsk; | |
3676 | ||
ee3de8d7 VM |
3677 | if (!dwc2_is_device_mode(hsotg)) |
3678 | return IRQ_NONE; | |
3679 | ||
5ad1d316 | 3680 | spin_lock(&hsotg->lock); |
5b7d70c6 | 3681 | irq_retry: |
f25c42b8 GS |
3682 | gintsts = dwc2_readl(hsotg, GINTSTS); |
3683 | gintmsk = dwc2_readl(hsotg, GINTMSK); | |
5b7d70c6 BD |
3684 | |
3685 | dev_dbg(hsotg->dev, "%s: %08x %08x (%08x) retry %d\n", | |
3686 | __func__, gintsts, gintsts & gintmsk, gintmsk, retry_count); | |
3687 | ||
3688 | gintsts &= gintmsk; | |
3689 | ||
8fc37b82 MYK |
3690 | if (gintsts & GINTSTS_RESETDET) { |
3691 | dev_dbg(hsotg->dev, "%s: USBRstDet\n", __func__); | |
3692 | ||
f25c42b8 | 3693 | dwc2_writel(hsotg, GINTSTS_RESETDET, GINTSTS); |
8fc37b82 MYK |
3694 | |
3695 | /* This event must be used only if controller is suspended */ | |
c9c394ab AP |
3696 | if (hsotg->in_ppd && hsotg->lx_state == DWC2_L2) |
3697 | dwc2_exit_partial_power_down(hsotg, 0, true); | |
3698 | ||
3699 | hsotg->lx_state = DWC2_L0; | |
8fc37b82 MYK |
3700 | } |
3701 | ||
3702 | if (gintsts & (GINTSTS_USBRST | GINTSTS_RESETDET)) { | |
f25c42b8 | 3703 | u32 usb_status = dwc2_readl(hsotg, GOTGCTL); |
8fc37b82 MYK |
3704 | u32 connected = hsotg->connected; |
3705 | ||
3706 | dev_dbg(hsotg->dev, "%s: USBRst\n", __func__); | |
3707 | dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n", | |
f25c42b8 | 3708 | dwc2_readl(hsotg, GNPTXSTS)); |
8fc37b82 | 3709 | |
f25c42b8 | 3710 | dwc2_writel(hsotg, GINTSTS_USBRST, GINTSTS); |
8fc37b82 MYK |
3711 | |
3712 | /* Report disconnection if it is not already done. */ | |
3713 | dwc2_hsotg_disconnect(hsotg); | |
3714 | ||
307bc11f | 3715 | /* Reset device address to zero */ |
f25c42b8 | 3716 | dwc2_clear_bit(hsotg, DCFG, DCFG_DEVADDR_MASK); |
307bc11f | 3717 | |
8fc37b82 MYK |
3718 | if (usb_status & GOTGCTL_BSESVLD && connected) |
3719 | dwc2_hsotg_core_init_disconnected(hsotg, true); | |
3720 | } | |
3721 | ||
47a1685f | 3722 | if (gintsts & GINTSTS_ENUMDONE) { |
f25c42b8 | 3723 | dwc2_writel(hsotg, GINTSTS_ENUMDONE, GINTSTS); |
a3395f0d | 3724 | |
1f91b4cc | 3725 | dwc2_hsotg_irq_enumdone(hsotg); |
5b7d70c6 BD |
3726 | } |
3727 | ||
47a1685f | 3728 | if (gintsts & (GINTSTS_OEPINT | GINTSTS_IEPINT)) { |
f25c42b8 GS |
3729 | u32 daint = dwc2_readl(hsotg, DAINT); |
3730 | u32 daintmsk = dwc2_readl(hsotg, DAINTMSK); | |
7e804650 | 3731 | u32 daint_out, daint_in; |
5b7d70c6 BD |
3732 | int ep; |
3733 | ||
7e804650 | 3734 | daint &= daintmsk; |
47a1685f DN |
3735 | daint_out = daint >> DAINT_OUTEP_SHIFT; |
3736 | daint_in = daint & ~(daint_out << DAINT_OUTEP_SHIFT); | |
7e804650 | 3737 | |
5b7d70c6 BD |
3738 | dev_dbg(hsotg->dev, "%s: daint=%08x\n", __func__, daint); |
3739 | ||
cec87f1d MYK |
3740 | for (ep = 0; ep < hsotg->num_of_eps && daint_out; |
3741 | ep++, daint_out >>= 1) { | |
5b7d70c6 | 3742 | if (daint_out & 1) |
1f91b4cc | 3743 | dwc2_hsotg_epint(hsotg, ep, 0); |
5b7d70c6 BD |
3744 | } |
3745 | ||
cec87f1d MYK |
3746 | for (ep = 0; ep < hsotg->num_of_eps && daint_in; |
3747 | ep++, daint_in >>= 1) { | |
5b7d70c6 | 3748 | if (daint_in & 1) |
1f91b4cc | 3749 | dwc2_hsotg_epint(hsotg, ep, 1); |
5b7d70c6 | 3750 | } |
5b7d70c6 BD |
3751 | } |
3752 | ||
5b7d70c6 BD |
3753 | /* check both FIFOs */ |
3754 | ||
47a1685f | 3755 | if (gintsts & GINTSTS_NPTXFEMP) { |
5b7d70c6 BD |
3756 | dev_dbg(hsotg->dev, "NPTxFEmp\n"); |
3757 | ||
8b9bc460 LM |
3758 | /* |
3759 | * Disable the interrupt to stop it happening again | |
5b7d70c6 | 3760 | * unless one of these endpoint routines decides that |
8b9bc460 LM |
3761 | * it needs re-enabling |
3762 | */ | |
5b7d70c6 | 3763 | |
1f91b4cc FB |
3764 | dwc2_hsotg_disable_gsint(hsotg, GINTSTS_NPTXFEMP); |
3765 | dwc2_hsotg_irq_fifoempty(hsotg, false); | |
5b7d70c6 BD |
3766 | } |
3767 | ||
47a1685f | 3768 | if (gintsts & GINTSTS_PTXFEMP) { |
5b7d70c6 BD |
3769 | dev_dbg(hsotg->dev, "PTxFEmp\n"); |
3770 | ||
94cb8fd6 | 3771 | /* See note in GINTSTS_NPTxFEmp */ |
5b7d70c6 | 3772 | |
1f91b4cc FB |
3773 | dwc2_hsotg_disable_gsint(hsotg, GINTSTS_PTXFEMP); |
3774 | dwc2_hsotg_irq_fifoempty(hsotg, true); | |
5b7d70c6 BD |
3775 | } |
3776 | ||
47a1685f | 3777 | if (gintsts & GINTSTS_RXFLVL) { |
8b9bc460 LM |
3778 | /* |
3779 | * note, since GINTSTS_RxFLvl doubles as FIFO-not-empty, | |
1f91b4cc | 3780 | * we need to retry dwc2_hsotg_handle_rx if this is still |
8b9bc460 LM |
3781 | * set. |
3782 | */ | |
5b7d70c6 | 3783 | |
1f91b4cc | 3784 | dwc2_hsotg_handle_rx(hsotg); |
5b7d70c6 BD |
3785 | } |
3786 | ||
47a1685f | 3787 | if (gintsts & GINTSTS_ERLYSUSP) { |
94cb8fd6 | 3788 | dev_dbg(hsotg->dev, "GINTSTS_ErlySusp\n"); |
f25c42b8 | 3789 | dwc2_writel(hsotg, GINTSTS_ERLYSUSP, GINTSTS); |
5b7d70c6 BD |
3790 | } |
3791 | ||
8b9bc460 LM |
3792 | /* |
3793 | * these next two seem to crop-up occasionally causing the core | |
5b7d70c6 | 3794 | * to shutdown the USB transfer, so try clearing them and logging |
8b9bc460 LM |
3795 | * the occurrence. |
3796 | */ | |
5b7d70c6 | 3797 | |
47a1685f | 3798 | if (gintsts & GINTSTS_GOUTNAKEFF) { |
837e9f00 VM |
3799 | u8 idx; |
3800 | u32 epctrl; | |
3801 | u32 gintmsk; | |
d8484552 | 3802 | u32 daintmsk; |
837e9f00 VM |
3803 | struct dwc2_hsotg_ep *hs_ep; |
3804 | ||
f25c42b8 | 3805 | daintmsk = dwc2_readl(hsotg, DAINTMSK); |
d8484552 | 3806 | daintmsk >>= DAINT_OUTEP_SHIFT; |
837e9f00 | 3807 | /* Mask this interrupt */ |
f25c42b8 | 3808 | gintmsk = dwc2_readl(hsotg, GINTMSK); |
837e9f00 | 3809 | gintmsk &= ~GINTSTS_GOUTNAKEFF; |
f25c42b8 | 3810 | dwc2_writel(hsotg, gintmsk, GINTMSK); |
837e9f00 VM |
3811 | |
3812 | dev_dbg(hsotg->dev, "GOUTNakEff triggered\n"); | |
d5d5f079 | 3813 | for (idx = 1; idx < hsotg->num_of_eps; idx++) { |
837e9f00 | 3814 | hs_ep = hsotg->eps_out[idx]; |
d8484552 | 3815 | /* Proceed only unmasked ISOC EPs */ |
6070636c | 3816 | if (BIT(idx) & ~daintmsk) |
d8484552 RK |
3817 | continue; |
3818 | ||
f25c42b8 | 3819 | epctrl = dwc2_readl(hsotg, DOEPCTL(idx)); |
837e9f00 | 3820 | |
6070636c MH |
3821 | //ISOC Ep's only |
3822 | if ((epctrl & DXEPCTL_EPENA) && hs_ep->isochronous) { | |
837e9f00 VM |
3823 | epctrl |= DXEPCTL_SNAK; |
3824 | epctrl |= DXEPCTL_EPDIS; | |
f25c42b8 | 3825 | dwc2_writel(hsotg, epctrl, DOEPCTL(idx)); |
6070636c MH |
3826 | continue; |
3827 | } | |
3828 | ||
3829 | //Non-ISOC EP's | |
3830 | if (hs_ep->halted) { | |
3831 | if (!(epctrl & DXEPCTL_EPENA)) | |
3832 | epctrl |= DXEPCTL_EPENA; | |
3833 | epctrl |= DXEPCTL_EPDIS; | |
3834 | epctrl |= DXEPCTL_STALL; | |
3835 | dwc2_writel(hsotg, epctrl, DOEPCTL(idx)); | |
837e9f00 VM |
3836 | } |
3837 | } | |
a3395f0d | 3838 | |
837e9f00 | 3839 | /* This interrupt bit is cleared in DXEPINT_EPDISBLD handler */ |
5b7d70c6 BD |
3840 | } |
3841 | ||
47a1685f | 3842 | if (gintsts & GINTSTS_GINNAKEFF) { |
5b7d70c6 BD |
3843 | dev_info(hsotg->dev, "GINNakEff triggered\n"); |
3844 | ||
f25c42b8 | 3845 | dwc2_set_bit(hsotg, DCTL, DCTL_CGNPINNAK); |
a3395f0d | 3846 | |
1f91b4cc | 3847 | dwc2_hsotg_dump(hsotg); |
5b7d70c6 BD |
3848 | } |
3849 | ||
381fc8f8 VM |
3850 | if (gintsts & GINTSTS_INCOMPL_SOIN) |
3851 | dwc2_gadget_handle_incomplete_isoc_in(hsotg); | |
ec1f9d9f | 3852 | |
381fc8f8 VM |
3853 | if (gintsts & GINTSTS_INCOMPL_SOOUT) |
3854 | dwc2_gadget_handle_incomplete_isoc_out(hsotg); | |
ec1f9d9f | 3855 | |
8b9bc460 LM |
3856 | /* |
3857 | * if we've had fifo events, we should try and go around the | |
3858 | * loop again to see if there's any point in returning yet. | |
3859 | */ | |
5b7d70c6 BD |
3860 | |
3861 | if (gintsts & IRQ_RETRY_MASK && --retry_count > 0) | |
77b6200e | 3862 | goto irq_retry; |
5b7d70c6 | 3863 | |
187c5298 GT |
3864 | /* Check WKUP_ALERT interrupt*/ |
3865 | if (hsotg->params.service_interval) | |
3866 | dwc2_gadget_wkup_alert_handler(hsotg); | |
3867 | ||
5ad1d316 LM |
3868 | spin_unlock(&hsotg->lock); |
3869 | ||
5b7d70c6 BD |
3870 | return IRQ_HANDLED; |
3871 | } | |
3872 | ||
a4f82771 VA |
3873 | static void dwc2_hsotg_ep_stop_xfr(struct dwc2_hsotg *hsotg, |
3874 | struct dwc2_hsotg_ep *hs_ep) | |
3875 | { | |
3876 | u32 epctrl_reg; | |
3877 | u32 epint_reg; | |
3878 | ||
3879 | epctrl_reg = hs_ep->dir_in ? DIEPCTL(hs_ep->index) : | |
3880 | DOEPCTL(hs_ep->index); | |
3881 | epint_reg = hs_ep->dir_in ? DIEPINT(hs_ep->index) : | |
3882 | DOEPINT(hs_ep->index); | |
3883 | ||
3884 | dev_dbg(hsotg->dev, "%s: stopping transfer on %s\n", __func__, | |
3885 | hs_ep->name); | |
3886 | ||
3887 | if (hs_ep->dir_in) { | |
3888 | if (hsotg->dedicated_fifos || hs_ep->periodic) { | |
f25c42b8 | 3889 | dwc2_set_bit(hsotg, epctrl_reg, DXEPCTL_SNAK); |
a4f82771 VA |
3890 | /* Wait for Nak effect */ |
3891 | if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg, | |
3892 | DXEPINT_INEPNAKEFF, 100)) | |
3893 | dev_warn(hsotg->dev, | |
3894 | "%s: timeout DIEPINT.NAKEFF\n", | |
3895 | __func__); | |
3896 | } else { | |
f25c42b8 | 3897 | dwc2_set_bit(hsotg, DCTL, DCTL_SGNPINNAK); |
a4f82771 VA |
3898 | /* Wait for Nak effect */ |
3899 | if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS, | |
3900 | GINTSTS_GINNAKEFF, 100)) | |
3901 | dev_warn(hsotg->dev, | |
3902 | "%s: timeout GINTSTS.GINNAKEFF\n", | |
3903 | __func__); | |
3904 | } | |
3905 | } else { | |
fecb3a17 MH |
3906 | /* Mask GINTSTS_GOUTNAKEFF interrupt */ |
3907 | dwc2_hsotg_disable_gsint(hsotg, GINTSTS_GOUTNAKEFF); | |
3908 | ||
f25c42b8 GS |
3909 | if (!(dwc2_readl(hsotg, GINTSTS) & GINTSTS_GOUTNAKEFF)) |
3910 | dwc2_set_bit(hsotg, DCTL, DCTL_SGOUTNAK); | |
a4f82771 | 3911 | |
fecb3a17 MH |
3912 | if (!using_dma(hsotg)) { |
3913 | /* Wait for GINTSTS_RXFLVL interrupt */ | |
3914 | if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS, | |
3915 | GINTSTS_RXFLVL, 100)) { | |
3916 | dev_warn(hsotg->dev, "%s: timeout GINTSTS.RXFLVL\n", | |
3917 | __func__); | |
3918 | } else { | |
3919 | /* | |
3920 | * Pop GLOBAL OUT NAK status packet from RxFIFO | |
3921 | * to assert GOUTNAKEFF interrupt | |
3922 | */ | |
3923 | dwc2_readl(hsotg, GRXSTSP); | |
3924 | } | |
3925 | } | |
3926 | ||
a4f82771 VA |
3927 | /* Wait for global nak to take effect */ |
3928 | if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS, | |
3929 | GINTSTS_GOUTNAKEFF, 100)) | |
3930 | dev_warn(hsotg->dev, "%s: timeout GINTSTS.GOUTNAKEFF\n", | |
3931 | __func__); | |
3932 | } | |
3933 | ||
3934 | /* Disable ep */ | |
f25c42b8 | 3935 | dwc2_set_bit(hsotg, epctrl_reg, DXEPCTL_EPDIS | DXEPCTL_SNAK); |
a4f82771 VA |
3936 | |
3937 | /* Wait for ep to be disabled */ | |
3938 | if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg, DXEPINT_EPDISBLD, 100)) | |
3939 | dev_warn(hsotg->dev, | |
3940 | "%s: timeout DOEPCTL.EPDisable\n", __func__); | |
3941 | ||
3942 | /* Clear EPDISBLD interrupt */ | |
f25c42b8 | 3943 | dwc2_set_bit(hsotg, epint_reg, DXEPINT_EPDISBLD); |
a4f82771 VA |
3944 | |
3945 | if (hs_ep->dir_in) { | |
3946 | unsigned short fifo_index; | |
3947 | ||
3948 | if (hsotg->dedicated_fifos || hs_ep->periodic) | |
3949 | fifo_index = hs_ep->fifo_index; | |
3950 | else | |
3951 | fifo_index = 0; | |
3952 | ||
3953 | /* Flush TX FIFO */ | |
3954 | dwc2_flush_tx_fifo(hsotg, fifo_index); | |
3955 | ||
3956 | /* Clear Global In NP NAK in Shared FIFO for non periodic ep */ | |
3957 | if (!hsotg->dedicated_fifos && !hs_ep->periodic) | |
f25c42b8 | 3958 | dwc2_set_bit(hsotg, DCTL, DCTL_CGNPINNAK); |
a4f82771 VA |
3959 | |
3960 | } else { | |
3961 | /* Remove global NAKs */ | |
f25c42b8 | 3962 | dwc2_set_bit(hsotg, DCTL, DCTL_CGOUTNAK); |
a4f82771 VA |
3963 | } |
3964 | } | |
3965 | ||
5b7d70c6 | 3966 | /** |
1f91b4cc | 3967 | * dwc2_hsotg_ep_enable - enable the given endpoint |
5b7d70c6 BD |
3968 | * @ep: The USB endpint to configure |
3969 | * @desc: The USB endpoint descriptor to configure with. | |
3970 | * | |
3971 | * This is called from the USB gadget code's usb_ep_enable(). | |
8b9bc460 | 3972 | */ |
1f91b4cc | 3973 | static int dwc2_hsotg_ep_enable(struct usb_ep *ep, |
9da51974 | 3974 | const struct usb_endpoint_descriptor *desc) |
5b7d70c6 | 3975 | { |
1f91b4cc | 3976 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 3977 | struct dwc2_hsotg *hsotg = hs_ep->parent; |
5b7d70c6 | 3978 | unsigned long flags; |
ca4c55ad | 3979 | unsigned int index = hs_ep->index; |
5b7d70c6 BD |
3980 | u32 epctrl_reg; |
3981 | u32 epctrl; | |
3982 | u32 mps; | |
ee2c40de | 3983 | u32 mc; |
837e9f00 | 3984 | u32 mask; |
ca4c55ad MYK |
3985 | unsigned int dir_in; |
3986 | unsigned int i, val, size; | |
19c190f9 | 3987 | int ret = 0; |
729cac69 | 3988 | unsigned char ep_type; |
54f37f56 | 3989 | int desc_num; |
5b7d70c6 BD |
3990 | |
3991 | dev_dbg(hsotg->dev, | |
3992 | "%s: ep %s: a 0x%02x, attr 0x%02x, mps 0x%04x, intr %d\n", | |
3993 | __func__, ep->name, desc->bEndpointAddress, desc->bmAttributes, | |
3994 | desc->wMaxPacketSize, desc->bInterval); | |
3995 | ||
3996 | /* not to be called for EP0 */ | |
8c3d6092 VA |
3997 | if (index == 0) { |
3998 | dev_err(hsotg->dev, "%s: called for EP 0\n", __func__); | |
3999 | return -EINVAL; | |
4000 | } | |
5b7d70c6 BD |
4001 | |
4002 | dir_in = (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) ? 1 : 0; | |
4003 | if (dir_in != hs_ep->dir_in) { | |
4004 | dev_err(hsotg->dev, "%s: direction mismatch!\n", __func__); | |
4005 | return -EINVAL; | |
4006 | } | |
4007 | ||
729cac69 | 4008 | ep_type = desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK; |
29cc8897 | 4009 | mps = usb_endpoint_maxp(desc); |
ee2c40de | 4010 | mc = usb_endpoint_maxp_mult(desc); |
5b7d70c6 | 4011 | |
729cac69 MH |
4012 | /* ISOC IN in DDMA supported bInterval up to 10 */ |
4013 | if (using_desc_dma(hsotg) && ep_type == USB_ENDPOINT_XFER_ISOC && | |
4014 | dir_in && desc->bInterval > 10) { | |
4015 | dev_err(hsotg->dev, | |
4016 | "%s: ISOC IN, DDMA: bInterval>10 not supported!\n", __func__); | |
4017 | return -EINVAL; | |
4018 | } | |
4019 | ||
4020 | /* High bandwidth ISOC OUT in DDMA not supported */ | |
4021 | if (using_desc_dma(hsotg) && ep_type == USB_ENDPOINT_XFER_ISOC && | |
4022 | !dir_in && mc > 1) { | |
4023 | dev_err(hsotg->dev, | |
4024 | "%s: ISOC OUT, DDMA: HB not supported!\n", __func__); | |
4025 | return -EINVAL; | |
4026 | } | |
4027 | ||
1f91b4cc | 4028 | /* note, we handle this here instead of dwc2_hsotg_set_ep_maxpacket */ |
5b7d70c6 | 4029 | |
94cb8fd6 | 4030 | epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index); |
f25c42b8 | 4031 | epctrl = dwc2_readl(hsotg, epctrl_reg); |
5b7d70c6 BD |
4032 | |
4033 | dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x from 0x%08x\n", | |
4034 | __func__, epctrl, epctrl_reg); | |
4035 | ||
54f37f56 MH |
4036 | if (using_desc_dma(hsotg) && ep_type == USB_ENDPOINT_XFER_ISOC) |
4037 | desc_num = MAX_DMA_DESC_NUM_HS_ISOC; | |
4038 | else | |
4039 | desc_num = MAX_DMA_DESC_NUM_GENERIC; | |
4040 | ||
5f54c54b | 4041 | /* Allocate DMA descriptor chain for non-ctrl endpoints */ |
9383e084 VM |
4042 | if (using_desc_dma(hsotg) && !hs_ep->desc_list) { |
4043 | hs_ep->desc_list = dmam_alloc_coherent(hsotg->dev, | |
54f37f56 | 4044 | desc_num * sizeof(struct dwc2_dma_desc), |
86e881e7 | 4045 | &hs_ep->desc_list_dma, GFP_ATOMIC); |
5f54c54b VA |
4046 | if (!hs_ep->desc_list) { |
4047 | ret = -ENOMEM; | |
4048 | goto error2; | |
4049 | } | |
4050 | } | |
4051 | ||
22258f49 | 4052 | spin_lock_irqsave(&hsotg->lock, flags); |
5b7d70c6 | 4053 | |
47a1685f DN |
4054 | epctrl &= ~(DXEPCTL_EPTYPE_MASK | DXEPCTL_MPS_MASK); |
4055 | epctrl |= DXEPCTL_MPS(mps); | |
5b7d70c6 | 4056 | |
8b9bc460 LM |
4057 | /* |
4058 | * mark the endpoint as active, otherwise the core may ignore | |
4059 | * transactions entirely for this endpoint | |
4060 | */ | |
47a1685f | 4061 | epctrl |= DXEPCTL_USBACTEP; |
5b7d70c6 | 4062 | |
5b7d70c6 | 4063 | /* update the endpoint state */ |
ee2c40de | 4064 | dwc2_hsotg_set_ep_maxpacket(hsotg, hs_ep->index, mps, mc, dir_in); |
5b7d70c6 BD |
4065 | |
4066 | /* default, set to non-periodic */ | |
1479e841 | 4067 | hs_ep->isochronous = 0; |
5b7d70c6 | 4068 | hs_ep->periodic = 0; |
a18ed7b0 | 4069 | hs_ep->halted = 0; |
b833ce15 | 4070 | hs_ep->wedged = 0; |
1479e841 | 4071 | hs_ep->interval = desc->bInterval; |
4fca54aa | 4072 | |
729cac69 | 4073 | switch (ep_type) { |
5b7d70c6 | 4074 | case USB_ENDPOINT_XFER_ISOC: |
47a1685f DN |
4075 | epctrl |= DXEPCTL_EPTYPE_ISO; |
4076 | epctrl |= DXEPCTL_SETEVENFR; | |
1479e841 | 4077 | hs_ep->isochronous = 1; |
142bd33f | 4078 | hs_ep->interval = 1 << (desc->bInterval - 1); |
837e9f00 | 4079 | hs_ep->target_frame = TARGET_FRAME_INITIAL; |
ab7d2192 | 4080 | hs_ep->next_desc = 0; |
729cac69 | 4081 | hs_ep->compl_desc = 0; |
837e9f00 | 4082 | if (dir_in) { |
1479e841 | 4083 | hs_ep->periodic = 1; |
f25c42b8 | 4084 | mask = dwc2_readl(hsotg, DIEPMSK); |
837e9f00 | 4085 | mask |= DIEPMSK_NAKMSK; |
f25c42b8 | 4086 | dwc2_writel(hsotg, mask, DIEPMSK); |
837e9f00 | 4087 | } else { |
f25c42b8 | 4088 | mask = dwc2_readl(hsotg, DOEPMSK); |
837e9f00 | 4089 | mask |= DOEPMSK_OUTTKNEPDISMSK; |
f25c42b8 | 4090 | dwc2_writel(hsotg, mask, DOEPMSK); |
837e9f00 | 4091 | } |
1479e841 | 4092 | break; |
5b7d70c6 BD |
4093 | |
4094 | case USB_ENDPOINT_XFER_BULK: | |
47a1685f | 4095 | epctrl |= DXEPCTL_EPTYPE_BULK; |
5b7d70c6 BD |
4096 | break; |
4097 | ||
4098 | case USB_ENDPOINT_XFER_INT: | |
b203d0a2 | 4099 | if (dir_in) |
5b7d70c6 | 4100 | hs_ep->periodic = 1; |
5b7d70c6 | 4101 | |
142bd33f VM |
4102 | if (hsotg->gadget.speed == USB_SPEED_HIGH) |
4103 | hs_ep->interval = 1 << (desc->bInterval - 1); | |
4104 | ||
47a1685f | 4105 | epctrl |= DXEPCTL_EPTYPE_INTERRUPT; |
5b7d70c6 BD |
4106 | break; |
4107 | ||
4108 | case USB_ENDPOINT_XFER_CONTROL: | |
47a1685f | 4109 | epctrl |= DXEPCTL_EPTYPE_CONTROL; |
5b7d70c6 BD |
4110 | break; |
4111 | } | |
4112 | ||
8b9bc460 LM |
4113 | /* |
4114 | * if the hardware has dedicated fifos, we must give each IN EP | |
10aebc77 BD |
4115 | * a unique tx-fifo even if it is non-periodic. |
4116 | */ | |
21f3bb52 | 4117 | if (dir_in && hsotg->dedicated_fifos) { |
644139f8 | 4118 | unsigned fifo_count = dwc2_hsotg_tx_fifo_count(hsotg); |
ca4c55ad MYK |
4119 | u32 fifo_index = 0; |
4120 | u32 fifo_size = UINT_MAX; | |
9da51974 JY |
4121 | |
4122 | size = hs_ep->ep.maxpacket * hs_ep->mc; | |
644139f8 | 4123 | for (i = 1; i <= fifo_count; ++i) { |
9da51974 | 4124 | if (hsotg->fifo_map & (1 << i)) |
b203d0a2 | 4125 | continue; |
f25c42b8 | 4126 | val = dwc2_readl(hsotg, DPTXFSIZN(i)); |
9da51974 | 4127 | val = (val >> FIFOSIZE_DEPTH_SHIFT) * 4; |
b203d0a2 RB |
4128 | if (val < size) |
4129 | continue; | |
ca4c55ad MYK |
4130 | /* Search for smallest acceptable fifo */ |
4131 | if (val < fifo_size) { | |
4132 | fifo_size = val; | |
4133 | fifo_index = i; | |
4134 | } | |
b203d0a2 | 4135 | } |
ca4c55ad | 4136 | if (!fifo_index) { |
5f2196bd MYK |
4137 | dev_err(hsotg->dev, |
4138 | "%s: No suitable fifo found\n", __func__); | |
b585a48b | 4139 | ret = -ENOMEM; |
5f54c54b | 4140 | goto error1; |
b585a48b | 4141 | } |
97311c8f | 4142 | epctrl &= ~(DXEPCTL_TXFNUM_LIMIT << DXEPCTL_TXFNUM_SHIFT); |
ca4c55ad MYK |
4143 | hsotg->fifo_map |= 1 << fifo_index; |
4144 | epctrl |= DXEPCTL_TXFNUM(fifo_index); | |
4145 | hs_ep->fifo_index = fifo_index; | |
4146 | hs_ep->fifo_size = fifo_size; | |
b203d0a2 | 4147 | } |
10aebc77 | 4148 | |
5b7d70c6 | 4149 | /* for non control endpoints, set PID to D0 */ |
837e9f00 | 4150 | if (index && !hs_ep->isochronous) |
47a1685f | 4151 | epctrl |= DXEPCTL_SETD0PID; |
5b7d70c6 | 4152 | |
5295322a AP |
4153 | /* WA for Full speed ISOC IN in DDMA mode. |
4154 | * By Clear NAK status of EP, core will send ZLP | |
4155 | * to IN token and assert NAK interrupt relying | |
4156 | * on TxFIFO status only | |
4157 | */ | |
4158 | ||
4159 | if (hsotg->gadget.speed == USB_SPEED_FULL && | |
4160 | hs_ep->isochronous && dir_in) { | |
4161 | /* The WA applies only to core versions from 2.72a | |
4162 | * to 4.00a (including both). Also for FS_IOT_1.00a | |
4163 | * and HS_IOT_1.00a. | |
4164 | */ | |
f25c42b8 | 4165 | u32 gsnpsid = dwc2_readl(hsotg, GSNPSID); |
5295322a AP |
4166 | |
4167 | if ((gsnpsid >= DWC2_CORE_REV_2_72a && | |
4168 | gsnpsid <= DWC2_CORE_REV_4_00a) || | |
4169 | gsnpsid == DWC2_FS_IOT_REV_1_00a || | |
4170 | gsnpsid == DWC2_HS_IOT_REV_1_00a) | |
4171 | epctrl |= DXEPCTL_CNAK; | |
4172 | } | |
4173 | ||
5b7d70c6 BD |
4174 | dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n", |
4175 | __func__, epctrl); | |
4176 | ||
f25c42b8 | 4177 | dwc2_writel(hsotg, epctrl, epctrl_reg); |
5b7d70c6 | 4178 | dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x\n", |
f25c42b8 | 4179 | __func__, dwc2_readl(hsotg, epctrl_reg)); |
5b7d70c6 BD |
4180 | |
4181 | /* enable the endpoint interrupt */ | |
1f91b4cc | 4182 | dwc2_hsotg_ctrl_epint(hsotg, index, dir_in, 1); |
5b7d70c6 | 4183 | |
5f54c54b | 4184 | error1: |
22258f49 | 4185 | spin_unlock_irqrestore(&hsotg->lock, flags); |
5f54c54b VA |
4186 | |
4187 | error2: | |
4188 | if (ret && using_desc_dma(hsotg) && hs_ep->desc_list) { | |
54f37f56 | 4189 | dmam_free_coherent(hsotg->dev, desc_num * |
5f54c54b VA |
4190 | sizeof(struct dwc2_dma_desc), |
4191 | hs_ep->desc_list, hs_ep->desc_list_dma); | |
4192 | hs_ep->desc_list = NULL; | |
4193 | } | |
4194 | ||
19c190f9 | 4195 | return ret; |
5b7d70c6 BD |
4196 | } |
4197 | ||
8b9bc460 | 4198 | /** |
1f91b4cc | 4199 | * dwc2_hsotg_ep_disable - disable given endpoint |
8b9bc460 LM |
4200 | * @ep: The endpoint to disable. |
4201 | */ | |
1f91b4cc | 4202 | static int dwc2_hsotg_ep_disable(struct usb_ep *ep) |
5b7d70c6 | 4203 | { |
1f91b4cc | 4204 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 4205 | struct dwc2_hsotg *hsotg = hs_ep->parent; |
5b7d70c6 BD |
4206 | int dir_in = hs_ep->dir_in; |
4207 | int index = hs_ep->index; | |
5b7d70c6 BD |
4208 | u32 epctrl_reg; |
4209 | u32 ctrl; | |
4210 | ||
1e011293 | 4211 | dev_dbg(hsotg->dev, "%s(ep %p)\n", __func__, ep); |
5b7d70c6 | 4212 | |
c6f5c050 | 4213 | if (ep == &hsotg->eps_out[0]->ep) { |
5b7d70c6 BD |
4214 | dev_err(hsotg->dev, "%s: called for ep0\n", __func__); |
4215 | return -EINVAL; | |
9b481092 JS |
4216 | } |
4217 | ||
4218 | if (hsotg->op_state != OTG_STATE_B_PERIPHERAL) { | |
4219 | dev_err(hsotg->dev, "%s: called in host mode?\n", __func__); | |
4220 | return -EINVAL; | |
5b7d70c6 BD |
4221 | } |
4222 | ||
94cb8fd6 | 4223 | epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index); |
5b7d70c6 | 4224 | |
f25c42b8 | 4225 | ctrl = dwc2_readl(hsotg, epctrl_reg); |
a4f82771 VA |
4226 | |
4227 | if (ctrl & DXEPCTL_EPENA) | |
4228 | dwc2_hsotg_ep_stop_xfr(hsotg, hs_ep); | |
4229 | ||
47a1685f DN |
4230 | ctrl &= ~DXEPCTL_EPENA; |
4231 | ctrl &= ~DXEPCTL_USBACTEP; | |
4232 | ctrl |= DXEPCTL_SNAK; | |
5b7d70c6 BD |
4233 | |
4234 | dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl); | |
f25c42b8 | 4235 | dwc2_writel(hsotg, ctrl, epctrl_reg); |
5b7d70c6 BD |
4236 | |
4237 | /* disable endpoint interrupts */ | |
1f91b4cc | 4238 | dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 0); |
5b7d70c6 | 4239 | |
1141ea01 MYK |
4240 | /* terminate all requests with shutdown */ |
4241 | kill_all_requests(hsotg, hs_ep, -ESHUTDOWN); | |
4242 | ||
1c07b20e RB |
4243 | hsotg->fifo_map &= ~(1 << hs_ep->fifo_index); |
4244 | hs_ep->fifo_index = 0; | |
4245 | hs_ep->fifo_size = 0; | |
4246 | ||
5b7d70c6 BD |
4247 | return 0; |
4248 | } | |
4249 | ||
4fe4f9fe MH |
4250 | static int dwc2_hsotg_ep_disable_lock(struct usb_ep *ep) |
4251 | { | |
4252 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); | |
4253 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
4254 | unsigned long flags; | |
4255 | int ret; | |
4256 | ||
4257 | spin_lock_irqsave(&hsotg->lock, flags); | |
4258 | ret = dwc2_hsotg_ep_disable(ep); | |
4259 | spin_unlock_irqrestore(&hsotg->lock, flags); | |
4260 | return ret; | |
4261 | } | |
4262 | ||
5b7d70c6 BD |
4263 | /** |
4264 | * on_list - check request is on the given endpoint | |
4265 | * @ep: The endpoint to check. | |
4266 | * @test: The request to test if it is on the endpoint. | |
8b9bc460 | 4267 | */ |
1f91b4cc | 4268 | static bool on_list(struct dwc2_hsotg_ep *ep, struct dwc2_hsotg_req *test) |
5b7d70c6 | 4269 | { |
1f91b4cc | 4270 | struct dwc2_hsotg_req *req, *treq; |
5b7d70c6 BD |
4271 | |
4272 | list_for_each_entry_safe(req, treq, &ep->queue, queue) { | |
4273 | if (req == test) | |
4274 | return true; | |
4275 | } | |
4276 | ||
4277 | return false; | |
4278 | } | |
4279 | ||
8b9bc460 | 4280 | /** |
1f91b4cc | 4281 | * dwc2_hsotg_ep_dequeue - dequeue given endpoint |
8b9bc460 LM |
4282 | * @ep: The endpoint to dequeue. |
4283 | * @req: The request to be removed from a queue. | |
4284 | */ | |
1f91b4cc | 4285 | static int dwc2_hsotg_ep_dequeue(struct usb_ep *ep, struct usb_request *req) |
5b7d70c6 | 4286 | { |
1f91b4cc FB |
4287 | struct dwc2_hsotg_req *hs_req = our_req(req); |
4288 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); | |
941fcce4 | 4289 | struct dwc2_hsotg *hs = hs_ep->parent; |
5b7d70c6 BD |
4290 | unsigned long flags; |
4291 | ||
1e011293 | 4292 | dev_dbg(hs->dev, "ep_dequeue(%p,%p)\n", ep, req); |
5b7d70c6 | 4293 | |
22258f49 | 4294 | spin_lock_irqsave(&hs->lock, flags); |
5b7d70c6 BD |
4295 | |
4296 | if (!on_list(hs_ep, hs_req)) { | |
22258f49 | 4297 | spin_unlock_irqrestore(&hs->lock, flags); |
5b7d70c6 BD |
4298 | return -EINVAL; |
4299 | } | |
4300 | ||
c524dd5f MYK |
4301 | /* Dequeue already started request */ |
4302 | if (req == &hs_ep->req->req) | |
4303 | dwc2_hsotg_ep_stop_xfr(hs, hs_ep); | |
4304 | ||
1f91b4cc | 4305 | dwc2_hsotg_complete_request(hs, hs_ep, hs_req, -ECONNRESET); |
22258f49 | 4306 | spin_unlock_irqrestore(&hs->lock, flags); |
5b7d70c6 BD |
4307 | |
4308 | return 0; | |
4309 | } | |
4310 | ||
b833ce15 MH |
4311 | /** |
4312 | * dwc2_gadget_ep_set_wedge - set wedge on a given endpoint | |
4313 | * @ep: The endpoint to be wedged. | |
4314 | * | |
4315 | */ | |
4316 | static int dwc2_gadget_ep_set_wedge(struct usb_ep *ep) | |
4317 | { | |
4318 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); | |
4319 | struct dwc2_hsotg *hs = hs_ep->parent; | |
4320 | ||
4321 | unsigned long flags; | |
4322 | int ret; | |
4323 | ||
4324 | spin_lock_irqsave(&hs->lock, flags); | |
4325 | hs_ep->wedged = 1; | |
4326 | ret = dwc2_hsotg_ep_sethalt(ep, 1, false); | |
4327 | spin_unlock_irqrestore(&hs->lock, flags); | |
4328 | ||
4329 | return ret; | |
4330 | } | |
4331 | ||
8b9bc460 | 4332 | /** |
1f91b4cc | 4333 | * dwc2_hsotg_ep_sethalt - set halt on a given endpoint |
8b9bc460 LM |
4334 | * @ep: The endpoint to set halt. |
4335 | * @value: Set or unset the halt. | |
51da43b5 VA |
4336 | * @now: If true, stall the endpoint now. Otherwise return -EAGAIN if |
4337 | * the endpoint is busy processing requests. | |
4338 | * | |
4339 | * We need to stall the endpoint immediately if request comes from set_feature | |
4340 | * protocol command handler. | |
8b9bc460 | 4341 | */ |
51da43b5 | 4342 | static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now) |
5b7d70c6 | 4343 | { |
1f91b4cc | 4344 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 4345 | struct dwc2_hsotg *hs = hs_ep->parent; |
5b7d70c6 | 4346 | int index = hs_ep->index; |
5b7d70c6 BD |
4347 | u32 epreg; |
4348 | u32 epctl; | |
9c39ddc6 | 4349 | u32 xfertype; |
5b7d70c6 BD |
4350 | |
4351 | dev_info(hs->dev, "%s(ep %p %s, %d)\n", __func__, ep, ep->name, value); | |
4352 | ||
c9f721b2 RB |
4353 | if (index == 0) { |
4354 | if (value) | |
1f91b4cc | 4355 | dwc2_hsotg_stall_ep0(hs); |
c9f721b2 RB |
4356 | else |
4357 | dev_warn(hs->dev, | |
4358 | "%s: can't clear halt on ep0\n", __func__); | |
4359 | return 0; | |
4360 | } | |
4361 | ||
15186f10 VA |
4362 | if (hs_ep->isochronous) { |
4363 | dev_err(hs->dev, "%s is Isochronous Endpoint\n", ep->name); | |
4364 | return -EINVAL; | |
4365 | } | |
4366 | ||
51da43b5 VA |
4367 | if (!now && value && !list_empty(&hs_ep->queue)) { |
4368 | dev_dbg(hs->dev, "%s request is pending, cannot halt\n", | |
4369 | ep->name); | |
4370 | return -EAGAIN; | |
4371 | } | |
4372 | ||
c6f5c050 MYK |
4373 | if (hs_ep->dir_in) { |
4374 | epreg = DIEPCTL(index); | |
f25c42b8 | 4375 | epctl = dwc2_readl(hs, epreg); |
c6f5c050 MYK |
4376 | |
4377 | if (value) { | |
5a350d53 | 4378 | epctl |= DXEPCTL_STALL | DXEPCTL_SNAK; |
c6f5c050 MYK |
4379 | if (epctl & DXEPCTL_EPENA) |
4380 | epctl |= DXEPCTL_EPDIS; | |
4381 | } else { | |
4382 | epctl &= ~DXEPCTL_STALL; | |
b833ce15 | 4383 | hs_ep->wedged = 0; |
c6f5c050 MYK |
4384 | xfertype = epctl & DXEPCTL_EPTYPE_MASK; |
4385 | if (xfertype == DXEPCTL_EPTYPE_BULK || | |
9da51974 | 4386 | xfertype == DXEPCTL_EPTYPE_INTERRUPT) |
77b6200e | 4387 | epctl |= DXEPCTL_SETD0PID; |
c6f5c050 | 4388 | } |
f25c42b8 | 4389 | dwc2_writel(hs, epctl, epreg); |
9c39ddc6 | 4390 | } else { |
c6f5c050 | 4391 | epreg = DOEPCTL(index); |
f25c42b8 | 4392 | epctl = dwc2_readl(hs, epreg); |
5b7d70c6 | 4393 | |
34c0887f | 4394 | if (value) { |
fecb3a17 MH |
4395 | /* Unmask GOUTNAKEFF interrupt */ |
4396 | dwc2_hsotg_en_gsint(hs, GINTSTS_GOUTNAKEFF); | |
4397 | ||
6070636c MH |
4398 | if (!(dwc2_readl(hs, GINTSTS) & GINTSTS_GOUTNAKEFF)) |
4399 | dwc2_set_bit(hs, DCTL, DCTL_SGOUTNAK); | |
4400 | // STALL bit will be set in GOUTNAKEFF interrupt handler | |
34c0887f | 4401 | } else { |
c6f5c050 | 4402 | epctl &= ~DXEPCTL_STALL; |
b833ce15 | 4403 | hs_ep->wedged = 0; |
c6f5c050 MYK |
4404 | xfertype = epctl & DXEPCTL_EPTYPE_MASK; |
4405 | if (xfertype == DXEPCTL_EPTYPE_BULK || | |
9da51974 | 4406 | xfertype == DXEPCTL_EPTYPE_INTERRUPT) |
77b6200e | 4407 | epctl |= DXEPCTL_SETD0PID; |
6070636c | 4408 | dwc2_writel(hs, epctl, epreg); |
c6f5c050 | 4409 | } |
9c39ddc6 | 4410 | } |
5b7d70c6 | 4411 | |
a18ed7b0 | 4412 | hs_ep->halted = value; |
5b7d70c6 BD |
4413 | return 0; |
4414 | } | |
4415 | ||
5ad1d316 | 4416 | /** |
1f91b4cc | 4417 | * dwc2_hsotg_ep_sethalt_lock - set halt on a given endpoint with lock held |
5ad1d316 LM |
4418 | * @ep: The endpoint to set halt. |
4419 | * @value: Set or unset the halt. | |
4420 | */ | |
1f91b4cc | 4421 | static int dwc2_hsotg_ep_sethalt_lock(struct usb_ep *ep, int value) |
5ad1d316 | 4422 | { |
1f91b4cc | 4423 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 4424 | struct dwc2_hsotg *hs = hs_ep->parent; |
8879904b JH |
4425 | unsigned long flags; |
4426 | int ret; | |
5ad1d316 LM |
4427 | |
4428 | spin_lock_irqsave(&hs->lock, flags); | |
51da43b5 | 4429 | ret = dwc2_hsotg_ep_sethalt(ep, value, false); |
5ad1d316 LM |
4430 | spin_unlock_irqrestore(&hs->lock, flags); |
4431 | ||
4432 | return ret; | |
4433 | } | |
4434 | ||
ebce561a | 4435 | static const struct usb_ep_ops dwc2_hsotg_ep_ops = { |
1f91b4cc | 4436 | .enable = dwc2_hsotg_ep_enable, |
4fe4f9fe | 4437 | .disable = dwc2_hsotg_ep_disable_lock, |
1f91b4cc FB |
4438 | .alloc_request = dwc2_hsotg_ep_alloc_request, |
4439 | .free_request = dwc2_hsotg_ep_free_request, | |
4440 | .queue = dwc2_hsotg_ep_queue_lock, | |
4441 | .dequeue = dwc2_hsotg_ep_dequeue, | |
4442 | .set_halt = dwc2_hsotg_ep_sethalt_lock, | |
b833ce15 | 4443 | .set_wedge = dwc2_gadget_ep_set_wedge, |
25985edc | 4444 | /* note, don't believe we have any call for the fifo routines */ |
5b7d70c6 BD |
4445 | }; |
4446 | ||
8b9bc460 | 4447 | /** |
9da51974 | 4448 | * dwc2_hsotg_init - initialize the usb core |
8b9bc460 LM |
4449 | * @hsotg: The driver state |
4450 | */ | |
1f91b4cc | 4451 | static void dwc2_hsotg_init(struct dwc2_hsotg *hsotg) |
b3f489b2 LM |
4452 | { |
4453 | /* unmask subset of endpoint interrupts */ | |
4454 | ||
f25c42b8 | 4455 | dwc2_writel(hsotg, DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK | |
95c8bc36 | 4456 | DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK, |
f25c42b8 | 4457 | DIEPMSK); |
b3f489b2 | 4458 | |
f25c42b8 | 4459 | dwc2_writel(hsotg, DOEPMSK_SETUPMSK | DOEPMSK_AHBERRMSK | |
95c8bc36 | 4460 | DOEPMSK_EPDISBLDMSK | DOEPMSK_XFERCOMPLMSK, |
f25c42b8 | 4461 | DOEPMSK); |
b3f489b2 | 4462 | |
f25c42b8 | 4463 | dwc2_writel(hsotg, 0, DAINTMSK); |
b3f489b2 LM |
4464 | |
4465 | /* Be in disconnected state until gadget is registered */ | |
f25c42b8 | 4466 | dwc2_set_bit(hsotg, DCTL, DCTL_SFTDISCON); |
b3f489b2 | 4467 | |
b3f489b2 LM |
4468 | /* setup fifos */ |
4469 | ||
4470 | dev_dbg(hsotg->dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n", | |
f25c42b8 GS |
4471 | dwc2_readl(hsotg, GRXFSIZ), |
4472 | dwc2_readl(hsotg, GNPTXFSIZ)); | |
b3f489b2 | 4473 | |
1f91b4cc | 4474 | dwc2_hsotg_init_fifo(hsotg); |
b3f489b2 | 4475 | |
f5090044 | 4476 | if (using_dma(hsotg)) |
f25c42b8 | 4477 | dwc2_set_bit(hsotg, GAHBCFG, GAHBCFG_DMA_EN); |
b3f489b2 LM |
4478 | } |
4479 | ||
8b9bc460 | 4480 | /** |
1f91b4cc | 4481 | * dwc2_hsotg_udc_start - prepare the udc for work |
8b9bc460 LM |
4482 | * @gadget: The usb gadget state |
4483 | * @driver: The usb gadget driver | |
4484 | * | |
4485 | * Perform initialization to prepare udc device and driver | |
4486 | * to work. | |
4487 | */ | |
1f91b4cc | 4488 | static int dwc2_hsotg_udc_start(struct usb_gadget *gadget, |
9da51974 | 4489 | struct usb_gadget_driver *driver) |
5b7d70c6 | 4490 | { |
941fcce4 | 4491 | struct dwc2_hsotg *hsotg = to_hsotg(gadget); |
5b9451f8 | 4492 | unsigned long flags; |
5b7d70c6 BD |
4493 | int ret; |
4494 | ||
4495 | if (!hsotg) { | |
a023da33 | 4496 | pr_err("%s: called with no device\n", __func__); |
5b7d70c6 BD |
4497 | return -ENODEV; |
4498 | } | |
4499 | ||
4500 | if (!driver) { | |
4501 | dev_err(hsotg->dev, "%s: no driver\n", __func__); | |
4502 | return -EINVAL; | |
4503 | } | |
4504 | ||
7177aed4 | 4505 | if (driver->max_speed < USB_SPEED_FULL) |
5b7d70c6 | 4506 | dev_err(hsotg->dev, "%s: bad speed\n", __func__); |
5b7d70c6 | 4507 | |
f65f0f10 | 4508 | if (!driver->setup) { |
5b7d70c6 BD |
4509 | dev_err(hsotg->dev, "%s: missing entry points\n", __func__); |
4510 | return -EINVAL; | |
4511 | } | |
4512 | ||
4513 | WARN_ON(hsotg->driver); | |
4514 | ||
4515 | driver->driver.bus = NULL; | |
4516 | hsotg->driver = driver; | |
7d7b2292 | 4517 | hsotg->gadget.dev.of_node = hsotg->dev->of_node; |
5b7d70c6 BD |
4518 | hsotg->gadget.speed = USB_SPEED_UNKNOWN; |
4519 | ||
09a75e85 MS |
4520 | if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) { |
4521 | ret = dwc2_lowlevel_hw_enable(hsotg); | |
4522 | if (ret) | |
4523 | goto err; | |
5b7d70c6 BD |
4524 | } |
4525 | ||
f6c01592 GH |
4526 | if (!IS_ERR_OR_NULL(hsotg->uphy)) |
4527 | otg_set_peripheral(hsotg->uphy->otg, &hsotg->gadget); | |
c816c47f | 4528 | |
5b9451f8 | 4529 | spin_lock_irqsave(&hsotg->lock, flags); |
d0f0ac56 JY |
4530 | if (dwc2_hw_is_device(hsotg)) { |
4531 | dwc2_hsotg_init(hsotg); | |
4532 | dwc2_hsotg_core_init_disconnected(hsotg, false); | |
4533 | } | |
4534 | ||
dc6e69e6 | 4535 | hsotg->enabled = 0; |
5b9451f8 MS |
4536 | spin_unlock_irqrestore(&hsotg->lock, flags); |
4537 | ||
10209abe | 4538 | gadget->sg_supported = using_desc_dma(hsotg); |
5b7d70c6 | 4539 | dev_info(hsotg->dev, "bound driver %s\n", driver->driver.name); |
5b9451f8 | 4540 | |
5b7d70c6 BD |
4541 | return 0; |
4542 | ||
4543 | err: | |
4544 | hsotg->driver = NULL; | |
5b7d70c6 BD |
4545 | return ret; |
4546 | } | |
4547 | ||
8b9bc460 | 4548 | /** |
1f91b4cc | 4549 | * dwc2_hsotg_udc_stop - stop the udc |
8b9bc460 | 4550 | * @gadget: The usb gadget state |
8b9bc460 LM |
4551 | * |
4552 | * Stop udc hw block and stay tunned for future transmissions | |
4553 | */ | |
1f91b4cc | 4554 | static int dwc2_hsotg_udc_stop(struct usb_gadget *gadget) |
5b7d70c6 | 4555 | { |
941fcce4 | 4556 | struct dwc2_hsotg *hsotg = to_hsotg(gadget); |
8879904b | 4557 | unsigned long flags; |
5b7d70c6 BD |
4558 | int ep; |
4559 | ||
4560 | if (!hsotg) | |
4561 | return -ENODEV; | |
4562 | ||
5b7d70c6 | 4563 | /* all endpoints should be shutdown */ |
c6f5c050 MYK |
4564 | for (ep = 1; ep < hsotg->num_of_eps; ep++) { |
4565 | if (hsotg->eps_in[ep]) | |
4fe4f9fe | 4566 | dwc2_hsotg_ep_disable_lock(&hsotg->eps_in[ep]->ep); |
c6f5c050 | 4567 | if (hsotg->eps_out[ep]) |
4fe4f9fe | 4568 | dwc2_hsotg_ep_disable_lock(&hsotg->eps_out[ep]->ep); |
c6f5c050 | 4569 | } |
5b7d70c6 | 4570 | |
2b19a52c LM |
4571 | spin_lock_irqsave(&hsotg->lock, flags); |
4572 | ||
32805c35 | 4573 | hsotg->driver = NULL; |
5b7d70c6 | 4574 | hsotg->gadget.speed = USB_SPEED_UNKNOWN; |
dc6e69e6 | 4575 | hsotg->enabled = 0; |
5b7d70c6 | 4576 | |
2b19a52c LM |
4577 | spin_unlock_irqrestore(&hsotg->lock, flags); |
4578 | ||
f6c01592 GH |
4579 | if (!IS_ERR_OR_NULL(hsotg->uphy)) |
4580 | otg_set_peripheral(hsotg->uphy->otg, NULL); | |
c816c47f | 4581 | |
09a75e85 MS |
4582 | if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) |
4583 | dwc2_lowlevel_hw_disable(hsotg); | |
5b7d70c6 BD |
4584 | |
4585 | return 0; | |
4586 | } | |
5b7d70c6 | 4587 | |
8b9bc460 | 4588 | /** |
1f91b4cc | 4589 | * dwc2_hsotg_gadget_getframe - read the frame number |
8b9bc460 LM |
4590 | * @gadget: The usb gadget state |
4591 | * | |
4592 | * Read the {micro} frame number | |
4593 | */ | |
1f91b4cc | 4594 | static int dwc2_hsotg_gadget_getframe(struct usb_gadget *gadget) |
5b7d70c6 | 4595 | { |
1f91b4cc | 4596 | return dwc2_hsotg_read_frameno(to_hsotg(gadget)); |
5b7d70c6 BD |
4597 | } |
4598 | ||
1a0808cb JK |
4599 | /** |
4600 | * dwc2_hsotg_set_selfpowered - set if device is self/bus powered | |
4601 | * @gadget: The usb gadget state | |
4602 | * @is_selfpowered: Whether the device is self-powered | |
4603 | * | |
4604 | * Set if the device is self or bus powered. | |
4605 | */ | |
4606 | static int dwc2_hsotg_set_selfpowered(struct usb_gadget *gadget, | |
4607 | int is_selfpowered) | |
4608 | { | |
4609 | struct dwc2_hsotg *hsotg = to_hsotg(gadget); | |
4610 | unsigned long flags; | |
4611 | ||
4612 | spin_lock_irqsave(&hsotg->lock, flags); | |
4613 | gadget->is_selfpowered = !!is_selfpowered; | |
4614 | spin_unlock_irqrestore(&hsotg->lock, flags); | |
4615 | ||
4616 | return 0; | |
4617 | } | |
4618 | ||
a188b689 | 4619 | /** |
1f91b4cc | 4620 | * dwc2_hsotg_pullup - connect/disconnect the USB PHY |
a188b689 LM |
4621 | * @gadget: The usb gadget state |
4622 | * @is_on: Current state of the USB PHY | |
4623 | * | |
4624 | * Connect/Disconnect the USB PHY pullup | |
4625 | */ | |
1f91b4cc | 4626 | static int dwc2_hsotg_pullup(struct usb_gadget *gadget, int is_on) |
a188b689 | 4627 | { |
941fcce4 | 4628 | struct dwc2_hsotg *hsotg = to_hsotg(gadget); |
8879904b | 4629 | unsigned long flags; |
a188b689 | 4630 | |
77ba9119 | 4631 | dev_dbg(hsotg->dev, "%s: is_on: %d op_state: %d\n", __func__, is_on, |
9da51974 | 4632 | hsotg->op_state); |
77ba9119 GH |
4633 | |
4634 | /* Don't modify pullup state while in host mode */ | |
4635 | if (hsotg->op_state != OTG_STATE_B_PERIPHERAL) { | |
4636 | hsotg->enabled = is_on; | |
4637 | return 0; | |
4638 | } | |
a188b689 LM |
4639 | |
4640 | spin_lock_irqsave(&hsotg->lock, flags); | |
4641 | if (is_on) { | |
dc6e69e6 | 4642 | hsotg->enabled = 1; |
1f91b4cc | 4643 | dwc2_hsotg_core_init_disconnected(hsotg, false); |
66e77a24 RK |
4644 | /* Enable ACG feature in device mode,if supported */ |
4645 | dwc2_enable_acg(hsotg); | |
1f91b4cc | 4646 | dwc2_hsotg_core_connect(hsotg); |
a188b689 | 4647 | } else { |
1f91b4cc FB |
4648 | dwc2_hsotg_core_disconnect(hsotg); |
4649 | dwc2_hsotg_disconnect(hsotg); | |
dc6e69e6 | 4650 | hsotg->enabled = 0; |
a188b689 LM |
4651 | } |
4652 | ||
4653 | hsotg->gadget.speed = USB_SPEED_UNKNOWN; | |
4654 | spin_unlock_irqrestore(&hsotg->lock, flags); | |
4655 | ||
4656 | return 0; | |
4657 | } | |
4658 | ||
1f91b4cc | 4659 | static int dwc2_hsotg_vbus_session(struct usb_gadget *gadget, int is_active) |
83d98223 GH |
4660 | { |
4661 | struct dwc2_hsotg *hsotg = to_hsotg(gadget); | |
4662 | unsigned long flags; | |
4663 | ||
4664 | dev_dbg(hsotg->dev, "%s: is_active: %d\n", __func__, is_active); | |
4665 | spin_lock_irqsave(&hsotg->lock, flags); | |
4666 | ||
61f7223b | 4667 | /* |
c9c394ab AP |
4668 | * If controller is in partial power down state, it must exit from |
4669 | * that state before being initialized / de-initialized | |
61f7223b | 4670 | */ |
c9c394ab AP |
4671 | if (hsotg->lx_state == DWC2_L2 && hsotg->in_ppd) |
4672 | /* | |
4673 | * No need to check the return value as | |
4674 | * registers are not being restored. | |
4675 | */ | |
4676 | dwc2_exit_partial_power_down(hsotg, 0, false); | |
61f7223b | 4677 | |
83d98223 | 4678 | if (is_active) { |
cd0e641c | 4679 | hsotg->op_state = OTG_STATE_B_PERIPHERAL; |
065d3931 | 4680 | |
1f91b4cc | 4681 | dwc2_hsotg_core_init_disconnected(hsotg, false); |
66e77a24 RK |
4682 | if (hsotg->enabled) { |
4683 | /* Enable ACG feature in device mode,if supported */ | |
4684 | dwc2_enable_acg(hsotg); | |
1f91b4cc | 4685 | dwc2_hsotg_core_connect(hsotg); |
66e77a24 | 4686 | } |
83d98223 | 4687 | } else { |
1f91b4cc FB |
4688 | dwc2_hsotg_core_disconnect(hsotg); |
4689 | dwc2_hsotg_disconnect(hsotg); | |
83d98223 GH |
4690 | } |
4691 | ||
4692 | spin_unlock_irqrestore(&hsotg->lock, flags); | |
4693 | return 0; | |
4694 | } | |
4695 | ||
596d696a | 4696 | /** |
1f91b4cc | 4697 | * dwc2_hsotg_vbus_draw - report bMaxPower field |
596d696a GH |
4698 | * @gadget: The usb gadget state |
4699 | * @mA: Amount of current | |
4700 | * | |
4701 | * Report how much power the device may consume to the phy. | |
4702 | */ | |
9da51974 | 4703 | static int dwc2_hsotg_vbus_draw(struct usb_gadget *gadget, unsigned int mA) |
596d696a GH |
4704 | { |
4705 | struct dwc2_hsotg *hsotg = to_hsotg(gadget); | |
4706 | ||
4707 | if (IS_ERR_OR_NULL(hsotg->uphy)) | |
4708 | return -ENOTSUPP; | |
4709 | return usb_phy_set_power(hsotg->uphy, mA); | |
4710 | } | |
4711 | ||
5324bad6 AA |
4712 | static void dwc2_gadget_set_speed(struct usb_gadget *g, enum usb_device_speed speed) |
4713 | { | |
4714 | struct dwc2_hsotg *hsotg = to_hsotg(g); | |
4715 | unsigned long flags; | |
4716 | ||
4717 | spin_lock_irqsave(&hsotg->lock, flags); | |
4718 | switch (speed) { | |
4719 | case USB_SPEED_HIGH: | |
4720 | hsotg->params.speed = DWC2_SPEED_PARAM_HIGH; | |
4721 | break; | |
4722 | case USB_SPEED_FULL: | |
4723 | hsotg->params.speed = DWC2_SPEED_PARAM_FULL; | |
4724 | break; | |
4725 | case USB_SPEED_LOW: | |
4726 | hsotg->params.speed = DWC2_SPEED_PARAM_LOW; | |
4727 | break; | |
4728 | default: | |
4729 | dev_err(hsotg->dev, "invalid speed (%d)\n", speed); | |
4730 | } | |
4731 | spin_unlock_irqrestore(&hsotg->lock, flags); | |
4732 | } | |
4733 | ||
1f91b4cc FB |
4734 | static const struct usb_gadget_ops dwc2_hsotg_gadget_ops = { |
4735 | .get_frame = dwc2_hsotg_gadget_getframe, | |
1a0808cb | 4736 | .set_selfpowered = dwc2_hsotg_set_selfpowered, |
1f91b4cc FB |
4737 | .udc_start = dwc2_hsotg_udc_start, |
4738 | .udc_stop = dwc2_hsotg_udc_stop, | |
4739 | .pullup = dwc2_hsotg_pullup, | |
5324bad6 | 4740 | .udc_set_speed = dwc2_gadget_set_speed, |
1f91b4cc FB |
4741 | .vbus_session = dwc2_hsotg_vbus_session, |
4742 | .vbus_draw = dwc2_hsotg_vbus_draw, | |
5b7d70c6 BD |
4743 | }; |
4744 | ||
4745 | /** | |
1f91b4cc | 4746 | * dwc2_hsotg_initep - initialise a single endpoint |
5b7d70c6 BD |
4747 | * @hsotg: The device state. |
4748 | * @hs_ep: The endpoint to be initialised. | |
4749 | * @epnum: The endpoint number | |
6fb914d7 | 4750 | * @dir_in: True if direction is in. |
5b7d70c6 BD |
4751 | * |
4752 | * Initialise the given endpoint (as part of the probe and device state | |
4753 | * creation) to give to the gadget driver. Setup the endpoint name, any | |
4754 | * direction information and other state that may be required. | |
4755 | */ | |
1f91b4cc | 4756 | static void dwc2_hsotg_initep(struct dwc2_hsotg *hsotg, |
9da51974 | 4757 | struct dwc2_hsotg_ep *hs_ep, |
c6f5c050 MYK |
4758 | int epnum, |
4759 | bool dir_in) | |
5b7d70c6 | 4760 | { |
5b7d70c6 BD |
4761 | char *dir; |
4762 | ||
4763 | if (epnum == 0) | |
4764 | dir = ""; | |
c6f5c050 | 4765 | else if (dir_in) |
5b7d70c6 | 4766 | dir = "in"; |
c6f5c050 MYK |
4767 | else |
4768 | dir = "out"; | |
5b7d70c6 | 4769 | |
c6f5c050 | 4770 | hs_ep->dir_in = dir_in; |
5b7d70c6 BD |
4771 | hs_ep->index = epnum; |
4772 | ||
4773 | snprintf(hs_ep->name, sizeof(hs_ep->name), "ep%d%s", epnum, dir); | |
4774 | ||
4775 | INIT_LIST_HEAD(&hs_ep->queue); | |
4776 | INIT_LIST_HEAD(&hs_ep->ep.ep_list); | |
4777 | ||
5b7d70c6 BD |
4778 | /* add to the list of endpoints known by the gadget driver */ |
4779 | if (epnum) | |
4780 | list_add_tail(&hs_ep->ep.ep_list, &hsotg->gadget.ep_list); | |
4781 | ||
4782 | hs_ep->parent = hsotg; | |
4783 | hs_ep->ep.name = hs_ep->name; | |
38e9002b VM |
4784 | |
4785 | if (hsotg->params.speed == DWC2_SPEED_PARAM_LOW) | |
4786 | usb_ep_set_maxpacket_limit(&hs_ep->ep, 8); | |
4787 | else | |
4788 | usb_ep_set_maxpacket_limit(&hs_ep->ep, | |
4789 | epnum ? 1024 : EP0_MPS_LIMIT); | |
1f91b4cc | 4790 | hs_ep->ep.ops = &dwc2_hsotg_ep_ops; |
5b7d70c6 | 4791 | |
2954522f RB |
4792 | if (epnum == 0) { |
4793 | hs_ep->ep.caps.type_control = true; | |
4794 | } else { | |
38e9002b VM |
4795 | if (hsotg->params.speed != DWC2_SPEED_PARAM_LOW) { |
4796 | hs_ep->ep.caps.type_iso = true; | |
4797 | hs_ep->ep.caps.type_bulk = true; | |
4798 | } | |
2954522f RB |
4799 | hs_ep->ep.caps.type_int = true; |
4800 | } | |
4801 | ||
4802 | if (dir_in) | |
4803 | hs_ep->ep.caps.dir_in = true; | |
4804 | else | |
4805 | hs_ep->ep.caps.dir_out = true; | |
4806 | ||
8b9bc460 LM |
4807 | /* |
4808 | * if we're using dma, we need to set the next-endpoint pointer | |
5b7d70c6 BD |
4809 | * to be something valid. |
4810 | */ | |
4811 | ||
4812 | if (using_dma(hsotg)) { | |
47a1685f | 4813 | u32 next = DXEPCTL_NEXTEP((epnum + 1) % 15); |
9da51974 | 4814 | |
c6f5c050 | 4815 | if (dir_in) |
f25c42b8 | 4816 | dwc2_writel(hsotg, next, DIEPCTL(epnum)); |
c6f5c050 | 4817 | else |
f25c42b8 | 4818 | dwc2_writel(hsotg, next, DOEPCTL(epnum)); |
5b7d70c6 BD |
4819 | } |
4820 | } | |
4821 | ||
b3f489b2 | 4822 | /** |
1f91b4cc | 4823 | * dwc2_hsotg_hw_cfg - read HW configuration registers |
6fb914d7 | 4824 | * @hsotg: Programming view of the DWC_otg controller |
b3f489b2 LM |
4825 | * |
4826 | * Read the USB core HW configuration registers | |
4827 | */ | |
1f91b4cc | 4828 | static int dwc2_hsotg_hw_cfg(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 4829 | { |
c6f5c050 MYK |
4830 | u32 cfg; |
4831 | u32 ep_type; | |
4832 | u32 i; | |
4833 | ||
b3f489b2 | 4834 | /* check hardware configuration */ |
5b7d70c6 | 4835 | |
43e90349 JY |
4836 | hsotg->num_of_eps = hsotg->hw_params.num_dev_ep; |
4837 | ||
c6f5c050 MYK |
4838 | /* Add ep0 */ |
4839 | hsotg->num_of_eps++; | |
10aebc77 | 4840 | |
b98866c2 JY |
4841 | hsotg->eps_in[0] = devm_kzalloc(hsotg->dev, |
4842 | sizeof(struct dwc2_hsotg_ep), | |
4843 | GFP_KERNEL); | |
c6f5c050 MYK |
4844 | if (!hsotg->eps_in[0]) |
4845 | return -ENOMEM; | |
1f91b4cc | 4846 | /* Same dwc2_hsotg_ep is used in both directions for ep0 */ |
c6f5c050 MYK |
4847 | hsotg->eps_out[0] = hsotg->eps_in[0]; |
4848 | ||
43e90349 | 4849 | cfg = hsotg->hw_params.dev_ep_dirs; |
251a17f5 | 4850 | for (i = 1, cfg >>= 2; i < hsotg->num_of_eps; i++, cfg >>= 2) { |
c6f5c050 MYK |
4851 | ep_type = cfg & 3; |
4852 | /* Direction in or both */ | |
4853 | if (!(ep_type & 2)) { | |
4854 | hsotg->eps_in[i] = devm_kzalloc(hsotg->dev, | |
1f91b4cc | 4855 | sizeof(struct dwc2_hsotg_ep), GFP_KERNEL); |
c6f5c050 MYK |
4856 | if (!hsotg->eps_in[i]) |
4857 | return -ENOMEM; | |
4858 | } | |
4859 | /* Direction out or both */ | |
4860 | if (!(ep_type & 1)) { | |
4861 | hsotg->eps_out[i] = devm_kzalloc(hsotg->dev, | |
1f91b4cc | 4862 | sizeof(struct dwc2_hsotg_ep), GFP_KERNEL); |
c6f5c050 MYK |
4863 | if (!hsotg->eps_out[i]) |
4864 | return -ENOMEM; | |
4865 | } | |
4866 | } | |
4867 | ||
43e90349 JY |
4868 | hsotg->fifo_mem = hsotg->hw_params.total_fifo_size; |
4869 | hsotg->dedicated_fifos = hsotg->hw_params.en_multiple_tx_fifo; | |
10aebc77 | 4870 | |
cff9eb75 MS |
4871 | dev_info(hsotg->dev, "EPs: %d, %s fifos, %d entries in SPRAM\n", |
4872 | hsotg->num_of_eps, | |
4873 | hsotg->dedicated_fifos ? "dedicated" : "shared", | |
4874 | hsotg->fifo_mem); | |
c6f5c050 | 4875 | return 0; |
5b7d70c6 BD |
4876 | } |
4877 | ||
8b9bc460 | 4878 | /** |
1f91b4cc | 4879 | * dwc2_hsotg_dump - dump state of the udc |
6fb914d7 GT |
4880 | * @hsotg: Programming view of the DWC_otg controller |
4881 | * | |
8b9bc460 | 4882 | */ |
1f91b4cc | 4883 | static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 4884 | { |
83a01804 | 4885 | #ifdef DEBUG |
5b7d70c6 | 4886 | struct device *dev = hsotg->dev; |
5b7d70c6 BD |
4887 | u32 val; |
4888 | int idx; | |
4889 | ||
4890 | dev_info(dev, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n", | |
f25c42b8 GS |
4891 | dwc2_readl(hsotg, DCFG), dwc2_readl(hsotg, DCTL), |
4892 | dwc2_readl(hsotg, DIEPMSK)); | |
5b7d70c6 | 4893 | |
f889f23d | 4894 | dev_info(dev, "GAHBCFG=0x%08x, GHWCFG1=0x%08x\n", |
f25c42b8 | 4895 | dwc2_readl(hsotg, GAHBCFG), dwc2_readl(hsotg, GHWCFG1)); |
5b7d70c6 BD |
4896 | |
4897 | dev_info(dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n", | |
f25c42b8 | 4898 | dwc2_readl(hsotg, GRXFSIZ), dwc2_readl(hsotg, GNPTXFSIZ)); |
5b7d70c6 BD |
4899 | |
4900 | /* show periodic fifo settings */ | |
4901 | ||
364f8e93 | 4902 | for (idx = 1; idx < hsotg->num_of_eps; idx++) { |
f25c42b8 | 4903 | val = dwc2_readl(hsotg, DPTXFSIZN(idx)); |
5b7d70c6 | 4904 | dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx, |
47a1685f DN |
4905 | val >> FIFOSIZE_DEPTH_SHIFT, |
4906 | val & FIFOSIZE_STARTADDR_MASK); | |
5b7d70c6 BD |
4907 | } |
4908 | ||
364f8e93 | 4909 | for (idx = 0; idx < hsotg->num_of_eps; idx++) { |
5b7d70c6 BD |
4910 | dev_info(dev, |
4911 | "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx, | |
f25c42b8 GS |
4912 | dwc2_readl(hsotg, DIEPCTL(idx)), |
4913 | dwc2_readl(hsotg, DIEPTSIZ(idx)), | |
4914 | dwc2_readl(hsotg, DIEPDMA(idx))); | |
5b7d70c6 | 4915 | |
f25c42b8 | 4916 | val = dwc2_readl(hsotg, DOEPCTL(idx)); |
5b7d70c6 BD |
4917 | dev_info(dev, |
4918 | "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", | |
f25c42b8 GS |
4919 | idx, dwc2_readl(hsotg, DOEPCTL(idx)), |
4920 | dwc2_readl(hsotg, DOEPTSIZ(idx)), | |
4921 | dwc2_readl(hsotg, DOEPDMA(idx))); | |
5b7d70c6 BD |
4922 | } |
4923 | ||
4924 | dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n", | |
f25c42b8 | 4925 | dwc2_readl(hsotg, DVBUSDIS), dwc2_readl(hsotg, DVBUSPULSE)); |
83a01804 | 4926 | #endif |
5b7d70c6 BD |
4927 | } |
4928 | ||
8b9bc460 | 4929 | /** |
117777b2 | 4930 | * dwc2_gadget_init - init function for gadget |
6fb914d7 GT |
4931 | * @hsotg: Programming view of the DWC_otg controller |
4932 | * | |
8b9bc460 | 4933 | */ |
f3768997 | 4934 | int dwc2_gadget_init(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 4935 | { |
117777b2 | 4936 | struct device *dev = hsotg->dev; |
5b7d70c6 BD |
4937 | int epnum; |
4938 | int ret; | |
43e90349 | 4939 | |
0a176279 GH |
4940 | /* Dump fifo information */ |
4941 | dev_dbg(dev, "NonPeriodic TXFIFO size: %d\n", | |
05ee799f JY |
4942 | hsotg->params.g_np_tx_fifo_size); |
4943 | dev_dbg(dev, "RXFIFO size: %d\n", hsotg->params.g_rx_fifo_size); | |
5b7d70c6 | 4944 | |
d327ab5b | 4945 | hsotg->gadget.max_speed = USB_SPEED_HIGH; |
1f91b4cc | 4946 | hsotg->gadget.ops = &dwc2_hsotg_gadget_ops; |
5b7d70c6 | 4947 | hsotg->gadget.name = dev_name(dev); |
fa389a6d | 4948 | hsotg->remote_wakeup_allowed = 0; |
7455f8b7 JY |
4949 | |
4950 | if (hsotg->params.lpm) | |
4951 | hsotg->gadget.lpm_capable = true; | |
4952 | ||
097ee662 GH |
4953 | if (hsotg->dr_mode == USB_DR_MODE_OTG) |
4954 | hsotg->gadget.is_otg = 1; | |
ec4cc657 MYK |
4955 | else if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) |
4956 | hsotg->op_state = OTG_STATE_B_PERIPHERAL; | |
5b7d70c6 | 4957 | |
1f91b4cc | 4958 | ret = dwc2_hsotg_hw_cfg(hsotg); |
c6f5c050 MYK |
4959 | if (ret) { |
4960 | dev_err(hsotg->dev, "Hardware configuration failed: %d\n", ret); | |
09a75e85 | 4961 | return ret; |
c6f5c050 MYK |
4962 | } |
4963 | ||
3f95001d MYK |
4964 | hsotg->ctrl_buff = devm_kzalloc(hsotg->dev, |
4965 | DWC2_CTRL_BUFF_SIZE, GFP_KERNEL); | |
8bae0f8c | 4966 | if (!hsotg->ctrl_buff) |
09a75e85 | 4967 | return -ENOMEM; |
3f95001d MYK |
4968 | |
4969 | hsotg->ep0_buff = devm_kzalloc(hsotg->dev, | |
4970 | DWC2_CTRL_BUFF_SIZE, GFP_KERNEL); | |
8bae0f8c | 4971 | if (!hsotg->ep0_buff) |
09a75e85 | 4972 | return -ENOMEM; |
3f95001d | 4973 | |
0f6b80c0 VA |
4974 | if (using_desc_dma(hsotg)) { |
4975 | ret = dwc2_gadget_alloc_ctrl_desc_chains(hsotg); | |
4976 | if (ret < 0) | |
4977 | return ret; | |
4978 | } | |
4979 | ||
f3768997 VM |
4980 | ret = devm_request_irq(hsotg->dev, hsotg->irq, dwc2_hsotg_irq, |
4981 | IRQF_SHARED, dev_name(hsotg->dev), hsotg); | |
eb3c56c5 | 4982 | if (ret < 0) { |
db8178c3 | 4983 | dev_err(dev, "cannot claim IRQ for gadget\n"); |
09a75e85 | 4984 | return ret; |
eb3c56c5 MS |
4985 | } |
4986 | ||
b3f489b2 LM |
4987 | /* hsotg->num_of_eps holds number of EPs other than ep0 */ |
4988 | ||
4989 | if (hsotg->num_of_eps == 0) { | |
4990 | dev_err(dev, "wrong number of EPs (zero)\n"); | |
09a75e85 | 4991 | return -EINVAL; |
b3f489b2 LM |
4992 | } |
4993 | ||
b3f489b2 LM |
4994 | /* setup endpoint information */ |
4995 | ||
4996 | INIT_LIST_HEAD(&hsotg->gadget.ep_list); | |
c6f5c050 | 4997 | hsotg->gadget.ep0 = &hsotg->eps_out[0]->ep; |
b3f489b2 LM |
4998 | |
4999 | /* allocate EP0 request */ | |
5000 | ||
1f91b4cc | 5001 | hsotg->ctrl_req = dwc2_hsotg_ep_alloc_request(&hsotg->eps_out[0]->ep, |
b3f489b2 LM |
5002 | GFP_KERNEL); |
5003 | if (!hsotg->ctrl_req) { | |
5004 | dev_err(dev, "failed to allocate ctrl req\n"); | |
09a75e85 | 5005 | return -ENOMEM; |
b3f489b2 | 5006 | } |
5b7d70c6 BD |
5007 | |
5008 | /* initialise the endpoints now the core has been initialised */ | |
c6f5c050 MYK |
5009 | for (epnum = 0; epnum < hsotg->num_of_eps; epnum++) { |
5010 | if (hsotg->eps_in[epnum]) | |
1f91b4cc | 5011 | dwc2_hsotg_initep(hsotg, hsotg->eps_in[epnum], |
9da51974 | 5012 | epnum, 1); |
c6f5c050 | 5013 | if (hsotg->eps_out[epnum]) |
1f91b4cc | 5014 | dwc2_hsotg_initep(hsotg, hsotg->eps_out[epnum], |
9da51974 | 5015 | epnum, 0); |
c6f5c050 | 5016 | } |
5b7d70c6 | 5017 | |
1f91b4cc | 5018 | dwc2_hsotg_dump(hsotg); |
5b7d70c6 | 5019 | |
5b7d70c6 | 5020 | return 0; |
5b7d70c6 BD |
5021 | } |
5022 | ||
8b9bc460 | 5023 | /** |
1f91b4cc | 5024 | * dwc2_hsotg_remove - remove function for hsotg driver |
6fb914d7 GT |
5025 | * @hsotg: Programming view of the DWC_otg controller |
5026 | * | |
8b9bc460 | 5027 | */ |
1f91b4cc | 5028 | int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 5029 | { |
0f91349b | 5030 | usb_del_gadget_udc(&hsotg->gadget); |
9bb073a0 | 5031 | dwc2_hsotg_ep_free_request(&hsotg->eps_out[0]->ep, hsotg->ctrl_req); |
31ee04de | 5032 | |
5b7d70c6 BD |
5033 | return 0; |
5034 | } | |
5035 | ||
1f91b4cc | 5036 | int dwc2_hsotg_suspend(struct dwc2_hsotg *hsotg) |
b83e333a | 5037 | { |
b83e333a | 5038 | unsigned long flags; |
b83e333a | 5039 | |
9e779778 | 5040 | if (hsotg->lx_state != DWC2_L0) |
09a75e85 | 5041 | return 0; |
9e779778 | 5042 | |
dc6e69e6 MS |
5043 | if (hsotg->driver) { |
5044 | int ep; | |
5045 | ||
b83e333a MS |
5046 | dev_info(hsotg->dev, "suspending usb gadget %s\n", |
5047 | hsotg->driver->driver.name); | |
5048 | ||
dc6e69e6 MS |
5049 | spin_lock_irqsave(&hsotg->lock, flags); |
5050 | if (hsotg->enabled) | |
1f91b4cc FB |
5051 | dwc2_hsotg_core_disconnect(hsotg); |
5052 | dwc2_hsotg_disconnect(hsotg); | |
dc6e69e6 MS |
5053 | hsotg->gadget.speed = USB_SPEED_UNKNOWN; |
5054 | spin_unlock_irqrestore(&hsotg->lock, flags); | |
b83e333a | 5055 | |
c6f5c050 MYK |
5056 | for (ep = 0; ep < hsotg->num_of_eps; ep++) { |
5057 | if (hsotg->eps_in[ep]) | |
4fe4f9fe | 5058 | dwc2_hsotg_ep_disable_lock(&hsotg->eps_in[ep]->ep); |
c6f5c050 | 5059 | if (hsotg->eps_out[ep]) |
4fe4f9fe | 5060 | dwc2_hsotg_ep_disable_lock(&hsotg->eps_out[ep]->ep); |
c6f5c050 | 5061 | } |
b83e333a MS |
5062 | } |
5063 | ||
09a75e85 | 5064 | return 0; |
b83e333a MS |
5065 | } |
5066 | ||
1f91b4cc | 5067 | int dwc2_hsotg_resume(struct dwc2_hsotg *hsotg) |
b83e333a | 5068 | { |
b83e333a | 5069 | unsigned long flags; |
b83e333a | 5070 | |
9e779778 | 5071 | if (hsotg->lx_state == DWC2_L2) |
09a75e85 | 5072 | return 0; |
9e779778 | 5073 | |
b83e333a MS |
5074 | if (hsotg->driver) { |
5075 | dev_info(hsotg->dev, "resuming usb gadget %s\n", | |
5076 | hsotg->driver->driver.name); | |
d00b4142 | 5077 | |
dc6e69e6 | 5078 | spin_lock_irqsave(&hsotg->lock, flags); |
1f91b4cc | 5079 | dwc2_hsotg_core_init_disconnected(hsotg, false); |
66e77a24 RK |
5080 | if (hsotg->enabled) { |
5081 | /* Enable ACG feature in device mode,if supported */ | |
5082 | dwc2_enable_acg(hsotg); | |
1f91b4cc | 5083 | dwc2_hsotg_core_connect(hsotg); |
66e77a24 | 5084 | } |
dc6e69e6 MS |
5085 | spin_unlock_irqrestore(&hsotg->lock, flags); |
5086 | } | |
b83e333a | 5087 | |
09a75e85 | 5088 | return 0; |
b83e333a | 5089 | } |
58e52ff6 JY |
5090 | |
5091 | /** | |
5092 | * dwc2_backup_device_registers() - Backup controller device registers. | |
5093 | * When suspending usb bus, registers needs to be backuped | |
5094 | * if controller power is disabled once suspended. | |
5095 | * | |
5096 | * @hsotg: Programming view of the DWC_otg controller | |
5097 | */ | |
5098 | int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg) | |
5099 | { | |
5100 | struct dwc2_dregs_backup *dr; | |
5101 | int i; | |
5102 | ||
5103 | dev_dbg(hsotg->dev, "%s\n", __func__); | |
5104 | ||
5105 | /* Backup dev regs */ | |
5106 | dr = &hsotg->dr_backup; | |
5107 | ||
f25c42b8 GS |
5108 | dr->dcfg = dwc2_readl(hsotg, DCFG); |
5109 | dr->dctl = dwc2_readl(hsotg, DCTL); | |
5110 | dr->daintmsk = dwc2_readl(hsotg, DAINTMSK); | |
5111 | dr->diepmsk = dwc2_readl(hsotg, DIEPMSK); | |
5112 | dr->doepmsk = dwc2_readl(hsotg, DOEPMSK); | |
58e52ff6 JY |
5113 | |
5114 | for (i = 0; i < hsotg->num_of_eps; i++) { | |
5115 | /* Backup IN EPs */ | |
f25c42b8 | 5116 | dr->diepctl[i] = dwc2_readl(hsotg, DIEPCTL(i)); |
58e52ff6 JY |
5117 | |
5118 | /* Ensure DATA PID is correctly configured */ | |
5119 | if (dr->diepctl[i] & DXEPCTL_DPID) | |
5120 | dr->diepctl[i] |= DXEPCTL_SETD1PID; | |
5121 | else | |
5122 | dr->diepctl[i] |= DXEPCTL_SETD0PID; | |
5123 | ||
f25c42b8 GS |
5124 | dr->dieptsiz[i] = dwc2_readl(hsotg, DIEPTSIZ(i)); |
5125 | dr->diepdma[i] = dwc2_readl(hsotg, DIEPDMA(i)); | |
58e52ff6 JY |
5126 | |
5127 | /* Backup OUT EPs */ | |
f25c42b8 | 5128 | dr->doepctl[i] = dwc2_readl(hsotg, DOEPCTL(i)); |
58e52ff6 JY |
5129 | |
5130 | /* Ensure DATA PID is correctly configured */ | |
5131 | if (dr->doepctl[i] & DXEPCTL_DPID) | |
5132 | dr->doepctl[i] |= DXEPCTL_SETD1PID; | |
5133 | else | |
5134 | dr->doepctl[i] |= DXEPCTL_SETD0PID; | |
5135 | ||
f25c42b8 GS |
5136 | dr->doeptsiz[i] = dwc2_readl(hsotg, DOEPTSIZ(i)); |
5137 | dr->doepdma[i] = dwc2_readl(hsotg, DOEPDMA(i)); | |
5138 | dr->dtxfsiz[i] = dwc2_readl(hsotg, DPTXFSIZN(i)); | |
58e52ff6 JY |
5139 | } |
5140 | dr->valid = true; | |
5141 | return 0; | |
5142 | } | |
5143 | ||
5144 | /** | |
5145 | * dwc2_restore_device_registers() - Restore controller device registers. | |
5146 | * When resuming usb bus, device registers needs to be restored | |
5147 | * if controller power were disabled. | |
5148 | * | |
5149 | * @hsotg: Programming view of the DWC_otg controller | |
9a5d2816 VM |
5150 | * @remote_wakeup: Indicates whether resume is initiated by Device or Host. |
5151 | * | |
5152 | * Return: 0 if successful, negative error code otherwise | |
58e52ff6 | 5153 | */ |
9a5d2816 | 5154 | int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg, int remote_wakeup) |
58e52ff6 JY |
5155 | { |
5156 | struct dwc2_dregs_backup *dr; | |
58e52ff6 JY |
5157 | int i; |
5158 | ||
5159 | dev_dbg(hsotg->dev, "%s\n", __func__); | |
5160 | ||
5161 | /* Restore dev regs */ | |
5162 | dr = &hsotg->dr_backup; | |
5163 | if (!dr->valid) { | |
5164 | dev_err(hsotg->dev, "%s: no device registers to restore\n", | |
5165 | __func__); | |
5166 | return -EINVAL; | |
5167 | } | |
5168 | dr->valid = false; | |
5169 | ||
9a5d2816 | 5170 | if (!remote_wakeup) |
f25c42b8 | 5171 | dwc2_writel(hsotg, dr->dctl, DCTL); |
9a5d2816 | 5172 | |
f25c42b8 GS |
5173 | dwc2_writel(hsotg, dr->daintmsk, DAINTMSK); |
5174 | dwc2_writel(hsotg, dr->diepmsk, DIEPMSK); | |
5175 | dwc2_writel(hsotg, dr->doepmsk, DOEPMSK); | |
58e52ff6 JY |
5176 | |
5177 | for (i = 0; i < hsotg->num_of_eps; i++) { | |
5178 | /* Restore IN EPs */ | |
f25c42b8 GS |
5179 | dwc2_writel(hsotg, dr->dieptsiz[i], DIEPTSIZ(i)); |
5180 | dwc2_writel(hsotg, dr->diepdma[i], DIEPDMA(i)); | |
5181 | dwc2_writel(hsotg, dr->doeptsiz[i], DOEPTSIZ(i)); | |
9a5d2816 VM |
5182 | /** WA for enabled EPx's IN in DDMA mode. On entering to |
5183 | * hibernation wrong value read and saved from DIEPDMAx, | |
5184 | * as result BNA interrupt asserted on hibernation exit | |
5185 | * by restoring from saved area. | |
5186 | */ | |
5187 | if (hsotg->params.g_dma_desc && | |
5188 | (dr->diepctl[i] & DXEPCTL_EPENA)) | |
5189 | dr->diepdma[i] = hsotg->eps_in[i]->desc_list_dma; | |
f25c42b8 GS |
5190 | dwc2_writel(hsotg, dr->dtxfsiz[i], DPTXFSIZN(i)); |
5191 | dwc2_writel(hsotg, dr->diepctl[i], DIEPCTL(i)); | |
58e52ff6 | 5192 | /* Restore OUT EPs */ |
f25c42b8 | 5193 | dwc2_writel(hsotg, dr->doeptsiz[i], DOEPTSIZ(i)); |
9a5d2816 VM |
5194 | /* WA for enabled EPx's OUT in DDMA mode. On entering to |
5195 | * hibernation wrong value read and saved from DOEPDMAx, | |
5196 | * as result BNA interrupt asserted on hibernation exit | |
5197 | * by restoring from saved area. | |
5198 | */ | |
5199 | if (hsotg->params.g_dma_desc && | |
5200 | (dr->doepctl[i] & DXEPCTL_EPENA)) | |
5201 | dr->doepdma[i] = hsotg->eps_out[i]->desc_list_dma; | |
f25c42b8 GS |
5202 | dwc2_writel(hsotg, dr->doepdma[i], DOEPDMA(i)); |
5203 | dwc2_writel(hsotg, dr->doepctl[i], DOEPCTL(i)); | |
58e52ff6 JY |
5204 | } |
5205 | ||
58e52ff6 JY |
5206 | return 0; |
5207 | } | |
21b03405 SA |
5208 | |
5209 | /** | |
5210 | * dwc2_gadget_init_lpm - Configure the core to support LPM in device mode | |
5211 | * | |
5212 | * @hsotg: Programming view of DWC_otg controller | |
5213 | * | |
5214 | */ | |
5215 | void dwc2_gadget_init_lpm(struct dwc2_hsotg *hsotg) | |
5216 | { | |
5217 | u32 val; | |
5218 | ||
5219 | if (!hsotg->params.lpm) | |
5220 | return; | |
5221 | ||
5222 | val = GLPMCFG_LPMCAP | GLPMCFG_APPL1RES; | |
5223 | val |= hsotg->params.hird_threshold_en ? GLPMCFG_HIRD_THRES_EN : 0; | |
5224 | val |= hsotg->params.lpm_clock_gating ? GLPMCFG_ENBLSLPM : 0; | |
5225 | val |= hsotg->params.hird_threshold << GLPMCFG_HIRD_THRES_SHIFT; | |
5226 | val |= hsotg->params.besl ? GLPMCFG_ENBESL : 0; | |
46637565 | 5227 | val |= GLPMCFG_LPM_REJECT_CTRL_CONTROL; |
9aed8c08 | 5228 | val |= GLPMCFG_LPM_ACCEPT_CTRL_ISOC; |
f25c42b8 GS |
5229 | dwc2_writel(hsotg, val, GLPMCFG); |
5230 | dev_dbg(hsotg->dev, "GLPMCFG=0x%08x\n", dwc2_readl(hsotg, GLPMCFG)); | |
4abe4537 GT |
5231 | |
5232 | /* Unmask WKUP_ALERT Interrupt */ | |
5233 | if (hsotg->params.service_interval) | |
5234 | dwc2_set_bit(hsotg, GINTMSK2, GINTMSK2_WKUP_ALERT_INT_MSK); | |
21b03405 | 5235 | } |
c5c403dc | 5236 | |
15d9dbf8 GT |
5237 | /** |
5238 | * dwc2_gadget_program_ref_clk - Program GREFCLK register in device mode | |
5239 | * | |
5240 | * @hsotg: Programming view of DWC_otg controller | |
5241 | * | |
5242 | */ | |
5243 | void dwc2_gadget_program_ref_clk(struct dwc2_hsotg *hsotg) | |
5244 | { | |
5245 | u32 val = 0; | |
5246 | ||
5247 | val |= GREFCLK_REF_CLK_MODE; | |
5248 | val |= hsotg->params.ref_clk_per << GREFCLK_REFCLKPER_SHIFT; | |
5249 | val |= hsotg->params.sof_cnt_wkup_alert << | |
5250 | GREFCLK_SOF_CNT_WKUP_ALERT_SHIFT; | |
5251 | ||
5252 | dwc2_writel(hsotg, val, GREFCLK); | |
5253 | dev_dbg(hsotg->dev, "GREFCLK=0x%08x\n", dwc2_readl(hsotg, GREFCLK)); | |
5254 | } | |
5255 | ||
c5c403dc VM |
5256 | /** |
5257 | * dwc2_gadget_enter_hibernation() - Put controller in Hibernation. | |
5258 | * | |
5259 | * @hsotg: Programming view of the DWC_otg controller | |
5260 | * | |
5261 | * Return non-zero if failed to enter to hibernation. | |
5262 | */ | |
5263 | int dwc2_gadget_enter_hibernation(struct dwc2_hsotg *hsotg) | |
5264 | { | |
5265 | u32 gpwrdn; | |
5266 | int ret = 0; | |
5267 | ||
5268 | /* Change to L2(suspend) state */ | |
5269 | hsotg->lx_state = DWC2_L2; | |
5270 | dev_dbg(hsotg->dev, "Start of hibernation completed\n"); | |
5271 | ret = dwc2_backup_global_registers(hsotg); | |
5272 | if (ret) { | |
5273 | dev_err(hsotg->dev, "%s: failed to backup global registers\n", | |
5274 | __func__); | |
5275 | return ret; | |
5276 | } | |
5277 | ret = dwc2_backup_device_registers(hsotg); | |
5278 | if (ret) { | |
5279 | dev_err(hsotg->dev, "%s: failed to backup device registers\n", | |
5280 | __func__); | |
5281 | return ret; | |
5282 | } | |
5283 | ||
5284 | gpwrdn = GPWRDN_PWRDNRSTN; | |
5285 | gpwrdn |= GPWRDN_PMUACTV; | |
f25c42b8 | 5286 | dwc2_writel(hsotg, gpwrdn, GPWRDN); |
c5c403dc VM |
5287 | udelay(10); |
5288 | ||
5289 | /* Set flag to indicate that we are in hibernation */ | |
5290 | hsotg->hibernated = 1; | |
5291 | ||
5292 | /* Enable interrupts from wake up logic */ | |
f25c42b8 | 5293 | gpwrdn = dwc2_readl(hsotg, GPWRDN); |
c5c403dc | 5294 | gpwrdn |= GPWRDN_PMUINTSEL; |
f25c42b8 | 5295 | dwc2_writel(hsotg, gpwrdn, GPWRDN); |
c5c403dc VM |
5296 | udelay(10); |
5297 | ||
5298 | /* Unmask device mode interrupts in GPWRDN */ | |
f25c42b8 | 5299 | gpwrdn = dwc2_readl(hsotg, GPWRDN); |
c5c403dc VM |
5300 | gpwrdn |= GPWRDN_RST_DET_MSK; |
5301 | gpwrdn |= GPWRDN_LNSTSCHG_MSK; | |
5302 | gpwrdn |= GPWRDN_STS_CHGINT_MSK; | |
f25c42b8 | 5303 | dwc2_writel(hsotg, gpwrdn, GPWRDN); |
c5c403dc VM |
5304 | udelay(10); |
5305 | ||
5306 | /* Enable Power Down Clamp */ | |
f25c42b8 | 5307 | gpwrdn = dwc2_readl(hsotg, GPWRDN); |
c5c403dc | 5308 | gpwrdn |= GPWRDN_PWRDNCLMP; |
f25c42b8 | 5309 | dwc2_writel(hsotg, gpwrdn, GPWRDN); |
c5c403dc VM |
5310 | udelay(10); |
5311 | ||
5312 | /* Switch off VDD */ | |
f25c42b8 | 5313 | gpwrdn = dwc2_readl(hsotg, GPWRDN); |
c5c403dc | 5314 | gpwrdn |= GPWRDN_PWRDNSWTCH; |
f25c42b8 | 5315 | dwc2_writel(hsotg, gpwrdn, GPWRDN); |
c5c403dc VM |
5316 | udelay(10); |
5317 | ||
5318 | /* Save gpwrdn register for further usage if stschng interrupt */ | |
f25c42b8 | 5319 | hsotg->gr_backup.gpwrdn = dwc2_readl(hsotg, GPWRDN); |
c5c403dc VM |
5320 | dev_dbg(hsotg->dev, "Hibernation completed\n"); |
5321 | ||
5322 | return ret; | |
5323 | } | |
5324 | ||
5325 | /** | |
5326 | * dwc2_gadget_exit_hibernation() | |
5327 | * This function is for exiting from Device mode hibernation by host initiated | |
5328 | * resume/reset and device initiated remote-wakeup. | |
5329 | * | |
5330 | * @hsotg: Programming view of the DWC_otg controller | |
5331 | * @rem_wakeup: indicates whether resume is initiated by Device or Host. | |
6fb914d7 | 5332 | * @reset: indicates whether resume is initiated by Reset. |
c5c403dc VM |
5333 | * |
5334 | * Return non-zero if failed to exit from hibernation. | |
5335 | */ | |
5336 | int dwc2_gadget_exit_hibernation(struct dwc2_hsotg *hsotg, | |
5337 | int rem_wakeup, int reset) | |
5338 | { | |
5339 | u32 pcgcctl; | |
5340 | u32 gpwrdn; | |
5341 | u32 dctl; | |
5342 | int ret = 0; | |
5343 | struct dwc2_gregs_backup *gr; | |
5344 | struct dwc2_dregs_backup *dr; | |
5345 | ||
5346 | gr = &hsotg->gr_backup; | |
5347 | dr = &hsotg->dr_backup; | |
5348 | ||
5349 | if (!hsotg->hibernated) { | |
5350 | dev_dbg(hsotg->dev, "Already exited from Hibernation\n"); | |
5351 | return 1; | |
5352 | } | |
5353 | dev_dbg(hsotg->dev, | |
5354 | "%s: called with rem_wakeup = %d reset = %d\n", | |
5355 | __func__, rem_wakeup, reset); | |
5356 | ||
5357 | dwc2_hib_restore_common(hsotg, rem_wakeup, 0); | |
5358 | ||
5359 | if (!reset) { | |
5360 | /* Clear all pending interupts */ | |
f25c42b8 | 5361 | dwc2_writel(hsotg, 0xffffffff, GINTSTS); |
c5c403dc VM |
5362 | } |
5363 | ||
5364 | /* De-assert Restore */ | |
f25c42b8 | 5365 | gpwrdn = dwc2_readl(hsotg, GPWRDN); |
c5c403dc | 5366 | gpwrdn &= ~GPWRDN_RESTORE; |
f25c42b8 | 5367 | dwc2_writel(hsotg, gpwrdn, GPWRDN); |
c5c403dc VM |
5368 | udelay(10); |
5369 | ||
5370 | if (!rem_wakeup) { | |
f25c42b8 | 5371 | pcgcctl = dwc2_readl(hsotg, PCGCTL); |
c5c403dc | 5372 | pcgcctl &= ~PCGCTL_RSTPDWNMODULE; |
f25c42b8 | 5373 | dwc2_writel(hsotg, pcgcctl, PCGCTL); |
c5c403dc VM |
5374 | } |
5375 | ||
5376 | /* Restore GUSBCFG, DCFG and DCTL */ | |
f25c42b8 GS |
5377 | dwc2_writel(hsotg, gr->gusbcfg, GUSBCFG); |
5378 | dwc2_writel(hsotg, dr->dcfg, DCFG); | |
5379 | dwc2_writel(hsotg, dr->dctl, DCTL); | |
c5c403dc | 5380 | |
b29b494b AP |
5381 | /* On USB Reset, reset device address to zero */ |
5382 | if (reset) | |
5383 | dwc2_clear_bit(hsotg, DCFG, DCFG_DEVADDR_MASK); | |
5384 | ||
c5c403dc | 5385 | /* De-assert Wakeup Logic */ |
f25c42b8 | 5386 | gpwrdn = dwc2_readl(hsotg, GPWRDN); |
c5c403dc | 5387 | gpwrdn &= ~GPWRDN_PMUACTV; |
f25c42b8 | 5388 | dwc2_writel(hsotg, gpwrdn, GPWRDN); |
c5c403dc VM |
5389 | |
5390 | if (rem_wakeup) { | |
5391 | udelay(10); | |
5392 | /* Start Remote Wakeup Signaling */ | |
f25c42b8 | 5393 | dwc2_writel(hsotg, dr->dctl | DCTL_RMTWKUPSIG, DCTL); |
c5c403dc VM |
5394 | } else { |
5395 | udelay(50); | |
5396 | /* Set Device programming done bit */ | |
f25c42b8 | 5397 | dctl = dwc2_readl(hsotg, DCTL); |
c5c403dc | 5398 | dctl |= DCTL_PWRONPRGDONE; |
f25c42b8 | 5399 | dwc2_writel(hsotg, dctl, DCTL); |
c5c403dc VM |
5400 | } |
5401 | /* Wait for interrupts which must be cleared */ | |
5402 | mdelay(2); | |
5403 | /* Clear all pending interupts */ | |
f25c42b8 | 5404 | dwc2_writel(hsotg, 0xffffffff, GINTSTS); |
c5c403dc VM |
5405 | |
5406 | /* Restore global registers */ | |
5407 | ret = dwc2_restore_global_registers(hsotg); | |
5408 | if (ret) { | |
5409 | dev_err(hsotg->dev, "%s: failed to restore registers\n", | |
5410 | __func__); | |
5411 | return ret; | |
5412 | } | |
5413 | ||
5414 | /* Restore device registers */ | |
5415 | ret = dwc2_restore_device_registers(hsotg, rem_wakeup); | |
5416 | if (ret) { | |
5417 | dev_err(hsotg->dev, "%s: failed to restore device registers\n", | |
5418 | __func__); | |
5419 | return ret; | |
5420 | } | |
5421 | ||
5422 | if (rem_wakeup) { | |
5423 | mdelay(10); | |
f25c42b8 | 5424 | dctl = dwc2_readl(hsotg, DCTL); |
c5c403dc | 5425 | dctl &= ~DCTL_RMTWKUPSIG; |
f25c42b8 | 5426 | dwc2_writel(hsotg, dctl, DCTL); |
c5c403dc VM |
5427 | } |
5428 | ||
5429 | hsotg->hibernated = 0; | |
5430 | hsotg->lx_state = DWC2_L0; | |
5431 | dev_dbg(hsotg->dev, "Hibernation recovery completes here\n"); | |
5432 | ||
5433 | return ret; | |
5434 | } | |
be2b960e AP |
5435 | |
5436 | /** | |
5437 | * dwc2_gadget_enter_partial_power_down() - Put controller in partial | |
5438 | * power down. | |
5439 | * | |
5440 | * @hsotg: Programming view of the DWC_otg controller | |
5441 | * | |
5442 | * Return: non-zero if failed to enter device partial power down. | |
5443 | * | |
5444 | * This function is for entering device mode partial power down. | |
5445 | */ | |
5446 | int dwc2_gadget_enter_partial_power_down(struct dwc2_hsotg *hsotg) | |
5447 | { | |
5448 | u32 pcgcctl; | |
5449 | int ret = 0; | |
5450 | ||
5451 | dev_dbg(hsotg->dev, "Entering device partial power down started.\n"); | |
5452 | ||
5453 | /* Backup all registers */ | |
5454 | ret = dwc2_backup_global_registers(hsotg); | |
5455 | if (ret) { | |
5456 | dev_err(hsotg->dev, "%s: failed to backup global registers\n", | |
5457 | __func__); | |
5458 | return ret; | |
5459 | } | |
5460 | ||
5461 | ret = dwc2_backup_device_registers(hsotg); | |
5462 | if (ret) { | |
5463 | dev_err(hsotg->dev, "%s: failed to backup device registers\n", | |
5464 | __func__); | |
5465 | return ret; | |
5466 | } | |
5467 | ||
5468 | /* | |
5469 | * Clear any pending interrupts since dwc2 will not be able to | |
5470 | * clear them after entering partial_power_down. | |
5471 | */ | |
5472 | dwc2_writel(hsotg, 0xffffffff, GINTSTS); | |
5473 | ||
5474 | /* Put the controller in low power state */ | |
5475 | pcgcctl = dwc2_readl(hsotg, PCGCTL); | |
5476 | ||
5477 | pcgcctl |= PCGCTL_PWRCLMP; | |
5478 | dwc2_writel(hsotg, pcgcctl, PCGCTL); | |
5479 | udelay(5); | |
5480 | ||
5481 | pcgcctl |= PCGCTL_RSTPDWNMODULE; | |
5482 | dwc2_writel(hsotg, pcgcctl, PCGCTL); | |
5483 | udelay(5); | |
5484 | ||
5485 | pcgcctl |= PCGCTL_STOPPCLK; | |
5486 | dwc2_writel(hsotg, pcgcctl, PCGCTL); | |
5487 | ||
5488 | /* Set in_ppd flag to 1 as here core enters suspend. */ | |
5489 | hsotg->in_ppd = 1; | |
5490 | hsotg->lx_state = DWC2_L2; | |
5491 | ||
5492 | dev_dbg(hsotg->dev, "Entering device partial power down completed.\n"); | |
5493 | ||
5494 | return ret; | |
5495 | } | |
5496 | ||
5497 | /* | |
5498 | * dwc2_gadget_exit_partial_power_down() - Exit controller from device partial | |
5499 | * power down. | |
5500 | * | |
5501 | * @hsotg: Programming view of the DWC_otg controller | |
5502 | * @restore: indicates whether need to restore the registers or not. | |
5503 | * | |
5504 | * Return: non-zero if failed to exit device partial power down. | |
5505 | * | |
5506 | * This function is for exiting from device mode partial power down. | |
5507 | */ | |
5508 | int dwc2_gadget_exit_partial_power_down(struct dwc2_hsotg *hsotg, | |
5509 | bool restore) | |
5510 | { | |
5511 | u32 pcgcctl; | |
5512 | u32 dctl; | |
5513 | struct dwc2_dregs_backup *dr; | |
5514 | int ret = 0; | |
5515 | ||
5516 | dr = &hsotg->dr_backup; | |
5517 | ||
5518 | dev_dbg(hsotg->dev, "Exiting device partial Power Down started.\n"); | |
5519 | ||
5520 | pcgcctl = dwc2_readl(hsotg, PCGCTL); | |
5521 | pcgcctl &= ~PCGCTL_STOPPCLK; | |
5522 | dwc2_writel(hsotg, pcgcctl, PCGCTL); | |
5523 | ||
5524 | pcgcctl = dwc2_readl(hsotg, PCGCTL); | |
5525 | pcgcctl &= ~PCGCTL_PWRCLMP; | |
5526 | dwc2_writel(hsotg, pcgcctl, PCGCTL); | |
5527 | ||
5528 | pcgcctl = dwc2_readl(hsotg, PCGCTL); | |
5529 | pcgcctl &= ~PCGCTL_RSTPDWNMODULE; | |
5530 | dwc2_writel(hsotg, pcgcctl, PCGCTL); | |
5531 | ||
5532 | udelay(100); | |
5533 | if (restore) { | |
5534 | ret = dwc2_restore_global_registers(hsotg); | |
5535 | if (ret) { | |
5536 | dev_err(hsotg->dev, "%s: failed to restore registers\n", | |
5537 | __func__); | |
5538 | return ret; | |
5539 | } | |
5540 | /* Restore DCFG */ | |
5541 | dwc2_writel(hsotg, dr->dcfg, DCFG); | |
5542 | ||
5543 | ret = dwc2_restore_device_registers(hsotg, 0); | |
5544 | if (ret) { | |
5545 | dev_err(hsotg->dev, "%s: failed to restore device registers\n", | |
5546 | __func__); | |
5547 | return ret; | |
5548 | } | |
5549 | } | |
5550 | ||
5551 | /* Set the Power-On Programming done bit */ | |
5552 | dctl = dwc2_readl(hsotg, DCTL); | |
5553 | dctl |= DCTL_PWRONPRGDONE; | |
5554 | dwc2_writel(hsotg, dctl, DCTL); | |
5555 | ||
5556 | /* Set in_ppd flag to 0 as here core exits from suspend. */ | |
5557 | hsotg->in_ppd = 0; | |
5558 | hsotg->lx_state = DWC2_L0; | |
5559 | ||
5560 | dev_dbg(hsotg->dev, "Exiting device partial Power Down completed.\n"); | |
5561 | return ret; | |
5562 | } | |
012466fc AP |
5563 | |
5564 | /** | |
5565 | * dwc2_gadget_enter_clock_gating() - Put controller in clock gating. | |
5566 | * | |
5567 | * @hsotg: Programming view of the DWC_otg controller | |
5568 | * | |
5569 | * Return: non-zero if failed to enter device partial power down. | |
5570 | * | |
5571 | * This function is for entering device mode clock gating. | |
5572 | */ | |
5573 | void dwc2_gadget_enter_clock_gating(struct dwc2_hsotg *hsotg) | |
5574 | { | |
5575 | u32 pcgctl; | |
5576 | ||
5577 | dev_dbg(hsotg->dev, "Entering device clock gating.\n"); | |
5578 | ||
5579 | /* Set the Phy Clock bit as suspend is received. */ | |
5580 | pcgctl = dwc2_readl(hsotg, PCGCTL); | |
5581 | pcgctl |= PCGCTL_STOPPCLK; | |
5582 | dwc2_writel(hsotg, pcgctl, PCGCTL); | |
5583 | udelay(5); | |
5584 | ||
5585 | /* Set the Gate hclk as suspend is received. */ | |
5586 | pcgctl = dwc2_readl(hsotg, PCGCTL); | |
5587 | pcgctl |= PCGCTL_GATEHCLK; | |
5588 | dwc2_writel(hsotg, pcgctl, PCGCTL); | |
5589 | udelay(5); | |
5590 | ||
5591 | hsotg->lx_state = DWC2_L2; | |
5592 | hsotg->bus_suspended = true; | |
5593 | } | |
5594 | ||
5595 | /* | |
5596 | * dwc2_gadget_exit_clock_gating() - Exit controller from device clock gating. | |
5597 | * | |
5598 | * @hsotg: Programming view of the DWC_otg controller | |
5599 | * @rem_wakeup: indicates whether remote wake up is enabled. | |
5600 | * | |
5601 | * This function is for exiting from device mode clock gating. | |
5602 | */ | |
5603 | void dwc2_gadget_exit_clock_gating(struct dwc2_hsotg *hsotg, int rem_wakeup) | |
5604 | { | |
5605 | u32 pcgctl; | |
5606 | u32 dctl; | |
5607 | ||
5608 | dev_dbg(hsotg->dev, "Exiting device clock gating.\n"); | |
5609 | ||
5610 | /* Clear the Gate hclk. */ | |
5611 | pcgctl = dwc2_readl(hsotg, PCGCTL); | |
5612 | pcgctl &= ~PCGCTL_GATEHCLK; | |
5613 | dwc2_writel(hsotg, pcgctl, PCGCTL); | |
5614 | udelay(5); | |
5615 | ||
5616 | /* Phy Clock bit. */ | |
5617 | pcgctl = dwc2_readl(hsotg, PCGCTL); | |
5618 | pcgctl &= ~PCGCTL_STOPPCLK; | |
5619 | dwc2_writel(hsotg, pcgctl, PCGCTL); | |
5620 | udelay(5); | |
5621 | ||
5622 | if (rem_wakeup) { | |
5623 | /* Set Remote Wakeup Signaling */ | |
5624 | dctl = dwc2_readl(hsotg, DCTL); | |
5625 | dctl |= DCTL_RMTWKUPSIG; | |
5626 | dwc2_writel(hsotg, dctl, DCTL); | |
5627 | } | |
5628 | ||
5629 | /* Change to L0 state */ | |
5630 | call_gadget(hsotg, resume); | |
5631 | hsotg->lx_state = DWC2_L0; | |
5632 | hsotg->bus_suspended = false; | |
5633 | } |