Commit | Line | Data |
---|---|---|
8b9bc460 | 1 | /** |
dfbc6fa3 AT |
2 | * Copyright (c) 2011 Samsung Electronics Co., Ltd. |
3 | * http://www.samsung.com | |
5b7d70c6 BD |
4 | * |
5 | * Copyright 2008 Openmoko, Inc. | |
6 | * Copyright 2008 Simtec Electronics | |
7 | * Ben Dooks <ben@simtec.co.uk> | |
8 | * http://armlinux.simtec.co.uk/ | |
9 | * | |
10 | * S3C USB2.0 High-speed / OtG driver | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License version 2 as | |
14 | * published by the Free Software Foundation. | |
8b9bc460 | 15 | */ |
5b7d70c6 BD |
16 | |
17 | #include <linux/kernel.h> | |
18 | #include <linux/module.h> | |
19 | #include <linux/spinlock.h> | |
20 | #include <linux/interrupt.h> | |
21 | #include <linux/platform_device.h> | |
22 | #include <linux/dma-mapping.h> | |
23 | #include <linux/debugfs.h> | |
7ad8096e | 24 | #include <linux/mutex.h> |
5b7d70c6 BD |
25 | #include <linux/seq_file.h> |
26 | #include <linux/delay.h> | |
27 | #include <linux/io.h> | |
5a0e3ad6 | 28 | #include <linux/slab.h> |
e50bf385 | 29 | #include <linux/clk.h> |
fc9a731e | 30 | #include <linux/regulator/consumer.h> |
c50f056c | 31 | #include <linux/of_platform.h> |
74084844 | 32 | #include <linux/phy/phy.h> |
5b7d70c6 BD |
33 | |
34 | #include <linux/usb/ch9.h> | |
35 | #include <linux/usb/gadget.h> | |
b2e587db | 36 | #include <linux/usb/phy.h> |
126625e1 | 37 | #include <linux/platform_data/s3c-hsotg.h> |
5b7d70c6 | 38 | |
f7c0b143 | 39 | #include "core.h" |
941fcce4 | 40 | #include "hw.h" |
5b7d70c6 BD |
41 | |
42 | /* conversion functions */ | |
43 | static inline struct s3c_hsotg_req *our_req(struct usb_request *req) | |
44 | { | |
45 | return container_of(req, struct s3c_hsotg_req, req); | |
46 | } | |
47 | ||
48 | static inline struct s3c_hsotg_ep *our_ep(struct usb_ep *ep) | |
49 | { | |
50 | return container_of(ep, struct s3c_hsotg_ep, ep); | |
51 | } | |
52 | ||
941fcce4 | 53 | static inline struct dwc2_hsotg *to_hsotg(struct usb_gadget *gadget) |
5b7d70c6 | 54 | { |
941fcce4 | 55 | return container_of(gadget, struct dwc2_hsotg, gadget); |
5b7d70c6 BD |
56 | } |
57 | ||
58 | static inline void __orr32(void __iomem *ptr, u32 val) | |
59 | { | |
60 | writel(readl(ptr) | val, ptr); | |
61 | } | |
62 | ||
63 | static inline void __bic32(void __iomem *ptr, u32 val) | |
64 | { | |
65 | writel(readl(ptr) & ~val, ptr); | |
66 | } | |
67 | ||
c6f5c050 MYK |
68 | static inline struct s3c_hsotg_ep *index_to_ep(struct dwc2_hsotg *hsotg, |
69 | u32 ep_index, u32 dir_in) | |
70 | { | |
71 | if (dir_in) | |
72 | return hsotg->eps_in[ep_index]; | |
73 | else | |
74 | return hsotg->eps_out[ep_index]; | |
75 | } | |
76 | ||
997f4f81 | 77 | /* forward declaration of functions */ |
941fcce4 | 78 | static void s3c_hsotg_dump(struct dwc2_hsotg *hsotg); |
5b7d70c6 BD |
79 | |
80 | /** | |
81 | * using_dma - return the DMA status of the driver. | |
82 | * @hsotg: The driver state. | |
83 | * | |
84 | * Return true if we're using DMA. | |
85 | * | |
86 | * Currently, we have the DMA support code worked into everywhere | |
87 | * that needs it, but the AMBA DMA implementation in the hardware can | |
88 | * only DMA from 32bit aligned addresses. This means that gadgets such | |
89 | * as the CDC Ethernet cannot work as they often pass packets which are | |
90 | * not 32bit aligned. | |
91 | * | |
92 | * Unfortunately the choice to use DMA or not is global to the controller | |
93 | * and seems to be only settable when the controller is being put through | |
94 | * a core reset. This means we either need to fix the gadgets to take | |
95 | * account of DMA alignment, or add bounce buffers (yuerk). | |
96 | * | |
edd74be8 | 97 | * g_using_dma is set depending on dts flag. |
5b7d70c6 | 98 | */ |
941fcce4 | 99 | static inline bool using_dma(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 100 | { |
edd74be8 | 101 | return hsotg->g_using_dma; |
5b7d70c6 BD |
102 | } |
103 | ||
104 | /** | |
105 | * s3c_hsotg_en_gsint - enable one or more of the general interrupt | |
106 | * @hsotg: The device state | |
107 | * @ints: A bitmask of the interrupts to enable | |
108 | */ | |
941fcce4 | 109 | static void s3c_hsotg_en_gsint(struct dwc2_hsotg *hsotg, u32 ints) |
5b7d70c6 | 110 | { |
94cb8fd6 | 111 | u32 gsintmsk = readl(hsotg->regs + GINTMSK); |
5b7d70c6 BD |
112 | u32 new_gsintmsk; |
113 | ||
114 | new_gsintmsk = gsintmsk | ints; | |
115 | ||
116 | if (new_gsintmsk != gsintmsk) { | |
117 | dev_dbg(hsotg->dev, "gsintmsk now 0x%08x\n", new_gsintmsk); | |
94cb8fd6 | 118 | writel(new_gsintmsk, hsotg->regs + GINTMSK); |
5b7d70c6 BD |
119 | } |
120 | } | |
121 | ||
122 | /** | |
123 | * s3c_hsotg_disable_gsint - disable one or more of the general interrupt | |
124 | * @hsotg: The device state | |
125 | * @ints: A bitmask of the interrupts to enable | |
126 | */ | |
941fcce4 | 127 | static void s3c_hsotg_disable_gsint(struct dwc2_hsotg *hsotg, u32 ints) |
5b7d70c6 | 128 | { |
94cb8fd6 | 129 | u32 gsintmsk = readl(hsotg->regs + GINTMSK); |
5b7d70c6 BD |
130 | u32 new_gsintmsk; |
131 | ||
132 | new_gsintmsk = gsintmsk & ~ints; | |
133 | ||
134 | if (new_gsintmsk != gsintmsk) | |
94cb8fd6 | 135 | writel(new_gsintmsk, hsotg->regs + GINTMSK); |
5b7d70c6 BD |
136 | } |
137 | ||
138 | /** | |
139 | * s3c_hsotg_ctrl_epint - enable/disable an endpoint irq | |
140 | * @hsotg: The device state | |
141 | * @ep: The endpoint index | |
142 | * @dir_in: True if direction is in. | |
143 | * @en: The enable value, true to enable | |
144 | * | |
145 | * Set or clear the mask for an individual endpoint's interrupt | |
146 | * request. | |
147 | */ | |
941fcce4 | 148 | static void s3c_hsotg_ctrl_epint(struct dwc2_hsotg *hsotg, |
5b7d70c6 BD |
149 | unsigned int ep, unsigned int dir_in, |
150 | unsigned int en) | |
151 | { | |
152 | unsigned long flags; | |
153 | u32 bit = 1 << ep; | |
154 | u32 daint; | |
155 | ||
156 | if (!dir_in) | |
157 | bit <<= 16; | |
158 | ||
159 | local_irq_save(flags); | |
94cb8fd6 | 160 | daint = readl(hsotg->regs + DAINTMSK); |
5b7d70c6 BD |
161 | if (en) |
162 | daint |= bit; | |
163 | else | |
164 | daint &= ~bit; | |
94cb8fd6 | 165 | writel(daint, hsotg->regs + DAINTMSK); |
5b7d70c6 BD |
166 | local_irq_restore(flags); |
167 | } | |
168 | ||
169 | /** | |
170 | * s3c_hsotg_init_fifo - initialise non-periodic FIFOs | |
171 | * @hsotg: The device instance. | |
172 | */ | |
941fcce4 | 173 | static void s3c_hsotg_init_fifo(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 174 | { |
0f002d20 BD |
175 | unsigned int ep; |
176 | unsigned int addr; | |
1703a6d3 | 177 | int timeout; |
0f002d20 BD |
178 | u32 val; |
179 | ||
0a176279 GH |
180 | /* set RX/NPTX FIFO sizes */ |
181 | writel(hsotg->g_rx_fifo_sz, hsotg->regs + GRXFSIZ); | |
182 | writel((hsotg->g_rx_fifo_sz << FIFOSIZE_STARTADDR_SHIFT) | | |
183 | (hsotg->g_np_g_tx_fifo_sz << FIFOSIZE_DEPTH_SHIFT), | |
184 | hsotg->regs + GNPTXFSIZ); | |
0f002d20 | 185 | |
8b9bc460 LM |
186 | /* |
187 | * arange all the rest of the TX FIFOs, as some versions of this | |
0f002d20 BD |
188 | * block have overlapping default addresses. This also ensures |
189 | * that if the settings have been changed, then they are set to | |
8b9bc460 LM |
190 | * known values. |
191 | */ | |
0f002d20 BD |
192 | |
193 | /* start at the end of the GNPTXFSIZ, rounded up */ | |
0a176279 | 194 | addr = hsotg->g_rx_fifo_sz + hsotg->g_np_g_tx_fifo_sz; |
0f002d20 | 195 | |
8b9bc460 | 196 | /* |
0a176279 | 197 | * Configure fifos sizes from provided configuration and assign |
b203d0a2 RB |
198 | * them to endpoints dynamically according to maxpacket size value of |
199 | * given endpoint. | |
8b9bc460 | 200 | */ |
0a176279 GH |
201 | for (ep = 1; ep < MAX_EPS_CHANNELS; ep++) { |
202 | if (!hsotg->g_tx_fifo_sz[ep]) | |
203 | continue; | |
0f002d20 | 204 | val = addr; |
0a176279 GH |
205 | val |= hsotg->g_tx_fifo_sz[ep] << FIFOSIZE_DEPTH_SHIFT; |
206 | WARN_ONCE(addr + hsotg->g_tx_fifo_sz[ep] > hsotg->fifo_mem, | |
cff9eb75 | 207 | "insufficient fifo memory"); |
0a176279 | 208 | addr += hsotg->g_tx_fifo_sz[ep]; |
0f002d20 | 209 | |
47a1685f | 210 | writel(val, hsotg->regs + DPTXFSIZN(ep)); |
0f002d20 | 211 | } |
1703a6d3 | 212 | |
8b9bc460 LM |
213 | /* |
214 | * according to p428 of the design guide, we need to ensure that | |
215 | * all fifos are flushed before continuing | |
216 | */ | |
1703a6d3 | 217 | |
47a1685f DN |
218 | writel(GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH | |
219 | GRSTCTL_RXFFLSH, hsotg->regs + GRSTCTL); | |
1703a6d3 BD |
220 | |
221 | /* wait until the fifos are both flushed */ | |
222 | timeout = 100; | |
223 | while (1) { | |
94cb8fd6 | 224 | val = readl(hsotg->regs + GRSTCTL); |
1703a6d3 | 225 | |
47a1685f | 226 | if ((val & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH)) == 0) |
1703a6d3 BD |
227 | break; |
228 | ||
229 | if (--timeout == 0) { | |
230 | dev_err(hsotg->dev, | |
231 | "%s: timeout flushing fifos (GRSTCTL=%08x)\n", | |
232 | __func__, val); | |
48b20bcb | 233 | break; |
1703a6d3 BD |
234 | } |
235 | ||
236 | udelay(1); | |
237 | } | |
238 | ||
239 | dev_dbg(hsotg->dev, "FIFOs reset, timeout at %d\n", timeout); | |
5b7d70c6 BD |
240 | } |
241 | ||
242 | /** | |
243 | * @ep: USB endpoint to allocate request for. | |
244 | * @flags: Allocation flags | |
245 | * | |
246 | * Allocate a new USB request structure appropriate for the specified endpoint | |
247 | */ | |
0978f8c5 MB |
248 | static struct usb_request *s3c_hsotg_ep_alloc_request(struct usb_ep *ep, |
249 | gfp_t flags) | |
5b7d70c6 BD |
250 | { |
251 | struct s3c_hsotg_req *req; | |
252 | ||
253 | req = kzalloc(sizeof(struct s3c_hsotg_req), flags); | |
254 | if (!req) | |
255 | return NULL; | |
256 | ||
257 | INIT_LIST_HEAD(&req->queue); | |
258 | ||
5b7d70c6 BD |
259 | return &req->req; |
260 | } | |
261 | ||
262 | /** | |
263 | * is_ep_periodic - return true if the endpoint is in periodic mode. | |
264 | * @hs_ep: The endpoint to query. | |
265 | * | |
266 | * Returns true if the endpoint is in periodic mode, meaning it is being | |
267 | * used for an Interrupt or ISO transfer. | |
268 | */ | |
269 | static inline int is_ep_periodic(struct s3c_hsotg_ep *hs_ep) | |
270 | { | |
271 | return hs_ep->periodic; | |
272 | } | |
273 | ||
274 | /** | |
275 | * s3c_hsotg_unmap_dma - unmap the DMA memory being used for the request | |
276 | * @hsotg: The device state. | |
277 | * @hs_ep: The endpoint for the request | |
278 | * @hs_req: The request being processed. | |
279 | * | |
280 | * This is the reverse of s3c_hsotg_map_dma(), called for the completion | |
281 | * of a request to ensure the buffer is ready for access by the caller. | |
8b9bc460 | 282 | */ |
941fcce4 | 283 | static void s3c_hsotg_unmap_dma(struct dwc2_hsotg *hsotg, |
5b7d70c6 BD |
284 | struct s3c_hsotg_ep *hs_ep, |
285 | struct s3c_hsotg_req *hs_req) | |
286 | { | |
287 | struct usb_request *req = &hs_req->req; | |
5b7d70c6 BD |
288 | |
289 | /* ignore this if we're not moving any data */ | |
290 | if (hs_req->req.length == 0) | |
291 | return; | |
292 | ||
17d966a3 | 293 | usb_gadget_unmap_request(&hsotg->gadget, req, hs_ep->dir_in); |
5b7d70c6 BD |
294 | } |
295 | ||
296 | /** | |
297 | * s3c_hsotg_write_fifo - write packet Data to the TxFIFO | |
298 | * @hsotg: The controller state. | |
299 | * @hs_ep: The endpoint we're going to write for. | |
300 | * @hs_req: The request to write data for. | |
301 | * | |
302 | * This is called when the TxFIFO has some space in it to hold a new | |
303 | * transmission and we have something to give it. The actual setup of | |
304 | * the data size is done elsewhere, so all we have to do is to actually | |
305 | * write the data. | |
306 | * | |
307 | * The return value is zero if there is more space (or nothing was done) | |
308 | * otherwise -ENOSPC is returned if the FIFO space was used up. | |
309 | * | |
310 | * This routine is only needed for PIO | |
8b9bc460 | 311 | */ |
941fcce4 | 312 | static int s3c_hsotg_write_fifo(struct dwc2_hsotg *hsotg, |
5b7d70c6 BD |
313 | struct s3c_hsotg_ep *hs_ep, |
314 | struct s3c_hsotg_req *hs_req) | |
315 | { | |
316 | bool periodic = is_ep_periodic(hs_ep); | |
94cb8fd6 | 317 | u32 gnptxsts = readl(hsotg->regs + GNPTXSTS); |
5b7d70c6 BD |
318 | int buf_pos = hs_req->req.actual; |
319 | int to_write = hs_ep->size_loaded; | |
320 | void *data; | |
321 | int can_write; | |
322 | int pkt_round; | |
4fca54aa | 323 | int max_transfer; |
5b7d70c6 BD |
324 | |
325 | to_write -= (buf_pos - hs_ep->last_load); | |
326 | ||
327 | /* if there's nothing to write, get out early */ | |
328 | if (to_write == 0) | |
329 | return 0; | |
330 | ||
10aebc77 | 331 | if (periodic && !hsotg->dedicated_fifos) { |
94cb8fd6 | 332 | u32 epsize = readl(hsotg->regs + DIEPTSIZ(hs_ep->index)); |
5b7d70c6 BD |
333 | int size_left; |
334 | int size_done; | |
335 | ||
8b9bc460 LM |
336 | /* |
337 | * work out how much data was loaded so we can calculate | |
338 | * how much data is left in the fifo. | |
339 | */ | |
5b7d70c6 | 340 | |
47a1685f | 341 | size_left = DXEPTSIZ_XFERSIZE_GET(epsize); |
5b7d70c6 | 342 | |
8b9bc460 LM |
343 | /* |
344 | * if shared fifo, we cannot write anything until the | |
e7a9ff54 BD |
345 | * previous data has been completely sent. |
346 | */ | |
347 | if (hs_ep->fifo_load != 0) { | |
47a1685f | 348 | s3c_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP); |
e7a9ff54 BD |
349 | return -ENOSPC; |
350 | } | |
351 | ||
5b7d70c6 BD |
352 | dev_dbg(hsotg->dev, "%s: left=%d, load=%d, fifo=%d, size %d\n", |
353 | __func__, size_left, | |
354 | hs_ep->size_loaded, hs_ep->fifo_load, hs_ep->fifo_size); | |
355 | ||
356 | /* how much of the data has moved */ | |
357 | size_done = hs_ep->size_loaded - size_left; | |
358 | ||
359 | /* how much data is left in the fifo */ | |
360 | can_write = hs_ep->fifo_load - size_done; | |
361 | dev_dbg(hsotg->dev, "%s: => can_write1=%d\n", | |
362 | __func__, can_write); | |
363 | ||
364 | can_write = hs_ep->fifo_size - can_write; | |
365 | dev_dbg(hsotg->dev, "%s: => can_write2=%d\n", | |
366 | __func__, can_write); | |
367 | ||
368 | if (can_write <= 0) { | |
47a1685f | 369 | s3c_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP); |
5b7d70c6 BD |
370 | return -ENOSPC; |
371 | } | |
10aebc77 | 372 | } else if (hsotg->dedicated_fifos && hs_ep->index != 0) { |
94cb8fd6 | 373 | can_write = readl(hsotg->regs + DTXFSTS(hs_ep->index)); |
10aebc77 BD |
374 | |
375 | can_write &= 0xffff; | |
376 | can_write *= 4; | |
5b7d70c6 | 377 | } else { |
47a1685f | 378 | if (GNPTXSTS_NP_TXQ_SPC_AVAIL_GET(gnptxsts) == 0) { |
5b7d70c6 BD |
379 | dev_dbg(hsotg->dev, |
380 | "%s: no queue slots available (0x%08x)\n", | |
381 | __func__, gnptxsts); | |
382 | ||
47a1685f | 383 | s3c_hsotg_en_gsint(hsotg, GINTSTS_NPTXFEMP); |
5b7d70c6 BD |
384 | return -ENOSPC; |
385 | } | |
386 | ||
47a1685f | 387 | can_write = GNPTXSTS_NP_TXF_SPC_AVAIL_GET(gnptxsts); |
679f9b7c | 388 | can_write *= 4; /* fifo size is in 32bit quantities. */ |
5b7d70c6 BD |
389 | } |
390 | ||
4fca54aa RB |
391 | max_transfer = hs_ep->ep.maxpacket * hs_ep->mc; |
392 | ||
393 | dev_dbg(hsotg->dev, "%s: GNPTXSTS=%08x, can=%d, to=%d, max_transfer %d\n", | |
394 | __func__, gnptxsts, can_write, to_write, max_transfer); | |
5b7d70c6 | 395 | |
8b9bc460 LM |
396 | /* |
397 | * limit to 512 bytes of data, it seems at least on the non-periodic | |
5b7d70c6 BD |
398 | * FIFO, requests of >512 cause the endpoint to get stuck with a |
399 | * fragment of the end of the transfer in it. | |
400 | */ | |
811f3303 | 401 | if (can_write > 512 && !periodic) |
5b7d70c6 BD |
402 | can_write = 512; |
403 | ||
8b9bc460 LM |
404 | /* |
405 | * limit the write to one max-packet size worth of data, but allow | |
03e10e5a | 406 | * the transfer to return that it did not run out of fifo space |
8b9bc460 LM |
407 | * doing it. |
408 | */ | |
4fca54aa RB |
409 | if (to_write > max_transfer) { |
410 | to_write = max_transfer; | |
03e10e5a | 411 | |
5cb2ff0c RB |
412 | /* it's needed only when we do not use dedicated fifos */ |
413 | if (!hsotg->dedicated_fifos) | |
414 | s3c_hsotg_en_gsint(hsotg, | |
47a1685f DN |
415 | periodic ? GINTSTS_PTXFEMP : |
416 | GINTSTS_NPTXFEMP); | |
03e10e5a BD |
417 | } |
418 | ||
5b7d70c6 BD |
419 | /* see if we can write data */ |
420 | ||
421 | if (to_write > can_write) { | |
422 | to_write = can_write; | |
4fca54aa | 423 | pkt_round = to_write % max_transfer; |
5b7d70c6 | 424 | |
8b9bc460 LM |
425 | /* |
426 | * Round the write down to an | |
5b7d70c6 BD |
427 | * exact number of packets. |
428 | * | |
429 | * Note, we do not currently check to see if we can ever | |
430 | * write a full packet or not to the FIFO. | |
431 | */ | |
432 | ||
433 | if (pkt_round) | |
434 | to_write -= pkt_round; | |
435 | ||
8b9bc460 LM |
436 | /* |
437 | * enable correct FIFO interrupt to alert us when there | |
438 | * is more room left. | |
439 | */ | |
5b7d70c6 | 440 | |
5cb2ff0c RB |
441 | /* it's needed only when we do not use dedicated fifos */ |
442 | if (!hsotg->dedicated_fifos) | |
443 | s3c_hsotg_en_gsint(hsotg, | |
47a1685f DN |
444 | periodic ? GINTSTS_PTXFEMP : |
445 | GINTSTS_NPTXFEMP); | |
5b7d70c6 BD |
446 | } |
447 | ||
448 | dev_dbg(hsotg->dev, "write %d/%d, can_write %d, done %d\n", | |
449 | to_write, hs_req->req.length, can_write, buf_pos); | |
450 | ||
451 | if (to_write <= 0) | |
452 | return -ENOSPC; | |
453 | ||
454 | hs_req->req.actual = buf_pos + to_write; | |
455 | hs_ep->total_data += to_write; | |
456 | ||
457 | if (periodic) | |
458 | hs_ep->fifo_load += to_write; | |
459 | ||
460 | to_write = DIV_ROUND_UP(to_write, 4); | |
461 | data = hs_req->req.buf + buf_pos; | |
462 | ||
1a7ed5be | 463 | iowrite32_rep(hsotg->regs + EPFIFO(hs_ep->index), data, to_write); |
5b7d70c6 BD |
464 | |
465 | return (to_write >= can_write) ? -ENOSPC : 0; | |
466 | } | |
467 | ||
468 | /** | |
469 | * get_ep_limit - get the maximum data legnth for this endpoint | |
470 | * @hs_ep: The endpoint | |
471 | * | |
472 | * Return the maximum data that can be queued in one go on a given endpoint | |
473 | * so that transfers that are too long can be split. | |
474 | */ | |
475 | static unsigned get_ep_limit(struct s3c_hsotg_ep *hs_ep) | |
476 | { | |
477 | int index = hs_ep->index; | |
478 | unsigned maxsize; | |
479 | unsigned maxpkt; | |
480 | ||
481 | if (index != 0) { | |
47a1685f DN |
482 | maxsize = DXEPTSIZ_XFERSIZE_LIMIT + 1; |
483 | maxpkt = DXEPTSIZ_PKTCNT_LIMIT + 1; | |
5b7d70c6 | 484 | } else { |
b05ca580 | 485 | maxsize = 64+64; |
66e5c643 | 486 | if (hs_ep->dir_in) |
47a1685f | 487 | maxpkt = DIEPTSIZ0_PKTCNT_LIMIT + 1; |
66e5c643 | 488 | else |
5b7d70c6 | 489 | maxpkt = 2; |
5b7d70c6 BD |
490 | } |
491 | ||
492 | /* we made the constant loading easier above by using +1 */ | |
493 | maxpkt--; | |
494 | maxsize--; | |
495 | ||
8b9bc460 LM |
496 | /* |
497 | * constrain by packet count if maxpkts*pktsize is greater | |
498 | * than the length register size. | |
499 | */ | |
5b7d70c6 BD |
500 | |
501 | if ((maxpkt * hs_ep->ep.maxpacket) < maxsize) | |
502 | maxsize = maxpkt * hs_ep->ep.maxpacket; | |
503 | ||
504 | return maxsize; | |
505 | } | |
506 | ||
507 | /** | |
508 | * s3c_hsotg_start_req - start a USB request from an endpoint's queue | |
509 | * @hsotg: The controller state. | |
510 | * @hs_ep: The endpoint to process a request for | |
511 | * @hs_req: The request to start. | |
512 | * @continuing: True if we are doing more for the current request. | |
513 | * | |
514 | * Start the given request running by setting the endpoint registers | |
515 | * appropriately, and writing any data to the FIFOs. | |
516 | */ | |
941fcce4 | 517 | static void s3c_hsotg_start_req(struct dwc2_hsotg *hsotg, |
5b7d70c6 BD |
518 | struct s3c_hsotg_ep *hs_ep, |
519 | struct s3c_hsotg_req *hs_req, | |
520 | bool continuing) | |
521 | { | |
522 | struct usb_request *ureq = &hs_req->req; | |
523 | int index = hs_ep->index; | |
524 | int dir_in = hs_ep->dir_in; | |
525 | u32 epctrl_reg; | |
526 | u32 epsize_reg; | |
527 | u32 epsize; | |
528 | u32 ctrl; | |
529 | unsigned length; | |
530 | unsigned packets; | |
531 | unsigned maxreq; | |
532 | ||
533 | if (index != 0) { | |
534 | if (hs_ep->req && !continuing) { | |
535 | dev_err(hsotg->dev, "%s: active request\n", __func__); | |
536 | WARN_ON(1); | |
537 | return; | |
538 | } else if (hs_ep->req != hs_req && continuing) { | |
539 | dev_err(hsotg->dev, | |
540 | "%s: continue different req\n", __func__); | |
541 | WARN_ON(1); | |
542 | return; | |
543 | } | |
544 | } | |
545 | ||
94cb8fd6 LM |
546 | epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index); |
547 | epsize_reg = dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index); | |
5b7d70c6 BD |
548 | |
549 | dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n", | |
550 | __func__, readl(hsotg->regs + epctrl_reg), index, | |
551 | hs_ep->dir_in ? "in" : "out"); | |
552 | ||
9c39ddc6 AT |
553 | /* If endpoint is stalled, we will restart request later */ |
554 | ctrl = readl(hsotg->regs + epctrl_reg); | |
555 | ||
47a1685f | 556 | if (ctrl & DXEPCTL_STALL) { |
9c39ddc6 AT |
557 | dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index); |
558 | return; | |
559 | } | |
560 | ||
5b7d70c6 | 561 | length = ureq->length - ureq->actual; |
71225bee LM |
562 | dev_dbg(hsotg->dev, "ureq->length:%d ureq->actual:%d\n", |
563 | ureq->length, ureq->actual); | |
5b7d70c6 BD |
564 | if (0) |
565 | dev_dbg(hsotg->dev, | |
0cc4cf6f | 566 | "REQ buf %p len %d dma %pad noi=%d zp=%d snok=%d\n", |
8b3bc14f | 567 | ureq->buf, length, &ureq->dma, |
5b7d70c6 BD |
568 | ureq->no_interrupt, ureq->zero, ureq->short_not_ok); |
569 | ||
570 | maxreq = get_ep_limit(hs_ep); | |
571 | if (length > maxreq) { | |
572 | int round = maxreq % hs_ep->ep.maxpacket; | |
573 | ||
574 | dev_dbg(hsotg->dev, "%s: length %d, max-req %d, r %d\n", | |
575 | __func__, length, maxreq, round); | |
576 | ||
577 | /* round down to multiple of packets */ | |
578 | if (round) | |
579 | maxreq -= round; | |
580 | ||
581 | length = maxreq; | |
582 | } | |
583 | ||
584 | if (length) | |
585 | packets = DIV_ROUND_UP(length, hs_ep->ep.maxpacket); | |
586 | else | |
587 | packets = 1; /* send one packet if length is zero. */ | |
588 | ||
4fca54aa RB |
589 | if (hs_ep->isochronous && length > (hs_ep->mc * hs_ep->ep.maxpacket)) { |
590 | dev_err(hsotg->dev, "req length > maxpacket*mc\n"); | |
591 | return; | |
592 | } | |
593 | ||
5b7d70c6 | 594 | if (dir_in && index != 0) |
4fca54aa | 595 | if (hs_ep->isochronous) |
47a1685f | 596 | epsize = DXEPTSIZ_MC(packets); |
4fca54aa | 597 | else |
47a1685f | 598 | epsize = DXEPTSIZ_MC(1); |
5b7d70c6 BD |
599 | else |
600 | epsize = 0; | |
601 | ||
f71b5e25 MYK |
602 | /* |
603 | * zero length packet should be programmed on its own and should not | |
604 | * be counted in DIEPTSIZ.PktCnt with other packets. | |
605 | */ | |
606 | if (dir_in && ureq->zero && !continuing) { | |
607 | /* Test if zlp is actually required. */ | |
608 | if ((ureq->length >= hs_ep->ep.maxpacket) && | |
609 | !(ureq->length % hs_ep->ep.maxpacket)) | |
610 | hs_ep->sent_zlp = 1; | |
5b7d70c6 BD |
611 | } |
612 | ||
47a1685f DN |
613 | epsize |= DXEPTSIZ_PKTCNT(packets); |
614 | epsize |= DXEPTSIZ_XFERSIZE(length); | |
5b7d70c6 BD |
615 | |
616 | dev_dbg(hsotg->dev, "%s: %d@%d/%d, 0x%08x => 0x%08x\n", | |
617 | __func__, packets, length, ureq->length, epsize, epsize_reg); | |
618 | ||
619 | /* store the request as the current one we're doing */ | |
620 | hs_ep->req = hs_req; | |
621 | ||
622 | /* write size / packets */ | |
623 | writel(epsize, hsotg->regs + epsize_reg); | |
624 | ||
db1d8ba3 | 625 | if (using_dma(hsotg) && !continuing) { |
5b7d70c6 BD |
626 | unsigned int dma_reg; |
627 | ||
8b9bc460 LM |
628 | /* |
629 | * write DMA address to control register, buffer already | |
630 | * synced by s3c_hsotg_ep_queue(). | |
631 | */ | |
5b7d70c6 | 632 | |
94cb8fd6 | 633 | dma_reg = dir_in ? DIEPDMA(index) : DOEPDMA(index); |
5b7d70c6 BD |
634 | writel(ureq->dma, hsotg->regs + dma_reg); |
635 | ||
0cc4cf6f | 636 | dev_dbg(hsotg->dev, "%s: %pad => 0x%08x\n", |
8b3bc14f | 637 | __func__, &ureq->dma, dma_reg); |
5b7d70c6 BD |
638 | } |
639 | ||
47a1685f DN |
640 | ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */ |
641 | ctrl |= DXEPCTL_USBACTEP; | |
71225bee | 642 | |
fe0b94ab | 643 | dev_dbg(hsotg->dev, "ep0 state:%d\n", hsotg->ep0_state); |
71225bee LM |
644 | |
645 | /* For Setup request do not clear NAK */ | |
fe0b94ab | 646 | if (!(index == 0 && hsotg->ep0_state == DWC2_EP0_SETUP)) |
47a1685f | 647 | ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */ |
71225bee | 648 | |
5b7d70c6 BD |
649 | dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl); |
650 | writel(ctrl, hsotg->regs + epctrl_reg); | |
651 | ||
8b9bc460 LM |
652 | /* |
653 | * set these, it seems that DMA support increments past the end | |
5b7d70c6 | 654 | * of the packet buffer so we need to calculate the length from |
8b9bc460 LM |
655 | * this information. |
656 | */ | |
5b7d70c6 BD |
657 | hs_ep->size_loaded = length; |
658 | hs_ep->last_load = ureq->actual; | |
659 | ||
660 | if (dir_in && !using_dma(hsotg)) { | |
661 | /* set these anyway, we may need them for non-periodic in */ | |
662 | hs_ep->fifo_load = 0; | |
663 | ||
664 | s3c_hsotg_write_fifo(hsotg, hs_ep, hs_req); | |
665 | } | |
666 | ||
8b9bc460 LM |
667 | /* |
668 | * clear the INTknTXFEmpMsk when we start request, more as a aide | |
669 | * to debugging to see what is going on. | |
670 | */ | |
5b7d70c6 | 671 | if (dir_in) |
47a1685f | 672 | writel(DIEPMSK_INTKNTXFEMPMSK, |
94cb8fd6 | 673 | hsotg->regs + DIEPINT(index)); |
5b7d70c6 | 674 | |
8b9bc460 LM |
675 | /* |
676 | * Note, trying to clear the NAK here causes problems with transmit | |
677 | * on the S3C6400 ending up with the TXFIFO becoming full. | |
678 | */ | |
5b7d70c6 BD |
679 | |
680 | /* check ep is enabled */ | |
47a1685f | 681 | if (!(readl(hsotg->regs + epctrl_reg) & DXEPCTL_EPENA)) |
1a0ed863 | 682 | dev_dbg(hsotg->dev, |
47a1685f | 683 | "ep%d: failed to become enabled (DXEPCTL=0x%08x)?\n", |
5b7d70c6 BD |
684 | index, readl(hsotg->regs + epctrl_reg)); |
685 | ||
47a1685f | 686 | dev_dbg(hsotg->dev, "%s: DXEPCTL=0x%08x\n", |
5b7d70c6 | 687 | __func__, readl(hsotg->regs + epctrl_reg)); |
afcf4169 RB |
688 | |
689 | /* enable ep interrupts */ | |
690 | s3c_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 1); | |
5b7d70c6 BD |
691 | } |
692 | ||
693 | /** | |
694 | * s3c_hsotg_map_dma - map the DMA memory being used for the request | |
695 | * @hsotg: The device state. | |
696 | * @hs_ep: The endpoint the request is on. | |
697 | * @req: The request being processed. | |
698 | * | |
699 | * We've been asked to queue a request, so ensure that the memory buffer | |
700 | * is correctly setup for DMA. If we've been passed an extant DMA address | |
701 | * then ensure the buffer has been synced to memory. If our buffer has no | |
702 | * DMA memory, then we map the memory and mark our request to allow us to | |
703 | * cleanup on completion. | |
8b9bc460 | 704 | */ |
941fcce4 | 705 | static int s3c_hsotg_map_dma(struct dwc2_hsotg *hsotg, |
5b7d70c6 BD |
706 | struct s3c_hsotg_ep *hs_ep, |
707 | struct usb_request *req) | |
708 | { | |
5b7d70c6 | 709 | struct s3c_hsotg_req *hs_req = our_req(req); |
e58ebcd1 | 710 | int ret; |
5b7d70c6 BD |
711 | |
712 | /* if the length is zero, ignore the DMA data */ | |
713 | if (hs_req->req.length == 0) | |
714 | return 0; | |
715 | ||
e58ebcd1 FB |
716 | ret = usb_gadget_map_request(&hsotg->gadget, req, hs_ep->dir_in); |
717 | if (ret) | |
718 | goto dma_error; | |
5b7d70c6 BD |
719 | |
720 | return 0; | |
721 | ||
722 | dma_error: | |
723 | dev_err(hsotg->dev, "%s: failed to map buffer %p, %d bytes\n", | |
724 | __func__, req->buf, req->length); | |
725 | ||
726 | return -EIO; | |
727 | } | |
728 | ||
729 | static int s3c_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req, | |
730 | gfp_t gfp_flags) | |
731 | { | |
732 | struct s3c_hsotg_req *hs_req = our_req(req); | |
733 | struct s3c_hsotg_ep *hs_ep = our_ep(ep); | |
941fcce4 | 734 | struct dwc2_hsotg *hs = hs_ep->parent; |
5b7d70c6 BD |
735 | bool first; |
736 | ||
737 | dev_dbg(hs->dev, "%s: req %p: %d@%p, noi=%d, zero=%d, snok=%d\n", | |
738 | ep->name, req, req->length, req->buf, req->no_interrupt, | |
739 | req->zero, req->short_not_ok); | |
740 | ||
741 | /* initialise status of the request */ | |
742 | INIT_LIST_HEAD(&hs_req->queue); | |
743 | req->actual = 0; | |
744 | req->status = -EINPROGRESS; | |
745 | ||
746 | /* if we're using DMA, sync the buffers as necessary */ | |
747 | if (using_dma(hs)) { | |
748 | int ret = s3c_hsotg_map_dma(hs, hs_ep, req); | |
749 | if (ret) | |
750 | return ret; | |
751 | } | |
752 | ||
5b7d70c6 BD |
753 | first = list_empty(&hs_ep->queue); |
754 | list_add_tail(&hs_req->queue, &hs_ep->queue); | |
755 | ||
756 | if (first) | |
757 | s3c_hsotg_start_req(hs, hs_ep, hs_req, false); | |
758 | ||
5b7d70c6 BD |
759 | return 0; |
760 | } | |
761 | ||
5ad1d316 LM |
762 | static int s3c_hsotg_ep_queue_lock(struct usb_ep *ep, struct usb_request *req, |
763 | gfp_t gfp_flags) | |
764 | { | |
765 | struct s3c_hsotg_ep *hs_ep = our_ep(ep); | |
941fcce4 | 766 | struct dwc2_hsotg *hs = hs_ep->parent; |
5ad1d316 LM |
767 | unsigned long flags = 0; |
768 | int ret = 0; | |
769 | ||
770 | spin_lock_irqsave(&hs->lock, flags); | |
771 | ret = s3c_hsotg_ep_queue(ep, req, gfp_flags); | |
772 | spin_unlock_irqrestore(&hs->lock, flags); | |
773 | ||
774 | return ret; | |
775 | } | |
776 | ||
5b7d70c6 BD |
777 | static void s3c_hsotg_ep_free_request(struct usb_ep *ep, |
778 | struct usb_request *req) | |
779 | { | |
780 | struct s3c_hsotg_req *hs_req = our_req(req); | |
781 | ||
782 | kfree(hs_req); | |
783 | } | |
784 | ||
785 | /** | |
786 | * s3c_hsotg_complete_oursetup - setup completion callback | |
787 | * @ep: The endpoint the request was on. | |
788 | * @req: The request completed. | |
789 | * | |
790 | * Called on completion of any requests the driver itself | |
791 | * submitted that need cleaning up. | |
792 | */ | |
793 | static void s3c_hsotg_complete_oursetup(struct usb_ep *ep, | |
794 | struct usb_request *req) | |
795 | { | |
796 | struct s3c_hsotg_ep *hs_ep = our_ep(ep); | |
941fcce4 | 797 | struct dwc2_hsotg *hsotg = hs_ep->parent; |
5b7d70c6 BD |
798 | |
799 | dev_dbg(hsotg->dev, "%s: ep %p, req %p\n", __func__, ep, req); | |
800 | ||
801 | s3c_hsotg_ep_free_request(ep, req); | |
802 | } | |
803 | ||
804 | /** | |
805 | * ep_from_windex - convert control wIndex value to endpoint | |
806 | * @hsotg: The driver state. | |
807 | * @windex: The control request wIndex field (in host order). | |
808 | * | |
809 | * Convert the given wIndex into a pointer to an driver endpoint | |
810 | * structure, or return NULL if it is not a valid endpoint. | |
8b9bc460 | 811 | */ |
941fcce4 | 812 | static struct s3c_hsotg_ep *ep_from_windex(struct dwc2_hsotg *hsotg, |
5b7d70c6 BD |
813 | u32 windex) |
814 | { | |
c6f5c050 | 815 | struct s3c_hsotg_ep *ep; |
5b7d70c6 BD |
816 | int dir = (windex & USB_DIR_IN) ? 1 : 0; |
817 | int idx = windex & 0x7F; | |
818 | ||
819 | if (windex >= 0x100) | |
820 | return NULL; | |
821 | ||
b3f489b2 | 822 | if (idx > hsotg->num_of_eps) |
5b7d70c6 BD |
823 | return NULL; |
824 | ||
c6f5c050 MYK |
825 | ep = index_to_ep(hsotg, idx, dir); |
826 | ||
5b7d70c6 BD |
827 | if (idx && ep->dir_in != dir) |
828 | return NULL; | |
829 | ||
830 | return ep; | |
831 | } | |
832 | ||
833 | /** | |
834 | * s3c_hsotg_send_reply - send reply to control request | |
835 | * @hsotg: The device state | |
836 | * @ep: Endpoint 0 | |
837 | * @buff: Buffer for request | |
838 | * @length: Length of reply. | |
839 | * | |
840 | * Create a request and queue it on the given endpoint. This is useful as | |
841 | * an internal method of sending replies to certain control requests, etc. | |
842 | */ | |
941fcce4 | 843 | static int s3c_hsotg_send_reply(struct dwc2_hsotg *hsotg, |
5b7d70c6 BD |
844 | struct s3c_hsotg_ep *ep, |
845 | void *buff, | |
846 | int length) | |
847 | { | |
848 | struct usb_request *req; | |
849 | int ret; | |
850 | ||
851 | dev_dbg(hsotg->dev, "%s: buff %p, len %d\n", __func__, buff, length); | |
852 | ||
853 | req = s3c_hsotg_ep_alloc_request(&ep->ep, GFP_ATOMIC); | |
854 | hsotg->ep0_reply = req; | |
855 | if (!req) { | |
856 | dev_warn(hsotg->dev, "%s: cannot alloc req\n", __func__); | |
857 | return -ENOMEM; | |
858 | } | |
859 | ||
860 | req->buf = hsotg->ep0_buff; | |
861 | req->length = length; | |
f71b5e25 MYK |
862 | /* |
863 | * zero flag is for sending zlp in DATA IN stage. It has no impact on | |
864 | * STATUS stage. | |
865 | */ | |
866 | req->zero = 0; | |
5b7d70c6 BD |
867 | req->complete = s3c_hsotg_complete_oursetup; |
868 | ||
869 | if (length) | |
870 | memcpy(req->buf, buff, length); | |
5b7d70c6 BD |
871 | |
872 | ret = s3c_hsotg_ep_queue(&ep->ep, req, GFP_ATOMIC); | |
873 | if (ret) { | |
874 | dev_warn(hsotg->dev, "%s: cannot queue req\n", __func__); | |
875 | return ret; | |
876 | } | |
877 | ||
878 | return 0; | |
879 | } | |
880 | ||
881 | /** | |
882 | * s3c_hsotg_process_req_status - process request GET_STATUS | |
883 | * @hsotg: The device state | |
884 | * @ctrl: USB control request | |
885 | */ | |
941fcce4 | 886 | static int s3c_hsotg_process_req_status(struct dwc2_hsotg *hsotg, |
5b7d70c6 BD |
887 | struct usb_ctrlrequest *ctrl) |
888 | { | |
c6f5c050 | 889 | struct s3c_hsotg_ep *ep0 = hsotg->eps_out[0]; |
5b7d70c6 BD |
890 | struct s3c_hsotg_ep *ep; |
891 | __le16 reply; | |
892 | int ret; | |
893 | ||
894 | dev_dbg(hsotg->dev, "%s: USB_REQ_GET_STATUS\n", __func__); | |
895 | ||
896 | if (!ep0->dir_in) { | |
897 | dev_warn(hsotg->dev, "%s: direction out?\n", __func__); | |
898 | return -EINVAL; | |
899 | } | |
900 | ||
901 | switch (ctrl->bRequestType & USB_RECIP_MASK) { | |
902 | case USB_RECIP_DEVICE: | |
903 | reply = cpu_to_le16(0); /* bit 0 => self powered, | |
904 | * bit 1 => remote wakeup */ | |
905 | break; | |
906 | ||
907 | case USB_RECIP_INTERFACE: | |
908 | /* currently, the data result should be zero */ | |
909 | reply = cpu_to_le16(0); | |
910 | break; | |
911 | ||
912 | case USB_RECIP_ENDPOINT: | |
913 | ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex)); | |
914 | if (!ep) | |
915 | return -ENOENT; | |
916 | ||
917 | reply = cpu_to_le16(ep->halted ? 1 : 0); | |
918 | break; | |
919 | ||
920 | default: | |
921 | return 0; | |
922 | } | |
923 | ||
924 | if (le16_to_cpu(ctrl->wLength) != 2) | |
925 | return -EINVAL; | |
926 | ||
927 | ret = s3c_hsotg_send_reply(hsotg, ep0, &reply, 2); | |
928 | if (ret) { | |
929 | dev_err(hsotg->dev, "%s: failed to send reply\n", __func__); | |
930 | return ret; | |
931 | } | |
932 | ||
933 | return 1; | |
934 | } | |
935 | ||
936 | static int s3c_hsotg_ep_sethalt(struct usb_ep *ep, int value); | |
937 | ||
9c39ddc6 AT |
938 | /** |
939 | * get_ep_head - return the first request on the endpoint | |
940 | * @hs_ep: The controller endpoint to get | |
941 | * | |
942 | * Get the first request on the endpoint. | |
943 | */ | |
944 | static struct s3c_hsotg_req *get_ep_head(struct s3c_hsotg_ep *hs_ep) | |
945 | { | |
946 | if (list_empty(&hs_ep->queue)) | |
947 | return NULL; | |
948 | ||
949 | return list_first_entry(&hs_ep->queue, struct s3c_hsotg_req, queue); | |
950 | } | |
951 | ||
5b7d70c6 BD |
952 | /** |
953 | * s3c_hsotg_process_req_featire - process request {SET,CLEAR}_FEATURE | |
954 | * @hsotg: The device state | |
955 | * @ctrl: USB control request | |
956 | */ | |
941fcce4 | 957 | static int s3c_hsotg_process_req_feature(struct dwc2_hsotg *hsotg, |
5b7d70c6 BD |
958 | struct usb_ctrlrequest *ctrl) |
959 | { | |
c6f5c050 | 960 | struct s3c_hsotg_ep *ep0 = hsotg->eps_out[0]; |
9c39ddc6 AT |
961 | struct s3c_hsotg_req *hs_req; |
962 | bool restart; | |
5b7d70c6 BD |
963 | bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE); |
964 | struct s3c_hsotg_ep *ep; | |
26ab3d0c | 965 | int ret; |
bd9ef7bf | 966 | bool halted; |
5b7d70c6 BD |
967 | |
968 | dev_dbg(hsotg->dev, "%s: %s_FEATURE\n", | |
969 | __func__, set ? "SET" : "CLEAR"); | |
970 | ||
971 | if (ctrl->bRequestType == USB_RECIP_ENDPOINT) { | |
972 | ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex)); | |
973 | if (!ep) { | |
974 | dev_dbg(hsotg->dev, "%s: no endpoint for 0x%04x\n", | |
975 | __func__, le16_to_cpu(ctrl->wIndex)); | |
976 | return -ENOENT; | |
977 | } | |
978 | ||
979 | switch (le16_to_cpu(ctrl->wValue)) { | |
980 | case USB_ENDPOINT_HALT: | |
bd9ef7bf RB |
981 | halted = ep->halted; |
982 | ||
5b7d70c6 | 983 | s3c_hsotg_ep_sethalt(&ep->ep, set); |
26ab3d0c AT |
984 | |
985 | ret = s3c_hsotg_send_reply(hsotg, ep0, NULL, 0); | |
986 | if (ret) { | |
987 | dev_err(hsotg->dev, | |
988 | "%s: failed to send reply\n", __func__); | |
989 | return ret; | |
990 | } | |
9c39ddc6 | 991 | |
bd9ef7bf RB |
992 | /* |
993 | * we have to complete all requests for ep if it was | |
994 | * halted, and the halt was cleared by CLEAR_FEATURE | |
995 | */ | |
996 | ||
997 | if (!set && halted) { | |
9c39ddc6 AT |
998 | /* |
999 | * If we have request in progress, | |
1000 | * then complete it | |
1001 | */ | |
1002 | if (ep->req) { | |
1003 | hs_req = ep->req; | |
1004 | ep->req = NULL; | |
1005 | list_del_init(&hs_req->queue); | |
304f7e5e MS |
1006 | usb_gadget_giveback_request(&ep->ep, |
1007 | &hs_req->req); | |
9c39ddc6 AT |
1008 | } |
1009 | ||
1010 | /* If we have pending request, then start it */ | |
1011 | restart = !list_empty(&ep->queue); | |
1012 | if (restart) { | |
1013 | hs_req = get_ep_head(ep); | |
1014 | s3c_hsotg_start_req(hsotg, ep, | |
1015 | hs_req, false); | |
1016 | } | |
1017 | } | |
1018 | ||
5b7d70c6 BD |
1019 | break; |
1020 | ||
1021 | default: | |
1022 | return -ENOENT; | |
1023 | } | |
1024 | } else | |
1025 | return -ENOENT; /* currently only deal with endpoint */ | |
1026 | ||
1027 | return 1; | |
1028 | } | |
1029 | ||
941fcce4 | 1030 | static void s3c_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg); |
ab93e014 | 1031 | |
c9f721b2 RB |
1032 | /** |
1033 | * s3c_hsotg_stall_ep0 - stall ep0 | |
1034 | * @hsotg: The device state | |
1035 | * | |
1036 | * Set stall for ep0 as response for setup request. | |
1037 | */ | |
941fcce4 | 1038 | static void s3c_hsotg_stall_ep0(struct dwc2_hsotg *hsotg) |
e9ebe7c3 | 1039 | { |
c6f5c050 | 1040 | struct s3c_hsotg_ep *ep0 = hsotg->eps_out[0]; |
c9f721b2 RB |
1041 | u32 reg; |
1042 | u32 ctrl; | |
1043 | ||
1044 | dev_dbg(hsotg->dev, "ep0 stall (dir=%d)\n", ep0->dir_in); | |
1045 | reg = (ep0->dir_in) ? DIEPCTL0 : DOEPCTL0; | |
1046 | ||
1047 | /* | |
1048 | * DxEPCTL_Stall will be cleared by EP once it has | |
1049 | * taken effect, so no need to clear later. | |
1050 | */ | |
1051 | ||
1052 | ctrl = readl(hsotg->regs + reg); | |
47a1685f DN |
1053 | ctrl |= DXEPCTL_STALL; |
1054 | ctrl |= DXEPCTL_CNAK; | |
c9f721b2 RB |
1055 | writel(ctrl, hsotg->regs + reg); |
1056 | ||
1057 | dev_dbg(hsotg->dev, | |
47a1685f | 1058 | "written DXEPCTL=0x%08x to %08x (DXEPCTL=0x%08x)\n", |
c9f721b2 RB |
1059 | ctrl, reg, readl(hsotg->regs + reg)); |
1060 | ||
1061 | /* | |
1062 | * complete won't be called, so we enqueue | |
1063 | * setup request here | |
1064 | */ | |
1065 | s3c_hsotg_enqueue_setup(hsotg); | |
1066 | } | |
1067 | ||
5b7d70c6 BD |
1068 | /** |
1069 | * s3c_hsotg_process_control - process a control request | |
1070 | * @hsotg: The device state | |
1071 | * @ctrl: The control request received | |
1072 | * | |
1073 | * The controller has received the SETUP phase of a control request, and | |
1074 | * needs to work out what to do next (and whether to pass it on to the | |
1075 | * gadget driver). | |
1076 | */ | |
941fcce4 | 1077 | static void s3c_hsotg_process_control(struct dwc2_hsotg *hsotg, |
5b7d70c6 BD |
1078 | struct usb_ctrlrequest *ctrl) |
1079 | { | |
c6f5c050 | 1080 | struct s3c_hsotg_ep *ep0 = hsotg->eps_out[0]; |
5b7d70c6 BD |
1081 | int ret = 0; |
1082 | u32 dcfg; | |
1083 | ||
5b7d70c6 BD |
1084 | dev_dbg(hsotg->dev, "ctrl Req=%02x, Type=%02x, V=%04x, L=%04x\n", |
1085 | ctrl->bRequest, ctrl->bRequestType, | |
1086 | ctrl->wValue, ctrl->wLength); | |
1087 | ||
fe0b94ab MYK |
1088 | if (ctrl->wLength == 0) { |
1089 | ep0->dir_in = 1; | |
1090 | hsotg->ep0_state = DWC2_EP0_STATUS_IN; | |
1091 | } else if (ctrl->bRequestType & USB_DIR_IN) { | |
5b7d70c6 | 1092 | ep0->dir_in = 1; |
fe0b94ab MYK |
1093 | hsotg->ep0_state = DWC2_EP0_DATA_IN; |
1094 | } else { | |
1095 | ep0->dir_in = 0; | |
1096 | hsotg->ep0_state = DWC2_EP0_DATA_OUT; | |
1097 | } | |
5b7d70c6 BD |
1098 | |
1099 | if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) { | |
1100 | switch (ctrl->bRequest) { | |
1101 | case USB_REQ_SET_ADDRESS: | |
94cb8fd6 | 1102 | dcfg = readl(hsotg->regs + DCFG); |
47a1685f | 1103 | dcfg &= ~DCFG_DEVADDR_MASK; |
d5dbd3f7 PZ |
1104 | dcfg |= (le16_to_cpu(ctrl->wValue) << |
1105 | DCFG_DEVADDR_SHIFT) & DCFG_DEVADDR_MASK; | |
94cb8fd6 | 1106 | writel(dcfg, hsotg->regs + DCFG); |
5b7d70c6 BD |
1107 | |
1108 | dev_info(hsotg->dev, "new address %d\n", ctrl->wValue); | |
1109 | ||
1110 | ret = s3c_hsotg_send_reply(hsotg, ep0, NULL, 0); | |
1111 | return; | |
1112 | ||
1113 | case USB_REQ_GET_STATUS: | |
1114 | ret = s3c_hsotg_process_req_status(hsotg, ctrl); | |
1115 | break; | |
1116 | ||
1117 | case USB_REQ_CLEAR_FEATURE: | |
1118 | case USB_REQ_SET_FEATURE: | |
1119 | ret = s3c_hsotg_process_req_feature(hsotg, ctrl); | |
1120 | break; | |
1121 | } | |
1122 | } | |
1123 | ||
1124 | /* as a fallback, try delivering it to the driver to deal with */ | |
1125 | ||
1126 | if (ret == 0 && hsotg->driver) { | |
93f599f2 | 1127 | spin_unlock(&hsotg->lock); |
5b7d70c6 | 1128 | ret = hsotg->driver->setup(&hsotg->gadget, ctrl); |
93f599f2 | 1129 | spin_lock(&hsotg->lock); |
5b7d70c6 BD |
1130 | if (ret < 0) |
1131 | dev_dbg(hsotg->dev, "driver->setup() ret %d\n", ret); | |
1132 | } | |
1133 | ||
8b9bc460 LM |
1134 | /* |
1135 | * the request is either unhandlable, or is not formatted correctly | |
5b7d70c6 BD |
1136 | * so respond with a STALL for the status stage to indicate failure. |
1137 | */ | |
1138 | ||
c9f721b2 RB |
1139 | if (ret < 0) |
1140 | s3c_hsotg_stall_ep0(hsotg); | |
5b7d70c6 BD |
1141 | } |
1142 | ||
5b7d70c6 BD |
1143 | /** |
1144 | * s3c_hsotg_complete_setup - completion of a setup transfer | |
1145 | * @ep: The endpoint the request was on. | |
1146 | * @req: The request completed. | |
1147 | * | |
1148 | * Called on completion of any requests the driver itself submitted for | |
1149 | * EP0 setup packets | |
1150 | */ | |
1151 | static void s3c_hsotg_complete_setup(struct usb_ep *ep, | |
1152 | struct usb_request *req) | |
1153 | { | |
1154 | struct s3c_hsotg_ep *hs_ep = our_ep(ep); | |
941fcce4 | 1155 | struct dwc2_hsotg *hsotg = hs_ep->parent; |
5b7d70c6 BD |
1156 | |
1157 | if (req->status < 0) { | |
1158 | dev_dbg(hsotg->dev, "%s: failed %d\n", __func__, req->status); | |
1159 | return; | |
1160 | } | |
1161 | ||
93f599f2 | 1162 | spin_lock(&hsotg->lock); |
5b7d70c6 BD |
1163 | if (req->actual == 0) |
1164 | s3c_hsotg_enqueue_setup(hsotg); | |
1165 | else | |
1166 | s3c_hsotg_process_control(hsotg, req->buf); | |
93f599f2 | 1167 | spin_unlock(&hsotg->lock); |
5b7d70c6 BD |
1168 | } |
1169 | ||
1170 | /** | |
1171 | * s3c_hsotg_enqueue_setup - start a request for EP0 packets | |
1172 | * @hsotg: The device state. | |
1173 | * | |
1174 | * Enqueue a request on EP0 if necessary to received any SETUP packets | |
1175 | * received from the host. | |
1176 | */ | |
941fcce4 | 1177 | static void s3c_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg) |
5b7d70c6 BD |
1178 | { |
1179 | struct usb_request *req = hsotg->ctrl_req; | |
1180 | struct s3c_hsotg_req *hs_req = our_req(req); | |
1181 | int ret; | |
1182 | ||
1183 | dev_dbg(hsotg->dev, "%s: queueing setup request\n", __func__); | |
1184 | ||
1185 | req->zero = 0; | |
1186 | req->length = 8; | |
1187 | req->buf = hsotg->ctrl_buff; | |
1188 | req->complete = s3c_hsotg_complete_setup; | |
1189 | ||
1190 | if (!list_empty(&hs_req->queue)) { | |
1191 | dev_dbg(hsotg->dev, "%s already queued???\n", __func__); | |
1192 | return; | |
1193 | } | |
1194 | ||
c6f5c050 | 1195 | hsotg->eps_out[0]->dir_in = 0; |
fe0b94ab MYK |
1196 | hsotg->eps_out[0]->sent_zlp = 0; |
1197 | hsotg->ep0_state = DWC2_EP0_SETUP; | |
5b7d70c6 | 1198 | |
c6f5c050 | 1199 | ret = s3c_hsotg_ep_queue(&hsotg->eps_out[0]->ep, req, GFP_ATOMIC); |
5b7d70c6 BD |
1200 | if (ret < 0) { |
1201 | dev_err(hsotg->dev, "%s: failed queue (%d)\n", __func__, ret); | |
8b9bc460 LM |
1202 | /* |
1203 | * Don't think there's much we can do other than watch the | |
1204 | * driver fail. | |
1205 | */ | |
5b7d70c6 BD |
1206 | } |
1207 | } | |
1208 | ||
fe0b94ab MYK |
1209 | static void s3c_hsotg_program_zlp(struct dwc2_hsotg *hsotg, |
1210 | struct s3c_hsotg_ep *hs_ep) | |
1211 | { | |
1212 | u32 ctrl; | |
1213 | u8 index = hs_ep->index; | |
1214 | u32 epctl_reg = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index); | |
1215 | u32 epsiz_reg = hs_ep->dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index); | |
1216 | ||
1217 | dev_dbg(hsotg->dev, "Sending zero-length packet on ep%d\n", index); | |
1218 | ||
1219 | writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) | | |
1220 | DXEPTSIZ_XFERSIZE(0), hsotg->regs + | |
1221 | epsiz_reg); | |
1222 | ||
1223 | ctrl = readl(hsotg->regs + epctl_reg); | |
1224 | ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */ | |
1225 | ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */ | |
1226 | ctrl |= DXEPCTL_USBACTEP; | |
1227 | writel(ctrl, hsotg->regs + epctl_reg); | |
1228 | } | |
1229 | ||
5b7d70c6 BD |
1230 | /** |
1231 | * s3c_hsotg_complete_request - complete a request given to us | |
1232 | * @hsotg: The device state. | |
1233 | * @hs_ep: The endpoint the request was on. | |
1234 | * @hs_req: The request to complete. | |
1235 | * @result: The result code (0 => Ok, otherwise errno) | |
1236 | * | |
1237 | * The given request has finished, so call the necessary completion | |
1238 | * if it has one and then look to see if we can start a new request | |
1239 | * on the endpoint. | |
1240 | * | |
1241 | * Note, expects the ep to already be locked as appropriate. | |
8b9bc460 | 1242 | */ |
941fcce4 | 1243 | static void s3c_hsotg_complete_request(struct dwc2_hsotg *hsotg, |
5b7d70c6 BD |
1244 | struct s3c_hsotg_ep *hs_ep, |
1245 | struct s3c_hsotg_req *hs_req, | |
1246 | int result) | |
1247 | { | |
1248 | bool restart; | |
1249 | ||
1250 | if (!hs_req) { | |
1251 | dev_dbg(hsotg->dev, "%s: nothing to complete?\n", __func__); | |
1252 | return; | |
1253 | } | |
1254 | ||
1255 | dev_dbg(hsotg->dev, "complete: ep %p %s, req %p, %d => %p\n", | |
1256 | hs_ep, hs_ep->ep.name, hs_req, result, hs_req->req.complete); | |
1257 | ||
8b9bc460 LM |
1258 | /* |
1259 | * only replace the status if we've not already set an error | |
1260 | * from a previous transaction | |
1261 | */ | |
5b7d70c6 BD |
1262 | |
1263 | if (hs_req->req.status == -EINPROGRESS) | |
1264 | hs_req->req.status = result; | |
1265 | ||
1266 | hs_ep->req = NULL; | |
1267 | list_del_init(&hs_req->queue); | |
1268 | ||
1269 | if (using_dma(hsotg)) | |
1270 | s3c_hsotg_unmap_dma(hsotg, hs_ep, hs_req); | |
1271 | ||
8b9bc460 LM |
1272 | /* |
1273 | * call the complete request with the locks off, just in case the | |
1274 | * request tries to queue more work for this endpoint. | |
1275 | */ | |
5b7d70c6 BD |
1276 | |
1277 | if (hs_req->req.complete) { | |
22258f49 | 1278 | spin_unlock(&hsotg->lock); |
304f7e5e | 1279 | usb_gadget_giveback_request(&hs_ep->ep, &hs_req->req); |
22258f49 | 1280 | spin_lock(&hsotg->lock); |
5b7d70c6 BD |
1281 | } |
1282 | ||
8b9bc460 LM |
1283 | /* |
1284 | * Look to see if there is anything else to do. Note, the completion | |
5b7d70c6 | 1285 | * of the previous request may have caused a new request to be started |
8b9bc460 LM |
1286 | * so be careful when doing this. |
1287 | */ | |
5b7d70c6 BD |
1288 | |
1289 | if (!hs_ep->req && result >= 0) { | |
1290 | restart = !list_empty(&hs_ep->queue); | |
1291 | if (restart) { | |
1292 | hs_req = get_ep_head(hs_ep); | |
1293 | s3c_hsotg_start_req(hsotg, hs_ep, hs_req, false); | |
1294 | } | |
1295 | } | |
1296 | } | |
1297 | ||
5b7d70c6 BD |
1298 | /** |
1299 | * s3c_hsotg_rx_data - receive data from the FIFO for an endpoint | |
1300 | * @hsotg: The device state. | |
1301 | * @ep_idx: The endpoint index for the data | |
1302 | * @size: The size of data in the fifo, in bytes | |
1303 | * | |
1304 | * The FIFO status shows there is data to read from the FIFO for a given | |
1305 | * endpoint, so sort out whether we need to read the data into a request | |
1306 | * that has been made for that endpoint. | |
1307 | */ | |
941fcce4 | 1308 | static void s3c_hsotg_rx_data(struct dwc2_hsotg *hsotg, int ep_idx, int size) |
5b7d70c6 | 1309 | { |
c6f5c050 | 1310 | struct s3c_hsotg_ep *hs_ep = hsotg->eps_out[ep_idx]; |
5b7d70c6 | 1311 | struct s3c_hsotg_req *hs_req = hs_ep->req; |
94cb8fd6 | 1312 | void __iomem *fifo = hsotg->regs + EPFIFO(ep_idx); |
5b7d70c6 BD |
1313 | int to_read; |
1314 | int max_req; | |
1315 | int read_ptr; | |
1316 | ||
22258f49 | 1317 | |
5b7d70c6 | 1318 | if (!hs_req) { |
94cb8fd6 | 1319 | u32 epctl = readl(hsotg->regs + DOEPCTL(ep_idx)); |
5b7d70c6 BD |
1320 | int ptr; |
1321 | ||
6b448af4 | 1322 | dev_dbg(hsotg->dev, |
47a1685f | 1323 | "%s: FIFO %d bytes on ep%d but no req (DXEPCTl=0x%08x)\n", |
5b7d70c6 BD |
1324 | __func__, size, ep_idx, epctl); |
1325 | ||
1326 | /* dump the data from the FIFO, we've nothing we can do */ | |
1327 | for (ptr = 0; ptr < size; ptr += 4) | |
1328 | (void)readl(fifo); | |
1329 | ||
1330 | return; | |
1331 | } | |
1332 | ||
5b7d70c6 BD |
1333 | to_read = size; |
1334 | read_ptr = hs_req->req.actual; | |
1335 | max_req = hs_req->req.length - read_ptr; | |
1336 | ||
a33e7136 BD |
1337 | dev_dbg(hsotg->dev, "%s: read %d/%d, done %d/%d\n", |
1338 | __func__, to_read, max_req, read_ptr, hs_req->req.length); | |
1339 | ||
5b7d70c6 | 1340 | if (to_read > max_req) { |
8b9bc460 LM |
1341 | /* |
1342 | * more data appeared than we where willing | |
5b7d70c6 BD |
1343 | * to deal with in this request. |
1344 | */ | |
1345 | ||
1346 | /* currently we don't deal this */ | |
1347 | WARN_ON_ONCE(1); | |
1348 | } | |
1349 | ||
5b7d70c6 BD |
1350 | hs_ep->total_data += to_read; |
1351 | hs_req->req.actual += to_read; | |
1352 | to_read = DIV_ROUND_UP(to_read, 4); | |
1353 | ||
8b9bc460 LM |
1354 | /* |
1355 | * note, we might over-write the buffer end by 3 bytes depending on | |
1356 | * alignment of the data. | |
1357 | */ | |
1a7ed5be | 1358 | ioread32_rep(fifo, hs_req->req.buf + read_ptr, to_read); |
5b7d70c6 BD |
1359 | } |
1360 | ||
1361 | /** | |
fe0b94ab | 1362 | * s3c_hsotg_ep0_zlp - send/receive zero-length packet on control endpoint |
5b7d70c6 | 1363 | * @hsotg: The device instance |
fe0b94ab | 1364 | * @dir_in: If IN zlp |
5b7d70c6 BD |
1365 | * |
1366 | * Generate a zero-length IN packet request for terminating a SETUP | |
1367 | * transaction. | |
1368 | * | |
1369 | * Note, since we don't write any data to the TxFIFO, then it is | |
25985edc | 1370 | * currently believed that we do not need to wait for any space in |
5b7d70c6 BD |
1371 | * the TxFIFO. |
1372 | */ | |
fe0b94ab | 1373 | static void s3c_hsotg_ep0_zlp(struct dwc2_hsotg *hsotg, bool dir_in) |
5b7d70c6 | 1374 | { |
c6f5c050 | 1375 | /* eps_out[0] is used in both directions */ |
fe0b94ab MYK |
1376 | hsotg->eps_out[0]->dir_in = dir_in; |
1377 | hsotg->ep0_state = dir_in ? DWC2_EP0_STATUS_IN : DWC2_EP0_STATUS_OUT; | |
5b7d70c6 | 1378 | |
fe0b94ab | 1379 | s3c_hsotg_program_zlp(hsotg, hsotg->eps_out[0]); |
5b7d70c6 BD |
1380 | } |
1381 | ||
1382 | /** | |
1383 | * s3c_hsotg_handle_outdone - handle receiving OutDone/SetupDone from RXFIFO | |
1384 | * @hsotg: The device instance | |
1385 | * @epnum: The endpoint received from | |
5b7d70c6 BD |
1386 | * |
1387 | * The RXFIFO has delivered an OutDone event, which means that the data | |
1388 | * transfer for an OUT endpoint has been completed, either by a short | |
1389 | * packet or by the finish of a transfer. | |
8b9bc460 | 1390 | */ |
fe0b94ab | 1391 | static void s3c_hsotg_handle_outdone(struct dwc2_hsotg *hsotg, int epnum) |
5b7d70c6 | 1392 | { |
94cb8fd6 | 1393 | u32 epsize = readl(hsotg->regs + DOEPTSIZ(epnum)); |
c6f5c050 | 1394 | struct s3c_hsotg_ep *hs_ep = hsotg->eps_out[epnum]; |
5b7d70c6 BD |
1395 | struct s3c_hsotg_req *hs_req = hs_ep->req; |
1396 | struct usb_request *req = &hs_req->req; | |
47a1685f | 1397 | unsigned size_left = DXEPTSIZ_XFERSIZE_GET(epsize); |
5b7d70c6 BD |
1398 | int result = 0; |
1399 | ||
1400 | if (!hs_req) { | |
1401 | dev_dbg(hsotg->dev, "%s: no request active\n", __func__); | |
1402 | return; | |
1403 | } | |
1404 | ||
fe0b94ab MYK |
1405 | if (epnum == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_OUT) { |
1406 | dev_dbg(hsotg->dev, "zlp packet received\n"); | |
1407 | s3c_hsotg_complete_request(hsotg, hs_ep, hs_req, 0); | |
1408 | s3c_hsotg_enqueue_setup(hsotg); | |
1409 | return; | |
1410 | } | |
1411 | ||
5b7d70c6 | 1412 | if (using_dma(hsotg)) { |
5b7d70c6 | 1413 | unsigned size_done; |
5b7d70c6 | 1414 | |
8b9bc460 LM |
1415 | /* |
1416 | * Calculate the size of the transfer by checking how much | |
5b7d70c6 BD |
1417 | * is left in the endpoint size register and then working it |
1418 | * out from the amount we loaded for the transfer. | |
1419 | * | |
1420 | * We need to do this as DMA pointers are always 32bit aligned | |
1421 | * so may overshoot/undershoot the transfer. | |
1422 | */ | |
1423 | ||
5b7d70c6 BD |
1424 | size_done = hs_ep->size_loaded - size_left; |
1425 | size_done += hs_ep->last_load; | |
1426 | ||
1427 | req->actual = size_done; | |
1428 | } | |
1429 | ||
a33e7136 BD |
1430 | /* if there is more request to do, schedule new transfer */ |
1431 | if (req->actual < req->length && size_left == 0) { | |
1432 | s3c_hsotg_start_req(hsotg, hs_ep, hs_req, true); | |
1433 | return; | |
1434 | } | |
1435 | ||
5b7d70c6 BD |
1436 | if (req->actual < req->length && req->short_not_ok) { |
1437 | dev_dbg(hsotg->dev, "%s: got %d/%d (short not ok) => error\n", | |
1438 | __func__, req->actual, req->length); | |
1439 | ||
8b9bc460 LM |
1440 | /* |
1441 | * todo - what should we return here? there's no one else | |
1442 | * even bothering to check the status. | |
1443 | */ | |
5b7d70c6 BD |
1444 | } |
1445 | ||
fe0b94ab MYK |
1446 | if (epnum == 0 && hsotg->ep0_state == DWC2_EP0_DATA_OUT) { |
1447 | /* Move to STATUS IN */ | |
1448 | s3c_hsotg_ep0_zlp(hsotg, true); | |
1449 | return; | |
5b7d70c6 BD |
1450 | } |
1451 | ||
5ad1d316 | 1452 | s3c_hsotg_complete_request(hsotg, hs_ep, hs_req, result); |
5b7d70c6 BD |
1453 | } |
1454 | ||
1455 | /** | |
1456 | * s3c_hsotg_read_frameno - read current frame number | |
1457 | * @hsotg: The device instance | |
1458 | * | |
1459 | * Return the current frame number | |
8b9bc460 | 1460 | */ |
941fcce4 | 1461 | static u32 s3c_hsotg_read_frameno(struct dwc2_hsotg *hsotg) |
5b7d70c6 BD |
1462 | { |
1463 | u32 dsts; | |
1464 | ||
94cb8fd6 LM |
1465 | dsts = readl(hsotg->regs + DSTS); |
1466 | dsts &= DSTS_SOFFN_MASK; | |
1467 | dsts >>= DSTS_SOFFN_SHIFT; | |
5b7d70c6 BD |
1468 | |
1469 | return dsts; | |
1470 | } | |
1471 | ||
1472 | /** | |
1473 | * s3c_hsotg_handle_rx - RX FIFO has data | |
1474 | * @hsotg: The device instance | |
1475 | * | |
1476 | * The IRQ handler has detected that the RX FIFO has some data in it | |
1477 | * that requires processing, so find out what is in there and do the | |
1478 | * appropriate read. | |
1479 | * | |
25985edc | 1480 | * The RXFIFO is a true FIFO, the packets coming out are still in packet |
5b7d70c6 BD |
1481 | * chunks, so if you have x packets received on an endpoint you'll get x |
1482 | * FIFO events delivered, each with a packet's worth of data in it. | |
1483 | * | |
1484 | * When using DMA, we should not be processing events from the RXFIFO | |
1485 | * as the actual data should be sent to the memory directly and we turn | |
1486 | * on the completion interrupts to get notifications of transfer completion. | |
1487 | */ | |
941fcce4 | 1488 | static void s3c_hsotg_handle_rx(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 1489 | { |
94cb8fd6 | 1490 | u32 grxstsr = readl(hsotg->regs + GRXSTSP); |
5b7d70c6 BD |
1491 | u32 epnum, status, size; |
1492 | ||
1493 | WARN_ON(using_dma(hsotg)); | |
1494 | ||
47a1685f DN |
1495 | epnum = grxstsr & GRXSTS_EPNUM_MASK; |
1496 | status = grxstsr & GRXSTS_PKTSTS_MASK; | |
5b7d70c6 | 1497 | |
47a1685f DN |
1498 | size = grxstsr & GRXSTS_BYTECNT_MASK; |
1499 | size >>= GRXSTS_BYTECNT_SHIFT; | |
5b7d70c6 BD |
1500 | |
1501 | if (1) | |
1502 | dev_dbg(hsotg->dev, "%s: GRXSTSP=0x%08x (%d@%d)\n", | |
1503 | __func__, grxstsr, size, epnum); | |
1504 | ||
47a1685f DN |
1505 | switch ((status & GRXSTS_PKTSTS_MASK) >> GRXSTS_PKTSTS_SHIFT) { |
1506 | case GRXSTS_PKTSTS_GLOBALOUTNAK: | |
1507 | dev_dbg(hsotg->dev, "GLOBALOUTNAK\n"); | |
5b7d70c6 BD |
1508 | break; |
1509 | ||
47a1685f | 1510 | case GRXSTS_PKTSTS_OUTDONE: |
5b7d70c6 BD |
1511 | dev_dbg(hsotg->dev, "OutDone (Frame=0x%08x)\n", |
1512 | s3c_hsotg_read_frameno(hsotg)); | |
1513 | ||
1514 | if (!using_dma(hsotg)) | |
fe0b94ab | 1515 | s3c_hsotg_handle_outdone(hsotg, epnum); |
5b7d70c6 BD |
1516 | break; |
1517 | ||
47a1685f | 1518 | case GRXSTS_PKTSTS_SETUPDONE: |
5b7d70c6 BD |
1519 | dev_dbg(hsotg->dev, |
1520 | "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n", | |
1521 | s3c_hsotg_read_frameno(hsotg), | |
94cb8fd6 | 1522 | readl(hsotg->regs + DOEPCTL(0))); |
fe0b94ab MYK |
1523 | /* |
1524 | * Call s3c_hsotg_handle_outdone here if it was not called from | |
1525 | * GRXSTS_PKTSTS_OUTDONE. That is, if the core didn't | |
1526 | * generate GRXSTS_PKTSTS_OUTDONE for setup packet. | |
1527 | */ | |
1528 | if (hsotg->ep0_state == DWC2_EP0_SETUP) | |
1529 | s3c_hsotg_handle_outdone(hsotg, epnum); | |
5b7d70c6 BD |
1530 | break; |
1531 | ||
47a1685f | 1532 | case GRXSTS_PKTSTS_OUTRX: |
5b7d70c6 BD |
1533 | s3c_hsotg_rx_data(hsotg, epnum, size); |
1534 | break; | |
1535 | ||
47a1685f | 1536 | case GRXSTS_PKTSTS_SETUPRX: |
5b7d70c6 BD |
1537 | dev_dbg(hsotg->dev, |
1538 | "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n", | |
1539 | s3c_hsotg_read_frameno(hsotg), | |
94cb8fd6 | 1540 | readl(hsotg->regs + DOEPCTL(0))); |
5b7d70c6 | 1541 | |
fe0b94ab MYK |
1542 | WARN_ON(hsotg->ep0_state != DWC2_EP0_SETUP); |
1543 | ||
5b7d70c6 BD |
1544 | s3c_hsotg_rx_data(hsotg, epnum, size); |
1545 | break; | |
1546 | ||
1547 | default: | |
1548 | dev_warn(hsotg->dev, "%s: unknown status %08x\n", | |
1549 | __func__, grxstsr); | |
1550 | ||
1551 | s3c_hsotg_dump(hsotg); | |
1552 | break; | |
1553 | } | |
1554 | } | |
1555 | ||
1556 | /** | |
1557 | * s3c_hsotg_ep0_mps - turn max packet size into register setting | |
1558 | * @mps: The maximum packet size in bytes. | |
8b9bc460 | 1559 | */ |
5b7d70c6 BD |
1560 | static u32 s3c_hsotg_ep0_mps(unsigned int mps) |
1561 | { | |
1562 | switch (mps) { | |
1563 | case 64: | |
94cb8fd6 | 1564 | return D0EPCTL_MPS_64; |
5b7d70c6 | 1565 | case 32: |
94cb8fd6 | 1566 | return D0EPCTL_MPS_32; |
5b7d70c6 | 1567 | case 16: |
94cb8fd6 | 1568 | return D0EPCTL_MPS_16; |
5b7d70c6 | 1569 | case 8: |
94cb8fd6 | 1570 | return D0EPCTL_MPS_8; |
5b7d70c6 BD |
1571 | } |
1572 | ||
1573 | /* bad max packet size, warn and return invalid result */ | |
1574 | WARN_ON(1); | |
1575 | return (u32)-1; | |
1576 | } | |
1577 | ||
1578 | /** | |
1579 | * s3c_hsotg_set_ep_maxpacket - set endpoint's max-packet field | |
1580 | * @hsotg: The driver state. | |
1581 | * @ep: The index number of the endpoint | |
1582 | * @mps: The maximum packet size in bytes | |
1583 | * | |
1584 | * Configure the maximum packet size for the given endpoint, updating | |
1585 | * the hardware control registers to reflect this. | |
1586 | */ | |
941fcce4 | 1587 | static void s3c_hsotg_set_ep_maxpacket(struct dwc2_hsotg *hsotg, |
c6f5c050 | 1588 | unsigned int ep, unsigned int mps, unsigned int dir_in) |
5b7d70c6 | 1589 | { |
c6f5c050 | 1590 | struct s3c_hsotg_ep *hs_ep; |
5b7d70c6 BD |
1591 | void __iomem *regs = hsotg->regs; |
1592 | u32 mpsval; | |
4fca54aa | 1593 | u32 mcval; |
5b7d70c6 BD |
1594 | u32 reg; |
1595 | ||
c6f5c050 MYK |
1596 | hs_ep = index_to_ep(hsotg, ep, dir_in); |
1597 | if (!hs_ep) | |
1598 | return; | |
1599 | ||
5b7d70c6 BD |
1600 | if (ep == 0) { |
1601 | /* EP0 is a special case */ | |
1602 | mpsval = s3c_hsotg_ep0_mps(mps); | |
1603 | if (mpsval > 3) | |
1604 | goto bad_mps; | |
e9edd199 | 1605 | hs_ep->ep.maxpacket = mps; |
4fca54aa | 1606 | hs_ep->mc = 1; |
5b7d70c6 | 1607 | } else { |
47a1685f | 1608 | mpsval = mps & DXEPCTL_MPS_MASK; |
e9edd199 | 1609 | if (mpsval > 1024) |
5b7d70c6 | 1610 | goto bad_mps; |
4fca54aa RB |
1611 | mcval = ((mps >> 11) & 0x3) + 1; |
1612 | hs_ep->mc = mcval; | |
1613 | if (mcval > 3) | |
1614 | goto bad_mps; | |
e9edd199 | 1615 | hs_ep->ep.maxpacket = mpsval; |
5b7d70c6 BD |
1616 | } |
1617 | ||
c6f5c050 MYK |
1618 | if (dir_in) { |
1619 | reg = readl(regs + DIEPCTL(ep)); | |
1620 | reg &= ~DXEPCTL_MPS_MASK; | |
1621 | reg |= mpsval; | |
1622 | writel(reg, regs + DIEPCTL(ep)); | |
1623 | } else { | |
94cb8fd6 | 1624 | reg = readl(regs + DOEPCTL(ep)); |
47a1685f | 1625 | reg &= ~DXEPCTL_MPS_MASK; |
659ad60c | 1626 | reg |= mpsval; |
94cb8fd6 | 1627 | writel(reg, regs + DOEPCTL(ep)); |
659ad60c | 1628 | } |
5b7d70c6 BD |
1629 | |
1630 | return; | |
1631 | ||
1632 | bad_mps: | |
1633 | dev_err(hsotg->dev, "ep%d: bad mps of %d\n", ep, mps); | |
1634 | } | |
1635 | ||
9c39ddc6 AT |
1636 | /** |
1637 | * s3c_hsotg_txfifo_flush - flush Tx FIFO | |
1638 | * @hsotg: The driver state | |
1639 | * @idx: The index for the endpoint (0..15) | |
1640 | */ | |
941fcce4 | 1641 | static void s3c_hsotg_txfifo_flush(struct dwc2_hsotg *hsotg, unsigned int idx) |
9c39ddc6 AT |
1642 | { |
1643 | int timeout; | |
1644 | int val; | |
1645 | ||
47a1685f | 1646 | writel(GRSTCTL_TXFNUM(idx) | GRSTCTL_TXFFLSH, |
94cb8fd6 | 1647 | hsotg->regs + GRSTCTL); |
9c39ddc6 AT |
1648 | |
1649 | /* wait until the fifo is flushed */ | |
1650 | timeout = 100; | |
1651 | ||
1652 | while (1) { | |
94cb8fd6 | 1653 | val = readl(hsotg->regs + GRSTCTL); |
9c39ddc6 | 1654 | |
47a1685f | 1655 | if ((val & (GRSTCTL_TXFFLSH)) == 0) |
9c39ddc6 AT |
1656 | break; |
1657 | ||
1658 | if (--timeout == 0) { | |
1659 | dev_err(hsotg->dev, | |
1660 | "%s: timeout flushing fifo (GRSTCTL=%08x)\n", | |
1661 | __func__, val); | |
e0cbe595 | 1662 | break; |
9c39ddc6 AT |
1663 | } |
1664 | ||
1665 | udelay(1); | |
1666 | } | |
1667 | } | |
5b7d70c6 BD |
1668 | |
1669 | /** | |
1670 | * s3c_hsotg_trytx - check to see if anything needs transmitting | |
1671 | * @hsotg: The driver state | |
1672 | * @hs_ep: The driver endpoint to check. | |
1673 | * | |
1674 | * Check to see if there is a request that has data to send, and if so | |
1675 | * make an attempt to write data into the FIFO. | |
1676 | */ | |
941fcce4 | 1677 | static int s3c_hsotg_trytx(struct dwc2_hsotg *hsotg, |
5b7d70c6 BD |
1678 | struct s3c_hsotg_ep *hs_ep) |
1679 | { | |
1680 | struct s3c_hsotg_req *hs_req = hs_ep->req; | |
1681 | ||
afcf4169 RB |
1682 | if (!hs_ep->dir_in || !hs_req) { |
1683 | /** | |
1684 | * if request is not enqueued, we disable interrupts | |
1685 | * for endpoints, excepting ep0 | |
1686 | */ | |
1687 | if (hs_ep->index != 0) | |
1688 | s3c_hsotg_ctrl_epint(hsotg, hs_ep->index, | |
1689 | hs_ep->dir_in, 0); | |
5b7d70c6 | 1690 | return 0; |
afcf4169 | 1691 | } |
5b7d70c6 BD |
1692 | |
1693 | if (hs_req->req.actual < hs_req->req.length) { | |
1694 | dev_dbg(hsotg->dev, "trying to write more for ep%d\n", | |
1695 | hs_ep->index); | |
1696 | return s3c_hsotg_write_fifo(hsotg, hs_ep, hs_req); | |
1697 | } | |
1698 | ||
1699 | return 0; | |
1700 | } | |
1701 | ||
1702 | /** | |
1703 | * s3c_hsotg_complete_in - complete IN transfer | |
1704 | * @hsotg: The device state. | |
1705 | * @hs_ep: The endpoint that has just completed. | |
1706 | * | |
1707 | * An IN transfer has been completed, update the transfer's state and then | |
1708 | * call the relevant completion routines. | |
1709 | */ | |
941fcce4 | 1710 | static void s3c_hsotg_complete_in(struct dwc2_hsotg *hsotg, |
5b7d70c6 BD |
1711 | struct s3c_hsotg_ep *hs_ep) |
1712 | { | |
1713 | struct s3c_hsotg_req *hs_req = hs_ep->req; | |
94cb8fd6 | 1714 | u32 epsize = readl(hsotg->regs + DIEPTSIZ(hs_ep->index)); |
5b7d70c6 BD |
1715 | int size_left, size_done; |
1716 | ||
1717 | if (!hs_req) { | |
1718 | dev_dbg(hsotg->dev, "XferCompl but no req\n"); | |
1719 | return; | |
1720 | } | |
1721 | ||
d3ca0259 | 1722 | /* Finish ZLP handling for IN EP0 transactions */ |
fe0b94ab MYK |
1723 | if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_IN) { |
1724 | dev_dbg(hsotg->dev, "zlp packet sent\n"); | |
5ad1d316 | 1725 | s3c_hsotg_complete_request(hsotg, hs_ep, hs_req, 0); |
fe0b94ab | 1726 | s3c_hsotg_enqueue_setup(hsotg); |
d3ca0259 LM |
1727 | return; |
1728 | } | |
1729 | ||
8b9bc460 LM |
1730 | /* |
1731 | * Calculate the size of the transfer by checking how much is left | |
5b7d70c6 BD |
1732 | * in the endpoint size register and then working it out from |
1733 | * the amount we loaded for the transfer. | |
1734 | * | |
1735 | * We do this even for DMA, as the transfer may have incremented | |
1736 | * past the end of the buffer (DMA transfers are always 32bit | |
1737 | * aligned). | |
1738 | */ | |
1739 | ||
47a1685f | 1740 | size_left = DXEPTSIZ_XFERSIZE_GET(epsize); |
5b7d70c6 BD |
1741 | |
1742 | size_done = hs_ep->size_loaded - size_left; | |
1743 | size_done += hs_ep->last_load; | |
1744 | ||
1745 | if (hs_req->req.actual != size_done) | |
1746 | dev_dbg(hsotg->dev, "%s: adjusting size done %d => %d\n", | |
1747 | __func__, hs_req->req.actual, size_done); | |
1748 | ||
1749 | hs_req->req.actual = size_done; | |
d3ca0259 LM |
1750 | dev_dbg(hsotg->dev, "req->length:%d req->actual:%d req->zero:%d\n", |
1751 | hs_req->req.length, hs_req->req.actual, hs_req->req.zero); | |
1752 | ||
5b7d70c6 BD |
1753 | if (!size_left && hs_req->req.actual < hs_req->req.length) { |
1754 | dev_dbg(hsotg->dev, "%s trying more for req...\n", __func__); | |
1755 | s3c_hsotg_start_req(hsotg, hs_ep, hs_req, true); | |
fe0b94ab MYK |
1756 | return; |
1757 | } | |
1758 | ||
f71b5e25 MYK |
1759 | /* Zlp for all endpoints, for ep0 only in DATA IN stage */ |
1760 | if (hs_ep->sent_zlp) { | |
1761 | s3c_hsotg_program_zlp(hsotg, hs_ep); | |
1762 | hs_ep->sent_zlp = 0; | |
1763 | /* transfer will be completed on next complete interrupt */ | |
1764 | return; | |
1765 | } | |
1766 | ||
fe0b94ab MYK |
1767 | if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_DATA_IN) { |
1768 | /* Move to STATUS OUT */ | |
1769 | s3c_hsotg_ep0_zlp(hsotg, false); | |
1770 | return; | |
1771 | } | |
1772 | ||
1773 | s3c_hsotg_complete_request(hsotg, hs_ep, hs_req, 0); | |
5b7d70c6 BD |
1774 | } |
1775 | ||
1776 | /** | |
1777 | * s3c_hsotg_epint - handle an in/out endpoint interrupt | |
1778 | * @hsotg: The driver state | |
1779 | * @idx: The index for the endpoint (0..15) | |
1780 | * @dir_in: Set if this is an IN endpoint | |
1781 | * | |
1782 | * Process and clear any interrupt pending for an individual endpoint | |
8b9bc460 | 1783 | */ |
941fcce4 | 1784 | static void s3c_hsotg_epint(struct dwc2_hsotg *hsotg, unsigned int idx, |
5b7d70c6 BD |
1785 | int dir_in) |
1786 | { | |
c6f5c050 | 1787 | struct s3c_hsotg_ep *hs_ep = index_to_ep(hsotg, idx, dir_in); |
94cb8fd6 LM |
1788 | u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx); |
1789 | u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx); | |
1790 | u32 epsiz_reg = dir_in ? DIEPTSIZ(idx) : DOEPTSIZ(idx); | |
5b7d70c6 | 1791 | u32 ints; |
1479e841 | 1792 | u32 ctrl; |
5b7d70c6 BD |
1793 | |
1794 | ints = readl(hsotg->regs + epint_reg); | |
1479e841 | 1795 | ctrl = readl(hsotg->regs + epctl_reg); |
5b7d70c6 | 1796 | |
a3395f0d AT |
1797 | /* Clear endpoint interrupts */ |
1798 | writel(ints, hsotg->regs + epint_reg); | |
1799 | ||
c6f5c050 MYK |
1800 | if (!hs_ep) { |
1801 | dev_err(hsotg->dev, "%s:Interrupt for unconfigured ep%d(%s)\n", | |
1802 | __func__, idx, dir_in ? "in" : "out"); | |
1803 | return; | |
1804 | } | |
1805 | ||
5b7d70c6 BD |
1806 | dev_dbg(hsotg->dev, "%s: ep%d(%s) DxEPINT=0x%08x\n", |
1807 | __func__, idx, dir_in ? "in" : "out", ints); | |
1808 | ||
b787d755 MYK |
1809 | /* Don't process XferCompl interrupt if it is a setup packet */ |
1810 | if (idx == 0 && (ints & (DXEPINT_SETUP | DXEPINT_SETUP_RCVD))) | |
1811 | ints &= ~DXEPINT_XFERCOMPL; | |
1812 | ||
47a1685f | 1813 | if (ints & DXEPINT_XFERCOMPL) { |
1479e841 | 1814 | if (hs_ep->isochronous && hs_ep->interval == 1) { |
47a1685f DN |
1815 | if (ctrl & DXEPCTL_EOFRNUM) |
1816 | ctrl |= DXEPCTL_SETEVENFR; | |
1479e841 | 1817 | else |
47a1685f | 1818 | ctrl |= DXEPCTL_SETODDFR; |
1479e841 RB |
1819 | writel(ctrl, hsotg->regs + epctl_reg); |
1820 | } | |
1821 | ||
5b7d70c6 | 1822 | dev_dbg(hsotg->dev, |
47a1685f | 1823 | "%s: XferCompl: DxEPCTL=0x%08x, DXEPTSIZ=%08x\n", |
5b7d70c6 BD |
1824 | __func__, readl(hsotg->regs + epctl_reg), |
1825 | readl(hsotg->regs + epsiz_reg)); | |
1826 | ||
8b9bc460 LM |
1827 | /* |
1828 | * we get OutDone from the FIFO, so we only need to look | |
1829 | * at completing IN requests here | |
1830 | */ | |
5b7d70c6 BD |
1831 | if (dir_in) { |
1832 | s3c_hsotg_complete_in(hsotg, hs_ep); | |
1833 | ||
c9a64ea8 | 1834 | if (idx == 0 && !hs_ep->req) |
5b7d70c6 BD |
1835 | s3c_hsotg_enqueue_setup(hsotg); |
1836 | } else if (using_dma(hsotg)) { | |
8b9bc460 LM |
1837 | /* |
1838 | * We're using DMA, we need to fire an OutDone here | |
1839 | * as we ignore the RXFIFO. | |
1840 | */ | |
5b7d70c6 | 1841 | |
fe0b94ab | 1842 | s3c_hsotg_handle_outdone(hsotg, idx); |
5b7d70c6 | 1843 | } |
5b7d70c6 BD |
1844 | } |
1845 | ||
47a1685f | 1846 | if (ints & DXEPINT_EPDISBLD) { |
5b7d70c6 | 1847 | dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__); |
5b7d70c6 | 1848 | |
9c39ddc6 AT |
1849 | if (dir_in) { |
1850 | int epctl = readl(hsotg->regs + epctl_reg); | |
1851 | ||
b203d0a2 | 1852 | s3c_hsotg_txfifo_flush(hsotg, hs_ep->fifo_index); |
9c39ddc6 | 1853 | |
47a1685f DN |
1854 | if ((epctl & DXEPCTL_STALL) && |
1855 | (epctl & DXEPCTL_EPTYPE_BULK)) { | |
94cb8fd6 | 1856 | int dctl = readl(hsotg->regs + DCTL); |
9c39ddc6 | 1857 | |
47a1685f | 1858 | dctl |= DCTL_CGNPINNAK; |
94cb8fd6 | 1859 | writel(dctl, hsotg->regs + DCTL); |
9c39ddc6 AT |
1860 | } |
1861 | } | |
1862 | } | |
1863 | ||
47a1685f | 1864 | if (ints & DXEPINT_AHBERR) |
5b7d70c6 | 1865 | dev_dbg(hsotg->dev, "%s: AHBErr\n", __func__); |
5b7d70c6 | 1866 | |
47a1685f | 1867 | if (ints & DXEPINT_SETUP) { /* Setup or Timeout */ |
5b7d70c6 BD |
1868 | dev_dbg(hsotg->dev, "%s: Setup/Timeout\n", __func__); |
1869 | ||
1870 | if (using_dma(hsotg) && idx == 0) { | |
8b9bc460 LM |
1871 | /* |
1872 | * this is the notification we've received a | |
5b7d70c6 BD |
1873 | * setup packet. In non-DMA mode we'd get this |
1874 | * from the RXFIFO, instead we need to process | |
8b9bc460 LM |
1875 | * the setup here. |
1876 | */ | |
5b7d70c6 BD |
1877 | |
1878 | if (dir_in) | |
1879 | WARN_ON_ONCE(1); | |
1880 | else | |
fe0b94ab | 1881 | s3c_hsotg_handle_outdone(hsotg, 0); |
5b7d70c6 | 1882 | } |
5b7d70c6 BD |
1883 | } |
1884 | ||
47a1685f | 1885 | if (ints & DXEPINT_BACK2BACKSETUP) |
5b7d70c6 | 1886 | dev_dbg(hsotg->dev, "%s: B2BSetup/INEPNakEff\n", __func__); |
5b7d70c6 | 1887 | |
1479e841 | 1888 | if (dir_in && !hs_ep->isochronous) { |
8b9bc460 | 1889 | /* not sure if this is important, but we'll clear it anyway */ |
47a1685f | 1890 | if (ints & DIEPMSK_INTKNTXFEMPMSK) { |
5b7d70c6 BD |
1891 | dev_dbg(hsotg->dev, "%s: ep%d: INTknTXFEmpMsk\n", |
1892 | __func__, idx); | |
5b7d70c6 BD |
1893 | } |
1894 | ||
1895 | /* this probably means something bad is happening */ | |
47a1685f | 1896 | if (ints & DIEPMSK_INTKNEPMISMSK) { |
5b7d70c6 BD |
1897 | dev_warn(hsotg->dev, "%s: ep%d: INTknEP\n", |
1898 | __func__, idx); | |
5b7d70c6 | 1899 | } |
10aebc77 BD |
1900 | |
1901 | /* FIFO has space or is empty (see GAHBCFG) */ | |
1902 | if (hsotg->dedicated_fifos && | |
47a1685f | 1903 | ints & DIEPMSK_TXFIFOEMPTY) { |
10aebc77 BD |
1904 | dev_dbg(hsotg->dev, "%s: ep%d: TxFIFOEmpty\n", |
1905 | __func__, idx); | |
70fa030f AT |
1906 | if (!using_dma(hsotg)) |
1907 | s3c_hsotg_trytx(hsotg, hs_ep); | |
10aebc77 | 1908 | } |
5b7d70c6 | 1909 | } |
5b7d70c6 BD |
1910 | } |
1911 | ||
1912 | /** | |
1913 | * s3c_hsotg_irq_enumdone - Handle EnumDone interrupt (enumeration done) | |
1914 | * @hsotg: The device state. | |
1915 | * | |
1916 | * Handle updating the device settings after the enumeration phase has | |
1917 | * been completed. | |
8b9bc460 | 1918 | */ |
941fcce4 | 1919 | static void s3c_hsotg_irq_enumdone(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 1920 | { |
94cb8fd6 | 1921 | u32 dsts = readl(hsotg->regs + DSTS); |
9b2667f1 | 1922 | int ep0_mps = 0, ep_mps = 8; |
5b7d70c6 | 1923 | |
8b9bc460 LM |
1924 | /* |
1925 | * This should signal the finish of the enumeration phase | |
5b7d70c6 | 1926 | * of the USB handshaking, so we should now know what rate |
8b9bc460 LM |
1927 | * we connected at. |
1928 | */ | |
5b7d70c6 BD |
1929 | |
1930 | dev_dbg(hsotg->dev, "EnumDone (DSTS=0x%08x)\n", dsts); | |
1931 | ||
8b9bc460 LM |
1932 | /* |
1933 | * note, since we're limited by the size of transfer on EP0, and | |
5b7d70c6 | 1934 | * it seems IN transfers must be a even number of packets we do |
8b9bc460 LM |
1935 | * not advertise a 64byte MPS on EP0. |
1936 | */ | |
5b7d70c6 BD |
1937 | |
1938 | /* catch both EnumSpd_FS and EnumSpd_FS48 */ | |
47a1685f DN |
1939 | switch (dsts & DSTS_ENUMSPD_MASK) { |
1940 | case DSTS_ENUMSPD_FS: | |
1941 | case DSTS_ENUMSPD_FS48: | |
5b7d70c6 | 1942 | hsotg->gadget.speed = USB_SPEED_FULL; |
5b7d70c6 | 1943 | ep0_mps = EP0_MPS_LIMIT; |
295538ff | 1944 | ep_mps = 1023; |
5b7d70c6 BD |
1945 | break; |
1946 | ||
47a1685f | 1947 | case DSTS_ENUMSPD_HS: |
5b7d70c6 | 1948 | hsotg->gadget.speed = USB_SPEED_HIGH; |
5b7d70c6 | 1949 | ep0_mps = EP0_MPS_LIMIT; |
295538ff | 1950 | ep_mps = 1024; |
5b7d70c6 BD |
1951 | break; |
1952 | ||
47a1685f | 1953 | case DSTS_ENUMSPD_LS: |
5b7d70c6 | 1954 | hsotg->gadget.speed = USB_SPEED_LOW; |
8b9bc460 LM |
1955 | /* |
1956 | * note, we don't actually support LS in this driver at the | |
5b7d70c6 BD |
1957 | * moment, and the documentation seems to imply that it isn't |
1958 | * supported by the PHYs on some of the devices. | |
1959 | */ | |
1960 | break; | |
1961 | } | |
e538dfda MN |
1962 | dev_info(hsotg->dev, "new device is %s\n", |
1963 | usb_speed_string(hsotg->gadget.speed)); | |
5b7d70c6 | 1964 | |
8b9bc460 LM |
1965 | /* |
1966 | * we should now know the maximum packet size for an | |
1967 | * endpoint, so set the endpoints to a default value. | |
1968 | */ | |
5b7d70c6 BD |
1969 | |
1970 | if (ep0_mps) { | |
1971 | int i; | |
c6f5c050 MYK |
1972 | /* Initialize ep0 for both in and out directions */ |
1973 | s3c_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 1); | |
1974 | s3c_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 0); | |
1975 | for (i = 1; i < hsotg->num_of_eps; i++) { | |
1976 | if (hsotg->eps_in[i]) | |
1977 | s3c_hsotg_set_ep_maxpacket(hsotg, i, ep_mps, 1); | |
1978 | if (hsotg->eps_out[i]) | |
1979 | s3c_hsotg_set_ep_maxpacket(hsotg, i, ep_mps, 0); | |
1980 | } | |
5b7d70c6 BD |
1981 | } |
1982 | ||
1983 | /* ensure after enumeration our EP0 is active */ | |
1984 | ||
1985 | s3c_hsotg_enqueue_setup(hsotg); | |
1986 | ||
1987 | dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n", | |
94cb8fd6 LM |
1988 | readl(hsotg->regs + DIEPCTL0), |
1989 | readl(hsotg->regs + DOEPCTL0)); | |
5b7d70c6 BD |
1990 | } |
1991 | ||
1992 | /** | |
1993 | * kill_all_requests - remove all requests from the endpoint's queue | |
1994 | * @hsotg: The device state. | |
1995 | * @ep: The endpoint the requests may be on. | |
1996 | * @result: The result code to use. | |
5b7d70c6 BD |
1997 | * |
1998 | * Go through the requests on the given endpoint and mark them | |
1999 | * completed with the given result code. | |
2000 | */ | |
941fcce4 | 2001 | static void kill_all_requests(struct dwc2_hsotg *hsotg, |
5b7d70c6 | 2002 | struct s3c_hsotg_ep *ep, |
6b448af4 | 2003 | int result) |
5b7d70c6 BD |
2004 | { |
2005 | struct s3c_hsotg_req *req, *treq; | |
b203d0a2 | 2006 | unsigned size; |
5b7d70c6 | 2007 | |
6b448af4 | 2008 | ep->req = NULL; |
5b7d70c6 | 2009 | |
6b448af4 | 2010 | list_for_each_entry_safe(req, treq, &ep->queue, queue) |
5b7d70c6 BD |
2011 | s3c_hsotg_complete_request(hsotg, ep, req, |
2012 | result); | |
6b448af4 | 2013 | |
b203d0a2 RB |
2014 | if (!hsotg->dedicated_fifos) |
2015 | return; | |
2016 | size = (readl(hsotg->regs + DTXFSTS(ep->index)) & 0xffff) * 4; | |
2017 | if (size < ep->fifo_size) | |
2018 | s3c_hsotg_txfifo_flush(hsotg, ep->fifo_index); | |
5b7d70c6 BD |
2019 | } |
2020 | ||
5b7d70c6 | 2021 | /** |
5e891342 | 2022 | * s3c_hsotg_disconnect - disconnect service |
5b7d70c6 BD |
2023 | * @hsotg: The device state. |
2024 | * | |
5e891342 LM |
2025 | * The device has been disconnected. Remove all current |
2026 | * transactions and signal the gadget driver that this | |
2027 | * has happened. | |
8b9bc460 | 2028 | */ |
4ace06e8 | 2029 | void s3c_hsotg_disconnect(struct dwc2_hsotg *hsotg) |
5b7d70c6 BD |
2030 | { |
2031 | unsigned ep; | |
2032 | ||
4ace06e8 MS |
2033 | if (!hsotg->connected) |
2034 | return; | |
2035 | ||
2036 | hsotg->connected = 0; | |
c6f5c050 MYK |
2037 | |
2038 | for (ep = 0; ep < hsotg->num_of_eps; ep++) { | |
2039 | if (hsotg->eps_in[ep]) | |
2040 | kill_all_requests(hsotg, hsotg->eps_in[ep], | |
2041 | -ESHUTDOWN); | |
2042 | if (hsotg->eps_out[ep]) | |
2043 | kill_all_requests(hsotg, hsotg->eps_out[ep], | |
2044 | -ESHUTDOWN); | |
2045 | } | |
5b7d70c6 BD |
2046 | |
2047 | call_gadget(hsotg, disconnect); | |
2048 | } | |
4ace06e8 | 2049 | EXPORT_SYMBOL_GPL(s3c_hsotg_disconnect); |
5b7d70c6 BD |
2050 | |
2051 | /** | |
2052 | * s3c_hsotg_irq_fifoempty - TX FIFO empty interrupt handler | |
2053 | * @hsotg: The device state: | |
2054 | * @periodic: True if this is a periodic FIFO interrupt | |
2055 | */ | |
941fcce4 | 2056 | static void s3c_hsotg_irq_fifoempty(struct dwc2_hsotg *hsotg, bool periodic) |
5b7d70c6 BD |
2057 | { |
2058 | struct s3c_hsotg_ep *ep; | |
2059 | int epno, ret; | |
2060 | ||
2061 | /* look through for any more data to transmit */ | |
b3f489b2 | 2062 | for (epno = 0; epno < hsotg->num_of_eps; epno++) { |
c6f5c050 MYK |
2063 | ep = index_to_ep(hsotg, epno, 1); |
2064 | ||
2065 | if (!ep) | |
2066 | continue; | |
5b7d70c6 BD |
2067 | |
2068 | if (!ep->dir_in) | |
2069 | continue; | |
2070 | ||
2071 | if ((periodic && !ep->periodic) || | |
2072 | (!periodic && ep->periodic)) | |
2073 | continue; | |
2074 | ||
2075 | ret = s3c_hsotg_trytx(hsotg, ep); | |
2076 | if (ret < 0) | |
2077 | break; | |
2078 | } | |
2079 | } | |
2080 | ||
5b7d70c6 | 2081 | /* IRQ flags which will trigger a retry around the IRQ loop */ |
47a1685f DN |
2082 | #define IRQ_RETRY_MASK (GINTSTS_NPTXFEMP | \ |
2083 | GINTSTS_PTXFEMP | \ | |
2084 | GINTSTS_RXFLVL) | |
5b7d70c6 | 2085 | |
308d734e LM |
2086 | /** |
2087 | * s3c_hsotg_corereset - issue softreset to the core | |
2088 | * @hsotg: The device state | |
2089 | * | |
2090 | * Issue a soft reset to the core, and await the core finishing it. | |
8b9bc460 | 2091 | */ |
941fcce4 | 2092 | static int s3c_hsotg_corereset(struct dwc2_hsotg *hsotg) |
308d734e LM |
2093 | { |
2094 | int timeout; | |
2095 | u32 grstctl; | |
2096 | ||
2097 | dev_dbg(hsotg->dev, "resetting core\n"); | |
2098 | ||
2099 | /* issue soft reset */ | |
47a1685f | 2100 | writel(GRSTCTL_CSFTRST, hsotg->regs + GRSTCTL); |
308d734e | 2101 | |
2868fea2 | 2102 | timeout = 10000; |
308d734e | 2103 | do { |
94cb8fd6 | 2104 | grstctl = readl(hsotg->regs + GRSTCTL); |
47a1685f | 2105 | } while ((grstctl & GRSTCTL_CSFTRST) && timeout-- > 0); |
308d734e | 2106 | |
47a1685f | 2107 | if (grstctl & GRSTCTL_CSFTRST) { |
308d734e LM |
2108 | dev_err(hsotg->dev, "Failed to get CSftRst asserted\n"); |
2109 | return -EINVAL; | |
2110 | } | |
2111 | ||
2868fea2 | 2112 | timeout = 10000; |
308d734e LM |
2113 | |
2114 | while (1) { | |
94cb8fd6 | 2115 | u32 grstctl = readl(hsotg->regs + GRSTCTL); |
308d734e LM |
2116 | |
2117 | if (timeout-- < 0) { | |
2118 | dev_info(hsotg->dev, | |
2119 | "%s: reset failed, GRSTCTL=%08x\n", | |
2120 | __func__, grstctl); | |
2121 | return -ETIMEDOUT; | |
2122 | } | |
2123 | ||
47a1685f | 2124 | if (!(grstctl & GRSTCTL_AHBIDLE)) |
308d734e LM |
2125 | continue; |
2126 | ||
2127 | break; /* reset done */ | |
2128 | } | |
2129 | ||
2130 | dev_dbg(hsotg->dev, "reset successful\n"); | |
2131 | return 0; | |
2132 | } | |
2133 | ||
8b9bc460 LM |
2134 | /** |
2135 | * s3c_hsotg_core_init - issue softreset to the core | |
2136 | * @hsotg: The device state | |
2137 | * | |
2138 | * Issue a soft reset to the core, and await the core finishing it. | |
2139 | */ | |
510ffaa4 | 2140 | void s3c_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg) |
308d734e LM |
2141 | { |
2142 | s3c_hsotg_corereset(hsotg); | |
2143 | ||
2144 | /* | |
2145 | * we must now enable ep0 ready for host detection and then | |
2146 | * set configuration. | |
2147 | */ | |
2148 | ||
2149 | /* set the PLL on, remove the HNP/SRP and set the PHY */ | |
47a1685f | 2150 | writel(hsotg->phyif | GUSBCFG_TOUTCAL(7) | |
94cb8fd6 | 2151 | (0x5 << 10), hsotg->regs + GUSBCFG); |
308d734e LM |
2152 | |
2153 | s3c_hsotg_init_fifo(hsotg); | |
2154 | ||
47a1685f | 2155 | __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON); |
308d734e | 2156 | |
47a1685f | 2157 | writel(1 << 18 | DCFG_DEVSPD_HS, hsotg->regs + DCFG); |
308d734e LM |
2158 | |
2159 | /* Clear any pending OTG interrupts */ | |
94cb8fd6 | 2160 | writel(0xffffffff, hsotg->regs + GOTGINT); |
308d734e LM |
2161 | |
2162 | /* Clear any pending interrupts */ | |
94cb8fd6 | 2163 | writel(0xffffffff, hsotg->regs + GINTSTS); |
308d734e | 2164 | |
47a1685f DN |
2165 | writel(GINTSTS_ERLYSUSP | GINTSTS_SESSREQINT | |
2166 | GINTSTS_GOUTNAKEFF | GINTSTS_GINNAKEFF | | |
2167 | GINTSTS_CONIDSTSCHNG | GINTSTS_USBRST | | |
2168 | GINTSTS_ENUMDONE | GINTSTS_OTGINT | | |
2169 | GINTSTS_USBSUSP | GINTSTS_WKUPINT, | |
2170 | hsotg->regs + GINTMSK); | |
308d734e LM |
2171 | |
2172 | if (using_dma(hsotg)) | |
47a1685f | 2173 | writel(GAHBCFG_GLBL_INTR_EN | GAHBCFG_DMA_EN | |
5f05048e | 2174 | (GAHBCFG_HBSTLEN_INCR4 << GAHBCFG_HBSTLEN_SHIFT), |
94cb8fd6 | 2175 | hsotg->regs + GAHBCFG); |
308d734e | 2176 | else |
47a1685f DN |
2177 | writel(((hsotg->dedicated_fifos) ? (GAHBCFG_NP_TXF_EMP_LVL | |
2178 | GAHBCFG_P_TXF_EMP_LVL) : 0) | | |
2179 | GAHBCFG_GLBL_INTR_EN, | |
8acc8296 | 2180 | hsotg->regs + GAHBCFG); |
308d734e LM |
2181 | |
2182 | /* | |
8acc8296 RB |
2183 | * If INTknTXFEmpMsk is enabled, it's important to disable ep interrupts |
2184 | * when we have no data to transfer. Otherwise we get being flooded by | |
2185 | * interrupts. | |
308d734e LM |
2186 | */ |
2187 | ||
6ff2e832 MYK |
2188 | writel(((hsotg->dedicated_fifos && !using_dma(hsotg)) ? |
2189 | DIEPMSK_TXFIFOEMPTY | DIEPMSK_INTKNTXFEMPMSK : 0) | | |
47a1685f DN |
2190 | DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK | |
2191 | DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK | | |
2192 | DIEPMSK_INTKNEPMISMSK, | |
2193 | hsotg->regs + DIEPMSK); | |
308d734e LM |
2194 | |
2195 | /* | |
2196 | * don't need XferCompl, we get that from RXFIFO in slave mode. In | |
2197 | * DMA mode we may need this. | |
2198 | */ | |
47a1685f DN |
2199 | writel((using_dma(hsotg) ? (DIEPMSK_XFERCOMPLMSK | |
2200 | DIEPMSK_TIMEOUTMSK) : 0) | | |
2201 | DOEPMSK_EPDISBLDMSK | DOEPMSK_AHBERRMSK | | |
2202 | DOEPMSK_SETUPMSK, | |
2203 | hsotg->regs + DOEPMSK); | |
308d734e | 2204 | |
94cb8fd6 | 2205 | writel(0, hsotg->regs + DAINTMSK); |
308d734e LM |
2206 | |
2207 | dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n", | |
94cb8fd6 LM |
2208 | readl(hsotg->regs + DIEPCTL0), |
2209 | readl(hsotg->regs + DOEPCTL0)); | |
308d734e LM |
2210 | |
2211 | /* enable in and out endpoint interrupts */ | |
47a1685f | 2212 | s3c_hsotg_en_gsint(hsotg, GINTSTS_OEPINT | GINTSTS_IEPINT); |
308d734e LM |
2213 | |
2214 | /* | |
2215 | * Enable the RXFIFO when in slave mode, as this is how we collect | |
2216 | * the data. In DMA mode, we get events from the FIFO but also | |
2217 | * things we cannot process, so do not use it. | |
2218 | */ | |
2219 | if (!using_dma(hsotg)) | |
47a1685f | 2220 | s3c_hsotg_en_gsint(hsotg, GINTSTS_RXFLVL); |
308d734e LM |
2221 | |
2222 | /* Enable interrupts for EP0 in and out */ | |
2223 | s3c_hsotg_ctrl_epint(hsotg, 0, 0, 1); | |
2224 | s3c_hsotg_ctrl_epint(hsotg, 0, 1, 1); | |
2225 | ||
47a1685f | 2226 | __orr32(hsotg->regs + DCTL, DCTL_PWRONPRGDONE); |
308d734e | 2227 | udelay(10); /* see openiboot */ |
47a1685f | 2228 | __bic32(hsotg->regs + DCTL, DCTL_PWRONPRGDONE); |
308d734e | 2229 | |
94cb8fd6 | 2230 | dev_dbg(hsotg->dev, "DCTL=0x%08x\n", readl(hsotg->regs + DCTL)); |
308d734e LM |
2231 | |
2232 | /* | |
94cb8fd6 | 2233 | * DxEPCTL_USBActEp says RO in manual, but seems to be set by |
308d734e LM |
2234 | * writing to the EPCTL register.. |
2235 | */ | |
2236 | ||
2237 | /* set to read 1 8byte packet */ | |
47a1685f DN |
2238 | writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) | |
2239 | DXEPTSIZ_XFERSIZE(8), hsotg->regs + DOEPTSIZ0); | |
308d734e | 2240 | |
c6f5c050 | 2241 | writel(s3c_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) | |
47a1685f DN |
2242 | DXEPCTL_CNAK | DXEPCTL_EPENA | |
2243 | DXEPCTL_USBACTEP, | |
94cb8fd6 | 2244 | hsotg->regs + DOEPCTL0); |
308d734e LM |
2245 | |
2246 | /* enable, but don't activate EP0in */ | |
c6f5c050 | 2247 | writel(s3c_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) | |
47a1685f | 2248 | DXEPCTL_USBACTEP, hsotg->regs + DIEPCTL0); |
308d734e LM |
2249 | |
2250 | s3c_hsotg_enqueue_setup(hsotg); | |
2251 | ||
2252 | dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n", | |
94cb8fd6 LM |
2253 | readl(hsotg->regs + DIEPCTL0), |
2254 | readl(hsotg->regs + DOEPCTL0)); | |
308d734e LM |
2255 | |
2256 | /* clear global NAKs */ | |
ad38dc5d | 2257 | writel(DCTL_CGOUTNAK | DCTL_CGNPINNAK | DCTL_SFTDISCON, |
94cb8fd6 | 2258 | hsotg->regs + DCTL); |
308d734e LM |
2259 | |
2260 | /* must be at-least 3ms to allow bus to see disconnect */ | |
2261 | mdelay(3); | |
2262 | ||
ac3c81f3 | 2263 | hsotg->last_rst = jiffies; |
ad38dc5d MS |
2264 | } |
2265 | ||
941fcce4 | 2266 | static void s3c_hsotg_core_disconnect(struct dwc2_hsotg *hsotg) |
ad38dc5d MS |
2267 | { |
2268 | /* set the soft-disconnect bit */ | |
2269 | __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON); | |
2270 | } | |
ac3c81f3 | 2271 | |
510ffaa4 | 2272 | void s3c_hsotg_core_connect(struct dwc2_hsotg *hsotg) |
ad38dc5d | 2273 | { |
308d734e | 2274 | /* remove the soft-disconnect and let's go */ |
47a1685f | 2275 | __bic32(hsotg->regs + DCTL, DCTL_SFTDISCON); |
308d734e LM |
2276 | } |
2277 | ||
5b7d70c6 BD |
2278 | /** |
2279 | * s3c_hsotg_irq - handle device interrupt | |
2280 | * @irq: The IRQ number triggered | |
2281 | * @pw: The pw value when registered the handler. | |
2282 | */ | |
2283 | static irqreturn_t s3c_hsotg_irq(int irq, void *pw) | |
2284 | { | |
941fcce4 | 2285 | struct dwc2_hsotg *hsotg = pw; |
5b7d70c6 BD |
2286 | int retry_count = 8; |
2287 | u32 gintsts; | |
2288 | u32 gintmsk; | |
2289 | ||
5ad1d316 | 2290 | spin_lock(&hsotg->lock); |
5b7d70c6 | 2291 | irq_retry: |
94cb8fd6 LM |
2292 | gintsts = readl(hsotg->regs + GINTSTS); |
2293 | gintmsk = readl(hsotg->regs + GINTMSK); | |
5b7d70c6 BD |
2294 | |
2295 | dev_dbg(hsotg->dev, "%s: %08x %08x (%08x) retry %d\n", | |
2296 | __func__, gintsts, gintsts & gintmsk, gintmsk, retry_count); | |
2297 | ||
2298 | gintsts &= gintmsk; | |
2299 | ||
47a1685f DN |
2300 | if (gintsts & GINTSTS_ENUMDONE) { |
2301 | writel(GINTSTS_ENUMDONE, hsotg->regs + GINTSTS); | |
a3395f0d AT |
2302 | |
2303 | s3c_hsotg_irq_enumdone(hsotg); | |
4ace06e8 | 2304 | hsotg->connected = 1; |
5b7d70c6 BD |
2305 | } |
2306 | ||
47a1685f | 2307 | if (gintsts & (GINTSTS_OEPINT | GINTSTS_IEPINT)) { |
94cb8fd6 | 2308 | u32 daint = readl(hsotg->regs + DAINT); |
7e804650 RB |
2309 | u32 daintmsk = readl(hsotg->regs + DAINTMSK); |
2310 | u32 daint_out, daint_in; | |
5b7d70c6 BD |
2311 | int ep; |
2312 | ||
7e804650 | 2313 | daint &= daintmsk; |
47a1685f DN |
2314 | daint_out = daint >> DAINT_OUTEP_SHIFT; |
2315 | daint_in = daint & ~(daint_out << DAINT_OUTEP_SHIFT); | |
7e804650 | 2316 | |
5b7d70c6 BD |
2317 | dev_dbg(hsotg->dev, "%s: daint=%08x\n", __func__, daint); |
2318 | ||
cec87f1d MYK |
2319 | for (ep = 0; ep < hsotg->num_of_eps && daint_out; |
2320 | ep++, daint_out >>= 1) { | |
5b7d70c6 BD |
2321 | if (daint_out & 1) |
2322 | s3c_hsotg_epint(hsotg, ep, 0); | |
2323 | } | |
2324 | ||
cec87f1d MYK |
2325 | for (ep = 0; ep < hsotg->num_of_eps && daint_in; |
2326 | ep++, daint_in >>= 1) { | |
5b7d70c6 BD |
2327 | if (daint_in & 1) |
2328 | s3c_hsotg_epint(hsotg, ep, 1); | |
2329 | } | |
5b7d70c6 BD |
2330 | } |
2331 | ||
47a1685f | 2332 | if (gintsts & GINTSTS_USBRST) { |
12a1f4dc | 2333 | |
94cb8fd6 | 2334 | u32 usb_status = readl(hsotg->regs + GOTGCTL); |
12a1f4dc | 2335 | |
9599815d | 2336 | dev_dbg(hsotg->dev, "%s: USBRst\n", __func__); |
5b7d70c6 | 2337 | dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n", |
94cb8fd6 | 2338 | readl(hsotg->regs + GNPTXSTS)); |
5b7d70c6 | 2339 | |
47a1685f | 2340 | writel(GINTSTS_USBRST, hsotg->regs + GINTSTS); |
a3395f0d | 2341 | |
94cb8fd6 | 2342 | if (usb_status & GOTGCTL_BSESVLD) { |
12a1f4dc LM |
2343 | if (time_after(jiffies, hsotg->last_rst + |
2344 | msecs_to_jiffies(200))) { | |
5b7d70c6 | 2345 | |
c6f5c050 | 2346 | kill_all_requests(hsotg, hsotg->eps_out[0], |
6b448af4 | 2347 | -ECONNRESET); |
5b7d70c6 | 2348 | |
ad38dc5d MS |
2349 | s3c_hsotg_core_init_disconnected(hsotg); |
2350 | s3c_hsotg_core_connect(hsotg); | |
12a1f4dc LM |
2351 | } |
2352 | } | |
5b7d70c6 BD |
2353 | } |
2354 | ||
2355 | /* check both FIFOs */ | |
2356 | ||
47a1685f | 2357 | if (gintsts & GINTSTS_NPTXFEMP) { |
5b7d70c6 BD |
2358 | dev_dbg(hsotg->dev, "NPTxFEmp\n"); |
2359 | ||
8b9bc460 LM |
2360 | /* |
2361 | * Disable the interrupt to stop it happening again | |
5b7d70c6 | 2362 | * unless one of these endpoint routines decides that |
8b9bc460 LM |
2363 | * it needs re-enabling |
2364 | */ | |
5b7d70c6 | 2365 | |
47a1685f | 2366 | s3c_hsotg_disable_gsint(hsotg, GINTSTS_NPTXFEMP); |
5b7d70c6 | 2367 | s3c_hsotg_irq_fifoempty(hsotg, false); |
5b7d70c6 BD |
2368 | } |
2369 | ||
47a1685f | 2370 | if (gintsts & GINTSTS_PTXFEMP) { |
5b7d70c6 BD |
2371 | dev_dbg(hsotg->dev, "PTxFEmp\n"); |
2372 | ||
94cb8fd6 | 2373 | /* See note in GINTSTS_NPTxFEmp */ |
5b7d70c6 | 2374 | |
47a1685f | 2375 | s3c_hsotg_disable_gsint(hsotg, GINTSTS_PTXFEMP); |
5b7d70c6 | 2376 | s3c_hsotg_irq_fifoempty(hsotg, true); |
5b7d70c6 BD |
2377 | } |
2378 | ||
47a1685f | 2379 | if (gintsts & GINTSTS_RXFLVL) { |
8b9bc460 LM |
2380 | /* |
2381 | * note, since GINTSTS_RxFLvl doubles as FIFO-not-empty, | |
5b7d70c6 | 2382 | * we need to retry s3c_hsotg_handle_rx if this is still |
8b9bc460 LM |
2383 | * set. |
2384 | */ | |
5b7d70c6 BD |
2385 | |
2386 | s3c_hsotg_handle_rx(hsotg); | |
5b7d70c6 BD |
2387 | } |
2388 | ||
47a1685f | 2389 | if (gintsts & GINTSTS_ERLYSUSP) { |
94cb8fd6 | 2390 | dev_dbg(hsotg->dev, "GINTSTS_ErlySusp\n"); |
47a1685f | 2391 | writel(GINTSTS_ERLYSUSP, hsotg->regs + GINTSTS); |
5b7d70c6 BD |
2392 | } |
2393 | ||
8b9bc460 LM |
2394 | /* |
2395 | * these next two seem to crop-up occasionally causing the core | |
5b7d70c6 | 2396 | * to shutdown the USB transfer, so try clearing them and logging |
8b9bc460 LM |
2397 | * the occurrence. |
2398 | */ | |
5b7d70c6 | 2399 | |
47a1685f | 2400 | if (gintsts & GINTSTS_GOUTNAKEFF) { |
5b7d70c6 BD |
2401 | dev_info(hsotg->dev, "GOUTNakEff triggered\n"); |
2402 | ||
47a1685f | 2403 | writel(DCTL_CGOUTNAK, hsotg->regs + DCTL); |
a3395f0d AT |
2404 | |
2405 | s3c_hsotg_dump(hsotg); | |
5b7d70c6 BD |
2406 | } |
2407 | ||
47a1685f | 2408 | if (gintsts & GINTSTS_GINNAKEFF) { |
5b7d70c6 BD |
2409 | dev_info(hsotg->dev, "GINNakEff triggered\n"); |
2410 | ||
47a1685f | 2411 | writel(DCTL_CGNPINNAK, hsotg->regs + DCTL); |
a3395f0d AT |
2412 | |
2413 | s3c_hsotg_dump(hsotg); | |
5b7d70c6 BD |
2414 | } |
2415 | ||
8b9bc460 LM |
2416 | /* |
2417 | * if we've had fifo events, we should try and go around the | |
2418 | * loop again to see if there's any point in returning yet. | |
2419 | */ | |
5b7d70c6 BD |
2420 | |
2421 | if (gintsts & IRQ_RETRY_MASK && --retry_count > 0) | |
2422 | goto irq_retry; | |
2423 | ||
5ad1d316 LM |
2424 | spin_unlock(&hsotg->lock); |
2425 | ||
5b7d70c6 BD |
2426 | return IRQ_HANDLED; |
2427 | } | |
2428 | ||
2429 | /** | |
2430 | * s3c_hsotg_ep_enable - enable the given endpoint | |
2431 | * @ep: The USB endpint to configure | |
2432 | * @desc: The USB endpoint descriptor to configure with. | |
2433 | * | |
2434 | * This is called from the USB gadget code's usb_ep_enable(). | |
8b9bc460 | 2435 | */ |
5b7d70c6 BD |
2436 | static int s3c_hsotg_ep_enable(struct usb_ep *ep, |
2437 | const struct usb_endpoint_descriptor *desc) | |
2438 | { | |
2439 | struct s3c_hsotg_ep *hs_ep = our_ep(ep); | |
941fcce4 | 2440 | struct dwc2_hsotg *hsotg = hs_ep->parent; |
5b7d70c6 BD |
2441 | unsigned long flags; |
2442 | int index = hs_ep->index; | |
2443 | u32 epctrl_reg; | |
2444 | u32 epctrl; | |
2445 | u32 mps; | |
2446 | int dir_in; | |
b203d0a2 | 2447 | int i, val, size; |
19c190f9 | 2448 | int ret = 0; |
5b7d70c6 BD |
2449 | |
2450 | dev_dbg(hsotg->dev, | |
2451 | "%s: ep %s: a 0x%02x, attr 0x%02x, mps 0x%04x, intr %d\n", | |
2452 | __func__, ep->name, desc->bEndpointAddress, desc->bmAttributes, | |
2453 | desc->wMaxPacketSize, desc->bInterval); | |
2454 | ||
2455 | /* not to be called for EP0 */ | |
2456 | WARN_ON(index == 0); | |
2457 | ||
2458 | dir_in = (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) ? 1 : 0; | |
2459 | if (dir_in != hs_ep->dir_in) { | |
2460 | dev_err(hsotg->dev, "%s: direction mismatch!\n", __func__); | |
2461 | return -EINVAL; | |
2462 | } | |
2463 | ||
29cc8897 | 2464 | mps = usb_endpoint_maxp(desc); |
5b7d70c6 BD |
2465 | |
2466 | /* note, we handle this here instead of s3c_hsotg_set_ep_maxpacket */ | |
2467 | ||
94cb8fd6 | 2468 | epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index); |
5b7d70c6 BD |
2469 | epctrl = readl(hsotg->regs + epctrl_reg); |
2470 | ||
2471 | dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x from 0x%08x\n", | |
2472 | __func__, epctrl, epctrl_reg); | |
2473 | ||
22258f49 | 2474 | spin_lock_irqsave(&hsotg->lock, flags); |
5b7d70c6 | 2475 | |
47a1685f DN |
2476 | epctrl &= ~(DXEPCTL_EPTYPE_MASK | DXEPCTL_MPS_MASK); |
2477 | epctrl |= DXEPCTL_MPS(mps); | |
5b7d70c6 | 2478 | |
8b9bc460 LM |
2479 | /* |
2480 | * mark the endpoint as active, otherwise the core may ignore | |
2481 | * transactions entirely for this endpoint | |
2482 | */ | |
47a1685f | 2483 | epctrl |= DXEPCTL_USBACTEP; |
5b7d70c6 | 2484 | |
8b9bc460 LM |
2485 | /* |
2486 | * set the NAK status on the endpoint, otherwise we might try and | |
5b7d70c6 BD |
2487 | * do something with data that we've yet got a request to process |
2488 | * since the RXFIFO will take data for an endpoint even if the | |
2489 | * size register hasn't been set. | |
2490 | */ | |
2491 | ||
47a1685f | 2492 | epctrl |= DXEPCTL_SNAK; |
5b7d70c6 BD |
2493 | |
2494 | /* update the endpoint state */ | |
c6f5c050 | 2495 | s3c_hsotg_set_ep_maxpacket(hsotg, hs_ep->index, mps, dir_in); |
5b7d70c6 BD |
2496 | |
2497 | /* default, set to non-periodic */ | |
1479e841 | 2498 | hs_ep->isochronous = 0; |
5b7d70c6 | 2499 | hs_ep->periodic = 0; |
a18ed7b0 | 2500 | hs_ep->halted = 0; |
1479e841 | 2501 | hs_ep->interval = desc->bInterval; |
5b7d70c6 | 2502 | |
4fca54aa RB |
2503 | if (hs_ep->interval > 1 && hs_ep->mc > 1) |
2504 | dev_err(hsotg->dev, "MC > 1 when interval is not 1\n"); | |
2505 | ||
5b7d70c6 BD |
2506 | switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) { |
2507 | case USB_ENDPOINT_XFER_ISOC: | |
47a1685f DN |
2508 | epctrl |= DXEPCTL_EPTYPE_ISO; |
2509 | epctrl |= DXEPCTL_SETEVENFR; | |
1479e841 RB |
2510 | hs_ep->isochronous = 1; |
2511 | if (dir_in) | |
2512 | hs_ep->periodic = 1; | |
2513 | break; | |
5b7d70c6 BD |
2514 | |
2515 | case USB_ENDPOINT_XFER_BULK: | |
47a1685f | 2516 | epctrl |= DXEPCTL_EPTYPE_BULK; |
5b7d70c6 BD |
2517 | break; |
2518 | ||
2519 | case USB_ENDPOINT_XFER_INT: | |
b203d0a2 | 2520 | if (dir_in) |
5b7d70c6 | 2521 | hs_ep->periodic = 1; |
5b7d70c6 | 2522 | |
47a1685f | 2523 | epctrl |= DXEPCTL_EPTYPE_INTERRUPT; |
5b7d70c6 BD |
2524 | break; |
2525 | ||
2526 | case USB_ENDPOINT_XFER_CONTROL: | |
47a1685f | 2527 | epctrl |= DXEPCTL_EPTYPE_CONTROL; |
5b7d70c6 BD |
2528 | break; |
2529 | } | |
2530 | ||
8b9bc460 LM |
2531 | /* |
2532 | * if the hardware has dedicated fifos, we must give each IN EP | |
10aebc77 BD |
2533 | * a unique tx-fifo even if it is non-periodic. |
2534 | */ | |
b203d0a2 RB |
2535 | if (dir_in && hsotg->dedicated_fifos) { |
2536 | size = hs_ep->ep.maxpacket*hs_ep->mc; | |
5f2196bd | 2537 | for (i = 1; i < hsotg->num_of_eps; ++i) { |
b203d0a2 RB |
2538 | if (hsotg->fifo_map & (1<<i)) |
2539 | continue; | |
2540 | val = readl(hsotg->regs + DPTXFSIZN(i)); | |
2541 | val = (val >> FIFOSIZE_DEPTH_SHIFT)*4; | |
2542 | if (val < size) | |
2543 | continue; | |
2544 | hsotg->fifo_map |= 1<<i; | |
2545 | ||
2546 | epctrl |= DXEPCTL_TXFNUM(i); | |
2547 | hs_ep->fifo_index = i; | |
2548 | hs_ep->fifo_size = val; | |
2549 | break; | |
2550 | } | |
5f2196bd MYK |
2551 | if (i == hsotg->num_of_eps) { |
2552 | dev_err(hsotg->dev, | |
2553 | "%s: No suitable fifo found\n", __func__); | |
b585a48b SM |
2554 | ret = -ENOMEM; |
2555 | goto error; | |
2556 | } | |
b203d0a2 | 2557 | } |
10aebc77 | 2558 | |
5b7d70c6 BD |
2559 | /* for non control endpoints, set PID to D0 */ |
2560 | if (index) | |
47a1685f | 2561 | epctrl |= DXEPCTL_SETD0PID; |
5b7d70c6 BD |
2562 | |
2563 | dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n", | |
2564 | __func__, epctrl); | |
2565 | ||
2566 | writel(epctrl, hsotg->regs + epctrl_reg); | |
2567 | dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x\n", | |
2568 | __func__, readl(hsotg->regs + epctrl_reg)); | |
2569 | ||
2570 | /* enable the endpoint interrupt */ | |
2571 | s3c_hsotg_ctrl_epint(hsotg, index, dir_in, 1); | |
2572 | ||
b585a48b | 2573 | error: |
22258f49 | 2574 | spin_unlock_irqrestore(&hsotg->lock, flags); |
19c190f9 | 2575 | return ret; |
5b7d70c6 BD |
2576 | } |
2577 | ||
8b9bc460 LM |
2578 | /** |
2579 | * s3c_hsotg_ep_disable - disable given endpoint | |
2580 | * @ep: The endpoint to disable. | |
2581 | */ | |
5b7d70c6 BD |
2582 | static int s3c_hsotg_ep_disable(struct usb_ep *ep) |
2583 | { | |
2584 | struct s3c_hsotg_ep *hs_ep = our_ep(ep); | |
941fcce4 | 2585 | struct dwc2_hsotg *hsotg = hs_ep->parent; |
5b7d70c6 BD |
2586 | int dir_in = hs_ep->dir_in; |
2587 | int index = hs_ep->index; | |
2588 | unsigned long flags; | |
2589 | u32 epctrl_reg; | |
2590 | u32 ctrl; | |
2591 | ||
1e011293 | 2592 | dev_dbg(hsotg->dev, "%s(ep %p)\n", __func__, ep); |
5b7d70c6 | 2593 | |
c6f5c050 | 2594 | if (ep == &hsotg->eps_out[0]->ep) { |
5b7d70c6 BD |
2595 | dev_err(hsotg->dev, "%s: called for ep0\n", __func__); |
2596 | return -EINVAL; | |
2597 | } | |
2598 | ||
94cb8fd6 | 2599 | epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index); |
5b7d70c6 | 2600 | |
5ad1d316 | 2601 | spin_lock_irqsave(&hsotg->lock, flags); |
5b7d70c6 | 2602 | |
b203d0a2 RB |
2603 | hsotg->fifo_map &= ~(1<<hs_ep->fifo_index); |
2604 | hs_ep->fifo_index = 0; | |
2605 | hs_ep->fifo_size = 0; | |
5b7d70c6 BD |
2606 | |
2607 | ctrl = readl(hsotg->regs + epctrl_reg); | |
47a1685f DN |
2608 | ctrl &= ~DXEPCTL_EPENA; |
2609 | ctrl &= ~DXEPCTL_USBACTEP; | |
2610 | ctrl |= DXEPCTL_SNAK; | |
5b7d70c6 BD |
2611 | |
2612 | dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl); | |
2613 | writel(ctrl, hsotg->regs + epctrl_reg); | |
2614 | ||
2615 | /* disable endpoint interrupts */ | |
2616 | s3c_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 0); | |
2617 | ||
1141ea01 MYK |
2618 | /* terminate all requests with shutdown */ |
2619 | kill_all_requests(hsotg, hs_ep, -ESHUTDOWN); | |
2620 | ||
22258f49 | 2621 | spin_unlock_irqrestore(&hsotg->lock, flags); |
5b7d70c6 BD |
2622 | return 0; |
2623 | } | |
2624 | ||
2625 | /** | |
2626 | * on_list - check request is on the given endpoint | |
2627 | * @ep: The endpoint to check. | |
2628 | * @test: The request to test if it is on the endpoint. | |
8b9bc460 | 2629 | */ |
5b7d70c6 BD |
2630 | static bool on_list(struct s3c_hsotg_ep *ep, struct s3c_hsotg_req *test) |
2631 | { | |
2632 | struct s3c_hsotg_req *req, *treq; | |
2633 | ||
2634 | list_for_each_entry_safe(req, treq, &ep->queue, queue) { | |
2635 | if (req == test) | |
2636 | return true; | |
2637 | } | |
2638 | ||
2639 | return false; | |
2640 | } | |
2641 | ||
8b9bc460 LM |
2642 | /** |
2643 | * s3c_hsotg_ep_dequeue - dequeue given endpoint | |
2644 | * @ep: The endpoint to dequeue. | |
2645 | * @req: The request to be removed from a queue. | |
2646 | */ | |
5b7d70c6 BD |
2647 | static int s3c_hsotg_ep_dequeue(struct usb_ep *ep, struct usb_request *req) |
2648 | { | |
2649 | struct s3c_hsotg_req *hs_req = our_req(req); | |
2650 | struct s3c_hsotg_ep *hs_ep = our_ep(ep); | |
941fcce4 | 2651 | struct dwc2_hsotg *hs = hs_ep->parent; |
5b7d70c6 BD |
2652 | unsigned long flags; |
2653 | ||
1e011293 | 2654 | dev_dbg(hs->dev, "ep_dequeue(%p,%p)\n", ep, req); |
5b7d70c6 | 2655 | |
22258f49 | 2656 | spin_lock_irqsave(&hs->lock, flags); |
5b7d70c6 BD |
2657 | |
2658 | if (!on_list(hs_ep, hs_req)) { | |
22258f49 | 2659 | spin_unlock_irqrestore(&hs->lock, flags); |
5b7d70c6 BD |
2660 | return -EINVAL; |
2661 | } | |
2662 | ||
2663 | s3c_hsotg_complete_request(hs, hs_ep, hs_req, -ECONNRESET); | |
22258f49 | 2664 | spin_unlock_irqrestore(&hs->lock, flags); |
5b7d70c6 BD |
2665 | |
2666 | return 0; | |
2667 | } | |
2668 | ||
8b9bc460 LM |
2669 | /** |
2670 | * s3c_hsotg_ep_sethalt - set halt on a given endpoint | |
2671 | * @ep: The endpoint to set halt. | |
2672 | * @value: Set or unset the halt. | |
2673 | */ | |
5b7d70c6 BD |
2674 | static int s3c_hsotg_ep_sethalt(struct usb_ep *ep, int value) |
2675 | { | |
2676 | struct s3c_hsotg_ep *hs_ep = our_ep(ep); | |
941fcce4 | 2677 | struct dwc2_hsotg *hs = hs_ep->parent; |
5b7d70c6 | 2678 | int index = hs_ep->index; |
5b7d70c6 BD |
2679 | u32 epreg; |
2680 | u32 epctl; | |
9c39ddc6 | 2681 | u32 xfertype; |
5b7d70c6 BD |
2682 | |
2683 | dev_info(hs->dev, "%s(ep %p %s, %d)\n", __func__, ep, ep->name, value); | |
2684 | ||
c9f721b2 RB |
2685 | if (index == 0) { |
2686 | if (value) | |
2687 | s3c_hsotg_stall_ep0(hs); | |
2688 | else | |
2689 | dev_warn(hs->dev, | |
2690 | "%s: can't clear halt on ep0\n", __func__); | |
2691 | return 0; | |
2692 | } | |
2693 | ||
c6f5c050 MYK |
2694 | if (hs_ep->dir_in) { |
2695 | epreg = DIEPCTL(index); | |
2696 | epctl = readl(hs->regs + epreg); | |
2697 | ||
2698 | if (value) { | |
2699 | epctl |= DXEPCTL_STALL + DXEPCTL_SNAK; | |
2700 | if (epctl & DXEPCTL_EPENA) | |
2701 | epctl |= DXEPCTL_EPDIS; | |
2702 | } else { | |
2703 | epctl &= ~DXEPCTL_STALL; | |
2704 | xfertype = epctl & DXEPCTL_EPTYPE_MASK; | |
2705 | if (xfertype == DXEPCTL_EPTYPE_BULK || | |
2706 | xfertype == DXEPCTL_EPTYPE_INTERRUPT) | |
2707 | epctl |= DXEPCTL_SETD0PID; | |
2708 | } | |
2709 | writel(epctl, hs->regs + epreg); | |
9c39ddc6 | 2710 | } else { |
5b7d70c6 | 2711 | |
c6f5c050 MYK |
2712 | epreg = DOEPCTL(index); |
2713 | epctl = readl(hs->regs + epreg); | |
5b7d70c6 | 2714 | |
c6f5c050 MYK |
2715 | if (value) |
2716 | epctl |= DXEPCTL_STALL; | |
2717 | else { | |
2718 | epctl &= ~DXEPCTL_STALL; | |
2719 | xfertype = epctl & DXEPCTL_EPTYPE_MASK; | |
2720 | if (xfertype == DXEPCTL_EPTYPE_BULK || | |
2721 | xfertype == DXEPCTL_EPTYPE_INTERRUPT) | |
2722 | epctl |= DXEPCTL_SETD0PID; | |
2723 | } | |
2724 | writel(epctl, hs->regs + epreg); | |
9c39ddc6 | 2725 | } |
5b7d70c6 | 2726 | |
a18ed7b0 RB |
2727 | hs_ep->halted = value; |
2728 | ||
5b7d70c6 BD |
2729 | return 0; |
2730 | } | |
2731 | ||
5ad1d316 LM |
2732 | /** |
2733 | * s3c_hsotg_ep_sethalt_lock - set halt on a given endpoint with lock held | |
2734 | * @ep: The endpoint to set halt. | |
2735 | * @value: Set or unset the halt. | |
2736 | */ | |
2737 | static int s3c_hsotg_ep_sethalt_lock(struct usb_ep *ep, int value) | |
2738 | { | |
2739 | struct s3c_hsotg_ep *hs_ep = our_ep(ep); | |
941fcce4 | 2740 | struct dwc2_hsotg *hs = hs_ep->parent; |
5ad1d316 LM |
2741 | unsigned long flags = 0; |
2742 | int ret = 0; | |
2743 | ||
2744 | spin_lock_irqsave(&hs->lock, flags); | |
2745 | ret = s3c_hsotg_ep_sethalt(ep, value); | |
2746 | spin_unlock_irqrestore(&hs->lock, flags); | |
2747 | ||
2748 | return ret; | |
2749 | } | |
2750 | ||
5b7d70c6 BD |
2751 | static struct usb_ep_ops s3c_hsotg_ep_ops = { |
2752 | .enable = s3c_hsotg_ep_enable, | |
2753 | .disable = s3c_hsotg_ep_disable, | |
2754 | .alloc_request = s3c_hsotg_ep_alloc_request, | |
2755 | .free_request = s3c_hsotg_ep_free_request, | |
5ad1d316 | 2756 | .queue = s3c_hsotg_ep_queue_lock, |
5b7d70c6 | 2757 | .dequeue = s3c_hsotg_ep_dequeue, |
5ad1d316 | 2758 | .set_halt = s3c_hsotg_ep_sethalt_lock, |
25985edc | 2759 | /* note, don't believe we have any call for the fifo routines */ |
5b7d70c6 BD |
2760 | }; |
2761 | ||
41188786 LM |
2762 | /** |
2763 | * s3c_hsotg_phy_enable - enable platform phy dev | |
8b9bc460 | 2764 | * @hsotg: The driver state |
41188786 LM |
2765 | * |
2766 | * A wrapper for platform code responsible for controlling | |
2767 | * low-level USB code | |
2768 | */ | |
941fcce4 | 2769 | static void s3c_hsotg_phy_enable(struct dwc2_hsotg *hsotg) |
41188786 LM |
2770 | { |
2771 | struct platform_device *pdev = to_platform_device(hsotg->dev); | |
2772 | ||
2773 | dev_dbg(hsotg->dev, "pdev 0x%p\n", pdev); | |
b2e587db | 2774 | |
ca2c5ba8 | 2775 | if (hsotg->uphy) |
74084844 | 2776 | usb_phy_init(hsotg->uphy); |
ca2c5ba8 | 2777 | else if (hsotg->plat && hsotg->plat->phy_init) |
41188786 | 2778 | hsotg->plat->phy_init(pdev, hsotg->plat->phy_type); |
ca2c5ba8 KD |
2779 | else { |
2780 | phy_init(hsotg->phy); | |
2781 | phy_power_on(hsotg->phy); | |
2782 | } | |
41188786 LM |
2783 | } |
2784 | ||
2785 | /** | |
2786 | * s3c_hsotg_phy_disable - disable platform phy dev | |
8b9bc460 | 2787 | * @hsotg: The driver state |
41188786 LM |
2788 | * |
2789 | * A wrapper for platform code responsible for controlling | |
2790 | * low-level USB code | |
2791 | */ | |
941fcce4 | 2792 | static void s3c_hsotg_phy_disable(struct dwc2_hsotg *hsotg) |
41188786 LM |
2793 | { |
2794 | struct platform_device *pdev = to_platform_device(hsotg->dev); | |
2795 | ||
ca2c5ba8 | 2796 | if (hsotg->uphy) |
74084844 | 2797 | usb_phy_shutdown(hsotg->uphy); |
ca2c5ba8 | 2798 | else if (hsotg->plat && hsotg->plat->phy_exit) |
41188786 | 2799 | hsotg->plat->phy_exit(pdev, hsotg->plat->phy_type); |
ca2c5ba8 KD |
2800 | else { |
2801 | phy_power_off(hsotg->phy); | |
2802 | phy_exit(hsotg->phy); | |
2803 | } | |
41188786 LM |
2804 | } |
2805 | ||
8b9bc460 LM |
2806 | /** |
2807 | * s3c_hsotg_init - initalize the usb core | |
2808 | * @hsotg: The driver state | |
2809 | */ | |
941fcce4 | 2810 | static void s3c_hsotg_init(struct dwc2_hsotg *hsotg) |
b3f489b2 LM |
2811 | { |
2812 | /* unmask subset of endpoint interrupts */ | |
2813 | ||
47a1685f DN |
2814 | writel(DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK | |
2815 | DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK, | |
2816 | hsotg->regs + DIEPMSK); | |
b3f489b2 | 2817 | |
47a1685f DN |
2818 | writel(DOEPMSK_SETUPMSK | DOEPMSK_AHBERRMSK | |
2819 | DOEPMSK_EPDISBLDMSK | DOEPMSK_XFERCOMPLMSK, | |
2820 | hsotg->regs + DOEPMSK); | |
b3f489b2 | 2821 | |
94cb8fd6 | 2822 | writel(0, hsotg->regs + DAINTMSK); |
b3f489b2 LM |
2823 | |
2824 | /* Be in disconnected state until gadget is registered */ | |
47a1685f | 2825 | __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON); |
b3f489b2 LM |
2826 | |
2827 | if (0) { | |
2828 | /* post global nak until we're ready */ | |
47a1685f | 2829 | writel(DCTL_SGNPINNAK | DCTL_SGOUTNAK, |
94cb8fd6 | 2830 | hsotg->regs + DCTL); |
b3f489b2 LM |
2831 | } |
2832 | ||
2833 | /* setup fifos */ | |
2834 | ||
2835 | dev_dbg(hsotg->dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n", | |
94cb8fd6 LM |
2836 | readl(hsotg->regs + GRXFSIZ), |
2837 | readl(hsotg->regs + GNPTXFSIZ)); | |
b3f489b2 LM |
2838 | |
2839 | s3c_hsotg_init_fifo(hsotg); | |
2840 | ||
2841 | /* set the PLL on, remove the HNP/SRP and set the PHY */ | |
47a1685f | 2842 | writel(GUSBCFG_PHYIF16 | GUSBCFG_TOUTCAL(7) | (0x5 << 10), |
94cb8fd6 | 2843 | hsotg->regs + GUSBCFG); |
b3f489b2 | 2844 | |
f5090044 GH |
2845 | if (using_dma(hsotg)) |
2846 | __orr32(hsotg->regs + GAHBCFG, GAHBCFG_DMA_EN); | |
b3f489b2 LM |
2847 | } |
2848 | ||
8b9bc460 LM |
2849 | /** |
2850 | * s3c_hsotg_udc_start - prepare the udc for work | |
2851 | * @gadget: The usb gadget state | |
2852 | * @driver: The usb gadget driver | |
2853 | * | |
2854 | * Perform initialization to prepare udc device and driver | |
2855 | * to work. | |
2856 | */ | |
f65f0f10 LM |
2857 | static int s3c_hsotg_udc_start(struct usb_gadget *gadget, |
2858 | struct usb_gadget_driver *driver) | |
5b7d70c6 | 2859 | { |
941fcce4 | 2860 | struct dwc2_hsotg *hsotg = to_hsotg(gadget); |
5b9451f8 | 2861 | unsigned long flags; |
5b7d70c6 BD |
2862 | int ret; |
2863 | ||
2864 | if (!hsotg) { | |
a023da33 | 2865 | pr_err("%s: called with no device\n", __func__); |
5b7d70c6 BD |
2866 | return -ENODEV; |
2867 | } | |
2868 | ||
2869 | if (!driver) { | |
2870 | dev_err(hsotg->dev, "%s: no driver\n", __func__); | |
2871 | return -EINVAL; | |
2872 | } | |
2873 | ||
7177aed4 | 2874 | if (driver->max_speed < USB_SPEED_FULL) |
5b7d70c6 | 2875 | dev_err(hsotg->dev, "%s: bad speed\n", __func__); |
5b7d70c6 | 2876 | |
f65f0f10 | 2877 | if (!driver->setup) { |
5b7d70c6 BD |
2878 | dev_err(hsotg->dev, "%s: missing entry points\n", __func__); |
2879 | return -EINVAL; | |
2880 | } | |
2881 | ||
7ad8096e | 2882 | mutex_lock(&hsotg->init_mutex); |
5b7d70c6 BD |
2883 | WARN_ON(hsotg->driver); |
2884 | ||
2885 | driver->driver.bus = NULL; | |
2886 | hsotg->driver = driver; | |
7d7b2292 | 2887 | hsotg->gadget.dev.of_node = hsotg->dev->of_node; |
5b7d70c6 BD |
2888 | hsotg->gadget.speed = USB_SPEED_UNKNOWN; |
2889 | ||
d00b4142 RB |
2890 | clk_enable(hsotg->clk); |
2891 | ||
f65f0f10 LM |
2892 | ret = regulator_bulk_enable(ARRAY_SIZE(hsotg->supplies), |
2893 | hsotg->supplies); | |
5b7d70c6 | 2894 | if (ret) { |
f65f0f10 | 2895 | dev_err(hsotg->dev, "failed to enable supplies: %d\n", ret); |
5b7d70c6 BD |
2896 | goto err; |
2897 | } | |
2898 | ||
c816c47f | 2899 | s3c_hsotg_phy_enable(hsotg); |
f6c01592 GH |
2900 | if (!IS_ERR_OR_NULL(hsotg->uphy)) |
2901 | otg_set_peripheral(hsotg->uphy->otg, &hsotg->gadget); | |
c816c47f | 2902 | |
5b9451f8 MS |
2903 | spin_lock_irqsave(&hsotg->lock, flags); |
2904 | s3c_hsotg_init(hsotg); | |
2905 | s3c_hsotg_core_init_disconnected(hsotg); | |
dc6e69e6 | 2906 | hsotg->enabled = 0; |
5b9451f8 MS |
2907 | spin_unlock_irqrestore(&hsotg->lock, flags); |
2908 | ||
5b7d70c6 | 2909 | dev_info(hsotg->dev, "bound driver %s\n", driver->driver.name); |
5b9451f8 | 2910 | |
7ad8096e MS |
2911 | mutex_unlock(&hsotg->init_mutex); |
2912 | ||
5b7d70c6 BD |
2913 | return 0; |
2914 | ||
2915 | err: | |
7ad8096e | 2916 | mutex_unlock(&hsotg->init_mutex); |
5b7d70c6 | 2917 | hsotg->driver = NULL; |
5b7d70c6 BD |
2918 | return ret; |
2919 | } | |
2920 | ||
8b9bc460 LM |
2921 | /** |
2922 | * s3c_hsotg_udc_stop - stop the udc | |
2923 | * @gadget: The usb gadget state | |
2924 | * @driver: The usb gadget driver | |
2925 | * | |
2926 | * Stop udc hw block and stay tunned for future transmissions | |
2927 | */ | |
22835b80 | 2928 | static int s3c_hsotg_udc_stop(struct usb_gadget *gadget) |
5b7d70c6 | 2929 | { |
941fcce4 | 2930 | struct dwc2_hsotg *hsotg = to_hsotg(gadget); |
2b19a52c | 2931 | unsigned long flags = 0; |
5b7d70c6 BD |
2932 | int ep; |
2933 | ||
2934 | if (!hsotg) | |
2935 | return -ENODEV; | |
2936 | ||
7ad8096e MS |
2937 | mutex_lock(&hsotg->init_mutex); |
2938 | ||
5b7d70c6 | 2939 | /* all endpoints should be shutdown */ |
c6f5c050 MYK |
2940 | for (ep = 1; ep < hsotg->num_of_eps; ep++) { |
2941 | if (hsotg->eps_in[ep]) | |
2942 | s3c_hsotg_ep_disable(&hsotg->eps_in[ep]->ep); | |
2943 | if (hsotg->eps_out[ep]) | |
2944 | s3c_hsotg_ep_disable(&hsotg->eps_out[ep]->ep); | |
2945 | } | |
5b7d70c6 | 2946 | |
2b19a52c LM |
2947 | spin_lock_irqsave(&hsotg->lock, flags); |
2948 | ||
32805c35 | 2949 | hsotg->driver = NULL; |
5b7d70c6 | 2950 | hsotg->gadget.speed = USB_SPEED_UNKNOWN; |
dc6e69e6 | 2951 | hsotg->enabled = 0; |
5b7d70c6 | 2952 | |
2b19a52c LM |
2953 | spin_unlock_irqrestore(&hsotg->lock, flags); |
2954 | ||
f6c01592 GH |
2955 | if (!IS_ERR_OR_NULL(hsotg->uphy)) |
2956 | otg_set_peripheral(hsotg->uphy->otg, NULL); | |
c816c47f MS |
2957 | s3c_hsotg_phy_disable(hsotg); |
2958 | ||
c8c10253 | 2959 | regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies), hsotg->supplies); |
5b7d70c6 | 2960 | |
d00b4142 RB |
2961 | clk_disable(hsotg->clk); |
2962 | ||
7ad8096e MS |
2963 | mutex_unlock(&hsotg->init_mutex); |
2964 | ||
5b7d70c6 BD |
2965 | return 0; |
2966 | } | |
5b7d70c6 | 2967 | |
8b9bc460 LM |
2968 | /** |
2969 | * s3c_hsotg_gadget_getframe - read the frame number | |
2970 | * @gadget: The usb gadget state | |
2971 | * | |
2972 | * Read the {micro} frame number | |
2973 | */ | |
5b7d70c6 BD |
2974 | static int s3c_hsotg_gadget_getframe(struct usb_gadget *gadget) |
2975 | { | |
2976 | return s3c_hsotg_read_frameno(to_hsotg(gadget)); | |
2977 | } | |
2978 | ||
a188b689 LM |
2979 | /** |
2980 | * s3c_hsotg_pullup - connect/disconnect the USB PHY | |
2981 | * @gadget: The usb gadget state | |
2982 | * @is_on: Current state of the USB PHY | |
2983 | * | |
2984 | * Connect/Disconnect the USB PHY pullup | |
2985 | */ | |
2986 | static int s3c_hsotg_pullup(struct usb_gadget *gadget, int is_on) | |
2987 | { | |
941fcce4 | 2988 | struct dwc2_hsotg *hsotg = to_hsotg(gadget); |
a188b689 LM |
2989 | unsigned long flags = 0; |
2990 | ||
d784f1e5 | 2991 | dev_dbg(hsotg->dev, "%s: is_on: %d\n", __func__, is_on); |
a188b689 | 2992 | |
7ad8096e | 2993 | mutex_lock(&hsotg->init_mutex); |
a188b689 LM |
2994 | spin_lock_irqsave(&hsotg->lock, flags); |
2995 | if (is_on) { | |
d00b4142 | 2996 | clk_enable(hsotg->clk); |
dc6e69e6 | 2997 | hsotg->enabled = 1; |
ad38dc5d | 2998 | s3c_hsotg_core_connect(hsotg); |
a188b689 | 2999 | } else { |
5b9451f8 | 3000 | s3c_hsotg_core_disconnect(hsotg); |
dc6e69e6 | 3001 | hsotg->enabled = 0; |
d00b4142 | 3002 | clk_disable(hsotg->clk); |
a188b689 LM |
3003 | } |
3004 | ||
3005 | hsotg->gadget.speed = USB_SPEED_UNKNOWN; | |
3006 | spin_unlock_irqrestore(&hsotg->lock, flags); | |
7ad8096e | 3007 | mutex_unlock(&hsotg->init_mutex); |
a188b689 LM |
3008 | |
3009 | return 0; | |
3010 | } | |
3011 | ||
83d98223 GH |
3012 | static int s3c_hsotg_vbus_session(struct usb_gadget *gadget, int is_active) |
3013 | { | |
3014 | struct dwc2_hsotg *hsotg = to_hsotg(gadget); | |
3015 | unsigned long flags; | |
3016 | ||
3017 | dev_dbg(hsotg->dev, "%s: is_active: %d\n", __func__, is_active); | |
3018 | spin_lock_irqsave(&hsotg->lock, flags); | |
3019 | ||
3020 | if (is_active) { | |
3021 | /* Kill any ep0 requests as controller will be reinitialized */ | |
3022 | kill_all_requests(hsotg, hsotg->eps_out[0], -ECONNRESET); | |
3023 | s3c_hsotg_core_init_disconnected(hsotg); | |
3024 | if (hsotg->enabled) | |
3025 | s3c_hsotg_core_connect(hsotg); | |
3026 | } else { | |
3027 | s3c_hsotg_core_disconnect(hsotg); | |
3028 | s3c_hsotg_disconnect(hsotg); | |
3029 | } | |
3030 | ||
3031 | spin_unlock_irqrestore(&hsotg->lock, flags); | |
3032 | return 0; | |
3033 | } | |
3034 | ||
eeef4587 | 3035 | static const struct usb_gadget_ops s3c_hsotg_gadget_ops = { |
5b7d70c6 | 3036 | .get_frame = s3c_hsotg_gadget_getframe, |
f65f0f10 LM |
3037 | .udc_start = s3c_hsotg_udc_start, |
3038 | .udc_stop = s3c_hsotg_udc_stop, | |
a188b689 | 3039 | .pullup = s3c_hsotg_pullup, |
83d98223 | 3040 | .vbus_session = s3c_hsotg_vbus_session, |
5b7d70c6 BD |
3041 | }; |
3042 | ||
3043 | /** | |
3044 | * s3c_hsotg_initep - initialise a single endpoint | |
3045 | * @hsotg: The device state. | |
3046 | * @hs_ep: The endpoint to be initialised. | |
3047 | * @epnum: The endpoint number | |
3048 | * | |
3049 | * Initialise the given endpoint (as part of the probe and device state | |
3050 | * creation) to give to the gadget driver. Setup the endpoint name, any | |
3051 | * direction information and other state that may be required. | |
3052 | */ | |
941fcce4 | 3053 | static void s3c_hsotg_initep(struct dwc2_hsotg *hsotg, |
5b7d70c6 | 3054 | struct s3c_hsotg_ep *hs_ep, |
c6f5c050 MYK |
3055 | int epnum, |
3056 | bool dir_in) | |
5b7d70c6 | 3057 | { |
5b7d70c6 BD |
3058 | char *dir; |
3059 | ||
3060 | if (epnum == 0) | |
3061 | dir = ""; | |
c6f5c050 | 3062 | else if (dir_in) |
5b7d70c6 | 3063 | dir = "in"; |
c6f5c050 MYK |
3064 | else |
3065 | dir = "out"; | |
5b7d70c6 | 3066 | |
c6f5c050 | 3067 | hs_ep->dir_in = dir_in; |
5b7d70c6 BD |
3068 | hs_ep->index = epnum; |
3069 | ||
3070 | snprintf(hs_ep->name, sizeof(hs_ep->name), "ep%d%s", epnum, dir); | |
3071 | ||
3072 | INIT_LIST_HEAD(&hs_ep->queue); | |
3073 | INIT_LIST_HEAD(&hs_ep->ep.ep_list); | |
3074 | ||
5b7d70c6 BD |
3075 | /* add to the list of endpoints known by the gadget driver */ |
3076 | if (epnum) | |
3077 | list_add_tail(&hs_ep->ep.ep_list, &hsotg->gadget.ep_list); | |
3078 | ||
3079 | hs_ep->parent = hsotg; | |
3080 | hs_ep->ep.name = hs_ep->name; | |
e117e742 | 3081 | usb_ep_set_maxpacket_limit(&hs_ep->ep, epnum ? 1024 : EP0_MPS_LIMIT); |
5b7d70c6 BD |
3082 | hs_ep->ep.ops = &s3c_hsotg_ep_ops; |
3083 | ||
8b9bc460 LM |
3084 | /* |
3085 | * if we're using dma, we need to set the next-endpoint pointer | |
5b7d70c6 BD |
3086 | * to be something valid. |
3087 | */ | |
3088 | ||
3089 | if (using_dma(hsotg)) { | |
47a1685f | 3090 | u32 next = DXEPCTL_NEXTEP((epnum + 1) % 15); |
c6f5c050 MYK |
3091 | if (dir_in) |
3092 | writel(next, hsotg->regs + DIEPCTL(epnum)); | |
3093 | else | |
3094 | writel(next, hsotg->regs + DOEPCTL(epnum)); | |
5b7d70c6 BD |
3095 | } |
3096 | } | |
3097 | ||
b3f489b2 LM |
3098 | /** |
3099 | * s3c_hsotg_hw_cfg - read HW configuration registers | |
3100 | * @param: The device state | |
3101 | * | |
3102 | * Read the USB core HW configuration registers | |
3103 | */ | |
c6f5c050 | 3104 | static int s3c_hsotg_hw_cfg(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 3105 | { |
c6f5c050 MYK |
3106 | u32 cfg; |
3107 | u32 ep_type; | |
3108 | u32 i; | |
3109 | ||
b3f489b2 | 3110 | /* check hardware configuration */ |
5b7d70c6 | 3111 | |
c6f5c050 MYK |
3112 | cfg = readl(hsotg->regs + GHWCFG2); |
3113 | hsotg->num_of_eps = (cfg >> 10) & 0xF; | |
3114 | /* Add ep0 */ | |
3115 | hsotg->num_of_eps++; | |
10aebc77 | 3116 | |
c6f5c050 MYK |
3117 | hsotg->eps_in[0] = devm_kzalloc(hsotg->dev, sizeof(struct s3c_hsotg_ep), |
3118 | GFP_KERNEL); | |
3119 | if (!hsotg->eps_in[0]) | |
3120 | return -ENOMEM; | |
3121 | /* Same s3c_hsotg_ep is used in both directions for ep0 */ | |
3122 | hsotg->eps_out[0] = hsotg->eps_in[0]; | |
3123 | ||
3124 | cfg = readl(hsotg->regs + GHWCFG1); | |
3125 | for (i = 1; i < hsotg->num_of_eps; i++, cfg >>= 2) { | |
3126 | ep_type = cfg & 3; | |
3127 | /* Direction in or both */ | |
3128 | if (!(ep_type & 2)) { | |
3129 | hsotg->eps_in[i] = devm_kzalloc(hsotg->dev, | |
3130 | sizeof(struct s3c_hsotg_ep), GFP_KERNEL); | |
3131 | if (!hsotg->eps_in[i]) | |
3132 | return -ENOMEM; | |
3133 | } | |
3134 | /* Direction out or both */ | |
3135 | if (!(ep_type & 1)) { | |
3136 | hsotg->eps_out[i] = devm_kzalloc(hsotg->dev, | |
3137 | sizeof(struct s3c_hsotg_ep), GFP_KERNEL); | |
3138 | if (!hsotg->eps_out[i]) | |
3139 | return -ENOMEM; | |
3140 | } | |
3141 | } | |
3142 | ||
3143 | cfg = readl(hsotg->regs + GHWCFG3); | |
3144 | hsotg->fifo_mem = (cfg >> 16); | |
10aebc77 | 3145 | |
c6f5c050 MYK |
3146 | cfg = readl(hsotg->regs + GHWCFG4); |
3147 | hsotg->dedicated_fifos = (cfg >> 25) & 1; | |
10aebc77 | 3148 | |
cff9eb75 MS |
3149 | dev_info(hsotg->dev, "EPs: %d, %s fifos, %d entries in SPRAM\n", |
3150 | hsotg->num_of_eps, | |
3151 | hsotg->dedicated_fifos ? "dedicated" : "shared", | |
3152 | hsotg->fifo_mem); | |
c6f5c050 | 3153 | return 0; |
5b7d70c6 BD |
3154 | } |
3155 | ||
8b9bc460 LM |
3156 | /** |
3157 | * s3c_hsotg_dump - dump state of the udc | |
3158 | * @param: The device state | |
3159 | */ | |
941fcce4 | 3160 | static void s3c_hsotg_dump(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 3161 | { |
83a01804 | 3162 | #ifdef DEBUG |
5b7d70c6 BD |
3163 | struct device *dev = hsotg->dev; |
3164 | void __iomem *regs = hsotg->regs; | |
3165 | u32 val; | |
3166 | int idx; | |
3167 | ||
3168 | dev_info(dev, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n", | |
94cb8fd6 LM |
3169 | readl(regs + DCFG), readl(regs + DCTL), |
3170 | readl(regs + DIEPMSK)); | |
5b7d70c6 BD |
3171 | |
3172 | dev_info(dev, "GAHBCFG=0x%08x, 0x44=0x%08x\n", | |
94cb8fd6 | 3173 | readl(regs + GAHBCFG), readl(regs + 0x44)); |
5b7d70c6 BD |
3174 | |
3175 | dev_info(dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n", | |
94cb8fd6 | 3176 | readl(regs + GRXFSIZ), readl(regs + GNPTXFSIZ)); |
5b7d70c6 BD |
3177 | |
3178 | /* show periodic fifo settings */ | |
3179 | ||
364f8e93 | 3180 | for (idx = 1; idx < hsotg->num_of_eps; idx++) { |
47a1685f | 3181 | val = readl(regs + DPTXFSIZN(idx)); |
5b7d70c6 | 3182 | dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx, |
47a1685f DN |
3183 | val >> FIFOSIZE_DEPTH_SHIFT, |
3184 | val & FIFOSIZE_STARTADDR_MASK); | |
5b7d70c6 BD |
3185 | } |
3186 | ||
364f8e93 | 3187 | for (idx = 0; idx < hsotg->num_of_eps; idx++) { |
5b7d70c6 BD |
3188 | dev_info(dev, |
3189 | "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx, | |
94cb8fd6 LM |
3190 | readl(regs + DIEPCTL(idx)), |
3191 | readl(regs + DIEPTSIZ(idx)), | |
3192 | readl(regs + DIEPDMA(idx))); | |
5b7d70c6 | 3193 | |
94cb8fd6 | 3194 | val = readl(regs + DOEPCTL(idx)); |
5b7d70c6 BD |
3195 | dev_info(dev, |
3196 | "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", | |
94cb8fd6 LM |
3197 | idx, readl(regs + DOEPCTL(idx)), |
3198 | readl(regs + DOEPTSIZ(idx)), | |
3199 | readl(regs + DOEPDMA(idx))); | |
5b7d70c6 BD |
3200 | |
3201 | } | |
3202 | ||
3203 | dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n", | |
94cb8fd6 | 3204 | readl(regs + DVBUSDIS), readl(regs + DVBUSPULSE)); |
83a01804 | 3205 | #endif |
5b7d70c6 BD |
3206 | } |
3207 | ||
5b7d70c6 BD |
3208 | /** |
3209 | * state_show - debugfs: show overall driver and device state. | |
3210 | * @seq: The seq file to write to. | |
3211 | * @v: Unused parameter. | |
3212 | * | |
3213 | * This debugfs entry shows the overall state of the hardware and | |
3214 | * some general information about each of the endpoints available | |
3215 | * to the system. | |
3216 | */ | |
3217 | static int state_show(struct seq_file *seq, void *v) | |
3218 | { | |
941fcce4 | 3219 | struct dwc2_hsotg *hsotg = seq->private; |
5b7d70c6 BD |
3220 | void __iomem *regs = hsotg->regs; |
3221 | int idx; | |
3222 | ||
3223 | seq_printf(seq, "DCFG=0x%08x, DCTL=0x%08x, DSTS=0x%08x\n", | |
94cb8fd6 LM |
3224 | readl(regs + DCFG), |
3225 | readl(regs + DCTL), | |
3226 | readl(regs + DSTS)); | |
5b7d70c6 BD |
3227 | |
3228 | seq_printf(seq, "DIEPMSK=0x%08x, DOEPMASK=0x%08x\n", | |
94cb8fd6 | 3229 | readl(regs + DIEPMSK), readl(regs + DOEPMSK)); |
5b7d70c6 BD |
3230 | |
3231 | seq_printf(seq, "GINTMSK=0x%08x, GINTSTS=0x%08x\n", | |
94cb8fd6 LM |
3232 | readl(regs + GINTMSK), |
3233 | readl(regs + GINTSTS)); | |
5b7d70c6 BD |
3234 | |
3235 | seq_printf(seq, "DAINTMSK=0x%08x, DAINT=0x%08x\n", | |
94cb8fd6 LM |
3236 | readl(regs + DAINTMSK), |
3237 | readl(regs + DAINT)); | |
5b7d70c6 BD |
3238 | |
3239 | seq_printf(seq, "GNPTXSTS=0x%08x, GRXSTSR=%08x\n", | |
94cb8fd6 LM |
3240 | readl(regs + GNPTXSTS), |
3241 | readl(regs + GRXSTSR)); | |
5b7d70c6 | 3242 | |
a023da33 | 3243 | seq_puts(seq, "\nEndpoint status:\n"); |
5b7d70c6 | 3244 | |
364f8e93 | 3245 | for (idx = 0; idx < hsotg->num_of_eps; idx++) { |
5b7d70c6 BD |
3246 | u32 in, out; |
3247 | ||
94cb8fd6 LM |
3248 | in = readl(regs + DIEPCTL(idx)); |
3249 | out = readl(regs + DOEPCTL(idx)); | |
5b7d70c6 BD |
3250 | |
3251 | seq_printf(seq, "ep%d: DIEPCTL=0x%08x, DOEPCTL=0x%08x", | |
3252 | idx, in, out); | |
3253 | ||
94cb8fd6 LM |
3254 | in = readl(regs + DIEPTSIZ(idx)); |
3255 | out = readl(regs + DOEPTSIZ(idx)); | |
5b7d70c6 BD |
3256 | |
3257 | seq_printf(seq, ", DIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x", | |
3258 | in, out); | |
3259 | ||
a023da33 | 3260 | seq_puts(seq, "\n"); |
5b7d70c6 BD |
3261 | } |
3262 | ||
3263 | return 0; | |
3264 | } | |
3265 | ||
3266 | static int state_open(struct inode *inode, struct file *file) | |
3267 | { | |
3268 | return single_open(file, state_show, inode->i_private); | |
3269 | } | |
3270 | ||
3271 | static const struct file_operations state_fops = { | |
3272 | .owner = THIS_MODULE, | |
3273 | .open = state_open, | |
3274 | .read = seq_read, | |
3275 | .llseek = seq_lseek, | |
3276 | .release = single_release, | |
3277 | }; | |
3278 | ||
3279 | /** | |
3280 | * fifo_show - debugfs: show the fifo information | |
3281 | * @seq: The seq_file to write data to. | |
3282 | * @v: Unused parameter. | |
3283 | * | |
3284 | * Show the FIFO information for the overall fifo and all the | |
3285 | * periodic transmission FIFOs. | |
8b9bc460 | 3286 | */ |
5b7d70c6 BD |
3287 | static int fifo_show(struct seq_file *seq, void *v) |
3288 | { | |
941fcce4 | 3289 | struct dwc2_hsotg *hsotg = seq->private; |
5b7d70c6 BD |
3290 | void __iomem *regs = hsotg->regs; |
3291 | u32 val; | |
3292 | int idx; | |
3293 | ||
a023da33 | 3294 | seq_puts(seq, "Non-periodic FIFOs:\n"); |
94cb8fd6 | 3295 | seq_printf(seq, "RXFIFO: Size %d\n", readl(regs + GRXFSIZ)); |
5b7d70c6 | 3296 | |
94cb8fd6 | 3297 | val = readl(regs + GNPTXFSIZ); |
5b7d70c6 | 3298 | seq_printf(seq, "NPTXFIFO: Size %d, Start 0x%08x\n", |
47a1685f DN |
3299 | val >> FIFOSIZE_DEPTH_SHIFT, |
3300 | val & FIFOSIZE_DEPTH_MASK); | |
5b7d70c6 | 3301 | |
a023da33 | 3302 | seq_puts(seq, "\nPeriodic TXFIFOs:\n"); |
5b7d70c6 | 3303 | |
364f8e93 | 3304 | for (idx = 1; idx < hsotg->num_of_eps; idx++) { |
47a1685f | 3305 | val = readl(regs + DPTXFSIZN(idx)); |
5b7d70c6 BD |
3306 | |
3307 | seq_printf(seq, "\tDPTXFIFO%2d: Size %d, Start 0x%08x\n", idx, | |
47a1685f DN |
3308 | val >> FIFOSIZE_DEPTH_SHIFT, |
3309 | val & FIFOSIZE_STARTADDR_MASK); | |
5b7d70c6 BD |
3310 | } |
3311 | ||
3312 | return 0; | |
3313 | } | |
3314 | ||
3315 | static int fifo_open(struct inode *inode, struct file *file) | |
3316 | { | |
3317 | return single_open(file, fifo_show, inode->i_private); | |
3318 | } | |
3319 | ||
3320 | static const struct file_operations fifo_fops = { | |
3321 | .owner = THIS_MODULE, | |
3322 | .open = fifo_open, | |
3323 | .read = seq_read, | |
3324 | .llseek = seq_lseek, | |
3325 | .release = single_release, | |
3326 | }; | |
3327 | ||
3328 | ||
3329 | static const char *decode_direction(int is_in) | |
3330 | { | |
3331 | return is_in ? "in" : "out"; | |
3332 | } | |
3333 | ||
3334 | /** | |
3335 | * ep_show - debugfs: show the state of an endpoint. | |
3336 | * @seq: The seq_file to write data to. | |
3337 | * @v: Unused parameter. | |
3338 | * | |
3339 | * This debugfs entry shows the state of the given endpoint (one is | |
3340 | * registered for each available). | |
8b9bc460 | 3341 | */ |
5b7d70c6 BD |
3342 | static int ep_show(struct seq_file *seq, void *v) |
3343 | { | |
3344 | struct s3c_hsotg_ep *ep = seq->private; | |
941fcce4 | 3345 | struct dwc2_hsotg *hsotg = ep->parent; |
5b7d70c6 BD |
3346 | struct s3c_hsotg_req *req; |
3347 | void __iomem *regs = hsotg->regs; | |
3348 | int index = ep->index; | |
3349 | int show_limit = 15; | |
3350 | unsigned long flags; | |
3351 | ||
3352 | seq_printf(seq, "Endpoint index %d, named %s, dir %s:\n", | |
3353 | ep->index, ep->ep.name, decode_direction(ep->dir_in)); | |
3354 | ||
3355 | /* first show the register state */ | |
3356 | ||
3357 | seq_printf(seq, "\tDIEPCTL=0x%08x, DOEPCTL=0x%08x\n", | |
94cb8fd6 LM |
3358 | readl(regs + DIEPCTL(index)), |
3359 | readl(regs + DOEPCTL(index))); | |
5b7d70c6 BD |
3360 | |
3361 | seq_printf(seq, "\tDIEPDMA=0x%08x, DOEPDMA=0x%08x\n", | |
94cb8fd6 LM |
3362 | readl(regs + DIEPDMA(index)), |
3363 | readl(regs + DOEPDMA(index))); | |
5b7d70c6 BD |
3364 | |
3365 | seq_printf(seq, "\tDIEPINT=0x%08x, DOEPINT=0x%08x\n", | |
94cb8fd6 LM |
3366 | readl(regs + DIEPINT(index)), |
3367 | readl(regs + DOEPINT(index))); | |
5b7d70c6 BD |
3368 | |
3369 | seq_printf(seq, "\tDIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x\n", | |
94cb8fd6 LM |
3370 | readl(regs + DIEPTSIZ(index)), |
3371 | readl(regs + DOEPTSIZ(index))); | |
5b7d70c6 | 3372 | |
a023da33 | 3373 | seq_puts(seq, "\n"); |
5b7d70c6 BD |
3374 | seq_printf(seq, "mps %d\n", ep->ep.maxpacket); |
3375 | seq_printf(seq, "total_data=%ld\n", ep->total_data); | |
3376 | ||
3377 | seq_printf(seq, "request list (%p,%p):\n", | |
3378 | ep->queue.next, ep->queue.prev); | |
3379 | ||
22258f49 | 3380 | spin_lock_irqsave(&hsotg->lock, flags); |
5b7d70c6 BD |
3381 | |
3382 | list_for_each_entry(req, &ep->queue, queue) { | |
3383 | if (--show_limit < 0) { | |
a023da33 | 3384 | seq_puts(seq, "not showing more requests...\n"); |
5b7d70c6 BD |
3385 | break; |
3386 | } | |
3387 | ||
3388 | seq_printf(seq, "%c req %p: %d bytes @%p, ", | |
3389 | req == ep->req ? '*' : ' ', | |
3390 | req, req->req.length, req->req.buf); | |
3391 | seq_printf(seq, "%d done, res %d\n", | |
3392 | req->req.actual, req->req.status); | |
3393 | } | |
3394 | ||
22258f49 | 3395 | spin_unlock_irqrestore(&hsotg->lock, flags); |
5b7d70c6 BD |
3396 | |
3397 | return 0; | |
3398 | } | |
3399 | ||
3400 | static int ep_open(struct inode *inode, struct file *file) | |
3401 | { | |
3402 | return single_open(file, ep_show, inode->i_private); | |
3403 | } | |
3404 | ||
3405 | static const struct file_operations ep_fops = { | |
3406 | .owner = THIS_MODULE, | |
3407 | .open = ep_open, | |
3408 | .read = seq_read, | |
3409 | .llseek = seq_lseek, | |
3410 | .release = single_release, | |
3411 | }; | |
3412 | ||
3413 | /** | |
3414 | * s3c_hsotg_create_debug - create debugfs directory and files | |
3415 | * @hsotg: The driver state | |
3416 | * | |
3417 | * Create the debugfs files to allow the user to get information | |
3418 | * about the state of the system. The directory name is created | |
3419 | * with the same name as the device itself, in case we end up | |
3420 | * with multiple blocks in future systems. | |
8b9bc460 | 3421 | */ |
941fcce4 | 3422 | static void s3c_hsotg_create_debug(struct dwc2_hsotg *hsotg) |
5b7d70c6 BD |
3423 | { |
3424 | struct dentry *root; | |
3425 | unsigned epidx; | |
3426 | ||
3427 | root = debugfs_create_dir(dev_name(hsotg->dev), NULL); | |
3428 | hsotg->debug_root = root; | |
3429 | if (IS_ERR(root)) { | |
3430 | dev_err(hsotg->dev, "cannot create debug root\n"); | |
3431 | return; | |
3432 | } | |
3433 | ||
3434 | /* create general state file */ | |
3435 | ||
3436 | hsotg->debug_file = debugfs_create_file("state", 0444, root, | |
3437 | hsotg, &state_fops); | |
3438 | ||
3439 | if (IS_ERR(hsotg->debug_file)) | |
3440 | dev_err(hsotg->dev, "%s: failed to create state\n", __func__); | |
3441 | ||
3442 | hsotg->debug_fifo = debugfs_create_file("fifo", 0444, root, | |
3443 | hsotg, &fifo_fops); | |
3444 | ||
3445 | if (IS_ERR(hsotg->debug_fifo)) | |
3446 | dev_err(hsotg->dev, "%s: failed to create fifo\n", __func__); | |
3447 | ||
c6f5c050 | 3448 | /* Create one file for each out endpoint */ |
b3f489b2 | 3449 | for (epidx = 0; epidx < hsotg->num_of_eps; epidx++) { |
c6f5c050 | 3450 | struct s3c_hsotg_ep *ep; |
5b7d70c6 | 3451 | |
c6f5c050 MYK |
3452 | ep = hsotg->eps_out[epidx]; |
3453 | if (ep) { | |
3454 | ep->debugfs = debugfs_create_file(ep->name, 0444, | |
3455 | root, ep, &ep_fops); | |
5b7d70c6 | 3456 | |
c6f5c050 MYK |
3457 | if (IS_ERR(ep->debugfs)) |
3458 | dev_err(hsotg->dev, "failed to create %s debug file\n", | |
3459 | ep->name); | |
3460 | } | |
3461 | } | |
3462 | /* Create one file for each in endpoint. EP0 is handled with out eps */ | |
3463 | for (epidx = 1; epidx < hsotg->num_of_eps; epidx++) { | |
3464 | struct s3c_hsotg_ep *ep; | |
3465 | ||
3466 | ep = hsotg->eps_in[epidx]; | |
3467 | if (ep) { | |
3468 | ep->debugfs = debugfs_create_file(ep->name, 0444, | |
3469 | root, ep, &ep_fops); | |
3470 | ||
3471 | if (IS_ERR(ep->debugfs)) | |
3472 | dev_err(hsotg->dev, "failed to create %s debug file\n", | |
3473 | ep->name); | |
3474 | } | |
5b7d70c6 BD |
3475 | } |
3476 | } | |
3477 | ||
3478 | /** | |
3479 | * s3c_hsotg_delete_debug - cleanup debugfs entries | |
3480 | * @hsotg: The driver state | |
3481 | * | |
3482 | * Cleanup (remove) the debugfs files for use on module exit. | |
8b9bc460 | 3483 | */ |
941fcce4 | 3484 | static void s3c_hsotg_delete_debug(struct dwc2_hsotg *hsotg) |
5b7d70c6 BD |
3485 | { |
3486 | unsigned epidx; | |
3487 | ||
b3f489b2 | 3488 | for (epidx = 0; epidx < hsotg->num_of_eps; epidx++) { |
c6f5c050 MYK |
3489 | if (hsotg->eps_in[epidx]) |
3490 | debugfs_remove(hsotg->eps_in[epidx]->debugfs); | |
3491 | if (hsotg->eps_out[epidx]) | |
3492 | debugfs_remove(hsotg->eps_out[epidx]->debugfs); | |
5b7d70c6 BD |
3493 | } |
3494 | ||
3495 | debugfs_remove(hsotg->debug_file); | |
3496 | debugfs_remove(hsotg->debug_fifo); | |
3497 | debugfs_remove(hsotg->debug_root); | |
3498 | } | |
3499 | ||
edd74be8 GH |
3500 | #ifdef CONFIG_OF |
3501 | static void s3c_hsotg_of_probe(struct dwc2_hsotg *hsotg) | |
3502 | { | |
3503 | struct device_node *np = hsotg->dev->of_node; | |
0a176279 GH |
3504 | u32 len = 0; |
3505 | u32 i = 0; | |
edd74be8 GH |
3506 | |
3507 | /* Enable dma if requested in device tree */ | |
3508 | hsotg->g_using_dma = of_property_read_bool(np, "g-use-dma"); | |
0a176279 GH |
3509 | |
3510 | /* | |
3511 | * Register TX periodic fifo size per endpoint. | |
3512 | * EP0 is excluded since it has no fifo configuration. | |
3513 | */ | |
3514 | if (!of_find_property(np, "g-tx-fifo-size", &len)) | |
3515 | goto rx_fifo; | |
3516 | ||
3517 | len /= sizeof(u32); | |
3518 | ||
3519 | /* Read tx fifo sizes other than ep0 */ | |
3520 | if (of_property_read_u32_array(np, "g-tx-fifo-size", | |
3521 | &hsotg->g_tx_fifo_sz[1], len)) | |
3522 | goto rx_fifo; | |
3523 | ||
3524 | /* Add ep0 */ | |
3525 | len++; | |
3526 | ||
3527 | /* Make remaining TX fifos unavailable */ | |
3528 | if (len < MAX_EPS_CHANNELS) { | |
3529 | for (i = len; i < MAX_EPS_CHANNELS; i++) | |
3530 | hsotg->g_tx_fifo_sz[i] = 0; | |
3531 | } | |
3532 | ||
3533 | rx_fifo: | |
3534 | /* Register RX fifo size */ | |
3535 | of_property_read_u32(np, "g-rx-fifo-size", &hsotg->g_rx_fifo_sz); | |
3536 | ||
3537 | /* Register NPTX fifo size */ | |
3538 | of_property_read_u32(np, "g-np-tx-fifo-size", | |
3539 | &hsotg->g_np_g_tx_fifo_sz); | |
edd74be8 GH |
3540 | } |
3541 | #else | |
3542 | static inline void s3c_hsotg_of_probe(struct dwc2_hsotg *hsotg) { } | |
3543 | #endif | |
3544 | ||
8b9bc460 | 3545 | /** |
117777b2 DN |
3546 | * dwc2_gadget_init - init function for gadget |
3547 | * @dwc2: The data structure for the DWC2 driver. | |
3548 | * @irq: The IRQ number for the controller. | |
8b9bc460 | 3549 | */ |
117777b2 | 3550 | int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq) |
5b7d70c6 | 3551 | { |
117777b2 DN |
3552 | struct device *dev = hsotg->dev; |
3553 | struct s3c_hsotg_plat *plat = dev->platform_data; | |
5b7d70c6 BD |
3554 | int epnum; |
3555 | int ret; | |
fc9a731e | 3556 | int i; |
0a176279 | 3557 | u32 p_tx_fifo[] = DWC2_G_P_LEGACY_TX_FIFO_SIZE; |
5b7d70c6 | 3558 | |
1b59fc7e KD |
3559 | /* Set default UTMI width */ |
3560 | hsotg->phyif = GUSBCFG_PHYIF16; | |
3561 | ||
edd74be8 GH |
3562 | s3c_hsotg_of_probe(hsotg); |
3563 | ||
0a176279 GH |
3564 | /* Initialize to legacy fifo configuration values */ |
3565 | hsotg->g_rx_fifo_sz = 2048; | |
3566 | hsotg->g_np_g_tx_fifo_sz = 1024; | |
3567 | memcpy(&hsotg->g_tx_fifo_sz[1], p_tx_fifo, sizeof(p_tx_fifo)); | |
3568 | /* Device tree specific probe */ | |
3569 | s3c_hsotg_of_probe(hsotg); | |
3570 | /* Dump fifo information */ | |
3571 | dev_dbg(dev, "NonPeriodic TXFIFO size: %d\n", | |
3572 | hsotg->g_np_g_tx_fifo_sz); | |
3573 | dev_dbg(dev, "RXFIFO size: %d\n", hsotg->g_rx_fifo_sz); | |
3574 | for (i = 0; i < MAX_EPS_CHANNELS; i++) | |
3575 | dev_dbg(dev, "Periodic TXFIFO%2d size: %d\n", i, | |
3576 | hsotg->g_tx_fifo_sz[i]); | |
74084844 | 3577 | /* |
135b3c43 YL |
3578 | * If platform probe couldn't find a generic PHY or an old style |
3579 | * USB PHY, fall back to pdata | |
74084844 | 3580 | */ |
135b3c43 YL |
3581 | if (IS_ERR_OR_NULL(hsotg->phy) && IS_ERR_OR_NULL(hsotg->uphy)) { |
3582 | plat = dev_get_platdata(dev); | |
3583 | if (!plat) { | |
3584 | dev_err(dev, | |
3585 | "no platform data or transceiver defined\n"); | |
3586 | return -EPROBE_DEFER; | |
3587 | } | |
3588 | hsotg->plat = plat; | |
3589 | } else if (hsotg->phy) { | |
1b59fc7e KD |
3590 | /* |
3591 | * If using the generic PHY framework, check if the PHY bus | |
3592 | * width is 8-bit and set the phyif appropriately. | |
3593 | */ | |
135b3c43 | 3594 | if (phy_get_bus_width(hsotg->phy) == 8) |
1b59fc7e KD |
3595 | hsotg->phyif = GUSBCFG_PHYIF8; |
3596 | } | |
b2e587db | 3597 | |
117777b2 | 3598 | hsotg->clk = devm_clk_get(dev, "otg"); |
31ee04de | 3599 | if (IS_ERR(hsotg->clk)) { |
8d736d8a | 3600 | hsotg->clk = NULL; |
f415fbd1 | 3601 | dev_dbg(dev, "cannot get otg clock\n"); |
5b7d70c6 BD |
3602 | } |
3603 | ||
d327ab5b | 3604 | hsotg->gadget.max_speed = USB_SPEED_HIGH; |
5b7d70c6 BD |
3605 | hsotg->gadget.ops = &s3c_hsotg_gadget_ops; |
3606 | hsotg->gadget.name = dev_name(dev); | |
5b7d70c6 | 3607 | |
5b7d70c6 BD |
3608 | /* reset the system */ |
3609 | ||
f415fbd1 DN |
3610 | ret = clk_prepare_enable(hsotg->clk); |
3611 | if (ret) { | |
3612 | dev_err(dev, "failed to enable otg clk\n"); | |
3613 | goto err_clk; | |
3614 | } | |
3615 | ||
31ee04de | 3616 | |
fc9a731e LM |
3617 | /* regulators */ |
3618 | ||
3619 | for (i = 0; i < ARRAY_SIZE(hsotg->supplies); i++) | |
3620 | hsotg->supplies[i].supply = s3c_hsotg_supply_names[i]; | |
3621 | ||
cd76213e | 3622 | ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(hsotg->supplies), |
fc9a731e LM |
3623 | hsotg->supplies); |
3624 | if (ret) { | |
3625 | dev_err(dev, "failed to request supplies: %d\n", ret); | |
338edabc | 3626 | goto err_clk; |
fc9a731e LM |
3627 | } |
3628 | ||
3629 | ret = regulator_bulk_enable(ARRAY_SIZE(hsotg->supplies), | |
3630 | hsotg->supplies); | |
3631 | ||
3632 | if (ret) { | |
941fcce4 | 3633 | dev_err(dev, "failed to enable supplies: %d\n", ret); |
c139ec27 | 3634 | goto err_clk; |
fc9a731e LM |
3635 | } |
3636 | ||
41188786 LM |
3637 | /* usb phy enable */ |
3638 | s3c_hsotg_phy_enable(hsotg); | |
5b7d70c6 | 3639 | |
5b7d70c6 | 3640 | s3c_hsotg_corereset(hsotg); |
c6f5c050 MYK |
3641 | ret = s3c_hsotg_hw_cfg(hsotg); |
3642 | if (ret) { | |
3643 | dev_err(hsotg->dev, "Hardware configuration failed: %d\n", ret); | |
3644 | goto err_clk; | |
3645 | } | |
3646 | ||
cff9eb75 | 3647 | s3c_hsotg_init(hsotg); |
b3f489b2 | 3648 | |
3f95001d MYK |
3649 | hsotg->ctrl_buff = devm_kzalloc(hsotg->dev, |
3650 | DWC2_CTRL_BUFF_SIZE, GFP_KERNEL); | |
3651 | if (!hsotg->ctrl_buff) { | |
3652 | dev_err(dev, "failed to allocate ctrl request buff\n"); | |
3653 | ret = -ENOMEM; | |
3654 | goto err_supplies; | |
3655 | } | |
3656 | ||
3657 | hsotg->ep0_buff = devm_kzalloc(hsotg->dev, | |
3658 | DWC2_CTRL_BUFF_SIZE, GFP_KERNEL); | |
3659 | if (!hsotg->ep0_buff) { | |
3660 | dev_err(dev, "failed to allocate ctrl reply buff\n"); | |
3661 | ret = -ENOMEM; | |
3662 | goto err_supplies; | |
3663 | } | |
3664 | ||
db8178c3 DN |
3665 | ret = devm_request_irq(hsotg->dev, irq, s3c_hsotg_irq, IRQF_SHARED, |
3666 | dev_name(hsotg->dev), hsotg); | |
eb3c56c5 MS |
3667 | if (ret < 0) { |
3668 | s3c_hsotg_phy_disable(hsotg); | |
3669 | clk_disable_unprepare(hsotg->clk); | |
3670 | regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies), | |
3671 | hsotg->supplies); | |
db8178c3 | 3672 | dev_err(dev, "cannot claim IRQ for gadget\n"); |
c139ec27 | 3673 | goto err_supplies; |
eb3c56c5 MS |
3674 | } |
3675 | ||
b3f489b2 LM |
3676 | /* hsotg->num_of_eps holds number of EPs other than ep0 */ |
3677 | ||
3678 | if (hsotg->num_of_eps == 0) { | |
3679 | dev_err(dev, "wrong number of EPs (zero)\n"); | |
dfdda5a0 | 3680 | ret = -EINVAL; |
b3f489b2 LM |
3681 | goto err_supplies; |
3682 | } | |
3683 | ||
b3f489b2 LM |
3684 | /* setup endpoint information */ |
3685 | ||
3686 | INIT_LIST_HEAD(&hsotg->gadget.ep_list); | |
c6f5c050 | 3687 | hsotg->gadget.ep0 = &hsotg->eps_out[0]->ep; |
b3f489b2 LM |
3688 | |
3689 | /* allocate EP0 request */ | |
3690 | ||
c6f5c050 | 3691 | hsotg->ctrl_req = s3c_hsotg_ep_alloc_request(&hsotg->eps_out[0]->ep, |
b3f489b2 LM |
3692 | GFP_KERNEL); |
3693 | if (!hsotg->ctrl_req) { | |
3694 | dev_err(dev, "failed to allocate ctrl req\n"); | |
dfdda5a0 | 3695 | ret = -ENOMEM; |
c6f5c050 | 3696 | goto err_supplies; |
b3f489b2 | 3697 | } |
5b7d70c6 BD |
3698 | |
3699 | /* initialise the endpoints now the core has been initialised */ | |
c6f5c050 MYK |
3700 | for (epnum = 0; epnum < hsotg->num_of_eps; epnum++) { |
3701 | if (hsotg->eps_in[epnum]) | |
3702 | s3c_hsotg_initep(hsotg, hsotg->eps_in[epnum], | |
3703 | epnum, 1); | |
3704 | if (hsotg->eps_out[epnum]) | |
3705 | s3c_hsotg_initep(hsotg, hsotg->eps_out[epnum], | |
3706 | epnum, 0); | |
3707 | } | |
5b7d70c6 | 3708 | |
f65f0f10 | 3709 | /* disable power and clock */ |
3a8146aa | 3710 | s3c_hsotg_phy_disable(hsotg); |
f65f0f10 LM |
3711 | |
3712 | ret = regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies), | |
3713 | hsotg->supplies); | |
3714 | if (ret) { | |
117777b2 | 3715 | dev_err(dev, "failed to disable supplies: %d\n", ret); |
c6f5c050 | 3716 | goto err_supplies; |
f65f0f10 LM |
3717 | } |
3718 | ||
117777b2 | 3719 | ret = usb_add_gadget_udc(dev, &hsotg->gadget); |
0f91349b | 3720 | if (ret) |
c6f5c050 | 3721 | goto err_supplies; |
0f91349b | 3722 | |
5b7d70c6 BD |
3723 | s3c_hsotg_create_debug(hsotg); |
3724 | ||
3725 | s3c_hsotg_dump(hsotg); | |
3726 | ||
5b7d70c6 BD |
3727 | return 0; |
3728 | ||
fc9a731e | 3729 | err_supplies: |
41188786 | 3730 | s3c_hsotg_phy_disable(hsotg); |
31ee04de | 3731 | err_clk: |
1d144c67 | 3732 | clk_disable_unprepare(hsotg->clk); |
338edabc | 3733 | |
5b7d70c6 BD |
3734 | return ret; |
3735 | } | |
117777b2 | 3736 | EXPORT_SYMBOL_GPL(dwc2_gadget_init); |
5b7d70c6 | 3737 | |
8b9bc460 LM |
3738 | /** |
3739 | * s3c_hsotg_remove - remove function for hsotg driver | |
3740 | * @pdev: The platform information for the driver | |
3741 | */ | |
117777b2 | 3742 | int s3c_hsotg_remove(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 3743 | { |
0f91349b | 3744 | usb_del_gadget_udc(&hsotg->gadget); |
5b7d70c6 | 3745 | s3c_hsotg_delete_debug(hsotg); |
04b4a0fc | 3746 | clk_disable_unprepare(hsotg->clk); |
31ee04de | 3747 | |
5b7d70c6 BD |
3748 | return 0; |
3749 | } | |
117777b2 | 3750 | EXPORT_SYMBOL_GPL(s3c_hsotg_remove); |
5b7d70c6 | 3751 | |
117777b2 | 3752 | int s3c_hsotg_suspend(struct dwc2_hsotg *hsotg) |
b83e333a | 3753 | { |
b83e333a MS |
3754 | unsigned long flags; |
3755 | int ret = 0; | |
3756 | ||
7ad8096e MS |
3757 | mutex_lock(&hsotg->init_mutex); |
3758 | ||
dc6e69e6 MS |
3759 | if (hsotg->driver) { |
3760 | int ep; | |
3761 | ||
b83e333a MS |
3762 | dev_info(hsotg->dev, "suspending usb gadget %s\n", |
3763 | hsotg->driver->driver.name); | |
3764 | ||
dc6e69e6 MS |
3765 | spin_lock_irqsave(&hsotg->lock, flags); |
3766 | if (hsotg->enabled) | |
3767 | s3c_hsotg_core_disconnect(hsotg); | |
3768 | s3c_hsotg_disconnect(hsotg); | |
3769 | hsotg->gadget.speed = USB_SPEED_UNKNOWN; | |
3770 | spin_unlock_irqrestore(&hsotg->lock, flags); | |
b83e333a | 3771 | |
dc6e69e6 | 3772 | s3c_hsotg_phy_disable(hsotg); |
b83e333a | 3773 | |
c6f5c050 MYK |
3774 | for (ep = 0; ep < hsotg->num_of_eps; ep++) { |
3775 | if (hsotg->eps_in[ep]) | |
3776 | s3c_hsotg_ep_disable(&hsotg->eps_in[ep]->ep); | |
3777 | if (hsotg->eps_out[ep]) | |
3778 | s3c_hsotg_ep_disable(&hsotg->eps_out[ep]->ep); | |
3779 | } | |
b83e333a MS |
3780 | |
3781 | ret = regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies), | |
3782 | hsotg->supplies); | |
d00b4142 | 3783 | clk_disable(hsotg->clk); |
b83e333a MS |
3784 | } |
3785 | ||
7ad8096e MS |
3786 | mutex_unlock(&hsotg->init_mutex); |
3787 | ||
b83e333a MS |
3788 | return ret; |
3789 | } | |
117777b2 | 3790 | EXPORT_SYMBOL_GPL(s3c_hsotg_suspend); |
b83e333a | 3791 | |
117777b2 | 3792 | int s3c_hsotg_resume(struct dwc2_hsotg *hsotg) |
b83e333a | 3793 | { |
b83e333a MS |
3794 | unsigned long flags; |
3795 | int ret = 0; | |
3796 | ||
7ad8096e MS |
3797 | mutex_lock(&hsotg->init_mutex); |
3798 | ||
b83e333a MS |
3799 | if (hsotg->driver) { |
3800 | dev_info(hsotg->dev, "resuming usb gadget %s\n", | |
3801 | hsotg->driver->driver.name); | |
d00b4142 RB |
3802 | |
3803 | clk_enable(hsotg->clk); | |
b83e333a | 3804 | ret = regulator_bulk_enable(ARRAY_SIZE(hsotg->supplies), |
dc6e69e6 | 3805 | hsotg->supplies); |
b83e333a | 3806 | |
dc6e69e6 | 3807 | s3c_hsotg_phy_enable(hsotg); |
b83e333a | 3808 | |
dc6e69e6 MS |
3809 | spin_lock_irqsave(&hsotg->lock, flags); |
3810 | s3c_hsotg_core_init_disconnected(hsotg); | |
3811 | if (hsotg->enabled) | |
3812 | s3c_hsotg_core_connect(hsotg); | |
3813 | spin_unlock_irqrestore(&hsotg->lock, flags); | |
3814 | } | |
7ad8096e | 3815 | mutex_unlock(&hsotg->init_mutex); |
b83e333a MS |
3816 | |
3817 | return ret; | |
3818 | } | |
117777b2 | 3819 | EXPORT_SYMBOL_GPL(s3c_hsotg_resume); |