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5fd54ace | 1 | // SPDX-License-Identifier: GPL-2.0 |
6fb914d7 | 2 | /* |
dfbc6fa3 AT |
3 | * Copyright (c) 2011 Samsung Electronics Co., Ltd. |
4 | * http://www.samsung.com | |
5b7d70c6 BD |
5 | * |
6 | * Copyright 2008 Openmoko, Inc. | |
7 | * Copyright 2008 Simtec Electronics | |
8 | * Ben Dooks <ben@simtec.co.uk> | |
9 | * http://armlinux.simtec.co.uk/ | |
10 | * | |
11 | * S3C USB2.0 High-speed / OtG driver | |
8b9bc460 | 12 | */ |
5b7d70c6 BD |
13 | |
14 | #include <linux/kernel.h> | |
15 | #include <linux/module.h> | |
16 | #include <linux/spinlock.h> | |
17 | #include <linux/interrupt.h> | |
18 | #include <linux/platform_device.h> | |
19 | #include <linux/dma-mapping.h> | |
7ad8096e | 20 | #include <linux/mutex.h> |
5b7d70c6 BD |
21 | #include <linux/seq_file.h> |
22 | #include <linux/delay.h> | |
23 | #include <linux/io.h> | |
5a0e3ad6 | 24 | #include <linux/slab.h> |
c50f056c | 25 | #include <linux/of_platform.h> |
5b7d70c6 BD |
26 | |
27 | #include <linux/usb/ch9.h> | |
28 | #include <linux/usb/gadget.h> | |
b2e587db | 29 | #include <linux/usb/phy.h> |
b4c53b4a MH |
30 | #include <linux/usb/composite.h> |
31 | ||
5b7d70c6 | 32 | |
f7c0b143 | 33 | #include "core.h" |
941fcce4 | 34 | #include "hw.h" |
5b7d70c6 BD |
35 | |
36 | /* conversion functions */ | |
1f91b4cc | 37 | static inline struct dwc2_hsotg_req *our_req(struct usb_request *req) |
5b7d70c6 | 38 | { |
1f91b4cc | 39 | return container_of(req, struct dwc2_hsotg_req, req); |
5b7d70c6 BD |
40 | } |
41 | ||
1f91b4cc | 42 | static inline struct dwc2_hsotg_ep *our_ep(struct usb_ep *ep) |
5b7d70c6 | 43 | { |
1f91b4cc | 44 | return container_of(ep, struct dwc2_hsotg_ep, ep); |
5b7d70c6 BD |
45 | } |
46 | ||
941fcce4 | 47 | static inline struct dwc2_hsotg *to_hsotg(struct usb_gadget *gadget) |
5b7d70c6 | 48 | { |
941fcce4 | 49 | return container_of(gadget, struct dwc2_hsotg, gadget); |
5b7d70c6 BD |
50 | } |
51 | ||
f25c42b8 | 52 | static inline void dwc2_set_bit(struct dwc2_hsotg *hsotg, u32 offset, u32 val) |
5b7d70c6 | 53 | { |
f25c42b8 | 54 | dwc2_writel(hsotg, dwc2_readl(hsotg, offset) | val, offset); |
5b7d70c6 BD |
55 | } |
56 | ||
f25c42b8 | 57 | static inline void dwc2_clear_bit(struct dwc2_hsotg *hsotg, u32 offset, u32 val) |
5b7d70c6 | 58 | { |
f25c42b8 | 59 | dwc2_writel(hsotg, dwc2_readl(hsotg, offset) & ~val, offset); |
5b7d70c6 BD |
60 | } |
61 | ||
1f91b4cc | 62 | static inline struct dwc2_hsotg_ep *index_to_ep(struct dwc2_hsotg *hsotg, |
c6f5c050 MYK |
63 | u32 ep_index, u32 dir_in) |
64 | { | |
65 | if (dir_in) | |
66 | return hsotg->eps_in[ep_index]; | |
67 | else | |
68 | return hsotg->eps_out[ep_index]; | |
69 | } | |
70 | ||
997f4f81 | 71 | /* forward declaration of functions */ |
1f91b4cc | 72 | static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg); |
5b7d70c6 BD |
73 | |
74 | /** | |
75 | * using_dma - return the DMA status of the driver. | |
76 | * @hsotg: The driver state. | |
77 | * | |
78 | * Return true if we're using DMA. | |
79 | * | |
80 | * Currently, we have the DMA support code worked into everywhere | |
81 | * that needs it, but the AMBA DMA implementation in the hardware can | |
82 | * only DMA from 32bit aligned addresses. This means that gadgets such | |
83 | * as the CDC Ethernet cannot work as they often pass packets which are | |
84 | * not 32bit aligned. | |
85 | * | |
86 | * Unfortunately the choice to use DMA or not is global to the controller | |
87 | * and seems to be only settable when the controller is being put through | |
88 | * a core reset. This means we either need to fix the gadgets to take | |
89 | * account of DMA alignment, or add bounce buffers (yuerk). | |
90 | * | |
edd74be8 | 91 | * g_using_dma is set depending on dts flag. |
5b7d70c6 | 92 | */ |
941fcce4 | 93 | static inline bool using_dma(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 94 | { |
05ee799f | 95 | return hsotg->params.g_dma; |
5b7d70c6 BD |
96 | } |
97 | ||
dec4b556 VA |
98 | /* |
99 | * using_desc_dma - return the descriptor DMA status of the driver. | |
100 | * @hsotg: The driver state. | |
101 | * | |
102 | * Return true if we're using descriptor DMA. | |
103 | */ | |
104 | static inline bool using_desc_dma(struct dwc2_hsotg *hsotg) | |
105 | { | |
106 | return hsotg->params.g_dma_desc; | |
107 | } | |
108 | ||
92d1635d VM |
109 | /** |
110 | * dwc2_gadget_incr_frame_num - Increments the targeted frame number. | |
111 | * @hs_ep: The endpoint | |
92d1635d VM |
112 | * |
113 | * This function will also check if the frame number overruns DSTS_SOFFN_LIMIT. | |
114 | * If an overrun occurs it will wrap the value and set the frame_overrun flag. | |
115 | */ | |
116 | static inline void dwc2_gadget_incr_frame_num(struct dwc2_hsotg_ep *hs_ep) | |
117 | { | |
118 | hs_ep->target_frame += hs_ep->interval; | |
119 | if (hs_ep->target_frame > DSTS_SOFFN_LIMIT) { | |
c1d5df69 | 120 | hs_ep->frame_overrun = true; |
92d1635d VM |
121 | hs_ep->target_frame &= DSTS_SOFFN_LIMIT; |
122 | } else { | |
c1d5df69 | 123 | hs_ep->frame_overrun = false; |
92d1635d VM |
124 | } |
125 | } | |
126 | ||
9d630b9c GT |
127 | /** |
128 | * dwc2_gadget_dec_frame_num_by_one - Decrements the targeted frame number | |
129 | * by one. | |
130 | * @hs_ep: The endpoint. | |
131 | * | |
132 | * This function used in service interval based scheduling flow to calculate | |
133 | * descriptor frame number filed value. For service interval mode frame | |
134 | * number in descriptor should point to last (u)frame in the interval. | |
135 | * | |
136 | */ | |
137 | static inline void dwc2_gadget_dec_frame_num_by_one(struct dwc2_hsotg_ep *hs_ep) | |
138 | { | |
139 | if (hs_ep->target_frame) | |
140 | hs_ep->target_frame -= 1; | |
141 | else | |
142 | hs_ep->target_frame = DSTS_SOFFN_LIMIT; | |
143 | } | |
144 | ||
5b7d70c6 | 145 | /** |
1f91b4cc | 146 | * dwc2_hsotg_en_gsint - enable one or more of the general interrupt |
5b7d70c6 BD |
147 | * @hsotg: The device state |
148 | * @ints: A bitmask of the interrupts to enable | |
149 | */ | |
1f91b4cc | 150 | static void dwc2_hsotg_en_gsint(struct dwc2_hsotg *hsotg, u32 ints) |
5b7d70c6 | 151 | { |
f25c42b8 | 152 | u32 gsintmsk = dwc2_readl(hsotg, GINTMSK); |
5b7d70c6 BD |
153 | u32 new_gsintmsk; |
154 | ||
155 | new_gsintmsk = gsintmsk | ints; | |
156 | ||
157 | if (new_gsintmsk != gsintmsk) { | |
158 | dev_dbg(hsotg->dev, "gsintmsk now 0x%08x\n", new_gsintmsk); | |
f25c42b8 | 159 | dwc2_writel(hsotg, new_gsintmsk, GINTMSK); |
5b7d70c6 BD |
160 | } |
161 | } | |
162 | ||
163 | /** | |
1f91b4cc | 164 | * dwc2_hsotg_disable_gsint - disable one or more of the general interrupt |
5b7d70c6 BD |
165 | * @hsotg: The device state |
166 | * @ints: A bitmask of the interrupts to enable | |
167 | */ | |
1f91b4cc | 168 | static void dwc2_hsotg_disable_gsint(struct dwc2_hsotg *hsotg, u32 ints) |
5b7d70c6 | 169 | { |
f25c42b8 | 170 | u32 gsintmsk = dwc2_readl(hsotg, GINTMSK); |
5b7d70c6 BD |
171 | u32 new_gsintmsk; |
172 | ||
173 | new_gsintmsk = gsintmsk & ~ints; | |
174 | ||
175 | if (new_gsintmsk != gsintmsk) | |
f25c42b8 | 176 | dwc2_writel(hsotg, new_gsintmsk, GINTMSK); |
5b7d70c6 BD |
177 | } |
178 | ||
179 | /** | |
1f91b4cc | 180 | * dwc2_hsotg_ctrl_epint - enable/disable an endpoint irq |
5b7d70c6 BD |
181 | * @hsotg: The device state |
182 | * @ep: The endpoint index | |
183 | * @dir_in: True if direction is in. | |
184 | * @en: The enable value, true to enable | |
185 | * | |
186 | * Set or clear the mask for an individual endpoint's interrupt | |
187 | * request. | |
188 | */ | |
1f91b4cc | 189 | static void dwc2_hsotg_ctrl_epint(struct dwc2_hsotg *hsotg, |
9da51974 | 190 | unsigned int ep, unsigned int dir_in, |
5b7d70c6 BD |
191 | unsigned int en) |
192 | { | |
193 | unsigned long flags; | |
194 | u32 bit = 1 << ep; | |
195 | u32 daint; | |
196 | ||
197 | if (!dir_in) | |
198 | bit <<= 16; | |
199 | ||
200 | local_irq_save(flags); | |
f25c42b8 | 201 | daint = dwc2_readl(hsotg, DAINTMSK); |
5b7d70c6 BD |
202 | if (en) |
203 | daint |= bit; | |
204 | else | |
205 | daint &= ~bit; | |
f25c42b8 | 206 | dwc2_writel(hsotg, daint, DAINTMSK); |
5b7d70c6 BD |
207 | local_irq_restore(flags); |
208 | } | |
209 | ||
c138ecfa SA |
210 | /** |
211 | * dwc2_hsotg_tx_fifo_count - return count of TX FIFOs in device mode | |
6fb914d7 GT |
212 | * |
213 | * @hsotg: Programming view of the DWC_otg controller | |
c138ecfa SA |
214 | */ |
215 | int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg *hsotg) | |
216 | { | |
217 | if (hsotg->hw_params.en_multiple_tx_fifo) | |
218 | /* In dedicated FIFO mode we need count of IN EPs */ | |
9273083a | 219 | return hsotg->hw_params.num_dev_in_eps; |
c138ecfa SA |
220 | else |
221 | /* In shared FIFO mode we need count of Periodic IN EPs */ | |
222 | return hsotg->hw_params.num_dev_perio_in_ep; | |
223 | } | |
224 | ||
c138ecfa SA |
225 | /** |
226 | * dwc2_hsotg_tx_fifo_total_depth - return total FIFO depth available for | |
227 | * device mode TX FIFOs | |
6fb914d7 GT |
228 | * |
229 | * @hsotg: Programming view of the DWC_otg controller | |
c138ecfa SA |
230 | */ |
231 | int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg) | |
232 | { | |
c138ecfa SA |
233 | int addr; |
234 | int tx_addr_max; | |
235 | u32 np_tx_fifo_size; | |
236 | ||
237 | np_tx_fifo_size = min_t(u32, hsotg->hw_params.dev_nperio_tx_fifo_size, | |
238 | hsotg->params.g_np_tx_fifo_size); | |
239 | ||
240 | /* Get Endpoint Info Control block size in DWORDs. */ | |
9273083a | 241 | tx_addr_max = hsotg->hw_params.total_fifo_size; |
c138ecfa SA |
242 | |
243 | addr = hsotg->params.g_rx_fifo_size + np_tx_fifo_size; | |
244 | if (tx_addr_max <= addr) | |
245 | return 0; | |
246 | ||
247 | return tx_addr_max - addr; | |
248 | } | |
249 | ||
187c5298 GT |
250 | /** |
251 | * dwc2_gadget_wkup_alert_handler - Handler for WKUP_ALERT interrupt | |
252 | * | |
253 | * @hsotg: Programming view of the DWC_otg controller | |
254 | * | |
255 | */ | |
256 | static void dwc2_gadget_wkup_alert_handler(struct dwc2_hsotg *hsotg) | |
257 | { | |
258 | u32 gintsts2; | |
259 | u32 gintmsk2; | |
260 | ||
261 | gintsts2 = dwc2_readl(hsotg, GINTSTS2); | |
262 | gintmsk2 = dwc2_readl(hsotg, GINTMSK2); | |
9607f3cd | 263 | gintsts2 &= gintmsk2; |
187c5298 GT |
264 | |
265 | if (gintsts2 & GINTSTS2_WKUP_ALERT_INT) { | |
266 | dev_dbg(hsotg->dev, "%s: Wkup_Alert_Int\n", __func__); | |
87b6d2c5 | 267 | dwc2_set_bit(hsotg, GINTSTS2, GINTSTS2_WKUP_ALERT_INT); |
d64bc8ee | 268 | dwc2_set_bit(hsotg, DCTL, DCTL_RMTWKUPSIG); |
187c5298 GT |
269 | } |
270 | } | |
271 | ||
c138ecfa SA |
272 | /** |
273 | * dwc2_hsotg_tx_fifo_average_depth - returns average depth of device mode | |
274 | * TX FIFOs | |
6fb914d7 GT |
275 | * |
276 | * @hsotg: Programming view of the DWC_otg controller | |
c138ecfa SA |
277 | */ |
278 | int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg *hsotg) | |
279 | { | |
280 | int tx_fifo_count; | |
281 | int tx_fifo_depth; | |
282 | ||
283 | tx_fifo_depth = dwc2_hsotg_tx_fifo_total_depth(hsotg); | |
284 | ||
285 | tx_fifo_count = dwc2_hsotg_tx_fifo_count(hsotg); | |
286 | ||
287 | if (!tx_fifo_count) | |
288 | return tx_fifo_depth; | |
289 | else | |
290 | return tx_fifo_depth / tx_fifo_count; | |
291 | } | |
292 | ||
5b7d70c6 | 293 | /** |
1f91b4cc | 294 | * dwc2_hsotg_init_fifo - initialise non-periodic FIFOs |
5b7d70c6 BD |
295 | * @hsotg: The device instance. |
296 | */ | |
1f91b4cc | 297 | static void dwc2_hsotg_init_fifo(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 298 | { |
2317eacd | 299 | unsigned int ep; |
0f002d20 | 300 | unsigned int addr; |
1703a6d3 | 301 | int timeout; |
79d6b8c5 | 302 | |
0f002d20 | 303 | u32 val; |
05ee799f | 304 | u32 *txfsz = hsotg->params.g_tx_fifo_size; |
0f002d20 | 305 | |
7fcbc95c GH |
306 | /* Reset fifo map if not correctly cleared during previous session */ |
307 | WARN_ON(hsotg->fifo_map); | |
308 | hsotg->fifo_map = 0; | |
309 | ||
0a176279 | 310 | /* set RX/NPTX FIFO sizes */ |
f25c42b8 GS |
311 | dwc2_writel(hsotg, hsotg->params.g_rx_fifo_size, GRXFSIZ); |
312 | dwc2_writel(hsotg, (hsotg->params.g_rx_fifo_size << | |
313 | FIFOSIZE_STARTADDR_SHIFT) | | |
05ee799f | 314 | (hsotg->params.g_np_tx_fifo_size << FIFOSIZE_DEPTH_SHIFT), |
f25c42b8 | 315 | GNPTXFSIZ); |
0f002d20 | 316 | |
8b9bc460 LM |
317 | /* |
318 | * arange all the rest of the TX FIFOs, as some versions of this | |
0f002d20 BD |
319 | * block have overlapping default addresses. This also ensures |
320 | * that if the settings have been changed, then they are set to | |
8b9bc460 LM |
321 | * known values. |
322 | */ | |
0f002d20 BD |
323 | |
324 | /* start at the end of the GNPTXFSIZ, rounded up */ | |
05ee799f | 325 | addr = hsotg->params.g_rx_fifo_size + hsotg->params.g_np_tx_fifo_size; |
0f002d20 | 326 | |
8b9bc460 | 327 | /* |
0a176279 | 328 | * Configure fifos sizes from provided configuration and assign |
b203d0a2 RB |
329 | * them to endpoints dynamically according to maxpacket size value of |
330 | * given endpoint. | |
8b9bc460 | 331 | */ |
2317eacd | 332 | for (ep = 1; ep < MAX_EPS_CHANNELS; ep++) { |
05ee799f | 333 | if (!txfsz[ep]) |
3fa95385 JY |
334 | continue; |
335 | val = addr; | |
05ee799f JY |
336 | val |= txfsz[ep] << FIFOSIZE_DEPTH_SHIFT; |
337 | WARN_ONCE(addr + txfsz[ep] > hsotg->fifo_mem, | |
3fa95385 | 338 | "insufficient fifo memory"); |
05ee799f | 339 | addr += txfsz[ep]; |
0f002d20 | 340 | |
f25c42b8 GS |
341 | dwc2_writel(hsotg, val, DPTXFSIZN(ep)); |
342 | val = dwc2_readl(hsotg, DPTXFSIZN(ep)); | |
0f002d20 | 343 | } |
1703a6d3 | 344 | |
f25c42b8 | 345 | dwc2_writel(hsotg, hsotg->hw_params.total_fifo_size | |
f87c842f | 346 | addr << GDFIFOCFG_EPINFOBASE_SHIFT, |
f25c42b8 | 347 | GDFIFOCFG); |
8b9bc460 LM |
348 | /* |
349 | * according to p428 of the design guide, we need to ensure that | |
350 | * all fifos are flushed before continuing | |
351 | */ | |
1703a6d3 | 352 | |
f25c42b8 GS |
353 | dwc2_writel(hsotg, GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH | |
354 | GRSTCTL_RXFFLSH, GRSTCTL); | |
1703a6d3 BD |
355 | |
356 | /* wait until the fifos are both flushed */ | |
357 | timeout = 100; | |
358 | while (1) { | |
f25c42b8 | 359 | val = dwc2_readl(hsotg, GRSTCTL); |
1703a6d3 | 360 | |
47a1685f | 361 | if ((val & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH)) == 0) |
1703a6d3 BD |
362 | break; |
363 | ||
364 | if (--timeout == 0) { | |
365 | dev_err(hsotg->dev, | |
366 | "%s: timeout flushing fifos (GRSTCTL=%08x)\n", | |
367 | __func__, val); | |
48b20bcb | 368 | break; |
1703a6d3 BD |
369 | } |
370 | ||
371 | udelay(1); | |
372 | } | |
373 | ||
374 | dev_dbg(hsotg->dev, "FIFOs reset, timeout at %d\n", timeout); | |
5b7d70c6 BD |
375 | } |
376 | ||
377 | /** | |
6fb914d7 | 378 | * dwc2_hsotg_ep_alloc_request - allocate USB rerequest structure |
5b7d70c6 BD |
379 | * @ep: USB endpoint to allocate request for. |
380 | * @flags: Allocation flags | |
381 | * | |
382 | * Allocate a new USB request structure appropriate for the specified endpoint | |
383 | */ | |
1f91b4cc | 384 | static struct usb_request *dwc2_hsotg_ep_alloc_request(struct usb_ep *ep, |
9da51974 | 385 | gfp_t flags) |
5b7d70c6 | 386 | { |
1f91b4cc | 387 | struct dwc2_hsotg_req *req; |
5b7d70c6 | 388 | |
ec33efe2 | 389 | req = kzalloc(sizeof(*req), flags); |
5b7d70c6 BD |
390 | if (!req) |
391 | return NULL; | |
392 | ||
393 | INIT_LIST_HEAD(&req->queue); | |
394 | ||
5b7d70c6 BD |
395 | return &req->req; |
396 | } | |
397 | ||
398 | /** | |
399 | * is_ep_periodic - return true if the endpoint is in periodic mode. | |
400 | * @hs_ep: The endpoint to query. | |
401 | * | |
402 | * Returns true if the endpoint is in periodic mode, meaning it is being | |
403 | * used for an Interrupt or ISO transfer. | |
404 | */ | |
1f91b4cc | 405 | static inline int is_ep_periodic(struct dwc2_hsotg_ep *hs_ep) |
5b7d70c6 BD |
406 | { |
407 | return hs_ep->periodic; | |
408 | } | |
409 | ||
410 | /** | |
1f91b4cc | 411 | * dwc2_hsotg_unmap_dma - unmap the DMA memory being used for the request |
5b7d70c6 BD |
412 | * @hsotg: The device state. |
413 | * @hs_ep: The endpoint for the request | |
414 | * @hs_req: The request being processed. | |
415 | * | |
1f91b4cc | 416 | * This is the reverse of dwc2_hsotg_map_dma(), called for the completion |
5b7d70c6 | 417 | * of a request to ensure the buffer is ready for access by the caller. |
8b9bc460 | 418 | */ |
1f91b4cc | 419 | static void dwc2_hsotg_unmap_dma(struct dwc2_hsotg *hsotg, |
9da51974 | 420 | struct dwc2_hsotg_ep *hs_ep, |
1f91b4cc | 421 | struct dwc2_hsotg_req *hs_req) |
5b7d70c6 BD |
422 | { |
423 | struct usb_request *req = &hs_req->req; | |
9da51974 | 424 | |
17d966a3 | 425 | usb_gadget_unmap_request(&hsotg->gadget, req, hs_ep->dir_in); |
5b7d70c6 BD |
426 | } |
427 | ||
0f6b80c0 VA |
428 | /* |
429 | * dwc2_gadget_alloc_ctrl_desc_chains - allocate DMA descriptor chains | |
430 | * for Control endpoint | |
431 | * @hsotg: The device state. | |
432 | * | |
433 | * This function will allocate 4 descriptor chains for EP 0: 2 for | |
434 | * Setup stage, per one for IN and OUT data/status transactions. | |
435 | */ | |
436 | static int dwc2_gadget_alloc_ctrl_desc_chains(struct dwc2_hsotg *hsotg) | |
437 | { | |
438 | hsotg->setup_desc[0] = | |
439 | dmam_alloc_coherent(hsotg->dev, | |
440 | sizeof(struct dwc2_dma_desc), | |
441 | &hsotg->setup_desc_dma[0], | |
442 | GFP_KERNEL); | |
443 | if (!hsotg->setup_desc[0]) | |
444 | goto fail; | |
445 | ||
446 | hsotg->setup_desc[1] = | |
447 | dmam_alloc_coherent(hsotg->dev, | |
448 | sizeof(struct dwc2_dma_desc), | |
449 | &hsotg->setup_desc_dma[1], | |
450 | GFP_KERNEL); | |
451 | if (!hsotg->setup_desc[1]) | |
452 | goto fail; | |
453 | ||
454 | hsotg->ctrl_in_desc = | |
455 | dmam_alloc_coherent(hsotg->dev, | |
456 | sizeof(struct dwc2_dma_desc), | |
457 | &hsotg->ctrl_in_desc_dma, | |
458 | GFP_KERNEL); | |
459 | if (!hsotg->ctrl_in_desc) | |
460 | goto fail; | |
461 | ||
462 | hsotg->ctrl_out_desc = | |
463 | dmam_alloc_coherent(hsotg->dev, | |
464 | sizeof(struct dwc2_dma_desc), | |
465 | &hsotg->ctrl_out_desc_dma, | |
466 | GFP_KERNEL); | |
467 | if (!hsotg->ctrl_out_desc) | |
468 | goto fail; | |
469 | ||
470 | return 0; | |
471 | ||
472 | fail: | |
473 | return -ENOMEM; | |
474 | } | |
475 | ||
5b7d70c6 | 476 | /** |
1f91b4cc | 477 | * dwc2_hsotg_write_fifo - write packet Data to the TxFIFO |
5b7d70c6 BD |
478 | * @hsotg: The controller state. |
479 | * @hs_ep: The endpoint we're going to write for. | |
480 | * @hs_req: The request to write data for. | |
481 | * | |
482 | * This is called when the TxFIFO has some space in it to hold a new | |
483 | * transmission and we have something to give it. The actual setup of | |
484 | * the data size is done elsewhere, so all we have to do is to actually | |
485 | * write the data. | |
486 | * | |
487 | * The return value is zero if there is more space (or nothing was done) | |
488 | * otherwise -ENOSPC is returned if the FIFO space was used up. | |
489 | * | |
490 | * This routine is only needed for PIO | |
8b9bc460 | 491 | */ |
1f91b4cc | 492 | static int dwc2_hsotg_write_fifo(struct dwc2_hsotg *hsotg, |
9da51974 | 493 | struct dwc2_hsotg_ep *hs_ep, |
1f91b4cc | 494 | struct dwc2_hsotg_req *hs_req) |
5b7d70c6 BD |
495 | { |
496 | bool periodic = is_ep_periodic(hs_ep); | |
f25c42b8 | 497 | u32 gnptxsts = dwc2_readl(hsotg, GNPTXSTS); |
5b7d70c6 BD |
498 | int buf_pos = hs_req->req.actual; |
499 | int to_write = hs_ep->size_loaded; | |
500 | void *data; | |
501 | int can_write; | |
502 | int pkt_round; | |
4fca54aa | 503 | int max_transfer; |
5b7d70c6 BD |
504 | |
505 | to_write -= (buf_pos - hs_ep->last_load); | |
506 | ||
507 | /* if there's nothing to write, get out early */ | |
508 | if (to_write == 0) | |
509 | return 0; | |
510 | ||
10aebc77 | 511 | if (periodic && !hsotg->dedicated_fifos) { |
f25c42b8 | 512 | u32 epsize = dwc2_readl(hsotg, DIEPTSIZ(hs_ep->index)); |
5b7d70c6 BD |
513 | int size_left; |
514 | int size_done; | |
515 | ||
8b9bc460 LM |
516 | /* |
517 | * work out how much data was loaded so we can calculate | |
518 | * how much data is left in the fifo. | |
519 | */ | |
5b7d70c6 | 520 | |
47a1685f | 521 | size_left = DXEPTSIZ_XFERSIZE_GET(epsize); |
5b7d70c6 | 522 | |
8b9bc460 LM |
523 | /* |
524 | * if shared fifo, we cannot write anything until the | |
e7a9ff54 BD |
525 | * previous data has been completely sent. |
526 | */ | |
527 | if (hs_ep->fifo_load != 0) { | |
1f91b4cc | 528 | dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP); |
e7a9ff54 BD |
529 | return -ENOSPC; |
530 | } | |
531 | ||
5b7d70c6 BD |
532 | dev_dbg(hsotg->dev, "%s: left=%d, load=%d, fifo=%d, size %d\n", |
533 | __func__, size_left, | |
534 | hs_ep->size_loaded, hs_ep->fifo_load, hs_ep->fifo_size); | |
535 | ||
536 | /* how much of the data has moved */ | |
537 | size_done = hs_ep->size_loaded - size_left; | |
538 | ||
539 | /* how much data is left in the fifo */ | |
540 | can_write = hs_ep->fifo_load - size_done; | |
541 | dev_dbg(hsotg->dev, "%s: => can_write1=%d\n", | |
542 | __func__, can_write); | |
543 | ||
544 | can_write = hs_ep->fifo_size - can_write; | |
545 | dev_dbg(hsotg->dev, "%s: => can_write2=%d\n", | |
546 | __func__, can_write); | |
547 | ||
548 | if (can_write <= 0) { | |
1f91b4cc | 549 | dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP); |
5b7d70c6 BD |
550 | return -ENOSPC; |
551 | } | |
10aebc77 | 552 | } else if (hsotg->dedicated_fifos && hs_ep->index != 0) { |
f25c42b8 GS |
553 | can_write = dwc2_readl(hsotg, |
554 | DTXFSTS(hs_ep->fifo_index)); | |
10aebc77 BD |
555 | |
556 | can_write &= 0xffff; | |
557 | can_write *= 4; | |
5b7d70c6 | 558 | } else { |
47a1685f | 559 | if (GNPTXSTS_NP_TXQ_SPC_AVAIL_GET(gnptxsts) == 0) { |
5b7d70c6 BD |
560 | dev_dbg(hsotg->dev, |
561 | "%s: no queue slots available (0x%08x)\n", | |
562 | __func__, gnptxsts); | |
563 | ||
1f91b4cc | 564 | dwc2_hsotg_en_gsint(hsotg, GINTSTS_NPTXFEMP); |
5b7d70c6 BD |
565 | return -ENOSPC; |
566 | } | |
567 | ||
47a1685f | 568 | can_write = GNPTXSTS_NP_TXF_SPC_AVAIL_GET(gnptxsts); |
679f9b7c | 569 | can_write *= 4; /* fifo size is in 32bit quantities. */ |
5b7d70c6 BD |
570 | } |
571 | ||
4fca54aa RB |
572 | max_transfer = hs_ep->ep.maxpacket * hs_ep->mc; |
573 | ||
574 | dev_dbg(hsotg->dev, "%s: GNPTXSTS=%08x, can=%d, to=%d, max_transfer %d\n", | |
9da51974 | 575 | __func__, gnptxsts, can_write, to_write, max_transfer); |
5b7d70c6 | 576 | |
8b9bc460 LM |
577 | /* |
578 | * limit to 512 bytes of data, it seems at least on the non-periodic | |
5b7d70c6 BD |
579 | * FIFO, requests of >512 cause the endpoint to get stuck with a |
580 | * fragment of the end of the transfer in it. | |
581 | */ | |
811f3303 | 582 | if (can_write > 512 && !periodic) |
5b7d70c6 BD |
583 | can_write = 512; |
584 | ||
8b9bc460 LM |
585 | /* |
586 | * limit the write to one max-packet size worth of data, but allow | |
03e10e5a | 587 | * the transfer to return that it did not run out of fifo space |
8b9bc460 LM |
588 | * doing it. |
589 | */ | |
4fca54aa RB |
590 | if (to_write > max_transfer) { |
591 | to_write = max_transfer; | |
03e10e5a | 592 | |
5cb2ff0c RB |
593 | /* it's needed only when we do not use dedicated fifos */ |
594 | if (!hsotg->dedicated_fifos) | |
1f91b4cc | 595 | dwc2_hsotg_en_gsint(hsotg, |
9da51974 | 596 | periodic ? GINTSTS_PTXFEMP : |
47a1685f | 597 | GINTSTS_NPTXFEMP); |
03e10e5a BD |
598 | } |
599 | ||
5b7d70c6 BD |
600 | /* see if we can write data */ |
601 | ||
602 | if (to_write > can_write) { | |
603 | to_write = can_write; | |
4fca54aa | 604 | pkt_round = to_write % max_transfer; |
5b7d70c6 | 605 | |
8b9bc460 LM |
606 | /* |
607 | * Round the write down to an | |
5b7d70c6 BD |
608 | * exact number of packets. |
609 | * | |
610 | * Note, we do not currently check to see if we can ever | |
611 | * write a full packet or not to the FIFO. | |
612 | */ | |
613 | ||
614 | if (pkt_round) | |
615 | to_write -= pkt_round; | |
616 | ||
8b9bc460 LM |
617 | /* |
618 | * enable correct FIFO interrupt to alert us when there | |
619 | * is more room left. | |
620 | */ | |
5b7d70c6 | 621 | |
5cb2ff0c RB |
622 | /* it's needed only when we do not use dedicated fifos */ |
623 | if (!hsotg->dedicated_fifos) | |
1f91b4cc | 624 | dwc2_hsotg_en_gsint(hsotg, |
9da51974 | 625 | periodic ? GINTSTS_PTXFEMP : |
47a1685f | 626 | GINTSTS_NPTXFEMP); |
5b7d70c6 BD |
627 | } |
628 | ||
629 | dev_dbg(hsotg->dev, "write %d/%d, can_write %d, done %d\n", | |
9da51974 | 630 | to_write, hs_req->req.length, can_write, buf_pos); |
5b7d70c6 BD |
631 | |
632 | if (to_write <= 0) | |
633 | return -ENOSPC; | |
634 | ||
635 | hs_req->req.actual = buf_pos + to_write; | |
636 | hs_ep->total_data += to_write; | |
637 | ||
638 | if (periodic) | |
639 | hs_ep->fifo_load += to_write; | |
640 | ||
641 | to_write = DIV_ROUND_UP(to_write, 4); | |
642 | data = hs_req->req.buf + buf_pos; | |
643 | ||
342ccce1 | 644 | dwc2_writel_rep(hsotg, EPFIFO(hs_ep->index), data, to_write); |
5b7d70c6 BD |
645 | |
646 | return (to_write >= can_write) ? -ENOSPC : 0; | |
647 | } | |
648 | ||
649 | /** | |
650 | * get_ep_limit - get the maximum data legnth for this endpoint | |
651 | * @hs_ep: The endpoint | |
652 | * | |
653 | * Return the maximum data that can be queued in one go on a given endpoint | |
654 | * so that transfers that are too long can be split. | |
655 | */ | |
9da51974 | 656 | static unsigned int get_ep_limit(struct dwc2_hsotg_ep *hs_ep) |
5b7d70c6 BD |
657 | { |
658 | int index = hs_ep->index; | |
9da51974 JY |
659 | unsigned int maxsize; |
660 | unsigned int maxpkt; | |
5b7d70c6 BD |
661 | |
662 | if (index != 0) { | |
47a1685f DN |
663 | maxsize = DXEPTSIZ_XFERSIZE_LIMIT + 1; |
664 | maxpkt = DXEPTSIZ_PKTCNT_LIMIT + 1; | |
5b7d70c6 | 665 | } else { |
9da51974 | 666 | maxsize = 64 + 64; |
66e5c643 | 667 | if (hs_ep->dir_in) |
47a1685f | 668 | maxpkt = DIEPTSIZ0_PKTCNT_LIMIT + 1; |
66e5c643 | 669 | else |
5b7d70c6 | 670 | maxpkt = 2; |
5b7d70c6 BD |
671 | } |
672 | ||
673 | /* we made the constant loading easier above by using +1 */ | |
674 | maxpkt--; | |
675 | maxsize--; | |
676 | ||
8b9bc460 LM |
677 | /* |
678 | * constrain by packet count if maxpkts*pktsize is greater | |
679 | * than the length register size. | |
680 | */ | |
5b7d70c6 BD |
681 | |
682 | if ((maxpkt * hs_ep->ep.maxpacket) < maxsize) | |
683 | maxsize = maxpkt * hs_ep->ep.maxpacket; | |
684 | ||
685 | return maxsize; | |
686 | } | |
687 | ||
381fc8f8 | 688 | /** |
38beaec6 JY |
689 | * dwc2_hsotg_read_frameno - read current frame number |
690 | * @hsotg: The device instance | |
691 | * | |
692 | * Return the current frame number | |
693 | */ | |
381fc8f8 VM |
694 | static u32 dwc2_hsotg_read_frameno(struct dwc2_hsotg *hsotg) |
695 | { | |
696 | u32 dsts; | |
697 | ||
f25c42b8 | 698 | dsts = dwc2_readl(hsotg, DSTS); |
381fc8f8 VM |
699 | dsts &= DSTS_SOFFN_MASK; |
700 | dsts >>= DSTS_SOFFN_SHIFT; | |
701 | ||
702 | return dsts; | |
703 | } | |
704 | ||
cf77b5fb VA |
705 | /** |
706 | * dwc2_gadget_get_chain_limit - get the maximum data payload value of the | |
707 | * DMA descriptor chain prepared for specific endpoint | |
708 | * @hs_ep: The endpoint | |
709 | * | |
710 | * Return the maximum data that can be queued in one go on a given endpoint | |
711 | * depending on its descriptor chain capacity so that transfers that | |
712 | * are too long can be split. | |
713 | */ | |
714 | static unsigned int dwc2_gadget_get_chain_limit(struct dwc2_hsotg_ep *hs_ep) | |
715 | { | |
b2c586eb | 716 | const struct usb_endpoint_descriptor *ep_desc = hs_ep->ep.desc; |
cf77b5fb VA |
717 | int is_isoc = hs_ep->isochronous; |
718 | unsigned int maxsize; | |
b2c586eb MH |
719 | u32 mps = hs_ep->ep.maxpacket; |
720 | int dir_in = hs_ep->dir_in; | |
cf77b5fb VA |
721 | |
722 | if (is_isoc) | |
54f37f56 MH |
723 | maxsize = (hs_ep->dir_in ? DEV_DMA_ISOC_TX_NBYTES_LIMIT : |
724 | DEV_DMA_ISOC_RX_NBYTES_LIMIT) * | |
725 | MAX_DMA_DESC_NUM_HS_ISOC; | |
cf77b5fb | 726 | else |
54f37f56 | 727 | maxsize = DEV_DMA_NBYTES_LIMIT * MAX_DMA_DESC_NUM_GENERIC; |
cf77b5fb | 728 | |
b2c586eb MH |
729 | /* Interrupt OUT EP with mps not multiple of 4 */ |
730 | if (hs_ep->index) | |
731 | if (usb_endpoint_xfer_int(ep_desc) && !dir_in && (mps % 4)) | |
732 | maxsize = mps * MAX_DMA_DESC_NUM_GENERIC; | |
733 | ||
cf77b5fb VA |
734 | return maxsize; |
735 | } | |
736 | ||
e02f9aa6 VA |
737 | /* |
738 | * dwc2_gadget_get_desc_params - get DMA descriptor parameters. | |
739 | * @hs_ep: The endpoint | |
740 | * @mask: RX/TX bytes mask to be defined | |
741 | * | |
742 | * Returns maximum data payload for one descriptor after analyzing endpoint | |
743 | * characteristics. | |
744 | * DMA descriptor transfer bytes limit depends on EP type: | |
745 | * Control out - MPS, | |
746 | * Isochronous - descriptor rx/tx bytes bitfield limit, | |
747 | * Control In/Bulk/Interrupt - multiple of mps. This will allow to not | |
748 | * have concatenations from various descriptors within one packet. | |
b2c586eb MH |
749 | * Interrupt OUT - if mps not multiple of 4 then a single packet corresponds |
750 | * to a single descriptor. | |
e02f9aa6 VA |
751 | * |
752 | * Selects corresponding mask for RX/TX bytes as well. | |
753 | */ | |
754 | static u32 dwc2_gadget_get_desc_params(struct dwc2_hsotg_ep *hs_ep, u32 *mask) | |
755 | { | |
b2c586eb | 756 | const struct usb_endpoint_descriptor *ep_desc = hs_ep->ep.desc; |
e02f9aa6 VA |
757 | u32 mps = hs_ep->ep.maxpacket; |
758 | int dir_in = hs_ep->dir_in; | |
759 | u32 desc_size = 0; | |
760 | ||
761 | if (!hs_ep->index && !dir_in) { | |
762 | desc_size = mps; | |
763 | *mask = DEV_DMA_NBYTES_MASK; | |
764 | } else if (hs_ep->isochronous) { | |
765 | if (dir_in) { | |
766 | desc_size = DEV_DMA_ISOC_TX_NBYTES_LIMIT; | |
767 | *mask = DEV_DMA_ISOC_TX_NBYTES_MASK; | |
768 | } else { | |
769 | desc_size = DEV_DMA_ISOC_RX_NBYTES_LIMIT; | |
770 | *mask = DEV_DMA_ISOC_RX_NBYTES_MASK; | |
771 | } | |
772 | } else { | |
773 | desc_size = DEV_DMA_NBYTES_LIMIT; | |
774 | *mask = DEV_DMA_NBYTES_MASK; | |
775 | ||
776 | /* Round down desc_size to be mps multiple */ | |
777 | desc_size -= desc_size % mps; | |
778 | } | |
779 | ||
b2c586eb MH |
780 | /* Interrupt OUT EP with mps not multiple of 4 */ |
781 | if (hs_ep->index) | |
782 | if (usb_endpoint_xfer_int(ep_desc) && !dir_in && (mps % 4)) { | |
783 | desc_size = mps; | |
784 | *mask = DEV_DMA_NBYTES_MASK; | |
785 | } | |
786 | ||
e02f9aa6 VA |
787 | return desc_size; |
788 | } | |
789 | ||
10209abe AP |
790 | static void dwc2_gadget_fill_nonisoc_xfer_ddma_one(struct dwc2_hsotg_ep *hs_ep, |
791 | struct dwc2_dma_desc **desc, | |
e02f9aa6 | 792 | dma_addr_t dma_buff, |
10209abe AP |
793 | unsigned int len, |
794 | bool true_last) | |
e02f9aa6 | 795 | { |
e02f9aa6 | 796 | int dir_in = hs_ep->dir_in; |
e02f9aa6 VA |
797 | u32 mps = hs_ep->ep.maxpacket; |
798 | u32 maxsize = 0; | |
799 | u32 offset = 0; | |
800 | u32 mask = 0; | |
801 | int i; | |
802 | ||
803 | maxsize = dwc2_gadget_get_desc_params(hs_ep, &mask); | |
804 | ||
805 | hs_ep->desc_count = (len / maxsize) + | |
806 | ((len % maxsize) ? 1 : 0); | |
807 | if (len == 0) | |
808 | hs_ep->desc_count = 1; | |
809 | ||
810 | for (i = 0; i < hs_ep->desc_count; ++i) { | |
10209abe AP |
811 | (*desc)->status = 0; |
812 | (*desc)->status |= (DEV_DMA_BUFF_STS_HBUSY | |
e02f9aa6 VA |
813 | << DEV_DMA_BUFF_STS_SHIFT); |
814 | ||
815 | if (len > maxsize) { | |
816 | if (!hs_ep->index && !dir_in) | |
10209abe | 817 | (*desc)->status |= (DEV_DMA_L | DEV_DMA_IOC); |
e02f9aa6 | 818 | |
10209abe AP |
819 | (*desc)->status |= |
820 | maxsize << DEV_DMA_NBYTES_SHIFT & mask; | |
821 | (*desc)->buf = dma_buff + offset; | |
e02f9aa6 VA |
822 | |
823 | len -= maxsize; | |
824 | offset += maxsize; | |
825 | } else { | |
10209abe AP |
826 | if (true_last) |
827 | (*desc)->status |= (DEV_DMA_L | DEV_DMA_IOC); | |
e02f9aa6 VA |
828 | |
829 | if (dir_in) | |
10209abe AP |
830 | (*desc)->status |= (len % mps) ? DEV_DMA_SHORT : |
831 | ((hs_ep->send_zlp && true_last) ? | |
832 | DEV_DMA_SHORT : 0); | |
e02f9aa6 | 833 | |
10209abe | 834 | (*desc)->status |= |
e02f9aa6 | 835 | len << DEV_DMA_NBYTES_SHIFT & mask; |
10209abe | 836 | (*desc)->buf = dma_buff + offset; |
e02f9aa6 VA |
837 | } |
838 | ||
10209abe AP |
839 | (*desc)->status &= ~DEV_DMA_BUFF_STS_MASK; |
840 | (*desc)->status |= (DEV_DMA_BUFF_STS_HREADY | |
e02f9aa6 | 841 | << DEV_DMA_BUFF_STS_SHIFT); |
10209abe AP |
842 | (*desc)++; |
843 | } | |
844 | } | |
845 | ||
846 | /* | |
847 | * dwc2_gadget_config_nonisoc_xfer_ddma - prepare non ISOC DMA desc chain. | |
848 | * @hs_ep: The endpoint | |
849 | * @ureq: Request to transfer | |
850 | * @offset: offset in bytes | |
851 | * @len: Length of the transfer | |
852 | * | |
853 | * This function will iterate over descriptor chain and fill its entries | |
854 | * with corresponding information based on transfer data. | |
855 | */ | |
856 | static void dwc2_gadget_config_nonisoc_xfer_ddma(struct dwc2_hsotg_ep *hs_ep, | |
066cfd07 | 857 | dma_addr_t dma_buff, |
10209abe AP |
858 | unsigned int len) |
859 | { | |
066cfd07 | 860 | struct usb_request *ureq = NULL; |
10209abe AP |
861 | struct dwc2_dma_desc *desc = hs_ep->desc_list; |
862 | struct scatterlist *sg; | |
863 | int i; | |
864 | u8 desc_count = 0; | |
865 | ||
066cfd07 AP |
866 | if (hs_ep->req) |
867 | ureq = &hs_ep->req->req; | |
868 | ||
10209abe | 869 | /* non-DMA sg buffer */ |
066cfd07 | 870 | if (!ureq || !ureq->num_sgs) { |
10209abe | 871 | dwc2_gadget_fill_nonisoc_xfer_ddma_one(hs_ep, &desc, |
066cfd07 | 872 | dma_buff, len, true); |
10209abe | 873 | return; |
e02f9aa6 | 874 | } |
10209abe AP |
875 | |
876 | /* DMA sg buffer */ | |
877 | for_each_sg(ureq->sg, sg, ureq->num_sgs, i) { | |
878 | dwc2_gadget_fill_nonisoc_xfer_ddma_one(hs_ep, &desc, | |
879 | sg_dma_address(sg) + sg->offset, sg_dma_len(sg), | |
880 | sg_is_last(sg)); | |
881 | desc_count += hs_ep->desc_count; | |
882 | } | |
883 | ||
884 | hs_ep->desc_count = desc_count; | |
e02f9aa6 VA |
885 | } |
886 | ||
540ccba0 VA |
887 | /* |
888 | * dwc2_gadget_fill_isoc_desc - fills next isochronous descriptor in chain. | |
889 | * @hs_ep: The isochronous endpoint. | |
890 | * @dma_buff: usb requests dma buffer. | |
891 | * @len: usb request transfer length. | |
892 | * | |
729cac69 | 893 | * Fills next free descriptor with the data of the arrived usb request, |
540ccba0 VA |
894 | * frame info, sets Last and IOC bits increments next_desc. If filled |
895 | * descriptor is not the first one, removes L bit from the previous descriptor | |
896 | * status. | |
897 | */ | |
898 | static int dwc2_gadget_fill_isoc_desc(struct dwc2_hsotg_ep *hs_ep, | |
899 | dma_addr_t dma_buff, unsigned int len) | |
900 | { | |
901 | struct dwc2_dma_desc *desc; | |
902 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
903 | u32 index; | |
540ccba0 | 904 | u32 mask = 0; |
1d8e5c00 | 905 | u8 pid = 0; |
540ccba0 | 906 | |
768a0741 | 907 | dwc2_gadget_get_desc_params(hs_ep, &mask); |
540ccba0 | 908 | |
729cac69 MH |
909 | index = hs_ep->next_desc; |
910 | desc = &hs_ep->desc_list[index]; | |
540ccba0 | 911 | |
729cac69 MH |
912 | /* Check if descriptor chain full */ |
913 | if ((desc->status >> DEV_DMA_BUFF_STS_SHIFT) == | |
914 | DEV_DMA_BUFF_STS_HREADY) { | |
915 | dev_dbg(hsotg->dev, "%s: desc chain full\n", __func__); | |
916 | return 1; | |
540ccba0 VA |
917 | } |
918 | ||
540ccba0 VA |
919 | /* Clear L bit of previous desc if more than one entries in the chain */ |
920 | if (hs_ep->next_desc) | |
921 | hs_ep->desc_list[index - 1].status &= ~DEV_DMA_L; | |
922 | ||
923 | dev_dbg(hsotg->dev, "%s: Filling ep %d, dir %s isoc desc # %d\n", | |
924 | __func__, hs_ep->index, hs_ep->dir_in ? "in" : "out", index); | |
925 | ||
926 | desc->status = 0; | |
927 | desc->status |= (DEV_DMA_BUFF_STS_HBUSY << DEV_DMA_BUFF_STS_SHIFT); | |
928 | ||
929 | desc->buf = dma_buff; | |
930 | desc->status |= (DEV_DMA_L | DEV_DMA_IOC | | |
931 | ((len << DEV_DMA_NBYTES_SHIFT) & mask)); | |
932 | ||
933 | if (hs_ep->dir_in) { | |
1d8e5c00 MH |
934 | if (len) |
935 | pid = DIV_ROUND_UP(len, hs_ep->ep.maxpacket); | |
936 | else | |
937 | pid = 1; | |
938 | desc->status |= ((pid << DEV_DMA_ISOC_PID_SHIFT) & | |
540ccba0 VA |
939 | DEV_DMA_ISOC_PID_MASK) | |
940 | ((len % hs_ep->ep.maxpacket) ? | |
941 | DEV_DMA_SHORT : 0) | | |
942 | ((hs_ep->target_frame << | |
943 | DEV_DMA_ISOC_FRNUM_SHIFT) & | |
944 | DEV_DMA_ISOC_FRNUM_MASK); | |
945 | } | |
946 | ||
947 | desc->status &= ~DEV_DMA_BUFF_STS_MASK; | |
948 | desc->status |= (DEV_DMA_BUFF_STS_HREADY << DEV_DMA_BUFF_STS_SHIFT); | |
949 | ||
729cac69 MH |
950 | /* Increment frame number by interval for IN */ |
951 | if (hs_ep->dir_in) | |
952 | dwc2_gadget_incr_frame_num(hs_ep); | |
953 | ||
540ccba0 VA |
954 | /* Update index of last configured entry in the chain */ |
955 | hs_ep->next_desc++; | |
54f37f56 | 956 | if (hs_ep->next_desc >= MAX_DMA_DESC_NUM_HS_ISOC) |
729cac69 | 957 | hs_ep->next_desc = 0; |
540ccba0 VA |
958 | |
959 | return 0; | |
960 | } | |
961 | ||
962 | /* | |
963 | * dwc2_gadget_start_isoc_ddma - start isochronous transfer in DDMA | |
964 | * @hs_ep: The isochronous endpoint. | |
965 | * | |
729cac69 | 966 | * Prepare descriptor chain for isochronous endpoints. Afterwards |
540ccba0 | 967 | * write DMA address to HW and enable the endpoint. |
540ccba0 VA |
968 | */ |
969 | static void dwc2_gadget_start_isoc_ddma(struct dwc2_hsotg_ep *hs_ep) | |
970 | { | |
971 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
972 | struct dwc2_hsotg_req *hs_req, *treq; | |
973 | int index = hs_ep->index; | |
974 | int ret; | |
729cac69 | 975 | int i; |
540ccba0 VA |
976 | u32 dma_reg; |
977 | u32 depctl; | |
978 | u32 ctrl; | |
729cac69 | 979 | struct dwc2_dma_desc *desc; |
540ccba0 VA |
980 | |
981 | if (list_empty(&hs_ep->queue)) { | |
1ffba905 | 982 | hs_ep->target_frame = TARGET_FRAME_INITIAL; |
540ccba0 VA |
983 | dev_dbg(hsotg->dev, "%s: No requests in queue\n", __func__); |
984 | return; | |
985 | } | |
986 | ||
729cac69 | 987 | /* Initialize descriptor chain by Host Busy status */ |
54f37f56 | 988 | for (i = 0; i < MAX_DMA_DESC_NUM_HS_ISOC; i++) { |
729cac69 MH |
989 | desc = &hs_ep->desc_list[i]; |
990 | desc->status = 0; | |
991 | desc->status |= (DEV_DMA_BUFF_STS_HBUSY | |
992 | << DEV_DMA_BUFF_STS_SHIFT); | |
993 | } | |
994 | ||
995 | hs_ep->next_desc = 0; | |
540ccba0 | 996 | list_for_each_entry_safe(hs_req, treq, &hs_ep->queue, queue) { |
10209abe AP |
997 | dma_addr_t dma_addr = hs_req->req.dma; |
998 | ||
999 | if (hs_req->req.num_sgs) { | |
1000 | WARN_ON(hs_req->req.num_sgs > 1); | |
1001 | dma_addr = sg_dma_address(hs_req->req.sg); | |
1002 | } | |
1003 | ret = dwc2_gadget_fill_isoc_desc(hs_ep, dma_addr, | |
540ccba0 | 1004 | hs_req->req.length); |
729cac69 | 1005 | if (ret) |
540ccba0 | 1006 | break; |
540ccba0 VA |
1007 | } |
1008 | ||
729cac69 | 1009 | hs_ep->compl_desc = 0; |
540ccba0 VA |
1010 | depctl = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index); |
1011 | dma_reg = hs_ep->dir_in ? DIEPDMA(index) : DOEPDMA(index); | |
1012 | ||
1013 | /* write descriptor chain address to control register */ | |
f25c42b8 | 1014 | dwc2_writel(hsotg, hs_ep->desc_list_dma, dma_reg); |
540ccba0 | 1015 | |
f25c42b8 | 1016 | ctrl = dwc2_readl(hsotg, depctl); |
540ccba0 | 1017 | ctrl |= DXEPCTL_EPENA | DXEPCTL_CNAK; |
f25c42b8 | 1018 | dwc2_writel(hsotg, ctrl, depctl); |
540ccba0 VA |
1019 | } |
1020 | ||
5b7d70c6 | 1021 | /** |
1f91b4cc | 1022 | * dwc2_hsotg_start_req - start a USB request from an endpoint's queue |
5b7d70c6 BD |
1023 | * @hsotg: The controller state. |
1024 | * @hs_ep: The endpoint to process a request for | |
1025 | * @hs_req: The request to start. | |
1026 | * @continuing: True if we are doing more for the current request. | |
1027 | * | |
1028 | * Start the given request running by setting the endpoint registers | |
1029 | * appropriately, and writing any data to the FIFOs. | |
1030 | */ | |
1f91b4cc | 1031 | static void dwc2_hsotg_start_req(struct dwc2_hsotg *hsotg, |
9da51974 | 1032 | struct dwc2_hsotg_ep *hs_ep, |
1f91b4cc | 1033 | struct dwc2_hsotg_req *hs_req, |
5b7d70c6 BD |
1034 | bool continuing) |
1035 | { | |
1036 | struct usb_request *ureq = &hs_req->req; | |
1037 | int index = hs_ep->index; | |
1038 | int dir_in = hs_ep->dir_in; | |
1039 | u32 epctrl_reg; | |
1040 | u32 epsize_reg; | |
1041 | u32 epsize; | |
1042 | u32 ctrl; | |
9da51974 JY |
1043 | unsigned int length; |
1044 | unsigned int packets; | |
1045 | unsigned int maxreq; | |
aa3e8bc8 | 1046 | unsigned int dma_reg; |
5b7d70c6 BD |
1047 | |
1048 | if (index != 0) { | |
1049 | if (hs_ep->req && !continuing) { | |
1050 | dev_err(hsotg->dev, "%s: active request\n", __func__); | |
1051 | WARN_ON(1); | |
1052 | return; | |
1053 | } else if (hs_ep->req != hs_req && continuing) { | |
1054 | dev_err(hsotg->dev, | |
1055 | "%s: continue different req\n", __func__); | |
1056 | WARN_ON(1); | |
1057 | return; | |
1058 | } | |
1059 | } | |
1060 | ||
aa3e8bc8 | 1061 | dma_reg = dir_in ? DIEPDMA(index) : DOEPDMA(index); |
94cb8fd6 LM |
1062 | epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index); |
1063 | epsize_reg = dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index); | |
5b7d70c6 BD |
1064 | |
1065 | dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n", | |
f25c42b8 | 1066 | __func__, dwc2_readl(hsotg, epctrl_reg), index, |
5b7d70c6 BD |
1067 | hs_ep->dir_in ? "in" : "out"); |
1068 | ||
9c39ddc6 | 1069 | /* If endpoint is stalled, we will restart request later */ |
f25c42b8 | 1070 | ctrl = dwc2_readl(hsotg, epctrl_reg); |
9c39ddc6 | 1071 | |
b2d4c54e | 1072 | if (index && ctrl & DXEPCTL_STALL) { |
9c39ddc6 AT |
1073 | dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index); |
1074 | return; | |
1075 | } | |
1076 | ||
5b7d70c6 | 1077 | length = ureq->length - ureq->actual; |
71225bee LM |
1078 | dev_dbg(hsotg->dev, "ureq->length:%d ureq->actual:%d\n", |
1079 | ureq->length, ureq->actual); | |
5b7d70c6 | 1080 | |
cf77b5fb VA |
1081 | if (!using_desc_dma(hsotg)) |
1082 | maxreq = get_ep_limit(hs_ep); | |
1083 | else | |
1084 | maxreq = dwc2_gadget_get_chain_limit(hs_ep); | |
1085 | ||
5b7d70c6 BD |
1086 | if (length > maxreq) { |
1087 | int round = maxreq % hs_ep->ep.maxpacket; | |
1088 | ||
1089 | dev_dbg(hsotg->dev, "%s: length %d, max-req %d, r %d\n", | |
1090 | __func__, length, maxreq, round); | |
1091 | ||
1092 | /* round down to multiple of packets */ | |
1093 | if (round) | |
1094 | maxreq -= round; | |
1095 | ||
1096 | length = maxreq; | |
1097 | } | |
1098 | ||
1099 | if (length) | |
1100 | packets = DIV_ROUND_UP(length, hs_ep->ep.maxpacket); | |
1101 | else | |
1102 | packets = 1; /* send one packet if length is zero. */ | |
1103 | ||
1104 | if (dir_in && index != 0) | |
4fca54aa | 1105 | if (hs_ep->isochronous) |
47a1685f | 1106 | epsize = DXEPTSIZ_MC(packets); |
4fca54aa | 1107 | else |
47a1685f | 1108 | epsize = DXEPTSIZ_MC(1); |
5b7d70c6 BD |
1109 | else |
1110 | epsize = 0; | |
1111 | ||
f71b5e25 MYK |
1112 | /* |
1113 | * zero length packet should be programmed on its own and should not | |
1114 | * be counted in DIEPTSIZ.PktCnt with other packets. | |
1115 | */ | |
1116 | if (dir_in && ureq->zero && !continuing) { | |
1117 | /* Test if zlp is actually required. */ | |
1118 | if ((ureq->length >= hs_ep->ep.maxpacket) && | |
9da51974 | 1119 | !(ureq->length % hs_ep->ep.maxpacket)) |
8a20fa45 | 1120 | hs_ep->send_zlp = 1; |
5b7d70c6 BD |
1121 | } |
1122 | ||
47a1685f DN |
1123 | epsize |= DXEPTSIZ_PKTCNT(packets); |
1124 | epsize |= DXEPTSIZ_XFERSIZE(length); | |
5b7d70c6 BD |
1125 | |
1126 | dev_dbg(hsotg->dev, "%s: %d@%d/%d, 0x%08x => 0x%08x\n", | |
1127 | __func__, packets, length, ureq->length, epsize, epsize_reg); | |
1128 | ||
1129 | /* store the request as the current one we're doing */ | |
1130 | hs_ep->req = hs_req; | |
1131 | ||
aa3e8bc8 VA |
1132 | if (using_desc_dma(hsotg)) { |
1133 | u32 offset = 0; | |
1134 | u32 mps = hs_ep->ep.maxpacket; | |
1135 | ||
1136 | /* Adjust length: EP0 - MPS, other OUT EPs - multiple of MPS */ | |
1137 | if (!dir_in) { | |
1138 | if (!index) | |
1139 | length = mps; | |
1140 | else if (length % mps) | |
1141 | length += (mps - (length % mps)); | |
1142 | } | |
5b7d70c6 | 1143 | |
b2c586eb | 1144 | if (continuing) |
aa3e8bc8 VA |
1145 | offset = ureq->actual; |
1146 | ||
1147 | /* Fill DDMA chain entries */ | |
066cfd07 | 1148 | dwc2_gadget_config_nonisoc_xfer_ddma(hs_ep, ureq->dma + offset, |
aa3e8bc8 VA |
1149 | length); |
1150 | ||
1151 | /* write descriptor chain address to control register */ | |
f25c42b8 | 1152 | dwc2_writel(hsotg, hs_ep->desc_list_dma, dma_reg); |
5b7d70c6 | 1153 | |
aa3e8bc8 VA |
1154 | dev_dbg(hsotg->dev, "%s: %08x pad => 0x%08x\n", |
1155 | __func__, (u32)hs_ep->desc_list_dma, dma_reg); | |
1156 | } else { | |
1157 | /* write size / packets */ | |
f25c42b8 | 1158 | dwc2_writel(hsotg, epsize, epsize_reg); |
aa3e8bc8 | 1159 | |
729e6574 | 1160 | if (using_dma(hsotg) && !continuing && (length != 0)) { |
aa3e8bc8 VA |
1161 | /* |
1162 | * write DMA address to control register, buffer | |
1163 | * already synced by dwc2_hsotg_ep_queue(). | |
1164 | */ | |
5b7d70c6 | 1165 | |
f25c42b8 | 1166 | dwc2_writel(hsotg, ureq->dma, dma_reg); |
aa3e8bc8 VA |
1167 | |
1168 | dev_dbg(hsotg->dev, "%s: %pad => 0x%08x\n", | |
1169 | __func__, &ureq->dma, dma_reg); | |
1170 | } | |
5b7d70c6 BD |
1171 | } |
1172 | ||
837e9f00 VM |
1173 | if (hs_ep->isochronous && hs_ep->interval == 1) { |
1174 | hs_ep->target_frame = dwc2_hsotg_read_frameno(hsotg); | |
1175 | dwc2_gadget_incr_frame_num(hs_ep); | |
1176 | ||
1177 | if (hs_ep->target_frame & 0x1) | |
1178 | ctrl |= DXEPCTL_SETODDFR; | |
1179 | else | |
1180 | ctrl |= DXEPCTL_SETEVENFR; | |
1181 | } | |
1182 | ||
47a1685f | 1183 | ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */ |
71225bee | 1184 | |
fe0b94ab | 1185 | dev_dbg(hsotg->dev, "ep0 state:%d\n", hsotg->ep0_state); |
71225bee LM |
1186 | |
1187 | /* For Setup request do not clear NAK */ | |
fe0b94ab | 1188 | if (!(index == 0 && hsotg->ep0_state == DWC2_EP0_SETUP)) |
47a1685f | 1189 | ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */ |
71225bee | 1190 | |
5b7d70c6 | 1191 | dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl); |
f25c42b8 | 1192 | dwc2_writel(hsotg, ctrl, epctrl_reg); |
5b7d70c6 | 1193 | |
8b9bc460 LM |
1194 | /* |
1195 | * set these, it seems that DMA support increments past the end | |
5b7d70c6 | 1196 | * of the packet buffer so we need to calculate the length from |
8b9bc460 LM |
1197 | * this information. |
1198 | */ | |
5b7d70c6 BD |
1199 | hs_ep->size_loaded = length; |
1200 | hs_ep->last_load = ureq->actual; | |
1201 | ||
1202 | if (dir_in && !using_dma(hsotg)) { | |
1203 | /* set these anyway, we may need them for non-periodic in */ | |
1204 | hs_ep->fifo_load = 0; | |
1205 | ||
1f91b4cc | 1206 | dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req); |
5b7d70c6 BD |
1207 | } |
1208 | ||
8b9bc460 LM |
1209 | /* |
1210 | * Note, trying to clear the NAK here causes problems with transmit | |
1211 | * on the S3C6400 ending up with the TXFIFO becoming full. | |
1212 | */ | |
5b7d70c6 BD |
1213 | |
1214 | /* check ep is enabled */ | |
f25c42b8 | 1215 | if (!(dwc2_readl(hsotg, epctrl_reg) & DXEPCTL_EPENA)) |
1a0ed863 | 1216 | dev_dbg(hsotg->dev, |
9da51974 | 1217 | "ep%d: failed to become enabled (DXEPCTL=0x%08x)?\n", |
f25c42b8 | 1218 | index, dwc2_readl(hsotg, epctrl_reg)); |
5b7d70c6 | 1219 | |
47a1685f | 1220 | dev_dbg(hsotg->dev, "%s: DXEPCTL=0x%08x\n", |
f25c42b8 | 1221 | __func__, dwc2_readl(hsotg, epctrl_reg)); |
afcf4169 RB |
1222 | |
1223 | /* enable ep interrupts */ | |
1f91b4cc | 1224 | dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 1); |
5b7d70c6 BD |
1225 | } |
1226 | ||
1227 | /** | |
1f91b4cc | 1228 | * dwc2_hsotg_map_dma - map the DMA memory being used for the request |
5b7d70c6 BD |
1229 | * @hsotg: The device state. |
1230 | * @hs_ep: The endpoint the request is on. | |
1231 | * @req: The request being processed. | |
1232 | * | |
1233 | * We've been asked to queue a request, so ensure that the memory buffer | |
1234 | * is correctly setup for DMA. If we've been passed an extant DMA address | |
1235 | * then ensure the buffer has been synced to memory. If our buffer has no | |
1236 | * DMA memory, then we map the memory and mark our request to allow us to | |
1237 | * cleanup on completion. | |
8b9bc460 | 1238 | */ |
1f91b4cc | 1239 | static int dwc2_hsotg_map_dma(struct dwc2_hsotg *hsotg, |
9da51974 | 1240 | struct dwc2_hsotg_ep *hs_ep, |
5b7d70c6 BD |
1241 | struct usb_request *req) |
1242 | { | |
e58ebcd1 | 1243 | int ret; |
5b7d70c6 | 1244 | |
e58ebcd1 FB |
1245 | ret = usb_gadget_map_request(&hsotg->gadget, req, hs_ep->dir_in); |
1246 | if (ret) | |
1247 | goto dma_error; | |
5b7d70c6 BD |
1248 | |
1249 | return 0; | |
1250 | ||
1251 | dma_error: | |
1252 | dev_err(hsotg->dev, "%s: failed to map buffer %p, %d bytes\n", | |
1253 | __func__, req->buf, req->length); | |
1254 | ||
1255 | return -EIO; | |
1256 | } | |
1257 | ||
1f91b4cc | 1258 | static int dwc2_hsotg_handle_unaligned_buf_start(struct dwc2_hsotg *hsotg, |
b98866c2 JY |
1259 | struct dwc2_hsotg_ep *hs_ep, |
1260 | struct dwc2_hsotg_req *hs_req) | |
7d24c1b5 MYK |
1261 | { |
1262 | void *req_buf = hs_req->req.buf; | |
1263 | ||
1264 | /* If dma is not being used or buffer is aligned */ | |
1265 | if (!using_dma(hsotg) || !((long)req_buf & 3)) | |
1266 | return 0; | |
1267 | ||
1268 | WARN_ON(hs_req->saved_req_buf); | |
1269 | ||
1270 | dev_dbg(hsotg->dev, "%s: %s: buf=%p length=%d\n", __func__, | |
9da51974 | 1271 | hs_ep->ep.name, req_buf, hs_req->req.length); |
7d24c1b5 MYK |
1272 | |
1273 | hs_req->req.buf = kmalloc(hs_req->req.length, GFP_ATOMIC); | |
1274 | if (!hs_req->req.buf) { | |
1275 | hs_req->req.buf = req_buf; | |
1276 | dev_err(hsotg->dev, | |
1277 | "%s: unable to allocate memory for bounce buffer\n", | |
1278 | __func__); | |
1279 | return -ENOMEM; | |
1280 | } | |
1281 | ||
1282 | /* Save actual buffer */ | |
1283 | hs_req->saved_req_buf = req_buf; | |
1284 | ||
1285 | if (hs_ep->dir_in) | |
1286 | memcpy(hs_req->req.buf, req_buf, hs_req->req.length); | |
1287 | return 0; | |
1288 | } | |
1289 | ||
b98866c2 JY |
1290 | static void |
1291 | dwc2_hsotg_handle_unaligned_buf_complete(struct dwc2_hsotg *hsotg, | |
1292 | struct dwc2_hsotg_ep *hs_ep, | |
1293 | struct dwc2_hsotg_req *hs_req) | |
7d24c1b5 MYK |
1294 | { |
1295 | /* If dma is not being used or buffer was aligned */ | |
1296 | if (!using_dma(hsotg) || !hs_req->saved_req_buf) | |
1297 | return; | |
1298 | ||
1299 | dev_dbg(hsotg->dev, "%s: %s: status=%d actual-length=%d\n", __func__, | |
1300 | hs_ep->ep.name, hs_req->req.status, hs_req->req.actual); | |
1301 | ||
1302 | /* Copy data from bounce buffer on successful out transfer */ | |
1303 | if (!hs_ep->dir_in && !hs_req->req.status) | |
1304 | memcpy(hs_req->saved_req_buf, hs_req->req.buf, | |
9da51974 | 1305 | hs_req->req.actual); |
7d24c1b5 MYK |
1306 | |
1307 | /* Free bounce buffer */ | |
1308 | kfree(hs_req->req.buf); | |
1309 | ||
1310 | hs_req->req.buf = hs_req->saved_req_buf; | |
1311 | hs_req->saved_req_buf = NULL; | |
1312 | } | |
1313 | ||
381fc8f8 VM |
1314 | /** |
1315 | * dwc2_gadget_target_frame_elapsed - Checks target frame | |
1316 | * @hs_ep: The driver endpoint to check | |
1317 | * | |
1318 | * Returns 1 if targeted frame elapsed. If returned 1 then we need to drop | |
1319 | * corresponding transfer. | |
1320 | */ | |
1321 | static bool dwc2_gadget_target_frame_elapsed(struct dwc2_hsotg_ep *hs_ep) | |
1322 | { | |
1323 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
1324 | u32 target_frame = hs_ep->target_frame; | |
c7c24e7a | 1325 | u32 current_frame = hsotg->frame_number; |
381fc8f8 VM |
1326 | bool frame_overrun = hs_ep->frame_overrun; |
1327 | ||
1328 | if (!frame_overrun && current_frame >= target_frame) | |
1329 | return true; | |
1330 | ||
1331 | if (frame_overrun && current_frame >= target_frame && | |
1332 | ((current_frame - target_frame) < DSTS_SOFFN_LIMIT / 2)) | |
1333 | return true; | |
1334 | ||
1335 | return false; | |
1336 | } | |
1337 | ||
e02f9aa6 VA |
1338 | /* |
1339 | * dwc2_gadget_set_ep0_desc_chain - Set EP's desc chain pointers | |
1340 | * @hsotg: The driver state | |
1341 | * @hs_ep: the ep descriptor chain is for | |
1342 | * | |
1343 | * Called to update EP0 structure's pointers depend on stage of | |
1344 | * control transfer. | |
1345 | */ | |
1346 | static int dwc2_gadget_set_ep0_desc_chain(struct dwc2_hsotg *hsotg, | |
1347 | struct dwc2_hsotg_ep *hs_ep) | |
1348 | { | |
1349 | switch (hsotg->ep0_state) { | |
1350 | case DWC2_EP0_SETUP: | |
1351 | case DWC2_EP0_STATUS_OUT: | |
1352 | hs_ep->desc_list = hsotg->setup_desc[0]; | |
1353 | hs_ep->desc_list_dma = hsotg->setup_desc_dma[0]; | |
1354 | break; | |
1355 | case DWC2_EP0_DATA_IN: | |
1356 | case DWC2_EP0_STATUS_IN: | |
1357 | hs_ep->desc_list = hsotg->ctrl_in_desc; | |
1358 | hs_ep->desc_list_dma = hsotg->ctrl_in_desc_dma; | |
1359 | break; | |
1360 | case DWC2_EP0_DATA_OUT: | |
1361 | hs_ep->desc_list = hsotg->ctrl_out_desc; | |
1362 | hs_ep->desc_list_dma = hsotg->ctrl_out_desc_dma; | |
1363 | break; | |
1364 | default: | |
1365 | dev_err(hsotg->dev, "invalid EP 0 state in queue %d\n", | |
1366 | hsotg->ep0_state); | |
1367 | return -EINVAL; | |
1368 | } | |
1369 | ||
1370 | return 0; | |
1371 | } | |
1372 | ||
1f91b4cc | 1373 | static int dwc2_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req, |
9da51974 | 1374 | gfp_t gfp_flags) |
5b7d70c6 | 1375 | { |
1f91b4cc FB |
1376 | struct dwc2_hsotg_req *hs_req = our_req(req); |
1377 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); | |
941fcce4 | 1378 | struct dwc2_hsotg *hs = hs_ep->parent; |
5b7d70c6 | 1379 | bool first; |
7d24c1b5 | 1380 | int ret; |
729cac69 MH |
1381 | u32 maxsize = 0; |
1382 | u32 mask = 0; | |
1383 | ||
5b7d70c6 BD |
1384 | |
1385 | dev_dbg(hs->dev, "%s: req %p: %d@%p, noi=%d, zero=%d, snok=%d\n", | |
1386 | ep->name, req, req->length, req->buf, req->no_interrupt, | |
1387 | req->zero, req->short_not_ok); | |
1388 | ||
7ababa92 | 1389 | /* Prevent new request submission when controller is suspended */ |
88b02f2c GT |
1390 | if (hs->lx_state != DWC2_L0) { |
1391 | dev_dbg(hs->dev, "%s: submit request only in active state\n", | |
9da51974 | 1392 | __func__); |
7ababa92 GH |
1393 | return -EAGAIN; |
1394 | } | |
1395 | ||
5b7d70c6 BD |
1396 | /* initialise status of the request */ |
1397 | INIT_LIST_HEAD(&hs_req->queue); | |
1398 | req->actual = 0; | |
1399 | req->status = -EINPROGRESS; | |
1400 | ||
860ef6cd MH |
1401 | /* Don't queue ISOC request if length greater than mps*mc */ |
1402 | if (hs_ep->isochronous && | |
1403 | req->length > (hs_ep->mc * hs_ep->ep.maxpacket)) { | |
1404 | dev_err(hs->dev, "req length > maxpacket*mc\n"); | |
1405 | return -EINVAL; | |
1406 | } | |
1407 | ||
729cac69 MH |
1408 | /* In DDMA mode for ISOC's don't queue request if length greater |
1409 | * than descriptor limits. | |
1410 | */ | |
1411 | if (using_desc_dma(hs) && hs_ep->isochronous) { | |
1412 | maxsize = dwc2_gadget_get_desc_params(hs_ep, &mask); | |
1413 | if (hs_ep->dir_in && req->length > maxsize) { | |
1414 | dev_err(hs->dev, "wrong length %d (maxsize=%d)\n", | |
1415 | req->length, maxsize); | |
1416 | return -EINVAL; | |
1417 | } | |
1418 | ||
1419 | if (!hs_ep->dir_in && req->length > hs_ep->ep.maxpacket) { | |
1420 | dev_err(hs->dev, "ISOC OUT: wrong length %d (mps=%d)\n", | |
1421 | req->length, hs_ep->ep.maxpacket); | |
1422 | return -EINVAL; | |
1423 | } | |
1424 | } | |
1425 | ||
1f91b4cc | 1426 | ret = dwc2_hsotg_handle_unaligned_buf_start(hs, hs_ep, hs_req); |
7d24c1b5 MYK |
1427 | if (ret) |
1428 | return ret; | |
1429 | ||
5b7d70c6 BD |
1430 | /* if we're using DMA, sync the buffers as necessary */ |
1431 | if (using_dma(hs)) { | |
1f91b4cc | 1432 | ret = dwc2_hsotg_map_dma(hs, hs_ep, req); |
5b7d70c6 BD |
1433 | if (ret) |
1434 | return ret; | |
1435 | } | |
e02f9aa6 VA |
1436 | /* If using descriptor DMA configure EP0 descriptor chain pointers */ |
1437 | if (using_desc_dma(hs) && !hs_ep->index) { | |
1438 | ret = dwc2_gadget_set_ep0_desc_chain(hs, hs_ep); | |
1439 | if (ret) | |
1440 | return ret; | |
1441 | } | |
5b7d70c6 | 1442 | |
5b7d70c6 BD |
1443 | first = list_empty(&hs_ep->queue); |
1444 | list_add_tail(&hs_req->queue, &hs_ep->queue); | |
1445 | ||
540ccba0 VA |
1446 | /* |
1447 | * Handle DDMA isochronous transfers separately - just add new entry | |
729cac69 | 1448 | * to the descriptor chain. |
540ccba0 VA |
1449 | * Transfer will be started once SW gets either one of NAK or |
1450 | * OutTknEpDis interrupts. | |
1451 | */ | |
729cac69 MH |
1452 | if (using_desc_dma(hs) && hs_ep->isochronous) { |
1453 | if (hs_ep->target_frame != TARGET_FRAME_INITIAL) { | |
10209abe AP |
1454 | dma_addr_t dma_addr = hs_req->req.dma; |
1455 | ||
1456 | if (hs_req->req.num_sgs) { | |
1457 | WARN_ON(hs_req->req.num_sgs > 1); | |
1458 | dma_addr = sg_dma_address(hs_req->req.sg); | |
1459 | } | |
1460 | dwc2_gadget_fill_isoc_desc(hs_ep, dma_addr, | |
729cac69 MH |
1461 | hs_req->req.length); |
1462 | } | |
540ccba0 VA |
1463 | return 0; |
1464 | } | |
1465 | ||
b4c53b4a MH |
1466 | /* Change EP direction if status phase request is after data out */ |
1467 | if (!hs_ep->index && !req->length && !hs_ep->dir_in && | |
1468 | hs->ep0_state == DWC2_EP0_DATA_OUT) | |
1469 | hs_ep->dir_in = 1; | |
1470 | ||
837e9f00 VM |
1471 | if (first) { |
1472 | if (!hs_ep->isochronous) { | |
1473 | dwc2_hsotg_start_req(hs, hs_ep, hs_req, false); | |
1474 | return 0; | |
1475 | } | |
1476 | ||
c7c24e7a AP |
1477 | /* Update current frame number value. */ |
1478 | hs->frame_number = dwc2_hsotg_read_frameno(hs); | |
1479 | while (dwc2_gadget_target_frame_elapsed(hs_ep)) { | |
837e9f00 | 1480 | dwc2_gadget_incr_frame_num(hs_ep); |
c7c24e7a AP |
1481 | /* Update current frame number value once more as it |
1482 | * changes here. | |
1483 | */ | |
1484 | hs->frame_number = dwc2_hsotg_read_frameno(hs); | |
1485 | } | |
5b7d70c6 | 1486 | |
837e9f00 VM |
1487 | if (hs_ep->target_frame != TARGET_FRAME_INITIAL) |
1488 | dwc2_hsotg_start_req(hs, hs_ep, hs_req, false); | |
1489 | } | |
5b7d70c6 BD |
1490 | return 0; |
1491 | } | |
1492 | ||
1f91b4cc | 1493 | static int dwc2_hsotg_ep_queue_lock(struct usb_ep *ep, struct usb_request *req, |
9da51974 | 1494 | gfp_t gfp_flags) |
5ad1d316 | 1495 | { |
1f91b4cc | 1496 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 1497 | struct dwc2_hsotg *hs = hs_ep->parent; |
5ad1d316 LM |
1498 | unsigned long flags = 0; |
1499 | int ret = 0; | |
1500 | ||
1501 | spin_lock_irqsave(&hs->lock, flags); | |
1f91b4cc | 1502 | ret = dwc2_hsotg_ep_queue(ep, req, gfp_flags); |
5ad1d316 LM |
1503 | spin_unlock_irqrestore(&hs->lock, flags); |
1504 | ||
1505 | return ret; | |
1506 | } | |
1507 | ||
1f91b4cc | 1508 | static void dwc2_hsotg_ep_free_request(struct usb_ep *ep, |
9da51974 | 1509 | struct usb_request *req) |
5b7d70c6 | 1510 | { |
1f91b4cc | 1511 | struct dwc2_hsotg_req *hs_req = our_req(req); |
5b7d70c6 BD |
1512 | |
1513 | kfree(hs_req); | |
1514 | } | |
1515 | ||
1516 | /** | |
1f91b4cc | 1517 | * dwc2_hsotg_complete_oursetup - setup completion callback |
5b7d70c6 BD |
1518 | * @ep: The endpoint the request was on. |
1519 | * @req: The request completed. | |
1520 | * | |
1521 | * Called on completion of any requests the driver itself | |
1522 | * submitted that need cleaning up. | |
1523 | */ | |
1f91b4cc | 1524 | static void dwc2_hsotg_complete_oursetup(struct usb_ep *ep, |
9da51974 | 1525 | struct usb_request *req) |
5b7d70c6 | 1526 | { |
1f91b4cc | 1527 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 1528 | struct dwc2_hsotg *hsotg = hs_ep->parent; |
5b7d70c6 BD |
1529 | |
1530 | dev_dbg(hsotg->dev, "%s: ep %p, req %p\n", __func__, ep, req); | |
1531 | ||
1f91b4cc | 1532 | dwc2_hsotg_ep_free_request(ep, req); |
5b7d70c6 BD |
1533 | } |
1534 | ||
1535 | /** | |
1536 | * ep_from_windex - convert control wIndex value to endpoint | |
1537 | * @hsotg: The driver state. | |
1538 | * @windex: The control request wIndex field (in host order). | |
1539 | * | |
1540 | * Convert the given wIndex into a pointer to an driver endpoint | |
1541 | * structure, or return NULL if it is not a valid endpoint. | |
8b9bc460 | 1542 | */ |
1f91b4cc | 1543 | static struct dwc2_hsotg_ep *ep_from_windex(struct dwc2_hsotg *hsotg, |
9da51974 | 1544 | u32 windex) |
5b7d70c6 | 1545 | { |
5b7d70c6 BD |
1546 | int dir = (windex & USB_DIR_IN) ? 1 : 0; |
1547 | int idx = windex & 0x7F; | |
1548 | ||
1549 | if (windex >= 0x100) | |
1550 | return NULL; | |
1551 | ||
b3f489b2 | 1552 | if (idx > hsotg->num_of_eps) |
5b7d70c6 BD |
1553 | return NULL; |
1554 | ||
f670e9f9 | 1555 | return index_to_ep(hsotg, idx, dir); |
5b7d70c6 BD |
1556 | } |
1557 | ||
9e14d0a5 | 1558 | /** |
1f91b4cc | 1559 | * dwc2_hsotg_set_test_mode - Enable usb Test Modes |
9e14d0a5 GH |
1560 | * @hsotg: The driver state. |
1561 | * @testmode: requested usb test mode | |
1562 | * Enable usb Test Mode requested by the Host. | |
1563 | */ | |
1f91b4cc | 1564 | int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode) |
9e14d0a5 | 1565 | { |
f25c42b8 | 1566 | int dctl = dwc2_readl(hsotg, DCTL); |
9e14d0a5 GH |
1567 | |
1568 | dctl &= ~DCTL_TSTCTL_MASK; | |
1569 | switch (testmode) { | |
62fb45d3 GKH |
1570 | case USB_TEST_J: |
1571 | case USB_TEST_K: | |
1572 | case USB_TEST_SE0_NAK: | |
1573 | case USB_TEST_PACKET: | |
1574 | case USB_TEST_FORCE_ENABLE: | |
9e14d0a5 GH |
1575 | dctl |= testmode << DCTL_TSTCTL_SHIFT; |
1576 | break; | |
1577 | default: | |
1578 | return -EINVAL; | |
1579 | } | |
f25c42b8 | 1580 | dwc2_writel(hsotg, dctl, DCTL); |
9e14d0a5 GH |
1581 | return 0; |
1582 | } | |
1583 | ||
5b7d70c6 | 1584 | /** |
1f91b4cc | 1585 | * dwc2_hsotg_send_reply - send reply to control request |
5b7d70c6 BD |
1586 | * @hsotg: The device state |
1587 | * @ep: Endpoint 0 | |
1588 | * @buff: Buffer for request | |
1589 | * @length: Length of reply. | |
1590 | * | |
1591 | * Create a request and queue it on the given endpoint. This is useful as | |
1592 | * an internal method of sending replies to certain control requests, etc. | |
1593 | */ | |
1f91b4cc | 1594 | static int dwc2_hsotg_send_reply(struct dwc2_hsotg *hsotg, |
9da51974 | 1595 | struct dwc2_hsotg_ep *ep, |
5b7d70c6 BD |
1596 | void *buff, |
1597 | int length) | |
1598 | { | |
1599 | struct usb_request *req; | |
1600 | int ret; | |
1601 | ||
1602 | dev_dbg(hsotg->dev, "%s: buff %p, len %d\n", __func__, buff, length); | |
1603 | ||
1f91b4cc | 1604 | req = dwc2_hsotg_ep_alloc_request(&ep->ep, GFP_ATOMIC); |
5b7d70c6 BD |
1605 | hsotg->ep0_reply = req; |
1606 | if (!req) { | |
1607 | dev_warn(hsotg->dev, "%s: cannot alloc req\n", __func__); | |
1608 | return -ENOMEM; | |
1609 | } | |
1610 | ||
1611 | req->buf = hsotg->ep0_buff; | |
1612 | req->length = length; | |
f71b5e25 MYK |
1613 | /* |
1614 | * zero flag is for sending zlp in DATA IN stage. It has no impact on | |
1615 | * STATUS stage. | |
1616 | */ | |
1617 | req->zero = 0; | |
1f91b4cc | 1618 | req->complete = dwc2_hsotg_complete_oursetup; |
5b7d70c6 BD |
1619 | |
1620 | if (length) | |
1621 | memcpy(req->buf, buff, length); | |
5b7d70c6 | 1622 | |
1f91b4cc | 1623 | ret = dwc2_hsotg_ep_queue(&ep->ep, req, GFP_ATOMIC); |
5b7d70c6 BD |
1624 | if (ret) { |
1625 | dev_warn(hsotg->dev, "%s: cannot queue req\n", __func__); | |
1626 | return ret; | |
1627 | } | |
1628 | ||
1629 | return 0; | |
1630 | } | |
1631 | ||
1632 | /** | |
1f91b4cc | 1633 | * dwc2_hsotg_process_req_status - process request GET_STATUS |
5b7d70c6 BD |
1634 | * @hsotg: The device state |
1635 | * @ctrl: USB control request | |
1636 | */ | |
1f91b4cc | 1637 | static int dwc2_hsotg_process_req_status(struct dwc2_hsotg *hsotg, |
9da51974 | 1638 | struct usb_ctrlrequest *ctrl) |
5b7d70c6 | 1639 | { |
1f91b4cc FB |
1640 | struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0]; |
1641 | struct dwc2_hsotg_ep *ep; | |
5b7d70c6 | 1642 | __le16 reply; |
9a0d6f7c | 1643 | u16 status; |
5b7d70c6 BD |
1644 | int ret; |
1645 | ||
1646 | dev_dbg(hsotg->dev, "%s: USB_REQ_GET_STATUS\n", __func__); | |
1647 | ||
1648 | if (!ep0->dir_in) { | |
1649 | dev_warn(hsotg->dev, "%s: direction out?\n", __func__); | |
1650 | return -EINVAL; | |
1651 | } | |
1652 | ||
1653 | switch (ctrl->bRequestType & USB_RECIP_MASK) { | |
1654 | case USB_RECIP_DEVICE: | |
1a0808cb JK |
1655 | status = hsotg->gadget.is_selfpowered << |
1656 | USB_DEVICE_SELF_POWERED; | |
9a0d6f7c MH |
1657 | status |= hsotg->remote_wakeup_allowed << |
1658 | USB_DEVICE_REMOTE_WAKEUP; | |
1659 | reply = cpu_to_le16(status); | |
5b7d70c6 BD |
1660 | break; |
1661 | ||
1662 | case USB_RECIP_INTERFACE: | |
1663 | /* currently, the data result should be zero */ | |
1664 | reply = cpu_to_le16(0); | |
1665 | break; | |
1666 | ||
1667 | case USB_RECIP_ENDPOINT: | |
1668 | ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex)); | |
1669 | if (!ep) | |
1670 | return -ENOENT; | |
1671 | ||
1672 | reply = cpu_to_le16(ep->halted ? 1 : 0); | |
1673 | break; | |
1674 | ||
1675 | default: | |
1676 | return 0; | |
1677 | } | |
1678 | ||
1679 | if (le16_to_cpu(ctrl->wLength) != 2) | |
1680 | return -EINVAL; | |
1681 | ||
1f91b4cc | 1682 | ret = dwc2_hsotg_send_reply(hsotg, ep0, &reply, 2); |
5b7d70c6 BD |
1683 | if (ret) { |
1684 | dev_err(hsotg->dev, "%s: failed to send reply\n", __func__); | |
1685 | return ret; | |
1686 | } | |
1687 | ||
1688 | return 1; | |
1689 | } | |
1690 | ||
51da43b5 | 1691 | static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now); |
5b7d70c6 | 1692 | |
9c39ddc6 AT |
1693 | /** |
1694 | * get_ep_head - return the first request on the endpoint | |
1695 | * @hs_ep: The controller endpoint to get | |
1696 | * | |
1697 | * Get the first request on the endpoint. | |
1698 | */ | |
1f91b4cc | 1699 | static struct dwc2_hsotg_req *get_ep_head(struct dwc2_hsotg_ep *hs_ep) |
9c39ddc6 | 1700 | { |
ffc4b406 MY |
1701 | return list_first_entry_or_null(&hs_ep->queue, struct dwc2_hsotg_req, |
1702 | queue); | |
9c39ddc6 AT |
1703 | } |
1704 | ||
41cc4cd2 VM |
1705 | /** |
1706 | * dwc2_gadget_start_next_request - Starts next request from ep queue | |
1707 | * @hs_ep: Endpoint structure | |
1708 | * | |
1709 | * If queue is empty and EP is ISOC-OUT - unmasks OUTTKNEPDIS which is masked | |
1710 | * in its handler. Hence we need to unmask it here to be able to do | |
1711 | * resynchronization. | |
1712 | */ | |
1713 | static void dwc2_gadget_start_next_request(struct dwc2_hsotg_ep *hs_ep) | |
1714 | { | |
1715 | u32 mask; | |
1716 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
1717 | int dir_in = hs_ep->dir_in; | |
1718 | struct dwc2_hsotg_req *hs_req; | |
1719 | u32 epmsk_reg = dir_in ? DIEPMSK : DOEPMSK; | |
1720 | ||
1721 | if (!list_empty(&hs_ep->queue)) { | |
1722 | hs_req = get_ep_head(hs_ep); | |
1723 | dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, false); | |
1724 | return; | |
1725 | } | |
1726 | if (!hs_ep->isochronous) | |
1727 | return; | |
1728 | ||
1729 | if (dir_in) { | |
1730 | dev_dbg(hsotg->dev, "%s: No more ISOC-IN requests\n", | |
1731 | __func__); | |
1732 | } else { | |
1733 | dev_dbg(hsotg->dev, "%s: No more ISOC-OUT requests\n", | |
1734 | __func__); | |
f25c42b8 | 1735 | mask = dwc2_readl(hsotg, epmsk_reg); |
41cc4cd2 | 1736 | mask |= DOEPMSK_OUTTKNEPDISMSK; |
f25c42b8 | 1737 | dwc2_writel(hsotg, mask, epmsk_reg); |
41cc4cd2 VM |
1738 | } |
1739 | } | |
1740 | ||
5b7d70c6 | 1741 | /** |
1f91b4cc | 1742 | * dwc2_hsotg_process_req_feature - process request {SET,CLEAR}_FEATURE |
5b7d70c6 BD |
1743 | * @hsotg: The device state |
1744 | * @ctrl: USB control request | |
1745 | */ | |
1f91b4cc | 1746 | static int dwc2_hsotg_process_req_feature(struct dwc2_hsotg *hsotg, |
9da51974 | 1747 | struct usb_ctrlrequest *ctrl) |
5b7d70c6 | 1748 | { |
1f91b4cc FB |
1749 | struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0]; |
1750 | struct dwc2_hsotg_req *hs_req; | |
5b7d70c6 | 1751 | bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE); |
1f91b4cc | 1752 | struct dwc2_hsotg_ep *ep; |
26ab3d0c | 1753 | int ret; |
bd9ef7bf | 1754 | bool halted; |
9e14d0a5 GH |
1755 | u32 recip; |
1756 | u32 wValue; | |
1757 | u32 wIndex; | |
5b7d70c6 BD |
1758 | |
1759 | dev_dbg(hsotg->dev, "%s: %s_FEATURE\n", | |
1760 | __func__, set ? "SET" : "CLEAR"); | |
1761 | ||
9e14d0a5 GH |
1762 | wValue = le16_to_cpu(ctrl->wValue); |
1763 | wIndex = le16_to_cpu(ctrl->wIndex); | |
1764 | recip = ctrl->bRequestType & USB_RECIP_MASK; | |
1765 | ||
1766 | switch (recip) { | |
1767 | case USB_RECIP_DEVICE: | |
1768 | switch (wValue) { | |
fa389a6d | 1769 | case USB_DEVICE_REMOTE_WAKEUP: |
9a0d6f7c MH |
1770 | if (set) |
1771 | hsotg->remote_wakeup_allowed = 1; | |
1772 | else | |
1773 | hsotg->remote_wakeup_allowed = 0; | |
fa389a6d VM |
1774 | break; |
1775 | ||
9e14d0a5 GH |
1776 | case USB_DEVICE_TEST_MODE: |
1777 | if ((wIndex & 0xff) != 0) | |
1778 | return -EINVAL; | |
1779 | if (!set) | |
1780 | return -EINVAL; | |
1781 | ||
1782 | hsotg->test_mode = wIndex >> 8; | |
9e14d0a5 GH |
1783 | break; |
1784 | default: | |
1785 | return -ENOENT; | |
1786 | } | |
9a0d6f7c MH |
1787 | |
1788 | ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0); | |
1789 | if (ret) { | |
1790 | dev_err(hsotg->dev, | |
1791 | "%s: failed to send reply\n", __func__); | |
1792 | return ret; | |
1793 | } | |
9e14d0a5 GH |
1794 | break; |
1795 | ||
1796 | case USB_RECIP_ENDPOINT: | |
1797 | ep = ep_from_windex(hsotg, wIndex); | |
5b7d70c6 BD |
1798 | if (!ep) { |
1799 | dev_dbg(hsotg->dev, "%s: no endpoint for 0x%04x\n", | |
9e14d0a5 | 1800 | __func__, wIndex); |
5b7d70c6 BD |
1801 | return -ENOENT; |
1802 | } | |
1803 | ||
9e14d0a5 | 1804 | switch (wValue) { |
5b7d70c6 | 1805 | case USB_ENDPOINT_HALT: |
bd9ef7bf RB |
1806 | halted = ep->halted; |
1807 | ||
51da43b5 | 1808 | dwc2_hsotg_ep_sethalt(&ep->ep, set, true); |
26ab3d0c | 1809 | |
1f91b4cc | 1810 | ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0); |
26ab3d0c AT |
1811 | if (ret) { |
1812 | dev_err(hsotg->dev, | |
1813 | "%s: failed to send reply\n", __func__); | |
1814 | return ret; | |
1815 | } | |
9c39ddc6 | 1816 | |
bd9ef7bf RB |
1817 | /* |
1818 | * we have to complete all requests for ep if it was | |
1819 | * halted, and the halt was cleared by CLEAR_FEATURE | |
1820 | */ | |
1821 | ||
1822 | if (!set && halted) { | |
9c39ddc6 AT |
1823 | /* |
1824 | * If we have request in progress, | |
1825 | * then complete it | |
1826 | */ | |
1827 | if (ep->req) { | |
1828 | hs_req = ep->req; | |
1829 | ep->req = NULL; | |
1830 | list_del_init(&hs_req->queue); | |
c00dd4a6 GH |
1831 | if (hs_req->req.complete) { |
1832 | spin_unlock(&hsotg->lock); | |
1833 | usb_gadget_giveback_request( | |
1834 | &ep->ep, &hs_req->req); | |
1835 | spin_lock(&hsotg->lock); | |
1836 | } | |
9c39ddc6 AT |
1837 | } |
1838 | ||
1839 | /* If we have pending request, then start it */ | |
34c0887f | 1840 | if (!ep->req) |
41cc4cd2 | 1841 | dwc2_gadget_start_next_request(ep); |
9c39ddc6 AT |
1842 | } |
1843 | ||
5b7d70c6 BD |
1844 | break; |
1845 | ||
1846 | default: | |
1847 | return -ENOENT; | |
1848 | } | |
9e14d0a5 GH |
1849 | break; |
1850 | default: | |
1851 | return -ENOENT; | |
1852 | } | |
5b7d70c6 BD |
1853 | return 1; |
1854 | } | |
1855 | ||
1f91b4cc | 1856 | static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg); |
ab93e014 | 1857 | |
c9f721b2 | 1858 | /** |
1f91b4cc | 1859 | * dwc2_hsotg_stall_ep0 - stall ep0 |
c9f721b2 RB |
1860 | * @hsotg: The device state |
1861 | * | |
1862 | * Set stall for ep0 as response for setup request. | |
1863 | */ | |
1f91b4cc | 1864 | static void dwc2_hsotg_stall_ep0(struct dwc2_hsotg *hsotg) |
e9ebe7c3 | 1865 | { |
1f91b4cc | 1866 | struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0]; |
c9f721b2 RB |
1867 | u32 reg; |
1868 | u32 ctrl; | |
1869 | ||
1870 | dev_dbg(hsotg->dev, "ep0 stall (dir=%d)\n", ep0->dir_in); | |
1871 | reg = (ep0->dir_in) ? DIEPCTL0 : DOEPCTL0; | |
1872 | ||
1873 | /* | |
1874 | * DxEPCTL_Stall will be cleared by EP once it has | |
1875 | * taken effect, so no need to clear later. | |
1876 | */ | |
1877 | ||
f25c42b8 | 1878 | ctrl = dwc2_readl(hsotg, reg); |
47a1685f DN |
1879 | ctrl |= DXEPCTL_STALL; |
1880 | ctrl |= DXEPCTL_CNAK; | |
f25c42b8 | 1881 | dwc2_writel(hsotg, ctrl, reg); |
c9f721b2 RB |
1882 | |
1883 | dev_dbg(hsotg->dev, | |
47a1685f | 1884 | "written DXEPCTL=0x%08x to %08x (DXEPCTL=0x%08x)\n", |
f25c42b8 | 1885 | ctrl, reg, dwc2_readl(hsotg, reg)); |
c9f721b2 RB |
1886 | |
1887 | /* | |
1888 | * complete won't be called, so we enqueue | |
1889 | * setup request here | |
1890 | */ | |
1f91b4cc | 1891 | dwc2_hsotg_enqueue_setup(hsotg); |
c9f721b2 RB |
1892 | } |
1893 | ||
5b7d70c6 | 1894 | /** |
1f91b4cc | 1895 | * dwc2_hsotg_process_control - process a control request |
5b7d70c6 BD |
1896 | * @hsotg: The device state |
1897 | * @ctrl: The control request received | |
1898 | * | |
1899 | * The controller has received the SETUP phase of a control request, and | |
1900 | * needs to work out what to do next (and whether to pass it on to the | |
1901 | * gadget driver). | |
1902 | */ | |
1f91b4cc | 1903 | static void dwc2_hsotg_process_control(struct dwc2_hsotg *hsotg, |
9da51974 | 1904 | struct usb_ctrlrequest *ctrl) |
5b7d70c6 | 1905 | { |
1f91b4cc | 1906 | struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0]; |
5b7d70c6 BD |
1907 | int ret = 0; |
1908 | u32 dcfg; | |
1909 | ||
e525e743 MYK |
1910 | dev_dbg(hsotg->dev, |
1911 | "ctrl Type=%02x, Req=%02x, V=%04x, I=%04x, L=%04x\n", | |
1912 | ctrl->bRequestType, ctrl->bRequest, ctrl->wValue, | |
1913 | ctrl->wIndex, ctrl->wLength); | |
5b7d70c6 | 1914 | |
fe0b94ab MYK |
1915 | if (ctrl->wLength == 0) { |
1916 | ep0->dir_in = 1; | |
1917 | hsotg->ep0_state = DWC2_EP0_STATUS_IN; | |
1918 | } else if (ctrl->bRequestType & USB_DIR_IN) { | |
5b7d70c6 | 1919 | ep0->dir_in = 1; |
fe0b94ab MYK |
1920 | hsotg->ep0_state = DWC2_EP0_DATA_IN; |
1921 | } else { | |
1922 | ep0->dir_in = 0; | |
1923 | hsotg->ep0_state = DWC2_EP0_DATA_OUT; | |
1924 | } | |
5b7d70c6 BD |
1925 | |
1926 | if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) { | |
1927 | switch (ctrl->bRequest) { | |
1928 | case USB_REQ_SET_ADDRESS: | |
6d713c15 | 1929 | hsotg->connected = 1; |
f25c42b8 | 1930 | dcfg = dwc2_readl(hsotg, DCFG); |
47a1685f | 1931 | dcfg &= ~DCFG_DEVADDR_MASK; |
d5dbd3f7 PZ |
1932 | dcfg |= (le16_to_cpu(ctrl->wValue) << |
1933 | DCFG_DEVADDR_SHIFT) & DCFG_DEVADDR_MASK; | |
f25c42b8 | 1934 | dwc2_writel(hsotg, dcfg, DCFG); |
5b7d70c6 BD |
1935 | |
1936 | dev_info(hsotg->dev, "new address %d\n", ctrl->wValue); | |
1937 | ||
1f91b4cc | 1938 | ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0); |
5b7d70c6 BD |
1939 | return; |
1940 | ||
1941 | case USB_REQ_GET_STATUS: | |
1f91b4cc | 1942 | ret = dwc2_hsotg_process_req_status(hsotg, ctrl); |
5b7d70c6 BD |
1943 | break; |
1944 | ||
1945 | case USB_REQ_CLEAR_FEATURE: | |
1946 | case USB_REQ_SET_FEATURE: | |
1f91b4cc | 1947 | ret = dwc2_hsotg_process_req_feature(hsotg, ctrl); |
5b7d70c6 BD |
1948 | break; |
1949 | } | |
1950 | } | |
1951 | ||
1952 | /* as a fallback, try delivering it to the driver to deal with */ | |
1953 | ||
1954 | if (ret == 0 && hsotg->driver) { | |
93f599f2 | 1955 | spin_unlock(&hsotg->lock); |
5b7d70c6 | 1956 | ret = hsotg->driver->setup(&hsotg->gadget, ctrl); |
93f599f2 | 1957 | spin_lock(&hsotg->lock); |
5b7d70c6 BD |
1958 | if (ret < 0) |
1959 | dev_dbg(hsotg->dev, "driver->setup() ret %d\n", ret); | |
1960 | } | |
1961 | ||
b4c53b4a MH |
1962 | hsotg->delayed_status = false; |
1963 | if (ret == USB_GADGET_DELAYED_STATUS) | |
1964 | hsotg->delayed_status = true; | |
1965 | ||
8b9bc460 LM |
1966 | /* |
1967 | * the request is either unhandlable, or is not formatted correctly | |
5b7d70c6 BD |
1968 | * so respond with a STALL for the status stage to indicate failure. |
1969 | */ | |
1970 | ||
c9f721b2 | 1971 | if (ret < 0) |
1f91b4cc | 1972 | dwc2_hsotg_stall_ep0(hsotg); |
5b7d70c6 BD |
1973 | } |
1974 | ||
5b7d70c6 | 1975 | /** |
1f91b4cc | 1976 | * dwc2_hsotg_complete_setup - completion of a setup transfer |
5b7d70c6 BD |
1977 | * @ep: The endpoint the request was on. |
1978 | * @req: The request completed. | |
1979 | * | |
1980 | * Called on completion of any requests the driver itself submitted for | |
1981 | * EP0 setup packets | |
1982 | */ | |
1f91b4cc | 1983 | static void dwc2_hsotg_complete_setup(struct usb_ep *ep, |
9da51974 | 1984 | struct usb_request *req) |
5b7d70c6 | 1985 | { |
1f91b4cc | 1986 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 1987 | struct dwc2_hsotg *hsotg = hs_ep->parent; |
5b7d70c6 BD |
1988 | |
1989 | if (req->status < 0) { | |
1990 | dev_dbg(hsotg->dev, "%s: failed %d\n", __func__, req->status); | |
1991 | return; | |
1992 | } | |
1993 | ||
93f599f2 | 1994 | spin_lock(&hsotg->lock); |
5b7d70c6 | 1995 | if (req->actual == 0) |
1f91b4cc | 1996 | dwc2_hsotg_enqueue_setup(hsotg); |
5b7d70c6 | 1997 | else |
1f91b4cc | 1998 | dwc2_hsotg_process_control(hsotg, req->buf); |
93f599f2 | 1999 | spin_unlock(&hsotg->lock); |
5b7d70c6 BD |
2000 | } |
2001 | ||
2002 | /** | |
1f91b4cc | 2003 | * dwc2_hsotg_enqueue_setup - start a request for EP0 packets |
5b7d70c6 BD |
2004 | * @hsotg: The device state. |
2005 | * | |
2006 | * Enqueue a request on EP0 if necessary to received any SETUP packets | |
2007 | * received from the host. | |
2008 | */ | |
1f91b4cc | 2009 | static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg) |
5b7d70c6 BD |
2010 | { |
2011 | struct usb_request *req = hsotg->ctrl_req; | |
1f91b4cc | 2012 | struct dwc2_hsotg_req *hs_req = our_req(req); |
5b7d70c6 BD |
2013 | int ret; |
2014 | ||
2015 | dev_dbg(hsotg->dev, "%s: queueing setup request\n", __func__); | |
2016 | ||
2017 | req->zero = 0; | |
2018 | req->length = 8; | |
2019 | req->buf = hsotg->ctrl_buff; | |
1f91b4cc | 2020 | req->complete = dwc2_hsotg_complete_setup; |
5b7d70c6 BD |
2021 | |
2022 | if (!list_empty(&hs_req->queue)) { | |
2023 | dev_dbg(hsotg->dev, "%s already queued???\n", __func__); | |
2024 | return; | |
2025 | } | |
2026 | ||
c6f5c050 | 2027 | hsotg->eps_out[0]->dir_in = 0; |
8a20fa45 | 2028 | hsotg->eps_out[0]->send_zlp = 0; |
fe0b94ab | 2029 | hsotg->ep0_state = DWC2_EP0_SETUP; |
5b7d70c6 | 2030 | |
1f91b4cc | 2031 | ret = dwc2_hsotg_ep_queue(&hsotg->eps_out[0]->ep, req, GFP_ATOMIC); |
5b7d70c6 BD |
2032 | if (ret < 0) { |
2033 | dev_err(hsotg->dev, "%s: failed queue (%d)\n", __func__, ret); | |
8b9bc460 LM |
2034 | /* |
2035 | * Don't think there's much we can do other than watch the | |
2036 | * driver fail. | |
2037 | */ | |
5b7d70c6 BD |
2038 | } |
2039 | } | |
2040 | ||
1f91b4cc | 2041 | static void dwc2_hsotg_program_zlp(struct dwc2_hsotg *hsotg, |
9da51974 | 2042 | struct dwc2_hsotg_ep *hs_ep) |
fe0b94ab MYK |
2043 | { |
2044 | u32 ctrl; | |
2045 | u8 index = hs_ep->index; | |
2046 | u32 epctl_reg = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index); | |
2047 | u32 epsiz_reg = hs_ep->dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index); | |
2048 | ||
ccb34a91 MYK |
2049 | if (hs_ep->dir_in) |
2050 | dev_dbg(hsotg->dev, "Sending zero-length packet on ep%d\n", | |
e02f9aa6 | 2051 | index); |
ccb34a91 MYK |
2052 | else |
2053 | dev_dbg(hsotg->dev, "Receiving zero-length packet on ep%d\n", | |
e02f9aa6 VA |
2054 | index); |
2055 | if (using_desc_dma(hsotg)) { | |
066cfd07 AP |
2056 | /* Not specific buffer needed for ep0 ZLP */ |
2057 | dma_addr_t dma = hs_ep->desc_list_dma; | |
2058 | ||
201ec568 MH |
2059 | if (!index) |
2060 | dwc2_gadget_set_ep0_desc_chain(hsotg, hs_ep); | |
2061 | ||
066cfd07 | 2062 | dwc2_gadget_config_nonisoc_xfer_ddma(hs_ep, dma, 0); |
e02f9aa6 | 2063 | } else { |
f25c42b8 GS |
2064 | dwc2_writel(hsotg, DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) | |
2065 | DXEPTSIZ_XFERSIZE(0), | |
e02f9aa6 VA |
2066 | epsiz_reg); |
2067 | } | |
fe0b94ab | 2068 | |
f25c42b8 | 2069 | ctrl = dwc2_readl(hsotg, epctl_reg); |
fe0b94ab MYK |
2070 | ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */ |
2071 | ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */ | |
2072 | ctrl |= DXEPCTL_USBACTEP; | |
f25c42b8 | 2073 | dwc2_writel(hsotg, ctrl, epctl_reg); |
fe0b94ab MYK |
2074 | } |
2075 | ||
5b7d70c6 | 2076 | /** |
1f91b4cc | 2077 | * dwc2_hsotg_complete_request - complete a request given to us |
5b7d70c6 BD |
2078 | * @hsotg: The device state. |
2079 | * @hs_ep: The endpoint the request was on. | |
2080 | * @hs_req: The request to complete. | |
2081 | * @result: The result code (0 => Ok, otherwise errno) | |
2082 | * | |
2083 | * The given request has finished, so call the necessary completion | |
2084 | * if it has one and then look to see if we can start a new request | |
2085 | * on the endpoint. | |
2086 | * | |
2087 | * Note, expects the ep to already be locked as appropriate. | |
8b9bc460 | 2088 | */ |
1f91b4cc | 2089 | static void dwc2_hsotg_complete_request(struct dwc2_hsotg *hsotg, |
9da51974 | 2090 | struct dwc2_hsotg_ep *hs_ep, |
1f91b4cc | 2091 | struct dwc2_hsotg_req *hs_req, |
5b7d70c6 BD |
2092 | int result) |
2093 | { | |
5b7d70c6 BD |
2094 | if (!hs_req) { |
2095 | dev_dbg(hsotg->dev, "%s: nothing to complete?\n", __func__); | |
2096 | return; | |
2097 | } | |
2098 | ||
2099 | dev_dbg(hsotg->dev, "complete: ep %p %s, req %p, %d => %p\n", | |
2100 | hs_ep, hs_ep->ep.name, hs_req, result, hs_req->req.complete); | |
2101 | ||
8b9bc460 LM |
2102 | /* |
2103 | * only replace the status if we've not already set an error | |
2104 | * from a previous transaction | |
2105 | */ | |
5b7d70c6 BD |
2106 | |
2107 | if (hs_req->req.status == -EINPROGRESS) | |
2108 | hs_req->req.status = result; | |
2109 | ||
44583fec YL |
2110 | if (using_dma(hsotg)) |
2111 | dwc2_hsotg_unmap_dma(hsotg, hs_ep, hs_req); | |
2112 | ||
1f91b4cc | 2113 | dwc2_hsotg_handle_unaligned_buf_complete(hsotg, hs_ep, hs_req); |
7d24c1b5 | 2114 | |
5b7d70c6 BD |
2115 | hs_ep->req = NULL; |
2116 | list_del_init(&hs_req->queue); | |
2117 | ||
8b9bc460 LM |
2118 | /* |
2119 | * call the complete request with the locks off, just in case the | |
2120 | * request tries to queue more work for this endpoint. | |
2121 | */ | |
5b7d70c6 BD |
2122 | |
2123 | if (hs_req->req.complete) { | |
22258f49 | 2124 | spin_unlock(&hsotg->lock); |
304f7e5e | 2125 | usb_gadget_giveback_request(&hs_ep->ep, &hs_req->req); |
22258f49 | 2126 | spin_lock(&hsotg->lock); |
5b7d70c6 BD |
2127 | } |
2128 | ||
540ccba0 VA |
2129 | /* In DDMA don't need to proceed to starting of next ISOC request */ |
2130 | if (using_desc_dma(hsotg) && hs_ep->isochronous) | |
2131 | return; | |
2132 | ||
8b9bc460 LM |
2133 | /* |
2134 | * Look to see if there is anything else to do. Note, the completion | |
5b7d70c6 | 2135 | * of the previous request may have caused a new request to be started |
8b9bc460 LM |
2136 | * so be careful when doing this. |
2137 | */ | |
5b7d70c6 | 2138 | |
34c0887f | 2139 | if (!hs_ep->req && result >= 0) |
41cc4cd2 | 2140 | dwc2_gadget_start_next_request(hs_ep); |
5b7d70c6 BD |
2141 | } |
2142 | ||
540ccba0 VA |
2143 | /* |
2144 | * dwc2_gadget_complete_isoc_request_ddma - complete an isoc request in DDMA | |
2145 | * @hs_ep: The endpoint the request was on. | |
2146 | * | |
2147 | * Get first request from the ep queue, determine descriptor on which complete | |
729cac69 MH |
2148 | * happened. SW discovers which descriptor currently in use by HW, adjusts |
2149 | * dma_address and calculates index of completed descriptor based on the value | |
2150 | * of DEPDMA register. Update actual length of request, giveback to gadget. | |
540ccba0 VA |
2151 | */ |
2152 | static void dwc2_gadget_complete_isoc_request_ddma(struct dwc2_hsotg_ep *hs_ep) | |
2153 | { | |
2154 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
2155 | struct dwc2_hsotg_req *hs_req; | |
2156 | struct usb_request *ureq; | |
540ccba0 VA |
2157 | u32 desc_sts; |
2158 | u32 mask; | |
2159 | ||
729cac69 | 2160 | desc_sts = hs_ep->desc_list[hs_ep->compl_desc].status; |
540ccba0 | 2161 | |
729cac69 MH |
2162 | /* Process only descriptors with buffer status set to DMA done */ |
2163 | while ((desc_sts & DEV_DMA_BUFF_STS_MASK) >> | |
2164 | DEV_DMA_BUFF_STS_SHIFT == DEV_DMA_BUFF_STS_DMADONE) { | |
540ccba0 | 2165 | |
729cac69 MH |
2166 | hs_req = get_ep_head(hs_ep); |
2167 | if (!hs_req) { | |
2168 | dev_warn(hsotg->dev, "%s: ISOC EP queue empty\n", __func__); | |
2169 | return; | |
2170 | } | |
2171 | ureq = &hs_req->req; | |
2172 | ||
2173 | /* Check completion status */ | |
2174 | if ((desc_sts & DEV_DMA_STS_MASK) >> DEV_DMA_STS_SHIFT == | |
2175 | DEV_DMA_STS_SUCC) { | |
2176 | mask = hs_ep->dir_in ? DEV_DMA_ISOC_TX_NBYTES_MASK : | |
2177 | DEV_DMA_ISOC_RX_NBYTES_MASK; | |
2178 | ureq->actual = ureq->length - ((desc_sts & mask) >> | |
2179 | DEV_DMA_ISOC_NBYTES_SHIFT); | |
2180 | ||
2181 | /* Adjust actual len for ISOC Out if len is | |
2182 | * not align of 4 | |
2183 | */ | |
2184 | if (!hs_ep->dir_in && ureq->length & 0x3) | |
2185 | ureq->actual += 4 - (ureq->length & 0x3); | |
c8006f67 MH |
2186 | |
2187 | /* Set actual frame number for completed transfers */ | |
2188 | ureq->frame_number = | |
2189 | (desc_sts & DEV_DMA_ISOC_FRNUM_MASK) >> | |
2190 | DEV_DMA_ISOC_FRNUM_SHIFT; | |
729cac69 | 2191 | } |
540ccba0 | 2192 | |
729cac69 | 2193 | dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0); |
95d2b037 | 2194 | |
729cac69 | 2195 | hs_ep->compl_desc++; |
54f37f56 | 2196 | if (hs_ep->compl_desc > (MAX_DMA_DESC_NUM_HS_ISOC - 1)) |
729cac69 MH |
2197 | hs_ep->compl_desc = 0; |
2198 | desc_sts = hs_ep->desc_list[hs_ep->compl_desc].status; | |
2199 | } | |
540ccba0 VA |
2200 | } |
2201 | ||
2202 | /* | |
729cac69 MH |
2203 | * dwc2_gadget_handle_isoc_bna - handle BNA interrupt for ISOC. |
2204 | * @hs_ep: The isochronous endpoint. | |
540ccba0 | 2205 | * |
729cac69 MH |
2206 | * If EP ISOC OUT then need to flush RX FIFO to remove source of BNA |
2207 | * interrupt. Reset target frame and next_desc to allow to start | |
2208 | * ISOC's on NAK interrupt for IN direction or on OUTTKNEPDIS | |
2209 | * interrupt for OUT direction. | |
540ccba0 | 2210 | */ |
729cac69 | 2211 | static void dwc2_gadget_handle_isoc_bna(struct dwc2_hsotg_ep *hs_ep) |
540ccba0 VA |
2212 | { |
2213 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
540ccba0 | 2214 | |
729cac69 MH |
2215 | if (!hs_ep->dir_in) |
2216 | dwc2_flush_rx_fifo(hsotg); | |
2217 | dwc2_hsotg_complete_request(hsotg, hs_ep, get_ep_head(hs_ep), 0); | |
540ccba0 | 2218 | |
729cac69 MH |
2219 | hs_ep->target_frame = TARGET_FRAME_INITIAL; |
2220 | hs_ep->next_desc = 0; | |
2221 | hs_ep->compl_desc = 0; | |
540ccba0 VA |
2222 | } |
2223 | ||
5b7d70c6 | 2224 | /** |
1f91b4cc | 2225 | * dwc2_hsotg_rx_data - receive data from the FIFO for an endpoint |
5b7d70c6 BD |
2226 | * @hsotg: The device state. |
2227 | * @ep_idx: The endpoint index for the data | |
2228 | * @size: The size of data in the fifo, in bytes | |
2229 | * | |
2230 | * The FIFO status shows there is data to read from the FIFO for a given | |
2231 | * endpoint, so sort out whether we need to read the data into a request | |
2232 | * that has been made for that endpoint. | |
2233 | */ | |
1f91b4cc | 2234 | static void dwc2_hsotg_rx_data(struct dwc2_hsotg *hsotg, int ep_idx, int size) |
5b7d70c6 | 2235 | { |
1f91b4cc FB |
2236 | struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[ep_idx]; |
2237 | struct dwc2_hsotg_req *hs_req = hs_ep->req; | |
5b7d70c6 BD |
2238 | int to_read; |
2239 | int max_req; | |
2240 | int read_ptr; | |
2241 | ||
2242 | if (!hs_req) { | |
f25c42b8 | 2243 | u32 epctl = dwc2_readl(hsotg, DOEPCTL(ep_idx)); |
5b7d70c6 BD |
2244 | int ptr; |
2245 | ||
6b448af4 | 2246 | dev_dbg(hsotg->dev, |
9da51974 | 2247 | "%s: FIFO %d bytes on ep%d but no req (DXEPCTl=0x%08x)\n", |
5b7d70c6 BD |
2248 | __func__, size, ep_idx, epctl); |
2249 | ||
2250 | /* dump the data from the FIFO, we've nothing we can do */ | |
2251 | for (ptr = 0; ptr < size; ptr += 4) | |
f25c42b8 | 2252 | (void)dwc2_readl(hsotg, EPFIFO(ep_idx)); |
5b7d70c6 BD |
2253 | |
2254 | return; | |
2255 | } | |
2256 | ||
5b7d70c6 BD |
2257 | to_read = size; |
2258 | read_ptr = hs_req->req.actual; | |
2259 | max_req = hs_req->req.length - read_ptr; | |
2260 | ||
a33e7136 BD |
2261 | dev_dbg(hsotg->dev, "%s: read %d/%d, done %d/%d\n", |
2262 | __func__, to_read, max_req, read_ptr, hs_req->req.length); | |
2263 | ||
5b7d70c6 | 2264 | if (to_read > max_req) { |
8b9bc460 LM |
2265 | /* |
2266 | * more data appeared than we where willing | |
5b7d70c6 BD |
2267 | * to deal with in this request. |
2268 | */ | |
2269 | ||
2270 | /* currently we don't deal this */ | |
2271 | WARN_ON_ONCE(1); | |
2272 | } | |
2273 | ||
5b7d70c6 BD |
2274 | hs_ep->total_data += to_read; |
2275 | hs_req->req.actual += to_read; | |
2276 | to_read = DIV_ROUND_UP(to_read, 4); | |
2277 | ||
8b9bc460 LM |
2278 | /* |
2279 | * note, we might over-write the buffer end by 3 bytes depending on | |
2280 | * alignment of the data. | |
2281 | */ | |
342ccce1 GS |
2282 | dwc2_readl_rep(hsotg, EPFIFO(ep_idx), |
2283 | hs_req->req.buf + read_ptr, to_read); | |
5b7d70c6 BD |
2284 | } |
2285 | ||
2286 | /** | |
1f91b4cc | 2287 | * dwc2_hsotg_ep0_zlp - send/receive zero-length packet on control endpoint |
5b7d70c6 | 2288 | * @hsotg: The device instance |
fe0b94ab | 2289 | * @dir_in: If IN zlp |
5b7d70c6 BD |
2290 | * |
2291 | * Generate a zero-length IN packet request for terminating a SETUP | |
2292 | * transaction. | |
2293 | * | |
2294 | * Note, since we don't write any data to the TxFIFO, then it is | |
25985edc | 2295 | * currently believed that we do not need to wait for any space in |
5b7d70c6 BD |
2296 | * the TxFIFO. |
2297 | */ | |
1f91b4cc | 2298 | static void dwc2_hsotg_ep0_zlp(struct dwc2_hsotg *hsotg, bool dir_in) |
5b7d70c6 | 2299 | { |
c6f5c050 | 2300 | /* eps_out[0] is used in both directions */ |
fe0b94ab MYK |
2301 | hsotg->eps_out[0]->dir_in = dir_in; |
2302 | hsotg->ep0_state = dir_in ? DWC2_EP0_STATUS_IN : DWC2_EP0_STATUS_OUT; | |
5b7d70c6 | 2303 | |
1f91b4cc | 2304 | dwc2_hsotg_program_zlp(hsotg, hsotg->eps_out[0]); |
5b7d70c6 BD |
2305 | } |
2306 | ||
ec1f9d9f | 2307 | static void dwc2_hsotg_change_ep_iso_parity(struct dwc2_hsotg *hsotg, |
9da51974 | 2308 | u32 epctl_reg) |
ec1f9d9f RB |
2309 | { |
2310 | u32 ctrl; | |
2311 | ||
f25c42b8 | 2312 | ctrl = dwc2_readl(hsotg, epctl_reg); |
ec1f9d9f RB |
2313 | if (ctrl & DXEPCTL_EOFRNUM) |
2314 | ctrl |= DXEPCTL_SETEVENFR; | |
2315 | else | |
2316 | ctrl |= DXEPCTL_SETODDFR; | |
f25c42b8 | 2317 | dwc2_writel(hsotg, ctrl, epctl_reg); |
ec1f9d9f RB |
2318 | } |
2319 | ||
aa3e8bc8 VA |
2320 | /* |
2321 | * dwc2_gadget_get_xfersize_ddma - get transferred bytes amount from desc | |
2322 | * @hs_ep - The endpoint on which transfer went | |
2323 | * | |
2324 | * Iterate over endpoints descriptor chain and get info on bytes remained | |
2325 | * in DMA descriptors after transfer has completed. Used for non isoc EPs. | |
2326 | */ | |
2327 | static unsigned int dwc2_gadget_get_xfersize_ddma(struct dwc2_hsotg_ep *hs_ep) | |
2328 | { | |
b2c586eb | 2329 | const struct usb_endpoint_descriptor *ep_desc = hs_ep->ep.desc; |
aa3e8bc8 VA |
2330 | struct dwc2_hsotg *hsotg = hs_ep->parent; |
2331 | unsigned int bytes_rem = 0; | |
b2c586eb | 2332 | unsigned int bytes_rem_correction = 0; |
aa3e8bc8 VA |
2333 | struct dwc2_dma_desc *desc = hs_ep->desc_list; |
2334 | int i; | |
2335 | u32 status; | |
b2c586eb MH |
2336 | u32 mps = hs_ep->ep.maxpacket; |
2337 | int dir_in = hs_ep->dir_in; | |
aa3e8bc8 VA |
2338 | |
2339 | if (!desc) | |
2340 | return -EINVAL; | |
2341 | ||
b2c586eb MH |
2342 | /* Interrupt OUT EP with mps not multiple of 4 */ |
2343 | if (hs_ep->index) | |
2344 | if (usb_endpoint_xfer_int(ep_desc) && !dir_in && (mps % 4)) | |
2345 | bytes_rem_correction = 4 - (mps % 4); | |
2346 | ||
aa3e8bc8 VA |
2347 | for (i = 0; i < hs_ep->desc_count; ++i) { |
2348 | status = desc->status; | |
2349 | bytes_rem += status & DEV_DMA_NBYTES_MASK; | |
b2c586eb | 2350 | bytes_rem -= bytes_rem_correction; |
aa3e8bc8 VA |
2351 | |
2352 | if (status & DEV_DMA_STS_MASK) | |
2353 | dev_err(hsotg->dev, "descriptor %d closed with %x\n", | |
2354 | i, status & DEV_DMA_STS_MASK); | |
b2c586eb MH |
2355 | |
2356 | if (status & DEV_DMA_L) | |
2357 | break; | |
2358 | ||
5acb4b97 | 2359 | desc++; |
aa3e8bc8 VA |
2360 | } |
2361 | ||
2362 | return bytes_rem; | |
2363 | } | |
2364 | ||
5b7d70c6 | 2365 | /** |
1f91b4cc | 2366 | * dwc2_hsotg_handle_outdone - handle receiving OutDone/SetupDone from RXFIFO |
5b7d70c6 BD |
2367 | * @hsotg: The device instance |
2368 | * @epnum: The endpoint received from | |
5b7d70c6 BD |
2369 | * |
2370 | * The RXFIFO has delivered an OutDone event, which means that the data | |
2371 | * transfer for an OUT endpoint has been completed, either by a short | |
2372 | * packet or by the finish of a transfer. | |
8b9bc460 | 2373 | */ |
1f91b4cc | 2374 | static void dwc2_hsotg_handle_outdone(struct dwc2_hsotg *hsotg, int epnum) |
5b7d70c6 | 2375 | { |
f25c42b8 | 2376 | u32 epsize = dwc2_readl(hsotg, DOEPTSIZ(epnum)); |
1f91b4cc FB |
2377 | struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[epnum]; |
2378 | struct dwc2_hsotg_req *hs_req = hs_ep->req; | |
5b7d70c6 | 2379 | struct usb_request *req = &hs_req->req; |
9da51974 | 2380 | unsigned int size_left = DXEPTSIZ_XFERSIZE_GET(epsize); |
5b7d70c6 BD |
2381 | int result = 0; |
2382 | ||
2383 | if (!hs_req) { | |
2384 | dev_dbg(hsotg->dev, "%s: no request active\n", __func__); | |
2385 | return; | |
2386 | } | |
2387 | ||
fe0b94ab MYK |
2388 | if (epnum == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_OUT) { |
2389 | dev_dbg(hsotg->dev, "zlp packet received\n"); | |
1f91b4cc FB |
2390 | dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0); |
2391 | dwc2_hsotg_enqueue_setup(hsotg); | |
fe0b94ab MYK |
2392 | return; |
2393 | } | |
2394 | ||
aa3e8bc8 VA |
2395 | if (using_desc_dma(hsotg)) |
2396 | size_left = dwc2_gadget_get_xfersize_ddma(hs_ep); | |
2397 | ||
5b7d70c6 | 2398 | if (using_dma(hsotg)) { |
9da51974 | 2399 | unsigned int size_done; |
5b7d70c6 | 2400 | |
8b9bc460 LM |
2401 | /* |
2402 | * Calculate the size of the transfer by checking how much | |
5b7d70c6 BD |
2403 | * is left in the endpoint size register and then working it |
2404 | * out from the amount we loaded for the transfer. | |
2405 | * | |
2406 | * We need to do this as DMA pointers are always 32bit aligned | |
2407 | * so may overshoot/undershoot the transfer. | |
2408 | */ | |
2409 | ||
5b7d70c6 BD |
2410 | size_done = hs_ep->size_loaded - size_left; |
2411 | size_done += hs_ep->last_load; | |
2412 | ||
2413 | req->actual = size_done; | |
2414 | } | |
2415 | ||
a33e7136 BD |
2416 | /* if there is more request to do, schedule new transfer */ |
2417 | if (req->actual < req->length && size_left == 0) { | |
1f91b4cc | 2418 | dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true); |
a33e7136 BD |
2419 | return; |
2420 | } | |
2421 | ||
5b7d70c6 BD |
2422 | if (req->actual < req->length && req->short_not_ok) { |
2423 | dev_dbg(hsotg->dev, "%s: got %d/%d (short not ok) => error\n", | |
2424 | __func__, req->actual, req->length); | |
2425 | ||
8b9bc460 LM |
2426 | /* |
2427 | * todo - what should we return here? there's no one else | |
2428 | * even bothering to check the status. | |
2429 | */ | |
5b7d70c6 BD |
2430 | } |
2431 | ||
ef750c71 VA |
2432 | /* DDMA IN status phase will start from StsPhseRcvd interrupt */ |
2433 | if (!using_desc_dma(hsotg) && epnum == 0 && | |
2434 | hsotg->ep0_state == DWC2_EP0_DATA_OUT) { | |
fe0b94ab | 2435 | /* Move to STATUS IN */ |
b4c53b4a MH |
2436 | if (!hsotg->delayed_status) |
2437 | dwc2_hsotg_ep0_zlp(hsotg, true); | |
5b7d70c6 BD |
2438 | } |
2439 | ||
ec1f9d9f RB |
2440 | /* |
2441 | * Slave mode OUT transfers do not go through XferComplete so | |
2442 | * adjust the ISOC parity here. | |
2443 | */ | |
2444 | if (!using_dma(hsotg)) { | |
ec1f9d9f RB |
2445 | if (hs_ep->isochronous && hs_ep->interval == 1) |
2446 | dwc2_hsotg_change_ep_iso_parity(hsotg, DOEPCTL(epnum)); | |
837e9f00 VM |
2447 | else if (hs_ep->isochronous && hs_ep->interval > 1) |
2448 | dwc2_gadget_incr_frame_num(hs_ep); | |
ec1f9d9f RB |
2449 | } |
2450 | ||
4faf3b36 MH |
2451 | /* Set actual frame number for completed transfers */ |
2452 | if (!using_desc_dma(hsotg) && hs_ep->isochronous) | |
2453 | req->frame_number = hsotg->frame_number; | |
2454 | ||
1f91b4cc | 2455 | dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, result); |
5b7d70c6 BD |
2456 | } |
2457 | ||
5b7d70c6 | 2458 | /** |
1f91b4cc | 2459 | * dwc2_hsotg_handle_rx - RX FIFO has data |
5b7d70c6 BD |
2460 | * @hsotg: The device instance |
2461 | * | |
2462 | * The IRQ handler has detected that the RX FIFO has some data in it | |
2463 | * that requires processing, so find out what is in there and do the | |
2464 | * appropriate read. | |
2465 | * | |
25985edc | 2466 | * The RXFIFO is a true FIFO, the packets coming out are still in packet |
5b7d70c6 BD |
2467 | * chunks, so if you have x packets received on an endpoint you'll get x |
2468 | * FIFO events delivered, each with a packet's worth of data in it. | |
2469 | * | |
2470 | * When using DMA, we should not be processing events from the RXFIFO | |
2471 | * as the actual data should be sent to the memory directly and we turn | |
2472 | * on the completion interrupts to get notifications of transfer completion. | |
2473 | */ | |
1f91b4cc | 2474 | static void dwc2_hsotg_handle_rx(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 2475 | { |
f25c42b8 | 2476 | u32 grxstsr = dwc2_readl(hsotg, GRXSTSP); |
5b7d70c6 BD |
2477 | u32 epnum, status, size; |
2478 | ||
2479 | WARN_ON(using_dma(hsotg)); | |
2480 | ||
47a1685f DN |
2481 | epnum = grxstsr & GRXSTS_EPNUM_MASK; |
2482 | status = grxstsr & GRXSTS_PKTSTS_MASK; | |
5b7d70c6 | 2483 | |
47a1685f DN |
2484 | size = grxstsr & GRXSTS_BYTECNT_MASK; |
2485 | size >>= GRXSTS_BYTECNT_SHIFT; | |
5b7d70c6 | 2486 | |
d7c747c5 | 2487 | dev_dbg(hsotg->dev, "%s: GRXSTSP=0x%08x (%d@%d)\n", |
9da51974 | 2488 | __func__, grxstsr, size, epnum); |
5b7d70c6 | 2489 | |
47a1685f DN |
2490 | switch ((status & GRXSTS_PKTSTS_MASK) >> GRXSTS_PKTSTS_SHIFT) { |
2491 | case GRXSTS_PKTSTS_GLOBALOUTNAK: | |
2492 | dev_dbg(hsotg->dev, "GLOBALOUTNAK\n"); | |
5b7d70c6 BD |
2493 | break; |
2494 | ||
47a1685f | 2495 | case GRXSTS_PKTSTS_OUTDONE: |
5b7d70c6 | 2496 | dev_dbg(hsotg->dev, "OutDone (Frame=0x%08x)\n", |
1f91b4cc | 2497 | dwc2_hsotg_read_frameno(hsotg)); |
5b7d70c6 BD |
2498 | |
2499 | if (!using_dma(hsotg)) | |
1f91b4cc | 2500 | dwc2_hsotg_handle_outdone(hsotg, epnum); |
5b7d70c6 BD |
2501 | break; |
2502 | ||
47a1685f | 2503 | case GRXSTS_PKTSTS_SETUPDONE: |
5b7d70c6 BD |
2504 | dev_dbg(hsotg->dev, |
2505 | "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n", | |
1f91b4cc | 2506 | dwc2_hsotg_read_frameno(hsotg), |
f25c42b8 | 2507 | dwc2_readl(hsotg, DOEPCTL(0))); |
fe0b94ab | 2508 | /* |
1f91b4cc | 2509 | * Call dwc2_hsotg_handle_outdone here if it was not called from |
fe0b94ab MYK |
2510 | * GRXSTS_PKTSTS_OUTDONE. That is, if the core didn't |
2511 | * generate GRXSTS_PKTSTS_OUTDONE for setup packet. | |
2512 | */ | |
2513 | if (hsotg->ep0_state == DWC2_EP0_SETUP) | |
1f91b4cc | 2514 | dwc2_hsotg_handle_outdone(hsotg, epnum); |
5b7d70c6 BD |
2515 | break; |
2516 | ||
47a1685f | 2517 | case GRXSTS_PKTSTS_OUTRX: |
1f91b4cc | 2518 | dwc2_hsotg_rx_data(hsotg, epnum, size); |
5b7d70c6 BD |
2519 | break; |
2520 | ||
47a1685f | 2521 | case GRXSTS_PKTSTS_SETUPRX: |
5b7d70c6 BD |
2522 | dev_dbg(hsotg->dev, |
2523 | "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n", | |
1f91b4cc | 2524 | dwc2_hsotg_read_frameno(hsotg), |
f25c42b8 | 2525 | dwc2_readl(hsotg, DOEPCTL(0))); |
5b7d70c6 | 2526 | |
fe0b94ab MYK |
2527 | WARN_ON(hsotg->ep0_state != DWC2_EP0_SETUP); |
2528 | ||
1f91b4cc | 2529 | dwc2_hsotg_rx_data(hsotg, epnum, size); |
5b7d70c6 BD |
2530 | break; |
2531 | ||
2532 | default: | |
2533 | dev_warn(hsotg->dev, "%s: unknown status %08x\n", | |
2534 | __func__, grxstsr); | |
2535 | ||
1f91b4cc | 2536 | dwc2_hsotg_dump(hsotg); |
5b7d70c6 BD |
2537 | break; |
2538 | } | |
2539 | } | |
2540 | ||
2541 | /** | |
1f91b4cc | 2542 | * dwc2_hsotg_ep0_mps - turn max packet size into register setting |
5b7d70c6 | 2543 | * @mps: The maximum packet size in bytes. |
8b9bc460 | 2544 | */ |
1f91b4cc | 2545 | static u32 dwc2_hsotg_ep0_mps(unsigned int mps) |
5b7d70c6 BD |
2546 | { |
2547 | switch (mps) { | |
2548 | case 64: | |
94cb8fd6 | 2549 | return D0EPCTL_MPS_64; |
5b7d70c6 | 2550 | case 32: |
94cb8fd6 | 2551 | return D0EPCTL_MPS_32; |
5b7d70c6 | 2552 | case 16: |
94cb8fd6 | 2553 | return D0EPCTL_MPS_16; |
5b7d70c6 | 2554 | case 8: |
94cb8fd6 | 2555 | return D0EPCTL_MPS_8; |
5b7d70c6 BD |
2556 | } |
2557 | ||
2558 | /* bad max packet size, warn and return invalid result */ | |
2559 | WARN_ON(1); | |
2560 | return (u32)-1; | |
2561 | } | |
2562 | ||
2563 | /** | |
1f91b4cc | 2564 | * dwc2_hsotg_set_ep_maxpacket - set endpoint's max-packet field |
5b7d70c6 BD |
2565 | * @hsotg: The driver state. |
2566 | * @ep: The index number of the endpoint | |
2567 | * @mps: The maximum packet size in bytes | |
ee2c40de | 2568 | * @mc: The multicount value |
6fb914d7 | 2569 | * @dir_in: True if direction is in. |
5b7d70c6 BD |
2570 | * |
2571 | * Configure the maximum packet size for the given endpoint, updating | |
2572 | * the hardware control registers to reflect this. | |
2573 | */ | |
1f91b4cc | 2574 | static void dwc2_hsotg_set_ep_maxpacket(struct dwc2_hsotg *hsotg, |
ee2c40de VM |
2575 | unsigned int ep, unsigned int mps, |
2576 | unsigned int mc, unsigned int dir_in) | |
5b7d70c6 | 2577 | { |
1f91b4cc | 2578 | struct dwc2_hsotg_ep *hs_ep; |
5b7d70c6 BD |
2579 | u32 reg; |
2580 | ||
c6f5c050 MYK |
2581 | hs_ep = index_to_ep(hsotg, ep, dir_in); |
2582 | if (!hs_ep) | |
2583 | return; | |
2584 | ||
5b7d70c6 | 2585 | if (ep == 0) { |
ee2c40de VM |
2586 | u32 mps_bytes = mps; |
2587 | ||
5b7d70c6 | 2588 | /* EP0 is a special case */ |
ee2c40de VM |
2589 | mps = dwc2_hsotg_ep0_mps(mps_bytes); |
2590 | if (mps > 3) | |
5b7d70c6 | 2591 | goto bad_mps; |
ee2c40de | 2592 | hs_ep->ep.maxpacket = mps_bytes; |
4fca54aa | 2593 | hs_ep->mc = 1; |
5b7d70c6 | 2594 | } else { |
ee2c40de | 2595 | if (mps > 1024) |
5b7d70c6 | 2596 | goto bad_mps; |
ee2c40de VM |
2597 | hs_ep->mc = mc; |
2598 | if (mc > 3) | |
4fca54aa | 2599 | goto bad_mps; |
ee2c40de | 2600 | hs_ep->ep.maxpacket = mps; |
5b7d70c6 BD |
2601 | } |
2602 | ||
c6f5c050 | 2603 | if (dir_in) { |
f25c42b8 | 2604 | reg = dwc2_readl(hsotg, DIEPCTL(ep)); |
c6f5c050 | 2605 | reg &= ~DXEPCTL_MPS_MASK; |
ee2c40de | 2606 | reg |= mps; |
f25c42b8 | 2607 | dwc2_writel(hsotg, reg, DIEPCTL(ep)); |
c6f5c050 | 2608 | } else { |
f25c42b8 | 2609 | reg = dwc2_readl(hsotg, DOEPCTL(ep)); |
47a1685f | 2610 | reg &= ~DXEPCTL_MPS_MASK; |
ee2c40de | 2611 | reg |= mps; |
f25c42b8 | 2612 | dwc2_writel(hsotg, reg, DOEPCTL(ep)); |
659ad60c | 2613 | } |
5b7d70c6 BD |
2614 | |
2615 | return; | |
2616 | ||
2617 | bad_mps: | |
2618 | dev_err(hsotg->dev, "ep%d: bad mps of %d\n", ep, mps); | |
2619 | } | |
2620 | ||
9c39ddc6 | 2621 | /** |
1f91b4cc | 2622 | * dwc2_hsotg_txfifo_flush - flush Tx FIFO |
9c39ddc6 AT |
2623 | * @hsotg: The driver state |
2624 | * @idx: The index for the endpoint (0..15) | |
2625 | */ | |
1f91b4cc | 2626 | static void dwc2_hsotg_txfifo_flush(struct dwc2_hsotg *hsotg, unsigned int idx) |
9c39ddc6 | 2627 | { |
f25c42b8 GS |
2628 | dwc2_writel(hsotg, GRSTCTL_TXFNUM(idx) | GRSTCTL_TXFFLSH, |
2629 | GRSTCTL); | |
9c39ddc6 AT |
2630 | |
2631 | /* wait until the fifo is flushed */ | |
79d6b8c5 SA |
2632 | if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL, GRSTCTL_TXFFLSH, 100)) |
2633 | dev_warn(hsotg->dev, "%s: timeout flushing fifo GRSTCTL_TXFFLSH\n", | |
2634 | __func__); | |
9c39ddc6 | 2635 | } |
5b7d70c6 BD |
2636 | |
2637 | /** | |
1f91b4cc | 2638 | * dwc2_hsotg_trytx - check to see if anything needs transmitting |
5b7d70c6 BD |
2639 | * @hsotg: The driver state |
2640 | * @hs_ep: The driver endpoint to check. | |
2641 | * | |
2642 | * Check to see if there is a request that has data to send, and if so | |
2643 | * make an attempt to write data into the FIFO. | |
2644 | */ | |
1f91b4cc | 2645 | static int dwc2_hsotg_trytx(struct dwc2_hsotg *hsotg, |
9da51974 | 2646 | struct dwc2_hsotg_ep *hs_ep) |
5b7d70c6 | 2647 | { |
1f91b4cc | 2648 | struct dwc2_hsotg_req *hs_req = hs_ep->req; |
5b7d70c6 | 2649 | |
afcf4169 RB |
2650 | if (!hs_ep->dir_in || !hs_req) { |
2651 | /** | |
2652 | * if request is not enqueued, we disable interrupts | |
2653 | * for endpoints, excepting ep0 | |
2654 | */ | |
2655 | if (hs_ep->index != 0) | |
1f91b4cc | 2656 | dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, |
9da51974 | 2657 | hs_ep->dir_in, 0); |
5b7d70c6 | 2658 | return 0; |
afcf4169 | 2659 | } |
5b7d70c6 BD |
2660 | |
2661 | if (hs_req->req.actual < hs_req->req.length) { | |
2662 | dev_dbg(hsotg->dev, "trying to write more for ep%d\n", | |
2663 | hs_ep->index); | |
1f91b4cc | 2664 | return dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req); |
5b7d70c6 BD |
2665 | } |
2666 | ||
2667 | return 0; | |
2668 | } | |
2669 | ||
2670 | /** | |
1f91b4cc | 2671 | * dwc2_hsotg_complete_in - complete IN transfer |
5b7d70c6 BD |
2672 | * @hsotg: The device state. |
2673 | * @hs_ep: The endpoint that has just completed. | |
2674 | * | |
2675 | * An IN transfer has been completed, update the transfer's state and then | |
2676 | * call the relevant completion routines. | |
2677 | */ | |
1f91b4cc | 2678 | static void dwc2_hsotg_complete_in(struct dwc2_hsotg *hsotg, |
9da51974 | 2679 | struct dwc2_hsotg_ep *hs_ep) |
5b7d70c6 | 2680 | { |
1f91b4cc | 2681 | struct dwc2_hsotg_req *hs_req = hs_ep->req; |
f25c42b8 | 2682 | u32 epsize = dwc2_readl(hsotg, DIEPTSIZ(hs_ep->index)); |
5b7d70c6 BD |
2683 | int size_left, size_done; |
2684 | ||
2685 | if (!hs_req) { | |
2686 | dev_dbg(hsotg->dev, "XferCompl but no req\n"); | |
2687 | return; | |
2688 | } | |
2689 | ||
d3ca0259 | 2690 | /* Finish ZLP handling for IN EP0 transactions */ |
fe0b94ab MYK |
2691 | if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_IN) { |
2692 | dev_dbg(hsotg->dev, "zlp packet sent\n"); | |
c3b22fe2 RK |
2693 | |
2694 | /* | |
2695 | * While send zlp for DWC2_EP0_STATUS_IN EP direction was | |
2696 | * changed to IN. Change back to complete OUT transfer request | |
2697 | */ | |
2698 | hs_ep->dir_in = 0; | |
2699 | ||
1f91b4cc | 2700 | dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0); |
9e14d0a5 GH |
2701 | if (hsotg->test_mode) { |
2702 | int ret; | |
2703 | ||
1f91b4cc | 2704 | ret = dwc2_hsotg_set_test_mode(hsotg, hsotg->test_mode); |
9e14d0a5 GH |
2705 | if (ret < 0) { |
2706 | dev_dbg(hsotg->dev, "Invalid Test #%d\n", | |
9da51974 | 2707 | hsotg->test_mode); |
1f91b4cc | 2708 | dwc2_hsotg_stall_ep0(hsotg); |
9e14d0a5 GH |
2709 | return; |
2710 | } | |
2711 | } | |
1f91b4cc | 2712 | dwc2_hsotg_enqueue_setup(hsotg); |
d3ca0259 LM |
2713 | return; |
2714 | } | |
2715 | ||
8b9bc460 LM |
2716 | /* |
2717 | * Calculate the size of the transfer by checking how much is left | |
5b7d70c6 BD |
2718 | * in the endpoint size register and then working it out from |
2719 | * the amount we loaded for the transfer. | |
2720 | * | |
2721 | * We do this even for DMA, as the transfer may have incremented | |
2722 | * past the end of the buffer (DMA transfers are always 32bit | |
2723 | * aligned). | |
2724 | */ | |
aa3e8bc8 VA |
2725 | if (using_desc_dma(hsotg)) { |
2726 | size_left = dwc2_gadget_get_xfersize_ddma(hs_ep); | |
2727 | if (size_left < 0) | |
2728 | dev_err(hsotg->dev, "error parsing DDMA results %d\n", | |
2729 | size_left); | |
2730 | } else { | |
2731 | size_left = DXEPTSIZ_XFERSIZE_GET(epsize); | |
2732 | } | |
5b7d70c6 BD |
2733 | |
2734 | size_done = hs_ep->size_loaded - size_left; | |
2735 | size_done += hs_ep->last_load; | |
2736 | ||
2737 | if (hs_req->req.actual != size_done) | |
2738 | dev_dbg(hsotg->dev, "%s: adjusting size done %d => %d\n", | |
2739 | __func__, hs_req->req.actual, size_done); | |
2740 | ||
2741 | hs_req->req.actual = size_done; | |
d3ca0259 LM |
2742 | dev_dbg(hsotg->dev, "req->length:%d req->actual:%d req->zero:%d\n", |
2743 | hs_req->req.length, hs_req->req.actual, hs_req->req.zero); | |
2744 | ||
5b7d70c6 BD |
2745 | if (!size_left && hs_req->req.actual < hs_req->req.length) { |
2746 | dev_dbg(hsotg->dev, "%s trying more for req...\n", __func__); | |
1f91b4cc | 2747 | dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true); |
fe0b94ab MYK |
2748 | return; |
2749 | } | |
2750 | ||
f71b5e25 | 2751 | /* Zlp for all endpoints, for ep0 only in DATA IN stage */ |
8a20fa45 | 2752 | if (hs_ep->send_zlp) { |
1f91b4cc | 2753 | dwc2_hsotg_program_zlp(hsotg, hs_ep); |
8a20fa45 | 2754 | hs_ep->send_zlp = 0; |
f71b5e25 MYK |
2755 | /* transfer will be completed on next complete interrupt */ |
2756 | return; | |
2757 | } | |
2758 | ||
fe0b94ab MYK |
2759 | if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_DATA_IN) { |
2760 | /* Move to STATUS OUT */ | |
1f91b4cc | 2761 | dwc2_hsotg_ep0_zlp(hsotg, false); |
fe0b94ab MYK |
2762 | return; |
2763 | } | |
2764 | ||
1f91b4cc | 2765 | dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0); |
5b7d70c6 BD |
2766 | } |
2767 | ||
32601588 VM |
2768 | /** |
2769 | * dwc2_gadget_read_ep_interrupts - reads interrupts for given ep | |
2770 | * @hsotg: The device state. | |
2771 | * @idx: Index of ep. | |
2772 | * @dir_in: Endpoint direction 1-in 0-out. | |
2773 | * | |
2774 | * Reads for endpoint with given index and direction, by masking | |
2775 | * epint_reg with coresponding mask. | |
2776 | */ | |
2777 | static u32 dwc2_gadget_read_ep_interrupts(struct dwc2_hsotg *hsotg, | |
2778 | unsigned int idx, int dir_in) | |
2779 | { | |
2780 | u32 epmsk_reg = dir_in ? DIEPMSK : DOEPMSK; | |
2781 | u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx); | |
2782 | u32 ints; | |
2783 | u32 mask; | |
2784 | u32 diepempmsk; | |
2785 | ||
f25c42b8 GS |
2786 | mask = dwc2_readl(hsotg, epmsk_reg); |
2787 | diepempmsk = dwc2_readl(hsotg, DIEPEMPMSK); | |
32601588 VM |
2788 | mask |= ((diepempmsk >> idx) & 0x1) ? DIEPMSK_TXFIFOEMPTY : 0; |
2789 | mask |= DXEPINT_SETUP_RCVD; | |
2790 | ||
f25c42b8 | 2791 | ints = dwc2_readl(hsotg, epint_reg); |
32601588 VM |
2792 | ints &= mask; |
2793 | return ints; | |
2794 | } | |
2795 | ||
bd9971f0 VM |
2796 | /** |
2797 | * dwc2_gadget_handle_ep_disabled - handle DXEPINT_EPDISBLD | |
2798 | * @hs_ep: The endpoint on which interrupt is asserted. | |
2799 | * | |
2800 | * This interrupt indicates that the endpoint has been disabled per the | |
2801 | * application's request. | |
2802 | * | |
2803 | * For IN endpoints flushes txfifo, in case of BULK clears DCTL_CGNPINNAK, | |
2804 | * in case of ISOC completes current request. | |
2805 | * | |
2806 | * For ISOC-OUT endpoints completes expired requests. If there is remaining | |
2807 | * request starts it. | |
2808 | */ | |
2809 | static void dwc2_gadget_handle_ep_disabled(struct dwc2_hsotg_ep *hs_ep) | |
2810 | { | |
2811 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
2812 | struct dwc2_hsotg_req *hs_req; | |
2813 | unsigned char idx = hs_ep->index; | |
2814 | int dir_in = hs_ep->dir_in; | |
2815 | u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx); | |
f25c42b8 | 2816 | int dctl = dwc2_readl(hsotg, DCTL); |
bd9971f0 VM |
2817 | |
2818 | dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__); | |
2819 | ||
2820 | if (dir_in) { | |
f25c42b8 | 2821 | int epctl = dwc2_readl(hsotg, epctl_reg); |
bd9971f0 VM |
2822 | |
2823 | dwc2_hsotg_txfifo_flush(hsotg, hs_ep->fifo_index); | |
2824 | ||
2825 | if (hs_ep->isochronous) { | |
2826 | dwc2_hsotg_complete_in(hsotg, hs_ep); | |
2827 | return; | |
2828 | } | |
2829 | ||
2830 | if ((epctl & DXEPCTL_STALL) && (epctl & DXEPCTL_EPTYPE_BULK)) { | |
f25c42b8 | 2831 | int dctl = dwc2_readl(hsotg, DCTL); |
bd9971f0 VM |
2832 | |
2833 | dctl |= DCTL_CGNPINNAK; | |
f25c42b8 | 2834 | dwc2_writel(hsotg, dctl, DCTL); |
bd9971f0 VM |
2835 | } |
2836 | return; | |
2837 | } | |
2838 | ||
2839 | if (dctl & DCTL_GOUTNAKSTS) { | |
2840 | dctl |= DCTL_CGOUTNAK; | |
f25c42b8 | 2841 | dwc2_writel(hsotg, dctl, DCTL); |
bd9971f0 VM |
2842 | } |
2843 | ||
2844 | if (!hs_ep->isochronous) | |
2845 | return; | |
2846 | ||
2847 | if (list_empty(&hs_ep->queue)) { | |
2848 | dev_dbg(hsotg->dev, "%s: complete_ep 0x%p, ep->queue empty!\n", | |
2849 | __func__, hs_ep); | |
2850 | return; | |
2851 | } | |
2852 | ||
2853 | do { | |
2854 | hs_req = get_ep_head(hs_ep); | |
2855 | if (hs_req) | |
2856 | dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, | |
2857 | -ENODATA); | |
2858 | dwc2_gadget_incr_frame_num(hs_ep); | |
c7c24e7a AP |
2859 | /* Update current frame number value. */ |
2860 | hsotg->frame_number = dwc2_hsotg_read_frameno(hsotg); | |
bd9971f0 VM |
2861 | } while (dwc2_gadget_target_frame_elapsed(hs_ep)); |
2862 | ||
2863 | dwc2_gadget_start_next_request(hs_ep); | |
2864 | } | |
2865 | ||
5321922c VM |
2866 | /** |
2867 | * dwc2_gadget_handle_out_token_ep_disabled - handle DXEPINT_OUTTKNEPDIS | |
6fb914d7 | 2868 | * @ep: The endpoint on which interrupt is asserted. |
5321922c VM |
2869 | * |
2870 | * This is starting point for ISOC-OUT transfer, synchronization done with | |
2871 | * first out token received from host while corresponding EP is disabled. | |
2872 | * | |
2873 | * Device does not know initial frame in which out token will come. For this | |
2874 | * HW generates OUTTKNEPDIS - out token is received while EP is disabled. Upon | |
2875 | * getting this interrupt SW starts calculation for next transfer frame. | |
2876 | */ | |
2877 | static void dwc2_gadget_handle_out_token_ep_disabled(struct dwc2_hsotg_ep *ep) | |
2878 | { | |
2879 | struct dwc2_hsotg *hsotg = ep->parent; | |
2880 | int dir_in = ep->dir_in; | |
2881 | u32 doepmsk; | |
2882 | ||
2883 | if (dir_in || !ep->isochronous) | |
2884 | return; | |
2885 | ||
540ccba0 VA |
2886 | if (using_desc_dma(hsotg)) { |
2887 | if (ep->target_frame == TARGET_FRAME_INITIAL) { | |
2888 | /* Start first ISO Out */ | |
4d4f1e79 | 2889 | ep->target_frame = hsotg->frame_number; |
540ccba0 VA |
2890 | dwc2_gadget_start_isoc_ddma(ep); |
2891 | } | |
2892 | return; | |
2893 | } | |
2894 | ||
5321922c VM |
2895 | if (ep->interval > 1 && |
2896 | ep->target_frame == TARGET_FRAME_INITIAL) { | |
5321922c VM |
2897 | u32 ctrl; |
2898 | ||
4d4f1e79 | 2899 | ep->target_frame = hsotg->frame_number; |
5321922c VM |
2900 | dwc2_gadget_incr_frame_num(ep); |
2901 | ||
f25c42b8 | 2902 | ctrl = dwc2_readl(hsotg, DOEPCTL(ep->index)); |
5321922c VM |
2903 | if (ep->target_frame & 0x1) |
2904 | ctrl |= DXEPCTL_SETODDFR; | |
2905 | else | |
2906 | ctrl |= DXEPCTL_SETEVENFR; | |
2907 | ||
f25c42b8 | 2908 | dwc2_writel(hsotg, ctrl, DOEPCTL(ep->index)); |
5321922c VM |
2909 | } |
2910 | ||
2911 | dwc2_gadget_start_next_request(ep); | |
f25c42b8 | 2912 | doepmsk = dwc2_readl(hsotg, DOEPMSK); |
5321922c | 2913 | doepmsk &= ~DOEPMSK_OUTTKNEPDISMSK; |
f25c42b8 | 2914 | dwc2_writel(hsotg, doepmsk, DOEPMSK); |
5321922c VM |
2915 | } |
2916 | ||
2917 | /** | |
38beaec6 JY |
2918 | * dwc2_gadget_handle_nak - handle NAK interrupt |
2919 | * @hs_ep: The endpoint on which interrupt is asserted. | |
2920 | * | |
2921 | * This is starting point for ISOC-IN transfer, synchronization done with | |
2922 | * first IN token received from host while corresponding EP is disabled. | |
2923 | * | |
2924 | * Device does not know when first one token will arrive from host. On first | |
2925 | * token arrival HW generates 2 interrupts: 'in token received while FIFO empty' | |
2926 | * and 'NAK'. NAK interrupt for ISOC-IN means that token has arrived and ZLP was | |
2927 | * sent in response to that as there was no data in FIFO. SW is basing on this | |
2928 | * interrupt to obtain frame in which token has come and then based on the | |
2929 | * interval calculates next frame for transfer. | |
2930 | */ | |
5321922c VM |
2931 | static void dwc2_gadget_handle_nak(struct dwc2_hsotg_ep *hs_ep) |
2932 | { | |
2933 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
2934 | int dir_in = hs_ep->dir_in; | |
2935 | ||
2936 | if (!dir_in || !hs_ep->isochronous) | |
2937 | return; | |
2938 | ||
2939 | if (hs_ep->target_frame == TARGET_FRAME_INITIAL) { | |
540ccba0 VA |
2940 | |
2941 | if (using_desc_dma(hsotg)) { | |
4d4f1e79 | 2942 | hs_ep->target_frame = hsotg->frame_number; |
729cac69 | 2943 | dwc2_gadget_incr_frame_num(hs_ep); |
48dac4e4 GT |
2944 | |
2945 | /* In service interval mode target_frame must | |
2946 | * be set to last (u)frame of the service interval. | |
2947 | */ | |
2948 | if (hsotg->params.service_interval) { | |
2949 | /* Set target_frame to the first (u)frame of | |
2950 | * the service interval | |
2951 | */ | |
2952 | hs_ep->target_frame &= ~hs_ep->interval + 1; | |
2953 | ||
2954 | /* Set target_frame to the last (u)frame of | |
2955 | * the service interval | |
2956 | */ | |
2957 | dwc2_gadget_incr_frame_num(hs_ep); | |
2958 | dwc2_gadget_dec_frame_num_by_one(hs_ep); | |
2959 | } | |
2960 | ||
540ccba0 VA |
2961 | dwc2_gadget_start_isoc_ddma(hs_ep); |
2962 | return; | |
2963 | } | |
2964 | ||
4d4f1e79 | 2965 | hs_ep->target_frame = hsotg->frame_number; |
5321922c | 2966 | if (hs_ep->interval > 1) { |
f25c42b8 | 2967 | u32 ctrl = dwc2_readl(hsotg, |
5321922c VM |
2968 | DIEPCTL(hs_ep->index)); |
2969 | if (hs_ep->target_frame & 0x1) | |
2970 | ctrl |= DXEPCTL_SETODDFR; | |
2971 | else | |
2972 | ctrl |= DXEPCTL_SETEVENFR; | |
2973 | ||
f25c42b8 | 2974 | dwc2_writel(hsotg, ctrl, DIEPCTL(hs_ep->index)); |
5321922c VM |
2975 | } |
2976 | ||
2977 | dwc2_hsotg_complete_request(hsotg, hs_ep, | |
2978 | get_ep_head(hs_ep), 0); | |
2979 | } | |
2980 | ||
729cac69 MH |
2981 | if (!using_desc_dma(hsotg)) |
2982 | dwc2_gadget_incr_frame_num(hs_ep); | |
5321922c VM |
2983 | } |
2984 | ||
5b7d70c6 | 2985 | /** |
1f91b4cc | 2986 | * dwc2_hsotg_epint - handle an in/out endpoint interrupt |
5b7d70c6 BD |
2987 | * @hsotg: The driver state |
2988 | * @idx: The index for the endpoint (0..15) | |
2989 | * @dir_in: Set if this is an IN endpoint | |
2990 | * | |
2991 | * Process and clear any interrupt pending for an individual endpoint | |
8b9bc460 | 2992 | */ |
1f91b4cc | 2993 | static void dwc2_hsotg_epint(struct dwc2_hsotg *hsotg, unsigned int idx, |
9da51974 | 2994 | int dir_in) |
5b7d70c6 | 2995 | { |
1f91b4cc | 2996 | struct dwc2_hsotg_ep *hs_ep = index_to_ep(hsotg, idx, dir_in); |
94cb8fd6 LM |
2997 | u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx); |
2998 | u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx); | |
2999 | u32 epsiz_reg = dir_in ? DIEPTSIZ(idx) : DOEPTSIZ(idx); | |
5b7d70c6 | 3000 | u32 ints; |
5b7d70c6 | 3001 | |
32601588 | 3002 | ints = dwc2_gadget_read_ep_interrupts(hsotg, idx, dir_in); |
5b7d70c6 | 3003 | |
a3395f0d | 3004 | /* Clear endpoint interrupts */ |
f25c42b8 | 3005 | dwc2_writel(hsotg, ints, epint_reg); |
a3395f0d | 3006 | |
c6f5c050 MYK |
3007 | if (!hs_ep) { |
3008 | dev_err(hsotg->dev, "%s:Interrupt for unconfigured ep%d(%s)\n", | |
9da51974 | 3009 | __func__, idx, dir_in ? "in" : "out"); |
c6f5c050 MYK |
3010 | return; |
3011 | } | |
3012 | ||
5b7d70c6 BD |
3013 | dev_dbg(hsotg->dev, "%s: ep%d(%s) DxEPINT=0x%08x\n", |
3014 | __func__, idx, dir_in ? "in" : "out", ints); | |
3015 | ||
b787d755 MYK |
3016 | /* Don't process XferCompl interrupt if it is a setup packet */ |
3017 | if (idx == 0 && (ints & (DXEPINT_SETUP | DXEPINT_SETUP_RCVD))) | |
3018 | ints &= ~DXEPINT_XFERCOMPL; | |
3019 | ||
f0afdb42 VA |
3020 | /* |
3021 | * Don't process XferCompl interrupt in DDMA if EP0 is still in SETUP | |
3022 | * stage and xfercomplete was generated without SETUP phase done | |
3023 | * interrupt. SW should parse received setup packet only after host's | |
3024 | * exit from setup phase of control transfer. | |
3025 | */ | |
3026 | if (using_desc_dma(hsotg) && idx == 0 && !hs_ep->dir_in && | |
3027 | hsotg->ep0_state == DWC2_EP0_SETUP && !(ints & DXEPINT_SETUP)) | |
3028 | ints &= ~DXEPINT_XFERCOMPL; | |
3029 | ||
837e9f00 | 3030 | if (ints & DXEPINT_XFERCOMPL) { |
5b7d70c6 | 3031 | dev_dbg(hsotg->dev, |
47a1685f | 3032 | "%s: XferCompl: DxEPCTL=0x%08x, DXEPTSIZ=%08x\n", |
f25c42b8 GS |
3033 | __func__, dwc2_readl(hsotg, epctl_reg), |
3034 | dwc2_readl(hsotg, epsiz_reg)); | |
5b7d70c6 | 3035 | |
540ccba0 VA |
3036 | /* In DDMA handle isochronous requests separately */ |
3037 | if (using_desc_dma(hsotg) && hs_ep->isochronous) { | |
729cac69 MH |
3038 | /* XferCompl set along with BNA */ |
3039 | if (!(ints & DXEPINT_BNAINTR)) | |
3040 | dwc2_gadget_complete_isoc_request_ddma(hs_ep); | |
540ccba0 VA |
3041 | } else if (dir_in) { |
3042 | /* | |
3043 | * We get OutDone from the FIFO, so we only | |
3044 | * need to look at completing IN requests here | |
3045 | * if operating slave mode | |
3046 | */ | |
837e9f00 VM |
3047 | if (hs_ep->isochronous && hs_ep->interval > 1) |
3048 | dwc2_gadget_incr_frame_num(hs_ep); | |
3049 | ||
1f91b4cc | 3050 | dwc2_hsotg_complete_in(hsotg, hs_ep); |
837e9f00 VM |
3051 | if (ints & DXEPINT_NAKINTRPT) |
3052 | ints &= ~DXEPINT_NAKINTRPT; | |
5b7d70c6 | 3053 | |
c9a64ea8 | 3054 | if (idx == 0 && !hs_ep->req) |
1f91b4cc | 3055 | dwc2_hsotg_enqueue_setup(hsotg); |
5b7d70c6 | 3056 | } else if (using_dma(hsotg)) { |
8b9bc460 LM |
3057 | /* |
3058 | * We're using DMA, we need to fire an OutDone here | |
3059 | * as we ignore the RXFIFO. | |
3060 | */ | |
837e9f00 VM |
3061 | if (hs_ep->isochronous && hs_ep->interval > 1) |
3062 | dwc2_gadget_incr_frame_num(hs_ep); | |
5b7d70c6 | 3063 | |
1f91b4cc | 3064 | dwc2_hsotg_handle_outdone(hsotg, idx); |
5b7d70c6 | 3065 | } |
5b7d70c6 BD |
3066 | } |
3067 | ||
bd9971f0 VM |
3068 | if (ints & DXEPINT_EPDISBLD) |
3069 | dwc2_gadget_handle_ep_disabled(hs_ep); | |
9c39ddc6 | 3070 | |
5321922c VM |
3071 | if (ints & DXEPINT_OUTTKNEPDIS) |
3072 | dwc2_gadget_handle_out_token_ep_disabled(hs_ep); | |
3073 | ||
3074 | if (ints & DXEPINT_NAKINTRPT) | |
3075 | dwc2_gadget_handle_nak(hs_ep); | |
3076 | ||
47a1685f | 3077 | if (ints & DXEPINT_AHBERR) |
5b7d70c6 | 3078 | dev_dbg(hsotg->dev, "%s: AHBErr\n", __func__); |
5b7d70c6 | 3079 | |
47a1685f | 3080 | if (ints & DXEPINT_SETUP) { /* Setup or Timeout */ |
5b7d70c6 BD |
3081 | dev_dbg(hsotg->dev, "%s: Setup/Timeout\n", __func__); |
3082 | ||
3083 | if (using_dma(hsotg) && idx == 0) { | |
8b9bc460 LM |
3084 | /* |
3085 | * this is the notification we've received a | |
5b7d70c6 BD |
3086 | * setup packet. In non-DMA mode we'd get this |
3087 | * from the RXFIFO, instead we need to process | |
8b9bc460 LM |
3088 | * the setup here. |
3089 | */ | |
5b7d70c6 BD |
3090 | |
3091 | if (dir_in) | |
3092 | WARN_ON_ONCE(1); | |
3093 | else | |
1f91b4cc | 3094 | dwc2_hsotg_handle_outdone(hsotg, 0); |
5b7d70c6 | 3095 | } |
5b7d70c6 BD |
3096 | } |
3097 | ||
ef750c71 | 3098 | if (ints & DXEPINT_STSPHSERCVD) { |
9d9a6b07 VA |
3099 | dev_dbg(hsotg->dev, "%s: StsPhseRcvd\n", __func__); |
3100 | ||
9e95a66c MH |
3101 | /* Safety check EP0 state when STSPHSERCVD asserted */ |
3102 | if (hsotg->ep0_state == DWC2_EP0_DATA_OUT) { | |
3103 | /* Move to STATUS IN for DDMA */ | |
b4c53b4a MH |
3104 | if (using_desc_dma(hsotg)) { |
3105 | if (!hsotg->delayed_status) | |
3106 | dwc2_hsotg_ep0_zlp(hsotg, true); | |
3107 | else | |
3108 | /* In case of 3 stage Control Write with delayed | |
3109 | * status, when Status IN transfer started | |
3110 | * before STSPHSERCVD asserted, NAKSTS bit not | |
3111 | * cleared by CNAK in dwc2_hsotg_start_req() | |
3112 | * function. Clear now NAKSTS to allow complete | |
3113 | * transfer. | |
3114 | */ | |
3115 | dwc2_set_bit(hsotg, DIEPCTL(0), | |
3116 | DXEPCTL_CNAK); | |
3117 | } | |
9e95a66c MH |
3118 | } |
3119 | ||
ef750c71 VA |
3120 | } |
3121 | ||
47a1685f | 3122 | if (ints & DXEPINT_BACK2BACKSETUP) |
5b7d70c6 | 3123 | dev_dbg(hsotg->dev, "%s: B2BSetup/INEPNakEff\n", __func__); |
5b7d70c6 | 3124 | |
540ccba0 VA |
3125 | if (ints & DXEPINT_BNAINTR) { |
3126 | dev_dbg(hsotg->dev, "%s: BNA interrupt\n", __func__); | |
540ccba0 | 3127 | if (hs_ep->isochronous) |
729cac69 | 3128 | dwc2_gadget_handle_isoc_bna(hs_ep); |
540ccba0 VA |
3129 | } |
3130 | ||
1479e841 | 3131 | if (dir_in && !hs_ep->isochronous) { |
8b9bc460 | 3132 | /* not sure if this is important, but we'll clear it anyway */ |
26ddef5d | 3133 | if (ints & DXEPINT_INTKNTXFEMP) { |
5b7d70c6 BD |
3134 | dev_dbg(hsotg->dev, "%s: ep%d: INTknTXFEmpMsk\n", |
3135 | __func__, idx); | |
5b7d70c6 BD |
3136 | } |
3137 | ||
3138 | /* this probably means something bad is happening */ | |
26ddef5d | 3139 | if (ints & DXEPINT_INTKNEPMIS) { |
5b7d70c6 BD |
3140 | dev_warn(hsotg->dev, "%s: ep%d: INTknEP\n", |
3141 | __func__, idx); | |
5b7d70c6 | 3142 | } |
10aebc77 BD |
3143 | |
3144 | /* FIFO has space or is empty (see GAHBCFG) */ | |
3145 | if (hsotg->dedicated_fifos && | |
26ddef5d | 3146 | ints & DXEPINT_TXFEMP) { |
10aebc77 BD |
3147 | dev_dbg(hsotg->dev, "%s: ep%d: TxFIFOEmpty\n", |
3148 | __func__, idx); | |
70fa030f | 3149 | if (!using_dma(hsotg)) |
1f91b4cc | 3150 | dwc2_hsotg_trytx(hsotg, hs_ep); |
10aebc77 | 3151 | } |
5b7d70c6 | 3152 | } |
5b7d70c6 BD |
3153 | } |
3154 | ||
3155 | /** | |
1f91b4cc | 3156 | * dwc2_hsotg_irq_enumdone - Handle EnumDone interrupt (enumeration done) |
5b7d70c6 BD |
3157 | * @hsotg: The device state. |
3158 | * | |
3159 | * Handle updating the device settings after the enumeration phase has | |
3160 | * been completed. | |
8b9bc460 | 3161 | */ |
1f91b4cc | 3162 | static void dwc2_hsotg_irq_enumdone(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 3163 | { |
f25c42b8 | 3164 | u32 dsts = dwc2_readl(hsotg, DSTS); |
9b2667f1 | 3165 | int ep0_mps = 0, ep_mps = 8; |
5b7d70c6 | 3166 | |
8b9bc460 LM |
3167 | /* |
3168 | * This should signal the finish of the enumeration phase | |
5b7d70c6 | 3169 | * of the USB handshaking, so we should now know what rate |
8b9bc460 LM |
3170 | * we connected at. |
3171 | */ | |
5b7d70c6 BD |
3172 | |
3173 | dev_dbg(hsotg->dev, "EnumDone (DSTS=0x%08x)\n", dsts); | |
3174 | ||
8b9bc460 LM |
3175 | /* |
3176 | * note, since we're limited by the size of transfer on EP0, and | |
5b7d70c6 | 3177 | * it seems IN transfers must be a even number of packets we do |
8b9bc460 LM |
3178 | * not advertise a 64byte MPS on EP0. |
3179 | */ | |
5b7d70c6 BD |
3180 | |
3181 | /* catch both EnumSpd_FS and EnumSpd_FS48 */ | |
6d76c92c | 3182 | switch ((dsts & DSTS_ENUMSPD_MASK) >> DSTS_ENUMSPD_SHIFT) { |
47a1685f DN |
3183 | case DSTS_ENUMSPD_FS: |
3184 | case DSTS_ENUMSPD_FS48: | |
5b7d70c6 | 3185 | hsotg->gadget.speed = USB_SPEED_FULL; |
5b7d70c6 | 3186 | ep0_mps = EP0_MPS_LIMIT; |
295538ff | 3187 | ep_mps = 1023; |
5b7d70c6 BD |
3188 | break; |
3189 | ||
47a1685f | 3190 | case DSTS_ENUMSPD_HS: |
5b7d70c6 | 3191 | hsotg->gadget.speed = USB_SPEED_HIGH; |
5b7d70c6 | 3192 | ep0_mps = EP0_MPS_LIMIT; |
295538ff | 3193 | ep_mps = 1024; |
5b7d70c6 BD |
3194 | break; |
3195 | ||
47a1685f | 3196 | case DSTS_ENUMSPD_LS: |
5b7d70c6 | 3197 | hsotg->gadget.speed = USB_SPEED_LOW; |
552d940f VM |
3198 | ep0_mps = 8; |
3199 | ep_mps = 8; | |
8b9bc460 LM |
3200 | /* |
3201 | * note, we don't actually support LS in this driver at the | |
5b7d70c6 BD |
3202 | * moment, and the documentation seems to imply that it isn't |
3203 | * supported by the PHYs on some of the devices. | |
3204 | */ | |
3205 | break; | |
3206 | } | |
e538dfda MN |
3207 | dev_info(hsotg->dev, "new device is %s\n", |
3208 | usb_speed_string(hsotg->gadget.speed)); | |
5b7d70c6 | 3209 | |
8b9bc460 LM |
3210 | /* |
3211 | * we should now know the maximum packet size for an | |
3212 | * endpoint, so set the endpoints to a default value. | |
3213 | */ | |
5b7d70c6 BD |
3214 | |
3215 | if (ep0_mps) { | |
3216 | int i; | |
c6f5c050 | 3217 | /* Initialize ep0 for both in and out directions */ |
ee2c40de VM |
3218 | dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 0, 1); |
3219 | dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 0, 0); | |
c6f5c050 MYK |
3220 | for (i = 1; i < hsotg->num_of_eps; i++) { |
3221 | if (hsotg->eps_in[i]) | |
ee2c40de VM |
3222 | dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps, |
3223 | 0, 1); | |
c6f5c050 | 3224 | if (hsotg->eps_out[i]) |
ee2c40de VM |
3225 | dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps, |
3226 | 0, 0); | |
c6f5c050 | 3227 | } |
5b7d70c6 BD |
3228 | } |
3229 | ||
3230 | /* ensure after enumeration our EP0 is active */ | |
3231 | ||
1f91b4cc | 3232 | dwc2_hsotg_enqueue_setup(hsotg); |
5b7d70c6 BD |
3233 | |
3234 | dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n", | |
f25c42b8 GS |
3235 | dwc2_readl(hsotg, DIEPCTL0), |
3236 | dwc2_readl(hsotg, DOEPCTL0)); | |
5b7d70c6 BD |
3237 | } |
3238 | ||
3239 | /** | |
3240 | * kill_all_requests - remove all requests from the endpoint's queue | |
3241 | * @hsotg: The device state. | |
3242 | * @ep: The endpoint the requests may be on. | |
3243 | * @result: The result code to use. | |
5b7d70c6 BD |
3244 | * |
3245 | * Go through the requests on the given endpoint and mark them | |
3246 | * completed with the given result code. | |
3247 | */ | |
941fcce4 | 3248 | static void kill_all_requests(struct dwc2_hsotg *hsotg, |
1f91b4cc | 3249 | struct dwc2_hsotg_ep *ep, |
6b448af4 | 3250 | int result) |
5b7d70c6 | 3251 | { |
9da51974 | 3252 | unsigned int size; |
5b7d70c6 | 3253 | |
6b448af4 | 3254 | ep->req = NULL; |
5b7d70c6 | 3255 | |
37bea42f JK |
3256 | while (!list_empty(&ep->queue)) { |
3257 | struct dwc2_hsotg_req *req = get_ep_head(ep); | |
3258 | ||
3259 | dwc2_hsotg_complete_request(hsotg, ep, req, result); | |
3260 | } | |
6b448af4 | 3261 | |
b203d0a2 RB |
3262 | if (!hsotg->dedicated_fifos) |
3263 | return; | |
f25c42b8 | 3264 | size = (dwc2_readl(hsotg, DTXFSTS(ep->fifo_index)) & 0xffff) * 4; |
b203d0a2 | 3265 | if (size < ep->fifo_size) |
1f91b4cc | 3266 | dwc2_hsotg_txfifo_flush(hsotg, ep->fifo_index); |
5b7d70c6 BD |
3267 | } |
3268 | ||
5b7d70c6 | 3269 | /** |
1f91b4cc | 3270 | * dwc2_hsotg_disconnect - disconnect service |
5b7d70c6 BD |
3271 | * @hsotg: The device state. |
3272 | * | |
5e891342 LM |
3273 | * The device has been disconnected. Remove all current |
3274 | * transactions and signal the gadget driver that this | |
3275 | * has happened. | |
8b9bc460 | 3276 | */ |
1f91b4cc | 3277 | void dwc2_hsotg_disconnect(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 3278 | { |
9da51974 | 3279 | unsigned int ep; |
5b7d70c6 | 3280 | |
4ace06e8 MS |
3281 | if (!hsotg->connected) |
3282 | return; | |
3283 | ||
3284 | hsotg->connected = 0; | |
9e14d0a5 | 3285 | hsotg->test_mode = 0; |
c6f5c050 | 3286 | |
dccf1bad | 3287 | /* all endpoints should be shutdown */ |
c6f5c050 MYK |
3288 | for (ep = 0; ep < hsotg->num_of_eps; ep++) { |
3289 | if (hsotg->eps_in[ep]) | |
4fe4f9fe MH |
3290 | kill_all_requests(hsotg, hsotg->eps_in[ep], |
3291 | -ESHUTDOWN); | |
c6f5c050 | 3292 | if (hsotg->eps_out[ep]) |
4fe4f9fe MH |
3293 | kill_all_requests(hsotg, hsotg->eps_out[ep], |
3294 | -ESHUTDOWN); | |
c6f5c050 | 3295 | } |
5b7d70c6 BD |
3296 | |
3297 | call_gadget(hsotg, disconnect); | |
065d3931 | 3298 | hsotg->lx_state = DWC2_L3; |
ce2b21a4 JS |
3299 | |
3300 | usb_gadget_set_state(&hsotg->gadget, USB_STATE_NOTATTACHED); | |
5b7d70c6 BD |
3301 | } |
3302 | ||
3303 | /** | |
1f91b4cc | 3304 | * dwc2_hsotg_irq_fifoempty - TX FIFO empty interrupt handler |
5b7d70c6 BD |
3305 | * @hsotg: The device state: |
3306 | * @periodic: True if this is a periodic FIFO interrupt | |
3307 | */ | |
1f91b4cc | 3308 | static void dwc2_hsotg_irq_fifoempty(struct dwc2_hsotg *hsotg, bool periodic) |
5b7d70c6 | 3309 | { |
1f91b4cc | 3310 | struct dwc2_hsotg_ep *ep; |
5b7d70c6 BD |
3311 | int epno, ret; |
3312 | ||
3313 | /* look through for any more data to transmit */ | |
b3f489b2 | 3314 | for (epno = 0; epno < hsotg->num_of_eps; epno++) { |
c6f5c050 MYK |
3315 | ep = index_to_ep(hsotg, epno, 1); |
3316 | ||
3317 | if (!ep) | |
3318 | continue; | |
5b7d70c6 BD |
3319 | |
3320 | if (!ep->dir_in) | |
3321 | continue; | |
3322 | ||
3323 | if ((periodic && !ep->periodic) || | |
3324 | (!periodic && ep->periodic)) | |
3325 | continue; | |
3326 | ||
1f91b4cc | 3327 | ret = dwc2_hsotg_trytx(hsotg, ep); |
5b7d70c6 BD |
3328 | if (ret < 0) |
3329 | break; | |
3330 | } | |
3331 | } | |
3332 | ||
5b7d70c6 | 3333 | /* IRQ flags which will trigger a retry around the IRQ loop */ |
47a1685f DN |
3334 | #define IRQ_RETRY_MASK (GINTSTS_NPTXFEMP | \ |
3335 | GINTSTS_PTXFEMP | \ | |
3336 | GINTSTS_RXFLVL) | |
5b7d70c6 | 3337 | |
4fe4f9fe | 3338 | static int dwc2_hsotg_ep_disable(struct usb_ep *ep); |
8b9bc460 | 3339 | /** |
1f91b4cc | 3340 | * dwc2_hsotg_core_init - issue softreset to the core |
8b9bc460 | 3341 | * @hsotg: The device state |
6fb914d7 | 3342 | * @is_usb_reset: Usb resetting flag |
8b9bc460 LM |
3343 | * |
3344 | * Issue a soft reset to the core, and await the core finishing it. | |
3345 | */ | |
1f91b4cc | 3346 | void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg, |
9da51974 | 3347 | bool is_usb_reset) |
308d734e | 3348 | { |
1ee6903b | 3349 | u32 intmsk; |
643cc4de | 3350 | u32 val; |
ecd9a7ad | 3351 | u32 usbcfg; |
79c3b5bb | 3352 | u32 dcfg = 0; |
dccf1bad | 3353 | int ep; |
643cc4de | 3354 | |
5390d438 MYK |
3355 | /* Kill any ep0 requests as controller will be reinitialized */ |
3356 | kill_all_requests(hsotg, hsotg->eps_out[0], -ECONNRESET); | |
3357 | ||
dccf1bad | 3358 | if (!is_usb_reset) { |
6e6360b6 | 3359 | if (dwc2_core_reset(hsotg, true)) |
86de4895 | 3360 | return; |
dccf1bad MH |
3361 | } else { |
3362 | /* all endpoints should be shutdown */ | |
3363 | for (ep = 1; ep < hsotg->num_of_eps; ep++) { | |
3364 | if (hsotg->eps_in[ep]) | |
3365 | dwc2_hsotg_ep_disable(&hsotg->eps_in[ep]->ep); | |
3366 | if (hsotg->eps_out[ep]) | |
3367 | dwc2_hsotg_ep_disable(&hsotg->eps_out[ep]->ep); | |
3368 | } | |
3369 | } | |
308d734e LM |
3370 | |
3371 | /* | |
3372 | * we must now enable ep0 ready for host detection and then | |
3373 | * set configuration. | |
3374 | */ | |
3375 | ||
ecd9a7ad | 3376 | /* keep other bits untouched (so e.g. forced modes are not lost) */ |
f25c42b8 | 3377 | usbcfg = dwc2_readl(hsotg, GUSBCFG); |
1e868545 | 3378 | usbcfg &= ~GUSBCFG_TOUTCAL_MASK; |
707d80f0 | 3379 | usbcfg |= GUSBCFG_TOUTCAL(7); |
ecd9a7ad | 3380 | |
1e868545 JM |
3381 | /* remove the HNP/SRP and set the PHY */ |
3382 | usbcfg &= ~(GUSBCFG_SRPCAP | GUSBCFG_HNPCAP); | |
3383 | dwc2_writel(hsotg, usbcfg, GUSBCFG); | |
707d80f0 | 3384 | |
1e868545 | 3385 | dwc2_phy_init(hsotg, true); |
308d734e | 3386 | |
1f91b4cc | 3387 | dwc2_hsotg_init_fifo(hsotg); |
308d734e | 3388 | |
643cc4de | 3389 | if (!is_usb_reset) |
f25c42b8 | 3390 | dwc2_set_bit(hsotg, DCTL, DCTL_SFTDISCON); |
308d734e | 3391 | |
79c3b5bb | 3392 | dcfg |= DCFG_EPMISCNT(1); |
38e9002b VM |
3393 | |
3394 | switch (hsotg->params.speed) { | |
3395 | case DWC2_SPEED_PARAM_LOW: | |
3396 | dcfg |= DCFG_DEVSPD_LS; | |
3397 | break; | |
3398 | case DWC2_SPEED_PARAM_FULL: | |
79c3b5bb VA |
3399 | if (hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS) |
3400 | dcfg |= DCFG_DEVSPD_FS48; | |
3401 | else | |
3402 | dcfg |= DCFG_DEVSPD_FS; | |
38e9002b VM |
3403 | break; |
3404 | default: | |
79c3b5bb VA |
3405 | dcfg |= DCFG_DEVSPD_HS; |
3406 | } | |
38e9002b | 3407 | |
b43ebc96 GT |
3408 | if (hsotg->params.ipg_isoc_en) |
3409 | dcfg |= DCFG_IPG_ISOC_SUPPORDED; | |
3410 | ||
f25c42b8 | 3411 | dwc2_writel(hsotg, dcfg, DCFG); |
308d734e LM |
3412 | |
3413 | /* Clear any pending OTG interrupts */ | |
f25c42b8 | 3414 | dwc2_writel(hsotg, 0xffffffff, GOTGINT); |
308d734e LM |
3415 | |
3416 | /* Clear any pending interrupts */ | |
f25c42b8 | 3417 | dwc2_writel(hsotg, 0xffffffff, GINTSTS); |
1ee6903b | 3418 | intmsk = GINTSTS_ERLYSUSP | GINTSTS_SESSREQINT | |
47a1685f | 3419 | GINTSTS_GOUTNAKEFF | GINTSTS_GINNAKEFF | |
1ee6903b GH |
3420 | GINTSTS_USBRST | GINTSTS_RESETDET | |
3421 | GINTSTS_ENUMDONE | GINTSTS_OTGINT | | |
376f0401 SA |
3422 | GINTSTS_USBSUSP | GINTSTS_WKUPINT | |
3423 | GINTSTS_LPMTRANRCVD; | |
f4736701 VA |
3424 | |
3425 | if (!using_desc_dma(hsotg)) | |
3426 | intmsk |= GINTSTS_INCOMPL_SOIN | GINTSTS_INCOMPL_SOOUT; | |
1ee6903b | 3427 | |
95832c00 | 3428 | if (!hsotg->params.external_id_pin_ctl) |
1ee6903b GH |
3429 | intmsk |= GINTSTS_CONIDSTSCHNG; |
3430 | ||
f25c42b8 | 3431 | dwc2_writel(hsotg, intmsk, GINTMSK); |
308d734e | 3432 | |
a5c18f11 | 3433 | if (using_dma(hsotg)) { |
f25c42b8 | 3434 | dwc2_writel(hsotg, GAHBCFG_GLBL_INTR_EN | GAHBCFG_DMA_EN | |
d1ac8c80 | 3435 | hsotg->params.ahbcfg, |
f25c42b8 | 3436 | GAHBCFG); |
a5c18f11 VA |
3437 | |
3438 | /* Set DDMA mode support in the core if needed */ | |
3439 | if (using_desc_dma(hsotg)) | |
f25c42b8 | 3440 | dwc2_set_bit(hsotg, DCFG, DCFG_DESCDMA_EN); |
a5c18f11 VA |
3441 | |
3442 | } else { | |
f25c42b8 | 3443 | dwc2_writel(hsotg, ((hsotg->dedicated_fifos) ? |
95c8bc36 AS |
3444 | (GAHBCFG_NP_TXF_EMP_LVL | |
3445 | GAHBCFG_P_TXF_EMP_LVL) : 0) | | |
f25c42b8 | 3446 | GAHBCFG_GLBL_INTR_EN, GAHBCFG); |
a5c18f11 | 3447 | } |
308d734e LM |
3448 | |
3449 | /* | |
8acc8296 RB |
3450 | * If INTknTXFEmpMsk is enabled, it's important to disable ep interrupts |
3451 | * when we have no data to transfer. Otherwise we get being flooded by | |
3452 | * interrupts. | |
308d734e LM |
3453 | */ |
3454 | ||
f25c42b8 | 3455 | dwc2_writel(hsotg, ((hsotg->dedicated_fifos && !using_dma(hsotg)) ? |
6ff2e832 | 3456 | DIEPMSK_TXFIFOEMPTY | DIEPMSK_INTKNTXFEMPMSK : 0) | |
47a1685f | 3457 | DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK | |
837e9f00 | 3458 | DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK, |
f25c42b8 | 3459 | DIEPMSK); |
308d734e LM |
3460 | |
3461 | /* | |
3462 | * don't need XferCompl, we get that from RXFIFO in slave mode. In | |
9d9a6b07 | 3463 | * DMA mode we may need this and StsPhseRcvd. |
308d734e | 3464 | */ |
f25c42b8 | 3465 | dwc2_writel(hsotg, (using_dma(hsotg) ? (DIEPMSK_XFERCOMPLMSK | |
9d9a6b07 | 3466 | DOEPMSK_STSPHSERCVDMSK) : 0) | |
47a1685f | 3467 | DOEPMSK_EPDISBLDMSK | DOEPMSK_AHBERRMSK | |
9d9a6b07 | 3468 | DOEPMSK_SETUPMSK, |
f25c42b8 | 3469 | DOEPMSK); |
308d734e | 3470 | |
ec01f0b2 | 3471 | /* Enable BNA interrupt for DDMA */ |
37981e00 | 3472 | if (using_desc_dma(hsotg)) { |
f25c42b8 GS |
3473 | dwc2_set_bit(hsotg, DOEPMSK, DOEPMSK_BNAMSK); |
3474 | dwc2_set_bit(hsotg, DIEPMSK, DIEPMSK_BNAININTRMSK); | |
37981e00 | 3475 | } |
ec01f0b2 | 3476 | |
ca531bc2 GT |
3477 | /* Enable Service Interval mode if supported */ |
3478 | if (using_desc_dma(hsotg) && hsotg->params.service_interval) | |
3479 | dwc2_set_bit(hsotg, DCTL, DCTL_SERVICE_INTERVAL_SUPPORTED); | |
3480 | ||
f25c42b8 | 3481 | dwc2_writel(hsotg, 0, DAINTMSK); |
308d734e LM |
3482 | |
3483 | dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n", | |
f25c42b8 GS |
3484 | dwc2_readl(hsotg, DIEPCTL0), |
3485 | dwc2_readl(hsotg, DOEPCTL0)); | |
308d734e LM |
3486 | |
3487 | /* enable in and out endpoint interrupts */ | |
1f91b4cc | 3488 | dwc2_hsotg_en_gsint(hsotg, GINTSTS_OEPINT | GINTSTS_IEPINT); |
308d734e LM |
3489 | |
3490 | /* | |
3491 | * Enable the RXFIFO when in slave mode, as this is how we collect | |
3492 | * the data. In DMA mode, we get events from the FIFO but also | |
3493 | * things we cannot process, so do not use it. | |
3494 | */ | |
3495 | if (!using_dma(hsotg)) | |
1f91b4cc | 3496 | dwc2_hsotg_en_gsint(hsotg, GINTSTS_RXFLVL); |
308d734e LM |
3497 | |
3498 | /* Enable interrupts for EP0 in and out */ | |
1f91b4cc FB |
3499 | dwc2_hsotg_ctrl_epint(hsotg, 0, 0, 1); |
3500 | dwc2_hsotg_ctrl_epint(hsotg, 0, 1, 1); | |
308d734e | 3501 | |
643cc4de | 3502 | if (!is_usb_reset) { |
f25c42b8 | 3503 | dwc2_set_bit(hsotg, DCTL, DCTL_PWRONPRGDONE); |
643cc4de | 3504 | udelay(10); /* see openiboot */ |
f25c42b8 | 3505 | dwc2_clear_bit(hsotg, DCTL, DCTL_PWRONPRGDONE); |
643cc4de | 3506 | } |
308d734e | 3507 | |
f25c42b8 | 3508 | dev_dbg(hsotg->dev, "DCTL=0x%08x\n", dwc2_readl(hsotg, DCTL)); |
308d734e LM |
3509 | |
3510 | /* | |
94cb8fd6 | 3511 | * DxEPCTL_USBActEp says RO in manual, but seems to be set by |
308d734e LM |
3512 | * writing to the EPCTL register.. |
3513 | */ | |
3514 | ||
3515 | /* set to read 1 8byte packet */ | |
f25c42b8 GS |
3516 | dwc2_writel(hsotg, DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) | |
3517 | DXEPTSIZ_XFERSIZE(8), DOEPTSIZ0); | |
308d734e | 3518 | |
f25c42b8 | 3519 | dwc2_writel(hsotg, dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) | |
47a1685f DN |
3520 | DXEPCTL_CNAK | DXEPCTL_EPENA | |
3521 | DXEPCTL_USBACTEP, | |
f25c42b8 | 3522 | DOEPCTL0); |
308d734e LM |
3523 | |
3524 | /* enable, but don't activate EP0in */ | |
f25c42b8 GS |
3525 | dwc2_writel(hsotg, dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) | |
3526 | DXEPCTL_USBACTEP, DIEPCTL0); | |
308d734e | 3527 | |
308d734e | 3528 | /* clear global NAKs */ |
643cc4de GH |
3529 | val = DCTL_CGOUTNAK | DCTL_CGNPINNAK; |
3530 | if (!is_usb_reset) | |
3531 | val |= DCTL_SFTDISCON; | |
f25c42b8 | 3532 | dwc2_set_bit(hsotg, DCTL, val); |
308d734e | 3533 | |
21b03405 SA |
3534 | /* configure the core to support LPM */ |
3535 | dwc2_gadget_init_lpm(hsotg); | |
3536 | ||
15d9dbf8 GT |
3537 | /* program GREFCLK register if needed */ |
3538 | if (using_desc_dma(hsotg) && hsotg->params.service_interval) | |
3539 | dwc2_gadget_program_ref_clk(hsotg); | |
3540 | ||
308d734e LM |
3541 | /* must be at-least 3ms to allow bus to see disconnect */ |
3542 | mdelay(3); | |
3543 | ||
065d3931 | 3544 | hsotg->lx_state = DWC2_L0; |
755d7395 VM |
3545 | |
3546 | dwc2_hsotg_enqueue_setup(hsotg); | |
3547 | ||
3548 | dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n", | |
f25c42b8 GS |
3549 | dwc2_readl(hsotg, DIEPCTL0), |
3550 | dwc2_readl(hsotg, DOEPCTL0)); | |
ad38dc5d MS |
3551 | } |
3552 | ||
17f93402 | 3553 | void dwc2_hsotg_core_disconnect(struct dwc2_hsotg *hsotg) |
ad38dc5d MS |
3554 | { |
3555 | /* set the soft-disconnect bit */ | |
f25c42b8 | 3556 | dwc2_set_bit(hsotg, DCTL, DCTL_SFTDISCON); |
ad38dc5d | 3557 | } |
ac3c81f3 | 3558 | |
1f91b4cc | 3559 | void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg) |
ad38dc5d | 3560 | { |
308d734e | 3561 | /* remove the soft-disconnect and let's go */ |
f25c42b8 | 3562 | dwc2_clear_bit(hsotg, DCTL, DCTL_SFTDISCON); |
308d734e LM |
3563 | } |
3564 | ||
381fc8f8 VM |
3565 | /** |
3566 | * dwc2_gadget_handle_incomplete_isoc_in - handle incomplete ISO IN Interrupt. | |
3567 | * @hsotg: The device state: | |
3568 | * | |
3569 | * This interrupt indicates one of the following conditions occurred while | |
3570 | * transmitting an ISOC transaction. | |
3571 | * - Corrupted IN Token for ISOC EP. | |
3572 | * - Packet not complete in FIFO. | |
3573 | * | |
3574 | * The following actions will be taken: | |
3575 | * - Determine the EP | |
3576 | * - Disable EP; when 'Endpoint Disabled' interrupt is received Flush FIFO | |
3577 | */ | |
3578 | static void dwc2_gadget_handle_incomplete_isoc_in(struct dwc2_hsotg *hsotg) | |
3579 | { | |
3580 | struct dwc2_hsotg_ep *hs_ep; | |
3581 | u32 epctrl; | |
1b4977c7 | 3582 | u32 daintmsk; |
381fc8f8 VM |
3583 | u32 idx; |
3584 | ||
3585 | dev_dbg(hsotg->dev, "Incomplete isoc in interrupt received:\n"); | |
3586 | ||
f25c42b8 | 3587 | daintmsk = dwc2_readl(hsotg, DAINTMSK); |
1b4977c7 | 3588 | |
d5d5f079 | 3589 | for (idx = 1; idx < hsotg->num_of_eps; idx++) { |
381fc8f8 | 3590 | hs_ep = hsotg->eps_in[idx]; |
1b4977c7 | 3591 | /* Proceed only unmasked ISOC EPs */ |
89066b36 | 3592 | if ((BIT(idx) & ~daintmsk) || !hs_ep->isochronous) |
1b4977c7 RK |
3593 | continue; |
3594 | ||
f25c42b8 | 3595 | epctrl = dwc2_readl(hsotg, DIEPCTL(idx)); |
1b4977c7 | 3596 | if ((epctrl & DXEPCTL_EPENA) && |
381fc8f8 VM |
3597 | dwc2_gadget_target_frame_elapsed(hs_ep)) { |
3598 | epctrl |= DXEPCTL_SNAK; | |
3599 | epctrl |= DXEPCTL_EPDIS; | |
f25c42b8 | 3600 | dwc2_writel(hsotg, epctrl, DIEPCTL(idx)); |
381fc8f8 VM |
3601 | } |
3602 | } | |
3603 | ||
3604 | /* Clear interrupt */ | |
f25c42b8 | 3605 | dwc2_writel(hsotg, GINTSTS_INCOMPL_SOIN, GINTSTS); |
381fc8f8 VM |
3606 | } |
3607 | ||
3608 | /** | |
3609 | * dwc2_gadget_handle_incomplete_isoc_out - handle incomplete ISO OUT Interrupt | |
3610 | * @hsotg: The device state: | |
3611 | * | |
3612 | * This interrupt indicates one of the following conditions occurred while | |
3613 | * transmitting an ISOC transaction. | |
3614 | * - Corrupted OUT Token for ISOC EP. | |
3615 | * - Packet not complete in FIFO. | |
3616 | * | |
3617 | * The following actions will be taken: | |
3618 | * - Determine the EP | |
3619 | * - Set DCTL_SGOUTNAK and unmask GOUTNAKEFF if target frame elapsed. | |
3620 | */ | |
3621 | static void dwc2_gadget_handle_incomplete_isoc_out(struct dwc2_hsotg *hsotg) | |
3622 | { | |
3623 | u32 gintsts; | |
3624 | u32 gintmsk; | |
689efb26 | 3625 | u32 daintmsk; |
381fc8f8 VM |
3626 | u32 epctrl; |
3627 | struct dwc2_hsotg_ep *hs_ep; | |
3628 | int idx; | |
3629 | ||
3630 | dev_dbg(hsotg->dev, "%s: GINTSTS_INCOMPL_SOOUT\n", __func__); | |
3631 | ||
f25c42b8 | 3632 | daintmsk = dwc2_readl(hsotg, DAINTMSK); |
689efb26 RK |
3633 | daintmsk >>= DAINT_OUTEP_SHIFT; |
3634 | ||
d5d5f079 | 3635 | for (idx = 1; idx < hsotg->num_of_eps; idx++) { |
381fc8f8 | 3636 | hs_ep = hsotg->eps_out[idx]; |
689efb26 | 3637 | /* Proceed only unmasked ISOC EPs */ |
89066b36 | 3638 | if ((BIT(idx) & ~daintmsk) || !hs_ep->isochronous) |
689efb26 RK |
3639 | continue; |
3640 | ||
f25c42b8 | 3641 | epctrl = dwc2_readl(hsotg, DOEPCTL(idx)); |
689efb26 | 3642 | if ((epctrl & DXEPCTL_EPENA) && |
381fc8f8 VM |
3643 | dwc2_gadget_target_frame_elapsed(hs_ep)) { |
3644 | /* Unmask GOUTNAKEFF interrupt */ | |
f25c42b8 | 3645 | gintmsk = dwc2_readl(hsotg, GINTMSK); |
381fc8f8 | 3646 | gintmsk |= GINTSTS_GOUTNAKEFF; |
f25c42b8 | 3647 | dwc2_writel(hsotg, gintmsk, GINTMSK); |
381fc8f8 | 3648 | |
f25c42b8 | 3649 | gintsts = dwc2_readl(hsotg, GINTSTS); |
689efb26 | 3650 | if (!(gintsts & GINTSTS_GOUTNAKEFF)) { |
f25c42b8 | 3651 | dwc2_set_bit(hsotg, DCTL, DCTL_SGOUTNAK); |
689efb26 RK |
3652 | break; |
3653 | } | |
381fc8f8 VM |
3654 | } |
3655 | } | |
3656 | ||
3657 | /* Clear interrupt */ | |
f25c42b8 | 3658 | dwc2_writel(hsotg, GINTSTS_INCOMPL_SOOUT, GINTSTS); |
381fc8f8 VM |
3659 | } |
3660 | ||
5b7d70c6 | 3661 | /** |
1f91b4cc | 3662 | * dwc2_hsotg_irq - handle device interrupt |
5b7d70c6 BD |
3663 | * @irq: The IRQ number triggered |
3664 | * @pw: The pw value when registered the handler. | |
3665 | */ | |
1f91b4cc | 3666 | static irqreturn_t dwc2_hsotg_irq(int irq, void *pw) |
5b7d70c6 | 3667 | { |
941fcce4 | 3668 | struct dwc2_hsotg *hsotg = pw; |
5b7d70c6 BD |
3669 | int retry_count = 8; |
3670 | u32 gintsts; | |
3671 | u32 gintmsk; | |
3672 | ||
ee3de8d7 VM |
3673 | if (!dwc2_is_device_mode(hsotg)) |
3674 | return IRQ_NONE; | |
3675 | ||
5ad1d316 | 3676 | spin_lock(&hsotg->lock); |
5b7d70c6 | 3677 | irq_retry: |
f25c42b8 GS |
3678 | gintsts = dwc2_readl(hsotg, GINTSTS); |
3679 | gintmsk = dwc2_readl(hsotg, GINTMSK); | |
5b7d70c6 BD |
3680 | |
3681 | dev_dbg(hsotg->dev, "%s: %08x %08x (%08x) retry %d\n", | |
3682 | __func__, gintsts, gintsts & gintmsk, gintmsk, retry_count); | |
3683 | ||
3684 | gintsts &= gintmsk; | |
3685 | ||
8fc37b82 MYK |
3686 | if (gintsts & GINTSTS_RESETDET) { |
3687 | dev_dbg(hsotg->dev, "%s: USBRstDet\n", __func__); | |
3688 | ||
f25c42b8 | 3689 | dwc2_writel(hsotg, GINTSTS_RESETDET, GINTSTS); |
8fc37b82 MYK |
3690 | |
3691 | /* This event must be used only if controller is suspended */ | |
c9c394ab AP |
3692 | if (hsotg->in_ppd && hsotg->lx_state == DWC2_L2) |
3693 | dwc2_exit_partial_power_down(hsotg, 0, true); | |
3694 | ||
3695 | hsotg->lx_state = DWC2_L0; | |
8fc37b82 MYK |
3696 | } |
3697 | ||
3698 | if (gintsts & (GINTSTS_USBRST | GINTSTS_RESETDET)) { | |
f25c42b8 | 3699 | u32 usb_status = dwc2_readl(hsotg, GOTGCTL); |
8fc37b82 MYK |
3700 | u32 connected = hsotg->connected; |
3701 | ||
3702 | dev_dbg(hsotg->dev, "%s: USBRst\n", __func__); | |
3703 | dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n", | |
f25c42b8 | 3704 | dwc2_readl(hsotg, GNPTXSTS)); |
8fc37b82 | 3705 | |
f25c42b8 | 3706 | dwc2_writel(hsotg, GINTSTS_USBRST, GINTSTS); |
8fc37b82 MYK |
3707 | |
3708 | /* Report disconnection if it is not already done. */ | |
3709 | dwc2_hsotg_disconnect(hsotg); | |
3710 | ||
307bc11f | 3711 | /* Reset device address to zero */ |
f25c42b8 | 3712 | dwc2_clear_bit(hsotg, DCFG, DCFG_DEVADDR_MASK); |
307bc11f | 3713 | |
8fc37b82 MYK |
3714 | if (usb_status & GOTGCTL_BSESVLD && connected) |
3715 | dwc2_hsotg_core_init_disconnected(hsotg, true); | |
3716 | } | |
3717 | ||
47a1685f | 3718 | if (gintsts & GINTSTS_ENUMDONE) { |
f25c42b8 | 3719 | dwc2_writel(hsotg, GINTSTS_ENUMDONE, GINTSTS); |
a3395f0d | 3720 | |
1f91b4cc | 3721 | dwc2_hsotg_irq_enumdone(hsotg); |
5b7d70c6 BD |
3722 | } |
3723 | ||
47a1685f | 3724 | if (gintsts & (GINTSTS_OEPINT | GINTSTS_IEPINT)) { |
f25c42b8 GS |
3725 | u32 daint = dwc2_readl(hsotg, DAINT); |
3726 | u32 daintmsk = dwc2_readl(hsotg, DAINTMSK); | |
7e804650 | 3727 | u32 daint_out, daint_in; |
5b7d70c6 BD |
3728 | int ep; |
3729 | ||
7e804650 | 3730 | daint &= daintmsk; |
47a1685f DN |
3731 | daint_out = daint >> DAINT_OUTEP_SHIFT; |
3732 | daint_in = daint & ~(daint_out << DAINT_OUTEP_SHIFT); | |
7e804650 | 3733 | |
5b7d70c6 BD |
3734 | dev_dbg(hsotg->dev, "%s: daint=%08x\n", __func__, daint); |
3735 | ||
cec87f1d MYK |
3736 | for (ep = 0; ep < hsotg->num_of_eps && daint_out; |
3737 | ep++, daint_out >>= 1) { | |
5b7d70c6 | 3738 | if (daint_out & 1) |
1f91b4cc | 3739 | dwc2_hsotg_epint(hsotg, ep, 0); |
5b7d70c6 BD |
3740 | } |
3741 | ||
cec87f1d MYK |
3742 | for (ep = 0; ep < hsotg->num_of_eps && daint_in; |
3743 | ep++, daint_in >>= 1) { | |
5b7d70c6 | 3744 | if (daint_in & 1) |
1f91b4cc | 3745 | dwc2_hsotg_epint(hsotg, ep, 1); |
5b7d70c6 | 3746 | } |
5b7d70c6 BD |
3747 | } |
3748 | ||
5b7d70c6 BD |
3749 | /* check both FIFOs */ |
3750 | ||
47a1685f | 3751 | if (gintsts & GINTSTS_NPTXFEMP) { |
5b7d70c6 BD |
3752 | dev_dbg(hsotg->dev, "NPTxFEmp\n"); |
3753 | ||
8b9bc460 LM |
3754 | /* |
3755 | * Disable the interrupt to stop it happening again | |
5b7d70c6 | 3756 | * unless one of these endpoint routines decides that |
8b9bc460 LM |
3757 | * it needs re-enabling |
3758 | */ | |
5b7d70c6 | 3759 | |
1f91b4cc FB |
3760 | dwc2_hsotg_disable_gsint(hsotg, GINTSTS_NPTXFEMP); |
3761 | dwc2_hsotg_irq_fifoempty(hsotg, false); | |
5b7d70c6 BD |
3762 | } |
3763 | ||
47a1685f | 3764 | if (gintsts & GINTSTS_PTXFEMP) { |
5b7d70c6 BD |
3765 | dev_dbg(hsotg->dev, "PTxFEmp\n"); |
3766 | ||
94cb8fd6 | 3767 | /* See note in GINTSTS_NPTxFEmp */ |
5b7d70c6 | 3768 | |
1f91b4cc FB |
3769 | dwc2_hsotg_disable_gsint(hsotg, GINTSTS_PTXFEMP); |
3770 | dwc2_hsotg_irq_fifoempty(hsotg, true); | |
5b7d70c6 BD |
3771 | } |
3772 | ||
47a1685f | 3773 | if (gintsts & GINTSTS_RXFLVL) { |
8b9bc460 LM |
3774 | /* |
3775 | * note, since GINTSTS_RxFLvl doubles as FIFO-not-empty, | |
1f91b4cc | 3776 | * we need to retry dwc2_hsotg_handle_rx if this is still |
8b9bc460 LM |
3777 | * set. |
3778 | */ | |
5b7d70c6 | 3779 | |
1f91b4cc | 3780 | dwc2_hsotg_handle_rx(hsotg); |
5b7d70c6 BD |
3781 | } |
3782 | ||
47a1685f | 3783 | if (gintsts & GINTSTS_ERLYSUSP) { |
94cb8fd6 | 3784 | dev_dbg(hsotg->dev, "GINTSTS_ErlySusp\n"); |
f25c42b8 | 3785 | dwc2_writel(hsotg, GINTSTS_ERLYSUSP, GINTSTS); |
5b7d70c6 BD |
3786 | } |
3787 | ||
8b9bc460 LM |
3788 | /* |
3789 | * these next two seem to crop-up occasionally causing the core | |
5b7d70c6 | 3790 | * to shutdown the USB transfer, so try clearing them and logging |
8b9bc460 LM |
3791 | * the occurrence. |
3792 | */ | |
5b7d70c6 | 3793 | |
47a1685f | 3794 | if (gintsts & GINTSTS_GOUTNAKEFF) { |
837e9f00 VM |
3795 | u8 idx; |
3796 | u32 epctrl; | |
3797 | u32 gintmsk; | |
d8484552 | 3798 | u32 daintmsk; |
837e9f00 VM |
3799 | struct dwc2_hsotg_ep *hs_ep; |
3800 | ||
f25c42b8 | 3801 | daintmsk = dwc2_readl(hsotg, DAINTMSK); |
d8484552 | 3802 | daintmsk >>= DAINT_OUTEP_SHIFT; |
837e9f00 | 3803 | /* Mask this interrupt */ |
f25c42b8 | 3804 | gintmsk = dwc2_readl(hsotg, GINTMSK); |
837e9f00 | 3805 | gintmsk &= ~GINTSTS_GOUTNAKEFF; |
f25c42b8 | 3806 | dwc2_writel(hsotg, gintmsk, GINTMSK); |
837e9f00 VM |
3807 | |
3808 | dev_dbg(hsotg->dev, "GOUTNakEff triggered\n"); | |
d5d5f079 | 3809 | for (idx = 1; idx < hsotg->num_of_eps; idx++) { |
837e9f00 | 3810 | hs_ep = hsotg->eps_out[idx]; |
d8484552 | 3811 | /* Proceed only unmasked ISOC EPs */ |
6070636c | 3812 | if (BIT(idx) & ~daintmsk) |
d8484552 RK |
3813 | continue; |
3814 | ||
f25c42b8 | 3815 | epctrl = dwc2_readl(hsotg, DOEPCTL(idx)); |
837e9f00 | 3816 | |
6070636c MH |
3817 | //ISOC Ep's only |
3818 | if ((epctrl & DXEPCTL_EPENA) && hs_ep->isochronous) { | |
837e9f00 VM |
3819 | epctrl |= DXEPCTL_SNAK; |
3820 | epctrl |= DXEPCTL_EPDIS; | |
f25c42b8 | 3821 | dwc2_writel(hsotg, epctrl, DOEPCTL(idx)); |
6070636c MH |
3822 | continue; |
3823 | } | |
3824 | ||
3825 | //Non-ISOC EP's | |
3826 | if (hs_ep->halted) { | |
3827 | if (!(epctrl & DXEPCTL_EPENA)) | |
3828 | epctrl |= DXEPCTL_EPENA; | |
3829 | epctrl |= DXEPCTL_EPDIS; | |
3830 | epctrl |= DXEPCTL_STALL; | |
3831 | dwc2_writel(hsotg, epctrl, DOEPCTL(idx)); | |
837e9f00 VM |
3832 | } |
3833 | } | |
a3395f0d | 3834 | |
837e9f00 | 3835 | /* This interrupt bit is cleared in DXEPINT_EPDISBLD handler */ |
5b7d70c6 BD |
3836 | } |
3837 | ||
47a1685f | 3838 | if (gintsts & GINTSTS_GINNAKEFF) { |
5b7d70c6 BD |
3839 | dev_info(hsotg->dev, "GINNakEff triggered\n"); |
3840 | ||
f25c42b8 | 3841 | dwc2_set_bit(hsotg, DCTL, DCTL_CGNPINNAK); |
a3395f0d | 3842 | |
1f91b4cc | 3843 | dwc2_hsotg_dump(hsotg); |
5b7d70c6 BD |
3844 | } |
3845 | ||
381fc8f8 VM |
3846 | if (gintsts & GINTSTS_INCOMPL_SOIN) |
3847 | dwc2_gadget_handle_incomplete_isoc_in(hsotg); | |
ec1f9d9f | 3848 | |
381fc8f8 VM |
3849 | if (gintsts & GINTSTS_INCOMPL_SOOUT) |
3850 | dwc2_gadget_handle_incomplete_isoc_out(hsotg); | |
ec1f9d9f | 3851 | |
8b9bc460 LM |
3852 | /* |
3853 | * if we've had fifo events, we should try and go around the | |
3854 | * loop again to see if there's any point in returning yet. | |
3855 | */ | |
5b7d70c6 BD |
3856 | |
3857 | if (gintsts & IRQ_RETRY_MASK && --retry_count > 0) | |
77b6200e | 3858 | goto irq_retry; |
5b7d70c6 | 3859 | |
187c5298 GT |
3860 | /* Check WKUP_ALERT interrupt*/ |
3861 | if (hsotg->params.service_interval) | |
3862 | dwc2_gadget_wkup_alert_handler(hsotg); | |
3863 | ||
5ad1d316 LM |
3864 | spin_unlock(&hsotg->lock); |
3865 | ||
5b7d70c6 BD |
3866 | return IRQ_HANDLED; |
3867 | } | |
3868 | ||
a4f82771 VA |
3869 | static void dwc2_hsotg_ep_stop_xfr(struct dwc2_hsotg *hsotg, |
3870 | struct dwc2_hsotg_ep *hs_ep) | |
3871 | { | |
3872 | u32 epctrl_reg; | |
3873 | u32 epint_reg; | |
3874 | ||
3875 | epctrl_reg = hs_ep->dir_in ? DIEPCTL(hs_ep->index) : | |
3876 | DOEPCTL(hs_ep->index); | |
3877 | epint_reg = hs_ep->dir_in ? DIEPINT(hs_ep->index) : | |
3878 | DOEPINT(hs_ep->index); | |
3879 | ||
3880 | dev_dbg(hsotg->dev, "%s: stopping transfer on %s\n", __func__, | |
3881 | hs_ep->name); | |
3882 | ||
3883 | if (hs_ep->dir_in) { | |
3884 | if (hsotg->dedicated_fifos || hs_ep->periodic) { | |
f25c42b8 | 3885 | dwc2_set_bit(hsotg, epctrl_reg, DXEPCTL_SNAK); |
a4f82771 VA |
3886 | /* Wait for Nak effect */ |
3887 | if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg, | |
3888 | DXEPINT_INEPNAKEFF, 100)) | |
3889 | dev_warn(hsotg->dev, | |
3890 | "%s: timeout DIEPINT.NAKEFF\n", | |
3891 | __func__); | |
3892 | } else { | |
f25c42b8 | 3893 | dwc2_set_bit(hsotg, DCTL, DCTL_SGNPINNAK); |
a4f82771 VA |
3894 | /* Wait for Nak effect */ |
3895 | if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS, | |
3896 | GINTSTS_GINNAKEFF, 100)) | |
3897 | dev_warn(hsotg->dev, | |
3898 | "%s: timeout GINTSTS.GINNAKEFF\n", | |
3899 | __func__); | |
3900 | } | |
3901 | } else { | |
f25c42b8 GS |
3902 | if (!(dwc2_readl(hsotg, GINTSTS) & GINTSTS_GOUTNAKEFF)) |
3903 | dwc2_set_bit(hsotg, DCTL, DCTL_SGOUTNAK); | |
a4f82771 VA |
3904 | |
3905 | /* Wait for global nak to take effect */ | |
3906 | if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS, | |
3907 | GINTSTS_GOUTNAKEFF, 100)) | |
3908 | dev_warn(hsotg->dev, "%s: timeout GINTSTS.GOUTNAKEFF\n", | |
3909 | __func__); | |
3910 | } | |
3911 | ||
3912 | /* Disable ep */ | |
f25c42b8 | 3913 | dwc2_set_bit(hsotg, epctrl_reg, DXEPCTL_EPDIS | DXEPCTL_SNAK); |
a4f82771 VA |
3914 | |
3915 | /* Wait for ep to be disabled */ | |
3916 | if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg, DXEPINT_EPDISBLD, 100)) | |
3917 | dev_warn(hsotg->dev, | |
3918 | "%s: timeout DOEPCTL.EPDisable\n", __func__); | |
3919 | ||
3920 | /* Clear EPDISBLD interrupt */ | |
f25c42b8 | 3921 | dwc2_set_bit(hsotg, epint_reg, DXEPINT_EPDISBLD); |
a4f82771 VA |
3922 | |
3923 | if (hs_ep->dir_in) { | |
3924 | unsigned short fifo_index; | |
3925 | ||
3926 | if (hsotg->dedicated_fifos || hs_ep->periodic) | |
3927 | fifo_index = hs_ep->fifo_index; | |
3928 | else | |
3929 | fifo_index = 0; | |
3930 | ||
3931 | /* Flush TX FIFO */ | |
3932 | dwc2_flush_tx_fifo(hsotg, fifo_index); | |
3933 | ||
3934 | /* Clear Global In NP NAK in Shared FIFO for non periodic ep */ | |
3935 | if (!hsotg->dedicated_fifos && !hs_ep->periodic) | |
f25c42b8 | 3936 | dwc2_set_bit(hsotg, DCTL, DCTL_CGNPINNAK); |
a4f82771 VA |
3937 | |
3938 | } else { | |
3939 | /* Remove global NAKs */ | |
f25c42b8 | 3940 | dwc2_set_bit(hsotg, DCTL, DCTL_CGOUTNAK); |
a4f82771 VA |
3941 | } |
3942 | } | |
3943 | ||
5b7d70c6 | 3944 | /** |
1f91b4cc | 3945 | * dwc2_hsotg_ep_enable - enable the given endpoint |
5b7d70c6 BD |
3946 | * @ep: The USB endpint to configure |
3947 | * @desc: The USB endpoint descriptor to configure with. | |
3948 | * | |
3949 | * This is called from the USB gadget code's usb_ep_enable(). | |
8b9bc460 | 3950 | */ |
1f91b4cc | 3951 | static int dwc2_hsotg_ep_enable(struct usb_ep *ep, |
9da51974 | 3952 | const struct usb_endpoint_descriptor *desc) |
5b7d70c6 | 3953 | { |
1f91b4cc | 3954 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 3955 | struct dwc2_hsotg *hsotg = hs_ep->parent; |
5b7d70c6 | 3956 | unsigned long flags; |
ca4c55ad | 3957 | unsigned int index = hs_ep->index; |
5b7d70c6 BD |
3958 | u32 epctrl_reg; |
3959 | u32 epctrl; | |
3960 | u32 mps; | |
ee2c40de | 3961 | u32 mc; |
837e9f00 | 3962 | u32 mask; |
ca4c55ad MYK |
3963 | unsigned int dir_in; |
3964 | unsigned int i, val, size; | |
19c190f9 | 3965 | int ret = 0; |
729cac69 | 3966 | unsigned char ep_type; |
54f37f56 | 3967 | int desc_num; |
5b7d70c6 BD |
3968 | |
3969 | dev_dbg(hsotg->dev, | |
3970 | "%s: ep %s: a 0x%02x, attr 0x%02x, mps 0x%04x, intr %d\n", | |
3971 | __func__, ep->name, desc->bEndpointAddress, desc->bmAttributes, | |
3972 | desc->wMaxPacketSize, desc->bInterval); | |
3973 | ||
3974 | /* not to be called for EP0 */ | |
8c3d6092 VA |
3975 | if (index == 0) { |
3976 | dev_err(hsotg->dev, "%s: called for EP 0\n", __func__); | |
3977 | return -EINVAL; | |
3978 | } | |
5b7d70c6 BD |
3979 | |
3980 | dir_in = (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) ? 1 : 0; | |
3981 | if (dir_in != hs_ep->dir_in) { | |
3982 | dev_err(hsotg->dev, "%s: direction mismatch!\n", __func__); | |
3983 | return -EINVAL; | |
3984 | } | |
3985 | ||
729cac69 | 3986 | ep_type = desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK; |
29cc8897 | 3987 | mps = usb_endpoint_maxp(desc); |
ee2c40de | 3988 | mc = usb_endpoint_maxp_mult(desc); |
5b7d70c6 | 3989 | |
729cac69 MH |
3990 | /* ISOC IN in DDMA supported bInterval up to 10 */ |
3991 | if (using_desc_dma(hsotg) && ep_type == USB_ENDPOINT_XFER_ISOC && | |
3992 | dir_in && desc->bInterval > 10) { | |
3993 | dev_err(hsotg->dev, | |
3994 | "%s: ISOC IN, DDMA: bInterval>10 not supported!\n", __func__); | |
3995 | return -EINVAL; | |
3996 | } | |
3997 | ||
3998 | /* High bandwidth ISOC OUT in DDMA not supported */ | |
3999 | if (using_desc_dma(hsotg) && ep_type == USB_ENDPOINT_XFER_ISOC && | |
4000 | !dir_in && mc > 1) { | |
4001 | dev_err(hsotg->dev, | |
4002 | "%s: ISOC OUT, DDMA: HB not supported!\n", __func__); | |
4003 | return -EINVAL; | |
4004 | } | |
4005 | ||
1f91b4cc | 4006 | /* note, we handle this here instead of dwc2_hsotg_set_ep_maxpacket */ |
5b7d70c6 | 4007 | |
94cb8fd6 | 4008 | epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index); |
f25c42b8 | 4009 | epctrl = dwc2_readl(hsotg, epctrl_reg); |
5b7d70c6 BD |
4010 | |
4011 | dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x from 0x%08x\n", | |
4012 | __func__, epctrl, epctrl_reg); | |
4013 | ||
54f37f56 MH |
4014 | if (using_desc_dma(hsotg) && ep_type == USB_ENDPOINT_XFER_ISOC) |
4015 | desc_num = MAX_DMA_DESC_NUM_HS_ISOC; | |
4016 | else | |
4017 | desc_num = MAX_DMA_DESC_NUM_GENERIC; | |
4018 | ||
5f54c54b | 4019 | /* Allocate DMA descriptor chain for non-ctrl endpoints */ |
9383e084 VM |
4020 | if (using_desc_dma(hsotg) && !hs_ep->desc_list) { |
4021 | hs_ep->desc_list = dmam_alloc_coherent(hsotg->dev, | |
54f37f56 | 4022 | desc_num * sizeof(struct dwc2_dma_desc), |
86e881e7 | 4023 | &hs_ep->desc_list_dma, GFP_ATOMIC); |
5f54c54b VA |
4024 | if (!hs_ep->desc_list) { |
4025 | ret = -ENOMEM; | |
4026 | goto error2; | |
4027 | } | |
4028 | } | |
4029 | ||
22258f49 | 4030 | spin_lock_irqsave(&hsotg->lock, flags); |
5b7d70c6 | 4031 | |
47a1685f DN |
4032 | epctrl &= ~(DXEPCTL_EPTYPE_MASK | DXEPCTL_MPS_MASK); |
4033 | epctrl |= DXEPCTL_MPS(mps); | |
5b7d70c6 | 4034 | |
8b9bc460 LM |
4035 | /* |
4036 | * mark the endpoint as active, otherwise the core may ignore | |
4037 | * transactions entirely for this endpoint | |
4038 | */ | |
47a1685f | 4039 | epctrl |= DXEPCTL_USBACTEP; |
5b7d70c6 | 4040 | |
5b7d70c6 | 4041 | /* update the endpoint state */ |
ee2c40de | 4042 | dwc2_hsotg_set_ep_maxpacket(hsotg, hs_ep->index, mps, mc, dir_in); |
5b7d70c6 BD |
4043 | |
4044 | /* default, set to non-periodic */ | |
1479e841 | 4045 | hs_ep->isochronous = 0; |
5b7d70c6 | 4046 | hs_ep->periodic = 0; |
a18ed7b0 | 4047 | hs_ep->halted = 0; |
1479e841 | 4048 | hs_ep->interval = desc->bInterval; |
4fca54aa | 4049 | |
729cac69 | 4050 | switch (ep_type) { |
5b7d70c6 | 4051 | case USB_ENDPOINT_XFER_ISOC: |
47a1685f DN |
4052 | epctrl |= DXEPCTL_EPTYPE_ISO; |
4053 | epctrl |= DXEPCTL_SETEVENFR; | |
1479e841 | 4054 | hs_ep->isochronous = 1; |
142bd33f | 4055 | hs_ep->interval = 1 << (desc->bInterval - 1); |
837e9f00 | 4056 | hs_ep->target_frame = TARGET_FRAME_INITIAL; |
ab7d2192 | 4057 | hs_ep->next_desc = 0; |
729cac69 | 4058 | hs_ep->compl_desc = 0; |
837e9f00 | 4059 | if (dir_in) { |
1479e841 | 4060 | hs_ep->periodic = 1; |
f25c42b8 | 4061 | mask = dwc2_readl(hsotg, DIEPMSK); |
837e9f00 | 4062 | mask |= DIEPMSK_NAKMSK; |
f25c42b8 | 4063 | dwc2_writel(hsotg, mask, DIEPMSK); |
837e9f00 | 4064 | } else { |
f25c42b8 | 4065 | mask = dwc2_readl(hsotg, DOEPMSK); |
837e9f00 | 4066 | mask |= DOEPMSK_OUTTKNEPDISMSK; |
f25c42b8 | 4067 | dwc2_writel(hsotg, mask, DOEPMSK); |
837e9f00 | 4068 | } |
1479e841 | 4069 | break; |
5b7d70c6 BD |
4070 | |
4071 | case USB_ENDPOINT_XFER_BULK: | |
47a1685f | 4072 | epctrl |= DXEPCTL_EPTYPE_BULK; |
5b7d70c6 BD |
4073 | break; |
4074 | ||
4075 | case USB_ENDPOINT_XFER_INT: | |
b203d0a2 | 4076 | if (dir_in) |
5b7d70c6 | 4077 | hs_ep->periodic = 1; |
5b7d70c6 | 4078 | |
142bd33f VM |
4079 | if (hsotg->gadget.speed == USB_SPEED_HIGH) |
4080 | hs_ep->interval = 1 << (desc->bInterval - 1); | |
4081 | ||
47a1685f | 4082 | epctrl |= DXEPCTL_EPTYPE_INTERRUPT; |
5b7d70c6 BD |
4083 | break; |
4084 | ||
4085 | case USB_ENDPOINT_XFER_CONTROL: | |
47a1685f | 4086 | epctrl |= DXEPCTL_EPTYPE_CONTROL; |
5b7d70c6 BD |
4087 | break; |
4088 | } | |
4089 | ||
8b9bc460 LM |
4090 | /* |
4091 | * if the hardware has dedicated fifos, we must give each IN EP | |
10aebc77 BD |
4092 | * a unique tx-fifo even if it is non-periodic. |
4093 | */ | |
21f3bb52 | 4094 | if (dir_in && hsotg->dedicated_fifos) { |
644139f8 | 4095 | unsigned fifo_count = dwc2_hsotg_tx_fifo_count(hsotg); |
ca4c55ad MYK |
4096 | u32 fifo_index = 0; |
4097 | u32 fifo_size = UINT_MAX; | |
9da51974 JY |
4098 | |
4099 | size = hs_ep->ep.maxpacket * hs_ep->mc; | |
644139f8 | 4100 | for (i = 1; i <= fifo_count; ++i) { |
9da51974 | 4101 | if (hsotg->fifo_map & (1 << i)) |
b203d0a2 | 4102 | continue; |
f25c42b8 | 4103 | val = dwc2_readl(hsotg, DPTXFSIZN(i)); |
9da51974 | 4104 | val = (val >> FIFOSIZE_DEPTH_SHIFT) * 4; |
b203d0a2 RB |
4105 | if (val < size) |
4106 | continue; | |
ca4c55ad MYK |
4107 | /* Search for smallest acceptable fifo */ |
4108 | if (val < fifo_size) { | |
4109 | fifo_size = val; | |
4110 | fifo_index = i; | |
4111 | } | |
b203d0a2 | 4112 | } |
ca4c55ad | 4113 | if (!fifo_index) { |
5f2196bd MYK |
4114 | dev_err(hsotg->dev, |
4115 | "%s: No suitable fifo found\n", __func__); | |
b585a48b | 4116 | ret = -ENOMEM; |
5f54c54b | 4117 | goto error1; |
b585a48b | 4118 | } |
97311c8f | 4119 | epctrl &= ~(DXEPCTL_TXFNUM_LIMIT << DXEPCTL_TXFNUM_SHIFT); |
ca4c55ad MYK |
4120 | hsotg->fifo_map |= 1 << fifo_index; |
4121 | epctrl |= DXEPCTL_TXFNUM(fifo_index); | |
4122 | hs_ep->fifo_index = fifo_index; | |
4123 | hs_ep->fifo_size = fifo_size; | |
b203d0a2 | 4124 | } |
10aebc77 | 4125 | |
5b7d70c6 | 4126 | /* for non control endpoints, set PID to D0 */ |
837e9f00 | 4127 | if (index && !hs_ep->isochronous) |
47a1685f | 4128 | epctrl |= DXEPCTL_SETD0PID; |
5b7d70c6 | 4129 | |
5295322a AP |
4130 | /* WA for Full speed ISOC IN in DDMA mode. |
4131 | * By Clear NAK status of EP, core will send ZLP | |
4132 | * to IN token and assert NAK interrupt relying | |
4133 | * on TxFIFO status only | |
4134 | */ | |
4135 | ||
4136 | if (hsotg->gadget.speed == USB_SPEED_FULL && | |
4137 | hs_ep->isochronous && dir_in) { | |
4138 | /* The WA applies only to core versions from 2.72a | |
4139 | * to 4.00a (including both). Also for FS_IOT_1.00a | |
4140 | * and HS_IOT_1.00a. | |
4141 | */ | |
f25c42b8 | 4142 | u32 gsnpsid = dwc2_readl(hsotg, GSNPSID); |
5295322a AP |
4143 | |
4144 | if ((gsnpsid >= DWC2_CORE_REV_2_72a && | |
4145 | gsnpsid <= DWC2_CORE_REV_4_00a) || | |
4146 | gsnpsid == DWC2_FS_IOT_REV_1_00a || | |
4147 | gsnpsid == DWC2_HS_IOT_REV_1_00a) | |
4148 | epctrl |= DXEPCTL_CNAK; | |
4149 | } | |
4150 | ||
5b7d70c6 BD |
4151 | dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n", |
4152 | __func__, epctrl); | |
4153 | ||
f25c42b8 | 4154 | dwc2_writel(hsotg, epctrl, epctrl_reg); |
5b7d70c6 | 4155 | dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x\n", |
f25c42b8 | 4156 | __func__, dwc2_readl(hsotg, epctrl_reg)); |
5b7d70c6 BD |
4157 | |
4158 | /* enable the endpoint interrupt */ | |
1f91b4cc | 4159 | dwc2_hsotg_ctrl_epint(hsotg, index, dir_in, 1); |
5b7d70c6 | 4160 | |
5f54c54b | 4161 | error1: |
22258f49 | 4162 | spin_unlock_irqrestore(&hsotg->lock, flags); |
5f54c54b VA |
4163 | |
4164 | error2: | |
4165 | if (ret && using_desc_dma(hsotg) && hs_ep->desc_list) { | |
54f37f56 | 4166 | dmam_free_coherent(hsotg->dev, desc_num * |
5f54c54b VA |
4167 | sizeof(struct dwc2_dma_desc), |
4168 | hs_ep->desc_list, hs_ep->desc_list_dma); | |
4169 | hs_ep->desc_list = NULL; | |
4170 | } | |
4171 | ||
19c190f9 | 4172 | return ret; |
5b7d70c6 BD |
4173 | } |
4174 | ||
8b9bc460 | 4175 | /** |
1f91b4cc | 4176 | * dwc2_hsotg_ep_disable - disable given endpoint |
8b9bc460 LM |
4177 | * @ep: The endpoint to disable. |
4178 | */ | |
1f91b4cc | 4179 | static int dwc2_hsotg_ep_disable(struct usb_ep *ep) |
5b7d70c6 | 4180 | { |
1f91b4cc | 4181 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 4182 | struct dwc2_hsotg *hsotg = hs_ep->parent; |
5b7d70c6 BD |
4183 | int dir_in = hs_ep->dir_in; |
4184 | int index = hs_ep->index; | |
5b7d70c6 BD |
4185 | u32 epctrl_reg; |
4186 | u32 ctrl; | |
4187 | ||
1e011293 | 4188 | dev_dbg(hsotg->dev, "%s(ep %p)\n", __func__, ep); |
5b7d70c6 | 4189 | |
c6f5c050 | 4190 | if (ep == &hsotg->eps_out[0]->ep) { |
5b7d70c6 BD |
4191 | dev_err(hsotg->dev, "%s: called for ep0\n", __func__); |
4192 | return -EINVAL; | |
9b481092 JS |
4193 | } |
4194 | ||
4195 | if (hsotg->op_state != OTG_STATE_B_PERIPHERAL) { | |
4196 | dev_err(hsotg->dev, "%s: called in host mode?\n", __func__); | |
4197 | return -EINVAL; | |
5b7d70c6 BD |
4198 | } |
4199 | ||
94cb8fd6 | 4200 | epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index); |
5b7d70c6 | 4201 | |
f25c42b8 | 4202 | ctrl = dwc2_readl(hsotg, epctrl_reg); |
a4f82771 VA |
4203 | |
4204 | if (ctrl & DXEPCTL_EPENA) | |
4205 | dwc2_hsotg_ep_stop_xfr(hsotg, hs_ep); | |
4206 | ||
47a1685f DN |
4207 | ctrl &= ~DXEPCTL_EPENA; |
4208 | ctrl &= ~DXEPCTL_USBACTEP; | |
4209 | ctrl |= DXEPCTL_SNAK; | |
5b7d70c6 BD |
4210 | |
4211 | dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl); | |
f25c42b8 | 4212 | dwc2_writel(hsotg, ctrl, epctrl_reg); |
5b7d70c6 BD |
4213 | |
4214 | /* disable endpoint interrupts */ | |
1f91b4cc | 4215 | dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 0); |
5b7d70c6 | 4216 | |
1141ea01 MYK |
4217 | /* terminate all requests with shutdown */ |
4218 | kill_all_requests(hsotg, hs_ep, -ESHUTDOWN); | |
4219 | ||
1c07b20e RB |
4220 | hsotg->fifo_map &= ~(1 << hs_ep->fifo_index); |
4221 | hs_ep->fifo_index = 0; | |
4222 | hs_ep->fifo_size = 0; | |
4223 | ||
5b7d70c6 BD |
4224 | return 0; |
4225 | } | |
4226 | ||
4fe4f9fe MH |
4227 | static int dwc2_hsotg_ep_disable_lock(struct usb_ep *ep) |
4228 | { | |
4229 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); | |
4230 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
4231 | unsigned long flags; | |
4232 | int ret; | |
4233 | ||
4234 | spin_lock_irqsave(&hsotg->lock, flags); | |
4235 | ret = dwc2_hsotg_ep_disable(ep); | |
4236 | spin_unlock_irqrestore(&hsotg->lock, flags); | |
4237 | return ret; | |
4238 | } | |
4239 | ||
5b7d70c6 BD |
4240 | /** |
4241 | * on_list - check request is on the given endpoint | |
4242 | * @ep: The endpoint to check. | |
4243 | * @test: The request to test if it is on the endpoint. | |
8b9bc460 | 4244 | */ |
1f91b4cc | 4245 | static bool on_list(struct dwc2_hsotg_ep *ep, struct dwc2_hsotg_req *test) |
5b7d70c6 | 4246 | { |
1f91b4cc | 4247 | struct dwc2_hsotg_req *req, *treq; |
5b7d70c6 BD |
4248 | |
4249 | list_for_each_entry_safe(req, treq, &ep->queue, queue) { | |
4250 | if (req == test) | |
4251 | return true; | |
4252 | } | |
4253 | ||
4254 | return false; | |
4255 | } | |
4256 | ||
8b9bc460 | 4257 | /** |
1f91b4cc | 4258 | * dwc2_hsotg_ep_dequeue - dequeue given endpoint |
8b9bc460 LM |
4259 | * @ep: The endpoint to dequeue. |
4260 | * @req: The request to be removed from a queue. | |
4261 | */ | |
1f91b4cc | 4262 | static int dwc2_hsotg_ep_dequeue(struct usb_ep *ep, struct usb_request *req) |
5b7d70c6 | 4263 | { |
1f91b4cc FB |
4264 | struct dwc2_hsotg_req *hs_req = our_req(req); |
4265 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); | |
941fcce4 | 4266 | struct dwc2_hsotg *hs = hs_ep->parent; |
5b7d70c6 BD |
4267 | unsigned long flags; |
4268 | ||
1e011293 | 4269 | dev_dbg(hs->dev, "ep_dequeue(%p,%p)\n", ep, req); |
5b7d70c6 | 4270 | |
22258f49 | 4271 | spin_lock_irqsave(&hs->lock, flags); |
5b7d70c6 BD |
4272 | |
4273 | if (!on_list(hs_ep, hs_req)) { | |
22258f49 | 4274 | spin_unlock_irqrestore(&hs->lock, flags); |
5b7d70c6 BD |
4275 | return -EINVAL; |
4276 | } | |
4277 | ||
c524dd5f MYK |
4278 | /* Dequeue already started request */ |
4279 | if (req == &hs_ep->req->req) | |
4280 | dwc2_hsotg_ep_stop_xfr(hs, hs_ep); | |
4281 | ||
1f91b4cc | 4282 | dwc2_hsotg_complete_request(hs, hs_ep, hs_req, -ECONNRESET); |
22258f49 | 4283 | spin_unlock_irqrestore(&hs->lock, flags); |
5b7d70c6 BD |
4284 | |
4285 | return 0; | |
4286 | } | |
4287 | ||
8b9bc460 | 4288 | /** |
1f91b4cc | 4289 | * dwc2_hsotg_ep_sethalt - set halt on a given endpoint |
8b9bc460 LM |
4290 | * @ep: The endpoint to set halt. |
4291 | * @value: Set or unset the halt. | |
51da43b5 VA |
4292 | * @now: If true, stall the endpoint now. Otherwise return -EAGAIN if |
4293 | * the endpoint is busy processing requests. | |
4294 | * | |
4295 | * We need to stall the endpoint immediately if request comes from set_feature | |
4296 | * protocol command handler. | |
8b9bc460 | 4297 | */ |
51da43b5 | 4298 | static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now) |
5b7d70c6 | 4299 | { |
1f91b4cc | 4300 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 4301 | struct dwc2_hsotg *hs = hs_ep->parent; |
5b7d70c6 | 4302 | int index = hs_ep->index; |
5b7d70c6 BD |
4303 | u32 epreg; |
4304 | u32 epctl; | |
9c39ddc6 | 4305 | u32 xfertype; |
5b7d70c6 BD |
4306 | |
4307 | dev_info(hs->dev, "%s(ep %p %s, %d)\n", __func__, ep, ep->name, value); | |
4308 | ||
c9f721b2 RB |
4309 | if (index == 0) { |
4310 | if (value) | |
1f91b4cc | 4311 | dwc2_hsotg_stall_ep0(hs); |
c9f721b2 RB |
4312 | else |
4313 | dev_warn(hs->dev, | |
4314 | "%s: can't clear halt on ep0\n", __func__); | |
4315 | return 0; | |
4316 | } | |
4317 | ||
15186f10 VA |
4318 | if (hs_ep->isochronous) { |
4319 | dev_err(hs->dev, "%s is Isochronous Endpoint\n", ep->name); | |
4320 | return -EINVAL; | |
4321 | } | |
4322 | ||
51da43b5 VA |
4323 | if (!now && value && !list_empty(&hs_ep->queue)) { |
4324 | dev_dbg(hs->dev, "%s request is pending, cannot halt\n", | |
4325 | ep->name); | |
4326 | return -EAGAIN; | |
4327 | } | |
4328 | ||
c6f5c050 MYK |
4329 | if (hs_ep->dir_in) { |
4330 | epreg = DIEPCTL(index); | |
f25c42b8 | 4331 | epctl = dwc2_readl(hs, epreg); |
c6f5c050 MYK |
4332 | |
4333 | if (value) { | |
5a350d53 | 4334 | epctl |= DXEPCTL_STALL | DXEPCTL_SNAK; |
c6f5c050 MYK |
4335 | if (epctl & DXEPCTL_EPENA) |
4336 | epctl |= DXEPCTL_EPDIS; | |
4337 | } else { | |
4338 | epctl &= ~DXEPCTL_STALL; | |
4339 | xfertype = epctl & DXEPCTL_EPTYPE_MASK; | |
4340 | if (xfertype == DXEPCTL_EPTYPE_BULK || | |
9da51974 | 4341 | xfertype == DXEPCTL_EPTYPE_INTERRUPT) |
77b6200e | 4342 | epctl |= DXEPCTL_SETD0PID; |
c6f5c050 | 4343 | } |
f25c42b8 | 4344 | dwc2_writel(hs, epctl, epreg); |
9c39ddc6 | 4345 | } else { |
c6f5c050 | 4346 | epreg = DOEPCTL(index); |
f25c42b8 | 4347 | epctl = dwc2_readl(hs, epreg); |
5b7d70c6 | 4348 | |
34c0887f | 4349 | if (value) { |
6070636c MH |
4350 | if (!(dwc2_readl(hs, GINTSTS) & GINTSTS_GOUTNAKEFF)) |
4351 | dwc2_set_bit(hs, DCTL, DCTL_SGOUTNAK); | |
4352 | // STALL bit will be set in GOUTNAKEFF interrupt handler | |
34c0887f | 4353 | } else { |
c6f5c050 MYK |
4354 | epctl &= ~DXEPCTL_STALL; |
4355 | xfertype = epctl & DXEPCTL_EPTYPE_MASK; | |
4356 | if (xfertype == DXEPCTL_EPTYPE_BULK || | |
9da51974 | 4357 | xfertype == DXEPCTL_EPTYPE_INTERRUPT) |
77b6200e | 4358 | epctl |= DXEPCTL_SETD0PID; |
6070636c | 4359 | dwc2_writel(hs, epctl, epreg); |
c6f5c050 | 4360 | } |
9c39ddc6 | 4361 | } |
5b7d70c6 | 4362 | |
a18ed7b0 | 4363 | hs_ep->halted = value; |
5b7d70c6 BD |
4364 | return 0; |
4365 | } | |
4366 | ||
5ad1d316 | 4367 | /** |
1f91b4cc | 4368 | * dwc2_hsotg_ep_sethalt_lock - set halt on a given endpoint with lock held |
5ad1d316 LM |
4369 | * @ep: The endpoint to set halt. |
4370 | * @value: Set or unset the halt. | |
4371 | */ | |
1f91b4cc | 4372 | static int dwc2_hsotg_ep_sethalt_lock(struct usb_ep *ep, int value) |
5ad1d316 | 4373 | { |
1f91b4cc | 4374 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 4375 | struct dwc2_hsotg *hs = hs_ep->parent; |
5ad1d316 LM |
4376 | unsigned long flags = 0; |
4377 | int ret = 0; | |
4378 | ||
4379 | spin_lock_irqsave(&hs->lock, flags); | |
51da43b5 | 4380 | ret = dwc2_hsotg_ep_sethalt(ep, value, false); |
5ad1d316 LM |
4381 | spin_unlock_irqrestore(&hs->lock, flags); |
4382 | ||
4383 | return ret; | |
4384 | } | |
4385 | ||
ebce561a | 4386 | static const struct usb_ep_ops dwc2_hsotg_ep_ops = { |
1f91b4cc | 4387 | .enable = dwc2_hsotg_ep_enable, |
4fe4f9fe | 4388 | .disable = dwc2_hsotg_ep_disable_lock, |
1f91b4cc FB |
4389 | .alloc_request = dwc2_hsotg_ep_alloc_request, |
4390 | .free_request = dwc2_hsotg_ep_free_request, | |
4391 | .queue = dwc2_hsotg_ep_queue_lock, | |
4392 | .dequeue = dwc2_hsotg_ep_dequeue, | |
4393 | .set_halt = dwc2_hsotg_ep_sethalt_lock, | |
25985edc | 4394 | /* note, don't believe we have any call for the fifo routines */ |
5b7d70c6 BD |
4395 | }; |
4396 | ||
8b9bc460 | 4397 | /** |
9da51974 | 4398 | * dwc2_hsotg_init - initialize the usb core |
8b9bc460 LM |
4399 | * @hsotg: The driver state |
4400 | */ | |
1f91b4cc | 4401 | static void dwc2_hsotg_init(struct dwc2_hsotg *hsotg) |
b3f489b2 LM |
4402 | { |
4403 | /* unmask subset of endpoint interrupts */ | |
4404 | ||
f25c42b8 | 4405 | dwc2_writel(hsotg, DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK | |
95c8bc36 | 4406 | DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK, |
f25c42b8 | 4407 | DIEPMSK); |
b3f489b2 | 4408 | |
f25c42b8 | 4409 | dwc2_writel(hsotg, DOEPMSK_SETUPMSK | DOEPMSK_AHBERRMSK | |
95c8bc36 | 4410 | DOEPMSK_EPDISBLDMSK | DOEPMSK_XFERCOMPLMSK, |
f25c42b8 | 4411 | DOEPMSK); |
b3f489b2 | 4412 | |
f25c42b8 | 4413 | dwc2_writel(hsotg, 0, DAINTMSK); |
b3f489b2 LM |
4414 | |
4415 | /* Be in disconnected state until gadget is registered */ | |
f25c42b8 | 4416 | dwc2_set_bit(hsotg, DCTL, DCTL_SFTDISCON); |
b3f489b2 | 4417 | |
b3f489b2 LM |
4418 | /* setup fifos */ |
4419 | ||
4420 | dev_dbg(hsotg->dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n", | |
f25c42b8 GS |
4421 | dwc2_readl(hsotg, GRXFSIZ), |
4422 | dwc2_readl(hsotg, GNPTXFSIZ)); | |
b3f489b2 | 4423 | |
1f91b4cc | 4424 | dwc2_hsotg_init_fifo(hsotg); |
b3f489b2 | 4425 | |
f5090044 | 4426 | if (using_dma(hsotg)) |
f25c42b8 | 4427 | dwc2_set_bit(hsotg, GAHBCFG, GAHBCFG_DMA_EN); |
b3f489b2 LM |
4428 | } |
4429 | ||
8b9bc460 | 4430 | /** |
1f91b4cc | 4431 | * dwc2_hsotg_udc_start - prepare the udc for work |
8b9bc460 LM |
4432 | * @gadget: The usb gadget state |
4433 | * @driver: The usb gadget driver | |
4434 | * | |
4435 | * Perform initialization to prepare udc device and driver | |
4436 | * to work. | |
4437 | */ | |
1f91b4cc | 4438 | static int dwc2_hsotg_udc_start(struct usb_gadget *gadget, |
9da51974 | 4439 | struct usb_gadget_driver *driver) |
5b7d70c6 | 4440 | { |
941fcce4 | 4441 | struct dwc2_hsotg *hsotg = to_hsotg(gadget); |
5b9451f8 | 4442 | unsigned long flags; |
5b7d70c6 BD |
4443 | int ret; |
4444 | ||
4445 | if (!hsotg) { | |
a023da33 | 4446 | pr_err("%s: called with no device\n", __func__); |
5b7d70c6 BD |
4447 | return -ENODEV; |
4448 | } | |
4449 | ||
4450 | if (!driver) { | |
4451 | dev_err(hsotg->dev, "%s: no driver\n", __func__); | |
4452 | return -EINVAL; | |
4453 | } | |
4454 | ||
7177aed4 | 4455 | if (driver->max_speed < USB_SPEED_FULL) |
5b7d70c6 | 4456 | dev_err(hsotg->dev, "%s: bad speed\n", __func__); |
5b7d70c6 | 4457 | |
f65f0f10 | 4458 | if (!driver->setup) { |
5b7d70c6 BD |
4459 | dev_err(hsotg->dev, "%s: missing entry points\n", __func__); |
4460 | return -EINVAL; | |
4461 | } | |
4462 | ||
4463 | WARN_ON(hsotg->driver); | |
4464 | ||
4465 | driver->driver.bus = NULL; | |
4466 | hsotg->driver = driver; | |
7d7b2292 | 4467 | hsotg->gadget.dev.of_node = hsotg->dev->of_node; |
5b7d70c6 BD |
4468 | hsotg->gadget.speed = USB_SPEED_UNKNOWN; |
4469 | ||
09a75e85 MS |
4470 | if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) { |
4471 | ret = dwc2_lowlevel_hw_enable(hsotg); | |
4472 | if (ret) | |
4473 | goto err; | |
5b7d70c6 BD |
4474 | } |
4475 | ||
f6c01592 GH |
4476 | if (!IS_ERR_OR_NULL(hsotg->uphy)) |
4477 | otg_set_peripheral(hsotg->uphy->otg, &hsotg->gadget); | |
c816c47f | 4478 | |
5b9451f8 | 4479 | spin_lock_irqsave(&hsotg->lock, flags); |
d0f0ac56 JY |
4480 | if (dwc2_hw_is_device(hsotg)) { |
4481 | dwc2_hsotg_init(hsotg); | |
4482 | dwc2_hsotg_core_init_disconnected(hsotg, false); | |
4483 | } | |
4484 | ||
dc6e69e6 | 4485 | hsotg->enabled = 0; |
5b9451f8 MS |
4486 | spin_unlock_irqrestore(&hsotg->lock, flags); |
4487 | ||
10209abe | 4488 | gadget->sg_supported = using_desc_dma(hsotg); |
5b7d70c6 | 4489 | dev_info(hsotg->dev, "bound driver %s\n", driver->driver.name); |
5b9451f8 | 4490 | |
5b7d70c6 BD |
4491 | return 0; |
4492 | ||
4493 | err: | |
4494 | hsotg->driver = NULL; | |
5b7d70c6 BD |
4495 | return ret; |
4496 | } | |
4497 | ||
8b9bc460 | 4498 | /** |
1f91b4cc | 4499 | * dwc2_hsotg_udc_stop - stop the udc |
8b9bc460 | 4500 | * @gadget: The usb gadget state |
8b9bc460 LM |
4501 | * |
4502 | * Stop udc hw block and stay tunned for future transmissions | |
4503 | */ | |
1f91b4cc | 4504 | static int dwc2_hsotg_udc_stop(struct usb_gadget *gadget) |
5b7d70c6 | 4505 | { |
941fcce4 | 4506 | struct dwc2_hsotg *hsotg = to_hsotg(gadget); |
2b19a52c | 4507 | unsigned long flags = 0; |
5b7d70c6 BD |
4508 | int ep; |
4509 | ||
4510 | if (!hsotg) | |
4511 | return -ENODEV; | |
4512 | ||
5b7d70c6 | 4513 | /* all endpoints should be shutdown */ |
c6f5c050 MYK |
4514 | for (ep = 1; ep < hsotg->num_of_eps; ep++) { |
4515 | if (hsotg->eps_in[ep]) | |
4fe4f9fe | 4516 | dwc2_hsotg_ep_disable_lock(&hsotg->eps_in[ep]->ep); |
c6f5c050 | 4517 | if (hsotg->eps_out[ep]) |
4fe4f9fe | 4518 | dwc2_hsotg_ep_disable_lock(&hsotg->eps_out[ep]->ep); |
c6f5c050 | 4519 | } |
5b7d70c6 | 4520 | |
2b19a52c LM |
4521 | spin_lock_irqsave(&hsotg->lock, flags); |
4522 | ||
32805c35 | 4523 | hsotg->driver = NULL; |
5b7d70c6 | 4524 | hsotg->gadget.speed = USB_SPEED_UNKNOWN; |
dc6e69e6 | 4525 | hsotg->enabled = 0; |
5b7d70c6 | 4526 | |
2b19a52c LM |
4527 | spin_unlock_irqrestore(&hsotg->lock, flags); |
4528 | ||
f6c01592 GH |
4529 | if (!IS_ERR_OR_NULL(hsotg->uphy)) |
4530 | otg_set_peripheral(hsotg->uphy->otg, NULL); | |
c816c47f | 4531 | |
09a75e85 MS |
4532 | if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) |
4533 | dwc2_lowlevel_hw_disable(hsotg); | |
5b7d70c6 BD |
4534 | |
4535 | return 0; | |
4536 | } | |
5b7d70c6 | 4537 | |
8b9bc460 | 4538 | /** |
1f91b4cc | 4539 | * dwc2_hsotg_gadget_getframe - read the frame number |
8b9bc460 LM |
4540 | * @gadget: The usb gadget state |
4541 | * | |
4542 | * Read the {micro} frame number | |
4543 | */ | |
1f91b4cc | 4544 | static int dwc2_hsotg_gadget_getframe(struct usb_gadget *gadget) |
5b7d70c6 | 4545 | { |
1f91b4cc | 4546 | return dwc2_hsotg_read_frameno(to_hsotg(gadget)); |
5b7d70c6 BD |
4547 | } |
4548 | ||
1a0808cb JK |
4549 | /** |
4550 | * dwc2_hsotg_set_selfpowered - set if device is self/bus powered | |
4551 | * @gadget: The usb gadget state | |
4552 | * @is_selfpowered: Whether the device is self-powered | |
4553 | * | |
4554 | * Set if the device is self or bus powered. | |
4555 | */ | |
4556 | static int dwc2_hsotg_set_selfpowered(struct usb_gadget *gadget, | |
4557 | int is_selfpowered) | |
4558 | { | |
4559 | struct dwc2_hsotg *hsotg = to_hsotg(gadget); | |
4560 | unsigned long flags; | |
4561 | ||
4562 | spin_lock_irqsave(&hsotg->lock, flags); | |
4563 | gadget->is_selfpowered = !!is_selfpowered; | |
4564 | spin_unlock_irqrestore(&hsotg->lock, flags); | |
4565 | ||
4566 | return 0; | |
4567 | } | |
4568 | ||
a188b689 | 4569 | /** |
1f91b4cc | 4570 | * dwc2_hsotg_pullup - connect/disconnect the USB PHY |
a188b689 LM |
4571 | * @gadget: The usb gadget state |
4572 | * @is_on: Current state of the USB PHY | |
4573 | * | |
4574 | * Connect/Disconnect the USB PHY pullup | |
4575 | */ | |
1f91b4cc | 4576 | static int dwc2_hsotg_pullup(struct usb_gadget *gadget, int is_on) |
a188b689 | 4577 | { |
941fcce4 | 4578 | struct dwc2_hsotg *hsotg = to_hsotg(gadget); |
a188b689 LM |
4579 | unsigned long flags = 0; |
4580 | ||
77ba9119 | 4581 | dev_dbg(hsotg->dev, "%s: is_on: %d op_state: %d\n", __func__, is_on, |
9da51974 | 4582 | hsotg->op_state); |
77ba9119 GH |
4583 | |
4584 | /* Don't modify pullup state while in host mode */ | |
4585 | if (hsotg->op_state != OTG_STATE_B_PERIPHERAL) { | |
4586 | hsotg->enabled = is_on; | |
4587 | return 0; | |
4588 | } | |
a188b689 LM |
4589 | |
4590 | spin_lock_irqsave(&hsotg->lock, flags); | |
4591 | if (is_on) { | |
dc6e69e6 | 4592 | hsotg->enabled = 1; |
1f91b4cc | 4593 | dwc2_hsotg_core_init_disconnected(hsotg, false); |
66e77a24 RK |
4594 | /* Enable ACG feature in device mode,if supported */ |
4595 | dwc2_enable_acg(hsotg); | |
1f91b4cc | 4596 | dwc2_hsotg_core_connect(hsotg); |
a188b689 | 4597 | } else { |
1f91b4cc FB |
4598 | dwc2_hsotg_core_disconnect(hsotg); |
4599 | dwc2_hsotg_disconnect(hsotg); | |
dc6e69e6 | 4600 | hsotg->enabled = 0; |
a188b689 LM |
4601 | } |
4602 | ||
4603 | hsotg->gadget.speed = USB_SPEED_UNKNOWN; | |
4604 | spin_unlock_irqrestore(&hsotg->lock, flags); | |
4605 | ||
4606 | return 0; | |
4607 | } | |
4608 | ||
1f91b4cc | 4609 | static int dwc2_hsotg_vbus_session(struct usb_gadget *gadget, int is_active) |
83d98223 GH |
4610 | { |
4611 | struct dwc2_hsotg *hsotg = to_hsotg(gadget); | |
4612 | unsigned long flags; | |
4613 | ||
4614 | dev_dbg(hsotg->dev, "%s: is_active: %d\n", __func__, is_active); | |
4615 | spin_lock_irqsave(&hsotg->lock, flags); | |
4616 | ||
61f7223b | 4617 | /* |
c9c394ab AP |
4618 | * If controller is in partial power down state, it must exit from |
4619 | * that state before being initialized / de-initialized | |
61f7223b | 4620 | */ |
c9c394ab AP |
4621 | if (hsotg->lx_state == DWC2_L2 && hsotg->in_ppd) |
4622 | /* | |
4623 | * No need to check the return value as | |
4624 | * registers are not being restored. | |
4625 | */ | |
4626 | dwc2_exit_partial_power_down(hsotg, 0, false); | |
61f7223b | 4627 | |
83d98223 | 4628 | if (is_active) { |
cd0e641c | 4629 | hsotg->op_state = OTG_STATE_B_PERIPHERAL; |
065d3931 | 4630 | |
1f91b4cc | 4631 | dwc2_hsotg_core_init_disconnected(hsotg, false); |
66e77a24 RK |
4632 | if (hsotg->enabled) { |
4633 | /* Enable ACG feature in device mode,if supported */ | |
4634 | dwc2_enable_acg(hsotg); | |
1f91b4cc | 4635 | dwc2_hsotg_core_connect(hsotg); |
66e77a24 | 4636 | } |
83d98223 | 4637 | } else { |
1f91b4cc FB |
4638 | dwc2_hsotg_core_disconnect(hsotg); |
4639 | dwc2_hsotg_disconnect(hsotg); | |
83d98223 GH |
4640 | } |
4641 | ||
4642 | spin_unlock_irqrestore(&hsotg->lock, flags); | |
4643 | return 0; | |
4644 | } | |
4645 | ||
596d696a | 4646 | /** |
1f91b4cc | 4647 | * dwc2_hsotg_vbus_draw - report bMaxPower field |
596d696a GH |
4648 | * @gadget: The usb gadget state |
4649 | * @mA: Amount of current | |
4650 | * | |
4651 | * Report how much power the device may consume to the phy. | |
4652 | */ | |
9da51974 | 4653 | static int dwc2_hsotg_vbus_draw(struct usb_gadget *gadget, unsigned int mA) |
596d696a GH |
4654 | { |
4655 | struct dwc2_hsotg *hsotg = to_hsotg(gadget); | |
4656 | ||
4657 | if (IS_ERR_OR_NULL(hsotg->uphy)) | |
4658 | return -ENOTSUPP; | |
4659 | return usb_phy_set_power(hsotg->uphy, mA); | |
4660 | } | |
4661 | ||
1f91b4cc FB |
4662 | static const struct usb_gadget_ops dwc2_hsotg_gadget_ops = { |
4663 | .get_frame = dwc2_hsotg_gadget_getframe, | |
1a0808cb | 4664 | .set_selfpowered = dwc2_hsotg_set_selfpowered, |
1f91b4cc FB |
4665 | .udc_start = dwc2_hsotg_udc_start, |
4666 | .udc_stop = dwc2_hsotg_udc_stop, | |
4667 | .pullup = dwc2_hsotg_pullup, | |
4668 | .vbus_session = dwc2_hsotg_vbus_session, | |
4669 | .vbus_draw = dwc2_hsotg_vbus_draw, | |
5b7d70c6 BD |
4670 | }; |
4671 | ||
4672 | /** | |
1f91b4cc | 4673 | * dwc2_hsotg_initep - initialise a single endpoint |
5b7d70c6 BD |
4674 | * @hsotg: The device state. |
4675 | * @hs_ep: The endpoint to be initialised. | |
4676 | * @epnum: The endpoint number | |
6fb914d7 | 4677 | * @dir_in: True if direction is in. |
5b7d70c6 BD |
4678 | * |
4679 | * Initialise the given endpoint (as part of the probe and device state | |
4680 | * creation) to give to the gadget driver. Setup the endpoint name, any | |
4681 | * direction information and other state that may be required. | |
4682 | */ | |
1f91b4cc | 4683 | static void dwc2_hsotg_initep(struct dwc2_hsotg *hsotg, |
9da51974 | 4684 | struct dwc2_hsotg_ep *hs_ep, |
c6f5c050 MYK |
4685 | int epnum, |
4686 | bool dir_in) | |
5b7d70c6 | 4687 | { |
5b7d70c6 BD |
4688 | char *dir; |
4689 | ||
4690 | if (epnum == 0) | |
4691 | dir = ""; | |
c6f5c050 | 4692 | else if (dir_in) |
5b7d70c6 | 4693 | dir = "in"; |
c6f5c050 MYK |
4694 | else |
4695 | dir = "out"; | |
5b7d70c6 | 4696 | |
c6f5c050 | 4697 | hs_ep->dir_in = dir_in; |
5b7d70c6 BD |
4698 | hs_ep->index = epnum; |
4699 | ||
4700 | snprintf(hs_ep->name, sizeof(hs_ep->name), "ep%d%s", epnum, dir); | |
4701 | ||
4702 | INIT_LIST_HEAD(&hs_ep->queue); | |
4703 | INIT_LIST_HEAD(&hs_ep->ep.ep_list); | |
4704 | ||
5b7d70c6 BD |
4705 | /* add to the list of endpoints known by the gadget driver */ |
4706 | if (epnum) | |
4707 | list_add_tail(&hs_ep->ep.ep_list, &hsotg->gadget.ep_list); | |
4708 | ||
4709 | hs_ep->parent = hsotg; | |
4710 | hs_ep->ep.name = hs_ep->name; | |
38e9002b VM |
4711 | |
4712 | if (hsotg->params.speed == DWC2_SPEED_PARAM_LOW) | |
4713 | usb_ep_set_maxpacket_limit(&hs_ep->ep, 8); | |
4714 | else | |
4715 | usb_ep_set_maxpacket_limit(&hs_ep->ep, | |
4716 | epnum ? 1024 : EP0_MPS_LIMIT); | |
1f91b4cc | 4717 | hs_ep->ep.ops = &dwc2_hsotg_ep_ops; |
5b7d70c6 | 4718 | |
2954522f RB |
4719 | if (epnum == 0) { |
4720 | hs_ep->ep.caps.type_control = true; | |
4721 | } else { | |
38e9002b VM |
4722 | if (hsotg->params.speed != DWC2_SPEED_PARAM_LOW) { |
4723 | hs_ep->ep.caps.type_iso = true; | |
4724 | hs_ep->ep.caps.type_bulk = true; | |
4725 | } | |
2954522f RB |
4726 | hs_ep->ep.caps.type_int = true; |
4727 | } | |
4728 | ||
4729 | if (dir_in) | |
4730 | hs_ep->ep.caps.dir_in = true; | |
4731 | else | |
4732 | hs_ep->ep.caps.dir_out = true; | |
4733 | ||
8b9bc460 LM |
4734 | /* |
4735 | * if we're using dma, we need to set the next-endpoint pointer | |
5b7d70c6 BD |
4736 | * to be something valid. |
4737 | */ | |
4738 | ||
4739 | if (using_dma(hsotg)) { | |
47a1685f | 4740 | u32 next = DXEPCTL_NEXTEP((epnum + 1) % 15); |
9da51974 | 4741 | |
c6f5c050 | 4742 | if (dir_in) |
f25c42b8 | 4743 | dwc2_writel(hsotg, next, DIEPCTL(epnum)); |
c6f5c050 | 4744 | else |
f25c42b8 | 4745 | dwc2_writel(hsotg, next, DOEPCTL(epnum)); |
5b7d70c6 BD |
4746 | } |
4747 | } | |
4748 | ||
b3f489b2 | 4749 | /** |
1f91b4cc | 4750 | * dwc2_hsotg_hw_cfg - read HW configuration registers |
6fb914d7 | 4751 | * @hsotg: Programming view of the DWC_otg controller |
b3f489b2 LM |
4752 | * |
4753 | * Read the USB core HW configuration registers | |
4754 | */ | |
1f91b4cc | 4755 | static int dwc2_hsotg_hw_cfg(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 4756 | { |
c6f5c050 MYK |
4757 | u32 cfg; |
4758 | u32 ep_type; | |
4759 | u32 i; | |
4760 | ||
b3f489b2 | 4761 | /* check hardware configuration */ |
5b7d70c6 | 4762 | |
43e90349 JY |
4763 | hsotg->num_of_eps = hsotg->hw_params.num_dev_ep; |
4764 | ||
c6f5c050 MYK |
4765 | /* Add ep0 */ |
4766 | hsotg->num_of_eps++; | |
10aebc77 | 4767 | |
b98866c2 JY |
4768 | hsotg->eps_in[0] = devm_kzalloc(hsotg->dev, |
4769 | sizeof(struct dwc2_hsotg_ep), | |
4770 | GFP_KERNEL); | |
c6f5c050 MYK |
4771 | if (!hsotg->eps_in[0]) |
4772 | return -ENOMEM; | |
1f91b4cc | 4773 | /* Same dwc2_hsotg_ep is used in both directions for ep0 */ |
c6f5c050 MYK |
4774 | hsotg->eps_out[0] = hsotg->eps_in[0]; |
4775 | ||
43e90349 | 4776 | cfg = hsotg->hw_params.dev_ep_dirs; |
251a17f5 | 4777 | for (i = 1, cfg >>= 2; i < hsotg->num_of_eps; i++, cfg >>= 2) { |
c6f5c050 MYK |
4778 | ep_type = cfg & 3; |
4779 | /* Direction in or both */ | |
4780 | if (!(ep_type & 2)) { | |
4781 | hsotg->eps_in[i] = devm_kzalloc(hsotg->dev, | |
1f91b4cc | 4782 | sizeof(struct dwc2_hsotg_ep), GFP_KERNEL); |
c6f5c050 MYK |
4783 | if (!hsotg->eps_in[i]) |
4784 | return -ENOMEM; | |
4785 | } | |
4786 | /* Direction out or both */ | |
4787 | if (!(ep_type & 1)) { | |
4788 | hsotg->eps_out[i] = devm_kzalloc(hsotg->dev, | |
1f91b4cc | 4789 | sizeof(struct dwc2_hsotg_ep), GFP_KERNEL); |
c6f5c050 MYK |
4790 | if (!hsotg->eps_out[i]) |
4791 | return -ENOMEM; | |
4792 | } | |
4793 | } | |
4794 | ||
43e90349 JY |
4795 | hsotg->fifo_mem = hsotg->hw_params.total_fifo_size; |
4796 | hsotg->dedicated_fifos = hsotg->hw_params.en_multiple_tx_fifo; | |
10aebc77 | 4797 | |
cff9eb75 MS |
4798 | dev_info(hsotg->dev, "EPs: %d, %s fifos, %d entries in SPRAM\n", |
4799 | hsotg->num_of_eps, | |
4800 | hsotg->dedicated_fifos ? "dedicated" : "shared", | |
4801 | hsotg->fifo_mem); | |
c6f5c050 | 4802 | return 0; |
5b7d70c6 BD |
4803 | } |
4804 | ||
8b9bc460 | 4805 | /** |
1f91b4cc | 4806 | * dwc2_hsotg_dump - dump state of the udc |
6fb914d7 GT |
4807 | * @hsotg: Programming view of the DWC_otg controller |
4808 | * | |
8b9bc460 | 4809 | */ |
1f91b4cc | 4810 | static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 4811 | { |
83a01804 | 4812 | #ifdef DEBUG |
5b7d70c6 | 4813 | struct device *dev = hsotg->dev; |
5b7d70c6 BD |
4814 | u32 val; |
4815 | int idx; | |
4816 | ||
4817 | dev_info(dev, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n", | |
f25c42b8 GS |
4818 | dwc2_readl(hsotg, DCFG), dwc2_readl(hsotg, DCTL), |
4819 | dwc2_readl(hsotg, DIEPMSK)); | |
5b7d70c6 | 4820 | |
f889f23d | 4821 | dev_info(dev, "GAHBCFG=0x%08x, GHWCFG1=0x%08x\n", |
f25c42b8 | 4822 | dwc2_readl(hsotg, GAHBCFG), dwc2_readl(hsotg, GHWCFG1)); |
5b7d70c6 BD |
4823 | |
4824 | dev_info(dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n", | |
f25c42b8 | 4825 | dwc2_readl(hsotg, GRXFSIZ), dwc2_readl(hsotg, GNPTXFSIZ)); |
5b7d70c6 BD |
4826 | |
4827 | /* show periodic fifo settings */ | |
4828 | ||
364f8e93 | 4829 | for (idx = 1; idx < hsotg->num_of_eps; idx++) { |
f25c42b8 | 4830 | val = dwc2_readl(hsotg, DPTXFSIZN(idx)); |
5b7d70c6 | 4831 | dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx, |
47a1685f DN |
4832 | val >> FIFOSIZE_DEPTH_SHIFT, |
4833 | val & FIFOSIZE_STARTADDR_MASK); | |
5b7d70c6 BD |
4834 | } |
4835 | ||
364f8e93 | 4836 | for (idx = 0; idx < hsotg->num_of_eps; idx++) { |
5b7d70c6 BD |
4837 | dev_info(dev, |
4838 | "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx, | |
f25c42b8 GS |
4839 | dwc2_readl(hsotg, DIEPCTL(idx)), |
4840 | dwc2_readl(hsotg, DIEPTSIZ(idx)), | |
4841 | dwc2_readl(hsotg, DIEPDMA(idx))); | |
5b7d70c6 | 4842 | |
f25c42b8 | 4843 | val = dwc2_readl(hsotg, DOEPCTL(idx)); |
5b7d70c6 BD |
4844 | dev_info(dev, |
4845 | "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", | |
f25c42b8 GS |
4846 | idx, dwc2_readl(hsotg, DOEPCTL(idx)), |
4847 | dwc2_readl(hsotg, DOEPTSIZ(idx)), | |
4848 | dwc2_readl(hsotg, DOEPDMA(idx))); | |
5b7d70c6 BD |
4849 | } |
4850 | ||
4851 | dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n", | |
f25c42b8 | 4852 | dwc2_readl(hsotg, DVBUSDIS), dwc2_readl(hsotg, DVBUSPULSE)); |
83a01804 | 4853 | #endif |
5b7d70c6 BD |
4854 | } |
4855 | ||
8b9bc460 | 4856 | /** |
117777b2 | 4857 | * dwc2_gadget_init - init function for gadget |
6fb914d7 GT |
4858 | * @hsotg: Programming view of the DWC_otg controller |
4859 | * | |
8b9bc460 | 4860 | */ |
f3768997 | 4861 | int dwc2_gadget_init(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 4862 | { |
117777b2 | 4863 | struct device *dev = hsotg->dev; |
5b7d70c6 BD |
4864 | int epnum; |
4865 | int ret; | |
43e90349 | 4866 | |
0a176279 GH |
4867 | /* Dump fifo information */ |
4868 | dev_dbg(dev, "NonPeriodic TXFIFO size: %d\n", | |
05ee799f JY |
4869 | hsotg->params.g_np_tx_fifo_size); |
4870 | dev_dbg(dev, "RXFIFO size: %d\n", hsotg->params.g_rx_fifo_size); | |
5b7d70c6 | 4871 | |
d327ab5b | 4872 | hsotg->gadget.max_speed = USB_SPEED_HIGH; |
1f91b4cc | 4873 | hsotg->gadget.ops = &dwc2_hsotg_gadget_ops; |
5b7d70c6 | 4874 | hsotg->gadget.name = dev_name(dev); |
fa389a6d | 4875 | hsotg->remote_wakeup_allowed = 0; |
7455f8b7 JY |
4876 | |
4877 | if (hsotg->params.lpm) | |
4878 | hsotg->gadget.lpm_capable = true; | |
4879 | ||
097ee662 GH |
4880 | if (hsotg->dr_mode == USB_DR_MODE_OTG) |
4881 | hsotg->gadget.is_otg = 1; | |
ec4cc657 MYK |
4882 | else if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) |
4883 | hsotg->op_state = OTG_STATE_B_PERIPHERAL; | |
5b7d70c6 | 4884 | |
1f91b4cc | 4885 | ret = dwc2_hsotg_hw_cfg(hsotg); |
c6f5c050 MYK |
4886 | if (ret) { |
4887 | dev_err(hsotg->dev, "Hardware configuration failed: %d\n", ret); | |
09a75e85 | 4888 | return ret; |
c6f5c050 MYK |
4889 | } |
4890 | ||
3f95001d MYK |
4891 | hsotg->ctrl_buff = devm_kzalloc(hsotg->dev, |
4892 | DWC2_CTRL_BUFF_SIZE, GFP_KERNEL); | |
8bae0f8c | 4893 | if (!hsotg->ctrl_buff) |
09a75e85 | 4894 | return -ENOMEM; |
3f95001d MYK |
4895 | |
4896 | hsotg->ep0_buff = devm_kzalloc(hsotg->dev, | |
4897 | DWC2_CTRL_BUFF_SIZE, GFP_KERNEL); | |
8bae0f8c | 4898 | if (!hsotg->ep0_buff) |
09a75e85 | 4899 | return -ENOMEM; |
3f95001d | 4900 | |
0f6b80c0 VA |
4901 | if (using_desc_dma(hsotg)) { |
4902 | ret = dwc2_gadget_alloc_ctrl_desc_chains(hsotg); | |
4903 | if (ret < 0) | |
4904 | return ret; | |
4905 | } | |
4906 | ||
f3768997 VM |
4907 | ret = devm_request_irq(hsotg->dev, hsotg->irq, dwc2_hsotg_irq, |
4908 | IRQF_SHARED, dev_name(hsotg->dev), hsotg); | |
eb3c56c5 | 4909 | if (ret < 0) { |
db8178c3 | 4910 | dev_err(dev, "cannot claim IRQ for gadget\n"); |
09a75e85 | 4911 | return ret; |
eb3c56c5 MS |
4912 | } |
4913 | ||
b3f489b2 LM |
4914 | /* hsotg->num_of_eps holds number of EPs other than ep0 */ |
4915 | ||
4916 | if (hsotg->num_of_eps == 0) { | |
4917 | dev_err(dev, "wrong number of EPs (zero)\n"); | |
09a75e85 | 4918 | return -EINVAL; |
b3f489b2 LM |
4919 | } |
4920 | ||
b3f489b2 LM |
4921 | /* setup endpoint information */ |
4922 | ||
4923 | INIT_LIST_HEAD(&hsotg->gadget.ep_list); | |
c6f5c050 | 4924 | hsotg->gadget.ep0 = &hsotg->eps_out[0]->ep; |
b3f489b2 LM |
4925 | |
4926 | /* allocate EP0 request */ | |
4927 | ||
1f91b4cc | 4928 | hsotg->ctrl_req = dwc2_hsotg_ep_alloc_request(&hsotg->eps_out[0]->ep, |
b3f489b2 LM |
4929 | GFP_KERNEL); |
4930 | if (!hsotg->ctrl_req) { | |
4931 | dev_err(dev, "failed to allocate ctrl req\n"); | |
09a75e85 | 4932 | return -ENOMEM; |
b3f489b2 | 4933 | } |
5b7d70c6 BD |
4934 | |
4935 | /* initialise the endpoints now the core has been initialised */ | |
c6f5c050 MYK |
4936 | for (epnum = 0; epnum < hsotg->num_of_eps; epnum++) { |
4937 | if (hsotg->eps_in[epnum]) | |
1f91b4cc | 4938 | dwc2_hsotg_initep(hsotg, hsotg->eps_in[epnum], |
9da51974 | 4939 | epnum, 1); |
c6f5c050 | 4940 | if (hsotg->eps_out[epnum]) |
1f91b4cc | 4941 | dwc2_hsotg_initep(hsotg, hsotg->eps_out[epnum], |
9da51974 | 4942 | epnum, 0); |
c6f5c050 | 4943 | } |
5b7d70c6 | 4944 | |
1f91b4cc | 4945 | dwc2_hsotg_dump(hsotg); |
5b7d70c6 | 4946 | |
5b7d70c6 | 4947 | return 0; |
5b7d70c6 BD |
4948 | } |
4949 | ||
8b9bc460 | 4950 | /** |
1f91b4cc | 4951 | * dwc2_hsotg_remove - remove function for hsotg driver |
6fb914d7 GT |
4952 | * @hsotg: Programming view of the DWC_otg controller |
4953 | * | |
8b9bc460 | 4954 | */ |
1f91b4cc | 4955 | int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 4956 | { |
0f91349b | 4957 | usb_del_gadget_udc(&hsotg->gadget); |
9bb073a0 | 4958 | dwc2_hsotg_ep_free_request(&hsotg->eps_out[0]->ep, hsotg->ctrl_req); |
31ee04de | 4959 | |
5b7d70c6 BD |
4960 | return 0; |
4961 | } | |
4962 | ||
1f91b4cc | 4963 | int dwc2_hsotg_suspend(struct dwc2_hsotg *hsotg) |
b83e333a | 4964 | { |
b83e333a | 4965 | unsigned long flags; |
b83e333a | 4966 | |
9e779778 | 4967 | if (hsotg->lx_state != DWC2_L0) |
09a75e85 | 4968 | return 0; |
9e779778 | 4969 | |
dc6e69e6 MS |
4970 | if (hsotg->driver) { |
4971 | int ep; | |
4972 | ||
b83e333a MS |
4973 | dev_info(hsotg->dev, "suspending usb gadget %s\n", |
4974 | hsotg->driver->driver.name); | |
4975 | ||
dc6e69e6 MS |
4976 | spin_lock_irqsave(&hsotg->lock, flags); |
4977 | if (hsotg->enabled) | |
1f91b4cc FB |
4978 | dwc2_hsotg_core_disconnect(hsotg); |
4979 | dwc2_hsotg_disconnect(hsotg); | |
dc6e69e6 MS |
4980 | hsotg->gadget.speed = USB_SPEED_UNKNOWN; |
4981 | spin_unlock_irqrestore(&hsotg->lock, flags); | |
b83e333a | 4982 | |
c6f5c050 MYK |
4983 | for (ep = 0; ep < hsotg->num_of_eps; ep++) { |
4984 | if (hsotg->eps_in[ep]) | |
4fe4f9fe | 4985 | dwc2_hsotg_ep_disable_lock(&hsotg->eps_in[ep]->ep); |
c6f5c050 | 4986 | if (hsotg->eps_out[ep]) |
4fe4f9fe | 4987 | dwc2_hsotg_ep_disable_lock(&hsotg->eps_out[ep]->ep); |
c6f5c050 | 4988 | } |
b83e333a MS |
4989 | } |
4990 | ||
09a75e85 | 4991 | return 0; |
b83e333a MS |
4992 | } |
4993 | ||
1f91b4cc | 4994 | int dwc2_hsotg_resume(struct dwc2_hsotg *hsotg) |
b83e333a | 4995 | { |
b83e333a | 4996 | unsigned long flags; |
b83e333a | 4997 | |
9e779778 | 4998 | if (hsotg->lx_state == DWC2_L2) |
09a75e85 | 4999 | return 0; |
9e779778 | 5000 | |
b83e333a MS |
5001 | if (hsotg->driver) { |
5002 | dev_info(hsotg->dev, "resuming usb gadget %s\n", | |
5003 | hsotg->driver->driver.name); | |
d00b4142 | 5004 | |
dc6e69e6 | 5005 | spin_lock_irqsave(&hsotg->lock, flags); |
1f91b4cc | 5006 | dwc2_hsotg_core_init_disconnected(hsotg, false); |
66e77a24 RK |
5007 | if (hsotg->enabled) { |
5008 | /* Enable ACG feature in device mode,if supported */ | |
5009 | dwc2_enable_acg(hsotg); | |
1f91b4cc | 5010 | dwc2_hsotg_core_connect(hsotg); |
66e77a24 | 5011 | } |
dc6e69e6 MS |
5012 | spin_unlock_irqrestore(&hsotg->lock, flags); |
5013 | } | |
b83e333a | 5014 | |
09a75e85 | 5015 | return 0; |
b83e333a | 5016 | } |
58e52ff6 JY |
5017 | |
5018 | /** | |
5019 | * dwc2_backup_device_registers() - Backup controller device registers. | |
5020 | * When suspending usb bus, registers needs to be backuped | |
5021 | * if controller power is disabled once suspended. | |
5022 | * | |
5023 | * @hsotg: Programming view of the DWC_otg controller | |
5024 | */ | |
5025 | int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg) | |
5026 | { | |
5027 | struct dwc2_dregs_backup *dr; | |
5028 | int i; | |
5029 | ||
5030 | dev_dbg(hsotg->dev, "%s\n", __func__); | |
5031 | ||
5032 | /* Backup dev regs */ | |
5033 | dr = &hsotg->dr_backup; | |
5034 | ||
f25c42b8 GS |
5035 | dr->dcfg = dwc2_readl(hsotg, DCFG); |
5036 | dr->dctl = dwc2_readl(hsotg, DCTL); | |
5037 | dr->daintmsk = dwc2_readl(hsotg, DAINTMSK); | |
5038 | dr->diepmsk = dwc2_readl(hsotg, DIEPMSK); | |
5039 | dr->doepmsk = dwc2_readl(hsotg, DOEPMSK); | |
58e52ff6 JY |
5040 | |
5041 | for (i = 0; i < hsotg->num_of_eps; i++) { | |
5042 | /* Backup IN EPs */ | |
f25c42b8 | 5043 | dr->diepctl[i] = dwc2_readl(hsotg, DIEPCTL(i)); |
58e52ff6 JY |
5044 | |
5045 | /* Ensure DATA PID is correctly configured */ | |
5046 | if (dr->diepctl[i] & DXEPCTL_DPID) | |
5047 | dr->diepctl[i] |= DXEPCTL_SETD1PID; | |
5048 | else | |
5049 | dr->diepctl[i] |= DXEPCTL_SETD0PID; | |
5050 | ||
f25c42b8 GS |
5051 | dr->dieptsiz[i] = dwc2_readl(hsotg, DIEPTSIZ(i)); |
5052 | dr->diepdma[i] = dwc2_readl(hsotg, DIEPDMA(i)); | |
58e52ff6 JY |
5053 | |
5054 | /* Backup OUT EPs */ | |
f25c42b8 | 5055 | dr->doepctl[i] = dwc2_readl(hsotg, DOEPCTL(i)); |
58e52ff6 JY |
5056 | |
5057 | /* Ensure DATA PID is correctly configured */ | |
5058 | if (dr->doepctl[i] & DXEPCTL_DPID) | |
5059 | dr->doepctl[i] |= DXEPCTL_SETD1PID; | |
5060 | else | |
5061 | dr->doepctl[i] |= DXEPCTL_SETD0PID; | |
5062 | ||
f25c42b8 GS |
5063 | dr->doeptsiz[i] = dwc2_readl(hsotg, DOEPTSIZ(i)); |
5064 | dr->doepdma[i] = dwc2_readl(hsotg, DOEPDMA(i)); | |
5065 | dr->dtxfsiz[i] = dwc2_readl(hsotg, DPTXFSIZN(i)); | |
58e52ff6 JY |
5066 | } |
5067 | dr->valid = true; | |
5068 | return 0; | |
5069 | } | |
5070 | ||
5071 | /** | |
5072 | * dwc2_restore_device_registers() - Restore controller device registers. | |
5073 | * When resuming usb bus, device registers needs to be restored | |
5074 | * if controller power were disabled. | |
5075 | * | |
5076 | * @hsotg: Programming view of the DWC_otg controller | |
9a5d2816 VM |
5077 | * @remote_wakeup: Indicates whether resume is initiated by Device or Host. |
5078 | * | |
5079 | * Return: 0 if successful, negative error code otherwise | |
58e52ff6 | 5080 | */ |
9a5d2816 | 5081 | int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg, int remote_wakeup) |
58e52ff6 JY |
5082 | { |
5083 | struct dwc2_dregs_backup *dr; | |
58e52ff6 JY |
5084 | int i; |
5085 | ||
5086 | dev_dbg(hsotg->dev, "%s\n", __func__); | |
5087 | ||
5088 | /* Restore dev regs */ | |
5089 | dr = &hsotg->dr_backup; | |
5090 | if (!dr->valid) { | |
5091 | dev_err(hsotg->dev, "%s: no device registers to restore\n", | |
5092 | __func__); | |
5093 | return -EINVAL; | |
5094 | } | |
5095 | dr->valid = false; | |
5096 | ||
9a5d2816 | 5097 | if (!remote_wakeup) |
f25c42b8 | 5098 | dwc2_writel(hsotg, dr->dctl, DCTL); |
9a5d2816 | 5099 | |
f25c42b8 GS |
5100 | dwc2_writel(hsotg, dr->daintmsk, DAINTMSK); |
5101 | dwc2_writel(hsotg, dr->diepmsk, DIEPMSK); | |
5102 | dwc2_writel(hsotg, dr->doepmsk, DOEPMSK); | |
58e52ff6 JY |
5103 | |
5104 | for (i = 0; i < hsotg->num_of_eps; i++) { | |
5105 | /* Restore IN EPs */ | |
f25c42b8 GS |
5106 | dwc2_writel(hsotg, dr->dieptsiz[i], DIEPTSIZ(i)); |
5107 | dwc2_writel(hsotg, dr->diepdma[i], DIEPDMA(i)); | |
5108 | dwc2_writel(hsotg, dr->doeptsiz[i], DOEPTSIZ(i)); | |
9a5d2816 VM |
5109 | /** WA for enabled EPx's IN in DDMA mode. On entering to |
5110 | * hibernation wrong value read and saved from DIEPDMAx, | |
5111 | * as result BNA interrupt asserted on hibernation exit | |
5112 | * by restoring from saved area. | |
5113 | */ | |
5114 | if (hsotg->params.g_dma_desc && | |
5115 | (dr->diepctl[i] & DXEPCTL_EPENA)) | |
5116 | dr->diepdma[i] = hsotg->eps_in[i]->desc_list_dma; | |
f25c42b8 GS |
5117 | dwc2_writel(hsotg, dr->dtxfsiz[i], DPTXFSIZN(i)); |
5118 | dwc2_writel(hsotg, dr->diepctl[i], DIEPCTL(i)); | |
58e52ff6 | 5119 | /* Restore OUT EPs */ |
f25c42b8 | 5120 | dwc2_writel(hsotg, dr->doeptsiz[i], DOEPTSIZ(i)); |
9a5d2816 VM |
5121 | /* WA for enabled EPx's OUT in DDMA mode. On entering to |
5122 | * hibernation wrong value read and saved from DOEPDMAx, | |
5123 | * as result BNA interrupt asserted on hibernation exit | |
5124 | * by restoring from saved area. | |
5125 | */ | |
5126 | if (hsotg->params.g_dma_desc && | |
5127 | (dr->doepctl[i] & DXEPCTL_EPENA)) | |
5128 | dr->doepdma[i] = hsotg->eps_out[i]->desc_list_dma; | |
f25c42b8 GS |
5129 | dwc2_writel(hsotg, dr->doepdma[i], DOEPDMA(i)); |
5130 | dwc2_writel(hsotg, dr->doepctl[i], DOEPCTL(i)); | |
58e52ff6 JY |
5131 | } |
5132 | ||
58e52ff6 JY |
5133 | return 0; |
5134 | } | |
21b03405 SA |
5135 | |
5136 | /** | |
5137 | * dwc2_gadget_init_lpm - Configure the core to support LPM in device mode | |
5138 | * | |
5139 | * @hsotg: Programming view of DWC_otg controller | |
5140 | * | |
5141 | */ | |
5142 | void dwc2_gadget_init_lpm(struct dwc2_hsotg *hsotg) | |
5143 | { | |
5144 | u32 val; | |
5145 | ||
5146 | if (!hsotg->params.lpm) | |
5147 | return; | |
5148 | ||
5149 | val = GLPMCFG_LPMCAP | GLPMCFG_APPL1RES; | |
5150 | val |= hsotg->params.hird_threshold_en ? GLPMCFG_HIRD_THRES_EN : 0; | |
5151 | val |= hsotg->params.lpm_clock_gating ? GLPMCFG_ENBLSLPM : 0; | |
5152 | val |= hsotg->params.hird_threshold << GLPMCFG_HIRD_THRES_SHIFT; | |
5153 | val |= hsotg->params.besl ? GLPMCFG_ENBESL : 0; | |
46637565 | 5154 | val |= GLPMCFG_LPM_REJECT_CTRL_CONTROL; |
9aed8c08 | 5155 | val |= GLPMCFG_LPM_ACCEPT_CTRL_ISOC; |
f25c42b8 GS |
5156 | dwc2_writel(hsotg, val, GLPMCFG); |
5157 | dev_dbg(hsotg->dev, "GLPMCFG=0x%08x\n", dwc2_readl(hsotg, GLPMCFG)); | |
4abe4537 GT |
5158 | |
5159 | /* Unmask WKUP_ALERT Interrupt */ | |
5160 | if (hsotg->params.service_interval) | |
5161 | dwc2_set_bit(hsotg, GINTMSK2, GINTMSK2_WKUP_ALERT_INT_MSK); | |
21b03405 | 5162 | } |
c5c403dc | 5163 | |
15d9dbf8 GT |
5164 | /** |
5165 | * dwc2_gadget_program_ref_clk - Program GREFCLK register in device mode | |
5166 | * | |
5167 | * @hsotg: Programming view of DWC_otg controller | |
5168 | * | |
5169 | */ | |
5170 | void dwc2_gadget_program_ref_clk(struct dwc2_hsotg *hsotg) | |
5171 | { | |
5172 | u32 val = 0; | |
5173 | ||
5174 | val |= GREFCLK_REF_CLK_MODE; | |
5175 | val |= hsotg->params.ref_clk_per << GREFCLK_REFCLKPER_SHIFT; | |
5176 | val |= hsotg->params.sof_cnt_wkup_alert << | |
5177 | GREFCLK_SOF_CNT_WKUP_ALERT_SHIFT; | |
5178 | ||
5179 | dwc2_writel(hsotg, val, GREFCLK); | |
5180 | dev_dbg(hsotg->dev, "GREFCLK=0x%08x\n", dwc2_readl(hsotg, GREFCLK)); | |
5181 | } | |
5182 | ||
c5c403dc VM |
5183 | /** |
5184 | * dwc2_gadget_enter_hibernation() - Put controller in Hibernation. | |
5185 | * | |
5186 | * @hsotg: Programming view of the DWC_otg controller | |
5187 | * | |
5188 | * Return non-zero if failed to enter to hibernation. | |
5189 | */ | |
5190 | int dwc2_gadget_enter_hibernation(struct dwc2_hsotg *hsotg) | |
5191 | { | |
5192 | u32 gpwrdn; | |
5193 | int ret = 0; | |
5194 | ||
5195 | /* Change to L2(suspend) state */ | |
5196 | hsotg->lx_state = DWC2_L2; | |
5197 | dev_dbg(hsotg->dev, "Start of hibernation completed\n"); | |
5198 | ret = dwc2_backup_global_registers(hsotg); | |
5199 | if (ret) { | |
5200 | dev_err(hsotg->dev, "%s: failed to backup global registers\n", | |
5201 | __func__); | |
5202 | return ret; | |
5203 | } | |
5204 | ret = dwc2_backup_device_registers(hsotg); | |
5205 | if (ret) { | |
5206 | dev_err(hsotg->dev, "%s: failed to backup device registers\n", | |
5207 | __func__); | |
5208 | return ret; | |
5209 | } | |
5210 | ||
5211 | gpwrdn = GPWRDN_PWRDNRSTN; | |
5212 | gpwrdn |= GPWRDN_PMUACTV; | |
f25c42b8 | 5213 | dwc2_writel(hsotg, gpwrdn, GPWRDN); |
c5c403dc VM |
5214 | udelay(10); |
5215 | ||
5216 | /* Set flag to indicate that we are in hibernation */ | |
5217 | hsotg->hibernated = 1; | |
5218 | ||
5219 | /* Enable interrupts from wake up logic */ | |
f25c42b8 | 5220 | gpwrdn = dwc2_readl(hsotg, GPWRDN); |
c5c403dc | 5221 | gpwrdn |= GPWRDN_PMUINTSEL; |
f25c42b8 | 5222 | dwc2_writel(hsotg, gpwrdn, GPWRDN); |
c5c403dc VM |
5223 | udelay(10); |
5224 | ||
5225 | /* Unmask device mode interrupts in GPWRDN */ | |
f25c42b8 | 5226 | gpwrdn = dwc2_readl(hsotg, GPWRDN); |
c5c403dc VM |
5227 | gpwrdn |= GPWRDN_RST_DET_MSK; |
5228 | gpwrdn |= GPWRDN_LNSTSCHG_MSK; | |
5229 | gpwrdn |= GPWRDN_STS_CHGINT_MSK; | |
f25c42b8 | 5230 | dwc2_writel(hsotg, gpwrdn, GPWRDN); |
c5c403dc VM |
5231 | udelay(10); |
5232 | ||
5233 | /* Enable Power Down Clamp */ | |
f25c42b8 | 5234 | gpwrdn = dwc2_readl(hsotg, GPWRDN); |
c5c403dc | 5235 | gpwrdn |= GPWRDN_PWRDNCLMP; |
f25c42b8 | 5236 | dwc2_writel(hsotg, gpwrdn, GPWRDN); |
c5c403dc VM |
5237 | udelay(10); |
5238 | ||
5239 | /* Switch off VDD */ | |
f25c42b8 | 5240 | gpwrdn = dwc2_readl(hsotg, GPWRDN); |
c5c403dc | 5241 | gpwrdn |= GPWRDN_PWRDNSWTCH; |
f25c42b8 | 5242 | dwc2_writel(hsotg, gpwrdn, GPWRDN); |
c5c403dc VM |
5243 | udelay(10); |
5244 | ||
5245 | /* Save gpwrdn register for further usage if stschng interrupt */ | |
f25c42b8 | 5246 | hsotg->gr_backup.gpwrdn = dwc2_readl(hsotg, GPWRDN); |
c5c403dc VM |
5247 | dev_dbg(hsotg->dev, "Hibernation completed\n"); |
5248 | ||
5249 | return ret; | |
5250 | } | |
5251 | ||
5252 | /** | |
5253 | * dwc2_gadget_exit_hibernation() | |
5254 | * This function is for exiting from Device mode hibernation by host initiated | |
5255 | * resume/reset and device initiated remote-wakeup. | |
5256 | * | |
5257 | * @hsotg: Programming view of the DWC_otg controller | |
5258 | * @rem_wakeup: indicates whether resume is initiated by Device or Host. | |
6fb914d7 | 5259 | * @reset: indicates whether resume is initiated by Reset. |
c5c403dc VM |
5260 | * |
5261 | * Return non-zero if failed to exit from hibernation. | |
5262 | */ | |
5263 | int dwc2_gadget_exit_hibernation(struct dwc2_hsotg *hsotg, | |
5264 | int rem_wakeup, int reset) | |
5265 | { | |
5266 | u32 pcgcctl; | |
5267 | u32 gpwrdn; | |
5268 | u32 dctl; | |
5269 | int ret = 0; | |
5270 | struct dwc2_gregs_backup *gr; | |
5271 | struct dwc2_dregs_backup *dr; | |
5272 | ||
5273 | gr = &hsotg->gr_backup; | |
5274 | dr = &hsotg->dr_backup; | |
5275 | ||
5276 | if (!hsotg->hibernated) { | |
5277 | dev_dbg(hsotg->dev, "Already exited from Hibernation\n"); | |
5278 | return 1; | |
5279 | } | |
5280 | dev_dbg(hsotg->dev, | |
5281 | "%s: called with rem_wakeup = %d reset = %d\n", | |
5282 | __func__, rem_wakeup, reset); | |
5283 | ||
5284 | dwc2_hib_restore_common(hsotg, rem_wakeup, 0); | |
5285 | ||
5286 | if (!reset) { | |
5287 | /* Clear all pending interupts */ | |
f25c42b8 | 5288 | dwc2_writel(hsotg, 0xffffffff, GINTSTS); |
c5c403dc VM |
5289 | } |
5290 | ||
5291 | /* De-assert Restore */ | |
f25c42b8 | 5292 | gpwrdn = dwc2_readl(hsotg, GPWRDN); |
c5c403dc | 5293 | gpwrdn &= ~GPWRDN_RESTORE; |
f25c42b8 | 5294 | dwc2_writel(hsotg, gpwrdn, GPWRDN); |
c5c403dc VM |
5295 | udelay(10); |
5296 | ||
5297 | if (!rem_wakeup) { | |
f25c42b8 | 5298 | pcgcctl = dwc2_readl(hsotg, PCGCTL); |
c5c403dc | 5299 | pcgcctl &= ~PCGCTL_RSTPDWNMODULE; |
f25c42b8 | 5300 | dwc2_writel(hsotg, pcgcctl, PCGCTL); |
c5c403dc VM |
5301 | } |
5302 | ||
5303 | /* Restore GUSBCFG, DCFG and DCTL */ | |
f25c42b8 GS |
5304 | dwc2_writel(hsotg, gr->gusbcfg, GUSBCFG); |
5305 | dwc2_writel(hsotg, dr->dcfg, DCFG); | |
5306 | dwc2_writel(hsotg, dr->dctl, DCTL); | |
c5c403dc | 5307 | |
b29b494b AP |
5308 | /* On USB Reset, reset device address to zero */ |
5309 | if (reset) | |
5310 | dwc2_clear_bit(hsotg, DCFG, DCFG_DEVADDR_MASK); | |
5311 | ||
c5c403dc | 5312 | /* De-assert Wakeup Logic */ |
f25c42b8 | 5313 | gpwrdn = dwc2_readl(hsotg, GPWRDN); |
c5c403dc | 5314 | gpwrdn &= ~GPWRDN_PMUACTV; |
f25c42b8 | 5315 | dwc2_writel(hsotg, gpwrdn, GPWRDN); |
c5c403dc VM |
5316 | |
5317 | if (rem_wakeup) { | |
5318 | udelay(10); | |
5319 | /* Start Remote Wakeup Signaling */ | |
f25c42b8 | 5320 | dwc2_writel(hsotg, dr->dctl | DCTL_RMTWKUPSIG, DCTL); |
c5c403dc VM |
5321 | } else { |
5322 | udelay(50); | |
5323 | /* Set Device programming done bit */ | |
f25c42b8 | 5324 | dctl = dwc2_readl(hsotg, DCTL); |
c5c403dc | 5325 | dctl |= DCTL_PWRONPRGDONE; |
f25c42b8 | 5326 | dwc2_writel(hsotg, dctl, DCTL); |
c5c403dc VM |
5327 | } |
5328 | /* Wait for interrupts which must be cleared */ | |
5329 | mdelay(2); | |
5330 | /* Clear all pending interupts */ | |
f25c42b8 | 5331 | dwc2_writel(hsotg, 0xffffffff, GINTSTS); |
c5c403dc VM |
5332 | |
5333 | /* Restore global registers */ | |
5334 | ret = dwc2_restore_global_registers(hsotg); | |
5335 | if (ret) { | |
5336 | dev_err(hsotg->dev, "%s: failed to restore registers\n", | |
5337 | __func__); | |
5338 | return ret; | |
5339 | } | |
5340 | ||
5341 | /* Restore device registers */ | |
5342 | ret = dwc2_restore_device_registers(hsotg, rem_wakeup); | |
5343 | if (ret) { | |
5344 | dev_err(hsotg->dev, "%s: failed to restore device registers\n", | |
5345 | __func__); | |
5346 | return ret; | |
5347 | } | |
5348 | ||
5349 | if (rem_wakeup) { | |
5350 | mdelay(10); | |
f25c42b8 | 5351 | dctl = dwc2_readl(hsotg, DCTL); |
c5c403dc | 5352 | dctl &= ~DCTL_RMTWKUPSIG; |
f25c42b8 | 5353 | dwc2_writel(hsotg, dctl, DCTL); |
c5c403dc VM |
5354 | } |
5355 | ||
5356 | hsotg->hibernated = 0; | |
5357 | hsotg->lx_state = DWC2_L0; | |
5358 | dev_dbg(hsotg->dev, "Hibernation recovery completes here\n"); | |
5359 | ||
5360 | return ret; | |
5361 | } | |
be2b960e AP |
5362 | |
5363 | /** | |
5364 | * dwc2_gadget_enter_partial_power_down() - Put controller in partial | |
5365 | * power down. | |
5366 | * | |
5367 | * @hsotg: Programming view of the DWC_otg controller | |
5368 | * | |
5369 | * Return: non-zero if failed to enter device partial power down. | |
5370 | * | |
5371 | * This function is for entering device mode partial power down. | |
5372 | */ | |
5373 | int dwc2_gadget_enter_partial_power_down(struct dwc2_hsotg *hsotg) | |
5374 | { | |
5375 | u32 pcgcctl; | |
5376 | int ret = 0; | |
5377 | ||
5378 | dev_dbg(hsotg->dev, "Entering device partial power down started.\n"); | |
5379 | ||
5380 | /* Backup all registers */ | |
5381 | ret = dwc2_backup_global_registers(hsotg); | |
5382 | if (ret) { | |
5383 | dev_err(hsotg->dev, "%s: failed to backup global registers\n", | |
5384 | __func__); | |
5385 | return ret; | |
5386 | } | |
5387 | ||
5388 | ret = dwc2_backup_device_registers(hsotg); | |
5389 | if (ret) { | |
5390 | dev_err(hsotg->dev, "%s: failed to backup device registers\n", | |
5391 | __func__); | |
5392 | return ret; | |
5393 | } | |
5394 | ||
5395 | /* | |
5396 | * Clear any pending interrupts since dwc2 will not be able to | |
5397 | * clear them after entering partial_power_down. | |
5398 | */ | |
5399 | dwc2_writel(hsotg, 0xffffffff, GINTSTS); | |
5400 | ||
5401 | /* Put the controller in low power state */ | |
5402 | pcgcctl = dwc2_readl(hsotg, PCGCTL); | |
5403 | ||
5404 | pcgcctl |= PCGCTL_PWRCLMP; | |
5405 | dwc2_writel(hsotg, pcgcctl, PCGCTL); | |
5406 | udelay(5); | |
5407 | ||
5408 | pcgcctl |= PCGCTL_RSTPDWNMODULE; | |
5409 | dwc2_writel(hsotg, pcgcctl, PCGCTL); | |
5410 | udelay(5); | |
5411 | ||
5412 | pcgcctl |= PCGCTL_STOPPCLK; | |
5413 | dwc2_writel(hsotg, pcgcctl, PCGCTL); | |
5414 | ||
5415 | /* Set in_ppd flag to 1 as here core enters suspend. */ | |
5416 | hsotg->in_ppd = 1; | |
5417 | hsotg->lx_state = DWC2_L2; | |
5418 | ||
5419 | dev_dbg(hsotg->dev, "Entering device partial power down completed.\n"); | |
5420 | ||
5421 | return ret; | |
5422 | } | |
5423 | ||
5424 | /* | |
5425 | * dwc2_gadget_exit_partial_power_down() - Exit controller from device partial | |
5426 | * power down. | |
5427 | * | |
5428 | * @hsotg: Programming view of the DWC_otg controller | |
5429 | * @restore: indicates whether need to restore the registers or not. | |
5430 | * | |
5431 | * Return: non-zero if failed to exit device partial power down. | |
5432 | * | |
5433 | * This function is for exiting from device mode partial power down. | |
5434 | */ | |
5435 | int dwc2_gadget_exit_partial_power_down(struct dwc2_hsotg *hsotg, | |
5436 | bool restore) | |
5437 | { | |
5438 | u32 pcgcctl; | |
5439 | u32 dctl; | |
5440 | struct dwc2_dregs_backup *dr; | |
5441 | int ret = 0; | |
5442 | ||
5443 | dr = &hsotg->dr_backup; | |
5444 | ||
5445 | dev_dbg(hsotg->dev, "Exiting device partial Power Down started.\n"); | |
5446 | ||
5447 | pcgcctl = dwc2_readl(hsotg, PCGCTL); | |
5448 | pcgcctl &= ~PCGCTL_STOPPCLK; | |
5449 | dwc2_writel(hsotg, pcgcctl, PCGCTL); | |
5450 | ||
5451 | pcgcctl = dwc2_readl(hsotg, PCGCTL); | |
5452 | pcgcctl &= ~PCGCTL_PWRCLMP; | |
5453 | dwc2_writel(hsotg, pcgcctl, PCGCTL); | |
5454 | ||
5455 | pcgcctl = dwc2_readl(hsotg, PCGCTL); | |
5456 | pcgcctl &= ~PCGCTL_RSTPDWNMODULE; | |
5457 | dwc2_writel(hsotg, pcgcctl, PCGCTL); | |
5458 | ||
5459 | udelay(100); | |
5460 | if (restore) { | |
5461 | ret = dwc2_restore_global_registers(hsotg); | |
5462 | if (ret) { | |
5463 | dev_err(hsotg->dev, "%s: failed to restore registers\n", | |
5464 | __func__); | |
5465 | return ret; | |
5466 | } | |
5467 | /* Restore DCFG */ | |
5468 | dwc2_writel(hsotg, dr->dcfg, DCFG); | |
5469 | ||
5470 | ret = dwc2_restore_device_registers(hsotg, 0); | |
5471 | if (ret) { | |
5472 | dev_err(hsotg->dev, "%s: failed to restore device registers\n", | |
5473 | __func__); | |
5474 | return ret; | |
5475 | } | |
5476 | } | |
5477 | ||
5478 | /* Set the Power-On Programming done bit */ | |
5479 | dctl = dwc2_readl(hsotg, DCTL); | |
5480 | dctl |= DCTL_PWRONPRGDONE; | |
5481 | dwc2_writel(hsotg, dctl, DCTL); | |
5482 | ||
5483 | /* Set in_ppd flag to 0 as here core exits from suspend. */ | |
5484 | hsotg->in_ppd = 0; | |
5485 | hsotg->lx_state = DWC2_L0; | |
5486 | ||
5487 | dev_dbg(hsotg->dev, "Exiting device partial Power Down completed.\n"); | |
5488 | return ret; | |
5489 | } | |
012466fc AP |
5490 | |
5491 | /** | |
5492 | * dwc2_gadget_enter_clock_gating() - Put controller in clock gating. | |
5493 | * | |
5494 | * @hsotg: Programming view of the DWC_otg controller | |
5495 | * | |
5496 | * Return: non-zero if failed to enter device partial power down. | |
5497 | * | |
5498 | * This function is for entering device mode clock gating. | |
5499 | */ | |
5500 | void dwc2_gadget_enter_clock_gating(struct dwc2_hsotg *hsotg) | |
5501 | { | |
5502 | u32 pcgctl; | |
5503 | ||
5504 | dev_dbg(hsotg->dev, "Entering device clock gating.\n"); | |
5505 | ||
5506 | /* Set the Phy Clock bit as suspend is received. */ | |
5507 | pcgctl = dwc2_readl(hsotg, PCGCTL); | |
5508 | pcgctl |= PCGCTL_STOPPCLK; | |
5509 | dwc2_writel(hsotg, pcgctl, PCGCTL); | |
5510 | udelay(5); | |
5511 | ||
5512 | /* Set the Gate hclk as suspend is received. */ | |
5513 | pcgctl = dwc2_readl(hsotg, PCGCTL); | |
5514 | pcgctl |= PCGCTL_GATEHCLK; | |
5515 | dwc2_writel(hsotg, pcgctl, PCGCTL); | |
5516 | udelay(5); | |
5517 | ||
5518 | hsotg->lx_state = DWC2_L2; | |
5519 | hsotg->bus_suspended = true; | |
5520 | } | |
5521 | ||
5522 | /* | |
5523 | * dwc2_gadget_exit_clock_gating() - Exit controller from device clock gating. | |
5524 | * | |
5525 | * @hsotg: Programming view of the DWC_otg controller | |
5526 | * @rem_wakeup: indicates whether remote wake up is enabled. | |
5527 | * | |
5528 | * This function is for exiting from device mode clock gating. | |
5529 | */ | |
5530 | void dwc2_gadget_exit_clock_gating(struct dwc2_hsotg *hsotg, int rem_wakeup) | |
5531 | { | |
5532 | u32 pcgctl; | |
5533 | u32 dctl; | |
5534 | ||
5535 | dev_dbg(hsotg->dev, "Exiting device clock gating.\n"); | |
5536 | ||
5537 | /* Clear the Gate hclk. */ | |
5538 | pcgctl = dwc2_readl(hsotg, PCGCTL); | |
5539 | pcgctl &= ~PCGCTL_GATEHCLK; | |
5540 | dwc2_writel(hsotg, pcgctl, PCGCTL); | |
5541 | udelay(5); | |
5542 | ||
5543 | /* Phy Clock bit. */ | |
5544 | pcgctl = dwc2_readl(hsotg, PCGCTL); | |
5545 | pcgctl &= ~PCGCTL_STOPPCLK; | |
5546 | dwc2_writel(hsotg, pcgctl, PCGCTL); | |
5547 | udelay(5); | |
5548 | ||
5549 | if (rem_wakeup) { | |
5550 | /* Set Remote Wakeup Signaling */ | |
5551 | dctl = dwc2_readl(hsotg, DCTL); | |
5552 | dctl |= DCTL_RMTWKUPSIG; | |
5553 | dwc2_writel(hsotg, dctl, DCTL); | |
5554 | } | |
5555 | ||
5556 | /* Change to L0 state */ | |
5557 | call_gadget(hsotg, resume); | |
5558 | hsotg->lx_state = DWC2_L0; | |
5559 | hsotg->bus_suspended = false; | |
5560 | } |