Commit | Line | Data |
---|---|---|
8b9bc460 | 1 | /** |
dfbc6fa3 AT |
2 | * Copyright (c) 2011 Samsung Electronics Co., Ltd. |
3 | * http://www.samsung.com | |
5b7d70c6 BD |
4 | * |
5 | * Copyright 2008 Openmoko, Inc. | |
6 | * Copyright 2008 Simtec Electronics | |
7 | * Ben Dooks <ben@simtec.co.uk> | |
8 | * http://armlinux.simtec.co.uk/ | |
9 | * | |
10 | * S3C USB2.0 High-speed / OtG driver | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License version 2 as | |
14 | * published by the Free Software Foundation. | |
8b9bc460 | 15 | */ |
5b7d70c6 BD |
16 | |
17 | #include <linux/kernel.h> | |
18 | #include <linux/module.h> | |
19 | #include <linux/spinlock.h> | |
20 | #include <linux/interrupt.h> | |
21 | #include <linux/platform_device.h> | |
22 | #include <linux/dma-mapping.h> | |
7ad8096e | 23 | #include <linux/mutex.h> |
5b7d70c6 BD |
24 | #include <linux/seq_file.h> |
25 | #include <linux/delay.h> | |
26 | #include <linux/io.h> | |
5a0e3ad6 | 27 | #include <linux/slab.h> |
e50bf385 | 28 | #include <linux/clk.h> |
fc9a731e | 29 | #include <linux/regulator/consumer.h> |
c50f056c | 30 | #include <linux/of_platform.h> |
74084844 | 31 | #include <linux/phy/phy.h> |
5b7d70c6 BD |
32 | |
33 | #include <linux/usb/ch9.h> | |
34 | #include <linux/usb/gadget.h> | |
b2e587db | 35 | #include <linux/usb/phy.h> |
126625e1 | 36 | #include <linux/platform_data/s3c-hsotg.h> |
5b7d70c6 | 37 | |
f7c0b143 | 38 | #include "core.h" |
941fcce4 | 39 | #include "hw.h" |
5b7d70c6 BD |
40 | |
41 | /* conversion functions */ | |
1f91b4cc | 42 | static inline struct dwc2_hsotg_req *our_req(struct usb_request *req) |
5b7d70c6 | 43 | { |
1f91b4cc | 44 | return container_of(req, struct dwc2_hsotg_req, req); |
5b7d70c6 BD |
45 | } |
46 | ||
1f91b4cc | 47 | static inline struct dwc2_hsotg_ep *our_ep(struct usb_ep *ep) |
5b7d70c6 | 48 | { |
1f91b4cc | 49 | return container_of(ep, struct dwc2_hsotg_ep, ep); |
5b7d70c6 BD |
50 | } |
51 | ||
941fcce4 | 52 | static inline struct dwc2_hsotg *to_hsotg(struct usb_gadget *gadget) |
5b7d70c6 | 53 | { |
941fcce4 | 54 | return container_of(gadget, struct dwc2_hsotg, gadget); |
5b7d70c6 BD |
55 | } |
56 | ||
57 | static inline void __orr32(void __iomem *ptr, u32 val) | |
58 | { | |
95c8bc36 | 59 | dwc2_writel(dwc2_readl(ptr) | val, ptr); |
5b7d70c6 BD |
60 | } |
61 | ||
62 | static inline void __bic32(void __iomem *ptr, u32 val) | |
63 | { | |
95c8bc36 | 64 | dwc2_writel(dwc2_readl(ptr) & ~val, ptr); |
5b7d70c6 BD |
65 | } |
66 | ||
1f91b4cc | 67 | static inline struct dwc2_hsotg_ep *index_to_ep(struct dwc2_hsotg *hsotg, |
c6f5c050 MYK |
68 | u32 ep_index, u32 dir_in) |
69 | { | |
70 | if (dir_in) | |
71 | return hsotg->eps_in[ep_index]; | |
72 | else | |
73 | return hsotg->eps_out[ep_index]; | |
74 | } | |
75 | ||
997f4f81 | 76 | /* forward declaration of functions */ |
1f91b4cc | 77 | static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg); |
5b7d70c6 BD |
78 | |
79 | /** | |
80 | * using_dma - return the DMA status of the driver. | |
81 | * @hsotg: The driver state. | |
82 | * | |
83 | * Return true if we're using DMA. | |
84 | * | |
85 | * Currently, we have the DMA support code worked into everywhere | |
86 | * that needs it, but the AMBA DMA implementation in the hardware can | |
87 | * only DMA from 32bit aligned addresses. This means that gadgets such | |
88 | * as the CDC Ethernet cannot work as they often pass packets which are | |
89 | * not 32bit aligned. | |
90 | * | |
91 | * Unfortunately the choice to use DMA or not is global to the controller | |
92 | * and seems to be only settable when the controller is being put through | |
93 | * a core reset. This means we either need to fix the gadgets to take | |
94 | * account of DMA alignment, or add bounce buffers (yuerk). | |
95 | * | |
edd74be8 | 96 | * g_using_dma is set depending on dts flag. |
5b7d70c6 | 97 | */ |
941fcce4 | 98 | static inline bool using_dma(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 99 | { |
edd74be8 | 100 | return hsotg->g_using_dma; |
5b7d70c6 BD |
101 | } |
102 | ||
103 | /** | |
1f91b4cc | 104 | * dwc2_hsotg_en_gsint - enable one or more of the general interrupt |
5b7d70c6 BD |
105 | * @hsotg: The device state |
106 | * @ints: A bitmask of the interrupts to enable | |
107 | */ | |
1f91b4cc | 108 | static void dwc2_hsotg_en_gsint(struct dwc2_hsotg *hsotg, u32 ints) |
5b7d70c6 | 109 | { |
95c8bc36 | 110 | u32 gsintmsk = dwc2_readl(hsotg->regs + GINTMSK); |
5b7d70c6 BD |
111 | u32 new_gsintmsk; |
112 | ||
113 | new_gsintmsk = gsintmsk | ints; | |
114 | ||
115 | if (new_gsintmsk != gsintmsk) { | |
116 | dev_dbg(hsotg->dev, "gsintmsk now 0x%08x\n", new_gsintmsk); | |
95c8bc36 | 117 | dwc2_writel(new_gsintmsk, hsotg->regs + GINTMSK); |
5b7d70c6 BD |
118 | } |
119 | } | |
120 | ||
121 | /** | |
1f91b4cc | 122 | * dwc2_hsotg_disable_gsint - disable one or more of the general interrupt |
5b7d70c6 BD |
123 | * @hsotg: The device state |
124 | * @ints: A bitmask of the interrupts to enable | |
125 | */ | |
1f91b4cc | 126 | static void dwc2_hsotg_disable_gsint(struct dwc2_hsotg *hsotg, u32 ints) |
5b7d70c6 | 127 | { |
95c8bc36 | 128 | u32 gsintmsk = dwc2_readl(hsotg->regs + GINTMSK); |
5b7d70c6 BD |
129 | u32 new_gsintmsk; |
130 | ||
131 | new_gsintmsk = gsintmsk & ~ints; | |
132 | ||
133 | if (new_gsintmsk != gsintmsk) | |
95c8bc36 | 134 | dwc2_writel(new_gsintmsk, hsotg->regs + GINTMSK); |
5b7d70c6 BD |
135 | } |
136 | ||
137 | /** | |
1f91b4cc | 138 | * dwc2_hsotg_ctrl_epint - enable/disable an endpoint irq |
5b7d70c6 BD |
139 | * @hsotg: The device state |
140 | * @ep: The endpoint index | |
141 | * @dir_in: True if direction is in. | |
142 | * @en: The enable value, true to enable | |
143 | * | |
144 | * Set or clear the mask for an individual endpoint's interrupt | |
145 | * request. | |
146 | */ | |
1f91b4cc | 147 | static void dwc2_hsotg_ctrl_epint(struct dwc2_hsotg *hsotg, |
5b7d70c6 BD |
148 | unsigned int ep, unsigned int dir_in, |
149 | unsigned int en) | |
150 | { | |
151 | unsigned long flags; | |
152 | u32 bit = 1 << ep; | |
153 | u32 daint; | |
154 | ||
155 | if (!dir_in) | |
156 | bit <<= 16; | |
157 | ||
158 | local_irq_save(flags); | |
95c8bc36 | 159 | daint = dwc2_readl(hsotg->regs + DAINTMSK); |
5b7d70c6 BD |
160 | if (en) |
161 | daint |= bit; | |
162 | else | |
163 | daint &= ~bit; | |
95c8bc36 | 164 | dwc2_writel(daint, hsotg->regs + DAINTMSK); |
5b7d70c6 BD |
165 | local_irq_restore(flags); |
166 | } | |
167 | ||
168 | /** | |
1f91b4cc | 169 | * dwc2_hsotg_init_fifo - initialise non-periodic FIFOs |
5b7d70c6 BD |
170 | * @hsotg: The device instance. |
171 | */ | |
1f91b4cc | 172 | static void dwc2_hsotg_init_fifo(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 173 | { |
0f002d20 BD |
174 | unsigned int ep; |
175 | unsigned int addr; | |
1703a6d3 | 176 | int timeout; |
0f002d20 BD |
177 | u32 val; |
178 | ||
7fcbc95c GH |
179 | /* Reset fifo map if not correctly cleared during previous session */ |
180 | WARN_ON(hsotg->fifo_map); | |
181 | hsotg->fifo_map = 0; | |
182 | ||
0a176279 | 183 | /* set RX/NPTX FIFO sizes */ |
95c8bc36 AS |
184 | dwc2_writel(hsotg->g_rx_fifo_sz, hsotg->regs + GRXFSIZ); |
185 | dwc2_writel((hsotg->g_rx_fifo_sz << FIFOSIZE_STARTADDR_SHIFT) | | |
0a176279 GH |
186 | (hsotg->g_np_g_tx_fifo_sz << FIFOSIZE_DEPTH_SHIFT), |
187 | hsotg->regs + GNPTXFSIZ); | |
0f002d20 | 188 | |
8b9bc460 LM |
189 | /* |
190 | * arange all the rest of the TX FIFOs, as some versions of this | |
0f002d20 BD |
191 | * block have overlapping default addresses. This also ensures |
192 | * that if the settings have been changed, then they are set to | |
8b9bc460 LM |
193 | * known values. |
194 | */ | |
0f002d20 BD |
195 | |
196 | /* start at the end of the GNPTXFSIZ, rounded up */ | |
0a176279 | 197 | addr = hsotg->g_rx_fifo_sz + hsotg->g_np_g_tx_fifo_sz; |
0f002d20 | 198 | |
8b9bc460 | 199 | /* |
0a176279 | 200 | * Configure fifos sizes from provided configuration and assign |
b203d0a2 RB |
201 | * them to endpoints dynamically according to maxpacket size value of |
202 | * given endpoint. | |
8b9bc460 | 203 | */ |
0a176279 GH |
204 | for (ep = 1; ep < MAX_EPS_CHANNELS; ep++) { |
205 | if (!hsotg->g_tx_fifo_sz[ep]) | |
206 | continue; | |
0f002d20 | 207 | val = addr; |
0a176279 GH |
208 | val |= hsotg->g_tx_fifo_sz[ep] << FIFOSIZE_DEPTH_SHIFT; |
209 | WARN_ONCE(addr + hsotg->g_tx_fifo_sz[ep] > hsotg->fifo_mem, | |
cff9eb75 | 210 | "insufficient fifo memory"); |
0a176279 | 211 | addr += hsotg->g_tx_fifo_sz[ep]; |
0f002d20 | 212 | |
95c8bc36 | 213 | dwc2_writel(val, hsotg->regs + DPTXFSIZN(ep)); |
0f002d20 | 214 | } |
1703a6d3 | 215 | |
8b9bc460 LM |
216 | /* |
217 | * according to p428 of the design guide, we need to ensure that | |
218 | * all fifos are flushed before continuing | |
219 | */ | |
1703a6d3 | 220 | |
95c8bc36 | 221 | dwc2_writel(GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH | |
47a1685f | 222 | GRSTCTL_RXFFLSH, hsotg->regs + GRSTCTL); |
1703a6d3 BD |
223 | |
224 | /* wait until the fifos are both flushed */ | |
225 | timeout = 100; | |
226 | while (1) { | |
95c8bc36 | 227 | val = dwc2_readl(hsotg->regs + GRSTCTL); |
1703a6d3 | 228 | |
47a1685f | 229 | if ((val & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH)) == 0) |
1703a6d3 BD |
230 | break; |
231 | ||
232 | if (--timeout == 0) { | |
233 | dev_err(hsotg->dev, | |
234 | "%s: timeout flushing fifos (GRSTCTL=%08x)\n", | |
235 | __func__, val); | |
48b20bcb | 236 | break; |
1703a6d3 BD |
237 | } |
238 | ||
239 | udelay(1); | |
240 | } | |
241 | ||
242 | dev_dbg(hsotg->dev, "FIFOs reset, timeout at %d\n", timeout); | |
5b7d70c6 BD |
243 | } |
244 | ||
245 | /** | |
246 | * @ep: USB endpoint to allocate request for. | |
247 | * @flags: Allocation flags | |
248 | * | |
249 | * Allocate a new USB request structure appropriate for the specified endpoint | |
250 | */ | |
1f91b4cc | 251 | static struct usb_request *dwc2_hsotg_ep_alloc_request(struct usb_ep *ep, |
0978f8c5 | 252 | gfp_t flags) |
5b7d70c6 | 253 | { |
1f91b4cc | 254 | struct dwc2_hsotg_req *req; |
5b7d70c6 | 255 | |
1f91b4cc | 256 | req = kzalloc(sizeof(struct dwc2_hsotg_req), flags); |
5b7d70c6 BD |
257 | if (!req) |
258 | return NULL; | |
259 | ||
260 | INIT_LIST_HEAD(&req->queue); | |
261 | ||
5b7d70c6 BD |
262 | return &req->req; |
263 | } | |
264 | ||
265 | /** | |
266 | * is_ep_periodic - return true if the endpoint is in periodic mode. | |
267 | * @hs_ep: The endpoint to query. | |
268 | * | |
269 | * Returns true if the endpoint is in periodic mode, meaning it is being | |
270 | * used for an Interrupt or ISO transfer. | |
271 | */ | |
1f91b4cc | 272 | static inline int is_ep_periodic(struct dwc2_hsotg_ep *hs_ep) |
5b7d70c6 BD |
273 | { |
274 | return hs_ep->periodic; | |
275 | } | |
276 | ||
277 | /** | |
1f91b4cc | 278 | * dwc2_hsotg_unmap_dma - unmap the DMA memory being used for the request |
5b7d70c6 BD |
279 | * @hsotg: The device state. |
280 | * @hs_ep: The endpoint for the request | |
281 | * @hs_req: The request being processed. | |
282 | * | |
1f91b4cc | 283 | * This is the reverse of dwc2_hsotg_map_dma(), called for the completion |
5b7d70c6 | 284 | * of a request to ensure the buffer is ready for access by the caller. |
8b9bc460 | 285 | */ |
1f91b4cc FB |
286 | static void dwc2_hsotg_unmap_dma(struct dwc2_hsotg *hsotg, |
287 | struct dwc2_hsotg_ep *hs_ep, | |
288 | struct dwc2_hsotg_req *hs_req) | |
5b7d70c6 BD |
289 | { |
290 | struct usb_request *req = &hs_req->req; | |
5b7d70c6 BD |
291 | |
292 | /* ignore this if we're not moving any data */ | |
293 | if (hs_req->req.length == 0) | |
294 | return; | |
295 | ||
17d966a3 | 296 | usb_gadget_unmap_request(&hsotg->gadget, req, hs_ep->dir_in); |
5b7d70c6 BD |
297 | } |
298 | ||
299 | /** | |
1f91b4cc | 300 | * dwc2_hsotg_write_fifo - write packet Data to the TxFIFO |
5b7d70c6 BD |
301 | * @hsotg: The controller state. |
302 | * @hs_ep: The endpoint we're going to write for. | |
303 | * @hs_req: The request to write data for. | |
304 | * | |
305 | * This is called when the TxFIFO has some space in it to hold a new | |
306 | * transmission and we have something to give it. The actual setup of | |
307 | * the data size is done elsewhere, so all we have to do is to actually | |
308 | * write the data. | |
309 | * | |
310 | * The return value is zero if there is more space (or nothing was done) | |
311 | * otherwise -ENOSPC is returned if the FIFO space was used up. | |
312 | * | |
313 | * This routine is only needed for PIO | |
8b9bc460 | 314 | */ |
1f91b4cc FB |
315 | static int dwc2_hsotg_write_fifo(struct dwc2_hsotg *hsotg, |
316 | struct dwc2_hsotg_ep *hs_ep, | |
317 | struct dwc2_hsotg_req *hs_req) | |
5b7d70c6 BD |
318 | { |
319 | bool periodic = is_ep_periodic(hs_ep); | |
95c8bc36 | 320 | u32 gnptxsts = dwc2_readl(hsotg->regs + GNPTXSTS); |
5b7d70c6 BD |
321 | int buf_pos = hs_req->req.actual; |
322 | int to_write = hs_ep->size_loaded; | |
323 | void *data; | |
324 | int can_write; | |
325 | int pkt_round; | |
4fca54aa | 326 | int max_transfer; |
5b7d70c6 BD |
327 | |
328 | to_write -= (buf_pos - hs_ep->last_load); | |
329 | ||
330 | /* if there's nothing to write, get out early */ | |
331 | if (to_write == 0) | |
332 | return 0; | |
333 | ||
10aebc77 | 334 | if (periodic && !hsotg->dedicated_fifos) { |
95c8bc36 | 335 | u32 epsize = dwc2_readl(hsotg->regs + DIEPTSIZ(hs_ep->index)); |
5b7d70c6 BD |
336 | int size_left; |
337 | int size_done; | |
338 | ||
8b9bc460 LM |
339 | /* |
340 | * work out how much data was loaded so we can calculate | |
341 | * how much data is left in the fifo. | |
342 | */ | |
5b7d70c6 | 343 | |
47a1685f | 344 | size_left = DXEPTSIZ_XFERSIZE_GET(epsize); |
5b7d70c6 | 345 | |
8b9bc460 LM |
346 | /* |
347 | * if shared fifo, we cannot write anything until the | |
e7a9ff54 BD |
348 | * previous data has been completely sent. |
349 | */ | |
350 | if (hs_ep->fifo_load != 0) { | |
1f91b4cc | 351 | dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP); |
e7a9ff54 BD |
352 | return -ENOSPC; |
353 | } | |
354 | ||
5b7d70c6 BD |
355 | dev_dbg(hsotg->dev, "%s: left=%d, load=%d, fifo=%d, size %d\n", |
356 | __func__, size_left, | |
357 | hs_ep->size_loaded, hs_ep->fifo_load, hs_ep->fifo_size); | |
358 | ||
359 | /* how much of the data has moved */ | |
360 | size_done = hs_ep->size_loaded - size_left; | |
361 | ||
362 | /* how much data is left in the fifo */ | |
363 | can_write = hs_ep->fifo_load - size_done; | |
364 | dev_dbg(hsotg->dev, "%s: => can_write1=%d\n", | |
365 | __func__, can_write); | |
366 | ||
367 | can_write = hs_ep->fifo_size - can_write; | |
368 | dev_dbg(hsotg->dev, "%s: => can_write2=%d\n", | |
369 | __func__, can_write); | |
370 | ||
371 | if (can_write <= 0) { | |
1f91b4cc | 372 | dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP); |
5b7d70c6 BD |
373 | return -ENOSPC; |
374 | } | |
10aebc77 | 375 | } else if (hsotg->dedicated_fifos && hs_ep->index != 0) { |
95c8bc36 | 376 | can_write = dwc2_readl(hsotg->regs + DTXFSTS(hs_ep->index)); |
10aebc77 BD |
377 | |
378 | can_write &= 0xffff; | |
379 | can_write *= 4; | |
5b7d70c6 | 380 | } else { |
47a1685f | 381 | if (GNPTXSTS_NP_TXQ_SPC_AVAIL_GET(gnptxsts) == 0) { |
5b7d70c6 BD |
382 | dev_dbg(hsotg->dev, |
383 | "%s: no queue slots available (0x%08x)\n", | |
384 | __func__, gnptxsts); | |
385 | ||
1f91b4cc | 386 | dwc2_hsotg_en_gsint(hsotg, GINTSTS_NPTXFEMP); |
5b7d70c6 BD |
387 | return -ENOSPC; |
388 | } | |
389 | ||
47a1685f | 390 | can_write = GNPTXSTS_NP_TXF_SPC_AVAIL_GET(gnptxsts); |
679f9b7c | 391 | can_write *= 4; /* fifo size is in 32bit quantities. */ |
5b7d70c6 BD |
392 | } |
393 | ||
4fca54aa RB |
394 | max_transfer = hs_ep->ep.maxpacket * hs_ep->mc; |
395 | ||
396 | dev_dbg(hsotg->dev, "%s: GNPTXSTS=%08x, can=%d, to=%d, max_transfer %d\n", | |
397 | __func__, gnptxsts, can_write, to_write, max_transfer); | |
5b7d70c6 | 398 | |
8b9bc460 LM |
399 | /* |
400 | * limit to 512 bytes of data, it seems at least on the non-periodic | |
5b7d70c6 BD |
401 | * FIFO, requests of >512 cause the endpoint to get stuck with a |
402 | * fragment of the end of the transfer in it. | |
403 | */ | |
811f3303 | 404 | if (can_write > 512 && !periodic) |
5b7d70c6 BD |
405 | can_write = 512; |
406 | ||
8b9bc460 LM |
407 | /* |
408 | * limit the write to one max-packet size worth of data, but allow | |
03e10e5a | 409 | * the transfer to return that it did not run out of fifo space |
8b9bc460 LM |
410 | * doing it. |
411 | */ | |
4fca54aa RB |
412 | if (to_write > max_transfer) { |
413 | to_write = max_transfer; | |
03e10e5a | 414 | |
5cb2ff0c RB |
415 | /* it's needed only when we do not use dedicated fifos */ |
416 | if (!hsotg->dedicated_fifos) | |
1f91b4cc | 417 | dwc2_hsotg_en_gsint(hsotg, |
47a1685f DN |
418 | periodic ? GINTSTS_PTXFEMP : |
419 | GINTSTS_NPTXFEMP); | |
03e10e5a BD |
420 | } |
421 | ||
5b7d70c6 BD |
422 | /* see if we can write data */ |
423 | ||
424 | if (to_write > can_write) { | |
425 | to_write = can_write; | |
4fca54aa | 426 | pkt_round = to_write % max_transfer; |
5b7d70c6 | 427 | |
8b9bc460 LM |
428 | /* |
429 | * Round the write down to an | |
5b7d70c6 BD |
430 | * exact number of packets. |
431 | * | |
432 | * Note, we do not currently check to see if we can ever | |
433 | * write a full packet or not to the FIFO. | |
434 | */ | |
435 | ||
436 | if (pkt_round) | |
437 | to_write -= pkt_round; | |
438 | ||
8b9bc460 LM |
439 | /* |
440 | * enable correct FIFO interrupt to alert us when there | |
441 | * is more room left. | |
442 | */ | |
5b7d70c6 | 443 | |
5cb2ff0c RB |
444 | /* it's needed only when we do not use dedicated fifos */ |
445 | if (!hsotg->dedicated_fifos) | |
1f91b4cc | 446 | dwc2_hsotg_en_gsint(hsotg, |
47a1685f DN |
447 | periodic ? GINTSTS_PTXFEMP : |
448 | GINTSTS_NPTXFEMP); | |
5b7d70c6 BD |
449 | } |
450 | ||
451 | dev_dbg(hsotg->dev, "write %d/%d, can_write %d, done %d\n", | |
452 | to_write, hs_req->req.length, can_write, buf_pos); | |
453 | ||
454 | if (to_write <= 0) | |
455 | return -ENOSPC; | |
456 | ||
457 | hs_req->req.actual = buf_pos + to_write; | |
458 | hs_ep->total_data += to_write; | |
459 | ||
460 | if (periodic) | |
461 | hs_ep->fifo_load += to_write; | |
462 | ||
463 | to_write = DIV_ROUND_UP(to_write, 4); | |
464 | data = hs_req->req.buf + buf_pos; | |
465 | ||
1a7ed5be | 466 | iowrite32_rep(hsotg->regs + EPFIFO(hs_ep->index), data, to_write); |
5b7d70c6 BD |
467 | |
468 | return (to_write >= can_write) ? -ENOSPC : 0; | |
469 | } | |
470 | ||
471 | /** | |
472 | * get_ep_limit - get the maximum data legnth for this endpoint | |
473 | * @hs_ep: The endpoint | |
474 | * | |
475 | * Return the maximum data that can be queued in one go on a given endpoint | |
476 | * so that transfers that are too long can be split. | |
477 | */ | |
1f91b4cc | 478 | static unsigned get_ep_limit(struct dwc2_hsotg_ep *hs_ep) |
5b7d70c6 BD |
479 | { |
480 | int index = hs_ep->index; | |
481 | unsigned maxsize; | |
482 | unsigned maxpkt; | |
483 | ||
484 | if (index != 0) { | |
47a1685f DN |
485 | maxsize = DXEPTSIZ_XFERSIZE_LIMIT + 1; |
486 | maxpkt = DXEPTSIZ_PKTCNT_LIMIT + 1; | |
5b7d70c6 | 487 | } else { |
b05ca580 | 488 | maxsize = 64+64; |
66e5c643 | 489 | if (hs_ep->dir_in) |
47a1685f | 490 | maxpkt = DIEPTSIZ0_PKTCNT_LIMIT + 1; |
66e5c643 | 491 | else |
5b7d70c6 | 492 | maxpkt = 2; |
5b7d70c6 BD |
493 | } |
494 | ||
495 | /* we made the constant loading easier above by using +1 */ | |
496 | maxpkt--; | |
497 | maxsize--; | |
498 | ||
8b9bc460 LM |
499 | /* |
500 | * constrain by packet count if maxpkts*pktsize is greater | |
501 | * than the length register size. | |
502 | */ | |
5b7d70c6 BD |
503 | |
504 | if ((maxpkt * hs_ep->ep.maxpacket) < maxsize) | |
505 | maxsize = maxpkt * hs_ep->ep.maxpacket; | |
506 | ||
507 | return maxsize; | |
508 | } | |
509 | ||
510 | /** | |
1f91b4cc | 511 | * dwc2_hsotg_start_req - start a USB request from an endpoint's queue |
5b7d70c6 BD |
512 | * @hsotg: The controller state. |
513 | * @hs_ep: The endpoint to process a request for | |
514 | * @hs_req: The request to start. | |
515 | * @continuing: True if we are doing more for the current request. | |
516 | * | |
517 | * Start the given request running by setting the endpoint registers | |
518 | * appropriately, and writing any data to the FIFOs. | |
519 | */ | |
1f91b4cc FB |
520 | static void dwc2_hsotg_start_req(struct dwc2_hsotg *hsotg, |
521 | struct dwc2_hsotg_ep *hs_ep, | |
522 | struct dwc2_hsotg_req *hs_req, | |
5b7d70c6 BD |
523 | bool continuing) |
524 | { | |
525 | struct usb_request *ureq = &hs_req->req; | |
526 | int index = hs_ep->index; | |
527 | int dir_in = hs_ep->dir_in; | |
528 | u32 epctrl_reg; | |
529 | u32 epsize_reg; | |
530 | u32 epsize; | |
531 | u32 ctrl; | |
532 | unsigned length; | |
533 | unsigned packets; | |
534 | unsigned maxreq; | |
535 | ||
536 | if (index != 0) { | |
537 | if (hs_ep->req && !continuing) { | |
538 | dev_err(hsotg->dev, "%s: active request\n", __func__); | |
539 | WARN_ON(1); | |
540 | return; | |
541 | } else if (hs_ep->req != hs_req && continuing) { | |
542 | dev_err(hsotg->dev, | |
543 | "%s: continue different req\n", __func__); | |
544 | WARN_ON(1); | |
545 | return; | |
546 | } | |
547 | } | |
548 | ||
94cb8fd6 LM |
549 | epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index); |
550 | epsize_reg = dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index); | |
5b7d70c6 BD |
551 | |
552 | dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n", | |
95c8bc36 | 553 | __func__, dwc2_readl(hsotg->regs + epctrl_reg), index, |
5b7d70c6 BD |
554 | hs_ep->dir_in ? "in" : "out"); |
555 | ||
9c39ddc6 | 556 | /* If endpoint is stalled, we will restart request later */ |
95c8bc36 | 557 | ctrl = dwc2_readl(hsotg->regs + epctrl_reg); |
9c39ddc6 | 558 | |
b2d4c54e | 559 | if (index && ctrl & DXEPCTL_STALL) { |
9c39ddc6 AT |
560 | dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index); |
561 | return; | |
562 | } | |
563 | ||
5b7d70c6 | 564 | length = ureq->length - ureq->actual; |
71225bee LM |
565 | dev_dbg(hsotg->dev, "ureq->length:%d ureq->actual:%d\n", |
566 | ureq->length, ureq->actual); | |
5b7d70c6 BD |
567 | |
568 | maxreq = get_ep_limit(hs_ep); | |
569 | if (length > maxreq) { | |
570 | int round = maxreq % hs_ep->ep.maxpacket; | |
571 | ||
572 | dev_dbg(hsotg->dev, "%s: length %d, max-req %d, r %d\n", | |
573 | __func__, length, maxreq, round); | |
574 | ||
575 | /* round down to multiple of packets */ | |
576 | if (round) | |
577 | maxreq -= round; | |
578 | ||
579 | length = maxreq; | |
580 | } | |
581 | ||
582 | if (length) | |
583 | packets = DIV_ROUND_UP(length, hs_ep->ep.maxpacket); | |
584 | else | |
585 | packets = 1; /* send one packet if length is zero. */ | |
586 | ||
4fca54aa RB |
587 | if (hs_ep->isochronous && length > (hs_ep->mc * hs_ep->ep.maxpacket)) { |
588 | dev_err(hsotg->dev, "req length > maxpacket*mc\n"); | |
589 | return; | |
590 | } | |
591 | ||
5b7d70c6 | 592 | if (dir_in && index != 0) |
4fca54aa | 593 | if (hs_ep->isochronous) |
47a1685f | 594 | epsize = DXEPTSIZ_MC(packets); |
4fca54aa | 595 | else |
47a1685f | 596 | epsize = DXEPTSIZ_MC(1); |
5b7d70c6 BD |
597 | else |
598 | epsize = 0; | |
599 | ||
f71b5e25 MYK |
600 | /* |
601 | * zero length packet should be programmed on its own and should not | |
602 | * be counted in DIEPTSIZ.PktCnt with other packets. | |
603 | */ | |
604 | if (dir_in && ureq->zero && !continuing) { | |
605 | /* Test if zlp is actually required. */ | |
606 | if ((ureq->length >= hs_ep->ep.maxpacket) && | |
607 | !(ureq->length % hs_ep->ep.maxpacket)) | |
8a20fa45 | 608 | hs_ep->send_zlp = 1; |
5b7d70c6 BD |
609 | } |
610 | ||
47a1685f DN |
611 | epsize |= DXEPTSIZ_PKTCNT(packets); |
612 | epsize |= DXEPTSIZ_XFERSIZE(length); | |
5b7d70c6 BD |
613 | |
614 | dev_dbg(hsotg->dev, "%s: %d@%d/%d, 0x%08x => 0x%08x\n", | |
615 | __func__, packets, length, ureq->length, epsize, epsize_reg); | |
616 | ||
617 | /* store the request as the current one we're doing */ | |
618 | hs_ep->req = hs_req; | |
619 | ||
620 | /* write size / packets */ | |
95c8bc36 | 621 | dwc2_writel(epsize, hsotg->regs + epsize_reg); |
5b7d70c6 | 622 | |
db1d8ba3 | 623 | if (using_dma(hsotg) && !continuing) { |
5b7d70c6 BD |
624 | unsigned int dma_reg; |
625 | ||
8b9bc460 LM |
626 | /* |
627 | * write DMA address to control register, buffer already | |
1f91b4cc | 628 | * synced by dwc2_hsotg_ep_queue(). |
8b9bc460 | 629 | */ |
5b7d70c6 | 630 | |
94cb8fd6 | 631 | dma_reg = dir_in ? DIEPDMA(index) : DOEPDMA(index); |
95c8bc36 | 632 | dwc2_writel(ureq->dma, hsotg->regs + dma_reg); |
5b7d70c6 | 633 | |
0cc4cf6f | 634 | dev_dbg(hsotg->dev, "%s: %pad => 0x%08x\n", |
8b3bc14f | 635 | __func__, &ureq->dma, dma_reg); |
5b7d70c6 BD |
636 | } |
637 | ||
47a1685f DN |
638 | ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */ |
639 | ctrl |= DXEPCTL_USBACTEP; | |
71225bee | 640 | |
fe0b94ab | 641 | dev_dbg(hsotg->dev, "ep0 state:%d\n", hsotg->ep0_state); |
71225bee LM |
642 | |
643 | /* For Setup request do not clear NAK */ | |
fe0b94ab | 644 | if (!(index == 0 && hsotg->ep0_state == DWC2_EP0_SETUP)) |
47a1685f | 645 | ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */ |
71225bee | 646 | |
5b7d70c6 | 647 | dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl); |
95c8bc36 | 648 | dwc2_writel(ctrl, hsotg->regs + epctrl_reg); |
5b7d70c6 | 649 | |
8b9bc460 LM |
650 | /* |
651 | * set these, it seems that DMA support increments past the end | |
5b7d70c6 | 652 | * of the packet buffer so we need to calculate the length from |
8b9bc460 LM |
653 | * this information. |
654 | */ | |
5b7d70c6 BD |
655 | hs_ep->size_loaded = length; |
656 | hs_ep->last_load = ureq->actual; | |
657 | ||
658 | if (dir_in && !using_dma(hsotg)) { | |
659 | /* set these anyway, we may need them for non-periodic in */ | |
660 | hs_ep->fifo_load = 0; | |
661 | ||
1f91b4cc | 662 | dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req); |
5b7d70c6 BD |
663 | } |
664 | ||
8b9bc460 LM |
665 | /* |
666 | * clear the INTknTXFEmpMsk when we start request, more as a aide | |
667 | * to debugging to see what is going on. | |
668 | */ | |
5b7d70c6 | 669 | if (dir_in) |
95c8bc36 | 670 | dwc2_writel(DIEPMSK_INTKNTXFEMPMSK, |
94cb8fd6 | 671 | hsotg->regs + DIEPINT(index)); |
5b7d70c6 | 672 | |
8b9bc460 LM |
673 | /* |
674 | * Note, trying to clear the NAK here causes problems with transmit | |
675 | * on the S3C6400 ending up with the TXFIFO becoming full. | |
676 | */ | |
5b7d70c6 BD |
677 | |
678 | /* check ep is enabled */ | |
95c8bc36 | 679 | if (!(dwc2_readl(hsotg->regs + epctrl_reg) & DXEPCTL_EPENA)) |
1a0ed863 | 680 | dev_dbg(hsotg->dev, |
47a1685f | 681 | "ep%d: failed to become enabled (DXEPCTL=0x%08x)?\n", |
95c8bc36 | 682 | index, dwc2_readl(hsotg->regs + epctrl_reg)); |
5b7d70c6 | 683 | |
47a1685f | 684 | dev_dbg(hsotg->dev, "%s: DXEPCTL=0x%08x\n", |
95c8bc36 | 685 | __func__, dwc2_readl(hsotg->regs + epctrl_reg)); |
afcf4169 RB |
686 | |
687 | /* enable ep interrupts */ | |
1f91b4cc | 688 | dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 1); |
5b7d70c6 BD |
689 | } |
690 | ||
691 | /** | |
1f91b4cc | 692 | * dwc2_hsotg_map_dma - map the DMA memory being used for the request |
5b7d70c6 BD |
693 | * @hsotg: The device state. |
694 | * @hs_ep: The endpoint the request is on. | |
695 | * @req: The request being processed. | |
696 | * | |
697 | * We've been asked to queue a request, so ensure that the memory buffer | |
698 | * is correctly setup for DMA. If we've been passed an extant DMA address | |
699 | * then ensure the buffer has been synced to memory. If our buffer has no | |
700 | * DMA memory, then we map the memory and mark our request to allow us to | |
701 | * cleanup on completion. | |
8b9bc460 | 702 | */ |
1f91b4cc FB |
703 | static int dwc2_hsotg_map_dma(struct dwc2_hsotg *hsotg, |
704 | struct dwc2_hsotg_ep *hs_ep, | |
5b7d70c6 BD |
705 | struct usb_request *req) |
706 | { | |
1f91b4cc | 707 | struct dwc2_hsotg_req *hs_req = our_req(req); |
e58ebcd1 | 708 | int ret; |
5b7d70c6 BD |
709 | |
710 | /* if the length is zero, ignore the DMA data */ | |
711 | if (hs_req->req.length == 0) | |
712 | return 0; | |
713 | ||
e58ebcd1 FB |
714 | ret = usb_gadget_map_request(&hsotg->gadget, req, hs_ep->dir_in); |
715 | if (ret) | |
716 | goto dma_error; | |
5b7d70c6 BD |
717 | |
718 | return 0; | |
719 | ||
720 | dma_error: | |
721 | dev_err(hsotg->dev, "%s: failed to map buffer %p, %d bytes\n", | |
722 | __func__, req->buf, req->length); | |
723 | ||
724 | return -EIO; | |
725 | } | |
726 | ||
1f91b4cc FB |
727 | static int dwc2_hsotg_handle_unaligned_buf_start(struct dwc2_hsotg *hsotg, |
728 | struct dwc2_hsotg_ep *hs_ep, struct dwc2_hsotg_req *hs_req) | |
7d24c1b5 MYK |
729 | { |
730 | void *req_buf = hs_req->req.buf; | |
731 | ||
732 | /* If dma is not being used or buffer is aligned */ | |
733 | if (!using_dma(hsotg) || !((long)req_buf & 3)) | |
734 | return 0; | |
735 | ||
736 | WARN_ON(hs_req->saved_req_buf); | |
737 | ||
738 | dev_dbg(hsotg->dev, "%s: %s: buf=%p length=%d\n", __func__, | |
739 | hs_ep->ep.name, req_buf, hs_req->req.length); | |
740 | ||
741 | hs_req->req.buf = kmalloc(hs_req->req.length, GFP_ATOMIC); | |
742 | if (!hs_req->req.buf) { | |
743 | hs_req->req.buf = req_buf; | |
744 | dev_err(hsotg->dev, | |
745 | "%s: unable to allocate memory for bounce buffer\n", | |
746 | __func__); | |
747 | return -ENOMEM; | |
748 | } | |
749 | ||
750 | /* Save actual buffer */ | |
751 | hs_req->saved_req_buf = req_buf; | |
752 | ||
753 | if (hs_ep->dir_in) | |
754 | memcpy(hs_req->req.buf, req_buf, hs_req->req.length); | |
755 | return 0; | |
756 | } | |
757 | ||
1f91b4cc FB |
758 | static void dwc2_hsotg_handle_unaligned_buf_complete(struct dwc2_hsotg *hsotg, |
759 | struct dwc2_hsotg_ep *hs_ep, struct dwc2_hsotg_req *hs_req) | |
7d24c1b5 MYK |
760 | { |
761 | /* If dma is not being used or buffer was aligned */ | |
762 | if (!using_dma(hsotg) || !hs_req->saved_req_buf) | |
763 | return; | |
764 | ||
765 | dev_dbg(hsotg->dev, "%s: %s: status=%d actual-length=%d\n", __func__, | |
766 | hs_ep->ep.name, hs_req->req.status, hs_req->req.actual); | |
767 | ||
768 | /* Copy data from bounce buffer on successful out transfer */ | |
769 | if (!hs_ep->dir_in && !hs_req->req.status) | |
770 | memcpy(hs_req->saved_req_buf, hs_req->req.buf, | |
771 | hs_req->req.actual); | |
772 | ||
773 | /* Free bounce buffer */ | |
774 | kfree(hs_req->req.buf); | |
775 | ||
776 | hs_req->req.buf = hs_req->saved_req_buf; | |
777 | hs_req->saved_req_buf = NULL; | |
778 | } | |
779 | ||
1f91b4cc | 780 | static int dwc2_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req, |
5b7d70c6 BD |
781 | gfp_t gfp_flags) |
782 | { | |
1f91b4cc FB |
783 | struct dwc2_hsotg_req *hs_req = our_req(req); |
784 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); | |
941fcce4 | 785 | struct dwc2_hsotg *hs = hs_ep->parent; |
5b7d70c6 | 786 | bool first; |
7d24c1b5 | 787 | int ret; |
5b7d70c6 BD |
788 | |
789 | dev_dbg(hs->dev, "%s: req %p: %d@%p, noi=%d, zero=%d, snok=%d\n", | |
790 | ep->name, req, req->length, req->buf, req->no_interrupt, | |
791 | req->zero, req->short_not_ok); | |
792 | ||
7ababa92 GH |
793 | /* Prevent new request submission when controller is suspended */ |
794 | if (hs->lx_state == DWC2_L2) { | |
795 | dev_dbg(hs->dev, "%s: don't submit request while suspended\n", | |
796 | __func__); | |
797 | return -EAGAIN; | |
798 | } | |
799 | ||
5b7d70c6 BD |
800 | /* initialise status of the request */ |
801 | INIT_LIST_HEAD(&hs_req->queue); | |
802 | req->actual = 0; | |
803 | req->status = -EINPROGRESS; | |
804 | ||
1f91b4cc | 805 | ret = dwc2_hsotg_handle_unaligned_buf_start(hs, hs_ep, hs_req); |
7d24c1b5 MYK |
806 | if (ret) |
807 | return ret; | |
808 | ||
5b7d70c6 BD |
809 | /* if we're using DMA, sync the buffers as necessary */ |
810 | if (using_dma(hs)) { | |
1f91b4cc | 811 | ret = dwc2_hsotg_map_dma(hs, hs_ep, req); |
5b7d70c6 BD |
812 | if (ret) |
813 | return ret; | |
814 | } | |
815 | ||
5b7d70c6 BD |
816 | first = list_empty(&hs_ep->queue); |
817 | list_add_tail(&hs_req->queue, &hs_ep->queue); | |
818 | ||
819 | if (first) | |
1f91b4cc | 820 | dwc2_hsotg_start_req(hs, hs_ep, hs_req, false); |
5b7d70c6 | 821 | |
5b7d70c6 BD |
822 | return 0; |
823 | } | |
824 | ||
1f91b4cc | 825 | static int dwc2_hsotg_ep_queue_lock(struct usb_ep *ep, struct usb_request *req, |
5ad1d316 LM |
826 | gfp_t gfp_flags) |
827 | { | |
1f91b4cc | 828 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 829 | struct dwc2_hsotg *hs = hs_ep->parent; |
5ad1d316 LM |
830 | unsigned long flags = 0; |
831 | int ret = 0; | |
832 | ||
833 | spin_lock_irqsave(&hs->lock, flags); | |
1f91b4cc | 834 | ret = dwc2_hsotg_ep_queue(ep, req, gfp_flags); |
5ad1d316 LM |
835 | spin_unlock_irqrestore(&hs->lock, flags); |
836 | ||
837 | return ret; | |
838 | } | |
839 | ||
1f91b4cc | 840 | static void dwc2_hsotg_ep_free_request(struct usb_ep *ep, |
5b7d70c6 BD |
841 | struct usb_request *req) |
842 | { | |
1f91b4cc | 843 | struct dwc2_hsotg_req *hs_req = our_req(req); |
5b7d70c6 BD |
844 | |
845 | kfree(hs_req); | |
846 | } | |
847 | ||
848 | /** | |
1f91b4cc | 849 | * dwc2_hsotg_complete_oursetup - setup completion callback |
5b7d70c6 BD |
850 | * @ep: The endpoint the request was on. |
851 | * @req: The request completed. | |
852 | * | |
853 | * Called on completion of any requests the driver itself | |
854 | * submitted that need cleaning up. | |
855 | */ | |
1f91b4cc | 856 | static void dwc2_hsotg_complete_oursetup(struct usb_ep *ep, |
5b7d70c6 BD |
857 | struct usb_request *req) |
858 | { | |
1f91b4cc | 859 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 860 | struct dwc2_hsotg *hsotg = hs_ep->parent; |
5b7d70c6 BD |
861 | |
862 | dev_dbg(hsotg->dev, "%s: ep %p, req %p\n", __func__, ep, req); | |
863 | ||
1f91b4cc | 864 | dwc2_hsotg_ep_free_request(ep, req); |
5b7d70c6 BD |
865 | } |
866 | ||
867 | /** | |
868 | * ep_from_windex - convert control wIndex value to endpoint | |
869 | * @hsotg: The driver state. | |
870 | * @windex: The control request wIndex field (in host order). | |
871 | * | |
872 | * Convert the given wIndex into a pointer to an driver endpoint | |
873 | * structure, or return NULL if it is not a valid endpoint. | |
8b9bc460 | 874 | */ |
1f91b4cc | 875 | static struct dwc2_hsotg_ep *ep_from_windex(struct dwc2_hsotg *hsotg, |
5b7d70c6 BD |
876 | u32 windex) |
877 | { | |
1f91b4cc | 878 | struct dwc2_hsotg_ep *ep; |
5b7d70c6 BD |
879 | int dir = (windex & USB_DIR_IN) ? 1 : 0; |
880 | int idx = windex & 0x7F; | |
881 | ||
882 | if (windex >= 0x100) | |
883 | return NULL; | |
884 | ||
b3f489b2 | 885 | if (idx > hsotg->num_of_eps) |
5b7d70c6 BD |
886 | return NULL; |
887 | ||
c6f5c050 MYK |
888 | ep = index_to_ep(hsotg, idx, dir); |
889 | ||
5b7d70c6 BD |
890 | if (idx && ep->dir_in != dir) |
891 | return NULL; | |
892 | ||
893 | return ep; | |
894 | } | |
895 | ||
9e14d0a5 | 896 | /** |
1f91b4cc | 897 | * dwc2_hsotg_set_test_mode - Enable usb Test Modes |
9e14d0a5 GH |
898 | * @hsotg: The driver state. |
899 | * @testmode: requested usb test mode | |
900 | * Enable usb Test Mode requested by the Host. | |
901 | */ | |
1f91b4cc | 902 | int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode) |
9e14d0a5 | 903 | { |
95c8bc36 | 904 | int dctl = dwc2_readl(hsotg->regs + DCTL); |
9e14d0a5 GH |
905 | |
906 | dctl &= ~DCTL_TSTCTL_MASK; | |
907 | switch (testmode) { | |
908 | case TEST_J: | |
909 | case TEST_K: | |
910 | case TEST_SE0_NAK: | |
911 | case TEST_PACKET: | |
912 | case TEST_FORCE_EN: | |
913 | dctl |= testmode << DCTL_TSTCTL_SHIFT; | |
914 | break; | |
915 | default: | |
916 | return -EINVAL; | |
917 | } | |
95c8bc36 | 918 | dwc2_writel(dctl, hsotg->regs + DCTL); |
9e14d0a5 GH |
919 | return 0; |
920 | } | |
921 | ||
5b7d70c6 | 922 | /** |
1f91b4cc | 923 | * dwc2_hsotg_send_reply - send reply to control request |
5b7d70c6 BD |
924 | * @hsotg: The device state |
925 | * @ep: Endpoint 0 | |
926 | * @buff: Buffer for request | |
927 | * @length: Length of reply. | |
928 | * | |
929 | * Create a request and queue it on the given endpoint. This is useful as | |
930 | * an internal method of sending replies to certain control requests, etc. | |
931 | */ | |
1f91b4cc FB |
932 | static int dwc2_hsotg_send_reply(struct dwc2_hsotg *hsotg, |
933 | struct dwc2_hsotg_ep *ep, | |
5b7d70c6 BD |
934 | void *buff, |
935 | int length) | |
936 | { | |
937 | struct usb_request *req; | |
938 | int ret; | |
939 | ||
940 | dev_dbg(hsotg->dev, "%s: buff %p, len %d\n", __func__, buff, length); | |
941 | ||
1f91b4cc | 942 | req = dwc2_hsotg_ep_alloc_request(&ep->ep, GFP_ATOMIC); |
5b7d70c6 BD |
943 | hsotg->ep0_reply = req; |
944 | if (!req) { | |
945 | dev_warn(hsotg->dev, "%s: cannot alloc req\n", __func__); | |
946 | return -ENOMEM; | |
947 | } | |
948 | ||
949 | req->buf = hsotg->ep0_buff; | |
950 | req->length = length; | |
f71b5e25 MYK |
951 | /* |
952 | * zero flag is for sending zlp in DATA IN stage. It has no impact on | |
953 | * STATUS stage. | |
954 | */ | |
955 | req->zero = 0; | |
1f91b4cc | 956 | req->complete = dwc2_hsotg_complete_oursetup; |
5b7d70c6 BD |
957 | |
958 | if (length) | |
959 | memcpy(req->buf, buff, length); | |
5b7d70c6 | 960 | |
1f91b4cc | 961 | ret = dwc2_hsotg_ep_queue(&ep->ep, req, GFP_ATOMIC); |
5b7d70c6 BD |
962 | if (ret) { |
963 | dev_warn(hsotg->dev, "%s: cannot queue req\n", __func__); | |
964 | return ret; | |
965 | } | |
966 | ||
967 | return 0; | |
968 | } | |
969 | ||
970 | /** | |
1f91b4cc | 971 | * dwc2_hsotg_process_req_status - process request GET_STATUS |
5b7d70c6 BD |
972 | * @hsotg: The device state |
973 | * @ctrl: USB control request | |
974 | */ | |
1f91b4cc | 975 | static int dwc2_hsotg_process_req_status(struct dwc2_hsotg *hsotg, |
5b7d70c6 BD |
976 | struct usb_ctrlrequest *ctrl) |
977 | { | |
1f91b4cc FB |
978 | struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0]; |
979 | struct dwc2_hsotg_ep *ep; | |
5b7d70c6 BD |
980 | __le16 reply; |
981 | int ret; | |
982 | ||
983 | dev_dbg(hsotg->dev, "%s: USB_REQ_GET_STATUS\n", __func__); | |
984 | ||
985 | if (!ep0->dir_in) { | |
986 | dev_warn(hsotg->dev, "%s: direction out?\n", __func__); | |
987 | return -EINVAL; | |
988 | } | |
989 | ||
990 | switch (ctrl->bRequestType & USB_RECIP_MASK) { | |
991 | case USB_RECIP_DEVICE: | |
992 | reply = cpu_to_le16(0); /* bit 0 => self powered, | |
993 | * bit 1 => remote wakeup */ | |
994 | break; | |
995 | ||
996 | case USB_RECIP_INTERFACE: | |
997 | /* currently, the data result should be zero */ | |
998 | reply = cpu_to_le16(0); | |
999 | break; | |
1000 | ||
1001 | case USB_RECIP_ENDPOINT: | |
1002 | ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex)); | |
1003 | if (!ep) | |
1004 | return -ENOENT; | |
1005 | ||
1006 | reply = cpu_to_le16(ep->halted ? 1 : 0); | |
1007 | break; | |
1008 | ||
1009 | default: | |
1010 | return 0; | |
1011 | } | |
1012 | ||
1013 | if (le16_to_cpu(ctrl->wLength) != 2) | |
1014 | return -EINVAL; | |
1015 | ||
1f91b4cc | 1016 | ret = dwc2_hsotg_send_reply(hsotg, ep0, &reply, 2); |
5b7d70c6 BD |
1017 | if (ret) { |
1018 | dev_err(hsotg->dev, "%s: failed to send reply\n", __func__); | |
1019 | return ret; | |
1020 | } | |
1021 | ||
1022 | return 1; | |
1023 | } | |
1024 | ||
1f91b4cc | 1025 | static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value); |
5b7d70c6 | 1026 | |
9c39ddc6 AT |
1027 | /** |
1028 | * get_ep_head - return the first request on the endpoint | |
1029 | * @hs_ep: The controller endpoint to get | |
1030 | * | |
1031 | * Get the first request on the endpoint. | |
1032 | */ | |
1f91b4cc | 1033 | static struct dwc2_hsotg_req *get_ep_head(struct dwc2_hsotg_ep *hs_ep) |
9c39ddc6 AT |
1034 | { |
1035 | if (list_empty(&hs_ep->queue)) | |
1036 | return NULL; | |
1037 | ||
1f91b4cc | 1038 | return list_first_entry(&hs_ep->queue, struct dwc2_hsotg_req, queue); |
9c39ddc6 AT |
1039 | } |
1040 | ||
5b7d70c6 | 1041 | /** |
1f91b4cc | 1042 | * dwc2_hsotg_process_req_feature - process request {SET,CLEAR}_FEATURE |
5b7d70c6 BD |
1043 | * @hsotg: The device state |
1044 | * @ctrl: USB control request | |
1045 | */ | |
1f91b4cc | 1046 | static int dwc2_hsotg_process_req_feature(struct dwc2_hsotg *hsotg, |
5b7d70c6 BD |
1047 | struct usb_ctrlrequest *ctrl) |
1048 | { | |
1f91b4cc FB |
1049 | struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0]; |
1050 | struct dwc2_hsotg_req *hs_req; | |
9c39ddc6 | 1051 | bool restart; |
5b7d70c6 | 1052 | bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE); |
1f91b4cc | 1053 | struct dwc2_hsotg_ep *ep; |
26ab3d0c | 1054 | int ret; |
bd9ef7bf | 1055 | bool halted; |
9e14d0a5 GH |
1056 | u32 recip; |
1057 | u32 wValue; | |
1058 | u32 wIndex; | |
5b7d70c6 BD |
1059 | |
1060 | dev_dbg(hsotg->dev, "%s: %s_FEATURE\n", | |
1061 | __func__, set ? "SET" : "CLEAR"); | |
1062 | ||
9e14d0a5 GH |
1063 | wValue = le16_to_cpu(ctrl->wValue); |
1064 | wIndex = le16_to_cpu(ctrl->wIndex); | |
1065 | recip = ctrl->bRequestType & USB_RECIP_MASK; | |
1066 | ||
1067 | switch (recip) { | |
1068 | case USB_RECIP_DEVICE: | |
1069 | switch (wValue) { | |
1070 | case USB_DEVICE_TEST_MODE: | |
1071 | if ((wIndex & 0xff) != 0) | |
1072 | return -EINVAL; | |
1073 | if (!set) | |
1074 | return -EINVAL; | |
1075 | ||
1076 | hsotg->test_mode = wIndex >> 8; | |
1f91b4cc | 1077 | ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0); |
9e14d0a5 GH |
1078 | if (ret) { |
1079 | dev_err(hsotg->dev, | |
1080 | "%s: failed to send reply\n", __func__); | |
1081 | return ret; | |
1082 | } | |
1083 | break; | |
1084 | default: | |
1085 | return -ENOENT; | |
1086 | } | |
1087 | break; | |
1088 | ||
1089 | case USB_RECIP_ENDPOINT: | |
1090 | ep = ep_from_windex(hsotg, wIndex); | |
5b7d70c6 BD |
1091 | if (!ep) { |
1092 | dev_dbg(hsotg->dev, "%s: no endpoint for 0x%04x\n", | |
9e14d0a5 | 1093 | __func__, wIndex); |
5b7d70c6 BD |
1094 | return -ENOENT; |
1095 | } | |
1096 | ||
9e14d0a5 | 1097 | switch (wValue) { |
5b7d70c6 | 1098 | case USB_ENDPOINT_HALT: |
bd9ef7bf RB |
1099 | halted = ep->halted; |
1100 | ||
1f91b4cc | 1101 | dwc2_hsotg_ep_sethalt(&ep->ep, set); |
26ab3d0c | 1102 | |
1f91b4cc | 1103 | ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0); |
26ab3d0c AT |
1104 | if (ret) { |
1105 | dev_err(hsotg->dev, | |
1106 | "%s: failed to send reply\n", __func__); | |
1107 | return ret; | |
1108 | } | |
9c39ddc6 | 1109 | |
bd9ef7bf RB |
1110 | /* |
1111 | * we have to complete all requests for ep if it was | |
1112 | * halted, and the halt was cleared by CLEAR_FEATURE | |
1113 | */ | |
1114 | ||
1115 | if (!set && halted) { | |
9c39ddc6 AT |
1116 | /* |
1117 | * If we have request in progress, | |
1118 | * then complete it | |
1119 | */ | |
1120 | if (ep->req) { | |
1121 | hs_req = ep->req; | |
1122 | ep->req = NULL; | |
1123 | list_del_init(&hs_req->queue); | |
c00dd4a6 GH |
1124 | if (hs_req->req.complete) { |
1125 | spin_unlock(&hsotg->lock); | |
1126 | usb_gadget_giveback_request( | |
1127 | &ep->ep, &hs_req->req); | |
1128 | spin_lock(&hsotg->lock); | |
1129 | } | |
9c39ddc6 AT |
1130 | } |
1131 | ||
1132 | /* If we have pending request, then start it */ | |
c00dd4a6 GH |
1133 | if (!ep->req) { |
1134 | restart = !list_empty(&ep->queue); | |
1135 | if (restart) { | |
1136 | hs_req = get_ep_head(ep); | |
1f91b4cc | 1137 | dwc2_hsotg_start_req(hsotg, ep, |
c00dd4a6 GH |
1138 | hs_req, false); |
1139 | } | |
9c39ddc6 AT |
1140 | } |
1141 | } | |
1142 | ||
5b7d70c6 BD |
1143 | break; |
1144 | ||
1145 | default: | |
1146 | return -ENOENT; | |
1147 | } | |
9e14d0a5 GH |
1148 | break; |
1149 | default: | |
1150 | return -ENOENT; | |
1151 | } | |
5b7d70c6 BD |
1152 | return 1; |
1153 | } | |
1154 | ||
1f91b4cc | 1155 | static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg); |
ab93e014 | 1156 | |
c9f721b2 | 1157 | /** |
1f91b4cc | 1158 | * dwc2_hsotg_stall_ep0 - stall ep0 |
c9f721b2 RB |
1159 | * @hsotg: The device state |
1160 | * | |
1161 | * Set stall for ep0 as response for setup request. | |
1162 | */ | |
1f91b4cc | 1163 | static void dwc2_hsotg_stall_ep0(struct dwc2_hsotg *hsotg) |
e9ebe7c3 | 1164 | { |
1f91b4cc | 1165 | struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0]; |
c9f721b2 RB |
1166 | u32 reg; |
1167 | u32 ctrl; | |
1168 | ||
1169 | dev_dbg(hsotg->dev, "ep0 stall (dir=%d)\n", ep0->dir_in); | |
1170 | reg = (ep0->dir_in) ? DIEPCTL0 : DOEPCTL0; | |
1171 | ||
1172 | /* | |
1173 | * DxEPCTL_Stall will be cleared by EP once it has | |
1174 | * taken effect, so no need to clear later. | |
1175 | */ | |
1176 | ||
95c8bc36 | 1177 | ctrl = dwc2_readl(hsotg->regs + reg); |
47a1685f DN |
1178 | ctrl |= DXEPCTL_STALL; |
1179 | ctrl |= DXEPCTL_CNAK; | |
95c8bc36 | 1180 | dwc2_writel(ctrl, hsotg->regs + reg); |
c9f721b2 RB |
1181 | |
1182 | dev_dbg(hsotg->dev, | |
47a1685f | 1183 | "written DXEPCTL=0x%08x to %08x (DXEPCTL=0x%08x)\n", |
95c8bc36 | 1184 | ctrl, reg, dwc2_readl(hsotg->regs + reg)); |
c9f721b2 RB |
1185 | |
1186 | /* | |
1187 | * complete won't be called, so we enqueue | |
1188 | * setup request here | |
1189 | */ | |
1f91b4cc | 1190 | dwc2_hsotg_enqueue_setup(hsotg); |
c9f721b2 RB |
1191 | } |
1192 | ||
5b7d70c6 | 1193 | /** |
1f91b4cc | 1194 | * dwc2_hsotg_process_control - process a control request |
5b7d70c6 BD |
1195 | * @hsotg: The device state |
1196 | * @ctrl: The control request received | |
1197 | * | |
1198 | * The controller has received the SETUP phase of a control request, and | |
1199 | * needs to work out what to do next (and whether to pass it on to the | |
1200 | * gadget driver). | |
1201 | */ | |
1f91b4cc | 1202 | static void dwc2_hsotg_process_control(struct dwc2_hsotg *hsotg, |
5b7d70c6 BD |
1203 | struct usb_ctrlrequest *ctrl) |
1204 | { | |
1f91b4cc | 1205 | struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0]; |
5b7d70c6 BD |
1206 | int ret = 0; |
1207 | u32 dcfg; | |
1208 | ||
e525e743 MYK |
1209 | dev_dbg(hsotg->dev, |
1210 | "ctrl Type=%02x, Req=%02x, V=%04x, I=%04x, L=%04x\n", | |
1211 | ctrl->bRequestType, ctrl->bRequest, ctrl->wValue, | |
1212 | ctrl->wIndex, ctrl->wLength); | |
5b7d70c6 | 1213 | |
fe0b94ab MYK |
1214 | if (ctrl->wLength == 0) { |
1215 | ep0->dir_in = 1; | |
1216 | hsotg->ep0_state = DWC2_EP0_STATUS_IN; | |
1217 | } else if (ctrl->bRequestType & USB_DIR_IN) { | |
5b7d70c6 | 1218 | ep0->dir_in = 1; |
fe0b94ab MYK |
1219 | hsotg->ep0_state = DWC2_EP0_DATA_IN; |
1220 | } else { | |
1221 | ep0->dir_in = 0; | |
1222 | hsotg->ep0_state = DWC2_EP0_DATA_OUT; | |
1223 | } | |
5b7d70c6 BD |
1224 | |
1225 | if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) { | |
1226 | switch (ctrl->bRequest) { | |
1227 | case USB_REQ_SET_ADDRESS: | |
6d713c15 | 1228 | hsotg->connected = 1; |
95c8bc36 | 1229 | dcfg = dwc2_readl(hsotg->regs + DCFG); |
47a1685f | 1230 | dcfg &= ~DCFG_DEVADDR_MASK; |
d5dbd3f7 PZ |
1231 | dcfg |= (le16_to_cpu(ctrl->wValue) << |
1232 | DCFG_DEVADDR_SHIFT) & DCFG_DEVADDR_MASK; | |
95c8bc36 | 1233 | dwc2_writel(dcfg, hsotg->regs + DCFG); |
5b7d70c6 BD |
1234 | |
1235 | dev_info(hsotg->dev, "new address %d\n", ctrl->wValue); | |
1236 | ||
1f91b4cc | 1237 | ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0); |
5b7d70c6 BD |
1238 | return; |
1239 | ||
1240 | case USB_REQ_GET_STATUS: | |
1f91b4cc | 1241 | ret = dwc2_hsotg_process_req_status(hsotg, ctrl); |
5b7d70c6 BD |
1242 | break; |
1243 | ||
1244 | case USB_REQ_CLEAR_FEATURE: | |
1245 | case USB_REQ_SET_FEATURE: | |
1f91b4cc | 1246 | ret = dwc2_hsotg_process_req_feature(hsotg, ctrl); |
5b7d70c6 BD |
1247 | break; |
1248 | } | |
1249 | } | |
1250 | ||
1251 | /* as a fallback, try delivering it to the driver to deal with */ | |
1252 | ||
1253 | if (ret == 0 && hsotg->driver) { | |
93f599f2 | 1254 | spin_unlock(&hsotg->lock); |
5b7d70c6 | 1255 | ret = hsotg->driver->setup(&hsotg->gadget, ctrl); |
93f599f2 | 1256 | spin_lock(&hsotg->lock); |
5b7d70c6 BD |
1257 | if (ret < 0) |
1258 | dev_dbg(hsotg->dev, "driver->setup() ret %d\n", ret); | |
1259 | } | |
1260 | ||
8b9bc460 LM |
1261 | /* |
1262 | * the request is either unhandlable, or is not formatted correctly | |
5b7d70c6 BD |
1263 | * so respond with a STALL for the status stage to indicate failure. |
1264 | */ | |
1265 | ||
c9f721b2 | 1266 | if (ret < 0) |
1f91b4cc | 1267 | dwc2_hsotg_stall_ep0(hsotg); |
5b7d70c6 BD |
1268 | } |
1269 | ||
5b7d70c6 | 1270 | /** |
1f91b4cc | 1271 | * dwc2_hsotg_complete_setup - completion of a setup transfer |
5b7d70c6 BD |
1272 | * @ep: The endpoint the request was on. |
1273 | * @req: The request completed. | |
1274 | * | |
1275 | * Called on completion of any requests the driver itself submitted for | |
1276 | * EP0 setup packets | |
1277 | */ | |
1f91b4cc | 1278 | static void dwc2_hsotg_complete_setup(struct usb_ep *ep, |
5b7d70c6 BD |
1279 | struct usb_request *req) |
1280 | { | |
1f91b4cc | 1281 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 1282 | struct dwc2_hsotg *hsotg = hs_ep->parent; |
5b7d70c6 BD |
1283 | |
1284 | if (req->status < 0) { | |
1285 | dev_dbg(hsotg->dev, "%s: failed %d\n", __func__, req->status); | |
1286 | return; | |
1287 | } | |
1288 | ||
93f599f2 | 1289 | spin_lock(&hsotg->lock); |
5b7d70c6 | 1290 | if (req->actual == 0) |
1f91b4cc | 1291 | dwc2_hsotg_enqueue_setup(hsotg); |
5b7d70c6 | 1292 | else |
1f91b4cc | 1293 | dwc2_hsotg_process_control(hsotg, req->buf); |
93f599f2 | 1294 | spin_unlock(&hsotg->lock); |
5b7d70c6 BD |
1295 | } |
1296 | ||
1297 | /** | |
1f91b4cc | 1298 | * dwc2_hsotg_enqueue_setup - start a request for EP0 packets |
5b7d70c6 BD |
1299 | * @hsotg: The device state. |
1300 | * | |
1301 | * Enqueue a request on EP0 if necessary to received any SETUP packets | |
1302 | * received from the host. | |
1303 | */ | |
1f91b4cc | 1304 | static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg) |
5b7d70c6 BD |
1305 | { |
1306 | struct usb_request *req = hsotg->ctrl_req; | |
1f91b4cc | 1307 | struct dwc2_hsotg_req *hs_req = our_req(req); |
5b7d70c6 BD |
1308 | int ret; |
1309 | ||
1310 | dev_dbg(hsotg->dev, "%s: queueing setup request\n", __func__); | |
1311 | ||
1312 | req->zero = 0; | |
1313 | req->length = 8; | |
1314 | req->buf = hsotg->ctrl_buff; | |
1f91b4cc | 1315 | req->complete = dwc2_hsotg_complete_setup; |
5b7d70c6 BD |
1316 | |
1317 | if (!list_empty(&hs_req->queue)) { | |
1318 | dev_dbg(hsotg->dev, "%s already queued???\n", __func__); | |
1319 | return; | |
1320 | } | |
1321 | ||
c6f5c050 | 1322 | hsotg->eps_out[0]->dir_in = 0; |
8a20fa45 | 1323 | hsotg->eps_out[0]->send_zlp = 0; |
fe0b94ab | 1324 | hsotg->ep0_state = DWC2_EP0_SETUP; |
5b7d70c6 | 1325 | |
1f91b4cc | 1326 | ret = dwc2_hsotg_ep_queue(&hsotg->eps_out[0]->ep, req, GFP_ATOMIC); |
5b7d70c6 BD |
1327 | if (ret < 0) { |
1328 | dev_err(hsotg->dev, "%s: failed queue (%d)\n", __func__, ret); | |
8b9bc460 LM |
1329 | /* |
1330 | * Don't think there's much we can do other than watch the | |
1331 | * driver fail. | |
1332 | */ | |
5b7d70c6 BD |
1333 | } |
1334 | } | |
1335 | ||
1f91b4cc FB |
1336 | static void dwc2_hsotg_program_zlp(struct dwc2_hsotg *hsotg, |
1337 | struct dwc2_hsotg_ep *hs_ep) | |
fe0b94ab MYK |
1338 | { |
1339 | u32 ctrl; | |
1340 | u8 index = hs_ep->index; | |
1341 | u32 epctl_reg = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index); | |
1342 | u32 epsiz_reg = hs_ep->dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index); | |
1343 | ||
ccb34a91 MYK |
1344 | if (hs_ep->dir_in) |
1345 | dev_dbg(hsotg->dev, "Sending zero-length packet on ep%d\n", | |
1346 | index); | |
1347 | else | |
1348 | dev_dbg(hsotg->dev, "Receiving zero-length packet on ep%d\n", | |
1349 | index); | |
fe0b94ab | 1350 | |
95c8bc36 AS |
1351 | dwc2_writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) | |
1352 | DXEPTSIZ_XFERSIZE(0), hsotg->regs + | |
1353 | epsiz_reg); | |
fe0b94ab | 1354 | |
95c8bc36 | 1355 | ctrl = dwc2_readl(hsotg->regs + epctl_reg); |
fe0b94ab MYK |
1356 | ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */ |
1357 | ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */ | |
1358 | ctrl |= DXEPCTL_USBACTEP; | |
95c8bc36 | 1359 | dwc2_writel(ctrl, hsotg->regs + epctl_reg); |
fe0b94ab MYK |
1360 | } |
1361 | ||
5b7d70c6 | 1362 | /** |
1f91b4cc | 1363 | * dwc2_hsotg_complete_request - complete a request given to us |
5b7d70c6 BD |
1364 | * @hsotg: The device state. |
1365 | * @hs_ep: The endpoint the request was on. | |
1366 | * @hs_req: The request to complete. | |
1367 | * @result: The result code (0 => Ok, otherwise errno) | |
1368 | * | |
1369 | * The given request has finished, so call the necessary completion | |
1370 | * if it has one and then look to see if we can start a new request | |
1371 | * on the endpoint. | |
1372 | * | |
1373 | * Note, expects the ep to already be locked as appropriate. | |
8b9bc460 | 1374 | */ |
1f91b4cc FB |
1375 | static void dwc2_hsotg_complete_request(struct dwc2_hsotg *hsotg, |
1376 | struct dwc2_hsotg_ep *hs_ep, | |
1377 | struct dwc2_hsotg_req *hs_req, | |
5b7d70c6 BD |
1378 | int result) |
1379 | { | |
1380 | bool restart; | |
1381 | ||
1382 | if (!hs_req) { | |
1383 | dev_dbg(hsotg->dev, "%s: nothing to complete?\n", __func__); | |
1384 | return; | |
1385 | } | |
1386 | ||
1387 | dev_dbg(hsotg->dev, "complete: ep %p %s, req %p, %d => %p\n", | |
1388 | hs_ep, hs_ep->ep.name, hs_req, result, hs_req->req.complete); | |
1389 | ||
8b9bc460 LM |
1390 | /* |
1391 | * only replace the status if we've not already set an error | |
1392 | * from a previous transaction | |
1393 | */ | |
5b7d70c6 BD |
1394 | |
1395 | if (hs_req->req.status == -EINPROGRESS) | |
1396 | hs_req->req.status = result; | |
1397 | ||
1f91b4cc | 1398 | dwc2_hsotg_handle_unaligned_buf_complete(hsotg, hs_ep, hs_req); |
7d24c1b5 | 1399 | |
5b7d70c6 BD |
1400 | hs_ep->req = NULL; |
1401 | list_del_init(&hs_req->queue); | |
1402 | ||
1403 | if (using_dma(hsotg)) | |
1f91b4cc | 1404 | dwc2_hsotg_unmap_dma(hsotg, hs_ep, hs_req); |
5b7d70c6 | 1405 | |
8b9bc460 LM |
1406 | /* |
1407 | * call the complete request with the locks off, just in case the | |
1408 | * request tries to queue more work for this endpoint. | |
1409 | */ | |
5b7d70c6 BD |
1410 | |
1411 | if (hs_req->req.complete) { | |
22258f49 | 1412 | spin_unlock(&hsotg->lock); |
304f7e5e | 1413 | usb_gadget_giveback_request(&hs_ep->ep, &hs_req->req); |
22258f49 | 1414 | spin_lock(&hsotg->lock); |
5b7d70c6 BD |
1415 | } |
1416 | ||
8b9bc460 LM |
1417 | /* |
1418 | * Look to see if there is anything else to do. Note, the completion | |
5b7d70c6 | 1419 | * of the previous request may have caused a new request to be started |
8b9bc460 LM |
1420 | * so be careful when doing this. |
1421 | */ | |
5b7d70c6 BD |
1422 | |
1423 | if (!hs_ep->req && result >= 0) { | |
1424 | restart = !list_empty(&hs_ep->queue); | |
1425 | if (restart) { | |
1426 | hs_req = get_ep_head(hs_ep); | |
1f91b4cc | 1427 | dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, false); |
5b7d70c6 BD |
1428 | } |
1429 | } | |
1430 | } | |
1431 | ||
5b7d70c6 | 1432 | /** |
1f91b4cc | 1433 | * dwc2_hsotg_rx_data - receive data from the FIFO for an endpoint |
5b7d70c6 BD |
1434 | * @hsotg: The device state. |
1435 | * @ep_idx: The endpoint index for the data | |
1436 | * @size: The size of data in the fifo, in bytes | |
1437 | * | |
1438 | * The FIFO status shows there is data to read from the FIFO for a given | |
1439 | * endpoint, so sort out whether we need to read the data into a request | |
1440 | * that has been made for that endpoint. | |
1441 | */ | |
1f91b4cc | 1442 | static void dwc2_hsotg_rx_data(struct dwc2_hsotg *hsotg, int ep_idx, int size) |
5b7d70c6 | 1443 | { |
1f91b4cc FB |
1444 | struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[ep_idx]; |
1445 | struct dwc2_hsotg_req *hs_req = hs_ep->req; | |
94cb8fd6 | 1446 | void __iomem *fifo = hsotg->regs + EPFIFO(ep_idx); |
5b7d70c6 BD |
1447 | int to_read; |
1448 | int max_req; | |
1449 | int read_ptr; | |
1450 | ||
22258f49 | 1451 | |
5b7d70c6 | 1452 | if (!hs_req) { |
95c8bc36 | 1453 | u32 epctl = dwc2_readl(hsotg->regs + DOEPCTL(ep_idx)); |
5b7d70c6 BD |
1454 | int ptr; |
1455 | ||
6b448af4 | 1456 | dev_dbg(hsotg->dev, |
47a1685f | 1457 | "%s: FIFO %d bytes on ep%d but no req (DXEPCTl=0x%08x)\n", |
5b7d70c6 BD |
1458 | __func__, size, ep_idx, epctl); |
1459 | ||
1460 | /* dump the data from the FIFO, we've nothing we can do */ | |
1461 | for (ptr = 0; ptr < size; ptr += 4) | |
95c8bc36 | 1462 | (void)dwc2_readl(fifo); |
5b7d70c6 BD |
1463 | |
1464 | return; | |
1465 | } | |
1466 | ||
5b7d70c6 BD |
1467 | to_read = size; |
1468 | read_ptr = hs_req->req.actual; | |
1469 | max_req = hs_req->req.length - read_ptr; | |
1470 | ||
a33e7136 BD |
1471 | dev_dbg(hsotg->dev, "%s: read %d/%d, done %d/%d\n", |
1472 | __func__, to_read, max_req, read_ptr, hs_req->req.length); | |
1473 | ||
5b7d70c6 | 1474 | if (to_read > max_req) { |
8b9bc460 LM |
1475 | /* |
1476 | * more data appeared than we where willing | |
5b7d70c6 BD |
1477 | * to deal with in this request. |
1478 | */ | |
1479 | ||
1480 | /* currently we don't deal this */ | |
1481 | WARN_ON_ONCE(1); | |
1482 | } | |
1483 | ||
5b7d70c6 BD |
1484 | hs_ep->total_data += to_read; |
1485 | hs_req->req.actual += to_read; | |
1486 | to_read = DIV_ROUND_UP(to_read, 4); | |
1487 | ||
8b9bc460 LM |
1488 | /* |
1489 | * note, we might over-write the buffer end by 3 bytes depending on | |
1490 | * alignment of the data. | |
1491 | */ | |
1a7ed5be | 1492 | ioread32_rep(fifo, hs_req->req.buf + read_ptr, to_read); |
5b7d70c6 BD |
1493 | } |
1494 | ||
1495 | /** | |
1f91b4cc | 1496 | * dwc2_hsotg_ep0_zlp - send/receive zero-length packet on control endpoint |
5b7d70c6 | 1497 | * @hsotg: The device instance |
fe0b94ab | 1498 | * @dir_in: If IN zlp |
5b7d70c6 BD |
1499 | * |
1500 | * Generate a zero-length IN packet request for terminating a SETUP | |
1501 | * transaction. | |
1502 | * | |
1503 | * Note, since we don't write any data to the TxFIFO, then it is | |
25985edc | 1504 | * currently believed that we do not need to wait for any space in |
5b7d70c6 BD |
1505 | * the TxFIFO. |
1506 | */ | |
1f91b4cc | 1507 | static void dwc2_hsotg_ep0_zlp(struct dwc2_hsotg *hsotg, bool dir_in) |
5b7d70c6 | 1508 | { |
c6f5c050 | 1509 | /* eps_out[0] is used in both directions */ |
fe0b94ab MYK |
1510 | hsotg->eps_out[0]->dir_in = dir_in; |
1511 | hsotg->ep0_state = dir_in ? DWC2_EP0_STATUS_IN : DWC2_EP0_STATUS_OUT; | |
5b7d70c6 | 1512 | |
1f91b4cc | 1513 | dwc2_hsotg_program_zlp(hsotg, hsotg->eps_out[0]); |
5b7d70c6 BD |
1514 | } |
1515 | ||
1516 | /** | |
1f91b4cc | 1517 | * dwc2_hsotg_handle_outdone - handle receiving OutDone/SetupDone from RXFIFO |
5b7d70c6 BD |
1518 | * @hsotg: The device instance |
1519 | * @epnum: The endpoint received from | |
5b7d70c6 BD |
1520 | * |
1521 | * The RXFIFO has delivered an OutDone event, which means that the data | |
1522 | * transfer for an OUT endpoint has been completed, either by a short | |
1523 | * packet or by the finish of a transfer. | |
8b9bc460 | 1524 | */ |
1f91b4cc | 1525 | static void dwc2_hsotg_handle_outdone(struct dwc2_hsotg *hsotg, int epnum) |
5b7d70c6 | 1526 | { |
95c8bc36 | 1527 | u32 epsize = dwc2_readl(hsotg->regs + DOEPTSIZ(epnum)); |
1f91b4cc FB |
1528 | struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[epnum]; |
1529 | struct dwc2_hsotg_req *hs_req = hs_ep->req; | |
5b7d70c6 | 1530 | struct usb_request *req = &hs_req->req; |
47a1685f | 1531 | unsigned size_left = DXEPTSIZ_XFERSIZE_GET(epsize); |
5b7d70c6 BD |
1532 | int result = 0; |
1533 | ||
1534 | if (!hs_req) { | |
1535 | dev_dbg(hsotg->dev, "%s: no request active\n", __func__); | |
1536 | return; | |
1537 | } | |
1538 | ||
fe0b94ab MYK |
1539 | if (epnum == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_OUT) { |
1540 | dev_dbg(hsotg->dev, "zlp packet received\n"); | |
1f91b4cc FB |
1541 | dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0); |
1542 | dwc2_hsotg_enqueue_setup(hsotg); | |
fe0b94ab MYK |
1543 | return; |
1544 | } | |
1545 | ||
5b7d70c6 | 1546 | if (using_dma(hsotg)) { |
5b7d70c6 | 1547 | unsigned size_done; |
5b7d70c6 | 1548 | |
8b9bc460 LM |
1549 | /* |
1550 | * Calculate the size of the transfer by checking how much | |
5b7d70c6 BD |
1551 | * is left in the endpoint size register and then working it |
1552 | * out from the amount we loaded for the transfer. | |
1553 | * | |
1554 | * We need to do this as DMA pointers are always 32bit aligned | |
1555 | * so may overshoot/undershoot the transfer. | |
1556 | */ | |
1557 | ||
5b7d70c6 BD |
1558 | size_done = hs_ep->size_loaded - size_left; |
1559 | size_done += hs_ep->last_load; | |
1560 | ||
1561 | req->actual = size_done; | |
1562 | } | |
1563 | ||
a33e7136 BD |
1564 | /* if there is more request to do, schedule new transfer */ |
1565 | if (req->actual < req->length && size_left == 0) { | |
1f91b4cc | 1566 | dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true); |
a33e7136 BD |
1567 | return; |
1568 | } | |
1569 | ||
5b7d70c6 BD |
1570 | if (req->actual < req->length && req->short_not_ok) { |
1571 | dev_dbg(hsotg->dev, "%s: got %d/%d (short not ok) => error\n", | |
1572 | __func__, req->actual, req->length); | |
1573 | ||
8b9bc460 LM |
1574 | /* |
1575 | * todo - what should we return here? there's no one else | |
1576 | * even bothering to check the status. | |
1577 | */ | |
5b7d70c6 BD |
1578 | } |
1579 | ||
fe0b94ab MYK |
1580 | if (epnum == 0 && hsotg->ep0_state == DWC2_EP0_DATA_OUT) { |
1581 | /* Move to STATUS IN */ | |
1f91b4cc | 1582 | dwc2_hsotg_ep0_zlp(hsotg, true); |
fe0b94ab | 1583 | return; |
5b7d70c6 BD |
1584 | } |
1585 | ||
1f91b4cc | 1586 | dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, result); |
5b7d70c6 BD |
1587 | } |
1588 | ||
1589 | /** | |
1f91b4cc | 1590 | * dwc2_hsotg_read_frameno - read current frame number |
5b7d70c6 BD |
1591 | * @hsotg: The device instance |
1592 | * | |
1593 | * Return the current frame number | |
8b9bc460 | 1594 | */ |
1f91b4cc | 1595 | static u32 dwc2_hsotg_read_frameno(struct dwc2_hsotg *hsotg) |
5b7d70c6 BD |
1596 | { |
1597 | u32 dsts; | |
1598 | ||
95c8bc36 | 1599 | dsts = dwc2_readl(hsotg->regs + DSTS); |
94cb8fd6 LM |
1600 | dsts &= DSTS_SOFFN_MASK; |
1601 | dsts >>= DSTS_SOFFN_SHIFT; | |
5b7d70c6 BD |
1602 | |
1603 | return dsts; | |
1604 | } | |
1605 | ||
1606 | /** | |
1f91b4cc | 1607 | * dwc2_hsotg_handle_rx - RX FIFO has data |
5b7d70c6 BD |
1608 | * @hsotg: The device instance |
1609 | * | |
1610 | * The IRQ handler has detected that the RX FIFO has some data in it | |
1611 | * that requires processing, so find out what is in there and do the | |
1612 | * appropriate read. | |
1613 | * | |
25985edc | 1614 | * The RXFIFO is a true FIFO, the packets coming out are still in packet |
5b7d70c6 BD |
1615 | * chunks, so if you have x packets received on an endpoint you'll get x |
1616 | * FIFO events delivered, each with a packet's worth of data in it. | |
1617 | * | |
1618 | * When using DMA, we should not be processing events from the RXFIFO | |
1619 | * as the actual data should be sent to the memory directly and we turn | |
1620 | * on the completion interrupts to get notifications of transfer completion. | |
1621 | */ | |
1f91b4cc | 1622 | static void dwc2_hsotg_handle_rx(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 1623 | { |
95c8bc36 | 1624 | u32 grxstsr = dwc2_readl(hsotg->regs + GRXSTSP); |
5b7d70c6 BD |
1625 | u32 epnum, status, size; |
1626 | ||
1627 | WARN_ON(using_dma(hsotg)); | |
1628 | ||
47a1685f DN |
1629 | epnum = grxstsr & GRXSTS_EPNUM_MASK; |
1630 | status = grxstsr & GRXSTS_PKTSTS_MASK; | |
5b7d70c6 | 1631 | |
47a1685f DN |
1632 | size = grxstsr & GRXSTS_BYTECNT_MASK; |
1633 | size >>= GRXSTS_BYTECNT_SHIFT; | |
5b7d70c6 | 1634 | |
d7c747c5 | 1635 | dev_dbg(hsotg->dev, "%s: GRXSTSP=0x%08x (%d@%d)\n", |
5b7d70c6 BD |
1636 | __func__, grxstsr, size, epnum); |
1637 | ||
47a1685f DN |
1638 | switch ((status & GRXSTS_PKTSTS_MASK) >> GRXSTS_PKTSTS_SHIFT) { |
1639 | case GRXSTS_PKTSTS_GLOBALOUTNAK: | |
1640 | dev_dbg(hsotg->dev, "GLOBALOUTNAK\n"); | |
5b7d70c6 BD |
1641 | break; |
1642 | ||
47a1685f | 1643 | case GRXSTS_PKTSTS_OUTDONE: |
5b7d70c6 | 1644 | dev_dbg(hsotg->dev, "OutDone (Frame=0x%08x)\n", |
1f91b4cc | 1645 | dwc2_hsotg_read_frameno(hsotg)); |
5b7d70c6 BD |
1646 | |
1647 | if (!using_dma(hsotg)) | |
1f91b4cc | 1648 | dwc2_hsotg_handle_outdone(hsotg, epnum); |
5b7d70c6 BD |
1649 | break; |
1650 | ||
47a1685f | 1651 | case GRXSTS_PKTSTS_SETUPDONE: |
5b7d70c6 BD |
1652 | dev_dbg(hsotg->dev, |
1653 | "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n", | |
1f91b4cc | 1654 | dwc2_hsotg_read_frameno(hsotg), |
95c8bc36 | 1655 | dwc2_readl(hsotg->regs + DOEPCTL(0))); |
fe0b94ab | 1656 | /* |
1f91b4cc | 1657 | * Call dwc2_hsotg_handle_outdone here if it was not called from |
fe0b94ab MYK |
1658 | * GRXSTS_PKTSTS_OUTDONE. That is, if the core didn't |
1659 | * generate GRXSTS_PKTSTS_OUTDONE for setup packet. | |
1660 | */ | |
1661 | if (hsotg->ep0_state == DWC2_EP0_SETUP) | |
1f91b4cc | 1662 | dwc2_hsotg_handle_outdone(hsotg, epnum); |
5b7d70c6 BD |
1663 | break; |
1664 | ||
47a1685f | 1665 | case GRXSTS_PKTSTS_OUTRX: |
1f91b4cc | 1666 | dwc2_hsotg_rx_data(hsotg, epnum, size); |
5b7d70c6 BD |
1667 | break; |
1668 | ||
47a1685f | 1669 | case GRXSTS_PKTSTS_SETUPRX: |
5b7d70c6 BD |
1670 | dev_dbg(hsotg->dev, |
1671 | "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n", | |
1f91b4cc | 1672 | dwc2_hsotg_read_frameno(hsotg), |
95c8bc36 | 1673 | dwc2_readl(hsotg->regs + DOEPCTL(0))); |
5b7d70c6 | 1674 | |
fe0b94ab MYK |
1675 | WARN_ON(hsotg->ep0_state != DWC2_EP0_SETUP); |
1676 | ||
1f91b4cc | 1677 | dwc2_hsotg_rx_data(hsotg, epnum, size); |
5b7d70c6 BD |
1678 | break; |
1679 | ||
1680 | default: | |
1681 | dev_warn(hsotg->dev, "%s: unknown status %08x\n", | |
1682 | __func__, grxstsr); | |
1683 | ||
1f91b4cc | 1684 | dwc2_hsotg_dump(hsotg); |
5b7d70c6 BD |
1685 | break; |
1686 | } | |
1687 | } | |
1688 | ||
1689 | /** | |
1f91b4cc | 1690 | * dwc2_hsotg_ep0_mps - turn max packet size into register setting |
5b7d70c6 | 1691 | * @mps: The maximum packet size in bytes. |
8b9bc460 | 1692 | */ |
1f91b4cc | 1693 | static u32 dwc2_hsotg_ep0_mps(unsigned int mps) |
5b7d70c6 BD |
1694 | { |
1695 | switch (mps) { | |
1696 | case 64: | |
94cb8fd6 | 1697 | return D0EPCTL_MPS_64; |
5b7d70c6 | 1698 | case 32: |
94cb8fd6 | 1699 | return D0EPCTL_MPS_32; |
5b7d70c6 | 1700 | case 16: |
94cb8fd6 | 1701 | return D0EPCTL_MPS_16; |
5b7d70c6 | 1702 | case 8: |
94cb8fd6 | 1703 | return D0EPCTL_MPS_8; |
5b7d70c6 BD |
1704 | } |
1705 | ||
1706 | /* bad max packet size, warn and return invalid result */ | |
1707 | WARN_ON(1); | |
1708 | return (u32)-1; | |
1709 | } | |
1710 | ||
1711 | /** | |
1f91b4cc | 1712 | * dwc2_hsotg_set_ep_maxpacket - set endpoint's max-packet field |
5b7d70c6 BD |
1713 | * @hsotg: The driver state. |
1714 | * @ep: The index number of the endpoint | |
1715 | * @mps: The maximum packet size in bytes | |
1716 | * | |
1717 | * Configure the maximum packet size for the given endpoint, updating | |
1718 | * the hardware control registers to reflect this. | |
1719 | */ | |
1f91b4cc | 1720 | static void dwc2_hsotg_set_ep_maxpacket(struct dwc2_hsotg *hsotg, |
c6f5c050 | 1721 | unsigned int ep, unsigned int mps, unsigned int dir_in) |
5b7d70c6 | 1722 | { |
1f91b4cc | 1723 | struct dwc2_hsotg_ep *hs_ep; |
5b7d70c6 BD |
1724 | void __iomem *regs = hsotg->regs; |
1725 | u32 mpsval; | |
4fca54aa | 1726 | u32 mcval; |
5b7d70c6 BD |
1727 | u32 reg; |
1728 | ||
c6f5c050 MYK |
1729 | hs_ep = index_to_ep(hsotg, ep, dir_in); |
1730 | if (!hs_ep) | |
1731 | return; | |
1732 | ||
5b7d70c6 BD |
1733 | if (ep == 0) { |
1734 | /* EP0 is a special case */ | |
1f91b4cc | 1735 | mpsval = dwc2_hsotg_ep0_mps(mps); |
5b7d70c6 BD |
1736 | if (mpsval > 3) |
1737 | goto bad_mps; | |
e9edd199 | 1738 | hs_ep->ep.maxpacket = mps; |
4fca54aa | 1739 | hs_ep->mc = 1; |
5b7d70c6 | 1740 | } else { |
47a1685f | 1741 | mpsval = mps & DXEPCTL_MPS_MASK; |
e9edd199 | 1742 | if (mpsval > 1024) |
5b7d70c6 | 1743 | goto bad_mps; |
4fca54aa RB |
1744 | mcval = ((mps >> 11) & 0x3) + 1; |
1745 | hs_ep->mc = mcval; | |
1746 | if (mcval > 3) | |
1747 | goto bad_mps; | |
e9edd199 | 1748 | hs_ep->ep.maxpacket = mpsval; |
5b7d70c6 BD |
1749 | } |
1750 | ||
c6f5c050 | 1751 | if (dir_in) { |
95c8bc36 | 1752 | reg = dwc2_readl(regs + DIEPCTL(ep)); |
c6f5c050 MYK |
1753 | reg &= ~DXEPCTL_MPS_MASK; |
1754 | reg |= mpsval; | |
95c8bc36 | 1755 | dwc2_writel(reg, regs + DIEPCTL(ep)); |
c6f5c050 | 1756 | } else { |
95c8bc36 | 1757 | reg = dwc2_readl(regs + DOEPCTL(ep)); |
47a1685f | 1758 | reg &= ~DXEPCTL_MPS_MASK; |
659ad60c | 1759 | reg |= mpsval; |
95c8bc36 | 1760 | dwc2_writel(reg, regs + DOEPCTL(ep)); |
659ad60c | 1761 | } |
5b7d70c6 BD |
1762 | |
1763 | return; | |
1764 | ||
1765 | bad_mps: | |
1766 | dev_err(hsotg->dev, "ep%d: bad mps of %d\n", ep, mps); | |
1767 | } | |
1768 | ||
9c39ddc6 | 1769 | /** |
1f91b4cc | 1770 | * dwc2_hsotg_txfifo_flush - flush Tx FIFO |
9c39ddc6 AT |
1771 | * @hsotg: The driver state |
1772 | * @idx: The index for the endpoint (0..15) | |
1773 | */ | |
1f91b4cc | 1774 | static void dwc2_hsotg_txfifo_flush(struct dwc2_hsotg *hsotg, unsigned int idx) |
9c39ddc6 AT |
1775 | { |
1776 | int timeout; | |
1777 | int val; | |
1778 | ||
95c8bc36 AS |
1779 | dwc2_writel(GRSTCTL_TXFNUM(idx) | GRSTCTL_TXFFLSH, |
1780 | hsotg->regs + GRSTCTL); | |
9c39ddc6 AT |
1781 | |
1782 | /* wait until the fifo is flushed */ | |
1783 | timeout = 100; | |
1784 | ||
1785 | while (1) { | |
95c8bc36 | 1786 | val = dwc2_readl(hsotg->regs + GRSTCTL); |
9c39ddc6 | 1787 | |
47a1685f | 1788 | if ((val & (GRSTCTL_TXFFLSH)) == 0) |
9c39ddc6 AT |
1789 | break; |
1790 | ||
1791 | if (--timeout == 0) { | |
1792 | dev_err(hsotg->dev, | |
1793 | "%s: timeout flushing fifo (GRSTCTL=%08x)\n", | |
1794 | __func__, val); | |
e0cbe595 | 1795 | break; |
9c39ddc6 AT |
1796 | } |
1797 | ||
1798 | udelay(1); | |
1799 | } | |
1800 | } | |
5b7d70c6 BD |
1801 | |
1802 | /** | |
1f91b4cc | 1803 | * dwc2_hsotg_trytx - check to see if anything needs transmitting |
5b7d70c6 BD |
1804 | * @hsotg: The driver state |
1805 | * @hs_ep: The driver endpoint to check. | |
1806 | * | |
1807 | * Check to see if there is a request that has data to send, and if so | |
1808 | * make an attempt to write data into the FIFO. | |
1809 | */ | |
1f91b4cc FB |
1810 | static int dwc2_hsotg_trytx(struct dwc2_hsotg *hsotg, |
1811 | struct dwc2_hsotg_ep *hs_ep) | |
5b7d70c6 | 1812 | { |
1f91b4cc | 1813 | struct dwc2_hsotg_req *hs_req = hs_ep->req; |
5b7d70c6 | 1814 | |
afcf4169 RB |
1815 | if (!hs_ep->dir_in || !hs_req) { |
1816 | /** | |
1817 | * if request is not enqueued, we disable interrupts | |
1818 | * for endpoints, excepting ep0 | |
1819 | */ | |
1820 | if (hs_ep->index != 0) | |
1f91b4cc | 1821 | dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, |
afcf4169 | 1822 | hs_ep->dir_in, 0); |
5b7d70c6 | 1823 | return 0; |
afcf4169 | 1824 | } |
5b7d70c6 BD |
1825 | |
1826 | if (hs_req->req.actual < hs_req->req.length) { | |
1827 | dev_dbg(hsotg->dev, "trying to write more for ep%d\n", | |
1828 | hs_ep->index); | |
1f91b4cc | 1829 | return dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req); |
5b7d70c6 BD |
1830 | } |
1831 | ||
1832 | return 0; | |
1833 | } | |
1834 | ||
1835 | /** | |
1f91b4cc | 1836 | * dwc2_hsotg_complete_in - complete IN transfer |
5b7d70c6 BD |
1837 | * @hsotg: The device state. |
1838 | * @hs_ep: The endpoint that has just completed. | |
1839 | * | |
1840 | * An IN transfer has been completed, update the transfer's state and then | |
1841 | * call the relevant completion routines. | |
1842 | */ | |
1f91b4cc FB |
1843 | static void dwc2_hsotg_complete_in(struct dwc2_hsotg *hsotg, |
1844 | struct dwc2_hsotg_ep *hs_ep) | |
5b7d70c6 | 1845 | { |
1f91b4cc | 1846 | struct dwc2_hsotg_req *hs_req = hs_ep->req; |
95c8bc36 | 1847 | u32 epsize = dwc2_readl(hsotg->regs + DIEPTSIZ(hs_ep->index)); |
5b7d70c6 BD |
1848 | int size_left, size_done; |
1849 | ||
1850 | if (!hs_req) { | |
1851 | dev_dbg(hsotg->dev, "XferCompl but no req\n"); | |
1852 | return; | |
1853 | } | |
1854 | ||
d3ca0259 | 1855 | /* Finish ZLP handling for IN EP0 transactions */ |
fe0b94ab MYK |
1856 | if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_IN) { |
1857 | dev_dbg(hsotg->dev, "zlp packet sent\n"); | |
1f91b4cc | 1858 | dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0); |
9e14d0a5 GH |
1859 | if (hsotg->test_mode) { |
1860 | int ret; | |
1861 | ||
1f91b4cc | 1862 | ret = dwc2_hsotg_set_test_mode(hsotg, hsotg->test_mode); |
9e14d0a5 GH |
1863 | if (ret < 0) { |
1864 | dev_dbg(hsotg->dev, "Invalid Test #%d\n", | |
1865 | hsotg->test_mode); | |
1f91b4cc | 1866 | dwc2_hsotg_stall_ep0(hsotg); |
9e14d0a5 GH |
1867 | return; |
1868 | } | |
1869 | } | |
1f91b4cc | 1870 | dwc2_hsotg_enqueue_setup(hsotg); |
d3ca0259 LM |
1871 | return; |
1872 | } | |
1873 | ||
8b9bc460 LM |
1874 | /* |
1875 | * Calculate the size of the transfer by checking how much is left | |
5b7d70c6 BD |
1876 | * in the endpoint size register and then working it out from |
1877 | * the amount we loaded for the transfer. | |
1878 | * | |
1879 | * We do this even for DMA, as the transfer may have incremented | |
1880 | * past the end of the buffer (DMA transfers are always 32bit | |
1881 | * aligned). | |
1882 | */ | |
1883 | ||
47a1685f | 1884 | size_left = DXEPTSIZ_XFERSIZE_GET(epsize); |
5b7d70c6 BD |
1885 | |
1886 | size_done = hs_ep->size_loaded - size_left; | |
1887 | size_done += hs_ep->last_load; | |
1888 | ||
1889 | if (hs_req->req.actual != size_done) | |
1890 | dev_dbg(hsotg->dev, "%s: adjusting size done %d => %d\n", | |
1891 | __func__, hs_req->req.actual, size_done); | |
1892 | ||
1893 | hs_req->req.actual = size_done; | |
d3ca0259 LM |
1894 | dev_dbg(hsotg->dev, "req->length:%d req->actual:%d req->zero:%d\n", |
1895 | hs_req->req.length, hs_req->req.actual, hs_req->req.zero); | |
1896 | ||
5b7d70c6 BD |
1897 | if (!size_left && hs_req->req.actual < hs_req->req.length) { |
1898 | dev_dbg(hsotg->dev, "%s trying more for req...\n", __func__); | |
1f91b4cc | 1899 | dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true); |
fe0b94ab MYK |
1900 | return; |
1901 | } | |
1902 | ||
f71b5e25 | 1903 | /* Zlp for all endpoints, for ep0 only in DATA IN stage */ |
8a20fa45 | 1904 | if (hs_ep->send_zlp) { |
1f91b4cc | 1905 | dwc2_hsotg_program_zlp(hsotg, hs_ep); |
8a20fa45 | 1906 | hs_ep->send_zlp = 0; |
f71b5e25 MYK |
1907 | /* transfer will be completed on next complete interrupt */ |
1908 | return; | |
1909 | } | |
1910 | ||
fe0b94ab MYK |
1911 | if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_DATA_IN) { |
1912 | /* Move to STATUS OUT */ | |
1f91b4cc | 1913 | dwc2_hsotg_ep0_zlp(hsotg, false); |
fe0b94ab MYK |
1914 | return; |
1915 | } | |
1916 | ||
1f91b4cc | 1917 | dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0); |
5b7d70c6 BD |
1918 | } |
1919 | ||
1920 | /** | |
1f91b4cc | 1921 | * dwc2_hsotg_epint - handle an in/out endpoint interrupt |
5b7d70c6 BD |
1922 | * @hsotg: The driver state |
1923 | * @idx: The index for the endpoint (0..15) | |
1924 | * @dir_in: Set if this is an IN endpoint | |
1925 | * | |
1926 | * Process and clear any interrupt pending for an individual endpoint | |
8b9bc460 | 1927 | */ |
1f91b4cc | 1928 | static void dwc2_hsotg_epint(struct dwc2_hsotg *hsotg, unsigned int idx, |
5b7d70c6 BD |
1929 | int dir_in) |
1930 | { | |
1f91b4cc | 1931 | struct dwc2_hsotg_ep *hs_ep = index_to_ep(hsotg, idx, dir_in); |
94cb8fd6 LM |
1932 | u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx); |
1933 | u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx); | |
1934 | u32 epsiz_reg = dir_in ? DIEPTSIZ(idx) : DOEPTSIZ(idx); | |
5b7d70c6 | 1935 | u32 ints; |
1479e841 | 1936 | u32 ctrl; |
5b7d70c6 | 1937 | |
95c8bc36 AS |
1938 | ints = dwc2_readl(hsotg->regs + epint_reg); |
1939 | ctrl = dwc2_readl(hsotg->regs + epctl_reg); | |
5b7d70c6 | 1940 | |
a3395f0d | 1941 | /* Clear endpoint interrupts */ |
95c8bc36 | 1942 | dwc2_writel(ints, hsotg->regs + epint_reg); |
a3395f0d | 1943 | |
c6f5c050 MYK |
1944 | if (!hs_ep) { |
1945 | dev_err(hsotg->dev, "%s:Interrupt for unconfigured ep%d(%s)\n", | |
1946 | __func__, idx, dir_in ? "in" : "out"); | |
1947 | return; | |
1948 | } | |
1949 | ||
5b7d70c6 BD |
1950 | dev_dbg(hsotg->dev, "%s: ep%d(%s) DxEPINT=0x%08x\n", |
1951 | __func__, idx, dir_in ? "in" : "out", ints); | |
1952 | ||
b787d755 MYK |
1953 | /* Don't process XferCompl interrupt if it is a setup packet */ |
1954 | if (idx == 0 && (ints & (DXEPINT_SETUP | DXEPINT_SETUP_RCVD))) | |
1955 | ints &= ~DXEPINT_XFERCOMPL; | |
1956 | ||
47a1685f | 1957 | if (ints & DXEPINT_XFERCOMPL) { |
1479e841 | 1958 | if (hs_ep->isochronous && hs_ep->interval == 1) { |
47a1685f DN |
1959 | if (ctrl & DXEPCTL_EOFRNUM) |
1960 | ctrl |= DXEPCTL_SETEVENFR; | |
1479e841 | 1961 | else |
47a1685f | 1962 | ctrl |= DXEPCTL_SETODDFR; |
95c8bc36 | 1963 | dwc2_writel(ctrl, hsotg->regs + epctl_reg); |
1479e841 RB |
1964 | } |
1965 | ||
5b7d70c6 | 1966 | dev_dbg(hsotg->dev, |
47a1685f | 1967 | "%s: XferCompl: DxEPCTL=0x%08x, DXEPTSIZ=%08x\n", |
95c8bc36 AS |
1968 | __func__, dwc2_readl(hsotg->regs + epctl_reg), |
1969 | dwc2_readl(hsotg->regs + epsiz_reg)); | |
5b7d70c6 | 1970 | |
8b9bc460 LM |
1971 | /* |
1972 | * we get OutDone from the FIFO, so we only need to look | |
1973 | * at completing IN requests here | |
1974 | */ | |
5b7d70c6 | 1975 | if (dir_in) { |
1f91b4cc | 1976 | dwc2_hsotg_complete_in(hsotg, hs_ep); |
5b7d70c6 | 1977 | |
c9a64ea8 | 1978 | if (idx == 0 && !hs_ep->req) |
1f91b4cc | 1979 | dwc2_hsotg_enqueue_setup(hsotg); |
5b7d70c6 | 1980 | } else if (using_dma(hsotg)) { |
8b9bc460 LM |
1981 | /* |
1982 | * We're using DMA, we need to fire an OutDone here | |
1983 | * as we ignore the RXFIFO. | |
1984 | */ | |
5b7d70c6 | 1985 | |
1f91b4cc | 1986 | dwc2_hsotg_handle_outdone(hsotg, idx); |
5b7d70c6 | 1987 | } |
5b7d70c6 BD |
1988 | } |
1989 | ||
47a1685f | 1990 | if (ints & DXEPINT_EPDISBLD) { |
5b7d70c6 | 1991 | dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__); |
5b7d70c6 | 1992 | |
9c39ddc6 | 1993 | if (dir_in) { |
95c8bc36 | 1994 | int epctl = dwc2_readl(hsotg->regs + epctl_reg); |
9c39ddc6 | 1995 | |
1f91b4cc | 1996 | dwc2_hsotg_txfifo_flush(hsotg, hs_ep->fifo_index); |
9c39ddc6 | 1997 | |
47a1685f DN |
1998 | if ((epctl & DXEPCTL_STALL) && |
1999 | (epctl & DXEPCTL_EPTYPE_BULK)) { | |
95c8bc36 | 2000 | int dctl = dwc2_readl(hsotg->regs + DCTL); |
9c39ddc6 | 2001 | |
47a1685f | 2002 | dctl |= DCTL_CGNPINNAK; |
95c8bc36 | 2003 | dwc2_writel(dctl, hsotg->regs + DCTL); |
9c39ddc6 AT |
2004 | } |
2005 | } | |
2006 | } | |
2007 | ||
47a1685f | 2008 | if (ints & DXEPINT_AHBERR) |
5b7d70c6 | 2009 | dev_dbg(hsotg->dev, "%s: AHBErr\n", __func__); |
5b7d70c6 | 2010 | |
47a1685f | 2011 | if (ints & DXEPINT_SETUP) { /* Setup or Timeout */ |
5b7d70c6 BD |
2012 | dev_dbg(hsotg->dev, "%s: Setup/Timeout\n", __func__); |
2013 | ||
2014 | if (using_dma(hsotg) && idx == 0) { | |
8b9bc460 LM |
2015 | /* |
2016 | * this is the notification we've received a | |
5b7d70c6 BD |
2017 | * setup packet. In non-DMA mode we'd get this |
2018 | * from the RXFIFO, instead we need to process | |
8b9bc460 LM |
2019 | * the setup here. |
2020 | */ | |
5b7d70c6 BD |
2021 | |
2022 | if (dir_in) | |
2023 | WARN_ON_ONCE(1); | |
2024 | else | |
1f91b4cc | 2025 | dwc2_hsotg_handle_outdone(hsotg, 0); |
5b7d70c6 | 2026 | } |
5b7d70c6 BD |
2027 | } |
2028 | ||
47a1685f | 2029 | if (ints & DXEPINT_BACK2BACKSETUP) |
5b7d70c6 | 2030 | dev_dbg(hsotg->dev, "%s: B2BSetup/INEPNakEff\n", __func__); |
5b7d70c6 | 2031 | |
1479e841 | 2032 | if (dir_in && !hs_ep->isochronous) { |
8b9bc460 | 2033 | /* not sure if this is important, but we'll clear it anyway */ |
47a1685f | 2034 | if (ints & DIEPMSK_INTKNTXFEMPMSK) { |
5b7d70c6 BD |
2035 | dev_dbg(hsotg->dev, "%s: ep%d: INTknTXFEmpMsk\n", |
2036 | __func__, idx); | |
5b7d70c6 BD |
2037 | } |
2038 | ||
2039 | /* this probably means something bad is happening */ | |
47a1685f | 2040 | if (ints & DIEPMSK_INTKNEPMISMSK) { |
5b7d70c6 BD |
2041 | dev_warn(hsotg->dev, "%s: ep%d: INTknEP\n", |
2042 | __func__, idx); | |
5b7d70c6 | 2043 | } |
10aebc77 BD |
2044 | |
2045 | /* FIFO has space or is empty (see GAHBCFG) */ | |
2046 | if (hsotg->dedicated_fifos && | |
47a1685f | 2047 | ints & DIEPMSK_TXFIFOEMPTY) { |
10aebc77 BD |
2048 | dev_dbg(hsotg->dev, "%s: ep%d: TxFIFOEmpty\n", |
2049 | __func__, idx); | |
70fa030f | 2050 | if (!using_dma(hsotg)) |
1f91b4cc | 2051 | dwc2_hsotg_trytx(hsotg, hs_ep); |
10aebc77 | 2052 | } |
5b7d70c6 | 2053 | } |
5b7d70c6 BD |
2054 | } |
2055 | ||
2056 | /** | |
1f91b4cc | 2057 | * dwc2_hsotg_irq_enumdone - Handle EnumDone interrupt (enumeration done) |
5b7d70c6 BD |
2058 | * @hsotg: The device state. |
2059 | * | |
2060 | * Handle updating the device settings after the enumeration phase has | |
2061 | * been completed. | |
8b9bc460 | 2062 | */ |
1f91b4cc | 2063 | static void dwc2_hsotg_irq_enumdone(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 2064 | { |
95c8bc36 | 2065 | u32 dsts = dwc2_readl(hsotg->regs + DSTS); |
9b2667f1 | 2066 | int ep0_mps = 0, ep_mps = 8; |
5b7d70c6 | 2067 | |
8b9bc460 LM |
2068 | /* |
2069 | * This should signal the finish of the enumeration phase | |
5b7d70c6 | 2070 | * of the USB handshaking, so we should now know what rate |
8b9bc460 LM |
2071 | * we connected at. |
2072 | */ | |
5b7d70c6 BD |
2073 | |
2074 | dev_dbg(hsotg->dev, "EnumDone (DSTS=0x%08x)\n", dsts); | |
2075 | ||
8b9bc460 LM |
2076 | /* |
2077 | * note, since we're limited by the size of transfer on EP0, and | |
5b7d70c6 | 2078 | * it seems IN transfers must be a even number of packets we do |
8b9bc460 LM |
2079 | * not advertise a 64byte MPS on EP0. |
2080 | */ | |
5b7d70c6 BD |
2081 | |
2082 | /* catch both EnumSpd_FS and EnumSpd_FS48 */ | |
47a1685f DN |
2083 | switch (dsts & DSTS_ENUMSPD_MASK) { |
2084 | case DSTS_ENUMSPD_FS: | |
2085 | case DSTS_ENUMSPD_FS48: | |
5b7d70c6 | 2086 | hsotg->gadget.speed = USB_SPEED_FULL; |
5b7d70c6 | 2087 | ep0_mps = EP0_MPS_LIMIT; |
295538ff | 2088 | ep_mps = 1023; |
5b7d70c6 BD |
2089 | break; |
2090 | ||
47a1685f | 2091 | case DSTS_ENUMSPD_HS: |
5b7d70c6 | 2092 | hsotg->gadget.speed = USB_SPEED_HIGH; |
5b7d70c6 | 2093 | ep0_mps = EP0_MPS_LIMIT; |
295538ff | 2094 | ep_mps = 1024; |
5b7d70c6 BD |
2095 | break; |
2096 | ||
47a1685f | 2097 | case DSTS_ENUMSPD_LS: |
5b7d70c6 | 2098 | hsotg->gadget.speed = USB_SPEED_LOW; |
8b9bc460 LM |
2099 | /* |
2100 | * note, we don't actually support LS in this driver at the | |
5b7d70c6 BD |
2101 | * moment, and the documentation seems to imply that it isn't |
2102 | * supported by the PHYs on some of the devices. | |
2103 | */ | |
2104 | break; | |
2105 | } | |
e538dfda MN |
2106 | dev_info(hsotg->dev, "new device is %s\n", |
2107 | usb_speed_string(hsotg->gadget.speed)); | |
5b7d70c6 | 2108 | |
8b9bc460 LM |
2109 | /* |
2110 | * we should now know the maximum packet size for an | |
2111 | * endpoint, so set the endpoints to a default value. | |
2112 | */ | |
5b7d70c6 BD |
2113 | |
2114 | if (ep0_mps) { | |
2115 | int i; | |
c6f5c050 | 2116 | /* Initialize ep0 for both in and out directions */ |
1f91b4cc FB |
2117 | dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 1); |
2118 | dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 0); | |
c6f5c050 MYK |
2119 | for (i = 1; i < hsotg->num_of_eps; i++) { |
2120 | if (hsotg->eps_in[i]) | |
1f91b4cc | 2121 | dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps, 1); |
c6f5c050 | 2122 | if (hsotg->eps_out[i]) |
1f91b4cc | 2123 | dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps, 0); |
c6f5c050 | 2124 | } |
5b7d70c6 BD |
2125 | } |
2126 | ||
2127 | /* ensure after enumeration our EP0 is active */ | |
2128 | ||
1f91b4cc | 2129 | dwc2_hsotg_enqueue_setup(hsotg); |
5b7d70c6 BD |
2130 | |
2131 | dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n", | |
95c8bc36 AS |
2132 | dwc2_readl(hsotg->regs + DIEPCTL0), |
2133 | dwc2_readl(hsotg->regs + DOEPCTL0)); | |
5b7d70c6 BD |
2134 | } |
2135 | ||
2136 | /** | |
2137 | * kill_all_requests - remove all requests from the endpoint's queue | |
2138 | * @hsotg: The device state. | |
2139 | * @ep: The endpoint the requests may be on. | |
2140 | * @result: The result code to use. | |
5b7d70c6 BD |
2141 | * |
2142 | * Go through the requests on the given endpoint and mark them | |
2143 | * completed with the given result code. | |
2144 | */ | |
941fcce4 | 2145 | static void kill_all_requests(struct dwc2_hsotg *hsotg, |
1f91b4cc | 2146 | struct dwc2_hsotg_ep *ep, |
6b448af4 | 2147 | int result) |
5b7d70c6 | 2148 | { |
1f91b4cc | 2149 | struct dwc2_hsotg_req *req, *treq; |
b203d0a2 | 2150 | unsigned size; |
5b7d70c6 | 2151 | |
6b448af4 | 2152 | ep->req = NULL; |
5b7d70c6 | 2153 | |
6b448af4 | 2154 | list_for_each_entry_safe(req, treq, &ep->queue, queue) |
1f91b4cc | 2155 | dwc2_hsotg_complete_request(hsotg, ep, req, |
5b7d70c6 | 2156 | result); |
6b448af4 | 2157 | |
b203d0a2 RB |
2158 | if (!hsotg->dedicated_fifos) |
2159 | return; | |
95c8bc36 | 2160 | size = (dwc2_readl(hsotg->regs + DTXFSTS(ep->index)) & 0xffff) * 4; |
b203d0a2 | 2161 | if (size < ep->fifo_size) |
1f91b4cc | 2162 | dwc2_hsotg_txfifo_flush(hsotg, ep->fifo_index); |
5b7d70c6 BD |
2163 | } |
2164 | ||
5b7d70c6 | 2165 | /** |
1f91b4cc | 2166 | * dwc2_hsotg_disconnect - disconnect service |
5b7d70c6 BD |
2167 | * @hsotg: The device state. |
2168 | * | |
5e891342 LM |
2169 | * The device has been disconnected. Remove all current |
2170 | * transactions and signal the gadget driver that this | |
2171 | * has happened. | |
8b9bc460 | 2172 | */ |
1f91b4cc | 2173 | void dwc2_hsotg_disconnect(struct dwc2_hsotg *hsotg) |
5b7d70c6 BD |
2174 | { |
2175 | unsigned ep; | |
2176 | ||
4ace06e8 MS |
2177 | if (!hsotg->connected) |
2178 | return; | |
2179 | ||
2180 | hsotg->connected = 0; | |
9e14d0a5 | 2181 | hsotg->test_mode = 0; |
c6f5c050 MYK |
2182 | |
2183 | for (ep = 0; ep < hsotg->num_of_eps; ep++) { | |
2184 | if (hsotg->eps_in[ep]) | |
2185 | kill_all_requests(hsotg, hsotg->eps_in[ep], | |
2186 | -ESHUTDOWN); | |
2187 | if (hsotg->eps_out[ep]) | |
2188 | kill_all_requests(hsotg, hsotg->eps_out[ep], | |
2189 | -ESHUTDOWN); | |
2190 | } | |
5b7d70c6 BD |
2191 | |
2192 | call_gadget(hsotg, disconnect); | |
065d3931 | 2193 | hsotg->lx_state = DWC2_L3; |
5b7d70c6 BD |
2194 | } |
2195 | ||
2196 | /** | |
1f91b4cc | 2197 | * dwc2_hsotg_irq_fifoempty - TX FIFO empty interrupt handler |
5b7d70c6 BD |
2198 | * @hsotg: The device state: |
2199 | * @periodic: True if this is a periodic FIFO interrupt | |
2200 | */ | |
1f91b4cc | 2201 | static void dwc2_hsotg_irq_fifoempty(struct dwc2_hsotg *hsotg, bool periodic) |
5b7d70c6 | 2202 | { |
1f91b4cc | 2203 | struct dwc2_hsotg_ep *ep; |
5b7d70c6 BD |
2204 | int epno, ret; |
2205 | ||
2206 | /* look through for any more data to transmit */ | |
b3f489b2 | 2207 | for (epno = 0; epno < hsotg->num_of_eps; epno++) { |
c6f5c050 MYK |
2208 | ep = index_to_ep(hsotg, epno, 1); |
2209 | ||
2210 | if (!ep) | |
2211 | continue; | |
5b7d70c6 BD |
2212 | |
2213 | if (!ep->dir_in) | |
2214 | continue; | |
2215 | ||
2216 | if ((periodic && !ep->periodic) || | |
2217 | (!periodic && ep->periodic)) | |
2218 | continue; | |
2219 | ||
1f91b4cc | 2220 | ret = dwc2_hsotg_trytx(hsotg, ep); |
5b7d70c6 BD |
2221 | if (ret < 0) |
2222 | break; | |
2223 | } | |
2224 | } | |
2225 | ||
5b7d70c6 | 2226 | /* IRQ flags which will trigger a retry around the IRQ loop */ |
47a1685f DN |
2227 | #define IRQ_RETRY_MASK (GINTSTS_NPTXFEMP | \ |
2228 | GINTSTS_PTXFEMP | \ | |
2229 | GINTSTS_RXFLVL) | |
5b7d70c6 | 2230 | |
308d734e | 2231 | /** |
1f91b4cc | 2232 | * dwc2_hsotg_corereset - issue softreset to the core |
308d734e LM |
2233 | * @hsotg: The device state |
2234 | * | |
2235 | * Issue a soft reset to the core, and await the core finishing it. | |
8b9bc460 | 2236 | */ |
1f91b4cc | 2237 | static int dwc2_hsotg_corereset(struct dwc2_hsotg *hsotg) |
308d734e LM |
2238 | { |
2239 | int timeout; | |
2240 | u32 grstctl; | |
2241 | ||
2242 | dev_dbg(hsotg->dev, "resetting core\n"); | |
2243 | ||
2244 | /* issue soft reset */ | |
95c8bc36 | 2245 | dwc2_writel(GRSTCTL_CSFTRST, hsotg->regs + GRSTCTL); |
308d734e | 2246 | |
2868fea2 | 2247 | timeout = 10000; |
308d734e | 2248 | do { |
95c8bc36 | 2249 | grstctl = dwc2_readl(hsotg->regs + GRSTCTL); |
47a1685f | 2250 | } while ((grstctl & GRSTCTL_CSFTRST) && timeout-- > 0); |
308d734e | 2251 | |
47a1685f | 2252 | if (grstctl & GRSTCTL_CSFTRST) { |
308d734e LM |
2253 | dev_err(hsotg->dev, "Failed to get CSftRst asserted\n"); |
2254 | return -EINVAL; | |
2255 | } | |
2256 | ||
2868fea2 | 2257 | timeout = 10000; |
308d734e LM |
2258 | |
2259 | while (1) { | |
95c8bc36 | 2260 | u32 grstctl = dwc2_readl(hsotg->regs + GRSTCTL); |
308d734e LM |
2261 | |
2262 | if (timeout-- < 0) { | |
2263 | dev_info(hsotg->dev, | |
2264 | "%s: reset failed, GRSTCTL=%08x\n", | |
2265 | __func__, grstctl); | |
2266 | return -ETIMEDOUT; | |
2267 | } | |
2268 | ||
47a1685f | 2269 | if (!(grstctl & GRSTCTL_AHBIDLE)) |
308d734e LM |
2270 | continue; |
2271 | ||
2272 | break; /* reset done */ | |
2273 | } | |
2274 | ||
2275 | dev_dbg(hsotg->dev, "reset successful\n"); | |
2276 | return 0; | |
2277 | } | |
2278 | ||
8b9bc460 | 2279 | /** |
1f91b4cc | 2280 | * dwc2_hsotg_core_init - issue softreset to the core |
8b9bc460 LM |
2281 | * @hsotg: The device state |
2282 | * | |
2283 | * Issue a soft reset to the core, and await the core finishing it. | |
2284 | */ | |
1f91b4cc | 2285 | void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg, |
643cc4de | 2286 | bool is_usb_reset) |
308d734e | 2287 | { |
1ee6903b | 2288 | u32 intmsk; |
643cc4de GH |
2289 | u32 val; |
2290 | ||
5390d438 MYK |
2291 | /* Kill any ep0 requests as controller will be reinitialized */ |
2292 | kill_all_requests(hsotg, hsotg->eps_out[0], -ECONNRESET); | |
2293 | ||
643cc4de | 2294 | if (!is_usb_reset) |
86de4895 GH |
2295 | if (dwc2_hsotg_corereset(hsotg)) |
2296 | return; | |
308d734e LM |
2297 | |
2298 | /* | |
2299 | * we must now enable ep0 ready for host detection and then | |
2300 | * set configuration. | |
2301 | */ | |
2302 | ||
2303 | /* set the PLL on, remove the HNP/SRP and set the PHY */ | |
fa4a8d72 | 2304 | val = (hsotg->phyif == GUSBCFG_PHYIF8) ? 9 : 5; |
95c8bc36 | 2305 | dwc2_writel(hsotg->phyif | GUSBCFG_TOUTCAL(7) | |
f889f23d | 2306 | (val << GUSBCFG_USBTRDTIM_SHIFT), hsotg->regs + GUSBCFG); |
308d734e | 2307 | |
1f91b4cc | 2308 | dwc2_hsotg_init_fifo(hsotg); |
308d734e | 2309 | |
643cc4de GH |
2310 | if (!is_usb_reset) |
2311 | __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON); | |
308d734e | 2312 | |
95c8bc36 | 2313 | dwc2_writel(DCFG_EPMISCNT(1) | DCFG_DEVSPD_HS, hsotg->regs + DCFG); |
308d734e LM |
2314 | |
2315 | /* Clear any pending OTG interrupts */ | |
95c8bc36 | 2316 | dwc2_writel(0xffffffff, hsotg->regs + GOTGINT); |
308d734e LM |
2317 | |
2318 | /* Clear any pending interrupts */ | |
95c8bc36 | 2319 | dwc2_writel(0xffffffff, hsotg->regs + GINTSTS); |
1ee6903b | 2320 | intmsk = GINTSTS_ERLYSUSP | GINTSTS_SESSREQINT | |
47a1685f | 2321 | GINTSTS_GOUTNAKEFF | GINTSTS_GINNAKEFF | |
1ee6903b GH |
2322 | GINTSTS_USBRST | GINTSTS_RESETDET | |
2323 | GINTSTS_ENUMDONE | GINTSTS_OTGINT | | |
2324 | GINTSTS_USBSUSP | GINTSTS_WKUPINT; | |
2325 | ||
2326 | if (hsotg->core_params->external_id_pin_ctl <= 0) | |
2327 | intmsk |= GINTSTS_CONIDSTSCHNG; | |
2328 | ||
2329 | dwc2_writel(intmsk, hsotg->regs + GINTMSK); | |
308d734e LM |
2330 | |
2331 | if (using_dma(hsotg)) | |
95c8bc36 AS |
2332 | dwc2_writel(GAHBCFG_GLBL_INTR_EN | GAHBCFG_DMA_EN | |
2333 | (GAHBCFG_HBSTLEN_INCR4 << GAHBCFG_HBSTLEN_SHIFT), | |
2334 | hsotg->regs + GAHBCFG); | |
308d734e | 2335 | else |
95c8bc36 AS |
2336 | dwc2_writel(((hsotg->dedicated_fifos) ? |
2337 | (GAHBCFG_NP_TXF_EMP_LVL | | |
2338 | GAHBCFG_P_TXF_EMP_LVL) : 0) | | |
2339 | GAHBCFG_GLBL_INTR_EN, hsotg->regs + GAHBCFG); | |
308d734e LM |
2340 | |
2341 | /* | |
8acc8296 RB |
2342 | * If INTknTXFEmpMsk is enabled, it's important to disable ep interrupts |
2343 | * when we have no data to transfer. Otherwise we get being flooded by | |
2344 | * interrupts. | |
308d734e LM |
2345 | */ |
2346 | ||
95c8bc36 | 2347 | dwc2_writel(((hsotg->dedicated_fifos && !using_dma(hsotg)) ? |
6ff2e832 | 2348 | DIEPMSK_TXFIFOEMPTY | DIEPMSK_INTKNTXFEMPMSK : 0) | |
47a1685f DN |
2349 | DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK | |
2350 | DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK | | |
2351 | DIEPMSK_INTKNEPMISMSK, | |
2352 | hsotg->regs + DIEPMSK); | |
308d734e LM |
2353 | |
2354 | /* | |
2355 | * don't need XferCompl, we get that from RXFIFO in slave mode. In | |
2356 | * DMA mode we may need this. | |
2357 | */ | |
95c8bc36 | 2358 | dwc2_writel((using_dma(hsotg) ? (DIEPMSK_XFERCOMPLMSK | |
47a1685f DN |
2359 | DIEPMSK_TIMEOUTMSK) : 0) | |
2360 | DOEPMSK_EPDISBLDMSK | DOEPMSK_AHBERRMSK | | |
2361 | DOEPMSK_SETUPMSK, | |
2362 | hsotg->regs + DOEPMSK); | |
308d734e | 2363 | |
95c8bc36 | 2364 | dwc2_writel(0, hsotg->regs + DAINTMSK); |
308d734e LM |
2365 | |
2366 | dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n", | |
95c8bc36 AS |
2367 | dwc2_readl(hsotg->regs + DIEPCTL0), |
2368 | dwc2_readl(hsotg->regs + DOEPCTL0)); | |
308d734e LM |
2369 | |
2370 | /* enable in and out endpoint interrupts */ | |
1f91b4cc | 2371 | dwc2_hsotg_en_gsint(hsotg, GINTSTS_OEPINT | GINTSTS_IEPINT); |
308d734e LM |
2372 | |
2373 | /* | |
2374 | * Enable the RXFIFO when in slave mode, as this is how we collect | |
2375 | * the data. In DMA mode, we get events from the FIFO but also | |
2376 | * things we cannot process, so do not use it. | |
2377 | */ | |
2378 | if (!using_dma(hsotg)) | |
1f91b4cc | 2379 | dwc2_hsotg_en_gsint(hsotg, GINTSTS_RXFLVL); |
308d734e LM |
2380 | |
2381 | /* Enable interrupts for EP0 in and out */ | |
1f91b4cc FB |
2382 | dwc2_hsotg_ctrl_epint(hsotg, 0, 0, 1); |
2383 | dwc2_hsotg_ctrl_epint(hsotg, 0, 1, 1); | |
308d734e | 2384 | |
643cc4de GH |
2385 | if (!is_usb_reset) { |
2386 | __orr32(hsotg->regs + DCTL, DCTL_PWRONPRGDONE); | |
2387 | udelay(10); /* see openiboot */ | |
2388 | __bic32(hsotg->regs + DCTL, DCTL_PWRONPRGDONE); | |
2389 | } | |
308d734e | 2390 | |
95c8bc36 | 2391 | dev_dbg(hsotg->dev, "DCTL=0x%08x\n", dwc2_readl(hsotg->regs + DCTL)); |
308d734e LM |
2392 | |
2393 | /* | |
94cb8fd6 | 2394 | * DxEPCTL_USBActEp says RO in manual, but seems to be set by |
308d734e LM |
2395 | * writing to the EPCTL register.. |
2396 | */ | |
2397 | ||
2398 | /* set to read 1 8byte packet */ | |
95c8bc36 | 2399 | dwc2_writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) | |
47a1685f | 2400 | DXEPTSIZ_XFERSIZE(8), hsotg->regs + DOEPTSIZ0); |
308d734e | 2401 | |
95c8bc36 | 2402 | dwc2_writel(dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) | |
47a1685f DN |
2403 | DXEPCTL_CNAK | DXEPCTL_EPENA | |
2404 | DXEPCTL_USBACTEP, | |
94cb8fd6 | 2405 | hsotg->regs + DOEPCTL0); |
308d734e LM |
2406 | |
2407 | /* enable, but don't activate EP0in */ | |
95c8bc36 | 2408 | dwc2_writel(dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) | |
47a1685f | 2409 | DXEPCTL_USBACTEP, hsotg->regs + DIEPCTL0); |
308d734e | 2410 | |
1f91b4cc | 2411 | dwc2_hsotg_enqueue_setup(hsotg); |
308d734e LM |
2412 | |
2413 | dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n", | |
95c8bc36 AS |
2414 | dwc2_readl(hsotg->regs + DIEPCTL0), |
2415 | dwc2_readl(hsotg->regs + DOEPCTL0)); | |
308d734e LM |
2416 | |
2417 | /* clear global NAKs */ | |
643cc4de GH |
2418 | val = DCTL_CGOUTNAK | DCTL_CGNPINNAK; |
2419 | if (!is_usb_reset) | |
2420 | val |= DCTL_SFTDISCON; | |
2421 | __orr32(hsotg->regs + DCTL, val); | |
308d734e LM |
2422 | |
2423 | /* must be at-least 3ms to allow bus to see disconnect */ | |
2424 | mdelay(3); | |
2425 | ||
065d3931 | 2426 | hsotg->lx_state = DWC2_L0; |
ad38dc5d MS |
2427 | } |
2428 | ||
1f91b4cc | 2429 | static void dwc2_hsotg_core_disconnect(struct dwc2_hsotg *hsotg) |
ad38dc5d MS |
2430 | { |
2431 | /* set the soft-disconnect bit */ | |
2432 | __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON); | |
2433 | } | |
ac3c81f3 | 2434 | |
1f91b4cc | 2435 | void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg) |
ad38dc5d | 2436 | { |
308d734e | 2437 | /* remove the soft-disconnect and let's go */ |
47a1685f | 2438 | __bic32(hsotg->regs + DCTL, DCTL_SFTDISCON); |
308d734e LM |
2439 | } |
2440 | ||
5b7d70c6 | 2441 | /** |
1f91b4cc | 2442 | * dwc2_hsotg_irq - handle device interrupt |
5b7d70c6 BD |
2443 | * @irq: The IRQ number triggered |
2444 | * @pw: The pw value when registered the handler. | |
2445 | */ | |
1f91b4cc | 2446 | static irqreturn_t dwc2_hsotg_irq(int irq, void *pw) |
5b7d70c6 | 2447 | { |
941fcce4 | 2448 | struct dwc2_hsotg *hsotg = pw; |
5b7d70c6 BD |
2449 | int retry_count = 8; |
2450 | u32 gintsts; | |
2451 | u32 gintmsk; | |
2452 | ||
5ad1d316 | 2453 | spin_lock(&hsotg->lock); |
5b7d70c6 | 2454 | irq_retry: |
95c8bc36 AS |
2455 | gintsts = dwc2_readl(hsotg->regs + GINTSTS); |
2456 | gintmsk = dwc2_readl(hsotg->regs + GINTMSK); | |
5b7d70c6 BD |
2457 | |
2458 | dev_dbg(hsotg->dev, "%s: %08x %08x (%08x) retry %d\n", | |
2459 | __func__, gintsts, gintsts & gintmsk, gintmsk, retry_count); | |
2460 | ||
2461 | gintsts &= gintmsk; | |
2462 | ||
47a1685f | 2463 | if (gintsts & GINTSTS_ENUMDONE) { |
95c8bc36 | 2464 | dwc2_writel(GINTSTS_ENUMDONE, hsotg->regs + GINTSTS); |
a3395f0d | 2465 | |
1f91b4cc | 2466 | dwc2_hsotg_irq_enumdone(hsotg); |
5b7d70c6 BD |
2467 | } |
2468 | ||
47a1685f | 2469 | if (gintsts & (GINTSTS_OEPINT | GINTSTS_IEPINT)) { |
95c8bc36 AS |
2470 | u32 daint = dwc2_readl(hsotg->regs + DAINT); |
2471 | u32 daintmsk = dwc2_readl(hsotg->regs + DAINTMSK); | |
7e804650 | 2472 | u32 daint_out, daint_in; |
5b7d70c6 BD |
2473 | int ep; |
2474 | ||
7e804650 | 2475 | daint &= daintmsk; |
47a1685f DN |
2476 | daint_out = daint >> DAINT_OUTEP_SHIFT; |
2477 | daint_in = daint & ~(daint_out << DAINT_OUTEP_SHIFT); | |
7e804650 | 2478 | |
5b7d70c6 BD |
2479 | dev_dbg(hsotg->dev, "%s: daint=%08x\n", __func__, daint); |
2480 | ||
cec87f1d MYK |
2481 | for (ep = 0; ep < hsotg->num_of_eps && daint_out; |
2482 | ep++, daint_out >>= 1) { | |
5b7d70c6 | 2483 | if (daint_out & 1) |
1f91b4cc | 2484 | dwc2_hsotg_epint(hsotg, ep, 0); |
5b7d70c6 BD |
2485 | } |
2486 | ||
cec87f1d MYK |
2487 | for (ep = 0; ep < hsotg->num_of_eps && daint_in; |
2488 | ep++, daint_in >>= 1) { | |
5b7d70c6 | 2489 | if (daint_in & 1) |
1f91b4cc | 2490 | dwc2_hsotg_epint(hsotg, ep, 1); |
5b7d70c6 | 2491 | } |
5b7d70c6 BD |
2492 | } |
2493 | ||
4876886f GH |
2494 | if (gintsts & GINTSTS_RESETDET) { |
2495 | dev_dbg(hsotg->dev, "%s: USBRstDet\n", __func__); | |
2496 | ||
95c8bc36 | 2497 | dwc2_writel(GINTSTS_RESETDET, hsotg->regs + GINTSTS); |
4876886f GH |
2498 | |
2499 | /* This event must be used only if controller is suspended */ | |
2500 | if (hsotg->lx_state == DWC2_L2) { | |
2501 | dwc2_exit_hibernation(hsotg, true); | |
2502 | hsotg->lx_state = DWC2_L0; | |
2503 | } | |
2504 | } | |
2505 | ||
2506 | if (gintsts & (GINTSTS_USBRST | GINTSTS_RESETDET)) { | |
12a1f4dc | 2507 | |
95c8bc36 | 2508 | u32 usb_status = dwc2_readl(hsotg->regs + GOTGCTL); |
2becdc62 | 2509 | u32 connected = hsotg->connected; |
12a1f4dc | 2510 | |
9599815d | 2511 | dev_dbg(hsotg->dev, "%s: USBRst\n", __func__); |
5b7d70c6 | 2512 | dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n", |
95c8bc36 | 2513 | dwc2_readl(hsotg->regs + GNPTXSTS)); |
5b7d70c6 | 2514 | |
95c8bc36 | 2515 | dwc2_writel(GINTSTS_USBRST, hsotg->regs + GINTSTS); |
a3395f0d | 2516 | |
6d713c15 | 2517 | /* Report disconnection if it is not already done. */ |
1f91b4cc | 2518 | dwc2_hsotg_disconnect(hsotg); |
6d713c15 | 2519 | |
2becdc62 MYK |
2520 | if (usb_status & GOTGCTL_BSESVLD && connected) |
2521 | dwc2_hsotg_core_init_disconnected(hsotg, true); | |
5b7d70c6 BD |
2522 | } |
2523 | ||
2524 | /* check both FIFOs */ | |
2525 | ||
47a1685f | 2526 | if (gintsts & GINTSTS_NPTXFEMP) { |
5b7d70c6 BD |
2527 | dev_dbg(hsotg->dev, "NPTxFEmp\n"); |
2528 | ||
8b9bc460 LM |
2529 | /* |
2530 | * Disable the interrupt to stop it happening again | |
5b7d70c6 | 2531 | * unless one of these endpoint routines decides that |
8b9bc460 LM |
2532 | * it needs re-enabling |
2533 | */ | |
5b7d70c6 | 2534 | |
1f91b4cc FB |
2535 | dwc2_hsotg_disable_gsint(hsotg, GINTSTS_NPTXFEMP); |
2536 | dwc2_hsotg_irq_fifoempty(hsotg, false); | |
5b7d70c6 BD |
2537 | } |
2538 | ||
47a1685f | 2539 | if (gintsts & GINTSTS_PTXFEMP) { |
5b7d70c6 BD |
2540 | dev_dbg(hsotg->dev, "PTxFEmp\n"); |
2541 | ||
94cb8fd6 | 2542 | /* See note in GINTSTS_NPTxFEmp */ |
5b7d70c6 | 2543 | |
1f91b4cc FB |
2544 | dwc2_hsotg_disable_gsint(hsotg, GINTSTS_PTXFEMP); |
2545 | dwc2_hsotg_irq_fifoempty(hsotg, true); | |
5b7d70c6 BD |
2546 | } |
2547 | ||
47a1685f | 2548 | if (gintsts & GINTSTS_RXFLVL) { |
8b9bc460 LM |
2549 | /* |
2550 | * note, since GINTSTS_RxFLvl doubles as FIFO-not-empty, | |
1f91b4cc | 2551 | * we need to retry dwc2_hsotg_handle_rx if this is still |
8b9bc460 LM |
2552 | * set. |
2553 | */ | |
5b7d70c6 | 2554 | |
1f91b4cc | 2555 | dwc2_hsotg_handle_rx(hsotg); |
5b7d70c6 BD |
2556 | } |
2557 | ||
47a1685f | 2558 | if (gintsts & GINTSTS_ERLYSUSP) { |
94cb8fd6 | 2559 | dev_dbg(hsotg->dev, "GINTSTS_ErlySusp\n"); |
95c8bc36 | 2560 | dwc2_writel(GINTSTS_ERLYSUSP, hsotg->regs + GINTSTS); |
5b7d70c6 BD |
2561 | } |
2562 | ||
8b9bc460 LM |
2563 | /* |
2564 | * these next two seem to crop-up occasionally causing the core | |
5b7d70c6 | 2565 | * to shutdown the USB transfer, so try clearing them and logging |
8b9bc460 LM |
2566 | * the occurrence. |
2567 | */ | |
5b7d70c6 | 2568 | |
47a1685f | 2569 | if (gintsts & GINTSTS_GOUTNAKEFF) { |
5b7d70c6 BD |
2570 | dev_info(hsotg->dev, "GOUTNakEff triggered\n"); |
2571 | ||
95c8bc36 | 2572 | dwc2_writel(DCTL_CGOUTNAK, hsotg->regs + DCTL); |
a3395f0d | 2573 | |
1f91b4cc | 2574 | dwc2_hsotg_dump(hsotg); |
5b7d70c6 BD |
2575 | } |
2576 | ||
47a1685f | 2577 | if (gintsts & GINTSTS_GINNAKEFF) { |
5b7d70c6 BD |
2578 | dev_info(hsotg->dev, "GINNakEff triggered\n"); |
2579 | ||
95c8bc36 | 2580 | dwc2_writel(DCTL_CGNPINNAK, hsotg->regs + DCTL); |
a3395f0d | 2581 | |
1f91b4cc | 2582 | dwc2_hsotg_dump(hsotg); |
5b7d70c6 BD |
2583 | } |
2584 | ||
8b9bc460 LM |
2585 | /* |
2586 | * if we've had fifo events, we should try and go around the | |
2587 | * loop again to see if there's any point in returning yet. | |
2588 | */ | |
5b7d70c6 BD |
2589 | |
2590 | if (gintsts & IRQ_RETRY_MASK && --retry_count > 0) | |
2591 | goto irq_retry; | |
2592 | ||
5ad1d316 LM |
2593 | spin_unlock(&hsotg->lock); |
2594 | ||
5b7d70c6 BD |
2595 | return IRQ_HANDLED; |
2596 | } | |
2597 | ||
2598 | /** | |
1f91b4cc | 2599 | * dwc2_hsotg_ep_enable - enable the given endpoint |
5b7d70c6 BD |
2600 | * @ep: The USB endpint to configure |
2601 | * @desc: The USB endpoint descriptor to configure with. | |
2602 | * | |
2603 | * This is called from the USB gadget code's usb_ep_enable(). | |
8b9bc460 | 2604 | */ |
1f91b4cc | 2605 | static int dwc2_hsotg_ep_enable(struct usb_ep *ep, |
5b7d70c6 BD |
2606 | const struct usb_endpoint_descriptor *desc) |
2607 | { | |
1f91b4cc | 2608 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 2609 | struct dwc2_hsotg *hsotg = hs_ep->parent; |
5b7d70c6 | 2610 | unsigned long flags; |
ca4c55ad | 2611 | unsigned int index = hs_ep->index; |
5b7d70c6 BD |
2612 | u32 epctrl_reg; |
2613 | u32 epctrl; | |
2614 | u32 mps; | |
ca4c55ad MYK |
2615 | unsigned int dir_in; |
2616 | unsigned int i, val, size; | |
19c190f9 | 2617 | int ret = 0; |
5b7d70c6 BD |
2618 | |
2619 | dev_dbg(hsotg->dev, | |
2620 | "%s: ep %s: a 0x%02x, attr 0x%02x, mps 0x%04x, intr %d\n", | |
2621 | __func__, ep->name, desc->bEndpointAddress, desc->bmAttributes, | |
2622 | desc->wMaxPacketSize, desc->bInterval); | |
2623 | ||
2624 | /* not to be called for EP0 */ | |
2625 | WARN_ON(index == 0); | |
2626 | ||
2627 | dir_in = (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) ? 1 : 0; | |
2628 | if (dir_in != hs_ep->dir_in) { | |
2629 | dev_err(hsotg->dev, "%s: direction mismatch!\n", __func__); | |
2630 | return -EINVAL; | |
2631 | } | |
2632 | ||
29cc8897 | 2633 | mps = usb_endpoint_maxp(desc); |
5b7d70c6 | 2634 | |
1f91b4cc | 2635 | /* note, we handle this here instead of dwc2_hsotg_set_ep_maxpacket */ |
5b7d70c6 | 2636 | |
94cb8fd6 | 2637 | epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index); |
95c8bc36 | 2638 | epctrl = dwc2_readl(hsotg->regs + epctrl_reg); |
5b7d70c6 BD |
2639 | |
2640 | dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x from 0x%08x\n", | |
2641 | __func__, epctrl, epctrl_reg); | |
2642 | ||
22258f49 | 2643 | spin_lock_irqsave(&hsotg->lock, flags); |
5b7d70c6 | 2644 | |
47a1685f DN |
2645 | epctrl &= ~(DXEPCTL_EPTYPE_MASK | DXEPCTL_MPS_MASK); |
2646 | epctrl |= DXEPCTL_MPS(mps); | |
5b7d70c6 | 2647 | |
8b9bc460 LM |
2648 | /* |
2649 | * mark the endpoint as active, otherwise the core may ignore | |
2650 | * transactions entirely for this endpoint | |
2651 | */ | |
47a1685f | 2652 | epctrl |= DXEPCTL_USBACTEP; |
5b7d70c6 | 2653 | |
8b9bc460 LM |
2654 | /* |
2655 | * set the NAK status on the endpoint, otherwise we might try and | |
5b7d70c6 BD |
2656 | * do something with data that we've yet got a request to process |
2657 | * since the RXFIFO will take data for an endpoint even if the | |
2658 | * size register hasn't been set. | |
2659 | */ | |
2660 | ||
47a1685f | 2661 | epctrl |= DXEPCTL_SNAK; |
5b7d70c6 BD |
2662 | |
2663 | /* update the endpoint state */ | |
1f91b4cc | 2664 | dwc2_hsotg_set_ep_maxpacket(hsotg, hs_ep->index, mps, dir_in); |
5b7d70c6 BD |
2665 | |
2666 | /* default, set to non-periodic */ | |
1479e841 | 2667 | hs_ep->isochronous = 0; |
5b7d70c6 | 2668 | hs_ep->periodic = 0; |
a18ed7b0 | 2669 | hs_ep->halted = 0; |
1479e841 | 2670 | hs_ep->interval = desc->bInterval; |
5b7d70c6 | 2671 | |
4fca54aa RB |
2672 | if (hs_ep->interval > 1 && hs_ep->mc > 1) |
2673 | dev_err(hsotg->dev, "MC > 1 when interval is not 1\n"); | |
2674 | ||
5b7d70c6 BD |
2675 | switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) { |
2676 | case USB_ENDPOINT_XFER_ISOC: | |
47a1685f DN |
2677 | epctrl |= DXEPCTL_EPTYPE_ISO; |
2678 | epctrl |= DXEPCTL_SETEVENFR; | |
1479e841 RB |
2679 | hs_ep->isochronous = 1; |
2680 | if (dir_in) | |
2681 | hs_ep->periodic = 1; | |
2682 | break; | |
5b7d70c6 BD |
2683 | |
2684 | case USB_ENDPOINT_XFER_BULK: | |
47a1685f | 2685 | epctrl |= DXEPCTL_EPTYPE_BULK; |
5b7d70c6 BD |
2686 | break; |
2687 | ||
2688 | case USB_ENDPOINT_XFER_INT: | |
b203d0a2 | 2689 | if (dir_in) |
5b7d70c6 | 2690 | hs_ep->periodic = 1; |
5b7d70c6 | 2691 | |
47a1685f | 2692 | epctrl |= DXEPCTL_EPTYPE_INTERRUPT; |
5b7d70c6 BD |
2693 | break; |
2694 | ||
2695 | case USB_ENDPOINT_XFER_CONTROL: | |
47a1685f | 2696 | epctrl |= DXEPCTL_EPTYPE_CONTROL; |
5b7d70c6 BD |
2697 | break; |
2698 | } | |
2699 | ||
4556e12c MYK |
2700 | /* If fifo is already allocated for this ep */ |
2701 | if (hs_ep->fifo_index) { | |
2702 | size = hs_ep->ep.maxpacket * hs_ep->mc; | |
2703 | /* If bigger fifo is required deallocate current one */ | |
2704 | if (size > hs_ep->fifo_size) { | |
2705 | hsotg->fifo_map &= ~(1 << hs_ep->fifo_index); | |
2706 | hs_ep->fifo_index = 0; | |
2707 | hs_ep->fifo_size = 0; | |
2708 | } | |
2709 | } | |
2710 | ||
8b9bc460 LM |
2711 | /* |
2712 | * if the hardware has dedicated fifos, we must give each IN EP | |
10aebc77 BD |
2713 | * a unique tx-fifo even if it is non-periodic. |
2714 | */ | |
4556e12c | 2715 | if (dir_in && hsotg->dedicated_fifos && !hs_ep->fifo_index) { |
ca4c55ad MYK |
2716 | u32 fifo_index = 0; |
2717 | u32 fifo_size = UINT_MAX; | |
b203d0a2 | 2718 | size = hs_ep->ep.maxpacket*hs_ep->mc; |
5f2196bd | 2719 | for (i = 1; i < hsotg->num_of_eps; ++i) { |
b203d0a2 RB |
2720 | if (hsotg->fifo_map & (1<<i)) |
2721 | continue; | |
95c8bc36 | 2722 | val = dwc2_readl(hsotg->regs + DPTXFSIZN(i)); |
b203d0a2 RB |
2723 | val = (val >> FIFOSIZE_DEPTH_SHIFT)*4; |
2724 | if (val < size) | |
2725 | continue; | |
ca4c55ad MYK |
2726 | /* Search for smallest acceptable fifo */ |
2727 | if (val < fifo_size) { | |
2728 | fifo_size = val; | |
2729 | fifo_index = i; | |
2730 | } | |
b203d0a2 | 2731 | } |
ca4c55ad | 2732 | if (!fifo_index) { |
5f2196bd MYK |
2733 | dev_err(hsotg->dev, |
2734 | "%s: No suitable fifo found\n", __func__); | |
b585a48b SM |
2735 | ret = -ENOMEM; |
2736 | goto error; | |
2737 | } | |
ca4c55ad MYK |
2738 | hsotg->fifo_map |= 1 << fifo_index; |
2739 | epctrl |= DXEPCTL_TXFNUM(fifo_index); | |
2740 | hs_ep->fifo_index = fifo_index; | |
2741 | hs_ep->fifo_size = fifo_size; | |
b203d0a2 | 2742 | } |
10aebc77 | 2743 | |
5b7d70c6 BD |
2744 | /* for non control endpoints, set PID to D0 */ |
2745 | if (index) | |
47a1685f | 2746 | epctrl |= DXEPCTL_SETD0PID; |
5b7d70c6 BD |
2747 | |
2748 | dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n", | |
2749 | __func__, epctrl); | |
2750 | ||
95c8bc36 | 2751 | dwc2_writel(epctrl, hsotg->regs + epctrl_reg); |
5b7d70c6 | 2752 | dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x\n", |
95c8bc36 | 2753 | __func__, dwc2_readl(hsotg->regs + epctrl_reg)); |
5b7d70c6 BD |
2754 | |
2755 | /* enable the endpoint interrupt */ | |
1f91b4cc | 2756 | dwc2_hsotg_ctrl_epint(hsotg, index, dir_in, 1); |
5b7d70c6 | 2757 | |
b585a48b | 2758 | error: |
22258f49 | 2759 | spin_unlock_irqrestore(&hsotg->lock, flags); |
19c190f9 | 2760 | return ret; |
5b7d70c6 BD |
2761 | } |
2762 | ||
8b9bc460 | 2763 | /** |
1f91b4cc | 2764 | * dwc2_hsotg_ep_disable - disable given endpoint |
8b9bc460 LM |
2765 | * @ep: The endpoint to disable. |
2766 | */ | |
1f91b4cc | 2767 | static int dwc2_hsotg_ep_disable(struct usb_ep *ep) |
5b7d70c6 | 2768 | { |
1f91b4cc | 2769 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 2770 | struct dwc2_hsotg *hsotg = hs_ep->parent; |
5b7d70c6 BD |
2771 | int dir_in = hs_ep->dir_in; |
2772 | int index = hs_ep->index; | |
2773 | unsigned long flags; | |
2774 | u32 epctrl_reg; | |
2775 | u32 ctrl; | |
2776 | ||
1e011293 | 2777 | dev_dbg(hsotg->dev, "%s(ep %p)\n", __func__, ep); |
5b7d70c6 | 2778 | |
c6f5c050 | 2779 | if (ep == &hsotg->eps_out[0]->ep) { |
5b7d70c6 BD |
2780 | dev_err(hsotg->dev, "%s: called for ep0\n", __func__); |
2781 | return -EINVAL; | |
2782 | } | |
2783 | ||
94cb8fd6 | 2784 | epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index); |
5b7d70c6 | 2785 | |
5ad1d316 | 2786 | spin_lock_irqsave(&hsotg->lock, flags); |
5b7d70c6 | 2787 | |
b203d0a2 RB |
2788 | hsotg->fifo_map &= ~(1<<hs_ep->fifo_index); |
2789 | hs_ep->fifo_index = 0; | |
2790 | hs_ep->fifo_size = 0; | |
5b7d70c6 | 2791 | |
95c8bc36 | 2792 | ctrl = dwc2_readl(hsotg->regs + epctrl_reg); |
47a1685f DN |
2793 | ctrl &= ~DXEPCTL_EPENA; |
2794 | ctrl &= ~DXEPCTL_USBACTEP; | |
2795 | ctrl |= DXEPCTL_SNAK; | |
5b7d70c6 BD |
2796 | |
2797 | dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl); | |
95c8bc36 | 2798 | dwc2_writel(ctrl, hsotg->regs + epctrl_reg); |
5b7d70c6 BD |
2799 | |
2800 | /* disable endpoint interrupts */ | |
1f91b4cc | 2801 | dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 0); |
5b7d70c6 | 2802 | |
1141ea01 MYK |
2803 | /* terminate all requests with shutdown */ |
2804 | kill_all_requests(hsotg, hs_ep, -ESHUTDOWN); | |
2805 | ||
22258f49 | 2806 | spin_unlock_irqrestore(&hsotg->lock, flags); |
5b7d70c6 BD |
2807 | return 0; |
2808 | } | |
2809 | ||
2810 | /** | |
2811 | * on_list - check request is on the given endpoint | |
2812 | * @ep: The endpoint to check. | |
2813 | * @test: The request to test if it is on the endpoint. | |
8b9bc460 | 2814 | */ |
1f91b4cc | 2815 | static bool on_list(struct dwc2_hsotg_ep *ep, struct dwc2_hsotg_req *test) |
5b7d70c6 | 2816 | { |
1f91b4cc | 2817 | struct dwc2_hsotg_req *req, *treq; |
5b7d70c6 BD |
2818 | |
2819 | list_for_each_entry_safe(req, treq, &ep->queue, queue) { | |
2820 | if (req == test) | |
2821 | return true; | |
2822 | } | |
2823 | ||
2824 | return false; | |
2825 | } | |
2826 | ||
c524dd5f MYK |
2827 | static int dwc2_hsotg_wait_bit_set(struct dwc2_hsotg *hs_otg, u32 reg, |
2828 | u32 bit, u32 timeout) | |
2829 | { | |
2830 | u32 i; | |
2831 | ||
2832 | for (i = 0; i < timeout; i++) { | |
2833 | if (dwc2_readl(hs_otg->regs + reg) & bit) | |
2834 | return 0; | |
2835 | udelay(1); | |
2836 | } | |
2837 | ||
2838 | return -ETIMEDOUT; | |
2839 | } | |
2840 | ||
2841 | static void dwc2_hsotg_ep_stop_xfr(struct dwc2_hsotg *hsotg, | |
2842 | struct dwc2_hsotg_ep *hs_ep) | |
2843 | { | |
2844 | u32 epctrl_reg; | |
2845 | u32 epint_reg; | |
2846 | ||
2847 | epctrl_reg = hs_ep->dir_in ? DIEPCTL(hs_ep->index) : | |
2848 | DOEPCTL(hs_ep->index); | |
2849 | epint_reg = hs_ep->dir_in ? DIEPINT(hs_ep->index) : | |
2850 | DOEPINT(hs_ep->index); | |
2851 | ||
2852 | dev_dbg(hsotg->dev, "%s: stopping transfer on %s\n", __func__, | |
2853 | hs_ep->name); | |
2854 | if (hs_ep->dir_in) { | |
2855 | __orr32(hsotg->regs + epctrl_reg, DXEPCTL_SNAK); | |
2856 | /* Wait for Nak effect */ | |
2857 | if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg, | |
2858 | DXEPINT_INEPNAKEFF, 100)) | |
2859 | dev_warn(hsotg->dev, | |
2860 | "%s: timeout DIEPINT.NAKEFF\n", __func__); | |
2861 | } else { | |
2862 | /* Clear any pending nak effect interrupt */ | |
2863 | dwc2_writel(GINTSTS_GINNAKEFF, hsotg->regs + GINTSTS); | |
2864 | ||
2865 | __orr32(hsotg->regs + DCTL, DCTL_SGNPINNAK); | |
2866 | ||
2867 | /* Wait for global nak to take effect */ | |
2868 | if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS, | |
2869 | GINTSTS_GINNAKEFF, 100)) | |
2870 | dev_warn(hsotg->dev, | |
2871 | "%s: timeout GINTSTS.GINNAKEFF\n", __func__); | |
2872 | } | |
2873 | ||
2874 | /* Disable ep */ | |
2875 | __orr32(hsotg->regs + epctrl_reg, DXEPCTL_EPDIS | DXEPCTL_SNAK); | |
2876 | ||
2877 | /* Wait for ep to be disabled */ | |
2878 | if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg, DXEPINT_EPDISBLD, 100)) | |
2879 | dev_warn(hsotg->dev, | |
2880 | "%s: timeout DOEPCTL.EPDisable\n", __func__); | |
2881 | ||
2882 | if (hs_ep->dir_in) { | |
2883 | if (hsotg->dedicated_fifos) { | |
2884 | dwc2_writel(GRSTCTL_TXFNUM(hs_ep->fifo_index) | | |
2885 | GRSTCTL_TXFFLSH, hsotg->regs + GRSTCTL); | |
2886 | /* Wait for fifo flush */ | |
2887 | if (dwc2_hsotg_wait_bit_set(hsotg, GRSTCTL, | |
2888 | GRSTCTL_TXFFLSH, 100)) | |
2889 | dev_warn(hsotg->dev, | |
2890 | "%s: timeout flushing fifos\n", | |
2891 | __func__); | |
2892 | } | |
2893 | /* TODO: Flush shared tx fifo */ | |
2894 | } else { | |
2895 | /* Remove global NAKs */ | |
2896 | __bic32(hsotg->regs + DCTL, DCTL_SGNPINNAK); | |
2897 | } | |
2898 | } | |
2899 | ||
8b9bc460 | 2900 | /** |
1f91b4cc | 2901 | * dwc2_hsotg_ep_dequeue - dequeue given endpoint |
8b9bc460 LM |
2902 | * @ep: The endpoint to dequeue. |
2903 | * @req: The request to be removed from a queue. | |
2904 | */ | |
1f91b4cc | 2905 | static int dwc2_hsotg_ep_dequeue(struct usb_ep *ep, struct usb_request *req) |
5b7d70c6 | 2906 | { |
1f91b4cc FB |
2907 | struct dwc2_hsotg_req *hs_req = our_req(req); |
2908 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); | |
941fcce4 | 2909 | struct dwc2_hsotg *hs = hs_ep->parent; |
5b7d70c6 BD |
2910 | unsigned long flags; |
2911 | ||
1e011293 | 2912 | dev_dbg(hs->dev, "ep_dequeue(%p,%p)\n", ep, req); |
5b7d70c6 | 2913 | |
22258f49 | 2914 | spin_lock_irqsave(&hs->lock, flags); |
5b7d70c6 BD |
2915 | |
2916 | if (!on_list(hs_ep, hs_req)) { | |
22258f49 | 2917 | spin_unlock_irqrestore(&hs->lock, flags); |
5b7d70c6 BD |
2918 | return -EINVAL; |
2919 | } | |
2920 | ||
c524dd5f MYK |
2921 | /* Dequeue already started request */ |
2922 | if (req == &hs_ep->req->req) | |
2923 | dwc2_hsotg_ep_stop_xfr(hs, hs_ep); | |
2924 | ||
1f91b4cc | 2925 | dwc2_hsotg_complete_request(hs, hs_ep, hs_req, -ECONNRESET); |
22258f49 | 2926 | spin_unlock_irqrestore(&hs->lock, flags); |
5b7d70c6 BD |
2927 | |
2928 | return 0; | |
2929 | } | |
2930 | ||
8b9bc460 | 2931 | /** |
1f91b4cc | 2932 | * dwc2_hsotg_ep_sethalt - set halt on a given endpoint |
8b9bc460 LM |
2933 | * @ep: The endpoint to set halt. |
2934 | * @value: Set or unset the halt. | |
2935 | */ | |
1f91b4cc | 2936 | static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value) |
5b7d70c6 | 2937 | { |
1f91b4cc | 2938 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 2939 | struct dwc2_hsotg *hs = hs_ep->parent; |
5b7d70c6 | 2940 | int index = hs_ep->index; |
5b7d70c6 BD |
2941 | u32 epreg; |
2942 | u32 epctl; | |
9c39ddc6 | 2943 | u32 xfertype; |
5b7d70c6 BD |
2944 | |
2945 | dev_info(hs->dev, "%s(ep %p %s, %d)\n", __func__, ep, ep->name, value); | |
2946 | ||
c9f721b2 RB |
2947 | if (index == 0) { |
2948 | if (value) | |
1f91b4cc | 2949 | dwc2_hsotg_stall_ep0(hs); |
c9f721b2 RB |
2950 | else |
2951 | dev_warn(hs->dev, | |
2952 | "%s: can't clear halt on ep0\n", __func__); | |
2953 | return 0; | |
2954 | } | |
2955 | ||
c6f5c050 MYK |
2956 | if (hs_ep->dir_in) { |
2957 | epreg = DIEPCTL(index); | |
95c8bc36 | 2958 | epctl = dwc2_readl(hs->regs + epreg); |
c6f5c050 MYK |
2959 | |
2960 | if (value) { | |
5a350d53 | 2961 | epctl |= DXEPCTL_STALL | DXEPCTL_SNAK; |
c6f5c050 MYK |
2962 | if (epctl & DXEPCTL_EPENA) |
2963 | epctl |= DXEPCTL_EPDIS; | |
2964 | } else { | |
2965 | epctl &= ~DXEPCTL_STALL; | |
2966 | xfertype = epctl & DXEPCTL_EPTYPE_MASK; | |
2967 | if (xfertype == DXEPCTL_EPTYPE_BULK || | |
2968 | xfertype == DXEPCTL_EPTYPE_INTERRUPT) | |
2969 | epctl |= DXEPCTL_SETD0PID; | |
2970 | } | |
95c8bc36 | 2971 | dwc2_writel(epctl, hs->regs + epreg); |
9c39ddc6 | 2972 | } else { |
5b7d70c6 | 2973 | |
c6f5c050 | 2974 | epreg = DOEPCTL(index); |
95c8bc36 | 2975 | epctl = dwc2_readl(hs->regs + epreg); |
5b7d70c6 | 2976 | |
c6f5c050 MYK |
2977 | if (value) |
2978 | epctl |= DXEPCTL_STALL; | |
2979 | else { | |
2980 | epctl &= ~DXEPCTL_STALL; | |
2981 | xfertype = epctl & DXEPCTL_EPTYPE_MASK; | |
2982 | if (xfertype == DXEPCTL_EPTYPE_BULK || | |
2983 | xfertype == DXEPCTL_EPTYPE_INTERRUPT) | |
2984 | epctl |= DXEPCTL_SETD0PID; | |
2985 | } | |
95c8bc36 | 2986 | dwc2_writel(epctl, hs->regs + epreg); |
9c39ddc6 | 2987 | } |
5b7d70c6 | 2988 | |
a18ed7b0 RB |
2989 | hs_ep->halted = value; |
2990 | ||
5b7d70c6 BD |
2991 | return 0; |
2992 | } | |
2993 | ||
5ad1d316 | 2994 | /** |
1f91b4cc | 2995 | * dwc2_hsotg_ep_sethalt_lock - set halt on a given endpoint with lock held |
5ad1d316 LM |
2996 | * @ep: The endpoint to set halt. |
2997 | * @value: Set or unset the halt. | |
2998 | */ | |
1f91b4cc | 2999 | static int dwc2_hsotg_ep_sethalt_lock(struct usb_ep *ep, int value) |
5ad1d316 | 3000 | { |
1f91b4cc | 3001 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 3002 | struct dwc2_hsotg *hs = hs_ep->parent; |
5ad1d316 LM |
3003 | unsigned long flags = 0; |
3004 | int ret = 0; | |
3005 | ||
3006 | spin_lock_irqsave(&hs->lock, flags); | |
1f91b4cc | 3007 | ret = dwc2_hsotg_ep_sethalt(ep, value); |
5ad1d316 LM |
3008 | spin_unlock_irqrestore(&hs->lock, flags); |
3009 | ||
3010 | return ret; | |
3011 | } | |
3012 | ||
1f91b4cc FB |
3013 | static struct usb_ep_ops dwc2_hsotg_ep_ops = { |
3014 | .enable = dwc2_hsotg_ep_enable, | |
3015 | .disable = dwc2_hsotg_ep_disable, | |
3016 | .alloc_request = dwc2_hsotg_ep_alloc_request, | |
3017 | .free_request = dwc2_hsotg_ep_free_request, | |
3018 | .queue = dwc2_hsotg_ep_queue_lock, | |
3019 | .dequeue = dwc2_hsotg_ep_dequeue, | |
3020 | .set_halt = dwc2_hsotg_ep_sethalt_lock, | |
25985edc | 3021 | /* note, don't believe we have any call for the fifo routines */ |
5b7d70c6 BD |
3022 | }; |
3023 | ||
41188786 | 3024 | /** |
1f91b4cc | 3025 | * dwc2_hsotg_phy_enable - enable platform phy dev |
8b9bc460 | 3026 | * @hsotg: The driver state |
41188786 LM |
3027 | * |
3028 | * A wrapper for platform code responsible for controlling | |
3029 | * low-level USB code | |
3030 | */ | |
1f91b4cc | 3031 | static void dwc2_hsotg_phy_enable(struct dwc2_hsotg *hsotg) |
41188786 LM |
3032 | { |
3033 | struct platform_device *pdev = to_platform_device(hsotg->dev); | |
3034 | ||
3035 | dev_dbg(hsotg->dev, "pdev 0x%p\n", pdev); | |
b2e587db | 3036 | |
ca2c5ba8 | 3037 | if (hsotg->uphy) |
74084844 | 3038 | usb_phy_init(hsotg->uphy); |
ca2c5ba8 | 3039 | else if (hsotg->plat && hsotg->plat->phy_init) |
41188786 | 3040 | hsotg->plat->phy_init(pdev, hsotg->plat->phy_type); |
ca2c5ba8 KD |
3041 | else { |
3042 | phy_init(hsotg->phy); | |
3043 | phy_power_on(hsotg->phy); | |
3044 | } | |
41188786 LM |
3045 | } |
3046 | ||
3047 | /** | |
1f91b4cc | 3048 | * dwc2_hsotg_phy_disable - disable platform phy dev |
8b9bc460 | 3049 | * @hsotg: The driver state |
41188786 LM |
3050 | * |
3051 | * A wrapper for platform code responsible for controlling | |
3052 | * low-level USB code | |
3053 | */ | |
1f91b4cc | 3054 | static void dwc2_hsotg_phy_disable(struct dwc2_hsotg *hsotg) |
41188786 LM |
3055 | { |
3056 | struct platform_device *pdev = to_platform_device(hsotg->dev); | |
3057 | ||
ca2c5ba8 | 3058 | if (hsotg->uphy) |
74084844 | 3059 | usb_phy_shutdown(hsotg->uphy); |
ca2c5ba8 | 3060 | else if (hsotg->plat && hsotg->plat->phy_exit) |
41188786 | 3061 | hsotg->plat->phy_exit(pdev, hsotg->plat->phy_type); |
ca2c5ba8 KD |
3062 | else { |
3063 | phy_power_off(hsotg->phy); | |
3064 | phy_exit(hsotg->phy); | |
3065 | } | |
41188786 LM |
3066 | } |
3067 | ||
8b9bc460 | 3068 | /** |
1f91b4cc | 3069 | * dwc2_hsotg_init - initalize the usb core |
8b9bc460 LM |
3070 | * @hsotg: The driver state |
3071 | */ | |
1f91b4cc | 3072 | static void dwc2_hsotg_init(struct dwc2_hsotg *hsotg) |
b3f489b2 | 3073 | { |
fa4a8d72 | 3074 | u32 trdtim; |
b3f489b2 LM |
3075 | /* unmask subset of endpoint interrupts */ |
3076 | ||
95c8bc36 AS |
3077 | dwc2_writel(DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK | |
3078 | DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK, | |
3079 | hsotg->regs + DIEPMSK); | |
b3f489b2 | 3080 | |
95c8bc36 AS |
3081 | dwc2_writel(DOEPMSK_SETUPMSK | DOEPMSK_AHBERRMSK | |
3082 | DOEPMSK_EPDISBLDMSK | DOEPMSK_XFERCOMPLMSK, | |
3083 | hsotg->regs + DOEPMSK); | |
b3f489b2 | 3084 | |
95c8bc36 | 3085 | dwc2_writel(0, hsotg->regs + DAINTMSK); |
b3f489b2 LM |
3086 | |
3087 | /* Be in disconnected state until gadget is registered */ | |
47a1685f | 3088 | __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON); |
b3f489b2 | 3089 | |
b3f489b2 LM |
3090 | /* setup fifos */ |
3091 | ||
3092 | dev_dbg(hsotg->dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n", | |
95c8bc36 AS |
3093 | dwc2_readl(hsotg->regs + GRXFSIZ), |
3094 | dwc2_readl(hsotg->regs + GNPTXFSIZ)); | |
b3f489b2 | 3095 | |
1f91b4cc | 3096 | dwc2_hsotg_init_fifo(hsotg); |
b3f489b2 LM |
3097 | |
3098 | /* set the PLL on, remove the HNP/SRP and set the PHY */ | |
fa4a8d72 | 3099 | trdtim = (hsotg->phyif == GUSBCFG_PHYIF8) ? 9 : 5; |
95c8bc36 | 3100 | dwc2_writel(hsotg->phyif | GUSBCFG_TOUTCAL(7) | |
f889f23d | 3101 | (trdtim << GUSBCFG_USBTRDTIM_SHIFT), |
fa4a8d72 | 3102 | hsotg->regs + GUSBCFG); |
b3f489b2 | 3103 | |
f5090044 GH |
3104 | if (using_dma(hsotg)) |
3105 | __orr32(hsotg->regs + GAHBCFG, GAHBCFG_DMA_EN); | |
b3f489b2 LM |
3106 | } |
3107 | ||
8b9bc460 | 3108 | /** |
1f91b4cc | 3109 | * dwc2_hsotg_udc_start - prepare the udc for work |
8b9bc460 LM |
3110 | * @gadget: The usb gadget state |
3111 | * @driver: The usb gadget driver | |
3112 | * | |
3113 | * Perform initialization to prepare udc device and driver | |
3114 | * to work. | |
3115 | */ | |
1f91b4cc | 3116 | static int dwc2_hsotg_udc_start(struct usb_gadget *gadget, |
f65f0f10 | 3117 | struct usb_gadget_driver *driver) |
5b7d70c6 | 3118 | { |
941fcce4 | 3119 | struct dwc2_hsotg *hsotg = to_hsotg(gadget); |
5b9451f8 | 3120 | unsigned long flags; |
5b7d70c6 BD |
3121 | int ret; |
3122 | ||
3123 | if (!hsotg) { | |
a023da33 | 3124 | pr_err("%s: called with no device\n", __func__); |
5b7d70c6 BD |
3125 | return -ENODEV; |
3126 | } | |
3127 | ||
3128 | if (!driver) { | |
3129 | dev_err(hsotg->dev, "%s: no driver\n", __func__); | |
3130 | return -EINVAL; | |
3131 | } | |
3132 | ||
7177aed4 | 3133 | if (driver->max_speed < USB_SPEED_FULL) |
5b7d70c6 | 3134 | dev_err(hsotg->dev, "%s: bad speed\n", __func__); |
5b7d70c6 | 3135 | |
f65f0f10 | 3136 | if (!driver->setup) { |
5b7d70c6 BD |
3137 | dev_err(hsotg->dev, "%s: missing entry points\n", __func__); |
3138 | return -EINVAL; | |
3139 | } | |
3140 | ||
7ad8096e | 3141 | mutex_lock(&hsotg->init_mutex); |
5b7d70c6 BD |
3142 | WARN_ON(hsotg->driver); |
3143 | ||
3144 | driver->driver.bus = NULL; | |
3145 | hsotg->driver = driver; | |
7d7b2292 | 3146 | hsotg->gadget.dev.of_node = hsotg->dev->of_node; |
5b7d70c6 BD |
3147 | hsotg->gadget.speed = USB_SPEED_UNKNOWN; |
3148 | ||
d00b4142 RB |
3149 | clk_enable(hsotg->clk); |
3150 | ||
f65f0f10 LM |
3151 | ret = regulator_bulk_enable(ARRAY_SIZE(hsotg->supplies), |
3152 | hsotg->supplies); | |
5b7d70c6 | 3153 | if (ret) { |
f65f0f10 | 3154 | dev_err(hsotg->dev, "failed to enable supplies: %d\n", ret); |
5b7d70c6 BD |
3155 | goto err; |
3156 | } | |
3157 | ||
1f91b4cc | 3158 | dwc2_hsotg_phy_enable(hsotg); |
f6c01592 GH |
3159 | if (!IS_ERR_OR_NULL(hsotg->uphy)) |
3160 | otg_set_peripheral(hsotg->uphy->otg, &hsotg->gadget); | |
c816c47f | 3161 | |
5b9451f8 | 3162 | spin_lock_irqsave(&hsotg->lock, flags); |
1f91b4cc FB |
3163 | dwc2_hsotg_init(hsotg); |
3164 | dwc2_hsotg_core_init_disconnected(hsotg, false); | |
dc6e69e6 | 3165 | hsotg->enabled = 0; |
5b9451f8 MS |
3166 | spin_unlock_irqrestore(&hsotg->lock, flags); |
3167 | ||
5b7d70c6 | 3168 | dev_info(hsotg->dev, "bound driver %s\n", driver->driver.name); |
5b9451f8 | 3169 | |
7ad8096e MS |
3170 | mutex_unlock(&hsotg->init_mutex); |
3171 | ||
5b7d70c6 BD |
3172 | return 0; |
3173 | ||
3174 | err: | |
7ad8096e | 3175 | mutex_unlock(&hsotg->init_mutex); |
5b7d70c6 | 3176 | hsotg->driver = NULL; |
5b7d70c6 BD |
3177 | return ret; |
3178 | } | |
3179 | ||
8b9bc460 | 3180 | /** |
1f91b4cc | 3181 | * dwc2_hsotg_udc_stop - stop the udc |
8b9bc460 LM |
3182 | * @gadget: The usb gadget state |
3183 | * @driver: The usb gadget driver | |
3184 | * | |
3185 | * Stop udc hw block and stay tunned for future transmissions | |
3186 | */ | |
1f91b4cc | 3187 | static int dwc2_hsotg_udc_stop(struct usb_gadget *gadget) |
5b7d70c6 | 3188 | { |
941fcce4 | 3189 | struct dwc2_hsotg *hsotg = to_hsotg(gadget); |
2b19a52c | 3190 | unsigned long flags = 0; |
5b7d70c6 BD |
3191 | int ep; |
3192 | ||
3193 | if (!hsotg) | |
3194 | return -ENODEV; | |
3195 | ||
7ad8096e MS |
3196 | mutex_lock(&hsotg->init_mutex); |
3197 | ||
5b7d70c6 | 3198 | /* all endpoints should be shutdown */ |
c6f5c050 MYK |
3199 | for (ep = 1; ep < hsotg->num_of_eps; ep++) { |
3200 | if (hsotg->eps_in[ep]) | |
1f91b4cc | 3201 | dwc2_hsotg_ep_disable(&hsotg->eps_in[ep]->ep); |
c6f5c050 | 3202 | if (hsotg->eps_out[ep]) |
1f91b4cc | 3203 | dwc2_hsotg_ep_disable(&hsotg->eps_out[ep]->ep); |
c6f5c050 | 3204 | } |
5b7d70c6 | 3205 | |
2b19a52c LM |
3206 | spin_lock_irqsave(&hsotg->lock, flags); |
3207 | ||
32805c35 | 3208 | hsotg->driver = NULL; |
5b7d70c6 | 3209 | hsotg->gadget.speed = USB_SPEED_UNKNOWN; |
dc6e69e6 | 3210 | hsotg->enabled = 0; |
5b7d70c6 | 3211 | |
2b19a52c LM |
3212 | spin_unlock_irqrestore(&hsotg->lock, flags); |
3213 | ||
f6c01592 GH |
3214 | if (!IS_ERR_OR_NULL(hsotg->uphy)) |
3215 | otg_set_peripheral(hsotg->uphy->otg, NULL); | |
1f91b4cc | 3216 | dwc2_hsotg_phy_disable(hsotg); |
c816c47f | 3217 | |
c8c10253 | 3218 | regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies), hsotg->supplies); |
5b7d70c6 | 3219 | |
d00b4142 RB |
3220 | clk_disable(hsotg->clk); |
3221 | ||
7ad8096e MS |
3222 | mutex_unlock(&hsotg->init_mutex); |
3223 | ||
5b7d70c6 BD |
3224 | return 0; |
3225 | } | |
5b7d70c6 | 3226 | |
8b9bc460 | 3227 | /** |
1f91b4cc | 3228 | * dwc2_hsotg_gadget_getframe - read the frame number |
8b9bc460 LM |
3229 | * @gadget: The usb gadget state |
3230 | * | |
3231 | * Read the {micro} frame number | |
3232 | */ | |
1f91b4cc | 3233 | static int dwc2_hsotg_gadget_getframe(struct usb_gadget *gadget) |
5b7d70c6 | 3234 | { |
1f91b4cc | 3235 | return dwc2_hsotg_read_frameno(to_hsotg(gadget)); |
5b7d70c6 BD |
3236 | } |
3237 | ||
a188b689 | 3238 | /** |
1f91b4cc | 3239 | * dwc2_hsotg_pullup - connect/disconnect the USB PHY |
a188b689 LM |
3240 | * @gadget: The usb gadget state |
3241 | * @is_on: Current state of the USB PHY | |
3242 | * | |
3243 | * Connect/Disconnect the USB PHY pullup | |
3244 | */ | |
1f91b4cc | 3245 | static int dwc2_hsotg_pullup(struct usb_gadget *gadget, int is_on) |
a188b689 | 3246 | { |
941fcce4 | 3247 | struct dwc2_hsotg *hsotg = to_hsotg(gadget); |
a188b689 LM |
3248 | unsigned long flags = 0; |
3249 | ||
77ba9119 GH |
3250 | dev_dbg(hsotg->dev, "%s: is_on: %d op_state: %d\n", __func__, is_on, |
3251 | hsotg->op_state); | |
3252 | ||
3253 | /* Don't modify pullup state while in host mode */ | |
3254 | if (hsotg->op_state != OTG_STATE_B_PERIPHERAL) { | |
3255 | hsotg->enabled = is_on; | |
3256 | return 0; | |
3257 | } | |
a188b689 | 3258 | |
7ad8096e | 3259 | mutex_lock(&hsotg->init_mutex); |
a188b689 LM |
3260 | spin_lock_irqsave(&hsotg->lock, flags); |
3261 | if (is_on) { | |
d00b4142 | 3262 | clk_enable(hsotg->clk); |
dc6e69e6 | 3263 | hsotg->enabled = 1; |
1f91b4cc FB |
3264 | dwc2_hsotg_core_init_disconnected(hsotg, false); |
3265 | dwc2_hsotg_core_connect(hsotg); | |
a188b689 | 3266 | } else { |
1f91b4cc FB |
3267 | dwc2_hsotg_core_disconnect(hsotg); |
3268 | dwc2_hsotg_disconnect(hsotg); | |
dc6e69e6 | 3269 | hsotg->enabled = 0; |
d00b4142 | 3270 | clk_disable(hsotg->clk); |
a188b689 LM |
3271 | } |
3272 | ||
3273 | hsotg->gadget.speed = USB_SPEED_UNKNOWN; | |
3274 | spin_unlock_irqrestore(&hsotg->lock, flags); | |
7ad8096e | 3275 | mutex_unlock(&hsotg->init_mutex); |
a188b689 LM |
3276 | |
3277 | return 0; | |
3278 | } | |
3279 | ||
1f91b4cc | 3280 | static int dwc2_hsotg_vbus_session(struct usb_gadget *gadget, int is_active) |
83d98223 GH |
3281 | { |
3282 | struct dwc2_hsotg *hsotg = to_hsotg(gadget); | |
3283 | unsigned long flags; | |
3284 | ||
3285 | dev_dbg(hsotg->dev, "%s: is_active: %d\n", __func__, is_active); | |
3286 | spin_lock_irqsave(&hsotg->lock, flags); | |
3287 | ||
61f7223b GH |
3288 | /* |
3289 | * If controller is hibernated, it must exit from hibernation | |
3290 | * before being initialized / de-initialized | |
3291 | */ | |
3292 | if (hsotg->lx_state == DWC2_L2) | |
3293 | dwc2_exit_hibernation(hsotg, false); | |
3294 | ||
83d98223 | 3295 | if (is_active) { |
cd0e641c | 3296 | hsotg->op_state = OTG_STATE_B_PERIPHERAL; |
065d3931 | 3297 | |
1f91b4cc | 3298 | dwc2_hsotg_core_init_disconnected(hsotg, false); |
83d98223 | 3299 | if (hsotg->enabled) |
1f91b4cc | 3300 | dwc2_hsotg_core_connect(hsotg); |
83d98223 | 3301 | } else { |
1f91b4cc FB |
3302 | dwc2_hsotg_core_disconnect(hsotg); |
3303 | dwc2_hsotg_disconnect(hsotg); | |
83d98223 GH |
3304 | } |
3305 | ||
3306 | spin_unlock_irqrestore(&hsotg->lock, flags); | |
3307 | return 0; | |
3308 | } | |
3309 | ||
596d696a | 3310 | /** |
1f91b4cc | 3311 | * dwc2_hsotg_vbus_draw - report bMaxPower field |
596d696a GH |
3312 | * @gadget: The usb gadget state |
3313 | * @mA: Amount of current | |
3314 | * | |
3315 | * Report how much power the device may consume to the phy. | |
3316 | */ | |
1f91b4cc | 3317 | static int dwc2_hsotg_vbus_draw(struct usb_gadget *gadget, unsigned mA) |
596d696a GH |
3318 | { |
3319 | struct dwc2_hsotg *hsotg = to_hsotg(gadget); | |
3320 | ||
3321 | if (IS_ERR_OR_NULL(hsotg->uphy)) | |
3322 | return -ENOTSUPP; | |
3323 | return usb_phy_set_power(hsotg->uphy, mA); | |
3324 | } | |
3325 | ||
1f91b4cc FB |
3326 | static const struct usb_gadget_ops dwc2_hsotg_gadget_ops = { |
3327 | .get_frame = dwc2_hsotg_gadget_getframe, | |
3328 | .udc_start = dwc2_hsotg_udc_start, | |
3329 | .udc_stop = dwc2_hsotg_udc_stop, | |
3330 | .pullup = dwc2_hsotg_pullup, | |
3331 | .vbus_session = dwc2_hsotg_vbus_session, | |
3332 | .vbus_draw = dwc2_hsotg_vbus_draw, | |
5b7d70c6 BD |
3333 | }; |
3334 | ||
3335 | /** | |
1f91b4cc | 3336 | * dwc2_hsotg_initep - initialise a single endpoint |
5b7d70c6 BD |
3337 | * @hsotg: The device state. |
3338 | * @hs_ep: The endpoint to be initialised. | |
3339 | * @epnum: The endpoint number | |
3340 | * | |
3341 | * Initialise the given endpoint (as part of the probe and device state | |
3342 | * creation) to give to the gadget driver. Setup the endpoint name, any | |
3343 | * direction information and other state that may be required. | |
3344 | */ | |
1f91b4cc FB |
3345 | static void dwc2_hsotg_initep(struct dwc2_hsotg *hsotg, |
3346 | struct dwc2_hsotg_ep *hs_ep, | |
c6f5c050 MYK |
3347 | int epnum, |
3348 | bool dir_in) | |
5b7d70c6 | 3349 | { |
5b7d70c6 BD |
3350 | char *dir; |
3351 | ||
3352 | if (epnum == 0) | |
3353 | dir = ""; | |
c6f5c050 | 3354 | else if (dir_in) |
5b7d70c6 | 3355 | dir = "in"; |
c6f5c050 MYK |
3356 | else |
3357 | dir = "out"; | |
5b7d70c6 | 3358 | |
c6f5c050 | 3359 | hs_ep->dir_in = dir_in; |
5b7d70c6 BD |
3360 | hs_ep->index = epnum; |
3361 | ||
3362 | snprintf(hs_ep->name, sizeof(hs_ep->name), "ep%d%s", epnum, dir); | |
3363 | ||
3364 | INIT_LIST_HEAD(&hs_ep->queue); | |
3365 | INIT_LIST_HEAD(&hs_ep->ep.ep_list); | |
3366 | ||
5b7d70c6 BD |
3367 | /* add to the list of endpoints known by the gadget driver */ |
3368 | if (epnum) | |
3369 | list_add_tail(&hs_ep->ep.ep_list, &hsotg->gadget.ep_list); | |
3370 | ||
3371 | hs_ep->parent = hsotg; | |
3372 | hs_ep->ep.name = hs_ep->name; | |
e117e742 | 3373 | usb_ep_set_maxpacket_limit(&hs_ep->ep, epnum ? 1024 : EP0_MPS_LIMIT); |
1f91b4cc | 3374 | hs_ep->ep.ops = &dwc2_hsotg_ep_ops; |
5b7d70c6 | 3375 | |
2954522f RB |
3376 | if (epnum == 0) { |
3377 | hs_ep->ep.caps.type_control = true; | |
3378 | } else { | |
3379 | hs_ep->ep.caps.type_iso = true; | |
3380 | hs_ep->ep.caps.type_bulk = true; | |
3381 | hs_ep->ep.caps.type_int = true; | |
3382 | } | |
3383 | ||
3384 | if (dir_in) | |
3385 | hs_ep->ep.caps.dir_in = true; | |
3386 | else | |
3387 | hs_ep->ep.caps.dir_out = true; | |
3388 | ||
8b9bc460 LM |
3389 | /* |
3390 | * if we're using dma, we need to set the next-endpoint pointer | |
5b7d70c6 BD |
3391 | * to be something valid. |
3392 | */ | |
3393 | ||
3394 | if (using_dma(hsotg)) { | |
47a1685f | 3395 | u32 next = DXEPCTL_NEXTEP((epnum + 1) % 15); |
c6f5c050 | 3396 | if (dir_in) |
95c8bc36 | 3397 | dwc2_writel(next, hsotg->regs + DIEPCTL(epnum)); |
c6f5c050 | 3398 | else |
95c8bc36 | 3399 | dwc2_writel(next, hsotg->regs + DOEPCTL(epnum)); |
5b7d70c6 BD |
3400 | } |
3401 | } | |
3402 | ||
b3f489b2 | 3403 | /** |
1f91b4cc | 3404 | * dwc2_hsotg_hw_cfg - read HW configuration registers |
b3f489b2 LM |
3405 | * @param: The device state |
3406 | * | |
3407 | * Read the USB core HW configuration registers | |
3408 | */ | |
1f91b4cc | 3409 | static int dwc2_hsotg_hw_cfg(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 3410 | { |
c6f5c050 MYK |
3411 | u32 cfg; |
3412 | u32 ep_type; | |
3413 | u32 i; | |
3414 | ||
b3f489b2 | 3415 | /* check hardware configuration */ |
5b7d70c6 | 3416 | |
95c8bc36 | 3417 | cfg = dwc2_readl(hsotg->regs + GHWCFG2); |
f889f23d | 3418 | hsotg->num_of_eps = (cfg >> GHWCFG2_NUM_DEV_EP_SHIFT) & 0xF; |
c6f5c050 MYK |
3419 | /* Add ep0 */ |
3420 | hsotg->num_of_eps++; | |
10aebc77 | 3421 | |
1f91b4cc | 3422 | hsotg->eps_in[0] = devm_kzalloc(hsotg->dev, sizeof(struct dwc2_hsotg_ep), |
c6f5c050 MYK |
3423 | GFP_KERNEL); |
3424 | if (!hsotg->eps_in[0]) | |
3425 | return -ENOMEM; | |
1f91b4cc | 3426 | /* Same dwc2_hsotg_ep is used in both directions for ep0 */ |
c6f5c050 MYK |
3427 | hsotg->eps_out[0] = hsotg->eps_in[0]; |
3428 | ||
95c8bc36 | 3429 | cfg = dwc2_readl(hsotg->regs + GHWCFG1); |
251a17f5 | 3430 | for (i = 1, cfg >>= 2; i < hsotg->num_of_eps; i++, cfg >>= 2) { |
c6f5c050 MYK |
3431 | ep_type = cfg & 3; |
3432 | /* Direction in or both */ | |
3433 | if (!(ep_type & 2)) { | |
3434 | hsotg->eps_in[i] = devm_kzalloc(hsotg->dev, | |
1f91b4cc | 3435 | sizeof(struct dwc2_hsotg_ep), GFP_KERNEL); |
c6f5c050 MYK |
3436 | if (!hsotg->eps_in[i]) |
3437 | return -ENOMEM; | |
3438 | } | |
3439 | /* Direction out or both */ | |
3440 | if (!(ep_type & 1)) { | |
3441 | hsotg->eps_out[i] = devm_kzalloc(hsotg->dev, | |
1f91b4cc | 3442 | sizeof(struct dwc2_hsotg_ep), GFP_KERNEL); |
c6f5c050 MYK |
3443 | if (!hsotg->eps_out[i]) |
3444 | return -ENOMEM; | |
3445 | } | |
3446 | } | |
3447 | ||
95c8bc36 | 3448 | cfg = dwc2_readl(hsotg->regs + GHWCFG3); |
f889f23d | 3449 | hsotg->fifo_mem = (cfg >> GHWCFG3_DFIFO_DEPTH_SHIFT); |
10aebc77 | 3450 | |
95c8bc36 | 3451 | cfg = dwc2_readl(hsotg->regs + GHWCFG4); |
f889f23d | 3452 | hsotg->dedicated_fifos = (cfg >> GHWCFG4_DED_FIFO_SHIFT) & 1; |
10aebc77 | 3453 | |
cff9eb75 MS |
3454 | dev_info(hsotg->dev, "EPs: %d, %s fifos, %d entries in SPRAM\n", |
3455 | hsotg->num_of_eps, | |
3456 | hsotg->dedicated_fifos ? "dedicated" : "shared", | |
3457 | hsotg->fifo_mem); | |
c6f5c050 | 3458 | return 0; |
5b7d70c6 BD |
3459 | } |
3460 | ||
8b9bc460 | 3461 | /** |
1f91b4cc | 3462 | * dwc2_hsotg_dump - dump state of the udc |
8b9bc460 LM |
3463 | * @param: The device state |
3464 | */ | |
1f91b4cc | 3465 | static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 3466 | { |
83a01804 | 3467 | #ifdef DEBUG |
5b7d70c6 BD |
3468 | struct device *dev = hsotg->dev; |
3469 | void __iomem *regs = hsotg->regs; | |
3470 | u32 val; | |
3471 | int idx; | |
3472 | ||
3473 | dev_info(dev, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n", | |
95c8bc36 AS |
3474 | dwc2_readl(regs + DCFG), dwc2_readl(regs + DCTL), |
3475 | dwc2_readl(regs + DIEPMSK)); | |
5b7d70c6 | 3476 | |
f889f23d | 3477 | dev_info(dev, "GAHBCFG=0x%08x, GHWCFG1=0x%08x\n", |
95c8bc36 | 3478 | dwc2_readl(regs + GAHBCFG), dwc2_readl(regs + GHWCFG1)); |
5b7d70c6 BD |
3479 | |
3480 | dev_info(dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n", | |
95c8bc36 | 3481 | dwc2_readl(regs + GRXFSIZ), dwc2_readl(regs + GNPTXFSIZ)); |
5b7d70c6 BD |
3482 | |
3483 | /* show periodic fifo settings */ | |
3484 | ||
364f8e93 | 3485 | for (idx = 1; idx < hsotg->num_of_eps; idx++) { |
95c8bc36 | 3486 | val = dwc2_readl(regs + DPTXFSIZN(idx)); |
5b7d70c6 | 3487 | dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx, |
47a1685f DN |
3488 | val >> FIFOSIZE_DEPTH_SHIFT, |
3489 | val & FIFOSIZE_STARTADDR_MASK); | |
5b7d70c6 BD |
3490 | } |
3491 | ||
364f8e93 | 3492 | for (idx = 0; idx < hsotg->num_of_eps; idx++) { |
5b7d70c6 BD |
3493 | dev_info(dev, |
3494 | "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx, | |
95c8bc36 AS |
3495 | dwc2_readl(regs + DIEPCTL(idx)), |
3496 | dwc2_readl(regs + DIEPTSIZ(idx)), | |
3497 | dwc2_readl(regs + DIEPDMA(idx))); | |
5b7d70c6 | 3498 | |
95c8bc36 | 3499 | val = dwc2_readl(regs + DOEPCTL(idx)); |
5b7d70c6 BD |
3500 | dev_info(dev, |
3501 | "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", | |
95c8bc36 AS |
3502 | idx, dwc2_readl(regs + DOEPCTL(idx)), |
3503 | dwc2_readl(regs + DOEPTSIZ(idx)), | |
3504 | dwc2_readl(regs + DOEPDMA(idx))); | |
5b7d70c6 BD |
3505 | |
3506 | } | |
3507 | ||
3508 | dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n", | |
95c8bc36 | 3509 | dwc2_readl(regs + DVBUSDIS), dwc2_readl(regs + DVBUSPULSE)); |
83a01804 | 3510 | #endif |
5b7d70c6 BD |
3511 | } |
3512 | ||
edd74be8 | 3513 | #ifdef CONFIG_OF |
1f91b4cc | 3514 | static void dwc2_hsotg_of_probe(struct dwc2_hsotg *hsotg) |
edd74be8 GH |
3515 | { |
3516 | struct device_node *np = hsotg->dev->of_node; | |
0a176279 GH |
3517 | u32 len = 0; |
3518 | u32 i = 0; | |
edd74be8 GH |
3519 | |
3520 | /* Enable dma if requested in device tree */ | |
3521 | hsotg->g_using_dma = of_property_read_bool(np, "g-use-dma"); | |
0a176279 GH |
3522 | |
3523 | /* | |
3524 | * Register TX periodic fifo size per endpoint. | |
3525 | * EP0 is excluded since it has no fifo configuration. | |
3526 | */ | |
3527 | if (!of_find_property(np, "g-tx-fifo-size", &len)) | |
3528 | goto rx_fifo; | |
3529 | ||
3530 | len /= sizeof(u32); | |
3531 | ||
3532 | /* Read tx fifo sizes other than ep0 */ | |
3533 | if (of_property_read_u32_array(np, "g-tx-fifo-size", | |
3534 | &hsotg->g_tx_fifo_sz[1], len)) | |
3535 | goto rx_fifo; | |
3536 | ||
3537 | /* Add ep0 */ | |
3538 | len++; | |
3539 | ||
3540 | /* Make remaining TX fifos unavailable */ | |
3541 | if (len < MAX_EPS_CHANNELS) { | |
3542 | for (i = len; i < MAX_EPS_CHANNELS; i++) | |
3543 | hsotg->g_tx_fifo_sz[i] = 0; | |
3544 | } | |
3545 | ||
3546 | rx_fifo: | |
3547 | /* Register RX fifo size */ | |
3548 | of_property_read_u32(np, "g-rx-fifo-size", &hsotg->g_rx_fifo_sz); | |
3549 | ||
3550 | /* Register NPTX fifo size */ | |
3551 | of_property_read_u32(np, "g-np-tx-fifo-size", | |
3552 | &hsotg->g_np_g_tx_fifo_sz); | |
edd74be8 GH |
3553 | } |
3554 | #else | |
1f91b4cc | 3555 | static inline void dwc2_hsotg_of_probe(struct dwc2_hsotg *hsotg) { } |
edd74be8 GH |
3556 | #endif |
3557 | ||
8b9bc460 | 3558 | /** |
117777b2 DN |
3559 | * dwc2_gadget_init - init function for gadget |
3560 | * @dwc2: The data structure for the DWC2 driver. | |
3561 | * @irq: The IRQ number for the controller. | |
8b9bc460 | 3562 | */ |
117777b2 | 3563 | int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq) |
5b7d70c6 | 3564 | { |
117777b2 | 3565 | struct device *dev = hsotg->dev; |
1f91b4cc | 3566 | struct dwc2_hsotg_plat *plat = dev->platform_data; |
5b7d70c6 BD |
3567 | int epnum; |
3568 | int ret; | |
fc9a731e | 3569 | int i; |
0a176279 | 3570 | u32 p_tx_fifo[] = DWC2_G_P_LEGACY_TX_FIFO_SIZE; |
5b7d70c6 | 3571 | |
1b59fc7e KD |
3572 | /* Set default UTMI width */ |
3573 | hsotg->phyif = GUSBCFG_PHYIF16; | |
3574 | ||
1f91b4cc | 3575 | dwc2_hsotg_of_probe(hsotg); |
edd74be8 | 3576 | |
0a176279 GH |
3577 | /* Initialize to legacy fifo configuration values */ |
3578 | hsotg->g_rx_fifo_sz = 2048; | |
3579 | hsotg->g_np_g_tx_fifo_sz = 1024; | |
3580 | memcpy(&hsotg->g_tx_fifo_sz[1], p_tx_fifo, sizeof(p_tx_fifo)); | |
3581 | /* Device tree specific probe */ | |
1f91b4cc | 3582 | dwc2_hsotg_of_probe(hsotg); |
0a176279 GH |
3583 | /* Dump fifo information */ |
3584 | dev_dbg(dev, "NonPeriodic TXFIFO size: %d\n", | |
3585 | hsotg->g_np_g_tx_fifo_sz); | |
3586 | dev_dbg(dev, "RXFIFO size: %d\n", hsotg->g_rx_fifo_sz); | |
3587 | for (i = 0; i < MAX_EPS_CHANNELS; i++) | |
3588 | dev_dbg(dev, "Periodic TXFIFO%2d size: %d\n", i, | |
3589 | hsotg->g_tx_fifo_sz[i]); | |
74084844 | 3590 | /* |
135b3c43 YL |
3591 | * If platform probe couldn't find a generic PHY or an old style |
3592 | * USB PHY, fall back to pdata | |
74084844 | 3593 | */ |
135b3c43 YL |
3594 | if (IS_ERR_OR_NULL(hsotg->phy) && IS_ERR_OR_NULL(hsotg->uphy)) { |
3595 | plat = dev_get_platdata(dev); | |
3596 | if (!plat) { | |
3597 | dev_err(dev, | |
3598 | "no platform data or transceiver defined\n"); | |
3599 | return -EPROBE_DEFER; | |
3600 | } | |
3601 | hsotg->plat = plat; | |
3602 | } else if (hsotg->phy) { | |
1b59fc7e KD |
3603 | /* |
3604 | * If using the generic PHY framework, check if the PHY bus | |
3605 | * width is 8-bit and set the phyif appropriately. | |
3606 | */ | |
135b3c43 | 3607 | if (phy_get_bus_width(hsotg->phy) == 8) |
1b59fc7e KD |
3608 | hsotg->phyif = GUSBCFG_PHYIF8; |
3609 | } | |
b2e587db | 3610 | |
117777b2 | 3611 | hsotg->clk = devm_clk_get(dev, "otg"); |
31ee04de | 3612 | if (IS_ERR(hsotg->clk)) { |
8d736d8a | 3613 | hsotg->clk = NULL; |
f415fbd1 | 3614 | dev_dbg(dev, "cannot get otg clock\n"); |
5b7d70c6 BD |
3615 | } |
3616 | ||
d327ab5b | 3617 | hsotg->gadget.max_speed = USB_SPEED_HIGH; |
1f91b4cc | 3618 | hsotg->gadget.ops = &dwc2_hsotg_gadget_ops; |
5b7d70c6 | 3619 | hsotg->gadget.name = dev_name(dev); |
097ee662 GH |
3620 | if (hsotg->dr_mode == USB_DR_MODE_OTG) |
3621 | hsotg->gadget.is_otg = 1; | |
ec4cc657 MYK |
3622 | else if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) |
3623 | hsotg->op_state = OTG_STATE_B_PERIPHERAL; | |
5b7d70c6 | 3624 | |
5b7d70c6 BD |
3625 | /* reset the system */ |
3626 | ||
f415fbd1 DN |
3627 | ret = clk_prepare_enable(hsotg->clk); |
3628 | if (ret) { | |
3629 | dev_err(dev, "failed to enable otg clk\n"); | |
3630 | goto err_clk; | |
3631 | } | |
3632 | ||
31ee04de | 3633 | |
fc9a731e LM |
3634 | /* regulators */ |
3635 | ||
3636 | for (i = 0; i < ARRAY_SIZE(hsotg->supplies); i++) | |
1f91b4cc | 3637 | hsotg->supplies[i].supply = dwc2_hsotg_supply_names[i]; |
fc9a731e | 3638 | |
cd76213e | 3639 | ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(hsotg->supplies), |
fc9a731e LM |
3640 | hsotg->supplies); |
3641 | if (ret) { | |
3642 | dev_err(dev, "failed to request supplies: %d\n", ret); | |
338edabc | 3643 | goto err_clk; |
fc9a731e LM |
3644 | } |
3645 | ||
3646 | ret = regulator_bulk_enable(ARRAY_SIZE(hsotg->supplies), | |
3647 | hsotg->supplies); | |
3648 | ||
3649 | if (ret) { | |
941fcce4 | 3650 | dev_err(dev, "failed to enable supplies: %d\n", ret); |
c139ec27 | 3651 | goto err_clk; |
fc9a731e LM |
3652 | } |
3653 | ||
41188786 | 3654 | /* usb phy enable */ |
1f91b4cc | 3655 | dwc2_hsotg_phy_enable(hsotg); |
5b7d70c6 | 3656 | |
1b7a66b4 GH |
3657 | /* |
3658 | * Force Device mode before initialization. | |
3659 | * This allows correctly configuring fifo for device mode. | |
3660 | */ | |
3661 | __bic32(hsotg->regs + GUSBCFG, GUSBCFG_FORCEHOSTMODE); | |
3662 | __orr32(hsotg->regs + GUSBCFG, GUSBCFG_FORCEDEVMODE); | |
3663 | ||
3664 | /* | |
3665 | * According to Synopsys databook, this sleep is needed for the force | |
3666 | * device mode to take effect. | |
3667 | */ | |
3668 | msleep(25); | |
3669 | ||
1f91b4cc FB |
3670 | dwc2_hsotg_corereset(hsotg); |
3671 | ret = dwc2_hsotg_hw_cfg(hsotg); | |
c6f5c050 MYK |
3672 | if (ret) { |
3673 | dev_err(hsotg->dev, "Hardware configuration failed: %d\n", ret); | |
3674 | goto err_clk; | |
3675 | } | |
3676 | ||
1f91b4cc | 3677 | dwc2_hsotg_init(hsotg); |
b3f489b2 | 3678 | |
1b7a66b4 GH |
3679 | /* Switch back to default configuration */ |
3680 | __bic32(hsotg->regs + GUSBCFG, GUSBCFG_FORCEDEVMODE); | |
3681 | ||
3f95001d MYK |
3682 | hsotg->ctrl_buff = devm_kzalloc(hsotg->dev, |
3683 | DWC2_CTRL_BUFF_SIZE, GFP_KERNEL); | |
3684 | if (!hsotg->ctrl_buff) { | |
3685 | dev_err(dev, "failed to allocate ctrl request buff\n"); | |
3686 | ret = -ENOMEM; | |
3687 | goto err_supplies; | |
3688 | } | |
3689 | ||
3690 | hsotg->ep0_buff = devm_kzalloc(hsotg->dev, | |
3691 | DWC2_CTRL_BUFF_SIZE, GFP_KERNEL); | |
3692 | if (!hsotg->ep0_buff) { | |
3693 | dev_err(dev, "failed to allocate ctrl reply buff\n"); | |
3694 | ret = -ENOMEM; | |
3695 | goto err_supplies; | |
3696 | } | |
3697 | ||
1f91b4cc | 3698 | ret = devm_request_irq(hsotg->dev, irq, dwc2_hsotg_irq, IRQF_SHARED, |
db8178c3 | 3699 | dev_name(hsotg->dev), hsotg); |
eb3c56c5 | 3700 | if (ret < 0) { |
1f91b4cc | 3701 | dwc2_hsotg_phy_disable(hsotg); |
eb3c56c5 MS |
3702 | clk_disable_unprepare(hsotg->clk); |
3703 | regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies), | |
3704 | hsotg->supplies); | |
db8178c3 | 3705 | dev_err(dev, "cannot claim IRQ for gadget\n"); |
c139ec27 | 3706 | goto err_supplies; |
eb3c56c5 MS |
3707 | } |
3708 | ||
b3f489b2 LM |
3709 | /* hsotg->num_of_eps holds number of EPs other than ep0 */ |
3710 | ||
3711 | if (hsotg->num_of_eps == 0) { | |
3712 | dev_err(dev, "wrong number of EPs (zero)\n"); | |
dfdda5a0 | 3713 | ret = -EINVAL; |
b3f489b2 LM |
3714 | goto err_supplies; |
3715 | } | |
3716 | ||
b3f489b2 LM |
3717 | /* setup endpoint information */ |
3718 | ||
3719 | INIT_LIST_HEAD(&hsotg->gadget.ep_list); | |
c6f5c050 | 3720 | hsotg->gadget.ep0 = &hsotg->eps_out[0]->ep; |
b3f489b2 LM |
3721 | |
3722 | /* allocate EP0 request */ | |
3723 | ||
1f91b4cc | 3724 | hsotg->ctrl_req = dwc2_hsotg_ep_alloc_request(&hsotg->eps_out[0]->ep, |
b3f489b2 LM |
3725 | GFP_KERNEL); |
3726 | if (!hsotg->ctrl_req) { | |
3727 | dev_err(dev, "failed to allocate ctrl req\n"); | |
dfdda5a0 | 3728 | ret = -ENOMEM; |
c6f5c050 | 3729 | goto err_supplies; |
b3f489b2 | 3730 | } |
5b7d70c6 BD |
3731 | |
3732 | /* initialise the endpoints now the core has been initialised */ | |
c6f5c050 MYK |
3733 | for (epnum = 0; epnum < hsotg->num_of_eps; epnum++) { |
3734 | if (hsotg->eps_in[epnum]) | |
1f91b4cc | 3735 | dwc2_hsotg_initep(hsotg, hsotg->eps_in[epnum], |
c6f5c050 MYK |
3736 | epnum, 1); |
3737 | if (hsotg->eps_out[epnum]) | |
1f91b4cc | 3738 | dwc2_hsotg_initep(hsotg, hsotg->eps_out[epnum], |
c6f5c050 MYK |
3739 | epnum, 0); |
3740 | } | |
5b7d70c6 | 3741 | |
f65f0f10 | 3742 | /* disable power and clock */ |
1f91b4cc | 3743 | dwc2_hsotg_phy_disable(hsotg); |
f65f0f10 LM |
3744 | |
3745 | ret = regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies), | |
3746 | hsotg->supplies); | |
3747 | if (ret) { | |
117777b2 | 3748 | dev_err(dev, "failed to disable supplies: %d\n", ret); |
c6f5c050 | 3749 | goto err_supplies; |
f65f0f10 LM |
3750 | } |
3751 | ||
117777b2 | 3752 | ret = usb_add_gadget_udc(dev, &hsotg->gadget); |
0f91349b | 3753 | if (ret) |
c6f5c050 | 3754 | goto err_supplies; |
0f91349b | 3755 | |
1f91b4cc | 3756 | dwc2_hsotg_dump(hsotg); |
5b7d70c6 | 3757 | |
5b7d70c6 BD |
3758 | return 0; |
3759 | ||
fc9a731e | 3760 | err_supplies: |
1f91b4cc | 3761 | dwc2_hsotg_phy_disable(hsotg); |
31ee04de | 3762 | err_clk: |
1d144c67 | 3763 | clk_disable_unprepare(hsotg->clk); |
338edabc | 3764 | |
5b7d70c6 BD |
3765 | return ret; |
3766 | } | |
3767 | ||
8b9bc460 | 3768 | /** |
1f91b4cc | 3769 | * dwc2_hsotg_remove - remove function for hsotg driver |
8b9bc460 LM |
3770 | * @pdev: The platform information for the driver |
3771 | */ | |
1f91b4cc | 3772 | int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 3773 | { |
0f91349b | 3774 | usb_del_gadget_udc(&hsotg->gadget); |
04b4a0fc | 3775 | clk_disable_unprepare(hsotg->clk); |
31ee04de | 3776 | |
5b7d70c6 BD |
3777 | return 0; |
3778 | } | |
3779 | ||
1f91b4cc | 3780 | int dwc2_hsotg_suspend(struct dwc2_hsotg *hsotg) |
b83e333a | 3781 | { |
b83e333a MS |
3782 | unsigned long flags; |
3783 | int ret = 0; | |
3784 | ||
9e779778 GH |
3785 | if (hsotg->lx_state != DWC2_L0) |
3786 | return ret; | |
3787 | ||
7ad8096e MS |
3788 | mutex_lock(&hsotg->init_mutex); |
3789 | ||
dc6e69e6 MS |
3790 | if (hsotg->driver) { |
3791 | int ep; | |
3792 | ||
b83e333a MS |
3793 | dev_info(hsotg->dev, "suspending usb gadget %s\n", |
3794 | hsotg->driver->driver.name); | |
3795 | ||
dc6e69e6 MS |
3796 | spin_lock_irqsave(&hsotg->lock, flags); |
3797 | if (hsotg->enabled) | |
1f91b4cc FB |
3798 | dwc2_hsotg_core_disconnect(hsotg); |
3799 | dwc2_hsotg_disconnect(hsotg); | |
dc6e69e6 MS |
3800 | hsotg->gadget.speed = USB_SPEED_UNKNOWN; |
3801 | spin_unlock_irqrestore(&hsotg->lock, flags); | |
b83e333a | 3802 | |
1f91b4cc | 3803 | dwc2_hsotg_phy_disable(hsotg); |
b83e333a | 3804 | |
c6f5c050 MYK |
3805 | for (ep = 0; ep < hsotg->num_of_eps; ep++) { |
3806 | if (hsotg->eps_in[ep]) | |
1f91b4cc | 3807 | dwc2_hsotg_ep_disable(&hsotg->eps_in[ep]->ep); |
c6f5c050 | 3808 | if (hsotg->eps_out[ep]) |
1f91b4cc | 3809 | dwc2_hsotg_ep_disable(&hsotg->eps_out[ep]->ep); |
c6f5c050 | 3810 | } |
b83e333a MS |
3811 | |
3812 | ret = regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies), | |
3813 | hsotg->supplies); | |
d00b4142 | 3814 | clk_disable(hsotg->clk); |
b83e333a MS |
3815 | } |
3816 | ||
7ad8096e MS |
3817 | mutex_unlock(&hsotg->init_mutex); |
3818 | ||
b83e333a MS |
3819 | return ret; |
3820 | } | |
3821 | ||
1f91b4cc | 3822 | int dwc2_hsotg_resume(struct dwc2_hsotg *hsotg) |
b83e333a | 3823 | { |
b83e333a MS |
3824 | unsigned long flags; |
3825 | int ret = 0; | |
3826 | ||
9e779778 GH |
3827 | if (hsotg->lx_state == DWC2_L2) |
3828 | return ret; | |
3829 | ||
7ad8096e MS |
3830 | mutex_lock(&hsotg->init_mutex); |
3831 | ||
b83e333a MS |
3832 | if (hsotg->driver) { |
3833 | dev_info(hsotg->dev, "resuming usb gadget %s\n", | |
3834 | hsotg->driver->driver.name); | |
d00b4142 RB |
3835 | |
3836 | clk_enable(hsotg->clk); | |
b83e333a | 3837 | ret = regulator_bulk_enable(ARRAY_SIZE(hsotg->supplies), |
dc6e69e6 | 3838 | hsotg->supplies); |
b83e333a | 3839 | |
1f91b4cc | 3840 | dwc2_hsotg_phy_enable(hsotg); |
b83e333a | 3841 | |
dc6e69e6 | 3842 | spin_lock_irqsave(&hsotg->lock, flags); |
1f91b4cc | 3843 | dwc2_hsotg_core_init_disconnected(hsotg, false); |
dc6e69e6 | 3844 | if (hsotg->enabled) |
1f91b4cc | 3845 | dwc2_hsotg_core_connect(hsotg); |
dc6e69e6 MS |
3846 | spin_unlock_irqrestore(&hsotg->lock, flags); |
3847 | } | |
7ad8096e | 3848 | mutex_unlock(&hsotg->init_mutex); |
b83e333a MS |
3849 | |
3850 | return ret; | |
3851 | } |