Commit | Line | Data |
---|---|---|
8b9bc460 | 1 | /** |
dfbc6fa3 AT |
2 | * Copyright (c) 2011 Samsung Electronics Co., Ltd. |
3 | * http://www.samsung.com | |
5b7d70c6 BD |
4 | * |
5 | * Copyright 2008 Openmoko, Inc. | |
6 | * Copyright 2008 Simtec Electronics | |
7 | * Ben Dooks <ben@simtec.co.uk> | |
8 | * http://armlinux.simtec.co.uk/ | |
9 | * | |
10 | * S3C USB2.0 High-speed / OtG driver | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License version 2 as | |
14 | * published by the Free Software Foundation. | |
8b9bc460 | 15 | */ |
5b7d70c6 BD |
16 | |
17 | #include <linux/kernel.h> | |
18 | #include <linux/module.h> | |
19 | #include <linux/spinlock.h> | |
20 | #include <linux/interrupt.h> | |
21 | #include <linux/platform_device.h> | |
22 | #include <linux/dma-mapping.h> | |
7ad8096e | 23 | #include <linux/mutex.h> |
5b7d70c6 BD |
24 | #include <linux/seq_file.h> |
25 | #include <linux/delay.h> | |
26 | #include <linux/io.h> | |
5a0e3ad6 | 27 | #include <linux/slab.h> |
c50f056c | 28 | #include <linux/of_platform.h> |
5b7d70c6 BD |
29 | |
30 | #include <linux/usb/ch9.h> | |
31 | #include <linux/usb/gadget.h> | |
b2e587db | 32 | #include <linux/usb/phy.h> |
5b7d70c6 | 33 | |
f7c0b143 | 34 | #include "core.h" |
941fcce4 | 35 | #include "hw.h" |
5b7d70c6 BD |
36 | |
37 | /* conversion functions */ | |
1f91b4cc | 38 | static inline struct dwc2_hsotg_req *our_req(struct usb_request *req) |
5b7d70c6 | 39 | { |
1f91b4cc | 40 | return container_of(req, struct dwc2_hsotg_req, req); |
5b7d70c6 BD |
41 | } |
42 | ||
1f91b4cc | 43 | static inline struct dwc2_hsotg_ep *our_ep(struct usb_ep *ep) |
5b7d70c6 | 44 | { |
1f91b4cc | 45 | return container_of(ep, struct dwc2_hsotg_ep, ep); |
5b7d70c6 BD |
46 | } |
47 | ||
941fcce4 | 48 | static inline struct dwc2_hsotg *to_hsotg(struct usb_gadget *gadget) |
5b7d70c6 | 49 | { |
941fcce4 | 50 | return container_of(gadget, struct dwc2_hsotg, gadget); |
5b7d70c6 BD |
51 | } |
52 | ||
53 | static inline void __orr32(void __iomem *ptr, u32 val) | |
54 | { | |
95c8bc36 | 55 | dwc2_writel(dwc2_readl(ptr) | val, ptr); |
5b7d70c6 BD |
56 | } |
57 | ||
58 | static inline void __bic32(void __iomem *ptr, u32 val) | |
59 | { | |
95c8bc36 | 60 | dwc2_writel(dwc2_readl(ptr) & ~val, ptr); |
5b7d70c6 BD |
61 | } |
62 | ||
1f91b4cc | 63 | static inline struct dwc2_hsotg_ep *index_to_ep(struct dwc2_hsotg *hsotg, |
c6f5c050 MYK |
64 | u32 ep_index, u32 dir_in) |
65 | { | |
66 | if (dir_in) | |
67 | return hsotg->eps_in[ep_index]; | |
68 | else | |
69 | return hsotg->eps_out[ep_index]; | |
70 | } | |
71 | ||
997f4f81 | 72 | /* forward declaration of functions */ |
1f91b4cc | 73 | static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg); |
5b7d70c6 BD |
74 | |
75 | /** | |
76 | * using_dma - return the DMA status of the driver. | |
77 | * @hsotg: The driver state. | |
78 | * | |
79 | * Return true if we're using DMA. | |
80 | * | |
81 | * Currently, we have the DMA support code worked into everywhere | |
82 | * that needs it, but the AMBA DMA implementation in the hardware can | |
83 | * only DMA from 32bit aligned addresses. This means that gadgets such | |
84 | * as the CDC Ethernet cannot work as they often pass packets which are | |
85 | * not 32bit aligned. | |
86 | * | |
87 | * Unfortunately the choice to use DMA or not is global to the controller | |
88 | * and seems to be only settable when the controller is being put through | |
89 | * a core reset. This means we either need to fix the gadgets to take | |
90 | * account of DMA alignment, or add bounce buffers (yuerk). | |
91 | * | |
edd74be8 | 92 | * g_using_dma is set depending on dts flag. |
5b7d70c6 | 93 | */ |
941fcce4 | 94 | static inline bool using_dma(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 95 | { |
edd74be8 | 96 | return hsotg->g_using_dma; |
5b7d70c6 BD |
97 | } |
98 | ||
92d1635d VM |
99 | /** |
100 | * dwc2_gadget_incr_frame_num - Increments the targeted frame number. | |
101 | * @hs_ep: The endpoint | |
102 | * @increment: The value to increment by | |
103 | * | |
104 | * This function will also check if the frame number overruns DSTS_SOFFN_LIMIT. | |
105 | * If an overrun occurs it will wrap the value and set the frame_overrun flag. | |
106 | */ | |
107 | static inline void dwc2_gadget_incr_frame_num(struct dwc2_hsotg_ep *hs_ep) | |
108 | { | |
109 | hs_ep->target_frame += hs_ep->interval; | |
110 | if (hs_ep->target_frame > DSTS_SOFFN_LIMIT) { | |
111 | hs_ep->frame_overrun = 1; | |
112 | hs_ep->target_frame &= DSTS_SOFFN_LIMIT; | |
113 | } else { | |
114 | hs_ep->frame_overrun = 0; | |
115 | } | |
116 | } | |
117 | ||
5b7d70c6 | 118 | /** |
1f91b4cc | 119 | * dwc2_hsotg_en_gsint - enable one or more of the general interrupt |
5b7d70c6 BD |
120 | * @hsotg: The device state |
121 | * @ints: A bitmask of the interrupts to enable | |
122 | */ | |
1f91b4cc | 123 | static void dwc2_hsotg_en_gsint(struct dwc2_hsotg *hsotg, u32 ints) |
5b7d70c6 | 124 | { |
95c8bc36 | 125 | u32 gsintmsk = dwc2_readl(hsotg->regs + GINTMSK); |
5b7d70c6 BD |
126 | u32 new_gsintmsk; |
127 | ||
128 | new_gsintmsk = gsintmsk | ints; | |
129 | ||
130 | if (new_gsintmsk != gsintmsk) { | |
131 | dev_dbg(hsotg->dev, "gsintmsk now 0x%08x\n", new_gsintmsk); | |
95c8bc36 | 132 | dwc2_writel(new_gsintmsk, hsotg->regs + GINTMSK); |
5b7d70c6 BD |
133 | } |
134 | } | |
135 | ||
136 | /** | |
1f91b4cc | 137 | * dwc2_hsotg_disable_gsint - disable one or more of the general interrupt |
5b7d70c6 BD |
138 | * @hsotg: The device state |
139 | * @ints: A bitmask of the interrupts to enable | |
140 | */ | |
1f91b4cc | 141 | static void dwc2_hsotg_disable_gsint(struct dwc2_hsotg *hsotg, u32 ints) |
5b7d70c6 | 142 | { |
95c8bc36 | 143 | u32 gsintmsk = dwc2_readl(hsotg->regs + GINTMSK); |
5b7d70c6 BD |
144 | u32 new_gsintmsk; |
145 | ||
146 | new_gsintmsk = gsintmsk & ~ints; | |
147 | ||
148 | if (new_gsintmsk != gsintmsk) | |
95c8bc36 | 149 | dwc2_writel(new_gsintmsk, hsotg->regs + GINTMSK); |
5b7d70c6 BD |
150 | } |
151 | ||
152 | /** | |
1f91b4cc | 153 | * dwc2_hsotg_ctrl_epint - enable/disable an endpoint irq |
5b7d70c6 BD |
154 | * @hsotg: The device state |
155 | * @ep: The endpoint index | |
156 | * @dir_in: True if direction is in. | |
157 | * @en: The enable value, true to enable | |
158 | * | |
159 | * Set or clear the mask for an individual endpoint's interrupt | |
160 | * request. | |
161 | */ | |
1f91b4cc | 162 | static void dwc2_hsotg_ctrl_epint(struct dwc2_hsotg *hsotg, |
5b7d70c6 BD |
163 | unsigned int ep, unsigned int dir_in, |
164 | unsigned int en) | |
165 | { | |
166 | unsigned long flags; | |
167 | u32 bit = 1 << ep; | |
168 | u32 daint; | |
169 | ||
170 | if (!dir_in) | |
171 | bit <<= 16; | |
172 | ||
173 | local_irq_save(flags); | |
95c8bc36 | 174 | daint = dwc2_readl(hsotg->regs + DAINTMSK); |
5b7d70c6 BD |
175 | if (en) |
176 | daint |= bit; | |
177 | else | |
178 | daint &= ~bit; | |
95c8bc36 | 179 | dwc2_writel(daint, hsotg->regs + DAINTMSK); |
5b7d70c6 BD |
180 | local_irq_restore(flags); |
181 | } | |
182 | ||
183 | /** | |
1f91b4cc | 184 | * dwc2_hsotg_init_fifo - initialise non-periodic FIFOs |
5b7d70c6 BD |
185 | * @hsotg: The device instance. |
186 | */ | |
1f91b4cc | 187 | static void dwc2_hsotg_init_fifo(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 188 | { |
0f002d20 BD |
189 | unsigned int ep; |
190 | unsigned int addr; | |
1703a6d3 | 191 | int timeout; |
0f002d20 BD |
192 | u32 val; |
193 | ||
7fcbc95c GH |
194 | /* Reset fifo map if not correctly cleared during previous session */ |
195 | WARN_ON(hsotg->fifo_map); | |
196 | hsotg->fifo_map = 0; | |
197 | ||
0a176279 | 198 | /* set RX/NPTX FIFO sizes */ |
95c8bc36 AS |
199 | dwc2_writel(hsotg->g_rx_fifo_sz, hsotg->regs + GRXFSIZ); |
200 | dwc2_writel((hsotg->g_rx_fifo_sz << FIFOSIZE_STARTADDR_SHIFT) | | |
0a176279 GH |
201 | (hsotg->g_np_g_tx_fifo_sz << FIFOSIZE_DEPTH_SHIFT), |
202 | hsotg->regs + GNPTXFSIZ); | |
0f002d20 | 203 | |
8b9bc460 LM |
204 | /* |
205 | * arange all the rest of the TX FIFOs, as some versions of this | |
0f002d20 BD |
206 | * block have overlapping default addresses. This also ensures |
207 | * that if the settings have been changed, then they are set to | |
8b9bc460 LM |
208 | * known values. |
209 | */ | |
0f002d20 BD |
210 | |
211 | /* start at the end of the GNPTXFSIZ, rounded up */ | |
0a176279 | 212 | addr = hsotg->g_rx_fifo_sz + hsotg->g_np_g_tx_fifo_sz; |
0f002d20 | 213 | |
8b9bc460 | 214 | /* |
0a176279 | 215 | * Configure fifos sizes from provided configuration and assign |
b203d0a2 RB |
216 | * them to endpoints dynamically according to maxpacket size value of |
217 | * given endpoint. | |
8b9bc460 | 218 | */ |
0a176279 GH |
219 | for (ep = 1; ep < MAX_EPS_CHANNELS; ep++) { |
220 | if (!hsotg->g_tx_fifo_sz[ep]) | |
221 | continue; | |
0f002d20 | 222 | val = addr; |
0a176279 GH |
223 | val |= hsotg->g_tx_fifo_sz[ep] << FIFOSIZE_DEPTH_SHIFT; |
224 | WARN_ONCE(addr + hsotg->g_tx_fifo_sz[ep] > hsotg->fifo_mem, | |
cff9eb75 | 225 | "insufficient fifo memory"); |
0a176279 | 226 | addr += hsotg->g_tx_fifo_sz[ep]; |
0f002d20 | 227 | |
95c8bc36 | 228 | dwc2_writel(val, hsotg->regs + DPTXFSIZN(ep)); |
0f002d20 | 229 | } |
1703a6d3 | 230 | |
8b9bc460 LM |
231 | /* |
232 | * according to p428 of the design guide, we need to ensure that | |
233 | * all fifos are flushed before continuing | |
234 | */ | |
1703a6d3 | 235 | |
95c8bc36 | 236 | dwc2_writel(GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH | |
47a1685f | 237 | GRSTCTL_RXFFLSH, hsotg->regs + GRSTCTL); |
1703a6d3 BD |
238 | |
239 | /* wait until the fifos are both flushed */ | |
240 | timeout = 100; | |
241 | while (1) { | |
95c8bc36 | 242 | val = dwc2_readl(hsotg->regs + GRSTCTL); |
1703a6d3 | 243 | |
47a1685f | 244 | if ((val & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH)) == 0) |
1703a6d3 BD |
245 | break; |
246 | ||
247 | if (--timeout == 0) { | |
248 | dev_err(hsotg->dev, | |
249 | "%s: timeout flushing fifos (GRSTCTL=%08x)\n", | |
250 | __func__, val); | |
48b20bcb | 251 | break; |
1703a6d3 BD |
252 | } |
253 | ||
254 | udelay(1); | |
255 | } | |
256 | ||
257 | dev_dbg(hsotg->dev, "FIFOs reset, timeout at %d\n", timeout); | |
5b7d70c6 BD |
258 | } |
259 | ||
260 | /** | |
261 | * @ep: USB endpoint to allocate request for. | |
262 | * @flags: Allocation flags | |
263 | * | |
264 | * Allocate a new USB request structure appropriate for the specified endpoint | |
265 | */ | |
1f91b4cc | 266 | static struct usb_request *dwc2_hsotg_ep_alloc_request(struct usb_ep *ep, |
0978f8c5 | 267 | gfp_t flags) |
5b7d70c6 | 268 | { |
1f91b4cc | 269 | struct dwc2_hsotg_req *req; |
5b7d70c6 | 270 | |
1f91b4cc | 271 | req = kzalloc(sizeof(struct dwc2_hsotg_req), flags); |
5b7d70c6 BD |
272 | if (!req) |
273 | return NULL; | |
274 | ||
275 | INIT_LIST_HEAD(&req->queue); | |
276 | ||
5b7d70c6 BD |
277 | return &req->req; |
278 | } | |
279 | ||
280 | /** | |
281 | * is_ep_periodic - return true if the endpoint is in periodic mode. | |
282 | * @hs_ep: The endpoint to query. | |
283 | * | |
284 | * Returns true if the endpoint is in periodic mode, meaning it is being | |
285 | * used for an Interrupt or ISO transfer. | |
286 | */ | |
1f91b4cc | 287 | static inline int is_ep_periodic(struct dwc2_hsotg_ep *hs_ep) |
5b7d70c6 BD |
288 | { |
289 | return hs_ep->periodic; | |
290 | } | |
291 | ||
292 | /** | |
1f91b4cc | 293 | * dwc2_hsotg_unmap_dma - unmap the DMA memory being used for the request |
5b7d70c6 BD |
294 | * @hsotg: The device state. |
295 | * @hs_ep: The endpoint for the request | |
296 | * @hs_req: The request being processed. | |
297 | * | |
1f91b4cc | 298 | * This is the reverse of dwc2_hsotg_map_dma(), called for the completion |
5b7d70c6 | 299 | * of a request to ensure the buffer is ready for access by the caller. |
8b9bc460 | 300 | */ |
1f91b4cc FB |
301 | static void dwc2_hsotg_unmap_dma(struct dwc2_hsotg *hsotg, |
302 | struct dwc2_hsotg_ep *hs_ep, | |
303 | struct dwc2_hsotg_req *hs_req) | |
5b7d70c6 BD |
304 | { |
305 | struct usb_request *req = &hs_req->req; | |
5b7d70c6 BD |
306 | |
307 | /* ignore this if we're not moving any data */ | |
308 | if (hs_req->req.length == 0) | |
309 | return; | |
310 | ||
17d966a3 | 311 | usb_gadget_unmap_request(&hsotg->gadget, req, hs_ep->dir_in); |
5b7d70c6 BD |
312 | } |
313 | ||
314 | /** | |
1f91b4cc | 315 | * dwc2_hsotg_write_fifo - write packet Data to the TxFIFO |
5b7d70c6 BD |
316 | * @hsotg: The controller state. |
317 | * @hs_ep: The endpoint we're going to write for. | |
318 | * @hs_req: The request to write data for. | |
319 | * | |
320 | * This is called when the TxFIFO has some space in it to hold a new | |
321 | * transmission and we have something to give it. The actual setup of | |
322 | * the data size is done elsewhere, so all we have to do is to actually | |
323 | * write the data. | |
324 | * | |
325 | * The return value is zero if there is more space (or nothing was done) | |
326 | * otherwise -ENOSPC is returned if the FIFO space was used up. | |
327 | * | |
328 | * This routine is only needed for PIO | |
8b9bc460 | 329 | */ |
1f91b4cc FB |
330 | static int dwc2_hsotg_write_fifo(struct dwc2_hsotg *hsotg, |
331 | struct dwc2_hsotg_ep *hs_ep, | |
332 | struct dwc2_hsotg_req *hs_req) | |
5b7d70c6 BD |
333 | { |
334 | bool periodic = is_ep_periodic(hs_ep); | |
95c8bc36 | 335 | u32 gnptxsts = dwc2_readl(hsotg->regs + GNPTXSTS); |
5b7d70c6 BD |
336 | int buf_pos = hs_req->req.actual; |
337 | int to_write = hs_ep->size_loaded; | |
338 | void *data; | |
339 | int can_write; | |
340 | int pkt_round; | |
4fca54aa | 341 | int max_transfer; |
5b7d70c6 BD |
342 | |
343 | to_write -= (buf_pos - hs_ep->last_load); | |
344 | ||
345 | /* if there's nothing to write, get out early */ | |
346 | if (to_write == 0) | |
347 | return 0; | |
348 | ||
10aebc77 | 349 | if (periodic && !hsotg->dedicated_fifos) { |
95c8bc36 | 350 | u32 epsize = dwc2_readl(hsotg->regs + DIEPTSIZ(hs_ep->index)); |
5b7d70c6 BD |
351 | int size_left; |
352 | int size_done; | |
353 | ||
8b9bc460 LM |
354 | /* |
355 | * work out how much data was loaded so we can calculate | |
356 | * how much data is left in the fifo. | |
357 | */ | |
5b7d70c6 | 358 | |
47a1685f | 359 | size_left = DXEPTSIZ_XFERSIZE_GET(epsize); |
5b7d70c6 | 360 | |
8b9bc460 LM |
361 | /* |
362 | * if shared fifo, we cannot write anything until the | |
e7a9ff54 BD |
363 | * previous data has been completely sent. |
364 | */ | |
365 | if (hs_ep->fifo_load != 0) { | |
1f91b4cc | 366 | dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP); |
e7a9ff54 BD |
367 | return -ENOSPC; |
368 | } | |
369 | ||
5b7d70c6 BD |
370 | dev_dbg(hsotg->dev, "%s: left=%d, load=%d, fifo=%d, size %d\n", |
371 | __func__, size_left, | |
372 | hs_ep->size_loaded, hs_ep->fifo_load, hs_ep->fifo_size); | |
373 | ||
374 | /* how much of the data has moved */ | |
375 | size_done = hs_ep->size_loaded - size_left; | |
376 | ||
377 | /* how much data is left in the fifo */ | |
378 | can_write = hs_ep->fifo_load - size_done; | |
379 | dev_dbg(hsotg->dev, "%s: => can_write1=%d\n", | |
380 | __func__, can_write); | |
381 | ||
382 | can_write = hs_ep->fifo_size - can_write; | |
383 | dev_dbg(hsotg->dev, "%s: => can_write2=%d\n", | |
384 | __func__, can_write); | |
385 | ||
386 | if (can_write <= 0) { | |
1f91b4cc | 387 | dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP); |
5b7d70c6 BD |
388 | return -ENOSPC; |
389 | } | |
10aebc77 | 390 | } else if (hsotg->dedicated_fifos && hs_ep->index != 0) { |
95c8bc36 | 391 | can_write = dwc2_readl(hsotg->regs + DTXFSTS(hs_ep->index)); |
10aebc77 BD |
392 | |
393 | can_write &= 0xffff; | |
394 | can_write *= 4; | |
5b7d70c6 | 395 | } else { |
47a1685f | 396 | if (GNPTXSTS_NP_TXQ_SPC_AVAIL_GET(gnptxsts) == 0) { |
5b7d70c6 BD |
397 | dev_dbg(hsotg->dev, |
398 | "%s: no queue slots available (0x%08x)\n", | |
399 | __func__, gnptxsts); | |
400 | ||
1f91b4cc | 401 | dwc2_hsotg_en_gsint(hsotg, GINTSTS_NPTXFEMP); |
5b7d70c6 BD |
402 | return -ENOSPC; |
403 | } | |
404 | ||
47a1685f | 405 | can_write = GNPTXSTS_NP_TXF_SPC_AVAIL_GET(gnptxsts); |
679f9b7c | 406 | can_write *= 4; /* fifo size is in 32bit quantities. */ |
5b7d70c6 BD |
407 | } |
408 | ||
4fca54aa RB |
409 | max_transfer = hs_ep->ep.maxpacket * hs_ep->mc; |
410 | ||
411 | dev_dbg(hsotg->dev, "%s: GNPTXSTS=%08x, can=%d, to=%d, max_transfer %d\n", | |
412 | __func__, gnptxsts, can_write, to_write, max_transfer); | |
5b7d70c6 | 413 | |
8b9bc460 LM |
414 | /* |
415 | * limit to 512 bytes of data, it seems at least on the non-periodic | |
5b7d70c6 BD |
416 | * FIFO, requests of >512 cause the endpoint to get stuck with a |
417 | * fragment of the end of the transfer in it. | |
418 | */ | |
811f3303 | 419 | if (can_write > 512 && !periodic) |
5b7d70c6 BD |
420 | can_write = 512; |
421 | ||
8b9bc460 LM |
422 | /* |
423 | * limit the write to one max-packet size worth of data, but allow | |
03e10e5a | 424 | * the transfer to return that it did not run out of fifo space |
8b9bc460 LM |
425 | * doing it. |
426 | */ | |
4fca54aa RB |
427 | if (to_write > max_transfer) { |
428 | to_write = max_transfer; | |
03e10e5a | 429 | |
5cb2ff0c RB |
430 | /* it's needed only when we do not use dedicated fifos */ |
431 | if (!hsotg->dedicated_fifos) | |
1f91b4cc | 432 | dwc2_hsotg_en_gsint(hsotg, |
47a1685f DN |
433 | periodic ? GINTSTS_PTXFEMP : |
434 | GINTSTS_NPTXFEMP); | |
03e10e5a BD |
435 | } |
436 | ||
5b7d70c6 BD |
437 | /* see if we can write data */ |
438 | ||
439 | if (to_write > can_write) { | |
440 | to_write = can_write; | |
4fca54aa | 441 | pkt_round = to_write % max_transfer; |
5b7d70c6 | 442 | |
8b9bc460 LM |
443 | /* |
444 | * Round the write down to an | |
5b7d70c6 BD |
445 | * exact number of packets. |
446 | * | |
447 | * Note, we do not currently check to see if we can ever | |
448 | * write a full packet or not to the FIFO. | |
449 | */ | |
450 | ||
451 | if (pkt_round) | |
452 | to_write -= pkt_round; | |
453 | ||
8b9bc460 LM |
454 | /* |
455 | * enable correct FIFO interrupt to alert us when there | |
456 | * is more room left. | |
457 | */ | |
5b7d70c6 | 458 | |
5cb2ff0c RB |
459 | /* it's needed only when we do not use dedicated fifos */ |
460 | if (!hsotg->dedicated_fifos) | |
1f91b4cc | 461 | dwc2_hsotg_en_gsint(hsotg, |
47a1685f DN |
462 | periodic ? GINTSTS_PTXFEMP : |
463 | GINTSTS_NPTXFEMP); | |
5b7d70c6 BD |
464 | } |
465 | ||
466 | dev_dbg(hsotg->dev, "write %d/%d, can_write %d, done %d\n", | |
467 | to_write, hs_req->req.length, can_write, buf_pos); | |
468 | ||
469 | if (to_write <= 0) | |
470 | return -ENOSPC; | |
471 | ||
472 | hs_req->req.actual = buf_pos + to_write; | |
473 | hs_ep->total_data += to_write; | |
474 | ||
475 | if (periodic) | |
476 | hs_ep->fifo_load += to_write; | |
477 | ||
478 | to_write = DIV_ROUND_UP(to_write, 4); | |
479 | data = hs_req->req.buf + buf_pos; | |
480 | ||
1a7ed5be | 481 | iowrite32_rep(hsotg->regs + EPFIFO(hs_ep->index), data, to_write); |
5b7d70c6 BD |
482 | |
483 | return (to_write >= can_write) ? -ENOSPC : 0; | |
484 | } | |
485 | ||
486 | /** | |
487 | * get_ep_limit - get the maximum data legnth for this endpoint | |
488 | * @hs_ep: The endpoint | |
489 | * | |
490 | * Return the maximum data that can be queued in one go on a given endpoint | |
491 | * so that transfers that are too long can be split. | |
492 | */ | |
1f91b4cc | 493 | static unsigned get_ep_limit(struct dwc2_hsotg_ep *hs_ep) |
5b7d70c6 BD |
494 | { |
495 | int index = hs_ep->index; | |
496 | unsigned maxsize; | |
497 | unsigned maxpkt; | |
498 | ||
499 | if (index != 0) { | |
47a1685f DN |
500 | maxsize = DXEPTSIZ_XFERSIZE_LIMIT + 1; |
501 | maxpkt = DXEPTSIZ_PKTCNT_LIMIT + 1; | |
5b7d70c6 | 502 | } else { |
b05ca580 | 503 | maxsize = 64+64; |
66e5c643 | 504 | if (hs_ep->dir_in) |
47a1685f | 505 | maxpkt = DIEPTSIZ0_PKTCNT_LIMIT + 1; |
66e5c643 | 506 | else |
5b7d70c6 | 507 | maxpkt = 2; |
5b7d70c6 BD |
508 | } |
509 | ||
510 | /* we made the constant loading easier above by using +1 */ | |
511 | maxpkt--; | |
512 | maxsize--; | |
513 | ||
8b9bc460 LM |
514 | /* |
515 | * constrain by packet count if maxpkts*pktsize is greater | |
516 | * than the length register size. | |
517 | */ | |
5b7d70c6 BD |
518 | |
519 | if ((maxpkt * hs_ep->ep.maxpacket) < maxsize) | |
520 | maxsize = maxpkt * hs_ep->ep.maxpacket; | |
521 | ||
522 | return maxsize; | |
523 | } | |
524 | ||
525 | /** | |
1f91b4cc | 526 | * dwc2_hsotg_start_req - start a USB request from an endpoint's queue |
5b7d70c6 BD |
527 | * @hsotg: The controller state. |
528 | * @hs_ep: The endpoint to process a request for | |
529 | * @hs_req: The request to start. | |
530 | * @continuing: True if we are doing more for the current request. | |
531 | * | |
532 | * Start the given request running by setting the endpoint registers | |
533 | * appropriately, and writing any data to the FIFOs. | |
534 | */ | |
1f91b4cc FB |
535 | static void dwc2_hsotg_start_req(struct dwc2_hsotg *hsotg, |
536 | struct dwc2_hsotg_ep *hs_ep, | |
537 | struct dwc2_hsotg_req *hs_req, | |
5b7d70c6 BD |
538 | bool continuing) |
539 | { | |
540 | struct usb_request *ureq = &hs_req->req; | |
541 | int index = hs_ep->index; | |
542 | int dir_in = hs_ep->dir_in; | |
543 | u32 epctrl_reg; | |
544 | u32 epsize_reg; | |
545 | u32 epsize; | |
546 | u32 ctrl; | |
547 | unsigned length; | |
548 | unsigned packets; | |
549 | unsigned maxreq; | |
550 | ||
551 | if (index != 0) { | |
552 | if (hs_ep->req && !continuing) { | |
553 | dev_err(hsotg->dev, "%s: active request\n", __func__); | |
554 | WARN_ON(1); | |
555 | return; | |
556 | } else if (hs_ep->req != hs_req && continuing) { | |
557 | dev_err(hsotg->dev, | |
558 | "%s: continue different req\n", __func__); | |
559 | WARN_ON(1); | |
560 | return; | |
561 | } | |
562 | } | |
563 | ||
94cb8fd6 LM |
564 | epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index); |
565 | epsize_reg = dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index); | |
5b7d70c6 BD |
566 | |
567 | dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n", | |
95c8bc36 | 568 | __func__, dwc2_readl(hsotg->regs + epctrl_reg), index, |
5b7d70c6 BD |
569 | hs_ep->dir_in ? "in" : "out"); |
570 | ||
9c39ddc6 | 571 | /* If endpoint is stalled, we will restart request later */ |
95c8bc36 | 572 | ctrl = dwc2_readl(hsotg->regs + epctrl_reg); |
9c39ddc6 | 573 | |
b2d4c54e | 574 | if (index && ctrl & DXEPCTL_STALL) { |
9c39ddc6 AT |
575 | dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index); |
576 | return; | |
577 | } | |
578 | ||
5b7d70c6 | 579 | length = ureq->length - ureq->actual; |
71225bee LM |
580 | dev_dbg(hsotg->dev, "ureq->length:%d ureq->actual:%d\n", |
581 | ureq->length, ureq->actual); | |
5b7d70c6 BD |
582 | |
583 | maxreq = get_ep_limit(hs_ep); | |
584 | if (length > maxreq) { | |
585 | int round = maxreq % hs_ep->ep.maxpacket; | |
586 | ||
587 | dev_dbg(hsotg->dev, "%s: length %d, max-req %d, r %d\n", | |
588 | __func__, length, maxreq, round); | |
589 | ||
590 | /* round down to multiple of packets */ | |
591 | if (round) | |
592 | maxreq -= round; | |
593 | ||
594 | length = maxreq; | |
595 | } | |
596 | ||
597 | if (length) | |
598 | packets = DIV_ROUND_UP(length, hs_ep->ep.maxpacket); | |
599 | else | |
600 | packets = 1; /* send one packet if length is zero. */ | |
601 | ||
4fca54aa RB |
602 | if (hs_ep->isochronous && length > (hs_ep->mc * hs_ep->ep.maxpacket)) { |
603 | dev_err(hsotg->dev, "req length > maxpacket*mc\n"); | |
604 | return; | |
605 | } | |
606 | ||
5b7d70c6 | 607 | if (dir_in && index != 0) |
4fca54aa | 608 | if (hs_ep->isochronous) |
47a1685f | 609 | epsize = DXEPTSIZ_MC(packets); |
4fca54aa | 610 | else |
47a1685f | 611 | epsize = DXEPTSIZ_MC(1); |
5b7d70c6 BD |
612 | else |
613 | epsize = 0; | |
614 | ||
f71b5e25 MYK |
615 | /* |
616 | * zero length packet should be programmed on its own and should not | |
617 | * be counted in DIEPTSIZ.PktCnt with other packets. | |
618 | */ | |
619 | if (dir_in && ureq->zero && !continuing) { | |
620 | /* Test if zlp is actually required. */ | |
621 | if ((ureq->length >= hs_ep->ep.maxpacket) && | |
622 | !(ureq->length % hs_ep->ep.maxpacket)) | |
8a20fa45 | 623 | hs_ep->send_zlp = 1; |
5b7d70c6 BD |
624 | } |
625 | ||
47a1685f DN |
626 | epsize |= DXEPTSIZ_PKTCNT(packets); |
627 | epsize |= DXEPTSIZ_XFERSIZE(length); | |
5b7d70c6 BD |
628 | |
629 | dev_dbg(hsotg->dev, "%s: %d@%d/%d, 0x%08x => 0x%08x\n", | |
630 | __func__, packets, length, ureq->length, epsize, epsize_reg); | |
631 | ||
632 | /* store the request as the current one we're doing */ | |
633 | hs_ep->req = hs_req; | |
634 | ||
635 | /* write size / packets */ | |
95c8bc36 | 636 | dwc2_writel(epsize, hsotg->regs + epsize_reg); |
5b7d70c6 | 637 | |
db1d8ba3 | 638 | if (using_dma(hsotg) && !continuing) { |
5b7d70c6 BD |
639 | unsigned int dma_reg; |
640 | ||
8b9bc460 LM |
641 | /* |
642 | * write DMA address to control register, buffer already | |
1f91b4cc | 643 | * synced by dwc2_hsotg_ep_queue(). |
8b9bc460 | 644 | */ |
5b7d70c6 | 645 | |
94cb8fd6 | 646 | dma_reg = dir_in ? DIEPDMA(index) : DOEPDMA(index); |
95c8bc36 | 647 | dwc2_writel(ureq->dma, hsotg->regs + dma_reg); |
5b7d70c6 | 648 | |
0cc4cf6f | 649 | dev_dbg(hsotg->dev, "%s: %pad => 0x%08x\n", |
8b3bc14f | 650 | __func__, &ureq->dma, dma_reg); |
5b7d70c6 BD |
651 | } |
652 | ||
47a1685f | 653 | ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */ |
71225bee | 654 | |
fe0b94ab | 655 | dev_dbg(hsotg->dev, "ep0 state:%d\n", hsotg->ep0_state); |
71225bee LM |
656 | |
657 | /* For Setup request do not clear NAK */ | |
fe0b94ab | 658 | if (!(index == 0 && hsotg->ep0_state == DWC2_EP0_SETUP)) |
47a1685f | 659 | ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */ |
71225bee | 660 | |
5b7d70c6 | 661 | dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl); |
95c8bc36 | 662 | dwc2_writel(ctrl, hsotg->regs + epctrl_reg); |
5b7d70c6 | 663 | |
8b9bc460 LM |
664 | /* |
665 | * set these, it seems that DMA support increments past the end | |
5b7d70c6 | 666 | * of the packet buffer so we need to calculate the length from |
8b9bc460 LM |
667 | * this information. |
668 | */ | |
5b7d70c6 BD |
669 | hs_ep->size_loaded = length; |
670 | hs_ep->last_load = ureq->actual; | |
671 | ||
672 | if (dir_in && !using_dma(hsotg)) { | |
673 | /* set these anyway, we may need them for non-periodic in */ | |
674 | hs_ep->fifo_load = 0; | |
675 | ||
1f91b4cc | 676 | dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req); |
5b7d70c6 BD |
677 | } |
678 | ||
8b9bc460 LM |
679 | /* |
680 | * Note, trying to clear the NAK here causes problems with transmit | |
681 | * on the S3C6400 ending up with the TXFIFO becoming full. | |
682 | */ | |
5b7d70c6 BD |
683 | |
684 | /* check ep is enabled */ | |
95c8bc36 | 685 | if (!(dwc2_readl(hsotg->regs + epctrl_reg) & DXEPCTL_EPENA)) |
1a0ed863 | 686 | dev_dbg(hsotg->dev, |
47a1685f | 687 | "ep%d: failed to become enabled (DXEPCTL=0x%08x)?\n", |
95c8bc36 | 688 | index, dwc2_readl(hsotg->regs + epctrl_reg)); |
5b7d70c6 | 689 | |
47a1685f | 690 | dev_dbg(hsotg->dev, "%s: DXEPCTL=0x%08x\n", |
95c8bc36 | 691 | __func__, dwc2_readl(hsotg->regs + epctrl_reg)); |
afcf4169 RB |
692 | |
693 | /* enable ep interrupts */ | |
1f91b4cc | 694 | dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 1); |
5b7d70c6 BD |
695 | } |
696 | ||
697 | /** | |
1f91b4cc | 698 | * dwc2_hsotg_map_dma - map the DMA memory being used for the request |
5b7d70c6 BD |
699 | * @hsotg: The device state. |
700 | * @hs_ep: The endpoint the request is on. | |
701 | * @req: The request being processed. | |
702 | * | |
703 | * We've been asked to queue a request, so ensure that the memory buffer | |
704 | * is correctly setup for DMA. If we've been passed an extant DMA address | |
705 | * then ensure the buffer has been synced to memory. If our buffer has no | |
706 | * DMA memory, then we map the memory and mark our request to allow us to | |
707 | * cleanup on completion. | |
8b9bc460 | 708 | */ |
1f91b4cc FB |
709 | static int dwc2_hsotg_map_dma(struct dwc2_hsotg *hsotg, |
710 | struct dwc2_hsotg_ep *hs_ep, | |
5b7d70c6 BD |
711 | struct usb_request *req) |
712 | { | |
1f91b4cc | 713 | struct dwc2_hsotg_req *hs_req = our_req(req); |
e58ebcd1 | 714 | int ret; |
5b7d70c6 BD |
715 | |
716 | /* if the length is zero, ignore the DMA data */ | |
717 | if (hs_req->req.length == 0) | |
718 | return 0; | |
719 | ||
e58ebcd1 FB |
720 | ret = usb_gadget_map_request(&hsotg->gadget, req, hs_ep->dir_in); |
721 | if (ret) | |
722 | goto dma_error; | |
5b7d70c6 BD |
723 | |
724 | return 0; | |
725 | ||
726 | dma_error: | |
727 | dev_err(hsotg->dev, "%s: failed to map buffer %p, %d bytes\n", | |
728 | __func__, req->buf, req->length); | |
729 | ||
730 | return -EIO; | |
731 | } | |
732 | ||
1f91b4cc FB |
733 | static int dwc2_hsotg_handle_unaligned_buf_start(struct dwc2_hsotg *hsotg, |
734 | struct dwc2_hsotg_ep *hs_ep, struct dwc2_hsotg_req *hs_req) | |
7d24c1b5 MYK |
735 | { |
736 | void *req_buf = hs_req->req.buf; | |
737 | ||
738 | /* If dma is not being used or buffer is aligned */ | |
739 | if (!using_dma(hsotg) || !((long)req_buf & 3)) | |
740 | return 0; | |
741 | ||
742 | WARN_ON(hs_req->saved_req_buf); | |
743 | ||
744 | dev_dbg(hsotg->dev, "%s: %s: buf=%p length=%d\n", __func__, | |
745 | hs_ep->ep.name, req_buf, hs_req->req.length); | |
746 | ||
747 | hs_req->req.buf = kmalloc(hs_req->req.length, GFP_ATOMIC); | |
748 | if (!hs_req->req.buf) { | |
749 | hs_req->req.buf = req_buf; | |
750 | dev_err(hsotg->dev, | |
751 | "%s: unable to allocate memory for bounce buffer\n", | |
752 | __func__); | |
753 | return -ENOMEM; | |
754 | } | |
755 | ||
756 | /* Save actual buffer */ | |
757 | hs_req->saved_req_buf = req_buf; | |
758 | ||
759 | if (hs_ep->dir_in) | |
760 | memcpy(hs_req->req.buf, req_buf, hs_req->req.length); | |
761 | return 0; | |
762 | } | |
763 | ||
1f91b4cc FB |
764 | static void dwc2_hsotg_handle_unaligned_buf_complete(struct dwc2_hsotg *hsotg, |
765 | struct dwc2_hsotg_ep *hs_ep, struct dwc2_hsotg_req *hs_req) | |
7d24c1b5 MYK |
766 | { |
767 | /* If dma is not being used or buffer was aligned */ | |
768 | if (!using_dma(hsotg) || !hs_req->saved_req_buf) | |
769 | return; | |
770 | ||
771 | dev_dbg(hsotg->dev, "%s: %s: status=%d actual-length=%d\n", __func__, | |
772 | hs_ep->ep.name, hs_req->req.status, hs_req->req.actual); | |
773 | ||
774 | /* Copy data from bounce buffer on successful out transfer */ | |
775 | if (!hs_ep->dir_in && !hs_req->req.status) | |
776 | memcpy(hs_req->saved_req_buf, hs_req->req.buf, | |
777 | hs_req->req.actual); | |
778 | ||
779 | /* Free bounce buffer */ | |
780 | kfree(hs_req->req.buf); | |
781 | ||
782 | hs_req->req.buf = hs_req->saved_req_buf; | |
783 | hs_req->saved_req_buf = NULL; | |
784 | } | |
785 | ||
1f91b4cc | 786 | static int dwc2_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req, |
5b7d70c6 BD |
787 | gfp_t gfp_flags) |
788 | { | |
1f91b4cc FB |
789 | struct dwc2_hsotg_req *hs_req = our_req(req); |
790 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); | |
941fcce4 | 791 | struct dwc2_hsotg *hs = hs_ep->parent; |
5b7d70c6 | 792 | bool first; |
7d24c1b5 | 793 | int ret; |
5b7d70c6 BD |
794 | |
795 | dev_dbg(hs->dev, "%s: req %p: %d@%p, noi=%d, zero=%d, snok=%d\n", | |
796 | ep->name, req, req->length, req->buf, req->no_interrupt, | |
797 | req->zero, req->short_not_ok); | |
798 | ||
7ababa92 GH |
799 | /* Prevent new request submission when controller is suspended */ |
800 | if (hs->lx_state == DWC2_L2) { | |
801 | dev_dbg(hs->dev, "%s: don't submit request while suspended\n", | |
802 | __func__); | |
803 | return -EAGAIN; | |
804 | } | |
805 | ||
5b7d70c6 BD |
806 | /* initialise status of the request */ |
807 | INIT_LIST_HEAD(&hs_req->queue); | |
808 | req->actual = 0; | |
809 | req->status = -EINPROGRESS; | |
810 | ||
1f91b4cc | 811 | ret = dwc2_hsotg_handle_unaligned_buf_start(hs, hs_ep, hs_req); |
7d24c1b5 MYK |
812 | if (ret) |
813 | return ret; | |
814 | ||
5b7d70c6 BD |
815 | /* if we're using DMA, sync the buffers as necessary */ |
816 | if (using_dma(hs)) { | |
1f91b4cc | 817 | ret = dwc2_hsotg_map_dma(hs, hs_ep, req); |
5b7d70c6 BD |
818 | if (ret) |
819 | return ret; | |
820 | } | |
821 | ||
5b7d70c6 BD |
822 | first = list_empty(&hs_ep->queue); |
823 | list_add_tail(&hs_req->queue, &hs_ep->queue); | |
824 | ||
825 | if (first) | |
1f91b4cc | 826 | dwc2_hsotg_start_req(hs, hs_ep, hs_req, false); |
5b7d70c6 | 827 | |
5b7d70c6 BD |
828 | return 0; |
829 | } | |
830 | ||
1f91b4cc | 831 | static int dwc2_hsotg_ep_queue_lock(struct usb_ep *ep, struct usb_request *req, |
5ad1d316 LM |
832 | gfp_t gfp_flags) |
833 | { | |
1f91b4cc | 834 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 835 | struct dwc2_hsotg *hs = hs_ep->parent; |
5ad1d316 LM |
836 | unsigned long flags = 0; |
837 | int ret = 0; | |
838 | ||
839 | spin_lock_irqsave(&hs->lock, flags); | |
1f91b4cc | 840 | ret = dwc2_hsotg_ep_queue(ep, req, gfp_flags); |
5ad1d316 LM |
841 | spin_unlock_irqrestore(&hs->lock, flags); |
842 | ||
843 | return ret; | |
844 | } | |
845 | ||
1f91b4cc | 846 | static void dwc2_hsotg_ep_free_request(struct usb_ep *ep, |
5b7d70c6 BD |
847 | struct usb_request *req) |
848 | { | |
1f91b4cc | 849 | struct dwc2_hsotg_req *hs_req = our_req(req); |
5b7d70c6 BD |
850 | |
851 | kfree(hs_req); | |
852 | } | |
853 | ||
854 | /** | |
1f91b4cc | 855 | * dwc2_hsotg_complete_oursetup - setup completion callback |
5b7d70c6 BD |
856 | * @ep: The endpoint the request was on. |
857 | * @req: The request completed. | |
858 | * | |
859 | * Called on completion of any requests the driver itself | |
860 | * submitted that need cleaning up. | |
861 | */ | |
1f91b4cc | 862 | static void dwc2_hsotg_complete_oursetup(struct usb_ep *ep, |
5b7d70c6 BD |
863 | struct usb_request *req) |
864 | { | |
1f91b4cc | 865 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 866 | struct dwc2_hsotg *hsotg = hs_ep->parent; |
5b7d70c6 BD |
867 | |
868 | dev_dbg(hsotg->dev, "%s: ep %p, req %p\n", __func__, ep, req); | |
869 | ||
1f91b4cc | 870 | dwc2_hsotg_ep_free_request(ep, req); |
5b7d70c6 BD |
871 | } |
872 | ||
873 | /** | |
874 | * ep_from_windex - convert control wIndex value to endpoint | |
875 | * @hsotg: The driver state. | |
876 | * @windex: The control request wIndex field (in host order). | |
877 | * | |
878 | * Convert the given wIndex into a pointer to an driver endpoint | |
879 | * structure, or return NULL if it is not a valid endpoint. | |
8b9bc460 | 880 | */ |
1f91b4cc | 881 | static struct dwc2_hsotg_ep *ep_from_windex(struct dwc2_hsotg *hsotg, |
5b7d70c6 BD |
882 | u32 windex) |
883 | { | |
1f91b4cc | 884 | struct dwc2_hsotg_ep *ep; |
5b7d70c6 BD |
885 | int dir = (windex & USB_DIR_IN) ? 1 : 0; |
886 | int idx = windex & 0x7F; | |
887 | ||
888 | if (windex >= 0x100) | |
889 | return NULL; | |
890 | ||
b3f489b2 | 891 | if (idx > hsotg->num_of_eps) |
5b7d70c6 BD |
892 | return NULL; |
893 | ||
c6f5c050 MYK |
894 | ep = index_to_ep(hsotg, idx, dir); |
895 | ||
5b7d70c6 BD |
896 | if (idx && ep->dir_in != dir) |
897 | return NULL; | |
898 | ||
899 | return ep; | |
900 | } | |
901 | ||
9e14d0a5 | 902 | /** |
1f91b4cc | 903 | * dwc2_hsotg_set_test_mode - Enable usb Test Modes |
9e14d0a5 GH |
904 | * @hsotg: The driver state. |
905 | * @testmode: requested usb test mode | |
906 | * Enable usb Test Mode requested by the Host. | |
907 | */ | |
1f91b4cc | 908 | int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode) |
9e14d0a5 | 909 | { |
95c8bc36 | 910 | int dctl = dwc2_readl(hsotg->regs + DCTL); |
9e14d0a5 GH |
911 | |
912 | dctl &= ~DCTL_TSTCTL_MASK; | |
913 | switch (testmode) { | |
914 | case TEST_J: | |
915 | case TEST_K: | |
916 | case TEST_SE0_NAK: | |
917 | case TEST_PACKET: | |
918 | case TEST_FORCE_EN: | |
919 | dctl |= testmode << DCTL_TSTCTL_SHIFT; | |
920 | break; | |
921 | default: | |
922 | return -EINVAL; | |
923 | } | |
95c8bc36 | 924 | dwc2_writel(dctl, hsotg->regs + DCTL); |
9e14d0a5 GH |
925 | return 0; |
926 | } | |
927 | ||
5b7d70c6 | 928 | /** |
1f91b4cc | 929 | * dwc2_hsotg_send_reply - send reply to control request |
5b7d70c6 BD |
930 | * @hsotg: The device state |
931 | * @ep: Endpoint 0 | |
932 | * @buff: Buffer for request | |
933 | * @length: Length of reply. | |
934 | * | |
935 | * Create a request and queue it on the given endpoint. This is useful as | |
936 | * an internal method of sending replies to certain control requests, etc. | |
937 | */ | |
1f91b4cc FB |
938 | static int dwc2_hsotg_send_reply(struct dwc2_hsotg *hsotg, |
939 | struct dwc2_hsotg_ep *ep, | |
5b7d70c6 BD |
940 | void *buff, |
941 | int length) | |
942 | { | |
943 | struct usb_request *req; | |
944 | int ret; | |
945 | ||
946 | dev_dbg(hsotg->dev, "%s: buff %p, len %d\n", __func__, buff, length); | |
947 | ||
1f91b4cc | 948 | req = dwc2_hsotg_ep_alloc_request(&ep->ep, GFP_ATOMIC); |
5b7d70c6 BD |
949 | hsotg->ep0_reply = req; |
950 | if (!req) { | |
951 | dev_warn(hsotg->dev, "%s: cannot alloc req\n", __func__); | |
952 | return -ENOMEM; | |
953 | } | |
954 | ||
955 | req->buf = hsotg->ep0_buff; | |
956 | req->length = length; | |
f71b5e25 MYK |
957 | /* |
958 | * zero flag is for sending zlp in DATA IN stage. It has no impact on | |
959 | * STATUS stage. | |
960 | */ | |
961 | req->zero = 0; | |
1f91b4cc | 962 | req->complete = dwc2_hsotg_complete_oursetup; |
5b7d70c6 BD |
963 | |
964 | if (length) | |
965 | memcpy(req->buf, buff, length); | |
5b7d70c6 | 966 | |
1f91b4cc | 967 | ret = dwc2_hsotg_ep_queue(&ep->ep, req, GFP_ATOMIC); |
5b7d70c6 BD |
968 | if (ret) { |
969 | dev_warn(hsotg->dev, "%s: cannot queue req\n", __func__); | |
970 | return ret; | |
971 | } | |
972 | ||
973 | return 0; | |
974 | } | |
975 | ||
976 | /** | |
1f91b4cc | 977 | * dwc2_hsotg_process_req_status - process request GET_STATUS |
5b7d70c6 BD |
978 | * @hsotg: The device state |
979 | * @ctrl: USB control request | |
980 | */ | |
1f91b4cc | 981 | static int dwc2_hsotg_process_req_status(struct dwc2_hsotg *hsotg, |
5b7d70c6 BD |
982 | struct usb_ctrlrequest *ctrl) |
983 | { | |
1f91b4cc FB |
984 | struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0]; |
985 | struct dwc2_hsotg_ep *ep; | |
5b7d70c6 BD |
986 | __le16 reply; |
987 | int ret; | |
988 | ||
989 | dev_dbg(hsotg->dev, "%s: USB_REQ_GET_STATUS\n", __func__); | |
990 | ||
991 | if (!ep0->dir_in) { | |
992 | dev_warn(hsotg->dev, "%s: direction out?\n", __func__); | |
993 | return -EINVAL; | |
994 | } | |
995 | ||
996 | switch (ctrl->bRequestType & USB_RECIP_MASK) { | |
997 | case USB_RECIP_DEVICE: | |
998 | reply = cpu_to_le16(0); /* bit 0 => self powered, | |
999 | * bit 1 => remote wakeup */ | |
1000 | break; | |
1001 | ||
1002 | case USB_RECIP_INTERFACE: | |
1003 | /* currently, the data result should be zero */ | |
1004 | reply = cpu_to_le16(0); | |
1005 | break; | |
1006 | ||
1007 | case USB_RECIP_ENDPOINT: | |
1008 | ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex)); | |
1009 | if (!ep) | |
1010 | return -ENOENT; | |
1011 | ||
1012 | reply = cpu_to_le16(ep->halted ? 1 : 0); | |
1013 | break; | |
1014 | ||
1015 | default: | |
1016 | return 0; | |
1017 | } | |
1018 | ||
1019 | if (le16_to_cpu(ctrl->wLength) != 2) | |
1020 | return -EINVAL; | |
1021 | ||
1f91b4cc | 1022 | ret = dwc2_hsotg_send_reply(hsotg, ep0, &reply, 2); |
5b7d70c6 BD |
1023 | if (ret) { |
1024 | dev_err(hsotg->dev, "%s: failed to send reply\n", __func__); | |
1025 | return ret; | |
1026 | } | |
1027 | ||
1028 | return 1; | |
1029 | } | |
1030 | ||
51da43b5 | 1031 | static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now); |
5b7d70c6 | 1032 | |
9c39ddc6 AT |
1033 | /** |
1034 | * get_ep_head - return the first request on the endpoint | |
1035 | * @hs_ep: The controller endpoint to get | |
1036 | * | |
1037 | * Get the first request on the endpoint. | |
1038 | */ | |
1f91b4cc | 1039 | static struct dwc2_hsotg_req *get_ep_head(struct dwc2_hsotg_ep *hs_ep) |
9c39ddc6 AT |
1040 | { |
1041 | if (list_empty(&hs_ep->queue)) | |
1042 | return NULL; | |
1043 | ||
1f91b4cc | 1044 | return list_first_entry(&hs_ep->queue, struct dwc2_hsotg_req, queue); |
9c39ddc6 AT |
1045 | } |
1046 | ||
41cc4cd2 VM |
1047 | /** |
1048 | * dwc2_gadget_start_next_request - Starts next request from ep queue | |
1049 | * @hs_ep: Endpoint structure | |
1050 | * | |
1051 | * If queue is empty and EP is ISOC-OUT - unmasks OUTTKNEPDIS which is masked | |
1052 | * in its handler. Hence we need to unmask it here to be able to do | |
1053 | * resynchronization. | |
1054 | */ | |
1055 | static void dwc2_gadget_start_next_request(struct dwc2_hsotg_ep *hs_ep) | |
1056 | { | |
1057 | u32 mask; | |
1058 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
1059 | int dir_in = hs_ep->dir_in; | |
1060 | struct dwc2_hsotg_req *hs_req; | |
1061 | u32 epmsk_reg = dir_in ? DIEPMSK : DOEPMSK; | |
1062 | ||
1063 | if (!list_empty(&hs_ep->queue)) { | |
1064 | hs_req = get_ep_head(hs_ep); | |
1065 | dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, false); | |
1066 | return; | |
1067 | } | |
1068 | if (!hs_ep->isochronous) | |
1069 | return; | |
1070 | ||
1071 | if (dir_in) { | |
1072 | dev_dbg(hsotg->dev, "%s: No more ISOC-IN requests\n", | |
1073 | __func__); | |
1074 | } else { | |
1075 | dev_dbg(hsotg->dev, "%s: No more ISOC-OUT requests\n", | |
1076 | __func__); | |
1077 | mask = dwc2_readl(hsotg->regs + epmsk_reg); | |
1078 | mask |= DOEPMSK_OUTTKNEPDISMSK; | |
1079 | dwc2_writel(mask, hsotg->regs + epmsk_reg); | |
1080 | } | |
1081 | } | |
1082 | ||
5b7d70c6 | 1083 | /** |
1f91b4cc | 1084 | * dwc2_hsotg_process_req_feature - process request {SET,CLEAR}_FEATURE |
5b7d70c6 BD |
1085 | * @hsotg: The device state |
1086 | * @ctrl: USB control request | |
1087 | */ | |
1f91b4cc | 1088 | static int dwc2_hsotg_process_req_feature(struct dwc2_hsotg *hsotg, |
5b7d70c6 BD |
1089 | struct usb_ctrlrequest *ctrl) |
1090 | { | |
1f91b4cc FB |
1091 | struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0]; |
1092 | struct dwc2_hsotg_req *hs_req; | |
5b7d70c6 | 1093 | bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE); |
1f91b4cc | 1094 | struct dwc2_hsotg_ep *ep; |
26ab3d0c | 1095 | int ret; |
bd9ef7bf | 1096 | bool halted; |
9e14d0a5 GH |
1097 | u32 recip; |
1098 | u32 wValue; | |
1099 | u32 wIndex; | |
5b7d70c6 BD |
1100 | |
1101 | dev_dbg(hsotg->dev, "%s: %s_FEATURE\n", | |
1102 | __func__, set ? "SET" : "CLEAR"); | |
1103 | ||
9e14d0a5 GH |
1104 | wValue = le16_to_cpu(ctrl->wValue); |
1105 | wIndex = le16_to_cpu(ctrl->wIndex); | |
1106 | recip = ctrl->bRequestType & USB_RECIP_MASK; | |
1107 | ||
1108 | switch (recip) { | |
1109 | case USB_RECIP_DEVICE: | |
1110 | switch (wValue) { | |
1111 | case USB_DEVICE_TEST_MODE: | |
1112 | if ((wIndex & 0xff) != 0) | |
1113 | return -EINVAL; | |
1114 | if (!set) | |
1115 | return -EINVAL; | |
1116 | ||
1117 | hsotg->test_mode = wIndex >> 8; | |
1f91b4cc | 1118 | ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0); |
9e14d0a5 GH |
1119 | if (ret) { |
1120 | dev_err(hsotg->dev, | |
1121 | "%s: failed to send reply\n", __func__); | |
1122 | return ret; | |
1123 | } | |
1124 | break; | |
1125 | default: | |
1126 | return -ENOENT; | |
1127 | } | |
1128 | break; | |
1129 | ||
1130 | case USB_RECIP_ENDPOINT: | |
1131 | ep = ep_from_windex(hsotg, wIndex); | |
5b7d70c6 BD |
1132 | if (!ep) { |
1133 | dev_dbg(hsotg->dev, "%s: no endpoint for 0x%04x\n", | |
9e14d0a5 | 1134 | __func__, wIndex); |
5b7d70c6 BD |
1135 | return -ENOENT; |
1136 | } | |
1137 | ||
9e14d0a5 | 1138 | switch (wValue) { |
5b7d70c6 | 1139 | case USB_ENDPOINT_HALT: |
bd9ef7bf RB |
1140 | halted = ep->halted; |
1141 | ||
51da43b5 | 1142 | dwc2_hsotg_ep_sethalt(&ep->ep, set, true); |
26ab3d0c | 1143 | |
1f91b4cc | 1144 | ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0); |
26ab3d0c AT |
1145 | if (ret) { |
1146 | dev_err(hsotg->dev, | |
1147 | "%s: failed to send reply\n", __func__); | |
1148 | return ret; | |
1149 | } | |
9c39ddc6 | 1150 | |
bd9ef7bf RB |
1151 | /* |
1152 | * we have to complete all requests for ep if it was | |
1153 | * halted, and the halt was cleared by CLEAR_FEATURE | |
1154 | */ | |
1155 | ||
1156 | if (!set && halted) { | |
9c39ddc6 AT |
1157 | /* |
1158 | * If we have request in progress, | |
1159 | * then complete it | |
1160 | */ | |
1161 | if (ep->req) { | |
1162 | hs_req = ep->req; | |
1163 | ep->req = NULL; | |
1164 | list_del_init(&hs_req->queue); | |
c00dd4a6 GH |
1165 | if (hs_req->req.complete) { |
1166 | spin_unlock(&hsotg->lock); | |
1167 | usb_gadget_giveback_request( | |
1168 | &ep->ep, &hs_req->req); | |
1169 | spin_lock(&hsotg->lock); | |
1170 | } | |
9c39ddc6 AT |
1171 | } |
1172 | ||
1173 | /* If we have pending request, then start it */ | |
c00dd4a6 | 1174 | if (!ep->req) { |
41cc4cd2 | 1175 | dwc2_gadget_start_next_request(ep); |
9c39ddc6 AT |
1176 | } |
1177 | } | |
1178 | ||
5b7d70c6 BD |
1179 | break; |
1180 | ||
1181 | default: | |
1182 | return -ENOENT; | |
1183 | } | |
9e14d0a5 GH |
1184 | break; |
1185 | default: | |
1186 | return -ENOENT; | |
1187 | } | |
5b7d70c6 BD |
1188 | return 1; |
1189 | } | |
1190 | ||
1f91b4cc | 1191 | static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg); |
ab93e014 | 1192 | |
c9f721b2 | 1193 | /** |
1f91b4cc | 1194 | * dwc2_hsotg_stall_ep0 - stall ep0 |
c9f721b2 RB |
1195 | * @hsotg: The device state |
1196 | * | |
1197 | * Set stall for ep0 as response for setup request. | |
1198 | */ | |
1f91b4cc | 1199 | static void dwc2_hsotg_stall_ep0(struct dwc2_hsotg *hsotg) |
e9ebe7c3 | 1200 | { |
1f91b4cc | 1201 | struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0]; |
c9f721b2 RB |
1202 | u32 reg; |
1203 | u32 ctrl; | |
1204 | ||
1205 | dev_dbg(hsotg->dev, "ep0 stall (dir=%d)\n", ep0->dir_in); | |
1206 | reg = (ep0->dir_in) ? DIEPCTL0 : DOEPCTL0; | |
1207 | ||
1208 | /* | |
1209 | * DxEPCTL_Stall will be cleared by EP once it has | |
1210 | * taken effect, so no need to clear later. | |
1211 | */ | |
1212 | ||
95c8bc36 | 1213 | ctrl = dwc2_readl(hsotg->regs + reg); |
47a1685f DN |
1214 | ctrl |= DXEPCTL_STALL; |
1215 | ctrl |= DXEPCTL_CNAK; | |
95c8bc36 | 1216 | dwc2_writel(ctrl, hsotg->regs + reg); |
c9f721b2 RB |
1217 | |
1218 | dev_dbg(hsotg->dev, | |
47a1685f | 1219 | "written DXEPCTL=0x%08x to %08x (DXEPCTL=0x%08x)\n", |
95c8bc36 | 1220 | ctrl, reg, dwc2_readl(hsotg->regs + reg)); |
c9f721b2 RB |
1221 | |
1222 | /* | |
1223 | * complete won't be called, so we enqueue | |
1224 | * setup request here | |
1225 | */ | |
1f91b4cc | 1226 | dwc2_hsotg_enqueue_setup(hsotg); |
c9f721b2 RB |
1227 | } |
1228 | ||
5b7d70c6 | 1229 | /** |
1f91b4cc | 1230 | * dwc2_hsotg_process_control - process a control request |
5b7d70c6 BD |
1231 | * @hsotg: The device state |
1232 | * @ctrl: The control request received | |
1233 | * | |
1234 | * The controller has received the SETUP phase of a control request, and | |
1235 | * needs to work out what to do next (and whether to pass it on to the | |
1236 | * gadget driver). | |
1237 | */ | |
1f91b4cc | 1238 | static void dwc2_hsotg_process_control(struct dwc2_hsotg *hsotg, |
5b7d70c6 BD |
1239 | struct usb_ctrlrequest *ctrl) |
1240 | { | |
1f91b4cc | 1241 | struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0]; |
5b7d70c6 BD |
1242 | int ret = 0; |
1243 | u32 dcfg; | |
1244 | ||
e525e743 MYK |
1245 | dev_dbg(hsotg->dev, |
1246 | "ctrl Type=%02x, Req=%02x, V=%04x, I=%04x, L=%04x\n", | |
1247 | ctrl->bRequestType, ctrl->bRequest, ctrl->wValue, | |
1248 | ctrl->wIndex, ctrl->wLength); | |
5b7d70c6 | 1249 | |
fe0b94ab MYK |
1250 | if (ctrl->wLength == 0) { |
1251 | ep0->dir_in = 1; | |
1252 | hsotg->ep0_state = DWC2_EP0_STATUS_IN; | |
1253 | } else if (ctrl->bRequestType & USB_DIR_IN) { | |
5b7d70c6 | 1254 | ep0->dir_in = 1; |
fe0b94ab MYK |
1255 | hsotg->ep0_state = DWC2_EP0_DATA_IN; |
1256 | } else { | |
1257 | ep0->dir_in = 0; | |
1258 | hsotg->ep0_state = DWC2_EP0_DATA_OUT; | |
1259 | } | |
5b7d70c6 BD |
1260 | |
1261 | if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) { | |
1262 | switch (ctrl->bRequest) { | |
1263 | case USB_REQ_SET_ADDRESS: | |
6d713c15 | 1264 | hsotg->connected = 1; |
95c8bc36 | 1265 | dcfg = dwc2_readl(hsotg->regs + DCFG); |
47a1685f | 1266 | dcfg &= ~DCFG_DEVADDR_MASK; |
d5dbd3f7 PZ |
1267 | dcfg |= (le16_to_cpu(ctrl->wValue) << |
1268 | DCFG_DEVADDR_SHIFT) & DCFG_DEVADDR_MASK; | |
95c8bc36 | 1269 | dwc2_writel(dcfg, hsotg->regs + DCFG); |
5b7d70c6 BD |
1270 | |
1271 | dev_info(hsotg->dev, "new address %d\n", ctrl->wValue); | |
1272 | ||
1f91b4cc | 1273 | ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0); |
5b7d70c6 BD |
1274 | return; |
1275 | ||
1276 | case USB_REQ_GET_STATUS: | |
1f91b4cc | 1277 | ret = dwc2_hsotg_process_req_status(hsotg, ctrl); |
5b7d70c6 BD |
1278 | break; |
1279 | ||
1280 | case USB_REQ_CLEAR_FEATURE: | |
1281 | case USB_REQ_SET_FEATURE: | |
1f91b4cc | 1282 | ret = dwc2_hsotg_process_req_feature(hsotg, ctrl); |
5b7d70c6 BD |
1283 | break; |
1284 | } | |
1285 | } | |
1286 | ||
1287 | /* as a fallback, try delivering it to the driver to deal with */ | |
1288 | ||
1289 | if (ret == 0 && hsotg->driver) { | |
93f599f2 | 1290 | spin_unlock(&hsotg->lock); |
5b7d70c6 | 1291 | ret = hsotg->driver->setup(&hsotg->gadget, ctrl); |
93f599f2 | 1292 | spin_lock(&hsotg->lock); |
5b7d70c6 BD |
1293 | if (ret < 0) |
1294 | dev_dbg(hsotg->dev, "driver->setup() ret %d\n", ret); | |
1295 | } | |
1296 | ||
8b9bc460 LM |
1297 | /* |
1298 | * the request is either unhandlable, or is not formatted correctly | |
5b7d70c6 BD |
1299 | * so respond with a STALL for the status stage to indicate failure. |
1300 | */ | |
1301 | ||
c9f721b2 | 1302 | if (ret < 0) |
1f91b4cc | 1303 | dwc2_hsotg_stall_ep0(hsotg); |
5b7d70c6 BD |
1304 | } |
1305 | ||
5b7d70c6 | 1306 | /** |
1f91b4cc | 1307 | * dwc2_hsotg_complete_setup - completion of a setup transfer |
5b7d70c6 BD |
1308 | * @ep: The endpoint the request was on. |
1309 | * @req: The request completed. | |
1310 | * | |
1311 | * Called on completion of any requests the driver itself submitted for | |
1312 | * EP0 setup packets | |
1313 | */ | |
1f91b4cc | 1314 | static void dwc2_hsotg_complete_setup(struct usb_ep *ep, |
5b7d70c6 BD |
1315 | struct usb_request *req) |
1316 | { | |
1f91b4cc | 1317 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 1318 | struct dwc2_hsotg *hsotg = hs_ep->parent; |
5b7d70c6 BD |
1319 | |
1320 | if (req->status < 0) { | |
1321 | dev_dbg(hsotg->dev, "%s: failed %d\n", __func__, req->status); | |
1322 | return; | |
1323 | } | |
1324 | ||
93f599f2 | 1325 | spin_lock(&hsotg->lock); |
5b7d70c6 | 1326 | if (req->actual == 0) |
1f91b4cc | 1327 | dwc2_hsotg_enqueue_setup(hsotg); |
5b7d70c6 | 1328 | else |
1f91b4cc | 1329 | dwc2_hsotg_process_control(hsotg, req->buf); |
93f599f2 | 1330 | spin_unlock(&hsotg->lock); |
5b7d70c6 BD |
1331 | } |
1332 | ||
1333 | /** | |
1f91b4cc | 1334 | * dwc2_hsotg_enqueue_setup - start a request for EP0 packets |
5b7d70c6 BD |
1335 | * @hsotg: The device state. |
1336 | * | |
1337 | * Enqueue a request on EP0 if necessary to received any SETUP packets | |
1338 | * received from the host. | |
1339 | */ | |
1f91b4cc | 1340 | static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg) |
5b7d70c6 BD |
1341 | { |
1342 | struct usb_request *req = hsotg->ctrl_req; | |
1f91b4cc | 1343 | struct dwc2_hsotg_req *hs_req = our_req(req); |
5b7d70c6 BD |
1344 | int ret; |
1345 | ||
1346 | dev_dbg(hsotg->dev, "%s: queueing setup request\n", __func__); | |
1347 | ||
1348 | req->zero = 0; | |
1349 | req->length = 8; | |
1350 | req->buf = hsotg->ctrl_buff; | |
1f91b4cc | 1351 | req->complete = dwc2_hsotg_complete_setup; |
5b7d70c6 BD |
1352 | |
1353 | if (!list_empty(&hs_req->queue)) { | |
1354 | dev_dbg(hsotg->dev, "%s already queued???\n", __func__); | |
1355 | return; | |
1356 | } | |
1357 | ||
c6f5c050 | 1358 | hsotg->eps_out[0]->dir_in = 0; |
8a20fa45 | 1359 | hsotg->eps_out[0]->send_zlp = 0; |
fe0b94ab | 1360 | hsotg->ep0_state = DWC2_EP0_SETUP; |
5b7d70c6 | 1361 | |
1f91b4cc | 1362 | ret = dwc2_hsotg_ep_queue(&hsotg->eps_out[0]->ep, req, GFP_ATOMIC); |
5b7d70c6 BD |
1363 | if (ret < 0) { |
1364 | dev_err(hsotg->dev, "%s: failed queue (%d)\n", __func__, ret); | |
8b9bc460 LM |
1365 | /* |
1366 | * Don't think there's much we can do other than watch the | |
1367 | * driver fail. | |
1368 | */ | |
5b7d70c6 BD |
1369 | } |
1370 | } | |
1371 | ||
1f91b4cc FB |
1372 | static void dwc2_hsotg_program_zlp(struct dwc2_hsotg *hsotg, |
1373 | struct dwc2_hsotg_ep *hs_ep) | |
fe0b94ab MYK |
1374 | { |
1375 | u32 ctrl; | |
1376 | u8 index = hs_ep->index; | |
1377 | u32 epctl_reg = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index); | |
1378 | u32 epsiz_reg = hs_ep->dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index); | |
1379 | ||
ccb34a91 MYK |
1380 | if (hs_ep->dir_in) |
1381 | dev_dbg(hsotg->dev, "Sending zero-length packet on ep%d\n", | |
1382 | index); | |
1383 | else | |
1384 | dev_dbg(hsotg->dev, "Receiving zero-length packet on ep%d\n", | |
1385 | index); | |
fe0b94ab | 1386 | |
95c8bc36 AS |
1387 | dwc2_writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) | |
1388 | DXEPTSIZ_XFERSIZE(0), hsotg->regs + | |
1389 | epsiz_reg); | |
fe0b94ab | 1390 | |
95c8bc36 | 1391 | ctrl = dwc2_readl(hsotg->regs + epctl_reg); |
fe0b94ab MYK |
1392 | ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */ |
1393 | ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */ | |
1394 | ctrl |= DXEPCTL_USBACTEP; | |
95c8bc36 | 1395 | dwc2_writel(ctrl, hsotg->regs + epctl_reg); |
fe0b94ab MYK |
1396 | } |
1397 | ||
5b7d70c6 | 1398 | /** |
1f91b4cc | 1399 | * dwc2_hsotg_complete_request - complete a request given to us |
5b7d70c6 BD |
1400 | * @hsotg: The device state. |
1401 | * @hs_ep: The endpoint the request was on. | |
1402 | * @hs_req: The request to complete. | |
1403 | * @result: The result code (0 => Ok, otherwise errno) | |
1404 | * | |
1405 | * The given request has finished, so call the necessary completion | |
1406 | * if it has one and then look to see if we can start a new request | |
1407 | * on the endpoint. | |
1408 | * | |
1409 | * Note, expects the ep to already be locked as appropriate. | |
8b9bc460 | 1410 | */ |
1f91b4cc FB |
1411 | static void dwc2_hsotg_complete_request(struct dwc2_hsotg *hsotg, |
1412 | struct dwc2_hsotg_ep *hs_ep, | |
1413 | struct dwc2_hsotg_req *hs_req, | |
5b7d70c6 BD |
1414 | int result) |
1415 | { | |
5b7d70c6 BD |
1416 | |
1417 | if (!hs_req) { | |
1418 | dev_dbg(hsotg->dev, "%s: nothing to complete?\n", __func__); | |
1419 | return; | |
1420 | } | |
1421 | ||
1422 | dev_dbg(hsotg->dev, "complete: ep %p %s, req %p, %d => %p\n", | |
1423 | hs_ep, hs_ep->ep.name, hs_req, result, hs_req->req.complete); | |
1424 | ||
8b9bc460 LM |
1425 | /* |
1426 | * only replace the status if we've not already set an error | |
1427 | * from a previous transaction | |
1428 | */ | |
5b7d70c6 BD |
1429 | |
1430 | if (hs_req->req.status == -EINPROGRESS) | |
1431 | hs_req->req.status = result; | |
1432 | ||
44583fec YL |
1433 | if (using_dma(hsotg)) |
1434 | dwc2_hsotg_unmap_dma(hsotg, hs_ep, hs_req); | |
1435 | ||
1f91b4cc | 1436 | dwc2_hsotg_handle_unaligned_buf_complete(hsotg, hs_ep, hs_req); |
7d24c1b5 | 1437 | |
5b7d70c6 BD |
1438 | hs_ep->req = NULL; |
1439 | list_del_init(&hs_req->queue); | |
1440 | ||
8b9bc460 LM |
1441 | /* |
1442 | * call the complete request with the locks off, just in case the | |
1443 | * request tries to queue more work for this endpoint. | |
1444 | */ | |
5b7d70c6 BD |
1445 | |
1446 | if (hs_req->req.complete) { | |
22258f49 | 1447 | spin_unlock(&hsotg->lock); |
304f7e5e | 1448 | usb_gadget_giveback_request(&hs_ep->ep, &hs_req->req); |
22258f49 | 1449 | spin_lock(&hsotg->lock); |
5b7d70c6 BD |
1450 | } |
1451 | ||
8b9bc460 LM |
1452 | /* |
1453 | * Look to see if there is anything else to do. Note, the completion | |
5b7d70c6 | 1454 | * of the previous request may have caused a new request to be started |
8b9bc460 LM |
1455 | * so be careful when doing this. |
1456 | */ | |
5b7d70c6 BD |
1457 | |
1458 | if (!hs_ep->req && result >= 0) { | |
41cc4cd2 | 1459 | dwc2_gadget_start_next_request(hs_ep); |
5b7d70c6 BD |
1460 | } |
1461 | } | |
1462 | ||
5b7d70c6 | 1463 | /** |
1f91b4cc | 1464 | * dwc2_hsotg_rx_data - receive data from the FIFO for an endpoint |
5b7d70c6 BD |
1465 | * @hsotg: The device state. |
1466 | * @ep_idx: The endpoint index for the data | |
1467 | * @size: The size of data in the fifo, in bytes | |
1468 | * | |
1469 | * The FIFO status shows there is data to read from the FIFO for a given | |
1470 | * endpoint, so sort out whether we need to read the data into a request | |
1471 | * that has been made for that endpoint. | |
1472 | */ | |
1f91b4cc | 1473 | static void dwc2_hsotg_rx_data(struct dwc2_hsotg *hsotg, int ep_idx, int size) |
5b7d70c6 | 1474 | { |
1f91b4cc FB |
1475 | struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[ep_idx]; |
1476 | struct dwc2_hsotg_req *hs_req = hs_ep->req; | |
94cb8fd6 | 1477 | void __iomem *fifo = hsotg->regs + EPFIFO(ep_idx); |
5b7d70c6 BD |
1478 | int to_read; |
1479 | int max_req; | |
1480 | int read_ptr; | |
1481 | ||
22258f49 | 1482 | |
5b7d70c6 | 1483 | if (!hs_req) { |
95c8bc36 | 1484 | u32 epctl = dwc2_readl(hsotg->regs + DOEPCTL(ep_idx)); |
5b7d70c6 BD |
1485 | int ptr; |
1486 | ||
6b448af4 | 1487 | dev_dbg(hsotg->dev, |
47a1685f | 1488 | "%s: FIFO %d bytes on ep%d but no req (DXEPCTl=0x%08x)\n", |
5b7d70c6 BD |
1489 | __func__, size, ep_idx, epctl); |
1490 | ||
1491 | /* dump the data from the FIFO, we've nothing we can do */ | |
1492 | for (ptr = 0; ptr < size; ptr += 4) | |
95c8bc36 | 1493 | (void)dwc2_readl(fifo); |
5b7d70c6 BD |
1494 | |
1495 | return; | |
1496 | } | |
1497 | ||
5b7d70c6 BD |
1498 | to_read = size; |
1499 | read_ptr = hs_req->req.actual; | |
1500 | max_req = hs_req->req.length - read_ptr; | |
1501 | ||
a33e7136 BD |
1502 | dev_dbg(hsotg->dev, "%s: read %d/%d, done %d/%d\n", |
1503 | __func__, to_read, max_req, read_ptr, hs_req->req.length); | |
1504 | ||
5b7d70c6 | 1505 | if (to_read > max_req) { |
8b9bc460 LM |
1506 | /* |
1507 | * more data appeared than we where willing | |
5b7d70c6 BD |
1508 | * to deal with in this request. |
1509 | */ | |
1510 | ||
1511 | /* currently we don't deal this */ | |
1512 | WARN_ON_ONCE(1); | |
1513 | } | |
1514 | ||
5b7d70c6 BD |
1515 | hs_ep->total_data += to_read; |
1516 | hs_req->req.actual += to_read; | |
1517 | to_read = DIV_ROUND_UP(to_read, 4); | |
1518 | ||
8b9bc460 LM |
1519 | /* |
1520 | * note, we might over-write the buffer end by 3 bytes depending on | |
1521 | * alignment of the data. | |
1522 | */ | |
1a7ed5be | 1523 | ioread32_rep(fifo, hs_req->req.buf + read_ptr, to_read); |
5b7d70c6 BD |
1524 | } |
1525 | ||
1526 | /** | |
1f91b4cc | 1527 | * dwc2_hsotg_ep0_zlp - send/receive zero-length packet on control endpoint |
5b7d70c6 | 1528 | * @hsotg: The device instance |
fe0b94ab | 1529 | * @dir_in: If IN zlp |
5b7d70c6 BD |
1530 | * |
1531 | * Generate a zero-length IN packet request for terminating a SETUP | |
1532 | * transaction. | |
1533 | * | |
1534 | * Note, since we don't write any data to the TxFIFO, then it is | |
25985edc | 1535 | * currently believed that we do not need to wait for any space in |
5b7d70c6 BD |
1536 | * the TxFIFO. |
1537 | */ | |
1f91b4cc | 1538 | static void dwc2_hsotg_ep0_zlp(struct dwc2_hsotg *hsotg, bool dir_in) |
5b7d70c6 | 1539 | { |
c6f5c050 | 1540 | /* eps_out[0] is used in both directions */ |
fe0b94ab MYK |
1541 | hsotg->eps_out[0]->dir_in = dir_in; |
1542 | hsotg->ep0_state = dir_in ? DWC2_EP0_STATUS_IN : DWC2_EP0_STATUS_OUT; | |
5b7d70c6 | 1543 | |
1f91b4cc | 1544 | dwc2_hsotg_program_zlp(hsotg, hsotg->eps_out[0]); |
5b7d70c6 BD |
1545 | } |
1546 | ||
ec1f9d9f RB |
1547 | static void dwc2_hsotg_change_ep_iso_parity(struct dwc2_hsotg *hsotg, |
1548 | u32 epctl_reg) | |
1549 | { | |
1550 | u32 ctrl; | |
1551 | ||
1552 | ctrl = dwc2_readl(hsotg->regs + epctl_reg); | |
1553 | if (ctrl & DXEPCTL_EOFRNUM) | |
1554 | ctrl |= DXEPCTL_SETEVENFR; | |
1555 | else | |
1556 | ctrl |= DXEPCTL_SETODDFR; | |
1557 | dwc2_writel(ctrl, hsotg->regs + epctl_reg); | |
1558 | } | |
1559 | ||
5b7d70c6 | 1560 | /** |
1f91b4cc | 1561 | * dwc2_hsotg_handle_outdone - handle receiving OutDone/SetupDone from RXFIFO |
5b7d70c6 BD |
1562 | * @hsotg: The device instance |
1563 | * @epnum: The endpoint received from | |
5b7d70c6 BD |
1564 | * |
1565 | * The RXFIFO has delivered an OutDone event, which means that the data | |
1566 | * transfer for an OUT endpoint has been completed, either by a short | |
1567 | * packet or by the finish of a transfer. | |
8b9bc460 | 1568 | */ |
1f91b4cc | 1569 | static void dwc2_hsotg_handle_outdone(struct dwc2_hsotg *hsotg, int epnum) |
5b7d70c6 | 1570 | { |
95c8bc36 | 1571 | u32 epsize = dwc2_readl(hsotg->regs + DOEPTSIZ(epnum)); |
1f91b4cc FB |
1572 | struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[epnum]; |
1573 | struct dwc2_hsotg_req *hs_req = hs_ep->req; | |
5b7d70c6 | 1574 | struct usb_request *req = &hs_req->req; |
47a1685f | 1575 | unsigned size_left = DXEPTSIZ_XFERSIZE_GET(epsize); |
5b7d70c6 BD |
1576 | int result = 0; |
1577 | ||
1578 | if (!hs_req) { | |
1579 | dev_dbg(hsotg->dev, "%s: no request active\n", __func__); | |
1580 | return; | |
1581 | } | |
1582 | ||
fe0b94ab MYK |
1583 | if (epnum == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_OUT) { |
1584 | dev_dbg(hsotg->dev, "zlp packet received\n"); | |
1f91b4cc FB |
1585 | dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0); |
1586 | dwc2_hsotg_enqueue_setup(hsotg); | |
fe0b94ab MYK |
1587 | return; |
1588 | } | |
1589 | ||
5b7d70c6 | 1590 | if (using_dma(hsotg)) { |
5b7d70c6 | 1591 | unsigned size_done; |
5b7d70c6 | 1592 | |
8b9bc460 LM |
1593 | /* |
1594 | * Calculate the size of the transfer by checking how much | |
5b7d70c6 BD |
1595 | * is left in the endpoint size register and then working it |
1596 | * out from the amount we loaded for the transfer. | |
1597 | * | |
1598 | * We need to do this as DMA pointers are always 32bit aligned | |
1599 | * so may overshoot/undershoot the transfer. | |
1600 | */ | |
1601 | ||
5b7d70c6 BD |
1602 | size_done = hs_ep->size_loaded - size_left; |
1603 | size_done += hs_ep->last_load; | |
1604 | ||
1605 | req->actual = size_done; | |
1606 | } | |
1607 | ||
a33e7136 BD |
1608 | /* if there is more request to do, schedule new transfer */ |
1609 | if (req->actual < req->length && size_left == 0) { | |
1f91b4cc | 1610 | dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true); |
a33e7136 BD |
1611 | return; |
1612 | } | |
1613 | ||
5b7d70c6 BD |
1614 | if (req->actual < req->length && req->short_not_ok) { |
1615 | dev_dbg(hsotg->dev, "%s: got %d/%d (short not ok) => error\n", | |
1616 | __func__, req->actual, req->length); | |
1617 | ||
8b9bc460 LM |
1618 | /* |
1619 | * todo - what should we return here? there's no one else | |
1620 | * even bothering to check the status. | |
1621 | */ | |
5b7d70c6 BD |
1622 | } |
1623 | ||
fe0b94ab MYK |
1624 | if (epnum == 0 && hsotg->ep0_state == DWC2_EP0_DATA_OUT) { |
1625 | /* Move to STATUS IN */ | |
1f91b4cc | 1626 | dwc2_hsotg_ep0_zlp(hsotg, true); |
fe0b94ab | 1627 | return; |
5b7d70c6 BD |
1628 | } |
1629 | ||
ec1f9d9f RB |
1630 | /* |
1631 | * Slave mode OUT transfers do not go through XferComplete so | |
1632 | * adjust the ISOC parity here. | |
1633 | */ | |
1634 | if (!using_dma(hsotg)) { | |
1635 | hs_ep->has_correct_parity = 1; | |
1636 | if (hs_ep->isochronous && hs_ep->interval == 1) | |
1637 | dwc2_hsotg_change_ep_iso_parity(hsotg, DOEPCTL(epnum)); | |
1638 | } | |
1639 | ||
1f91b4cc | 1640 | dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, result); |
5b7d70c6 BD |
1641 | } |
1642 | ||
1643 | /** | |
1f91b4cc | 1644 | * dwc2_hsotg_read_frameno - read current frame number |
5b7d70c6 BD |
1645 | * @hsotg: The device instance |
1646 | * | |
1647 | * Return the current frame number | |
8b9bc460 | 1648 | */ |
1f91b4cc | 1649 | static u32 dwc2_hsotg_read_frameno(struct dwc2_hsotg *hsotg) |
5b7d70c6 BD |
1650 | { |
1651 | u32 dsts; | |
1652 | ||
95c8bc36 | 1653 | dsts = dwc2_readl(hsotg->regs + DSTS); |
94cb8fd6 LM |
1654 | dsts &= DSTS_SOFFN_MASK; |
1655 | dsts >>= DSTS_SOFFN_SHIFT; | |
5b7d70c6 BD |
1656 | |
1657 | return dsts; | |
1658 | } | |
1659 | ||
1660 | /** | |
1f91b4cc | 1661 | * dwc2_hsotg_handle_rx - RX FIFO has data |
5b7d70c6 BD |
1662 | * @hsotg: The device instance |
1663 | * | |
1664 | * The IRQ handler has detected that the RX FIFO has some data in it | |
1665 | * that requires processing, so find out what is in there and do the | |
1666 | * appropriate read. | |
1667 | * | |
25985edc | 1668 | * The RXFIFO is a true FIFO, the packets coming out are still in packet |
5b7d70c6 BD |
1669 | * chunks, so if you have x packets received on an endpoint you'll get x |
1670 | * FIFO events delivered, each with a packet's worth of data in it. | |
1671 | * | |
1672 | * When using DMA, we should not be processing events from the RXFIFO | |
1673 | * as the actual data should be sent to the memory directly and we turn | |
1674 | * on the completion interrupts to get notifications of transfer completion. | |
1675 | */ | |
1f91b4cc | 1676 | static void dwc2_hsotg_handle_rx(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 1677 | { |
95c8bc36 | 1678 | u32 grxstsr = dwc2_readl(hsotg->regs + GRXSTSP); |
5b7d70c6 BD |
1679 | u32 epnum, status, size; |
1680 | ||
1681 | WARN_ON(using_dma(hsotg)); | |
1682 | ||
47a1685f DN |
1683 | epnum = grxstsr & GRXSTS_EPNUM_MASK; |
1684 | status = grxstsr & GRXSTS_PKTSTS_MASK; | |
5b7d70c6 | 1685 | |
47a1685f DN |
1686 | size = grxstsr & GRXSTS_BYTECNT_MASK; |
1687 | size >>= GRXSTS_BYTECNT_SHIFT; | |
5b7d70c6 | 1688 | |
d7c747c5 | 1689 | dev_dbg(hsotg->dev, "%s: GRXSTSP=0x%08x (%d@%d)\n", |
5b7d70c6 BD |
1690 | __func__, grxstsr, size, epnum); |
1691 | ||
47a1685f DN |
1692 | switch ((status & GRXSTS_PKTSTS_MASK) >> GRXSTS_PKTSTS_SHIFT) { |
1693 | case GRXSTS_PKTSTS_GLOBALOUTNAK: | |
1694 | dev_dbg(hsotg->dev, "GLOBALOUTNAK\n"); | |
5b7d70c6 BD |
1695 | break; |
1696 | ||
47a1685f | 1697 | case GRXSTS_PKTSTS_OUTDONE: |
5b7d70c6 | 1698 | dev_dbg(hsotg->dev, "OutDone (Frame=0x%08x)\n", |
1f91b4cc | 1699 | dwc2_hsotg_read_frameno(hsotg)); |
5b7d70c6 BD |
1700 | |
1701 | if (!using_dma(hsotg)) | |
1f91b4cc | 1702 | dwc2_hsotg_handle_outdone(hsotg, epnum); |
5b7d70c6 BD |
1703 | break; |
1704 | ||
47a1685f | 1705 | case GRXSTS_PKTSTS_SETUPDONE: |
5b7d70c6 BD |
1706 | dev_dbg(hsotg->dev, |
1707 | "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n", | |
1f91b4cc | 1708 | dwc2_hsotg_read_frameno(hsotg), |
95c8bc36 | 1709 | dwc2_readl(hsotg->regs + DOEPCTL(0))); |
fe0b94ab | 1710 | /* |
1f91b4cc | 1711 | * Call dwc2_hsotg_handle_outdone here if it was not called from |
fe0b94ab MYK |
1712 | * GRXSTS_PKTSTS_OUTDONE. That is, if the core didn't |
1713 | * generate GRXSTS_PKTSTS_OUTDONE for setup packet. | |
1714 | */ | |
1715 | if (hsotg->ep0_state == DWC2_EP0_SETUP) | |
1f91b4cc | 1716 | dwc2_hsotg_handle_outdone(hsotg, epnum); |
5b7d70c6 BD |
1717 | break; |
1718 | ||
47a1685f | 1719 | case GRXSTS_PKTSTS_OUTRX: |
1f91b4cc | 1720 | dwc2_hsotg_rx_data(hsotg, epnum, size); |
5b7d70c6 BD |
1721 | break; |
1722 | ||
47a1685f | 1723 | case GRXSTS_PKTSTS_SETUPRX: |
5b7d70c6 BD |
1724 | dev_dbg(hsotg->dev, |
1725 | "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n", | |
1f91b4cc | 1726 | dwc2_hsotg_read_frameno(hsotg), |
95c8bc36 | 1727 | dwc2_readl(hsotg->regs + DOEPCTL(0))); |
5b7d70c6 | 1728 | |
fe0b94ab MYK |
1729 | WARN_ON(hsotg->ep0_state != DWC2_EP0_SETUP); |
1730 | ||
1f91b4cc | 1731 | dwc2_hsotg_rx_data(hsotg, epnum, size); |
5b7d70c6 BD |
1732 | break; |
1733 | ||
1734 | default: | |
1735 | dev_warn(hsotg->dev, "%s: unknown status %08x\n", | |
1736 | __func__, grxstsr); | |
1737 | ||
1f91b4cc | 1738 | dwc2_hsotg_dump(hsotg); |
5b7d70c6 BD |
1739 | break; |
1740 | } | |
1741 | } | |
1742 | ||
1743 | /** | |
1f91b4cc | 1744 | * dwc2_hsotg_ep0_mps - turn max packet size into register setting |
5b7d70c6 | 1745 | * @mps: The maximum packet size in bytes. |
8b9bc460 | 1746 | */ |
1f91b4cc | 1747 | static u32 dwc2_hsotg_ep0_mps(unsigned int mps) |
5b7d70c6 BD |
1748 | { |
1749 | switch (mps) { | |
1750 | case 64: | |
94cb8fd6 | 1751 | return D0EPCTL_MPS_64; |
5b7d70c6 | 1752 | case 32: |
94cb8fd6 | 1753 | return D0EPCTL_MPS_32; |
5b7d70c6 | 1754 | case 16: |
94cb8fd6 | 1755 | return D0EPCTL_MPS_16; |
5b7d70c6 | 1756 | case 8: |
94cb8fd6 | 1757 | return D0EPCTL_MPS_8; |
5b7d70c6 BD |
1758 | } |
1759 | ||
1760 | /* bad max packet size, warn and return invalid result */ | |
1761 | WARN_ON(1); | |
1762 | return (u32)-1; | |
1763 | } | |
1764 | ||
1765 | /** | |
1f91b4cc | 1766 | * dwc2_hsotg_set_ep_maxpacket - set endpoint's max-packet field |
5b7d70c6 BD |
1767 | * @hsotg: The driver state. |
1768 | * @ep: The index number of the endpoint | |
1769 | * @mps: The maximum packet size in bytes | |
1770 | * | |
1771 | * Configure the maximum packet size for the given endpoint, updating | |
1772 | * the hardware control registers to reflect this. | |
1773 | */ | |
1f91b4cc | 1774 | static void dwc2_hsotg_set_ep_maxpacket(struct dwc2_hsotg *hsotg, |
c6f5c050 | 1775 | unsigned int ep, unsigned int mps, unsigned int dir_in) |
5b7d70c6 | 1776 | { |
1f91b4cc | 1777 | struct dwc2_hsotg_ep *hs_ep; |
5b7d70c6 BD |
1778 | void __iomem *regs = hsotg->regs; |
1779 | u32 mpsval; | |
4fca54aa | 1780 | u32 mcval; |
5b7d70c6 BD |
1781 | u32 reg; |
1782 | ||
c6f5c050 MYK |
1783 | hs_ep = index_to_ep(hsotg, ep, dir_in); |
1784 | if (!hs_ep) | |
1785 | return; | |
1786 | ||
5b7d70c6 BD |
1787 | if (ep == 0) { |
1788 | /* EP0 is a special case */ | |
1f91b4cc | 1789 | mpsval = dwc2_hsotg_ep0_mps(mps); |
5b7d70c6 BD |
1790 | if (mpsval > 3) |
1791 | goto bad_mps; | |
e9edd199 | 1792 | hs_ep->ep.maxpacket = mps; |
4fca54aa | 1793 | hs_ep->mc = 1; |
5b7d70c6 | 1794 | } else { |
47a1685f | 1795 | mpsval = mps & DXEPCTL_MPS_MASK; |
e9edd199 | 1796 | if (mpsval > 1024) |
5b7d70c6 | 1797 | goto bad_mps; |
4fca54aa RB |
1798 | mcval = ((mps >> 11) & 0x3) + 1; |
1799 | hs_ep->mc = mcval; | |
1800 | if (mcval > 3) | |
1801 | goto bad_mps; | |
e9edd199 | 1802 | hs_ep->ep.maxpacket = mpsval; |
5b7d70c6 BD |
1803 | } |
1804 | ||
c6f5c050 | 1805 | if (dir_in) { |
95c8bc36 | 1806 | reg = dwc2_readl(regs + DIEPCTL(ep)); |
c6f5c050 MYK |
1807 | reg &= ~DXEPCTL_MPS_MASK; |
1808 | reg |= mpsval; | |
95c8bc36 | 1809 | dwc2_writel(reg, regs + DIEPCTL(ep)); |
c6f5c050 | 1810 | } else { |
95c8bc36 | 1811 | reg = dwc2_readl(regs + DOEPCTL(ep)); |
47a1685f | 1812 | reg &= ~DXEPCTL_MPS_MASK; |
659ad60c | 1813 | reg |= mpsval; |
95c8bc36 | 1814 | dwc2_writel(reg, regs + DOEPCTL(ep)); |
659ad60c | 1815 | } |
5b7d70c6 BD |
1816 | |
1817 | return; | |
1818 | ||
1819 | bad_mps: | |
1820 | dev_err(hsotg->dev, "ep%d: bad mps of %d\n", ep, mps); | |
1821 | } | |
1822 | ||
9c39ddc6 | 1823 | /** |
1f91b4cc | 1824 | * dwc2_hsotg_txfifo_flush - flush Tx FIFO |
9c39ddc6 AT |
1825 | * @hsotg: The driver state |
1826 | * @idx: The index for the endpoint (0..15) | |
1827 | */ | |
1f91b4cc | 1828 | static void dwc2_hsotg_txfifo_flush(struct dwc2_hsotg *hsotg, unsigned int idx) |
9c39ddc6 AT |
1829 | { |
1830 | int timeout; | |
1831 | int val; | |
1832 | ||
95c8bc36 AS |
1833 | dwc2_writel(GRSTCTL_TXFNUM(idx) | GRSTCTL_TXFFLSH, |
1834 | hsotg->regs + GRSTCTL); | |
9c39ddc6 AT |
1835 | |
1836 | /* wait until the fifo is flushed */ | |
1837 | timeout = 100; | |
1838 | ||
1839 | while (1) { | |
95c8bc36 | 1840 | val = dwc2_readl(hsotg->regs + GRSTCTL); |
9c39ddc6 | 1841 | |
47a1685f | 1842 | if ((val & (GRSTCTL_TXFFLSH)) == 0) |
9c39ddc6 AT |
1843 | break; |
1844 | ||
1845 | if (--timeout == 0) { | |
1846 | dev_err(hsotg->dev, | |
1847 | "%s: timeout flushing fifo (GRSTCTL=%08x)\n", | |
1848 | __func__, val); | |
e0cbe595 | 1849 | break; |
9c39ddc6 AT |
1850 | } |
1851 | ||
1852 | udelay(1); | |
1853 | } | |
1854 | } | |
5b7d70c6 BD |
1855 | |
1856 | /** | |
1f91b4cc | 1857 | * dwc2_hsotg_trytx - check to see if anything needs transmitting |
5b7d70c6 BD |
1858 | * @hsotg: The driver state |
1859 | * @hs_ep: The driver endpoint to check. | |
1860 | * | |
1861 | * Check to see if there is a request that has data to send, and if so | |
1862 | * make an attempt to write data into the FIFO. | |
1863 | */ | |
1f91b4cc FB |
1864 | static int dwc2_hsotg_trytx(struct dwc2_hsotg *hsotg, |
1865 | struct dwc2_hsotg_ep *hs_ep) | |
5b7d70c6 | 1866 | { |
1f91b4cc | 1867 | struct dwc2_hsotg_req *hs_req = hs_ep->req; |
5b7d70c6 | 1868 | |
afcf4169 RB |
1869 | if (!hs_ep->dir_in || !hs_req) { |
1870 | /** | |
1871 | * if request is not enqueued, we disable interrupts | |
1872 | * for endpoints, excepting ep0 | |
1873 | */ | |
1874 | if (hs_ep->index != 0) | |
1f91b4cc | 1875 | dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, |
afcf4169 | 1876 | hs_ep->dir_in, 0); |
5b7d70c6 | 1877 | return 0; |
afcf4169 | 1878 | } |
5b7d70c6 BD |
1879 | |
1880 | if (hs_req->req.actual < hs_req->req.length) { | |
1881 | dev_dbg(hsotg->dev, "trying to write more for ep%d\n", | |
1882 | hs_ep->index); | |
1f91b4cc | 1883 | return dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req); |
5b7d70c6 BD |
1884 | } |
1885 | ||
1886 | return 0; | |
1887 | } | |
1888 | ||
1889 | /** | |
1f91b4cc | 1890 | * dwc2_hsotg_complete_in - complete IN transfer |
5b7d70c6 BD |
1891 | * @hsotg: The device state. |
1892 | * @hs_ep: The endpoint that has just completed. | |
1893 | * | |
1894 | * An IN transfer has been completed, update the transfer's state and then | |
1895 | * call the relevant completion routines. | |
1896 | */ | |
1f91b4cc FB |
1897 | static void dwc2_hsotg_complete_in(struct dwc2_hsotg *hsotg, |
1898 | struct dwc2_hsotg_ep *hs_ep) | |
5b7d70c6 | 1899 | { |
1f91b4cc | 1900 | struct dwc2_hsotg_req *hs_req = hs_ep->req; |
95c8bc36 | 1901 | u32 epsize = dwc2_readl(hsotg->regs + DIEPTSIZ(hs_ep->index)); |
5b7d70c6 BD |
1902 | int size_left, size_done; |
1903 | ||
1904 | if (!hs_req) { | |
1905 | dev_dbg(hsotg->dev, "XferCompl but no req\n"); | |
1906 | return; | |
1907 | } | |
1908 | ||
d3ca0259 | 1909 | /* Finish ZLP handling for IN EP0 transactions */ |
fe0b94ab MYK |
1910 | if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_IN) { |
1911 | dev_dbg(hsotg->dev, "zlp packet sent\n"); | |
1f91b4cc | 1912 | dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0); |
9e14d0a5 GH |
1913 | if (hsotg->test_mode) { |
1914 | int ret; | |
1915 | ||
1f91b4cc | 1916 | ret = dwc2_hsotg_set_test_mode(hsotg, hsotg->test_mode); |
9e14d0a5 GH |
1917 | if (ret < 0) { |
1918 | dev_dbg(hsotg->dev, "Invalid Test #%d\n", | |
1919 | hsotg->test_mode); | |
1f91b4cc | 1920 | dwc2_hsotg_stall_ep0(hsotg); |
9e14d0a5 GH |
1921 | return; |
1922 | } | |
1923 | } | |
1f91b4cc | 1924 | dwc2_hsotg_enqueue_setup(hsotg); |
d3ca0259 LM |
1925 | return; |
1926 | } | |
1927 | ||
8b9bc460 LM |
1928 | /* |
1929 | * Calculate the size of the transfer by checking how much is left | |
5b7d70c6 BD |
1930 | * in the endpoint size register and then working it out from |
1931 | * the amount we loaded for the transfer. | |
1932 | * | |
1933 | * We do this even for DMA, as the transfer may have incremented | |
1934 | * past the end of the buffer (DMA transfers are always 32bit | |
1935 | * aligned). | |
1936 | */ | |
1937 | ||
47a1685f | 1938 | size_left = DXEPTSIZ_XFERSIZE_GET(epsize); |
5b7d70c6 BD |
1939 | |
1940 | size_done = hs_ep->size_loaded - size_left; | |
1941 | size_done += hs_ep->last_load; | |
1942 | ||
1943 | if (hs_req->req.actual != size_done) | |
1944 | dev_dbg(hsotg->dev, "%s: adjusting size done %d => %d\n", | |
1945 | __func__, hs_req->req.actual, size_done); | |
1946 | ||
1947 | hs_req->req.actual = size_done; | |
d3ca0259 LM |
1948 | dev_dbg(hsotg->dev, "req->length:%d req->actual:%d req->zero:%d\n", |
1949 | hs_req->req.length, hs_req->req.actual, hs_req->req.zero); | |
1950 | ||
5b7d70c6 BD |
1951 | if (!size_left && hs_req->req.actual < hs_req->req.length) { |
1952 | dev_dbg(hsotg->dev, "%s trying more for req...\n", __func__); | |
1f91b4cc | 1953 | dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true); |
fe0b94ab MYK |
1954 | return; |
1955 | } | |
1956 | ||
f71b5e25 | 1957 | /* Zlp for all endpoints, for ep0 only in DATA IN stage */ |
8a20fa45 | 1958 | if (hs_ep->send_zlp) { |
1f91b4cc | 1959 | dwc2_hsotg_program_zlp(hsotg, hs_ep); |
8a20fa45 | 1960 | hs_ep->send_zlp = 0; |
f71b5e25 MYK |
1961 | /* transfer will be completed on next complete interrupt */ |
1962 | return; | |
1963 | } | |
1964 | ||
fe0b94ab MYK |
1965 | if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_DATA_IN) { |
1966 | /* Move to STATUS OUT */ | |
1f91b4cc | 1967 | dwc2_hsotg_ep0_zlp(hsotg, false); |
fe0b94ab MYK |
1968 | return; |
1969 | } | |
1970 | ||
1f91b4cc | 1971 | dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0); |
5b7d70c6 BD |
1972 | } |
1973 | ||
32601588 VM |
1974 | /** |
1975 | * dwc2_gadget_read_ep_interrupts - reads interrupts for given ep | |
1976 | * @hsotg: The device state. | |
1977 | * @idx: Index of ep. | |
1978 | * @dir_in: Endpoint direction 1-in 0-out. | |
1979 | * | |
1980 | * Reads for endpoint with given index and direction, by masking | |
1981 | * epint_reg with coresponding mask. | |
1982 | */ | |
1983 | static u32 dwc2_gadget_read_ep_interrupts(struct dwc2_hsotg *hsotg, | |
1984 | unsigned int idx, int dir_in) | |
1985 | { | |
1986 | u32 epmsk_reg = dir_in ? DIEPMSK : DOEPMSK; | |
1987 | u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx); | |
1988 | u32 ints; | |
1989 | u32 mask; | |
1990 | u32 diepempmsk; | |
1991 | ||
1992 | mask = dwc2_readl(hsotg->regs + epmsk_reg); | |
1993 | diepempmsk = dwc2_readl(hsotg->regs + DIEPEMPMSK); | |
1994 | mask |= ((diepempmsk >> idx) & 0x1) ? DIEPMSK_TXFIFOEMPTY : 0; | |
1995 | mask |= DXEPINT_SETUP_RCVD; | |
1996 | ||
1997 | ints = dwc2_readl(hsotg->regs + epint_reg); | |
1998 | ints &= mask; | |
1999 | return ints; | |
2000 | } | |
2001 | ||
5321922c VM |
2002 | /** |
2003 | * dwc2_gadget_handle_out_token_ep_disabled - handle DXEPINT_OUTTKNEPDIS | |
2004 | * @hs_ep: The endpoint on which interrupt is asserted. | |
2005 | * | |
2006 | * This is starting point for ISOC-OUT transfer, synchronization done with | |
2007 | * first out token received from host while corresponding EP is disabled. | |
2008 | * | |
2009 | * Device does not know initial frame in which out token will come. For this | |
2010 | * HW generates OUTTKNEPDIS - out token is received while EP is disabled. Upon | |
2011 | * getting this interrupt SW starts calculation for next transfer frame. | |
2012 | */ | |
2013 | static void dwc2_gadget_handle_out_token_ep_disabled(struct dwc2_hsotg_ep *ep) | |
2014 | { | |
2015 | struct dwc2_hsotg *hsotg = ep->parent; | |
2016 | int dir_in = ep->dir_in; | |
2017 | u32 doepmsk; | |
2018 | ||
2019 | if (dir_in || !ep->isochronous) | |
2020 | return; | |
2021 | ||
2022 | dwc2_hsotg_complete_request(hsotg, ep, get_ep_head(ep), -ENODATA); | |
2023 | ||
2024 | if (ep->interval > 1 && | |
2025 | ep->target_frame == TARGET_FRAME_INITIAL) { | |
2026 | u32 dsts; | |
2027 | u32 ctrl; | |
2028 | ||
2029 | dsts = dwc2_readl(hsotg->regs + DSTS); | |
2030 | ep->target_frame = dwc2_hsotg_read_frameno(hsotg); | |
2031 | dwc2_gadget_incr_frame_num(ep); | |
2032 | ||
2033 | ctrl = dwc2_readl(hsotg->regs + DOEPCTL(ep->index)); | |
2034 | if (ep->target_frame & 0x1) | |
2035 | ctrl |= DXEPCTL_SETODDFR; | |
2036 | else | |
2037 | ctrl |= DXEPCTL_SETEVENFR; | |
2038 | ||
2039 | dwc2_writel(ctrl, hsotg->regs + DOEPCTL(ep->index)); | |
2040 | } | |
2041 | ||
2042 | dwc2_gadget_start_next_request(ep); | |
2043 | doepmsk = dwc2_readl(hsotg->regs + DOEPMSK); | |
2044 | doepmsk &= ~DOEPMSK_OUTTKNEPDISMSK; | |
2045 | dwc2_writel(doepmsk, hsotg->regs + DOEPMSK); | |
2046 | } | |
2047 | ||
2048 | /** | |
2049 | * dwc2_gadget_handle_nak - handle NAK interrupt | |
2050 | * @hs_ep: The endpoint on which interrupt is asserted. | |
2051 | * | |
2052 | * This is starting point for ISOC-IN transfer, synchronization done with | |
2053 | * first IN token received from host while corresponding EP is disabled. | |
2054 | * | |
2055 | * Device does not know when first one token will arrive from host. On first | |
2056 | * token arrival HW generates 2 interrupts: 'in token received while FIFO empty' | |
2057 | * and 'NAK'. NAK interrupt for ISOC-IN means that token has arrived and ZLP was | |
2058 | * sent in response to that as there was no data in FIFO. SW is basing on this | |
2059 | * interrupt to obtain frame in which token has come and then based on the | |
2060 | * interval calculates next frame for transfer. | |
2061 | */ | |
2062 | static void dwc2_gadget_handle_nak(struct dwc2_hsotg_ep *hs_ep) | |
2063 | { | |
2064 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
2065 | int dir_in = hs_ep->dir_in; | |
2066 | ||
2067 | if (!dir_in || !hs_ep->isochronous) | |
2068 | return; | |
2069 | ||
2070 | if (hs_ep->target_frame == TARGET_FRAME_INITIAL) { | |
2071 | hs_ep->target_frame = dwc2_hsotg_read_frameno(hsotg); | |
2072 | if (hs_ep->interval > 1) { | |
2073 | u32 ctrl = dwc2_readl(hsotg->regs + | |
2074 | DIEPCTL(hs_ep->index)); | |
2075 | if (hs_ep->target_frame & 0x1) | |
2076 | ctrl |= DXEPCTL_SETODDFR; | |
2077 | else | |
2078 | ctrl |= DXEPCTL_SETEVENFR; | |
2079 | ||
2080 | dwc2_writel(ctrl, hsotg->regs + DIEPCTL(hs_ep->index)); | |
2081 | } | |
2082 | ||
2083 | dwc2_hsotg_complete_request(hsotg, hs_ep, | |
2084 | get_ep_head(hs_ep), 0); | |
2085 | } | |
2086 | ||
2087 | dwc2_gadget_incr_frame_num(hs_ep); | |
2088 | } | |
2089 | ||
5b7d70c6 | 2090 | /** |
1f91b4cc | 2091 | * dwc2_hsotg_epint - handle an in/out endpoint interrupt |
5b7d70c6 BD |
2092 | * @hsotg: The driver state |
2093 | * @idx: The index for the endpoint (0..15) | |
2094 | * @dir_in: Set if this is an IN endpoint | |
2095 | * | |
2096 | * Process and clear any interrupt pending for an individual endpoint | |
8b9bc460 | 2097 | */ |
1f91b4cc | 2098 | static void dwc2_hsotg_epint(struct dwc2_hsotg *hsotg, unsigned int idx, |
5b7d70c6 BD |
2099 | int dir_in) |
2100 | { | |
1f91b4cc | 2101 | struct dwc2_hsotg_ep *hs_ep = index_to_ep(hsotg, idx, dir_in); |
94cb8fd6 LM |
2102 | u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx); |
2103 | u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx); | |
2104 | u32 epsiz_reg = dir_in ? DIEPTSIZ(idx) : DOEPTSIZ(idx); | |
5b7d70c6 | 2105 | u32 ints; |
1479e841 | 2106 | u32 ctrl; |
5b7d70c6 | 2107 | |
32601588 | 2108 | ints = dwc2_gadget_read_ep_interrupts(hsotg, idx, dir_in); |
95c8bc36 | 2109 | ctrl = dwc2_readl(hsotg->regs + epctl_reg); |
5b7d70c6 | 2110 | |
a3395f0d | 2111 | /* Clear endpoint interrupts */ |
95c8bc36 | 2112 | dwc2_writel(ints, hsotg->regs + epint_reg); |
a3395f0d | 2113 | |
c6f5c050 MYK |
2114 | if (!hs_ep) { |
2115 | dev_err(hsotg->dev, "%s:Interrupt for unconfigured ep%d(%s)\n", | |
2116 | __func__, idx, dir_in ? "in" : "out"); | |
2117 | return; | |
2118 | } | |
2119 | ||
5b7d70c6 BD |
2120 | dev_dbg(hsotg->dev, "%s: ep%d(%s) DxEPINT=0x%08x\n", |
2121 | __func__, idx, dir_in ? "in" : "out", ints); | |
2122 | ||
b787d755 MYK |
2123 | /* Don't process XferCompl interrupt if it is a setup packet */ |
2124 | if (idx == 0 && (ints & (DXEPINT_SETUP | DXEPINT_SETUP_RCVD))) | |
2125 | ints &= ~DXEPINT_XFERCOMPL; | |
2126 | ||
47a1685f | 2127 | if (ints & DXEPINT_XFERCOMPL) { |
ec1f9d9f RB |
2128 | hs_ep->has_correct_parity = 1; |
2129 | if (hs_ep->isochronous && hs_ep->interval == 1) | |
2130 | dwc2_hsotg_change_ep_iso_parity(hsotg, epctl_reg); | |
1479e841 | 2131 | |
5b7d70c6 | 2132 | dev_dbg(hsotg->dev, |
47a1685f | 2133 | "%s: XferCompl: DxEPCTL=0x%08x, DXEPTSIZ=%08x\n", |
95c8bc36 AS |
2134 | __func__, dwc2_readl(hsotg->regs + epctl_reg), |
2135 | dwc2_readl(hsotg->regs + epsiz_reg)); | |
5b7d70c6 | 2136 | |
8b9bc460 LM |
2137 | /* |
2138 | * we get OutDone from the FIFO, so we only need to look | |
2139 | * at completing IN requests here | |
2140 | */ | |
5b7d70c6 | 2141 | if (dir_in) { |
1f91b4cc | 2142 | dwc2_hsotg_complete_in(hsotg, hs_ep); |
5b7d70c6 | 2143 | |
c9a64ea8 | 2144 | if (idx == 0 && !hs_ep->req) |
1f91b4cc | 2145 | dwc2_hsotg_enqueue_setup(hsotg); |
5b7d70c6 | 2146 | } else if (using_dma(hsotg)) { |
8b9bc460 LM |
2147 | /* |
2148 | * We're using DMA, we need to fire an OutDone here | |
2149 | * as we ignore the RXFIFO. | |
2150 | */ | |
5b7d70c6 | 2151 | |
1f91b4cc | 2152 | dwc2_hsotg_handle_outdone(hsotg, idx); |
5b7d70c6 | 2153 | } |
5b7d70c6 BD |
2154 | } |
2155 | ||
47a1685f | 2156 | if (ints & DXEPINT_EPDISBLD) { |
5b7d70c6 | 2157 | dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__); |
5b7d70c6 | 2158 | |
9c39ddc6 | 2159 | if (dir_in) { |
95c8bc36 | 2160 | int epctl = dwc2_readl(hsotg->regs + epctl_reg); |
9c39ddc6 | 2161 | |
1f91b4cc | 2162 | dwc2_hsotg_txfifo_flush(hsotg, hs_ep->fifo_index); |
9c39ddc6 | 2163 | |
47a1685f DN |
2164 | if ((epctl & DXEPCTL_STALL) && |
2165 | (epctl & DXEPCTL_EPTYPE_BULK)) { | |
95c8bc36 | 2166 | int dctl = dwc2_readl(hsotg->regs + DCTL); |
9c39ddc6 | 2167 | |
47a1685f | 2168 | dctl |= DCTL_CGNPINNAK; |
95c8bc36 | 2169 | dwc2_writel(dctl, hsotg->regs + DCTL); |
9c39ddc6 AT |
2170 | } |
2171 | } | |
2172 | } | |
2173 | ||
5321922c VM |
2174 | if (ints & DXEPINT_OUTTKNEPDIS) |
2175 | dwc2_gadget_handle_out_token_ep_disabled(hs_ep); | |
2176 | ||
2177 | if (ints & DXEPINT_NAKINTRPT) | |
2178 | dwc2_gadget_handle_nak(hs_ep); | |
2179 | ||
47a1685f | 2180 | if (ints & DXEPINT_AHBERR) |
5b7d70c6 | 2181 | dev_dbg(hsotg->dev, "%s: AHBErr\n", __func__); |
5b7d70c6 | 2182 | |
47a1685f | 2183 | if (ints & DXEPINT_SETUP) { /* Setup or Timeout */ |
5b7d70c6 BD |
2184 | dev_dbg(hsotg->dev, "%s: Setup/Timeout\n", __func__); |
2185 | ||
2186 | if (using_dma(hsotg) && idx == 0) { | |
8b9bc460 LM |
2187 | /* |
2188 | * this is the notification we've received a | |
5b7d70c6 BD |
2189 | * setup packet. In non-DMA mode we'd get this |
2190 | * from the RXFIFO, instead we need to process | |
8b9bc460 LM |
2191 | * the setup here. |
2192 | */ | |
5b7d70c6 BD |
2193 | |
2194 | if (dir_in) | |
2195 | WARN_ON_ONCE(1); | |
2196 | else | |
1f91b4cc | 2197 | dwc2_hsotg_handle_outdone(hsotg, 0); |
5b7d70c6 | 2198 | } |
5b7d70c6 BD |
2199 | } |
2200 | ||
47a1685f | 2201 | if (ints & DXEPINT_BACK2BACKSETUP) |
5b7d70c6 | 2202 | dev_dbg(hsotg->dev, "%s: B2BSetup/INEPNakEff\n", __func__); |
5b7d70c6 | 2203 | |
1479e841 | 2204 | if (dir_in && !hs_ep->isochronous) { |
8b9bc460 | 2205 | /* not sure if this is important, but we'll clear it anyway */ |
26ddef5d | 2206 | if (ints & DXEPINT_INTKNTXFEMP) { |
5b7d70c6 BD |
2207 | dev_dbg(hsotg->dev, "%s: ep%d: INTknTXFEmpMsk\n", |
2208 | __func__, idx); | |
5b7d70c6 BD |
2209 | } |
2210 | ||
2211 | /* this probably means something bad is happening */ | |
26ddef5d | 2212 | if (ints & DXEPINT_INTKNEPMIS) { |
5b7d70c6 BD |
2213 | dev_warn(hsotg->dev, "%s: ep%d: INTknEP\n", |
2214 | __func__, idx); | |
5b7d70c6 | 2215 | } |
10aebc77 BD |
2216 | |
2217 | /* FIFO has space or is empty (see GAHBCFG) */ | |
2218 | if (hsotg->dedicated_fifos && | |
26ddef5d | 2219 | ints & DXEPINT_TXFEMP) { |
10aebc77 BD |
2220 | dev_dbg(hsotg->dev, "%s: ep%d: TxFIFOEmpty\n", |
2221 | __func__, idx); | |
70fa030f | 2222 | if (!using_dma(hsotg)) |
1f91b4cc | 2223 | dwc2_hsotg_trytx(hsotg, hs_ep); |
10aebc77 | 2224 | } |
5b7d70c6 | 2225 | } |
5b7d70c6 BD |
2226 | } |
2227 | ||
2228 | /** | |
1f91b4cc | 2229 | * dwc2_hsotg_irq_enumdone - Handle EnumDone interrupt (enumeration done) |
5b7d70c6 BD |
2230 | * @hsotg: The device state. |
2231 | * | |
2232 | * Handle updating the device settings after the enumeration phase has | |
2233 | * been completed. | |
8b9bc460 | 2234 | */ |
1f91b4cc | 2235 | static void dwc2_hsotg_irq_enumdone(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 2236 | { |
95c8bc36 | 2237 | u32 dsts = dwc2_readl(hsotg->regs + DSTS); |
9b2667f1 | 2238 | int ep0_mps = 0, ep_mps = 8; |
5b7d70c6 | 2239 | |
8b9bc460 LM |
2240 | /* |
2241 | * This should signal the finish of the enumeration phase | |
5b7d70c6 | 2242 | * of the USB handshaking, so we should now know what rate |
8b9bc460 LM |
2243 | * we connected at. |
2244 | */ | |
5b7d70c6 BD |
2245 | |
2246 | dev_dbg(hsotg->dev, "EnumDone (DSTS=0x%08x)\n", dsts); | |
2247 | ||
8b9bc460 LM |
2248 | /* |
2249 | * note, since we're limited by the size of transfer on EP0, and | |
5b7d70c6 | 2250 | * it seems IN transfers must be a even number of packets we do |
8b9bc460 LM |
2251 | * not advertise a 64byte MPS on EP0. |
2252 | */ | |
5b7d70c6 BD |
2253 | |
2254 | /* catch both EnumSpd_FS and EnumSpd_FS48 */ | |
6d76c92c | 2255 | switch ((dsts & DSTS_ENUMSPD_MASK) >> DSTS_ENUMSPD_SHIFT) { |
47a1685f DN |
2256 | case DSTS_ENUMSPD_FS: |
2257 | case DSTS_ENUMSPD_FS48: | |
5b7d70c6 | 2258 | hsotg->gadget.speed = USB_SPEED_FULL; |
5b7d70c6 | 2259 | ep0_mps = EP0_MPS_LIMIT; |
295538ff | 2260 | ep_mps = 1023; |
5b7d70c6 BD |
2261 | break; |
2262 | ||
47a1685f | 2263 | case DSTS_ENUMSPD_HS: |
5b7d70c6 | 2264 | hsotg->gadget.speed = USB_SPEED_HIGH; |
5b7d70c6 | 2265 | ep0_mps = EP0_MPS_LIMIT; |
295538ff | 2266 | ep_mps = 1024; |
5b7d70c6 BD |
2267 | break; |
2268 | ||
47a1685f | 2269 | case DSTS_ENUMSPD_LS: |
5b7d70c6 | 2270 | hsotg->gadget.speed = USB_SPEED_LOW; |
8b9bc460 LM |
2271 | /* |
2272 | * note, we don't actually support LS in this driver at the | |
5b7d70c6 BD |
2273 | * moment, and the documentation seems to imply that it isn't |
2274 | * supported by the PHYs on some of the devices. | |
2275 | */ | |
2276 | break; | |
2277 | } | |
e538dfda MN |
2278 | dev_info(hsotg->dev, "new device is %s\n", |
2279 | usb_speed_string(hsotg->gadget.speed)); | |
5b7d70c6 | 2280 | |
8b9bc460 LM |
2281 | /* |
2282 | * we should now know the maximum packet size for an | |
2283 | * endpoint, so set the endpoints to a default value. | |
2284 | */ | |
5b7d70c6 BD |
2285 | |
2286 | if (ep0_mps) { | |
2287 | int i; | |
c6f5c050 | 2288 | /* Initialize ep0 for both in and out directions */ |
1f91b4cc FB |
2289 | dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 1); |
2290 | dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 0); | |
c6f5c050 MYK |
2291 | for (i = 1; i < hsotg->num_of_eps; i++) { |
2292 | if (hsotg->eps_in[i]) | |
1f91b4cc | 2293 | dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps, 1); |
c6f5c050 | 2294 | if (hsotg->eps_out[i]) |
1f91b4cc | 2295 | dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps, 0); |
c6f5c050 | 2296 | } |
5b7d70c6 BD |
2297 | } |
2298 | ||
2299 | /* ensure after enumeration our EP0 is active */ | |
2300 | ||
1f91b4cc | 2301 | dwc2_hsotg_enqueue_setup(hsotg); |
5b7d70c6 BD |
2302 | |
2303 | dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n", | |
95c8bc36 AS |
2304 | dwc2_readl(hsotg->regs + DIEPCTL0), |
2305 | dwc2_readl(hsotg->regs + DOEPCTL0)); | |
5b7d70c6 BD |
2306 | } |
2307 | ||
2308 | /** | |
2309 | * kill_all_requests - remove all requests from the endpoint's queue | |
2310 | * @hsotg: The device state. | |
2311 | * @ep: The endpoint the requests may be on. | |
2312 | * @result: The result code to use. | |
5b7d70c6 BD |
2313 | * |
2314 | * Go through the requests on the given endpoint and mark them | |
2315 | * completed with the given result code. | |
2316 | */ | |
941fcce4 | 2317 | static void kill_all_requests(struct dwc2_hsotg *hsotg, |
1f91b4cc | 2318 | struct dwc2_hsotg_ep *ep, |
6b448af4 | 2319 | int result) |
5b7d70c6 | 2320 | { |
1f91b4cc | 2321 | struct dwc2_hsotg_req *req, *treq; |
b203d0a2 | 2322 | unsigned size; |
5b7d70c6 | 2323 | |
6b448af4 | 2324 | ep->req = NULL; |
5b7d70c6 | 2325 | |
6b448af4 | 2326 | list_for_each_entry_safe(req, treq, &ep->queue, queue) |
1f91b4cc | 2327 | dwc2_hsotg_complete_request(hsotg, ep, req, |
5b7d70c6 | 2328 | result); |
6b448af4 | 2329 | |
b203d0a2 RB |
2330 | if (!hsotg->dedicated_fifos) |
2331 | return; | |
95c8bc36 | 2332 | size = (dwc2_readl(hsotg->regs + DTXFSTS(ep->index)) & 0xffff) * 4; |
b203d0a2 | 2333 | if (size < ep->fifo_size) |
1f91b4cc | 2334 | dwc2_hsotg_txfifo_flush(hsotg, ep->fifo_index); |
5b7d70c6 BD |
2335 | } |
2336 | ||
5b7d70c6 | 2337 | /** |
1f91b4cc | 2338 | * dwc2_hsotg_disconnect - disconnect service |
5b7d70c6 BD |
2339 | * @hsotg: The device state. |
2340 | * | |
5e891342 LM |
2341 | * The device has been disconnected. Remove all current |
2342 | * transactions and signal the gadget driver that this | |
2343 | * has happened. | |
8b9bc460 | 2344 | */ |
1f91b4cc | 2345 | void dwc2_hsotg_disconnect(struct dwc2_hsotg *hsotg) |
5b7d70c6 BD |
2346 | { |
2347 | unsigned ep; | |
2348 | ||
4ace06e8 MS |
2349 | if (!hsotg->connected) |
2350 | return; | |
2351 | ||
2352 | hsotg->connected = 0; | |
9e14d0a5 | 2353 | hsotg->test_mode = 0; |
c6f5c050 MYK |
2354 | |
2355 | for (ep = 0; ep < hsotg->num_of_eps; ep++) { | |
2356 | if (hsotg->eps_in[ep]) | |
2357 | kill_all_requests(hsotg, hsotg->eps_in[ep], | |
2358 | -ESHUTDOWN); | |
2359 | if (hsotg->eps_out[ep]) | |
2360 | kill_all_requests(hsotg, hsotg->eps_out[ep], | |
2361 | -ESHUTDOWN); | |
2362 | } | |
5b7d70c6 BD |
2363 | |
2364 | call_gadget(hsotg, disconnect); | |
065d3931 | 2365 | hsotg->lx_state = DWC2_L3; |
5b7d70c6 BD |
2366 | } |
2367 | ||
2368 | /** | |
1f91b4cc | 2369 | * dwc2_hsotg_irq_fifoempty - TX FIFO empty interrupt handler |
5b7d70c6 BD |
2370 | * @hsotg: The device state: |
2371 | * @periodic: True if this is a periodic FIFO interrupt | |
2372 | */ | |
1f91b4cc | 2373 | static void dwc2_hsotg_irq_fifoempty(struct dwc2_hsotg *hsotg, bool periodic) |
5b7d70c6 | 2374 | { |
1f91b4cc | 2375 | struct dwc2_hsotg_ep *ep; |
5b7d70c6 BD |
2376 | int epno, ret; |
2377 | ||
2378 | /* look through for any more data to transmit */ | |
b3f489b2 | 2379 | for (epno = 0; epno < hsotg->num_of_eps; epno++) { |
c6f5c050 MYK |
2380 | ep = index_to_ep(hsotg, epno, 1); |
2381 | ||
2382 | if (!ep) | |
2383 | continue; | |
5b7d70c6 BD |
2384 | |
2385 | if (!ep->dir_in) | |
2386 | continue; | |
2387 | ||
2388 | if ((periodic && !ep->periodic) || | |
2389 | (!periodic && ep->periodic)) | |
2390 | continue; | |
2391 | ||
1f91b4cc | 2392 | ret = dwc2_hsotg_trytx(hsotg, ep); |
5b7d70c6 BD |
2393 | if (ret < 0) |
2394 | break; | |
2395 | } | |
2396 | } | |
2397 | ||
5b7d70c6 | 2398 | /* IRQ flags which will trigger a retry around the IRQ loop */ |
47a1685f DN |
2399 | #define IRQ_RETRY_MASK (GINTSTS_NPTXFEMP | \ |
2400 | GINTSTS_PTXFEMP | \ | |
2401 | GINTSTS_RXFLVL) | |
5b7d70c6 | 2402 | |
8b9bc460 | 2403 | /** |
1f91b4cc | 2404 | * dwc2_hsotg_core_init - issue softreset to the core |
8b9bc460 LM |
2405 | * @hsotg: The device state |
2406 | * | |
2407 | * Issue a soft reset to the core, and await the core finishing it. | |
2408 | */ | |
1f91b4cc | 2409 | void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg, |
643cc4de | 2410 | bool is_usb_reset) |
308d734e | 2411 | { |
1ee6903b | 2412 | u32 intmsk; |
643cc4de | 2413 | u32 val; |
ecd9a7ad | 2414 | u32 usbcfg; |
643cc4de | 2415 | |
5390d438 MYK |
2416 | /* Kill any ep0 requests as controller will be reinitialized */ |
2417 | kill_all_requests(hsotg, hsotg->eps_out[0], -ECONNRESET); | |
2418 | ||
643cc4de | 2419 | if (!is_usb_reset) |
241729ba | 2420 | if (dwc2_core_reset(hsotg)) |
86de4895 | 2421 | return; |
308d734e LM |
2422 | |
2423 | /* | |
2424 | * we must now enable ep0 ready for host detection and then | |
2425 | * set configuration. | |
2426 | */ | |
2427 | ||
ecd9a7ad PR |
2428 | /* keep other bits untouched (so e.g. forced modes are not lost) */ |
2429 | usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); | |
2430 | usbcfg &= ~(GUSBCFG_TOUTCAL_MASK | GUSBCFG_PHYIF16 | GUSBCFG_SRPCAP | | |
2431 | GUSBCFG_HNPCAP); | |
2432 | ||
308d734e | 2433 | /* set the PLL on, remove the HNP/SRP and set the PHY */ |
fa4a8d72 | 2434 | val = (hsotg->phyif == GUSBCFG_PHYIF8) ? 9 : 5; |
ecd9a7ad PR |
2435 | usbcfg |= hsotg->phyif | GUSBCFG_TOUTCAL(7) | |
2436 | (val << GUSBCFG_USBTRDTIM_SHIFT); | |
2437 | dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); | |
308d734e | 2438 | |
1f91b4cc | 2439 | dwc2_hsotg_init_fifo(hsotg); |
308d734e | 2440 | |
643cc4de GH |
2441 | if (!is_usb_reset) |
2442 | __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON); | |
308d734e | 2443 | |
95c8bc36 | 2444 | dwc2_writel(DCFG_EPMISCNT(1) | DCFG_DEVSPD_HS, hsotg->regs + DCFG); |
308d734e LM |
2445 | |
2446 | /* Clear any pending OTG interrupts */ | |
95c8bc36 | 2447 | dwc2_writel(0xffffffff, hsotg->regs + GOTGINT); |
308d734e LM |
2448 | |
2449 | /* Clear any pending interrupts */ | |
95c8bc36 | 2450 | dwc2_writel(0xffffffff, hsotg->regs + GINTSTS); |
1ee6903b | 2451 | intmsk = GINTSTS_ERLYSUSP | GINTSTS_SESSREQINT | |
47a1685f | 2452 | GINTSTS_GOUTNAKEFF | GINTSTS_GINNAKEFF | |
1ee6903b GH |
2453 | GINTSTS_USBRST | GINTSTS_RESETDET | |
2454 | GINTSTS_ENUMDONE | GINTSTS_OTGINT | | |
ec1f9d9f RB |
2455 | GINTSTS_USBSUSP | GINTSTS_WKUPINT | |
2456 | GINTSTS_INCOMPL_SOIN | GINTSTS_INCOMPL_SOOUT; | |
1ee6903b GH |
2457 | |
2458 | if (hsotg->core_params->external_id_pin_ctl <= 0) | |
2459 | intmsk |= GINTSTS_CONIDSTSCHNG; | |
2460 | ||
2461 | dwc2_writel(intmsk, hsotg->regs + GINTMSK); | |
308d734e LM |
2462 | |
2463 | if (using_dma(hsotg)) | |
95c8bc36 AS |
2464 | dwc2_writel(GAHBCFG_GLBL_INTR_EN | GAHBCFG_DMA_EN | |
2465 | (GAHBCFG_HBSTLEN_INCR4 << GAHBCFG_HBSTLEN_SHIFT), | |
2466 | hsotg->regs + GAHBCFG); | |
308d734e | 2467 | else |
95c8bc36 AS |
2468 | dwc2_writel(((hsotg->dedicated_fifos) ? |
2469 | (GAHBCFG_NP_TXF_EMP_LVL | | |
2470 | GAHBCFG_P_TXF_EMP_LVL) : 0) | | |
2471 | GAHBCFG_GLBL_INTR_EN, hsotg->regs + GAHBCFG); | |
308d734e LM |
2472 | |
2473 | /* | |
8acc8296 RB |
2474 | * If INTknTXFEmpMsk is enabled, it's important to disable ep interrupts |
2475 | * when we have no data to transfer. Otherwise we get being flooded by | |
2476 | * interrupts. | |
308d734e LM |
2477 | */ |
2478 | ||
95c8bc36 | 2479 | dwc2_writel(((hsotg->dedicated_fifos && !using_dma(hsotg)) ? |
6ff2e832 | 2480 | DIEPMSK_TXFIFOEMPTY | DIEPMSK_INTKNTXFEMPMSK : 0) | |
47a1685f DN |
2481 | DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK | |
2482 | DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK | | |
2483 | DIEPMSK_INTKNEPMISMSK, | |
2484 | hsotg->regs + DIEPMSK); | |
308d734e LM |
2485 | |
2486 | /* | |
2487 | * don't need XferCompl, we get that from RXFIFO in slave mode. In | |
2488 | * DMA mode we may need this. | |
2489 | */ | |
95c8bc36 | 2490 | dwc2_writel((using_dma(hsotg) ? (DIEPMSK_XFERCOMPLMSK | |
47a1685f DN |
2491 | DIEPMSK_TIMEOUTMSK) : 0) | |
2492 | DOEPMSK_EPDISBLDMSK | DOEPMSK_AHBERRMSK | | |
2493 | DOEPMSK_SETUPMSK, | |
2494 | hsotg->regs + DOEPMSK); | |
308d734e | 2495 | |
95c8bc36 | 2496 | dwc2_writel(0, hsotg->regs + DAINTMSK); |
308d734e LM |
2497 | |
2498 | dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n", | |
95c8bc36 AS |
2499 | dwc2_readl(hsotg->regs + DIEPCTL0), |
2500 | dwc2_readl(hsotg->regs + DOEPCTL0)); | |
308d734e LM |
2501 | |
2502 | /* enable in and out endpoint interrupts */ | |
1f91b4cc | 2503 | dwc2_hsotg_en_gsint(hsotg, GINTSTS_OEPINT | GINTSTS_IEPINT); |
308d734e LM |
2504 | |
2505 | /* | |
2506 | * Enable the RXFIFO when in slave mode, as this is how we collect | |
2507 | * the data. In DMA mode, we get events from the FIFO but also | |
2508 | * things we cannot process, so do not use it. | |
2509 | */ | |
2510 | if (!using_dma(hsotg)) | |
1f91b4cc | 2511 | dwc2_hsotg_en_gsint(hsotg, GINTSTS_RXFLVL); |
308d734e LM |
2512 | |
2513 | /* Enable interrupts for EP0 in and out */ | |
1f91b4cc FB |
2514 | dwc2_hsotg_ctrl_epint(hsotg, 0, 0, 1); |
2515 | dwc2_hsotg_ctrl_epint(hsotg, 0, 1, 1); | |
308d734e | 2516 | |
643cc4de GH |
2517 | if (!is_usb_reset) { |
2518 | __orr32(hsotg->regs + DCTL, DCTL_PWRONPRGDONE); | |
2519 | udelay(10); /* see openiboot */ | |
2520 | __bic32(hsotg->regs + DCTL, DCTL_PWRONPRGDONE); | |
2521 | } | |
308d734e | 2522 | |
95c8bc36 | 2523 | dev_dbg(hsotg->dev, "DCTL=0x%08x\n", dwc2_readl(hsotg->regs + DCTL)); |
308d734e LM |
2524 | |
2525 | /* | |
94cb8fd6 | 2526 | * DxEPCTL_USBActEp says RO in manual, but seems to be set by |
308d734e LM |
2527 | * writing to the EPCTL register.. |
2528 | */ | |
2529 | ||
2530 | /* set to read 1 8byte packet */ | |
95c8bc36 | 2531 | dwc2_writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) | |
47a1685f | 2532 | DXEPTSIZ_XFERSIZE(8), hsotg->regs + DOEPTSIZ0); |
308d734e | 2533 | |
95c8bc36 | 2534 | dwc2_writel(dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) | |
47a1685f DN |
2535 | DXEPCTL_CNAK | DXEPCTL_EPENA | |
2536 | DXEPCTL_USBACTEP, | |
94cb8fd6 | 2537 | hsotg->regs + DOEPCTL0); |
308d734e LM |
2538 | |
2539 | /* enable, but don't activate EP0in */ | |
95c8bc36 | 2540 | dwc2_writel(dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) | |
47a1685f | 2541 | DXEPCTL_USBACTEP, hsotg->regs + DIEPCTL0); |
308d734e | 2542 | |
1f91b4cc | 2543 | dwc2_hsotg_enqueue_setup(hsotg); |
308d734e LM |
2544 | |
2545 | dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n", | |
95c8bc36 AS |
2546 | dwc2_readl(hsotg->regs + DIEPCTL0), |
2547 | dwc2_readl(hsotg->regs + DOEPCTL0)); | |
308d734e LM |
2548 | |
2549 | /* clear global NAKs */ | |
643cc4de GH |
2550 | val = DCTL_CGOUTNAK | DCTL_CGNPINNAK; |
2551 | if (!is_usb_reset) | |
2552 | val |= DCTL_SFTDISCON; | |
2553 | __orr32(hsotg->regs + DCTL, val); | |
308d734e LM |
2554 | |
2555 | /* must be at-least 3ms to allow bus to see disconnect */ | |
2556 | mdelay(3); | |
2557 | ||
065d3931 | 2558 | hsotg->lx_state = DWC2_L0; |
ad38dc5d MS |
2559 | } |
2560 | ||
1f91b4cc | 2561 | static void dwc2_hsotg_core_disconnect(struct dwc2_hsotg *hsotg) |
ad38dc5d MS |
2562 | { |
2563 | /* set the soft-disconnect bit */ | |
2564 | __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON); | |
2565 | } | |
ac3c81f3 | 2566 | |
1f91b4cc | 2567 | void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg) |
ad38dc5d | 2568 | { |
308d734e | 2569 | /* remove the soft-disconnect and let's go */ |
47a1685f | 2570 | __bic32(hsotg->regs + DCTL, DCTL_SFTDISCON); |
308d734e LM |
2571 | } |
2572 | ||
5b7d70c6 | 2573 | /** |
1f91b4cc | 2574 | * dwc2_hsotg_irq - handle device interrupt |
5b7d70c6 BD |
2575 | * @irq: The IRQ number triggered |
2576 | * @pw: The pw value when registered the handler. | |
2577 | */ | |
1f91b4cc | 2578 | static irqreturn_t dwc2_hsotg_irq(int irq, void *pw) |
5b7d70c6 | 2579 | { |
941fcce4 | 2580 | struct dwc2_hsotg *hsotg = pw; |
5b7d70c6 BD |
2581 | int retry_count = 8; |
2582 | u32 gintsts; | |
2583 | u32 gintmsk; | |
2584 | ||
ee3de8d7 VM |
2585 | if (!dwc2_is_device_mode(hsotg)) |
2586 | return IRQ_NONE; | |
2587 | ||
5ad1d316 | 2588 | spin_lock(&hsotg->lock); |
5b7d70c6 | 2589 | irq_retry: |
95c8bc36 AS |
2590 | gintsts = dwc2_readl(hsotg->regs + GINTSTS); |
2591 | gintmsk = dwc2_readl(hsotg->regs + GINTMSK); | |
5b7d70c6 BD |
2592 | |
2593 | dev_dbg(hsotg->dev, "%s: %08x %08x (%08x) retry %d\n", | |
2594 | __func__, gintsts, gintsts & gintmsk, gintmsk, retry_count); | |
2595 | ||
2596 | gintsts &= gintmsk; | |
2597 | ||
8fc37b82 MYK |
2598 | if (gintsts & GINTSTS_RESETDET) { |
2599 | dev_dbg(hsotg->dev, "%s: USBRstDet\n", __func__); | |
2600 | ||
2601 | dwc2_writel(GINTSTS_RESETDET, hsotg->regs + GINTSTS); | |
2602 | ||
2603 | /* This event must be used only if controller is suspended */ | |
2604 | if (hsotg->lx_state == DWC2_L2) { | |
2605 | dwc2_exit_hibernation(hsotg, true); | |
2606 | hsotg->lx_state = DWC2_L0; | |
2607 | } | |
2608 | } | |
2609 | ||
2610 | if (gintsts & (GINTSTS_USBRST | GINTSTS_RESETDET)) { | |
2611 | ||
2612 | u32 usb_status = dwc2_readl(hsotg->regs + GOTGCTL); | |
2613 | u32 connected = hsotg->connected; | |
2614 | ||
2615 | dev_dbg(hsotg->dev, "%s: USBRst\n", __func__); | |
2616 | dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n", | |
2617 | dwc2_readl(hsotg->regs + GNPTXSTS)); | |
2618 | ||
2619 | dwc2_writel(GINTSTS_USBRST, hsotg->regs + GINTSTS); | |
2620 | ||
2621 | /* Report disconnection if it is not already done. */ | |
2622 | dwc2_hsotg_disconnect(hsotg); | |
2623 | ||
2624 | if (usb_status & GOTGCTL_BSESVLD && connected) | |
2625 | dwc2_hsotg_core_init_disconnected(hsotg, true); | |
2626 | } | |
2627 | ||
47a1685f | 2628 | if (gintsts & GINTSTS_ENUMDONE) { |
95c8bc36 | 2629 | dwc2_writel(GINTSTS_ENUMDONE, hsotg->regs + GINTSTS); |
a3395f0d | 2630 | |
1f91b4cc | 2631 | dwc2_hsotg_irq_enumdone(hsotg); |
5b7d70c6 BD |
2632 | } |
2633 | ||
47a1685f | 2634 | if (gintsts & (GINTSTS_OEPINT | GINTSTS_IEPINT)) { |
95c8bc36 AS |
2635 | u32 daint = dwc2_readl(hsotg->regs + DAINT); |
2636 | u32 daintmsk = dwc2_readl(hsotg->regs + DAINTMSK); | |
7e804650 | 2637 | u32 daint_out, daint_in; |
5b7d70c6 BD |
2638 | int ep; |
2639 | ||
7e804650 | 2640 | daint &= daintmsk; |
47a1685f DN |
2641 | daint_out = daint >> DAINT_OUTEP_SHIFT; |
2642 | daint_in = daint & ~(daint_out << DAINT_OUTEP_SHIFT); | |
7e804650 | 2643 | |
5b7d70c6 BD |
2644 | dev_dbg(hsotg->dev, "%s: daint=%08x\n", __func__, daint); |
2645 | ||
cec87f1d MYK |
2646 | for (ep = 0; ep < hsotg->num_of_eps && daint_out; |
2647 | ep++, daint_out >>= 1) { | |
5b7d70c6 | 2648 | if (daint_out & 1) |
1f91b4cc | 2649 | dwc2_hsotg_epint(hsotg, ep, 0); |
5b7d70c6 BD |
2650 | } |
2651 | ||
cec87f1d MYK |
2652 | for (ep = 0; ep < hsotg->num_of_eps && daint_in; |
2653 | ep++, daint_in >>= 1) { | |
5b7d70c6 | 2654 | if (daint_in & 1) |
1f91b4cc | 2655 | dwc2_hsotg_epint(hsotg, ep, 1); |
5b7d70c6 | 2656 | } |
5b7d70c6 BD |
2657 | } |
2658 | ||
5b7d70c6 BD |
2659 | /* check both FIFOs */ |
2660 | ||
47a1685f | 2661 | if (gintsts & GINTSTS_NPTXFEMP) { |
5b7d70c6 BD |
2662 | dev_dbg(hsotg->dev, "NPTxFEmp\n"); |
2663 | ||
8b9bc460 LM |
2664 | /* |
2665 | * Disable the interrupt to stop it happening again | |
5b7d70c6 | 2666 | * unless one of these endpoint routines decides that |
8b9bc460 LM |
2667 | * it needs re-enabling |
2668 | */ | |
5b7d70c6 | 2669 | |
1f91b4cc FB |
2670 | dwc2_hsotg_disable_gsint(hsotg, GINTSTS_NPTXFEMP); |
2671 | dwc2_hsotg_irq_fifoempty(hsotg, false); | |
5b7d70c6 BD |
2672 | } |
2673 | ||
47a1685f | 2674 | if (gintsts & GINTSTS_PTXFEMP) { |
5b7d70c6 BD |
2675 | dev_dbg(hsotg->dev, "PTxFEmp\n"); |
2676 | ||
94cb8fd6 | 2677 | /* See note in GINTSTS_NPTxFEmp */ |
5b7d70c6 | 2678 | |
1f91b4cc FB |
2679 | dwc2_hsotg_disable_gsint(hsotg, GINTSTS_PTXFEMP); |
2680 | dwc2_hsotg_irq_fifoempty(hsotg, true); | |
5b7d70c6 BD |
2681 | } |
2682 | ||
47a1685f | 2683 | if (gintsts & GINTSTS_RXFLVL) { |
8b9bc460 LM |
2684 | /* |
2685 | * note, since GINTSTS_RxFLvl doubles as FIFO-not-empty, | |
1f91b4cc | 2686 | * we need to retry dwc2_hsotg_handle_rx if this is still |
8b9bc460 LM |
2687 | * set. |
2688 | */ | |
5b7d70c6 | 2689 | |
1f91b4cc | 2690 | dwc2_hsotg_handle_rx(hsotg); |
5b7d70c6 BD |
2691 | } |
2692 | ||
47a1685f | 2693 | if (gintsts & GINTSTS_ERLYSUSP) { |
94cb8fd6 | 2694 | dev_dbg(hsotg->dev, "GINTSTS_ErlySusp\n"); |
95c8bc36 | 2695 | dwc2_writel(GINTSTS_ERLYSUSP, hsotg->regs + GINTSTS); |
5b7d70c6 BD |
2696 | } |
2697 | ||
8b9bc460 LM |
2698 | /* |
2699 | * these next two seem to crop-up occasionally causing the core | |
5b7d70c6 | 2700 | * to shutdown the USB transfer, so try clearing them and logging |
8b9bc460 LM |
2701 | * the occurrence. |
2702 | */ | |
5b7d70c6 | 2703 | |
47a1685f | 2704 | if (gintsts & GINTSTS_GOUTNAKEFF) { |
5b7d70c6 BD |
2705 | dev_info(hsotg->dev, "GOUTNakEff triggered\n"); |
2706 | ||
3be99cd0 | 2707 | __orr32(hsotg->regs + DCTL, DCTL_CGOUTNAK); |
a3395f0d | 2708 | |
1f91b4cc | 2709 | dwc2_hsotg_dump(hsotg); |
5b7d70c6 BD |
2710 | } |
2711 | ||
47a1685f | 2712 | if (gintsts & GINTSTS_GINNAKEFF) { |
5b7d70c6 BD |
2713 | dev_info(hsotg->dev, "GINNakEff triggered\n"); |
2714 | ||
3be99cd0 | 2715 | __orr32(hsotg->regs + DCTL, DCTL_CGNPINNAK); |
a3395f0d | 2716 | |
1f91b4cc | 2717 | dwc2_hsotg_dump(hsotg); |
5b7d70c6 BD |
2718 | } |
2719 | ||
ec1f9d9f RB |
2720 | if (gintsts & GINTSTS_INCOMPL_SOIN) { |
2721 | u32 idx, epctl_reg; | |
2722 | struct dwc2_hsotg_ep *hs_ep; | |
2723 | ||
2724 | dev_dbg(hsotg->dev, "%s: GINTSTS_INCOMPL_SOIN\n", __func__); | |
2725 | for (idx = 1; idx < hsotg->num_of_eps; idx++) { | |
2726 | hs_ep = hsotg->eps_in[idx]; | |
2727 | ||
2728 | if (!hs_ep->isochronous || hs_ep->has_correct_parity) | |
2729 | continue; | |
2730 | ||
2731 | epctl_reg = DIEPCTL(idx); | |
2732 | dwc2_hsotg_change_ep_iso_parity(hsotg, epctl_reg); | |
2733 | } | |
2734 | dwc2_writel(GINTSTS_INCOMPL_SOIN, hsotg->regs + GINTSTS); | |
2735 | } | |
2736 | ||
2737 | if (gintsts & GINTSTS_INCOMPL_SOOUT) { | |
2738 | u32 idx, epctl_reg; | |
2739 | struct dwc2_hsotg_ep *hs_ep; | |
2740 | ||
2741 | dev_dbg(hsotg->dev, "%s: GINTSTS_INCOMPL_SOOUT\n", __func__); | |
2742 | for (idx = 1; idx < hsotg->num_of_eps; idx++) { | |
2743 | hs_ep = hsotg->eps_out[idx]; | |
2744 | ||
2745 | if (!hs_ep->isochronous || hs_ep->has_correct_parity) | |
2746 | continue; | |
2747 | ||
2748 | epctl_reg = DOEPCTL(idx); | |
2749 | dwc2_hsotg_change_ep_iso_parity(hsotg, epctl_reg); | |
2750 | } | |
2751 | dwc2_writel(GINTSTS_INCOMPL_SOOUT, hsotg->regs + GINTSTS); | |
2752 | } | |
2753 | ||
8b9bc460 LM |
2754 | /* |
2755 | * if we've had fifo events, we should try and go around the | |
2756 | * loop again to see if there's any point in returning yet. | |
2757 | */ | |
5b7d70c6 BD |
2758 | |
2759 | if (gintsts & IRQ_RETRY_MASK && --retry_count > 0) | |
2760 | goto irq_retry; | |
2761 | ||
5ad1d316 LM |
2762 | spin_unlock(&hsotg->lock); |
2763 | ||
5b7d70c6 BD |
2764 | return IRQ_HANDLED; |
2765 | } | |
2766 | ||
2767 | /** | |
1f91b4cc | 2768 | * dwc2_hsotg_ep_enable - enable the given endpoint |
5b7d70c6 BD |
2769 | * @ep: The USB endpint to configure |
2770 | * @desc: The USB endpoint descriptor to configure with. | |
2771 | * | |
2772 | * This is called from the USB gadget code's usb_ep_enable(). | |
8b9bc460 | 2773 | */ |
1f91b4cc | 2774 | static int dwc2_hsotg_ep_enable(struct usb_ep *ep, |
5b7d70c6 BD |
2775 | const struct usb_endpoint_descriptor *desc) |
2776 | { | |
1f91b4cc | 2777 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 2778 | struct dwc2_hsotg *hsotg = hs_ep->parent; |
5b7d70c6 | 2779 | unsigned long flags; |
ca4c55ad | 2780 | unsigned int index = hs_ep->index; |
5b7d70c6 BD |
2781 | u32 epctrl_reg; |
2782 | u32 epctrl; | |
2783 | u32 mps; | |
ca4c55ad MYK |
2784 | unsigned int dir_in; |
2785 | unsigned int i, val, size; | |
19c190f9 | 2786 | int ret = 0; |
5b7d70c6 BD |
2787 | |
2788 | dev_dbg(hsotg->dev, | |
2789 | "%s: ep %s: a 0x%02x, attr 0x%02x, mps 0x%04x, intr %d\n", | |
2790 | __func__, ep->name, desc->bEndpointAddress, desc->bmAttributes, | |
2791 | desc->wMaxPacketSize, desc->bInterval); | |
2792 | ||
2793 | /* not to be called for EP0 */ | |
8c3d6092 VA |
2794 | if (index == 0) { |
2795 | dev_err(hsotg->dev, "%s: called for EP 0\n", __func__); | |
2796 | return -EINVAL; | |
2797 | } | |
5b7d70c6 BD |
2798 | |
2799 | dir_in = (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) ? 1 : 0; | |
2800 | if (dir_in != hs_ep->dir_in) { | |
2801 | dev_err(hsotg->dev, "%s: direction mismatch!\n", __func__); | |
2802 | return -EINVAL; | |
2803 | } | |
2804 | ||
29cc8897 | 2805 | mps = usb_endpoint_maxp(desc); |
5b7d70c6 | 2806 | |
1f91b4cc | 2807 | /* note, we handle this here instead of dwc2_hsotg_set_ep_maxpacket */ |
5b7d70c6 | 2808 | |
94cb8fd6 | 2809 | epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index); |
95c8bc36 | 2810 | epctrl = dwc2_readl(hsotg->regs + epctrl_reg); |
5b7d70c6 BD |
2811 | |
2812 | dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x from 0x%08x\n", | |
2813 | __func__, epctrl, epctrl_reg); | |
2814 | ||
22258f49 | 2815 | spin_lock_irqsave(&hsotg->lock, flags); |
5b7d70c6 | 2816 | |
47a1685f DN |
2817 | epctrl &= ~(DXEPCTL_EPTYPE_MASK | DXEPCTL_MPS_MASK); |
2818 | epctrl |= DXEPCTL_MPS(mps); | |
5b7d70c6 | 2819 | |
8b9bc460 LM |
2820 | /* |
2821 | * mark the endpoint as active, otherwise the core may ignore | |
2822 | * transactions entirely for this endpoint | |
2823 | */ | |
47a1685f | 2824 | epctrl |= DXEPCTL_USBACTEP; |
5b7d70c6 | 2825 | |
8b9bc460 LM |
2826 | /* |
2827 | * set the NAK status on the endpoint, otherwise we might try and | |
5b7d70c6 BD |
2828 | * do something with data that we've yet got a request to process |
2829 | * since the RXFIFO will take data for an endpoint even if the | |
2830 | * size register hasn't been set. | |
2831 | */ | |
2832 | ||
47a1685f | 2833 | epctrl |= DXEPCTL_SNAK; |
5b7d70c6 BD |
2834 | |
2835 | /* update the endpoint state */ | |
1f91b4cc | 2836 | dwc2_hsotg_set_ep_maxpacket(hsotg, hs_ep->index, mps, dir_in); |
5b7d70c6 BD |
2837 | |
2838 | /* default, set to non-periodic */ | |
1479e841 | 2839 | hs_ep->isochronous = 0; |
5b7d70c6 | 2840 | hs_ep->periodic = 0; |
a18ed7b0 | 2841 | hs_ep->halted = 0; |
1479e841 | 2842 | hs_ep->interval = desc->bInterval; |
4fca54aa | 2843 | |
5b7d70c6 BD |
2844 | switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) { |
2845 | case USB_ENDPOINT_XFER_ISOC: | |
47a1685f DN |
2846 | epctrl |= DXEPCTL_EPTYPE_ISO; |
2847 | epctrl |= DXEPCTL_SETEVENFR; | |
1479e841 | 2848 | hs_ep->isochronous = 1; |
142bd33f | 2849 | hs_ep->interval = 1 << (desc->bInterval - 1); |
1479e841 RB |
2850 | if (dir_in) |
2851 | hs_ep->periodic = 1; | |
2852 | break; | |
5b7d70c6 BD |
2853 | |
2854 | case USB_ENDPOINT_XFER_BULK: | |
47a1685f | 2855 | epctrl |= DXEPCTL_EPTYPE_BULK; |
5b7d70c6 BD |
2856 | break; |
2857 | ||
2858 | case USB_ENDPOINT_XFER_INT: | |
b203d0a2 | 2859 | if (dir_in) |
5b7d70c6 | 2860 | hs_ep->periodic = 1; |
5b7d70c6 | 2861 | |
142bd33f VM |
2862 | if (hsotg->gadget.speed == USB_SPEED_HIGH) |
2863 | hs_ep->interval = 1 << (desc->bInterval - 1); | |
2864 | ||
47a1685f | 2865 | epctrl |= DXEPCTL_EPTYPE_INTERRUPT; |
5b7d70c6 BD |
2866 | break; |
2867 | ||
2868 | case USB_ENDPOINT_XFER_CONTROL: | |
47a1685f | 2869 | epctrl |= DXEPCTL_EPTYPE_CONTROL; |
5b7d70c6 BD |
2870 | break; |
2871 | } | |
2872 | ||
4556e12c MYK |
2873 | /* If fifo is already allocated for this ep */ |
2874 | if (hs_ep->fifo_index) { | |
2875 | size = hs_ep->ep.maxpacket * hs_ep->mc; | |
2876 | /* If bigger fifo is required deallocate current one */ | |
2877 | if (size > hs_ep->fifo_size) { | |
2878 | hsotg->fifo_map &= ~(1 << hs_ep->fifo_index); | |
2879 | hs_ep->fifo_index = 0; | |
2880 | hs_ep->fifo_size = 0; | |
2881 | } | |
2882 | } | |
2883 | ||
8b9bc460 LM |
2884 | /* |
2885 | * if the hardware has dedicated fifos, we must give each IN EP | |
10aebc77 BD |
2886 | * a unique tx-fifo even if it is non-periodic. |
2887 | */ | |
4556e12c | 2888 | if (dir_in && hsotg->dedicated_fifos && !hs_ep->fifo_index) { |
ca4c55ad MYK |
2889 | u32 fifo_index = 0; |
2890 | u32 fifo_size = UINT_MAX; | |
b203d0a2 | 2891 | size = hs_ep->ep.maxpacket*hs_ep->mc; |
5f2196bd | 2892 | for (i = 1; i < hsotg->num_of_eps; ++i) { |
b203d0a2 RB |
2893 | if (hsotg->fifo_map & (1<<i)) |
2894 | continue; | |
95c8bc36 | 2895 | val = dwc2_readl(hsotg->regs + DPTXFSIZN(i)); |
b203d0a2 RB |
2896 | val = (val >> FIFOSIZE_DEPTH_SHIFT)*4; |
2897 | if (val < size) | |
2898 | continue; | |
ca4c55ad MYK |
2899 | /* Search for smallest acceptable fifo */ |
2900 | if (val < fifo_size) { | |
2901 | fifo_size = val; | |
2902 | fifo_index = i; | |
2903 | } | |
b203d0a2 | 2904 | } |
ca4c55ad | 2905 | if (!fifo_index) { |
5f2196bd MYK |
2906 | dev_err(hsotg->dev, |
2907 | "%s: No suitable fifo found\n", __func__); | |
b585a48b SM |
2908 | ret = -ENOMEM; |
2909 | goto error; | |
2910 | } | |
ca4c55ad MYK |
2911 | hsotg->fifo_map |= 1 << fifo_index; |
2912 | epctrl |= DXEPCTL_TXFNUM(fifo_index); | |
2913 | hs_ep->fifo_index = fifo_index; | |
2914 | hs_ep->fifo_size = fifo_size; | |
b203d0a2 | 2915 | } |
10aebc77 | 2916 | |
5b7d70c6 BD |
2917 | /* for non control endpoints, set PID to D0 */ |
2918 | if (index) | |
47a1685f | 2919 | epctrl |= DXEPCTL_SETD0PID; |
5b7d70c6 BD |
2920 | |
2921 | dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n", | |
2922 | __func__, epctrl); | |
2923 | ||
95c8bc36 | 2924 | dwc2_writel(epctrl, hsotg->regs + epctrl_reg); |
5b7d70c6 | 2925 | dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x\n", |
95c8bc36 | 2926 | __func__, dwc2_readl(hsotg->regs + epctrl_reg)); |
5b7d70c6 BD |
2927 | |
2928 | /* enable the endpoint interrupt */ | |
1f91b4cc | 2929 | dwc2_hsotg_ctrl_epint(hsotg, index, dir_in, 1); |
5b7d70c6 | 2930 | |
b585a48b | 2931 | error: |
22258f49 | 2932 | spin_unlock_irqrestore(&hsotg->lock, flags); |
19c190f9 | 2933 | return ret; |
5b7d70c6 BD |
2934 | } |
2935 | ||
8b9bc460 | 2936 | /** |
1f91b4cc | 2937 | * dwc2_hsotg_ep_disable - disable given endpoint |
8b9bc460 LM |
2938 | * @ep: The endpoint to disable. |
2939 | */ | |
1f91b4cc | 2940 | static int dwc2_hsotg_ep_disable(struct usb_ep *ep) |
5b7d70c6 | 2941 | { |
1f91b4cc | 2942 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 2943 | struct dwc2_hsotg *hsotg = hs_ep->parent; |
5b7d70c6 BD |
2944 | int dir_in = hs_ep->dir_in; |
2945 | int index = hs_ep->index; | |
2946 | unsigned long flags; | |
2947 | u32 epctrl_reg; | |
2948 | u32 ctrl; | |
2949 | ||
1e011293 | 2950 | dev_dbg(hsotg->dev, "%s(ep %p)\n", __func__, ep); |
5b7d70c6 | 2951 | |
c6f5c050 | 2952 | if (ep == &hsotg->eps_out[0]->ep) { |
5b7d70c6 BD |
2953 | dev_err(hsotg->dev, "%s: called for ep0\n", __func__); |
2954 | return -EINVAL; | |
2955 | } | |
2956 | ||
94cb8fd6 | 2957 | epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index); |
5b7d70c6 | 2958 | |
5ad1d316 | 2959 | spin_lock_irqsave(&hsotg->lock, flags); |
5b7d70c6 | 2960 | |
b203d0a2 RB |
2961 | hsotg->fifo_map &= ~(1<<hs_ep->fifo_index); |
2962 | hs_ep->fifo_index = 0; | |
2963 | hs_ep->fifo_size = 0; | |
5b7d70c6 | 2964 | |
95c8bc36 | 2965 | ctrl = dwc2_readl(hsotg->regs + epctrl_reg); |
47a1685f DN |
2966 | ctrl &= ~DXEPCTL_EPENA; |
2967 | ctrl &= ~DXEPCTL_USBACTEP; | |
2968 | ctrl |= DXEPCTL_SNAK; | |
5b7d70c6 BD |
2969 | |
2970 | dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl); | |
95c8bc36 | 2971 | dwc2_writel(ctrl, hsotg->regs + epctrl_reg); |
5b7d70c6 BD |
2972 | |
2973 | /* disable endpoint interrupts */ | |
1f91b4cc | 2974 | dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 0); |
5b7d70c6 | 2975 | |
1141ea01 MYK |
2976 | /* terminate all requests with shutdown */ |
2977 | kill_all_requests(hsotg, hs_ep, -ESHUTDOWN); | |
2978 | ||
22258f49 | 2979 | spin_unlock_irqrestore(&hsotg->lock, flags); |
5b7d70c6 BD |
2980 | return 0; |
2981 | } | |
2982 | ||
2983 | /** | |
2984 | * on_list - check request is on the given endpoint | |
2985 | * @ep: The endpoint to check. | |
2986 | * @test: The request to test if it is on the endpoint. | |
8b9bc460 | 2987 | */ |
1f91b4cc | 2988 | static bool on_list(struct dwc2_hsotg_ep *ep, struct dwc2_hsotg_req *test) |
5b7d70c6 | 2989 | { |
1f91b4cc | 2990 | struct dwc2_hsotg_req *req, *treq; |
5b7d70c6 BD |
2991 | |
2992 | list_for_each_entry_safe(req, treq, &ep->queue, queue) { | |
2993 | if (req == test) | |
2994 | return true; | |
2995 | } | |
2996 | ||
2997 | return false; | |
2998 | } | |
2999 | ||
c524dd5f MYK |
3000 | static int dwc2_hsotg_wait_bit_set(struct dwc2_hsotg *hs_otg, u32 reg, |
3001 | u32 bit, u32 timeout) | |
3002 | { | |
3003 | u32 i; | |
3004 | ||
3005 | for (i = 0; i < timeout; i++) { | |
3006 | if (dwc2_readl(hs_otg->regs + reg) & bit) | |
3007 | return 0; | |
3008 | udelay(1); | |
3009 | } | |
3010 | ||
3011 | return -ETIMEDOUT; | |
3012 | } | |
3013 | ||
3014 | static void dwc2_hsotg_ep_stop_xfr(struct dwc2_hsotg *hsotg, | |
3015 | struct dwc2_hsotg_ep *hs_ep) | |
3016 | { | |
3017 | u32 epctrl_reg; | |
3018 | u32 epint_reg; | |
3019 | ||
3020 | epctrl_reg = hs_ep->dir_in ? DIEPCTL(hs_ep->index) : | |
3021 | DOEPCTL(hs_ep->index); | |
3022 | epint_reg = hs_ep->dir_in ? DIEPINT(hs_ep->index) : | |
3023 | DOEPINT(hs_ep->index); | |
3024 | ||
3025 | dev_dbg(hsotg->dev, "%s: stopping transfer on %s\n", __func__, | |
3026 | hs_ep->name); | |
3027 | if (hs_ep->dir_in) { | |
3028 | __orr32(hsotg->regs + epctrl_reg, DXEPCTL_SNAK); | |
3029 | /* Wait for Nak effect */ | |
3030 | if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg, | |
3031 | DXEPINT_INEPNAKEFF, 100)) | |
3032 | dev_warn(hsotg->dev, | |
3033 | "%s: timeout DIEPINT.NAKEFF\n", __func__); | |
3034 | } else { | |
6b58cb07 VM |
3035 | if (!(dwc2_readl(hsotg->regs + GINTSTS) & GINTSTS_GOUTNAKEFF)) |
3036 | __orr32(hsotg->regs + DCTL, DCTL_SGOUTNAK); | |
c524dd5f MYK |
3037 | |
3038 | /* Wait for global nak to take effect */ | |
3039 | if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS, | |
0676c7e7 | 3040 | GINTSTS_GOUTNAKEFF, 100)) |
c524dd5f | 3041 | dev_warn(hsotg->dev, |
0676c7e7 | 3042 | "%s: timeout GINTSTS.GOUTNAKEFF\n", __func__); |
c524dd5f MYK |
3043 | } |
3044 | ||
3045 | /* Disable ep */ | |
3046 | __orr32(hsotg->regs + epctrl_reg, DXEPCTL_EPDIS | DXEPCTL_SNAK); | |
3047 | ||
3048 | /* Wait for ep to be disabled */ | |
3049 | if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg, DXEPINT_EPDISBLD, 100)) | |
3050 | dev_warn(hsotg->dev, | |
3051 | "%s: timeout DOEPCTL.EPDisable\n", __func__); | |
3052 | ||
3053 | if (hs_ep->dir_in) { | |
3054 | if (hsotg->dedicated_fifos) { | |
3055 | dwc2_writel(GRSTCTL_TXFNUM(hs_ep->fifo_index) | | |
3056 | GRSTCTL_TXFFLSH, hsotg->regs + GRSTCTL); | |
3057 | /* Wait for fifo flush */ | |
3058 | if (dwc2_hsotg_wait_bit_set(hsotg, GRSTCTL, | |
3059 | GRSTCTL_TXFFLSH, 100)) | |
3060 | dev_warn(hsotg->dev, | |
3061 | "%s: timeout flushing fifos\n", | |
3062 | __func__); | |
3063 | } | |
3064 | /* TODO: Flush shared tx fifo */ | |
3065 | } else { | |
3066 | /* Remove global NAKs */ | |
0676c7e7 | 3067 | __bic32(hsotg->regs + DCTL, DCTL_SGOUTNAK); |
c524dd5f MYK |
3068 | } |
3069 | } | |
3070 | ||
8b9bc460 | 3071 | /** |
1f91b4cc | 3072 | * dwc2_hsotg_ep_dequeue - dequeue given endpoint |
8b9bc460 LM |
3073 | * @ep: The endpoint to dequeue. |
3074 | * @req: The request to be removed from a queue. | |
3075 | */ | |
1f91b4cc | 3076 | static int dwc2_hsotg_ep_dequeue(struct usb_ep *ep, struct usb_request *req) |
5b7d70c6 | 3077 | { |
1f91b4cc FB |
3078 | struct dwc2_hsotg_req *hs_req = our_req(req); |
3079 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); | |
941fcce4 | 3080 | struct dwc2_hsotg *hs = hs_ep->parent; |
5b7d70c6 BD |
3081 | unsigned long flags; |
3082 | ||
1e011293 | 3083 | dev_dbg(hs->dev, "ep_dequeue(%p,%p)\n", ep, req); |
5b7d70c6 | 3084 | |
22258f49 | 3085 | spin_lock_irqsave(&hs->lock, flags); |
5b7d70c6 BD |
3086 | |
3087 | if (!on_list(hs_ep, hs_req)) { | |
22258f49 | 3088 | spin_unlock_irqrestore(&hs->lock, flags); |
5b7d70c6 BD |
3089 | return -EINVAL; |
3090 | } | |
3091 | ||
c524dd5f MYK |
3092 | /* Dequeue already started request */ |
3093 | if (req == &hs_ep->req->req) | |
3094 | dwc2_hsotg_ep_stop_xfr(hs, hs_ep); | |
3095 | ||
1f91b4cc | 3096 | dwc2_hsotg_complete_request(hs, hs_ep, hs_req, -ECONNRESET); |
22258f49 | 3097 | spin_unlock_irqrestore(&hs->lock, flags); |
5b7d70c6 BD |
3098 | |
3099 | return 0; | |
3100 | } | |
3101 | ||
8b9bc460 | 3102 | /** |
1f91b4cc | 3103 | * dwc2_hsotg_ep_sethalt - set halt on a given endpoint |
8b9bc460 LM |
3104 | * @ep: The endpoint to set halt. |
3105 | * @value: Set or unset the halt. | |
51da43b5 VA |
3106 | * @now: If true, stall the endpoint now. Otherwise return -EAGAIN if |
3107 | * the endpoint is busy processing requests. | |
3108 | * | |
3109 | * We need to stall the endpoint immediately if request comes from set_feature | |
3110 | * protocol command handler. | |
8b9bc460 | 3111 | */ |
51da43b5 | 3112 | static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now) |
5b7d70c6 | 3113 | { |
1f91b4cc | 3114 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 3115 | struct dwc2_hsotg *hs = hs_ep->parent; |
5b7d70c6 | 3116 | int index = hs_ep->index; |
5b7d70c6 BD |
3117 | u32 epreg; |
3118 | u32 epctl; | |
9c39ddc6 | 3119 | u32 xfertype; |
5b7d70c6 BD |
3120 | |
3121 | dev_info(hs->dev, "%s(ep %p %s, %d)\n", __func__, ep, ep->name, value); | |
3122 | ||
c9f721b2 RB |
3123 | if (index == 0) { |
3124 | if (value) | |
1f91b4cc | 3125 | dwc2_hsotg_stall_ep0(hs); |
c9f721b2 RB |
3126 | else |
3127 | dev_warn(hs->dev, | |
3128 | "%s: can't clear halt on ep0\n", __func__); | |
3129 | return 0; | |
3130 | } | |
3131 | ||
15186f10 VA |
3132 | if (hs_ep->isochronous) { |
3133 | dev_err(hs->dev, "%s is Isochronous Endpoint\n", ep->name); | |
3134 | return -EINVAL; | |
3135 | } | |
3136 | ||
51da43b5 VA |
3137 | if (!now && value && !list_empty(&hs_ep->queue)) { |
3138 | dev_dbg(hs->dev, "%s request is pending, cannot halt\n", | |
3139 | ep->name); | |
3140 | return -EAGAIN; | |
3141 | } | |
3142 | ||
c6f5c050 MYK |
3143 | if (hs_ep->dir_in) { |
3144 | epreg = DIEPCTL(index); | |
95c8bc36 | 3145 | epctl = dwc2_readl(hs->regs + epreg); |
c6f5c050 MYK |
3146 | |
3147 | if (value) { | |
5a350d53 | 3148 | epctl |= DXEPCTL_STALL | DXEPCTL_SNAK; |
c6f5c050 MYK |
3149 | if (epctl & DXEPCTL_EPENA) |
3150 | epctl |= DXEPCTL_EPDIS; | |
3151 | } else { | |
3152 | epctl &= ~DXEPCTL_STALL; | |
3153 | xfertype = epctl & DXEPCTL_EPTYPE_MASK; | |
3154 | if (xfertype == DXEPCTL_EPTYPE_BULK || | |
3155 | xfertype == DXEPCTL_EPTYPE_INTERRUPT) | |
3156 | epctl |= DXEPCTL_SETD0PID; | |
3157 | } | |
95c8bc36 | 3158 | dwc2_writel(epctl, hs->regs + epreg); |
9c39ddc6 | 3159 | } else { |
5b7d70c6 | 3160 | |
c6f5c050 | 3161 | epreg = DOEPCTL(index); |
95c8bc36 | 3162 | epctl = dwc2_readl(hs->regs + epreg); |
5b7d70c6 | 3163 | |
c6f5c050 MYK |
3164 | if (value) |
3165 | epctl |= DXEPCTL_STALL; | |
3166 | else { | |
3167 | epctl &= ~DXEPCTL_STALL; | |
3168 | xfertype = epctl & DXEPCTL_EPTYPE_MASK; | |
3169 | if (xfertype == DXEPCTL_EPTYPE_BULK || | |
3170 | xfertype == DXEPCTL_EPTYPE_INTERRUPT) | |
3171 | epctl |= DXEPCTL_SETD0PID; | |
3172 | } | |
95c8bc36 | 3173 | dwc2_writel(epctl, hs->regs + epreg); |
9c39ddc6 | 3174 | } |
5b7d70c6 | 3175 | |
a18ed7b0 RB |
3176 | hs_ep->halted = value; |
3177 | ||
5b7d70c6 BD |
3178 | return 0; |
3179 | } | |
3180 | ||
5ad1d316 | 3181 | /** |
1f91b4cc | 3182 | * dwc2_hsotg_ep_sethalt_lock - set halt on a given endpoint with lock held |
5ad1d316 LM |
3183 | * @ep: The endpoint to set halt. |
3184 | * @value: Set or unset the halt. | |
3185 | */ | |
1f91b4cc | 3186 | static int dwc2_hsotg_ep_sethalt_lock(struct usb_ep *ep, int value) |
5ad1d316 | 3187 | { |
1f91b4cc | 3188 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 3189 | struct dwc2_hsotg *hs = hs_ep->parent; |
5ad1d316 LM |
3190 | unsigned long flags = 0; |
3191 | int ret = 0; | |
3192 | ||
3193 | spin_lock_irqsave(&hs->lock, flags); | |
51da43b5 | 3194 | ret = dwc2_hsotg_ep_sethalt(ep, value, false); |
5ad1d316 LM |
3195 | spin_unlock_irqrestore(&hs->lock, flags); |
3196 | ||
3197 | return ret; | |
3198 | } | |
3199 | ||
1f91b4cc FB |
3200 | static struct usb_ep_ops dwc2_hsotg_ep_ops = { |
3201 | .enable = dwc2_hsotg_ep_enable, | |
3202 | .disable = dwc2_hsotg_ep_disable, | |
3203 | .alloc_request = dwc2_hsotg_ep_alloc_request, | |
3204 | .free_request = dwc2_hsotg_ep_free_request, | |
3205 | .queue = dwc2_hsotg_ep_queue_lock, | |
3206 | .dequeue = dwc2_hsotg_ep_dequeue, | |
3207 | .set_halt = dwc2_hsotg_ep_sethalt_lock, | |
25985edc | 3208 | /* note, don't believe we have any call for the fifo routines */ |
5b7d70c6 BD |
3209 | }; |
3210 | ||
8b9bc460 | 3211 | /** |
1f91b4cc | 3212 | * dwc2_hsotg_init - initalize the usb core |
8b9bc460 LM |
3213 | * @hsotg: The driver state |
3214 | */ | |
1f91b4cc | 3215 | static void dwc2_hsotg_init(struct dwc2_hsotg *hsotg) |
b3f489b2 | 3216 | { |
fa4a8d72 | 3217 | u32 trdtim; |
ecd9a7ad | 3218 | u32 usbcfg; |
b3f489b2 LM |
3219 | /* unmask subset of endpoint interrupts */ |
3220 | ||
95c8bc36 AS |
3221 | dwc2_writel(DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK | |
3222 | DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK, | |
3223 | hsotg->regs + DIEPMSK); | |
b3f489b2 | 3224 | |
95c8bc36 AS |
3225 | dwc2_writel(DOEPMSK_SETUPMSK | DOEPMSK_AHBERRMSK | |
3226 | DOEPMSK_EPDISBLDMSK | DOEPMSK_XFERCOMPLMSK, | |
3227 | hsotg->regs + DOEPMSK); | |
b3f489b2 | 3228 | |
95c8bc36 | 3229 | dwc2_writel(0, hsotg->regs + DAINTMSK); |
b3f489b2 LM |
3230 | |
3231 | /* Be in disconnected state until gadget is registered */ | |
47a1685f | 3232 | __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON); |
b3f489b2 | 3233 | |
b3f489b2 LM |
3234 | /* setup fifos */ |
3235 | ||
3236 | dev_dbg(hsotg->dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n", | |
95c8bc36 AS |
3237 | dwc2_readl(hsotg->regs + GRXFSIZ), |
3238 | dwc2_readl(hsotg->regs + GNPTXFSIZ)); | |
b3f489b2 | 3239 | |
1f91b4cc | 3240 | dwc2_hsotg_init_fifo(hsotg); |
b3f489b2 | 3241 | |
ecd9a7ad PR |
3242 | /* keep other bits untouched (so e.g. forced modes are not lost) */ |
3243 | usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); | |
3244 | usbcfg &= ~(GUSBCFG_TOUTCAL_MASK | GUSBCFG_PHYIF16 | GUSBCFG_SRPCAP | | |
3245 | GUSBCFG_HNPCAP); | |
3246 | ||
b3f489b2 | 3247 | /* set the PLL on, remove the HNP/SRP and set the PHY */ |
fa4a8d72 | 3248 | trdtim = (hsotg->phyif == GUSBCFG_PHYIF8) ? 9 : 5; |
ecd9a7ad PR |
3249 | usbcfg |= hsotg->phyif | GUSBCFG_TOUTCAL(7) | |
3250 | (trdtim << GUSBCFG_USBTRDTIM_SHIFT); | |
3251 | dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); | |
b3f489b2 | 3252 | |
f5090044 GH |
3253 | if (using_dma(hsotg)) |
3254 | __orr32(hsotg->regs + GAHBCFG, GAHBCFG_DMA_EN); | |
b3f489b2 LM |
3255 | } |
3256 | ||
8b9bc460 | 3257 | /** |
1f91b4cc | 3258 | * dwc2_hsotg_udc_start - prepare the udc for work |
8b9bc460 LM |
3259 | * @gadget: The usb gadget state |
3260 | * @driver: The usb gadget driver | |
3261 | * | |
3262 | * Perform initialization to prepare udc device and driver | |
3263 | * to work. | |
3264 | */ | |
1f91b4cc | 3265 | static int dwc2_hsotg_udc_start(struct usb_gadget *gadget, |
f65f0f10 | 3266 | struct usb_gadget_driver *driver) |
5b7d70c6 | 3267 | { |
941fcce4 | 3268 | struct dwc2_hsotg *hsotg = to_hsotg(gadget); |
5b9451f8 | 3269 | unsigned long flags; |
5b7d70c6 BD |
3270 | int ret; |
3271 | ||
3272 | if (!hsotg) { | |
a023da33 | 3273 | pr_err("%s: called with no device\n", __func__); |
5b7d70c6 BD |
3274 | return -ENODEV; |
3275 | } | |
3276 | ||
3277 | if (!driver) { | |
3278 | dev_err(hsotg->dev, "%s: no driver\n", __func__); | |
3279 | return -EINVAL; | |
3280 | } | |
3281 | ||
7177aed4 | 3282 | if (driver->max_speed < USB_SPEED_FULL) |
5b7d70c6 | 3283 | dev_err(hsotg->dev, "%s: bad speed\n", __func__); |
5b7d70c6 | 3284 | |
f65f0f10 | 3285 | if (!driver->setup) { |
5b7d70c6 BD |
3286 | dev_err(hsotg->dev, "%s: missing entry points\n", __func__); |
3287 | return -EINVAL; | |
3288 | } | |
3289 | ||
3290 | WARN_ON(hsotg->driver); | |
3291 | ||
3292 | driver->driver.bus = NULL; | |
3293 | hsotg->driver = driver; | |
7d7b2292 | 3294 | hsotg->gadget.dev.of_node = hsotg->dev->of_node; |
5b7d70c6 BD |
3295 | hsotg->gadget.speed = USB_SPEED_UNKNOWN; |
3296 | ||
09a75e85 MS |
3297 | if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) { |
3298 | ret = dwc2_lowlevel_hw_enable(hsotg); | |
3299 | if (ret) | |
3300 | goto err; | |
5b7d70c6 BD |
3301 | } |
3302 | ||
f6c01592 GH |
3303 | if (!IS_ERR_OR_NULL(hsotg->uphy)) |
3304 | otg_set_peripheral(hsotg->uphy->otg, &hsotg->gadget); | |
c816c47f | 3305 | |
5b9451f8 | 3306 | spin_lock_irqsave(&hsotg->lock, flags); |
1f91b4cc FB |
3307 | dwc2_hsotg_init(hsotg); |
3308 | dwc2_hsotg_core_init_disconnected(hsotg, false); | |
dc6e69e6 | 3309 | hsotg->enabled = 0; |
5b9451f8 MS |
3310 | spin_unlock_irqrestore(&hsotg->lock, flags); |
3311 | ||
5b7d70c6 | 3312 | dev_info(hsotg->dev, "bound driver %s\n", driver->driver.name); |
5b9451f8 | 3313 | |
5b7d70c6 BD |
3314 | return 0; |
3315 | ||
3316 | err: | |
3317 | hsotg->driver = NULL; | |
5b7d70c6 BD |
3318 | return ret; |
3319 | } | |
3320 | ||
8b9bc460 | 3321 | /** |
1f91b4cc | 3322 | * dwc2_hsotg_udc_stop - stop the udc |
8b9bc460 LM |
3323 | * @gadget: The usb gadget state |
3324 | * @driver: The usb gadget driver | |
3325 | * | |
3326 | * Stop udc hw block and stay tunned for future transmissions | |
3327 | */ | |
1f91b4cc | 3328 | static int dwc2_hsotg_udc_stop(struct usb_gadget *gadget) |
5b7d70c6 | 3329 | { |
941fcce4 | 3330 | struct dwc2_hsotg *hsotg = to_hsotg(gadget); |
2b19a52c | 3331 | unsigned long flags = 0; |
5b7d70c6 BD |
3332 | int ep; |
3333 | ||
3334 | if (!hsotg) | |
3335 | return -ENODEV; | |
3336 | ||
5b7d70c6 | 3337 | /* all endpoints should be shutdown */ |
c6f5c050 MYK |
3338 | for (ep = 1; ep < hsotg->num_of_eps; ep++) { |
3339 | if (hsotg->eps_in[ep]) | |
1f91b4cc | 3340 | dwc2_hsotg_ep_disable(&hsotg->eps_in[ep]->ep); |
c6f5c050 | 3341 | if (hsotg->eps_out[ep]) |
1f91b4cc | 3342 | dwc2_hsotg_ep_disable(&hsotg->eps_out[ep]->ep); |
c6f5c050 | 3343 | } |
5b7d70c6 | 3344 | |
2b19a52c LM |
3345 | spin_lock_irqsave(&hsotg->lock, flags); |
3346 | ||
32805c35 | 3347 | hsotg->driver = NULL; |
5b7d70c6 | 3348 | hsotg->gadget.speed = USB_SPEED_UNKNOWN; |
dc6e69e6 | 3349 | hsotg->enabled = 0; |
5b7d70c6 | 3350 | |
2b19a52c LM |
3351 | spin_unlock_irqrestore(&hsotg->lock, flags); |
3352 | ||
f6c01592 GH |
3353 | if (!IS_ERR_OR_NULL(hsotg->uphy)) |
3354 | otg_set_peripheral(hsotg->uphy->otg, NULL); | |
c816c47f | 3355 | |
09a75e85 MS |
3356 | if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) |
3357 | dwc2_lowlevel_hw_disable(hsotg); | |
5b7d70c6 BD |
3358 | |
3359 | return 0; | |
3360 | } | |
5b7d70c6 | 3361 | |
8b9bc460 | 3362 | /** |
1f91b4cc | 3363 | * dwc2_hsotg_gadget_getframe - read the frame number |
8b9bc460 LM |
3364 | * @gadget: The usb gadget state |
3365 | * | |
3366 | * Read the {micro} frame number | |
3367 | */ | |
1f91b4cc | 3368 | static int dwc2_hsotg_gadget_getframe(struct usb_gadget *gadget) |
5b7d70c6 | 3369 | { |
1f91b4cc | 3370 | return dwc2_hsotg_read_frameno(to_hsotg(gadget)); |
5b7d70c6 BD |
3371 | } |
3372 | ||
a188b689 | 3373 | /** |
1f91b4cc | 3374 | * dwc2_hsotg_pullup - connect/disconnect the USB PHY |
a188b689 LM |
3375 | * @gadget: The usb gadget state |
3376 | * @is_on: Current state of the USB PHY | |
3377 | * | |
3378 | * Connect/Disconnect the USB PHY pullup | |
3379 | */ | |
1f91b4cc | 3380 | static int dwc2_hsotg_pullup(struct usb_gadget *gadget, int is_on) |
a188b689 | 3381 | { |
941fcce4 | 3382 | struct dwc2_hsotg *hsotg = to_hsotg(gadget); |
a188b689 LM |
3383 | unsigned long flags = 0; |
3384 | ||
77ba9119 GH |
3385 | dev_dbg(hsotg->dev, "%s: is_on: %d op_state: %d\n", __func__, is_on, |
3386 | hsotg->op_state); | |
3387 | ||
3388 | /* Don't modify pullup state while in host mode */ | |
3389 | if (hsotg->op_state != OTG_STATE_B_PERIPHERAL) { | |
3390 | hsotg->enabled = is_on; | |
3391 | return 0; | |
3392 | } | |
a188b689 LM |
3393 | |
3394 | spin_lock_irqsave(&hsotg->lock, flags); | |
3395 | if (is_on) { | |
dc6e69e6 | 3396 | hsotg->enabled = 1; |
1f91b4cc FB |
3397 | dwc2_hsotg_core_init_disconnected(hsotg, false); |
3398 | dwc2_hsotg_core_connect(hsotg); | |
a188b689 | 3399 | } else { |
1f91b4cc FB |
3400 | dwc2_hsotg_core_disconnect(hsotg); |
3401 | dwc2_hsotg_disconnect(hsotg); | |
dc6e69e6 | 3402 | hsotg->enabled = 0; |
a188b689 LM |
3403 | } |
3404 | ||
3405 | hsotg->gadget.speed = USB_SPEED_UNKNOWN; | |
3406 | spin_unlock_irqrestore(&hsotg->lock, flags); | |
3407 | ||
3408 | return 0; | |
3409 | } | |
3410 | ||
1f91b4cc | 3411 | static int dwc2_hsotg_vbus_session(struct usb_gadget *gadget, int is_active) |
83d98223 GH |
3412 | { |
3413 | struct dwc2_hsotg *hsotg = to_hsotg(gadget); | |
3414 | unsigned long flags; | |
3415 | ||
3416 | dev_dbg(hsotg->dev, "%s: is_active: %d\n", __func__, is_active); | |
3417 | spin_lock_irqsave(&hsotg->lock, flags); | |
3418 | ||
61f7223b GH |
3419 | /* |
3420 | * If controller is hibernated, it must exit from hibernation | |
3421 | * before being initialized / de-initialized | |
3422 | */ | |
3423 | if (hsotg->lx_state == DWC2_L2) | |
3424 | dwc2_exit_hibernation(hsotg, false); | |
3425 | ||
83d98223 | 3426 | if (is_active) { |
cd0e641c | 3427 | hsotg->op_state = OTG_STATE_B_PERIPHERAL; |
065d3931 | 3428 | |
1f91b4cc | 3429 | dwc2_hsotg_core_init_disconnected(hsotg, false); |
83d98223 | 3430 | if (hsotg->enabled) |
1f91b4cc | 3431 | dwc2_hsotg_core_connect(hsotg); |
83d98223 | 3432 | } else { |
1f91b4cc FB |
3433 | dwc2_hsotg_core_disconnect(hsotg); |
3434 | dwc2_hsotg_disconnect(hsotg); | |
83d98223 GH |
3435 | } |
3436 | ||
3437 | spin_unlock_irqrestore(&hsotg->lock, flags); | |
3438 | return 0; | |
3439 | } | |
3440 | ||
596d696a | 3441 | /** |
1f91b4cc | 3442 | * dwc2_hsotg_vbus_draw - report bMaxPower field |
596d696a GH |
3443 | * @gadget: The usb gadget state |
3444 | * @mA: Amount of current | |
3445 | * | |
3446 | * Report how much power the device may consume to the phy. | |
3447 | */ | |
1f91b4cc | 3448 | static int dwc2_hsotg_vbus_draw(struct usb_gadget *gadget, unsigned mA) |
596d696a GH |
3449 | { |
3450 | struct dwc2_hsotg *hsotg = to_hsotg(gadget); | |
3451 | ||
3452 | if (IS_ERR_OR_NULL(hsotg->uphy)) | |
3453 | return -ENOTSUPP; | |
3454 | return usb_phy_set_power(hsotg->uphy, mA); | |
3455 | } | |
3456 | ||
1f91b4cc FB |
3457 | static const struct usb_gadget_ops dwc2_hsotg_gadget_ops = { |
3458 | .get_frame = dwc2_hsotg_gadget_getframe, | |
3459 | .udc_start = dwc2_hsotg_udc_start, | |
3460 | .udc_stop = dwc2_hsotg_udc_stop, | |
3461 | .pullup = dwc2_hsotg_pullup, | |
3462 | .vbus_session = dwc2_hsotg_vbus_session, | |
3463 | .vbus_draw = dwc2_hsotg_vbus_draw, | |
5b7d70c6 BD |
3464 | }; |
3465 | ||
3466 | /** | |
1f91b4cc | 3467 | * dwc2_hsotg_initep - initialise a single endpoint |
5b7d70c6 BD |
3468 | * @hsotg: The device state. |
3469 | * @hs_ep: The endpoint to be initialised. | |
3470 | * @epnum: The endpoint number | |
3471 | * | |
3472 | * Initialise the given endpoint (as part of the probe and device state | |
3473 | * creation) to give to the gadget driver. Setup the endpoint name, any | |
3474 | * direction information and other state that may be required. | |
3475 | */ | |
1f91b4cc FB |
3476 | static void dwc2_hsotg_initep(struct dwc2_hsotg *hsotg, |
3477 | struct dwc2_hsotg_ep *hs_ep, | |
c6f5c050 MYK |
3478 | int epnum, |
3479 | bool dir_in) | |
5b7d70c6 | 3480 | { |
5b7d70c6 BD |
3481 | char *dir; |
3482 | ||
3483 | if (epnum == 0) | |
3484 | dir = ""; | |
c6f5c050 | 3485 | else if (dir_in) |
5b7d70c6 | 3486 | dir = "in"; |
c6f5c050 MYK |
3487 | else |
3488 | dir = "out"; | |
5b7d70c6 | 3489 | |
c6f5c050 | 3490 | hs_ep->dir_in = dir_in; |
5b7d70c6 BD |
3491 | hs_ep->index = epnum; |
3492 | ||
3493 | snprintf(hs_ep->name, sizeof(hs_ep->name), "ep%d%s", epnum, dir); | |
3494 | ||
3495 | INIT_LIST_HEAD(&hs_ep->queue); | |
3496 | INIT_LIST_HEAD(&hs_ep->ep.ep_list); | |
3497 | ||
5b7d70c6 BD |
3498 | /* add to the list of endpoints known by the gadget driver */ |
3499 | if (epnum) | |
3500 | list_add_tail(&hs_ep->ep.ep_list, &hsotg->gadget.ep_list); | |
3501 | ||
3502 | hs_ep->parent = hsotg; | |
3503 | hs_ep->ep.name = hs_ep->name; | |
e117e742 | 3504 | usb_ep_set_maxpacket_limit(&hs_ep->ep, epnum ? 1024 : EP0_MPS_LIMIT); |
1f91b4cc | 3505 | hs_ep->ep.ops = &dwc2_hsotg_ep_ops; |
5b7d70c6 | 3506 | |
2954522f RB |
3507 | if (epnum == 0) { |
3508 | hs_ep->ep.caps.type_control = true; | |
3509 | } else { | |
3510 | hs_ep->ep.caps.type_iso = true; | |
3511 | hs_ep->ep.caps.type_bulk = true; | |
3512 | hs_ep->ep.caps.type_int = true; | |
3513 | } | |
3514 | ||
3515 | if (dir_in) | |
3516 | hs_ep->ep.caps.dir_in = true; | |
3517 | else | |
3518 | hs_ep->ep.caps.dir_out = true; | |
3519 | ||
8b9bc460 LM |
3520 | /* |
3521 | * if we're using dma, we need to set the next-endpoint pointer | |
5b7d70c6 BD |
3522 | * to be something valid. |
3523 | */ | |
3524 | ||
3525 | if (using_dma(hsotg)) { | |
47a1685f | 3526 | u32 next = DXEPCTL_NEXTEP((epnum + 1) % 15); |
c6f5c050 | 3527 | if (dir_in) |
95c8bc36 | 3528 | dwc2_writel(next, hsotg->regs + DIEPCTL(epnum)); |
c6f5c050 | 3529 | else |
95c8bc36 | 3530 | dwc2_writel(next, hsotg->regs + DOEPCTL(epnum)); |
5b7d70c6 BD |
3531 | } |
3532 | } | |
3533 | ||
b3f489b2 | 3534 | /** |
1f91b4cc | 3535 | * dwc2_hsotg_hw_cfg - read HW configuration registers |
b3f489b2 LM |
3536 | * @param: The device state |
3537 | * | |
3538 | * Read the USB core HW configuration registers | |
3539 | */ | |
1f91b4cc | 3540 | static int dwc2_hsotg_hw_cfg(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 3541 | { |
c6f5c050 MYK |
3542 | u32 cfg; |
3543 | u32 ep_type; | |
3544 | u32 i; | |
3545 | ||
b3f489b2 | 3546 | /* check hardware configuration */ |
5b7d70c6 | 3547 | |
43e90349 JY |
3548 | hsotg->num_of_eps = hsotg->hw_params.num_dev_ep; |
3549 | ||
c6f5c050 MYK |
3550 | /* Add ep0 */ |
3551 | hsotg->num_of_eps++; | |
10aebc77 | 3552 | |
1f91b4cc | 3553 | hsotg->eps_in[0] = devm_kzalloc(hsotg->dev, sizeof(struct dwc2_hsotg_ep), |
c6f5c050 MYK |
3554 | GFP_KERNEL); |
3555 | if (!hsotg->eps_in[0]) | |
3556 | return -ENOMEM; | |
1f91b4cc | 3557 | /* Same dwc2_hsotg_ep is used in both directions for ep0 */ |
c6f5c050 MYK |
3558 | hsotg->eps_out[0] = hsotg->eps_in[0]; |
3559 | ||
43e90349 | 3560 | cfg = hsotg->hw_params.dev_ep_dirs; |
251a17f5 | 3561 | for (i = 1, cfg >>= 2; i < hsotg->num_of_eps; i++, cfg >>= 2) { |
c6f5c050 MYK |
3562 | ep_type = cfg & 3; |
3563 | /* Direction in or both */ | |
3564 | if (!(ep_type & 2)) { | |
3565 | hsotg->eps_in[i] = devm_kzalloc(hsotg->dev, | |
1f91b4cc | 3566 | sizeof(struct dwc2_hsotg_ep), GFP_KERNEL); |
c6f5c050 MYK |
3567 | if (!hsotg->eps_in[i]) |
3568 | return -ENOMEM; | |
3569 | } | |
3570 | /* Direction out or both */ | |
3571 | if (!(ep_type & 1)) { | |
3572 | hsotg->eps_out[i] = devm_kzalloc(hsotg->dev, | |
1f91b4cc | 3573 | sizeof(struct dwc2_hsotg_ep), GFP_KERNEL); |
c6f5c050 MYK |
3574 | if (!hsotg->eps_out[i]) |
3575 | return -ENOMEM; | |
3576 | } | |
3577 | } | |
3578 | ||
43e90349 JY |
3579 | hsotg->fifo_mem = hsotg->hw_params.total_fifo_size; |
3580 | hsotg->dedicated_fifos = hsotg->hw_params.en_multiple_tx_fifo; | |
10aebc77 | 3581 | |
cff9eb75 MS |
3582 | dev_info(hsotg->dev, "EPs: %d, %s fifos, %d entries in SPRAM\n", |
3583 | hsotg->num_of_eps, | |
3584 | hsotg->dedicated_fifos ? "dedicated" : "shared", | |
3585 | hsotg->fifo_mem); | |
c6f5c050 | 3586 | return 0; |
5b7d70c6 BD |
3587 | } |
3588 | ||
8b9bc460 | 3589 | /** |
1f91b4cc | 3590 | * dwc2_hsotg_dump - dump state of the udc |
8b9bc460 LM |
3591 | * @param: The device state |
3592 | */ | |
1f91b4cc | 3593 | static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 3594 | { |
83a01804 | 3595 | #ifdef DEBUG |
5b7d70c6 BD |
3596 | struct device *dev = hsotg->dev; |
3597 | void __iomem *regs = hsotg->regs; | |
3598 | u32 val; | |
3599 | int idx; | |
3600 | ||
3601 | dev_info(dev, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n", | |
95c8bc36 AS |
3602 | dwc2_readl(regs + DCFG), dwc2_readl(regs + DCTL), |
3603 | dwc2_readl(regs + DIEPMSK)); | |
5b7d70c6 | 3604 | |
f889f23d | 3605 | dev_info(dev, "GAHBCFG=0x%08x, GHWCFG1=0x%08x\n", |
95c8bc36 | 3606 | dwc2_readl(regs + GAHBCFG), dwc2_readl(regs + GHWCFG1)); |
5b7d70c6 BD |
3607 | |
3608 | dev_info(dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n", | |
95c8bc36 | 3609 | dwc2_readl(regs + GRXFSIZ), dwc2_readl(regs + GNPTXFSIZ)); |
5b7d70c6 BD |
3610 | |
3611 | /* show periodic fifo settings */ | |
3612 | ||
364f8e93 | 3613 | for (idx = 1; idx < hsotg->num_of_eps; idx++) { |
95c8bc36 | 3614 | val = dwc2_readl(regs + DPTXFSIZN(idx)); |
5b7d70c6 | 3615 | dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx, |
47a1685f DN |
3616 | val >> FIFOSIZE_DEPTH_SHIFT, |
3617 | val & FIFOSIZE_STARTADDR_MASK); | |
5b7d70c6 BD |
3618 | } |
3619 | ||
364f8e93 | 3620 | for (idx = 0; idx < hsotg->num_of_eps; idx++) { |
5b7d70c6 BD |
3621 | dev_info(dev, |
3622 | "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx, | |
95c8bc36 AS |
3623 | dwc2_readl(regs + DIEPCTL(idx)), |
3624 | dwc2_readl(regs + DIEPTSIZ(idx)), | |
3625 | dwc2_readl(regs + DIEPDMA(idx))); | |
5b7d70c6 | 3626 | |
95c8bc36 | 3627 | val = dwc2_readl(regs + DOEPCTL(idx)); |
5b7d70c6 BD |
3628 | dev_info(dev, |
3629 | "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", | |
95c8bc36 AS |
3630 | idx, dwc2_readl(regs + DOEPCTL(idx)), |
3631 | dwc2_readl(regs + DOEPTSIZ(idx)), | |
3632 | dwc2_readl(regs + DOEPDMA(idx))); | |
5b7d70c6 BD |
3633 | |
3634 | } | |
3635 | ||
3636 | dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n", | |
95c8bc36 | 3637 | dwc2_readl(regs + DVBUSDIS), dwc2_readl(regs + DVBUSPULSE)); |
83a01804 | 3638 | #endif |
5b7d70c6 BD |
3639 | } |
3640 | ||
edd74be8 | 3641 | #ifdef CONFIG_OF |
1f91b4cc | 3642 | static void dwc2_hsotg_of_probe(struct dwc2_hsotg *hsotg) |
edd74be8 GH |
3643 | { |
3644 | struct device_node *np = hsotg->dev->of_node; | |
0a176279 GH |
3645 | u32 len = 0; |
3646 | u32 i = 0; | |
edd74be8 GH |
3647 | |
3648 | /* Enable dma if requested in device tree */ | |
3649 | hsotg->g_using_dma = of_property_read_bool(np, "g-use-dma"); | |
0a176279 GH |
3650 | |
3651 | /* | |
3652 | * Register TX periodic fifo size per endpoint. | |
3653 | * EP0 is excluded since it has no fifo configuration. | |
3654 | */ | |
3655 | if (!of_find_property(np, "g-tx-fifo-size", &len)) | |
3656 | goto rx_fifo; | |
3657 | ||
3658 | len /= sizeof(u32); | |
3659 | ||
3660 | /* Read tx fifo sizes other than ep0 */ | |
3661 | if (of_property_read_u32_array(np, "g-tx-fifo-size", | |
3662 | &hsotg->g_tx_fifo_sz[1], len)) | |
3663 | goto rx_fifo; | |
3664 | ||
3665 | /* Add ep0 */ | |
3666 | len++; | |
3667 | ||
3668 | /* Make remaining TX fifos unavailable */ | |
3669 | if (len < MAX_EPS_CHANNELS) { | |
3670 | for (i = len; i < MAX_EPS_CHANNELS; i++) | |
3671 | hsotg->g_tx_fifo_sz[i] = 0; | |
3672 | } | |
3673 | ||
3674 | rx_fifo: | |
3675 | /* Register RX fifo size */ | |
3676 | of_property_read_u32(np, "g-rx-fifo-size", &hsotg->g_rx_fifo_sz); | |
3677 | ||
3678 | /* Register NPTX fifo size */ | |
3679 | of_property_read_u32(np, "g-np-tx-fifo-size", | |
3680 | &hsotg->g_np_g_tx_fifo_sz); | |
edd74be8 GH |
3681 | } |
3682 | #else | |
1f91b4cc | 3683 | static inline void dwc2_hsotg_of_probe(struct dwc2_hsotg *hsotg) { } |
edd74be8 GH |
3684 | #endif |
3685 | ||
8b9bc460 | 3686 | /** |
117777b2 DN |
3687 | * dwc2_gadget_init - init function for gadget |
3688 | * @dwc2: The data structure for the DWC2 driver. | |
3689 | * @irq: The IRQ number for the controller. | |
8b9bc460 | 3690 | */ |
117777b2 | 3691 | int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq) |
5b7d70c6 | 3692 | { |
117777b2 | 3693 | struct device *dev = hsotg->dev; |
5b7d70c6 BD |
3694 | int epnum; |
3695 | int ret; | |
fc9a731e | 3696 | int i; |
0a176279 | 3697 | u32 p_tx_fifo[] = DWC2_G_P_LEGACY_TX_FIFO_SIZE; |
5b7d70c6 | 3698 | |
0a176279 GH |
3699 | /* Initialize to legacy fifo configuration values */ |
3700 | hsotg->g_rx_fifo_sz = 2048; | |
3701 | hsotg->g_np_g_tx_fifo_sz = 1024; | |
3702 | memcpy(&hsotg->g_tx_fifo_sz[1], p_tx_fifo, sizeof(p_tx_fifo)); | |
3703 | /* Device tree specific probe */ | |
1f91b4cc | 3704 | dwc2_hsotg_of_probe(hsotg); |
43e90349 JY |
3705 | |
3706 | /* Check against largest possible value. */ | |
3707 | if (hsotg->g_np_g_tx_fifo_sz > | |
3708 | hsotg->hw_params.dev_nperio_tx_fifo_size) { | |
3709 | dev_warn(dev, "Specified GNPTXFDEP=%d > %d\n", | |
3710 | hsotg->g_np_g_tx_fifo_sz, | |
3711 | hsotg->hw_params.dev_nperio_tx_fifo_size); | |
3712 | hsotg->g_np_g_tx_fifo_sz = | |
3713 | hsotg->hw_params.dev_nperio_tx_fifo_size; | |
3714 | } | |
3715 | ||
0a176279 GH |
3716 | /* Dump fifo information */ |
3717 | dev_dbg(dev, "NonPeriodic TXFIFO size: %d\n", | |
3718 | hsotg->g_np_g_tx_fifo_sz); | |
3719 | dev_dbg(dev, "RXFIFO size: %d\n", hsotg->g_rx_fifo_sz); | |
3720 | for (i = 0; i < MAX_EPS_CHANNELS; i++) | |
3721 | dev_dbg(dev, "Periodic TXFIFO%2d size: %d\n", i, | |
3722 | hsotg->g_tx_fifo_sz[i]); | |
5b7d70c6 | 3723 | |
d327ab5b | 3724 | hsotg->gadget.max_speed = USB_SPEED_HIGH; |
1f91b4cc | 3725 | hsotg->gadget.ops = &dwc2_hsotg_gadget_ops; |
5b7d70c6 | 3726 | hsotg->gadget.name = dev_name(dev); |
097ee662 GH |
3727 | if (hsotg->dr_mode == USB_DR_MODE_OTG) |
3728 | hsotg->gadget.is_otg = 1; | |
ec4cc657 MYK |
3729 | else if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) |
3730 | hsotg->op_state = OTG_STATE_B_PERIPHERAL; | |
5b7d70c6 | 3731 | |
1f91b4cc | 3732 | ret = dwc2_hsotg_hw_cfg(hsotg); |
c6f5c050 MYK |
3733 | if (ret) { |
3734 | dev_err(hsotg->dev, "Hardware configuration failed: %d\n", ret); | |
09a75e85 | 3735 | return ret; |
c6f5c050 MYK |
3736 | } |
3737 | ||
3f95001d MYK |
3738 | hsotg->ctrl_buff = devm_kzalloc(hsotg->dev, |
3739 | DWC2_CTRL_BUFF_SIZE, GFP_KERNEL); | |
3740 | if (!hsotg->ctrl_buff) { | |
3741 | dev_err(dev, "failed to allocate ctrl request buff\n"); | |
09a75e85 | 3742 | return -ENOMEM; |
3f95001d MYK |
3743 | } |
3744 | ||
3745 | hsotg->ep0_buff = devm_kzalloc(hsotg->dev, | |
3746 | DWC2_CTRL_BUFF_SIZE, GFP_KERNEL); | |
3747 | if (!hsotg->ep0_buff) { | |
3748 | dev_err(dev, "failed to allocate ctrl reply buff\n"); | |
09a75e85 | 3749 | return -ENOMEM; |
3f95001d MYK |
3750 | } |
3751 | ||
1f91b4cc | 3752 | ret = devm_request_irq(hsotg->dev, irq, dwc2_hsotg_irq, IRQF_SHARED, |
db8178c3 | 3753 | dev_name(hsotg->dev), hsotg); |
eb3c56c5 | 3754 | if (ret < 0) { |
db8178c3 | 3755 | dev_err(dev, "cannot claim IRQ for gadget\n"); |
09a75e85 | 3756 | return ret; |
eb3c56c5 MS |
3757 | } |
3758 | ||
b3f489b2 LM |
3759 | /* hsotg->num_of_eps holds number of EPs other than ep0 */ |
3760 | ||
3761 | if (hsotg->num_of_eps == 0) { | |
3762 | dev_err(dev, "wrong number of EPs (zero)\n"); | |
09a75e85 | 3763 | return -EINVAL; |
b3f489b2 LM |
3764 | } |
3765 | ||
b3f489b2 LM |
3766 | /* setup endpoint information */ |
3767 | ||
3768 | INIT_LIST_HEAD(&hsotg->gadget.ep_list); | |
c6f5c050 | 3769 | hsotg->gadget.ep0 = &hsotg->eps_out[0]->ep; |
b3f489b2 LM |
3770 | |
3771 | /* allocate EP0 request */ | |
3772 | ||
1f91b4cc | 3773 | hsotg->ctrl_req = dwc2_hsotg_ep_alloc_request(&hsotg->eps_out[0]->ep, |
b3f489b2 LM |
3774 | GFP_KERNEL); |
3775 | if (!hsotg->ctrl_req) { | |
3776 | dev_err(dev, "failed to allocate ctrl req\n"); | |
09a75e85 | 3777 | return -ENOMEM; |
b3f489b2 | 3778 | } |
5b7d70c6 BD |
3779 | |
3780 | /* initialise the endpoints now the core has been initialised */ | |
c6f5c050 MYK |
3781 | for (epnum = 0; epnum < hsotg->num_of_eps; epnum++) { |
3782 | if (hsotg->eps_in[epnum]) | |
1f91b4cc | 3783 | dwc2_hsotg_initep(hsotg, hsotg->eps_in[epnum], |
c6f5c050 MYK |
3784 | epnum, 1); |
3785 | if (hsotg->eps_out[epnum]) | |
1f91b4cc | 3786 | dwc2_hsotg_initep(hsotg, hsotg->eps_out[epnum], |
c6f5c050 MYK |
3787 | epnum, 0); |
3788 | } | |
5b7d70c6 | 3789 | |
117777b2 | 3790 | ret = usb_add_gadget_udc(dev, &hsotg->gadget); |
0f91349b | 3791 | if (ret) |
09a75e85 | 3792 | return ret; |
0f91349b | 3793 | |
1f91b4cc | 3794 | dwc2_hsotg_dump(hsotg); |
5b7d70c6 | 3795 | |
5b7d70c6 | 3796 | return 0; |
5b7d70c6 BD |
3797 | } |
3798 | ||
8b9bc460 | 3799 | /** |
1f91b4cc | 3800 | * dwc2_hsotg_remove - remove function for hsotg driver |
8b9bc460 LM |
3801 | * @pdev: The platform information for the driver |
3802 | */ | |
1f91b4cc | 3803 | int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 3804 | { |
0f91349b | 3805 | usb_del_gadget_udc(&hsotg->gadget); |
31ee04de | 3806 | |
5b7d70c6 BD |
3807 | return 0; |
3808 | } | |
3809 | ||
1f91b4cc | 3810 | int dwc2_hsotg_suspend(struct dwc2_hsotg *hsotg) |
b83e333a | 3811 | { |
b83e333a | 3812 | unsigned long flags; |
b83e333a | 3813 | |
9e779778 | 3814 | if (hsotg->lx_state != DWC2_L0) |
09a75e85 | 3815 | return 0; |
9e779778 | 3816 | |
dc6e69e6 MS |
3817 | if (hsotg->driver) { |
3818 | int ep; | |
3819 | ||
b83e333a MS |
3820 | dev_info(hsotg->dev, "suspending usb gadget %s\n", |
3821 | hsotg->driver->driver.name); | |
3822 | ||
dc6e69e6 MS |
3823 | spin_lock_irqsave(&hsotg->lock, flags); |
3824 | if (hsotg->enabled) | |
1f91b4cc FB |
3825 | dwc2_hsotg_core_disconnect(hsotg); |
3826 | dwc2_hsotg_disconnect(hsotg); | |
dc6e69e6 MS |
3827 | hsotg->gadget.speed = USB_SPEED_UNKNOWN; |
3828 | spin_unlock_irqrestore(&hsotg->lock, flags); | |
b83e333a | 3829 | |
c6f5c050 MYK |
3830 | for (ep = 0; ep < hsotg->num_of_eps; ep++) { |
3831 | if (hsotg->eps_in[ep]) | |
1f91b4cc | 3832 | dwc2_hsotg_ep_disable(&hsotg->eps_in[ep]->ep); |
c6f5c050 | 3833 | if (hsotg->eps_out[ep]) |
1f91b4cc | 3834 | dwc2_hsotg_ep_disable(&hsotg->eps_out[ep]->ep); |
c6f5c050 | 3835 | } |
b83e333a MS |
3836 | } |
3837 | ||
09a75e85 | 3838 | return 0; |
b83e333a MS |
3839 | } |
3840 | ||
1f91b4cc | 3841 | int dwc2_hsotg_resume(struct dwc2_hsotg *hsotg) |
b83e333a | 3842 | { |
b83e333a | 3843 | unsigned long flags; |
b83e333a | 3844 | |
9e779778 | 3845 | if (hsotg->lx_state == DWC2_L2) |
09a75e85 | 3846 | return 0; |
9e779778 | 3847 | |
b83e333a MS |
3848 | if (hsotg->driver) { |
3849 | dev_info(hsotg->dev, "resuming usb gadget %s\n", | |
3850 | hsotg->driver->driver.name); | |
d00b4142 | 3851 | |
dc6e69e6 | 3852 | spin_lock_irqsave(&hsotg->lock, flags); |
1f91b4cc | 3853 | dwc2_hsotg_core_init_disconnected(hsotg, false); |
dc6e69e6 | 3854 | if (hsotg->enabled) |
1f91b4cc | 3855 | dwc2_hsotg_core_connect(hsotg); |
dc6e69e6 MS |
3856 | spin_unlock_irqrestore(&hsotg->lock, flags); |
3857 | } | |
b83e333a | 3858 | |
09a75e85 | 3859 | return 0; |
b83e333a | 3860 | } |
58e52ff6 JY |
3861 | |
3862 | /** | |
3863 | * dwc2_backup_device_registers() - Backup controller device registers. | |
3864 | * When suspending usb bus, registers needs to be backuped | |
3865 | * if controller power is disabled once suspended. | |
3866 | * | |
3867 | * @hsotg: Programming view of the DWC_otg controller | |
3868 | */ | |
3869 | int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg) | |
3870 | { | |
3871 | struct dwc2_dregs_backup *dr; | |
3872 | int i; | |
3873 | ||
3874 | dev_dbg(hsotg->dev, "%s\n", __func__); | |
3875 | ||
3876 | /* Backup dev regs */ | |
3877 | dr = &hsotg->dr_backup; | |
3878 | ||
3879 | dr->dcfg = dwc2_readl(hsotg->regs + DCFG); | |
3880 | dr->dctl = dwc2_readl(hsotg->regs + DCTL); | |
3881 | dr->daintmsk = dwc2_readl(hsotg->regs + DAINTMSK); | |
3882 | dr->diepmsk = dwc2_readl(hsotg->regs + DIEPMSK); | |
3883 | dr->doepmsk = dwc2_readl(hsotg->regs + DOEPMSK); | |
3884 | ||
3885 | for (i = 0; i < hsotg->num_of_eps; i++) { | |
3886 | /* Backup IN EPs */ | |
3887 | dr->diepctl[i] = dwc2_readl(hsotg->regs + DIEPCTL(i)); | |
3888 | ||
3889 | /* Ensure DATA PID is correctly configured */ | |
3890 | if (dr->diepctl[i] & DXEPCTL_DPID) | |
3891 | dr->diepctl[i] |= DXEPCTL_SETD1PID; | |
3892 | else | |
3893 | dr->diepctl[i] |= DXEPCTL_SETD0PID; | |
3894 | ||
3895 | dr->dieptsiz[i] = dwc2_readl(hsotg->regs + DIEPTSIZ(i)); | |
3896 | dr->diepdma[i] = dwc2_readl(hsotg->regs + DIEPDMA(i)); | |
3897 | ||
3898 | /* Backup OUT EPs */ | |
3899 | dr->doepctl[i] = dwc2_readl(hsotg->regs + DOEPCTL(i)); | |
3900 | ||
3901 | /* Ensure DATA PID is correctly configured */ | |
3902 | if (dr->doepctl[i] & DXEPCTL_DPID) | |
3903 | dr->doepctl[i] |= DXEPCTL_SETD1PID; | |
3904 | else | |
3905 | dr->doepctl[i] |= DXEPCTL_SETD0PID; | |
3906 | ||
3907 | dr->doeptsiz[i] = dwc2_readl(hsotg->regs + DOEPTSIZ(i)); | |
3908 | dr->doepdma[i] = dwc2_readl(hsotg->regs + DOEPDMA(i)); | |
3909 | } | |
3910 | dr->valid = true; | |
3911 | return 0; | |
3912 | } | |
3913 | ||
3914 | /** | |
3915 | * dwc2_restore_device_registers() - Restore controller device registers. | |
3916 | * When resuming usb bus, device registers needs to be restored | |
3917 | * if controller power were disabled. | |
3918 | * | |
3919 | * @hsotg: Programming view of the DWC_otg controller | |
3920 | */ | |
3921 | int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg) | |
3922 | { | |
3923 | struct dwc2_dregs_backup *dr; | |
3924 | u32 dctl; | |
3925 | int i; | |
3926 | ||
3927 | dev_dbg(hsotg->dev, "%s\n", __func__); | |
3928 | ||
3929 | /* Restore dev regs */ | |
3930 | dr = &hsotg->dr_backup; | |
3931 | if (!dr->valid) { | |
3932 | dev_err(hsotg->dev, "%s: no device registers to restore\n", | |
3933 | __func__); | |
3934 | return -EINVAL; | |
3935 | } | |
3936 | dr->valid = false; | |
3937 | ||
3938 | dwc2_writel(dr->dcfg, hsotg->regs + DCFG); | |
3939 | dwc2_writel(dr->dctl, hsotg->regs + DCTL); | |
3940 | dwc2_writel(dr->daintmsk, hsotg->regs + DAINTMSK); | |
3941 | dwc2_writel(dr->diepmsk, hsotg->regs + DIEPMSK); | |
3942 | dwc2_writel(dr->doepmsk, hsotg->regs + DOEPMSK); | |
3943 | ||
3944 | for (i = 0; i < hsotg->num_of_eps; i++) { | |
3945 | /* Restore IN EPs */ | |
3946 | dwc2_writel(dr->diepctl[i], hsotg->regs + DIEPCTL(i)); | |
3947 | dwc2_writel(dr->dieptsiz[i], hsotg->regs + DIEPTSIZ(i)); | |
3948 | dwc2_writel(dr->diepdma[i], hsotg->regs + DIEPDMA(i)); | |
3949 | ||
3950 | /* Restore OUT EPs */ | |
3951 | dwc2_writel(dr->doepctl[i], hsotg->regs + DOEPCTL(i)); | |
3952 | dwc2_writel(dr->doeptsiz[i], hsotg->regs + DOEPTSIZ(i)); | |
3953 | dwc2_writel(dr->doepdma[i], hsotg->regs + DOEPDMA(i)); | |
3954 | } | |
3955 | ||
3956 | /* Set the Power-On Programming done bit */ | |
3957 | dctl = dwc2_readl(hsotg->regs + DCTL); | |
3958 | dctl |= DCTL_PWRONPRGDONE; | |
3959 | dwc2_writel(dctl, hsotg->regs + DCTL); | |
3960 | ||
3961 | return 0; | |
3962 | } |