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5fd54ace | 1 | // SPDX-License-Identifier: GPL-2.0 |
6fb914d7 | 2 | /* |
dfbc6fa3 AT |
3 | * Copyright (c) 2011 Samsung Electronics Co., Ltd. |
4 | * http://www.samsung.com | |
5b7d70c6 BD |
5 | * |
6 | * Copyright 2008 Openmoko, Inc. | |
7 | * Copyright 2008 Simtec Electronics | |
8 | * Ben Dooks <ben@simtec.co.uk> | |
9 | * http://armlinux.simtec.co.uk/ | |
10 | * | |
11 | * S3C USB2.0 High-speed / OtG driver | |
8b9bc460 | 12 | */ |
5b7d70c6 BD |
13 | |
14 | #include <linux/kernel.h> | |
15 | #include <linux/module.h> | |
16 | #include <linux/spinlock.h> | |
17 | #include <linux/interrupt.h> | |
18 | #include <linux/platform_device.h> | |
19 | #include <linux/dma-mapping.h> | |
7ad8096e | 20 | #include <linux/mutex.h> |
5b7d70c6 BD |
21 | #include <linux/seq_file.h> |
22 | #include <linux/delay.h> | |
23 | #include <linux/io.h> | |
5a0e3ad6 | 24 | #include <linux/slab.h> |
c50f056c | 25 | #include <linux/of_platform.h> |
5b7d70c6 BD |
26 | |
27 | #include <linux/usb/ch9.h> | |
28 | #include <linux/usb/gadget.h> | |
b2e587db | 29 | #include <linux/usb/phy.h> |
b4c53b4a MH |
30 | #include <linux/usb/composite.h> |
31 | ||
5b7d70c6 | 32 | |
f7c0b143 | 33 | #include "core.h" |
941fcce4 | 34 | #include "hw.h" |
5b7d70c6 BD |
35 | |
36 | /* conversion functions */ | |
1f91b4cc | 37 | static inline struct dwc2_hsotg_req *our_req(struct usb_request *req) |
5b7d70c6 | 38 | { |
1f91b4cc | 39 | return container_of(req, struct dwc2_hsotg_req, req); |
5b7d70c6 BD |
40 | } |
41 | ||
1f91b4cc | 42 | static inline struct dwc2_hsotg_ep *our_ep(struct usb_ep *ep) |
5b7d70c6 | 43 | { |
1f91b4cc | 44 | return container_of(ep, struct dwc2_hsotg_ep, ep); |
5b7d70c6 BD |
45 | } |
46 | ||
941fcce4 | 47 | static inline struct dwc2_hsotg *to_hsotg(struct usb_gadget *gadget) |
5b7d70c6 | 48 | { |
941fcce4 | 49 | return container_of(gadget, struct dwc2_hsotg, gadget); |
5b7d70c6 BD |
50 | } |
51 | ||
f25c42b8 | 52 | static inline void dwc2_set_bit(struct dwc2_hsotg *hsotg, u32 offset, u32 val) |
5b7d70c6 | 53 | { |
f25c42b8 | 54 | dwc2_writel(hsotg, dwc2_readl(hsotg, offset) | val, offset); |
5b7d70c6 BD |
55 | } |
56 | ||
f25c42b8 | 57 | static inline void dwc2_clear_bit(struct dwc2_hsotg *hsotg, u32 offset, u32 val) |
5b7d70c6 | 58 | { |
f25c42b8 | 59 | dwc2_writel(hsotg, dwc2_readl(hsotg, offset) & ~val, offset); |
5b7d70c6 BD |
60 | } |
61 | ||
1f91b4cc | 62 | static inline struct dwc2_hsotg_ep *index_to_ep(struct dwc2_hsotg *hsotg, |
c6f5c050 MYK |
63 | u32 ep_index, u32 dir_in) |
64 | { | |
65 | if (dir_in) | |
66 | return hsotg->eps_in[ep_index]; | |
67 | else | |
68 | return hsotg->eps_out[ep_index]; | |
69 | } | |
70 | ||
997f4f81 | 71 | /* forward declaration of functions */ |
1f91b4cc | 72 | static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg); |
5b7d70c6 BD |
73 | |
74 | /** | |
75 | * using_dma - return the DMA status of the driver. | |
76 | * @hsotg: The driver state. | |
77 | * | |
78 | * Return true if we're using DMA. | |
79 | * | |
80 | * Currently, we have the DMA support code worked into everywhere | |
81 | * that needs it, but the AMBA DMA implementation in the hardware can | |
82 | * only DMA from 32bit aligned addresses. This means that gadgets such | |
83 | * as the CDC Ethernet cannot work as they often pass packets which are | |
84 | * not 32bit aligned. | |
85 | * | |
86 | * Unfortunately the choice to use DMA or not is global to the controller | |
87 | * and seems to be only settable when the controller is being put through | |
88 | * a core reset. This means we either need to fix the gadgets to take | |
89 | * account of DMA alignment, or add bounce buffers (yuerk). | |
90 | * | |
edd74be8 | 91 | * g_using_dma is set depending on dts flag. |
5b7d70c6 | 92 | */ |
941fcce4 | 93 | static inline bool using_dma(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 94 | { |
05ee799f | 95 | return hsotg->params.g_dma; |
5b7d70c6 BD |
96 | } |
97 | ||
dec4b556 VA |
98 | /* |
99 | * using_desc_dma - return the descriptor DMA status of the driver. | |
100 | * @hsotg: The driver state. | |
101 | * | |
102 | * Return true if we're using descriptor DMA. | |
103 | */ | |
104 | static inline bool using_desc_dma(struct dwc2_hsotg *hsotg) | |
105 | { | |
106 | return hsotg->params.g_dma_desc; | |
107 | } | |
108 | ||
92d1635d VM |
109 | /** |
110 | * dwc2_gadget_incr_frame_num - Increments the targeted frame number. | |
111 | * @hs_ep: The endpoint | |
92d1635d VM |
112 | * |
113 | * This function will also check if the frame number overruns DSTS_SOFFN_LIMIT. | |
114 | * If an overrun occurs it will wrap the value and set the frame_overrun flag. | |
115 | */ | |
116 | static inline void dwc2_gadget_incr_frame_num(struct dwc2_hsotg_ep *hs_ep) | |
117 | { | |
118 | hs_ep->target_frame += hs_ep->interval; | |
119 | if (hs_ep->target_frame > DSTS_SOFFN_LIMIT) { | |
c1d5df69 | 120 | hs_ep->frame_overrun = true; |
92d1635d VM |
121 | hs_ep->target_frame &= DSTS_SOFFN_LIMIT; |
122 | } else { | |
c1d5df69 | 123 | hs_ep->frame_overrun = false; |
92d1635d VM |
124 | } |
125 | } | |
126 | ||
9d630b9c GT |
127 | /** |
128 | * dwc2_gadget_dec_frame_num_by_one - Decrements the targeted frame number | |
129 | * by one. | |
130 | * @hs_ep: The endpoint. | |
131 | * | |
132 | * This function used in service interval based scheduling flow to calculate | |
133 | * descriptor frame number filed value. For service interval mode frame | |
134 | * number in descriptor should point to last (u)frame in the interval. | |
135 | * | |
136 | */ | |
137 | static inline void dwc2_gadget_dec_frame_num_by_one(struct dwc2_hsotg_ep *hs_ep) | |
138 | { | |
139 | if (hs_ep->target_frame) | |
140 | hs_ep->target_frame -= 1; | |
141 | else | |
142 | hs_ep->target_frame = DSTS_SOFFN_LIMIT; | |
143 | } | |
144 | ||
5b7d70c6 | 145 | /** |
1f91b4cc | 146 | * dwc2_hsotg_en_gsint - enable one or more of the general interrupt |
5b7d70c6 BD |
147 | * @hsotg: The device state |
148 | * @ints: A bitmask of the interrupts to enable | |
149 | */ | |
1f91b4cc | 150 | static void dwc2_hsotg_en_gsint(struct dwc2_hsotg *hsotg, u32 ints) |
5b7d70c6 | 151 | { |
f25c42b8 | 152 | u32 gsintmsk = dwc2_readl(hsotg, GINTMSK); |
5b7d70c6 BD |
153 | u32 new_gsintmsk; |
154 | ||
155 | new_gsintmsk = gsintmsk | ints; | |
156 | ||
157 | if (new_gsintmsk != gsintmsk) { | |
158 | dev_dbg(hsotg->dev, "gsintmsk now 0x%08x\n", new_gsintmsk); | |
f25c42b8 | 159 | dwc2_writel(hsotg, new_gsintmsk, GINTMSK); |
5b7d70c6 BD |
160 | } |
161 | } | |
162 | ||
163 | /** | |
1f91b4cc | 164 | * dwc2_hsotg_disable_gsint - disable one or more of the general interrupt |
5b7d70c6 BD |
165 | * @hsotg: The device state |
166 | * @ints: A bitmask of the interrupts to enable | |
167 | */ | |
1f91b4cc | 168 | static void dwc2_hsotg_disable_gsint(struct dwc2_hsotg *hsotg, u32 ints) |
5b7d70c6 | 169 | { |
f25c42b8 | 170 | u32 gsintmsk = dwc2_readl(hsotg, GINTMSK); |
5b7d70c6 BD |
171 | u32 new_gsintmsk; |
172 | ||
173 | new_gsintmsk = gsintmsk & ~ints; | |
174 | ||
175 | if (new_gsintmsk != gsintmsk) | |
f25c42b8 | 176 | dwc2_writel(hsotg, new_gsintmsk, GINTMSK); |
5b7d70c6 BD |
177 | } |
178 | ||
179 | /** | |
1f91b4cc | 180 | * dwc2_hsotg_ctrl_epint - enable/disable an endpoint irq |
5b7d70c6 BD |
181 | * @hsotg: The device state |
182 | * @ep: The endpoint index | |
183 | * @dir_in: True if direction is in. | |
184 | * @en: The enable value, true to enable | |
185 | * | |
186 | * Set or clear the mask for an individual endpoint's interrupt | |
187 | * request. | |
188 | */ | |
1f91b4cc | 189 | static void dwc2_hsotg_ctrl_epint(struct dwc2_hsotg *hsotg, |
9da51974 | 190 | unsigned int ep, unsigned int dir_in, |
5b7d70c6 BD |
191 | unsigned int en) |
192 | { | |
193 | unsigned long flags; | |
194 | u32 bit = 1 << ep; | |
195 | u32 daint; | |
196 | ||
197 | if (!dir_in) | |
198 | bit <<= 16; | |
199 | ||
200 | local_irq_save(flags); | |
f25c42b8 | 201 | daint = dwc2_readl(hsotg, DAINTMSK); |
5b7d70c6 BD |
202 | if (en) |
203 | daint |= bit; | |
204 | else | |
205 | daint &= ~bit; | |
f25c42b8 | 206 | dwc2_writel(hsotg, daint, DAINTMSK); |
5b7d70c6 BD |
207 | local_irq_restore(flags); |
208 | } | |
209 | ||
c138ecfa SA |
210 | /** |
211 | * dwc2_hsotg_tx_fifo_count - return count of TX FIFOs in device mode | |
6fb914d7 GT |
212 | * |
213 | * @hsotg: Programming view of the DWC_otg controller | |
c138ecfa SA |
214 | */ |
215 | int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg *hsotg) | |
216 | { | |
217 | if (hsotg->hw_params.en_multiple_tx_fifo) | |
218 | /* In dedicated FIFO mode we need count of IN EPs */ | |
9273083a | 219 | return hsotg->hw_params.num_dev_in_eps; |
c138ecfa SA |
220 | else |
221 | /* In shared FIFO mode we need count of Periodic IN EPs */ | |
222 | return hsotg->hw_params.num_dev_perio_in_ep; | |
223 | } | |
224 | ||
c138ecfa SA |
225 | /** |
226 | * dwc2_hsotg_tx_fifo_total_depth - return total FIFO depth available for | |
227 | * device mode TX FIFOs | |
6fb914d7 GT |
228 | * |
229 | * @hsotg: Programming view of the DWC_otg controller | |
c138ecfa SA |
230 | */ |
231 | int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg) | |
232 | { | |
c138ecfa SA |
233 | int addr; |
234 | int tx_addr_max; | |
235 | u32 np_tx_fifo_size; | |
236 | ||
237 | np_tx_fifo_size = min_t(u32, hsotg->hw_params.dev_nperio_tx_fifo_size, | |
238 | hsotg->params.g_np_tx_fifo_size); | |
239 | ||
240 | /* Get Endpoint Info Control block size in DWORDs. */ | |
9273083a | 241 | tx_addr_max = hsotg->hw_params.total_fifo_size; |
c138ecfa SA |
242 | |
243 | addr = hsotg->params.g_rx_fifo_size + np_tx_fifo_size; | |
244 | if (tx_addr_max <= addr) | |
245 | return 0; | |
246 | ||
247 | return tx_addr_max - addr; | |
248 | } | |
249 | ||
187c5298 GT |
250 | /** |
251 | * dwc2_gadget_wkup_alert_handler - Handler for WKUP_ALERT interrupt | |
252 | * | |
253 | * @hsotg: Programming view of the DWC_otg controller | |
254 | * | |
255 | */ | |
256 | static void dwc2_gadget_wkup_alert_handler(struct dwc2_hsotg *hsotg) | |
257 | { | |
258 | u32 gintsts2; | |
259 | u32 gintmsk2; | |
260 | ||
261 | gintsts2 = dwc2_readl(hsotg, GINTSTS2); | |
262 | gintmsk2 = dwc2_readl(hsotg, GINTMSK2); | |
263 | ||
264 | if (gintsts2 & GINTSTS2_WKUP_ALERT_INT) { | |
265 | dev_dbg(hsotg->dev, "%s: Wkup_Alert_Int\n", __func__); | |
87b6d2c5 | 266 | dwc2_set_bit(hsotg, GINTSTS2, GINTSTS2_WKUP_ALERT_INT); |
d64bc8ee | 267 | dwc2_set_bit(hsotg, DCTL, DCTL_RMTWKUPSIG); |
187c5298 GT |
268 | } |
269 | } | |
270 | ||
c138ecfa SA |
271 | /** |
272 | * dwc2_hsotg_tx_fifo_average_depth - returns average depth of device mode | |
273 | * TX FIFOs | |
6fb914d7 GT |
274 | * |
275 | * @hsotg: Programming view of the DWC_otg controller | |
c138ecfa SA |
276 | */ |
277 | int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg *hsotg) | |
278 | { | |
279 | int tx_fifo_count; | |
280 | int tx_fifo_depth; | |
281 | ||
282 | tx_fifo_depth = dwc2_hsotg_tx_fifo_total_depth(hsotg); | |
283 | ||
284 | tx_fifo_count = dwc2_hsotg_tx_fifo_count(hsotg); | |
285 | ||
286 | if (!tx_fifo_count) | |
287 | return tx_fifo_depth; | |
288 | else | |
289 | return tx_fifo_depth / tx_fifo_count; | |
290 | } | |
291 | ||
5b7d70c6 | 292 | /** |
1f91b4cc | 293 | * dwc2_hsotg_init_fifo - initialise non-periodic FIFOs |
5b7d70c6 BD |
294 | * @hsotg: The device instance. |
295 | */ | |
1f91b4cc | 296 | static void dwc2_hsotg_init_fifo(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 297 | { |
2317eacd | 298 | unsigned int ep; |
0f002d20 | 299 | unsigned int addr; |
1703a6d3 | 300 | int timeout; |
79d6b8c5 | 301 | |
0f002d20 | 302 | u32 val; |
05ee799f | 303 | u32 *txfsz = hsotg->params.g_tx_fifo_size; |
0f002d20 | 304 | |
7fcbc95c GH |
305 | /* Reset fifo map if not correctly cleared during previous session */ |
306 | WARN_ON(hsotg->fifo_map); | |
307 | hsotg->fifo_map = 0; | |
308 | ||
0a176279 | 309 | /* set RX/NPTX FIFO sizes */ |
f25c42b8 GS |
310 | dwc2_writel(hsotg, hsotg->params.g_rx_fifo_size, GRXFSIZ); |
311 | dwc2_writel(hsotg, (hsotg->params.g_rx_fifo_size << | |
312 | FIFOSIZE_STARTADDR_SHIFT) | | |
05ee799f | 313 | (hsotg->params.g_np_tx_fifo_size << FIFOSIZE_DEPTH_SHIFT), |
f25c42b8 | 314 | GNPTXFSIZ); |
0f002d20 | 315 | |
8b9bc460 LM |
316 | /* |
317 | * arange all the rest of the TX FIFOs, as some versions of this | |
0f002d20 BD |
318 | * block have overlapping default addresses. This also ensures |
319 | * that if the settings have been changed, then they are set to | |
8b9bc460 LM |
320 | * known values. |
321 | */ | |
0f002d20 BD |
322 | |
323 | /* start at the end of the GNPTXFSIZ, rounded up */ | |
05ee799f | 324 | addr = hsotg->params.g_rx_fifo_size + hsotg->params.g_np_tx_fifo_size; |
0f002d20 | 325 | |
8b9bc460 | 326 | /* |
0a176279 | 327 | * Configure fifos sizes from provided configuration and assign |
b203d0a2 RB |
328 | * them to endpoints dynamically according to maxpacket size value of |
329 | * given endpoint. | |
8b9bc460 | 330 | */ |
2317eacd | 331 | for (ep = 1; ep < MAX_EPS_CHANNELS; ep++) { |
05ee799f | 332 | if (!txfsz[ep]) |
3fa95385 JY |
333 | continue; |
334 | val = addr; | |
05ee799f JY |
335 | val |= txfsz[ep] << FIFOSIZE_DEPTH_SHIFT; |
336 | WARN_ONCE(addr + txfsz[ep] > hsotg->fifo_mem, | |
3fa95385 | 337 | "insufficient fifo memory"); |
05ee799f | 338 | addr += txfsz[ep]; |
0f002d20 | 339 | |
f25c42b8 GS |
340 | dwc2_writel(hsotg, val, DPTXFSIZN(ep)); |
341 | val = dwc2_readl(hsotg, DPTXFSIZN(ep)); | |
0f002d20 | 342 | } |
1703a6d3 | 343 | |
f25c42b8 | 344 | dwc2_writel(hsotg, hsotg->hw_params.total_fifo_size | |
f87c842f | 345 | addr << GDFIFOCFG_EPINFOBASE_SHIFT, |
f25c42b8 | 346 | GDFIFOCFG); |
8b9bc460 LM |
347 | /* |
348 | * according to p428 of the design guide, we need to ensure that | |
349 | * all fifos are flushed before continuing | |
350 | */ | |
1703a6d3 | 351 | |
f25c42b8 GS |
352 | dwc2_writel(hsotg, GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH | |
353 | GRSTCTL_RXFFLSH, GRSTCTL); | |
1703a6d3 BD |
354 | |
355 | /* wait until the fifos are both flushed */ | |
356 | timeout = 100; | |
357 | while (1) { | |
f25c42b8 | 358 | val = dwc2_readl(hsotg, GRSTCTL); |
1703a6d3 | 359 | |
47a1685f | 360 | if ((val & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH)) == 0) |
1703a6d3 BD |
361 | break; |
362 | ||
363 | if (--timeout == 0) { | |
364 | dev_err(hsotg->dev, | |
365 | "%s: timeout flushing fifos (GRSTCTL=%08x)\n", | |
366 | __func__, val); | |
48b20bcb | 367 | break; |
1703a6d3 BD |
368 | } |
369 | ||
370 | udelay(1); | |
371 | } | |
372 | ||
373 | dev_dbg(hsotg->dev, "FIFOs reset, timeout at %d\n", timeout); | |
5b7d70c6 BD |
374 | } |
375 | ||
376 | /** | |
6fb914d7 | 377 | * dwc2_hsotg_ep_alloc_request - allocate USB rerequest structure |
5b7d70c6 BD |
378 | * @ep: USB endpoint to allocate request for. |
379 | * @flags: Allocation flags | |
380 | * | |
381 | * Allocate a new USB request structure appropriate for the specified endpoint | |
382 | */ | |
1f91b4cc | 383 | static struct usb_request *dwc2_hsotg_ep_alloc_request(struct usb_ep *ep, |
9da51974 | 384 | gfp_t flags) |
5b7d70c6 | 385 | { |
1f91b4cc | 386 | struct dwc2_hsotg_req *req; |
5b7d70c6 | 387 | |
ec33efe2 | 388 | req = kzalloc(sizeof(*req), flags); |
5b7d70c6 BD |
389 | if (!req) |
390 | return NULL; | |
391 | ||
392 | INIT_LIST_HEAD(&req->queue); | |
393 | ||
5b7d70c6 BD |
394 | return &req->req; |
395 | } | |
396 | ||
397 | /** | |
398 | * is_ep_periodic - return true if the endpoint is in periodic mode. | |
399 | * @hs_ep: The endpoint to query. | |
400 | * | |
401 | * Returns true if the endpoint is in periodic mode, meaning it is being | |
402 | * used for an Interrupt or ISO transfer. | |
403 | */ | |
1f91b4cc | 404 | static inline int is_ep_periodic(struct dwc2_hsotg_ep *hs_ep) |
5b7d70c6 BD |
405 | { |
406 | return hs_ep->periodic; | |
407 | } | |
408 | ||
409 | /** | |
1f91b4cc | 410 | * dwc2_hsotg_unmap_dma - unmap the DMA memory being used for the request |
5b7d70c6 BD |
411 | * @hsotg: The device state. |
412 | * @hs_ep: The endpoint for the request | |
413 | * @hs_req: The request being processed. | |
414 | * | |
1f91b4cc | 415 | * This is the reverse of dwc2_hsotg_map_dma(), called for the completion |
5b7d70c6 | 416 | * of a request to ensure the buffer is ready for access by the caller. |
8b9bc460 | 417 | */ |
1f91b4cc | 418 | static void dwc2_hsotg_unmap_dma(struct dwc2_hsotg *hsotg, |
9da51974 | 419 | struct dwc2_hsotg_ep *hs_ep, |
1f91b4cc | 420 | struct dwc2_hsotg_req *hs_req) |
5b7d70c6 BD |
421 | { |
422 | struct usb_request *req = &hs_req->req; | |
9da51974 | 423 | |
17d966a3 | 424 | usb_gadget_unmap_request(&hsotg->gadget, req, hs_ep->dir_in); |
5b7d70c6 BD |
425 | } |
426 | ||
0f6b80c0 VA |
427 | /* |
428 | * dwc2_gadget_alloc_ctrl_desc_chains - allocate DMA descriptor chains | |
429 | * for Control endpoint | |
430 | * @hsotg: The device state. | |
431 | * | |
432 | * This function will allocate 4 descriptor chains for EP 0: 2 for | |
433 | * Setup stage, per one for IN and OUT data/status transactions. | |
434 | */ | |
435 | static int dwc2_gadget_alloc_ctrl_desc_chains(struct dwc2_hsotg *hsotg) | |
436 | { | |
437 | hsotg->setup_desc[0] = | |
438 | dmam_alloc_coherent(hsotg->dev, | |
439 | sizeof(struct dwc2_dma_desc), | |
440 | &hsotg->setup_desc_dma[0], | |
441 | GFP_KERNEL); | |
442 | if (!hsotg->setup_desc[0]) | |
443 | goto fail; | |
444 | ||
445 | hsotg->setup_desc[1] = | |
446 | dmam_alloc_coherent(hsotg->dev, | |
447 | sizeof(struct dwc2_dma_desc), | |
448 | &hsotg->setup_desc_dma[1], | |
449 | GFP_KERNEL); | |
450 | if (!hsotg->setup_desc[1]) | |
451 | goto fail; | |
452 | ||
453 | hsotg->ctrl_in_desc = | |
454 | dmam_alloc_coherent(hsotg->dev, | |
455 | sizeof(struct dwc2_dma_desc), | |
456 | &hsotg->ctrl_in_desc_dma, | |
457 | GFP_KERNEL); | |
458 | if (!hsotg->ctrl_in_desc) | |
459 | goto fail; | |
460 | ||
461 | hsotg->ctrl_out_desc = | |
462 | dmam_alloc_coherent(hsotg->dev, | |
463 | sizeof(struct dwc2_dma_desc), | |
464 | &hsotg->ctrl_out_desc_dma, | |
465 | GFP_KERNEL); | |
466 | if (!hsotg->ctrl_out_desc) | |
467 | goto fail; | |
468 | ||
469 | return 0; | |
470 | ||
471 | fail: | |
472 | return -ENOMEM; | |
473 | } | |
474 | ||
5b7d70c6 | 475 | /** |
1f91b4cc | 476 | * dwc2_hsotg_write_fifo - write packet Data to the TxFIFO |
5b7d70c6 BD |
477 | * @hsotg: The controller state. |
478 | * @hs_ep: The endpoint we're going to write for. | |
479 | * @hs_req: The request to write data for. | |
480 | * | |
481 | * This is called when the TxFIFO has some space in it to hold a new | |
482 | * transmission and we have something to give it. The actual setup of | |
483 | * the data size is done elsewhere, so all we have to do is to actually | |
484 | * write the data. | |
485 | * | |
486 | * The return value is zero if there is more space (or nothing was done) | |
487 | * otherwise -ENOSPC is returned if the FIFO space was used up. | |
488 | * | |
489 | * This routine is only needed for PIO | |
8b9bc460 | 490 | */ |
1f91b4cc | 491 | static int dwc2_hsotg_write_fifo(struct dwc2_hsotg *hsotg, |
9da51974 | 492 | struct dwc2_hsotg_ep *hs_ep, |
1f91b4cc | 493 | struct dwc2_hsotg_req *hs_req) |
5b7d70c6 BD |
494 | { |
495 | bool periodic = is_ep_periodic(hs_ep); | |
f25c42b8 | 496 | u32 gnptxsts = dwc2_readl(hsotg, GNPTXSTS); |
5b7d70c6 BD |
497 | int buf_pos = hs_req->req.actual; |
498 | int to_write = hs_ep->size_loaded; | |
499 | void *data; | |
500 | int can_write; | |
501 | int pkt_round; | |
4fca54aa | 502 | int max_transfer; |
5b7d70c6 BD |
503 | |
504 | to_write -= (buf_pos - hs_ep->last_load); | |
505 | ||
506 | /* if there's nothing to write, get out early */ | |
507 | if (to_write == 0) | |
508 | return 0; | |
509 | ||
10aebc77 | 510 | if (periodic && !hsotg->dedicated_fifos) { |
f25c42b8 | 511 | u32 epsize = dwc2_readl(hsotg, DIEPTSIZ(hs_ep->index)); |
5b7d70c6 BD |
512 | int size_left; |
513 | int size_done; | |
514 | ||
8b9bc460 LM |
515 | /* |
516 | * work out how much data was loaded so we can calculate | |
517 | * how much data is left in the fifo. | |
518 | */ | |
5b7d70c6 | 519 | |
47a1685f | 520 | size_left = DXEPTSIZ_XFERSIZE_GET(epsize); |
5b7d70c6 | 521 | |
8b9bc460 LM |
522 | /* |
523 | * if shared fifo, we cannot write anything until the | |
e7a9ff54 BD |
524 | * previous data has been completely sent. |
525 | */ | |
526 | if (hs_ep->fifo_load != 0) { | |
1f91b4cc | 527 | dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP); |
e7a9ff54 BD |
528 | return -ENOSPC; |
529 | } | |
530 | ||
5b7d70c6 BD |
531 | dev_dbg(hsotg->dev, "%s: left=%d, load=%d, fifo=%d, size %d\n", |
532 | __func__, size_left, | |
533 | hs_ep->size_loaded, hs_ep->fifo_load, hs_ep->fifo_size); | |
534 | ||
535 | /* how much of the data has moved */ | |
536 | size_done = hs_ep->size_loaded - size_left; | |
537 | ||
538 | /* how much data is left in the fifo */ | |
539 | can_write = hs_ep->fifo_load - size_done; | |
540 | dev_dbg(hsotg->dev, "%s: => can_write1=%d\n", | |
541 | __func__, can_write); | |
542 | ||
543 | can_write = hs_ep->fifo_size - can_write; | |
544 | dev_dbg(hsotg->dev, "%s: => can_write2=%d\n", | |
545 | __func__, can_write); | |
546 | ||
547 | if (can_write <= 0) { | |
1f91b4cc | 548 | dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP); |
5b7d70c6 BD |
549 | return -ENOSPC; |
550 | } | |
10aebc77 | 551 | } else if (hsotg->dedicated_fifos && hs_ep->index != 0) { |
f25c42b8 GS |
552 | can_write = dwc2_readl(hsotg, |
553 | DTXFSTS(hs_ep->fifo_index)); | |
10aebc77 BD |
554 | |
555 | can_write &= 0xffff; | |
556 | can_write *= 4; | |
5b7d70c6 | 557 | } else { |
47a1685f | 558 | if (GNPTXSTS_NP_TXQ_SPC_AVAIL_GET(gnptxsts) == 0) { |
5b7d70c6 BD |
559 | dev_dbg(hsotg->dev, |
560 | "%s: no queue slots available (0x%08x)\n", | |
561 | __func__, gnptxsts); | |
562 | ||
1f91b4cc | 563 | dwc2_hsotg_en_gsint(hsotg, GINTSTS_NPTXFEMP); |
5b7d70c6 BD |
564 | return -ENOSPC; |
565 | } | |
566 | ||
47a1685f | 567 | can_write = GNPTXSTS_NP_TXF_SPC_AVAIL_GET(gnptxsts); |
679f9b7c | 568 | can_write *= 4; /* fifo size is in 32bit quantities. */ |
5b7d70c6 BD |
569 | } |
570 | ||
4fca54aa RB |
571 | max_transfer = hs_ep->ep.maxpacket * hs_ep->mc; |
572 | ||
573 | dev_dbg(hsotg->dev, "%s: GNPTXSTS=%08x, can=%d, to=%d, max_transfer %d\n", | |
9da51974 | 574 | __func__, gnptxsts, can_write, to_write, max_transfer); |
5b7d70c6 | 575 | |
8b9bc460 LM |
576 | /* |
577 | * limit to 512 bytes of data, it seems at least on the non-periodic | |
5b7d70c6 BD |
578 | * FIFO, requests of >512 cause the endpoint to get stuck with a |
579 | * fragment of the end of the transfer in it. | |
580 | */ | |
811f3303 | 581 | if (can_write > 512 && !periodic) |
5b7d70c6 BD |
582 | can_write = 512; |
583 | ||
8b9bc460 LM |
584 | /* |
585 | * limit the write to one max-packet size worth of data, but allow | |
03e10e5a | 586 | * the transfer to return that it did not run out of fifo space |
8b9bc460 LM |
587 | * doing it. |
588 | */ | |
4fca54aa RB |
589 | if (to_write > max_transfer) { |
590 | to_write = max_transfer; | |
03e10e5a | 591 | |
5cb2ff0c RB |
592 | /* it's needed only when we do not use dedicated fifos */ |
593 | if (!hsotg->dedicated_fifos) | |
1f91b4cc | 594 | dwc2_hsotg_en_gsint(hsotg, |
9da51974 | 595 | periodic ? GINTSTS_PTXFEMP : |
47a1685f | 596 | GINTSTS_NPTXFEMP); |
03e10e5a BD |
597 | } |
598 | ||
5b7d70c6 BD |
599 | /* see if we can write data */ |
600 | ||
601 | if (to_write > can_write) { | |
602 | to_write = can_write; | |
4fca54aa | 603 | pkt_round = to_write % max_transfer; |
5b7d70c6 | 604 | |
8b9bc460 LM |
605 | /* |
606 | * Round the write down to an | |
5b7d70c6 BD |
607 | * exact number of packets. |
608 | * | |
609 | * Note, we do not currently check to see if we can ever | |
610 | * write a full packet or not to the FIFO. | |
611 | */ | |
612 | ||
613 | if (pkt_round) | |
614 | to_write -= pkt_round; | |
615 | ||
8b9bc460 LM |
616 | /* |
617 | * enable correct FIFO interrupt to alert us when there | |
618 | * is more room left. | |
619 | */ | |
5b7d70c6 | 620 | |
5cb2ff0c RB |
621 | /* it's needed only when we do not use dedicated fifos */ |
622 | if (!hsotg->dedicated_fifos) | |
1f91b4cc | 623 | dwc2_hsotg_en_gsint(hsotg, |
9da51974 | 624 | periodic ? GINTSTS_PTXFEMP : |
47a1685f | 625 | GINTSTS_NPTXFEMP); |
5b7d70c6 BD |
626 | } |
627 | ||
628 | dev_dbg(hsotg->dev, "write %d/%d, can_write %d, done %d\n", | |
9da51974 | 629 | to_write, hs_req->req.length, can_write, buf_pos); |
5b7d70c6 BD |
630 | |
631 | if (to_write <= 0) | |
632 | return -ENOSPC; | |
633 | ||
634 | hs_req->req.actual = buf_pos + to_write; | |
635 | hs_ep->total_data += to_write; | |
636 | ||
637 | if (periodic) | |
638 | hs_ep->fifo_load += to_write; | |
639 | ||
640 | to_write = DIV_ROUND_UP(to_write, 4); | |
641 | data = hs_req->req.buf + buf_pos; | |
642 | ||
342ccce1 | 643 | dwc2_writel_rep(hsotg, EPFIFO(hs_ep->index), data, to_write); |
5b7d70c6 BD |
644 | |
645 | return (to_write >= can_write) ? -ENOSPC : 0; | |
646 | } | |
647 | ||
648 | /** | |
649 | * get_ep_limit - get the maximum data legnth for this endpoint | |
650 | * @hs_ep: The endpoint | |
651 | * | |
652 | * Return the maximum data that can be queued in one go on a given endpoint | |
653 | * so that transfers that are too long can be split. | |
654 | */ | |
9da51974 | 655 | static unsigned int get_ep_limit(struct dwc2_hsotg_ep *hs_ep) |
5b7d70c6 BD |
656 | { |
657 | int index = hs_ep->index; | |
9da51974 JY |
658 | unsigned int maxsize; |
659 | unsigned int maxpkt; | |
5b7d70c6 BD |
660 | |
661 | if (index != 0) { | |
47a1685f DN |
662 | maxsize = DXEPTSIZ_XFERSIZE_LIMIT + 1; |
663 | maxpkt = DXEPTSIZ_PKTCNT_LIMIT + 1; | |
5b7d70c6 | 664 | } else { |
9da51974 | 665 | maxsize = 64 + 64; |
66e5c643 | 666 | if (hs_ep->dir_in) |
47a1685f | 667 | maxpkt = DIEPTSIZ0_PKTCNT_LIMIT + 1; |
66e5c643 | 668 | else |
5b7d70c6 | 669 | maxpkt = 2; |
5b7d70c6 BD |
670 | } |
671 | ||
672 | /* we made the constant loading easier above by using +1 */ | |
673 | maxpkt--; | |
674 | maxsize--; | |
675 | ||
8b9bc460 LM |
676 | /* |
677 | * constrain by packet count if maxpkts*pktsize is greater | |
678 | * than the length register size. | |
679 | */ | |
5b7d70c6 BD |
680 | |
681 | if ((maxpkt * hs_ep->ep.maxpacket) < maxsize) | |
682 | maxsize = maxpkt * hs_ep->ep.maxpacket; | |
683 | ||
684 | return maxsize; | |
685 | } | |
686 | ||
381fc8f8 | 687 | /** |
38beaec6 JY |
688 | * dwc2_hsotg_read_frameno - read current frame number |
689 | * @hsotg: The device instance | |
690 | * | |
691 | * Return the current frame number | |
692 | */ | |
381fc8f8 VM |
693 | static u32 dwc2_hsotg_read_frameno(struct dwc2_hsotg *hsotg) |
694 | { | |
695 | u32 dsts; | |
696 | ||
f25c42b8 | 697 | dsts = dwc2_readl(hsotg, DSTS); |
381fc8f8 VM |
698 | dsts &= DSTS_SOFFN_MASK; |
699 | dsts >>= DSTS_SOFFN_SHIFT; | |
700 | ||
701 | return dsts; | |
702 | } | |
703 | ||
cf77b5fb VA |
704 | /** |
705 | * dwc2_gadget_get_chain_limit - get the maximum data payload value of the | |
706 | * DMA descriptor chain prepared for specific endpoint | |
707 | * @hs_ep: The endpoint | |
708 | * | |
709 | * Return the maximum data that can be queued in one go on a given endpoint | |
710 | * depending on its descriptor chain capacity so that transfers that | |
711 | * are too long can be split. | |
712 | */ | |
713 | static unsigned int dwc2_gadget_get_chain_limit(struct dwc2_hsotg_ep *hs_ep) | |
714 | { | |
715 | int is_isoc = hs_ep->isochronous; | |
716 | unsigned int maxsize; | |
717 | ||
718 | if (is_isoc) | |
719 | maxsize = hs_ep->dir_in ? DEV_DMA_ISOC_TX_NBYTES_LIMIT : | |
720 | DEV_DMA_ISOC_RX_NBYTES_LIMIT; | |
721 | else | |
722 | maxsize = DEV_DMA_NBYTES_LIMIT; | |
723 | ||
724 | /* Above size of one descriptor was chosen, multiple it */ | |
725 | maxsize *= MAX_DMA_DESC_NUM_GENERIC; | |
726 | ||
727 | return maxsize; | |
728 | } | |
729 | ||
e02f9aa6 VA |
730 | /* |
731 | * dwc2_gadget_get_desc_params - get DMA descriptor parameters. | |
732 | * @hs_ep: The endpoint | |
733 | * @mask: RX/TX bytes mask to be defined | |
734 | * | |
735 | * Returns maximum data payload for one descriptor after analyzing endpoint | |
736 | * characteristics. | |
737 | * DMA descriptor transfer bytes limit depends on EP type: | |
738 | * Control out - MPS, | |
739 | * Isochronous - descriptor rx/tx bytes bitfield limit, | |
740 | * Control In/Bulk/Interrupt - multiple of mps. This will allow to not | |
741 | * have concatenations from various descriptors within one packet. | |
742 | * | |
743 | * Selects corresponding mask for RX/TX bytes as well. | |
744 | */ | |
745 | static u32 dwc2_gadget_get_desc_params(struct dwc2_hsotg_ep *hs_ep, u32 *mask) | |
746 | { | |
747 | u32 mps = hs_ep->ep.maxpacket; | |
748 | int dir_in = hs_ep->dir_in; | |
749 | u32 desc_size = 0; | |
750 | ||
751 | if (!hs_ep->index && !dir_in) { | |
752 | desc_size = mps; | |
753 | *mask = DEV_DMA_NBYTES_MASK; | |
754 | } else if (hs_ep->isochronous) { | |
755 | if (dir_in) { | |
756 | desc_size = DEV_DMA_ISOC_TX_NBYTES_LIMIT; | |
757 | *mask = DEV_DMA_ISOC_TX_NBYTES_MASK; | |
758 | } else { | |
759 | desc_size = DEV_DMA_ISOC_RX_NBYTES_LIMIT; | |
760 | *mask = DEV_DMA_ISOC_RX_NBYTES_MASK; | |
761 | } | |
762 | } else { | |
763 | desc_size = DEV_DMA_NBYTES_LIMIT; | |
764 | *mask = DEV_DMA_NBYTES_MASK; | |
765 | ||
766 | /* Round down desc_size to be mps multiple */ | |
767 | desc_size -= desc_size % mps; | |
768 | } | |
769 | ||
770 | return desc_size; | |
771 | } | |
772 | ||
10209abe AP |
773 | static void dwc2_gadget_fill_nonisoc_xfer_ddma_one(struct dwc2_hsotg_ep *hs_ep, |
774 | struct dwc2_dma_desc **desc, | |
e02f9aa6 | 775 | dma_addr_t dma_buff, |
10209abe AP |
776 | unsigned int len, |
777 | bool true_last) | |
e02f9aa6 | 778 | { |
e02f9aa6 | 779 | int dir_in = hs_ep->dir_in; |
e02f9aa6 VA |
780 | u32 mps = hs_ep->ep.maxpacket; |
781 | u32 maxsize = 0; | |
782 | u32 offset = 0; | |
783 | u32 mask = 0; | |
784 | int i; | |
785 | ||
786 | maxsize = dwc2_gadget_get_desc_params(hs_ep, &mask); | |
787 | ||
788 | hs_ep->desc_count = (len / maxsize) + | |
789 | ((len % maxsize) ? 1 : 0); | |
790 | if (len == 0) | |
791 | hs_ep->desc_count = 1; | |
792 | ||
793 | for (i = 0; i < hs_ep->desc_count; ++i) { | |
10209abe AP |
794 | (*desc)->status = 0; |
795 | (*desc)->status |= (DEV_DMA_BUFF_STS_HBUSY | |
e02f9aa6 VA |
796 | << DEV_DMA_BUFF_STS_SHIFT); |
797 | ||
798 | if (len > maxsize) { | |
799 | if (!hs_ep->index && !dir_in) | |
10209abe | 800 | (*desc)->status |= (DEV_DMA_L | DEV_DMA_IOC); |
e02f9aa6 | 801 | |
10209abe AP |
802 | (*desc)->status |= |
803 | maxsize << DEV_DMA_NBYTES_SHIFT & mask; | |
804 | (*desc)->buf = dma_buff + offset; | |
e02f9aa6 VA |
805 | |
806 | len -= maxsize; | |
807 | offset += maxsize; | |
808 | } else { | |
10209abe AP |
809 | if (true_last) |
810 | (*desc)->status |= (DEV_DMA_L | DEV_DMA_IOC); | |
e02f9aa6 VA |
811 | |
812 | if (dir_in) | |
10209abe AP |
813 | (*desc)->status |= (len % mps) ? DEV_DMA_SHORT : |
814 | ((hs_ep->send_zlp && true_last) ? | |
815 | DEV_DMA_SHORT : 0); | |
e02f9aa6 | 816 | |
10209abe | 817 | (*desc)->status |= |
e02f9aa6 | 818 | len << DEV_DMA_NBYTES_SHIFT & mask; |
10209abe | 819 | (*desc)->buf = dma_buff + offset; |
e02f9aa6 VA |
820 | } |
821 | ||
10209abe AP |
822 | (*desc)->status &= ~DEV_DMA_BUFF_STS_MASK; |
823 | (*desc)->status |= (DEV_DMA_BUFF_STS_HREADY | |
e02f9aa6 | 824 | << DEV_DMA_BUFF_STS_SHIFT); |
10209abe AP |
825 | (*desc)++; |
826 | } | |
827 | } | |
828 | ||
829 | /* | |
830 | * dwc2_gadget_config_nonisoc_xfer_ddma - prepare non ISOC DMA desc chain. | |
831 | * @hs_ep: The endpoint | |
832 | * @ureq: Request to transfer | |
833 | * @offset: offset in bytes | |
834 | * @len: Length of the transfer | |
835 | * | |
836 | * This function will iterate over descriptor chain and fill its entries | |
837 | * with corresponding information based on transfer data. | |
838 | */ | |
839 | static void dwc2_gadget_config_nonisoc_xfer_ddma(struct dwc2_hsotg_ep *hs_ep, | |
840 | struct usb_request *ureq, | |
841 | unsigned int offset, | |
842 | unsigned int len) | |
843 | { | |
844 | struct dwc2_dma_desc *desc = hs_ep->desc_list; | |
845 | struct scatterlist *sg; | |
846 | int i; | |
847 | u8 desc_count = 0; | |
848 | ||
849 | /* non-DMA sg buffer */ | |
850 | if (!ureq->num_sgs) { | |
851 | dwc2_gadget_fill_nonisoc_xfer_ddma_one(hs_ep, &desc, | |
852 | ureq->dma + offset, len, true); | |
853 | return; | |
e02f9aa6 | 854 | } |
10209abe AP |
855 | |
856 | /* DMA sg buffer */ | |
857 | for_each_sg(ureq->sg, sg, ureq->num_sgs, i) { | |
858 | dwc2_gadget_fill_nonisoc_xfer_ddma_one(hs_ep, &desc, | |
859 | sg_dma_address(sg) + sg->offset, sg_dma_len(sg), | |
860 | sg_is_last(sg)); | |
861 | desc_count += hs_ep->desc_count; | |
862 | } | |
863 | ||
864 | hs_ep->desc_count = desc_count; | |
e02f9aa6 VA |
865 | } |
866 | ||
540ccba0 VA |
867 | /* |
868 | * dwc2_gadget_fill_isoc_desc - fills next isochronous descriptor in chain. | |
869 | * @hs_ep: The isochronous endpoint. | |
870 | * @dma_buff: usb requests dma buffer. | |
871 | * @len: usb request transfer length. | |
872 | * | |
729cac69 | 873 | * Fills next free descriptor with the data of the arrived usb request, |
540ccba0 VA |
874 | * frame info, sets Last and IOC bits increments next_desc. If filled |
875 | * descriptor is not the first one, removes L bit from the previous descriptor | |
876 | * status. | |
877 | */ | |
878 | static int dwc2_gadget_fill_isoc_desc(struct dwc2_hsotg_ep *hs_ep, | |
879 | dma_addr_t dma_buff, unsigned int len) | |
880 | { | |
881 | struct dwc2_dma_desc *desc; | |
882 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
883 | u32 index; | |
884 | u32 maxsize = 0; | |
885 | u32 mask = 0; | |
1d8e5c00 | 886 | u8 pid = 0; |
540ccba0 VA |
887 | |
888 | maxsize = dwc2_gadget_get_desc_params(hs_ep, &mask); | |
540ccba0 | 889 | |
729cac69 MH |
890 | index = hs_ep->next_desc; |
891 | desc = &hs_ep->desc_list[index]; | |
540ccba0 | 892 | |
729cac69 MH |
893 | /* Check if descriptor chain full */ |
894 | if ((desc->status >> DEV_DMA_BUFF_STS_SHIFT) == | |
895 | DEV_DMA_BUFF_STS_HREADY) { | |
896 | dev_dbg(hsotg->dev, "%s: desc chain full\n", __func__); | |
897 | return 1; | |
540ccba0 VA |
898 | } |
899 | ||
540ccba0 VA |
900 | /* Clear L bit of previous desc if more than one entries in the chain */ |
901 | if (hs_ep->next_desc) | |
902 | hs_ep->desc_list[index - 1].status &= ~DEV_DMA_L; | |
903 | ||
904 | dev_dbg(hsotg->dev, "%s: Filling ep %d, dir %s isoc desc # %d\n", | |
905 | __func__, hs_ep->index, hs_ep->dir_in ? "in" : "out", index); | |
906 | ||
907 | desc->status = 0; | |
908 | desc->status |= (DEV_DMA_BUFF_STS_HBUSY << DEV_DMA_BUFF_STS_SHIFT); | |
909 | ||
910 | desc->buf = dma_buff; | |
911 | desc->status |= (DEV_DMA_L | DEV_DMA_IOC | | |
912 | ((len << DEV_DMA_NBYTES_SHIFT) & mask)); | |
913 | ||
914 | if (hs_ep->dir_in) { | |
1d8e5c00 MH |
915 | if (len) |
916 | pid = DIV_ROUND_UP(len, hs_ep->ep.maxpacket); | |
917 | else | |
918 | pid = 1; | |
919 | desc->status |= ((pid << DEV_DMA_ISOC_PID_SHIFT) & | |
540ccba0 VA |
920 | DEV_DMA_ISOC_PID_MASK) | |
921 | ((len % hs_ep->ep.maxpacket) ? | |
922 | DEV_DMA_SHORT : 0) | | |
923 | ((hs_ep->target_frame << | |
924 | DEV_DMA_ISOC_FRNUM_SHIFT) & | |
925 | DEV_DMA_ISOC_FRNUM_MASK); | |
926 | } | |
927 | ||
928 | desc->status &= ~DEV_DMA_BUFF_STS_MASK; | |
929 | desc->status |= (DEV_DMA_BUFF_STS_HREADY << DEV_DMA_BUFF_STS_SHIFT); | |
930 | ||
729cac69 MH |
931 | /* Increment frame number by interval for IN */ |
932 | if (hs_ep->dir_in) | |
933 | dwc2_gadget_incr_frame_num(hs_ep); | |
934 | ||
540ccba0 VA |
935 | /* Update index of last configured entry in the chain */ |
936 | hs_ep->next_desc++; | |
729cac69 MH |
937 | if (hs_ep->next_desc >= MAX_DMA_DESC_NUM_GENERIC) |
938 | hs_ep->next_desc = 0; | |
540ccba0 VA |
939 | |
940 | return 0; | |
941 | } | |
942 | ||
943 | /* | |
944 | * dwc2_gadget_start_isoc_ddma - start isochronous transfer in DDMA | |
945 | * @hs_ep: The isochronous endpoint. | |
946 | * | |
729cac69 | 947 | * Prepare descriptor chain for isochronous endpoints. Afterwards |
540ccba0 | 948 | * write DMA address to HW and enable the endpoint. |
540ccba0 VA |
949 | */ |
950 | static void dwc2_gadget_start_isoc_ddma(struct dwc2_hsotg_ep *hs_ep) | |
951 | { | |
952 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
953 | struct dwc2_hsotg_req *hs_req, *treq; | |
954 | int index = hs_ep->index; | |
955 | int ret; | |
729cac69 | 956 | int i; |
540ccba0 VA |
957 | u32 dma_reg; |
958 | u32 depctl; | |
959 | u32 ctrl; | |
729cac69 | 960 | struct dwc2_dma_desc *desc; |
540ccba0 VA |
961 | |
962 | if (list_empty(&hs_ep->queue)) { | |
1ffba905 | 963 | hs_ep->target_frame = TARGET_FRAME_INITIAL; |
540ccba0 VA |
964 | dev_dbg(hsotg->dev, "%s: No requests in queue\n", __func__); |
965 | return; | |
966 | } | |
967 | ||
729cac69 MH |
968 | /* Initialize descriptor chain by Host Busy status */ |
969 | for (i = 0; i < MAX_DMA_DESC_NUM_GENERIC; i++) { | |
970 | desc = &hs_ep->desc_list[i]; | |
971 | desc->status = 0; | |
972 | desc->status |= (DEV_DMA_BUFF_STS_HBUSY | |
973 | << DEV_DMA_BUFF_STS_SHIFT); | |
974 | } | |
975 | ||
976 | hs_ep->next_desc = 0; | |
540ccba0 | 977 | list_for_each_entry_safe(hs_req, treq, &hs_ep->queue, queue) { |
10209abe AP |
978 | dma_addr_t dma_addr = hs_req->req.dma; |
979 | ||
980 | if (hs_req->req.num_sgs) { | |
981 | WARN_ON(hs_req->req.num_sgs > 1); | |
982 | dma_addr = sg_dma_address(hs_req->req.sg); | |
983 | } | |
984 | ret = dwc2_gadget_fill_isoc_desc(hs_ep, dma_addr, | |
540ccba0 | 985 | hs_req->req.length); |
729cac69 | 986 | if (ret) |
540ccba0 | 987 | break; |
540ccba0 VA |
988 | } |
989 | ||
729cac69 | 990 | hs_ep->compl_desc = 0; |
540ccba0 VA |
991 | depctl = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index); |
992 | dma_reg = hs_ep->dir_in ? DIEPDMA(index) : DOEPDMA(index); | |
993 | ||
994 | /* write descriptor chain address to control register */ | |
f25c42b8 | 995 | dwc2_writel(hsotg, hs_ep->desc_list_dma, dma_reg); |
540ccba0 | 996 | |
f25c42b8 | 997 | ctrl = dwc2_readl(hsotg, depctl); |
540ccba0 | 998 | ctrl |= DXEPCTL_EPENA | DXEPCTL_CNAK; |
f25c42b8 | 999 | dwc2_writel(hsotg, ctrl, depctl); |
540ccba0 VA |
1000 | } |
1001 | ||
5b7d70c6 | 1002 | /** |
1f91b4cc | 1003 | * dwc2_hsotg_start_req - start a USB request from an endpoint's queue |
5b7d70c6 BD |
1004 | * @hsotg: The controller state. |
1005 | * @hs_ep: The endpoint to process a request for | |
1006 | * @hs_req: The request to start. | |
1007 | * @continuing: True if we are doing more for the current request. | |
1008 | * | |
1009 | * Start the given request running by setting the endpoint registers | |
1010 | * appropriately, and writing any data to the FIFOs. | |
1011 | */ | |
1f91b4cc | 1012 | static void dwc2_hsotg_start_req(struct dwc2_hsotg *hsotg, |
9da51974 | 1013 | struct dwc2_hsotg_ep *hs_ep, |
1f91b4cc | 1014 | struct dwc2_hsotg_req *hs_req, |
5b7d70c6 BD |
1015 | bool continuing) |
1016 | { | |
1017 | struct usb_request *ureq = &hs_req->req; | |
1018 | int index = hs_ep->index; | |
1019 | int dir_in = hs_ep->dir_in; | |
1020 | u32 epctrl_reg; | |
1021 | u32 epsize_reg; | |
1022 | u32 epsize; | |
1023 | u32 ctrl; | |
9da51974 JY |
1024 | unsigned int length; |
1025 | unsigned int packets; | |
1026 | unsigned int maxreq; | |
aa3e8bc8 | 1027 | unsigned int dma_reg; |
5b7d70c6 BD |
1028 | |
1029 | if (index != 0) { | |
1030 | if (hs_ep->req && !continuing) { | |
1031 | dev_err(hsotg->dev, "%s: active request\n", __func__); | |
1032 | WARN_ON(1); | |
1033 | return; | |
1034 | } else if (hs_ep->req != hs_req && continuing) { | |
1035 | dev_err(hsotg->dev, | |
1036 | "%s: continue different req\n", __func__); | |
1037 | WARN_ON(1); | |
1038 | return; | |
1039 | } | |
1040 | } | |
1041 | ||
aa3e8bc8 | 1042 | dma_reg = dir_in ? DIEPDMA(index) : DOEPDMA(index); |
94cb8fd6 LM |
1043 | epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index); |
1044 | epsize_reg = dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index); | |
5b7d70c6 BD |
1045 | |
1046 | dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n", | |
f25c42b8 | 1047 | __func__, dwc2_readl(hsotg, epctrl_reg), index, |
5b7d70c6 BD |
1048 | hs_ep->dir_in ? "in" : "out"); |
1049 | ||
9c39ddc6 | 1050 | /* If endpoint is stalled, we will restart request later */ |
f25c42b8 | 1051 | ctrl = dwc2_readl(hsotg, epctrl_reg); |
9c39ddc6 | 1052 | |
b2d4c54e | 1053 | if (index && ctrl & DXEPCTL_STALL) { |
9c39ddc6 AT |
1054 | dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index); |
1055 | return; | |
1056 | } | |
1057 | ||
5b7d70c6 | 1058 | length = ureq->length - ureq->actual; |
71225bee LM |
1059 | dev_dbg(hsotg->dev, "ureq->length:%d ureq->actual:%d\n", |
1060 | ureq->length, ureq->actual); | |
5b7d70c6 | 1061 | |
cf77b5fb VA |
1062 | if (!using_desc_dma(hsotg)) |
1063 | maxreq = get_ep_limit(hs_ep); | |
1064 | else | |
1065 | maxreq = dwc2_gadget_get_chain_limit(hs_ep); | |
1066 | ||
5b7d70c6 BD |
1067 | if (length > maxreq) { |
1068 | int round = maxreq % hs_ep->ep.maxpacket; | |
1069 | ||
1070 | dev_dbg(hsotg->dev, "%s: length %d, max-req %d, r %d\n", | |
1071 | __func__, length, maxreq, round); | |
1072 | ||
1073 | /* round down to multiple of packets */ | |
1074 | if (round) | |
1075 | maxreq -= round; | |
1076 | ||
1077 | length = maxreq; | |
1078 | } | |
1079 | ||
1080 | if (length) | |
1081 | packets = DIV_ROUND_UP(length, hs_ep->ep.maxpacket); | |
1082 | else | |
1083 | packets = 1; /* send one packet if length is zero. */ | |
1084 | ||
4fca54aa RB |
1085 | if (hs_ep->isochronous && length > (hs_ep->mc * hs_ep->ep.maxpacket)) { |
1086 | dev_err(hsotg->dev, "req length > maxpacket*mc\n"); | |
1087 | return; | |
1088 | } | |
1089 | ||
5b7d70c6 | 1090 | if (dir_in && index != 0) |
4fca54aa | 1091 | if (hs_ep->isochronous) |
47a1685f | 1092 | epsize = DXEPTSIZ_MC(packets); |
4fca54aa | 1093 | else |
47a1685f | 1094 | epsize = DXEPTSIZ_MC(1); |
5b7d70c6 BD |
1095 | else |
1096 | epsize = 0; | |
1097 | ||
f71b5e25 MYK |
1098 | /* |
1099 | * zero length packet should be programmed on its own and should not | |
1100 | * be counted in DIEPTSIZ.PktCnt with other packets. | |
1101 | */ | |
1102 | if (dir_in && ureq->zero && !continuing) { | |
1103 | /* Test if zlp is actually required. */ | |
1104 | if ((ureq->length >= hs_ep->ep.maxpacket) && | |
9da51974 | 1105 | !(ureq->length % hs_ep->ep.maxpacket)) |
8a20fa45 | 1106 | hs_ep->send_zlp = 1; |
5b7d70c6 BD |
1107 | } |
1108 | ||
47a1685f DN |
1109 | epsize |= DXEPTSIZ_PKTCNT(packets); |
1110 | epsize |= DXEPTSIZ_XFERSIZE(length); | |
5b7d70c6 BD |
1111 | |
1112 | dev_dbg(hsotg->dev, "%s: %d@%d/%d, 0x%08x => 0x%08x\n", | |
1113 | __func__, packets, length, ureq->length, epsize, epsize_reg); | |
1114 | ||
1115 | /* store the request as the current one we're doing */ | |
1116 | hs_ep->req = hs_req; | |
1117 | ||
aa3e8bc8 VA |
1118 | if (using_desc_dma(hsotg)) { |
1119 | u32 offset = 0; | |
1120 | u32 mps = hs_ep->ep.maxpacket; | |
1121 | ||
1122 | /* Adjust length: EP0 - MPS, other OUT EPs - multiple of MPS */ | |
1123 | if (!dir_in) { | |
1124 | if (!index) | |
1125 | length = mps; | |
1126 | else if (length % mps) | |
1127 | length += (mps - (length % mps)); | |
1128 | } | |
5b7d70c6 | 1129 | |
8b9bc460 | 1130 | /* |
aa3e8bc8 VA |
1131 | * If more data to send, adjust DMA for EP0 out data stage. |
1132 | * ureq->dma stays unchanged, hence increment it by already | |
1133 | * passed passed data count before starting new transaction. | |
8b9bc460 | 1134 | */ |
aa3e8bc8 VA |
1135 | if (!index && hsotg->ep0_state == DWC2_EP0_DATA_OUT && |
1136 | continuing) | |
1137 | offset = ureq->actual; | |
1138 | ||
1139 | /* Fill DDMA chain entries */ | |
10209abe | 1140 | dwc2_gadget_config_nonisoc_xfer_ddma(hs_ep, ureq, offset, |
aa3e8bc8 VA |
1141 | length); |
1142 | ||
1143 | /* write descriptor chain address to control register */ | |
f25c42b8 | 1144 | dwc2_writel(hsotg, hs_ep->desc_list_dma, dma_reg); |
5b7d70c6 | 1145 | |
aa3e8bc8 VA |
1146 | dev_dbg(hsotg->dev, "%s: %08x pad => 0x%08x\n", |
1147 | __func__, (u32)hs_ep->desc_list_dma, dma_reg); | |
1148 | } else { | |
1149 | /* write size / packets */ | |
f25c42b8 | 1150 | dwc2_writel(hsotg, epsize, epsize_reg); |
aa3e8bc8 | 1151 | |
729e6574 | 1152 | if (using_dma(hsotg) && !continuing && (length != 0)) { |
aa3e8bc8 VA |
1153 | /* |
1154 | * write DMA address to control register, buffer | |
1155 | * already synced by dwc2_hsotg_ep_queue(). | |
1156 | */ | |
5b7d70c6 | 1157 | |
f25c42b8 | 1158 | dwc2_writel(hsotg, ureq->dma, dma_reg); |
aa3e8bc8 VA |
1159 | |
1160 | dev_dbg(hsotg->dev, "%s: %pad => 0x%08x\n", | |
1161 | __func__, &ureq->dma, dma_reg); | |
1162 | } | |
5b7d70c6 BD |
1163 | } |
1164 | ||
837e9f00 VM |
1165 | if (hs_ep->isochronous && hs_ep->interval == 1) { |
1166 | hs_ep->target_frame = dwc2_hsotg_read_frameno(hsotg); | |
1167 | dwc2_gadget_incr_frame_num(hs_ep); | |
1168 | ||
1169 | if (hs_ep->target_frame & 0x1) | |
1170 | ctrl |= DXEPCTL_SETODDFR; | |
1171 | else | |
1172 | ctrl |= DXEPCTL_SETEVENFR; | |
1173 | } | |
1174 | ||
47a1685f | 1175 | ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */ |
71225bee | 1176 | |
fe0b94ab | 1177 | dev_dbg(hsotg->dev, "ep0 state:%d\n", hsotg->ep0_state); |
71225bee LM |
1178 | |
1179 | /* For Setup request do not clear NAK */ | |
fe0b94ab | 1180 | if (!(index == 0 && hsotg->ep0_state == DWC2_EP0_SETUP)) |
47a1685f | 1181 | ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */ |
71225bee | 1182 | |
5b7d70c6 | 1183 | dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl); |
f25c42b8 | 1184 | dwc2_writel(hsotg, ctrl, epctrl_reg); |
5b7d70c6 | 1185 | |
8b9bc460 LM |
1186 | /* |
1187 | * set these, it seems that DMA support increments past the end | |
5b7d70c6 | 1188 | * of the packet buffer so we need to calculate the length from |
8b9bc460 LM |
1189 | * this information. |
1190 | */ | |
5b7d70c6 BD |
1191 | hs_ep->size_loaded = length; |
1192 | hs_ep->last_load = ureq->actual; | |
1193 | ||
1194 | if (dir_in && !using_dma(hsotg)) { | |
1195 | /* set these anyway, we may need them for non-periodic in */ | |
1196 | hs_ep->fifo_load = 0; | |
1197 | ||
1f91b4cc | 1198 | dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req); |
5b7d70c6 BD |
1199 | } |
1200 | ||
8b9bc460 LM |
1201 | /* |
1202 | * Note, trying to clear the NAK here causes problems with transmit | |
1203 | * on the S3C6400 ending up with the TXFIFO becoming full. | |
1204 | */ | |
5b7d70c6 BD |
1205 | |
1206 | /* check ep is enabled */ | |
f25c42b8 | 1207 | if (!(dwc2_readl(hsotg, epctrl_reg) & DXEPCTL_EPENA)) |
1a0ed863 | 1208 | dev_dbg(hsotg->dev, |
9da51974 | 1209 | "ep%d: failed to become enabled (DXEPCTL=0x%08x)?\n", |
f25c42b8 | 1210 | index, dwc2_readl(hsotg, epctrl_reg)); |
5b7d70c6 | 1211 | |
47a1685f | 1212 | dev_dbg(hsotg->dev, "%s: DXEPCTL=0x%08x\n", |
f25c42b8 | 1213 | __func__, dwc2_readl(hsotg, epctrl_reg)); |
afcf4169 RB |
1214 | |
1215 | /* enable ep interrupts */ | |
1f91b4cc | 1216 | dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 1); |
5b7d70c6 BD |
1217 | } |
1218 | ||
1219 | /** | |
1f91b4cc | 1220 | * dwc2_hsotg_map_dma - map the DMA memory being used for the request |
5b7d70c6 BD |
1221 | * @hsotg: The device state. |
1222 | * @hs_ep: The endpoint the request is on. | |
1223 | * @req: The request being processed. | |
1224 | * | |
1225 | * We've been asked to queue a request, so ensure that the memory buffer | |
1226 | * is correctly setup for DMA. If we've been passed an extant DMA address | |
1227 | * then ensure the buffer has been synced to memory. If our buffer has no | |
1228 | * DMA memory, then we map the memory and mark our request to allow us to | |
1229 | * cleanup on completion. | |
8b9bc460 | 1230 | */ |
1f91b4cc | 1231 | static int dwc2_hsotg_map_dma(struct dwc2_hsotg *hsotg, |
9da51974 | 1232 | struct dwc2_hsotg_ep *hs_ep, |
5b7d70c6 BD |
1233 | struct usb_request *req) |
1234 | { | |
e58ebcd1 | 1235 | int ret; |
5b7d70c6 | 1236 | |
e58ebcd1 FB |
1237 | ret = usb_gadget_map_request(&hsotg->gadget, req, hs_ep->dir_in); |
1238 | if (ret) | |
1239 | goto dma_error; | |
5b7d70c6 BD |
1240 | |
1241 | return 0; | |
1242 | ||
1243 | dma_error: | |
1244 | dev_err(hsotg->dev, "%s: failed to map buffer %p, %d bytes\n", | |
1245 | __func__, req->buf, req->length); | |
1246 | ||
1247 | return -EIO; | |
1248 | } | |
1249 | ||
1f91b4cc | 1250 | static int dwc2_hsotg_handle_unaligned_buf_start(struct dwc2_hsotg *hsotg, |
b98866c2 JY |
1251 | struct dwc2_hsotg_ep *hs_ep, |
1252 | struct dwc2_hsotg_req *hs_req) | |
7d24c1b5 MYK |
1253 | { |
1254 | void *req_buf = hs_req->req.buf; | |
1255 | ||
1256 | /* If dma is not being used or buffer is aligned */ | |
1257 | if (!using_dma(hsotg) || !((long)req_buf & 3)) | |
1258 | return 0; | |
1259 | ||
1260 | WARN_ON(hs_req->saved_req_buf); | |
1261 | ||
1262 | dev_dbg(hsotg->dev, "%s: %s: buf=%p length=%d\n", __func__, | |
9da51974 | 1263 | hs_ep->ep.name, req_buf, hs_req->req.length); |
7d24c1b5 MYK |
1264 | |
1265 | hs_req->req.buf = kmalloc(hs_req->req.length, GFP_ATOMIC); | |
1266 | if (!hs_req->req.buf) { | |
1267 | hs_req->req.buf = req_buf; | |
1268 | dev_err(hsotg->dev, | |
1269 | "%s: unable to allocate memory for bounce buffer\n", | |
1270 | __func__); | |
1271 | return -ENOMEM; | |
1272 | } | |
1273 | ||
1274 | /* Save actual buffer */ | |
1275 | hs_req->saved_req_buf = req_buf; | |
1276 | ||
1277 | if (hs_ep->dir_in) | |
1278 | memcpy(hs_req->req.buf, req_buf, hs_req->req.length); | |
1279 | return 0; | |
1280 | } | |
1281 | ||
b98866c2 JY |
1282 | static void |
1283 | dwc2_hsotg_handle_unaligned_buf_complete(struct dwc2_hsotg *hsotg, | |
1284 | struct dwc2_hsotg_ep *hs_ep, | |
1285 | struct dwc2_hsotg_req *hs_req) | |
7d24c1b5 MYK |
1286 | { |
1287 | /* If dma is not being used or buffer was aligned */ | |
1288 | if (!using_dma(hsotg) || !hs_req->saved_req_buf) | |
1289 | return; | |
1290 | ||
1291 | dev_dbg(hsotg->dev, "%s: %s: status=%d actual-length=%d\n", __func__, | |
1292 | hs_ep->ep.name, hs_req->req.status, hs_req->req.actual); | |
1293 | ||
1294 | /* Copy data from bounce buffer on successful out transfer */ | |
1295 | if (!hs_ep->dir_in && !hs_req->req.status) | |
1296 | memcpy(hs_req->saved_req_buf, hs_req->req.buf, | |
9da51974 | 1297 | hs_req->req.actual); |
7d24c1b5 MYK |
1298 | |
1299 | /* Free bounce buffer */ | |
1300 | kfree(hs_req->req.buf); | |
1301 | ||
1302 | hs_req->req.buf = hs_req->saved_req_buf; | |
1303 | hs_req->saved_req_buf = NULL; | |
1304 | } | |
1305 | ||
381fc8f8 VM |
1306 | /** |
1307 | * dwc2_gadget_target_frame_elapsed - Checks target frame | |
1308 | * @hs_ep: The driver endpoint to check | |
1309 | * | |
1310 | * Returns 1 if targeted frame elapsed. If returned 1 then we need to drop | |
1311 | * corresponding transfer. | |
1312 | */ | |
1313 | static bool dwc2_gadget_target_frame_elapsed(struct dwc2_hsotg_ep *hs_ep) | |
1314 | { | |
1315 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
1316 | u32 target_frame = hs_ep->target_frame; | |
c7c24e7a | 1317 | u32 current_frame = hsotg->frame_number; |
381fc8f8 VM |
1318 | bool frame_overrun = hs_ep->frame_overrun; |
1319 | ||
1320 | if (!frame_overrun && current_frame >= target_frame) | |
1321 | return true; | |
1322 | ||
1323 | if (frame_overrun && current_frame >= target_frame && | |
1324 | ((current_frame - target_frame) < DSTS_SOFFN_LIMIT / 2)) | |
1325 | return true; | |
1326 | ||
1327 | return false; | |
1328 | } | |
1329 | ||
e02f9aa6 VA |
1330 | /* |
1331 | * dwc2_gadget_set_ep0_desc_chain - Set EP's desc chain pointers | |
1332 | * @hsotg: The driver state | |
1333 | * @hs_ep: the ep descriptor chain is for | |
1334 | * | |
1335 | * Called to update EP0 structure's pointers depend on stage of | |
1336 | * control transfer. | |
1337 | */ | |
1338 | static int dwc2_gadget_set_ep0_desc_chain(struct dwc2_hsotg *hsotg, | |
1339 | struct dwc2_hsotg_ep *hs_ep) | |
1340 | { | |
1341 | switch (hsotg->ep0_state) { | |
1342 | case DWC2_EP0_SETUP: | |
1343 | case DWC2_EP0_STATUS_OUT: | |
1344 | hs_ep->desc_list = hsotg->setup_desc[0]; | |
1345 | hs_ep->desc_list_dma = hsotg->setup_desc_dma[0]; | |
1346 | break; | |
1347 | case DWC2_EP0_DATA_IN: | |
1348 | case DWC2_EP0_STATUS_IN: | |
1349 | hs_ep->desc_list = hsotg->ctrl_in_desc; | |
1350 | hs_ep->desc_list_dma = hsotg->ctrl_in_desc_dma; | |
1351 | break; | |
1352 | case DWC2_EP0_DATA_OUT: | |
1353 | hs_ep->desc_list = hsotg->ctrl_out_desc; | |
1354 | hs_ep->desc_list_dma = hsotg->ctrl_out_desc_dma; | |
1355 | break; | |
1356 | default: | |
1357 | dev_err(hsotg->dev, "invalid EP 0 state in queue %d\n", | |
1358 | hsotg->ep0_state); | |
1359 | return -EINVAL; | |
1360 | } | |
1361 | ||
1362 | return 0; | |
1363 | } | |
1364 | ||
1f91b4cc | 1365 | static int dwc2_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req, |
9da51974 | 1366 | gfp_t gfp_flags) |
5b7d70c6 | 1367 | { |
1f91b4cc FB |
1368 | struct dwc2_hsotg_req *hs_req = our_req(req); |
1369 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); | |
941fcce4 | 1370 | struct dwc2_hsotg *hs = hs_ep->parent; |
5b7d70c6 | 1371 | bool first; |
7d24c1b5 | 1372 | int ret; |
729cac69 MH |
1373 | u32 maxsize = 0; |
1374 | u32 mask = 0; | |
1375 | ||
5b7d70c6 BD |
1376 | |
1377 | dev_dbg(hs->dev, "%s: req %p: %d@%p, noi=%d, zero=%d, snok=%d\n", | |
1378 | ep->name, req, req->length, req->buf, req->no_interrupt, | |
1379 | req->zero, req->short_not_ok); | |
1380 | ||
7ababa92 | 1381 | /* Prevent new request submission when controller is suspended */ |
88b02f2c GT |
1382 | if (hs->lx_state != DWC2_L0) { |
1383 | dev_dbg(hs->dev, "%s: submit request only in active state\n", | |
9da51974 | 1384 | __func__); |
7ababa92 GH |
1385 | return -EAGAIN; |
1386 | } | |
1387 | ||
5b7d70c6 BD |
1388 | /* initialise status of the request */ |
1389 | INIT_LIST_HEAD(&hs_req->queue); | |
1390 | req->actual = 0; | |
1391 | req->status = -EINPROGRESS; | |
1392 | ||
729cac69 MH |
1393 | /* In DDMA mode for ISOC's don't queue request if length greater |
1394 | * than descriptor limits. | |
1395 | */ | |
1396 | if (using_desc_dma(hs) && hs_ep->isochronous) { | |
1397 | maxsize = dwc2_gadget_get_desc_params(hs_ep, &mask); | |
1398 | if (hs_ep->dir_in && req->length > maxsize) { | |
1399 | dev_err(hs->dev, "wrong length %d (maxsize=%d)\n", | |
1400 | req->length, maxsize); | |
1401 | return -EINVAL; | |
1402 | } | |
1403 | ||
1404 | if (!hs_ep->dir_in && req->length > hs_ep->ep.maxpacket) { | |
1405 | dev_err(hs->dev, "ISOC OUT: wrong length %d (mps=%d)\n", | |
1406 | req->length, hs_ep->ep.maxpacket); | |
1407 | return -EINVAL; | |
1408 | } | |
1409 | } | |
1410 | ||
1f91b4cc | 1411 | ret = dwc2_hsotg_handle_unaligned_buf_start(hs, hs_ep, hs_req); |
7d24c1b5 MYK |
1412 | if (ret) |
1413 | return ret; | |
1414 | ||
5b7d70c6 BD |
1415 | /* if we're using DMA, sync the buffers as necessary */ |
1416 | if (using_dma(hs)) { | |
1f91b4cc | 1417 | ret = dwc2_hsotg_map_dma(hs, hs_ep, req); |
5b7d70c6 BD |
1418 | if (ret) |
1419 | return ret; | |
1420 | } | |
e02f9aa6 VA |
1421 | /* If using descriptor DMA configure EP0 descriptor chain pointers */ |
1422 | if (using_desc_dma(hs) && !hs_ep->index) { | |
1423 | ret = dwc2_gadget_set_ep0_desc_chain(hs, hs_ep); | |
1424 | if (ret) | |
1425 | return ret; | |
1426 | } | |
5b7d70c6 | 1427 | |
5b7d70c6 BD |
1428 | first = list_empty(&hs_ep->queue); |
1429 | list_add_tail(&hs_req->queue, &hs_ep->queue); | |
1430 | ||
540ccba0 VA |
1431 | /* |
1432 | * Handle DDMA isochronous transfers separately - just add new entry | |
729cac69 | 1433 | * to the descriptor chain. |
540ccba0 VA |
1434 | * Transfer will be started once SW gets either one of NAK or |
1435 | * OutTknEpDis interrupts. | |
1436 | */ | |
729cac69 MH |
1437 | if (using_desc_dma(hs) && hs_ep->isochronous) { |
1438 | if (hs_ep->target_frame != TARGET_FRAME_INITIAL) { | |
10209abe AP |
1439 | dma_addr_t dma_addr = hs_req->req.dma; |
1440 | ||
1441 | if (hs_req->req.num_sgs) { | |
1442 | WARN_ON(hs_req->req.num_sgs > 1); | |
1443 | dma_addr = sg_dma_address(hs_req->req.sg); | |
1444 | } | |
1445 | dwc2_gadget_fill_isoc_desc(hs_ep, dma_addr, | |
729cac69 MH |
1446 | hs_req->req.length); |
1447 | } | |
540ccba0 VA |
1448 | return 0; |
1449 | } | |
1450 | ||
b4c53b4a MH |
1451 | /* Change EP direction if status phase request is after data out */ |
1452 | if (!hs_ep->index && !req->length && !hs_ep->dir_in && | |
1453 | hs->ep0_state == DWC2_EP0_DATA_OUT) | |
1454 | hs_ep->dir_in = 1; | |
1455 | ||
837e9f00 VM |
1456 | if (first) { |
1457 | if (!hs_ep->isochronous) { | |
1458 | dwc2_hsotg_start_req(hs, hs_ep, hs_req, false); | |
1459 | return 0; | |
1460 | } | |
1461 | ||
c7c24e7a AP |
1462 | /* Update current frame number value. */ |
1463 | hs->frame_number = dwc2_hsotg_read_frameno(hs); | |
1464 | while (dwc2_gadget_target_frame_elapsed(hs_ep)) { | |
837e9f00 | 1465 | dwc2_gadget_incr_frame_num(hs_ep); |
c7c24e7a AP |
1466 | /* Update current frame number value once more as it |
1467 | * changes here. | |
1468 | */ | |
1469 | hs->frame_number = dwc2_hsotg_read_frameno(hs); | |
1470 | } | |
5b7d70c6 | 1471 | |
837e9f00 VM |
1472 | if (hs_ep->target_frame != TARGET_FRAME_INITIAL) |
1473 | dwc2_hsotg_start_req(hs, hs_ep, hs_req, false); | |
1474 | } | |
5b7d70c6 BD |
1475 | return 0; |
1476 | } | |
1477 | ||
1f91b4cc | 1478 | static int dwc2_hsotg_ep_queue_lock(struct usb_ep *ep, struct usb_request *req, |
9da51974 | 1479 | gfp_t gfp_flags) |
5ad1d316 | 1480 | { |
1f91b4cc | 1481 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 1482 | struct dwc2_hsotg *hs = hs_ep->parent; |
5ad1d316 LM |
1483 | unsigned long flags = 0; |
1484 | int ret = 0; | |
1485 | ||
1486 | spin_lock_irqsave(&hs->lock, flags); | |
1f91b4cc | 1487 | ret = dwc2_hsotg_ep_queue(ep, req, gfp_flags); |
5ad1d316 LM |
1488 | spin_unlock_irqrestore(&hs->lock, flags); |
1489 | ||
1490 | return ret; | |
1491 | } | |
1492 | ||
1f91b4cc | 1493 | static void dwc2_hsotg_ep_free_request(struct usb_ep *ep, |
9da51974 | 1494 | struct usb_request *req) |
5b7d70c6 | 1495 | { |
1f91b4cc | 1496 | struct dwc2_hsotg_req *hs_req = our_req(req); |
5b7d70c6 BD |
1497 | |
1498 | kfree(hs_req); | |
1499 | } | |
1500 | ||
1501 | /** | |
1f91b4cc | 1502 | * dwc2_hsotg_complete_oursetup - setup completion callback |
5b7d70c6 BD |
1503 | * @ep: The endpoint the request was on. |
1504 | * @req: The request completed. | |
1505 | * | |
1506 | * Called on completion of any requests the driver itself | |
1507 | * submitted that need cleaning up. | |
1508 | */ | |
1f91b4cc | 1509 | static void dwc2_hsotg_complete_oursetup(struct usb_ep *ep, |
9da51974 | 1510 | struct usb_request *req) |
5b7d70c6 | 1511 | { |
1f91b4cc | 1512 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 1513 | struct dwc2_hsotg *hsotg = hs_ep->parent; |
5b7d70c6 BD |
1514 | |
1515 | dev_dbg(hsotg->dev, "%s: ep %p, req %p\n", __func__, ep, req); | |
1516 | ||
1f91b4cc | 1517 | dwc2_hsotg_ep_free_request(ep, req); |
5b7d70c6 BD |
1518 | } |
1519 | ||
1520 | /** | |
1521 | * ep_from_windex - convert control wIndex value to endpoint | |
1522 | * @hsotg: The driver state. | |
1523 | * @windex: The control request wIndex field (in host order). | |
1524 | * | |
1525 | * Convert the given wIndex into a pointer to an driver endpoint | |
1526 | * structure, or return NULL if it is not a valid endpoint. | |
8b9bc460 | 1527 | */ |
1f91b4cc | 1528 | static struct dwc2_hsotg_ep *ep_from_windex(struct dwc2_hsotg *hsotg, |
9da51974 | 1529 | u32 windex) |
5b7d70c6 | 1530 | { |
1f91b4cc | 1531 | struct dwc2_hsotg_ep *ep; |
5b7d70c6 BD |
1532 | int dir = (windex & USB_DIR_IN) ? 1 : 0; |
1533 | int idx = windex & 0x7F; | |
1534 | ||
1535 | if (windex >= 0x100) | |
1536 | return NULL; | |
1537 | ||
b3f489b2 | 1538 | if (idx > hsotg->num_of_eps) |
5b7d70c6 BD |
1539 | return NULL; |
1540 | ||
c6f5c050 MYK |
1541 | ep = index_to_ep(hsotg, idx, dir); |
1542 | ||
5b7d70c6 BD |
1543 | if (idx && ep->dir_in != dir) |
1544 | return NULL; | |
1545 | ||
1546 | return ep; | |
1547 | } | |
1548 | ||
9e14d0a5 | 1549 | /** |
1f91b4cc | 1550 | * dwc2_hsotg_set_test_mode - Enable usb Test Modes |
9e14d0a5 GH |
1551 | * @hsotg: The driver state. |
1552 | * @testmode: requested usb test mode | |
1553 | * Enable usb Test Mode requested by the Host. | |
1554 | */ | |
1f91b4cc | 1555 | int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode) |
9e14d0a5 | 1556 | { |
f25c42b8 | 1557 | int dctl = dwc2_readl(hsotg, DCTL); |
9e14d0a5 GH |
1558 | |
1559 | dctl &= ~DCTL_TSTCTL_MASK; | |
1560 | switch (testmode) { | |
1561 | case TEST_J: | |
1562 | case TEST_K: | |
1563 | case TEST_SE0_NAK: | |
1564 | case TEST_PACKET: | |
1565 | case TEST_FORCE_EN: | |
1566 | dctl |= testmode << DCTL_TSTCTL_SHIFT; | |
1567 | break; | |
1568 | default: | |
1569 | return -EINVAL; | |
1570 | } | |
f25c42b8 | 1571 | dwc2_writel(hsotg, dctl, DCTL); |
9e14d0a5 GH |
1572 | return 0; |
1573 | } | |
1574 | ||
5b7d70c6 | 1575 | /** |
1f91b4cc | 1576 | * dwc2_hsotg_send_reply - send reply to control request |
5b7d70c6 BD |
1577 | * @hsotg: The device state |
1578 | * @ep: Endpoint 0 | |
1579 | * @buff: Buffer for request | |
1580 | * @length: Length of reply. | |
1581 | * | |
1582 | * Create a request and queue it on the given endpoint. This is useful as | |
1583 | * an internal method of sending replies to certain control requests, etc. | |
1584 | */ | |
1f91b4cc | 1585 | static int dwc2_hsotg_send_reply(struct dwc2_hsotg *hsotg, |
9da51974 | 1586 | struct dwc2_hsotg_ep *ep, |
5b7d70c6 BD |
1587 | void *buff, |
1588 | int length) | |
1589 | { | |
1590 | struct usb_request *req; | |
1591 | int ret; | |
1592 | ||
1593 | dev_dbg(hsotg->dev, "%s: buff %p, len %d\n", __func__, buff, length); | |
1594 | ||
1f91b4cc | 1595 | req = dwc2_hsotg_ep_alloc_request(&ep->ep, GFP_ATOMIC); |
5b7d70c6 BD |
1596 | hsotg->ep0_reply = req; |
1597 | if (!req) { | |
1598 | dev_warn(hsotg->dev, "%s: cannot alloc req\n", __func__); | |
1599 | return -ENOMEM; | |
1600 | } | |
1601 | ||
1602 | req->buf = hsotg->ep0_buff; | |
1603 | req->length = length; | |
f71b5e25 MYK |
1604 | /* |
1605 | * zero flag is for sending zlp in DATA IN stage. It has no impact on | |
1606 | * STATUS stage. | |
1607 | */ | |
1608 | req->zero = 0; | |
1f91b4cc | 1609 | req->complete = dwc2_hsotg_complete_oursetup; |
5b7d70c6 BD |
1610 | |
1611 | if (length) | |
1612 | memcpy(req->buf, buff, length); | |
5b7d70c6 | 1613 | |
1f91b4cc | 1614 | ret = dwc2_hsotg_ep_queue(&ep->ep, req, GFP_ATOMIC); |
5b7d70c6 BD |
1615 | if (ret) { |
1616 | dev_warn(hsotg->dev, "%s: cannot queue req\n", __func__); | |
1617 | return ret; | |
1618 | } | |
1619 | ||
1620 | return 0; | |
1621 | } | |
1622 | ||
1623 | /** | |
1f91b4cc | 1624 | * dwc2_hsotg_process_req_status - process request GET_STATUS |
5b7d70c6 BD |
1625 | * @hsotg: The device state |
1626 | * @ctrl: USB control request | |
1627 | */ | |
1f91b4cc | 1628 | static int dwc2_hsotg_process_req_status(struct dwc2_hsotg *hsotg, |
9da51974 | 1629 | struct usb_ctrlrequest *ctrl) |
5b7d70c6 | 1630 | { |
1f91b4cc FB |
1631 | struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0]; |
1632 | struct dwc2_hsotg_ep *ep; | |
5b7d70c6 BD |
1633 | __le16 reply; |
1634 | int ret; | |
1635 | ||
1636 | dev_dbg(hsotg->dev, "%s: USB_REQ_GET_STATUS\n", __func__); | |
1637 | ||
1638 | if (!ep0->dir_in) { | |
1639 | dev_warn(hsotg->dev, "%s: direction out?\n", __func__); | |
1640 | return -EINVAL; | |
1641 | } | |
1642 | ||
1643 | switch (ctrl->bRequestType & USB_RECIP_MASK) { | |
1644 | case USB_RECIP_DEVICE: | |
38beaec6 JY |
1645 | /* |
1646 | * bit 0 => self powered | |
1647 | * bit 1 => remote wakeup | |
1648 | */ | |
1649 | reply = cpu_to_le16(0); | |
5b7d70c6 BD |
1650 | break; |
1651 | ||
1652 | case USB_RECIP_INTERFACE: | |
1653 | /* currently, the data result should be zero */ | |
1654 | reply = cpu_to_le16(0); | |
1655 | break; | |
1656 | ||
1657 | case USB_RECIP_ENDPOINT: | |
1658 | ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex)); | |
1659 | if (!ep) | |
1660 | return -ENOENT; | |
1661 | ||
1662 | reply = cpu_to_le16(ep->halted ? 1 : 0); | |
1663 | break; | |
1664 | ||
1665 | default: | |
1666 | return 0; | |
1667 | } | |
1668 | ||
1669 | if (le16_to_cpu(ctrl->wLength) != 2) | |
1670 | return -EINVAL; | |
1671 | ||
1f91b4cc | 1672 | ret = dwc2_hsotg_send_reply(hsotg, ep0, &reply, 2); |
5b7d70c6 BD |
1673 | if (ret) { |
1674 | dev_err(hsotg->dev, "%s: failed to send reply\n", __func__); | |
1675 | return ret; | |
1676 | } | |
1677 | ||
1678 | return 1; | |
1679 | } | |
1680 | ||
51da43b5 | 1681 | static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now); |
5b7d70c6 | 1682 | |
9c39ddc6 AT |
1683 | /** |
1684 | * get_ep_head - return the first request on the endpoint | |
1685 | * @hs_ep: The controller endpoint to get | |
1686 | * | |
1687 | * Get the first request on the endpoint. | |
1688 | */ | |
1f91b4cc | 1689 | static struct dwc2_hsotg_req *get_ep_head(struct dwc2_hsotg_ep *hs_ep) |
9c39ddc6 | 1690 | { |
ffc4b406 MY |
1691 | return list_first_entry_or_null(&hs_ep->queue, struct dwc2_hsotg_req, |
1692 | queue); | |
9c39ddc6 AT |
1693 | } |
1694 | ||
41cc4cd2 VM |
1695 | /** |
1696 | * dwc2_gadget_start_next_request - Starts next request from ep queue | |
1697 | * @hs_ep: Endpoint structure | |
1698 | * | |
1699 | * If queue is empty and EP is ISOC-OUT - unmasks OUTTKNEPDIS which is masked | |
1700 | * in its handler. Hence we need to unmask it here to be able to do | |
1701 | * resynchronization. | |
1702 | */ | |
1703 | static void dwc2_gadget_start_next_request(struct dwc2_hsotg_ep *hs_ep) | |
1704 | { | |
1705 | u32 mask; | |
1706 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
1707 | int dir_in = hs_ep->dir_in; | |
1708 | struct dwc2_hsotg_req *hs_req; | |
1709 | u32 epmsk_reg = dir_in ? DIEPMSK : DOEPMSK; | |
1710 | ||
1711 | if (!list_empty(&hs_ep->queue)) { | |
1712 | hs_req = get_ep_head(hs_ep); | |
1713 | dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, false); | |
1714 | return; | |
1715 | } | |
1716 | if (!hs_ep->isochronous) | |
1717 | return; | |
1718 | ||
1719 | if (dir_in) { | |
1720 | dev_dbg(hsotg->dev, "%s: No more ISOC-IN requests\n", | |
1721 | __func__); | |
1722 | } else { | |
1723 | dev_dbg(hsotg->dev, "%s: No more ISOC-OUT requests\n", | |
1724 | __func__); | |
f25c42b8 | 1725 | mask = dwc2_readl(hsotg, epmsk_reg); |
41cc4cd2 | 1726 | mask |= DOEPMSK_OUTTKNEPDISMSK; |
f25c42b8 | 1727 | dwc2_writel(hsotg, mask, epmsk_reg); |
41cc4cd2 VM |
1728 | } |
1729 | } | |
1730 | ||
5b7d70c6 | 1731 | /** |
1f91b4cc | 1732 | * dwc2_hsotg_process_req_feature - process request {SET,CLEAR}_FEATURE |
5b7d70c6 BD |
1733 | * @hsotg: The device state |
1734 | * @ctrl: USB control request | |
1735 | */ | |
1f91b4cc | 1736 | static int dwc2_hsotg_process_req_feature(struct dwc2_hsotg *hsotg, |
9da51974 | 1737 | struct usb_ctrlrequest *ctrl) |
5b7d70c6 | 1738 | { |
1f91b4cc FB |
1739 | struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0]; |
1740 | struct dwc2_hsotg_req *hs_req; | |
5b7d70c6 | 1741 | bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE); |
1f91b4cc | 1742 | struct dwc2_hsotg_ep *ep; |
26ab3d0c | 1743 | int ret; |
bd9ef7bf | 1744 | bool halted; |
9e14d0a5 GH |
1745 | u32 recip; |
1746 | u32 wValue; | |
1747 | u32 wIndex; | |
5b7d70c6 BD |
1748 | |
1749 | dev_dbg(hsotg->dev, "%s: %s_FEATURE\n", | |
1750 | __func__, set ? "SET" : "CLEAR"); | |
1751 | ||
9e14d0a5 GH |
1752 | wValue = le16_to_cpu(ctrl->wValue); |
1753 | wIndex = le16_to_cpu(ctrl->wIndex); | |
1754 | recip = ctrl->bRequestType & USB_RECIP_MASK; | |
1755 | ||
1756 | switch (recip) { | |
1757 | case USB_RECIP_DEVICE: | |
1758 | switch (wValue) { | |
fa389a6d VM |
1759 | case USB_DEVICE_REMOTE_WAKEUP: |
1760 | hsotg->remote_wakeup_allowed = 1; | |
1761 | break; | |
1762 | ||
9e14d0a5 GH |
1763 | case USB_DEVICE_TEST_MODE: |
1764 | if ((wIndex & 0xff) != 0) | |
1765 | return -EINVAL; | |
1766 | if (!set) | |
1767 | return -EINVAL; | |
1768 | ||
1769 | hsotg->test_mode = wIndex >> 8; | |
1f91b4cc | 1770 | ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0); |
9e14d0a5 GH |
1771 | if (ret) { |
1772 | dev_err(hsotg->dev, | |
1773 | "%s: failed to send reply\n", __func__); | |
1774 | return ret; | |
1775 | } | |
1776 | break; | |
1777 | default: | |
1778 | return -ENOENT; | |
1779 | } | |
1780 | break; | |
1781 | ||
1782 | case USB_RECIP_ENDPOINT: | |
1783 | ep = ep_from_windex(hsotg, wIndex); | |
5b7d70c6 BD |
1784 | if (!ep) { |
1785 | dev_dbg(hsotg->dev, "%s: no endpoint for 0x%04x\n", | |
9e14d0a5 | 1786 | __func__, wIndex); |
5b7d70c6 BD |
1787 | return -ENOENT; |
1788 | } | |
1789 | ||
9e14d0a5 | 1790 | switch (wValue) { |
5b7d70c6 | 1791 | case USB_ENDPOINT_HALT: |
bd9ef7bf RB |
1792 | halted = ep->halted; |
1793 | ||
51da43b5 | 1794 | dwc2_hsotg_ep_sethalt(&ep->ep, set, true); |
26ab3d0c | 1795 | |
1f91b4cc | 1796 | ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0); |
26ab3d0c AT |
1797 | if (ret) { |
1798 | dev_err(hsotg->dev, | |
1799 | "%s: failed to send reply\n", __func__); | |
1800 | return ret; | |
1801 | } | |
9c39ddc6 | 1802 | |
bd9ef7bf RB |
1803 | /* |
1804 | * we have to complete all requests for ep if it was | |
1805 | * halted, and the halt was cleared by CLEAR_FEATURE | |
1806 | */ | |
1807 | ||
1808 | if (!set && halted) { | |
9c39ddc6 AT |
1809 | /* |
1810 | * If we have request in progress, | |
1811 | * then complete it | |
1812 | */ | |
1813 | if (ep->req) { | |
1814 | hs_req = ep->req; | |
1815 | ep->req = NULL; | |
1816 | list_del_init(&hs_req->queue); | |
c00dd4a6 GH |
1817 | if (hs_req->req.complete) { |
1818 | spin_unlock(&hsotg->lock); | |
1819 | usb_gadget_giveback_request( | |
1820 | &ep->ep, &hs_req->req); | |
1821 | spin_lock(&hsotg->lock); | |
1822 | } | |
9c39ddc6 AT |
1823 | } |
1824 | ||
1825 | /* If we have pending request, then start it */ | |
34c0887f | 1826 | if (!ep->req) |
41cc4cd2 | 1827 | dwc2_gadget_start_next_request(ep); |
9c39ddc6 AT |
1828 | } |
1829 | ||
5b7d70c6 BD |
1830 | break; |
1831 | ||
1832 | default: | |
1833 | return -ENOENT; | |
1834 | } | |
9e14d0a5 GH |
1835 | break; |
1836 | default: | |
1837 | return -ENOENT; | |
1838 | } | |
5b7d70c6 BD |
1839 | return 1; |
1840 | } | |
1841 | ||
1f91b4cc | 1842 | static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg); |
ab93e014 | 1843 | |
c9f721b2 | 1844 | /** |
1f91b4cc | 1845 | * dwc2_hsotg_stall_ep0 - stall ep0 |
c9f721b2 RB |
1846 | * @hsotg: The device state |
1847 | * | |
1848 | * Set stall for ep0 as response for setup request. | |
1849 | */ | |
1f91b4cc | 1850 | static void dwc2_hsotg_stall_ep0(struct dwc2_hsotg *hsotg) |
e9ebe7c3 | 1851 | { |
1f91b4cc | 1852 | struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0]; |
c9f721b2 RB |
1853 | u32 reg; |
1854 | u32 ctrl; | |
1855 | ||
1856 | dev_dbg(hsotg->dev, "ep0 stall (dir=%d)\n", ep0->dir_in); | |
1857 | reg = (ep0->dir_in) ? DIEPCTL0 : DOEPCTL0; | |
1858 | ||
1859 | /* | |
1860 | * DxEPCTL_Stall will be cleared by EP once it has | |
1861 | * taken effect, so no need to clear later. | |
1862 | */ | |
1863 | ||
f25c42b8 | 1864 | ctrl = dwc2_readl(hsotg, reg); |
47a1685f DN |
1865 | ctrl |= DXEPCTL_STALL; |
1866 | ctrl |= DXEPCTL_CNAK; | |
f25c42b8 | 1867 | dwc2_writel(hsotg, ctrl, reg); |
c9f721b2 RB |
1868 | |
1869 | dev_dbg(hsotg->dev, | |
47a1685f | 1870 | "written DXEPCTL=0x%08x to %08x (DXEPCTL=0x%08x)\n", |
f25c42b8 | 1871 | ctrl, reg, dwc2_readl(hsotg, reg)); |
c9f721b2 RB |
1872 | |
1873 | /* | |
1874 | * complete won't be called, so we enqueue | |
1875 | * setup request here | |
1876 | */ | |
1f91b4cc | 1877 | dwc2_hsotg_enqueue_setup(hsotg); |
c9f721b2 RB |
1878 | } |
1879 | ||
5b7d70c6 | 1880 | /** |
1f91b4cc | 1881 | * dwc2_hsotg_process_control - process a control request |
5b7d70c6 BD |
1882 | * @hsotg: The device state |
1883 | * @ctrl: The control request received | |
1884 | * | |
1885 | * The controller has received the SETUP phase of a control request, and | |
1886 | * needs to work out what to do next (and whether to pass it on to the | |
1887 | * gadget driver). | |
1888 | */ | |
1f91b4cc | 1889 | static void dwc2_hsotg_process_control(struct dwc2_hsotg *hsotg, |
9da51974 | 1890 | struct usb_ctrlrequest *ctrl) |
5b7d70c6 | 1891 | { |
1f91b4cc | 1892 | struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0]; |
5b7d70c6 BD |
1893 | int ret = 0; |
1894 | u32 dcfg; | |
1895 | ||
e525e743 MYK |
1896 | dev_dbg(hsotg->dev, |
1897 | "ctrl Type=%02x, Req=%02x, V=%04x, I=%04x, L=%04x\n", | |
1898 | ctrl->bRequestType, ctrl->bRequest, ctrl->wValue, | |
1899 | ctrl->wIndex, ctrl->wLength); | |
5b7d70c6 | 1900 | |
fe0b94ab MYK |
1901 | if (ctrl->wLength == 0) { |
1902 | ep0->dir_in = 1; | |
1903 | hsotg->ep0_state = DWC2_EP0_STATUS_IN; | |
1904 | } else if (ctrl->bRequestType & USB_DIR_IN) { | |
5b7d70c6 | 1905 | ep0->dir_in = 1; |
fe0b94ab MYK |
1906 | hsotg->ep0_state = DWC2_EP0_DATA_IN; |
1907 | } else { | |
1908 | ep0->dir_in = 0; | |
1909 | hsotg->ep0_state = DWC2_EP0_DATA_OUT; | |
1910 | } | |
5b7d70c6 BD |
1911 | |
1912 | if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) { | |
1913 | switch (ctrl->bRequest) { | |
1914 | case USB_REQ_SET_ADDRESS: | |
6d713c15 | 1915 | hsotg->connected = 1; |
f25c42b8 | 1916 | dcfg = dwc2_readl(hsotg, DCFG); |
47a1685f | 1917 | dcfg &= ~DCFG_DEVADDR_MASK; |
d5dbd3f7 PZ |
1918 | dcfg |= (le16_to_cpu(ctrl->wValue) << |
1919 | DCFG_DEVADDR_SHIFT) & DCFG_DEVADDR_MASK; | |
f25c42b8 | 1920 | dwc2_writel(hsotg, dcfg, DCFG); |
5b7d70c6 BD |
1921 | |
1922 | dev_info(hsotg->dev, "new address %d\n", ctrl->wValue); | |
1923 | ||
1f91b4cc | 1924 | ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0); |
5b7d70c6 BD |
1925 | return; |
1926 | ||
1927 | case USB_REQ_GET_STATUS: | |
1f91b4cc | 1928 | ret = dwc2_hsotg_process_req_status(hsotg, ctrl); |
5b7d70c6 BD |
1929 | break; |
1930 | ||
1931 | case USB_REQ_CLEAR_FEATURE: | |
1932 | case USB_REQ_SET_FEATURE: | |
1f91b4cc | 1933 | ret = dwc2_hsotg_process_req_feature(hsotg, ctrl); |
5b7d70c6 BD |
1934 | break; |
1935 | } | |
1936 | } | |
1937 | ||
1938 | /* as a fallback, try delivering it to the driver to deal with */ | |
1939 | ||
1940 | if (ret == 0 && hsotg->driver) { | |
93f599f2 | 1941 | spin_unlock(&hsotg->lock); |
5b7d70c6 | 1942 | ret = hsotg->driver->setup(&hsotg->gadget, ctrl); |
93f599f2 | 1943 | spin_lock(&hsotg->lock); |
5b7d70c6 BD |
1944 | if (ret < 0) |
1945 | dev_dbg(hsotg->dev, "driver->setup() ret %d\n", ret); | |
1946 | } | |
1947 | ||
b4c53b4a MH |
1948 | hsotg->delayed_status = false; |
1949 | if (ret == USB_GADGET_DELAYED_STATUS) | |
1950 | hsotg->delayed_status = true; | |
1951 | ||
8b9bc460 LM |
1952 | /* |
1953 | * the request is either unhandlable, or is not formatted correctly | |
5b7d70c6 BD |
1954 | * so respond with a STALL for the status stage to indicate failure. |
1955 | */ | |
1956 | ||
c9f721b2 | 1957 | if (ret < 0) |
1f91b4cc | 1958 | dwc2_hsotg_stall_ep0(hsotg); |
5b7d70c6 BD |
1959 | } |
1960 | ||
5b7d70c6 | 1961 | /** |
1f91b4cc | 1962 | * dwc2_hsotg_complete_setup - completion of a setup transfer |
5b7d70c6 BD |
1963 | * @ep: The endpoint the request was on. |
1964 | * @req: The request completed. | |
1965 | * | |
1966 | * Called on completion of any requests the driver itself submitted for | |
1967 | * EP0 setup packets | |
1968 | */ | |
1f91b4cc | 1969 | static void dwc2_hsotg_complete_setup(struct usb_ep *ep, |
9da51974 | 1970 | struct usb_request *req) |
5b7d70c6 | 1971 | { |
1f91b4cc | 1972 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 1973 | struct dwc2_hsotg *hsotg = hs_ep->parent; |
5b7d70c6 BD |
1974 | |
1975 | if (req->status < 0) { | |
1976 | dev_dbg(hsotg->dev, "%s: failed %d\n", __func__, req->status); | |
1977 | return; | |
1978 | } | |
1979 | ||
93f599f2 | 1980 | spin_lock(&hsotg->lock); |
5b7d70c6 | 1981 | if (req->actual == 0) |
1f91b4cc | 1982 | dwc2_hsotg_enqueue_setup(hsotg); |
5b7d70c6 | 1983 | else |
1f91b4cc | 1984 | dwc2_hsotg_process_control(hsotg, req->buf); |
93f599f2 | 1985 | spin_unlock(&hsotg->lock); |
5b7d70c6 BD |
1986 | } |
1987 | ||
1988 | /** | |
1f91b4cc | 1989 | * dwc2_hsotg_enqueue_setup - start a request for EP0 packets |
5b7d70c6 BD |
1990 | * @hsotg: The device state. |
1991 | * | |
1992 | * Enqueue a request on EP0 if necessary to received any SETUP packets | |
1993 | * received from the host. | |
1994 | */ | |
1f91b4cc | 1995 | static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg) |
5b7d70c6 BD |
1996 | { |
1997 | struct usb_request *req = hsotg->ctrl_req; | |
1f91b4cc | 1998 | struct dwc2_hsotg_req *hs_req = our_req(req); |
5b7d70c6 BD |
1999 | int ret; |
2000 | ||
2001 | dev_dbg(hsotg->dev, "%s: queueing setup request\n", __func__); | |
2002 | ||
2003 | req->zero = 0; | |
2004 | req->length = 8; | |
2005 | req->buf = hsotg->ctrl_buff; | |
1f91b4cc | 2006 | req->complete = dwc2_hsotg_complete_setup; |
5b7d70c6 BD |
2007 | |
2008 | if (!list_empty(&hs_req->queue)) { | |
2009 | dev_dbg(hsotg->dev, "%s already queued???\n", __func__); | |
2010 | return; | |
2011 | } | |
2012 | ||
c6f5c050 | 2013 | hsotg->eps_out[0]->dir_in = 0; |
8a20fa45 | 2014 | hsotg->eps_out[0]->send_zlp = 0; |
fe0b94ab | 2015 | hsotg->ep0_state = DWC2_EP0_SETUP; |
5b7d70c6 | 2016 | |
1f91b4cc | 2017 | ret = dwc2_hsotg_ep_queue(&hsotg->eps_out[0]->ep, req, GFP_ATOMIC); |
5b7d70c6 BD |
2018 | if (ret < 0) { |
2019 | dev_err(hsotg->dev, "%s: failed queue (%d)\n", __func__, ret); | |
8b9bc460 LM |
2020 | /* |
2021 | * Don't think there's much we can do other than watch the | |
2022 | * driver fail. | |
2023 | */ | |
5b7d70c6 BD |
2024 | } |
2025 | } | |
2026 | ||
1f91b4cc | 2027 | static void dwc2_hsotg_program_zlp(struct dwc2_hsotg *hsotg, |
9da51974 | 2028 | struct dwc2_hsotg_ep *hs_ep) |
fe0b94ab MYK |
2029 | { |
2030 | u32 ctrl; | |
2031 | u8 index = hs_ep->index; | |
2032 | u32 epctl_reg = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index); | |
2033 | u32 epsiz_reg = hs_ep->dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index); | |
2034 | ||
ccb34a91 MYK |
2035 | if (hs_ep->dir_in) |
2036 | dev_dbg(hsotg->dev, "Sending zero-length packet on ep%d\n", | |
e02f9aa6 | 2037 | index); |
ccb34a91 MYK |
2038 | else |
2039 | dev_dbg(hsotg->dev, "Receiving zero-length packet on ep%d\n", | |
e02f9aa6 VA |
2040 | index); |
2041 | if (using_desc_dma(hsotg)) { | |
201ec568 MH |
2042 | if (!index) |
2043 | dwc2_gadget_set_ep0_desc_chain(hsotg, hs_ep); | |
2044 | ||
10209abe AP |
2045 | /* Not specific buffer needed for ep0 ZLP */ |
2046 | dwc2_gadget_fill_nonisoc_xfer_ddma_one(hs_ep, &hs_ep->desc_list, | |
2047 | hs_ep->desc_list_dma, 0, true); | |
e02f9aa6 | 2048 | } else { |
f25c42b8 GS |
2049 | dwc2_writel(hsotg, DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) | |
2050 | DXEPTSIZ_XFERSIZE(0), | |
e02f9aa6 VA |
2051 | epsiz_reg); |
2052 | } | |
fe0b94ab | 2053 | |
f25c42b8 | 2054 | ctrl = dwc2_readl(hsotg, epctl_reg); |
fe0b94ab MYK |
2055 | ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */ |
2056 | ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */ | |
2057 | ctrl |= DXEPCTL_USBACTEP; | |
f25c42b8 | 2058 | dwc2_writel(hsotg, ctrl, epctl_reg); |
fe0b94ab MYK |
2059 | } |
2060 | ||
5b7d70c6 | 2061 | /** |
1f91b4cc | 2062 | * dwc2_hsotg_complete_request - complete a request given to us |
5b7d70c6 BD |
2063 | * @hsotg: The device state. |
2064 | * @hs_ep: The endpoint the request was on. | |
2065 | * @hs_req: The request to complete. | |
2066 | * @result: The result code (0 => Ok, otherwise errno) | |
2067 | * | |
2068 | * The given request has finished, so call the necessary completion | |
2069 | * if it has one and then look to see if we can start a new request | |
2070 | * on the endpoint. | |
2071 | * | |
2072 | * Note, expects the ep to already be locked as appropriate. | |
8b9bc460 | 2073 | */ |
1f91b4cc | 2074 | static void dwc2_hsotg_complete_request(struct dwc2_hsotg *hsotg, |
9da51974 | 2075 | struct dwc2_hsotg_ep *hs_ep, |
1f91b4cc | 2076 | struct dwc2_hsotg_req *hs_req, |
5b7d70c6 BD |
2077 | int result) |
2078 | { | |
5b7d70c6 BD |
2079 | if (!hs_req) { |
2080 | dev_dbg(hsotg->dev, "%s: nothing to complete?\n", __func__); | |
2081 | return; | |
2082 | } | |
2083 | ||
2084 | dev_dbg(hsotg->dev, "complete: ep %p %s, req %p, %d => %p\n", | |
2085 | hs_ep, hs_ep->ep.name, hs_req, result, hs_req->req.complete); | |
2086 | ||
8b9bc460 LM |
2087 | /* |
2088 | * only replace the status if we've not already set an error | |
2089 | * from a previous transaction | |
2090 | */ | |
5b7d70c6 BD |
2091 | |
2092 | if (hs_req->req.status == -EINPROGRESS) | |
2093 | hs_req->req.status = result; | |
2094 | ||
44583fec YL |
2095 | if (using_dma(hsotg)) |
2096 | dwc2_hsotg_unmap_dma(hsotg, hs_ep, hs_req); | |
2097 | ||
1f91b4cc | 2098 | dwc2_hsotg_handle_unaligned_buf_complete(hsotg, hs_ep, hs_req); |
7d24c1b5 | 2099 | |
5b7d70c6 BD |
2100 | hs_ep->req = NULL; |
2101 | list_del_init(&hs_req->queue); | |
2102 | ||
8b9bc460 LM |
2103 | /* |
2104 | * call the complete request with the locks off, just in case the | |
2105 | * request tries to queue more work for this endpoint. | |
2106 | */ | |
5b7d70c6 BD |
2107 | |
2108 | if (hs_req->req.complete) { | |
22258f49 | 2109 | spin_unlock(&hsotg->lock); |
304f7e5e | 2110 | usb_gadget_giveback_request(&hs_ep->ep, &hs_req->req); |
22258f49 | 2111 | spin_lock(&hsotg->lock); |
5b7d70c6 BD |
2112 | } |
2113 | ||
540ccba0 VA |
2114 | /* In DDMA don't need to proceed to starting of next ISOC request */ |
2115 | if (using_desc_dma(hsotg) && hs_ep->isochronous) | |
2116 | return; | |
2117 | ||
8b9bc460 LM |
2118 | /* |
2119 | * Look to see if there is anything else to do. Note, the completion | |
5b7d70c6 | 2120 | * of the previous request may have caused a new request to be started |
8b9bc460 LM |
2121 | * so be careful when doing this. |
2122 | */ | |
5b7d70c6 | 2123 | |
34c0887f | 2124 | if (!hs_ep->req && result >= 0) |
41cc4cd2 | 2125 | dwc2_gadget_start_next_request(hs_ep); |
5b7d70c6 BD |
2126 | } |
2127 | ||
540ccba0 VA |
2128 | /* |
2129 | * dwc2_gadget_complete_isoc_request_ddma - complete an isoc request in DDMA | |
2130 | * @hs_ep: The endpoint the request was on. | |
2131 | * | |
2132 | * Get first request from the ep queue, determine descriptor on which complete | |
729cac69 MH |
2133 | * happened. SW discovers which descriptor currently in use by HW, adjusts |
2134 | * dma_address and calculates index of completed descriptor based on the value | |
2135 | * of DEPDMA register. Update actual length of request, giveback to gadget. | |
540ccba0 VA |
2136 | */ |
2137 | static void dwc2_gadget_complete_isoc_request_ddma(struct dwc2_hsotg_ep *hs_ep) | |
2138 | { | |
2139 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
2140 | struct dwc2_hsotg_req *hs_req; | |
2141 | struct usb_request *ureq; | |
540ccba0 VA |
2142 | u32 desc_sts; |
2143 | u32 mask; | |
2144 | ||
729cac69 | 2145 | desc_sts = hs_ep->desc_list[hs_ep->compl_desc].status; |
540ccba0 | 2146 | |
729cac69 MH |
2147 | /* Process only descriptors with buffer status set to DMA done */ |
2148 | while ((desc_sts & DEV_DMA_BUFF_STS_MASK) >> | |
2149 | DEV_DMA_BUFF_STS_SHIFT == DEV_DMA_BUFF_STS_DMADONE) { | |
540ccba0 | 2150 | |
729cac69 MH |
2151 | hs_req = get_ep_head(hs_ep); |
2152 | if (!hs_req) { | |
2153 | dev_warn(hsotg->dev, "%s: ISOC EP queue empty\n", __func__); | |
2154 | return; | |
2155 | } | |
2156 | ureq = &hs_req->req; | |
2157 | ||
2158 | /* Check completion status */ | |
2159 | if ((desc_sts & DEV_DMA_STS_MASK) >> DEV_DMA_STS_SHIFT == | |
2160 | DEV_DMA_STS_SUCC) { | |
2161 | mask = hs_ep->dir_in ? DEV_DMA_ISOC_TX_NBYTES_MASK : | |
2162 | DEV_DMA_ISOC_RX_NBYTES_MASK; | |
2163 | ureq->actual = ureq->length - ((desc_sts & mask) >> | |
2164 | DEV_DMA_ISOC_NBYTES_SHIFT); | |
2165 | ||
2166 | /* Adjust actual len for ISOC Out if len is | |
2167 | * not align of 4 | |
2168 | */ | |
2169 | if (!hs_ep->dir_in && ureq->length & 0x3) | |
2170 | ureq->actual += 4 - (ureq->length & 0x3); | |
2171 | } | |
540ccba0 | 2172 | |
729cac69 | 2173 | dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0); |
95d2b037 | 2174 | |
729cac69 MH |
2175 | hs_ep->compl_desc++; |
2176 | if (hs_ep->compl_desc > (MAX_DMA_DESC_NUM_GENERIC - 1)) | |
2177 | hs_ep->compl_desc = 0; | |
2178 | desc_sts = hs_ep->desc_list[hs_ep->compl_desc].status; | |
2179 | } | |
540ccba0 VA |
2180 | } |
2181 | ||
2182 | /* | |
729cac69 MH |
2183 | * dwc2_gadget_handle_isoc_bna - handle BNA interrupt for ISOC. |
2184 | * @hs_ep: The isochronous endpoint. | |
540ccba0 | 2185 | * |
729cac69 MH |
2186 | * If EP ISOC OUT then need to flush RX FIFO to remove source of BNA |
2187 | * interrupt. Reset target frame and next_desc to allow to start | |
2188 | * ISOC's on NAK interrupt for IN direction or on OUTTKNEPDIS | |
2189 | * interrupt for OUT direction. | |
540ccba0 | 2190 | */ |
729cac69 | 2191 | static void dwc2_gadget_handle_isoc_bna(struct dwc2_hsotg_ep *hs_ep) |
540ccba0 VA |
2192 | { |
2193 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
540ccba0 | 2194 | |
729cac69 MH |
2195 | if (!hs_ep->dir_in) |
2196 | dwc2_flush_rx_fifo(hsotg); | |
2197 | dwc2_hsotg_complete_request(hsotg, hs_ep, get_ep_head(hs_ep), 0); | |
540ccba0 | 2198 | |
729cac69 MH |
2199 | hs_ep->target_frame = TARGET_FRAME_INITIAL; |
2200 | hs_ep->next_desc = 0; | |
2201 | hs_ep->compl_desc = 0; | |
540ccba0 VA |
2202 | } |
2203 | ||
5b7d70c6 | 2204 | /** |
1f91b4cc | 2205 | * dwc2_hsotg_rx_data - receive data from the FIFO for an endpoint |
5b7d70c6 BD |
2206 | * @hsotg: The device state. |
2207 | * @ep_idx: The endpoint index for the data | |
2208 | * @size: The size of data in the fifo, in bytes | |
2209 | * | |
2210 | * The FIFO status shows there is data to read from the FIFO for a given | |
2211 | * endpoint, so sort out whether we need to read the data into a request | |
2212 | * that has been made for that endpoint. | |
2213 | */ | |
1f91b4cc | 2214 | static void dwc2_hsotg_rx_data(struct dwc2_hsotg *hsotg, int ep_idx, int size) |
5b7d70c6 | 2215 | { |
1f91b4cc FB |
2216 | struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[ep_idx]; |
2217 | struct dwc2_hsotg_req *hs_req = hs_ep->req; | |
5b7d70c6 BD |
2218 | int to_read; |
2219 | int max_req; | |
2220 | int read_ptr; | |
2221 | ||
2222 | if (!hs_req) { | |
f25c42b8 | 2223 | u32 epctl = dwc2_readl(hsotg, DOEPCTL(ep_idx)); |
5b7d70c6 BD |
2224 | int ptr; |
2225 | ||
6b448af4 | 2226 | dev_dbg(hsotg->dev, |
9da51974 | 2227 | "%s: FIFO %d bytes on ep%d but no req (DXEPCTl=0x%08x)\n", |
5b7d70c6 BD |
2228 | __func__, size, ep_idx, epctl); |
2229 | ||
2230 | /* dump the data from the FIFO, we've nothing we can do */ | |
2231 | for (ptr = 0; ptr < size; ptr += 4) | |
f25c42b8 | 2232 | (void)dwc2_readl(hsotg, EPFIFO(ep_idx)); |
5b7d70c6 BD |
2233 | |
2234 | return; | |
2235 | } | |
2236 | ||
5b7d70c6 BD |
2237 | to_read = size; |
2238 | read_ptr = hs_req->req.actual; | |
2239 | max_req = hs_req->req.length - read_ptr; | |
2240 | ||
a33e7136 BD |
2241 | dev_dbg(hsotg->dev, "%s: read %d/%d, done %d/%d\n", |
2242 | __func__, to_read, max_req, read_ptr, hs_req->req.length); | |
2243 | ||
5b7d70c6 | 2244 | if (to_read > max_req) { |
8b9bc460 LM |
2245 | /* |
2246 | * more data appeared than we where willing | |
5b7d70c6 BD |
2247 | * to deal with in this request. |
2248 | */ | |
2249 | ||
2250 | /* currently we don't deal this */ | |
2251 | WARN_ON_ONCE(1); | |
2252 | } | |
2253 | ||
5b7d70c6 BD |
2254 | hs_ep->total_data += to_read; |
2255 | hs_req->req.actual += to_read; | |
2256 | to_read = DIV_ROUND_UP(to_read, 4); | |
2257 | ||
8b9bc460 LM |
2258 | /* |
2259 | * note, we might over-write the buffer end by 3 bytes depending on | |
2260 | * alignment of the data. | |
2261 | */ | |
342ccce1 GS |
2262 | dwc2_readl_rep(hsotg, EPFIFO(ep_idx), |
2263 | hs_req->req.buf + read_ptr, to_read); | |
5b7d70c6 BD |
2264 | } |
2265 | ||
2266 | /** | |
1f91b4cc | 2267 | * dwc2_hsotg_ep0_zlp - send/receive zero-length packet on control endpoint |
5b7d70c6 | 2268 | * @hsotg: The device instance |
fe0b94ab | 2269 | * @dir_in: If IN zlp |
5b7d70c6 BD |
2270 | * |
2271 | * Generate a zero-length IN packet request for terminating a SETUP | |
2272 | * transaction. | |
2273 | * | |
2274 | * Note, since we don't write any data to the TxFIFO, then it is | |
25985edc | 2275 | * currently believed that we do not need to wait for any space in |
5b7d70c6 BD |
2276 | * the TxFIFO. |
2277 | */ | |
1f91b4cc | 2278 | static void dwc2_hsotg_ep0_zlp(struct dwc2_hsotg *hsotg, bool dir_in) |
5b7d70c6 | 2279 | { |
c6f5c050 | 2280 | /* eps_out[0] is used in both directions */ |
fe0b94ab MYK |
2281 | hsotg->eps_out[0]->dir_in = dir_in; |
2282 | hsotg->ep0_state = dir_in ? DWC2_EP0_STATUS_IN : DWC2_EP0_STATUS_OUT; | |
5b7d70c6 | 2283 | |
1f91b4cc | 2284 | dwc2_hsotg_program_zlp(hsotg, hsotg->eps_out[0]); |
5b7d70c6 BD |
2285 | } |
2286 | ||
ec1f9d9f | 2287 | static void dwc2_hsotg_change_ep_iso_parity(struct dwc2_hsotg *hsotg, |
9da51974 | 2288 | u32 epctl_reg) |
ec1f9d9f RB |
2289 | { |
2290 | u32 ctrl; | |
2291 | ||
f25c42b8 | 2292 | ctrl = dwc2_readl(hsotg, epctl_reg); |
ec1f9d9f RB |
2293 | if (ctrl & DXEPCTL_EOFRNUM) |
2294 | ctrl |= DXEPCTL_SETEVENFR; | |
2295 | else | |
2296 | ctrl |= DXEPCTL_SETODDFR; | |
f25c42b8 | 2297 | dwc2_writel(hsotg, ctrl, epctl_reg); |
ec1f9d9f RB |
2298 | } |
2299 | ||
aa3e8bc8 VA |
2300 | /* |
2301 | * dwc2_gadget_get_xfersize_ddma - get transferred bytes amount from desc | |
2302 | * @hs_ep - The endpoint on which transfer went | |
2303 | * | |
2304 | * Iterate over endpoints descriptor chain and get info on bytes remained | |
2305 | * in DMA descriptors after transfer has completed. Used for non isoc EPs. | |
2306 | */ | |
2307 | static unsigned int dwc2_gadget_get_xfersize_ddma(struct dwc2_hsotg_ep *hs_ep) | |
2308 | { | |
2309 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
2310 | unsigned int bytes_rem = 0; | |
2311 | struct dwc2_dma_desc *desc = hs_ep->desc_list; | |
2312 | int i; | |
2313 | u32 status; | |
2314 | ||
2315 | if (!desc) | |
2316 | return -EINVAL; | |
2317 | ||
2318 | for (i = 0; i < hs_ep->desc_count; ++i) { | |
2319 | status = desc->status; | |
2320 | bytes_rem += status & DEV_DMA_NBYTES_MASK; | |
2321 | ||
2322 | if (status & DEV_DMA_STS_MASK) | |
2323 | dev_err(hsotg->dev, "descriptor %d closed with %x\n", | |
2324 | i, status & DEV_DMA_STS_MASK); | |
2325 | } | |
2326 | ||
2327 | return bytes_rem; | |
2328 | } | |
2329 | ||
5b7d70c6 | 2330 | /** |
1f91b4cc | 2331 | * dwc2_hsotg_handle_outdone - handle receiving OutDone/SetupDone from RXFIFO |
5b7d70c6 BD |
2332 | * @hsotg: The device instance |
2333 | * @epnum: The endpoint received from | |
5b7d70c6 BD |
2334 | * |
2335 | * The RXFIFO has delivered an OutDone event, which means that the data | |
2336 | * transfer for an OUT endpoint has been completed, either by a short | |
2337 | * packet or by the finish of a transfer. | |
8b9bc460 | 2338 | */ |
1f91b4cc | 2339 | static void dwc2_hsotg_handle_outdone(struct dwc2_hsotg *hsotg, int epnum) |
5b7d70c6 | 2340 | { |
f25c42b8 | 2341 | u32 epsize = dwc2_readl(hsotg, DOEPTSIZ(epnum)); |
1f91b4cc FB |
2342 | struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[epnum]; |
2343 | struct dwc2_hsotg_req *hs_req = hs_ep->req; | |
5b7d70c6 | 2344 | struct usb_request *req = &hs_req->req; |
9da51974 | 2345 | unsigned int size_left = DXEPTSIZ_XFERSIZE_GET(epsize); |
5b7d70c6 BD |
2346 | int result = 0; |
2347 | ||
2348 | if (!hs_req) { | |
2349 | dev_dbg(hsotg->dev, "%s: no request active\n", __func__); | |
2350 | return; | |
2351 | } | |
2352 | ||
fe0b94ab MYK |
2353 | if (epnum == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_OUT) { |
2354 | dev_dbg(hsotg->dev, "zlp packet received\n"); | |
1f91b4cc FB |
2355 | dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0); |
2356 | dwc2_hsotg_enqueue_setup(hsotg); | |
fe0b94ab MYK |
2357 | return; |
2358 | } | |
2359 | ||
aa3e8bc8 VA |
2360 | if (using_desc_dma(hsotg)) |
2361 | size_left = dwc2_gadget_get_xfersize_ddma(hs_ep); | |
2362 | ||
5b7d70c6 | 2363 | if (using_dma(hsotg)) { |
9da51974 | 2364 | unsigned int size_done; |
5b7d70c6 | 2365 | |
8b9bc460 LM |
2366 | /* |
2367 | * Calculate the size of the transfer by checking how much | |
5b7d70c6 BD |
2368 | * is left in the endpoint size register and then working it |
2369 | * out from the amount we loaded for the transfer. | |
2370 | * | |
2371 | * We need to do this as DMA pointers are always 32bit aligned | |
2372 | * so may overshoot/undershoot the transfer. | |
2373 | */ | |
2374 | ||
5b7d70c6 BD |
2375 | size_done = hs_ep->size_loaded - size_left; |
2376 | size_done += hs_ep->last_load; | |
2377 | ||
2378 | req->actual = size_done; | |
2379 | } | |
2380 | ||
a33e7136 BD |
2381 | /* if there is more request to do, schedule new transfer */ |
2382 | if (req->actual < req->length && size_left == 0) { | |
1f91b4cc | 2383 | dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true); |
a33e7136 BD |
2384 | return; |
2385 | } | |
2386 | ||
5b7d70c6 BD |
2387 | if (req->actual < req->length && req->short_not_ok) { |
2388 | dev_dbg(hsotg->dev, "%s: got %d/%d (short not ok) => error\n", | |
2389 | __func__, req->actual, req->length); | |
2390 | ||
8b9bc460 LM |
2391 | /* |
2392 | * todo - what should we return here? there's no one else | |
2393 | * even bothering to check the status. | |
2394 | */ | |
5b7d70c6 BD |
2395 | } |
2396 | ||
ef750c71 VA |
2397 | /* DDMA IN status phase will start from StsPhseRcvd interrupt */ |
2398 | if (!using_desc_dma(hsotg) && epnum == 0 && | |
2399 | hsotg->ep0_state == DWC2_EP0_DATA_OUT) { | |
fe0b94ab | 2400 | /* Move to STATUS IN */ |
b4c53b4a MH |
2401 | if (!hsotg->delayed_status) |
2402 | dwc2_hsotg_ep0_zlp(hsotg, true); | |
5b7d70c6 BD |
2403 | } |
2404 | ||
ec1f9d9f RB |
2405 | /* |
2406 | * Slave mode OUT transfers do not go through XferComplete so | |
2407 | * adjust the ISOC parity here. | |
2408 | */ | |
2409 | if (!using_dma(hsotg)) { | |
ec1f9d9f RB |
2410 | if (hs_ep->isochronous && hs_ep->interval == 1) |
2411 | dwc2_hsotg_change_ep_iso_parity(hsotg, DOEPCTL(epnum)); | |
837e9f00 VM |
2412 | else if (hs_ep->isochronous && hs_ep->interval > 1) |
2413 | dwc2_gadget_incr_frame_num(hs_ep); | |
ec1f9d9f RB |
2414 | } |
2415 | ||
1f91b4cc | 2416 | dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, result); |
5b7d70c6 BD |
2417 | } |
2418 | ||
5b7d70c6 | 2419 | /** |
1f91b4cc | 2420 | * dwc2_hsotg_handle_rx - RX FIFO has data |
5b7d70c6 BD |
2421 | * @hsotg: The device instance |
2422 | * | |
2423 | * The IRQ handler has detected that the RX FIFO has some data in it | |
2424 | * that requires processing, so find out what is in there and do the | |
2425 | * appropriate read. | |
2426 | * | |
25985edc | 2427 | * The RXFIFO is a true FIFO, the packets coming out are still in packet |
5b7d70c6 BD |
2428 | * chunks, so if you have x packets received on an endpoint you'll get x |
2429 | * FIFO events delivered, each with a packet's worth of data in it. | |
2430 | * | |
2431 | * When using DMA, we should not be processing events from the RXFIFO | |
2432 | * as the actual data should be sent to the memory directly and we turn | |
2433 | * on the completion interrupts to get notifications of transfer completion. | |
2434 | */ | |
1f91b4cc | 2435 | static void dwc2_hsotg_handle_rx(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 2436 | { |
f25c42b8 | 2437 | u32 grxstsr = dwc2_readl(hsotg, GRXSTSP); |
5b7d70c6 BD |
2438 | u32 epnum, status, size; |
2439 | ||
2440 | WARN_ON(using_dma(hsotg)); | |
2441 | ||
47a1685f DN |
2442 | epnum = grxstsr & GRXSTS_EPNUM_MASK; |
2443 | status = grxstsr & GRXSTS_PKTSTS_MASK; | |
5b7d70c6 | 2444 | |
47a1685f DN |
2445 | size = grxstsr & GRXSTS_BYTECNT_MASK; |
2446 | size >>= GRXSTS_BYTECNT_SHIFT; | |
5b7d70c6 | 2447 | |
d7c747c5 | 2448 | dev_dbg(hsotg->dev, "%s: GRXSTSP=0x%08x (%d@%d)\n", |
9da51974 | 2449 | __func__, grxstsr, size, epnum); |
5b7d70c6 | 2450 | |
47a1685f DN |
2451 | switch ((status & GRXSTS_PKTSTS_MASK) >> GRXSTS_PKTSTS_SHIFT) { |
2452 | case GRXSTS_PKTSTS_GLOBALOUTNAK: | |
2453 | dev_dbg(hsotg->dev, "GLOBALOUTNAK\n"); | |
5b7d70c6 BD |
2454 | break; |
2455 | ||
47a1685f | 2456 | case GRXSTS_PKTSTS_OUTDONE: |
5b7d70c6 | 2457 | dev_dbg(hsotg->dev, "OutDone (Frame=0x%08x)\n", |
1f91b4cc | 2458 | dwc2_hsotg_read_frameno(hsotg)); |
5b7d70c6 BD |
2459 | |
2460 | if (!using_dma(hsotg)) | |
1f91b4cc | 2461 | dwc2_hsotg_handle_outdone(hsotg, epnum); |
5b7d70c6 BD |
2462 | break; |
2463 | ||
47a1685f | 2464 | case GRXSTS_PKTSTS_SETUPDONE: |
5b7d70c6 BD |
2465 | dev_dbg(hsotg->dev, |
2466 | "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n", | |
1f91b4cc | 2467 | dwc2_hsotg_read_frameno(hsotg), |
f25c42b8 | 2468 | dwc2_readl(hsotg, DOEPCTL(0))); |
fe0b94ab | 2469 | /* |
1f91b4cc | 2470 | * Call dwc2_hsotg_handle_outdone here if it was not called from |
fe0b94ab MYK |
2471 | * GRXSTS_PKTSTS_OUTDONE. That is, if the core didn't |
2472 | * generate GRXSTS_PKTSTS_OUTDONE for setup packet. | |
2473 | */ | |
2474 | if (hsotg->ep0_state == DWC2_EP0_SETUP) | |
1f91b4cc | 2475 | dwc2_hsotg_handle_outdone(hsotg, epnum); |
5b7d70c6 BD |
2476 | break; |
2477 | ||
47a1685f | 2478 | case GRXSTS_PKTSTS_OUTRX: |
1f91b4cc | 2479 | dwc2_hsotg_rx_data(hsotg, epnum, size); |
5b7d70c6 BD |
2480 | break; |
2481 | ||
47a1685f | 2482 | case GRXSTS_PKTSTS_SETUPRX: |
5b7d70c6 BD |
2483 | dev_dbg(hsotg->dev, |
2484 | "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n", | |
1f91b4cc | 2485 | dwc2_hsotg_read_frameno(hsotg), |
f25c42b8 | 2486 | dwc2_readl(hsotg, DOEPCTL(0))); |
5b7d70c6 | 2487 | |
fe0b94ab MYK |
2488 | WARN_ON(hsotg->ep0_state != DWC2_EP0_SETUP); |
2489 | ||
1f91b4cc | 2490 | dwc2_hsotg_rx_data(hsotg, epnum, size); |
5b7d70c6 BD |
2491 | break; |
2492 | ||
2493 | default: | |
2494 | dev_warn(hsotg->dev, "%s: unknown status %08x\n", | |
2495 | __func__, grxstsr); | |
2496 | ||
1f91b4cc | 2497 | dwc2_hsotg_dump(hsotg); |
5b7d70c6 BD |
2498 | break; |
2499 | } | |
2500 | } | |
2501 | ||
2502 | /** | |
1f91b4cc | 2503 | * dwc2_hsotg_ep0_mps - turn max packet size into register setting |
5b7d70c6 | 2504 | * @mps: The maximum packet size in bytes. |
8b9bc460 | 2505 | */ |
1f91b4cc | 2506 | static u32 dwc2_hsotg_ep0_mps(unsigned int mps) |
5b7d70c6 BD |
2507 | { |
2508 | switch (mps) { | |
2509 | case 64: | |
94cb8fd6 | 2510 | return D0EPCTL_MPS_64; |
5b7d70c6 | 2511 | case 32: |
94cb8fd6 | 2512 | return D0EPCTL_MPS_32; |
5b7d70c6 | 2513 | case 16: |
94cb8fd6 | 2514 | return D0EPCTL_MPS_16; |
5b7d70c6 | 2515 | case 8: |
94cb8fd6 | 2516 | return D0EPCTL_MPS_8; |
5b7d70c6 BD |
2517 | } |
2518 | ||
2519 | /* bad max packet size, warn and return invalid result */ | |
2520 | WARN_ON(1); | |
2521 | return (u32)-1; | |
2522 | } | |
2523 | ||
2524 | /** | |
1f91b4cc | 2525 | * dwc2_hsotg_set_ep_maxpacket - set endpoint's max-packet field |
5b7d70c6 BD |
2526 | * @hsotg: The driver state. |
2527 | * @ep: The index number of the endpoint | |
2528 | * @mps: The maximum packet size in bytes | |
ee2c40de | 2529 | * @mc: The multicount value |
6fb914d7 | 2530 | * @dir_in: True if direction is in. |
5b7d70c6 BD |
2531 | * |
2532 | * Configure the maximum packet size for the given endpoint, updating | |
2533 | * the hardware control registers to reflect this. | |
2534 | */ | |
1f91b4cc | 2535 | static void dwc2_hsotg_set_ep_maxpacket(struct dwc2_hsotg *hsotg, |
ee2c40de VM |
2536 | unsigned int ep, unsigned int mps, |
2537 | unsigned int mc, unsigned int dir_in) | |
5b7d70c6 | 2538 | { |
1f91b4cc | 2539 | struct dwc2_hsotg_ep *hs_ep; |
5b7d70c6 BD |
2540 | u32 reg; |
2541 | ||
c6f5c050 MYK |
2542 | hs_ep = index_to_ep(hsotg, ep, dir_in); |
2543 | if (!hs_ep) | |
2544 | return; | |
2545 | ||
5b7d70c6 | 2546 | if (ep == 0) { |
ee2c40de VM |
2547 | u32 mps_bytes = mps; |
2548 | ||
5b7d70c6 | 2549 | /* EP0 is a special case */ |
ee2c40de VM |
2550 | mps = dwc2_hsotg_ep0_mps(mps_bytes); |
2551 | if (mps > 3) | |
5b7d70c6 | 2552 | goto bad_mps; |
ee2c40de | 2553 | hs_ep->ep.maxpacket = mps_bytes; |
4fca54aa | 2554 | hs_ep->mc = 1; |
5b7d70c6 | 2555 | } else { |
ee2c40de | 2556 | if (mps > 1024) |
5b7d70c6 | 2557 | goto bad_mps; |
ee2c40de VM |
2558 | hs_ep->mc = mc; |
2559 | if (mc > 3) | |
4fca54aa | 2560 | goto bad_mps; |
ee2c40de | 2561 | hs_ep->ep.maxpacket = mps; |
5b7d70c6 BD |
2562 | } |
2563 | ||
c6f5c050 | 2564 | if (dir_in) { |
f25c42b8 | 2565 | reg = dwc2_readl(hsotg, DIEPCTL(ep)); |
c6f5c050 | 2566 | reg &= ~DXEPCTL_MPS_MASK; |
ee2c40de | 2567 | reg |= mps; |
f25c42b8 | 2568 | dwc2_writel(hsotg, reg, DIEPCTL(ep)); |
c6f5c050 | 2569 | } else { |
f25c42b8 | 2570 | reg = dwc2_readl(hsotg, DOEPCTL(ep)); |
47a1685f | 2571 | reg &= ~DXEPCTL_MPS_MASK; |
ee2c40de | 2572 | reg |= mps; |
f25c42b8 | 2573 | dwc2_writel(hsotg, reg, DOEPCTL(ep)); |
659ad60c | 2574 | } |
5b7d70c6 BD |
2575 | |
2576 | return; | |
2577 | ||
2578 | bad_mps: | |
2579 | dev_err(hsotg->dev, "ep%d: bad mps of %d\n", ep, mps); | |
2580 | } | |
2581 | ||
9c39ddc6 | 2582 | /** |
1f91b4cc | 2583 | * dwc2_hsotg_txfifo_flush - flush Tx FIFO |
9c39ddc6 AT |
2584 | * @hsotg: The driver state |
2585 | * @idx: The index for the endpoint (0..15) | |
2586 | */ | |
1f91b4cc | 2587 | static void dwc2_hsotg_txfifo_flush(struct dwc2_hsotg *hsotg, unsigned int idx) |
9c39ddc6 | 2588 | { |
f25c42b8 GS |
2589 | dwc2_writel(hsotg, GRSTCTL_TXFNUM(idx) | GRSTCTL_TXFFLSH, |
2590 | GRSTCTL); | |
9c39ddc6 AT |
2591 | |
2592 | /* wait until the fifo is flushed */ | |
79d6b8c5 SA |
2593 | if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL, GRSTCTL_TXFFLSH, 100)) |
2594 | dev_warn(hsotg->dev, "%s: timeout flushing fifo GRSTCTL_TXFFLSH\n", | |
2595 | __func__); | |
9c39ddc6 | 2596 | } |
5b7d70c6 BD |
2597 | |
2598 | /** | |
1f91b4cc | 2599 | * dwc2_hsotg_trytx - check to see if anything needs transmitting |
5b7d70c6 BD |
2600 | * @hsotg: The driver state |
2601 | * @hs_ep: The driver endpoint to check. | |
2602 | * | |
2603 | * Check to see if there is a request that has data to send, and if so | |
2604 | * make an attempt to write data into the FIFO. | |
2605 | */ | |
1f91b4cc | 2606 | static int dwc2_hsotg_trytx(struct dwc2_hsotg *hsotg, |
9da51974 | 2607 | struct dwc2_hsotg_ep *hs_ep) |
5b7d70c6 | 2608 | { |
1f91b4cc | 2609 | struct dwc2_hsotg_req *hs_req = hs_ep->req; |
5b7d70c6 | 2610 | |
afcf4169 RB |
2611 | if (!hs_ep->dir_in || !hs_req) { |
2612 | /** | |
2613 | * if request is not enqueued, we disable interrupts | |
2614 | * for endpoints, excepting ep0 | |
2615 | */ | |
2616 | if (hs_ep->index != 0) | |
1f91b4cc | 2617 | dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, |
9da51974 | 2618 | hs_ep->dir_in, 0); |
5b7d70c6 | 2619 | return 0; |
afcf4169 | 2620 | } |
5b7d70c6 BD |
2621 | |
2622 | if (hs_req->req.actual < hs_req->req.length) { | |
2623 | dev_dbg(hsotg->dev, "trying to write more for ep%d\n", | |
2624 | hs_ep->index); | |
1f91b4cc | 2625 | return dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req); |
5b7d70c6 BD |
2626 | } |
2627 | ||
2628 | return 0; | |
2629 | } | |
2630 | ||
2631 | /** | |
1f91b4cc | 2632 | * dwc2_hsotg_complete_in - complete IN transfer |
5b7d70c6 BD |
2633 | * @hsotg: The device state. |
2634 | * @hs_ep: The endpoint that has just completed. | |
2635 | * | |
2636 | * An IN transfer has been completed, update the transfer's state and then | |
2637 | * call the relevant completion routines. | |
2638 | */ | |
1f91b4cc | 2639 | static void dwc2_hsotg_complete_in(struct dwc2_hsotg *hsotg, |
9da51974 | 2640 | struct dwc2_hsotg_ep *hs_ep) |
5b7d70c6 | 2641 | { |
1f91b4cc | 2642 | struct dwc2_hsotg_req *hs_req = hs_ep->req; |
f25c42b8 | 2643 | u32 epsize = dwc2_readl(hsotg, DIEPTSIZ(hs_ep->index)); |
5b7d70c6 BD |
2644 | int size_left, size_done; |
2645 | ||
2646 | if (!hs_req) { | |
2647 | dev_dbg(hsotg->dev, "XferCompl but no req\n"); | |
2648 | return; | |
2649 | } | |
2650 | ||
d3ca0259 | 2651 | /* Finish ZLP handling for IN EP0 transactions */ |
fe0b94ab MYK |
2652 | if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_IN) { |
2653 | dev_dbg(hsotg->dev, "zlp packet sent\n"); | |
c3b22fe2 RK |
2654 | |
2655 | /* | |
2656 | * While send zlp for DWC2_EP0_STATUS_IN EP direction was | |
2657 | * changed to IN. Change back to complete OUT transfer request | |
2658 | */ | |
2659 | hs_ep->dir_in = 0; | |
2660 | ||
1f91b4cc | 2661 | dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0); |
9e14d0a5 GH |
2662 | if (hsotg->test_mode) { |
2663 | int ret; | |
2664 | ||
1f91b4cc | 2665 | ret = dwc2_hsotg_set_test_mode(hsotg, hsotg->test_mode); |
9e14d0a5 GH |
2666 | if (ret < 0) { |
2667 | dev_dbg(hsotg->dev, "Invalid Test #%d\n", | |
9da51974 | 2668 | hsotg->test_mode); |
1f91b4cc | 2669 | dwc2_hsotg_stall_ep0(hsotg); |
9e14d0a5 GH |
2670 | return; |
2671 | } | |
2672 | } | |
1f91b4cc | 2673 | dwc2_hsotg_enqueue_setup(hsotg); |
d3ca0259 LM |
2674 | return; |
2675 | } | |
2676 | ||
8b9bc460 LM |
2677 | /* |
2678 | * Calculate the size of the transfer by checking how much is left | |
5b7d70c6 BD |
2679 | * in the endpoint size register and then working it out from |
2680 | * the amount we loaded for the transfer. | |
2681 | * | |
2682 | * We do this even for DMA, as the transfer may have incremented | |
2683 | * past the end of the buffer (DMA transfers are always 32bit | |
2684 | * aligned). | |
2685 | */ | |
aa3e8bc8 VA |
2686 | if (using_desc_dma(hsotg)) { |
2687 | size_left = dwc2_gadget_get_xfersize_ddma(hs_ep); | |
2688 | if (size_left < 0) | |
2689 | dev_err(hsotg->dev, "error parsing DDMA results %d\n", | |
2690 | size_left); | |
2691 | } else { | |
2692 | size_left = DXEPTSIZ_XFERSIZE_GET(epsize); | |
2693 | } | |
5b7d70c6 BD |
2694 | |
2695 | size_done = hs_ep->size_loaded - size_left; | |
2696 | size_done += hs_ep->last_load; | |
2697 | ||
2698 | if (hs_req->req.actual != size_done) | |
2699 | dev_dbg(hsotg->dev, "%s: adjusting size done %d => %d\n", | |
2700 | __func__, hs_req->req.actual, size_done); | |
2701 | ||
2702 | hs_req->req.actual = size_done; | |
d3ca0259 LM |
2703 | dev_dbg(hsotg->dev, "req->length:%d req->actual:%d req->zero:%d\n", |
2704 | hs_req->req.length, hs_req->req.actual, hs_req->req.zero); | |
2705 | ||
5b7d70c6 BD |
2706 | if (!size_left && hs_req->req.actual < hs_req->req.length) { |
2707 | dev_dbg(hsotg->dev, "%s trying more for req...\n", __func__); | |
1f91b4cc | 2708 | dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true); |
fe0b94ab MYK |
2709 | return; |
2710 | } | |
2711 | ||
f71b5e25 | 2712 | /* Zlp for all endpoints, for ep0 only in DATA IN stage */ |
8a20fa45 | 2713 | if (hs_ep->send_zlp) { |
1f91b4cc | 2714 | dwc2_hsotg_program_zlp(hsotg, hs_ep); |
8a20fa45 | 2715 | hs_ep->send_zlp = 0; |
f71b5e25 MYK |
2716 | /* transfer will be completed on next complete interrupt */ |
2717 | return; | |
2718 | } | |
2719 | ||
fe0b94ab MYK |
2720 | if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_DATA_IN) { |
2721 | /* Move to STATUS OUT */ | |
1f91b4cc | 2722 | dwc2_hsotg_ep0_zlp(hsotg, false); |
fe0b94ab MYK |
2723 | return; |
2724 | } | |
2725 | ||
1f91b4cc | 2726 | dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0); |
5b7d70c6 BD |
2727 | } |
2728 | ||
32601588 VM |
2729 | /** |
2730 | * dwc2_gadget_read_ep_interrupts - reads interrupts for given ep | |
2731 | * @hsotg: The device state. | |
2732 | * @idx: Index of ep. | |
2733 | * @dir_in: Endpoint direction 1-in 0-out. | |
2734 | * | |
2735 | * Reads for endpoint with given index and direction, by masking | |
2736 | * epint_reg with coresponding mask. | |
2737 | */ | |
2738 | static u32 dwc2_gadget_read_ep_interrupts(struct dwc2_hsotg *hsotg, | |
2739 | unsigned int idx, int dir_in) | |
2740 | { | |
2741 | u32 epmsk_reg = dir_in ? DIEPMSK : DOEPMSK; | |
2742 | u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx); | |
2743 | u32 ints; | |
2744 | u32 mask; | |
2745 | u32 diepempmsk; | |
2746 | ||
f25c42b8 GS |
2747 | mask = dwc2_readl(hsotg, epmsk_reg); |
2748 | diepempmsk = dwc2_readl(hsotg, DIEPEMPMSK); | |
32601588 VM |
2749 | mask |= ((diepempmsk >> idx) & 0x1) ? DIEPMSK_TXFIFOEMPTY : 0; |
2750 | mask |= DXEPINT_SETUP_RCVD; | |
2751 | ||
f25c42b8 | 2752 | ints = dwc2_readl(hsotg, epint_reg); |
32601588 VM |
2753 | ints &= mask; |
2754 | return ints; | |
2755 | } | |
2756 | ||
bd9971f0 VM |
2757 | /** |
2758 | * dwc2_gadget_handle_ep_disabled - handle DXEPINT_EPDISBLD | |
2759 | * @hs_ep: The endpoint on which interrupt is asserted. | |
2760 | * | |
2761 | * This interrupt indicates that the endpoint has been disabled per the | |
2762 | * application's request. | |
2763 | * | |
2764 | * For IN endpoints flushes txfifo, in case of BULK clears DCTL_CGNPINNAK, | |
2765 | * in case of ISOC completes current request. | |
2766 | * | |
2767 | * For ISOC-OUT endpoints completes expired requests. If there is remaining | |
2768 | * request starts it. | |
2769 | */ | |
2770 | static void dwc2_gadget_handle_ep_disabled(struct dwc2_hsotg_ep *hs_ep) | |
2771 | { | |
2772 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
2773 | struct dwc2_hsotg_req *hs_req; | |
2774 | unsigned char idx = hs_ep->index; | |
2775 | int dir_in = hs_ep->dir_in; | |
2776 | u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx); | |
f25c42b8 | 2777 | int dctl = dwc2_readl(hsotg, DCTL); |
bd9971f0 VM |
2778 | |
2779 | dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__); | |
2780 | ||
2781 | if (dir_in) { | |
f25c42b8 | 2782 | int epctl = dwc2_readl(hsotg, epctl_reg); |
bd9971f0 VM |
2783 | |
2784 | dwc2_hsotg_txfifo_flush(hsotg, hs_ep->fifo_index); | |
2785 | ||
2786 | if (hs_ep->isochronous) { | |
2787 | dwc2_hsotg_complete_in(hsotg, hs_ep); | |
2788 | return; | |
2789 | } | |
2790 | ||
2791 | if ((epctl & DXEPCTL_STALL) && (epctl & DXEPCTL_EPTYPE_BULK)) { | |
f25c42b8 | 2792 | int dctl = dwc2_readl(hsotg, DCTL); |
bd9971f0 VM |
2793 | |
2794 | dctl |= DCTL_CGNPINNAK; | |
f25c42b8 | 2795 | dwc2_writel(hsotg, dctl, DCTL); |
bd9971f0 VM |
2796 | } |
2797 | return; | |
2798 | } | |
2799 | ||
2800 | if (dctl & DCTL_GOUTNAKSTS) { | |
2801 | dctl |= DCTL_CGOUTNAK; | |
f25c42b8 | 2802 | dwc2_writel(hsotg, dctl, DCTL); |
bd9971f0 VM |
2803 | } |
2804 | ||
2805 | if (!hs_ep->isochronous) | |
2806 | return; | |
2807 | ||
2808 | if (list_empty(&hs_ep->queue)) { | |
2809 | dev_dbg(hsotg->dev, "%s: complete_ep 0x%p, ep->queue empty!\n", | |
2810 | __func__, hs_ep); | |
2811 | return; | |
2812 | } | |
2813 | ||
2814 | do { | |
2815 | hs_req = get_ep_head(hs_ep); | |
2816 | if (hs_req) | |
2817 | dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, | |
2818 | -ENODATA); | |
2819 | dwc2_gadget_incr_frame_num(hs_ep); | |
c7c24e7a AP |
2820 | /* Update current frame number value. */ |
2821 | hsotg->frame_number = dwc2_hsotg_read_frameno(hsotg); | |
bd9971f0 VM |
2822 | } while (dwc2_gadget_target_frame_elapsed(hs_ep)); |
2823 | ||
2824 | dwc2_gadget_start_next_request(hs_ep); | |
2825 | } | |
2826 | ||
5321922c VM |
2827 | /** |
2828 | * dwc2_gadget_handle_out_token_ep_disabled - handle DXEPINT_OUTTKNEPDIS | |
6fb914d7 | 2829 | * @ep: The endpoint on which interrupt is asserted. |
5321922c VM |
2830 | * |
2831 | * This is starting point for ISOC-OUT transfer, synchronization done with | |
2832 | * first out token received from host while corresponding EP is disabled. | |
2833 | * | |
2834 | * Device does not know initial frame in which out token will come. For this | |
2835 | * HW generates OUTTKNEPDIS - out token is received while EP is disabled. Upon | |
2836 | * getting this interrupt SW starts calculation for next transfer frame. | |
2837 | */ | |
2838 | static void dwc2_gadget_handle_out_token_ep_disabled(struct dwc2_hsotg_ep *ep) | |
2839 | { | |
2840 | struct dwc2_hsotg *hsotg = ep->parent; | |
2841 | int dir_in = ep->dir_in; | |
2842 | u32 doepmsk; | |
2843 | ||
2844 | if (dir_in || !ep->isochronous) | |
2845 | return; | |
2846 | ||
540ccba0 VA |
2847 | if (using_desc_dma(hsotg)) { |
2848 | if (ep->target_frame == TARGET_FRAME_INITIAL) { | |
2849 | /* Start first ISO Out */ | |
4d4f1e79 | 2850 | ep->target_frame = hsotg->frame_number; |
540ccba0 VA |
2851 | dwc2_gadget_start_isoc_ddma(ep); |
2852 | } | |
2853 | return; | |
2854 | } | |
2855 | ||
5321922c VM |
2856 | if (ep->interval > 1 && |
2857 | ep->target_frame == TARGET_FRAME_INITIAL) { | |
5321922c VM |
2858 | u32 ctrl; |
2859 | ||
4d4f1e79 | 2860 | ep->target_frame = hsotg->frame_number; |
5321922c VM |
2861 | dwc2_gadget_incr_frame_num(ep); |
2862 | ||
f25c42b8 | 2863 | ctrl = dwc2_readl(hsotg, DOEPCTL(ep->index)); |
5321922c VM |
2864 | if (ep->target_frame & 0x1) |
2865 | ctrl |= DXEPCTL_SETODDFR; | |
2866 | else | |
2867 | ctrl |= DXEPCTL_SETEVENFR; | |
2868 | ||
f25c42b8 | 2869 | dwc2_writel(hsotg, ctrl, DOEPCTL(ep->index)); |
5321922c VM |
2870 | } |
2871 | ||
2872 | dwc2_gadget_start_next_request(ep); | |
f25c42b8 | 2873 | doepmsk = dwc2_readl(hsotg, DOEPMSK); |
5321922c | 2874 | doepmsk &= ~DOEPMSK_OUTTKNEPDISMSK; |
f25c42b8 | 2875 | dwc2_writel(hsotg, doepmsk, DOEPMSK); |
5321922c VM |
2876 | } |
2877 | ||
2878 | /** | |
38beaec6 JY |
2879 | * dwc2_gadget_handle_nak - handle NAK interrupt |
2880 | * @hs_ep: The endpoint on which interrupt is asserted. | |
2881 | * | |
2882 | * This is starting point for ISOC-IN transfer, synchronization done with | |
2883 | * first IN token received from host while corresponding EP is disabled. | |
2884 | * | |
2885 | * Device does not know when first one token will arrive from host. On first | |
2886 | * token arrival HW generates 2 interrupts: 'in token received while FIFO empty' | |
2887 | * and 'NAK'. NAK interrupt for ISOC-IN means that token has arrived and ZLP was | |
2888 | * sent in response to that as there was no data in FIFO. SW is basing on this | |
2889 | * interrupt to obtain frame in which token has come and then based on the | |
2890 | * interval calculates next frame for transfer. | |
2891 | */ | |
5321922c VM |
2892 | static void dwc2_gadget_handle_nak(struct dwc2_hsotg_ep *hs_ep) |
2893 | { | |
2894 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
2895 | int dir_in = hs_ep->dir_in; | |
2896 | ||
2897 | if (!dir_in || !hs_ep->isochronous) | |
2898 | return; | |
2899 | ||
2900 | if (hs_ep->target_frame == TARGET_FRAME_INITIAL) { | |
540ccba0 VA |
2901 | |
2902 | if (using_desc_dma(hsotg)) { | |
4d4f1e79 | 2903 | hs_ep->target_frame = hsotg->frame_number; |
729cac69 | 2904 | dwc2_gadget_incr_frame_num(hs_ep); |
48dac4e4 GT |
2905 | |
2906 | /* In service interval mode target_frame must | |
2907 | * be set to last (u)frame of the service interval. | |
2908 | */ | |
2909 | if (hsotg->params.service_interval) { | |
2910 | /* Set target_frame to the first (u)frame of | |
2911 | * the service interval | |
2912 | */ | |
2913 | hs_ep->target_frame &= ~hs_ep->interval + 1; | |
2914 | ||
2915 | /* Set target_frame to the last (u)frame of | |
2916 | * the service interval | |
2917 | */ | |
2918 | dwc2_gadget_incr_frame_num(hs_ep); | |
2919 | dwc2_gadget_dec_frame_num_by_one(hs_ep); | |
2920 | } | |
2921 | ||
540ccba0 VA |
2922 | dwc2_gadget_start_isoc_ddma(hs_ep); |
2923 | return; | |
2924 | } | |
2925 | ||
4d4f1e79 | 2926 | hs_ep->target_frame = hsotg->frame_number; |
5321922c | 2927 | if (hs_ep->interval > 1) { |
f25c42b8 | 2928 | u32 ctrl = dwc2_readl(hsotg, |
5321922c VM |
2929 | DIEPCTL(hs_ep->index)); |
2930 | if (hs_ep->target_frame & 0x1) | |
2931 | ctrl |= DXEPCTL_SETODDFR; | |
2932 | else | |
2933 | ctrl |= DXEPCTL_SETEVENFR; | |
2934 | ||
f25c42b8 | 2935 | dwc2_writel(hsotg, ctrl, DIEPCTL(hs_ep->index)); |
5321922c VM |
2936 | } |
2937 | ||
2938 | dwc2_hsotg_complete_request(hsotg, hs_ep, | |
2939 | get_ep_head(hs_ep), 0); | |
2940 | } | |
2941 | ||
729cac69 MH |
2942 | if (!using_desc_dma(hsotg)) |
2943 | dwc2_gadget_incr_frame_num(hs_ep); | |
5321922c VM |
2944 | } |
2945 | ||
5b7d70c6 | 2946 | /** |
1f91b4cc | 2947 | * dwc2_hsotg_epint - handle an in/out endpoint interrupt |
5b7d70c6 BD |
2948 | * @hsotg: The driver state |
2949 | * @idx: The index for the endpoint (0..15) | |
2950 | * @dir_in: Set if this is an IN endpoint | |
2951 | * | |
2952 | * Process and clear any interrupt pending for an individual endpoint | |
8b9bc460 | 2953 | */ |
1f91b4cc | 2954 | static void dwc2_hsotg_epint(struct dwc2_hsotg *hsotg, unsigned int idx, |
9da51974 | 2955 | int dir_in) |
5b7d70c6 | 2956 | { |
1f91b4cc | 2957 | struct dwc2_hsotg_ep *hs_ep = index_to_ep(hsotg, idx, dir_in); |
94cb8fd6 LM |
2958 | u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx); |
2959 | u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx); | |
2960 | u32 epsiz_reg = dir_in ? DIEPTSIZ(idx) : DOEPTSIZ(idx); | |
5b7d70c6 | 2961 | u32 ints; |
1479e841 | 2962 | u32 ctrl; |
5b7d70c6 | 2963 | |
32601588 | 2964 | ints = dwc2_gadget_read_ep_interrupts(hsotg, idx, dir_in); |
f25c42b8 | 2965 | ctrl = dwc2_readl(hsotg, epctl_reg); |
5b7d70c6 | 2966 | |
a3395f0d | 2967 | /* Clear endpoint interrupts */ |
f25c42b8 | 2968 | dwc2_writel(hsotg, ints, epint_reg); |
a3395f0d | 2969 | |
c6f5c050 MYK |
2970 | if (!hs_ep) { |
2971 | dev_err(hsotg->dev, "%s:Interrupt for unconfigured ep%d(%s)\n", | |
9da51974 | 2972 | __func__, idx, dir_in ? "in" : "out"); |
c6f5c050 MYK |
2973 | return; |
2974 | } | |
2975 | ||
5b7d70c6 BD |
2976 | dev_dbg(hsotg->dev, "%s: ep%d(%s) DxEPINT=0x%08x\n", |
2977 | __func__, idx, dir_in ? "in" : "out", ints); | |
2978 | ||
b787d755 MYK |
2979 | /* Don't process XferCompl interrupt if it is a setup packet */ |
2980 | if (idx == 0 && (ints & (DXEPINT_SETUP | DXEPINT_SETUP_RCVD))) | |
2981 | ints &= ~DXEPINT_XFERCOMPL; | |
2982 | ||
f0afdb42 VA |
2983 | /* |
2984 | * Don't process XferCompl interrupt in DDMA if EP0 is still in SETUP | |
2985 | * stage and xfercomplete was generated without SETUP phase done | |
2986 | * interrupt. SW should parse received setup packet only after host's | |
2987 | * exit from setup phase of control transfer. | |
2988 | */ | |
2989 | if (using_desc_dma(hsotg) && idx == 0 && !hs_ep->dir_in && | |
2990 | hsotg->ep0_state == DWC2_EP0_SETUP && !(ints & DXEPINT_SETUP)) | |
2991 | ints &= ~DXEPINT_XFERCOMPL; | |
2992 | ||
837e9f00 | 2993 | if (ints & DXEPINT_XFERCOMPL) { |
5b7d70c6 | 2994 | dev_dbg(hsotg->dev, |
47a1685f | 2995 | "%s: XferCompl: DxEPCTL=0x%08x, DXEPTSIZ=%08x\n", |
f25c42b8 GS |
2996 | __func__, dwc2_readl(hsotg, epctl_reg), |
2997 | dwc2_readl(hsotg, epsiz_reg)); | |
5b7d70c6 | 2998 | |
540ccba0 VA |
2999 | /* In DDMA handle isochronous requests separately */ |
3000 | if (using_desc_dma(hsotg) && hs_ep->isochronous) { | |
729cac69 MH |
3001 | /* XferCompl set along with BNA */ |
3002 | if (!(ints & DXEPINT_BNAINTR)) | |
3003 | dwc2_gadget_complete_isoc_request_ddma(hs_ep); | |
540ccba0 VA |
3004 | } else if (dir_in) { |
3005 | /* | |
3006 | * We get OutDone from the FIFO, so we only | |
3007 | * need to look at completing IN requests here | |
3008 | * if operating slave mode | |
3009 | */ | |
837e9f00 VM |
3010 | if (hs_ep->isochronous && hs_ep->interval > 1) |
3011 | dwc2_gadget_incr_frame_num(hs_ep); | |
3012 | ||
1f91b4cc | 3013 | dwc2_hsotg_complete_in(hsotg, hs_ep); |
837e9f00 VM |
3014 | if (ints & DXEPINT_NAKINTRPT) |
3015 | ints &= ~DXEPINT_NAKINTRPT; | |
5b7d70c6 | 3016 | |
c9a64ea8 | 3017 | if (idx == 0 && !hs_ep->req) |
1f91b4cc | 3018 | dwc2_hsotg_enqueue_setup(hsotg); |
5b7d70c6 | 3019 | } else if (using_dma(hsotg)) { |
8b9bc460 LM |
3020 | /* |
3021 | * We're using DMA, we need to fire an OutDone here | |
3022 | * as we ignore the RXFIFO. | |
3023 | */ | |
837e9f00 VM |
3024 | if (hs_ep->isochronous && hs_ep->interval > 1) |
3025 | dwc2_gadget_incr_frame_num(hs_ep); | |
5b7d70c6 | 3026 | |
1f91b4cc | 3027 | dwc2_hsotg_handle_outdone(hsotg, idx); |
5b7d70c6 | 3028 | } |
5b7d70c6 BD |
3029 | } |
3030 | ||
bd9971f0 VM |
3031 | if (ints & DXEPINT_EPDISBLD) |
3032 | dwc2_gadget_handle_ep_disabled(hs_ep); | |
9c39ddc6 | 3033 | |
5321922c VM |
3034 | if (ints & DXEPINT_OUTTKNEPDIS) |
3035 | dwc2_gadget_handle_out_token_ep_disabled(hs_ep); | |
3036 | ||
3037 | if (ints & DXEPINT_NAKINTRPT) | |
3038 | dwc2_gadget_handle_nak(hs_ep); | |
3039 | ||
47a1685f | 3040 | if (ints & DXEPINT_AHBERR) |
5b7d70c6 | 3041 | dev_dbg(hsotg->dev, "%s: AHBErr\n", __func__); |
5b7d70c6 | 3042 | |
47a1685f | 3043 | if (ints & DXEPINT_SETUP) { /* Setup or Timeout */ |
5b7d70c6 BD |
3044 | dev_dbg(hsotg->dev, "%s: Setup/Timeout\n", __func__); |
3045 | ||
3046 | if (using_dma(hsotg) && idx == 0) { | |
8b9bc460 LM |
3047 | /* |
3048 | * this is the notification we've received a | |
5b7d70c6 BD |
3049 | * setup packet. In non-DMA mode we'd get this |
3050 | * from the RXFIFO, instead we need to process | |
8b9bc460 LM |
3051 | * the setup here. |
3052 | */ | |
5b7d70c6 BD |
3053 | |
3054 | if (dir_in) | |
3055 | WARN_ON_ONCE(1); | |
3056 | else | |
1f91b4cc | 3057 | dwc2_hsotg_handle_outdone(hsotg, 0); |
5b7d70c6 | 3058 | } |
5b7d70c6 BD |
3059 | } |
3060 | ||
ef750c71 | 3061 | if (ints & DXEPINT_STSPHSERCVD) { |
9d9a6b07 VA |
3062 | dev_dbg(hsotg->dev, "%s: StsPhseRcvd\n", __func__); |
3063 | ||
9e95a66c MH |
3064 | /* Safety check EP0 state when STSPHSERCVD asserted */ |
3065 | if (hsotg->ep0_state == DWC2_EP0_DATA_OUT) { | |
3066 | /* Move to STATUS IN for DDMA */ | |
b4c53b4a MH |
3067 | if (using_desc_dma(hsotg)) { |
3068 | if (!hsotg->delayed_status) | |
3069 | dwc2_hsotg_ep0_zlp(hsotg, true); | |
3070 | else | |
3071 | /* In case of 3 stage Control Write with delayed | |
3072 | * status, when Status IN transfer started | |
3073 | * before STSPHSERCVD asserted, NAKSTS bit not | |
3074 | * cleared by CNAK in dwc2_hsotg_start_req() | |
3075 | * function. Clear now NAKSTS to allow complete | |
3076 | * transfer. | |
3077 | */ | |
3078 | dwc2_set_bit(hsotg, DIEPCTL(0), | |
3079 | DXEPCTL_CNAK); | |
3080 | } | |
9e95a66c MH |
3081 | } |
3082 | ||
ef750c71 VA |
3083 | } |
3084 | ||
47a1685f | 3085 | if (ints & DXEPINT_BACK2BACKSETUP) |
5b7d70c6 | 3086 | dev_dbg(hsotg->dev, "%s: B2BSetup/INEPNakEff\n", __func__); |
5b7d70c6 | 3087 | |
540ccba0 VA |
3088 | if (ints & DXEPINT_BNAINTR) { |
3089 | dev_dbg(hsotg->dev, "%s: BNA interrupt\n", __func__); | |
540ccba0 | 3090 | if (hs_ep->isochronous) |
729cac69 | 3091 | dwc2_gadget_handle_isoc_bna(hs_ep); |
540ccba0 VA |
3092 | } |
3093 | ||
1479e841 | 3094 | if (dir_in && !hs_ep->isochronous) { |
8b9bc460 | 3095 | /* not sure if this is important, but we'll clear it anyway */ |
26ddef5d | 3096 | if (ints & DXEPINT_INTKNTXFEMP) { |
5b7d70c6 BD |
3097 | dev_dbg(hsotg->dev, "%s: ep%d: INTknTXFEmpMsk\n", |
3098 | __func__, idx); | |
5b7d70c6 BD |
3099 | } |
3100 | ||
3101 | /* this probably means something bad is happening */ | |
26ddef5d | 3102 | if (ints & DXEPINT_INTKNEPMIS) { |
5b7d70c6 BD |
3103 | dev_warn(hsotg->dev, "%s: ep%d: INTknEP\n", |
3104 | __func__, idx); | |
5b7d70c6 | 3105 | } |
10aebc77 BD |
3106 | |
3107 | /* FIFO has space or is empty (see GAHBCFG) */ | |
3108 | if (hsotg->dedicated_fifos && | |
26ddef5d | 3109 | ints & DXEPINT_TXFEMP) { |
10aebc77 BD |
3110 | dev_dbg(hsotg->dev, "%s: ep%d: TxFIFOEmpty\n", |
3111 | __func__, idx); | |
70fa030f | 3112 | if (!using_dma(hsotg)) |
1f91b4cc | 3113 | dwc2_hsotg_trytx(hsotg, hs_ep); |
10aebc77 | 3114 | } |
5b7d70c6 | 3115 | } |
5b7d70c6 BD |
3116 | } |
3117 | ||
3118 | /** | |
1f91b4cc | 3119 | * dwc2_hsotg_irq_enumdone - Handle EnumDone interrupt (enumeration done) |
5b7d70c6 BD |
3120 | * @hsotg: The device state. |
3121 | * | |
3122 | * Handle updating the device settings after the enumeration phase has | |
3123 | * been completed. | |
8b9bc460 | 3124 | */ |
1f91b4cc | 3125 | static void dwc2_hsotg_irq_enumdone(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 3126 | { |
f25c42b8 | 3127 | u32 dsts = dwc2_readl(hsotg, DSTS); |
9b2667f1 | 3128 | int ep0_mps = 0, ep_mps = 8; |
5b7d70c6 | 3129 | |
8b9bc460 LM |
3130 | /* |
3131 | * This should signal the finish of the enumeration phase | |
5b7d70c6 | 3132 | * of the USB handshaking, so we should now know what rate |
8b9bc460 LM |
3133 | * we connected at. |
3134 | */ | |
5b7d70c6 BD |
3135 | |
3136 | dev_dbg(hsotg->dev, "EnumDone (DSTS=0x%08x)\n", dsts); | |
3137 | ||
8b9bc460 LM |
3138 | /* |
3139 | * note, since we're limited by the size of transfer on EP0, and | |
5b7d70c6 | 3140 | * it seems IN transfers must be a even number of packets we do |
8b9bc460 LM |
3141 | * not advertise a 64byte MPS on EP0. |
3142 | */ | |
5b7d70c6 BD |
3143 | |
3144 | /* catch both EnumSpd_FS and EnumSpd_FS48 */ | |
6d76c92c | 3145 | switch ((dsts & DSTS_ENUMSPD_MASK) >> DSTS_ENUMSPD_SHIFT) { |
47a1685f DN |
3146 | case DSTS_ENUMSPD_FS: |
3147 | case DSTS_ENUMSPD_FS48: | |
5b7d70c6 | 3148 | hsotg->gadget.speed = USB_SPEED_FULL; |
5b7d70c6 | 3149 | ep0_mps = EP0_MPS_LIMIT; |
295538ff | 3150 | ep_mps = 1023; |
5b7d70c6 BD |
3151 | break; |
3152 | ||
47a1685f | 3153 | case DSTS_ENUMSPD_HS: |
5b7d70c6 | 3154 | hsotg->gadget.speed = USB_SPEED_HIGH; |
5b7d70c6 | 3155 | ep0_mps = EP0_MPS_LIMIT; |
295538ff | 3156 | ep_mps = 1024; |
5b7d70c6 BD |
3157 | break; |
3158 | ||
47a1685f | 3159 | case DSTS_ENUMSPD_LS: |
5b7d70c6 | 3160 | hsotg->gadget.speed = USB_SPEED_LOW; |
552d940f VM |
3161 | ep0_mps = 8; |
3162 | ep_mps = 8; | |
8b9bc460 LM |
3163 | /* |
3164 | * note, we don't actually support LS in this driver at the | |
5b7d70c6 BD |
3165 | * moment, and the documentation seems to imply that it isn't |
3166 | * supported by the PHYs on some of the devices. | |
3167 | */ | |
3168 | break; | |
3169 | } | |
e538dfda MN |
3170 | dev_info(hsotg->dev, "new device is %s\n", |
3171 | usb_speed_string(hsotg->gadget.speed)); | |
5b7d70c6 | 3172 | |
8b9bc460 LM |
3173 | /* |
3174 | * we should now know the maximum packet size for an | |
3175 | * endpoint, so set the endpoints to a default value. | |
3176 | */ | |
5b7d70c6 BD |
3177 | |
3178 | if (ep0_mps) { | |
3179 | int i; | |
c6f5c050 | 3180 | /* Initialize ep0 for both in and out directions */ |
ee2c40de VM |
3181 | dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 0, 1); |
3182 | dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 0, 0); | |
c6f5c050 MYK |
3183 | for (i = 1; i < hsotg->num_of_eps; i++) { |
3184 | if (hsotg->eps_in[i]) | |
ee2c40de VM |
3185 | dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps, |
3186 | 0, 1); | |
c6f5c050 | 3187 | if (hsotg->eps_out[i]) |
ee2c40de VM |
3188 | dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps, |
3189 | 0, 0); | |
c6f5c050 | 3190 | } |
5b7d70c6 BD |
3191 | } |
3192 | ||
3193 | /* ensure after enumeration our EP0 is active */ | |
3194 | ||
1f91b4cc | 3195 | dwc2_hsotg_enqueue_setup(hsotg); |
5b7d70c6 BD |
3196 | |
3197 | dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n", | |
f25c42b8 GS |
3198 | dwc2_readl(hsotg, DIEPCTL0), |
3199 | dwc2_readl(hsotg, DOEPCTL0)); | |
5b7d70c6 BD |
3200 | } |
3201 | ||
3202 | /** | |
3203 | * kill_all_requests - remove all requests from the endpoint's queue | |
3204 | * @hsotg: The device state. | |
3205 | * @ep: The endpoint the requests may be on. | |
3206 | * @result: The result code to use. | |
5b7d70c6 BD |
3207 | * |
3208 | * Go through the requests on the given endpoint and mark them | |
3209 | * completed with the given result code. | |
3210 | */ | |
941fcce4 | 3211 | static void kill_all_requests(struct dwc2_hsotg *hsotg, |
1f91b4cc | 3212 | struct dwc2_hsotg_ep *ep, |
6b448af4 | 3213 | int result) |
5b7d70c6 | 3214 | { |
1f91b4cc | 3215 | struct dwc2_hsotg_req *req, *treq; |
9da51974 | 3216 | unsigned int size; |
5b7d70c6 | 3217 | |
6b448af4 | 3218 | ep->req = NULL; |
5b7d70c6 | 3219 | |
6b448af4 | 3220 | list_for_each_entry_safe(req, treq, &ep->queue, queue) |
1f91b4cc | 3221 | dwc2_hsotg_complete_request(hsotg, ep, req, |
9da51974 | 3222 | result); |
6b448af4 | 3223 | |
b203d0a2 RB |
3224 | if (!hsotg->dedicated_fifos) |
3225 | return; | |
f25c42b8 | 3226 | size = (dwc2_readl(hsotg, DTXFSTS(ep->fifo_index)) & 0xffff) * 4; |
b203d0a2 | 3227 | if (size < ep->fifo_size) |
1f91b4cc | 3228 | dwc2_hsotg_txfifo_flush(hsotg, ep->fifo_index); |
5b7d70c6 BD |
3229 | } |
3230 | ||
5b7d70c6 | 3231 | /** |
1f91b4cc | 3232 | * dwc2_hsotg_disconnect - disconnect service |
5b7d70c6 BD |
3233 | * @hsotg: The device state. |
3234 | * | |
5e891342 LM |
3235 | * The device has been disconnected. Remove all current |
3236 | * transactions and signal the gadget driver that this | |
3237 | * has happened. | |
8b9bc460 | 3238 | */ |
1f91b4cc | 3239 | void dwc2_hsotg_disconnect(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 3240 | { |
9da51974 | 3241 | unsigned int ep; |
5b7d70c6 | 3242 | |
4ace06e8 MS |
3243 | if (!hsotg->connected) |
3244 | return; | |
3245 | ||
3246 | hsotg->connected = 0; | |
9e14d0a5 | 3247 | hsotg->test_mode = 0; |
c6f5c050 | 3248 | |
dccf1bad | 3249 | /* all endpoints should be shutdown */ |
c6f5c050 MYK |
3250 | for (ep = 0; ep < hsotg->num_of_eps; ep++) { |
3251 | if (hsotg->eps_in[ep]) | |
4fe4f9fe MH |
3252 | kill_all_requests(hsotg, hsotg->eps_in[ep], |
3253 | -ESHUTDOWN); | |
c6f5c050 | 3254 | if (hsotg->eps_out[ep]) |
4fe4f9fe MH |
3255 | kill_all_requests(hsotg, hsotg->eps_out[ep], |
3256 | -ESHUTDOWN); | |
c6f5c050 | 3257 | } |
5b7d70c6 BD |
3258 | |
3259 | call_gadget(hsotg, disconnect); | |
065d3931 | 3260 | hsotg->lx_state = DWC2_L3; |
ce2b21a4 JS |
3261 | |
3262 | usb_gadget_set_state(&hsotg->gadget, USB_STATE_NOTATTACHED); | |
5b7d70c6 BD |
3263 | } |
3264 | ||
3265 | /** | |
1f91b4cc | 3266 | * dwc2_hsotg_irq_fifoempty - TX FIFO empty interrupt handler |
5b7d70c6 BD |
3267 | * @hsotg: The device state: |
3268 | * @periodic: True if this is a periodic FIFO interrupt | |
3269 | */ | |
1f91b4cc | 3270 | static void dwc2_hsotg_irq_fifoempty(struct dwc2_hsotg *hsotg, bool periodic) |
5b7d70c6 | 3271 | { |
1f91b4cc | 3272 | struct dwc2_hsotg_ep *ep; |
5b7d70c6 BD |
3273 | int epno, ret; |
3274 | ||
3275 | /* look through for any more data to transmit */ | |
b3f489b2 | 3276 | for (epno = 0; epno < hsotg->num_of_eps; epno++) { |
c6f5c050 MYK |
3277 | ep = index_to_ep(hsotg, epno, 1); |
3278 | ||
3279 | if (!ep) | |
3280 | continue; | |
5b7d70c6 BD |
3281 | |
3282 | if (!ep->dir_in) | |
3283 | continue; | |
3284 | ||
3285 | if ((periodic && !ep->periodic) || | |
3286 | (!periodic && ep->periodic)) | |
3287 | continue; | |
3288 | ||
1f91b4cc | 3289 | ret = dwc2_hsotg_trytx(hsotg, ep); |
5b7d70c6 BD |
3290 | if (ret < 0) |
3291 | break; | |
3292 | } | |
3293 | } | |
3294 | ||
5b7d70c6 | 3295 | /* IRQ flags which will trigger a retry around the IRQ loop */ |
47a1685f DN |
3296 | #define IRQ_RETRY_MASK (GINTSTS_NPTXFEMP | \ |
3297 | GINTSTS_PTXFEMP | \ | |
3298 | GINTSTS_RXFLVL) | |
5b7d70c6 | 3299 | |
4fe4f9fe | 3300 | static int dwc2_hsotg_ep_disable(struct usb_ep *ep); |
8b9bc460 | 3301 | /** |
1f91b4cc | 3302 | * dwc2_hsotg_core_init - issue softreset to the core |
8b9bc460 | 3303 | * @hsotg: The device state |
6fb914d7 | 3304 | * @is_usb_reset: Usb resetting flag |
8b9bc460 LM |
3305 | * |
3306 | * Issue a soft reset to the core, and await the core finishing it. | |
3307 | */ | |
1f91b4cc | 3308 | void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg, |
9da51974 | 3309 | bool is_usb_reset) |
308d734e | 3310 | { |
1ee6903b | 3311 | u32 intmsk; |
643cc4de | 3312 | u32 val; |
ecd9a7ad | 3313 | u32 usbcfg; |
79c3b5bb | 3314 | u32 dcfg = 0; |
dccf1bad | 3315 | int ep; |
643cc4de | 3316 | |
5390d438 MYK |
3317 | /* Kill any ep0 requests as controller will be reinitialized */ |
3318 | kill_all_requests(hsotg, hsotg->eps_out[0], -ECONNRESET); | |
3319 | ||
dccf1bad | 3320 | if (!is_usb_reset) { |
6e6360b6 | 3321 | if (dwc2_core_reset(hsotg, true)) |
86de4895 | 3322 | return; |
dccf1bad MH |
3323 | } else { |
3324 | /* all endpoints should be shutdown */ | |
3325 | for (ep = 1; ep < hsotg->num_of_eps; ep++) { | |
3326 | if (hsotg->eps_in[ep]) | |
3327 | dwc2_hsotg_ep_disable(&hsotg->eps_in[ep]->ep); | |
3328 | if (hsotg->eps_out[ep]) | |
3329 | dwc2_hsotg_ep_disable(&hsotg->eps_out[ep]->ep); | |
3330 | } | |
3331 | } | |
308d734e LM |
3332 | |
3333 | /* | |
3334 | * we must now enable ep0 ready for host detection and then | |
3335 | * set configuration. | |
3336 | */ | |
3337 | ||
ecd9a7ad | 3338 | /* keep other bits untouched (so e.g. forced modes are not lost) */ |
f25c42b8 | 3339 | usbcfg = dwc2_readl(hsotg, GUSBCFG); |
1e868545 | 3340 | usbcfg &= ~GUSBCFG_TOUTCAL_MASK; |
707d80f0 | 3341 | usbcfg |= GUSBCFG_TOUTCAL(7); |
ecd9a7ad | 3342 | |
1e868545 JM |
3343 | /* remove the HNP/SRP and set the PHY */ |
3344 | usbcfg &= ~(GUSBCFG_SRPCAP | GUSBCFG_HNPCAP); | |
3345 | dwc2_writel(hsotg, usbcfg, GUSBCFG); | |
707d80f0 | 3346 | |
1e868545 | 3347 | dwc2_phy_init(hsotg, true); |
308d734e | 3348 | |
1f91b4cc | 3349 | dwc2_hsotg_init_fifo(hsotg); |
308d734e | 3350 | |
643cc4de | 3351 | if (!is_usb_reset) |
f25c42b8 | 3352 | dwc2_set_bit(hsotg, DCTL, DCTL_SFTDISCON); |
308d734e | 3353 | |
79c3b5bb | 3354 | dcfg |= DCFG_EPMISCNT(1); |
38e9002b VM |
3355 | |
3356 | switch (hsotg->params.speed) { | |
3357 | case DWC2_SPEED_PARAM_LOW: | |
3358 | dcfg |= DCFG_DEVSPD_LS; | |
3359 | break; | |
3360 | case DWC2_SPEED_PARAM_FULL: | |
79c3b5bb VA |
3361 | if (hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS) |
3362 | dcfg |= DCFG_DEVSPD_FS48; | |
3363 | else | |
3364 | dcfg |= DCFG_DEVSPD_FS; | |
38e9002b VM |
3365 | break; |
3366 | default: | |
79c3b5bb VA |
3367 | dcfg |= DCFG_DEVSPD_HS; |
3368 | } | |
38e9002b | 3369 | |
b43ebc96 GT |
3370 | if (hsotg->params.ipg_isoc_en) |
3371 | dcfg |= DCFG_IPG_ISOC_SUPPORDED; | |
3372 | ||
f25c42b8 | 3373 | dwc2_writel(hsotg, dcfg, DCFG); |
308d734e LM |
3374 | |
3375 | /* Clear any pending OTG interrupts */ | |
f25c42b8 | 3376 | dwc2_writel(hsotg, 0xffffffff, GOTGINT); |
308d734e LM |
3377 | |
3378 | /* Clear any pending interrupts */ | |
f25c42b8 | 3379 | dwc2_writel(hsotg, 0xffffffff, GINTSTS); |
1ee6903b | 3380 | intmsk = GINTSTS_ERLYSUSP | GINTSTS_SESSREQINT | |
47a1685f | 3381 | GINTSTS_GOUTNAKEFF | GINTSTS_GINNAKEFF | |
1ee6903b GH |
3382 | GINTSTS_USBRST | GINTSTS_RESETDET | |
3383 | GINTSTS_ENUMDONE | GINTSTS_OTGINT | | |
376f0401 SA |
3384 | GINTSTS_USBSUSP | GINTSTS_WKUPINT | |
3385 | GINTSTS_LPMTRANRCVD; | |
f4736701 VA |
3386 | |
3387 | if (!using_desc_dma(hsotg)) | |
3388 | intmsk |= GINTSTS_INCOMPL_SOIN | GINTSTS_INCOMPL_SOOUT; | |
1ee6903b | 3389 | |
95832c00 | 3390 | if (!hsotg->params.external_id_pin_ctl) |
1ee6903b GH |
3391 | intmsk |= GINTSTS_CONIDSTSCHNG; |
3392 | ||
f25c42b8 | 3393 | dwc2_writel(hsotg, intmsk, GINTMSK); |
308d734e | 3394 | |
a5c18f11 | 3395 | if (using_dma(hsotg)) { |
f25c42b8 | 3396 | dwc2_writel(hsotg, GAHBCFG_GLBL_INTR_EN | GAHBCFG_DMA_EN | |
d1ac8c80 | 3397 | hsotg->params.ahbcfg, |
f25c42b8 | 3398 | GAHBCFG); |
a5c18f11 VA |
3399 | |
3400 | /* Set DDMA mode support in the core if needed */ | |
3401 | if (using_desc_dma(hsotg)) | |
f25c42b8 | 3402 | dwc2_set_bit(hsotg, DCFG, DCFG_DESCDMA_EN); |
a5c18f11 VA |
3403 | |
3404 | } else { | |
f25c42b8 | 3405 | dwc2_writel(hsotg, ((hsotg->dedicated_fifos) ? |
95c8bc36 AS |
3406 | (GAHBCFG_NP_TXF_EMP_LVL | |
3407 | GAHBCFG_P_TXF_EMP_LVL) : 0) | | |
f25c42b8 | 3408 | GAHBCFG_GLBL_INTR_EN, GAHBCFG); |
a5c18f11 | 3409 | } |
308d734e LM |
3410 | |
3411 | /* | |
8acc8296 RB |
3412 | * If INTknTXFEmpMsk is enabled, it's important to disable ep interrupts |
3413 | * when we have no data to transfer. Otherwise we get being flooded by | |
3414 | * interrupts. | |
308d734e LM |
3415 | */ |
3416 | ||
f25c42b8 | 3417 | dwc2_writel(hsotg, ((hsotg->dedicated_fifos && !using_dma(hsotg)) ? |
6ff2e832 | 3418 | DIEPMSK_TXFIFOEMPTY | DIEPMSK_INTKNTXFEMPMSK : 0) | |
47a1685f | 3419 | DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK | |
837e9f00 | 3420 | DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK, |
f25c42b8 | 3421 | DIEPMSK); |
308d734e LM |
3422 | |
3423 | /* | |
3424 | * don't need XferCompl, we get that from RXFIFO in slave mode. In | |
9d9a6b07 | 3425 | * DMA mode we may need this and StsPhseRcvd. |
308d734e | 3426 | */ |
f25c42b8 | 3427 | dwc2_writel(hsotg, (using_dma(hsotg) ? (DIEPMSK_XFERCOMPLMSK | |
9d9a6b07 | 3428 | DOEPMSK_STSPHSERCVDMSK) : 0) | |
47a1685f | 3429 | DOEPMSK_EPDISBLDMSK | DOEPMSK_AHBERRMSK | |
9d9a6b07 | 3430 | DOEPMSK_SETUPMSK, |
f25c42b8 | 3431 | DOEPMSK); |
308d734e | 3432 | |
ec01f0b2 | 3433 | /* Enable BNA interrupt for DDMA */ |
37981e00 | 3434 | if (using_desc_dma(hsotg)) { |
f25c42b8 GS |
3435 | dwc2_set_bit(hsotg, DOEPMSK, DOEPMSK_BNAMSK); |
3436 | dwc2_set_bit(hsotg, DIEPMSK, DIEPMSK_BNAININTRMSK); | |
37981e00 | 3437 | } |
ec01f0b2 | 3438 | |
ca531bc2 GT |
3439 | /* Enable Service Interval mode if supported */ |
3440 | if (using_desc_dma(hsotg) && hsotg->params.service_interval) | |
3441 | dwc2_set_bit(hsotg, DCTL, DCTL_SERVICE_INTERVAL_SUPPORTED); | |
3442 | ||
f25c42b8 | 3443 | dwc2_writel(hsotg, 0, DAINTMSK); |
308d734e LM |
3444 | |
3445 | dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n", | |
f25c42b8 GS |
3446 | dwc2_readl(hsotg, DIEPCTL0), |
3447 | dwc2_readl(hsotg, DOEPCTL0)); | |
308d734e LM |
3448 | |
3449 | /* enable in and out endpoint interrupts */ | |
1f91b4cc | 3450 | dwc2_hsotg_en_gsint(hsotg, GINTSTS_OEPINT | GINTSTS_IEPINT); |
308d734e LM |
3451 | |
3452 | /* | |
3453 | * Enable the RXFIFO when in slave mode, as this is how we collect | |
3454 | * the data. In DMA mode, we get events from the FIFO but also | |
3455 | * things we cannot process, so do not use it. | |
3456 | */ | |
3457 | if (!using_dma(hsotg)) | |
1f91b4cc | 3458 | dwc2_hsotg_en_gsint(hsotg, GINTSTS_RXFLVL); |
308d734e LM |
3459 | |
3460 | /* Enable interrupts for EP0 in and out */ | |
1f91b4cc FB |
3461 | dwc2_hsotg_ctrl_epint(hsotg, 0, 0, 1); |
3462 | dwc2_hsotg_ctrl_epint(hsotg, 0, 1, 1); | |
308d734e | 3463 | |
643cc4de | 3464 | if (!is_usb_reset) { |
f25c42b8 | 3465 | dwc2_set_bit(hsotg, DCTL, DCTL_PWRONPRGDONE); |
643cc4de | 3466 | udelay(10); /* see openiboot */ |
f25c42b8 | 3467 | dwc2_clear_bit(hsotg, DCTL, DCTL_PWRONPRGDONE); |
643cc4de | 3468 | } |
308d734e | 3469 | |
f25c42b8 | 3470 | dev_dbg(hsotg->dev, "DCTL=0x%08x\n", dwc2_readl(hsotg, DCTL)); |
308d734e LM |
3471 | |
3472 | /* | |
94cb8fd6 | 3473 | * DxEPCTL_USBActEp says RO in manual, but seems to be set by |
308d734e LM |
3474 | * writing to the EPCTL register.. |
3475 | */ | |
3476 | ||
3477 | /* set to read 1 8byte packet */ | |
f25c42b8 GS |
3478 | dwc2_writel(hsotg, DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) | |
3479 | DXEPTSIZ_XFERSIZE(8), DOEPTSIZ0); | |
308d734e | 3480 | |
f25c42b8 | 3481 | dwc2_writel(hsotg, dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) | |
47a1685f DN |
3482 | DXEPCTL_CNAK | DXEPCTL_EPENA | |
3483 | DXEPCTL_USBACTEP, | |
f25c42b8 | 3484 | DOEPCTL0); |
308d734e LM |
3485 | |
3486 | /* enable, but don't activate EP0in */ | |
f25c42b8 GS |
3487 | dwc2_writel(hsotg, dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) | |
3488 | DXEPCTL_USBACTEP, DIEPCTL0); | |
308d734e | 3489 | |
308d734e | 3490 | /* clear global NAKs */ |
643cc4de GH |
3491 | val = DCTL_CGOUTNAK | DCTL_CGNPINNAK; |
3492 | if (!is_usb_reset) | |
3493 | val |= DCTL_SFTDISCON; | |
f25c42b8 | 3494 | dwc2_set_bit(hsotg, DCTL, val); |
308d734e | 3495 | |
21b03405 SA |
3496 | /* configure the core to support LPM */ |
3497 | dwc2_gadget_init_lpm(hsotg); | |
3498 | ||
15d9dbf8 GT |
3499 | /* program GREFCLK register if needed */ |
3500 | if (using_desc_dma(hsotg) && hsotg->params.service_interval) | |
3501 | dwc2_gadget_program_ref_clk(hsotg); | |
3502 | ||
308d734e LM |
3503 | /* must be at-least 3ms to allow bus to see disconnect */ |
3504 | mdelay(3); | |
3505 | ||
065d3931 | 3506 | hsotg->lx_state = DWC2_L0; |
755d7395 VM |
3507 | |
3508 | dwc2_hsotg_enqueue_setup(hsotg); | |
3509 | ||
3510 | dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n", | |
f25c42b8 GS |
3511 | dwc2_readl(hsotg, DIEPCTL0), |
3512 | dwc2_readl(hsotg, DOEPCTL0)); | |
ad38dc5d MS |
3513 | } |
3514 | ||
1f91b4cc | 3515 | static void dwc2_hsotg_core_disconnect(struct dwc2_hsotg *hsotg) |
ad38dc5d MS |
3516 | { |
3517 | /* set the soft-disconnect bit */ | |
f25c42b8 | 3518 | dwc2_set_bit(hsotg, DCTL, DCTL_SFTDISCON); |
ad38dc5d | 3519 | } |
ac3c81f3 | 3520 | |
1f91b4cc | 3521 | void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg) |
ad38dc5d | 3522 | { |
308d734e | 3523 | /* remove the soft-disconnect and let's go */ |
f25c42b8 | 3524 | dwc2_clear_bit(hsotg, DCTL, DCTL_SFTDISCON); |
308d734e LM |
3525 | } |
3526 | ||
381fc8f8 VM |
3527 | /** |
3528 | * dwc2_gadget_handle_incomplete_isoc_in - handle incomplete ISO IN Interrupt. | |
3529 | * @hsotg: The device state: | |
3530 | * | |
3531 | * This interrupt indicates one of the following conditions occurred while | |
3532 | * transmitting an ISOC transaction. | |
3533 | * - Corrupted IN Token for ISOC EP. | |
3534 | * - Packet not complete in FIFO. | |
3535 | * | |
3536 | * The following actions will be taken: | |
3537 | * - Determine the EP | |
3538 | * - Disable EP; when 'Endpoint Disabled' interrupt is received Flush FIFO | |
3539 | */ | |
3540 | static void dwc2_gadget_handle_incomplete_isoc_in(struct dwc2_hsotg *hsotg) | |
3541 | { | |
3542 | struct dwc2_hsotg_ep *hs_ep; | |
3543 | u32 epctrl; | |
1b4977c7 | 3544 | u32 daintmsk; |
381fc8f8 VM |
3545 | u32 idx; |
3546 | ||
3547 | dev_dbg(hsotg->dev, "Incomplete isoc in interrupt received:\n"); | |
3548 | ||
f25c42b8 | 3549 | daintmsk = dwc2_readl(hsotg, DAINTMSK); |
1b4977c7 | 3550 | |
d5d5f079 | 3551 | for (idx = 1; idx < hsotg->num_of_eps; idx++) { |
381fc8f8 | 3552 | hs_ep = hsotg->eps_in[idx]; |
1b4977c7 | 3553 | /* Proceed only unmasked ISOC EPs */ |
89066b36 | 3554 | if ((BIT(idx) & ~daintmsk) || !hs_ep->isochronous) |
1b4977c7 RK |
3555 | continue; |
3556 | ||
f25c42b8 | 3557 | epctrl = dwc2_readl(hsotg, DIEPCTL(idx)); |
1b4977c7 | 3558 | if ((epctrl & DXEPCTL_EPENA) && |
381fc8f8 VM |
3559 | dwc2_gadget_target_frame_elapsed(hs_ep)) { |
3560 | epctrl |= DXEPCTL_SNAK; | |
3561 | epctrl |= DXEPCTL_EPDIS; | |
f25c42b8 | 3562 | dwc2_writel(hsotg, epctrl, DIEPCTL(idx)); |
381fc8f8 VM |
3563 | } |
3564 | } | |
3565 | ||
3566 | /* Clear interrupt */ | |
f25c42b8 | 3567 | dwc2_writel(hsotg, GINTSTS_INCOMPL_SOIN, GINTSTS); |
381fc8f8 VM |
3568 | } |
3569 | ||
3570 | /** | |
3571 | * dwc2_gadget_handle_incomplete_isoc_out - handle incomplete ISO OUT Interrupt | |
3572 | * @hsotg: The device state: | |
3573 | * | |
3574 | * This interrupt indicates one of the following conditions occurred while | |
3575 | * transmitting an ISOC transaction. | |
3576 | * - Corrupted OUT Token for ISOC EP. | |
3577 | * - Packet not complete in FIFO. | |
3578 | * | |
3579 | * The following actions will be taken: | |
3580 | * - Determine the EP | |
3581 | * - Set DCTL_SGOUTNAK and unmask GOUTNAKEFF if target frame elapsed. | |
3582 | */ | |
3583 | static void dwc2_gadget_handle_incomplete_isoc_out(struct dwc2_hsotg *hsotg) | |
3584 | { | |
3585 | u32 gintsts; | |
3586 | u32 gintmsk; | |
689efb26 | 3587 | u32 daintmsk; |
381fc8f8 VM |
3588 | u32 epctrl; |
3589 | struct dwc2_hsotg_ep *hs_ep; | |
3590 | int idx; | |
3591 | ||
3592 | dev_dbg(hsotg->dev, "%s: GINTSTS_INCOMPL_SOOUT\n", __func__); | |
3593 | ||
f25c42b8 | 3594 | daintmsk = dwc2_readl(hsotg, DAINTMSK); |
689efb26 RK |
3595 | daintmsk >>= DAINT_OUTEP_SHIFT; |
3596 | ||
d5d5f079 | 3597 | for (idx = 1; idx < hsotg->num_of_eps; idx++) { |
381fc8f8 | 3598 | hs_ep = hsotg->eps_out[idx]; |
689efb26 | 3599 | /* Proceed only unmasked ISOC EPs */ |
89066b36 | 3600 | if ((BIT(idx) & ~daintmsk) || !hs_ep->isochronous) |
689efb26 RK |
3601 | continue; |
3602 | ||
f25c42b8 | 3603 | epctrl = dwc2_readl(hsotg, DOEPCTL(idx)); |
689efb26 | 3604 | if ((epctrl & DXEPCTL_EPENA) && |
381fc8f8 VM |
3605 | dwc2_gadget_target_frame_elapsed(hs_ep)) { |
3606 | /* Unmask GOUTNAKEFF interrupt */ | |
f25c42b8 | 3607 | gintmsk = dwc2_readl(hsotg, GINTMSK); |
381fc8f8 | 3608 | gintmsk |= GINTSTS_GOUTNAKEFF; |
f25c42b8 | 3609 | dwc2_writel(hsotg, gintmsk, GINTMSK); |
381fc8f8 | 3610 | |
f25c42b8 | 3611 | gintsts = dwc2_readl(hsotg, GINTSTS); |
689efb26 | 3612 | if (!(gintsts & GINTSTS_GOUTNAKEFF)) { |
f25c42b8 | 3613 | dwc2_set_bit(hsotg, DCTL, DCTL_SGOUTNAK); |
689efb26 RK |
3614 | break; |
3615 | } | |
381fc8f8 VM |
3616 | } |
3617 | } | |
3618 | ||
3619 | /* Clear interrupt */ | |
f25c42b8 | 3620 | dwc2_writel(hsotg, GINTSTS_INCOMPL_SOOUT, GINTSTS); |
381fc8f8 VM |
3621 | } |
3622 | ||
5b7d70c6 | 3623 | /** |
1f91b4cc | 3624 | * dwc2_hsotg_irq - handle device interrupt |
5b7d70c6 BD |
3625 | * @irq: The IRQ number triggered |
3626 | * @pw: The pw value when registered the handler. | |
3627 | */ | |
1f91b4cc | 3628 | static irqreturn_t dwc2_hsotg_irq(int irq, void *pw) |
5b7d70c6 | 3629 | { |
941fcce4 | 3630 | struct dwc2_hsotg *hsotg = pw; |
5b7d70c6 BD |
3631 | int retry_count = 8; |
3632 | u32 gintsts; | |
3633 | u32 gintmsk; | |
3634 | ||
ee3de8d7 VM |
3635 | if (!dwc2_is_device_mode(hsotg)) |
3636 | return IRQ_NONE; | |
3637 | ||
5ad1d316 | 3638 | spin_lock(&hsotg->lock); |
5b7d70c6 | 3639 | irq_retry: |
f25c42b8 GS |
3640 | gintsts = dwc2_readl(hsotg, GINTSTS); |
3641 | gintmsk = dwc2_readl(hsotg, GINTMSK); | |
5b7d70c6 BD |
3642 | |
3643 | dev_dbg(hsotg->dev, "%s: %08x %08x (%08x) retry %d\n", | |
3644 | __func__, gintsts, gintsts & gintmsk, gintmsk, retry_count); | |
3645 | ||
3646 | gintsts &= gintmsk; | |
3647 | ||
8fc37b82 MYK |
3648 | if (gintsts & GINTSTS_RESETDET) { |
3649 | dev_dbg(hsotg->dev, "%s: USBRstDet\n", __func__); | |
3650 | ||
f25c42b8 | 3651 | dwc2_writel(hsotg, GINTSTS_RESETDET, GINTSTS); |
8fc37b82 MYK |
3652 | |
3653 | /* This event must be used only if controller is suspended */ | |
3654 | if (hsotg->lx_state == DWC2_L2) { | |
41ba9b9b | 3655 | dwc2_exit_partial_power_down(hsotg, true); |
8fc37b82 MYK |
3656 | hsotg->lx_state = DWC2_L0; |
3657 | } | |
3658 | } | |
3659 | ||
3660 | if (gintsts & (GINTSTS_USBRST | GINTSTS_RESETDET)) { | |
f25c42b8 | 3661 | u32 usb_status = dwc2_readl(hsotg, GOTGCTL); |
8fc37b82 MYK |
3662 | u32 connected = hsotg->connected; |
3663 | ||
3664 | dev_dbg(hsotg->dev, "%s: USBRst\n", __func__); | |
3665 | dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n", | |
f25c42b8 | 3666 | dwc2_readl(hsotg, GNPTXSTS)); |
8fc37b82 | 3667 | |
f25c42b8 | 3668 | dwc2_writel(hsotg, GINTSTS_USBRST, GINTSTS); |
8fc37b82 MYK |
3669 | |
3670 | /* Report disconnection if it is not already done. */ | |
3671 | dwc2_hsotg_disconnect(hsotg); | |
3672 | ||
307bc11f | 3673 | /* Reset device address to zero */ |
f25c42b8 | 3674 | dwc2_clear_bit(hsotg, DCFG, DCFG_DEVADDR_MASK); |
307bc11f | 3675 | |
8fc37b82 MYK |
3676 | if (usb_status & GOTGCTL_BSESVLD && connected) |
3677 | dwc2_hsotg_core_init_disconnected(hsotg, true); | |
3678 | } | |
3679 | ||
47a1685f | 3680 | if (gintsts & GINTSTS_ENUMDONE) { |
f25c42b8 | 3681 | dwc2_writel(hsotg, GINTSTS_ENUMDONE, GINTSTS); |
a3395f0d | 3682 | |
1f91b4cc | 3683 | dwc2_hsotg_irq_enumdone(hsotg); |
5b7d70c6 BD |
3684 | } |
3685 | ||
47a1685f | 3686 | if (gintsts & (GINTSTS_OEPINT | GINTSTS_IEPINT)) { |
f25c42b8 GS |
3687 | u32 daint = dwc2_readl(hsotg, DAINT); |
3688 | u32 daintmsk = dwc2_readl(hsotg, DAINTMSK); | |
7e804650 | 3689 | u32 daint_out, daint_in; |
5b7d70c6 BD |
3690 | int ep; |
3691 | ||
7e804650 | 3692 | daint &= daintmsk; |
47a1685f DN |
3693 | daint_out = daint >> DAINT_OUTEP_SHIFT; |
3694 | daint_in = daint & ~(daint_out << DAINT_OUTEP_SHIFT); | |
7e804650 | 3695 | |
5b7d70c6 BD |
3696 | dev_dbg(hsotg->dev, "%s: daint=%08x\n", __func__, daint); |
3697 | ||
cec87f1d MYK |
3698 | for (ep = 0; ep < hsotg->num_of_eps && daint_out; |
3699 | ep++, daint_out >>= 1) { | |
5b7d70c6 | 3700 | if (daint_out & 1) |
1f91b4cc | 3701 | dwc2_hsotg_epint(hsotg, ep, 0); |
5b7d70c6 BD |
3702 | } |
3703 | ||
cec87f1d MYK |
3704 | for (ep = 0; ep < hsotg->num_of_eps && daint_in; |
3705 | ep++, daint_in >>= 1) { | |
5b7d70c6 | 3706 | if (daint_in & 1) |
1f91b4cc | 3707 | dwc2_hsotg_epint(hsotg, ep, 1); |
5b7d70c6 | 3708 | } |
5b7d70c6 BD |
3709 | } |
3710 | ||
5b7d70c6 BD |
3711 | /* check both FIFOs */ |
3712 | ||
47a1685f | 3713 | if (gintsts & GINTSTS_NPTXFEMP) { |
5b7d70c6 BD |
3714 | dev_dbg(hsotg->dev, "NPTxFEmp\n"); |
3715 | ||
8b9bc460 LM |
3716 | /* |
3717 | * Disable the interrupt to stop it happening again | |
5b7d70c6 | 3718 | * unless one of these endpoint routines decides that |
8b9bc460 LM |
3719 | * it needs re-enabling |
3720 | */ | |
5b7d70c6 | 3721 | |
1f91b4cc FB |
3722 | dwc2_hsotg_disable_gsint(hsotg, GINTSTS_NPTXFEMP); |
3723 | dwc2_hsotg_irq_fifoempty(hsotg, false); | |
5b7d70c6 BD |
3724 | } |
3725 | ||
47a1685f | 3726 | if (gintsts & GINTSTS_PTXFEMP) { |
5b7d70c6 BD |
3727 | dev_dbg(hsotg->dev, "PTxFEmp\n"); |
3728 | ||
94cb8fd6 | 3729 | /* See note in GINTSTS_NPTxFEmp */ |
5b7d70c6 | 3730 | |
1f91b4cc FB |
3731 | dwc2_hsotg_disable_gsint(hsotg, GINTSTS_PTXFEMP); |
3732 | dwc2_hsotg_irq_fifoempty(hsotg, true); | |
5b7d70c6 BD |
3733 | } |
3734 | ||
47a1685f | 3735 | if (gintsts & GINTSTS_RXFLVL) { |
8b9bc460 LM |
3736 | /* |
3737 | * note, since GINTSTS_RxFLvl doubles as FIFO-not-empty, | |
1f91b4cc | 3738 | * we need to retry dwc2_hsotg_handle_rx if this is still |
8b9bc460 LM |
3739 | * set. |
3740 | */ | |
5b7d70c6 | 3741 | |
1f91b4cc | 3742 | dwc2_hsotg_handle_rx(hsotg); |
5b7d70c6 BD |
3743 | } |
3744 | ||
47a1685f | 3745 | if (gintsts & GINTSTS_ERLYSUSP) { |
94cb8fd6 | 3746 | dev_dbg(hsotg->dev, "GINTSTS_ErlySusp\n"); |
f25c42b8 | 3747 | dwc2_writel(hsotg, GINTSTS_ERLYSUSP, GINTSTS); |
5b7d70c6 BD |
3748 | } |
3749 | ||
8b9bc460 LM |
3750 | /* |
3751 | * these next two seem to crop-up occasionally causing the core | |
5b7d70c6 | 3752 | * to shutdown the USB transfer, so try clearing them and logging |
8b9bc460 LM |
3753 | * the occurrence. |
3754 | */ | |
5b7d70c6 | 3755 | |
47a1685f | 3756 | if (gintsts & GINTSTS_GOUTNAKEFF) { |
837e9f00 VM |
3757 | u8 idx; |
3758 | u32 epctrl; | |
3759 | u32 gintmsk; | |
d8484552 | 3760 | u32 daintmsk; |
837e9f00 VM |
3761 | struct dwc2_hsotg_ep *hs_ep; |
3762 | ||
f25c42b8 | 3763 | daintmsk = dwc2_readl(hsotg, DAINTMSK); |
d8484552 | 3764 | daintmsk >>= DAINT_OUTEP_SHIFT; |
837e9f00 | 3765 | /* Mask this interrupt */ |
f25c42b8 | 3766 | gintmsk = dwc2_readl(hsotg, GINTMSK); |
837e9f00 | 3767 | gintmsk &= ~GINTSTS_GOUTNAKEFF; |
f25c42b8 | 3768 | dwc2_writel(hsotg, gintmsk, GINTMSK); |
837e9f00 VM |
3769 | |
3770 | dev_dbg(hsotg->dev, "GOUTNakEff triggered\n"); | |
d5d5f079 | 3771 | for (idx = 1; idx < hsotg->num_of_eps; idx++) { |
837e9f00 | 3772 | hs_ep = hsotg->eps_out[idx]; |
d8484552 | 3773 | /* Proceed only unmasked ISOC EPs */ |
89066b36 | 3774 | if ((BIT(idx) & ~daintmsk) || !hs_ep->isochronous) |
d8484552 RK |
3775 | continue; |
3776 | ||
f25c42b8 | 3777 | epctrl = dwc2_readl(hsotg, DOEPCTL(idx)); |
837e9f00 | 3778 | |
d8484552 | 3779 | if (epctrl & DXEPCTL_EPENA) { |
837e9f00 VM |
3780 | epctrl |= DXEPCTL_SNAK; |
3781 | epctrl |= DXEPCTL_EPDIS; | |
f25c42b8 | 3782 | dwc2_writel(hsotg, epctrl, DOEPCTL(idx)); |
837e9f00 VM |
3783 | } |
3784 | } | |
a3395f0d | 3785 | |
837e9f00 | 3786 | /* This interrupt bit is cleared in DXEPINT_EPDISBLD handler */ |
5b7d70c6 BD |
3787 | } |
3788 | ||
47a1685f | 3789 | if (gintsts & GINTSTS_GINNAKEFF) { |
5b7d70c6 BD |
3790 | dev_info(hsotg->dev, "GINNakEff triggered\n"); |
3791 | ||
f25c42b8 | 3792 | dwc2_set_bit(hsotg, DCTL, DCTL_CGNPINNAK); |
a3395f0d | 3793 | |
1f91b4cc | 3794 | dwc2_hsotg_dump(hsotg); |
5b7d70c6 BD |
3795 | } |
3796 | ||
381fc8f8 VM |
3797 | if (gintsts & GINTSTS_INCOMPL_SOIN) |
3798 | dwc2_gadget_handle_incomplete_isoc_in(hsotg); | |
ec1f9d9f | 3799 | |
381fc8f8 VM |
3800 | if (gintsts & GINTSTS_INCOMPL_SOOUT) |
3801 | dwc2_gadget_handle_incomplete_isoc_out(hsotg); | |
ec1f9d9f | 3802 | |
8b9bc460 LM |
3803 | /* |
3804 | * if we've had fifo events, we should try and go around the | |
3805 | * loop again to see if there's any point in returning yet. | |
3806 | */ | |
5b7d70c6 BD |
3807 | |
3808 | if (gintsts & IRQ_RETRY_MASK && --retry_count > 0) | |
77b6200e | 3809 | goto irq_retry; |
5b7d70c6 | 3810 | |
187c5298 GT |
3811 | /* Check WKUP_ALERT interrupt*/ |
3812 | if (hsotg->params.service_interval) | |
3813 | dwc2_gadget_wkup_alert_handler(hsotg); | |
3814 | ||
5ad1d316 LM |
3815 | spin_unlock(&hsotg->lock); |
3816 | ||
5b7d70c6 BD |
3817 | return IRQ_HANDLED; |
3818 | } | |
3819 | ||
a4f82771 VA |
3820 | static void dwc2_hsotg_ep_stop_xfr(struct dwc2_hsotg *hsotg, |
3821 | struct dwc2_hsotg_ep *hs_ep) | |
3822 | { | |
3823 | u32 epctrl_reg; | |
3824 | u32 epint_reg; | |
3825 | ||
3826 | epctrl_reg = hs_ep->dir_in ? DIEPCTL(hs_ep->index) : | |
3827 | DOEPCTL(hs_ep->index); | |
3828 | epint_reg = hs_ep->dir_in ? DIEPINT(hs_ep->index) : | |
3829 | DOEPINT(hs_ep->index); | |
3830 | ||
3831 | dev_dbg(hsotg->dev, "%s: stopping transfer on %s\n", __func__, | |
3832 | hs_ep->name); | |
3833 | ||
3834 | if (hs_ep->dir_in) { | |
3835 | if (hsotg->dedicated_fifos || hs_ep->periodic) { | |
f25c42b8 | 3836 | dwc2_set_bit(hsotg, epctrl_reg, DXEPCTL_SNAK); |
a4f82771 VA |
3837 | /* Wait for Nak effect */ |
3838 | if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg, | |
3839 | DXEPINT_INEPNAKEFF, 100)) | |
3840 | dev_warn(hsotg->dev, | |
3841 | "%s: timeout DIEPINT.NAKEFF\n", | |
3842 | __func__); | |
3843 | } else { | |
f25c42b8 | 3844 | dwc2_set_bit(hsotg, DCTL, DCTL_SGNPINNAK); |
a4f82771 VA |
3845 | /* Wait for Nak effect */ |
3846 | if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS, | |
3847 | GINTSTS_GINNAKEFF, 100)) | |
3848 | dev_warn(hsotg->dev, | |
3849 | "%s: timeout GINTSTS.GINNAKEFF\n", | |
3850 | __func__); | |
3851 | } | |
3852 | } else { | |
f25c42b8 GS |
3853 | if (!(dwc2_readl(hsotg, GINTSTS) & GINTSTS_GOUTNAKEFF)) |
3854 | dwc2_set_bit(hsotg, DCTL, DCTL_SGOUTNAK); | |
a4f82771 VA |
3855 | |
3856 | /* Wait for global nak to take effect */ | |
3857 | if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS, | |
3858 | GINTSTS_GOUTNAKEFF, 100)) | |
3859 | dev_warn(hsotg->dev, "%s: timeout GINTSTS.GOUTNAKEFF\n", | |
3860 | __func__); | |
3861 | } | |
3862 | ||
3863 | /* Disable ep */ | |
f25c42b8 | 3864 | dwc2_set_bit(hsotg, epctrl_reg, DXEPCTL_EPDIS | DXEPCTL_SNAK); |
a4f82771 VA |
3865 | |
3866 | /* Wait for ep to be disabled */ | |
3867 | if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg, DXEPINT_EPDISBLD, 100)) | |
3868 | dev_warn(hsotg->dev, | |
3869 | "%s: timeout DOEPCTL.EPDisable\n", __func__); | |
3870 | ||
3871 | /* Clear EPDISBLD interrupt */ | |
f25c42b8 | 3872 | dwc2_set_bit(hsotg, epint_reg, DXEPINT_EPDISBLD); |
a4f82771 VA |
3873 | |
3874 | if (hs_ep->dir_in) { | |
3875 | unsigned short fifo_index; | |
3876 | ||
3877 | if (hsotg->dedicated_fifos || hs_ep->periodic) | |
3878 | fifo_index = hs_ep->fifo_index; | |
3879 | else | |
3880 | fifo_index = 0; | |
3881 | ||
3882 | /* Flush TX FIFO */ | |
3883 | dwc2_flush_tx_fifo(hsotg, fifo_index); | |
3884 | ||
3885 | /* Clear Global In NP NAK in Shared FIFO for non periodic ep */ | |
3886 | if (!hsotg->dedicated_fifos && !hs_ep->periodic) | |
f25c42b8 | 3887 | dwc2_set_bit(hsotg, DCTL, DCTL_CGNPINNAK); |
a4f82771 VA |
3888 | |
3889 | } else { | |
3890 | /* Remove global NAKs */ | |
f25c42b8 | 3891 | dwc2_set_bit(hsotg, DCTL, DCTL_CGOUTNAK); |
a4f82771 VA |
3892 | } |
3893 | } | |
3894 | ||
5b7d70c6 | 3895 | /** |
1f91b4cc | 3896 | * dwc2_hsotg_ep_enable - enable the given endpoint |
5b7d70c6 BD |
3897 | * @ep: The USB endpint to configure |
3898 | * @desc: The USB endpoint descriptor to configure with. | |
3899 | * | |
3900 | * This is called from the USB gadget code's usb_ep_enable(). | |
8b9bc460 | 3901 | */ |
1f91b4cc | 3902 | static int dwc2_hsotg_ep_enable(struct usb_ep *ep, |
9da51974 | 3903 | const struct usb_endpoint_descriptor *desc) |
5b7d70c6 | 3904 | { |
1f91b4cc | 3905 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 3906 | struct dwc2_hsotg *hsotg = hs_ep->parent; |
5b7d70c6 | 3907 | unsigned long flags; |
ca4c55ad | 3908 | unsigned int index = hs_ep->index; |
5b7d70c6 BD |
3909 | u32 epctrl_reg; |
3910 | u32 epctrl; | |
3911 | u32 mps; | |
ee2c40de | 3912 | u32 mc; |
837e9f00 | 3913 | u32 mask; |
ca4c55ad MYK |
3914 | unsigned int dir_in; |
3915 | unsigned int i, val, size; | |
19c190f9 | 3916 | int ret = 0; |
729cac69 | 3917 | unsigned char ep_type; |
5b7d70c6 BD |
3918 | |
3919 | dev_dbg(hsotg->dev, | |
3920 | "%s: ep %s: a 0x%02x, attr 0x%02x, mps 0x%04x, intr %d\n", | |
3921 | __func__, ep->name, desc->bEndpointAddress, desc->bmAttributes, | |
3922 | desc->wMaxPacketSize, desc->bInterval); | |
3923 | ||
3924 | /* not to be called for EP0 */ | |
8c3d6092 VA |
3925 | if (index == 0) { |
3926 | dev_err(hsotg->dev, "%s: called for EP 0\n", __func__); | |
3927 | return -EINVAL; | |
3928 | } | |
5b7d70c6 BD |
3929 | |
3930 | dir_in = (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) ? 1 : 0; | |
3931 | if (dir_in != hs_ep->dir_in) { | |
3932 | dev_err(hsotg->dev, "%s: direction mismatch!\n", __func__); | |
3933 | return -EINVAL; | |
3934 | } | |
3935 | ||
729cac69 | 3936 | ep_type = desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK; |
29cc8897 | 3937 | mps = usb_endpoint_maxp(desc); |
ee2c40de | 3938 | mc = usb_endpoint_maxp_mult(desc); |
5b7d70c6 | 3939 | |
729cac69 MH |
3940 | /* ISOC IN in DDMA supported bInterval up to 10 */ |
3941 | if (using_desc_dma(hsotg) && ep_type == USB_ENDPOINT_XFER_ISOC && | |
3942 | dir_in && desc->bInterval > 10) { | |
3943 | dev_err(hsotg->dev, | |
3944 | "%s: ISOC IN, DDMA: bInterval>10 not supported!\n", __func__); | |
3945 | return -EINVAL; | |
3946 | } | |
3947 | ||
3948 | /* High bandwidth ISOC OUT in DDMA not supported */ | |
3949 | if (using_desc_dma(hsotg) && ep_type == USB_ENDPOINT_XFER_ISOC && | |
3950 | !dir_in && mc > 1) { | |
3951 | dev_err(hsotg->dev, | |
3952 | "%s: ISOC OUT, DDMA: HB not supported!\n", __func__); | |
3953 | return -EINVAL; | |
3954 | } | |
3955 | ||
1f91b4cc | 3956 | /* note, we handle this here instead of dwc2_hsotg_set_ep_maxpacket */ |
5b7d70c6 | 3957 | |
94cb8fd6 | 3958 | epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index); |
f25c42b8 | 3959 | epctrl = dwc2_readl(hsotg, epctrl_reg); |
5b7d70c6 BD |
3960 | |
3961 | dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x from 0x%08x\n", | |
3962 | __func__, epctrl, epctrl_reg); | |
3963 | ||
5f54c54b | 3964 | /* Allocate DMA descriptor chain for non-ctrl endpoints */ |
9383e084 VM |
3965 | if (using_desc_dma(hsotg) && !hs_ep->desc_list) { |
3966 | hs_ep->desc_list = dmam_alloc_coherent(hsotg->dev, | |
5f54c54b VA |
3967 | MAX_DMA_DESC_NUM_GENERIC * |
3968 | sizeof(struct dwc2_dma_desc), | |
86e881e7 | 3969 | &hs_ep->desc_list_dma, GFP_ATOMIC); |
5f54c54b VA |
3970 | if (!hs_ep->desc_list) { |
3971 | ret = -ENOMEM; | |
3972 | goto error2; | |
3973 | } | |
3974 | } | |
3975 | ||
22258f49 | 3976 | spin_lock_irqsave(&hsotg->lock, flags); |
5b7d70c6 | 3977 | |
47a1685f DN |
3978 | epctrl &= ~(DXEPCTL_EPTYPE_MASK | DXEPCTL_MPS_MASK); |
3979 | epctrl |= DXEPCTL_MPS(mps); | |
5b7d70c6 | 3980 | |
8b9bc460 LM |
3981 | /* |
3982 | * mark the endpoint as active, otherwise the core may ignore | |
3983 | * transactions entirely for this endpoint | |
3984 | */ | |
47a1685f | 3985 | epctrl |= DXEPCTL_USBACTEP; |
5b7d70c6 | 3986 | |
5b7d70c6 | 3987 | /* update the endpoint state */ |
ee2c40de | 3988 | dwc2_hsotg_set_ep_maxpacket(hsotg, hs_ep->index, mps, mc, dir_in); |
5b7d70c6 BD |
3989 | |
3990 | /* default, set to non-periodic */ | |
1479e841 | 3991 | hs_ep->isochronous = 0; |
5b7d70c6 | 3992 | hs_ep->periodic = 0; |
a18ed7b0 | 3993 | hs_ep->halted = 0; |
1479e841 | 3994 | hs_ep->interval = desc->bInterval; |
4fca54aa | 3995 | |
729cac69 | 3996 | switch (ep_type) { |
5b7d70c6 | 3997 | case USB_ENDPOINT_XFER_ISOC: |
47a1685f DN |
3998 | epctrl |= DXEPCTL_EPTYPE_ISO; |
3999 | epctrl |= DXEPCTL_SETEVENFR; | |
1479e841 | 4000 | hs_ep->isochronous = 1; |
142bd33f | 4001 | hs_ep->interval = 1 << (desc->bInterval - 1); |
837e9f00 | 4002 | hs_ep->target_frame = TARGET_FRAME_INITIAL; |
ab7d2192 | 4003 | hs_ep->next_desc = 0; |
729cac69 | 4004 | hs_ep->compl_desc = 0; |
837e9f00 | 4005 | if (dir_in) { |
1479e841 | 4006 | hs_ep->periodic = 1; |
f25c42b8 | 4007 | mask = dwc2_readl(hsotg, DIEPMSK); |
837e9f00 | 4008 | mask |= DIEPMSK_NAKMSK; |
f25c42b8 | 4009 | dwc2_writel(hsotg, mask, DIEPMSK); |
837e9f00 | 4010 | } else { |
f25c42b8 | 4011 | mask = dwc2_readl(hsotg, DOEPMSK); |
837e9f00 | 4012 | mask |= DOEPMSK_OUTTKNEPDISMSK; |
f25c42b8 | 4013 | dwc2_writel(hsotg, mask, DOEPMSK); |
837e9f00 | 4014 | } |
1479e841 | 4015 | break; |
5b7d70c6 BD |
4016 | |
4017 | case USB_ENDPOINT_XFER_BULK: | |
47a1685f | 4018 | epctrl |= DXEPCTL_EPTYPE_BULK; |
5b7d70c6 BD |
4019 | break; |
4020 | ||
4021 | case USB_ENDPOINT_XFER_INT: | |
b203d0a2 | 4022 | if (dir_in) |
5b7d70c6 | 4023 | hs_ep->periodic = 1; |
5b7d70c6 | 4024 | |
142bd33f VM |
4025 | if (hsotg->gadget.speed == USB_SPEED_HIGH) |
4026 | hs_ep->interval = 1 << (desc->bInterval - 1); | |
4027 | ||
47a1685f | 4028 | epctrl |= DXEPCTL_EPTYPE_INTERRUPT; |
5b7d70c6 BD |
4029 | break; |
4030 | ||
4031 | case USB_ENDPOINT_XFER_CONTROL: | |
47a1685f | 4032 | epctrl |= DXEPCTL_EPTYPE_CONTROL; |
5b7d70c6 BD |
4033 | break; |
4034 | } | |
4035 | ||
8b9bc460 LM |
4036 | /* |
4037 | * if the hardware has dedicated fifos, we must give each IN EP | |
10aebc77 BD |
4038 | * a unique tx-fifo even if it is non-periodic. |
4039 | */ | |
21f3bb52 | 4040 | if (dir_in && hsotg->dedicated_fifos) { |
ca4c55ad MYK |
4041 | u32 fifo_index = 0; |
4042 | u32 fifo_size = UINT_MAX; | |
9da51974 JY |
4043 | |
4044 | size = hs_ep->ep.maxpacket * hs_ep->mc; | |
5f2196bd | 4045 | for (i = 1; i < hsotg->num_of_eps; ++i) { |
9da51974 | 4046 | if (hsotg->fifo_map & (1 << i)) |
b203d0a2 | 4047 | continue; |
f25c42b8 | 4048 | val = dwc2_readl(hsotg, DPTXFSIZN(i)); |
9da51974 | 4049 | val = (val >> FIFOSIZE_DEPTH_SHIFT) * 4; |
b203d0a2 RB |
4050 | if (val < size) |
4051 | continue; | |
ca4c55ad MYK |
4052 | /* Search for smallest acceptable fifo */ |
4053 | if (val < fifo_size) { | |
4054 | fifo_size = val; | |
4055 | fifo_index = i; | |
4056 | } | |
b203d0a2 | 4057 | } |
ca4c55ad | 4058 | if (!fifo_index) { |
5f2196bd MYK |
4059 | dev_err(hsotg->dev, |
4060 | "%s: No suitable fifo found\n", __func__); | |
b585a48b | 4061 | ret = -ENOMEM; |
5f54c54b | 4062 | goto error1; |
b585a48b | 4063 | } |
97311c8f | 4064 | epctrl &= ~(DXEPCTL_TXFNUM_LIMIT << DXEPCTL_TXFNUM_SHIFT); |
ca4c55ad MYK |
4065 | hsotg->fifo_map |= 1 << fifo_index; |
4066 | epctrl |= DXEPCTL_TXFNUM(fifo_index); | |
4067 | hs_ep->fifo_index = fifo_index; | |
4068 | hs_ep->fifo_size = fifo_size; | |
b203d0a2 | 4069 | } |
10aebc77 | 4070 | |
5b7d70c6 | 4071 | /* for non control endpoints, set PID to D0 */ |
837e9f00 | 4072 | if (index && !hs_ep->isochronous) |
47a1685f | 4073 | epctrl |= DXEPCTL_SETD0PID; |
5b7d70c6 | 4074 | |
5295322a AP |
4075 | /* WA for Full speed ISOC IN in DDMA mode. |
4076 | * By Clear NAK status of EP, core will send ZLP | |
4077 | * to IN token and assert NAK interrupt relying | |
4078 | * on TxFIFO status only | |
4079 | */ | |
4080 | ||
4081 | if (hsotg->gadget.speed == USB_SPEED_FULL && | |
4082 | hs_ep->isochronous && dir_in) { | |
4083 | /* The WA applies only to core versions from 2.72a | |
4084 | * to 4.00a (including both). Also for FS_IOT_1.00a | |
4085 | * and HS_IOT_1.00a. | |
4086 | */ | |
f25c42b8 | 4087 | u32 gsnpsid = dwc2_readl(hsotg, GSNPSID); |
5295322a AP |
4088 | |
4089 | if ((gsnpsid >= DWC2_CORE_REV_2_72a && | |
4090 | gsnpsid <= DWC2_CORE_REV_4_00a) || | |
4091 | gsnpsid == DWC2_FS_IOT_REV_1_00a || | |
4092 | gsnpsid == DWC2_HS_IOT_REV_1_00a) | |
4093 | epctrl |= DXEPCTL_CNAK; | |
4094 | } | |
4095 | ||
5b7d70c6 BD |
4096 | dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n", |
4097 | __func__, epctrl); | |
4098 | ||
f25c42b8 | 4099 | dwc2_writel(hsotg, epctrl, epctrl_reg); |
5b7d70c6 | 4100 | dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x\n", |
f25c42b8 | 4101 | __func__, dwc2_readl(hsotg, epctrl_reg)); |
5b7d70c6 BD |
4102 | |
4103 | /* enable the endpoint interrupt */ | |
1f91b4cc | 4104 | dwc2_hsotg_ctrl_epint(hsotg, index, dir_in, 1); |
5b7d70c6 | 4105 | |
5f54c54b | 4106 | error1: |
22258f49 | 4107 | spin_unlock_irqrestore(&hsotg->lock, flags); |
5f54c54b VA |
4108 | |
4109 | error2: | |
4110 | if (ret && using_desc_dma(hsotg) && hs_ep->desc_list) { | |
9383e084 | 4111 | dmam_free_coherent(hsotg->dev, MAX_DMA_DESC_NUM_GENERIC * |
5f54c54b VA |
4112 | sizeof(struct dwc2_dma_desc), |
4113 | hs_ep->desc_list, hs_ep->desc_list_dma); | |
4114 | hs_ep->desc_list = NULL; | |
4115 | } | |
4116 | ||
19c190f9 | 4117 | return ret; |
5b7d70c6 BD |
4118 | } |
4119 | ||
8b9bc460 | 4120 | /** |
1f91b4cc | 4121 | * dwc2_hsotg_ep_disable - disable given endpoint |
8b9bc460 LM |
4122 | * @ep: The endpoint to disable. |
4123 | */ | |
1f91b4cc | 4124 | static int dwc2_hsotg_ep_disable(struct usb_ep *ep) |
5b7d70c6 | 4125 | { |
1f91b4cc | 4126 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 4127 | struct dwc2_hsotg *hsotg = hs_ep->parent; |
5b7d70c6 BD |
4128 | int dir_in = hs_ep->dir_in; |
4129 | int index = hs_ep->index; | |
5b7d70c6 BD |
4130 | u32 epctrl_reg; |
4131 | u32 ctrl; | |
4132 | ||
1e011293 | 4133 | dev_dbg(hsotg->dev, "%s(ep %p)\n", __func__, ep); |
5b7d70c6 | 4134 | |
c6f5c050 | 4135 | if (ep == &hsotg->eps_out[0]->ep) { |
5b7d70c6 BD |
4136 | dev_err(hsotg->dev, "%s: called for ep0\n", __func__); |
4137 | return -EINVAL; | |
9b481092 JS |
4138 | } |
4139 | ||
4140 | if (hsotg->op_state != OTG_STATE_B_PERIPHERAL) { | |
4141 | dev_err(hsotg->dev, "%s: called in host mode?\n", __func__); | |
4142 | return -EINVAL; | |
5b7d70c6 BD |
4143 | } |
4144 | ||
94cb8fd6 | 4145 | epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index); |
5b7d70c6 | 4146 | |
f25c42b8 | 4147 | ctrl = dwc2_readl(hsotg, epctrl_reg); |
a4f82771 VA |
4148 | |
4149 | if (ctrl & DXEPCTL_EPENA) | |
4150 | dwc2_hsotg_ep_stop_xfr(hsotg, hs_ep); | |
4151 | ||
47a1685f DN |
4152 | ctrl &= ~DXEPCTL_EPENA; |
4153 | ctrl &= ~DXEPCTL_USBACTEP; | |
4154 | ctrl |= DXEPCTL_SNAK; | |
5b7d70c6 BD |
4155 | |
4156 | dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl); | |
f25c42b8 | 4157 | dwc2_writel(hsotg, ctrl, epctrl_reg); |
5b7d70c6 BD |
4158 | |
4159 | /* disable endpoint interrupts */ | |
1f91b4cc | 4160 | dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 0); |
5b7d70c6 | 4161 | |
1141ea01 MYK |
4162 | /* terminate all requests with shutdown */ |
4163 | kill_all_requests(hsotg, hs_ep, -ESHUTDOWN); | |
4164 | ||
1c07b20e RB |
4165 | hsotg->fifo_map &= ~(1 << hs_ep->fifo_index); |
4166 | hs_ep->fifo_index = 0; | |
4167 | hs_ep->fifo_size = 0; | |
4168 | ||
5b7d70c6 BD |
4169 | return 0; |
4170 | } | |
4171 | ||
4fe4f9fe MH |
4172 | static int dwc2_hsotg_ep_disable_lock(struct usb_ep *ep) |
4173 | { | |
4174 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); | |
4175 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
4176 | unsigned long flags; | |
4177 | int ret; | |
4178 | ||
4179 | spin_lock_irqsave(&hsotg->lock, flags); | |
4180 | ret = dwc2_hsotg_ep_disable(ep); | |
4181 | spin_unlock_irqrestore(&hsotg->lock, flags); | |
4182 | return ret; | |
4183 | } | |
4184 | ||
5b7d70c6 BD |
4185 | /** |
4186 | * on_list - check request is on the given endpoint | |
4187 | * @ep: The endpoint to check. | |
4188 | * @test: The request to test if it is on the endpoint. | |
8b9bc460 | 4189 | */ |
1f91b4cc | 4190 | static bool on_list(struct dwc2_hsotg_ep *ep, struct dwc2_hsotg_req *test) |
5b7d70c6 | 4191 | { |
1f91b4cc | 4192 | struct dwc2_hsotg_req *req, *treq; |
5b7d70c6 BD |
4193 | |
4194 | list_for_each_entry_safe(req, treq, &ep->queue, queue) { | |
4195 | if (req == test) | |
4196 | return true; | |
4197 | } | |
4198 | ||
4199 | return false; | |
4200 | } | |
4201 | ||
8b9bc460 | 4202 | /** |
1f91b4cc | 4203 | * dwc2_hsotg_ep_dequeue - dequeue given endpoint |
8b9bc460 LM |
4204 | * @ep: The endpoint to dequeue. |
4205 | * @req: The request to be removed from a queue. | |
4206 | */ | |
1f91b4cc | 4207 | static int dwc2_hsotg_ep_dequeue(struct usb_ep *ep, struct usb_request *req) |
5b7d70c6 | 4208 | { |
1f91b4cc FB |
4209 | struct dwc2_hsotg_req *hs_req = our_req(req); |
4210 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); | |
941fcce4 | 4211 | struct dwc2_hsotg *hs = hs_ep->parent; |
5b7d70c6 BD |
4212 | unsigned long flags; |
4213 | ||
1e011293 | 4214 | dev_dbg(hs->dev, "ep_dequeue(%p,%p)\n", ep, req); |
5b7d70c6 | 4215 | |
22258f49 | 4216 | spin_lock_irqsave(&hs->lock, flags); |
5b7d70c6 BD |
4217 | |
4218 | if (!on_list(hs_ep, hs_req)) { | |
22258f49 | 4219 | spin_unlock_irqrestore(&hs->lock, flags); |
5b7d70c6 BD |
4220 | return -EINVAL; |
4221 | } | |
4222 | ||
c524dd5f MYK |
4223 | /* Dequeue already started request */ |
4224 | if (req == &hs_ep->req->req) | |
4225 | dwc2_hsotg_ep_stop_xfr(hs, hs_ep); | |
4226 | ||
1f91b4cc | 4227 | dwc2_hsotg_complete_request(hs, hs_ep, hs_req, -ECONNRESET); |
22258f49 | 4228 | spin_unlock_irqrestore(&hs->lock, flags); |
5b7d70c6 BD |
4229 | |
4230 | return 0; | |
4231 | } | |
4232 | ||
8b9bc460 | 4233 | /** |
1f91b4cc | 4234 | * dwc2_hsotg_ep_sethalt - set halt on a given endpoint |
8b9bc460 LM |
4235 | * @ep: The endpoint to set halt. |
4236 | * @value: Set or unset the halt. | |
51da43b5 VA |
4237 | * @now: If true, stall the endpoint now. Otherwise return -EAGAIN if |
4238 | * the endpoint is busy processing requests. | |
4239 | * | |
4240 | * We need to stall the endpoint immediately if request comes from set_feature | |
4241 | * protocol command handler. | |
8b9bc460 | 4242 | */ |
51da43b5 | 4243 | static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now) |
5b7d70c6 | 4244 | { |
1f91b4cc | 4245 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 4246 | struct dwc2_hsotg *hs = hs_ep->parent; |
5b7d70c6 | 4247 | int index = hs_ep->index; |
5b7d70c6 BD |
4248 | u32 epreg; |
4249 | u32 epctl; | |
9c39ddc6 | 4250 | u32 xfertype; |
5b7d70c6 BD |
4251 | |
4252 | dev_info(hs->dev, "%s(ep %p %s, %d)\n", __func__, ep, ep->name, value); | |
4253 | ||
c9f721b2 RB |
4254 | if (index == 0) { |
4255 | if (value) | |
1f91b4cc | 4256 | dwc2_hsotg_stall_ep0(hs); |
c9f721b2 RB |
4257 | else |
4258 | dev_warn(hs->dev, | |
4259 | "%s: can't clear halt on ep0\n", __func__); | |
4260 | return 0; | |
4261 | } | |
4262 | ||
15186f10 VA |
4263 | if (hs_ep->isochronous) { |
4264 | dev_err(hs->dev, "%s is Isochronous Endpoint\n", ep->name); | |
4265 | return -EINVAL; | |
4266 | } | |
4267 | ||
51da43b5 VA |
4268 | if (!now && value && !list_empty(&hs_ep->queue)) { |
4269 | dev_dbg(hs->dev, "%s request is pending, cannot halt\n", | |
4270 | ep->name); | |
4271 | return -EAGAIN; | |
4272 | } | |
4273 | ||
c6f5c050 MYK |
4274 | if (hs_ep->dir_in) { |
4275 | epreg = DIEPCTL(index); | |
f25c42b8 | 4276 | epctl = dwc2_readl(hs, epreg); |
c6f5c050 MYK |
4277 | |
4278 | if (value) { | |
5a350d53 | 4279 | epctl |= DXEPCTL_STALL | DXEPCTL_SNAK; |
c6f5c050 MYK |
4280 | if (epctl & DXEPCTL_EPENA) |
4281 | epctl |= DXEPCTL_EPDIS; | |
4282 | } else { | |
4283 | epctl &= ~DXEPCTL_STALL; | |
4284 | xfertype = epctl & DXEPCTL_EPTYPE_MASK; | |
4285 | if (xfertype == DXEPCTL_EPTYPE_BULK || | |
9da51974 | 4286 | xfertype == DXEPCTL_EPTYPE_INTERRUPT) |
77b6200e | 4287 | epctl |= DXEPCTL_SETD0PID; |
c6f5c050 | 4288 | } |
f25c42b8 | 4289 | dwc2_writel(hs, epctl, epreg); |
9c39ddc6 | 4290 | } else { |
c6f5c050 | 4291 | epreg = DOEPCTL(index); |
f25c42b8 | 4292 | epctl = dwc2_readl(hs, epreg); |
5b7d70c6 | 4293 | |
34c0887f | 4294 | if (value) { |
c6f5c050 | 4295 | epctl |= DXEPCTL_STALL; |
34c0887f | 4296 | } else { |
c6f5c050 MYK |
4297 | epctl &= ~DXEPCTL_STALL; |
4298 | xfertype = epctl & DXEPCTL_EPTYPE_MASK; | |
4299 | if (xfertype == DXEPCTL_EPTYPE_BULK || | |
9da51974 | 4300 | xfertype == DXEPCTL_EPTYPE_INTERRUPT) |
77b6200e | 4301 | epctl |= DXEPCTL_SETD0PID; |
c6f5c050 | 4302 | } |
f25c42b8 | 4303 | dwc2_writel(hs, epctl, epreg); |
9c39ddc6 | 4304 | } |
5b7d70c6 | 4305 | |
a18ed7b0 RB |
4306 | hs_ep->halted = value; |
4307 | ||
5b7d70c6 BD |
4308 | return 0; |
4309 | } | |
4310 | ||
5ad1d316 | 4311 | /** |
1f91b4cc | 4312 | * dwc2_hsotg_ep_sethalt_lock - set halt on a given endpoint with lock held |
5ad1d316 LM |
4313 | * @ep: The endpoint to set halt. |
4314 | * @value: Set or unset the halt. | |
4315 | */ | |
1f91b4cc | 4316 | static int dwc2_hsotg_ep_sethalt_lock(struct usb_ep *ep, int value) |
5ad1d316 | 4317 | { |
1f91b4cc | 4318 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 4319 | struct dwc2_hsotg *hs = hs_ep->parent; |
5ad1d316 LM |
4320 | unsigned long flags = 0; |
4321 | int ret = 0; | |
4322 | ||
4323 | spin_lock_irqsave(&hs->lock, flags); | |
51da43b5 | 4324 | ret = dwc2_hsotg_ep_sethalt(ep, value, false); |
5ad1d316 LM |
4325 | spin_unlock_irqrestore(&hs->lock, flags); |
4326 | ||
4327 | return ret; | |
4328 | } | |
4329 | ||
ebce561a | 4330 | static const struct usb_ep_ops dwc2_hsotg_ep_ops = { |
1f91b4cc | 4331 | .enable = dwc2_hsotg_ep_enable, |
4fe4f9fe | 4332 | .disable = dwc2_hsotg_ep_disable_lock, |
1f91b4cc FB |
4333 | .alloc_request = dwc2_hsotg_ep_alloc_request, |
4334 | .free_request = dwc2_hsotg_ep_free_request, | |
4335 | .queue = dwc2_hsotg_ep_queue_lock, | |
4336 | .dequeue = dwc2_hsotg_ep_dequeue, | |
4337 | .set_halt = dwc2_hsotg_ep_sethalt_lock, | |
25985edc | 4338 | /* note, don't believe we have any call for the fifo routines */ |
5b7d70c6 BD |
4339 | }; |
4340 | ||
8b9bc460 | 4341 | /** |
9da51974 | 4342 | * dwc2_hsotg_init - initialize the usb core |
8b9bc460 LM |
4343 | * @hsotg: The driver state |
4344 | */ | |
1f91b4cc | 4345 | static void dwc2_hsotg_init(struct dwc2_hsotg *hsotg) |
b3f489b2 LM |
4346 | { |
4347 | /* unmask subset of endpoint interrupts */ | |
4348 | ||
f25c42b8 | 4349 | dwc2_writel(hsotg, DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK | |
95c8bc36 | 4350 | DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK, |
f25c42b8 | 4351 | DIEPMSK); |
b3f489b2 | 4352 | |
f25c42b8 | 4353 | dwc2_writel(hsotg, DOEPMSK_SETUPMSK | DOEPMSK_AHBERRMSK | |
95c8bc36 | 4354 | DOEPMSK_EPDISBLDMSK | DOEPMSK_XFERCOMPLMSK, |
f25c42b8 | 4355 | DOEPMSK); |
b3f489b2 | 4356 | |
f25c42b8 | 4357 | dwc2_writel(hsotg, 0, DAINTMSK); |
b3f489b2 LM |
4358 | |
4359 | /* Be in disconnected state until gadget is registered */ | |
f25c42b8 | 4360 | dwc2_set_bit(hsotg, DCTL, DCTL_SFTDISCON); |
b3f489b2 | 4361 | |
b3f489b2 LM |
4362 | /* setup fifos */ |
4363 | ||
4364 | dev_dbg(hsotg->dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n", | |
f25c42b8 GS |
4365 | dwc2_readl(hsotg, GRXFSIZ), |
4366 | dwc2_readl(hsotg, GNPTXFSIZ)); | |
b3f489b2 | 4367 | |
1f91b4cc | 4368 | dwc2_hsotg_init_fifo(hsotg); |
b3f489b2 | 4369 | |
f5090044 | 4370 | if (using_dma(hsotg)) |
f25c42b8 | 4371 | dwc2_set_bit(hsotg, GAHBCFG, GAHBCFG_DMA_EN); |
b3f489b2 LM |
4372 | } |
4373 | ||
8b9bc460 | 4374 | /** |
1f91b4cc | 4375 | * dwc2_hsotg_udc_start - prepare the udc for work |
8b9bc460 LM |
4376 | * @gadget: The usb gadget state |
4377 | * @driver: The usb gadget driver | |
4378 | * | |
4379 | * Perform initialization to prepare udc device and driver | |
4380 | * to work. | |
4381 | */ | |
1f91b4cc | 4382 | static int dwc2_hsotg_udc_start(struct usb_gadget *gadget, |
9da51974 | 4383 | struct usb_gadget_driver *driver) |
5b7d70c6 | 4384 | { |
941fcce4 | 4385 | struct dwc2_hsotg *hsotg = to_hsotg(gadget); |
5b9451f8 | 4386 | unsigned long flags; |
5b7d70c6 BD |
4387 | int ret; |
4388 | ||
4389 | if (!hsotg) { | |
a023da33 | 4390 | pr_err("%s: called with no device\n", __func__); |
5b7d70c6 BD |
4391 | return -ENODEV; |
4392 | } | |
4393 | ||
4394 | if (!driver) { | |
4395 | dev_err(hsotg->dev, "%s: no driver\n", __func__); | |
4396 | return -EINVAL; | |
4397 | } | |
4398 | ||
7177aed4 | 4399 | if (driver->max_speed < USB_SPEED_FULL) |
5b7d70c6 | 4400 | dev_err(hsotg->dev, "%s: bad speed\n", __func__); |
5b7d70c6 | 4401 | |
f65f0f10 | 4402 | if (!driver->setup) { |
5b7d70c6 BD |
4403 | dev_err(hsotg->dev, "%s: missing entry points\n", __func__); |
4404 | return -EINVAL; | |
4405 | } | |
4406 | ||
4407 | WARN_ON(hsotg->driver); | |
4408 | ||
4409 | driver->driver.bus = NULL; | |
4410 | hsotg->driver = driver; | |
7d7b2292 | 4411 | hsotg->gadget.dev.of_node = hsotg->dev->of_node; |
5b7d70c6 BD |
4412 | hsotg->gadget.speed = USB_SPEED_UNKNOWN; |
4413 | ||
09a75e85 MS |
4414 | if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) { |
4415 | ret = dwc2_lowlevel_hw_enable(hsotg); | |
4416 | if (ret) | |
4417 | goto err; | |
5b7d70c6 BD |
4418 | } |
4419 | ||
f6c01592 GH |
4420 | if (!IS_ERR_OR_NULL(hsotg->uphy)) |
4421 | otg_set_peripheral(hsotg->uphy->otg, &hsotg->gadget); | |
c816c47f | 4422 | |
5b9451f8 | 4423 | spin_lock_irqsave(&hsotg->lock, flags); |
d0f0ac56 JY |
4424 | if (dwc2_hw_is_device(hsotg)) { |
4425 | dwc2_hsotg_init(hsotg); | |
4426 | dwc2_hsotg_core_init_disconnected(hsotg, false); | |
4427 | } | |
4428 | ||
dc6e69e6 | 4429 | hsotg->enabled = 0; |
5b9451f8 MS |
4430 | spin_unlock_irqrestore(&hsotg->lock, flags); |
4431 | ||
10209abe | 4432 | gadget->sg_supported = using_desc_dma(hsotg); |
5b7d70c6 | 4433 | dev_info(hsotg->dev, "bound driver %s\n", driver->driver.name); |
5b9451f8 | 4434 | |
5b7d70c6 BD |
4435 | return 0; |
4436 | ||
4437 | err: | |
4438 | hsotg->driver = NULL; | |
5b7d70c6 BD |
4439 | return ret; |
4440 | } | |
4441 | ||
8b9bc460 | 4442 | /** |
1f91b4cc | 4443 | * dwc2_hsotg_udc_stop - stop the udc |
8b9bc460 | 4444 | * @gadget: The usb gadget state |
8b9bc460 LM |
4445 | * |
4446 | * Stop udc hw block and stay tunned for future transmissions | |
4447 | */ | |
1f91b4cc | 4448 | static int dwc2_hsotg_udc_stop(struct usb_gadget *gadget) |
5b7d70c6 | 4449 | { |
941fcce4 | 4450 | struct dwc2_hsotg *hsotg = to_hsotg(gadget); |
2b19a52c | 4451 | unsigned long flags = 0; |
5b7d70c6 BD |
4452 | int ep; |
4453 | ||
4454 | if (!hsotg) | |
4455 | return -ENODEV; | |
4456 | ||
5b7d70c6 | 4457 | /* all endpoints should be shutdown */ |
c6f5c050 MYK |
4458 | for (ep = 1; ep < hsotg->num_of_eps; ep++) { |
4459 | if (hsotg->eps_in[ep]) | |
4fe4f9fe | 4460 | dwc2_hsotg_ep_disable_lock(&hsotg->eps_in[ep]->ep); |
c6f5c050 | 4461 | if (hsotg->eps_out[ep]) |
4fe4f9fe | 4462 | dwc2_hsotg_ep_disable_lock(&hsotg->eps_out[ep]->ep); |
c6f5c050 | 4463 | } |
5b7d70c6 | 4464 | |
2b19a52c LM |
4465 | spin_lock_irqsave(&hsotg->lock, flags); |
4466 | ||
32805c35 | 4467 | hsotg->driver = NULL; |
5b7d70c6 | 4468 | hsotg->gadget.speed = USB_SPEED_UNKNOWN; |
dc6e69e6 | 4469 | hsotg->enabled = 0; |
5b7d70c6 | 4470 | |
2b19a52c LM |
4471 | spin_unlock_irqrestore(&hsotg->lock, flags); |
4472 | ||
f6c01592 GH |
4473 | if (!IS_ERR_OR_NULL(hsotg->uphy)) |
4474 | otg_set_peripheral(hsotg->uphy->otg, NULL); | |
c816c47f | 4475 | |
09a75e85 MS |
4476 | if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) |
4477 | dwc2_lowlevel_hw_disable(hsotg); | |
5b7d70c6 BD |
4478 | |
4479 | return 0; | |
4480 | } | |
5b7d70c6 | 4481 | |
8b9bc460 | 4482 | /** |
1f91b4cc | 4483 | * dwc2_hsotg_gadget_getframe - read the frame number |
8b9bc460 LM |
4484 | * @gadget: The usb gadget state |
4485 | * | |
4486 | * Read the {micro} frame number | |
4487 | */ | |
1f91b4cc | 4488 | static int dwc2_hsotg_gadget_getframe(struct usb_gadget *gadget) |
5b7d70c6 | 4489 | { |
1f91b4cc | 4490 | return dwc2_hsotg_read_frameno(to_hsotg(gadget)); |
5b7d70c6 BD |
4491 | } |
4492 | ||
a188b689 | 4493 | /** |
1f91b4cc | 4494 | * dwc2_hsotg_pullup - connect/disconnect the USB PHY |
a188b689 LM |
4495 | * @gadget: The usb gadget state |
4496 | * @is_on: Current state of the USB PHY | |
4497 | * | |
4498 | * Connect/Disconnect the USB PHY pullup | |
4499 | */ | |
1f91b4cc | 4500 | static int dwc2_hsotg_pullup(struct usb_gadget *gadget, int is_on) |
a188b689 | 4501 | { |
941fcce4 | 4502 | struct dwc2_hsotg *hsotg = to_hsotg(gadget); |
a188b689 LM |
4503 | unsigned long flags = 0; |
4504 | ||
77ba9119 | 4505 | dev_dbg(hsotg->dev, "%s: is_on: %d op_state: %d\n", __func__, is_on, |
9da51974 | 4506 | hsotg->op_state); |
77ba9119 GH |
4507 | |
4508 | /* Don't modify pullup state while in host mode */ | |
4509 | if (hsotg->op_state != OTG_STATE_B_PERIPHERAL) { | |
4510 | hsotg->enabled = is_on; | |
4511 | return 0; | |
4512 | } | |
a188b689 LM |
4513 | |
4514 | spin_lock_irqsave(&hsotg->lock, flags); | |
4515 | if (is_on) { | |
dc6e69e6 | 4516 | hsotg->enabled = 1; |
1f91b4cc | 4517 | dwc2_hsotg_core_init_disconnected(hsotg, false); |
66e77a24 RK |
4518 | /* Enable ACG feature in device mode,if supported */ |
4519 | dwc2_enable_acg(hsotg); | |
1f91b4cc | 4520 | dwc2_hsotg_core_connect(hsotg); |
a188b689 | 4521 | } else { |
1f91b4cc FB |
4522 | dwc2_hsotg_core_disconnect(hsotg); |
4523 | dwc2_hsotg_disconnect(hsotg); | |
dc6e69e6 | 4524 | hsotg->enabled = 0; |
a188b689 LM |
4525 | } |
4526 | ||
4527 | hsotg->gadget.speed = USB_SPEED_UNKNOWN; | |
4528 | spin_unlock_irqrestore(&hsotg->lock, flags); | |
4529 | ||
4530 | return 0; | |
4531 | } | |
4532 | ||
1f91b4cc | 4533 | static int dwc2_hsotg_vbus_session(struct usb_gadget *gadget, int is_active) |
83d98223 GH |
4534 | { |
4535 | struct dwc2_hsotg *hsotg = to_hsotg(gadget); | |
4536 | unsigned long flags; | |
4537 | ||
4538 | dev_dbg(hsotg->dev, "%s: is_active: %d\n", __func__, is_active); | |
4539 | spin_lock_irqsave(&hsotg->lock, flags); | |
4540 | ||
61f7223b | 4541 | /* |
41ba9b9b | 4542 | * If controller is hibernated, it must exit from power_down |
61f7223b GH |
4543 | * before being initialized / de-initialized |
4544 | */ | |
4545 | if (hsotg->lx_state == DWC2_L2) | |
41ba9b9b | 4546 | dwc2_exit_partial_power_down(hsotg, false); |
61f7223b | 4547 | |
83d98223 | 4548 | if (is_active) { |
cd0e641c | 4549 | hsotg->op_state = OTG_STATE_B_PERIPHERAL; |
065d3931 | 4550 | |
1f91b4cc | 4551 | dwc2_hsotg_core_init_disconnected(hsotg, false); |
66e77a24 RK |
4552 | if (hsotg->enabled) { |
4553 | /* Enable ACG feature in device mode,if supported */ | |
4554 | dwc2_enable_acg(hsotg); | |
1f91b4cc | 4555 | dwc2_hsotg_core_connect(hsotg); |
66e77a24 | 4556 | } |
83d98223 | 4557 | } else { |
1f91b4cc FB |
4558 | dwc2_hsotg_core_disconnect(hsotg); |
4559 | dwc2_hsotg_disconnect(hsotg); | |
83d98223 GH |
4560 | } |
4561 | ||
4562 | spin_unlock_irqrestore(&hsotg->lock, flags); | |
4563 | return 0; | |
4564 | } | |
4565 | ||
596d696a | 4566 | /** |
1f91b4cc | 4567 | * dwc2_hsotg_vbus_draw - report bMaxPower field |
596d696a GH |
4568 | * @gadget: The usb gadget state |
4569 | * @mA: Amount of current | |
4570 | * | |
4571 | * Report how much power the device may consume to the phy. | |
4572 | */ | |
9da51974 | 4573 | static int dwc2_hsotg_vbus_draw(struct usb_gadget *gadget, unsigned int mA) |
596d696a GH |
4574 | { |
4575 | struct dwc2_hsotg *hsotg = to_hsotg(gadget); | |
4576 | ||
4577 | if (IS_ERR_OR_NULL(hsotg->uphy)) | |
4578 | return -ENOTSUPP; | |
4579 | return usb_phy_set_power(hsotg->uphy, mA); | |
4580 | } | |
4581 | ||
1f91b4cc FB |
4582 | static const struct usb_gadget_ops dwc2_hsotg_gadget_ops = { |
4583 | .get_frame = dwc2_hsotg_gadget_getframe, | |
4584 | .udc_start = dwc2_hsotg_udc_start, | |
4585 | .udc_stop = dwc2_hsotg_udc_stop, | |
4586 | .pullup = dwc2_hsotg_pullup, | |
4587 | .vbus_session = dwc2_hsotg_vbus_session, | |
4588 | .vbus_draw = dwc2_hsotg_vbus_draw, | |
5b7d70c6 BD |
4589 | }; |
4590 | ||
4591 | /** | |
1f91b4cc | 4592 | * dwc2_hsotg_initep - initialise a single endpoint |
5b7d70c6 BD |
4593 | * @hsotg: The device state. |
4594 | * @hs_ep: The endpoint to be initialised. | |
4595 | * @epnum: The endpoint number | |
6fb914d7 | 4596 | * @dir_in: True if direction is in. |
5b7d70c6 BD |
4597 | * |
4598 | * Initialise the given endpoint (as part of the probe and device state | |
4599 | * creation) to give to the gadget driver. Setup the endpoint name, any | |
4600 | * direction information and other state that may be required. | |
4601 | */ | |
1f91b4cc | 4602 | static void dwc2_hsotg_initep(struct dwc2_hsotg *hsotg, |
9da51974 | 4603 | struct dwc2_hsotg_ep *hs_ep, |
c6f5c050 MYK |
4604 | int epnum, |
4605 | bool dir_in) | |
5b7d70c6 | 4606 | { |
5b7d70c6 BD |
4607 | char *dir; |
4608 | ||
4609 | if (epnum == 0) | |
4610 | dir = ""; | |
c6f5c050 | 4611 | else if (dir_in) |
5b7d70c6 | 4612 | dir = "in"; |
c6f5c050 MYK |
4613 | else |
4614 | dir = "out"; | |
5b7d70c6 | 4615 | |
c6f5c050 | 4616 | hs_ep->dir_in = dir_in; |
5b7d70c6 BD |
4617 | hs_ep->index = epnum; |
4618 | ||
4619 | snprintf(hs_ep->name, sizeof(hs_ep->name), "ep%d%s", epnum, dir); | |
4620 | ||
4621 | INIT_LIST_HEAD(&hs_ep->queue); | |
4622 | INIT_LIST_HEAD(&hs_ep->ep.ep_list); | |
4623 | ||
5b7d70c6 BD |
4624 | /* add to the list of endpoints known by the gadget driver */ |
4625 | if (epnum) | |
4626 | list_add_tail(&hs_ep->ep.ep_list, &hsotg->gadget.ep_list); | |
4627 | ||
4628 | hs_ep->parent = hsotg; | |
4629 | hs_ep->ep.name = hs_ep->name; | |
38e9002b VM |
4630 | |
4631 | if (hsotg->params.speed == DWC2_SPEED_PARAM_LOW) | |
4632 | usb_ep_set_maxpacket_limit(&hs_ep->ep, 8); | |
4633 | else | |
4634 | usb_ep_set_maxpacket_limit(&hs_ep->ep, | |
4635 | epnum ? 1024 : EP0_MPS_LIMIT); | |
1f91b4cc | 4636 | hs_ep->ep.ops = &dwc2_hsotg_ep_ops; |
5b7d70c6 | 4637 | |
2954522f RB |
4638 | if (epnum == 0) { |
4639 | hs_ep->ep.caps.type_control = true; | |
4640 | } else { | |
38e9002b VM |
4641 | if (hsotg->params.speed != DWC2_SPEED_PARAM_LOW) { |
4642 | hs_ep->ep.caps.type_iso = true; | |
4643 | hs_ep->ep.caps.type_bulk = true; | |
4644 | } | |
2954522f RB |
4645 | hs_ep->ep.caps.type_int = true; |
4646 | } | |
4647 | ||
4648 | if (dir_in) | |
4649 | hs_ep->ep.caps.dir_in = true; | |
4650 | else | |
4651 | hs_ep->ep.caps.dir_out = true; | |
4652 | ||
8b9bc460 LM |
4653 | /* |
4654 | * if we're using dma, we need to set the next-endpoint pointer | |
5b7d70c6 BD |
4655 | * to be something valid. |
4656 | */ | |
4657 | ||
4658 | if (using_dma(hsotg)) { | |
47a1685f | 4659 | u32 next = DXEPCTL_NEXTEP((epnum + 1) % 15); |
9da51974 | 4660 | |
c6f5c050 | 4661 | if (dir_in) |
f25c42b8 | 4662 | dwc2_writel(hsotg, next, DIEPCTL(epnum)); |
c6f5c050 | 4663 | else |
f25c42b8 | 4664 | dwc2_writel(hsotg, next, DOEPCTL(epnum)); |
5b7d70c6 BD |
4665 | } |
4666 | } | |
4667 | ||
b3f489b2 | 4668 | /** |
1f91b4cc | 4669 | * dwc2_hsotg_hw_cfg - read HW configuration registers |
6fb914d7 | 4670 | * @hsotg: Programming view of the DWC_otg controller |
b3f489b2 LM |
4671 | * |
4672 | * Read the USB core HW configuration registers | |
4673 | */ | |
1f91b4cc | 4674 | static int dwc2_hsotg_hw_cfg(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 4675 | { |
c6f5c050 MYK |
4676 | u32 cfg; |
4677 | u32 ep_type; | |
4678 | u32 i; | |
4679 | ||
b3f489b2 | 4680 | /* check hardware configuration */ |
5b7d70c6 | 4681 | |
43e90349 JY |
4682 | hsotg->num_of_eps = hsotg->hw_params.num_dev_ep; |
4683 | ||
c6f5c050 MYK |
4684 | /* Add ep0 */ |
4685 | hsotg->num_of_eps++; | |
10aebc77 | 4686 | |
b98866c2 JY |
4687 | hsotg->eps_in[0] = devm_kzalloc(hsotg->dev, |
4688 | sizeof(struct dwc2_hsotg_ep), | |
4689 | GFP_KERNEL); | |
c6f5c050 MYK |
4690 | if (!hsotg->eps_in[0]) |
4691 | return -ENOMEM; | |
1f91b4cc | 4692 | /* Same dwc2_hsotg_ep is used in both directions for ep0 */ |
c6f5c050 MYK |
4693 | hsotg->eps_out[0] = hsotg->eps_in[0]; |
4694 | ||
43e90349 | 4695 | cfg = hsotg->hw_params.dev_ep_dirs; |
251a17f5 | 4696 | for (i = 1, cfg >>= 2; i < hsotg->num_of_eps; i++, cfg >>= 2) { |
c6f5c050 MYK |
4697 | ep_type = cfg & 3; |
4698 | /* Direction in or both */ | |
4699 | if (!(ep_type & 2)) { | |
4700 | hsotg->eps_in[i] = devm_kzalloc(hsotg->dev, | |
1f91b4cc | 4701 | sizeof(struct dwc2_hsotg_ep), GFP_KERNEL); |
c6f5c050 MYK |
4702 | if (!hsotg->eps_in[i]) |
4703 | return -ENOMEM; | |
4704 | } | |
4705 | /* Direction out or both */ | |
4706 | if (!(ep_type & 1)) { | |
4707 | hsotg->eps_out[i] = devm_kzalloc(hsotg->dev, | |
1f91b4cc | 4708 | sizeof(struct dwc2_hsotg_ep), GFP_KERNEL); |
c6f5c050 MYK |
4709 | if (!hsotg->eps_out[i]) |
4710 | return -ENOMEM; | |
4711 | } | |
4712 | } | |
4713 | ||
43e90349 JY |
4714 | hsotg->fifo_mem = hsotg->hw_params.total_fifo_size; |
4715 | hsotg->dedicated_fifos = hsotg->hw_params.en_multiple_tx_fifo; | |
10aebc77 | 4716 | |
cff9eb75 MS |
4717 | dev_info(hsotg->dev, "EPs: %d, %s fifos, %d entries in SPRAM\n", |
4718 | hsotg->num_of_eps, | |
4719 | hsotg->dedicated_fifos ? "dedicated" : "shared", | |
4720 | hsotg->fifo_mem); | |
c6f5c050 | 4721 | return 0; |
5b7d70c6 BD |
4722 | } |
4723 | ||
8b9bc460 | 4724 | /** |
1f91b4cc | 4725 | * dwc2_hsotg_dump - dump state of the udc |
6fb914d7 GT |
4726 | * @hsotg: Programming view of the DWC_otg controller |
4727 | * | |
8b9bc460 | 4728 | */ |
1f91b4cc | 4729 | static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 4730 | { |
83a01804 | 4731 | #ifdef DEBUG |
5b7d70c6 | 4732 | struct device *dev = hsotg->dev; |
5b7d70c6 BD |
4733 | u32 val; |
4734 | int idx; | |
4735 | ||
4736 | dev_info(dev, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n", | |
f25c42b8 GS |
4737 | dwc2_readl(hsotg, DCFG), dwc2_readl(hsotg, DCTL), |
4738 | dwc2_readl(hsotg, DIEPMSK)); | |
5b7d70c6 | 4739 | |
f889f23d | 4740 | dev_info(dev, "GAHBCFG=0x%08x, GHWCFG1=0x%08x\n", |
f25c42b8 | 4741 | dwc2_readl(hsotg, GAHBCFG), dwc2_readl(hsotg, GHWCFG1)); |
5b7d70c6 BD |
4742 | |
4743 | dev_info(dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n", | |
f25c42b8 | 4744 | dwc2_readl(hsotg, GRXFSIZ), dwc2_readl(hsotg, GNPTXFSIZ)); |
5b7d70c6 BD |
4745 | |
4746 | /* show periodic fifo settings */ | |
4747 | ||
364f8e93 | 4748 | for (idx = 1; idx < hsotg->num_of_eps; idx++) { |
f25c42b8 | 4749 | val = dwc2_readl(hsotg, DPTXFSIZN(idx)); |
5b7d70c6 | 4750 | dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx, |
47a1685f DN |
4751 | val >> FIFOSIZE_DEPTH_SHIFT, |
4752 | val & FIFOSIZE_STARTADDR_MASK); | |
5b7d70c6 BD |
4753 | } |
4754 | ||
364f8e93 | 4755 | for (idx = 0; idx < hsotg->num_of_eps; idx++) { |
5b7d70c6 BD |
4756 | dev_info(dev, |
4757 | "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx, | |
f25c42b8 GS |
4758 | dwc2_readl(hsotg, DIEPCTL(idx)), |
4759 | dwc2_readl(hsotg, DIEPTSIZ(idx)), | |
4760 | dwc2_readl(hsotg, DIEPDMA(idx))); | |
5b7d70c6 | 4761 | |
f25c42b8 | 4762 | val = dwc2_readl(hsotg, DOEPCTL(idx)); |
5b7d70c6 BD |
4763 | dev_info(dev, |
4764 | "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", | |
f25c42b8 GS |
4765 | idx, dwc2_readl(hsotg, DOEPCTL(idx)), |
4766 | dwc2_readl(hsotg, DOEPTSIZ(idx)), | |
4767 | dwc2_readl(hsotg, DOEPDMA(idx))); | |
5b7d70c6 BD |
4768 | } |
4769 | ||
4770 | dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n", | |
f25c42b8 | 4771 | dwc2_readl(hsotg, DVBUSDIS), dwc2_readl(hsotg, DVBUSPULSE)); |
83a01804 | 4772 | #endif |
5b7d70c6 BD |
4773 | } |
4774 | ||
8b9bc460 | 4775 | /** |
117777b2 | 4776 | * dwc2_gadget_init - init function for gadget |
6fb914d7 GT |
4777 | * @hsotg: Programming view of the DWC_otg controller |
4778 | * | |
8b9bc460 | 4779 | */ |
f3768997 | 4780 | int dwc2_gadget_init(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 4781 | { |
117777b2 | 4782 | struct device *dev = hsotg->dev; |
5b7d70c6 BD |
4783 | int epnum; |
4784 | int ret; | |
43e90349 | 4785 | |
0a176279 GH |
4786 | /* Dump fifo information */ |
4787 | dev_dbg(dev, "NonPeriodic TXFIFO size: %d\n", | |
05ee799f JY |
4788 | hsotg->params.g_np_tx_fifo_size); |
4789 | dev_dbg(dev, "RXFIFO size: %d\n", hsotg->params.g_rx_fifo_size); | |
5b7d70c6 | 4790 | |
d327ab5b | 4791 | hsotg->gadget.max_speed = USB_SPEED_HIGH; |
1f91b4cc | 4792 | hsotg->gadget.ops = &dwc2_hsotg_gadget_ops; |
5b7d70c6 | 4793 | hsotg->gadget.name = dev_name(dev); |
fa389a6d | 4794 | hsotg->remote_wakeup_allowed = 0; |
7455f8b7 JY |
4795 | |
4796 | if (hsotg->params.lpm) | |
4797 | hsotg->gadget.lpm_capable = true; | |
4798 | ||
097ee662 GH |
4799 | if (hsotg->dr_mode == USB_DR_MODE_OTG) |
4800 | hsotg->gadget.is_otg = 1; | |
ec4cc657 MYK |
4801 | else if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) |
4802 | hsotg->op_state = OTG_STATE_B_PERIPHERAL; | |
5b7d70c6 | 4803 | |
1f91b4cc | 4804 | ret = dwc2_hsotg_hw_cfg(hsotg); |
c6f5c050 MYK |
4805 | if (ret) { |
4806 | dev_err(hsotg->dev, "Hardware configuration failed: %d\n", ret); | |
09a75e85 | 4807 | return ret; |
c6f5c050 MYK |
4808 | } |
4809 | ||
3f95001d MYK |
4810 | hsotg->ctrl_buff = devm_kzalloc(hsotg->dev, |
4811 | DWC2_CTRL_BUFF_SIZE, GFP_KERNEL); | |
8bae0f8c | 4812 | if (!hsotg->ctrl_buff) |
09a75e85 | 4813 | return -ENOMEM; |
3f95001d MYK |
4814 | |
4815 | hsotg->ep0_buff = devm_kzalloc(hsotg->dev, | |
4816 | DWC2_CTRL_BUFF_SIZE, GFP_KERNEL); | |
8bae0f8c | 4817 | if (!hsotg->ep0_buff) |
09a75e85 | 4818 | return -ENOMEM; |
3f95001d | 4819 | |
0f6b80c0 VA |
4820 | if (using_desc_dma(hsotg)) { |
4821 | ret = dwc2_gadget_alloc_ctrl_desc_chains(hsotg); | |
4822 | if (ret < 0) | |
4823 | return ret; | |
4824 | } | |
4825 | ||
f3768997 VM |
4826 | ret = devm_request_irq(hsotg->dev, hsotg->irq, dwc2_hsotg_irq, |
4827 | IRQF_SHARED, dev_name(hsotg->dev), hsotg); | |
eb3c56c5 | 4828 | if (ret < 0) { |
db8178c3 | 4829 | dev_err(dev, "cannot claim IRQ for gadget\n"); |
09a75e85 | 4830 | return ret; |
eb3c56c5 MS |
4831 | } |
4832 | ||
b3f489b2 LM |
4833 | /* hsotg->num_of_eps holds number of EPs other than ep0 */ |
4834 | ||
4835 | if (hsotg->num_of_eps == 0) { | |
4836 | dev_err(dev, "wrong number of EPs (zero)\n"); | |
09a75e85 | 4837 | return -EINVAL; |
b3f489b2 LM |
4838 | } |
4839 | ||
b3f489b2 LM |
4840 | /* setup endpoint information */ |
4841 | ||
4842 | INIT_LIST_HEAD(&hsotg->gadget.ep_list); | |
c6f5c050 | 4843 | hsotg->gadget.ep0 = &hsotg->eps_out[0]->ep; |
b3f489b2 LM |
4844 | |
4845 | /* allocate EP0 request */ | |
4846 | ||
1f91b4cc | 4847 | hsotg->ctrl_req = dwc2_hsotg_ep_alloc_request(&hsotg->eps_out[0]->ep, |
b3f489b2 LM |
4848 | GFP_KERNEL); |
4849 | if (!hsotg->ctrl_req) { | |
4850 | dev_err(dev, "failed to allocate ctrl req\n"); | |
09a75e85 | 4851 | return -ENOMEM; |
b3f489b2 | 4852 | } |
5b7d70c6 BD |
4853 | |
4854 | /* initialise the endpoints now the core has been initialised */ | |
c6f5c050 MYK |
4855 | for (epnum = 0; epnum < hsotg->num_of_eps; epnum++) { |
4856 | if (hsotg->eps_in[epnum]) | |
1f91b4cc | 4857 | dwc2_hsotg_initep(hsotg, hsotg->eps_in[epnum], |
9da51974 | 4858 | epnum, 1); |
c6f5c050 | 4859 | if (hsotg->eps_out[epnum]) |
1f91b4cc | 4860 | dwc2_hsotg_initep(hsotg, hsotg->eps_out[epnum], |
9da51974 | 4861 | epnum, 0); |
c6f5c050 | 4862 | } |
5b7d70c6 | 4863 | |
117777b2 | 4864 | ret = usb_add_gadget_udc(dev, &hsotg->gadget); |
9bb073a0 GT |
4865 | if (ret) { |
4866 | dwc2_hsotg_ep_free_request(&hsotg->eps_out[0]->ep, | |
4867 | hsotg->ctrl_req); | |
09a75e85 | 4868 | return ret; |
9bb073a0 | 4869 | } |
1f91b4cc | 4870 | dwc2_hsotg_dump(hsotg); |
5b7d70c6 | 4871 | |
5b7d70c6 | 4872 | return 0; |
5b7d70c6 BD |
4873 | } |
4874 | ||
8b9bc460 | 4875 | /** |
1f91b4cc | 4876 | * dwc2_hsotg_remove - remove function for hsotg driver |
6fb914d7 GT |
4877 | * @hsotg: Programming view of the DWC_otg controller |
4878 | * | |
8b9bc460 | 4879 | */ |
1f91b4cc | 4880 | int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 4881 | { |
0f91349b | 4882 | usb_del_gadget_udc(&hsotg->gadget); |
9bb073a0 | 4883 | dwc2_hsotg_ep_free_request(&hsotg->eps_out[0]->ep, hsotg->ctrl_req); |
31ee04de | 4884 | |
5b7d70c6 BD |
4885 | return 0; |
4886 | } | |
4887 | ||
1f91b4cc | 4888 | int dwc2_hsotg_suspend(struct dwc2_hsotg *hsotg) |
b83e333a | 4889 | { |
b83e333a | 4890 | unsigned long flags; |
b83e333a | 4891 | |
9e779778 | 4892 | if (hsotg->lx_state != DWC2_L0) |
09a75e85 | 4893 | return 0; |
9e779778 | 4894 | |
dc6e69e6 MS |
4895 | if (hsotg->driver) { |
4896 | int ep; | |
4897 | ||
b83e333a MS |
4898 | dev_info(hsotg->dev, "suspending usb gadget %s\n", |
4899 | hsotg->driver->driver.name); | |
4900 | ||
dc6e69e6 MS |
4901 | spin_lock_irqsave(&hsotg->lock, flags); |
4902 | if (hsotg->enabled) | |
1f91b4cc FB |
4903 | dwc2_hsotg_core_disconnect(hsotg); |
4904 | dwc2_hsotg_disconnect(hsotg); | |
dc6e69e6 MS |
4905 | hsotg->gadget.speed = USB_SPEED_UNKNOWN; |
4906 | spin_unlock_irqrestore(&hsotg->lock, flags); | |
b83e333a | 4907 | |
c6f5c050 MYK |
4908 | for (ep = 0; ep < hsotg->num_of_eps; ep++) { |
4909 | if (hsotg->eps_in[ep]) | |
4fe4f9fe | 4910 | dwc2_hsotg_ep_disable_lock(&hsotg->eps_in[ep]->ep); |
c6f5c050 | 4911 | if (hsotg->eps_out[ep]) |
4fe4f9fe | 4912 | dwc2_hsotg_ep_disable_lock(&hsotg->eps_out[ep]->ep); |
c6f5c050 | 4913 | } |
b83e333a MS |
4914 | } |
4915 | ||
09a75e85 | 4916 | return 0; |
b83e333a MS |
4917 | } |
4918 | ||
1f91b4cc | 4919 | int dwc2_hsotg_resume(struct dwc2_hsotg *hsotg) |
b83e333a | 4920 | { |
b83e333a | 4921 | unsigned long flags; |
b83e333a | 4922 | |
9e779778 | 4923 | if (hsotg->lx_state == DWC2_L2) |
09a75e85 | 4924 | return 0; |
9e779778 | 4925 | |
b83e333a MS |
4926 | if (hsotg->driver) { |
4927 | dev_info(hsotg->dev, "resuming usb gadget %s\n", | |
4928 | hsotg->driver->driver.name); | |
d00b4142 | 4929 | |
dc6e69e6 | 4930 | spin_lock_irqsave(&hsotg->lock, flags); |
1f91b4cc | 4931 | dwc2_hsotg_core_init_disconnected(hsotg, false); |
66e77a24 RK |
4932 | if (hsotg->enabled) { |
4933 | /* Enable ACG feature in device mode,if supported */ | |
4934 | dwc2_enable_acg(hsotg); | |
1f91b4cc | 4935 | dwc2_hsotg_core_connect(hsotg); |
66e77a24 | 4936 | } |
dc6e69e6 MS |
4937 | spin_unlock_irqrestore(&hsotg->lock, flags); |
4938 | } | |
b83e333a | 4939 | |
09a75e85 | 4940 | return 0; |
b83e333a | 4941 | } |
58e52ff6 JY |
4942 | |
4943 | /** | |
4944 | * dwc2_backup_device_registers() - Backup controller device registers. | |
4945 | * When suspending usb bus, registers needs to be backuped | |
4946 | * if controller power is disabled once suspended. | |
4947 | * | |
4948 | * @hsotg: Programming view of the DWC_otg controller | |
4949 | */ | |
4950 | int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg) | |
4951 | { | |
4952 | struct dwc2_dregs_backup *dr; | |
4953 | int i; | |
4954 | ||
4955 | dev_dbg(hsotg->dev, "%s\n", __func__); | |
4956 | ||
4957 | /* Backup dev regs */ | |
4958 | dr = &hsotg->dr_backup; | |
4959 | ||
f25c42b8 GS |
4960 | dr->dcfg = dwc2_readl(hsotg, DCFG); |
4961 | dr->dctl = dwc2_readl(hsotg, DCTL); | |
4962 | dr->daintmsk = dwc2_readl(hsotg, DAINTMSK); | |
4963 | dr->diepmsk = dwc2_readl(hsotg, DIEPMSK); | |
4964 | dr->doepmsk = dwc2_readl(hsotg, DOEPMSK); | |
58e52ff6 JY |
4965 | |
4966 | for (i = 0; i < hsotg->num_of_eps; i++) { | |
4967 | /* Backup IN EPs */ | |
f25c42b8 | 4968 | dr->diepctl[i] = dwc2_readl(hsotg, DIEPCTL(i)); |
58e52ff6 JY |
4969 | |
4970 | /* Ensure DATA PID is correctly configured */ | |
4971 | if (dr->diepctl[i] & DXEPCTL_DPID) | |
4972 | dr->diepctl[i] |= DXEPCTL_SETD1PID; | |
4973 | else | |
4974 | dr->diepctl[i] |= DXEPCTL_SETD0PID; | |
4975 | ||
f25c42b8 GS |
4976 | dr->dieptsiz[i] = dwc2_readl(hsotg, DIEPTSIZ(i)); |
4977 | dr->diepdma[i] = dwc2_readl(hsotg, DIEPDMA(i)); | |
58e52ff6 JY |
4978 | |
4979 | /* Backup OUT EPs */ | |
f25c42b8 | 4980 | dr->doepctl[i] = dwc2_readl(hsotg, DOEPCTL(i)); |
58e52ff6 JY |
4981 | |
4982 | /* Ensure DATA PID is correctly configured */ | |
4983 | if (dr->doepctl[i] & DXEPCTL_DPID) | |
4984 | dr->doepctl[i] |= DXEPCTL_SETD1PID; | |
4985 | else | |
4986 | dr->doepctl[i] |= DXEPCTL_SETD0PID; | |
4987 | ||
f25c42b8 GS |
4988 | dr->doeptsiz[i] = dwc2_readl(hsotg, DOEPTSIZ(i)); |
4989 | dr->doepdma[i] = dwc2_readl(hsotg, DOEPDMA(i)); | |
4990 | dr->dtxfsiz[i] = dwc2_readl(hsotg, DPTXFSIZN(i)); | |
58e52ff6 JY |
4991 | } |
4992 | dr->valid = true; | |
4993 | return 0; | |
4994 | } | |
4995 | ||
4996 | /** | |
4997 | * dwc2_restore_device_registers() - Restore controller device registers. | |
4998 | * When resuming usb bus, device registers needs to be restored | |
4999 | * if controller power were disabled. | |
5000 | * | |
5001 | * @hsotg: Programming view of the DWC_otg controller | |
9a5d2816 VM |
5002 | * @remote_wakeup: Indicates whether resume is initiated by Device or Host. |
5003 | * | |
5004 | * Return: 0 if successful, negative error code otherwise | |
58e52ff6 | 5005 | */ |
9a5d2816 | 5006 | int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg, int remote_wakeup) |
58e52ff6 JY |
5007 | { |
5008 | struct dwc2_dregs_backup *dr; | |
58e52ff6 JY |
5009 | int i; |
5010 | ||
5011 | dev_dbg(hsotg->dev, "%s\n", __func__); | |
5012 | ||
5013 | /* Restore dev regs */ | |
5014 | dr = &hsotg->dr_backup; | |
5015 | if (!dr->valid) { | |
5016 | dev_err(hsotg->dev, "%s: no device registers to restore\n", | |
5017 | __func__); | |
5018 | return -EINVAL; | |
5019 | } | |
5020 | dr->valid = false; | |
5021 | ||
9a5d2816 | 5022 | if (!remote_wakeup) |
f25c42b8 | 5023 | dwc2_writel(hsotg, dr->dctl, DCTL); |
9a5d2816 | 5024 | |
f25c42b8 GS |
5025 | dwc2_writel(hsotg, dr->daintmsk, DAINTMSK); |
5026 | dwc2_writel(hsotg, dr->diepmsk, DIEPMSK); | |
5027 | dwc2_writel(hsotg, dr->doepmsk, DOEPMSK); | |
58e52ff6 JY |
5028 | |
5029 | for (i = 0; i < hsotg->num_of_eps; i++) { | |
5030 | /* Restore IN EPs */ | |
f25c42b8 GS |
5031 | dwc2_writel(hsotg, dr->dieptsiz[i], DIEPTSIZ(i)); |
5032 | dwc2_writel(hsotg, dr->diepdma[i], DIEPDMA(i)); | |
5033 | dwc2_writel(hsotg, dr->doeptsiz[i], DOEPTSIZ(i)); | |
9a5d2816 VM |
5034 | /** WA for enabled EPx's IN in DDMA mode. On entering to |
5035 | * hibernation wrong value read and saved from DIEPDMAx, | |
5036 | * as result BNA interrupt asserted on hibernation exit | |
5037 | * by restoring from saved area. | |
5038 | */ | |
5039 | if (hsotg->params.g_dma_desc && | |
5040 | (dr->diepctl[i] & DXEPCTL_EPENA)) | |
5041 | dr->diepdma[i] = hsotg->eps_in[i]->desc_list_dma; | |
f25c42b8 GS |
5042 | dwc2_writel(hsotg, dr->dtxfsiz[i], DPTXFSIZN(i)); |
5043 | dwc2_writel(hsotg, dr->diepctl[i], DIEPCTL(i)); | |
58e52ff6 | 5044 | /* Restore OUT EPs */ |
f25c42b8 | 5045 | dwc2_writel(hsotg, dr->doeptsiz[i], DOEPTSIZ(i)); |
9a5d2816 VM |
5046 | /* WA for enabled EPx's OUT in DDMA mode. On entering to |
5047 | * hibernation wrong value read and saved from DOEPDMAx, | |
5048 | * as result BNA interrupt asserted on hibernation exit | |
5049 | * by restoring from saved area. | |
5050 | */ | |
5051 | if (hsotg->params.g_dma_desc && | |
5052 | (dr->doepctl[i] & DXEPCTL_EPENA)) | |
5053 | dr->doepdma[i] = hsotg->eps_out[i]->desc_list_dma; | |
f25c42b8 GS |
5054 | dwc2_writel(hsotg, dr->doepdma[i], DOEPDMA(i)); |
5055 | dwc2_writel(hsotg, dr->doepctl[i], DOEPCTL(i)); | |
58e52ff6 JY |
5056 | } |
5057 | ||
58e52ff6 JY |
5058 | return 0; |
5059 | } | |
21b03405 SA |
5060 | |
5061 | /** | |
5062 | * dwc2_gadget_init_lpm - Configure the core to support LPM in device mode | |
5063 | * | |
5064 | * @hsotg: Programming view of DWC_otg controller | |
5065 | * | |
5066 | */ | |
5067 | void dwc2_gadget_init_lpm(struct dwc2_hsotg *hsotg) | |
5068 | { | |
5069 | u32 val; | |
5070 | ||
5071 | if (!hsotg->params.lpm) | |
5072 | return; | |
5073 | ||
5074 | val = GLPMCFG_LPMCAP | GLPMCFG_APPL1RES; | |
5075 | val |= hsotg->params.hird_threshold_en ? GLPMCFG_HIRD_THRES_EN : 0; | |
5076 | val |= hsotg->params.lpm_clock_gating ? GLPMCFG_ENBLSLPM : 0; | |
5077 | val |= hsotg->params.hird_threshold << GLPMCFG_HIRD_THRES_SHIFT; | |
5078 | val |= hsotg->params.besl ? GLPMCFG_ENBESL : 0; | |
46637565 | 5079 | val |= GLPMCFG_LPM_REJECT_CTRL_CONTROL; |
9aed8c08 | 5080 | val |= GLPMCFG_LPM_ACCEPT_CTRL_ISOC; |
f25c42b8 GS |
5081 | dwc2_writel(hsotg, val, GLPMCFG); |
5082 | dev_dbg(hsotg->dev, "GLPMCFG=0x%08x\n", dwc2_readl(hsotg, GLPMCFG)); | |
4abe4537 GT |
5083 | |
5084 | /* Unmask WKUP_ALERT Interrupt */ | |
5085 | if (hsotg->params.service_interval) | |
5086 | dwc2_set_bit(hsotg, GINTMSK2, GINTMSK2_WKUP_ALERT_INT_MSK); | |
21b03405 | 5087 | } |
c5c403dc | 5088 | |
15d9dbf8 GT |
5089 | /** |
5090 | * dwc2_gadget_program_ref_clk - Program GREFCLK register in device mode | |
5091 | * | |
5092 | * @hsotg: Programming view of DWC_otg controller | |
5093 | * | |
5094 | */ | |
5095 | void dwc2_gadget_program_ref_clk(struct dwc2_hsotg *hsotg) | |
5096 | { | |
5097 | u32 val = 0; | |
5098 | ||
5099 | val |= GREFCLK_REF_CLK_MODE; | |
5100 | val |= hsotg->params.ref_clk_per << GREFCLK_REFCLKPER_SHIFT; | |
5101 | val |= hsotg->params.sof_cnt_wkup_alert << | |
5102 | GREFCLK_SOF_CNT_WKUP_ALERT_SHIFT; | |
5103 | ||
5104 | dwc2_writel(hsotg, val, GREFCLK); | |
5105 | dev_dbg(hsotg->dev, "GREFCLK=0x%08x\n", dwc2_readl(hsotg, GREFCLK)); | |
5106 | } | |
5107 | ||
c5c403dc VM |
5108 | /** |
5109 | * dwc2_gadget_enter_hibernation() - Put controller in Hibernation. | |
5110 | * | |
5111 | * @hsotg: Programming view of the DWC_otg controller | |
5112 | * | |
5113 | * Return non-zero if failed to enter to hibernation. | |
5114 | */ | |
5115 | int dwc2_gadget_enter_hibernation(struct dwc2_hsotg *hsotg) | |
5116 | { | |
5117 | u32 gpwrdn; | |
5118 | int ret = 0; | |
5119 | ||
5120 | /* Change to L2(suspend) state */ | |
5121 | hsotg->lx_state = DWC2_L2; | |
5122 | dev_dbg(hsotg->dev, "Start of hibernation completed\n"); | |
5123 | ret = dwc2_backup_global_registers(hsotg); | |
5124 | if (ret) { | |
5125 | dev_err(hsotg->dev, "%s: failed to backup global registers\n", | |
5126 | __func__); | |
5127 | return ret; | |
5128 | } | |
5129 | ret = dwc2_backup_device_registers(hsotg); | |
5130 | if (ret) { | |
5131 | dev_err(hsotg->dev, "%s: failed to backup device registers\n", | |
5132 | __func__); | |
5133 | return ret; | |
5134 | } | |
5135 | ||
5136 | gpwrdn = GPWRDN_PWRDNRSTN; | |
5137 | gpwrdn |= GPWRDN_PMUACTV; | |
f25c42b8 | 5138 | dwc2_writel(hsotg, gpwrdn, GPWRDN); |
c5c403dc VM |
5139 | udelay(10); |
5140 | ||
5141 | /* Set flag to indicate that we are in hibernation */ | |
5142 | hsotg->hibernated = 1; | |
5143 | ||
5144 | /* Enable interrupts from wake up logic */ | |
f25c42b8 | 5145 | gpwrdn = dwc2_readl(hsotg, GPWRDN); |
c5c403dc | 5146 | gpwrdn |= GPWRDN_PMUINTSEL; |
f25c42b8 | 5147 | dwc2_writel(hsotg, gpwrdn, GPWRDN); |
c5c403dc VM |
5148 | udelay(10); |
5149 | ||
5150 | /* Unmask device mode interrupts in GPWRDN */ | |
f25c42b8 | 5151 | gpwrdn = dwc2_readl(hsotg, GPWRDN); |
c5c403dc VM |
5152 | gpwrdn |= GPWRDN_RST_DET_MSK; |
5153 | gpwrdn |= GPWRDN_LNSTSCHG_MSK; | |
5154 | gpwrdn |= GPWRDN_STS_CHGINT_MSK; | |
f25c42b8 | 5155 | dwc2_writel(hsotg, gpwrdn, GPWRDN); |
c5c403dc VM |
5156 | udelay(10); |
5157 | ||
5158 | /* Enable Power Down Clamp */ | |
f25c42b8 | 5159 | gpwrdn = dwc2_readl(hsotg, GPWRDN); |
c5c403dc | 5160 | gpwrdn |= GPWRDN_PWRDNCLMP; |
f25c42b8 | 5161 | dwc2_writel(hsotg, gpwrdn, GPWRDN); |
c5c403dc VM |
5162 | udelay(10); |
5163 | ||
5164 | /* Switch off VDD */ | |
f25c42b8 | 5165 | gpwrdn = dwc2_readl(hsotg, GPWRDN); |
c5c403dc | 5166 | gpwrdn |= GPWRDN_PWRDNSWTCH; |
f25c42b8 | 5167 | dwc2_writel(hsotg, gpwrdn, GPWRDN); |
c5c403dc VM |
5168 | udelay(10); |
5169 | ||
5170 | /* Save gpwrdn register for further usage if stschng interrupt */ | |
f25c42b8 | 5171 | hsotg->gr_backup.gpwrdn = dwc2_readl(hsotg, GPWRDN); |
c5c403dc VM |
5172 | dev_dbg(hsotg->dev, "Hibernation completed\n"); |
5173 | ||
5174 | return ret; | |
5175 | } | |
5176 | ||
5177 | /** | |
5178 | * dwc2_gadget_exit_hibernation() | |
5179 | * This function is for exiting from Device mode hibernation by host initiated | |
5180 | * resume/reset and device initiated remote-wakeup. | |
5181 | * | |
5182 | * @hsotg: Programming view of the DWC_otg controller | |
5183 | * @rem_wakeup: indicates whether resume is initiated by Device or Host. | |
6fb914d7 | 5184 | * @reset: indicates whether resume is initiated by Reset. |
c5c403dc VM |
5185 | * |
5186 | * Return non-zero if failed to exit from hibernation. | |
5187 | */ | |
5188 | int dwc2_gadget_exit_hibernation(struct dwc2_hsotg *hsotg, | |
5189 | int rem_wakeup, int reset) | |
5190 | { | |
5191 | u32 pcgcctl; | |
5192 | u32 gpwrdn; | |
5193 | u32 dctl; | |
5194 | int ret = 0; | |
5195 | struct dwc2_gregs_backup *gr; | |
5196 | struct dwc2_dregs_backup *dr; | |
5197 | ||
5198 | gr = &hsotg->gr_backup; | |
5199 | dr = &hsotg->dr_backup; | |
5200 | ||
5201 | if (!hsotg->hibernated) { | |
5202 | dev_dbg(hsotg->dev, "Already exited from Hibernation\n"); | |
5203 | return 1; | |
5204 | } | |
5205 | dev_dbg(hsotg->dev, | |
5206 | "%s: called with rem_wakeup = %d reset = %d\n", | |
5207 | __func__, rem_wakeup, reset); | |
5208 | ||
5209 | dwc2_hib_restore_common(hsotg, rem_wakeup, 0); | |
5210 | ||
5211 | if (!reset) { | |
5212 | /* Clear all pending interupts */ | |
f25c42b8 | 5213 | dwc2_writel(hsotg, 0xffffffff, GINTSTS); |
c5c403dc VM |
5214 | } |
5215 | ||
5216 | /* De-assert Restore */ | |
f25c42b8 | 5217 | gpwrdn = dwc2_readl(hsotg, GPWRDN); |
c5c403dc | 5218 | gpwrdn &= ~GPWRDN_RESTORE; |
f25c42b8 | 5219 | dwc2_writel(hsotg, gpwrdn, GPWRDN); |
c5c403dc VM |
5220 | udelay(10); |
5221 | ||
5222 | if (!rem_wakeup) { | |
f25c42b8 | 5223 | pcgcctl = dwc2_readl(hsotg, PCGCTL); |
c5c403dc | 5224 | pcgcctl &= ~PCGCTL_RSTPDWNMODULE; |
f25c42b8 | 5225 | dwc2_writel(hsotg, pcgcctl, PCGCTL); |
c5c403dc VM |
5226 | } |
5227 | ||
5228 | /* Restore GUSBCFG, DCFG and DCTL */ | |
f25c42b8 GS |
5229 | dwc2_writel(hsotg, gr->gusbcfg, GUSBCFG); |
5230 | dwc2_writel(hsotg, dr->dcfg, DCFG); | |
5231 | dwc2_writel(hsotg, dr->dctl, DCTL); | |
c5c403dc VM |
5232 | |
5233 | /* De-assert Wakeup Logic */ | |
f25c42b8 | 5234 | gpwrdn = dwc2_readl(hsotg, GPWRDN); |
c5c403dc | 5235 | gpwrdn &= ~GPWRDN_PMUACTV; |
f25c42b8 | 5236 | dwc2_writel(hsotg, gpwrdn, GPWRDN); |
c5c403dc VM |
5237 | |
5238 | if (rem_wakeup) { | |
5239 | udelay(10); | |
5240 | /* Start Remote Wakeup Signaling */ | |
f25c42b8 | 5241 | dwc2_writel(hsotg, dr->dctl | DCTL_RMTWKUPSIG, DCTL); |
c5c403dc VM |
5242 | } else { |
5243 | udelay(50); | |
5244 | /* Set Device programming done bit */ | |
f25c42b8 | 5245 | dctl = dwc2_readl(hsotg, DCTL); |
c5c403dc | 5246 | dctl |= DCTL_PWRONPRGDONE; |
f25c42b8 | 5247 | dwc2_writel(hsotg, dctl, DCTL); |
c5c403dc VM |
5248 | } |
5249 | /* Wait for interrupts which must be cleared */ | |
5250 | mdelay(2); | |
5251 | /* Clear all pending interupts */ | |
f25c42b8 | 5252 | dwc2_writel(hsotg, 0xffffffff, GINTSTS); |
c5c403dc VM |
5253 | |
5254 | /* Restore global registers */ | |
5255 | ret = dwc2_restore_global_registers(hsotg); | |
5256 | if (ret) { | |
5257 | dev_err(hsotg->dev, "%s: failed to restore registers\n", | |
5258 | __func__); | |
5259 | return ret; | |
5260 | } | |
5261 | ||
5262 | /* Restore device registers */ | |
5263 | ret = dwc2_restore_device_registers(hsotg, rem_wakeup); | |
5264 | if (ret) { | |
5265 | dev_err(hsotg->dev, "%s: failed to restore device registers\n", | |
5266 | __func__); | |
5267 | return ret; | |
5268 | } | |
5269 | ||
5270 | if (rem_wakeup) { | |
5271 | mdelay(10); | |
f25c42b8 | 5272 | dctl = dwc2_readl(hsotg, DCTL); |
c5c403dc | 5273 | dctl &= ~DCTL_RMTWKUPSIG; |
f25c42b8 | 5274 | dwc2_writel(hsotg, dctl, DCTL); |
c5c403dc VM |
5275 | } |
5276 | ||
5277 | hsotg->hibernated = 0; | |
5278 | hsotg->lx_state = DWC2_L0; | |
5279 | dev_dbg(hsotg->dev, "Hibernation recovery completes here\n"); | |
5280 | ||
5281 | return ret; | |
5282 | } |