usb: gadget: Introduce usb_gadget_giveback_request()
[linux-block.git] / drivers / usb / dwc2 / gadget.c
CommitLineData
8b9bc460 1/**
dfbc6fa3
AT
2 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
5b7d70c6
BD
4 *
5 * Copyright 2008 Openmoko, Inc.
6 * Copyright 2008 Simtec Electronics
7 * Ben Dooks <ben@simtec.co.uk>
8 * http://armlinux.simtec.co.uk/
9 *
10 * S3C USB2.0 High-speed / OtG driver
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
8b9bc460 15 */
5b7d70c6
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16
17#include <linux/kernel.h>
18#include <linux/module.h>
19#include <linux/spinlock.h>
20#include <linux/interrupt.h>
21#include <linux/platform_device.h>
22#include <linux/dma-mapping.h>
23#include <linux/debugfs.h>
24#include <linux/seq_file.h>
25#include <linux/delay.h>
26#include <linux/io.h>
5a0e3ad6 27#include <linux/slab.h>
e50bf385 28#include <linux/clk.h>
fc9a731e 29#include <linux/regulator/consumer.h>
c50f056c 30#include <linux/of_platform.h>
74084844 31#include <linux/phy/phy.h>
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32
33#include <linux/usb/ch9.h>
34#include <linux/usb/gadget.h>
b2e587db 35#include <linux/usb/phy.h>
126625e1 36#include <linux/platform_data/s3c-hsotg.h>
5b7d70c6 37
f7c0b143 38#include "core.h"
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BD
39
40/* conversion functions */
41static inline struct s3c_hsotg_req *our_req(struct usb_request *req)
42{
43 return container_of(req, struct s3c_hsotg_req, req);
44}
45
46static inline struct s3c_hsotg_ep *our_ep(struct usb_ep *ep)
47{
48 return container_of(ep, struct s3c_hsotg_ep, ep);
49}
50
51static inline struct s3c_hsotg *to_hsotg(struct usb_gadget *gadget)
52{
53 return container_of(gadget, struct s3c_hsotg, gadget);
54}
55
56static inline void __orr32(void __iomem *ptr, u32 val)
57{
58 writel(readl(ptr) | val, ptr);
59}
60
61static inline void __bic32(void __iomem *ptr, u32 val)
62{
63 writel(readl(ptr) & ~val, ptr);
64}
65
66/* forward decleration of functions */
67static void s3c_hsotg_dump(struct s3c_hsotg *hsotg);
68
69/**
70 * using_dma - return the DMA status of the driver.
71 * @hsotg: The driver state.
72 *
73 * Return true if we're using DMA.
74 *
75 * Currently, we have the DMA support code worked into everywhere
76 * that needs it, but the AMBA DMA implementation in the hardware can
77 * only DMA from 32bit aligned addresses. This means that gadgets such
78 * as the CDC Ethernet cannot work as they often pass packets which are
79 * not 32bit aligned.
80 *
81 * Unfortunately the choice to use DMA or not is global to the controller
82 * and seems to be only settable when the controller is being put through
83 * a core reset. This means we either need to fix the gadgets to take
84 * account of DMA alignment, or add bounce buffers (yuerk).
85 *
86 * Until this issue is sorted out, we always return 'false'.
87 */
88static inline bool using_dma(struct s3c_hsotg *hsotg)
89{
90 return false; /* support is not complete */
91}
92
93/**
94 * s3c_hsotg_en_gsint - enable one or more of the general interrupt
95 * @hsotg: The device state
96 * @ints: A bitmask of the interrupts to enable
97 */
98static void s3c_hsotg_en_gsint(struct s3c_hsotg *hsotg, u32 ints)
99{
94cb8fd6 100 u32 gsintmsk = readl(hsotg->regs + GINTMSK);
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BD
101 u32 new_gsintmsk;
102
103 new_gsintmsk = gsintmsk | ints;
104
105 if (new_gsintmsk != gsintmsk) {
106 dev_dbg(hsotg->dev, "gsintmsk now 0x%08x\n", new_gsintmsk);
94cb8fd6 107 writel(new_gsintmsk, hsotg->regs + GINTMSK);
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BD
108 }
109}
110
111/**
112 * s3c_hsotg_disable_gsint - disable one or more of the general interrupt
113 * @hsotg: The device state
114 * @ints: A bitmask of the interrupts to enable
115 */
116static void s3c_hsotg_disable_gsint(struct s3c_hsotg *hsotg, u32 ints)
117{
94cb8fd6 118 u32 gsintmsk = readl(hsotg->regs + GINTMSK);
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BD
119 u32 new_gsintmsk;
120
121 new_gsintmsk = gsintmsk & ~ints;
122
123 if (new_gsintmsk != gsintmsk)
94cb8fd6 124 writel(new_gsintmsk, hsotg->regs + GINTMSK);
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BD
125}
126
127/**
128 * s3c_hsotg_ctrl_epint - enable/disable an endpoint irq
129 * @hsotg: The device state
130 * @ep: The endpoint index
131 * @dir_in: True if direction is in.
132 * @en: The enable value, true to enable
133 *
134 * Set or clear the mask for an individual endpoint's interrupt
135 * request.
136 */
137static void s3c_hsotg_ctrl_epint(struct s3c_hsotg *hsotg,
138 unsigned int ep, unsigned int dir_in,
139 unsigned int en)
140{
141 unsigned long flags;
142 u32 bit = 1 << ep;
143 u32 daint;
144
145 if (!dir_in)
146 bit <<= 16;
147
148 local_irq_save(flags);
94cb8fd6 149 daint = readl(hsotg->regs + DAINTMSK);
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BD
150 if (en)
151 daint |= bit;
152 else
153 daint &= ~bit;
94cb8fd6 154 writel(daint, hsotg->regs + DAINTMSK);
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BD
155 local_irq_restore(flags);
156}
157
158/**
159 * s3c_hsotg_init_fifo - initialise non-periodic FIFOs
160 * @hsotg: The device instance.
161 */
162static void s3c_hsotg_init_fifo(struct s3c_hsotg *hsotg)
163{
0f002d20
BD
164 unsigned int ep;
165 unsigned int addr;
166 unsigned int size;
1703a6d3 167 int timeout;
0f002d20
BD
168 u32 val;
169
6d091ee7 170 /* set FIFO sizes to 2048/1024 */
5b7d70c6 171
94cb8fd6 172 writel(2048, hsotg->regs + GRXFSIZ);
47a1685f
DN
173 writel((2048 << FIFOSIZE_STARTADDR_SHIFT) |
174 (1024 << FIFOSIZE_DEPTH_SHIFT), hsotg->regs + GNPTXFSIZ);
0f002d20 175
8b9bc460
LM
176 /*
177 * arange all the rest of the TX FIFOs, as some versions of this
0f002d20
BD
178 * block have overlapping default addresses. This also ensures
179 * that if the settings have been changed, then they are set to
8b9bc460
LM
180 * known values.
181 */
0f002d20
BD
182
183 /* start at the end of the GNPTXFSIZ, rounded up */
184 addr = 2048 + 1024;
0f002d20 185
8b9bc460 186 /*
b203d0a2
RB
187 * Because we have not enough memory to have each TX FIFO of size at
188 * least 3072 bytes (the maximum single packet size), we create four
189 * FIFOs of lenght 1024, and four of length 3072 bytes, and assing
190 * them to endpoints dynamically according to maxpacket size value of
191 * given endpoint.
8b9bc460 192 */
0f002d20 193
b203d0a2
RB
194 /* 256*4=1024 bytes FIFO length */
195 size = 256;
196 for (ep = 1; ep <= 4; ep++) {
197 val = addr;
198 val |= size << FIFOSIZE_DEPTH_SHIFT;
199 WARN_ONCE(addr + size > hsotg->fifo_mem,
200 "insufficient fifo memory");
201 addr += size;
202
203 writel(val, hsotg->regs + DPTXFSIZN(ep));
204 }
205 /* 768*4=3072 bytes FIFO length */
206 size = 768;
207 for (ep = 5; ep <= 8; ep++) {
0f002d20 208 val = addr;
47a1685f 209 val |= size << FIFOSIZE_DEPTH_SHIFT;
cff9eb75
MS
210 WARN_ONCE(addr + size > hsotg->fifo_mem,
211 "insufficient fifo memory");
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BD
212 addr += size;
213
47a1685f 214 writel(val, hsotg->regs + DPTXFSIZN(ep));
0f002d20 215 }
1703a6d3 216
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LM
217 /*
218 * according to p428 of the design guide, we need to ensure that
219 * all fifos are flushed before continuing
220 */
1703a6d3 221
47a1685f
DN
222 writel(GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH |
223 GRSTCTL_RXFFLSH, hsotg->regs + GRSTCTL);
1703a6d3
BD
224
225 /* wait until the fifos are both flushed */
226 timeout = 100;
227 while (1) {
94cb8fd6 228 val = readl(hsotg->regs + GRSTCTL);
1703a6d3 229
47a1685f 230 if ((val & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH)) == 0)
1703a6d3
BD
231 break;
232
233 if (--timeout == 0) {
234 dev_err(hsotg->dev,
235 "%s: timeout flushing fifos (GRSTCTL=%08x)\n",
236 __func__, val);
237 }
238
239 udelay(1);
240 }
241
242 dev_dbg(hsotg->dev, "FIFOs reset, timeout at %d\n", timeout);
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BD
243}
244
245/**
246 * @ep: USB endpoint to allocate request for.
247 * @flags: Allocation flags
248 *
249 * Allocate a new USB request structure appropriate for the specified endpoint
250 */
0978f8c5
MB
251static struct usb_request *s3c_hsotg_ep_alloc_request(struct usb_ep *ep,
252 gfp_t flags)
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BD
253{
254 struct s3c_hsotg_req *req;
255
256 req = kzalloc(sizeof(struct s3c_hsotg_req), flags);
257 if (!req)
258 return NULL;
259
260 INIT_LIST_HEAD(&req->queue);
261
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BD
262 return &req->req;
263}
264
265/**
266 * is_ep_periodic - return true if the endpoint is in periodic mode.
267 * @hs_ep: The endpoint to query.
268 *
269 * Returns true if the endpoint is in periodic mode, meaning it is being
270 * used for an Interrupt or ISO transfer.
271 */
272static inline int is_ep_periodic(struct s3c_hsotg_ep *hs_ep)
273{
274 return hs_ep->periodic;
275}
276
277/**
278 * s3c_hsotg_unmap_dma - unmap the DMA memory being used for the request
279 * @hsotg: The device state.
280 * @hs_ep: The endpoint for the request
281 * @hs_req: The request being processed.
282 *
283 * This is the reverse of s3c_hsotg_map_dma(), called for the completion
284 * of a request to ensure the buffer is ready for access by the caller.
8b9bc460 285 */
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BD
286static void s3c_hsotg_unmap_dma(struct s3c_hsotg *hsotg,
287 struct s3c_hsotg_ep *hs_ep,
288 struct s3c_hsotg_req *hs_req)
289{
290 struct usb_request *req = &hs_req->req;
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BD
291
292 /* ignore this if we're not moving any data */
293 if (hs_req->req.length == 0)
294 return;
295
17d966a3 296 usb_gadget_unmap_request(&hsotg->gadget, req, hs_ep->dir_in);
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BD
297}
298
299/**
300 * s3c_hsotg_write_fifo - write packet Data to the TxFIFO
301 * @hsotg: The controller state.
302 * @hs_ep: The endpoint we're going to write for.
303 * @hs_req: The request to write data for.
304 *
305 * This is called when the TxFIFO has some space in it to hold a new
306 * transmission and we have something to give it. The actual setup of
307 * the data size is done elsewhere, so all we have to do is to actually
308 * write the data.
309 *
310 * The return value is zero if there is more space (or nothing was done)
311 * otherwise -ENOSPC is returned if the FIFO space was used up.
312 *
313 * This routine is only needed for PIO
8b9bc460 314 */
5b7d70c6
BD
315static int s3c_hsotg_write_fifo(struct s3c_hsotg *hsotg,
316 struct s3c_hsotg_ep *hs_ep,
317 struct s3c_hsotg_req *hs_req)
318{
319 bool periodic = is_ep_periodic(hs_ep);
94cb8fd6 320 u32 gnptxsts = readl(hsotg->regs + GNPTXSTS);
5b7d70c6
BD
321 int buf_pos = hs_req->req.actual;
322 int to_write = hs_ep->size_loaded;
323 void *data;
324 int can_write;
325 int pkt_round;
4fca54aa 326 int max_transfer;
5b7d70c6
BD
327
328 to_write -= (buf_pos - hs_ep->last_load);
329
330 /* if there's nothing to write, get out early */
331 if (to_write == 0)
332 return 0;
333
10aebc77 334 if (periodic && !hsotg->dedicated_fifos) {
94cb8fd6 335 u32 epsize = readl(hsotg->regs + DIEPTSIZ(hs_ep->index));
5b7d70c6
BD
336 int size_left;
337 int size_done;
338
8b9bc460
LM
339 /*
340 * work out how much data was loaded so we can calculate
341 * how much data is left in the fifo.
342 */
5b7d70c6 343
47a1685f 344 size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
5b7d70c6 345
8b9bc460
LM
346 /*
347 * if shared fifo, we cannot write anything until the
e7a9ff54
BD
348 * previous data has been completely sent.
349 */
350 if (hs_ep->fifo_load != 0) {
47a1685f 351 s3c_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP);
e7a9ff54
BD
352 return -ENOSPC;
353 }
354
5b7d70c6
BD
355 dev_dbg(hsotg->dev, "%s: left=%d, load=%d, fifo=%d, size %d\n",
356 __func__, size_left,
357 hs_ep->size_loaded, hs_ep->fifo_load, hs_ep->fifo_size);
358
359 /* how much of the data has moved */
360 size_done = hs_ep->size_loaded - size_left;
361
362 /* how much data is left in the fifo */
363 can_write = hs_ep->fifo_load - size_done;
364 dev_dbg(hsotg->dev, "%s: => can_write1=%d\n",
365 __func__, can_write);
366
367 can_write = hs_ep->fifo_size - can_write;
368 dev_dbg(hsotg->dev, "%s: => can_write2=%d\n",
369 __func__, can_write);
370
371 if (can_write <= 0) {
47a1685f 372 s3c_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP);
5b7d70c6
BD
373 return -ENOSPC;
374 }
10aebc77 375 } else if (hsotg->dedicated_fifos && hs_ep->index != 0) {
94cb8fd6 376 can_write = readl(hsotg->regs + DTXFSTS(hs_ep->index));
10aebc77
BD
377
378 can_write &= 0xffff;
379 can_write *= 4;
5b7d70c6 380 } else {
47a1685f 381 if (GNPTXSTS_NP_TXQ_SPC_AVAIL_GET(gnptxsts) == 0) {
5b7d70c6
BD
382 dev_dbg(hsotg->dev,
383 "%s: no queue slots available (0x%08x)\n",
384 __func__, gnptxsts);
385
47a1685f 386 s3c_hsotg_en_gsint(hsotg, GINTSTS_NPTXFEMP);
5b7d70c6
BD
387 return -ENOSPC;
388 }
389
47a1685f 390 can_write = GNPTXSTS_NP_TXF_SPC_AVAIL_GET(gnptxsts);
679f9b7c 391 can_write *= 4; /* fifo size is in 32bit quantities. */
5b7d70c6
BD
392 }
393
4fca54aa
RB
394 max_transfer = hs_ep->ep.maxpacket * hs_ep->mc;
395
396 dev_dbg(hsotg->dev, "%s: GNPTXSTS=%08x, can=%d, to=%d, max_transfer %d\n",
397 __func__, gnptxsts, can_write, to_write, max_transfer);
5b7d70c6 398
8b9bc460
LM
399 /*
400 * limit to 512 bytes of data, it seems at least on the non-periodic
5b7d70c6
BD
401 * FIFO, requests of >512 cause the endpoint to get stuck with a
402 * fragment of the end of the transfer in it.
403 */
811f3303 404 if (can_write > 512 && !periodic)
5b7d70c6
BD
405 can_write = 512;
406
8b9bc460
LM
407 /*
408 * limit the write to one max-packet size worth of data, but allow
03e10e5a 409 * the transfer to return that it did not run out of fifo space
8b9bc460
LM
410 * doing it.
411 */
4fca54aa
RB
412 if (to_write > max_transfer) {
413 to_write = max_transfer;
03e10e5a 414
5cb2ff0c
RB
415 /* it's needed only when we do not use dedicated fifos */
416 if (!hsotg->dedicated_fifos)
417 s3c_hsotg_en_gsint(hsotg,
47a1685f
DN
418 periodic ? GINTSTS_PTXFEMP :
419 GINTSTS_NPTXFEMP);
03e10e5a
BD
420 }
421
5b7d70c6
BD
422 /* see if we can write data */
423
424 if (to_write > can_write) {
425 to_write = can_write;
4fca54aa 426 pkt_round = to_write % max_transfer;
5b7d70c6 427
8b9bc460
LM
428 /*
429 * Round the write down to an
5b7d70c6
BD
430 * exact number of packets.
431 *
432 * Note, we do not currently check to see if we can ever
433 * write a full packet or not to the FIFO.
434 */
435
436 if (pkt_round)
437 to_write -= pkt_round;
438
8b9bc460
LM
439 /*
440 * enable correct FIFO interrupt to alert us when there
441 * is more room left.
442 */
5b7d70c6 443
5cb2ff0c
RB
444 /* it's needed only when we do not use dedicated fifos */
445 if (!hsotg->dedicated_fifos)
446 s3c_hsotg_en_gsint(hsotg,
47a1685f
DN
447 periodic ? GINTSTS_PTXFEMP :
448 GINTSTS_NPTXFEMP);
5b7d70c6
BD
449 }
450
451 dev_dbg(hsotg->dev, "write %d/%d, can_write %d, done %d\n",
452 to_write, hs_req->req.length, can_write, buf_pos);
453
454 if (to_write <= 0)
455 return -ENOSPC;
456
457 hs_req->req.actual = buf_pos + to_write;
458 hs_ep->total_data += to_write;
459
460 if (periodic)
461 hs_ep->fifo_load += to_write;
462
463 to_write = DIV_ROUND_UP(to_write, 4);
464 data = hs_req->req.buf + buf_pos;
465
1a7ed5be 466 iowrite32_rep(hsotg->regs + EPFIFO(hs_ep->index), data, to_write);
5b7d70c6
BD
467
468 return (to_write >= can_write) ? -ENOSPC : 0;
469}
470
471/**
472 * get_ep_limit - get the maximum data legnth for this endpoint
473 * @hs_ep: The endpoint
474 *
475 * Return the maximum data that can be queued in one go on a given endpoint
476 * so that transfers that are too long can be split.
477 */
478static unsigned get_ep_limit(struct s3c_hsotg_ep *hs_ep)
479{
480 int index = hs_ep->index;
481 unsigned maxsize;
482 unsigned maxpkt;
483
484 if (index != 0) {
47a1685f
DN
485 maxsize = DXEPTSIZ_XFERSIZE_LIMIT + 1;
486 maxpkt = DXEPTSIZ_PKTCNT_LIMIT + 1;
5b7d70c6 487 } else {
b05ca580 488 maxsize = 64+64;
66e5c643 489 if (hs_ep->dir_in)
47a1685f 490 maxpkt = DIEPTSIZ0_PKTCNT_LIMIT + 1;
66e5c643 491 else
5b7d70c6 492 maxpkt = 2;
5b7d70c6
BD
493 }
494
495 /* we made the constant loading easier above by using +1 */
496 maxpkt--;
497 maxsize--;
498
8b9bc460
LM
499 /*
500 * constrain by packet count if maxpkts*pktsize is greater
501 * than the length register size.
502 */
5b7d70c6
BD
503
504 if ((maxpkt * hs_ep->ep.maxpacket) < maxsize)
505 maxsize = maxpkt * hs_ep->ep.maxpacket;
506
507 return maxsize;
508}
509
510/**
511 * s3c_hsotg_start_req - start a USB request from an endpoint's queue
512 * @hsotg: The controller state.
513 * @hs_ep: The endpoint to process a request for
514 * @hs_req: The request to start.
515 * @continuing: True if we are doing more for the current request.
516 *
517 * Start the given request running by setting the endpoint registers
518 * appropriately, and writing any data to the FIFOs.
519 */
520static void s3c_hsotg_start_req(struct s3c_hsotg *hsotg,
521 struct s3c_hsotg_ep *hs_ep,
522 struct s3c_hsotg_req *hs_req,
523 bool continuing)
524{
525 struct usb_request *ureq = &hs_req->req;
526 int index = hs_ep->index;
527 int dir_in = hs_ep->dir_in;
528 u32 epctrl_reg;
529 u32 epsize_reg;
530 u32 epsize;
531 u32 ctrl;
532 unsigned length;
533 unsigned packets;
534 unsigned maxreq;
535
536 if (index != 0) {
537 if (hs_ep->req && !continuing) {
538 dev_err(hsotg->dev, "%s: active request\n", __func__);
539 WARN_ON(1);
540 return;
541 } else if (hs_ep->req != hs_req && continuing) {
542 dev_err(hsotg->dev,
543 "%s: continue different req\n", __func__);
544 WARN_ON(1);
545 return;
546 }
547 }
548
94cb8fd6
LM
549 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
550 epsize_reg = dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index);
5b7d70c6
BD
551
552 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n",
553 __func__, readl(hsotg->regs + epctrl_reg), index,
554 hs_ep->dir_in ? "in" : "out");
555
9c39ddc6
AT
556 /* If endpoint is stalled, we will restart request later */
557 ctrl = readl(hsotg->regs + epctrl_reg);
558
47a1685f 559 if (ctrl & DXEPCTL_STALL) {
9c39ddc6
AT
560 dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index);
561 return;
562 }
563
5b7d70c6 564 length = ureq->length - ureq->actual;
71225bee
LM
565 dev_dbg(hsotg->dev, "ureq->length:%d ureq->actual:%d\n",
566 ureq->length, ureq->actual);
5b7d70c6
BD
567 if (0)
568 dev_dbg(hsotg->dev,
0cc4cf6f 569 "REQ buf %p len %d dma %pad noi=%d zp=%d snok=%d\n",
8b3bc14f 570 ureq->buf, length, &ureq->dma,
5b7d70c6
BD
571 ureq->no_interrupt, ureq->zero, ureq->short_not_ok);
572
573 maxreq = get_ep_limit(hs_ep);
574 if (length > maxreq) {
575 int round = maxreq % hs_ep->ep.maxpacket;
576
577 dev_dbg(hsotg->dev, "%s: length %d, max-req %d, r %d\n",
578 __func__, length, maxreq, round);
579
580 /* round down to multiple of packets */
581 if (round)
582 maxreq -= round;
583
584 length = maxreq;
585 }
586
587 if (length)
588 packets = DIV_ROUND_UP(length, hs_ep->ep.maxpacket);
589 else
590 packets = 1; /* send one packet if length is zero. */
591
4fca54aa
RB
592 if (hs_ep->isochronous && length > (hs_ep->mc * hs_ep->ep.maxpacket)) {
593 dev_err(hsotg->dev, "req length > maxpacket*mc\n");
594 return;
595 }
596
5b7d70c6 597 if (dir_in && index != 0)
4fca54aa 598 if (hs_ep->isochronous)
47a1685f 599 epsize = DXEPTSIZ_MC(packets);
4fca54aa 600 else
47a1685f 601 epsize = DXEPTSIZ_MC(1);
5b7d70c6
BD
602 else
603 epsize = 0;
604
605 if (index != 0 && ureq->zero) {
8b9bc460
LM
606 /*
607 * test for the packets being exactly right for the
608 * transfer
609 */
5b7d70c6
BD
610
611 if (length == (packets * hs_ep->ep.maxpacket))
612 packets++;
613 }
614
47a1685f
DN
615 epsize |= DXEPTSIZ_PKTCNT(packets);
616 epsize |= DXEPTSIZ_XFERSIZE(length);
5b7d70c6
BD
617
618 dev_dbg(hsotg->dev, "%s: %d@%d/%d, 0x%08x => 0x%08x\n",
619 __func__, packets, length, ureq->length, epsize, epsize_reg);
620
621 /* store the request as the current one we're doing */
622 hs_ep->req = hs_req;
623
624 /* write size / packets */
625 writel(epsize, hsotg->regs + epsize_reg);
626
db1d8ba3 627 if (using_dma(hsotg) && !continuing) {
5b7d70c6
BD
628 unsigned int dma_reg;
629
8b9bc460
LM
630 /*
631 * write DMA address to control register, buffer already
632 * synced by s3c_hsotg_ep_queue().
633 */
5b7d70c6 634
94cb8fd6 635 dma_reg = dir_in ? DIEPDMA(index) : DOEPDMA(index);
5b7d70c6
BD
636 writel(ureq->dma, hsotg->regs + dma_reg);
637
0cc4cf6f 638 dev_dbg(hsotg->dev, "%s: %pad => 0x%08x\n",
8b3bc14f 639 __func__, &ureq->dma, dma_reg);
5b7d70c6
BD
640 }
641
47a1685f
DN
642 ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */
643 ctrl |= DXEPCTL_USBACTEP;
71225bee
LM
644
645 dev_dbg(hsotg->dev, "setup req:%d\n", hsotg->setup);
646
647 /* For Setup request do not clear NAK */
648 if (hsotg->setup && index == 0)
649 hsotg->setup = 0;
650 else
47a1685f 651 ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */
71225bee 652
5b7d70c6
BD
653
654 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
655 writel(ctrl, hsotg->regs + epctrl_reg);
656
8b9bc460
LM
657 /*
658 * set these, it seems that DMA support increments past the end
5b7d70c6 659 * of the packet buffer so we need to calculate the length from
8b9bc460
LM
660 * this information.
661 */
5b7d70c6
BD
662 hs_ep->size_loaded = length;
663 hs_ep->last_load = ureq->actual;
664
665 if (dir_in && !using_dma(hsotg)) {
666 /* set these anyway, we may need them for non-periodic in */
667 hs_ep->fifo_load = 0;
668
669 s3c_hsotg_write_fifo(hsotg, hs_ep, hs_req);
670 }
671
8b9bc460
LM
672 /*
673 * clear the INTknTXFEmpMsk when we start request, more as a aide
674 * to debugging to see what is going on.
675 */
5b7d70c6 676 if (dir_in)
47a1685f 677 writel(DIEPMSK_INTKNTXFEMPMSK,
94cb8fd6 678 hsotg->regs + DIEPINT(index));
5b7d70c6 679
8b9bc460
LM
680 /*
681 * Note, trying to clear the NAK here causes problems with transmit
682 * on the S3C6400 ending up with the TXFIFO becoming full.
683 */
5b7d70c6
BD
684
685 /* check ep is enabled */
47a1685f 686 if (!(readl(hsotg->regs + epctrl_reg) & DXEPCTL_EPENA))
5b7d70c6 687 dev_warn(hsotg->dev,
47a1685f 688 "ep%d: failed to become enabled (DXEPCTL=0x%08x)?\n",
5b7d70c6
BD
689 index, readl(hsotg->regs + epctrl_reg));
690
47a1685f 691 dev_dbg(hsotg->dev, "%s: DXEPCTL=0x%08x\n",
5b7d70c6 692 __func__, readl(hsotg->regs + epctrl_reg));
afcf4169
RB
693
694 /* enable ep interrupts */
695 s3c_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 1);
5b7d70c6
BD
696}
697
698/**
699 * s3c_hsotg_map_dma - map the DMA memory being used for the request
700 * @hsotg: The device state.
701 * @hs_ep: The endpoint the request is on.
702 * @req: The request being processed.
703 *
704 * We've been asked to queue a request, so ensure that the memory buffer
705 * is correctly setup for DMA. If we've been passed an extant DMA address
706 * then ensure the buffer has been synced to memory. If our buffer has no
707 * DMA memory, then we map the memory and mark our request to allow us to
708 * cleanup on completion.
8b9bc460 709 */
5b7d70c6
BD
710static int s3c_hsotg_map_dma(struct s3c_hsotg *hsotg,
711 struct s3c_hsotg_ep *hs_ep,
712 struct usb_request *req)
713{
5b7d70c6 714 struct s3c_hsotg_req *hs_req = our_req(req);
e58ebcd1 715 int ret;
5b7d70c6
BD
716
717 /* if the length is zero, ignore the DMA data */
718 if (hs_req->req.length == 0)
719 return 0;
720
e58ebcd1
FB
721 ret = usb_gadget_map_request(&hsotg->gadget, req, hs_ep->dir_in);
722 if (ret)
723 goto dma_error;
5b7d70c6
BD
724
725 return 0;
726
727dma_error:
728 dev_err(hsotg->dev, "%s: failed to map buffer %p, %d bytes\n",
729 __func__, req->buf, req->length);
730
731 return -EIO;
732}
733
734static int s3c_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req,
735 gfp_t gfp_flags)
736{
737 struct s3c_hsotg_req *hs_req = our_req(req);
738 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
739 struct s3c_hsotg *hs = hs_ep->parent;
5b7d70c6
BD
740 bool first;
741
742 dev_dbg(hs->dev, "%s: req %p: %d@%p, noi=%d, zero=%d, snok=%d\n",
743 ep->name, req, req->length, req->buf, req->no_interrupt,
744 req->zero, req->short_not_ok);
745
746 /* initialise status of the request */
747 INIT_LIST_HEAD(&hs_req->queue);
748 req->actual = 0;
749 req->status = -EINPROGRESS;
750
751 /* if we're using DMA, sync the buffers as necessary */
752 if (using_dma(hs)) {
753 int ret = s3c_hsotg_map_dma(hs, hs_ep, req);
754 if (ret)
755 return ret;
756 }
757
5b7d70c6
BD
758 first = list_empty(&hs_ep->queue);
759 list_add_tail(&hs_req->queue, &hs_ep->queue);
760
761 if (first)
762 s3c_hsotg_start_req(hs, hs_ep, hs_req, false);
763
5b7d70c6
BD
764 return 0;
765}
766
5ad1d316
LM
767static int s3c_hsotg_ep_queue_lock(struct usb_ep *ep, struct usb_request *req,
768 gfp_t gfp_flags)
769{
770 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
771 struct s3c_hsotg *hs = hs_ep->parent;
772 unsigned long flags = 0;
773 int ret = 0;
774
775 spin_lock_irqsave(&hs->lock, flags);
776 ret = s3c_hsotg_ep_queue(ep, req, gfp_flags);
777 spin_unlock_irqrestore(&hs->lock, flags);
778
779 return ret;
780}
781
5b7d70c6
BD
782static void s3c_hsotg_ep_free_request(struct usb_ep *ep,
783 struct usb_request *req)
784{
785 struct s3c_hsotg_req *hs_req = our_req(req);
786
787 kfree(hs_req);
788}
789
790/**
791 * s3c_hsotg_complete_oursetup - setup completion callback
792 * @ep: The endpoint the request was on.
793 * @req: The request completed.
794 *
795 * Called on completion of any requests the driver itself
796 * submitted that need cleaning up.
797 */
798static void s3c_hsotg_complete_oursetup(struct usb_ep *ep,
799 struct usb_request *req)
800{
801 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
802 struct s3c_hsotg *hsotg = hs_ep->parent;
803
804 dev_dbg(hsotg->dev, "%s: ep %p, req %p\n", __func__, ep, req);
805
806 s3c_hsotg_ep_free_request(ep, req);
807}
808
809/**
810 * ep_from_windex - convert control wIndex value to endpoint
811 * @hsotg: The driver state.
812 * @windex: The control request wIndex field (in host order).
813 *
814 * Convert the given wIndex into a pointer to an driver endpoint
815 * structure, or return NULL if it is not a valid endpoint.
8b9bc460 816 */
5b7d70c6
BD
817static struct s3c_hsotg_ep *ep_from_windex(struct s3c_hsotg *hsotg,
818 u32 windex)
819{
820 struct s3c_hsotg_ep *ep = &hsotg->eps[windex & 0x7F];
821 int dir = (windex & USB_DIR_IN) ? 1 : 0;
822 int idx = windex & 0x7F;
823
824 if (windex >= 0x100)
825 return NULL;
826
b3f489b2 827 if (idx > hsotg->num_of_eps)
5b7d70c6
BD
828 return NULL;
829
830 if (idx && ep->dir_in != dir)
831 return NULL;
832
833 return ep;
834}
835
836/**
837 * s3c_hsotg_send_reply - send reply to control request
838 * @hsotg: The device state
839 * @ep: Endpoint 0
840 * @buff: Buffer for request
841 * @length: Length of reply.
842 *
843 * Create a request and queue it on the given endpoint. This is useful as
844 * an internal method of sending replies to certain control requests, etc.
845 */
846static int s3c_hsotg_send_reply(struct s3c_hsotg *hsotg,
847 struct s3c_hsotg_ep *ep,
848 void *buff,
849 int length)
850{
851 struct usb_request *req;
852 int ret;
853
854 dev_dbg(hsotg->dev, "%s: buff %p, len %d\n", __func__, buff, length);
855
856 req = s3c_hsotg_ep_alloc_request(&ep->ep, GFP_ATOMIC);
857 hsotg->ep0_reply = req;
858 if (!req) {
859 dev_warn(hsotg->dev, "%s: cannot alloc req\n", __func__);
860 return -ENOMEM;
861 }
862
863 req->buf = hsotg->ep0_buff;
864 req->length = length;
865 req->zero = 1; /* always do zero-length final transfer */
866 req->complete = s3c_hsotg_complete_oursetup;
867
868 if (length)
869 memcpy(req->buf, buff, length);
870 else
871 ep->sent_zlp = 1;
872
873 ret = s3c_hsotg_ep_queue(&ep->ep, req, GFP_ATOMIC);
874 if (ret) {
875 dev_warn(hsotg->dev, "%s: cannot queue req\n", __func__);
876 return ret;
877 }
878
879 return 0;
880}
881
882/**
883 * s3c_hsotg_process_req_status - process request GET_STATUS
884 * @hsotg: The device state
885 * @ctrl: USB control request
886 */
887static int s3c_hsotg_process_req_status(struct s3c_hsotg *hsotg,
888 struct usb_ctrlrequest *ctrl)
889{
890 struct s3c_hsotg_ep *ep0 = &hsotg->eps[0];
891 struct s3c_hsotg_ep *ep;
892 __le16 reply;
893 int ret;
894
895 dev_dbg(hsotg->dev, "%s: USB_REQ_GET_STATUS\n", __func__);
896
897 if (!ep0->dir_in) {
898 dev_warn(hsotg->dev, "%s: direction out?\n", __func__);
899 return -EINVAL;
900 }
901
902 switch (ctrl->bRequestType & USB_RECIP_MASK) {
903 case USB_RECIP_DEVICE:
904 reply = cpu_to_le16(0); /* bit 0 => self powered,
905 * bit 1 => remote wakeup */
906 break;
907
908 case USB_RECIP_INTERFACE:
909 /* currently, the data result should be zero */
910 reply = cpu_to_le16(0);
911 break;
912
913 case USB_RECIP_ENDPOINT:
914 ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex));
915 if (!ep)
916 return -ENOENT;
917
918 reply = cpu_to_le16(ep->halted ? 1 : 0);
919 break;
920
921 default:
922 return 0;
923 }
924
925 if (le16_to_cpu(ctrl->wLength) != 2)
926 return -EINVAL;
927
928 ret = s3c_hsotg_send_reply(hsotg, ep0, &reply, 2);
929 if (ret) {
930 dev_err(hsotg->dev, "%s: failed to send reply\n", __func__);
931 return ret;
932 }
933
934 return 1;
935}
936
937static int s3c_hsotg_ep_sethalt(struct usb_ep *ep, int value);
938
9c39ddc6
AT
939/**
940 * get_ep_head - return the first request on the endpoint
941 * @hs_ep: The controller endpoint to get
942 *
943 * Get the first request on the endpoint.
944 */
945static struct s3c_hsotg_req *get_ep_head(struct s3c_hsotg_ep *hs_ep)
946{
947 if (list_empty(&hs_ep->queue))
948 return NULL;
949
950 return list_first_entry(&hs_ep->queue, struct s3c_hsotg_req, queue);
951}
952
5b7d70c6
BD
953/**
954 * s3c_hsotg_process_req_featire - process request {SET,CLEAR}_FEATURE
955 * @hsotg: The device state
956 * @ctrl: USB control request
957 */
958static int s3c_hsotg_process_req_feature(struct s3c_hsotg *hsotg,
959 struct usb_ctrlrequest *ctrl)
960{
26ab3d0c 961 struct s3c_hsotg_ep *ep0 = &hsotg->eps[0];
9c39ddc6
AT
962 struct s3c_hsotg_req *hs_req;
963 bool restart;
5b7d70c6
BD
964 bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE);
965 struct s3c_hsotg_ep *ep;
26ab3d0c 966 int ret;
bd9ef7bf 967 bool halted;
5b7d70c6
BD
968
969 dev_dbg(hsotg->dev, "%s: %s_FEATURE\n",
970 __func__, set ? "SET" : "CLEAR");
971
972 if (ctrl->bRequestType == USB_RECIP_ENDPOINT) {
973 ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex));
974 if (!ep) {
975 dev_dbg(hsotg->dev, "%s: no endpoint for 0x%04x\n",
976 __func__, le16_to_cpu(ctrl->wIndex));
977 return -ENOENT;
978 }
979
980 switch (le16_to_cpu(ctrl->wValue)) {
981 case USB_ENDPOINT_HALT:
bd9ef7bf
RB
982 halted = ep->halted;
983
5b7d70c6 984 s3c_hsotg_ep_sethalt(&ep->ep, set);
26ab3d0c
AT
985
986 ret = s3c_hsotg_send_reply(hsotg, ep0, NULL, 0);
987 if (ret) {
988 dev_err(hsotg->dev,
989 "%s: failed to send reply\n", __func__);
990 return ret;
991 }
9c39ddc6 992
bd9ef7bf
RB
993 /*
994 * we have to complete all requests for ep if it was
995 * halted, and the halt was cleared by CLEAR_FEATURE
996 */
997
998 if (!set && halted) {
9c39ddc6
AT
999 /*
1000 * If we have request in progress,
1001 * then complete it
1002 */
1003 if (ep->req) {
1004 hs_req = ep->req;
1005 ep->req = NULL;
1006 list_del_init(&hs_req->queue);
1007 hs_req->req.complete(&ep->ep,
1008 &hs_req->req);
1009 }
1010
1011 /* If we have pending request, then start it */
1012 restart = !list_empty(&ep->queue);
1013 if (restart) {
1014 hs_req = get_ep_head(ep);
1015 s3c_hsotg_start_req(hsotg, ep,
1016 hs_req, false);
1017 }
1018 }
1019
5b7d70c6
BD
1020 break;
1021
1022 default:
1023 return -ENOENT;
1024 }
1025 } else
1026 return -ENOENT; /* currently only deal with endpoint */
1027
1028 return 1;
1029}
1030
ab93e014 1031static void s3c_hsotg_enqueue_setup(struct s3c_hsotg *hsotg);
d18f7116 1032static void s3c_hsotg_disconnect(struct s3c_hsotg *hsotg);
ab93e014 1033
c9f721b2
RB
1034/**
1035 * s3c_hsotg_stall_ep0 - stall ep0
1036 * @hsotg: The device state
1037 *
1038 * Set stall for ep0 as response for setup request.
1039 */
e9ebe7c3
JH
1040static void s3c_hsotg_stall_ep0(struct s3c_hsotg *hsotg)
1041{
c9f721b2
RB
1042 struct s3c_hsotg_ep *ep0 = &hsotg->eps[0];
1043 u32 reg;
1044 u32 ctrl;
1045
1046 dev_dbg(hsotg->dev, "ep0 stall (dir=%d)\n", ep0->dir_in);
1047 reg = (ep0->dir_in) ? DIEPCTL0 : DOEPCTL0;
1048
1049 /*
1050 * DxEPCTL_Stall will be cleared by EP once it has
1051 * taken effect, so no need to clear later.
1052 */
1053
1054 ctrl = readl(hsotg->regs + reg);
47a1685f
DN
1055 ctrl |= DXEPCTL_STALL;
1056 ctrl |= DXEPCTL_CNAK;
c9f721b2
RB
1057 writel(ctrl, hsotg->regs + reg);
1058
1059 dev_dbg(hsotg->dev,
47a1685f 1060 "written DXEPCTL=0x%08x to %08x (DXEPCTL=0x%08x)\n",
c9f721b2
RB
1061 ctrl, reg, readl(hsotg->regs + reg));
1062
1063 /*
1064 * complete won't be called, so we enqueue
1065 * setup request here
1066 */
1067 s3c_hsotg_enqueue_setup(hsotg);
1068}
1069
5b7d70c6
BD
1070/**
1071 * s3c_hsotg_process_control - process a control request
1072 * @hsotg: The device state
1073 * @ctrl: The control request received
1074 *
1075 * The controller has received the SETUP phase of a control request, and
1076 * needs to work out what to do next (and whether to pass it on to the
1077 * gadget driver).
1078 */
1079static void s3c_hsotg_process_control(struct s3c_hsotg *hsotg,
1080 struct usb_ctrlrequest *ctrl)
1081{
1082 struct s3c_hsotg_ep *ep0 = &hsotg->eps[0];
1083 int ret = 0;
1084 u32 dcfg;
1085
1086 ep0->sent_zlp = 0;
1087
1088 dev_dbg(hsotg->dev, "ctrl Req=%02x, Type=%02x, V=%04x, L=%04x\n",
1089 ctrl->bRequest, ctrl->bRequestType,
1090 ctrl->wValue, ctrl->wLength);
1091
8b9bc460
LM
1092 /*
1093 * record the direction of the request, for later use when enquing
1094 * packets onto EP0.
1095 */
5b7d70c6
BD
1096
1097 ep0->dir_in = (ctrl->bRequestType & USB_DIR_IN) ? 1 : 0;
1098 dev_dbg(hsotg->dev, "ctrl: dir_in=%d\n", ep0->dir_in);
1099
8b9bc460
LM
1100 /*
1101 * if we've no data with this request, then the last part of the
1102 * transaction is going to implicitly be IN.
1103 */
5b7d70c6
BD
1104 if (ctrl->wLength == 0)
1105 ep0->dir_in = 1;
1106
1107 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
1108 switch (ctrl->bRequest) {
1109 case USB_REQ_SET_ADDRESS:
d18f7116 1110 s3c_hsotg_disconnect(hsotg);
94cb8fd6 1111 dcfg = readl(hsotg->regs + DCFG);
47a1685f 1112 dcfg &= ~DCFG_DEVADDR_MASK;
d5dbd3f7
PZ
1113 dcfg |= (le16_to_cpu(ctrl->wValue) <<
1114 DCFG_DEVADDR_SHIFT) & DCFG_DEVADDR_MASK;
94cb8fd6 1115 writel(dcfg, hsotg->regs + DCFG);
5b7d70c6
BD
1116
1117 dev_info(hsotg->dev, "new address %d\n", ctrl->wValue);
1118
1119 ret = s3c_hsotg_send_reply(hsotg, ep0, NULL, 0);
1120 return;
1121
1122 case USB_REQ_GET_STATUS:
1123 ret = s3c_hsotg_process_req_status(hsotg, ctrl);
1124 break;
1125
1126 case USB_REQ_CLEAR_FEATURE:
1127 case USB_REQ_SET_FEATURE:
1128 ret = s3c_hsotg_process_req_feature(hsotg, ctrl);
1129 break;
1130 }
1131 }
1132
1133 /* as a fallback, try delivering it to the driver to deal with */
1134
1135 if (ret == 0 && hsotg->driver) {
93f599f2 1136 spin_unlock(&hsotg->lock);
5b7d70c6 1137 ret = hsotg->driver->setup(&hsotg->gadget, ctrl);
93f599f2 1138 spin_lock(&hsotg->lock);
5b7d70c6
BD
1139 if (ret < 0)
1140 dev_dbg(hsotg->dev, "driver->setup() ret %d\n", ret);
1141 }
1142
8b9bc460
LM
1143 /*
1144 * the request is either unhandlable, or is not formatted correctly
5b7d70c6
BD
1145 * so respond with a STALL for the status stage to indicate failure.
1146 */
1147
c9f721b2
RB
1148 if (ret < 0)
1149 s3c_hsotg_stall_ep0(hsotg);
5b7d70c6
BD
1150}
1151
5b7d70c6
BD
1152/**
1153 * s3c_hsotg_complete_setup - completion of a setup transfer
1154 * @ep: The endpoint the request was on.
1155 * @req: The request completed.
1156 *
1157 * Called on completion of any requests the driver itself submitted for
1158 * EP0 setup packets
1159 */
1160static void s3c_hsotg_complete_setup(struct usb_ep *ep,
1161 struct usb_request *req)
1162{
1163 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
1164 struct s3c_hsotg *hsotg = hs_ep->parent;
1165
1166 if (req->status < 0) {
1167 dev_dbg(hsotg->dev, "%s: failed %d\n", __func__, req->status);
1168 return;
1169 }
1170
93f599f2 1171 spin_lock(&hsotg->lock);
5b7d70c6
BD
1172 if (req->actual == 0)
1173 s3c_hsotg_enqueue_setup(hsotg);
1174 else
1175 s3c_hsotg_process_control(hsotg, req->buf);
93f599f2 1176 spin_unlock(&hsotg->lock);
5b7d70c6
BD
1177}
1178
1179/**
1180 * s3c_hsotg_enqueue_setup - start a request for EP0 packets
1181 * @hsotg: The device state.
1182 *
1183 * Enqueue a request on EP0 if necessary to received any SETUP packets
1184 * received from the host.
1185 */
1186static void s3c_hsotg_enqueue_setup(struct s3c_hsotg *hsotg)
1187{
1188 struct usb_request *req = hsotg->ctrl_req;
1189 struct s3c_hsotg_req *hs_req = our_req(req);
1190 int ret;
1191
1192 dev_dbg(hsotg->dev, "%s: queueing setup request\n", __func__);
1193
1194 req->zero = 0;
1195 req->length = 8;
1196 req->buf = hsotg->ctrl_buff;
1197 req->complete = s3c_hsotg_complete_setup;
1198
1199 if (!list_empty(&hs_req->queue)) {
1200 dev_dbg(hsotg->dev, "%s already queued???\n", __func__);
1201 return;
1202 }
1203
1204 hsotg->eps[0].dir_in = 0;
1205
1206 ret = s3c_hsotg_ep_queue(&hsotg->eps[0].ep, req, GFP_ATOMIC);
1207 if (ret < 0) {
1208 dev_err(hsotg->dev, "%s: failed queue (%d)\n", __func__, ret);
8b9bc460
LM
1209 /*
1210 * Don't think there's much we can do other than watch the
1211 * driver fail.
1212 */
5b7d70c6
BD
1213 }
1214}
1215
5b7d70c6
BD
1216/**
1217 * s3c_hsotg_complete_request - complete a request given to us
1218 * @hsotg: The device state.
1219 * @hs_ep: The endpoint the request was on.
1220 * @hs_req: The request to complete.
1221 * @result: The result code (0 => Ok, otherwise errno)
1222 *
1223 * The given request has finished, so call the necessary completion
1224 * if it has one and then look to see if we can start a new request
1225 * on the endpoint.
1226 *
1227 * Note, expects the ep to already be locked as appropriate.
8b9bc460 1228 */
5b7d70c6
BD
1229static void s3c_hsotg_complete_request(struct s3c_hsotg *hsotg,
1230 struct s3c_hsotg_ep *hs_ep,
1231 struct s3c_hsotg_req *hs_req,
1232 int result)
1233{
1234 bool restart;
1235
1236 if (!hs_req) {
1237 dev_dbg(hsotg->dev, "%s: nothing to complete?\n", __func__);
1238 return;
1239 }
1240
1241 dev_dbg(hsotg->dev, "complete: ep %p %s, req %p, %d => %p\n",
1242 hs_ep, hs_ep->ep.name, hs_req, result, hs_req->req.complete);
1243
8b9bc460
LM
1244 /*
1245 * only replace the status if we've not already set an error
1246 * from a previous transaction
1247 */
5b7d70c6
BD
1248
1249 if (hs_req->req.status == -EINPROGRESS)
1250 hs_req->req.status = result;
1251
1252 hs_ep->req = NULL;
1253 list_del_init(&hs_req->queue);
1254
1255 if (using_dma(hsotg))
1256 s3c_hsotg_unmap_dma(hsotg, hs_ep, hs_req);
1257
8b9bc460
LM
1258 /*
1259 * call the complete request with the locks off, just in case the
1260 * request tries to queue more work for this endpoint.
1261 */
5b7d70c6
BD
1262
1263 if (hs_req->req.complete) {
22258f49 1264 spin_unlock(&hsotg->lock);
5b7d70c6 1265 hs_req->req.complete(&hs_ep->ep, &hs_req->req);
22258f49 1266 spin_lock(&hsotg->lock);
5b7d70c6
BD
1267 }
1268
8b9bc460
LM
1269 /*
1270 * Look to see if there is anything else to do. Note, the completion
5b7d70c6 1271 * of the previous request may have caused a new request to be started
8b9bc460
LM
1272 * so be careful when doing this.
1273 */
5b7d70c6
BD
1274
1275 if (!hs_ep->req && result >= 0) {
1276 restart = !list_empty(&hs_ep->queue);
1277 if (restart) {
1278 hs_req = get_ep_head(hs_ep);
1279 s3c_hsotg_start_req(hsotg, hs_ep, hs_req, false);
1280 }
1281 }
1282}
1283
5b7d70c6
BD
1284/**
1285 * s3c_hsotg_rx_data - receive data from the FIFO for an endpoint
1286 * @hsotg: The device state.
1287 * @ep_idx: The endpoint index for the data
1288 * @size: The size of data in the fifo, in bytes
1289 *
1290 * The FIFO status shows there is data to read from the FIFO for a given
1291 * endpoint, so sort out whether we need to read the data into a request
1292 * that has been made for that endpoint.
1293 */
1294static void s3c_hsotg_rx_data(struct s3c_hsotg *hsotg, int ep_idx, int size)
1295{
1296 struct s3c_hsotg_ep *hs_ep = &hsotg->eps[ep_idx];
1297 struct s3c_hsotg_req *hs_req = hs_ep->req;
94cb8fd6 1298 void __iomem *fifo = hsotg->regs + EPFIFO(ep_idx);
5b7d70c6
BD
1299 int to_read;
1300 int max_req;
1301 int read_ptr;
1302
22258f49 1303
5b7d70c6 1304 if (!hs_req) {
94cb8fd6 1305 u32 epctl = readl(hsotg->regs + DOEPCTL(ep_idx));
5b7d70c6
BD
1306 int ptr;
1307
1308 dev_warn(hsotg->dev,
47a1685f 1309 "%s: FIFO %d bytes on ep%d but no req (DXEPCTl=0x%08x)\n",
5b7d70c6
BD
1310 __func__, size, ep_idx, epctl);
1311
1312 /* dump the data from the FIFO, we've nothing we can do */
1313 for (ptr = 0; ptr < size; ptr += 4)
1314 (void)readl(fifo);
1315
1316 return;
1317 }
1318
5b7d70c6
BD
1319 to_read = size;
1320 read_ptr = hs_req->req.actual;
1321 max_req = hs_req->req.length - read_ptr;
1322
a33e7136
BD
1323 dev_dbg(hsotg->dev, "%s: read %d/%d, done %d/%d\n",
1324 __func__, to_read, max_req, read_ptr, hs_req->req.length);
1325
5b7d70c6 1326 if (to_read > max_req) {
8b9bc460
LM
1327 /*
1328 * more data appeared than we where willing
5b7d70c6
BD
1329 * to deal with in this request.
1330 */
1331
1332 /* currently we don't deal this */
1333 WARN_ON_ONCE(1);
1334 }
1335
5b7d70c6
BD
1336 hs_ep->total_data += to_read;
1337 hs_req->req.actual += to_read;
1338 to_read = DIV_ROUND_UP(to_read, 4);
1339
8b9bc460
LM
1340 /*
1341 * note, we might over-write the buffer end by 3 bytes depending on
1342 * alignment of the data.
1343 */
1a7ed5be 1344 ioread32_rep(fifo, hs_req->req.buf + read_ptr, to_read);
5b7d70c6
BD
1345}
1346
1347/**
1348 * s3c_hsotg_send_zlp - send zero-length packet on control endpoint
1349 * @hsotg: The device instance
1350 * @req: The request currently on this endpoint
1351 *
1352 * Generate a zero-length IN packet request for terminating a SETUP
1353 * transaction.
1354 *
1355 * Note, since we don't write any data to the TxFIFO, then it is
25985edc 1356 * currently believed that we do not need to wait for any space in
5b7d70c6
BD
1357 * the TxFIFO.
1358 */
1359static void s3c_hsotg_send_zlp(struct s3c_hsotg *hsotg,
1360 struct s3c_hsotg_req *req)
1361{
1362 u32 ctrl;
1363
1364 if (!req) {
1365 dev_warn(hsotg->dev, "%s: no request?\n", __func__);
1366 return;
1367 }
1368
1369 if (req->req.length == 0) {
1370 hsotg->eps[0].sent_zlp = 1;
1371 s3c_hsotg_enqueue_setup(hsotg);
1372 return;
1373 }
1374
1375 hsotg->eps[0].dir_in = 1;
1376 hsotg->eps[0].sent_zlp = 1;
1377
1378 dev_dbg(hsotg->dev, "sending zero-length packet\n");
1379
1380 /* issue a zero-sized packet to terminate this */
47a1685f
DN
1381 writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
1382 DXEPTSIZ_XFERSIZE(0), hsotg->regs + DIEPTSIZ(0));
5b7d70c6 1383
94cb8fd6 1384 ctrl = readl(hsotg->regs + DIEPCTL0);
47a1685f
DN
1385 ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */
1386 ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */
1387 ctrl |= DXEPCTL_USBACTEP;
94cb8fd6 1388 writel(ctrl, hsotg->regs + DIEPCTL0);
5b7d70c6
BD
1389}
1390
1391/**
1392 * s3c_hsotg_handle_outdone - handle receiving OutDone/SetupDone from RXFIFO
1393 * @hsotg: The device instance
1394 * @epnum: The endpoint received from
1395 * @was_setup: Set if processing a SetupDone event.
1396 *
1397 * The RXFIFO has delivered an OutDone event, which means that the data
1398 * transfer for an OUT endpoint has been completed, either by a short
1399 * packet or by the finish of a transfer.
8b9bc460 1400 */
5b7d70c6
BD
1401static void s3c_hsotg_handle_outdone(struct s3c_hsotg *hsotg,
1402 int epnum, bool was_setup)
1403{
94cb8fd6 1404 u32 epsize = readl(hsotg->regs + DOEPTSIZ(epnum));
5b7d70c6
BD
1405 struct s3c_hsotg_ep *hs_ep = &hsotg->eps[epnum];
1406 struct s3c_hsotg_req *hs_req = hs_ep->req;
1407 struct usb_request *req = &hs_req->req;
47a1685f 1408 unsigned size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
5b7d70c6
BD
1409 int result = 0;
1410
1411 if (!hs_req) {
1412 dev_dbg(hsotg->dev, "%s: no request active\n", __func__);
1413 return;
1414 }
1415
1416 if (using_dma(hsotg)) {
5b7d70c6 1417 unsigned size_done;
5b7d70c6 1418
8b9bc460
LM
1419 /*
1420 * Calculate the size of the transfer by checking how much
5b7d70c6
BD
1421 * is left in the endpoint size register and then working it
1422 * out from the amount we loaded for the transfer.
1423 *
1424 * We need to do this as DMA pointers are always 32bit aligned
1425 * so may overshoot/undershoot the transfer.
1426 */
1427
5b7d70c6
BD
1428 size_done = hs_ep->size_loaded - size_left;
1429 size_done += hs_ep->last_load;
1430
1431 req->actual = size_done;
1432 }
1433
a33e7136
BD
1434 /* if there is more request to do, schedule new transfer */
1435 if (req->actual < req->length && size_left == 0) {
1436 s3c_hsotg_start_req(hsotg, hs_ep, hs_req, true);
1437 return;
71225bee
LM
1438 } else if (epnum == 0) {
1439 /*
1440 * After was_setup = 1 =>
1441 * set CNAK for non Setup requests
1442 */
1443 hsotg->setup = was_setup ? 0 : 1;
a33e7136
BD
1444 }
1445
5b7d70c6
BD
1446 if (req->actual < req->length && req->short_not_ok) {
1447 dev_dbg(hsotg->dev, "%s: got %d/%d (short not ok) => error\n",
1448 __func__, req->actual, req->length);
1449
8b9bc460
LM
1450 /*
1451 * todo - what should we return here? there's no one else
1452 * even bothering to check the status.
1453 */
5b7d70c6
BD
1454 }
1455
1456 if (epnum == 0) {
d3ca0259
LM
1457 /*
1458 * Condition req->complete != s3c_hsotg_complete_setup says:
1459 * send ZLP when we have an asynchronous request from gadget
1460 */
5b7d70c6
BD
1461 if (!was_setup && req->complete != s3c_hsotg_complete_setup)
1462 s3c_hsotg_send_zlp(hsotg, hs_req);
1463 }
1464
5ad1d316 1465 s3c_hsotg_complete_request(hsotg, hs_ep, hs_req, result);
5b7d70c6
BD
1466}
1467
1468/**
1469 * s3c_hsotg_read_frameno - read current frame number
1470 * @hsotg: The device instance
1471 *
1472 * Return the current frame number
8b9bc460 1473 */
5b7d70c6
BD
1474static u32 s3c_hsotg_read_frameno(struct s3c_hsotg *hsotg)
1475{
1476 u32 dsts;
1477
94cb8fd6
LM
1478 dsts = readl(hsotg->regs + DSTS);
1479 dsts &= DSTS_SOFFN_MASK;
1480 dsts >>= DSTS_SOFFN_SHIFT;
5b7d70c6
BD
1481
1482 return dsts;
1483}
1484
1485/**
1486 * s3c_hsotg_handle_rx - RX FIFO has data
1487 * @hsotg: The device instance
1488 *
1489 * The IRQ handler has detected that the RX FIFO has some data in it
1490 * that requires processing, so find out what is in there and do the
1491 * appropriate read.
1492 *
25985edc 1493 * The RXFIFO is a true FIFO, the packets coming out are still in packet
5b7d70c6
BD
1494 * chunks, so if you have x packets received on an endpoint you'll get x
1495 * FIFO events delivered, each with a packet's worth of data in it.
1496 *
1497 * When using DMA, we should not be processing events from the RXFIFO
1498 * as the actual data should be sent to the memory directly and we turn
1499 * on the completion interrupts to get notifications of transfer completion.
1500 */
0978f8c5 1501static void s3c_hsotg_handle_rx(struct s3c_hsotg *hsotg)
5b7d70c6 1502{
94cb8fd6 1503 u32 grxstsr = readl(hsotg->regs + GRXSTSP);
5b7d70c6
BD
1504 u32 epnum, status, size;
1505
1506 WARN_ON(using_dma(hsotg));
1507
47a1685f
DN
1508 epnum = grxstsr & GRXSTS_EPNUM_MASK;
1509 status = grxstsr & GRXSTS_PKTSTS_MASK;
5b7d70c6 1510
47a1685f
DN
1511 size = grxstsr & GRXSTS_BYTECNT_MASK;
1512 size >>= GRXSTS_BYTECNT_SHIFT;
5b7d70c6
BD
1513
1514 if (1)
1515 dev_dbg(hsotg->dev, "%s: GRXSTSP=0x%08x (%d@%d)\n",
1516 __func__, grxstsr, size, epnum);
1517
47a1685f
DN
1518 switch ((status & GRXSTS_PKTSTS_MASK) >> GRXSTS_PKTSTS_SHIFT) {
1519 case GRXSTS_PKTSTS_GLOBALOUTNAK:
1520 dev_dbg(hsotg->dev, "GLOBALOUTNAK\n");
5b7d70c6
BD
1521 break;
1522
47a1685f 1523 case GRXSTS_PKTSTS_OUTDONE:
5b7d70c6
BD
1524 dev_dbg(hsotg->dev, "OutDone (Frame=0x%08x)\n",
1525 s3c_hsotg_read_frameno(hsotg));
1526
1527 if (!using_dma(hsotg))
1528 s3c_hsotg_handle_outdone(hsotg, epnum, false);
1529 break;
1530
47a1685f 1531 case GRXSTS_PKTSTS_SETUPDONE:
5b7d70c6
BD
1532 dev_dbg(hsotg->dev,
1533 "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
1534 s3c_hsotg_read_frameno(hsotg),
94cb8fd6 1535 readl(hsotg->regs + DOEPCTL(0)));
5b7d70c6
BD
1536
1537 s3c_hsotg_handle_outdone(hsotg, epnum, true);
1538 break;
1539
47a1685f 1540 case GRXSTS_PKTSTS_OUTRX:
5b7d70c6
BD
1541 s3c_hsotg_rx_data(hsotg, epnum, size);
1542 break;
1543
47a1685f 1544 case GRXSTS_PKTSTS_SETUPRX:
5b7d70c6
BD
1545 dev_dbg(hsotg->dev,
1546 "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
1547 s3c_hsotg_read_frameno(hsotg),
94cb8fd6 1548 readl(hsotg->regs + DOEPCTL(0)));
5b7d70c6
BD
1549
1550 s3c_hsotg_rx_data(hsotg, epnum, size);
1551 break;
1552
1553 default:
1554 dev_warn(hsotg->dev, "%s: unknown status %08x\n",
1555 __func__, grxstsr);
1556
1557 s3c_hsotg_dump(hsotg);
1558 break;
1559 }
1560}
1561
1562/**
1563 * s3c_hsotg_ep0_mps - turn max packet size into register setting
1564 * @mps: The maximum packet size in bytes.
8b9bc460 1565 */
5b7d70c6
BD
1566static u32 s3c_hsotg_ep0_mps(unsigned int mps)
1567{
1568 switch (mps) {
1569 case 64:
94cb8fd6 1570 return D0EPCTL_MPS_64;
5b7d70c6 1571 case 32:
94cb8fd6 1572 return D0EPCTL_MPS_32;
5b7d70c6 1573 case 16:
94cb8fd6 1574 return D0EPCTL_MPS_16;
5b7d70c6 1575 case 8:
94cb8fd6 1576 return D0EPCTL_MPS_8;
5b7d70c6
BD
1577 }
1578
1579 /* bad max packet size, warn and return invalid result */
1580 WARN_ON(1);
1581 return (u32)-1;
1582}
1583
1584/**
1585 * s3c_hsotg_set_ep_maxpacket - set endpoint's max-packet field
1586 * @hsotg: The driver state.
1587 * @ep: The index number of the endpoint
1588 * @mps: The maximum packet size in bytes
1589 *
1590 * Configure the maximum packet size for the given endpoint, updating
1591 * the hardware control registers to reflect this.
1592 */
1593static void s3c_hsotg_set_ep_maxpacket(struct s3c_hsotg *hsotg,
1594 unsigned int ep, unsigned int mps)
1595{
1596 struct s3c_hsotg_ep *hs_ep = &hsotg->eps[ep];
1597 void __iomem *regs = hsotg->regs;
1598 u32 mpsval;
4fca54aa 1599 u32 mcval;
5b7d70c6
BD
1600 u32 reg;
1601
1602 if (ep == 0) {
1603 /* EP0 is a special case */
1604 mpsval = s3c_hsotg_ep0_mps(mps);
1605 if (mpsval > 3)
1606 goto bad_mps;
e9edd199 1607 hs_ep->ep.maxpacket = mps;
4fca54aa 1608 hs_ep->mc = 1;
5b7d70c6 1609 } else {
47a1685f 1610 mpsval = mps & DXEPCTL_MPS_MASK;
e9edd199 1611 if (mpsval > 1024)
5b7d70c6 1612 goto bad_mps;
4fca54aa
RB
1613 mcval = ((mps >> 11) & 0x3) + 1;
1614 hs_ep->mc = mcval;
1615 if (mcval > 3)
1616 goto bad_mps;
e9edd199 1617 hs_ep->ep.maxpacket = mpsval;
5b7d70c6
BD
1618 }
1619
8b9bc460
LM
1620 /*
1621 * update both the in and out endpoint controldir_ registers, even
1622 * if one of the directions may not be in use.
1623 */
5b7d70c6 1624
94cb8fd6 1625 reg = readl(regs + DIEPCTL(ep));
47a1685f 1626 reg &= ~DXEPCTL_MPS_MASK;
5b7d70c6 1627 reg |= mpsval;
94cb8fd6 1628 writel(reg, regs + DIEPCTL(ep));
5b7d70c6 1629
659ad60c 1630 if (ep) {
94cb8fd6 1631 reg = readl(regs + DOEPCTL(ep));
47a1685f 1632 reg &= ~DXEPCTL_MPS_MASK;
659ad60c 1633 reg |= mpsval;
94cb8fd6 1634 writel(reg, regs + DOEPCTL(ep));
659ad60c 1635 }
5b7d70c6
BD
1636
1637 return;
1638
1639bad_mps:
1640 dev_err(hsotg->dev, "ep%d: bad mps of %d\n", ep, mps);
1641}
1642
9c39ddc6
AT
1643/**
1644 * s3c_hsotg_txfifo_flush - flush Tx FIFO
1645 * @hsotg: The driver state
1646 * @idx: The index for the endpoint (0..15)
1647 */
1648static void s3c_hsotg_txfifo_flush(struct s3c_hsotg *hsotg, unsigned int idx)
1649{
1650 int timeout;
1651 int val;
1652
47a1685f 1653 writel(GRSTCTL_TXFNUM(idx) | GRSTCTL_TXFFLSH,
94cb8fd6 1654 hsotg->regs + GRSTCTL);
9c39ddc6
AT
1655
1656 /* wait until the fifo is flushed */
1657 timeout = 100;
1658
1659 while (1) {
94cb8fd6 1660 val = readl(hsotg->regs + GRSTCTL);
9c39ddc6 1661
47a1685f 1662 if ((val & (GRSTCTL_TXFFLSH)) == 0)
9c39ddc6
AT
1663 break;
1664
1665 if (--timeout == 0) {
1666 dev_err(hsotg->dev,
1667 "%s: timeout flushing fifo (GRSTCTL=%08x)\n",
1668 __func__, val);
e0cbe595 1669 break;
9c39ddc6
AT
1670 }
1671
1672 udelay(1);
1673 }
1674}
5b7d70c6
BD
1675
1676/**
1677 * s3c_hsotg_trytx - check to see if anything needs transmitting
1678 * @hsotg: The driver state
1679 * @hs_ep: The driver endpoint to check.
1680 *
1681 * Check to see if there is a request that has data to send, and if so
1682 * make an attempt to write data into the FIFO.
1683 */
1684static int s3c_hsotg_trytx(struct s3c_hsotg *hsotg,
1685 struct s3c_hsotg_ep *hs_ep)
1686{
1687 struct s3c_hsotg_req *hs_req = hs_ep->req;
1688
afcf4169
RB
1689 if (!hs_ep->dir_in || !hs_req) {
1690 /**
1691 * if request is not enqueued, we disable interrupts
1692 * for endpoints, excepting ep0
1693 */
1694 if (hs_ep->index != 0)
1695 s3c_hsotg_ctrl_epint(hsotg, hs_ep->index,
1696 hs_ep->dir_in, 0);
5b7d70c6 1697 return 0;
afcf4169 1698 }
5b7d70c6
BD
1699
1700 if (hs_req->req.actual < hs_req->req.length) {
1701 dev_dbg(hsotg->dev, "trying to write more for ep%d\n",
1702 hs_ep->index);
1703 return s3c_hsotg_write_fifo(hsotg, hs_ep, hs_req);
1704 }
1705
1706 return 0;
1707}
1708
1709/**
1710 * s3c_hsotg_complete_in - complete IN transfer
1711 * @hsotg: The device state.
1712 * @hs_ep: The endpoint that has just completed.
1713 *
1714 * An IN transfer has been completed, update the transfer's state and then
1715 * call the relevant completion routines.
1716 */
1717static void s3c_hsotg_complete_in(struct s3c_hsotg *hsotg,
1718 struct s3c_hsotg_ep *hs_ep)
1719{
1720 struct s3c_hsotg_req *hs_req = hs_ep->req;
94cb8fd6 1721 u32 epsize = readl(hsotg->regs + DIEPTSIZ(hs_ep->index));
5b7d70c6
BD
1722 int size_left, size_done;
1723
1724 if (!hs_req) {
1725 dev_dbg(hsotg->dev, "XferCompl but no req\n");
1726 return;
1727 }
1728
d3ca0259
LM
1729 /* Finish ZLP handling for IN EP0 transactions */
1730 if (hsotg->eps[0].sent_zlp) {
1731 dev_dbg(hsotg->dev, "zlp packet received\n");
5ad1d316 1732 s3c_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
d3ca0259
LM
1733 return;
1734 }
1735
8b9bc460
LM
1736 /*
1737 * Calculate the size of the transfer by checking how much is left
5b7d70c6
BD
1738 * in the endpoint size register and then working it out from
1739 * the amount we loaded for the transfer.
1740 *
1741 * We do this even for DMA, as the transfer may have incremented
1742 * past the end of the buffer (DMA transfers are always 32bit
1743 * aligned).
1744 */
1745
47a1685f 1746 size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
5b7d70c6
BD
1747
1748 size_done = hs_ep->size_loaded - size_left;
1749 size_done += hs_ep->last_load;
1750
1751 if (hs_req->req.actual != size_done)
1752 dev_dbg(hsotg->dev, "%s: adjusting size done %d => %d\n",
1753 __func__, hs_req->req.actual, size_done);
1754
1755 hs_req->req.actual = size_done;
d3ca0259
LM
1756 dev_dbg(hsotg->dev, "req->length:%d req->actual:%d req->zero:%d\n",
1757 hs_req->req.length, hs_req->req.actual, hs_req->req.zero);
1758
1759 /*
1760 * Check if dealing with Maximum Packet Size(MPS) IN transfer at EP0
1761 * When sent data is a multiple MPS size (e.g. 64B ,128B ,192B
1762 * ,256B ... ), after last MPS sized packet send IN ZLP packet to
1763 * inform the host that no more data is available.
1764 * The state of req.zero member is checked to be sure that the value to
1765 * send is smaller than wValue expected from host.
1766 * Check req.length to NOT send another ZLP when the current one is
1767 * under completion (the one for which this completion has been called).
1768 */
1769 if (hs_req->req.length && hs_ep->index == 0 && hs_req->req.zero &&
1770 hs_req->req.length == hs_req->req.actual &&
1771 !(hs_req->req.length % hs_ep->ep.maxpacket)) {
1772
1773 dev_dbg(hsotg->dev, "ep0 zlp IN packet sent\n");
1774 s3c_hsotg_send_zlp(hsotg, hs_req);
5b7d70c6 1775
d3ca0259
LM
1776 return;
1777 }
5b7d70c6
BD
1778
1779 if (!size_left && hs_req->req.actual < hs_req->req.length) {
1780 dev_dbg(hsotg->dev, "%s trying more for req...\n", __func__);
1781 s3c_hsotg_start_req(hsotg, hs_ep, hs_req, true);
1782 } else
5ad1d316 1783 s3c_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
5b7d70c6
BD
1784}
1785
1786/**
1787 * s3c_hsotg_epint - handle an in/out endpoint interrupt
1788 * @hsotg: The driver state
1789 * @idx: The index for the endpoint (0..15)
1790 * @dir_in: Set if this is an IN endpoint
1791 *
1792 * Process and clear any interrupt pending for an individual endpoint
8b9bc460 1793 */
5b7d70c6
BD
1794static void s3c_hsotg_epint(struct s3c_hsotg *hsotg, unsigned int idx,
1795 int dir_in)
1796{
1797 struct s3c_hsotg_ep *hs_ep = &hsotg->eps[idx];
94cb8fd6
LM
1798 u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx);
1799 u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx);
1800 u32 epsiz_reg = dir_in ? DIEPTSIZ(idx) : DOEPTSIZ(idx);
5b7d70c6 1801 u32 ints;
1479e841 1802 u32 ctrl;
5b7d70c6
BD
1803
1804 ints = readl(hsotg->regs + epint_reg);
1479e841 1805 ctrl = readl(hsotg->regs + epctl_reg);
5b7d70c6 1806
a3395f0d
AT
1807 /* Clear endpoint interrupts */
1808 writel(ints, hsotg->regs + epint_reg);
1809
5b7d70c6
BD
1810 dev_dbg(hsotg->dev, "%s: ep%d(%s) DxEPINT=0x%08x\n",
1811 __func__, idx, dir_in ? "in" : "out", ints);
1812
47a1685f 1813 if (ints & DXEPINT_XFERCOMPL) {
1479e841 1814 if (hs_ep->isochronous && hs_ep->interval == 1) {
47a1685f
DN
1815 if (ctrl & DXEPCTL_EOFRNUM)
1816 ctrl |= DXEPCTL_SETEVENFR;
1479e841 1817 else
47a1685f 1818 ctrl |= DXEPCTL_SETODDFR;
1479e841
RB
1819 writel(ctrl, hsotg->regs + epctl_reg);
1820 }
1821
5b7d70c6 1822 dev_dbg(hsotg->dev,
47a1685f 1823 "%s: XferCompl: DxEPCTL=0x%08x, DXEPTSIZ=%08x\n",
5b7d70c6
BD
1824 __func__, readl(hsotg->regs + epctl_reg),
1825 readl(hsotg->regs + epsiz_reg));
1826
8b9bc460
LM
1827 /*
1828 * we get OutDone from the FIFO, so we only need to look
1829 * at completing IN requests here
1830 */
5b7d70c6
BD
1831 if (dir_in) {
1832 s3c_hsotg_complete_in(hsotg, hs_ep);
1833
c9a64ea8 1834 if (idx == 0 && !hs_ep->req)
5b7d70c6
BD
1835 s3c_hsotg_enqueue_setup(hsotg);
1836 } else if (using_dma(hsotg)) {
8b9bc460
LM
1837 /*
1838 * We're using DMA, we need to fire an OutDone here
1839 * as we ignore the RXFIFO.
1840 */
5b7d70c6
BD
1841
1842 s3c_hsotg_handle_outdone(hsotg, idx, false);
1843 }
5b7d70c6
BD
1844 }
1845
47a1685f 1846 if (ints & DXEPINT_EPDISBLD) {
5b7d70c6 1847 dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__);
5b7d70c6 1848
9c39ddc6
AT
1849 if (dir_in) {
1850 int epctl = readl(hsotg->regs + epctl_reg);
1851
b203d0a2 1852 s3c_hsotg_txfifo_flush(hsotg, hs_ep->fifo_index);
9c39ddc6 1853
47a1685f
DN
1854 if ((epctl & DXEPCTL_STALL) &&
1855 (epctl & DXEPCTL_EPTYPE_BULK)) {
94cb8fd6 1856 int dctl = readl(hsotg->regs + DCTL);
9c39ddc6 1857
47a1685f 1858 dctl |= DCTL_CGNPINNAK;
94cb8fd6 1859 writel(dctl, hsotg->regs + DCTL);
9c39ddc6
AT
1860 }
1861 }
1862 }
1863
47a1685f 1864 if (ints & DXEPINT_AHBERR)
5b7d70c6 1865 dev_dbg(hsotg->dev, "%s: AHBErr\n", __func__);
5b7d70c6 1866
47a1685f 1867 if (ints & DXEPINT_SETUP) { /* Setup or Timeout */
5b7d70c6
BD
1868 dev_dbg(hsotg->dev, "%s: Setup/Timeout\n", __func__);
1869
1870 if (using_dma(hsotg) && idx == 0) {
8b9bc460
LM
1871 /*
1872 * this is the notification we've received a
5b7d70c6
BD
1873 * setup packet. In non-DMA mode we'd get this
1874 * from the RXFIFO, instead we need to process
8b9bc460
LM
1875 * the setup here.
1876 */
5b7d70c6
BD
1877
1878 if (dir_in)
1879 WARN_ON_ONCE(1);
1880 else
1881 s3c_hsotg_handle_outdone(hsotg, 0, true);
1882 }
5b7d70c6
BD
1883 }
1884
47a1685f 1885 if (ints & DXEPINT_BACK2BACKSETUP)
5b7d70c6 1886 dev_dbg(hsotg->dev, "%s: B2BSetup/INEPNakEff\n", __func__);
5b7d70c6 1887
1479e841 1888 if (dir_in && !hs_ep->isochronous) {
8b9bc460 1889 /* not sure if this is important, but we'll clear it anyway */
47a1685f 1890 if (ints & DIEPMSK_INTKNTXFEMPMSK) {
5b7d70c6
BD
1891 dev_dbg(hsotg->dev, "%s: ep%d: INTknTXFEmpMsk\n",
1892 __func__, idx);
5b7d70c6
BD
1893 }
1894
1895 /* this probably means something bad is happening */
47a1685f 1896 if (ints & DIEPMSK_INTKNEPMISMSK) {
5b7d70c6
BD
1897 dev_warn(hsotg->dev, "%s: ep%d: INTknEP\n",
1898 __func__, idx);
5b7d70c6 1899 }
10aebc77
BD
1900
1901 /* FIFO has space or is empty (see GAHBCFG) */
1902 if (hsotg->dedicated_fifos &&
47a1685f 1903 ints & DIEPMSK_TXFIFOEMPTY) {
10aebc77
BD
1904 dev_dbg(hsotg->dev, "%s: ep%d: TxFIFOEmpty\n",
1905 __func__, idx);
70fa030f
AT
1906 if (!using_dma(hsotg))
1907 s3c_hsotg_trytx(hsotg, hs_ep);
10aebc77 1908 }
5b7d70c6 1909 }
5b7d70c6
BD
1910}
1911
1912/**
1913 * s3c_hsotg_irq_enumdone - Handle EnumDone interrupt (enumeration done)
1914 * @hsotg: The device state.
1915 *
1916 * Handle updating the device settings after the enumeration phase has
1917 * been completed.
8b9bc460 1918 */
5b7d70c6
BD
1919static void s3c_hsotg_irq_enumdone(struct s3c_hsotg *hsotg)
1920{
94cb8fd6 1921 u32 dsts = readl(hsotg->regs + DSTS);
9b2667f1 1922 int ep0_mps = 0, ep_mps = 8;
5b7d70c6 1923
8b9bc460
LM
1924 /*
1925 * This should signal the finish of the enumeration phase
5b7d70c6 1926 * of the USB handshaking, so we should now know what rate
8b9bc460
LM
1927 * we connected at.
1928 */
5b7d70c6
BD
1929
1930 dev_dbg(hsotg->dev, "EnumDone (DSTS=0x%08x)\n", dsts);
1931
8b9bc460
LM
1932 /*
1933 * note, since we're limited by the size of transfer on EP0, and
5b7d70c6 1934 * it seems IN transfers must be a even number of packets we do
8b9bc460
LM
1935 * not advertise a 64byte MPS on EP0.
1936 */
5b7d70c6
BD
1937
1938 /* catch both EnumSpd_FS and EnumSpd_FS48 */
47a1685f
DN
1939 switch (dsts & DSTS_ENUMSPD_MASK) {
1940 case DSTS_ENUMSPD_FS:
1941 case DSTS_ENUMSPD_FS48:
5b7d70c6 1942 hsotg->gadget.speed = USB_SPEED_FULL;
5b7d70c6 1943 ep0_mps = EP0_MPS_LIMIT;
295538ff 1944 ep_mps = 1023;
5b7d70c6
BD
1945 break;
1946
47a1685f 1947 case DSTS_ENUMSPD_HS:
5b7d70c6 1948 hsotg->gadget.speed = USB_SPEED_HIGH;
5b7d70c6 1949 ep0_mps = EP0_MPS_LIMIT;
295538ff 1950 ep_mps = 1024;
5b7d70c6
BD
1951 break;
1952
47a1685f 1953 case DSTS_ENUMSPD_LS:
5b7d70c6 1954 hsotg->gadget.speed = USB_SPEED_LOW;
8b9bc460
LM
1955 /*
1956 * note, we don't actually support LS in this driver at the
5b7d70c6
BD
1957 * moment, and the documentation seems to imply that it isn't
1958 * supported by the PHYs on some of the devices.
1959 */
1960 break;
1961 }
e538dfda
MN
1962 dev_info(hsotg->dev, "new device is %s\n",
1963 usb_speed_string(hsotg->gadget.speed));
5b7d70c6 1964
8b9bc460
LM
1965 /*
1966 * we should now know the maximum packet size for an
1967 * endpoint, so set the endpoints to a default value.
1968 */
5b7d70c6
BD
1969
1970 if (ep0_mps) {
1971 int i;
1972 s3c_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps);
b3f489b2 1973 for (i = 1; i < hsotg->num_of_eps; i++)
5b7d70c6
BD
1974 s3c_hsotg_set_ep_maxpacket(hsotg, i, ep_mps);
1975 }
1976
1977 /* ensure after enumeration our EP0 is active */
1978
1979 s3c_hsotg_enqueue_setup(hsotg);
1980
1981 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
94cb8fd6
LM
1982 readl(hsotg->regs + DIEPCTL0),
1983 readl(hsotg->regs + DOEPCTL0));
5b7d70c6
BD
1984}
1985
1986/**
1987 * kill_all_requests - remove all requests from the endpoint's queue
1988 * @hsotg: The device state.
1989 * @ep: The endpoint the requests may be on.
1990 * @result: The result code to use.
1991 * @force: Force removal of any current requests
1992 *
1993 * Go through the requests on the given endpoint and mark them
1994 * completed with the given result code.
1995 */
1996static void kill_all_requests(struct s3c_hsotg *hsotg,
1997 struct s3c_hsotg_ep *ep,
1998 int result, bool force)
1999{
2000 struct s3c_hsotg_req *req, *treq;
b203d0a2 2001 unsigned size;
5b7d70c6
BD
2002
2003 list_for_each_entry_safe(req, treq, &ep->queue, queue) {
8b9bc460
LM
2004 /*
2005 * currently, we can't do much about an already
2006 * running request on an in endpoint
2007 */
5b7d70c6
BD
2008
2009 if (ep->req == req && ep->dir_in && !force)
2010 continue;
2011
2012 s3c_hsotg_complete_request(hsotg, ep, req,
2013 result);
2014 }
b203d0a2
RB
2015 if (!hsotg->dedicated_fifos)
2016 return;
2017 size = (readl(hsotg->regs + DTXFSTS(ep->index)) & 0xffff) * 4;
2018 if (size < ep->fifo_size)
2019 s3c_hsotg_txfifo_flush(hsotg, ep->fifo_index);
5b7d70c6
BD
2020}
2021
5b7d70c6 2022/**
5e891342 2023 * s3c_hsotg_disconnect - disconnect service
5b7d70c6
BD
2024 * @hsotg: The device state.
2025 *
5e891342
LM
2026 * The device has been disconnected. Remove all current
2027 * transactions and signal the gadget driver that this
2028 * has happened.
8b9bc460 2029 */
5e891342 2030static void s3c_hsotg_disconnect(struct s3c_hsotg *hsotg)
5b7d70c6
BD
2031{
2032 unsigned ep;
2033
b3f489b2 2034 for (ep = 0; ep < hsotg->num_of_eps; ep++)
5b7d70c6
BD
2035 kill_all_requests(hsotg, &hsotg->eps[ep], -ESHUTDOWN, true);
2036
2037 call_gadget(hsotg, disconnect);
2038}
2039
2040/**
2041 * s3c_hsotg_irq_fifoempty - TX FIFO empty interrupt handler
2042 * @hsotg: The device state:
2043 * @periodic: True if this is a periodic FIFO interrupt
2044 */
2045static void s3c_hsotg_irq_fifoempty(struct s3c_hsotg *hsotg, bool periodic)
2046{
2047 struct s3c_hsotg_ep *ep;
2048 int epno, ret;
2049
2050 /* look through for any more data to transmit */
2051
b3f489b2 2052 for (epno = 0; epno < hsotg->num_of_eps; epno++) {
5b7d70c6
BD
2053 ep = &hsotg->eps[epno];
2054
2055 if (!ep->dir_in)
2056 continue;
2057
2058 if ((periodic && !ep->periodic) ||
2059 (!periodic && ep->periodic))
2060 continue;
2061
2062 ret = s3c_hsotg_trytx(hsotg, ep);
2063 if (ret < 0)
2064 break;
2065 }
2066}
2067
5b7d70c6 2068/* IRQ flags which will trigger a retry around the IRQ loop */
47a1685f
DN
2069#define IRQ_RETRY_MASK (GINTSTS_NPTXFEMP | \
2070 GINTSTS_PTXFEMP | \
2071 GINTSTS_RXFLVL)
5b7d70c6 2072
308d734e
LM
2073/**
2074 * s3c_hsotg_corereset - issue softreset to the core
2075 * @hsotg: The device state
2076 *
2077 * Issue a soft reset to the core, and await the core finishing it.
8b9bc460 2078 */
308d734e
LM
2079static int s3c_hsotg_corereset(struct s3c_hsotg *hsotg)
2080{
2081 int timeout;
2082 u32 grstctl;
2083
2084 dev_dbg(hsotg->dev, "resetting core\n");
2085
2086 /* issue soft reset */
47a1685f 2087 writel(GRSTCTL_CSFTRST, hsotg->regs + GRSTCTL);
308d734e 2088
2868fea2 2089 timeout = 10000;
308d734e 2090 do {
94cb8fd6 2091 grstctl = readl(hsotg->regs + GRSTCTL);
47a1685f 2092 } while ((grstctl & GRSTCTL_CSFTRST) && timeout-- > 0);
308d734e 2093
47a1685f 2094 if (grstctl & GRSTCTL_CSFTRST) {
308d734e
LM
2095 dev_err(hsotg->dev, "Failed to get CSftRst asserted\n");
2096 return -EINVAL;
2097 }
2098
2868fea2 2099 timeout = 10000;
308d734e
LM
2100
2101 while (1) {
94cb8fd6 2102 u32 grstctl = readl(hsotg->regs + GRSTCTL);
308d734e
LM
2103
2104 if (timeout-- < 0) {
2105 dev_info(hsotg->dev,
2106 "%s: reset failed, GRSTCTL=%08x\n",
2107 __func__, grstctl);
2108 return -ETIMEDOUT;
2109 }
2110
47a1685f 2111 if (!(grstctl & GRSTCTL_AHBIDLE))
308d734e
LM
2112 continue;
2113
2114 break; /* reset done */
2115 }
2116
2117 dev_dbg(hsotg->dev, "reset successful\n");
2118 return 0;
2119}
2120
8b9bc460
LM
2121/**
2122 * s3c_hsotg_core_init - issue softreset to the core
2123 * @hsotg: The device state
2124 *
2125 * Issue a soft reset to the core, and await the core finishing it.
2126 */
308d734e
LM
2127static void s3c_hsotg_core_init(struct s3c_hsotg *hsotg)
2128{
2129 s3c_hsotg_corereset(hsotg);
2130
2131 /*
2132 * we must now enable ep0 ready for host detection and then
2133 * set configuration.
2134 */
2135
2136 /* set the PLL on, remove the HNP/SRP and set the PHY */
47a1685f 2137 writel(hsotg->phyif | GUSBCFG_TOUTCAL(7) |
94cb8fd6 2138 (0x5 << 10), hsotg->regs + GUSBCFG);
308d734e
LM
2139
2140 s3c_hsotg_init_fifo(hsotg);
2141
47a1685f 2142 __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON);
308d734e 2143
47a1685f 2144 writel(1 << 18 | DCFG_DEVSPD_HS, hsotg->regs + DCFG);
308d734e
LM
2145
2146 /* Clear any pending OTG interrupts */
94cb8fd6 2147 writel(0xffffffff, hsotg->regs + GOTGINT);
308d734e
LM
2148
2149 /* Clear any pending interrupts */
94cb8fd6 2150 writel(0xffffffff, hsotg->regs + GINTSTS);
308d734e 2151
47a1685f
DN
2152 writel(GINTSTS_ERLYSUSP | GINTSTS_SESSREQINT |
2153 GINTSTS_GOUTNAKEFF | GINTSTS_GINNAKEFF |
2154 GINTSTS_CONIDSTSCHNG | GINTSTS_USBRST |
2155 GINTSTS_ENUMDONE | GINTSTS_OTGINT |
2156 GINTSTS_USBSUSP | GINTSTS_WKUPINT,
2157 hsotg->regs + GINTMSK);
308d734e
LM
2158
2159 if (using_dma(hsotg))
47a1685f
DN
2160 writel(GAHBCFG_GLBL_INTR_EN | GAHBCFG_DMA_EN |
2161 GAHBCFG_HBSTLEN_INCR4,
94cb8fd6 2162 hsotg->regs + GAHBCFG);
308d734e 2163 else
47a1685f
DN
2164 writel(((hsotg->dedicated_fifos) ? (GAHBCFG_NP_TXF_EMP_LVL |
2165 GAHBCFG_P_TXF_EMP_LVL) : 0) |
2166 GAHBCFG_GLBL_INTR_EN,
8acc8296 2167 hsotg->regs + GAHBCFG);
308d734e
LM
2168
2169 /*
8acc8296
RB
2170 * If INTknTXFEmpMsk is enabled, it's important to disable ep interrupts
2171 * when we have no data to transfer. Otherwise we get being flooded by
2172 * interrupts.
308d734e
LM
2173 */
2174
47a1685f
DN
2175 writel(((hsotg->dedicated_fifos) ? DIEPMSK_TXFIFOEMPTY |
2176 DIEPMSK_INTKNTXFEMPMSK : 0) |
2177 DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK |
2178 DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK |
2179 DIEPMSK_INTKNEPMISMSK,
2180 hsotg->regs + DIEPMSK);
308d734e
LM
2181
2182 /*
2183 * don't need XferCompl, we get that from RXFIFO in slave mode. In
2184 * DMA mode we may need this.
2185 */
47a1685f
DN
2186 writel((using_dma(hsotg) ? (DIEPMSK_XFERCOMPLMSK |
2187 DIEPMSK_TIMEOUTMSK) : 0) |
2188 DOEPMSK_EPDISBLDMSK | DOEPMSK_AHBERRMSK |
2189 DOEPMSK_SETUPMSK,
2190 hsotg->regs + DOEPMSK);
308d734e 2191
94cb8fd6 2192 writel(0, hsotg->regs + DAINTMSK);
308d734e
LM
2193
2194 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
94cb8fd6
LM
2195 readl(hsotg->regs + DIEPCTL0),
2196 readl(hsotg->regs + DOEPCTL0));
308d734e
LM
2197
2198 /* enable in and out endpoint interrupts */
47a1685f 2199 s3c_hsotg_en_gsint(hsotg, GINTSTS_OEPINT | GINTSTS_IEPINT);
308d734e
LM
2200
2201 /*
2202 * Enable the RXFIFO when in slave mode, as this is how we collect
2203 * the data. In DMA mode, we get events from the FIFO but also
2204 * things we cannot process, so do not use it.
2205 */
2206 if (!using_dma(hsotg))
47a1685f 2207 s3c_hsotg_en_gsint(hsotg, GINTSTS_RXFLVL);
308d734e
LM
2208
2209 /* Enable interrupts for EP0 in and out */
2210 s3c_hsotg_ctrl_epint(hsotg, 0, 0, 1);
2211 s3c_hsotg_ctrl_epint(hsotg, 0, 1, 1);
2212
47a1685f 2213 __orr32(hsotg->regs + DCTL, DCTL_PWRONPRGDONE);
308d734e 2214 udelay(10); /* see openiboot */
47a1685f 2215 __bic32(hsotg->regs + DCTL, DCTL_PWRONPRGDONE);
308d734e 2216
94cb8fd6 2217 dev_dbg(hsotg->dev, "DCTL=0x%08x\n", readl(hsotg->regs + DCTL));
308d734e
LM
2218
2219 /*
94cb8fd6 2220 * DxEPCTL_USBActEp says RO in manual, but seems to be set by
308d734e
LM
2221 * writing to the EPCTL register..
2222 */
2223
2224 /* set to read 1 8byte packet */
47a1685f
DN
2225 writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
2226 DXEPTSIZ_XFERSIZE(8), hsotg->regs + DOEPTSIZ0);
308d734e
LM
2227
2228 writel(s3c_hsotg_ep0_mps(hsotg->eps[0].ep.maxpacket) |
47a1685f
DN
2229 DXEPCTL_CNAK | DXEPCTL_EPENA |
2230 DXEPCTL_USBACTEP,
94cb8fd6 2231 hsotg->regs + DOEPCTL0);
308d734e
LM
2232
2233 /* enable, but don't activate EP0in */
2234 writel(s3c_hsotg_ep0_mps(hsotg->eps[0].ep.maxpacket) |
47a1685f 2235 DXEPCTL_USBACTEP, hsotg->regs + DIEPCTL0);
308d734e
LM
2236
2237 s3c_hsotg_enqueue_setup(hsotg);
2238
2239 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
94cb8fd6
LM
2240 readl(hsotg->regs + DIEPCTL0),
2241 readl(hsotg->regs + DOEPCTL0));
308d734e
LM
2242
2243 /* clear global NAKs */
47a1685f 2244 writel(DCTL_CGOUTNAK | DCTL_CGNPINNAK,
94cb8fd6 2245 hsotg->regs + DCTL);
308d734e
LM
2246
2247 /* must be at-least 3ms to allow bus to see disconnect */
2248 mdelay(3);
2249
2250 /* remove the soft-disconnect and let's go */
47a1685f 2251 __bic32(hsotg->regs + DCTL, DCTL_SFTDISCON);
308d734e
LM
2252}
2253
5b7d70c6
BD
2254/**
2255 * s3c_hsotg_irq - handle device interrupt
2256 * @irq: The IRQ number triggered
2257 * @pw: The pw value when registered the handler.
2258 */
2259static irqreturn_t s3c_hsotg_irq(int irq, void *pw)
2260{
2261 struct s3c_hsotg *hsotg = pw;
2262 int retry_count = 8;
2263 u32 gintsts;
2264 u32 gintmsk;
2265
5ad1d316 2266 spin_lock(&hsotg->lock);
5b7d70c6 2267irq_retry:
94cb8fd6
LM
2268 gintsts = readl(hsotg->regs + GINTSTS);
2269 gintmsk = readl(hsotg->regs + GINTMSK);
5b7d70c6
BD
2270
2271 dev_dbg(hsotg->dev, "%s: %08x %08x (%08x) retry %d\n",
2272 __func__, gintsts, gintsts & gintmsk, gintmsk, retry_count);
2273
2274 gintsts &= gintmsk;
2275
47a1685f 2276 if (gintsts & GINTSTS_OTGINT) {
94cb8fd6 2277 u32 otgint = readl(hsotg->regs + GOTGINT);
5b7d70c6
BD
2278
2279 dev_info(hsotg->dev, "OTGInt: %08x\n", otgint);
2280
94cb8fd6 2281 writel(otgint, hsotg->regs + GOTGINT);
5b7d70c6
BD
2282 }
2283
47a1685f 2284 if (gintsts & GINTSTS_SESSREQINT) {
5b7d70c6 2285 dev_dbg(hsotg->dev, "%s: SessReqInt\n", __func__);
47a1685f 2286 writel(GINTSTS_SESSREQINT, hsotg->regs + GINTSTS);
5b7d70c6
BD
2287 }
2288
47a1685f
DN
2289 if (gintsts & GINTSTS_ENUMDONE) {
2290 writel(GINTSTS_ENUMDONE, hsotg->regs + GINTSTS);
a3395f0d
AT
2291
2292 s3c_hsotg_irq_enumdone(hsotg);
5b7d70c6
BD
2293 }
2294
47a1685f 2295 if (gintsts & GINTSTS_CONIDSTSCHNG) {
5b7d70c6 2296 dev_dbg(hsotg->dev, "ConIDStsChg (DSTS=0x%08x, GOTCTL=%08x)\n",
94cb8fd6
LM
2297 readl(hsotg->regs + DSTS),
2298 readl(hsotg->regs + GOTGCTL));
5b7d70c6 2299
47a1685f 2300 writel(GINTSTS_CONIDSTSCHNG, hsotg->regs + GINTSTS);
5b7d70c6
BD
2301 }
2302
47a1685f 2303 if (gintsts & (GINTSTS_OEPINT | GINTSTS_IEPINT)) {
94cb8fd6 2304 u32 daint = readl(hsotg->regs + DAINT);
7e804650
RB
2305 u32 daintmsk = readl(hsotg->regs + DAINTMSK);
2306 u32 daint_out, daint_in;
5b7d70c6
BD
2307 int ep;
2308
7e804650 2309 daint &= daintmsk;
47a1685f
DN
2310 daint_out = daint >> DAINT_OUTEP_SHIFT;
2311 daint_in = daint & ~(daint_out << DAINT_OUTEP_SHIFT);
7e804650 2312
5b7d70c6
BD
2313 dev_dbg(hsotg->dev, "%s: daint=%08x\n", __func__, daint);
2314
2315 for (ep = 0; ep < 15 && daint_out; ep++, daint_out >>= 1) {
2316 if (daint_out & 1)
2317 s3c_hsotg_epint(hsotg, ep, 0);
2318 }
2319
2320 for (ep = 0; ep < 15 && daint_in; ep++, daint_in >>= 1) {
2321 if (daint_in & 1)
2322 s3c_hsotg_epint(hsotg, ep, 1);
2323 }
5b7d70c6
BD
2324 }
2325
47a1685f 2326 if (gintsts & GINTSTS_USBRST) {
12a1f4dc 2327
94cb8fd6 2328 u32 usb_status = readl(hsotg->regs + GOTGCTL);
12a1f4dc 2329
5b7d70c6
BD
2330 dev_info(hsotg->dev, "%s: USBRst\n", __func__);
2331 dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n",
94cb8fd6 2332 readl(hsotg->regs + GNPTXSTS));
5b7d70c6 2333
47a1685f 2334 writel(GINTSTS_USBRST, hsotg->regs + GINTSTS);
a3395f0d 2335
94cb8fd6 2336 if (usb_status & GOTGCTL_BSESVLD) {
12a1f4dc
LM
2337 if (time_after(jiffies, hsotg->last_rst +
2338 msecs_to_jiffies(200))) {
5b7d70c6 2339
12a1f4dc
LM
2340 kill_all_requests(hsotg, &hsotg->eps[0],
2341 -ECONNRESET, true);
5b7d70c6 2342
12a1f4dc
LM
2343 s3c_hsotg_core_init(hsotg);
2344 hsotg->last_rst = jiffies;
2345 }
2346 }
5b7d70c6
BD
2347 }
2348
2349 /* check both FIFOs */
2350
47a1685f 2351 if (gintsts & GINTSTS_NPTXFEMP) {
5b7d70c6
BD
2352 dev_dbg(hsotg->dev, "NPTxFEmp\n");
2353
8b9bc460
LM
2354 /*
2355 * Disable the interrupt to stop it happening again
5b7d70c6 2356 * unless one of these endpoint routines decides that
8b9bc460
LM
2357 * it needs re-enabling
2358 */
5b7d70c6 2359
47a1685f 2360 s3c_hsotg_disable_gsint(hsotg, GINTSTS_NPTXFEMP);
5b7d70c6 2361 s3c_hsotg_irq_fifoempty(hsotg, false);
5b7d70c6
BD
2362 }
2363
47a1685f 2364 if (gintsts & GINTSTS_PTXFEMP) {
5b7d70c6
BD
2365 dev_dbg(hsotg->dev, "PTxFEmp\n");
2366
94cb8fd6 2367 /* See note in GINTSTS_NPTxFEmp */
5b7d70c6 2368
47a1685f 2369 s3c_hsotg_disable_gsint(hsotg, GINTSTS_PTXFEMP);
5b7d70c6 2370 s3c_hsotg_irq_fifoempty(hsotg, true);
5b7d70c6
BD
2371 }
2372
47a1685f 2373 if (gintsts & GINTSTS_RXFLVL) {
8b9bc460
LM
2374 /*
2375 * note, since GINTSTS_RxFLvl doubles as FIFO-not-empty,
5b7d70c6 2376 * we need to retry s3c_hsotg_handle_rx if this is still
8b9bc460
LM
2377 * set.
2378 */
5b7d70c6
BD
2379
2380 s3c_hsotg_handle_rx(hsotg);
5b7d70c6
BD
2381 }
2382
47a1685f 2383 if (gintsts & GINTSTS_MODEMIS) {
5b7d70c6 2384 dev_warn(hsotg->dev, "warning, mode mismatch triggered\n");
47a1685f 2385 writel(GINTSTS_MODEMIS, hsotg->regs + GINTSTS);
5b7d70c6
BD
2386 }
2387
47a1685f 2388 if (gintsts & GINTSTS_USBSUSP) {
94cb8fd6 2389 dev_info(hsotg->dev, "GINTSTS_USBSusp\n");
47a1685f 2390 writel(GINTSTS_USBSUSP, hsotg->regs + GINTSTS);
5b7d70c6
BD
2391
2392 call_gadget(hsotg, suspend);
2393 }
2394
47a1685f 2395 if (gintsts & GINTSTS_WKUPINT) {
94cb8fd6 2396 dev_info(hsotg->dev, "GINTSTS_WkUpIn\n");
47a1685f 2397 writel(GINTSTS_WKUPINT, hsotg->regs + GINTSTS);
5b7d70c6
BD
2398
2399 call_gadget(hsotg, resume);
2400 }
2401
47a1685f 2402 if (gintsts & GINTSTS_ERLYSUSP) {
94cb8fd6 2403 dev_dbg(hsotg->dev, "GINTSTS_ErlySusp\n");
47a1685f 2404 writel(GINTSTS_ERLYSUSP, hsotg->regs + GINTSTS);
5b7d70c6
BD
2405 }
2406
8b9bc460
LM
2407 /*
2408 * these next two seem to crop-up occasionally causing the core
5b7d70c6 2409 * to shutdown the USB transfer, so try clearing them and logging
8b9bc460
LM
2410 * the occurrence.
2411 */
5b7d70c6 2412
47a1685f 2413 if (gintsts & GINTSTS_GOUTNAKEFF) {
5b7d70c6
BD
2414 dev_info(hsotg->dev, "GOUTNakEff triggered\n");
2415
47a1685f 2416 writel(DCTL_CGOUTNAK, hsotg->regs + DCTL);
a3395f0d
AT
2417
2418 s3c_hsotg_dump(hsotg);
5b7d70c6
BD
2419 }
2420
47a1685f 2421 if (gintsts & GINTSTS_GINNAKEFF) {
5b7d70c6
BD
2422 dev_info(hsotg->dev, "GINNakEff triggered\n");
2423
47a1685f 2424 writel(DCTL_CGNPINNAK, hsotg->regs + DCTL);
a3395f0d
AT
2425
2426 s3c_hsotg_dump(hsotg);
5b7d70c6
BD
2427 }
2428
8b9bc460
LM
2429 /*
2430 * if we've had fifo events, we should try and go around the
2431 * loop again to see if there's any point in returning yet.
2432 */
5b7d70c6
BD
2433
2434 if (gintsts & IRQ_RETRY_MASK && --retry_count > 0)
2435 goto irq_retry;
2436
5ad1d316
LM
2437 spin_unlock(&hsotg->lock);
2438
5b7d70c6
BD
2439 return IRQ_HANDLED;
2440}
2441
2442/**
2443 * s3c_hsotg_ep_enable - enable the given endpoint
2444 * @ep: The USB endpint to configure
2445 * @desc: The USB endpoint descriptor to configure with.
2446 *
2447 * This is called from the USB gadget code's usb_ep_enable().
8b9bc460 2448 */
5b7d70c6
BD
2449static int s3c_hsotg_ep_enable(struct usb_ep *ep,
2450 const struct usb_endpoint_descriptor *desc)
2451{
2452 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
2453 struct s3c_hsotg *hsotg = hs_ep->parent;
2454 unsigned long flags;
2455 int index = hs_ep->index;
2456 u32 epctrl_reg;
2457 u32 epctrl;
2458 u32 mps;
2459 int dir_in;
b203d0a2 2460 int i, val, size;
19c190f9 2461 int ret = 0;
5b7d70c6
BD
2462
2463 dev_dbg(hsotg->dev,
2464 "%s: ep %s: a 0x%02x, attr 0x%02x, mps 0x%04x, intr %d\n",
2465 __func__, ep->name, desc->bEndpointAddress, desc->bmAttributes,
2466 desc->wMaxPacketSize, desc->bInterval);
2467
2468 /* not to be called for EP0 */
2469 WARN_ON(index == 0);
2470
2471 dir_in = (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) ? 1 : 0;
2472 if (dir_in != hs_ep->dir_in) {
2473 dev_err(hsotg->dev, "%s: direction mismatch!\n", __func__);
2474 return -EINVAL;
2475 }
2476
29cc8897 2477 mps = usb_endpoint_maxp(desc);
5b7d70c6
BD
2478
2479 /* note, we handle this here instead of s3c_hsotg_set_ep_maxpacket */
2480
94cb8fd6 2481 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
5b7d70c6
BD
2482 epctrl = readl(hsotg->regs + epctrl_reg);
2483
2484 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x from 0x%08x\n",
2485 __func__, epctrl, epctrl_reg);
2486
22258f49 2487 spin_lock_irqsave(&hsotg->lock, flags);
5b7d70c6 2488
47a1685f
DN
2489 epctrl &= ~(DXEPCTL_EPTYPE_MASK | DXEPCTL_MPS_MASK);
2490 epctrl |= DXEPCTL_MPS(mps);
5b7d70c6 2491
8b9bc460
LM
2492 /*
2493 * mark the endpoint as active, otherwise the core may ignore
2494 * transactions entirely for this endpoint
2495 */
47a1685f 2496 epctrl |= DXEPCTL_USBACTEP;
5b7d70c6 2497
8b9bc460
LM
2498 /*
2499 * set the NAK status on the endpoint, otherwise we might try and
5b7d70c6
BD
2500 * do something with data that we've yet got a request to process
2501 * since the RXFIFO will take data for an endpoint even if the
2502 * size register hasn't been set.
2503 */
2504
47a1685f 2505 epctrl |= DXEPCTL_SNAK;
5b7d70c6
BD
2506
2507 /* update the endpoint state */
e9edd199 2508 s3c_hsotg_set_ep_maxpacket(hsotg, hs_ep->index, mps);
5b7d70c6
BD
2509
2510 /* default, set to non-periodic */
1479e841 2511 hs_ep->isochronous = 0;
5b7d70c6 2512 hs_ep->periodic = 0;
a18ed7b0 2513 hs_ep->halted = 0;
1479e841 2514 hs_ep->interval = desc->bInterval;
5b7d70c6 2515
4fca54aa
RB
2516 if (hs_ep->interval > 1 && hs_ep->mc > 1)
2517 dev_err(hsotg->dev, "MC > 1 when interval is not 1\n");
2518
5b7d70c6
BD
2519 switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
2520 case USB_ENDPOINT_XFER_ISOC:
47a1685f
DN
2521 epctrl |= DXEPCTL_EPTYPE_ISO;
2522 epctrl |= DXEPCTL_SETEVENFR;
1479e841
RB
2523 hs_ep->isochronous = 1;
2524 if (dir_in)
2525 hs_ep->periodic = 1;
2526 break;
5b7d70c6
BD
2527
2528 case USB_ENDPOINT_XFER_BULK:
47a1685f 2529 epctrl |= DXEPCTL_EPTYPE_BULK;
5b7d70c6
BD
2530 break;
2531
2532 case USB_ENDPOINT_XFER_INT:
b203d0a2 2533 if (dir_in)
5b7d70c6 2534 hs_ep->periodic = 1;
5b7d70c6 2535
47a1685f 2536 epctrl |= DXEPCTL_EPTYPE_INTERRUPT;
5b7d70c6
BD
2537 break;
2538
2539 case USB_ENDPOINT_XFER_CONTROL:
47a1685f 2540 epctrl |= DXEPCTL_EPTYPE_CONTROL;
5b7d70c6
BD
2541 break;
2542 }
2543
8b9bc460
LM
2544 /*
2545 * if the hardware has dedicated fifos, we must give each IN EP
10aebc77
BD
2546 * a unique tx-fifo even if it is non-periodic.
2547 */
b203d0a2
RB
2548 if (dir_in && hsotg->dedicated_fifos) {
2549 size = hs_ep->ep.maxpacket*hs_ep->mc;
2550 for (i = 1; i <= 8; ++i) {
2551 if (hsotg->fifo_map & (1<<i))
2552 continue;
2553 val = readl(hsotg->regs + DPTXFSIZN(i));
2554 val = (val >> FIFOSIZE_DEPTH_SHIFT)*4;
2555 if (val < size)
2556 continue;
2557 hsotg->fifo_map |= 1<<i;
2558
2559 epctrl |= DXEPCTL_TXFNUM(i);
2560 hs_ep->fifo_index = i;
2561 hs_ep->fifo_size = val;
2562 break;
2563 }
2564 if (i == 8)
2565 return -ENOMEM;
2566 }
10aebc77 2567
5b7d70c6
BD
2568 /* for non control endpoints, set PID to D0 */
2569 if (index)
47a1685f 2570 epctrl |= DXEPCTL_SETD0PID;
5b7d70c6
BD
2571
2572 dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n",
2573 __func__, epctrl);
2574
2575 writel(epctrl, hsotg->regs + epctrl_reg);
2576 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x\n",
2577 __func__, readl(hsotg->regs + epctrl_reg));
2578
2579 /* enable the endpoint interrupt */
2580 s3c_hsotg_ctrl_epint(hsotg, index, dir_in, 1);
2581
22258f49 2582 spin_unlock_irqrestore(&hsotg->lock, flags);
19c190f9 2583 return ret;
5b7d70c6
BD
2584}
2585
8b9bc460
LM
2586/**
2587 * s3c_hsotg_ep_disable - disable given endpoint
2588 * @ep: The endpoint to disable.
2589 */
5b7d70c6
BD
2590static int s3c_hsotg_ep_disable(struct usb_ep *ep)
2591{
2592 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
2593 struct s3c_hsotg *hsotg = hs_ep->parent;
2594 int dir_in = hs_ep->dir_in;
2595 int index = hs_ep->index;
2596 unsigned long flags;
2597 u32 epctrl_reg;
2598 u32 ctrl;
2599
1e011293 2600 dev_dbg(hsotg->dev, "%s(ep %p)\n", __func__, ep);
5b7d70c6
BD
2601
2602 if (ep == &hsotg->eps[0].ep) {
2603 dev_err(hsotg->dev, "%s: called for ep0\n", __func__);
2604 return -EINVAL;
2605 }
2606
94cb8fd6 2607 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
5b7d70c6 2608
5ad1d316 2609 spin_lock_irqsave(&hsotg->lock, flags);
5b7d70c6
BD
2610 /* terminate all requests with shutdown */
2611 kill_all_requests(hsotg, hs_ep, -ESHUTDOWN, false);
2612
b203d0a2
RB
2613 hsotg->fifo_map &= ~(1<<hs_ep->fifo_index);
2614 hs_ep->fifo_index = 0;
2615 hs_ep->fifo_size = 0;
5b7d70c6
BD
2616
2617 ctrl = readl(hsotg->regs + epctrl_reg);
47a1685f
DN
2618 ctrl &= ~DXEPCTL_EPENA;
2619 ctrl &= ~DXEPCTL_USBACTEP;
2620 ctrl |= DXEPCTL_SNAK;
5b7d70c6
BD
2621
2622 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
2623 writel(ctrl, hsotg->regs + epctrl_reg);
2624
2625 /* disable endpoint interrupts */
2626 s3c_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 0);
2627
22258f49 2628 spin_unlock_irqrestore(&hsotg->lock, flags);
5b7d70c6
BD
2629 return 0;
2630}
2631
2632/**
2633 * on_list - check request is on the given endpoint
2634 * @ep: The endpoint to check.
2635 * @test: The request to test if it is on the endpoint.
8b9bc460 2636 */
5b7d70c6
BD
2637static bool on_list(struct s3c_hsotg_ep *ep, struct s3c_hsotg_req *test)
2638{
2639 struct s3c_hsotg_req *req, *treq;
2640
2641 list_for_each_entry_safe(req, treq, &ep->queue, queue) {
2642 if (req == test)
2643 return true;
2644 }
2645
2646 return false;
2647}
2648
8b9bc460
LM
2649/**
2650 * s3c_hsotg_ep_dequeue - dequeue given endpoint
2651 * @ep: The endpoint to dequeue.
2652 * @req: The request to be removed from a queue.
2653 */
5b7d70c6
BD
2654static int s3c_hsotg_ep_dequeue(struct usb_ep *ep, struct usb_request *req)
2655{
2656 struct s3c_hsotg_req *hs_req = our_req(req);
2657 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
2658 struct s3c_hsotg *hs = hs_ep->parent;
2659 unsigned long flags;
2660
1e011293 2661 dev_dbg(hs->dev, "ep_dequeue(%p,%p)\n", ep, req);
5b7d70c6 2662
22258f49 2663 spin_lock_irqsave(&hs->lock, flags);
5b7d70c6
BD
2664
2665 if (!on_list(hs_ep, hs_req)) {
22258f49 2666 spin_unlock_irqrestore(&hs->lock, flags);
5b7d70c6
BD
2667 return -EINVAL;
2668 }
2669
2670 s3c_hsotg_complete_request(hs, hs_ep, hs_req, -ECONNRESET);
22258f49 2671 spin_unlock_irqrestore(&hs->lock, flags);
5b7d70c6
BD
2672
2673 return 0;
2674}
2675
8b9bc460
LM
2676/**
2677 * s3c_hsotg_ep_sethalt - set halt on a given endpoint
2678 * @ep: The endpoint to set halt.
2679 * @value: Set or unset the halt.
2680 */
5b7d70c6
BD
2681static int s3c_hsotg_ep_sethalt(struct usb_ep *ep, int value)
2682{
2683 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
2684 struct s3c_hsotg *hs = hs_ep->parent;
2685 int index = hs_ep->index;
5b7d70c6
BD
2686 u32 epreg;
2687 u32 epctl;
9c39ddc6 2688 u32 xfertype;
5b7d70c6
BD
2689
2690 dev_info(hs->dev, "%s(ep %p %s, %d)\n", __func__, ep, ep->name, value);
2691
c9f721b2
RB
2692 if (index == 0) {
2693 if (value)
2694 s3c_hsotg_stall_ep0(hs);
2695 else
2696 dev_warn(hs->dev,
2697 "%s: can't clear halt on ep0\n", __func__);
2698 return 0;
2699 }
2700
5b7d70c6
BD
2701 /* write both IN and OUT control registers */
2702
94cb8fd6 2703 epreg = DIEPCTL(index);
5b7d70c6
BD
2704 epctl = readl(hs->regs + epreg);
2705
9c39ddc6 2706 if (value) {
47a1685f
DN
2707 epctl |= DXEPCTL_STALL + DXEPCTL_SNAK;
2708 if (epctl & DXEPCTL_EPENA)
2709 epctl |= DXEPCTL_EPDIS;
9c39ddc6 2710 } else {
47a1685f
DN
2711 epctl &= ~DXEPCTL_STALL;
2712 xfertype = epctl & DXEPCTL_EPTYPE_MASK;
2713 if (xfertype == DXEPCTL_EPTYPE_BULK ||
2714 xfertype == DXEPCTL_EPTYPE_INTERRUPT)
2715 epctl |= DXEPCTL_SETD0PID;
9c39ddc6 2716 }
5b7d70c6
BD
2717
2718 writel(epctl, hs->regs + epreg);
2719
94cb8fd6 2720 epreg = DOEPCTL(index);
5b7d70c6
BD
2721 epctl = readl(hs->regs + epreg);
2722
2723 if (value)
47a1685f 2724 epctl |= DXEPCTL_STALL;
9c39ddc6 2725 else {
47a1685f
DN
2726 epctl &= ~DXEPCTL_STALL;
2727 xfertype = epctl & DXEPCTL_EPTYPE_MASK;
2728 if (xfertype == DXEPCTL_EPTYPE_BULK ||
2729 xfertype == DXEPCTL_EPTYPE_INTERRUPT)
2730 epctl |= DXEPCTL_SETD0PID;
9c39ddc6 2731 }
5b7d70c6
BD
2732
2733 writel(epctl, hs->regs + epreg);
2734
a18ed7b0
RB
2735 hs_ep->halted = value;
2736
5b7d70c6
BD
2737 return 0;
2738}
2739
5ad1d316
LM
2740/**
2741 * s3c_hsotg_ep_sethalt_lock - set halt on a given endpoint with lock held
2742 * @ep: The endpoint to set halt.
2743 * @value: Set or unset the halt.
2744 */
2745static int s3c_hsotg_ep_sethalt_lock(struct usb_ep *ep, int value)
2746{
2747 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
2748 struct s3c_hsotg *hs = hs_ep->parent;
2749 unsigned long flags = 0;
2750 int ret = 0;
2751
2752 spin_lock_irqsave(&hs->lock, flags);
2753 ret = s3c_hsotg_ep_sethalt(ep, value);
2754 spin_unlock_irqrestore(&hs->lock, flags);
2755
2756 return ret;
2757}
2758
5b7d70c6
BD
2759static struct usb_ep_ops s3c_hsotg_ep_ops = {
2760 .enable = s3c_hsotg_ep_enable,
2761 .disable = s3c_hsotg_ep_disable,
2762 .alloc_request = s3c_hsotg_ep_alloc_request,
2763 .free_request = s3c_hsotg_ep_free_request,
5ad1d316 2764 .queue = s3c_hsotg_ep_queue_lock,
5b7d70c6 2765 .dequeue = s3c_hsotg_ep_dequeue,
5ad1d316 2766 .set_halt = s3c_hsotg_ep_sethalt_lock,
25985edc 2767 /* note, don't believe we have any call for the fifo routines */
5b7d70c6
BD
2768};
2769
41188786
LM
2770/**
2771 * s3c_hsotg_phy_enable - enable platform phy dev
8b9bc460 2772 * @hsotg: The driver state
41188786
LM
2773 *
2774 * A wrapper for platform code responsible for controlling
2775 * low-level USB code
2776 */
2777static void s3c_hsotg_phy_enable(struct s3c_hsotg *hsotg)
2778{
2779 struct platform_device *pdev = to_platform_device(hsotg->dev);
2780
2781 dev_dbg(hsotg->dev, "pdev 0x%p\n", pdev);
b2e587db 2782
ca2c5ba8 2783 if (hsotg->uphy)
74084844 2784 usb_phy_init(hsotg->uphy);
ca2c5ba8 2785 else if (hsotg->plat && hsotg->plat->phy_init)
41188786 2786 hsotg->plat->phy_init(pdev, hsotg->plat->phy_type);
ca2c5ba8
KD
2787 else {
2788 phy_init(hsotg->phy);
2789 phy_power_on(hsotg->phy);
2790 }
41188786
LM
2791}
2792
2793/**
2794 * s3c_hsotg_phy_disable - disable platform phy dev
8b9bc460 2795 * @hsotg: The driver state
41188786
LM
2796 *
2797 * A wrapper for platform code responsible for controlling
2798 * low-level USB code
2799 */
2800static void s3c_hsotg_phy_disable(struct s3c_hsotg *hsotg)
2801{
2802 struct platform_device *pdev = to_platform_device(hsotg->dev);
2803
ca2c5ba8 2804 if (hsotg->uphy)
74084844 2805 usb_phy_shutdown(hsotg->uphy);
ca2c5ba8 2806 else if (hsotg->plat && hsotg->plat->phy_exit)
41188786 2807 hsotg->plat->phy_exit(pdev, hsotg->plat->phy_type);
ca2c5ba8
KD
2808 else {
2809 phy_power_off(hsotg->phy);
2810 phy_exit(hsotg->phy);
2811 }
41188786
LM
2812}
2813
8b9bc460
LM
2814/**
2815 * s3c_hsotg_init - initalize the usb core
2816 * @hsotg: The driver state
2817 */
b3f489b2
LM
2818static void s3c_hsotg_init(struct s3c_hsotg *hsotg)
2819{
2820 /* unmask subset of endpoint interrupts */
2821
47a1685f
DN
2822 writel(DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK |
2823 DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK,
2824 hsotg->regs + DIEPMSK);
b3f489b2 2825
47a1685f
DN
2826 writel(DOEPMSK_SETUPMSK | DOEPMSK_AHBERRMSK |
2827 DOEPMSK_EPDISBLDMSK | DOEPMSK_XFERCOMPLMSK,
2828 hsotg->regs + DOEPMSK);
b3f489b2 2829
94cb8fd6 2830 writel(0, hsotg->regs + DAINTMSK);
b3f489b2
LM
2831
2832 /* Be in disconnected state until gadget is registered */
47a1685f 2833 __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON);
b3f489b2
LM
2834
2835 if (0) {
2836 /* post global nak until we're ready */
47a1685f 2837 writel(DCTL_SGNPINNAK | DCTL_SGOUTNAK,
94cb8fd6 2838 hsotg->regs + DCTL);
b3f489b2
LM
2839 }
2840
2841 /* setup fifos */
2842
2843 dev_dbg(hsotg->dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
94cb8fd6
LM
2844 readl(hsotg->regs + GRXFSIZ),
2845 readl(hsotg->regs + GNPTXFSIZ));
b3f489b2
LM
2846
2847 s3c_hsotg_init_fifo(hsotg);
2848
2849 /* set the PLL on, remove the HNP/SRP and set the PHY */
47a1685f 2850 writel(GUSBCFG_PHYIF16 | GUSBCFG_TOUTCAL(7) | (0x5 << 10),
94cb8fd6 2851 hsotg->regs + GUSBCFG);
b3f489b2 2852
47a1685f 2853 writel(using_dma(hsotg) ? GAHBCFG_DMA_EN : 0x0,
94cb8fd6 2854 hsotg->regs + GAHBCFG);
b3f489b2
LM
2855}
2856
8b9bc460
LM
2857/**
2858 * s3c_hsotg_udc_start - prepare the udc for work
2859 * @gadget: The usb gadget state
2860 * @driver: The usb gadget driver
2861 *
2862 * Perform initialization to prepare udc device and driver
2863 * to work.
2864 */
f65f0f10
LM
2865static int s3c_hsotg_udc_start(struct usb_gadget *gadget,
2866 struct usb_gadget_driver *driver)
5b7d70c6 2867{
f99b2bfe 2868 struct s3c_hsotg *hsotg = to_hsotg(gadget);
5b7d70c6
BD
2869 int ret;
2870
2871 if (!hsotg) {
a023da33 2872 pr_err("%s: called with no device\n", __func__);
5b7d70c6
BD
2873 return -ENODEV;
2874 }
2875
2876 if (!driver) {
2877 dev_err(hsotg->dev, "%s: no driver\n", __func__);
2878 return -EINVAL;
2879 }
2880
7177aed4 2881 if (driver->max_speed < USB_SPEED_FULL)
5b7d70c6 2882 dev_err(hsotg->dev, "%s: bad speed\n", __func__);
5b7d70c6 2883
f65f0f10 2884 if (!driver->setup) {
5b7d70c6
BD
2885 dev_err(hsotg->dev, "%s: missing entry points\n", __func__);
2886 return -EINVAL;
2887 }
2888
2889 WARN_ON(hsotg->driver);
2890
2891 driver->driver.bus = NULL;
2892 hsotg->driver = driver;
7d7b2292 2893 hsotg->gadget.dev.of_node = hsotg->dev->of_node;
5b7d70c6
BD
2894 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
2895
d00b4142
RB
2896 clk_enable(hsotg->clk);
2897
f65f0f10
LM
2898 ret = regulator_bulk_enable(ARRAY_SIZE(hsotg->supplies),
2899 hsotg->supplies);
5b7d70c6 2900 if (ret) {
f65f0f10 2901 dev_err(hsotg->dev, "failed to enable supplies: %d\n", ret);
5b7d70c6
BD
2902 goto err;
2903 }
2904
12a1f4dc 2905 hsotg->last_rst = jiffies;
5b7d70c6
BD
2906 dev_info(hsotg->dev, "bound driver %s\n", driver->driver.name);
2907 return 0;
2908
2909err:
2910 hsotg->driver = NULL;
5b7d70c6
BD
2911 return ret;
2912}
2913
8b9bc460
LM
2914/**
2915 * s3c_hsotg_udc_stop - stop the udc
2916 * @gadget: The usb gadget state
2917 * @driver: The usb gadget driver
2918 *
2919 * Stop udc hw block and stay tunned for future transmissions
2920 */
f65f0f10
LM
2921static int s3c_hsotg_udc_stop(struct usb_gadget *gadget,
2922 struct usb_gadget_driver *driver)
5b7d70c6 2923{
f99b2bfe 2924 struct s3c_hsotg *hsotg = to_hsotg(gadget);
2b19a52c 2925 unsigned long flags = 0;
5b7d70c6
BD
2926 int ep;
2927
2928 if (!hsotg)
2929 return -ENODEV;
2930
5b7d70c6 2931 /* all endpoints should be shutdown */
604eac3c 2932 for (ep = 1; ep < hsotg->num_of_eps; ep++)
5b7d70c6
BD
2933 s3c_hsotg_ep_disable(&hsotg->eps[ep].ep);
2934
2b19a52c
LM
2935 spin_lock_irqsave(&hsotg->lock, flags);
2936
c8c10253
MS
2937 if (!driver)
2938 hsotg->driver = NULL;
2939
5b7d70c6 2940 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
5b7d70c6 2941
2b19a52c
LM
2942 spin_unlock_irqrestore(&hsotg->lock, flags);
2943
c8c10253 2944 regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies), hsotg->supplies);
5b7d70c6 2945
d00b4142
RB
2946 clk_disable(hsotg->clk);
2947
5b7d70c6
BD
2948 return 0;
2949}
5b7d70c6 2950
8b9bc460
LM
2951/**
2952 * s3c_hsotg_gadget_getframe - read the frame number
2953 * @gadget: The usb gadget state
2954 *
2955 * Read the {micro} frame number
2956 */
5b7d70c6
BD
2957static int s3c_hsotg_gadget_getframe(struct usb_gadget *gadget)
2958{
2959 return s3c_hsotg_read_frameno(to_hsotg(gadget));
2960}
2961
a188b689
LM
2962/**
2963 * s3c_hsotg_pullup - connect/disconnect the USB PHY
2964 * @gadget: The usb gadget state
2965 * @is_on: Current state of the USB PHY
2966 *
2967 * Connect/Disconnect the USB PHY pullup
2968 */
2969static int s3c_hsotg_pullup(struct usb_gadget *gadget, int is_on)
2970{
2971 struct s3c_hsotg *hsotg = to_hsotg(gadget);
2972 unsigned long flags = 0;
2973
d784f1e5 2974 dev_dbg(hsotg->dev, "%s: is_on: %d\n", __func__, is_on);
a188b689
LM
2975
2976 spin_lock_irqsave(&hsotg->lock, flags);
2977 if (is_on) {
2978 s3c_hsotg_phy_enable(hsotg);
d00b4142 2979 clk_enable(hsotg->clk);
a188b689
LM
2980 s3c_hsotg_core_init(hsotg);
2981 } else {
d00b4142 2982 clk_disable(hsotg->clk);
a188b689
LM
2983 s3c_hsotg_phy_disable(hsotg);
2984 }
2985
2986 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
2987 spin_unlock_irqrestore(&hsotg->lock, flags);
2988
2989 return 0;
2990}
2991
eeef4587 2992static const struct usb_gadget_ops s3c_hsotg_gadget_ops = {
5b7d70c6 2993 .get_frame = s3c_hsotg_gadget_getframe,
f65f0f10
LM
2994 .udc_start = s3c_hsotg_udc_start,
2995 .udc_stop = s3c_hsotg_udc_stop,
a188b689 2996 .pullup = s3c_hsotg_pullup,
5b7d70c6
BD
2997};
2998
2999/**
3000 * s3c_hsotg_initep - initialise a single endpoint
3001 * @hsotg: The device state.
3002 * @hs_ep: The endpoint to be initialised.
3003 * @epnum: The endpoint number
3004 *
3005 * Initialise the given endpoint (as part of the probe and device state
3006 * creation) to give to the gadget driver. Setup the endpoint name, any
3007 * direction information and other state that may be required.
3008 */
41ac7b3a 3009static void s3c_hsotg_initep(struct s3c_hsotg *hsotg,
5b7d70c6
BD
3010 struct s3c_hsotg_ep *hs_ep,
3011 int epnum)
3012{
5b7d70c6
BD
3013 char *dir;
3014
3015 if (epnum == 0)
3016 dir = "";
3017 else if ((epnum % 2) == 0) {
3018 dir = "out";
3019 } else {
3020 dir = "in";
3021 hs_ep->dir_in = 1;
3022 }
3023
3024 hs_ep->index = epnum;
3025
3026 snprintf(hs_ep->name, sizeof(hs_ep->name), "ep%d%s", epnum, dir);
3027
3028 INIT_LIST_HEAD(&hs_ep->queue);
3029 INIT_LIST_HEAD(&hs_ep->ep.ep_list);
3030
5b7d70c6
BD
3031 /* add to the list of endpoints known by the gadget driver */
3032 if (epnum)
3033 list_add_tail(&hs_ep->ep.ep_list, &hsotg->gadget.ep_list);
3034
3035 hs_ep->parent = hsotg;
3036 hs_ep->ep.name = hs_ep->name;
e117e742 3037 usb_ep_set_maxpacket_limit(&hs_ep->ep, epnum ? 1024 : EP0_MPS_LIMIT);
5b7d70c6
BD
3038 hs_ep->ep.ops = &s3c_hsotg_ep_ops;
3039
8b9bc460
LM
3040 /*
3041 * if we're using dma, we need to set the next-endpoint pointer
5b7d70c6
BD
3042 * to be something valid.
3043 */
3044
3045 if (using_dma(hsotg)) {
47a1685f 3046 u32 next = DXEPCTL_NEXTEP((epnum + 1) % 15);
94cb8fd6
LM
3047 writel(next, hsotg->regs + DIEPCTL(epnum));
3048 writel(next, hsotg->regs + DOEPCTL(epnum));
5b7d70c6
BD
3049 }
3050}
3051
b3f489b2
LM
3052/**
3053 * s3c_hsotg_hw_cfg - read HW configuration registers
3054 * @param: The device state
3055 *
3056 * Read the USB core HW configuration registers
3057 */
3058static void s3c_hsotg_hw_cfg(struct s3c_hsotg *hsotg)
5b7d70c6 3059{
cff9eb75 3060 u32 cfg2, cfg3, cfg4;
b3f489b2 3061 /* check hardware configuration */
5b7d70c6 3062
b3f489b2
LM
3063 cfg2 = readl(hsotg->regs + 0x48);
3064 hsotg->num_of_eps = (cfg2 >> 10) & 0xF;
10aebc77 3065
cff9eb75
MS
3066 cfg3 = readl(hsotg->regs + 0x4C);
3067 hsotg->fifo_mem = (cfg3 >> 16);
10aebc77
BD
3068
3069 cfg4 = readl(hsotg->regs + 0x50);
3070 hsotg->dedicated_fifos = (cfg4 >> 25) & 1;
3071
cff9eb75
MS
3072 dev_info(hsotg->dev, "EPs: %d, %s fifos, %d entries in SPRAM\n",
3073 hsotg->num_of_eps,
3074 hsotg->dedicated_fifos ? "dedicated" : "shared",
3075 hsotg->fifo_mem);
5b7d70c6
BD
3076}
3077
8b9bc460
LM
3078/**
3079 * s3c_hsotg_dump - dump state of the udc
3080 * @param: The device state
3081 */
5b7d70c6
BD
3082static void s3c_hsotg_dump(struct s3c_hsotg *hsotg)
3083{
83a01804 3084#ifdef DEBUG
5b7d70c6
BD
3085 struct device *dev = hsotg->dev;
3086 void __iomem *regs = hsotg->regs;
3087 u32 val;
3088 int idx;
3089
3090 dev_info(dev, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n",
94cb8fd6
LM
3091 readl(regs + DCFG), readl(regs + DCTL),
3092 readl(regs + DIEPMSK));
5b7d70c6
BD
3093
3094 dev_info(dev, "GAHBCFG=0x%08x, 0x44=0x%08x\n",
94cb8fd6 3095 readl(regs + GAHBCFG), readl(regs + 0x44));
5b7d70c6
BD
3096
3097 dev_info(dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
94cb8fd6 3098 readl(regs + GRXFSIZ), readl(regs + GNPTXFSIZ));
5b7d70c6
BD
3099
3100 /* show periodic fifo settings */
3101
3102 for (idx = 1; idx <= 15; idx++) {
47a1685f 3103 val = readl(regs + DPTXFSIZN(idx));
5b7d70c6 3104 dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx,
47a1685f
DN
3105 val >> FIFOSIZE_DEPTH_SHIFT,
3106 val & FIFOSIZE_STARTADDR_MASK);
5b7d70c6
BD
3107 }
3108
3109 for (idx = 0; idx < 15; idx++) {
3110 dev_info(dev,
3111 "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx,
94cb8fd6
LM
3112 readl(regs + DIEPCTL(idx)),
3113 readl(regs + DIEPTSIZ(idx)),
3114 readl(regs + DIEPDMA(idx)));
5b7d70c6 3115
94cb8fd6 3116 val = readl(regs + DOEPCTL(idx));
5b7d70c6
BD
3117 dev_info(dev,
3118 "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n",
94cb8fd6
LM
3119 idx, readl(regs + DOEPCTL(idx)),
3120 readl(regs + DOEPTSIZ(idx)),
3121 readl(regs + DOEPDMA(idx)));
5b7d70c6
BD
3122
3123 }
3124
3125 dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n",
94cb8fd6 3126 readl(regs + DVBUSDIS), readl(regs + DVBUSPULSE));
83a01804 3127#endif
5b7d70c6
BD
3128}
3129
5b7d70c6
BD
3130/**
3131 * state_show - debugfs: show overall driver and device state.
3132 * @seq: The seq file to write to.
3133 * @v: Unused parameter.
3134 *
3135 * This debugfs entry shows the overall state of the hardware and
3136 * some general information about each of the endpoints available
3137 * to the system.
3138 */
3139static int state_show(struct seq_file *seq, void *v)
3140{
3141 struct s3c_hsotg *hsotg = seq->private;
3142 void __iomem *regs = hsotg->regs;
3143 int idx;
3144
3145 seq_printf(seq, "DCFG=0x%08x, DCTL=0x%08x, DSTS=0x%08x\n",
94cb8fd6
LM
3146 readl(regs + DCFG),
3147 readl(regs + DCTL),
3148 readl(regs + DSTS));
5b7d70c6
BD
3149
3150 seq_printf(seq, "DIEPMSK=0x%08x, DOEPMASK=0x%08x\n",
94cb8fd6 3151 readl(regs + DIEPMSK), readl(regs + DOEPMSK));
5b7d70c6
BD
3152
3153 seq_printf(seq, "GINTMSK=0x%08x, GINTSTS=0x%08x\n",
94cb8fd6
LM
3154 readl(regs + GINTMSK),
3155 readl(regs + GINTSTS));
5b7d70c6
BD
3156
3157 seq_printf(seq, "DAINTMSK=0x%08x, DAINT=0x%08x\n",
94cb8fd6
LM
3158 readl(regs + DAINTMSK),
3159 readl(regs + DAINT));
5b7d70c6
BD
3160
3161 seq_printf(seq, "GNPTXSTS=0x%08x, GRXSTSR=%08x\n",
94cb8fd6
LM
3162 readl(regs + GNPTXSTS),
3163 readl(regs + GRXSTSR));
5b7d70c6 3164
a023da33 3165 seq_puts(seq, "\nEndpoint status:\n");
5b7d70c6
BD
3166
3167 for (idx = 0; idx < 15; idx++) {
3168 u32 in, out;
3169
94cb8fd6
LM
3170 in = readl(regs + DIEPCTL(idx));
3171 out = readl(regs + DOEPCTL(idx));
5b7d70c6
BD
3172
3173 seq_printf(seq, "ep%d: DIEPCTL=0x%08x, DOEPCTL=0x%08x",
3174 idx, in, out);
3175
94cb8fd6
LM
3176 in = readl(regs + DIEPTSIZ(idx));
3177 out = readl(regs + DOEPTSIZ(idx));
5b7d70c6
BD
3178
3179 seq_printf(seq, ", DIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x",
3180 in, out);
3181
a023da33 3182 seq_puts(seq, "\n");
5b7d70c6
BD
3183 }
3184
3185 return 0;
3186}
3187
3188static int state_open(struct inode *inode, struct file *file)
3189{
3190 return single_open(file, state_show, inode->i_private);
3191}
3192
3193static const struct file_operations state_fops = {
3194 .owner = THIS_MODULE,
3195 .open = state_open,
3196 .read = seq_read,
3197 .llseek = seq_lseek,
3198 .release = single_release,
3199};
3200
3201/**
3202 * fifo_show - debugfs: show the fifo information
3203 * @seq: The seq_file to write data to.
3204 * @v: Unused parameter.
3205 *
3206 * Show the FIFO information for the overall fifo and all the
3207 * periodic transmission FIFOs.
8b9bc460 3208 */
5b7d70c6
BD
3209static int fifo_show(struct seq_file *seq, void *v)
3210{
3211 struct s3c_hsotg *hsotg = seq->private;
3212 void __iomem *regs = hsotg->regs;
3213 u32 val;
3214 int idx;
3215
a023da33 3216 seq_puts(seq, "Non-periodic FIFOs:\n");
94cb8fd6 3217 seq_printf(seq, "RXFIFO: Size %d\n", readl(regs + GRXFSIZ));
5b7d70c6 3218
94cb8fd6 3219 val = readl(regs + GNPTXFSIZ);
5b7d70c6 3220 seq_printf(seq, "NPTXFIFO: Size %d, Start 0x%08x\n",
47a1685f
DN
3221 val >> FIFOSIZE_DEPTH_SHIFT,
3222 val & FIFOSIZE_DEPTH_MASK);
5b7d70c6 3223
a023da33 3224 seq_puts(seq, "\nPeriodic TXFIFOs:\n");
5b7d70c6
BD
3225
3226 for (idx = 1; idx <= 15; idx++) {
47a1685f 3227 val = readl(regs + DPTXFSIZN(idx));
5b7d70c6
BD
3228
3229 seq_printf(seq, "\tDPTXFIFO%2d: Size %d, Start 0x%08x\n", idx,
47a1685f
DN
3230 val >> FIFOSIZE_DEPTH_SHIFT,
3231 val & FIFOSIZE_STARTADDR_MASK);
5b7d70c6
BD
3232 }
3233
3234 return 0;
3235}
3236
3237static int fifo_open(struct inode *inode, struct file *file)
3238{
3239 return single_open(file, fifo_show, inode->i_private);
3240}
3241
3242static const struct file_operations fifo_fops = {
3243 .owner = THIS_MODULE,
3244 .open = fifo_open,
3245 .read = seq_read,
3246 .llseek = seq_lseek,
3247 .release = single_release,
3248};
3249
3250
3251static const char *decode_direction(int is_in)
3252{
3253 return is_in ? "in" : "out";
3254}
3255
3256/**
3257 * ep_show - debugfs: show the state of an endpoint.
3258 * @seq: The seq_file to write data to.
3259 * @v: Unused parameter.
3260 *
3261 * This debugfs entry shows the state of the given endpoint (one is
3262 * registered for each available).
8b9bc460 3263 */
5b7d70c6
BD
3264static int ep_show(struct seq_file *seq, void *v)
3265{
3266 struct s3c_hsotg_ep *ep = seq->private;
3267 struct s3c_hsotg *hsotg = ep->parent;
3268 struct s3c_hsotg_req *req;
3269 void __iomem *regs = hsotg->regs;
3270 int index = ep->index;
3271 int show_limit = 15;
3272 unsigned long flags;
3273
3274 seq_printf(seq, "Endpoint index %d, named %s, dir %s:\n",
3275 ep->index, ep->ep.name, decode_direction(ep->dir_in));
3276
3277 /* first show the register state */
3278
3279 seq_printf(seq, "\tDIEPCTL=0x%08x, DOEPCTL=0x%08x\n",
94cb8fd6
LM
3280 readl(regs + DIEPCTL(index)),
3281 readl(regs + DOEPCTL(index)));
5b7d70c6
BD
3282
3283 seq_printf(seq, "\tDIEPDMA=0x%08x, DOEPDMA=0x%08x\n",
94cb8fd6
LM
3284 readl(regs + DIEPDMA(index)),
3285 readl(regs + DOEPDMA(index)));
5b7d70c6
BD
3286
3287 seq_printf(seq, "\tDIEPINT=0x%08x, DOEPINT=0x%08x\n",
94cb8fd6
LM
3288 readl(regs + DIEPINT(index)),
3289 readl(regs + DOEPINT(index)));
5b7d70c6
BD
3290
3291 seq_printf(seq, "\tDIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x\n",
94cb8fd6
LM
3292 readl(regs + DIEPTSIZ(index)),
3293 readl(regs + DOEPTSIZ(index)));
5b7d70c6 3294
a023da33 3295 seq_puts(seq, "\n");
5b7d70c6
BD
3296 seq_printf(seq, "mps %d\n", ep->ep.maxpacket);
3297 seq_printf(seq, "total_data=%ld\n", ep->total_data);
3298
3299 seq_printf(seq, "request list (%p,%p):\n",
3300 ep->queue.next, ep->queue.prev);
3301
22258f49 3302 spin_lock_irqsave(&hsotg->lock, flags);
5b7d70c6
BD
3303
3304 list_for_each_entry(req, &ep->queue, queue) {
3305 if (--show_limit < 0) {
a023da33 3306 seq_puts(seq, "not showing more requests...\n");
5b7d70c6
BD
3307 break;
3308 }
3309
3310 seq_printf(seq, "%c req %p: %d bytes @%p, ",
3311 req == ep->req ? '*' : ' ',
3312 req, req->req.length, req->req.buf);
3313 seq_printf(seq, "%d done, res %d\n",
3314 req->req.actual, req->req.status);
3315 }
3316
22258f49 3317 spin_unlock_irqrestore(&hsotg->lock, flags);
5b7d70c6
BD
3318
3319 return 0;
3320}
3321
3322static int ep_open(struct inode *inode, struct file *file)
3323{
3324 return single_open(file, ep_show, inode->i_private);
3325}
3326
3327static const struct file_operations ep_fops = {
3328 .owner = THIS_MODULE,
3329 .open = ep_open,
3330 .read = seq_read,
3331 .llseek = seq_lseek,
3332 .release = single_release,
3333};
3334
3335/**
3336 * s3c_hsotg_create_debug - create debugfs directory and files
3337 * @hsotg: The driver state
3338 *
3339 * Create the debugfs files to allow the user to get information
3340 * about the state of the system. The directory name is created
3341 * with the same name as the device itself, in case we end up
3342 * with multiple blocks in future systems.
8b9bc460 3343 */
41ac7b3a 3344static void s3c_hsotg_create_debug(struct s3c_hsotg *hsotg)
5b7d70c6
BD
3345{
3346 struct dentry *root;
3347 unsigned epidx;
3348
3349 root = debugfs_create_dir(dev_name(hsotg->dev), NULL);
3350 hsotg->debug_root = root;
3351 if (IS_ERR(root)) {
3352 dev_err(hsotg->dev, "cannot create debug root\n");
3353 return;
3354 }
3355
3356 /* create general state file */
3357
3358 hsotg->debug_file = debugfs_create_file("state", 0444, root,
3359 hsotg, &state_fops);
3360
3361 if (IS_ERR(hsotg->debug_file))
3362 dev_err(hsotg->dev, "%s: failed to create state\n", __func__);
3363
3364 hsotg->debug_fifo = debugfs_create_file("fifo", 0444, root,
3365 hsotg, &fifo_fops);
3366
3367 if (IS_ERR(hsotg->debug_fifo))
3368 dev_err(hsotg->dev, "%s: failed to create fifo\n", __func__);
3369
3370 /* create one file for each endpoint */
3371
b3f489b2 3372 for (epidx = 0; epidx < hsotg->num_of_eps; epidx++) {
5b7d70c6
BD
3373 struct s3c_hsotg_ep *ep = &hsotg->eps[epidx];
3374
3375 ep->debugfs = debugfs_create_file(ep->name, 0444,
3376 root, ep, &ep_fops);
3377
3378 if (IS_ERR(ep->debugfs))
3379 dev_err(hsotg->dev, "failed to create %s debug file\n",
3380 ep->name);
3381 }
3382}
3383
3384/**
3385 * s3c_hsotg_delete_debug - cleanup debugfs entries
3386 * @hsotg: The driver state
3387 *
3388 * Cleanup (remove) the debugfs files for use on module exit.
8b9bc460 3389 */
fb4e98ab 3390static void s3c_hsotg_delete_debug(struct s3c_hsotg *hsotg)
5b7d70c6
BD
3391{
3392 unsigned epidx;
3393
b3f489b2 3394 for (epidx = 0; epidx < hsotg->num_of_eps; epidx++) {
5b7d70c6
BD
3395 struct s3c_hsotg_ep *ep = &hsotg->eps[epidx];
3396 debugfs_remove(ep->debugfs);
3397 }
3398
3399 debugfs_remove(hsotg->debug_file);
3400 debugfs_remove(hsotg->debug_fifo);
3401 debugfs_remove(hsotg->debug_root);
3402}
3403
8b9bc460
LM
3404/**
3405 * s3c_hsotg_probe - probe function for hsotg driver
3406 * @pdev: The platform information for the driver
3407 */
f026a52d 3408
41ac7b3a 3409static int s3c_hsotg_probe(struct platform_device *pdev)
5b7d70c6 3410{
e01ee9f5 3411 struct s3c_hsotg_plat *plat = dev_get_platdata(&pdev->dev);
74084844
MP
3412 struct phy *phy;
3413 struct usb_phy *uphy;
5b7d70c6 3414 struct device *dev = &pdev->dev;
b3f489b2 3415 struct s3c_hsotg_ep *eps;
5b7d70c6
BD
3416 struct s3c_hsotg *hsotg;
3417 struct resource *res;
3418 int epnum;
3419 int ret;
fc9a731e 3420 int i;
5b7d70c6 3421
338edabc 3422 hsotg = devm_kzalloc(&pdev->dev, sizeof(struct s3c_hsotg), GFP_KERNEL);
d04477d8 3423 if (!hsotg)
5b7d70c6 3424 return -ENOMEM;
5b7d70c6 3425
1b59fc7e
KD
3426 /* Set default UTMI width */
3427 hsotg->phyif = GUSBCFG_PHYIF16;
3428
74084844
MP
3429 /*
3430 * Attempt to find a generic PHY, then look for an old style
3431 * USB PHY, finally fall back to pdata
3432 */
3433 phy = devm_phy_get(&pdev->dev, "usb2-phy");
f4f5ba5e 3434 if (IS_ERR(phy)) {
74084844
MP
3435 uphy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
3436 if (IS_ERR(uphy)) {
3437 /* Fallback for pdata */
3438 plat = dev_get_platdata(&pdev->dev);
3439 if (!plat) {
3440 dev_err(&pdev->dev,
3441 "no platform data or transceiver defined\n");
3442 return -EPROBE_DEFER;
3443 }
b2e587db 3444 hsotg->plat = plat;
74084844
MP
3445 } else
3446 hsotg->uphy = uphy;
1b59fc7e 3447 } else {
b2e587db 3448 hsotg->phy = phy;
1b59fc7e
KD
3449 /*
3450 * If using the generic PHY framework, check if the PHY bus
3451 * width is 8-bit and set the phyif appropriately.
3452 */
3453 if (phy_get_bus_width(phy) == 8)
3454 hsotg->phyif = GUSBCFG_PHYIF8;
3455 }
b2e587db 3456
5b7d70c6 3457 hsotg->dev = dev;
5b7d70c6 3458
84749c6d 3459 hsotg->clk = devm_clk_get(&pdev->dev, "otg");
31ee04de
MS
3460 if (IS_ERR(hsotg->clk)) {
3461 dev_err(dev, "cannot get otg clock\n");
338edabc 3462 return PTR_ERR(hsotg->clk);
31ee04de
MS
3463 }
3464
5b7d70c6
BD
3465 platform_set_drvdata(pdev, hsotg);
3466
3467 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
5b7d70c6 3468
148e1134
TR
3469 hsotg->regs = devm_ioremap_resource(&pdev->dev, res);
3470 if (IS_ERR(hsotg->regs)) {
3471 ret = PTR_ERR(hsotg->regs);
338edabc 3472 goto err_clk;
5b7d70c6
BD
3473 }
3474
3475 ret = platform_get_irq(pdev, 0);
3476 if (ret < 0) {
3477 dev_err(dev, "cannot find IRQ\n");
338edabc 3478 goto err_clk;
5b7d70c6
BD
3479 }
3480
22258f49
LM
3481 spin_lock_init(&hsotg->lock);
3482
5b7d70c6
BD
3483 hsotg->irq = ret;
3484
5b7d70c6
BD
3485 dev_info(dev, "regs %p, irq %d\n", hsotg->regs, hsotg->irq);
3486
d327ab5b 3487 hsotg->gadget.max_speed = USB_SPEED_HIGH;
5b7d70c6
BD
3488 hsotg->gadget.ops = &s3c_hsotg_gadget_ops;
3489 hsotg->gadget.name = dev_name(dev);
5b7d70c6 3490
5b7d70c6
BD
3491 /* reset the system */
3492
04b4a0fc 3493 clk_prepare_enable(hsotg->clk);
31ee04de 3494
fc9a731e
LM
3495 /* regulators */
3496
3497 for (i = 0; i < ARRAY_SIZE(hsotg->supplies); i++)
3498 hsotg->supplies[i].supply = s3c_hsotg_supply_names[i];
3499
cd76213e 3500 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(hsotg->supplies),
fc9a731e
LM
3501 hsotg->supplies);
3502 if (ret) {
3503 dev_err(dev, "failed to request supplies: %d\n", ret);
338edabc 3504 goto err_clk;
fc9a731e
LM
3505 }
3506
3507 ret = regulator_bulk_enable(ARRAY_SIZE(hsotg->supplies),
3508 hsotg->supplies);
3509
3510 if (ret) {
3511 dev_err(hsotg->dev, "failed to enable supplies: %d\n", ret);
3512 goto err_supplies;
3513 }
3514
41188786
LM
3515 /* usb phy enable */
3516 s3c_hsotg_phy_enable(hsotg);
5b7d70c6 3517
5b7d70c6 3518 s3c_hsotg_corereset(hsotg);
b3f489b2 3519 s3c_hsotg_hw_cfg(hsotg);
cff9eb75 3520 s3c_hsotg_init(hsotg);
b3f489b2 3521
eb3c56c5
MS
3522 ret = devm_request_irq(&pdev->dev, hsotg->irq, s3c_hsotg_irq, 0,
3523 dev_name(dev), hsotg);
3524 if (ret < 0) {
3525 s3c_hsotg_phy_disable(hsotg);
3526 clk_disable_unprepare(hsotg->clk);
3527 regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies),
3528 hsotg->supplies);
3529 dev_err(dev, "cannot claim IRQ\n");
3530 goto err_clk;
3531 }
3532
b3f489b2
LM
3533 /* hsotg->num_of_eps holds number of EPs other than ep0 */
3534
3535 if (hsotg->num_of_eps == 0) {
3536 dev_err(dev, "wrong number of EPs (zero)\n");
dfdda5a0 3537 ret = -EINVAL;
b3f489b2
LM
3538 goto err_supplies;
3539 }
3540
3541 eps = kcalloc(hsotg->num_of_eps + 1, sizeof(struct s3c_hsotg_ep),
3542 GFP_KERNEL);
3543 if (!eps) {
dfdda5a0 3544 ret = -ENOMEM;
b3f489b2
LM
3545 goto err_supplies;
3546 }
3547
3548 hsotg->eps = eps;
3549
3550 /* setup endpoint information */
3551
3552 INIT_LIST_HEAD(&hsotg->gadget.ep_list);
3553 hsotg->gadget.ep0 = &hsotg->eps[0].ep;
3554
3555 /* allocate EP0 request */
3556
3557 hsotg->ctrl_req = s3c_hsotg_ep_alloc_request(&hsotg->eps[0].ep,
3558 GFP_KERNEL);
3559 if (!hsotg->ctrl_req) {
3560 dev_err(dev, "failed to allocate ctrl req\n");
dfdda5a0 3561 ret = -ENOMEM;
b3f489b2
LM
3562 goto err_ep_mem;
3563 }
5b7d70c6
BD
3564
3565 /* initialise the endpoints now the core has been initialised */
b3f489b2 3566 for (epnum = 0; epnum < hsotg->num_of_eps; epnum++)
5b7d70c6
BD
3567 s3c_hsotg_initep(hsotg, &hsotg->eps[epnum], epnum);
3568
f65f0f10
LM
3569 /* disable power and clock */
3570
3571 ret = regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies),
3572 hsotg->supplies);
3573 if (ret) {
3574 dev_err(hsotg->dev, "failed to disable supplies: %d\n", ret);
3575 goto err_ep_mem;
3576 }
3577
3578 s3c_hsotg_phy_disable(hsotg);
3579
0f91349b
SAS
3580 ret = usb_add_gadget_udc(&pdev->dev, &hsotg->gadget);
3581 if (ret)
b3f489b2 3582 goto err_ep_mem;
0f91349b 3583
5b7d70c6
BD
3584 s3c_hsotg_create_debug(hsotg);
3585
3586 s3c_hsotg_dump(hsotg);
3587
5b7d70c6
BD
3588 return 0;
3589
1d144c67 3590err_ep_mem:
b3f489b2 3591 kfree(eps);
fc9a731e 3592err_supplies:
41188786 3593 s3c_hsotg_phy_disable(hsotg);
31ee04de 3594err_clk:
1d144c67 3595 clk_disable_unprepare(hsotg->clk);
338edabc 3596
5b7d70c6
BD
3597 return ret;
3598}
3599
8b9bc460
LM
3600/**
3601 * s3c_hsotg_remove - remove function for hsotg driver
3602 * @pdev: The platform information for the driver
3603 */
fb4e98ab 3604static int s3c_hsotg_remove(struct platform_device *pdev)
5b7d70c6
BD
3605{
3606 struct s3c_hsotg *hsotg = platform_get_drvdata(pdev);
3607
0f91349b
SAS
3608 usb_del_gadget_udc(&hsotg->gadget);
3609
5b7d70c6
BD
3610 s3c_hsotg_delete_debug(hsotg);
3611
f65f0f10
LM
3612 if (hsotg->driver) {
3613 /* should have been done already by driver model core */
3614 usb_gadget_unregister_driver(hsotg->driver);
3615 }
5b7d70c6 3616
04b4a0fc 3617 clk_disable_unprepare(hsotg->clk);
31ee04de 3618
5b7d70c6
BD
3619 return 0;
3620}
3621
b83e333a
MS
3622static int s3c_hsotg_suspend(struct platform_device *pdev, pm_message_t state)
3623{
3624 struct s3c_hsotg *hsotg = platform_get_drvdata(pdev);
3625 unsigned long flags;
3626 int ret = 0;
3627
3628 if (hsotg->driver)
3629 dev_info(hsotg->dev, "suspending usb gadget %s\n",
3630 hsotg->driver->driver.name);
3631
3632 spin_lock_irqsave(&hsotg->lock, flags);
3633 s3c_hsotg_disconnect(hsotg);
3634 s3c_hsotg_phy_disable(hsotg);
3635 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
3636 spin_unlock_irqrestore(&hsotg->lock, flags);
3637
3638 if (hsotg->driver) {
3639 int ep;
3640 for (ep = 0; ep < hsotg->num_of_eps; ep++)
3641 s3c_hsotg_ep_disable(&hsotg->eps[ep].ep);
3642
3643 ret = regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies),
3644 hsotg->supplies);
d00b4142 3645 clk_disable(hsotg->clk);
b83e333a
MS
3646 }
3647
3648 return ret;
3649}
3650
3651static int s3c_hsotg_resume(struct platform_device *pdev)
3652{
3653 struct s3c_hsotg *hsotg = platform_get_drvdata(pdev);
3654 unsigned long flags;
3655 int ret = 0;
3656
3657 if (hsotg->driver) {
3658 dev_info(hsotg->dev, "resuming usb gadget %s\n",
3659 hsotg->driver->driver.name);
d00b4142
RB
3660
3661 clk_enable(hsotg->clk);
b83e333a
MS
3662 ret = regulator_bulk_enable(ARRAY_SIZE(hsotg->supplies),
3663 hsotg->supplies);
3664 }
3665
3666 spin_lock_irqsave(&hsotg->lock, flags);
3667 hsotg->last_rst = jiffies;
3668 s3c_hsotg_phy_enable(hsotg);
3669 s3c_hsotg_core_init(hsotg);
3670 spin_unlock_irqrestore(&hsotg->lock, flags);
3671
3672 return ret;
3673}
5b7d70c6 3674
c50f056c
TF
3675#ifdef CONFIG_OF
3676static const struct of_device_id s3c_hsotg_of_ids[] = {
3677 { .compatible = "samsung,s3c6400-hsotg", },
0d33d825 3678 { .compatible = "snps,dwc2", },
c50f056c
TF
3679 { /* sentinel */ }
3680};
3681MODULE_DEVICE_TABLE(of, s3c_hsotg_of_ids);
3682#endif
3683
5b7d70c6
BD
3684static struct platform_driver s3c_hsotg_driver = {
3685 .driver = {
3686 .name = "s3c-hsotg",
3687 .owner = THIS_MODULE,
c50f056c 3688 .of_match_table = of_match_ptr(s3c_hsotg_of_ids),
5b7d70c6
BD
3689 },
3690 .probe = s3c_hsotg_probe,
7690417d 3691 .remove = s3c_hsotg_remove,
5b7d70c6
BD
3692 .suspend = s3c_hsotg_suspend,
3693 .resume = s3c_hsotg_resume,
3694};
3695
cc27c96c 3696module_platform_driver(s3c_hsotg_driver);
5b7d70c6
BD
3697
3698MODULE_DESCRIPTION("Samsung S3C USB High-speed/OtG device");
3699MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
3700MODULE_LICENSE("GPL");
3701MODULE_ALIAS("platform:s3c-hsotg");