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5fd54ace | 1 | // SPDX-License-Identifier: GPL-2.0 |
8b9bc460 | 2 | /** |
dfbc6fa3 AT |
3 | * Copyright (c) 2011 Samsung Electronics Co., Ltd. |
4 | * http://www.samsung.com | |
5b7d70c6 BD |
5 | * |
6 | * Copyright 2008 Openmoko, Inc. | |
7 | * Copyright 2008 Simtec Electronics | |
8 | * Ben Dooks <ben@simtec.co.uk> | |
9 | * http://armlinux.simtec.co.uk/ | |
10 | * | |
11 | * S3C USB2.0 High-speed / OtG driver | |
8b9bc460 | 12 | */ |
5b7d70c6 BD |
13 | |
14 | #include <linux/kernel.h> | |
15 | #include <linux/module.h> | |
16 | #include <linux/spinlock.h> | |
17 | #include <linux/interrupt.h> | |
18 | #include <linux/platform_device.h> | |
19 | #include <linux/dma-mapping.h> | |
7ad8096e | 20 | #include <linux/mutex.h> |
5b7d70c6 BD |
21 | #include <linux/seq_file.h> |
22 | #include <linux/delay.h> | |
23 | #include <linux/io.h> | |
5a0e3ad6 | 24 | #include <linux/slab.h> |
c50f056c | 25 | #include <linux/of_platform.h> |
5b7d70c6 BD |
26 | |
27 | #include <linux/usb/ch9.h> | |
28 | #include <linux/usb/gadget.h> | |
b2e587db | 29 | #include <linux/usb/phy.h> |
5b7d70c6 | 30 | |
f7c0b143 | 31 | #include "core.h" |
941fcce4 | 32 | #include "hw.h" |
5b7d70c6 BD |
33 | |
34 | /* conversion functions */ | |
1f91b4cc | 35 | static inline struct dwc2_hsotg_req *our_req(struct usb_request *req) |
5b7d70c6 | 36 | { |
1f91b4cc | 37 | return container_of(req, struct dwc2_hsotg_req, req); |
5b7d70c6 BD |
38 | } |
39 | ||
1f91b4cc | 40 | static inline struct dwc2_hsotg_ep *our_ep(struct usb_ep *ep) |
5b7d70c6 | 41 | { |
1f91b4cc | 42 | return container_of(ep, struct dwc2_hsotg_ep, ep); |
5b7d70c6 BD |
43 | } |
44 | ||
941fcce4 | 45 | static inline struct dwc2_hsotg *to_hsotg(struct usb_gadget *gadget) |
5b7d70c6 | 46 | { |
941fcce4 | 47 | return container_of(gadget, struct dwc2_hsotg, gadget); |
5b7d70c6 BD |
48 | } |
49 | ||
abd064a1 | 50 | static inline void dwc2_set_bit(void __iomem *ptr, u32 val) |
5b7d70c6 | 51 | { |
95c8bc36 | 52 | dwc2_writel(dwc2_readl(ptr) | val, ptr); |
5b7d70c6 BD |
53 | } |
54 | ||
abd064a1 | 55 | static inline void dwc2_clear_bit(void __iomem *ptr, u32 val) |
5b7d70c6 | 56 | { |
95c8bc36 | 57 | dwc2_writel(dwc2_readl(ptr) & ~val, ptr); |
5b7d70c6 BD |
58 | } |
59 | ||
1f91b4cc | 60 | static inline struct dwc2_hsotg_ep *index_to_ep(struct dwc2_hsotg *hsotg, |
c6f5c050 MYK |
61 | u32 ep_index, u32 dir_in) |
62 | { | |
63 | if (dir_in) | |
64 | return hsotg->eps_in[ep_index]; | |
65 | else | |
66 | return hsotg->eps_out[ep_index]; | |
67 | } | |
68 | ||
997f4f81 | 69 | /* forward declaration of functions */ |
1f91b4cc | 70 | static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg); |
5b7d70c6 BD |
71 | |
72 | /** | |
73 | * using_dma - return the DMA status of the driver. | |
74 | * @hsotg: The driver state. | |
75 | * | |
76 | * Return true if we're using DMA. | |
77 | * | |
78 | * Currently, we have the DMA support code worked into everywhere | |
79 | * that needs it, but the AMBA DMA implementation in the hardware can | |
80 | * only DMA from 32bit aligned addresses. This means that gadgets such | |
81 | * as the CDC Ethernet cannot work as they often pass packets which are | |
82 | * not 32bit aligned. | |
83 | * | |
84 | * Unfortunately the choice to use DMA or not is global to the controller | |
85 | * and seems to be only settable when the controller is being put through | |
86 | * a core reset. This means we either need to fix the gadgets to take | |
87 | * account of DMA alignment, or add bounce buffers (yuerk). | |
88 | * | |
edd74be8 | 89 | * g_using_dma is set depending on dts flag. |
5b7d70c6 | 90 | */ |
941fcce4 | 91 | static inline bool using_dma(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 92 | { |
05ee799f | 93 | return hsotg->params.g_dma; |
5b7d70c6 BD |
94 | } |
95 | ||
dec4b556 VA |
96 | /* |
97 | * using_desc_dma - return the descriptor DMA status of the driver. | |
98 | * @hsotg: The driver state. | |
99 | * | |
100 | * Return true if we're using descriptor DMA. | |
101 | */ | |
102 | static inline bool using_desc_dma(struct dwc2_hsotg *hsotg) | |
103 | { | |
104 | return hsotg->params.g_dma_desc; | |
105 | } | |
106 | ||
92d1635d VM |
107 | /** |
108 | * dwc2_gadget_incr_frame_num - Increments the targeted frame number. | |
109 | * @hs_ep: The endpoint | |
110 | * @increment: The value to increment by | |
111 | * | |
112 | * This function will also check if the frame number overruns DSTS_SOFFN_LIMIT. | |
113 | * If an overrun occurs it will wrap the value and set the frame_overrun flag. | |
114 | */ | |
115 | static inline void dwc2_gadget_incr_frame_num(struct dwc2_hsotg_ep *hs_ep) | |
116 | { | |
117 | hs_ep->target_frame += hs_ep->interval; | |
118 | if (hs_ep->target_frame > DSTS_SOFFN_LIMIT) { | |
c1d5df69 | 119 | hs_ep->frame_overrun = true; |
92d1635d VM |
120 | hs_ep->target_frame &= DSTS_SOFFN_LIMIT; |
121 | } else { | |
c1d5df69 | 122 | hs_ep->frame_overrun = false; |
92d1635d VM |
123 | } |
124 | } | |
125 | ||
5b7d70c6 | 126 | /** |
1f91b4cc | 127 | * dwc2_hsotg_en_gsint - enable one or more of the general interrupt |
5b7d70c6 BD |
128 | * @hsotg: The device state |
129 | * @ints: A bitmask of the interrupts to enable | |
130 | */ | |
1f91b4cc | 131 | static void dwc2_hsotg_en_gsint(struct dwc2_hsotg *hsotg, u32 ints) |
5b7d70c6 | 132 | { |
95c8bc36 | 133 | u32 gsintmsk = dwc2_readl(hsotg->regs + GINTMSK); |
5b7d70c6 BD |
134 | u32 new_gsintmsk; |
135 | ||
136 | new_gsintmsk = gsintmsk | ints; | |
137 | ||
138 | if (new_gsintmsk != gsintmsk) { | |
139 | dev_dbg(hsotg->dev, "gsintmsk now 0x%08x\n", new_gsintmsk); | |
95c8bc36 | 140 | dwc2_writel(new_gsintmsk, hsotg->regs + GINTMSK); |
5b7d70c6 BD |
141 | } |
142 | } | |
143 | ||
144 | /** | |
1f91b4cc | 145 | * dwc2_hsotg_disable_gsint - disable one or more of the general interrupt |
5b7d70c6 BD |
146 | * @hsotg: The device state |
147 | * @ints: A bitmask of the interrupts to enable | |
148 | */ | |
1f91b4cc | 149 | static void dwc2_hsotg_disable_gsint(struct dwc2_hsotg *hsotg, u32 ints) |
5b7d70c6 | 150 | { |
95c8bc36 | 151 | u32 gsintmsk = dwc2_readl(hsotg->regs + GINTMSK); |
5b7d70c6 BD |
152 | u32 new_gsintmsk; |
153 | ||
154 | new_gsintmsk = gsintmsk & ~ints; | |
155 | ||
156 | if (new_gsintmsk != gsintmsk) | |
95c8bc36 | 157 | dwc2_writel(new_gsintmsk, hsotg->regs + GINTMSK); |
5b7d70c6 BD |
158 | } |
159 | ||
160 | /** | |
1f91b4cc | 161 | * dwc2_hsotg_ctrl_epint - enable/disable an endpoint irq |
5b7d70c6 BD |
162 | * @hsotg: The device state |
163 | * @ep: The endpoint index | |
164 | * @dir_in: True if direction is in. | |
165 | * @en: The enable value, true to enable | |
166 | * | |
167 | * Set or clear the mask for an individual endpoint's interrupt | |
168 | * request. | |
169 | */ | |
1f91b4cc | 170 | static void dwc2_hsotg_ctrl_epint(struct dwc2_hsotg *hsotg, |
9da51974 | 171 | unsigned int ep, unsigned int dir_in, |
5b7d70c6 BD |
172 | unsigned int en) |
173 | { | |
174 | unsigned long flags; | |
175 | u32 bit = 1 << ep; | |
176 | u32 daint; | |
177 | ||
178 | if (!dir_in) | |
179 | bit <<= 16; | |
180 | ||
181 | local_irq_save(flags); | |
95c8bc36 | 182 | daint = dwc2_readl(hsotg->regs + DAINTMSK); |
5b7d70c6 BD |
183 | if (en) |
184 | daint |= bit; | |
185 | else | |
186 | daint &= ~bit; | |
95c8bc36 | 187 | dwc2_writel(daint, hsotg->regs + DAINTMSK); |
5b7d70c6 BD |
188 | local_irq_restore(flags); |
189 | } | |
190 | ||
c138ecfa SA |
191 | /** |
192 | * dwc2_hsotg_tx_fifo_count - return count of TX FIFOs in device mode | |
193 | */ | |
194 | int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg *hsotg) | |
195 | { | |
196 | if (hsotg->hw_params.en_multiple_tx_fifo) | |
197 | /* In dedicated FIFO mode we need count of IN EPs */ | |
9273083a | 198 | return hsotg->hw_params.num_dev_in_eps; |
c138ecfa SA |
199 | else |
200 | /* In shared FIFO mode we need count of Periodic IN EPs */ | |
201 | return hsotg->hw_params.num_dev_perio_in_ep; | |
202 | } | |
203 | ||
c138ecfa SA |
204 | /** |
205 | * dwc2_hsotg_tx_fifo_total_depth - return total FIFO depth available for | |
206 | * device mode TX FIFOs | |
207 | */ | |
208 | int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg) | |
209 | { | |
c138ecfa SA |
210 | int addr; |
211 | int tx_addr_max; | |
212 | u32 np_tx_fifo_size; | |
213 | ||
214 | np_tx_fifo_size = min_t(u32, hsotg->hw_params.dev_nperio_tx_fifo_size, | |
215 | hsotg->params.g_np_tx_fifo_size); | |
216 | ||
217 | /* Get Endpoint Info Control block size in DWORDs. */ | |
9273083a | 218 | tx_addr_max = hsotg->hw_params.total_fifo_size; |
c138ecfa SA |
219 | |
220 | addr = hsotg->params.g_rx_fifo_size + np_tx_fifo_size; | |
221 | if (tx_addr_max <= addr) | |
222 | return 0; | |
223 | ||
224 | return tx_addr_max - addr; | |
225 | } | |
226 | ||
227 | /** | |
228 | * dwc2_hsotg_tx_fifo_average_depth - returns average depth of device mode | |
229 | * TX FIFOs | |
230 | */ | |
231 | int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg *hsotg) | |
232 | { | |
233 | int tx_fifo_count; | |
234 | int tx_fifo_depth; | |
235 | ||
236 | tx_fifo_depth = dwc2_hsotg_tx_fifo_total_depth(hsotg); | |
237 | ||
238 | tx_fifo_count = dwc2_hsotg_tx_fifo_count(hsotg); | |
239 | ||
240 | if (!tx_fifo_count) | |
241 | return tx_fifo_depth; | |
242 | else | |
243 | return tx_fifo_depth / tx_fifo_count; | |
244 | } | |
245 | ||
5b7d70c6 | 246 | /** |
1f91b4cc | 247 | * dwc2_hsotg_init_fifo - initialise non-periodic FIFOs |
5b7d70c6 BD |
248 | * @hsotg: The device instance. |
249 | */ | |
1f91b4cc | 250 | static void dwc2_hsotg_init_fifo(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 251 | { |
2317eacd | 252 | unsigned int ep; |
0f002d20 | 253 | unsigned int addr; |
1703a6d3 | 254 | int timeout; |
79d6b8c5 | 255 | |
0f002d20 | 256 | u32 val; |
05ee799f | 257 | u32 *txfsz = hsotg->params.g_tx_fifo_size; |
0f002d20 | 258 | |
7fcbc95c GH |
259 | /* Reset fifo map if not correctly cleared during previous session */ |
260 | WARN_ON(hsotg->fifo_map); | |
261 | hsotg->fifo_map = 0; | |
262 | ||
0a176279 | 263 | /* set RX/NPTX FIFO sizes */ |
05ee799f JY |
264 | dwc2_writel(hsotg->params.g_rx_fifo_size, hsotg->regs + GRXFSIZ); |
265 | dwc2_writel((hsotg->params.g_rx_fifo_size << FIFOSIZE_STARTADDR_SHIFT) | | |
266 | (hsotg->params.g_np_tx_fifo_size << FIFOSIZE_DEPTH_SHIFT), | |
267 | hsotg->regs + GNPTXFSIZ); | |
0f002d20 | 268 | |
8b9bc460 LM |
269 | /* |
270 | * arange all the rest of the TX FIFOs, as some versions of this | |
0f002d20 BD |
271 | * block have overlapping default addresses. This also ensures |
272 | * that if the settings have been changed, then they are set to | |
8b9bc460 LM |
273 | * known values. |
274 | */ | |
0f002d20 BD |
275 | |
276 | /* start at the end of the GNPTXFSIZ, rounded up */ | |
05ee799f | 277 | addr = hsotg->params.g_rx_fifo_size + hsotg->params.g_np_tx_fifo_size; |
0f002d20 | 278 | |
8b9bc460 | 279 | /* |
0a176279 | 280 | * Configure fifos sizes from provided configuration and assign |
b203d0a2 RB |
281 | * them to endpoints dynamically according to maxpacket size value of |
282 | * given endpoint. | |
8b9bc460 | 283 | */ |
2317eacd | 284 | for (ep = 1; ep < MAX_EPS_CHANNELS; ep++) { |
05ee799f | 285 | if (!txfsz[ep]) |
3fa95385 JY |
286 | continue; |
287 | val = addr; | |
05ee799f JY |
288 | val |= txfsz[ep] << FIFOSIZE_DEPTH_SHIFT; |
289 | WARN_ONCE(addr + txfsz[ep] > hsotg->fifo_mem, | |
3fa95385 | 290 | "insufficient fifo memory"); |
05ee799f | 291 | addr += txfsz[ep]; |
0f002d20 | 292 | |
2317eacd | 293 | dwc2_writel(val, hsotg->regs + DPTXFSIZN(ep)); |
05ee799f | 294 | val = dwc2_readl(hsotg->regs + DPTXFSIZN(ep)); |
0f002d20 | 295 | } |
1703a6d3 | 296 | |
f87c842f SA |
297 | dwc2_writel(hsotg->hw_params.total_fifo_size | |
298 | addr << GDFIFOCFG_EPINFOBASE_SHIFT, | |
299 | hsotg->regs + GDFIFOCFG); | |
8b9bc460 LM |
300 | /* |
301 | * according to p428 of the design guide, we need to ensure that | |
302 | * all fifos are flushed before continuing | |
303 | */ | |
1703a6d3 | 304 | |
95c8bc36 | 305 | dwc2_writel(GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH | |
47a1685f | 306 | GRSTCTL_RXFFLSH, hsotg->regs + GRSTCTL); |
1703a6d3 BD |
307 | |
308 | /* wait until the fifos are both flushed */ | |
309 | timeout = 100; | |
310 | while (1) { | |
95c8bc36 | 311 | val = dwc2_readl(hsotg->regs + GRSTCTL); |
1703a6d3 | 312 | |
47a1685f | 313 | if ((val & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH)) == 0) |
1703a6d3 BD |
314 | break; |
315 | ||
316 | if (--timeout == 0) { | |
317 | dev_err(hsotg->dev, | |
318 | "%s: timeout flushing fifos (GRSTCTL=%08x)\n", | |
319 | __func__, val); | |
48b20bcb | 320 | break; |
1703a6d3 BD |
321 | } |
322 | ||
323 | udelay(1); | |
324 | } | |
325 | ||
326 | dev_dbg(hsotg->dev, "FIFOs reset, timeout at %d\n", timeout); | |
5b7d70c6 BD |
327 | } |
328 | ||
329 | /** | |
330 | * @ep: USB endpoint to allocate request for. | |
331 | * @flags: Allocation flags | |
332 | * | |
333 | * Allocate a new USB request structure appropriate for the specified endpoint | |
334 | */ | |
1f91b4cc | 335 | static struct usb_request *dwc2_hsotg_ep_alloc_request(struct usb_ep *ep, |
9da51974 | 336 | gfp_t flags) |
5b7d70c6 | 337 | { |
1f91b4cc | 338 | struct dwc2_hsotg_req *req; |
5b7d70c6 | 339 | |
ec33efe2 | 340 | req = kzalloc(sizeof(*req), flags); |
5b7d70c6 BD |
341 | if (!req) |
342 | return NULL; | |
343 | ||
344 | INIT_LIST_HEAD(&req->queue); | |
345 | ||
5b7d70c6 BD |
346 | return &req->req; |
347 | } | |
348 | ||
349 | /** | |
350 | * is_ep_periodic - return true if the endpoint is in periodic mode. | |
351 | * @hs_ep: The endpoint to query. | |
352 | * | |
353 | * Returns true if the endpoint is in periodic mode, meaning it is being | |
354 | * used for an Interrupt or ISO transfer. | |
355 | */ | |
1f91b4cc | 356 | static inline int is_ep_periodic(struct dwc2_hsotg_ep *hs_ep) |
5b7d70c6 BD |
357 | { |
358 | return hs_ep->periodic; | |
359 | } | |
360 | ||
361 | /** | |
1f91b4cc | 362 | * dwc2_hsotg_unmap_dma - unmap the DMA memory being used for the request |
5b7d70c6 BD |
363 | * @hsotg: The device state. |
364 | * @hs_ep: The endpoint for the request | |
365 | * @hs_req: The request being processed. | |
366 | * | |
1f91b4cc | 367 | * This is the reverse of dwc2_hsotg_map_dma(), called for the completion |
5b7d70c6 | 368 | * of a request to ensure the buffer is ready for access by the caller. |
8b9bc460 | 369 | */ |
1f91b4cc | 370 | static void dwc2_hsotg_unmap_dma(struct dwc2_hsotg *hsotg, |
9da51974 | 371 | struct dwc2_hsotg_ep *hs_ep, |
1f91b4cc | 372 | struct dwc2_hsotg_req *hs_req) |
5b7d70c6 BD |
373 | { |
374 | struct usb_request *req = &hs_req->req; | |
9da51974 | 375 | |
17d966a3 | 376 | usb_gadget_unmap_request(&hsotg->gadget, req, hs_ep->dir_in); |
5b7d70c6 BD |
377 | } |
378 | ||
0f6b80c0 VA |
379 | /* |
380 | * dwc2_gadget_alloc_ctrl_desc_chains - allocate DMA descriptor chains | |
381 | * for Control endpoint | |
382 | * @hsotg: The device state. | |
383 | * | |
384 | * This function will allocate 4 descriptor chains for EP 0: 2 for | |
385 | * Setup stage, per one for IN and OUT data/status transactions. | |
386 | */ | |
387 | static int dwc2_gadget_alloc_ctrl_desc_chains(struct dwc2_hsotg *hsotg) | |
388 | { | |
389 | hsotg->setup_desc[0] = | |
390 | dmam_alloc_coherent(hsotg->dev, | |
391 | sizeof(struct dwc2_dma_desc), | |
392 | &hsotg->setup_desc_dma[0], | |
393 | GFP_KERNEL); | |
394 | if (!hsotg->setup_desc[0]) | |
395 | goto fail; | |
396 | ||
397 | hsotg->setup_desc[1] = | |
398 | dmam_alloc_coherent(hsotg->dev, | |
399 | sizeof(struct dwc2_dma_desc), | |
400 | &hsotg->setup_desc_dma[1], | |
401 | GFP_KERNEL); | |
402 | if (!hsotg->setup_desc[1]) | |
403 | goto fail; | |
404 | ||
405 | hsotg->ctrl_in_desc = | |
406 | dmam_alloc_coherent(hsotg->dev, | |
407 | sizeof(struct dwc2_dma_desc), | |
408 | &hsotg->ctrl_in_desc_dma, | |
409 | GFP_KERNEL); | |
410 | if (!hsotg->ctrl_in_desc) | |
411 | goto fail; | |
412 | ||
413 | hsotg->ctrl_out_desc = | |
414 | dmam_alloc_coherent(hsotg->dev, | |
415 | sizeof(struct dwc2_dma_desc), | |
416 | &hsotg->ctrl_out_desc_dma, | |
417 | GFP_KERNEL); | |
418 | if (!hsotg->ctrl_out_desc) | |
419 | goto fail; | |
420 | ||
421 | return 0; | |
422 | ||
423 | fail: | |
424 | return -ENOMEM; | |
425 | } | |
426 | ||
5b7d70c6 | 427 | /** |
1f91b4cc | 428 | * dwc2_hsotg_write_fifo - write packet Data to the TxFIFO |
5b7d70c6 BD |
429 | * @hsotg: The controller state. |
430 | * @hs_ep: The endpoint we're going to write for. | |
431 | * @hs_req: The request to write data for. | |
432 | * | |
433 | * This is called when the TxFIFO has some space in it to hold a new | |
434 | * transmission and we have something to give it. The actual setup of | |
435 | * the data size is done elsewhere, so all we have to do is to actually | |
436 | * write the data. | |
437 | * | |
438 | * The return value is zero if there is more space (or nothing was done) | |
439 | * otherwise -ENOSPC is returned if the FIFO space was used up. | |
440 | * | |
441 | * This routine is only needed for PIO | |
8b9bc460 | 442 | */ |
1f91b4cc | 443 | static int dwc2_hsotg_write_fifo(struct dwc2_hsotg *hsotg, |
9da51974 | 444 | struct dwc2_hsotg_ep *hs_ep, |
1f91b4cc | 445 | struct dwc2_hsotg_req *hs_req) |
5b7d70c6 BD |
446 | { |
447 | bool periodic = is_ep_periodic(hs_ep); | |
95c8bc36 | 448 | u32 gnptxsts = dwc2_readl(hsotg->regs + GNPTXSTS); |
5b7d70c6 BD |
449 | int buf_pos = hs_req->req.actual; |
450 | int to_write = hs_ep->size_loaded; | |
451 | void *data; | |
452 | int can_write; | |
453 | int pkt_round; | |
4fca54aa | 454 | int max_transfer; |
5b7d70c6 BD |
455 | |
456 | to_write -= (buf_pos - hs_ep->last_load); | |
457 | ||
458 | /* if there's nothing to write, get out early */ | |
459 | if (to_write == 0) | |
460 | return 0; | |
461 | ||
10aebc77 | 462 | if (periodic && !hsotg->dedicated_fifos) { |
95c8bc36 | 463 | u32 epsize = dwc2_readl(hsotg->regs + DIEPTSIZ(hs_ep->index)); |
5b7d70c6 BD |
464 | int size_left; |
465 | int size_done; | |
466 | ||
8b9bc460 LM |
467 | /* |
468 | * work out how much data was loaded so we can calculate | |
469 | * how much data is left in the fifo. | |
470 | */ | |
5b7d70c6 | 471 | |
47a1685f | 472 | size_left = DXEPTSIZ_XFERSIZE_GET(epsize); |
5b7d70c6 | 473 | |
8b9bc460 LM |
474 | /* |
475 | * if shared fifo, we cannot write anything until the | |
e7a9ff54 BD |
476 | * previous data has been completely sent. |
477 | */ | |
478 | if (hs_ep->fifo_load != 0) { | |
1f91b4cc | 479 | dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP); |
e7a9ff54 BD |
480 | return -ENOSPC; |
481 | } | |
482 | ||
5b7d70c6 BD |
483 | dev_dbg(hsotg->dev, "%s: left=%d, load=%d, fifo=%d, size %d\n", |
484 | __func__, size_left, | |
485 | hs_ep->size_loaded, hs_ep->fifo_load, hs_ep->fifo_size); | |
486 | ||
487 | /* how much of the data has moved */ | |
488 | size_done = hs_ep->size_loaded - size_left; | |
489 | ||
490 | /* how much data is left in the fifo */ | |
491 | can_write = hs_ep->fifo_load - size_done; | |
492 | dev_dbg(hsotg->dev, "%s: => can_write1=%d\n", | |
493 | __func__, can_write); | |
494 | ||
495 | can_write = hs_ep->fifo_size - can_write; | |
496 | dev_dbg(hsotg->dev, "%s: => can_write2=%d\n", | |
497 | __func__, can_write); | |
498 | ||
499 | if (can_write <= 0) { | |
1f91b4cc | 500 | dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP); |
5b7d70c6 BD |
501 | return -ENOSPC; |
502 | } | |
10aebc77 | 503 | } else if (hsotg->dedicated_fifos && hs_ep->index != 0) { |
ad674a15 RB |
504 | can_write = dwc2_readl(hsotg->regs + |
505 | DTXFSTS(hs_ep->fifo_index)); | |
10aebc77 BD |
506 | |
507 | can_write &= 0xffff; | |
508 | can_write *= 4; | |
5b7d70c6 | 509 | } else { |
47a1685f | 510 | if (GNPTXSTS_NP_TXQ_SPC_AVAIL_GET(gnptxsts) == 0) { |
5b7d70c6 BD |
511 | dev_dbg(hsotg->dev, |
512 | "%s: no queue slots available (0x%08x)\n", | |
513 | __func__, gnptxsts); | |
514 | ||
1f91b4cc | 515 | dwc2_hsotg_en_gsint(hsotg, GINTSTS_NPTXFEMP); |
5b7d70c6 BD |
516 | return -ENOSPC; |
517 | } | |
518 | ||
47a1685f | 519 | can_write = GNPTXSTS_NP_TXF_SPC_AVAIL_GET(gnptxsts); |
679f9b7c | 520 | can_write *= 4; /* fifo size is in 32bit quantities. */ |
5b7d70c6 BD |
521 | } |
522 | ||
4fca54aa RB |
523 | max_transfer = hs_ep->ep.maxpacket * hs_ep->mc; |
524 | ||
525 | dev_dbg(hsotg->dev, "%s: GNPTXSTS=%08x, can=%d, to=%d, max_transfer %d\n", | |
9da51974 | 526 | __func__, gnptxsts, can_write, to_write, max_transfer); |
5b7d70c6 | 527 | |
8b9bc460 LM |
528 | /* |
529 | * limit to 512 bytes of data, it seems at least on the non-periodic | |
5b7d70c6 BD |
530 | * FIFO, requests of >512 cause the endpoint to get stuck with a |
531 | * fragment of the end of the transfer in it. | |
532 | */ | |
811f3303 | 533 | if (can_write > 512 && !periodic) |
5b7d70c6 BD |
534 | can_write = 512; |
535 | ||
8b9bc460 LM |
536 | /* |
537 | * limit the write to one max-packet size worth of data, but allow | |
03e10e5a | 538 | * the transfer to return that it did not run out of fifo space |
8b9bc460 LM |
539 | * doing it. |
540 | */ | |
4fca54aa RB |
541 | if (to_write > max_transfer) { |
542 | to_write = max_transfer; | |
03e10e5a | 543 | |
5cb2ff0c RB |
544 | /* it's needed only when we do not use dedicated fifos */ |
545 | if (!hsotg->dedicated_fifos) | |
1f91b4cc | 546 | dwc2_hsotg_en_gsint(hsotg, |
9da51974 | 547 | periodic ? GINTSTS_PTXFEMP : |
47a1685f | 548 | GINTSTS_NPTXFEMP); |
03e10e5a BD |
549 | } |
550 | ||
5b7d70c6 BD |
551 | /* see if we can write data */ |
552 | ||
553 | if (to_write > can_write) { | |
554 | to_write = can_write; | |
4fca54aa | 555 | pkt_round = to_write % max_transfer; |
5b7d70c6 | 556 | |
8b9bc460 LM |
557 | /* |
558 | * Round the write down to an | |
5b7d70c6 BD |
559 | * exact number of packets. |
560 | * | |
561 | * Note, we do not currently check to see if we can ever | |
562 | * write a full packet or not to the FIFO. | |
563 | */ | |
564 | ||
565 | if (pkt_round) | |
566 | to_write -= pkt_round; | |
567 | ||
8b9bc460 LM |
568 | /* |
569 | * enable correct FIFO interrupt to alert us when there | |
570 | * is more room left. | |
571 | */ | |
5b7d70c6 | 572 | |
5cb2ff0c RB |
573 | /* it's needed only when we do not use dedicated fifos */ |
574 | if (!hsotg->dedicated_fifos) | |
1f91b4cc | 575 | dwc2_hsotg_en_gsint(hsotg, |
9da51974 | 576 | periodic ? GINTSTS_PTXFEMP : |
47a1685f | 577 | GINTSTS_NPTXFEMP); |
5b7d70c6 BD |
578 | } |
579 | ||
580 | dev_dbg(hsotg->dev, "write %d/%d, can_write %d, done %d\n", | |
9da51974 | 581 | to_write, hs_req->req.length, can_write, buf_pos); |
5b7d70c6 BD |
582 | |
583 | if (to_write <= 0) | |
584 | return -ENOSPC; | |
585 | ||
586 | hs_req->req.actual = buf_pos + to_write; | |
587 | hs_ep->total_data += to_write; | |
588 | ||
589 | if (periodic) | |
590 | hs_ep->fifo_load += to_write; | |
591 | ||
592 | to_write = DIV_ROUND_UP(to_write, 4); | |
593 | data = hs_req->req.buf + buf_pos; | |
594 | ||
1a7ed5be | 595 | iowrite32_rep(hsotg->regs + EPFIFO(hs_ep->index), data, to_write); |
5b7d70c6 BD |
596 | |
597 | return (to_write >= can_write) ? -ENOSPC : 0; | |
598 | } | |
599 | ||
600 | /** | |
601 | * get_ep_limit - get the maximum data legnth for this endpoint | |
602 | * @hs_ep: The endpoint | |
603 | * | |
604 | * Return the maximum data that can be queued in one go on a given endpoint | |
605 | * so that transfers that are too long can be split. | |
606 | */ | |
9da51974 | 607 | static unsigned int get_ep_limit(struct dwc2_hsotg_ep *hs_ep) |
5b7d70c6 BD |
608 | { |
609 | int index = hs_ep->index; | |
9da51974 JY |
610 | unsigned int maxsize; |
611 | unsigned int maxpkt; | |
5b7d70c6 BD |
612 | |
613 | if (index != 0) { | |
47a1685f DN |
614 | maxsize = DXEPTSIZ_XFERSIZE_LIMIT + 1; |
615 | maxpkt = DXEPTSIZ_PKTCNT_LIMIT + 1; | |
5b7d70c6 | 616 | } else { |
9da51974 | 617 | maxsize = 64 + 64; |
66e5c643 | 618 | if (hs_ep->dir_in) |
47a1685f | 619 | maxpkt = DIEPTSIZ0_PKTCNT_LIMIT + 1; |
66e5c643 | 620 | else |
5b7d70c6 | 621 | maxpkt = 2; |
5b7d70c6 BD |
622 | } |
623 | ||
624 | /* we made the constant loading easier above by using +1 */ | |
625 | maxpkt--; | |
626 | maxsize--; | |
627 | ||
8b9bc460 LM |
628 | /* |
629 | * constrain by packet count if maxpkts*pktsize is greater | |
630 | * than the length register size. | |
631 | */ | |
5b7d70c6 BD |
632 | |
633 | if ((maxpkt * hs_ep->ep.maxpacket) < maxsize) | |
634 | maxsize = maxpkt * hs_ep->ep.maxpacket; | |
635 | ||
636 | return maxsize; | |
637 | } | |
638 | ||
381fc8f8 | 639 | /** |
38beaec6 JY |
640 | * dwc2_hsotg_read_frameno - read current frame number |
641 | * @hsotg: The device instance | |
642 | * | |
643 | * Return the current frame number | |
644 | */ | |
381fc8f8 VM |
645 | static u32 dwc2_hsotg_read_frameno(struct dwc2_hsotg *hsotg) |
646 | { | |
647 | u32 dsts; | |
648 | ||
649 | dsts = dwc2_readl(hsotg->regs + DSTS); | |
650 | dsts &= DSTS_SOFFN_MASK; | |
651 | dsts >>= DSTS_SOFFN_SHIFT; | |
652 | ||
653 | return dsts; | |
654 | } | |
655 | ||
cf77b5fb VA |
656 | /** |
657 | * dwc2_gadget_get_chain_limit - get the maximum data payload value of the | |
658 | * DMA descriptor chain prepared for specific endpoint | |
659 | * @hs_ep: The endpoint | |
660 | * | |
661 | * Return the maximum data that can be queued in one go on a given endpoint | |
662 | * depending on its descriptor chain capacity so that transfers that | |
663 | * are too long can be split. | |
664 | */ | |
665 | static unsigned int dwc2_gadget_get_chain_limit(struct dwc2_hsotg_ep *hs_ep) | |
666 | { | |
667 | int is_isoc = hs_ep->isochronous; | |
668 | unsigned int maxsize; | |
669 | ||
670 | if (is_isoc) | |
671 | maxsize = hs_ep->dir_in ? DEV_DMA_ISOC_TX_NBYTES_LIMIT : | |
672 | DEV_DMA_ISOC_RX_NBYTES_LIMIT; | |
673 | else | |
674 | maxsize = DEV_DMA_NBYTES_LIMIT; | |
675 | ||
676 | /* Above size of one descriptor was chosen, multiple it */ | |
677 | maxsize *= MAX_DMA_DESC_NUM_GENERIC; | |
678 | ||
679 | return maxsize; | |
680 | } | |
681 | ||
e02f9aa6 VA |
682 | /* |
683 | * dwc2_gadget_get_desc_params - get DMA descriptor parameters. | |
684 | * @hs_ep: The endpoint | |
685 | * @mask: RX/TX bytes mask to be defined | |
686 | * | |
687 | * Returns maximum data payload for one descriptor after analyzing endpoint | |
688 | * characteristics. | |
689 | * DMA descriptor transfer bytes limit depends on EP type: | |
690 | * Control out - MPS, | |
691 | * Isochronous - descriptor rx/tx bytes bitfield limit, | |
692 | * Control In/Bulk/Interrupt - multiple of mps. This will allow to not | |
693 | * have concatenations from various descriptors within one packet. | |
694 | * | |
695 | * Selects corresponding mask for RX/TX bytes as well. | |
696 | */ | |
697 | static u32 dwc2_gadget_get_desc_params(struct dwc2_hsotg_ep *hs_ep, u32 *mask) | |
698 | { | |
699 | u32 mps = hs_ep->ep.maxpacket; | |
700 | int dir_in = hs_ep->dir_in; | |
701 | u32 desc_size = 0; | |
702 | ||
703 | if (!hs_ep->index && !dir_in) { | |
704 | desc_size = mps; | |
705 | *mask = DEV_DMA_NBYTES_MASK; | |
706 | } else if (hs_ep->isochronous) { | |
707 | if (dir_in) { | |
708 | desc_size = DEV_DMA_ISOC_TX_NBYTES_LIMIT; | |
709 | *mask = DEV_DMA_ISOC_TX_NBYTES_MASK; | |
710 | } else { | |
711 | desc_size = DEV_DMA_ISOC_RX_NBYTES_LIMIT; | |
712 | *mask = DEV_DMA_ISOC_RX_NBYTES_MASK; | |
713 | } | |
714 | } else { | |
715 | desc_size = DEV_DMA_NBYTES_LIMIT; | |
716 | *mask = DEV_DMA_NBYTES_MASK; | |
717 | ||
718 | /* Round down desc_size to be mps multiple */ | |
719 | desc_size -= desc_size % mps; | |
720 | } | |
721 | ||
722 | return desc_size; | |
723 | } | |
724 | ||
725 | /* | |
726 | * dwc2_gadget_config_nonisoc_xfer_ddma - prepare non ISOC DMA desc chain. | |
727 | * @hs_ep: The endpoint | |
728 | * @dma_buff: DMA address to use | |
729 | * @len: Length of the transfer | |
730 | * | |
731 | * This function will iterate over descriptor chain and fill its entries | |
732 | * with corresponding information based on transfer data. | |
733 | */ | |
734 | static void dwc2_gadget_config_nonisoc_xfer_ddma(struct dwc2_hsotg_ep *hs_ep, | |
735 | dma_addr_t dma_buff, | |
736 | unsigned int len) | |
737 | { | |
738 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
739 | int dir_in = hs_ep->dir_in; | |
740 | struct dwc2_dma_desc *desc = hs_ep->desc_list; | |
741 | u32 mps = hs_ep->ep.maxpacket; | |
742 | u32 maxsize = 0; | |
743 | u32 offset = 0; | |
744 | u32 mask = 0; | |
745 | int i; | |
746 | ||
747 | maxsize = dwc2_gadget_get_desc_params(hs_ep, &mask); | |
748 | ||
749 | hs_ep->desc_count = (len / maxsize) + | |
750 | ((len % maxsize) ? 1 : 0); | |
751 | if (len == 0) | |
752 | hs_ep->desc_count = 1; | |
753 | ||
754 | for (i = 0; i < hs_ep->desc_count; ++i) { | |
755 | desc->status = 0; | |
756 | desc->status |= (DEV_DMA_BUFF_STS_HBUSY | |
757 | << DEV_DMA_BUFF_STS_SHIFT); | |
758 | ||
759 | if (len > maxsize) { | |
760 | if (!hs_ep->index && !dir_in) | |
761 | desc->status |= (DEV_DMA_L | DEV_DMA_IOC); | |
762 | ||
763 | desc->status |= (maxsize << | |
764 | DEV_DMA_NBYTES_SHIFT & mask); | |
765 | desc->buf = dma_buff + offset; | |
766 | ||
767 | len -= maxsize; | |
768 | offset += maxsize; | |
769 | } else { | |
770 | desc->status |= (DEV_DMA_L | DEV_DMA_IOC); | |
771 | ||
772 | if (dir_in) | |
773 | desc->status |= (len % mps) ? DEV_DMA_SHORT : | |
774 | ((hs_ep->send_zlp) ? DEV_DMA_SHORT : 0); | |
775 | if (len > maxsize) | |
776 | dev_err(hsotg->dev, "wrong len %d\n", len); | |
777 | ||
778 | desc->status |= | |
779 | len << DEV_DMA_NBYTES_SHIFT & mask; | |
780 | desc->buf = dma_buff + offset; | |
781 | } | |
782 | ||
783 | desc->status &= ~DEV_DMA_BUFF_STS_MASK; | |
784 | desc->status |= (DEV_DMA_BUFF_STS_HREADY | |
785 | << DEV_DMA_BUFF_STS_SHIFT); | |
786 | desc++; | |
787 | } | |
788 | } | |
789 | ||
540ccba0 VA |
790 | /* |
791 | * dwc2_gadget_fill_isoc_desc - fills next isochronous descriptor in chain. | |
792 | * @hs_ep: The isochronous endpoint. | |
793 | * @dma_buff: usb requests dma buffer. | |
794 | * @len: usb request transfer length. | |
795 | * | |
729cac69 | 796 | * Fills next free descriptor with the data of the arrived usb request, |
540ccba0 VA |
797 | * frame info, sets Last and IOC bits increments next_desc. If filled |
798 | * descriptor is not the first one, removes L bit from the previous descriptor | |
799 | * status. | |
800 | */ | |
801 | static int dwc2_gadget_fill_isoc_desc(struct dwc2_hsotg_ep *hs_ep, | |
802 | dma_addr_t dma_buff, unsigned int len) | |
803 | { | |
804 | struct dwc2_dma_desc *desc; | |
805 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
806 | u32 index; | |
807 | u32 maxsize = 0; | |
808 | u32 mask = 0; | |
809 | ||
810 | maxsize = dwc2_gadget_get_desc_params(hs_ep, &mask); | |
540ccba0 | 811 | |
729cac69 MH |
812 | index = hs_ep->next_desc; |
813 | desc = &hs_ep->desc_list[index]; | |
540ccba0 | 814 | |
729cac69 MH |
815 | /* Check if descriptor chain full */ |
816 | if ((desc->status >> DEV_DMA_BUFF_STS_SHIFT) == | |
817 | DEV_DMA_BUFF_STS_HREADY) { | |
818 | dev_dbg(hsotg->dev, "%s: desc chain full\n", __func__); | |
819 | return 1; | |
540ccba0 VA |
820 | } |
821 | ||
540ccba0 VA |
822 | /* Clear L bit of previous desc if more than one entries in the chain */ |
823 | if (hs_ep->next_desc) | |
824 | hs_ep->desc_list[index - 1].status &= ~DEV_DMA_L; | |
825 | ||
826 | dev_dbg(hsotg->dev, "%s: Filling ep %d, dir %s isoc desc # %d\n", | |
827 | __func__, hs_ep->index, hs_ep->dir_in ? "in" : "out", index); | |
828 | ||
829 | desc->status = 0; | |
830 | desc->status |= (DEV_DMA_BUFF_STS_HBUSY << DEV_DMA_BUFF_STS_SHIFT); | |
831 | ||
832 | desc->buf = dma_buff; | |
833 | desc->status |= (DEV_DMA_L | DEV_DMA_IOC | | |
834 | ((len << DEV_DMA_NBYTES_SHIFT) & mask)); | |
835 | ||
836 | if (hs_ep->dir_in) { | |
837 | desc->status |= ((hs_ep->mc << DEV_DMA_ISOC_PID_SHIFT) & | |
838 | DEV_DMA_ISOC_PID_MASK) | | |
839 | ((len % hs_ep->ep.maxpacket) ? | |
840 | DEV_DMA_SHORT : 0) | | |
841 | ((hs_ep->target_frame << | |
842 | DEV_DMA_ISOC_FRNUM_SHIFT) & | |
843 | DEV_DMA_ISOC_FRNUM_MASK); | |
844 | } | |
845 | ||
846 | desc->status &= ~DEV_DMA_BUFF_STS_MASK; | |
847 | desc->status |= (DEV_DMA_BUFF_STS_HREADY << DEV_DMA_BUFF_STS_SHIFT); | |
848 | ||
729cac69 MH |
849 | /* Increment frame number by interval for IN */ |
850 | if (hs_ep->dir_in) | |
851 | dwc2_gadget_incr_frame_num(hs_ep); | |
852 | ||
540ccba0 VA |
853 | /* Update index of last configured entry in the chain */ |
854 | hs_ep->next_desc++; | |
729cac69 MH |
855 | if (hs_ep->next_desc >= MAX_DMA_DESC_NUM_GENERIC) |
856 | hs_ep->next_desc = 0; | |
540ccba0 VA |
857 | |
858 | return 0; | |
859 | } | |
860 | ||
861 | /* | |
862 | * dwc2_gadget_start_isoc_ddma - start isochronous transfer in DDMA | |
863 | * @hs_ep: The isochronous endpoint. | |
864 | * | |
729cac69 | 865 | * Prepare descriptor chain for isochronous endpoints. Afterwards |
540ccba0 | 866 | * write DMA address to HW and enable the endpoint. |
540ccba0 VA |
867 | */ |
868 | static void dwc2_gadget_start_isoc_ddma(struct dwc2_hsotg_ep *hs_ep) | |
869 | { | |
870 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
871 | struct dwc2_hsotg_req *hs_req, *treq; | |
872 | int index = hs_ep->index; | |
873 | int ret; | |
729cac69 | 874 | int i; |
540ccba0 VA |
875 | u32 dma_reg; |
876 | u32 depctl; | |
877 | u32 ctrl; | |
729cac69 | 878 | struct dwc2_dma_desc *desc; |
540ccba0 VA |
879 | |
880 | if (list_empty(&hs_ep->queue)) { | |
881 | dev_dbg(hsotg->dev, "%s: No requests in queue\n", __func__); | |
882 | return; | |
883 | } | |
884 | ||
729cac69 MH |
885 | /* Initialize descriptor chain by Host Busy status */ |
886 | for (i = 0; i < MAX_DMA_DESC_NUM_GENERIC; i++) { | |
887 | desc = &hs_ep->desc_list[i]; | |
888 | desc->status = 0; | |
889 | desc->status |= (DEV_DMA_BUFF_STS_HBUSY | |
890 | << DEV_DMA_BUFF_STS_SHIFT); | |
891 | } | |
892 | ||
893 | hs_ep->next_desc = 0; | |
540ccba0 VA |
894 | list_for_each_entry_safe(hs_req, treq, &hs_ep->queue, queue) { |
895 | ret = dwc2_gadget_fill_isoc_desc(hs_ep, hs_req->req.dma, | |
896 | hs_req->req.length); | |
729cac69 | 897 | if (ret) |
540ccba0 | 898 | break; |
540ccba0 VA |
899 | } |
900 | ||
729cac69 | 901 | hs_ep->compl_desc = 0; |
540ccba0 VA |
902 | depctl = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index); |
903 | dma_reg = hs_ep->dir_in ? DIEPDMA(index) : DOEPDMA(index); | |
904 | ||
905 | /* write descriptor chain address to control register */ | |
906 | dwc2_writel(hs_ep->desc_list_dma, hsotg->regs + dma_reg); | |
907 | ||
908 | ctrl = dwc2_readl(hsotg->regs + depctl); | |
909 | ctrl |= DXEPCTL_EPENA | DXEPCTL_CNAK; | |
910 | dwc2_writel(ctrl, hsotg->regs + depctl); | |
540ccba0 VA |
911 | } |
912 | ||
5b7d70c6 | 913 | /** |
1f91b4cc | 914 | * dwc2_hsotg_start_req - start a USB request from an endpoint's queue |
5b7d70c6 BD |
915 | * @hsotg: The controller state. |
916 | * @hs_ep: The endpoint to process a request for | |
917 | * @hs_req: The request to start. | |
918 | * @continuing: True if we are doing more for the current request. | |
919 | * | |
920 | * Start the given request running by setting the endpoint registers | |
921 | * appropriately, and writing any data to the FIFOs. | |
922 | */ | |
1f91b4cc | 923 | static void dwc2_hsotg_start_req(struct dwc2_hsotg *hsotg, |
9da51974 | 924 | struct dwc2_hsotg_ep *hs_ep, |
1f91b4cc | 925 | struct dwc2_hsotg_req *hs_req, |
5b7d70c6 BD |
926 | bool continuing) |
927 | { | |
928 | struct usb_request *ureq = &hs_req->req; | |
929 | int index = hs_ep->index; | |
930 | int dir_in = hs_ep->dir_in; | |
931 | u32 epctrl_reg; | |
932 | u32 epsize_reg; | |
933 | u32 epsize; | |
934 | u32 ctrl; | |
9da51974 JY |
935 | unsigned int length; |
936 | unsigned int packets; | |
937 | unsigned int maxreq; | |
aa3e8bc8 | 938 | unsigned int dma_reg; |
5b7d70c6 BD |
939 | |
940 | if (index != 0) { | |
941 | if (hs_ep->req && !continuing) { | |
942 | dev_err(hsotg->dev, "%s: active request\n", __func__); | |
943 | WARN_ON(1); | |
944 | return; | |
945 | } else if (hs_ep->req != hs_req && continuing) { | |
946 | dev_err(hsotg->dev, | |
947 | "%s: continue different req\n", __func__); | |
948 | WARN_ON(1); | |
949 | return; | |
950 | } | |
951 | } | |
952 | ||
aa3e8bc8 | 953 | dma_reg = dir_in ? DIEPDMA(index) : DOEPDMA(index); |
94cb8fd6 LM |
954 | epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index); |
955 | epsize_reg = dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index); | |
5b7d70c6 BD |
956 | |
957 | dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n", | |
95c8bc36 | 958 | __func__, dwc2_readl(hsotg->regs + epctrl_reg), index, |
5b7d70c6 BD |
959 | hs_ep->dir_in ? "in" : "out"); |
960 | ||
9c39ddc6 | 961 | /* If endpoint is stalled, we will restart request later */ |
95c8bc36 | 962 | ctrl = dwc2_readl(hsotg->regs + epctrl_reg); |
9c39ddc6 | 963 | |
b2d4c54e | 964 | if (index && ctrl & DXEPCTL_STALL) { |
9c39ddc6 AT |
965 | dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index); |
966 | return; | |
967 | } | |
968 | ||
5b7d70c6 | 969 | length = ureq->length - ureq->actual; |
71225bee LM |
970 | dev_dbg(hsotg->dev, "ureq->length:%d ureq->actual:%d\n", |
971 | ureq->length, ureq->actual); | |
5b7d70c6 | 972 | |
cf77b5fb VA |
973 | if (!using_desc_dma(hsotg)) |
974 | maxreq = get_ep_limit(hs_ep); | |
975 | else | |
976 | maxreq = dwc2_gadget_get_chain_limit(hs_ep); | |
977 | ||
5b7d70c6 BD |
978 | if (length > maxreq) { |
979 | int round = maxreq % hs_ep->ep.maxpacket; | |
980 | ||
981 | dev_dbg(hsotg->dev, "%s: length %d, max-req %d, r %d\n", | |
982 | __func__, length, maxreq, round); | |
983 | ||
984 | /* round down to multiple of packets */ | |
985 | if (round) | |
986 | maxreq -= round; | |
987 | ||
988 | length = maxreq; | |
989 | } | |
990 | ||
991 | if (length) | |
992 | packets = DIV_ROUND_UP(length, hs_ep->ep.maxpacket); | |
993 | else | |
994 | packets = 1; /* send one packet if length is zero. */ | |
995 | ||
4fca54aa RB |
996 | if (hs_ep->isochronous && length > (hs_ep->mc * hs_ep->ep.maxpacket)) { |
997 | dev_err(hsotg->dev, "req length > maxpacket*mc\n"); | |
998 | return; | |
999 | } | |
1000 | ||
5b7d70c6 | 1001 | if (dir_in && index != 0) |
4fca54aa | 1002 | if (hs_ep->isochronous) |
47a1685f | 1003 | epsize = DXEPTSIZ_MC(packets); |
4fca54aa | 1004 | else |
47a1685f | 1005 | epsize = DXEPTSIZ_MC(1); |
5b7d70c6 BD |
1006 | else |
1007 | epsize = 0; | |
1008 | ||
f71b5e25 MYK |
1009 | /* |
1010 | * zero length packet should be programmed on its own and should not | |
1011 | * be counted in DIEPTSIZ.PktCnt with other packets. | |
1012 | */ | |
1013 | if (dir_in && ureq->zero && !continuing) { | |
1014 | /* Test if zlp is actually required. */ | |
1015 | if ((ureq->length >= hs_ep->ep.maxpacket) && | |
9da51974 | 1016 | !(ureq->length % hs_ep->ep.maxpacket)) |
8a20fa45 | 1017 | hs_ep->send_zlp = 1; |
5b7d70c6 BD |
1018 | } |
1019 | ||
47a1685f DN |
1020 | epsize |= DXEPTSIZ_PKTCNT(packets); |
1021 | epsize |= DXEPTSIZ_XFERSIZE(length); | |
5b7d70c6 BD |
1022 | |
1023 | dev_dbg(hsotg->dev, "%s: %d@%d/%d, 0x%08x => 0x%08x\n", | |
1024 | __func__, packets, length, ureq->length, epsize, epsize_reg); | |
1025 | ||
1026 | /* store the request as the current one we're doing */ | |
1027 | hs_ep->req = hs_req; | |
1028 | ||
aa3e8bc8 VA |
1029 | if (using_desc_dma(hsotg)) { |
1030 | u32 offset = 0; | |
1031 | u32 mps = hs_ep->ep.maxpacket; | |
1032 | ||
1033 | /* Adjust length: EP0 - MPS, other OUT EPs - multiple of MPS */ | |
1034 | if (!dir_in) { | |
1035 | if (!index) | |
1036 | length = mps; | |
1037 | else if (length % mps) | |
1038 | length += (mps - (length % mps)); | |
1039 | } | |
5b7d70c6 | 1040 | |
8b9bc460 | 1041 | /* |
aa3e8bc8 VA |
1042 | * If more data to send, adjust DMA for EP0 out data stage. |
1043 | * ureq->dma stays unchanged, hence increment it by already | |
1044 | * passed passed data count before starting new transaction. | |
8b9bc460 | 1045 | */ |
aa3e8bc8 VA |
1046 | if (!index && hsotg->ep0_state == DWC2_EP0_DATA_OUT && |
1047 | continuing) | |
1048 | offset = ureq->actual; | |
1049 | ||
1050 | /* Fill DDMA chain entries */ | |
1051 | dwc2_gadget_config_nonisoc_xfer_ddma(hs_ep, ureq->dma + offset, | |
1052 | length); | |
1053 | ||
1054 | /* write descriptor chain address to control register */ | |
1055 | dwc2_writel(hs_ep->desc_list_dma, hsotg->regs + dma_reg); | |
5b7d70c6 | 1056 | |
aa3e8bc8 VA |
1057 | dev_dbg(hsotg->dev, "%s: %08x pad => 0x%08x\n", |
1058 | __func__, (u32)hs_ep->desc_list_dma, dma_reg); | |
1059 | } else { | |
1060 | /* write size / packets */ | |
1061 | dwc2_writel(epsize, hsotg->regs + epsize_reg); | |
1062 | ||
729e6574 | 1063 | if (using_dma(hsotg) && !continuing && (length != 0)) { |
aa3e8bc8 VA |
1064 | /* |
1065 | * write DMA address to control register, buffer | |
1066 | * already synced by dwc2_hsotg_ep_queue(). | |
1067 | */ | |
5b7d70c6 | 1068 | |
aa3e8bc8 VA |
1069 | dwc2_writel(ureq->dma, hsotg->regs + dma_reg); |
1070 | ||
1071 | dev_dbg(hsotg->dev, "%s: %pad => 0x%08x\n", | |
1072 | __func__, &ureq->dma, dma_reg); | |
1073 | } | |
5b7d70c6 BD |
1074 | } |
1075 | ||
837e9f00 VM |
1076 | if (hs_ep->isochronous && hs_ep->interval == 1) { |
1077 | hs_ep->target_frame = dwc2_hsotg_read_frameno(hsotg); | |
1078 | dwc2_gadget_incr_frame_num(hs_ep); | |
1079 | ||
1080 | if (hs_ep->target_frame & 0x1) | |
1081 | ctrl |= DXEPCTL_SETODDFR; | |
1082 | else | |
1083 | ctrl |= DXEPCTL_SETEVENFR; | |
1084 | } | |
1085 | ||
47a1685f | 1086 | ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */ |
71225bee | 1087 | |
fe0b94ab | 1088 | dev_dbg(hsotg->dev, "ep0 state:%d\n", hsotg->ep0_state); |
71225bee LM |
1089 | |
1090 | /* For Setup request do not clear NAK */ | |
fe0b94ab | 1091 | if (!(index == 0 && hsotg->ep0_state == DWC2_EP0_SETUP)) |
47a1685f | 1092 | ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */ |
71225bee | 1093 | |
5b7d70c6 | 1094 | dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl); |
95c8bc36 | 1095 | dwc2_writel(ctrl, hsotg->regs + epctrl_reg); |
5b7d70c6 | 1096 | |
8b9bc460 LM |
1097 | /* |
1098 | * set these, it seems that DMA support increments past the end | |
5b7d70c6 | 1099 | * of the packet buffer so we need to calculate the length from |
8b9bc460 LM |
1100 | * this information. |
1101 | */ | |
5b7d70c6 BD |
1102 | hs_ep->size_loaded = length; |
1103 | hs_ep->last_load = ureq->actual; | |
1104 | ||
1105 | if (dir_in && !using_dma(hsotg)) { | |
1106 | /* set these anyway, we may need them for non-periodic in */ | |
1107 | hs_ep->fifo_load = 0; | |
1108 | ||
1f91b4cc | 1109 | dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req); |
5b7d70c6 BD |
1110 | } |
1111 | ||
8b9bc460 LM |
1112 | /* |
1113 | * Note, trying to clear the NAK here causes problems with transmit | |
1114 | * on the S3C6400 ending up with the TXFIFO becoming full. | |
1115 | */ | |
5b7d70c6 BD |
1116 | |
1117 | /* check ep is enabled */ | |
95c8bc36 | 1118 | if (!(dwc2_readl(hsotg->regs + epctrl_reg) & DXEPCTL_EPENA)) |
1a0ed863 | 1119 | dev_dbg(hsotg->dev, |
9da51974 | 1120 | "ep%d: failed to become enabled (DXEPCTL=0x%08x)?\n", |
95c8bc36 | 1121 | index, dwc2_readl(hsotg->regs + epctrl_reg)); |
5b7d70c6 | 1122 | |
47a1685f | 1123 | dev_dbg(hsotg->dev, "%s: DXEPCTL=0x%08x\n", |
95c8bc36 | 1124 | __func__, dwc2_readl(hsotg->regs + epctrl_reg)); |
afcf4169 RB |
1125 | |
1126 | /* enable ep interrupts */ | |
1f91b4cc | 1127 | dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 1); |
5b7d70c6 BD |
1128 | } |
1129 | ||
1130 | /** | |
1f91b4cc | 1131 | * dwc2_hsotg_map_dma - map the DMA memory being used for the request |
5b7d70c6 BD |
1132 | * @hsotg: The device state. |
1133 | * @hs_ep: The endpoint the request is on. | |
1134 | * @req: The request being processed. | |
1135 | * | |
1136 | * We've been asked to queue a request, so ensure that the memory buffer | |
1137 | * is correctly setup for DMA. If we've been passed an extant DMA address | |
1138 | * then ensure the buffer has been synced to memory. If our buffer has no | |
1139 | * DMA memory, then we map the memory and mark our request to allow us to | |
1140 | * cleanup on completion. | |
8b9bc460 | 1141 | */ |
1f91b4cc | 1142 | static int dwc2_hsotg_map_dma(struct dwc2_hsotg *hsotg, |
9da51974 | 1143 | struct dwc2_hsotg_ep *hs_ep, |
5b7d70c6 BD |
1144 | struct usb_request *req) |
1145 | { | |
e58ebcd1 | 1146 | int ret; |
5b7d70c6 | 1147 | |
e58ebcd1 FB |
1148 | ret = usb_gadget_map_request(&hsotg->gadget, req, hs_ep->dir_in); |
1149 | if (ret) | |
1150 | goto dma_error; | |
5b7d70c6 BD |
1151 | |
1152 | return 0; | |
1153 | ||
1154 | dma_error: | |
1155 | dev_err(hsotg->dev, "%s: failed to map buffer %p, %d bytes\n", | |
1156 | __func__, req->buf, req->length); | |
1157 | ||
1158 | return -EIO; | |
1159 | } | |
1160 | ||
1f91b4cc | 1161 | static int dwc2_hsotg_handle_unaligned_buf_start(struct dwc2_hsotg *hsotg, |
b98866c2 JY |
1162 | struct dwc2_hsotg_ep *hs_ep, |
1163 | struct dwc2_hsotg_req *hs_req) | |
7d24c1b5 MYK |
1164 | { |
1165 | void *req_buf = hs_req->req.buf; | |
1166 | ||
1167 | /* If dma is not being used or buffer is aligned */ | |
1168 | if (!using_dma(hsotg) || !((long)req_buf & 3)) | |
1169 | return 0; | |
1170 | ||
1171 | WARN_ON(hs_req->saved_req_buf); | |
1172 | ||
1173 | dev_dbg(hsotg->dev, "%s: %s: buf=%p length=%d\n", __func__, | |
9da51974 | 1174 | hs_ep->ep.name, req_buf, hs_req->req.length); |
7d24c1b5 MYK |
1175 | |
1176 | hs_req->req.buf = kmalloc(hs_req->req.length, GFP_ATOMIC); | |
1177 | if (!hs_req->req.buf) { | |
1178 | hs_req->req.buf = req_buf; | |
1179 | dev_err(hsotg->dev, | |
1180 | "%s: unable to allocate memory for bounce buffer\n", | |
1181 | __func__); | |
1182 | return -ENOMEM; | |
1183 | } | |
1184 | ||
1185 | /* Save actual buffer */ | |
1186 | hs_req->saved_req_buf = req_buf; | |
1187 | ||
1188 | if (hs_ep->dir_in) | |
1189 | memcpy(hs_req->req.buf, req_buf, hs_req->req.length); | |
1190 | return 0; | |
1191 | } | |
1192 | ||
b98866c2 JY |
1193 | static void |
1194 | dwc2_hsotg_handle_unaligned_buf_complete(struct dwc2_hsotg *hsotg, | |
1195 | struct dwc2_hsotg_ep *hs_ep, | |
1196 | struct dwc2_hsotg_req *hs_req) | |
7d24c1b5 MYK |
1197 | { |
1198 | /* If dma is not being used or buffer was aligned */ | |
1199 | if (!using_dma(hsotg) || !hs_req->saved_req_buf) | |
1200 | return; | |
1201 | ||
1202 | dev_dbg(hsotg->dev, "%s: %s: status=%d actual-length=%d\n", __func__, | |
1203 | hs_ep->ep.name, hs_req->req.status, hs_req->req.actual); | |
1204 | ||
1205 | /* Copy data from bounce buffer on successful out transfer */ | |
1206 | if (!hs_ep->dir_in && !hs_req->req.status) | |
1207 | memcpy(hs_req->saved_req_buf, hs_req->req.buf, | |
9da51974 | 1208 | hs_req->req.actual); |
7d24c1b5 MYK |
1209 | |
1210 | /* Free bounce buffer */ | |
1211 | kfree(hs_req->req.buf); | |
1212 | ||
1213 | hs_req->req.buf = hs_req->saved_req_buf; | |
1214 | hs_req->saved_req_buf = NULL; | |
1215 | } | |
1216 | ||
381fc8f8 VM |
1217 | /** |
1218 | * dwc2_gadget_target_frame_elapsed - Checks target frame | |
1219 | * @hs_ep: The driver endpoint to check | |
1220 | * | |
1221 | * Returns 1 if targeted frame elapsed. If returned 1 then we need to drop | |
1222 | * corresponding transfer. | |
1223 | */ | |
1224 | static bool dwc2_gadget_target_frame_elapsed(struct dwc2_hsotg_ep *hs_ep) | |
1225 | { | |
1226 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
1227 | u32 target_frame = hs_ep->target_frame; | |
1228 | u32 current_frame = dwc2_hsotg_read_frameno(hsotg); | |
1229 | bool frame_overrun = hs_ep->frame_overrun; | |
1230 | ||
1231 | if (!frame_overrun && current_frame >= target_frame) | |
1232 | return true; | |
1233 | ||
1234 | if (frame_overrun && current_frame >= target_frame && | |
1235 | ((current_frame - target_frame) < DSTS_SOFFN_LIMIT / 2)) | |
1236 | return true; | |
1237 | ||
1238 | return false; | |
1239 | } | |
1240 | ||
e02f9aa6 VA |
1241 | /* |
1242 | * dwc2_gadget_set_ep0_desc_chain - Set EP's desc chain pointers | |
1243 | * @hsotg: The driver state | |
1244 | * @hs_ep: the ep descriptor chain is for | |
1245 | * | |
1246 | * Called to update EP0 structure's pointers depend on stage of | |
1247 | * control transfer. | |
1248 | */ | |
1249 | static int dwc2_gadget_set_ep0_desc_chain(struct dwc2_hsotg *hsotg, | |
1250 | struct dwc2_hsotg_ep *hs_ep) | |
1251 | { | |
1252 | switch (hsotg->ep0_state) { | |
1253 | case DWC2_EP0_SETUP: | |
1254 | case DWC2_EP0_STATUS_OUT: | |
1255 | hs_ep->desc_list = hsotg->setup_desc[0]; | |
1256 | hs_ep->desc_list_dma = hsotg->setup_desc_dma[0]; | |
1257 | break; | |
1258 | case DWC2_EP0_DATA_IN: | |
1259 | case DWC2_EP0_STATUS_IN: | |
1260 | hs_ep->desc_list = hsotg->ctrl_in_desc; | |
1261 | hs_ep->desc_list_dma = hsotg->ctrl_in_desc_dma; | |
1262 | break; | |
1263 | case DWC2_EP0_DATA_OUT: | |
1264 | hs_ep->desc_list = hsotg->ctrl_out_desc; | |
1265 | hs_ep->desc_list_dma = hsotg->ctrl_out_desc_dma; | |
1266 | break; | |
1267 | default: | |
1268 | dev_err(hsotg->dev, "invalid EP 0 state in queue %d\n", | |
1269 | hsotg->ep0_state); | |
1270 | return -EINVAL; | |
1271 | } | |
1272 | ||
1273 | return 0; | |
1274 | } | |
1275 | ||
1f91b4cc | 1276 | static int dwc2_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req, |
9da51974 | 1277 | gfp_t gfp_flags) |
5b7d70c6 | 1278 | { |
1f91b4cc FB |
1279 | struct dwc2_hsotg_req *hs_req = our_req(req); |
1280 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); | |
941fcce4 | 1281 | struct dwc2_hsotg *hs = hs_ep->parent; |
5b7d70c6 | 1282 | bool first; |
7d24c1b5 | 1283 | int ret; |
729cac69 MH |
1284 | u32 maxsize = 0; |
1285 | u32 mask = 0; | |
1286 | ||
5b7d70c6 BD |
1287 | |
1288 | dev_dbg(hs->dev, "%s: req %p: %d@%p, noi=%d, zero=%d, snok=%d\n", | |
1289 | ep->name, req, req->length, req->buf, req->no_interrupt, | |
1290 | req->zero, req->short_not_ok); | |
1291 | ||
7ababa92 | 1292 | /* Prevent new request submission when controller is suspended */ |
88b02f2c GT |
1293 | if (hs->lx_state != DWC2_L0) { |
1294 | dev_dbg(hs->dev, "%s: submit request only in active state\n", | |
9da51974 | 1295 | __func__); |
7ababa92 GH |
1296 | return -EAGAIN; |
1297 | } | |
1298 | ||
5b7d70c6 BD |
1299 | /* initialise status of the request */ |
1300 | INIT_LIST_HEAD(&hs_req->queue); | |
1301 | req->actual = 0; | |
1302 | req->status = -EINPROGRESS; | |
1303 | ||
729cac69 MH |
1304 | /* In DDMA mode for ISOC's don't queue request if length greater |
1305 | * than descriptor limits. | |
1306 | */ | |
1307 | if (using_desc_dma(hs) && hs_ep->isochronous) { | |
1308 | maxsize = dwc2_gadget_get_desc_params(hs_ep, &mask); | |
1309 | if (hs_ep->dir_in && req->length > maxsize) { | |
1310 | dev_err(hs->dev, "wrong length %d (maxsize=%d)\n", | |
1311 | req->length, maxsize); | |
1312 | return -EINVAL; | |
1313 | } | |
1314 | ||
1315 | if (!hs_ep->dir_in && req->length > hs_ep->ep.maxpacket) { | |
1316 | dev_err(hs->dev, "ISOC OUT: wrong length %d (mps=%d)\n", | |
1317 | req->length, hs_ep->ep.maxpacket); | |
1318 | return -EINVAL; | |
1319 | } | |
1320 | } | |
1321 | ||
1f91b4cc | 1322 | ret = dwc2_hsotg_handle_unaligned_buf_start(hs, hs_ep, hs_req); |
7d24c1b5 MYK |
1323 | if (ret) |
1324 | return ret; | |
1325 | ||
5b7d70c6 BD |
1326 | /* if we're using DMA, sync the buffers as necessary */ |
1327 | if (using_dma(hs)) { | |
1f91b4cc | 1328 | ret = dwc2_hsotg_map_dma(hs, hs_ep, req); |
5b7d70c6 BD |
1329 | if (ret) |
1330 | return ret; | |
1331 | } | |
e02f9aa6 VA |
1332 | /* If using descriptor DMA configure EP0 descriptor chain pointers */ |
1333 | if (using_desc_dma(hs) && !hs_ep->index) { | |
1334 | ret = dwc2_gadget_set_ep0_desc_chain(hs, hs_ep); | |
1335 | if (ret) | |
1336 | return ret; | |
1337 | } | |
5b7d70c6 | 1338 | |
5b7d70c6 BD |
1339 | first = list_empty(&hs_ep->queue); |
1340 | list_add_tail(&hs_req->queue, &hs_ep->queue); | |
1341 | ||
540ccba0 VA |
1342 | /* |
1343 | * Handle DDMA isochronous transfers separately - just add new entry | |
729cac69 | 1344 | * to the descriptor chain. |
540ccba0 VA |
1345 | * Transfer will be started once SW gets either one of NAK or |
1346 | * OutTknEpDis interrupts. | |
1347 | */ | |
729cac69 MH |
1348 | if (using_desc_dma(hs) && hs_ep->isochronous) { |
1349 | if (hs_ep->target_frame != TARGET_FRAME_INITIAL) { | |
1350 | dwc2_gadget_fill_isoc_desc(hs_ep, hs_req->req.dma, | |
1351 | hs_req->req.length); | |
1352 | } | |
540ccba0 VA |
1353 | return 0; |
1354 | } | |
1355 | ||
837e9f00 VM |
1356 | if (first) { |
1357 | if (!hs_ep->isochronous) { | |
1358 | dwc2_hsotg_start_req(hs, hs_ep, hs_req, false); | |
1359 | return 0; | |
1360 | } | |
1361 | ||
1362 | while (dwc2_gadget_target_frame_elapsed(hs_ep)) | |
1363 | dwc2_gadget_incr_frame_num(hs_ep); | |
5b7d70c6 | 1364 | |
837e9f00 VM |
1365 | if (hs_ep->target_frame != TARGET_FRAME_INITIAL) |
1366 | dwc2_hsotg_start_req(hs, hs_ep, hs_req, false); | |
1367 | } | |
5b7d70c6 BD |
1368 | return 0; |
1369 | } | |
1370 | ||
1f91b4cc | 1371 | static int dwc2_hsotg_ep_queue_lock(struct usb_ep *ep, struct usb_request *req, |
9da51974 | 1372 | gfp_t gfp_flags) |
5ad1d316 | 1373 | { |
1f91b4cc | 1374 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 1375 | struct dwc2_hsotg *hs = hs_ep->parent; |
5ad1d316 LM |
1376 | unsigned long flags = 0; |
1377 | int ret = 0; | |
1378 | ||
1379 | spin_lock_irqsave(&hs->lock, flags); | |
1f91b4cc | 1380 | ret = dwc2_hsotg_ep_queue(ep, req, gfp_flags); |
5ad1d316 LM |
1381 | spin_unlock_irqrestore(&hs->lock, flags); |
1382 | ||
1383 | return ret; | |
1384 | } | |
1385 | ||
1f91b4cc | 1386 | static void dwc2_hsotg_ep_free_request(struct usb_ep *ep, |
9da51974 | 1387 | struct usb_request *req) |
5b7d70c6 | 1388 | { |
1f91b4cc | 1389 | struct dwc2_hsotg_req *hs_req = our_req(req); |
5b7d70c6 BD |
1390 | |
1391 | kfree(hs_req); | |
1392 | } | |
1393 | ||
1394 | /** | |
1f91b4cc | 1395 | * dwc2_hsotg_complete_oursetup - setup completion callback |
5b7d70c6 BD |
1396 | * @ep: The endpoint the request was on. |
1397 | * @req: The request completed. | |
1398 | * | |
1399 | * Called on completion of any requests the driver itself | |
1400 | * submitted that need cleaning up. | |
1401 | */ | |
1f91b4cc | 1402 | static void dwc2_hsotg_complete_oursetup(struct usb_ep *ep, |
9da51974 | 1403 | struct usb_request *req) |
5b7d70c6 | 1404 | { |
1f91b4cc | 1405 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 1406 | struct dwc2_hsotg *hsotg = hs_ep->parent; |
5b7d70c6 BD |
1407 | |
1408 | dev_dbg(hsotg->dev, "%s: ep %p, req %p\n", __func__, ep, req); | |
1409 | ||
1f91b4cc | 1410 | dwc2_hsotg_ep_free_request(ep, req); |
5b7d70c6 BD |
1411 | } |
1412 | ||
1413 | /** | |
1414 | * ep_from_windex - convert control wIndex value to endpoint | |
1415 | * @hsotg: The driver state. | |
1416 | * @windex: The control request wIndex field (in host order). | |
1417 | * | |
1418 | * Convert the given wIndex into a pointer to an driver endpoint | |
1419 | * structure, or return NULL if it is not a valid endpoint. | |
8b9bc460 | 1420 | */ |
1f91b4cc | 1421 | static struct dwc2_hsotg_ep *ep_from_windex(struct dwc2_hsotg *hsotg, |
9da51974 | 1422 | u32 windex) |
5b7d70c6 | 1423 | { |
1f91b4cc | 1424 | struct dwc2_hsotg_ep *ep; |
5b7d70c6 BD |
1425 | int dir = (windex & USB_DIR_IN) ? 1 : 0; |
1426 | int idx = windex & 0x7F; | |
1427 | ||
1428 | if (windex >= 0x100) | |
1429 | return NULL; | |
1430 | ||
b3f489b2 | 1431 | if (idx > hsotg->num_of_eps) |
5b7d70c6 BD |
1432 | return NULL; |
1433 | ||
c6f5c050 MYK |
1434 | ep = index_to_ep(hsotg, idx, dir); |
1435 | ||
5b7d70c6 BD |
1436 | if (idx && ep->dir_in != dir) |
1437 | return NULL; | |
1438 | ||
1439 | return ep; | |
1440 | } | |
1441 | ||
9e14d0a5 | 1442 | /** |
1f91b4cc | 1443 | * dwc2_hsotg_set_test_mode - Enable usb Test Modes |
9e14d0a5 GH |
1444 | * @hsotg: The driver state. |
1445 | * @testmode: requested usb test mode | |
1446 | * Enable usb Test Mode requested by the Host. | |
1447 | */ | |
1f91b4cc | 1448 | int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode) |
9e14d0a5 | 1449 | { |
95c8bc36 | 1450 | int dctl = dwc2_readl(hsotg->regs + DCTL); |
9e14d0a5 GH |
1451 | |
1452 | dctl &= ~DCTL_TSTCTL_MASK; | |
1453 | switch (testmode) { | |
1454 | case TEST_J: | |
1455 | case TEST_K: | |
1456 | case TEST_SE0_NAK: | |
1457 | case TEST_PACKET: | |
1458 | case TEST_FORCE_EN: | |
1459 | dctl |= testmode << DCTL_TSTCTL_SHIFT; | |
1460 | break; | |
1461 | default: | |
1462 | return -EINVAL; | |
1463 | } | |
95c8bc36 | 1464 | dwc2_writel(dctl, hsotg->regs + DCTL); |
9e14d0a5 GH |
1465 | return 0; |
1466 | } | |
1467 | ||
5b7d70c6 | 1468 | /** |
1f91b4cc | 1469 | * dwc2_hsotg_send_reply - send reply to control request |
5b7d70c6 BD |
1470 | * @hsotg: The device state |
1471 | * @ep: Endpoint 0 | |
1472 | * @buff: Buffer for request | |
1473 | * @length: Length of reply. | |
1474 | * | |
1475 | * Create a request and queue it on the given endpoint. This is useful as | |
1476 | * an internal method of sending replies to certain control requests, etc. | |
1477 | */ | |
1f91b4cc | 1478 | static int dwc2_hsotg_send_reply(struct dwc2_hsotg *hsotg, |
9da51974 | 1479 | struct dwc2_hsotg_ep *ep, |
5b7d70c6 BD |
1480 | void *buff, |
1481 | int length) | |
1482 | { | |
1483 | struct usb_request *req; | |
1484 | int ret; | |
1485 | ||
1486 | dev_dbg(hsotg->dev, "%s: buff %p, len %d\n", __func__, buff, length); | |
1487 | ||
1f91b4cc | 1488 | req = dwc2_hsotg_ep_alloc_request(&ep->ep, GFP_ATOMIC); |
5b7d70c6 BD |
1489 | hsotg->ep0_reply = req; |
1490 | if (!req) { | |
1491 | dev_warn(hsotg->dev, "%s: cannot alloc req\n", __func__); | |
1492 | return -ENOMEM; | |
1493 | } | |
1494 | ||
1495 | req->buf = hsotg->ep0_buff; | |
1496 | req->length = length; | |
f71b5e25 MYK |
1497 | /* |
1498 | * zero flag is for sending zlp in DATA IN stage. It has no impact on | |
1499 | * STATUS stage. | |
1500 | */ | |
1501 | req->zero = 0; | |
1f91b4cc | 1502 | req->complete = dwc2_hsotg_complete_oursetup; |
5b7d70c6 BD |
1503 | |
1504 | if (length) | |
1505 | memcpy(req->buf, buff, length); | |
5b7d70c6 | 1506 | |
1f91b4cc | 1507 | ret = dwc2_hsotg_ep_queue(&ep->ep, req, GFP_ATOMIC); |
5b7d70c6 BD |
1508 | if (ret) { |
1509 | dev_warn(hsotg->dev, "%s: cannot queue req\n", __func__); | |
1510 | return ret; | |
1511 | } | |
1512 | ||
1513 | return 0; | |
1514 | } | |
1515 | ||
1516 | /** | |
1f91b4cc | 1517 | * dwc2_hsotg_process_req_status - process request GET_STATUS |
5b7d70c6 BD |
1518 | * @hsotg: The device state |
1519 | * @ctrl: USB control request | |
1520 | */ | |
1f91b4cc | 1521 | static int dwc2_hsotg_process_req_status(struct dwc2_hsotg *hsotg, |
9da51974 | 1522 | struct usb_ctrlrequest *ctrl) |
5b7d70c6 | 1523 | { |
1f91b4cc FB |
1524 | struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0]; |
1525 | struct dwc2_hsotg_ep *ep; | |
5b7d70c6 BD |
1526 | __le16 reply; |
1527 | int ret; | |
1528 | ||
1529 | dev_dbg(hsotg->dev, "%s: USB_REQ_GET_STATUS\n", __func__); | |
1530 | ||
1531 | if (!ep0->dir_in) { | |
1532 | dev_warn(hsotg->dev, "%s: direction out?\n", __func__); | |
1533 | return -EINVAL; | |
1534 | } | |
1535 | ||
1536 | switch (ctrl->bRequestType & USB_RECIP_MASK) { | |
1537 | case USB_RECIP_DEVICE: | |
38beaec6 JY |
1538 | /* |
1539 | * bit 0 => self powered | |
1540 | * bit 1 => remote wakeup | |
1541 | */ | |
1542 | reply = cpu_to_le16(0); | |
5b7d70c6 BD |
1543 | break; |
1544 | ||
1545 | case USB_RECIP_INTERFACE: | |
1546 | /* currently, the data result should be zero */ | |
1547 | reply = cpu_to_le16(0); | |
1548 | break; | |
1549 | ||
1550 | case USB_RECIP_ENDPOINT: | |
1551 | ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex)); | |
1552 | if (!ep) | |
1553 | return -ENOENT; | |
1554 | ||
1555 | reply = cpu_to_le16(ep->halted ? 1 : 0); | |
1556 | break; | |
1557 | ||
1558 | default: | |
1559 | return 0; | |
1560 | } | |
1561 | ||
1562 | if (le16_to_cpu(ctrl->wLength) != 2) | |
1563 | return -EINVAL; | |
1564 | ||
1f91b4cc | 1565 | ret = dwc2_hsotg_send_reply(hsotg, ep0, &reply, 2); |
5b7d70c6 BD |
1566 | if (ret) { |
1567 | dev_err(hsotg->dev, "%s: failed to send reply\n", __func__); | |
1568 | return ret; | |
1569 | } | |
1570 | ||
1571 | return 1; | |
1572 | } | |
1573 | ||
51da43b5 | 1574 | static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now); |
5b7d70c6 | 1575 | |
9c39ddc6 AT |
1576 | /** |
1577 | * get_ep_head - return the first request on the endpoint | |
1578 | * @hs_ep: The controller endpoint to get | |
1579 | * | |
1580 | * Get the first request on the endpoint. | |
1581 | */ | |
1f91b4cc | 1582 | static struct dwc2_hsotg_req *get_ep_head(struct dwc2_hsotg_ep *hs_ep) |
9c39ddc6 | 1583 | { |
ffc4b406 MY |
1584 | return list_first_entry_or_null(&hs_ep->queue, struct dwc2_hsotg_req, |
1585 | queue); | |
9c39ddc6 AT |
1586 | } |
1587 | ||
41cc4cd2 VM |
1588 | /** |
1589 | * dwc2_gadget_start_next_request - Starts next request from ep queue | |
1590 | * @hs_ep: Endpoint structure | |
1591 | * | |
1592 | * If queue is empty and EP is ISOC-OUT - unmasks OUTTKNEPDIS which is masked | |
1593 | * in its handler. Hence we need to unmask it here to be able to do | |
1594 | * resynchronization. | |
1595 | */ | |
1596 | static void dwc2_gadget_start_next_request(struct dwc2_hsotg_ep *hs_ep) | |
1597 | { | |
1598 | u32 mask; | |
1599 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
1600 | int dir_in = hs_ep->dir_in; | |
1601 | struct dwc2_hsotg_req *hs_req; | |
1602 | u32 epmsk_reg = dir_in ? DIEPMSK : DOEPMSK; | |
1603 | ||
1604 | if (!list_empty(&hs_ep->queue)) { | |
1605 | hs_req = get_ep_head(hs_ep); | |
1606 | dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, false); | |
1607 | return; | |
1608 | } | |
1609 | if (!hs_ep->isochronous) | |
1610 | return; | |
1611 | ||
1612 | if (dir_in) { | |
1613 | dev_dbg(hsotg->dev, "%s: No more ISOC-IN requests\n", | |
1614 | __func__); | |
1615 | } else { | |
1616 | dev_dbg(hsotg->dev, "%s: No more ISOC-OUT requests\n", | |
1617 | __func__); | |
1618 | mask = dwc2_readl(hsotg->regs + epmsk_reg); | |
1619 | mask |= DOEPMSK_OUTTKNEPDISMSK; | |
1620 | dwc2_writel(mask, hsotg->regs + epmsk_reg); | |
1621 | } | |
1622 | } | |
1623 | ||
5b7d70c6 | 1624 | /** |
1f91b4cc | 1625 | * dwc2_hsotg_process_req_feature - process request {SET,CLEAR}_FEATURE |
5b7d70c6 BD |
1626 | * @hsotg: The device state |
1627 | * @ctrl: USB control request | |
1628 | */ | |
1f91b4cc | 1629 | static int dwc2_hsotg_process_req_feature(struct dwc2_hsotg *hsotg, |
9da51974 | 1630 | struct usb_ctrlrequest *ctrl) |
5b7d70c6 | 1631 | { |
1f91b4cc FB |
1632 | struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0]; |
1633 | struct dwc2_hsotg_req *hs_req; | |
5b7d70c6 | 1634 | bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE); |
1f91b4cc | 1635 | struct dwc2_hsotg_ep *ep; |
26ab3d0c | 1636 | int ret; |
bd9ef7bf | 1637 | bool halted; |
9e14d0a5 GH |
1638 | u32 recip; |
1639 | u32 wValue; | |
1640 | u32 wIndex; | |
5b7d70c6 BD |
1641 | |
1642 | dev_dbg(hsotg->dev, "%s: %s_FEATURE\n", | |
1643 | __func__, set ? "SET" : "CLEAR"); | |
1644 | ||
9e14d0a5 GH |
1645 | wValue = le16_to_cpu(ctrl->wValue); |
1646 | wIndex = le16_to_cpu(ctrl->wIndex); | |
1647 | recip = ctrl->bRequestType & USB_RECIP_MASK; | |
1648 | ||
1649 | switch (recip) { | |
1650 | case USB_RECIP_DEVICE: | |
1651 | switch (wValue) { | |
fa389a6d VM |
1652 | case USB_DEVICE_REMOTE_WAKEUP: |
1653 | hsotg->remote_wakeup_allowed = 1; | |
1654 | break; | |
1655 | ||
9e14d0a5 GH |
1656 | case USB_DEVICE_TEST_MODE: |
1657 | if ((wIndex & 0xff) != 0) | |
1658 | return -EINVAL; | |
1659 | if (!set) | |
1660 | return -EINVAL; | |
1661 | ||
1662 | hsotg->test_mode = wIndex >> 8; | |
1f91b4cc | 1663 | ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0); |
9e14d0a5 GH |
1664 | if (ret) { |
1665 | dev_err(hsotg->dev, | |
1666 | "%s: failed to send reply\n", __func__); | |
1667 | return ret; | |
1668 | } | |
1669 | break; | |
1670 | default: | |
1671 | return -ENOENT; | |
1672 | } | |
1673 | break; | |
1674 | ||
1675 | case USB_RECIP_ENDPOINT: | |
1676 | ep = ep_from_windex(hsotg, wIndex); | |
5b7d70c6 BD |
1677 | if (!ep) { |
1678 | dev_dbg(hsotg->dev, "%s: no endpoint for 0x%04x\n", | |
9e14d0a5 | 1679 | __func__, wIndex); |
5b7d70c6 BD |
1680 | return -ENOENT; |
1681 | } | |
1682 | ||
9e14d0a5 | 1683 | switch (wValue) { |
5b7d70c6 | 1684 | case USB_ENDPOINT_HALT: |
bd9ef7bf RB |
1685 | halted = ep->halted; |
1686 | ||
51da43b5 | 1687 | dwc2_hsotg_ep_sethalt(&ep->ep, set, true); |
26ab3d0c | 1688 | |
1f91b4cc | 1689 | ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0); |
26ab3d0c AT |
1690 | if (ret) { |
1691 | dev_err(hsotg->dev, | |
1692 | "%s: failed to send reply\n", __func__); | |
1693 | return ret; | |
1694 | } | |
9c39ddc6 | 1695 | |
bd9ef7bf RB |
1696 | /* |
1697 | * we have to complete all requests for ep if it was | |
1698 | * halted, and the halt was cleared by CLEAR_FEATURE | |
1699 | */ | |
1700 | ||
1701 | if (!set && halted) { | |
9c39ddc6 AT |
1702 | /* |
1703 | * If we have request in progress, | |
1704 | * then complete it | |
1705 | */ | |
1706 | if (ep->req) { | |
1707 | hs_req = ep->req; | |
1708 | ep->req = NULL; | |
1709 | list_del_init(&hs_req->queue); | |
c00dd4a6 GH |
1710 | if (hs_req->req.complete) { |
1711 | spin_unlock(&hsotg->lock); | |
1712 | usb_gadget_giveback_request( | |
1713 | &ep->ep, &hs_req->req); | |
1714 | spin_lock(&hsotg->lock); | |
1715 | } | |
9c39ddc6 AT |
1716 | } |
1717 | ||
1718 | /* If we have pending request, then start it */ | |
34c0887f | 1719 | if (!ep->req) |
41cc4cd2 | 1720 | dwc2_gadget_start_next_request(ep); |
9c39ddc6 AT |
1721 | } |
1722 | ||
5b7d70c6 BD |
1723 | break; |
1724 | ||
1725 | default: | |
1726 | return -ENOENT; | |
1727 | } | |
9e14d0a5 GH |
1728 | break; |
1729 | default: | |
1730 | return -ENOENT; | |
1731 | } | |
5b7d70c6 BD |
1732 | return 1; |
1733 | } | |
1734 | ||
1f91b4cc | 1735 | static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg); |
ab93e014 | 1736 | |
c9f721b2 | 1737 | /** |
1f91b4cc | 1738 | * dwc2_hsotg_stall_ep0 - stall ep0 |
c9f721b2 RB |
1739 | * @hsotg: The device state |
1740 | * | |
1741 | * Set stall for ep0 as response for setup request. | |
1742 | */ | |
1f91b4cc | 1743 | static void dwc2_hsotg_stall_ep0(struct dwc2_hsotg *hsotg) |
e9ebe7c3 | 1744 | { |
1f91b4cc | 1745 | struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0]; |
c9f721b2 RB |
1746 | u32 reg; |
1747 | u32 ctrl; | |
1748 | ||
1749 | dev_dbg(hsotg->dev, "ep0 stall (dir=%d)\n", ep0->dir_in); | |
1750 | reg = (ep0->dir_in) ? DIEPCTL0 : DOEPCTL0; | |
1751 | ||
1752 | /* | |
1753 | * DxEPCTL_Stall will be cleared by EP once it has | |
1754 | * taken effect, so no need to clear later. | |
1755 | */ | |
1756 | ||
95c8bc36 | 1757 | ctrl = dwc2_readl(hsotg->regs + reg); |
47a1685f DN |
1758 | ctrl |= DXEPCTL_STALL; |
1759 | ctrl |= DXEPCTL_CNAK; | |
95c8bc36 | 1760 | dwc2_writel(ctrl, hsotg->regs + reg); |
c9f721b2 RB |
1761 | |
1762 | dev_dbg(hsotg->dev, | |
47a1685f | 1763 | "written DXEPCTL=0x%08x to %08x (DXEPCTL=0x%08x)\n", |
95c8bc36 | 1764 | ctrl, reg, dwc2_readl(hsotg->regs + reg)); |
c9f721b2 RB |
1765 | |
1766 | /* | |
1767 | * complete won't be called, so we enqueue | |
1768 | * setup request here | |
1769 | */ | |
1f91b4cc | 1770 | dwc2_hsotg_enqueue_setup(hsotg); |
c9f721b2 RB |
1771 | } |
1772 | ||
5b7d70c6 | 1773 | /** |
1f91b4cc | 1774 | * dwc2_hsotg_process_control - process a control request |
5b7d70c6 BD |
1775 | * @hsotg: The device state |
1776 | * @ctrl: The control request received | |
1777 | * | |
1778 | * The controller has received the SETUP phase of a control request, and | |
1779 | * needs to work out what to do next (and whether to pass it on to the | |
1780 | * gadget driver). | |
1781 | */ | |
1f91b4cc | 1782 | static void dwc2_hsotg_process_control(struct dwc2_hsotg *hsotg, |
9da51974 | 1783 | struct usb_ctrlrequest *ctrl) |
5b7d70c6 | 1784 | { |
1f91b4cc | 1785 | struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0]; |
5b7d70c6 BD |
1786 | int ret = 0; |
1787 | u32 dcfg; | |
1788 | ||
e525e743 MYK |
1789 | dev_dbg(hsotg->dev, |
1790 | "ctrl Type=%02x, Req=%02x, V=%04x, I=%04x, L=%04x\n", | |
1791 | ctrl->bRequestType, ctrl->bRequest, ctrl->wValue, | |
1792 | ctrl->wIndex, ctrl->wLength); | |
5b7d70c6 | 1793 | |
fe0b94ab MYK |
1794 | if (ctrl->wLength == 0) { |
1795 | ep0->dir_in = 1; | |
1796 | hsotg->ep0_state = DWC2_EP0_STATUS_IN; | |
1797 | } else if (ctrl->bRequestType & USB_DIR_IN) { | |
5b7d70c6 | 1798 | ep0->dir_in = 1; |
fe0b94ab MYK |
1799 | hsotg->ep0_state = DWC2_EP0_DATA_IN; |
1800 | } else { | |
1801 | ep0->dir_in = 0; | |
1802 | hsotg->ep0_state = DWC2_EP0_DATA_OUT; | |
1803 | } | |
5b7d70c6 BD |
1804 | |
1805 | if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) { | |
1806 | switch (ctrl->bRequest) { | |
1807 | case USB_REQ_SET_ADDRESS: | |
6d713c15 | 1808 | hsotg->connected = 1; |
95c8bc36 | 1809 | dcfg = dwc2_readl(hsotg->regs + DCFG); |
47a1685f | 1810 | dcfg &= ~DCFG_DEVADDR_MASK; |
d5dbd3f7 PZ |
1811 | dcfg |= (le16_to_cpu(ctrl->wValue) << |
1812 | DCFG_DEVADDR_SHIFT) & DCFG_DEVADDR_MASK; | |
95c8bc36 | 1813 | dwc2_writel(dcfg, hsotg->regs + DCFG); |
5b7d70c6 BD |
1814 | |
1815 | dev_info(hsotg->dev, "new address %d\n", ctrl->wValue); | |
1816 | ||
1f91b4cc | 1817 | ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0); |
5b7d70c6 BD |
1818 | return; |
1819 | ||
1820 | case USB_REQ_GET_STATUS: | |
1f91b4cc | 1821 | ret = dwc2_hsotg_process_req_status(hsotg, ctrl); |
5b7d70c6 BD |
1822 | break; |
1823 | ||
1824 | case USB_REQ_CLEAR_FEATURE: | |
1825 | case USB_REQ_SET_FEATURE: | |
1f91b4cc | 1826 | ret = dwc2_hsotg_process_req_feature(hsotg, ctrl); |
5b7d70c6 BD |
1827 | break; |
1828 | } | |
1829 | } | |
1830 | ||
1831 | /* as a fallback, try delivering it to the driver to deal with */ | |
1832 | ||
1833 | if (ret == 0 && hsotg->driver) { | |
93f599f2 | 1834 | spin_unlock(&hsotg->lock); |
5b7d70c6 | 1835 | ret = hsotg->driver->setup(&hsotg->gadget, ctrl); |
93f599f2 | 1836 | spin_lock(&hsotg->lock); |
5b7d70c6 BD |
1837 | if (ret < 0) |
1838 | dev_dbg(hsotg->dev, "driver->setup() ret %d\n", ret); | |
1839 | } | |
1840 | ||
8b9bc460 LM |
1841 | /* |
1842 | * the request is either unhandlable, or is not formatted correctly | |
5b7d70c6 BD |
1843 | * so respond with a STALL for the status stage to indicate failure. |
1844 | */ | |
1845 | ||
c9f721b2 | 1846 | if (ret < 0) |
1f91b4cc | 1847 | dwc2_hsotg_stall_ep0(hsotg); |
5b7d70c6 BD |
1848 | } |
1849 | ||
5b7d70c6 | 1850 | /** |
1f91b4cc | 1851 | * dwc2_hsotg_complete_setup - completion of a setup transfer |
5b7d70c6 BD |
1852 | * @ep: The endpoint the request was on. |
1853 | * @req: The request completed. | |
1854 | * | |
1855 | * Called on completion of any requests the driver itself submitted for | |
1856 | * EP0 setup packets | |
1857 | */ | |
1f91b4cc | 1858 | static void dwc2_hsotg_complete_setup(struct usb_ep *ep, |
9da51974 | 1859 | struct usb_request *req) |
5b7d70c6 | 1860 | { |
1f91b4cc | 1861 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 1862 | struct dwc2_hsotg *hsotg = hs_ep->parent; |
5b7d70c6 BD |
1863 | |
1864 | if (req->status < 0) { | |
1865 | dev_dbg(hsotg->dev, "%s: failed %d\n", __func__, req->status); | |
1866 | return; | |
1867 | } | |
1868 | ||
93f599f2 | 1869 | spin_lock(&hsotg->lock); |
5b7d70c6 | 1870 | if (req->actual == 0) |
1f91b4cc | 1871 | dwc2_hsotg_enqueue_setup(hsotg); |
5b7d70c6 | 1872 | else |
1f91b4cc | 1873 | dwc2_hsotg_process_control(hsotg, req->buf); |
93f599f2 | 1874 | spin_unlock(&hsotg->lock); |
5b7d70c6 BD |
1875 | } |
1876 | ||
1877 | /** | |
1f91b4cc | 1878 | * dwc2_hsotg_enqueue_setup - start a request for EP0 packets |
5b7d70c6 BD |
1879 | * @hsotg: The device state. |
1880 | * | |
1881 | * Enqueue a request on EP0 if necessary to received any SETUP packets | |
1882 | * received from the host. | |
1883 | */ | |
1f91b4cc | 1884 | static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg) |
5b7d70c6 BD |
1885 | { |
1886 | struct usb_request *req = hsotg->ctrl_req; | |
1f91b4cc | 1887 | struct dwc2_hsotg_req *hs_req = our_req(req); |
5b7d70c6 BD |
1888 | int ret; |
1889 | ||
1890 | dev_dbg(hsotg->dev, "%s: queueing setup request\n", __func__); | |
1891 | ||
1892 | req->zero = 0; | |
1893 | req->length = 8; | |
1894 | req->buf = hsotg->ctrl_buff; | |
1f91b4cc | 1895 | req->complete = dwc2_hsotg_complete_setup; |
5b7d70c6 BD |
1896 | |
1897 | if (!list_empty(&hs_req->queue)) { | |
1898 | dev_dbg(hsotg->dev, "%s already queued???\n", __func__); | |
1899 | return; | |
1900 | } | |
1901 | ||
c6f5c050 | 1902 | hsotg->eps_out[0]->dir_in = 0; |
8a20fa45 | 1903 | hsotg->eps_out[0]->send_zlp = 0; |
fe0b94ab | 1904 | hsotg->ep0_state = DWC2_EP0_SETUP; |
5b7d70c6 | 1905 | |
1f91b4cc | 1906 | ret = dwc2_hsotg_ep_queue(&hsotg->eps_out[0]->ep, req, GFP_ATOMIC); |
5b7d70c6 BD |
1907 | if (ret < 0) { |
1908 | dev_err(hsotg->dev, "%s: failed queue (%d)\n", __func__, ret); | |
8b9bc460 LM |
1909 | /* |
1910 | * Don't think there's much we can do other than watch the | |
1911 | * driver fail. | |
1912 | */ | |
5b7d70c6 BD |
1913 | } |
1914 | } | |
1915 | ||
1f91b4cc | 1916 | static void dwc2_hsotg_program_zlp(struct dwc2_hsotg *hsotg, |
9da51974 | 1917 | struct dwc2_hsotg_ep *hs_ep) |
fe0b94ab MYK |
1918 | { |
1919 | u32 ctrl; | |
1920 | u8 index = hs_ep->index; | |
1921 | u32 epctl_reg = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index); | |
1922 | u32 epsiz_reg = hs_ep->dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index); | |
1923 | ||
ccb34a91 MYK |
1924 | if (hs_ep->dir_in) |
1925 | dev_dbg(hsotg->dev, "Sending zero-length packet on ep%d\n", | |
e02f9aa6 | 1926 | index); |
ccb34a91 MYK |
1927 | else |
1928 | dev_dbg(hsotg->dev, "Receiving zero-length packet on ep%d\n", | |
e02f9aa6 VA |
1929 | index); |
1930 | if (using_desc_dma(hsotg)) { | |
1931 | /* Not specific buffer needed for ep0 ZLP */ | |
1932 | dma_addr_t dma = hs_ep->desc_list_dma; | |
fe0b94ab | 1933 | |
201ec568 MH |
1934 | if (!index) |
1935 | dwc2_gadget_set_ep0_desc_chain(hsotg, hs_ep); | |
1936 | ||
e02f9aa6 VA |
1937 | dwc2_gadget_config_nonisoc_xfer_ddma(hs_ep, dma, 0); |
1938 | } else { | |
1939 | dwc2_writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) | | |
1940 | DXEPTSIZ_XFERSIZE(0), hsotg->regs + | |
1941 | epsiz_reg); | |
1942 | } | |
fe0b94ab | 1943 | |
95c8bc36 | 1944 | ctrl = dwc2_readl(hsotg->regs + epctl_reg); |
fe0b94ab MYK |
1945 | ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */ |
1946 | ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */ | |
1947 | ctrl |= DXEPCTL_USBACTEP; | |
95c8bc36 | 1948 | dwc2_writel(ctrl, hsotg->regs + epctl_reg); |
fe0b94ab MYK |
1949 | } |
1950 | ||
5b7d70c6 | 1951 | /** |
1f91b4cc | 1952 | * dwc2_hsotg_complete_request - complete a request given to us |
5b7d70c6 BD |
1953 | * @hsotg: The device state. |
1954 | * @hs_ep: The endpoint the request was on. | |
1955 | * @hs_req: The request to complete. | |
1956 | * @result: The result code (0 => Ok, otherwise errno) | |
1957 | * | |
1958 | * The given request has finished, so call the necessary completion | |
1959 | * if it has one and then look to see if we can start a new request | |
1960 | * on the endpoint. | |
1961 | * | |
1962 | * Note, expects the ep to already be locked as appropriate. | |
8b9bc460 | 1963 | */ |
1f91b4cc | 1964 | static void dwc2_hsotg_complete_request(struct dwc2_hsotg *hsotg, |
9da51974 | 1965 | struct dwc2_hsotg_ep *hs_ep, |
1f91b4cc | 1966 | struct dwc2_hsotg_req *hs_req, |
5b7d70c6 BD |
1967 | int result) |
1968 | { | |
5b7d70c6 BD |
1969 | if (!hs_req) { |
1970 | dev_dbg(hsotg->dev, "%s: nothing to complete?\n", __func__); | |
1971 | return; | |
1972 | } | |
1973 | ||
1974 | dev_dbg(hsotg->dev, "complete: ep %p %s, req %p, %d => %p\n", | |
1975 | hs_ep, hs_ep->ep.name, hs_req, result, hs_req->req.complete); | |
1976 | ||
8b9bc460 LM |
1977 | /* |
1978 | * only replace the status if we've not already set an error | |
1979 | * from a previous transaction | |
1980 | */ | |
5b7d70c6 BD |
1981 | |
1982 | if (hs_req->req.status == -EINPROGRESS) | |
1983 | hs_req->req.status = result; | |
1984 | ||
44583fec YL |
1985 | if (using_dma(hsotg)) |
1986 | dwc2_hsotg_unmap_dma(hsotg, hs_ep, hs_req); | |
1987 | ||
1f91b4cc | 1988 | dwc2_hsotg_handle_unaligned_buf_complete(hsotg, hs_ep, hs_req); |
7d24c1b5 | 1989 | |
5b7d70c6 BD |
1990 | hs_ep->req = NULL; |
1991 | list_del_init(&hs_req->queue); | |
1992 | ||
8b9bc460 LM |
1993 | /* |
1994 | * call the complete request with the locks off, just in case the | |
1995 | * request tries to queue more work for this endpoint. | |
1996 | */ | |
5b7d70c6 BD |
1997 | |
1998 | if (hs_req->req.complete) { | |
22258f49 | 1999 | spin_unlock(&hsotg->lock); |
304f7e5e | 2000 | usb_gadget_giveback_request(&hs_ep->ep, &hs_req->req); |
22258f49 | 2001 | spin_lock(&hsotg->lock); |
5b7d70c6 BD |
2002 | } |
2003 | ||
540ccba0 VA |
2004 | /* In DDMA don't need to proceed to starting of next ISOC request */ |
2005 | if (using_desc_dma(hsotg) && hs_ep->isochronous) | |
2006 | return; | |
2007 | ||
8b9bc460 LM |
2008 | /* |
2009 | * Look to see if there is anything else to do. Note, the completion | |
5b7d70c6 | 2010 | * of the previous request may have caused a new request to be started |
8b9bc460 LM |
2011 | * so be careful when doing this. |
2012 | */ | |
5b7d70c6 | 2013 | |
34c0887f | 2014 | if (!hs_ep->req && result >= 0) |
41cc4cd2 | 2015 | dwc2_gadget_start_next_request(hs_ep); |
5b7d70c6 BD |
2016 | } |
2017 | ||
540ccba0 VA |
2018 | /* |
2019 | * dwc2_gadget_complete_isoc_request_ddma - complete an isoc request in DDMA | |
2020 | * @hs_ep: The endpoint the request was on. | |
2021 | * | |
2022 | * Get first request from the ep queue, determine descriptor on which complete | |
729cac69 MH |
2023 | * happened. SW discovers which descriptor currently in use by HW, adjusts |
2024 | * dma_address and calculates index of completed descriptor based on the value | |
2025 | * of DEPDMA register. Update actual length of request, giveback to gadget. | |
540ccba0 VA |
2026 | */ |
2027 | static void dwc2_gadget_complete_isoc_request_ddma(struct dwc2_hsotg_ep *hs_ep) | |
2028 | { | |
2029 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
2030 | struct dwc2_hsotg_req *hs_req; | |
2031 | struct usb_request *ureq; | |
540ccba0 VA |
2032 | u32 desc_sts; |
2033 | u32 mask; | |
2034 | ||
729cac69 | 2035 | desc_sts = hs_ep->desc_list[hs_ep->compl_desc].status; |
540ccba0 | 2036 | |
729cac69 MH |
2037 | /* Process only descriptors with buffer status set to DMA done */ |
2038 | while ((desc_sts & DEV_DMA_BUFF_STS_MASK) >> | |
2039 | DEV_DMA_BUFF_STS_SHIFT == DEV_DMA_BUFF_STS_DMADONE) { | |
540ccba0 | 2040 | |
729cac69 MH |
2041 | hs_req = get_ep_head(hs_ep); |
2042 | if (!hs_req) { | |
2043 | dev_warn(hsotg->dev, "%s: ISOC EP queue empty\n", __func__); | |
2044 | return; | |
2045 | } | |
2046 | ureq = &hs_req->req; | |
2047 | ||
2048 | /* Check completion status */ | |
2049 | if ((desc_sts & DEV_DMA_STS_MASK) >> DEV_DMA_STS_SHIFT == | |
2050 | DEV_DMA_STS_SUCC) { | |
2051 | mask = hs_ep->dir_in ? DEV_DMA_ISOC_TX_NBYTES_MASK : | |
2052 | DEV_DMA_ISOC_RX_NBYTES_MASK; | |
2053 | ureq->actual = ureq->length - ((desc_sts & mask) >> | |
2054 | DEV_DMA_ISOC_NBYTES_SHIFT); | |
2055 | ||
2056 | /* Adjust actual len for ISOC Out if len is | |
2057 | * not align of 4 | |
2058 | */ | |
2059 | if (!hs_ep->dir_in && ureq->length & 0x3) | |
2060 | ureq->actual += 4 - (ureq->length & 0x3); | |
2061 | } | |
540ccba0 | 2062 | |
729cac69 | 2063 | dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0); |
95d2b037 | 2064 | |
729cac69 MH |
2065 | hs_ep->compl_desc++; |
2066 | if (hs_ep->compl_desc > (MAX_DMA_DESC_NUM_GENERIC - 1)) | |
2067 | hs_ep->compl_desc = 0; | |
2068 | desc_sts = hs_ep->desc_list[hs_ep->compl_desc].status; | |
2069 | } | |
540ccba0 VA |
2070 | } |
2071 | ||
2072 | /* | |
729cac69 MH |
2073 | * dwc2_gadget_handle_isoc_bna - handle BNA interrupt for ISOC. |
2074 | * @hs_ep: The isochronous endpoint. | |
540ccba0 | 2075 | * |
729cac69 MH |
2076 | * If EP ISOC OUT then need to flush RX FIFO to remove source of BNA |
2077 | * interrupt. Reset target frame and next_desc to allow to start | |
2078 | * ISOC's on NAK interrupt for IN direction or on OUTTKNEPDIS | |
2079 | * interrupt for OUT direction. | |
540ccba0 | 2080 | */ |
729cac69 | 2081 | static void dwc2_gadget_handle_isoc_bna(struct dwc2_hsotg_ep *hs_ep) |
540ccba0 VA |
2082 | { |
2083 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
540ccba0 | 2084 | |
729cac69 MH |
2085 | if (!hs_ep->dir_in) |
2086 | dwc2_flush_rx_fifo(hsotg); | |
2087 | dwc2_hsotg_complete_request(hsotg, hs_ep, get_ep_head(hs_ep), 0); | |
540ccba0 | 2088 | |
729cac69 MH |
2089 | hs_ep->target_frame = TARGET_FRAME_INITIAL; |
2090 | hs_ep->next_desc = 0; | |
2091 | hs_ep->compl_desc = 0; | |
540ccba0 VA |
2092 | } |
2093 | ||
5b7d70c6 | 2094 | /** |
1f91b4cc | 2095 | * dwc2_hsotg_rx_data - receive data from the FIFO for an endpoint |
5b7d70c6 BD |
2096 | * @hsotg: The device state. |
2097 | * @ep_idx: The endpoint index for the data | |
2098 | * @size: The size of data in the fifo, in bytes | |
2099 | * | |
2100 | * The FIFO status shows there is data to read from the FIFO for a given | |
2101 | * endpoint, so sort out whether we need to read the data into a request | |
2102 | * that has been made for that endpoint. | |
2103 | */ | |
1f91b4cc | 2104 | static void dwc2_hsotg_rx_data(struct dwc2_hsotg *hsotg, int ep_idx, int size) |
5b7d70c6 | 2105 | { |
1f91b4cc FB |
2106 | struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[ep_idx]; |
2107 | struct dwc2_hsotg_req *hs_req = hs_ep->req; | |
94cb8fd6 | 2108 | void __iomem *fifo = hsotg->regs + EPFIFO(ep_idx); |
5b7d70c6 BD |
2109 | int to_read; |
2110 | int max_req; | |
2111 | int read_ptr; | |
2112 | ||
2113 | if (!hs_req) { | |
95c8bc36 | 2114 | u32 epctl = dwc2_readl(hsotg->regs + DOEPCTL(ep_idx)); |
5b7d70c6 BD |
2115 | int ptr; |
2116 | ||
6b448af4 | 2117 | dev_dbg(hsotg->dev, |
9da51974 | 2118 | "%s: FIFO %d bytes on ep%d but no req (DXEPCTl=0x%08x)\n", |
5b7d70c6 BD |
2119 | __func__, size, ep_idx, epctl); |
2120 | ||
2121 | /* dump the data from the FIFO, we've nothing we can do */ | |
2122 | for (ptr = 0; ptr < size; ptr += 4) | |
95c8bc36 | 2123 | (void)dwc2_readl(fifo); |
5b7d70c6 BD |
2124 | |
2125 | return; | |
2126 | } | |
2127 | ||
5b7d70c6 BD |
2128 | to_read = size; |
2129 | read_ptr = hs_req->req.actual; | |
2130 | max_req = hs_req->req.length - read_ptr; | |
2131 | ||
a33e7136 BD |
2132 | dev_dbg(hsotg->dev, "%s: read %d/%d, done %d/%d\n", |
2133 | __func__, to_read, max_req, read_ptr, hs_req->req.length); | |
2134 | ||
5b7d70c6 | 2135 | if (to_read > max_req) { |
8b9bc460 LM |
2136 | /* |
2137 | * more data appeared than we where willing | |
5b7d70c6 BD |
2138 | * to deal with in this request. |
2139 | */ | |
2140 | ||
2141 | /* currently we don't deal this */ | |
2142 | WARN_ON_ONCE(1); | |
2143 | } | |
2144 | ||
5b7d70c6 BD |
2145 | hs_ep->total_data += to_read; |
2146 | hs_req->req.actual += to_read; | |
2147 | to_read = DIV_ROUND_UP(to_read, 4); | |
2148 | ||
8b9bc460 LM |
2149 | /* |
2150 | * note, we might over-write the buffer end by 3 bytes depending on | |
2151 | * alignment of the data. | |
2152 | */ | |
1a7ed5be | 2153 | ioread32_rep(fifo, hs_req->req.buf + read_ptr, to_read); |
5b7d70c6 BD |
2154 | } |
2155 | ||
2156 | /** | |
1f91b4cc | 2157 | * dwc2_hsotg_ep0_zlp - send/receive zero-length packet on control endpoint |
5b7d70c6 | 2158 | * @hsotg: The device instance |
fe0b94ab | 2159 | * @dir_in: If IN zlp |
5b7d70c6 BD |
2160 | * |
2161 | * Generate a zero-length IN packet request for terminating a SETUP | |
2162 | * transaction. | |
2163 | * | |
2164 | * Note, since we don't write any data to the TxFIFO, then it is | |
25985edc | 2165 | * currently believed that we do not need to wait for any space in |
5b7d70c6 BD |
2166 | * the TxFIFO. |
2167 | */ | |
1f91b4cc | 2168 | static void dwc2_hsotg_ep0_zlp(struct dwc2_hsotg *hsotg, bool dir_in) |
5b7d70c6 | 2169 | { |
c6f5c050 | 2170 | /* eps_out[0] is used in both directions */ |
fe0b94ab MYK |
2171 | hsotg->eps_out[0]->dir_in = dir_in; |
2172 | hsotg->ep0_state = dir_in ? DWC2_EP0_STATUS_IN : DWC2_EP0_STATUS_OUT; | |
5b7d70c6 | 2173 | |
1f91b4cc | 2174 | dwc2_hsotg_program_zlp(hsotg, hsotg->eps_out[0]); |
5b7d70c6 BD |
2175 | } |
2176 | ||
ec1f9d9f | 2177 | static void dwc2_hsotg_change_ep_iso_parity(struct dwc2_hsotg *hsotg, |
9da51974 | 2178 | u32 epctl_reg) |
ec1f9d9f RB |
2179 | { |
2180 | u32 ctrl; | |
2181 | ||
2182 | ctrl = dwc2_readl(hsotg->regs + epctl_reg); | |
2183 | if (ctrl & DXEPCTL_EOFRNUM) | |
2184 | ctrl |= DXEPCTL_SETEVENFR; | |
2185 | else | |
2186 | ctrl |= DXEPCTL_SETODDFR; | |
2187 | dwc2_writel(ctrl, hsotg->regs + epctl_reg); | |
2188 | } | |
2189 | ||
aa3e8bc8 VA |
2190 | /* |
2191 | * dwc2_gadget_get_xfersize_ddma - get transferred bytes amount from desc | |
2192 | * @hs_ep - The endpoint on which transfer went | |
2193 | * | |
2194 | * Iterate over endpoints descriptor chain and get info on bytes remained | |
2195 | * in DMA descriptors after transfer has completed. Used for non isoc EPs. | |
2196 | */ | |
2197 | static unsigned int dwc2_gadget_get_xfersize_ddma(struct dwc2_hsotg_ep *hs_ep) | |
2198 | { | |
2199 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
2200 | unsigned int bytes_rem = 0; | |
2201 | struct dwc2_dma_desc *desc = hs_ep->desc_list; | |
2202 | int i; | |
2203 | u32 status; | |
2204 | ||
2205 | if (!desc) | |
2206 | return -EINVAL; | |
2207 | ||
2208 | for (i = 0; i < hs_ep->desc_count; ++i) { | |
2209 | status = desc->status; | |
2210 | bytes_rem += status & DEV_DMA_NBYTES_MASK; | |
2211 | ||
2212 | if (status & DEV_DMA_STS_MASK) | |
2213 | dev_err(hsotg->dev, "descriptor %d closed with %x\n", | |
2214 | i, status & DEV_DMA_STS_MASK); | |
2215 | } | |
2216 | ||
2217 | return bytes_rem; | |
2218 | } | |
2219 | ||
5b7d70c6 | 2220 | /** |
1f91b4cc | 2221 | * dwc2_hsotg_handle_outdone - handle receiving OutDone/SetupDone from RXFIFO |
5b7d70c6 BD |
2222 | * @hsotg: The device instance |
2223 | * @epnum: The endpoint received from | |
5b7d70c6 BD |
2224 | * |
2225 | * The RXFIFO has delivered an OutDone event, which means that the data | |
2226 | * transfer for an OUT endpoint has been completed, either by a short | |
2227 | * packet or by the finish of a transfer. | |
8b9bc460 | 2228 | */ |
1f91b4cc | 2229 | static void dwc2_hsotg_handle_outdone(struct dwc2_hsotg *hsotg, int epnum) |
5b7d70c6 | 2230 | { |
95c8bc36 | 2231 | u32 epsize = dwc2_readl(hsotg->regs + DOEPTSIZ(epnum)); |
1f91b4cc FB |
2232 | struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[epnum]; |
2233 | struct dwc2_hsotg_req *hs_req = hs_ep->req; | |
5b7d70c6 | 2234 | struct usb_request *req = &hs_req->req; |
9da51974 | 2235 | unsigned int size_left = DXEPTSIZ_XFERSIZE_GET(epsize); |
5b7d70c6 BD |
2236 | int result = 0; |
2237 | ||
2238 | if (!hs_req) { | |
2239 | dev_dbg(hsotg->dev, "%s: no request active\n", __func__); | |
2240 | return; | |
2241 | } | |
2242 | ||
fe0b94ab MYK |
2243 | if (epnum == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_OUT) { |
2244 | dev_dbg(hsotg->dev, "zlp packet received\n"); | |
1f91b4cc FB |
2245 | dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0); |
2246 | dwc2_hsotg_enqueue_setup(hsotg); | |
fe0b94ab MYK |
2247 | return; |
2248 | } | |
2249 | ||
aa3e8bc8 VA |
2250 | if (using_desc_dma(hsotg)) |
2251 | size_left = dwc2_gadget_get_xfersize_ddma(hs_ep); | |
2252 | ||
5b7d70c6 | 2253 | if (using_dma(hsotg)) { |
9da51974 | 2254 | unsigned int size_done; |
5b7d70c6 | 2255 | |
8b9bc460 LM |
2256 | /* |
2257 | * Calculate the size of the transfer by checking how much | |
5b7d70c6 BD |
2258 | * is left in the endpoint size register and then working it |
2259 | * out from the amount we loaded for the transfer. | |
2260 | * | |
2261 | * We need to do this as DMA pointers are always 32bit aligned | |
2262 | * so may overshoot/undershoot the transfer. | |
2263 | */ | |
2264 | ||
5b7d70c6 BD |
2265 | size_done = hs_ep->size_loaded - size_left; |
2266 | size_done += hs_ep->last_load; | |
2267 | ||
2268 | req->actual = size_done; | |
2269 | } | |
2270 | ||
a33e7136 BD |
2271 | /* if there is more request to do, schedule new transfer */ |
2272 | if (req->actual < req->length && size_left == 0) { | |
1f91b4cc | 2273 | dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true); |
a33e7136 BD |
2274 | return; |
2275 | } | |
2276 | ||
5b7d70c6 BD |
2277 | if (req->actual < req->length && req->short_not_ok) { |
2278 | dev_dbg(hsotg->dev, "%s: got %d/%d (short not ok) => error\n", | |
2279 | __func__, req->actual, req->length); | |
2280 | ||
8b9bc460 LM |
2281 | /* |
2282 | * todo - what should we return here? there's no one else | |
2283 | * even bothering to check the status. | |
2284 | */ | |
5b7d70c6 BD |
2285 | } |
2286 | ||
ef750c71 VA |
2287 | /* DDMA IN status phase will start from StsPhseRcvd interrupt */ |
2288 | if (!using_desc_dma(hsotg) && epnum == 0 && | |
2289 | hsotg->ep0_state == DWC2_EP0_DATA_OUT) { | |
fe0b94ab | 2290 | /* Move to STATUS IN */ |
1f91b4cc | 2291 | dwc2_hsotg_ep0_zlp(hsotg, true); |
fe0b94ab | 2292 | return; |
5b7d70c6 BD |
2293 | } |
2294 | ||
ec1f9d9f RB |
2295 | /* |
2296 | * Slave mode OUT transfers do not go through XferComplete so | |
2297 | * adjust the ISOC parity here. | |
2298 | */ | |
2299 | if (!using_dma(hsotg)) { | |
ec1f9d9f RB |
2300 | if (hs_ep->isochronous && hs_ep->interval == 1) |
2301 | dwc2_hsotg_change_ep_iso_parity(hsotg, DOEPCTL(epnum)); | |
837e9f00 VM |
2302 | else if (hs_ep->isochronous && hs_ep->interval > 1) |
2303 | dwc2_gadget_incr_frame_num(hs_ep); | |
ec1f9d9f RB |
2304 | } |
2305 | ||
1f91b4cc | 2306 | dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, result); |
5b7d70c6 BD |
2307 | } |
2308 | ||
5b7d70c6 | 2309 | /** |
1f91b4cc | 2310 | * dwc2_hsotg_handle_rx - RX FIFO has data |
5b7d70c6 BD |
2311 | * @hsotg: The device instance |
2312 | * | |
2313 | * The IRQ handler has detected that the RX FIFO has some data in it | |
2314 | * that requires processing, so find out what is in there and do the | |
2315 | * appropriate read. | |
2316 | * | |
25985edc | 2317 | * The RXFIFO is a true FIFO, the packets coming out are still in packet |
5b7d70c6 BD |
2318 | * chunks, so if you have x packets received on an endpoint you'll get x |
2319 | * FIFO events delivered, each with a packet's worth of data in it. | |
2320 | * | |
2321 | * When using DMA, we should not be processing events from the RXFIFO | |
2322 | * as the actual data should be sent to the memory directly and we turn | |
2323 | * on the completion interrupts to get notifications of transfer completion. | |
2324 | */ | |
1f91b4cc | 2325 | static void dwc2_hsotg_handle_rx(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 2326 | { |
95c8bc36 | 2327 | u32 grxstsr = dwc2_readl(hsotg->regs + GRXSTSP); |
5b7d70c6 BD |
2328 | u32 epnum, status, size; |
2329 | ||
2330 | WARN_ON(using_dma(hsotg)); | |
2331 | ||
47a1685f DN |
2332 | epnum = grxstsr & GRXSTS_EPNUM_MASK; |
2333 | status = grxstsr & GRXSTS_PKTSTS_MASK; | |
5b7d70c6 | 2334 | |
47a1685f DN |
2335 | size = grxstsr & GRXSTS_BYTECNT_MASK; |
2336 | size >>= GRXSTS_BYTECNT_SHIFT; | |
5b7d70c6 | 2337 | |
d7c747c5 | 2338 | dev_dbg(hsotg->dev, "%s: GRXSTSP=0x%08x (%d@%d)\n", |
9da51974 | 2339 | __func__, grxstsr, size, epnum); |
5b7d70c6 | 2340 | |
47a1685f DN |
2341 | switch ((status & GRXSTS_PKTSTS_MASK) >> GRXSTS_PKTSTS_SHIFT) { |
2342 | case GRXSTS_PKTSTS_GLOBALOUTNAK: | |
2343 | dev_dbg(hsotg->dev, "GLOBALOUTNAK\n"); | |
5b7d70c6 BD |
2344 | break; |
2345 | ||
47a1685f | 2346 | case GRXSTS_PKTSTS_OUTDONE: |
5b7d70c6 | 2347 | dev_dbg(hsotg->dev, "OutDone (Frame=0x%08x)\n", |
1f91b4cc | 2348 | dwc2_hsotg_read_frameno(hsotg)); |
5b7d70c6 BD |
2349 | |
2350 | if (!using_dma(hsotg)) | |
1f91b4cc | 2351 | dwc2_hsotg_handle_outdone(hsotg, epnum); |
5b7d70c6 BD |
2352 | break; |
2353 | ||
47a1685f | 2354 | case GRXSTS_PKTSTS_SETUPDONE: |
5b7d70c6 BD |
2355 | dev_dbg(hsotg->dev, |
2356 | "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n", | |
1f91b4cc | 2357 | dwc2_hsotg_read_frameno(hsotg), |
95c8bc36 | 2358 | dwc2_readl(hsotg->regs + DOEPCTL(0))); |
fe0b94ab | 2359 | /* |
1f91b4cc | 2360 | * Call dwc2_hsotg_handle_outdone here if it was not called from |
fe0b94ab MYK |
2361 | * GRXSTS_PKTSTS_OUTDONE. That is, if the core didn't |
2362 | * generate GRXSTS_PKTSTS_OUTDONE for setup packet. | |
2363 | */ | |
2364 | if (hsotg->ep0_state == DWC2_EP0_SETUP) | |
1f91b4cc | 2365 | dwc2_hsotg_handle_outdone(hsotg, epnum); |
5b7d70c6 BD |
2366 | break; |
2367 | ||
47a1685f | 2368 | case GRXSTS_PKTSTS_OUTRX: |
1f91b4cc | 2369 | dwc2_hsotg_rx_data(hsotg, epnum, size); |
5b7d70c6 BD |
2370 | break; |
2371 | ||
47a1685f | 2372 | case GRXSTS_PKTSTS_SETUPRX: |
5b7d70c6 BD |
2373 | dev_dbg(hsotg->dev, |
2374 | "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n", | |
1f91b4cc | 2375 | dwc2_hsotg_read_frameno(hsotg), |
95c8bc36 | 2376 | dwc2_readl(hsotg->regs + DOEPCTL(0))); |
5b7d70c6 | 2377 | |
fe0b94ab MYK |
2378 | WARN_ON(hsotg->ep0_state != DWC2_EP0_SETUP); |
2379 | ||
1f91b4cc | 2380 | dwc2_hsotg_rx_data(hsotg, epnum, size); |
5b7d70c6 BD |
2381 | break; |
2382 | ||
2383 | default: | |
2384 | dev_warn(hsotg->dev, "%s: unknown status %08x\n", | |
2385 | __func__, grxstsr); | |
2386 | ||
1f91b4cc | 2387 | dwc2_hsotg_dump(hsotg); |
5b7d70c6 BD |
2388 | break; |
2389 | } | |
2390 | } | |
2391 | ||
2392 | /** | |
1f91b4cc | 2393 | * dwc2_hsotg_ep0_mps - turn max packet size into register setting |
5b7d70c6 | 2394 | * @mps: The maximum packet size in bytes. |
8b9bc460 | 2395 | */ |
1f91b4cc | 2396 | static u32 dwc2_hsotg_ep0_mps(unsigned int mps) |
5b7d70c6 BD |
2397 | { |
2398 | switch (mps) { | |
2399 | case 64: | |
94cb8fd6 | 2400 | return D0EPCTL_MPS_64; |
5b7d70c6 | 2401 | case 32: |
94cb8fd6 | 2402 | return D0EPCTL_MPS_32; |
5b7d70c6 | 2403 | case 16: |
94cb8fd6 | 2404 | return D0EPCTL_MPS_16; |
5b7d70c6 | 2405 | case 8: |
94cb8fd6 | 2406 | return D0EPCTL_MPS_8; |
5b7d70c6 BD |
2407 | } |
2408 | ||
2409 | /* bad max packet size, warn and return invalid result */ | |
2410 | WARN_ON(1); | |
2411 | return (u32)-1; | |
2412 | } | |
2413 | ||
2414 | /** | |
1f91b4cc | 2415 | * dwc2_hsotg_set_ep_maxpacket - set endpoint's max-packet field |
5b7d70c6 BD |
2416 | * @hsotg: The driver state. |
2417 | * @ep: The index number of the endpoint | |
2418 | * @mps: The maximum packet size in bytes | |
ee2c40de | 2419 | * @mc: The multicount value |
5b7d70c6 BD |
2420 | * |
2421 | * Configure the maximum packet size for the given endpoint, updating | |
2422 | * the hardware control registers to reflect this. | |
2423 | */ | |
1f91b4cc | 2424 | static void dwc2_hsotg_set_ep_maxpacket(struct dwc2_hsotg *hsotg, |
ee2c40de VM |
2425 | unsigned int ep, unsigned int mps, |
2426 | unsigned int mc, unsigned int dir_in) | |
5b7d70c6 | 2427 | { |
1f91b4cc | 2428 | struct dwc2_hsotg_ep *hs_ep; |
5b7d70c6 | 2429 | void __iomem *regs = hsotg->regs; |
5b7d70c6 BD |
2430 | u32 reg; |
2431 | ||
c6f5c050 MYK |
2432 | hs_ep = index_to_ep(hsotg, ep, dir_in); |
2433 | if (!hs_ep) | |
2434 | return; | |
2435 | ||
5b7d70c6 | 2436 | if (ep == 0) { |
ee2c40de VM |
2437 | u32 mps_bytes = mps; |
2438 | ||
5b7d70c6 | 2439 | /* EP0 is a special case */ |
ee2c40de VM |
2440 | mps = dwc2_hsotg_ep0_mps(mps_bytes); |
2441 | if (mps > 3) | |
5b7d70c6 | 2442 | goto bad_mps; |
ee2c40de | 2443 | hs_ep->ep.maxpacket = mps_bytes; |
4fca54aa | 2444 | hs_ep->mc = 1; |
5b7d70c6 | 2445 | } else { |
ee2c40de | 2446 | if (mps > 1024) |
5b7d70c6 | 2447 | goto bad_mps; |
ee2c40de VM |
2448 | hs_ep->mc = mc; |
2449 | if (mc > 3) | |
4fca54aa | 2450 | goto bad_mps; |
ee2c40de | 2451 | hs_ep->ep.maxpacket = mps; |
5b7d70c6 BD |
2452 | } |
2453 | ||
c6f5c050 | 2454 | if (dir_in) { |
95c8bc36 | 2455 | reg = dwc2_readl(regs + DIEPCTL(ep)); |
c6f5c050 | 2456 | reg &= ~DXEPCTL_MPS_MASK; |
ee2c40de | 2457 | reg |= mps; |
95c8bc36 | 2458 | dwc2_writel(reg, regs + DIEPCTL(ep)); |
c6f5c050 | 2459 | } else { |
95c8bc36 | 2460 | reg = dwc2_readl(regs + DOEPCTL(ep)); |
47a1685f | 2461 | reg &= ~DXEPCTL_MPS_MASK; |
ee2c40de | 2462 | reg |= mps; |
95c8bc36 | 2463 | dwc2_writel(reg, regs + DOEPCTL(ep)); |
659ad60c | 2464 | } |
5b7d70c6 BD |
2465 | |
2466 | return; | |
2467 | ||
2468 | bad_mps: | |
2469 | dev_err(hsotg->dev, "ep%d: bad mps of %d\n", ep, mps); | |
2470 | } | |
2471 | ||
9c39ddc6 | 2472 | /** |
1f91b4cc | 2473 | * dwc2_hsotg_txfifo_flush - flush Tx FIFO |
9c39ddc6 AT |
2474 | * @hsotg: The driver state |
2475 | * @idx: The index for the endpoint (0..15) | |
2476 | */ | |
1f91b4cc | 2477 | static void dwc2_hsotg_txfifo_flush(struct dwc2_hsotg *hsotg, unsigned int idx) |
9c39ddc6 | 2478 | { |
95c8bc36 AS |
2479 | dwc2_writel(GRSTCTL_TXFNUM(idx) | GRSTCTL_TXFFLSH, |
2480 | hsotg->regs + GRSTCTL); | |
9c39ddc6 AT |
2481 | |
2482 | /* wait until the fifo is flushed */ | |
79d6b8c5 SA |
2483 | if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL, GRSTCTL_TXFFLSH, 100)) |
2484 | dev_warn(hsotg->dev, "%s: timeout flushing fifo GRSTCTL_TXFFLSH\n", | |
2485 | __func__); | |
9c39ddc6 | 2486 | } |
5b7d70c6 BD |
2487 | |
2488 | /** | |
1f91b4cc | 2489 | * dwc2_hsotg_trytx - check to see if anything needs transmitting |
5b7d70c6 BD |
2490 | * @hsotg: The driver state |
2491 | * @hs_ep: The driver endpoint to check. | |
2492 | * | |
2493 | * Check to see if there is a request that has data to send, and if so | |
2494 | * make an attempt to write data into the FIFO. | |
2495 | */ | |
1f91b4cc | 2496 | static int dwc2_hsotg_trytx(struct dwc2_hsotg *hsotg, |
9da51974 | 2497 | struct dwc2_hsotg_ep *hs_ep) |
5b7d70c6 | 2498 | { |
1f91b4cc | 2499 | struct dwc2_hsotg_req *hs_req = hs_ep->req; |
5b7d70c6 | 2500 | |
afcf4169 RB |
2501 | if (!hs_ep->dir_in || !hs_req) { |
2502 | /** | |
2503 | * if request is not enqueued, we disable interrupts | |
2504 | * for endpoints, excepting ep0 | |
2505 | */ | |
2506 | if (hs_ep->index != 0) | |
1f91b4cc | 2507 | dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, |
9da51974 | 2508 | hs_ep->dir_in, 0); |
5b7d70c6 | 2509 | return 0; |
afcf4169 | 2510 | } |
5b7d70c6 BD |
2511 | |
2512 | if (hs_req->req.actual < hs_req->req.length) { | |
2513 | dev_dbg(hsotg->dev, "trying to write more for ep%d\n", | |
2514 | hs_ep->index); | |
1f91b4cc | 2515 | return dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req); |
5b7d70c6 BD |
2516 | } |
2517 | ||
2518 | return 0; | |
2519 | } | |
2520 | ||
2521 | /** | |
1f91b4cc | 2522 | * dwc2_hsotg_complete_in - complete IN transfer |
5b7d70c6 BD |
2523 | * @hsotg: The device state. |
2524 | * @hs_ep: The endpoint that has just completed. | |
2525 | * | |
2526 | * An IN transfer has been completed, update the transfer's state and then | |
2527 | * call the relevant completion routines. | |
2528 | */ | |
1f91b4cc | 2529 | static void dwc2_hsotg_complete_in(struct dwc2_hsotg *hsotg, |
9da51974 | 2530 | struct dwc2_hsotg_ep *hs_ep) |
5b7d70c6 | 2531 | { |
1f91b4cc | 2532 | struct dwc2_hsotg_req *hs_req = hs_ep->req; |
95c8bc36 | 2533 | u32 epsize = dwc2_readl(hsotg->regs + DIEPTSIZ(hs_ep->index)); |
5b7d70c6 BD |
2534 | int size_left, size_done; |
2535 | ||
2536 | if (!hs_req) { | |
2537 | dev_dbg(hsotg->dev, "XferCompl but no req\n"); | |
2538 | return; | |
2539 | } | |
2540 | ||
d3ca0259 | 2541 | /* Finish ZLP handling for IN EP0 transactions */ |
fe0b94ab MYK |
2542 | if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_IN) { |
2543 | dev_dbg(hsotg->dev, "zlp packet sent\n"); | |
c3b22fe2 RK |
2544 | |
2545 | /* | |
2546 | * While send zlp for DWC2_EP0_STATUS_IN EP direction was | |
2547 | * changed to IN. Change back to complete OUT transfer request | |
2548 | */ | |
2549 | hs_ep->dir_in = 0; | |
2550 | ||
1f91b4cc | 2551 | dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0); |
9e14d0a5 GH |
2552 | if (hsotg->test_mode) { |
2553 | int ret; | |
2554 | ||
1f91b4cc | 2555 | ret = dwc2_hsotg_set_test_mode(hsotg, hsotg->test_mode); |
9e14d0a5 GH |
2556 | if (ret < 0) { |
2557 | dev_dbg(hsotg->dev, "Invalid Test #%d\n", | |
9da51974 | 2558 | hsotg->test_mode); |
1f91b4cc | 2559 | dwc2_hsotg_stall_ep0(hsotg); |
9e14d0a5 GH |
2560 | return; |
2561 | } | |
2562 | } | |
1f91b4cc | 2563 | dwc2_hsotg_enqueue_setup(hsotg); |
d3ca0259 LM |
2564 | return; |
2565 | } | |
2566 | ||
8b9bc460 LM |
2567 | /* |
2568 | * Calculate the size of the transfer by checking how much is left | |
5b7d70c6 BD |
2569 | * in the endpoint size register and then working it out from |
2570 | * the amount we loaded for the transfer. | |
2571 | * | |
2572 | * We do this even for DMA, as the transfer may have incremented | |
2573 | * past the end of the buffer (DMA transfers are always 32bit | |
2574 | * aligned). | |
2575 | */ | |
aa3e8bc8 VA |
2576 | if (using_desc_dma(hsotg)) { |
2577 | size_left = dwc2_gadget_get_xfersize_ddma(hs_ep); | |
2578 | if (size_left < 0) | |
2579 | dev_err(hsotg->dev, "error parsing DDMA results %d\n", | |
2580 | size_left); | |
2581 | } else { | |
2582 | size_left = DXEPTSIZ_XFERSIZE_GET(epsize); | |
2583 | } | |
5b7d70c6 BD |
2584 | |
2585 | size_done = hs_ep->size_loaded - size_left; | |
2586 | size_done += hs_ep->last_load; | |
2587 | ||
2588 | if (hs_req->req.actual != size_done) | |
2589 | dev_dbg(hsotg->dev, "%s: adjusting size done %d => %d\n", | |
2590 | __func__, hs_req->req.actual, size_done); | |
2591 | ||
2592 | hs_req->req.actual = size_done; | |
d3ca0259 LM |
2593 | dev_dbg(hsotg->dev, "req->length:%d req->actual:%d req->zero:%d\n", |
2594 | hs_req->req.length, hs_req->req.actual, hs_req->req.zero); | |
2595 | ||
5b7d70c6 BD |
2596 | if (!size_left && hs_req->req.actual < hs_req->req.length) { |
2597 | dev_dbg(hsotg->dev, "%s trying more for req...\n", __func__); | |
1f91b4cc | 2598 | dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true); |
fe0b94ab MYK |
2599 | return; |
2600 | } | |
2601 | ||
f71b5e25 | 2602 | /* Zlp for all endpoints, for ep0 only in DATA IN stage */ |
8a20fa45 | 2603 | if (hs_ep->send_zlp) { |
1f91b4cc | 2604 | dwc2_hsotg_program_zlp(hsotg, hs_ep); |
8a20fa45 | 2605 | hs_ep->send_zlp = 0; |
f71b5e25 MYK |
2606 | /* transfer will be completed on next complete interrupt */ |
2607 | return; | |
2608 | } | |
2609 | ||
fe0b94ab MYK |
2610 | if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_DATA_IN) { |
2611 | /* Move to STATUS OUT */ | |
1f91b4cc | 2612 | dwc2_hsotg_ep0_zlp(hsotg, false); |
fe0b94ab MYK |
2613 | return; |
2614 | } | |
2615 | ||
1f91b4cc | 2616 | dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0); |
5b7d70c6 BD |
2617 | } |
2618 | ||
32601588 VM |
2619 | /** |
2620 | * dwc2_gadget_read_ep_interrupts - reads interrupts for given ep | |
2621 | * @hsotg: The device state. | |
2622 | * @idx: Index of ep. | |
2623 | * @dir_in: Endpoint direction 1-in 0-out. | |
2624 | * | |
2625 | * Reads for endpoint with given index and direction, by masking | |
2626 | * epint_reg with coresponding mask. | |
2627 | */ | |
2628 | static u32 dwc2_gadget_read_ep_interrupts(struct dwc2_hsotg *hsotg, | |
2629 | unsigned int idx, int dir_in) | |
2630 | { | |
2631 | u32 epmsk_reg = dir_in ? DIEPMSK : DOEPMSK; | |
2632 | u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx); | |
2633 | u32 ints; | |
2634 | u32 mask; | |
2635 | u32 diepempmsk; | |
2636 | ||
2637 | mask = dwc2_readl(hsotg->regs + epmsk_reg); | |
2638 | diepempmsk = dwc2_readl(hsotg->regs + DIEPEMPMSK); | |
2639 | mask |= ((diepempmsk >> idx) & 0x1) ? DIEPMSK_TXFIFOEMPTY : 0; | |
2640 | mask |= DXEPINT_SETUP_RCVD; | |
2641 | ||
2642 | ints = dwc2_readl(hsotg->regs + epint_reg); | |
2643 | ints &= mask; | |
2644 | return ints; | |
2645 | } | |
2646 | ||
bd9971f0 VM |
2647 | /** |
2648 | * dwc2_gadget_handle_ep_disabled - handle DXEPINT_EPDISBLD | |
2649 | * @hs_ep: The endpoint on which interrupt is asserted. | |
2650 | * | |
2651 | * This interrupt indicates that the endpoint has been disabled per the | |
2652 | * application's request. | |
2653 | * | |
2654 | * For IN endpoints flushes txfifo, in case of BULK clears DCTL_CGNPINNAK, | |
2655 | * in case of ISOC completes current request. | |
2656 | * | |
2657 | * For ISOC-OUT endpoints completes expired requests. If there is remaining | |
2658 | * request starts it. | |
2659 | */ | |
2660 | static void dwc2_gadget_handle_ep_disabled(struct dwc2_hsotg_ep *hs_ep) | |
2661 | { | |
2662 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
2663 | struct dwc2_hsotg_req *hs_req; | |
2664 | unsigned char idx = hs_ep->index; | |
2665 | int dir_in = hs_ep->dir_in; | |
2666 | u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx); | |
2667 | int dctl = dwc2_readl(hsotg->regs + DCTL); | |
2668 | ||
2669 | dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__); | |
2670 | ||
2671 | if (dir_in) { | |
2672 | int epctl = dwc2_readl(hsotg->regs + epctl_reg); | |
2673 | ||
2674 | dwc2_hsotg_txfifo_flush(hsotg, hs_ep->fifo_index); | |
2675 | ||
2676 | if (hs_ep->isochronous) { | |
2677 | dwc2_hsotg_complete_in(hsotg, hs_ep); | |
2678 | return; | |
2679 | } | |
2680 | ||
2681 | if ((epctl & DXEPCTL_STALL) && (epctl & DXEPCTL_EPTYPE_BULK)) { | |
2682 | int dctl = dwc2_readl(hsotg->regs + DCTL); | |
2683 | ||
2684 | dctl |= DCTL_CGNPINNAK; | |
2685 | dwc2_writel(dctl, hsotg->regs + DCTL); | |
2686 | } | |
2687 | return; | |
2688 | } | |
2689 | ||
2690 | if (dctl & DCTL_GOUTNAKSTS) { | |
2691 | dctl |= DCTL_CGOUTNAK; | |
2692 | dwc2_writel(dctl, hsotg->regs + DCTL); | |
2693 | } | |
2694 | ||
2695 | if (!hs_ep->isochronous) | |
2696 | return; | |
2697 | ||
2698 | if (list_empty(&hs_ep->queue)) { | |
2699 | dev_dbg(hsotg->dev, "%s: complete_ep 0x%p, ep->queue empty!\n", | |
2700 | __func__, hs_ep); | |
2701 | return; | |
2702 | } | |
2703 | ||
2704 | do { | |
2705 | hs_req = get_ep_head(hs_ep); | |
2706 | if (hs_req) | |
2707 | dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, | |
2708 | -ENODATA); | |
2709 | dwc2_gadget_incr_frame_num(hs_ep); | |
2710 | } while (dwc2_gadget_target_frame_elapsed(hs_ep)); | |
2711 | ||
2712 | dwc2_gadget_start_next_request(hs_ep); | |
2713 | } | |
2714 | ||
5321922c VM |
2715 | /** |
2716 | * dwc2_gadget_handle_out_token_ep_disabled - handle DXEPINT_OUTTKNEPDIS | |
2717 | * @hs_ep: The endpoint on which interrupt is asserted. | |
2718 | * | |
2719 | * This is starting point for ISOC-OUT transfer, synchronization done with | |
2720 | * first out token received from host while corresponding EP is disabled. | |
2721 | * | |
2722 | * Device does not know initial frame in which out token will come. For this | |
2723 | * HW generates OUTTKNEPDIS - out token is received while EP is disabled. Upon | |
2724 | * getting this interrupt SW starts calculation for next transfer frame. | |
2725 | */ | |
2726 | static void dwc2_gadget_handle_out_token_ep_disabled(struct dwc2_hsotg_ep *ep) | |
2727 | { | |
2728 | struct dwc2_hsotg *hsotg = ep->parent; | |
2729 | int dir_in = ep->dir_in; | |
2730 | u32 doepmsk; | |
540ccba0 | 2731 | u32 tmp; |
5321922c VM |
2732 | |
2733 | if (dir_in || !ep->isochronous) | |
2734 | return; | |
2735 | ||
540ccba0 VA |
2736 | /* |
2737 | * Store frame in which irq was asserted here, as | |
2738 | * it can change while completing request below. | |
2739 | */ | |
2740 | tmp = dwc2_hsotg_read_frameno(hsotg); | |
2741 | ||
729cac69 | 2742 | dwc2_hsotg_complete_request(hsotg, ep, get_ep_head(ep), 0); |
5321922c | 2743 | |
540ccba0 VA |
2744 | if (using_desc_dma(hsotg)) { |
2745 | if (ep->target_frame == TARGET_FRAME_INITIAL) { | |
2746 | /* Start first ISO Out */ | |
2747 | ep->target_frame = tmp; | |
2748 | dwc2_gadget_start_isoc_ddma(ep); | |
2749 | } | |
2750 | return; | |
2751 | } | |
2752 | ||
5321922c VM |
2753 | if (ep->interval > 1 && |
2754 | ep->target_frame == TARGET_FRAME_INITIAL) { | |
2755 | u32 dsts; | |
2756 | u32 ctrl; | |
2757 | ||
2758 | dsts = dwc2_readl(hsotg->regs + DSTS); | |
2759 | ep->target_frame = dwc2_hsotg_read_frameno(hsotg); | |
2760 | dwc2_gadget_incr_frame_num(ep); | |
2761 | ||
2762 | ctrl = dwc2_readl(hsotg->regs + DOEPCTL(ep->index)); | |
2763 | if (ep->target_frame & 0x1) | |
2764 | ctrl |= DXEPCTL_SETODDFR; | |
2765 | else | |
2766 | ctrl |= DXEPCTL_SETEVENFR; | |
2767 | ||
2768 | dwc2_writel(ctrl, hsotg->regs + DOEPCTL(ep->index)); | |
2769 | } | |
2770 | ||
2771 | dwc2_gadget_start_next_request(ep); | |
2772 | doepmsk = dwc2_readl(hsotg->regs + DOEPMSK); | |
2773 | doepmsk &= ~DOEPMSK_OUTTKNEPDISMSK; | |
2774 | dwc2_writel(doepmsk, hsotg->regs + DOEPMSK); | |
2775 | } | |
2776 | ||
2777 | /** | |
38beaec6 JY |
2778 | * dwc2_gadget_handle_nak - handle NAK interrupt |
2779 | * @hs_ep: The endpoint on which interrupt is asserted. | |
2780 | * | |
2781 | * This is starting point for ISOC-IN transfer, synchronization done with | |
2782 | * first IN token received from host while corresponding EP is disabled. | |
2783 | * | |
2784 | * Device does not know when first one token will arrive from host. On first | |
2785 | * token arrival HW generates 2 interrupts: 'in token received while FIFO empty' | |
2786 | * and 'NAK'. NAK interrupt for ISOC-IN means that token has arrived and ZLP was | |
2787 | * sent in response to that as there was no data in FIFO. SW is basing on this | |
2788 | * interrupt to obtain frame in which token has come and then based on the | |
2789 | * interval calculates next frame for transfer. | |
2790 | */ | |
5321922c VM |
2791 | static void dwc2_gadget_handle_nak(struct dwc2_hsotg_ep *hs_ep) |
2792 | { | |
2793 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
2794 | int dir_in = hs_ep->dir_in; | |
729cac69 | 2795 | u32 tmp; |
5321922c VM |
2796 | |
2797 | if (!dir_in || !hs_ep->isochronous) | |
2798 | return; | |
2799 | ||
2800 | if (hs_ep->target_frame == TARGET_FRAME_INITIAL) { | |
540ccba0 | 2801 | |
729cac69 | 2802 | tmp = dwc2_hsotg_read_frameno(hsotg); |
540ccba0 | 2803 | if (using_desc_dma(hsotg)) { |
729cac69 MH |
2804 | dwc2_hsotg_complete_request(hsotg, hs_ep, |
2805 | get_ep_head(hs_ep), 0); | |
2806 | ||
2807 | hs_ep->target_frame = tmp; | |
2808 | dwc2_gadget_incr_frame_num(hs_ep); | |
540ccba0 VA |
2809 | dwc2_gadget_start_isoc_ddma(hs_ep); |
2810 | return; | |
2811 | } | |
2812 | ||
729cac69 | 2813 | hs_ep->target_frame = tmp; |
5321922c VM |
2814 | if (hs_ep->interval > 1) { |
2815 | u32 ctrl = dwc2_readl(hsotg->regs + | |
2816 | DIEPCTL(hs_ep->index)); | |
2817 | if (hs_ep->target_frame & 0x1) | |
2818 | ctrl |= DXEPCTL_SETODDFR; | |
2819 | else | |
2820 | ctrl |= DXEPCTL_SETEVENFR; | |
2821 | ||
2822 | dwc2_writel(ctrl, hsotg->regs + DIEPCTL(hs_ep->index)); | |
2823 | } | |
2824 | ||
2825 | dwc2_hsotg_complete_request(hsotg, hs_ep, | |
2826 | get_ep_head(hs_ep), 0); | |
2827 | } | |
2828 | ||
729cac69 MH |
2829 | if (!using_desc_dma(hsotg)) |
2830 | dwc2_gadget_incr_frame_num(hs_ep); | |
5321922c VM |
2831 | } |
2832 | ||
5b7d70c6 | 2833 | /** |
1f91b4cc | 2834 | * dwc2_hsotg_epint - handle an in/out endpoint interrupt |
5b7d70c6 BD |
2835 | * @hsotg: The driver state |
2836 | * @idx: The index for the endpoint (0..15) | |
2837 | * @dir_in: Set if this is an IN endpoint | |
2838 | * | |
2839 | * Process and clear any interrupt pending for an individual endpoint | |
8b9bc460 | 2840 | */ |
1f91b4cc | 2841 | static void dwc2_hsotg_epint(struct dwc2_hsotg *hsotg, unsigned int idx, |
9da51974 | 2842 | int dir_in) |
5b7d70c6 | 2843 | { |
1f91b4cc | 2844 | struct dwc2_hsotg_ep *hs_ep = index_to_ep(hsotg, idx, dir_in); |
94cb8fd6 LM |
2845 | u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx); |
2846 | u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx); | |
2847 | u32 epsiz_reg = dir_in ? DIEPTSIZ(idx) : DOEPTSIZ(idx); | |
5b7d70c6 | 2848 | u32 ints; |
1479e841 | 2849 | u32 ctrl; |
5b7d70c6 | 2850 | |
32601588 | 2851 | ints = dwc2_gadget_read_ep_interrupts(hsotg, idx, dir_in); |
95c8bc36 | 2852 | ctrl = dwc2_readl(hsotg->regs + epctl_reg); |
5b7d70c6 | 2853 | |
a3395f0d | 2854 | /* Clear endpoint interrupts */ |
95c8bc36 | 2855 | dwc2_writel(ints, hsotg->regs + epint_reg); |
a3395f0d | 2856 | |
c6f5c050 MYK |
2857 | if (!hs_ep) { |
2858 | dev_err(hsotg->dev, "%s:Interrupt for unconfigured ep%d(%s)\n", | |
9da51974 | 2859 | __func__, idx, dir_in ? "in" : "out"); |
c6f5c050 MYK |
2860 | return; |
2861 | } | |
2862 | ||
5b7d70c6 BD |
2863 | dev_dbg(hsotg->dev, "%s: ep%d(%s) DxEPINT=0x%08x\n", |
2864 | __func__, idx, dir_in ? "in" : "out", ints); | |
2865 | ||
b787d755 MYK |
2866 | /* Don't process XferCompl interrupt if it is a setup packet */ |
2867 | if (idx == 0 && (ints & (DXEPINT_SETUP | DXEPINT_SETUP_RCVD))) | |
2868 | ints &= ~DXEPINT_XFERCOMPL; | |
2869 | ||
f0afdb42 VA |
2870 | /* |
2871 | * Don't process XferCompl interrupt in DDMA if EP0 is still in SETUP | |
2872 | * stage and xfercomplete was generated without SETUP phase done | |
2873 | * interrupt. SW should parse received setup packet only after host's | |
2874 | * exit from setup phase of control transfer. | |
2875 | */ | |
2876 | if (using_desc_dma(hsotg) && idx == 0 && !hs_ep->dir_in && | |
2877 | hsotg->ep0_state == DWC2_EP0_SETUP && !(ints & DXEPINT_SETUP)) | |
2878 | ints &= ~DXEPINT_XFERCOMPL; | |
2879 | ||
837e9f00 | 2880 | if (ints & DXEPINT_XFERCOMPL) { |
5b7d70c6 | 2881 | dev_dbg(hsotg->dev, |
47a1685f | 2882 | "%s: XferCompl: DxEPCTL=0x%08x, DXEPTSIZ=%08x\n", |
95c8bc36 AS |
2883 | __func__, dwc2_readl(hsotg->regs + epctl_reg), |
2884 | dwc2_readl(hsotg->regs + epsiz_reg)); | |
5b7d70c6 | 2885 | |
540ccba0 VA |
2886 | /* In DDMA handle isochronous requests separately */ |
2887 | if (using_desc_dma(hsotg) && hs_ep->isochronous) { | |
729cac69 MH |
2888 | /* XferCompl set along with BNA */ |
2889 | if (!(ints & DXEPINT_BNAINTR)) | |
2890 | dwc2_gadget_complete_isoc_request_ddma(hs_ep); | |
540ccba0 VA |
2891 | } else if (dir_in) { |
2892 | /* | |
2893 | * We get OutDone from the FIFO, so we only | |
2894 | * need to look at completing IN requests here | |
2895 | * if operating slave mode | |
2896 | */ | |
837e9f00 VM |
2897 | if (hs_ep->isochronous && hs_ep->interval > 1) |
2898 | dwc2_gadget_incr_frame_num(hs_ep); | |
2899 | ||
1f91b4cc | 2900 | dwc2_hsotg_complete_in(hsotg, hs_ep); |
837e9f00 VM |
2901 | if (ints & DXEPINT_NAKINTRPT) |
2902 | ints &= ~DXEPINT_NAKINTRPT; | |
5b7d70c6 | 2903 | |
c9a64ea8 | 2904 | if (idx == 0 && !hs_ep->req) |
1f91b4cc | 2905 | dwc2_hsotg_enqueue_setup(hsotg); |
5b7d70c6 | 2906 | } else if (using_dma(hsotg)) { |
8b9bc460 LM |
2907 | /* |
2908 | * We're using DMA, we need to fire an OutDone here | |
2909 | * as we ignore the RXFIFO. | |
2910 | */ | |
837e9f00 VM |
2911 | if (hs_ep->isochronous && hs_ep->interval > 1) |
2912 | dwc2_gadget_incr_frame_num(hs_ep); | |
5b7d70c6 | 2913 | |
1f91b4cc | 2914 | dwc2_hsotg_handle_outdone(hsotg, idx); |
5b7d70c6 | 2915 | } |
5b7d70c6 BD |
2916 | } |
2917 | ||
bd9971f0 VM |
2918 | if (ints & DXEPINT_EPDISBLD) |
2919 | dwc2_gadget_handle_ep_disabled(hs_ep); | |
9c39ddc6 | 2920 | |
5321922c VM |
2921 | if (ints & DXEPINT_OUTTKNEPDIS) |
2922 | dwc2_gadget_handle_out_token_ep_disabled(hs_ep); | |
2923 | ||
2924 | if (ints & DXEPINT_NAKINTRPT) | |
2925 | dwc2_gadget_handle_nak(hs_ep); | |
2926 | ||
47a1685f | 2927 | if (ints & DXEPINT_AHBERR) |
5b7d70c6 | 2928 | dev_dbg(hsotg->dev, "%s: AHBErr\n", __func__); |
5b7d70c6 | 2929 | |
47a1685f | 2930 | if (ints & DXEPINT_SETUP) { /* Setup or Timeout */ |
5b7d70c6 BD |
2931 | dev_dbg(hsotg->dev, "%s: Setup/Timeout\n", __func__); |
2932 | ||
2933 | if (using_dma(hsotg) && idx == 0) { | |
8b9bc460 LM |
2934 | /* |
2935 | * this is the notification we've received a | |
5b7d70c6 BD |
2936 | * setup packet. In non-DMA mode we'd get this |
2937 | * from the RXFIFO, instead we need to process | |
8b9bc460 LM |
2938 | * the setup here. |
2939 | */ | |
5b7d70c6 BD |
2940 | |
2941 | if (dir_in) | |
2942 | WARN_ON_ONCE(1); | |
2943 | else | |
1f91b4cc | 2944 | dwc2_hsotg_handle_outdone(hsotg, 0); |
5b7d70c6 | 2945 | } |
5b7d70c6 BD |
2946 | } |
2947 | ||
ef750c71 | 2948 | if (ints & DXEPINT_STSPHSERCVD) { |
9d9a6b07 VA |
2949 | dev_dbg(hsotg->dev, "%s: StsPhseRcvd\n", __func__); |
2950 | ||
9e95a66c MH |
2951 | /* Safety check EP0 state when STSPHSERCVD asserted */ |
2952 | if (hsotg->ep0_state == DWC2_EP0_DATA_OUT) { | |
2953 | /* Move to STATUS IN for DDMA */ | |
2954 | if (using_desc_dma(hsotg)) | |
2955 | dwc2_hsotg_ep0_zlp(hsotg, true); | |
2956 | } | |
2957 | ||
ef750c71 VA |
2958 | } |
2959 | ||
47a1685f | 2960 | if (ints & DXEPINT_BACK2BACKSETUP) |
5b7d70c6 | 2961 | dev_dbg(hsotg->dev, "%s: B2BSetup/INEPNakEff\n", __func__); |
5b7d70c6 | 2962 | |
540ccba0 VA |
2963 | if (ints & DXEPINT_BNAINTR) { |
2964 | dev_dbg(hsotg->dev, "%s: BNA interrupt\n", __func__); | |
540ccba0 | 2965 | if (hs_ep->isochronous) |
729cac69 | 2966 | dwc2_gadget_handle_isoc_bna(hs_ep); |
540ccba0 VA |
2967 | } |
2968 | ||
1479e841 | 2969 | if (dir_in && !hs_ep->isochronous) { |
8b9bc460 | 2970 | /* not sure if this is important, but we'll clear it anyway */ |
26ddef5d | 2971 | if (ints & DXEPINT_INTKNTXFEMP) { |
5b7d70c6 BD |
2972 | dev_dbg(hsotg->dev, "%s: ep%d: INTknTXFEmpMsk\n", |
2973 | __func__, idx); | |
5b7d70c6 BD |
2974 | } |
2975 | ||
2976 | /* this probably means something bad is happening */ | |
26ddef5d | 2977 | if (ints & DXEPINT_INTKNEPMIS) { |
5b7d70c6 BD |
2978 | dev_warn(hsotg->dev, "%s: ep%d: INTknEP\n", |
2979 | __func__, idx); | |
5b7d70c6 | 2980 | } |
10aebc77 BD |
2981 | |
2982 | /* FIFO has space or is empty (see GAHBCFG) */ | |
2983 | if (hsotg->dedicated_fifos && | |
26ddef5d | 2984 | ints & DXEPINT_TXFEMP) { |
10aebc77 BD |
2985 | dev_dbg(hsotg->dev, "%s: ep%d: TxFIFOEmpty\n", |
2986 | __func__, idx); | |
70fa030f | 2987 | if (!using_dma(hsotg)) |
1f91b4cc | 2988 | dwc2_hsotg_trytx(hsotg, hs_ep); |
10aebc77 | 2989 | } |
5b7d70c6 | 2990 | } |
5b7d70c6 BD |
2991 | } |
2992 | ||
2993 | /** | |
1f91b4cc | 2994 | * dwc2_hsotg_irq_enumdone - Handle EnumDone interrupt (enumeration done) |
5b7d70c6 BD |
2995 | * @hsotg: The device state. |
2996 | * | |
2997 | * Handle updating the device settings after the enumeration phase has | |
2998 | * been completed. | |
8b9bc460 | 2999 | */ |
1f91b4cc | 3000 | static void dwc2_hsotg_irq_enumdone(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 3001 | { |
95c8bc36 | 3002 | u32 dsts = dwc2_readl(hsotg->regs + DSTS); |
9b2667f1 | 3003 | int ep0_mps = 0, ep_mps = 8; |
5b7d70c6 | 3004 | |
8b9bc460 LM |
3005 | /* |
3006 | * This should signal the finish of the enumeration phase | |
5b7d70c6 | 3007 | * of the USB handshaking, so we should now know what rate |
8b9bc460 LM |
3008 | * we connected at. |
3009 | */ | |
5b7d70c6 BD |
3010 | |
3011 | dev_dbg(hsotg->dev, "EnumDone (DSTS=0x%08x)\n", dsts); | |
3012 | ||
8b9bc460 LM |
3013 | /* |
3014 | * note, since we're limited by the size of transfer on EP0, and | |
5b7d70c6 | 3015 | * it seems IN transfers must be a even number of packets we do |
8b9bc460 LM |
3016 | * not advertise a 64byte MPS on EP0. |
3017 | */ | |
5b7d70c6 BD |
3018 | |
3019 | /* catch both EnumSpd_FS and EnumSpd_FS48 */ | |
6d76c92c | 3020 | switch ((dsts & DSTS_ENUMSPD_MASK) >> DSTS_ENUMSPD_SHIFT) { |
47a1685f DN |
3021 | case DSTS_ENUMSPD_FS: |
3022 | case DSTS_ENUMSPD_FS48: | |
5b7d70c6 | 3023 | hsotg->gadget.speed = USB_SPEED_FULL; |
5b7d70c6 | 3024 | ep0_mps = EP0_MPS_LIMIT; |
295538ff | 3025 | ep_mps = 1023; |
5b7d70c6 BD |
3026 | break; |
3027 | ||
47a1685f | 3028 | case DSTS_ENUMSPD_HS: |
5b7d70c6 | 3029 | hsotg->gadget.speed = USB_SPEED_HIGH; |
5b7d70c6 | 3030 | ep0_mps = EP0_MPS_LIMIT; |
295538ff | 3031 | ep_mps = 1024; |
5b7d70c6 BD |
3032 | break; |
3033 | ||
47a1685f | 3034 | case DSTS_ENUMSPD_LS: |
5b7d70c6 | 3035 | hsotg->gadget.speed = USB_SPEED_LOW; |
552d940f VM |
3036 | ep0_mps = 8; |
3037 | ep_mps = 8; | |
8b9bc460 LM |
3038 | /* |
3039 | * note, we don't actually support LS in this driver at the | |
5b7d70c6 BD |
3040 | * moment, and the documentation seems to imply that it isn't |
3041 | * supported by the PHYs on some of the devices. | |
3042 | */ | |
3043 | break; | |
3044 | } | |
e538dfda MN |
3045 | dev_info(hsotg->dev, "new device is %s\n", |
3046 | usb_speed_string(hsotg->gadget.speed)); | |
5b7d70c6 | 3047 | |
8b9bc460 LM |
3048 | /* |
3049 | * we should now know the maximum packet size for an | |
3050 | * endpoint, so set the endpoints to a default value. | |
3051 | */ | |
5b7d70c6 BD |
3052 | |
3053 | if (ep0_mps) { | |
3054 | int i; | |
c6f5c050 | 3055 | /* Initialize ep0 for both in and out directions */ |
ee2c40de VM |
3056 | dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 0, 1); |
3057 | dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 0, 0); | |
c6f5c050 MYK |
3058 | for (i = 1; i < hsotg->num_of_eps; i++) { |
3059 | if (hsotg->eps_in[i]) | |
ee2c40de VM |
3060 | dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps, |
3061 | 0, 1); | |
c6f5c050 | 3062 | if (hsotg->eps_out[i]) |
ee2c40de VM |
3063 | dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps, |
3064 | 0, 0); | |
c6f5c050 | 3065 | } |
5b7d70c6 BD |
3066 | } |
3067 | ||
3068 | /* ensure after enumeration our EP0 is active */ | |
3069 | ||
1f91b4cc | 3070 | dwc2_hsotg_enqueue_setup(hsotg); |
5b7d70c6 BD |
3071 | |
3072 | dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n", | |
95c8bc36 AS |
3073 | dwc2_readl(hsotg->regs + DIEPCTL0), |
3074 | dwc2_readl(hsotg->regs + DOEPCTL0)); | |
5b7d70c6 BD |
3075 | } |
3076 | ||
3077 | /** | |
3078 | * kill_all_requests - remove all requests from the endpoint's queue | |
3079 | * @hsotg: The device state. | |
3080 | * @ep: The endpoint the requests may be on. | |
3081 | * @result: The result code to use. | |
5b7d70c6 BD |
3082 | * |
3083 | * Go through the requests on the given endpoint and mark them | |
3084 | * completed with the given result code. | |
3085 | */ | |
941fcce4 | 3086 | static void kill_all_requests(struct dwc2_hsotg *hsotg, |
1f91b4cc | 3087 | struct dwc2_hsotg_ep *ep, |
6b448af4 | 3088 | int result) |
5b7d70c6 | 3089 | { |
1f91b4cc | 3090 | struct dwc2_hsotg_req *req, *treq; |
9da51974 | 3091 | unsigned int size; |
5b7d70c6 | 3092 | |
6b448af4 | 3093 | ep->req = NULL; |
5b7d70c6 | 3094 | |
6b448af4 | 3095 | list_for_each_entry_safe(req, treq, &ep->queue, queue) |
1f91b4cc | 3096 | dwc2_hsotg_complete_request(hsotg, ep, req, |
9da51974 | 3097 | result); |
6b448af4 | 3098 | |
b203d0a2 RB |
3099 | if (!hsotg->dedicated_fifos) |
3100 | return; | |
ad674a15 | 3101 | size = (dwc2_readl(hsotg->regs + DTXFSTS(ep->fifo_index)) & 0xffff) * 4; |
b203d0a2 | 3102 | if (size < ep->fifo_size) |
1f91b4cc | 3103 | dwc2_hsotg_txfifo_flush(hsotg, ep->fifo_index); |
5b7d70c6 BD |
3104 | } |
3105 | ||
5b7d70c6 | 3106 | /** |
1f91b4cc | 3107 | * dwc2_hsotg_disconnect - disconnect service |
5b7d70c6 BD |
3108 | * @hsotg: The device state. |
3109 | * | |
5e891342 LM |
3110 | * The device has been disconnected. Remove all current |
3111 | * transactions and signal the gadget driver that this | |
3112 | * has happened. | |
8b9bc460 | 3113 | */ |
1f91b4cc | 3114 | void dwc2_hsotg_disconnect(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 3115 | { |
9da51974 | 3116 | unsigned int ep; |
5b7d70c6 | 3117 | |
4ace06e8 MS |
3118 | if (!hsotg->connected) |
3119 | return; | |
3120 | ||
3121 | hsotg->connected = 0; | |
9e14d0a5 | 3122 | hsotg->test_mode = 0; |
c6f5c050 MYK |
3123 | |
3124 | for (ep = 0; ep < hsotg->num_of_eps; ep++) { | |
3125 | if (hsotg->eps_in[ep]) | |
3126 | kill_all_requests(hsotg, hsotg->eps_in[ep], | |
9da51974 | 3127 | -ESHUTDOWN); |
c6f5c050 MYK |
3128 | if (hsotg->eps_out[ep]) |
3129 | kill_all_requests(hsotg, hsotg->eps_out[ep], | |
9da51974 | 3130 | -ESHUTDOWN); |
c6f5c050 | 3131 | } |
5b7d70c6 BD |
3132 | |
3133 | call_gadget(hsotg, disconnect); | |
065d3931 | 3134 | hsotg->lx_state = DWC2_L3; |
ce2b21a4 JS |
3135 | |
3136 | usb_gadget_set_state(&hsotg->gadget, USB_STATE_NOTATTACHED); | |
5b7d70c6 BD |
3137 | } |
3138 | ||
3139 | /** | |
1f91b4cc | 3140 | * dwc2_hsotg_irq_fifoempty - TX FIFO empty interrupt handler |
5b7d70c6 BD |
3141 | * @hsotg: The device state: |
3142 | * @periodic: True if this is a periodic FIFO interrupt | |
3143 | */ | |
1f91b4cc | 3144 | static void dwc2_hsotg_irq_fifoempty(struct dwc2_hsotg *hsotg, bool periodic) |
5b7d70c6 | 3145 | { |
1f91b4cc | 3146 | struct dwc2_hsotg_ep *ep; |
5b7d70c6 BD |
3147 | int epno, ret; |
3148 | ||
3149 | /* look through for any more data to transmit */ | |
b3f489b2 | 3150 | for (epno = 0; epno < hsotg->num_of_eps; epno++) { |
c6f5c050 MYK |
3151 | ep = index_to_ep(hsotg, epno, 1); |
3152 | ||
3153 | if (!ep) | |
3154 | continue; | |
5b7d70c6 BD |
3155 | |
3156 | if (!ep->dir_in) | |
3157 | continue; | |
3158 | ||
3159 | if ((periodic && !ep->periodic) || | |
3160 | (!periodic && ep->periodic)) | |
3161 | continue; | |
3162 | ||
1f91b4cc | 3163 | ret = dwc2_hsotg_trytx(hsotg, ep); |
5b7d70c6 BD |
3164 | if (ret < 0) |
3165 | break; | |
3166 | } | |
3167 | } | |
3168 | ||
5b7d70c6 | 3169 | /* IRQ flags which will trigger a retry around the IRQ loop */ |
47a1685f DN |
3170 | #define IRQ_RETRY_MASK (GINTSTS_NPTXFEMP | \ |
3171 | GINTSTS_PTXFEMP | \ | |
3172 | GINTSTS_RXFLVL) | |
5b7d70c6 | 3173 | |
8b9bc460 | 3174 | /** |
1f91b4cc | 3175 | * dwc2_hsotg_core_init - issue softreset to the core |
8b9bc460 LM |
3176 | * @hsotg: The device state |
3177 | * | |
3178 | * Issue a soft reset to the core, and await the core finishing it. | |
3179 | */ | |
1f91b4cc | 3180 | void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg, |
9da51974 | 3181 | bool is_usb_reset) |
308d734e | 3182 | { |
1ee6903b | 3183 | u32 intmsk; |
643cc4de | 3184 | u32 val; |
ecd9a7ad | 3185 | u32 usbcfg; |
79c3b5bb | 3186 | u32 dcfg = 0; |
643cc4de | 3187 | |
5390d438 MYK |
3188 | /* Kill any ep0 requests as controller will be reinitialized */ |
3189 | kill_all_requests(hsotg, hsotg->eps_out[0], -ECONNRESET); | |
3190 | ||
643cc4de | 3191 | if (!is_usb_reset) |
6e6360b6 | 3192 | if (dwc2_core_reset(hsotg, true)) |
86de4895 | 3193 | return; |
308d734e LM |
3194 | |
3195 | /* | |
3196 | * we must now enable ep0 ready for host detection and then | |
3197 | * set configuration. | |
3198 | */ | |
3199 | ||
ecd9a7ad PR |
3200 | /* keep other bits untouched (so e.g. forced modes are not lost) */ |
3201 | usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); | |
3202 | usbcfg &= ~(GUSBCFG_TOUTCAL_MASK | GUSBCFG_PHYIF16 | GUSBCFG_SRPCAP | | |
ca02954a | 3203 | GUSBCFG_HNPCAP | GUSBCFG_USBTRDTIM_MASK); |
ecd9a7ad | 3204 | |
79c3b5bb | 3205 | if (hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS && |
38e9002b VM |
3206 | (hsotg->params.speed == DWC2_SPEED_PARAM_FULL || |
3207 | hsotg->params.speed == DWC2_SPEED_PARAM_LOW)) { | |
79c3b5bb VA |
3208 | /* FS/LS Dedicated Transceiver Interface */ |
3209 | usbcfg |= GUSBCFG_PHYSEL; | |
3210 | } else { | |
3211 | /* set the PLL on, remove the HNP/SRP and set the PHY */ | |
3212 | val = (hsotg->phyif == GUSBCFG_PHYIF8) ? 9 : 5; | |
3213 | usbcfg |= hsotg->phyif | GUSBCFG_TOUTCAL(7) | | |
3214 | (val << GUSBCFG_USBTRDTIM_SHIFT); | |
3215 | } | |
ecd9a7ad | 3216 | dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); |
308d734e | 3217 | |
1f91b4cc | 3218 | dwc2_hsotg_init_fifo(hsotg); |
308d734e | 3219 | |
643cc4de | 3220 | if (!is_usb_reset) |
abd064a1 | 3221 | dwc2_set_bit(hsotg->regs + DCTL, DCTL_SFTDISCON); |
308d734e | 3222 | |
79c3b5bb | 3223 | dcfg |= DCFG_EPMISCNT(1); |
38e9002b VM |
3224 | |
3225 | switch (hsotg->params.speed) { | |
3226 | case DWC2_SPEED_PARAM_LOW: | |
3227 | dcfg |= DCFG_DEVSPD_LS; | |
3228 | break; | |
3229 | case DWC2_SPEED_PARAM_FULL: | |
79c3b5bb VA |
3230 | if (hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS) |
3231 | dcfg |= DCFG_DEVSPD_FS48; | |
3232 | else | |
3233 | dcfg |= DCFG_DEVSPD_FS; | |
38e9002b VM |
3234 | break; |
3235 | default: | |
79c3b5bb VA |
3236 | dcfg |= DCFG_DEVSPD_HS; |
3237 | } | |
38e9002b | 3238 | |
79c3b5bb | 3239 | dwc2_writel(dcfg, hsotg->regs + DCFG); |
308d734e LM |
3240 | |
3241 | /* Clear any pending OTG interrupts */ | |
95c8bc36 | 3242 | dwc2_writel(0xffffffff, hsotg->regs + GOTGINT); |
308d734e LM |
3243 | |
3244 | /* Clear any pending interrupts */ | |
95c8bc36 | 3245 | dwc2_writel(0xffffffff, hsotg->regs + GINTSTS); |
1ee6903b | 3246 | intmsk = GINTSTS_ERLYSUSP | GINTSTS_SESSREQINT | |
47a1685f | 3247 | GINTSTS_GOUTNAKEFF | GINTSTS_GINNAKEFF | |
1ee6903b GH |
3248 | GINTSTS_USBRST | GINTSTS_RESETDET | |
3249 | GINTSTS_ENUMDONE | GINTSTS_OTGINT | | |
376f0401 SA |
3250 | GINTSTS_USBSUSP | GINTSTS_WKUPINT | |
3251 | GINTSTS_LPMTRANRCVD; | |
f4736701 VA |
3252 | |
3253 | if (!using_desc_dma(hsotg)) | |
3254 | intmsk |= GINTSTS_INCOMPL_SOIN | GINTSTS_INCOMPL_SOOUT; | |
1ee6903b | 3255 | |
95832c00 | 3256 | if (!hsotg->params.external_id_pin_ctl) |
1ee6903b GH |
3257 | intmsk |= GINTSTS_CONIDSTSCHNG; |
3258 | ||
3259 | dwc2_writel(intmsk, hsotg->regs + GINTMSK); | |
308d734e | 3260 | |
a5c18f11 | 3261 | if (using_dma(hsotg)) { |
95c8bc36 | 3262 | dwc2_writel(GAHBCFG_GLBL_INTR_EN | GAHBCFG_DMA_EN | |
d1ac8c80 | 3263 | hsotg->params.ahbcfg, |
95c8bc36 | 3264 | hsotg->regs + GAHBCFG); |
a5c18f11 VA |
3265 | |
3266 | /* Set DDMA mode support in the core if needed */ | |
3267 | if (using_desc_dma(hsotg)) | |
abd064a1 | 3268 | dwc2_set_bit(hsotg->regs + DCFG, DCFG_DESCDMA_EN); |
a5c18f11 VA |
3269 | |
3270 | } else { | |
95c8bc36 AS |
3271 | dwc2_writel(((hsotg->dedicated_fifos) ? |
3272 | (GAHBCFG_NP_TXF_EMP_LVL | | |
3273 | GAHBCFG_P_TXF_EMP_LVL) : 0) | | |
3274 | GAHBCFG_GLBL_INTR_EN, hsotg->regs + GAHBCFG); | |
a5c18f11 | 3275 | } |
308d734e LM |
3276 | |
3277 | /* | |
8acc8296 RB |
3278 | * If INTknTXFEmpMsk is enabled, it's important to disable ep interrupts |
3279 | * when we have no data to transfer. Otherwise we get being flooded by | |
3280 | * interrupts. | |
308d734e LM |
3281 | */ |
3282 | ||
95c8bc36 | 3283 | dwc2_writel(((hsotg->dedicated_fifos && !using_dma(hsotg)) ? |
6ff2e832 | 3284 | DIEPMSK_TXFIFOEMPTY | DIEPMSK_INTKNTXFEMPMSK : 0) | |
47a1685f | 3285 | DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK | |
837e9f00 | 3286 | DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK, |
47a1685f | 3287 | hsotg->regs + DIEPMSK); |
308d734e LM |
3288 | |
3289 | /* | |
3290 | * don't need XferCompl, we get that from RXFIFO in slave mode. In | |
9d9a6b07 | 3291 | * DMA mode we may need this and StsPhseRcvd. |
308d734e | 3292 | */ |
9d9a6b07 VA |
3293 | dwc2_writel((using_dma(hsotg) ? (DIEPMSK_XFERCOMPLMSK | |
3294 | DOEPMSK_STSPHSERCVDMSK) : 0) | | |
47a1685f | 3295 | DOEPMSK_EPDISBLDMSK | DOEPMSK_AHBERRMSK | |
9d9a6b07 | 3296 | DOEPMSK_SETUPMSK, |
47a1685f | 3297 | hsotg->regs + DOEPMSK); |
308d734e | 3298 | |
ec01f0b2 | 3299 | /* Enable BNA interrupt for DDMA */ |
37981e00 | 3300 | if (using_desc_dma(hsotg)) { |
abd064a1 | 3301 | dwc2_set_bit(hsotg->regs + DOEPMSK, DOEPMSK_BNAMSK); |
37981e00 MH |
3302 | dwc2_set_bit(hsotg->regs + DIEPMSK, DIEPMSK_BNAININTRMSK); |
3303 | } | |
ec01f0b2 | 3304 | |
95c8bc36 | 3305 | dwc2_writel(0, hsotg->regs + DAINTMSK); |
308d734e LM |
3306 | |
3307 | dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n", | |
95c8bc36 AS |
3308 | dwc2_readl(hsotg->regs + DIEPCTL0), |
3309 | dwc2_readl(hsotg->regs + DOEPCTL0)); | |
308d734e LM |
3310 | |
3311 | /* enable in and out endpoint interrupts */ | |
1f91b4cc | 3312 | dwc2_hsotg_en_gsint(hsotg, GINTSTS_OEPINT | GINTSTS_IEPINT); |
308d734e LM |
3313 | |
3314 | /* | |
3315 | * Enable the RXFIFO when in slave mode, as this is how we collect | |
3316 | * the data. In DMA mode, we get events from the FIFO but also | |
3317 | * things we cannot process, so do not use it. | |
3318 | */ | |
3319 | if (!using_dma(hsotg)) | |
1f91b4cc | 3320 | dwc2_hsotg_en_gsint(hsotg, GINTSTS_RXFLVL); |
308d734e LM |
3321 | |
3322 | /* Enable interrupts for EP0 in and out */ | |
1f91b4cc FB |
3323 | dwc2_hsotg_ctrl_epint(hsotg, 0, 0, 1); |
3324 | dwc2_hsotg_ctrl_epint(hsotg, 0, 1, 1); | |
308d734e | 3325 | |
643cc4de | 3326 | if (!is_usb_reset) { |
abd064a1 | 3327 | dwc2_set_bit(hsotg->regs + DCTL, DCTL_PWRONPRGDONE); |
643cc4de | 3328 | udelay(10); /* see openiboot */ |
abd064a1 | 3329 | dwc2_clear_bit(hsotg->regs + DCTL, DCTL_PWRONPRGDONE); |
643cc4de | 3330 | } |
308d734e | 3331 | |
95c8bc36 | 3332 | dev_dbg(hsotg->dev, "DCTL=0x%08x\n", dwc2_readl(hsotg->regs + DCTL)); |
308d734e LM |
3333 | |
3334 | /* | |
94cb8fd6 | 3335 | * DxEPCTL_USBActEp says RO in manual, but seems to be set by |
308d734e LM |
3336 | * writing to the EPCTL register.. |
3337 | */ | |
3338 | ||
3339 | /* set to read 1 8byte packet */ | |
95c8bc36 | 3340 | dwc2_writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) | |
47a1685f | 3341 | DXEPTSIZ_XFERSIZE(8), hsotg->regs + DOEPTSIZ0); |
308d734e | 3342 | |
95c8bc36 | 3343 | dwc2_writel(dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) | |
47a1685f DN |
3344 | DXEPCTL_CNAK | DXEPCTL_EPENA | |
3345 | DXEPCTL_USBACTEP, | |
94cb8fd6 | 3346 | hsotg->regs + DOEPCTL0); |
308d734e LM |
3347 | |
3348 | /* enable, but don't activate EP0in */ | |
95c8bc36 | 3349 | dwc2_writel(dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) | |
47a1685f | 3350 | DXEPCTL_USBACTEP, hsotg->regs + DIEPCTL0); |
308d734e | 3351 | |
308d734e | 3352 | /* clear global NAKs */ |
643cc4de GH |
3353 | val = DCTL_CGOUTNAK | DCTL_CGNPINNAK; |
3354 | if (!is_usb_reset) | |
3355 | val |= DCTL_SFTDISCON; | |
abd064a1 | 3356 | dwc2_set_bit(hsotg->regs + DCTL, val); |
308d734e | 3357 | |
21b03405 SA |
3358 | /* configure the core to support LPM */ |
3359 | dwc2_gadget_init_lpm(hsotg); | |
3360 | ||
308d734e LM |
3361 | /* must be at-least 3ms to allow bus to see disconnect */ |
3362 | mdelay(3); | |
3363 | ||
065d3931 | 3364 | hsotg->lx_state = DWC2_L0; |
755d7395 VM |
3365 | |
3366 | dwc2_hsotg_enqueue_setup(hsotg); | |
3367 | ||
3368 | dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n", | |
3369 | dwc2_readl(hsotg->regs + DIEPCTL0), | |
3370 | dwc2_readl(hsotg->regs + DOEPCTL0)); | |
ad38dc5d MS |
3371 | } |
3372 | ||
1f91b4cc | 3373 | static void dwc2_hsotg_core_disconnect(struct dwc2_hsotg *hsotg) |
ad38dc5d MS |
3374 | { |
3375 | /* set the soft-disconnect bit */ | |
abd064a1 | 3376 | dwc2_set_bit(hsotg->regs + DCTL, DCTL_SFTDISCON); |
ad38dc5d | 3377 | } |
ac3c81f3 | 3378 | |
1f91b4cc | 3379 | void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg) |
ad38dc5d | 3380 | { |
308d734e | 3381 | /* remove the soft-disconnect and let's go */ |
abd064a1 | 3382 | dwc2_clear_bit(hsotg->regs + DCTL, DCTL_SFTDISCON); |
308d734e LM |
3383 | } |
3384 | ||
381fc8f8 VM |
3385 | /** |
3386 | * dwc2_gadget_handle_incomplete_isoc_in - handle incomplete ISO IN Interrupt. | |
3387 | * @hsotg: The device state: | |
3388 | * | |
3389 | * This interrupt indicates one of the following conditions occurred while | |
3390 | * transmitting an ISOC transaction. | |
3391 | * - Corrupted IN Token for ISOC EP. | |
3392 | * - Packet not complete in FIFO. | |
3393 | * | |
3394 | * The following actions will be taken: | |
3395 | * - Determine the EP | |
3396 | * - Disable EP; when 'Endpoint Disabled' interrupt is received Flush FIFO | |
3397 | */ | |
3398 | static void dwc2_gadget_handle_incomplete_isoc_in(struct dwc2_hsotg *hsotg) | |
3399 | { | |
3400 | struct dwc2_hsotg_ep *hs_ep; | |
3401 | u32 epctrl; | |
1b4977c7 | 3402 | u32 daintmsk; |
381fc8f8 VM |
3403 | u32 idx; |
3404 | ||
3405 | dev_dbg(hsotg->dev, "Incomplete isoc in interrupt received:\n"); | |
3406 | ||
1b4977c7 RK |
3407 | daintmsk = dwc2_readl(hsotg->regs + DAINTMSK); |
3408 | ||
381fc8f8 VM |
3409 | for (idx = 1; idx <= hsotg->num_of_eps; idx++) { |
3410 | hs_ep = hsotg->eps_in[idx]; | |
1b4977c7 RK |
3411 | /* Proceed only unmasked ISOC EPs */ |
3412 | if (!hs_ep->isochronous || (BIT(idx) & ~daintmsk)) | |
3413 | continue; | |
3414 | ||
381fc8f8 | 3415 | epctrl = dwc2_readl(hsotg->regs + DIEPCTL(idx)); |
1b4977c7 | 3416 | if ((epctrl & DXEPCTL_EPENA) && |
381fc8f8 VM |
3417 | dwc2_gadget_target_frame_elapsed(hs_ep)) { |
3418 | epctrl |= DXEPCTL_SNAK; | |
3419 | epctrl |= DXEPCTL_EPDIS; | |
3420 | dwc2_writel(epctrl, hsotg->regs + DIEPCTL(idx)); | |
3421 | } | |
3422 | } | |
3423 | ||
3424 | /* Clear interrupt */ | |
3425 | dwc2_writel(GINTSTS_INCOMPL_SOIN, hsotg->regs + GINTSTS); | |
3426 | } | |
3427 | ||
3428 | /** | |
3429 | * dwc2_gadget_handle_incomplete_isoc_out - handle incomplete ISO OUT Interrupt | |
3430 | * @hsotg: The device state: | |
3431 | * | |
3432 | * This interrupt indicates one of the following conditions occurred while | |
3433 | * transmitting an ISOC transaction. | |
3434 | * - Corrupted OUT Token for ISOC EP. | |
3435 | * - Packet not complete in FIFO. | |
3436 | * | |
3437 | * The following actions will be taken: | |
3438 | * - Determine the EP | |
3439 | * - Set DCTL_SGOUTNAK and unmask GOUTNAKEFF if target frame elapsed. | |
3440 | */ | |
3441 | static void dwc2_gadget_handle_incomplete_isoc_out(struct dwc2_hsotg *hsotg) | |
3442 | { | |
3443 | u32 gintsts; | |
3444 | u32 gintmsk; | |
689efb26 | 3445 | u32 daintmsk; |
381fc8f8 VM |
3446 | u32 epctrl; |
3447 | struct dwc2_hsotg_ep *hs_ep; | |
3448 | int idx; | |
3449 | ||
3450 | dev_dbg(hsotg->dev, "%s: GINTSTS_INCOMPL_SOOUT\n", __func__); | |
3451 | ||
689efb26 RK |
3452 | daintmsk = dwc2_readl(hsotg->regs + DAINTMSK); |
3453 | daintmsk >>= DAINT_OUTEP_SHIFT; | |
3454 | ||
381fc8f8 VM |
3455 | for (idx = 1; idx <= hsotg->num_of_eps; idx++) { |
3456 | hs_ep = hsotg->eps_out[idx]; | |
689efb26 RK |
3457 | /* Proceed only unmasked ISOC EPs */ |
3458 | if (!hs_ep->isochronous || (BIT(idx) & ~daintmsk)) | |
3459 | continue; | |
3460 | ||
381fc8f8 | 3461 | epctrl = dwc2_readl(hsotg->regs + DOEPCTL(idx)); |
689efb26 | 3462 | if ((epctrl & DXEPCTL_EPENA) && |
381fc8f8 VM |
3463 | dwc2_gadget_target_frame_elapsed(hs_ep)) { |
3464 | /* Unmask GOUTNAKEFF interrupt */ | |
3465 | gintmsk = dwc2_readl(hsotg->regs + GINTMSK); | |
3466 | gintmsk |= GINTSTS_GOUTNAKEFF; | |
3467 | dwc2_writel(gintmsk, hsotg->regs + GINTMSK); | |
3468 | ||
3469 | gintsts = dwc2_readl(hsotg->regs + GINTSTS); | |
689efb26 | 3470 | if (!(gintsts & GINTSTS_GOUTNAKEFF)) { |
abd064a1 | 3471 | dwc2_set_bit(hsotg->regs + DCTL, DCTL_SGOUTNAK); |
689efb26 RK |
3472 | break; |
3473 | } | |
381fc8f8 VM |
3474 | } |
3475 | } | |
3476 | ||
3477 | /* Clear interrupt */ | |
3478 | dwc2_writel(GINTSTS_INCOMPL_SOOUT, hsotg->regs + GINTSTS); | |
3479 | } | |
3480 | ||
5b7d70c6 | 3481 | /** |
1f91b4cc | 3482 | * dwc2_hsotg_irq - handle device interrupt |
5b7d70c6 BD |
3483 | * @irq: The IRQ number triggered |
3484 | * @pw: The pw value when registered the handler. | |
3485 | */ | |
1f91b4cc | 3486 | static irqreturn_t dwc2_hsotg_irq(int irq, void *pw) |
5b7d70c6 | 3487 | { |
941fcce4 | 3488 | struct dwc2_hsotg *hsotg = pw; |
5b7d70c6 BD |
3489 | int retry_count = 8; |
3490 | u32 gintsts; | |
3491 | u32 gintmsk; | |
3492 | ||
ee3de8d7 VM |
3493 | if (!dwc2_is_device_mode(hsotg)) |
3494 | return IRQ_NONE; | |
3495 | ||
5ad1d316 | 3496 | spin_lock(&hsotg->lock); |
5b7d70c6 | 3497 | irq_retry: |
95c8bc36 AS |
3498 | gintsts = dwc2_readl(hsotg->regs + GINTSTS); |
3499 | gintmsk = dwc2_readl(hsotg->regs + GINTMSK); | |
5b7d70c6 BD |
3500 | |
3501 | dev_dbg(hsotg->dev, "%s: %08x %08x (%08x) retry %d\n", | |
3502 | __func__, gintsts, gintsts & gintmsk, gintmsk, retry_count); | |
3503 | ||
3504 | gintsts &= gintmsk; | |
3505 | ||
8fc37b82 MYK |
3506 | if (gintsts & GINTSTS_RESETDET) { |
3507 | dev_dbg(hsotg->dev, "%s: USBRstDet\n", __func__); | |
3508 | ||
3509 | dwc2_writel(GINTSTS_RESETDET, hsotg->regs + GINTSTS); | |
3510 | ||
3511 | /* This event must be used only if controller is suspended */ | |
3512 | if (hsotg->lx_state == DWC2_L2) { | |
41ba9b9b | 3513 | dwc2_exit_partial_power_down(hsotg, true); |
8fc37b82 MYK |
3514 | hsotg->lx_state = DWC2_L0; |
3515 | } | |
3516 | } | |
3517 | ||
3518 | if (gintsts & (GINTSTS_USBRST | GINTSTS_RESETDET)) { | |
8fc37b82 MYK |
3519 | u32 usb_status = dwc2_readl(hsotg->regs + GOTGCTL); |
3520 | u32 connected = hsotg->connected; | |
3521 | ||
3522 | dev_dbg(hsotg->dev, "%s: USBRst\n", __func__); | |
3523 | dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n", | |
3524 | dwc2_readl(hsotg->regs + GNPTXSTS)); | |
3525 | ||
3526 | dwc2_writel(GINTSTS_USBRST, hsotg->regs + GINTSTS); | |
3527 | ||
3528 | /* Report disconnection if it is not already done. */ | |
3529 | dwc2_hsotg_disconnect(hsotg); | |
3530 | ||
307bc11f | 3531 | /* Reset device address to zero */ |
abd064a1 | 3532 | dwc2_clear_bit(hsotg->regs + DCFG, DCFG_DEVADDR_MASK); |
307bc11f | 3533 | |
8fc37b82 MYK |
3534 | if (usb_status & GOTGCTL_BSESVLD && connected) |
3535 | dwc2_hsotg_core_init_disconnected(hsotg, true); | |
3536 | } | |
3537 | ||
47a1685f | 3538 | if (gintsts & GINTSTS_ENUMDONE) { |
95c8bc36 | 3539 | dwc2_writel(GINTSTS_ENUMDONE, hsotg->regs + GINTSTS); |
a3395f0d | 3540 | |
1f91b4cc | 3541 | dwc2_hsotg_irq_enumdone(hsotg); |
5b7d70c6 BD |
3542 | } |
3543 | ||
47a1685f | 3544 | if (gintsts & (GINTSTS_OEPINT | GINTSTS_IEPINT)) { |
95c8bc36 AS |
3545 | u32 daint = dwc2_readl(hsotg->regs + DAINT); |
3546 | u32 daintmsk = dwc2_readl(hsotg->regs + DAINTMSK); | |
7e804650 | 3547 | u32 daint_out, daint_in; |
5b7d70c6 BD |
3548 | int ep; |
3549 | ||
7e804650 | 3550 | daint &= daintmsk; |
47a1685f DN |
3551 | daint_out = daint >> DAINT_OUTEP_SHIFT; |
3552 | daint_in = daint & ~(daint_out << DAINT_OUTEP_SHIFT); | |
7e804650 | 3553 | |
5b7d70c6 BD |
3554 | dev_dbg(hsotg->dev, "%s: daint=%08x\n", __func__, daint); |
3555 | ||
cec87f1d MYK |
3556 | for (ep = 0; ep < hsotg->num_of_eps && daint_out; |
3557 | ep++, daint_out >>= 1) { | |
5b7d70c6 | 3558 | if (daint_out & 1) |
1f91b4cc | 3559 | dwc2_hsotg_epint(hsotg, ep, 0); |
5b7d70c6 BD |
3560 | } |
3561 | ||
cec87f1d MYK |
3562 | for (ep = 0; ep < hsotg->num_of_eps && daint_in; |
3563 | ep++, daint_in >>= 1) { | |
5b7d70c6 | 3564 | if (daint_in & 1) |
1f91b4cc | 3565 | dwc2_hsotg_epint(hsotg, ep, 1); |
5b7d70c6 | 3566 | } |
5b7d70c6 BD |
3567 | } |
3568 | ||
5b7d70c6 BD |
3569 | /* check both FIFOs */ |
3570 | ||
47a1685f | 3571 | if (gintsts & GINTSTS_NPTXFEMP) { |
5b7d70c6 BD |
3572 | dev_dbg(hsotg->dev, "NPTxFEmp\n"); |
3573 | ||
8b9bc460 LM |
3574 | /* |
3575 | * Disable the interrupt to stop it happening again | |
5b7d70c6 | 3576 | * unless one of these endpoint routines decides that |
8b9bc460 LM |
3577 | * it needs re-enabling |
3578 | */ | |
5b7d70c6 | 3579 | |
1f91b4cc FB |
3580 | dwc2_hsotg_disable_gsint(hsotg, GINTSTS_NPTXFEMP); |
3581 | dwc2_hsotg_irq_fifoempty(hsotg, false); | |
5b7d70c6 BD |
3582 | } |
3583 | ||
47a1685f | 3584 | if (gintsts & GINTSTS_PTXFEMP) { |
5b7d70c6 BD |
3585 | dev_dbg(hsotg->dev, "PTxFEmp\n"); |
3586 | ||
94cb8fd6 | 3587 | /* See note in GINTSTS_NPTxFEmp */ |
5b7d70c6 | 3588 | |
1f91b4cc FB |
3589 | dwc2_hsotg_disable_gsint(hsotg, GINTSTS_PTXFEMP); |
3590 | dwc2_hsotg_irq_fifoempty(hsotg, true); | |
5b7d70c6 BD |
3591 | } |
3592 | ||
47a1685f | 3593 | if (gintsts & GINTSTS_RXFLVL) { |
8b9bc460 LM |
3594 | /* |
3595 | * note, since GINTSTS_RxFLvl doubles as FIFO-not-empty, | |
1f91b4cc | 3596 | * we need to retry dwc2_hsotg_handle_rx if this is still |
8b9bc460 LM |
3597 | * set. |
3598 | */ | |
5b7d70c6 | 3599 | |
1f91b4cc | 3600 | dwc2_hsotg_handle_rx(hsotg); |
5b7d70c6 BD |
3601 | } |
3602 | ||
47a1685f | 3603 | if (gintsts & GINTSTS_ERLYSUSP) { |
94cb8fd6 | 3604 | dev_dbg(hsotg->dev, "GINTSTS_ErlySusp\n"); |
95c8bc36 | 3605 | dwc2_writel(GINTSTS_ERLYSUSP, hsotg->regs + GINTSTS); |
5b7d70c6 BD |
3606 | } |
3607 | ||
8b9bc460 LM |
3608 | /* |
3609 | * these next two seem to crop-up occasionally causing the core | |
5b7d70c6 | 3610 | * to shutdown the USB transfer, so try clearing them and logging |
8b9bc460 LM |
3611 | * the occurrence. |
3612 | */ | |
5b7d70c6 | 3613 | |
47a1685f | 3614 | if (gintsts & GINTSTS_GOUTNAKEFF) { |
837e9f00 VM |
3615 | u8 idx; |
3616 | u32 epctrl; | |
3617 | u32 gintmsk; | |
d8484552 | 3618 | u32 daintmsk; |
837e9f00 VM |
3619 | struct dwc2_hsotg_ep *hs_ep; |
3620 | ||
d8484552 RK |
3621 | daintmsk = dwc2_readl(hsotg->regs + DAINTMSK); |
3622 | daintmsk >>= DAINT_OUTEP_SHIFT; | |
837e9f00 VM |
3623 | /* Mask this interrupt */ |
3624 | gintmsk = dwc2_readl(hsotg->regs + GINTMSK); | |
3625 | gintmsk &= ~GINTSTS_GOUTNAKEFF; | |
3626 | dwc2_writel(gintmsk, hsotg->regs + GINTMSK); | |
3627 | ||
3628 | dev_dbg(hsotg->dev, "GOUTNakEff triggered\n"); | |
3629 | for (idx = 1; idx <= hsotg->num_of_eps; idx++) { | |
3630 | hs_ep = hsotg->eps_out[idx]; | |
d8484552 RK |
3631 | /* Proceed only unmasked ISOC EPs */ |
3632 | if (!hs_ep->isochronous || (BIT(idx) & ~daintmsk)) | |
3633 | continue; | |
3634 | ||
837e9f00 VM |
3635 | epctrl = dwc2_readl(hsotg->regs + DOEPCTL(idx)); |
3636 | ||
d8484552 | 3637 | if (epctrl & DXEPCTL_EPENA) { |
837e9f00 VM |
3638 | epctrl |= DXEPCTL_SNAK; |
3639 | epctrl |= DXEPCTL_EPDIS; | |
3640 | dwc2_writel(epctrl, hsotg->regs + DOEPCTL(idx)); | |
3641 | } | |
3642 | } | |
a3395f0d | 3643 | |
837e9f00 | 3644 | /* This interrupt bit is cleared in DXEPINT_EPDISBLD handler */ |
5b7d70c6 BD |
3645 | } |
3646 | ||
47a1685f | 3647 | if (gintsts & GINTSTS_GINNAKEFF) { |
5b7d70c6 BD |
3648 | dev_info(hsotg->dev, "GINNakEff triggered\n"); |
3649 | ||
abd064a1 | 3650 | dwc2_set_bit(hsotg->regs + DCTL, DCTL_CGNPINNAK); |
a3395f0d | 3651 | |
1f91b4cc | 3652 | dwc2_hsotg_dump(hsotg); |
5b7d70c6 BD |
3653 | } |
3654 | ||
381fc8f8 VM |
3655 | if (gintsts & GINTSTS_INCOMPL_SOIN) |
3656 | dwc2_gadget_handle_incomplete_isoc_in(hsotg); | |
ec1f9d9f | 3657 | |
381fc8f8 VM |
3658 | if (gintsts & GINTSTS_INCOMPL_SOOUT) |
3659 | dwc2_gadget_handle_incomplete_isoc_out(hsotg); | |
ec1f9d9f | 3660 | |
8b9bc460 LM |
3661 | /* |
3662 | * if we've had fifo events, we should try and go around the | |
3663 | * loop again to see if there's any point in returning yet. | |
3664 | */ | |
5b7d70c6 BD |
3665 | |
3666 | if (gintsts & IRQ_RETRY_MASK && --retry_count > 0) | |
77b6200e | 3667 | goto irq_retry; |
5b7d70c6 | 3668 | |
5ad1d316 LM |
3669 | spin_unlock(&hsotg->lock); |
3670 | ||
5b7d70c6 BD |
3671 | return IRQ_HANDLED; |
3672 | } | |
3673 | ||
a4f82771 VA |
3674 | static void dwc2_hsotg_ep_stop_xfr(struct dwc2_hsotg *hsotg, |
3675 | struct dwc2_hsotg_ep *hs_ep) | |
3676 | { | |
3677 | u32 epctrl_reg; | |
3678 | u32 epint_reg; | |
3679 | ||
3680 | epctrl_reg = hs_ep->dir_in ? DIEPCTL(hs_ep->index) : | |
3681 | DOEPCTL(hs_ep->index); | |
3682 | epint_reg = hs_ep->dir_in ? DIEPINT(hs_ep->index) : | |
3683 | DOEPINT(hs_ep->index); | |
3684 | ||
3685 | dev_dbg(hsotg->dev, "%s: stopping transfer on %s\n", __func__, | |
3686 | hs_ep->name); | |
3687 | ||
3688 | if (hs_ep->dir_in) { | |
3689 | if (hsotg->dedicated_fifos || hs_ep->periodic) { | |
abd064a1 | 3690 | dwc2_set_bit(hsotg->regs + epctrl_reg, DXEPCTL_SNAK); |
a4f82771 VA |
3691 | /* Wait for Nak effect */ |
3692 | if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg, | |
3693 | DXEPINT_INEPNAKEFF, 100)) | |
3694 | dev_warn(hsotg->dev, | |
3695 | "%s: timeout DIEPINT.NAKEFF\n", | |
3696 | __func__); | |
3697 | } else { | |
abd064a1 | 3698 | dwc2_set_bit(hsotg->regs + DCTL, DCTL_SGNPINNAK); |
a4f82771 VA |
3699 | /* Wait for Nak effect */ |
3700 | if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS, | |
3701 | GINTSTS_GINNAKEFF, 100)) | |
3702 | dev_warn(hsotg->dev, | |
3703 | "%s: timeout GINTSTS.GINNAKEFF\n", | |
3704 | __func__); | |
3705 | } | |
3706 | } else { | |
3707 | if (!(dwc2_readl(hsotg->regs + GINTSTS) & GINTSTS_GOUTNAKEFF)) | |
abd064a1 | 3708 | dwc2_set_bit(hsotg->regs + DCTL, DCTL_SGOUTNAK); |
a4f82771 VA |
3709 | |
3710 | /* Wait for global nak to take effect */ | |
3711 | if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS, | |
3712 | GINTSTS_GOUTNAKEFF, 100)) | |
3713 | dev_warn(hsotg->dev, "%s: timeout GINTSTS.GOUTNAKEFF\n", | |
3714 | __func__); | |
3715 | } | |
3716 | ||
3717 | /* Disable ep */ | |
abd064a1 | 3718 | dwc2_set_bit(hsotg->regs + epctrl_reg, DXEPCTL_EPDIS | DXEPCTL_SNAK); |
a4f82771 VA |
3719 | |
3720 | /* Wait for ep to be disabled */ | |
3721 | if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg, DXEPINT_EPDISBLD, 100)) | |
3722 | dev_warn(hsotg->dev, | |
3723 | "%s: timeout DOEPCTL.EPDisable\n", __func__); | |
3724 | ||
3725 | /* Clear EPDISBLD interrupt */ | |
abd064a1 | 3726 | dwc2_set_bit(hsotg->regs + epint_reg, DXEPINT_EPDISBLD); |
a4f82771 VA |
3727 | |
3728 | if (hs_ep->dir_in) { | |
3729 | unsigned short fifo_index; | |
3730 | ||
3731 | if (hsotg->dedicated_fifos || hs_ep->periodic) | |
3732 | fifo_index = hs_ep->fifo_index; | |
3733 | else | |
3734 | fifo_index = 0; | |
3735 | ||
3736 | /* Flush TX FIFO */ | |
3737 | dwc2_flush_tx_fifo(hsotg, fifo_index); | |
3738 | ||
3739 | /* Clear Global In NP NAK in Shared FIFO for non periodic ep */ | |
3740 | if (!hsotg->dedicated_fifos && !hs_ep->periodic) | |
abd064a1 | 3741 | dwc2_set_bit(hsotg->regs + DCTL, DCTL_CGNPINNAK); |
a4f82771 VA |
3742 | |
3743 | } else { | |
3744 | /* Remove global NAKs */ | |
abd064a1 | 3745 | dwc2_set_bit(hsotg->regs + DCTL, DCTL_CGOUTNAK); |
a4f82771 VA |
3746 | } |
3747 | } | |
3748 | ||
5b7d70c6 | 3749 | /** |
1f91b4cc | 3750 | * dwc2_hsotg_ep_enable - enable the given endpoint |
5b7d70c6 BD |
3751 | * @ep: The USB endpint to configure |
3752 | * @desc: The USB endpoint descriptor to configure with. | |
3753 | * | |
3754 | * This is called from the USB gadget code's usb_ep_enable(). | |
8b9bc460 | 3755 | */ |
1f91b4cc | 3756 | static int dwc2_hsotg_ep_enable(struct usb_ep *ep, |
9da51974 | 3757 | const struct usb_endpoint_descriptor *desc) |
5b7d70c6 | 3758 | { |
1f91b4cc | 3759 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 3760 | struct dwc2_hsotg *hsotg = hs_ep->parent; |
5b7d70c6 | 3761 | unsigned long flags; |
ca4c55ad | 3762 | unsigned int index = hs_ep->index; |
5b7d70c6 BD |
3763 | u32 epctrl_reg; |
3764 | u32 epctrl; | |
3765 | u32 mps; | |
ee2c40de | 3766 | u32 mc; |
837e9f00 | 3767 | u32 mask; |
ca4c55ad MYK |
3768 | unsigned int dir_in; |
3769 | unsigned int i, val, size; | |
19c190f9 | 3770 | int ret = 0; |
729cac69 | 3771 | unsigned char ep_type; |
5b7d70c6 BD |
3772 | |
3773 | dev_dbg(hsotg->dev, | |
3774 | "%s: ep %s: a 0x%02x, attr 0x%02x, mps 0x%04x, intr %d\n", | |
3775 | __func__, ep->name, desc->bEndpointAddress, desc->bmAttributes, | |
3776 | desc->wMaxPacketSize, desc->bInterval); | |
3777 | ||
3778 | /* not to be called for EP0 */ | |
8c3d6092 VA |
3779 | if (index == 0) { |
3780 | dev_err(hsotg->dev, "%s: called for EP 0\n", __func__); | |
3781 | return -EINVAL; | |
3782 | } | |
5b7d70c6 BD |
3783 | |
3784 | dir_in = (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) ? 1 : 0; | |
3785 | if (dir_in != hs_ep->dir_in) { | |
3786 | dev_err(hsotg->dev, "%s: direction mismatch!\n", __func__); | |
3787 | return -EINVAL; | |
3788 | } | |
3789 | ||
729cac69 | 3790 | ep_type = desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK; |
29cc8897 | 3791 | mps = usb_endpoint_maxp(desc); |
ee2c40de | 3792 | mc = usb_endpoint_maxp_mult(desc); |
5b7d70c6 | 3793 | |
729cac69 MH |
3794 | /* ISOC IN in DDMA supported bInterval up to 10 */ |
3795 | if (using_desc_dma(hsotg) && ep_type == USB_ENDPOINT_XFER_ISOC && | |
3796 | dir_in && desc->bInterval > 10) { | |
3797 | dev_err(hsotg->dev, | |
3798 | "%s: ISOC IN, DDMA: bInterval>10 not supported!\n", __func__); | |
3799 | return -EINVAL; | |
3800 | } | |
3801 | ||
3802 | /* High bandwidth ISOC OUT in DDMA not supported */ | |
3803 | if (using_desc_dma(hsotg) && ep_type == USB_ENDPOINT_XFER_ISOC && | |
3804 | !dir_in && mc > 1) { | |
3805 | dev_err(hsotg->dev, | |
3806 | "%s: ISOC OUT, DDMA: HB not supported!\n", __func__); | |
3807 | return -EINVAL; | |
3808 | } | |
3809 | ||
1f91b4cc | 3810 | /* note, we handle this here instead of dwc2_hsotg_set_ep_maxpacket */ |
5b7d70c6 | 3811 | |
94cb8fd6 | 3812 | epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index); |
95c8bc36 | 3813 | epctrl = dwc2_readl(hsotg->regs + epctrl_reg); |
5b7d70c6 BD |
3814 | |
3815 | dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x from 0x%08x\n", | |
3816 | __func__, epctrl, epctrl_reg); | |
3817 | ||
5f54c54b | 3818 | /* Allocate DMA descriptor chain for non-ctrl endpoints */ |
9383e084 VM |
3819 | if (using_desc_dma(hsotg) && !hs_ep->desc_list) { |
3820 | hs_ep->desc_list = dmam_alloc_coherent(hsotg->dev, | |
5f54c54b VA |
3821 | MAX_DMA_DESC_NUM_GENERIC * |
3822 | sizeof(struct dwc2_dma_desc), | |
86e881e7 | 3823 | &hs_ep->desc_list_dma, GFP_ATOMIC); |
5f54c54b VA |
3824 | if (!hs_ep->desc_list) { |
3825 | ret = -ENOMEM; | |
3826 | goto error2; | |
3827 | } | |
3828 | } | |
3829 | ||
22258f49 | 3830 | spin_lock_irqsave(&hsotg->lock, flags); |
5b7d70c6 | 3831 | |
47a1685f DN |
3832 | epctrl &= ~(DXEPCTL_EPTYPE_MASK | DXEPCTL_MPS_MASK); |
3833 | epctrl |= DXEPCTL_MPS(mps); | |
5b7d70c6 | 3834 | |
8b9bc460 LM |
3835 | /* |
3836 | * mark the endpoint as active, otherwise the core may ignore | |
3837 | * transactions entirely for this endpoint | |
3838 | */ | |
47a1685f | 3839 | epctrl |= DXEPCTL_USBACTEP; |
5b7d70c6 | 3840 | |
5b7d70c6 | 3841 | /* update the endpoint state */ |
ee2c40de | 3842 | dwc2_hsotg_set_ep_maxpacket(hsotg, hs_ep->index, mps, mc, dir_in); |
5b7d70c6 BD |
3843 | |
3844 | /* default, set to non-periodic */ | |
1479e841 | 3845 | hs_ep->isochronous = 0; |
5b7d70c6 | 3846 | hs_ep->periodic = 0; |
a18ed7b0 | 3847 | hs_ep->halted = 0; |
1479e841 | 3848 | hs_ep->interval = desc->bInterval; |
4fca54aa | 3849 | |
729cac69 | 3850 | switch (ep_type) { |
5b7d70c6 | 3851 | case USB_ENDPOINT_XFER_ISOC: |
47a1685f DN |
3852 | epctrl |= DXEPCTL_EPTYPE_ISO; |
3853 | epctrl |= DXEPCTL_SETEVENFR; | |
1479e841 | 3854 | hs_ep->isochronous = 1; |
142bd33f | 3855 | hs_ep->interval = 1 << (desc->bInterval - 1); |
837e9f00 | 3856 | hs_ep->target_frame = TARGET_FRAME_INITIAL; |
ab7d2192 | 3857 | hs_ep->next_desc = 0; |
729cac69 | 3858 | hs_ep->compl_desc = 0; |
837e9f00 | 3859 | if (dir_in) { |
1479e841 | 3860 | hs_ep->periodic = 1; |
837e9f00 VM |
3861 | mask = dwc2_readl(hsotg->regs + DIEPMSK); |
3862 | mask |= DIEPMSK_NAKMSK; | |
3863 | dwc2_writel(mask, hsotg->regs + DIEPMSK); | |
3864 | } else { | |
3865 | mask = dwc2_readl(hsotg->regs + DOEPMSK); | |
3866 | mask |= DOEPMSK_OUTTKNEPDISMSK; | |
3867 | dwc2_writel(mask, hsotg->regs + DOEPMSK); | |
3868 | } | |
1479e841 | 3869 | break; |
5b7d70c6 BD |
3870 | |
3871 | case USB_ENDPOINT_XFER_BULK: | |
47a1685f | 3872 | epctrl |= DXEPCTL_EPTYPE_BULK; |
5b7d70c6 BD |
3873 | break; |
3874 | ||
3875 | case USB_ENDPOINT_XFER_INT: | |
b203d0a2 | 3876 | if (dir_in) |
5b7d70c6 | 3877 | hs_ep->periodic = 1; |
5b7d70c6 | 3878 | |
142bd33f VM |
3879 | if (hsotg->gadget.speed == USB_SPEED_HIGH) |
3880 | hs_ep->interval = 1 << (desc->bInterval - 1); | |
3881 | ||
47a1685f | 3882 | epctrl |= DXEPCTL_EPTYPE_INTERRUPT; |
5b7d70c6 BD |
3883 | break; |
3884 | ||
3885 | case USB_ENDPOINT_XFER_CONTROL: | |
47a1685f | 3886 | epctrl |= DXEPCTL_EPTYPE_CONTROL; |
5b7d70c6 BD |
3887 | break; |
3888 | } | |
3889 | ||
8b9bc460 LM |
3890 | /* |
3891 | * if the hardware has dedicated fifos, we must give each IN EP | |
10aebc77 BD |
3892 | * a unique tx-fifo even if it is non-periodic. |
3893 | */ | |
21f3bb52 | 3894 | if (dir_in && hsotg->dedicated_fifos) { |
ca4c55ad MYK |
3895 | u32 fifo_index = 0; |
3896 | u32 fifo_size = UINT_MAX; | |
9da51974 JY |
3897 | |
3898 | size = hs_ep->ep.maxpacket * hs_ep->mc; | |
5f2196bd | 3899 | for (i = 1; i < hsotg->num_of_eps; ++i) { |
9da51974 | 3900 | if (hsotg->fifo_map & (1 << i)) |
b203d0a2 | 3901 | continue; |
95c8bc36 | 3902 | val = dwc2_readl(hsotg->regs + DPTXFSIZN(i)); |
9da51974 | 3903 | val = (val >> FIFOSIZE_DEPTH_SHIFT) * 4; |
b203d0a2 RB |
3904 | if (val < size) |
3905 | continue; | |
ca4c55ad MYK |
3906 | /* Search for smallest acceptable fifo */ |
3907 | if (val < fifo_size) { | |
3908 | fifo_size = val; | |
3909 | fifo_index = i; | |
3910 | } | |
b203d0a2 | 3911 | } |
ca4c55ad | 3912 | if (!fifo_index) { |
5f2196bd MYK |
3913 | dev_err(hsotg->dev, |
3914 | "%s: No suitable fifo found\n", __func__); | |
b585a48b | 3915 | ret = -ENOMEM; |
5f54c54b | 3916 | goto error1; |
b585a48b | 3917 | } |
ca4c55ad MYK |
3918 | hsotg->fifo_map |= 1 << fifo_index; |
3919 | epctrl |= DXEPCTL_TXFNUM(fifo_index); | |
3920 | hs_ep->fifo_index = fifo_index; | |
3921 | hs_ep->fifo_size = fifo_size; | |
b203d0a2 | 3922 | } |
10aebc77 | 3923 | |
5b7d70c6 | 3924 | /* for non control endpoints, set PID to D0 */ |
837e9f00 | 3925 | if (index && !hs_ep->isochronous) |
47a1685f | 3926 | epctrl |= DXEPCTL_SETD0PID; |
5b7d70c6 BD |
3927 | |
3928 | dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n", | |
3929 | __func__, epctrl); | |
3930 | ||
95c8bc36 | 3931 | dwc2_writel(epctrl, hsotg->regs + epctrl_reg); |
5b7d70c6 | 3932 | dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x\n", |
95c8bc36 | 3933 | __func__, dwc2_readl(hsotg->regs + epctrl_reg)); |
5b7d70c6 BD |
3934 | |
3935 | /* enable the endpoint interrupt */ | |
1f91b4cc | 3936 | dwc2_hsotg_ctrl_epint(hsotg, index, dir_in, 1); |
5b7d70c6 | 3937 | |
5f54c54b | 3938 | error1: |
22258f49 | 3939 | spin_unlock_irqrestore(&hsotg->lock, flags); |
5f54c54b VA |
3940 | |
3941 | error2: | |
3942 | if (ret && using_desc_dma(hsotg) && hs_ep->desc_list) { | |
9383e084 | 3943 | dmam_free_coherent(hsotg->dev, MAX_DMA_DESC_NUM_GENERIC * |
5f54c54b VA |
3944 | sizeof(struct dwc2_dma_desc), |
3945 | hs_ep->desc_list, hs_ep->desc_list_dma); | |
3946 | hs_ep->desc_list = NULL; | |
3947 | } | |
3948 | ||
19c190f9 | 3949 | return ret; |
5b7d70c6 BD |
3950 | } |
3951 | ||
8b9bc460 | 3952 | /** |
1f91b4cc | 3953 | * dwc2_hsotg_ep_disable - disable given endpoint |
8b9bc460 LM |
3954 | * @ep: The endpoint to disable. |
3955 | */ | |
1f91b4cc | 3956 | static int dwc2_hsotg_ep_disable(struct usb_ep *ep) |
5b7d70c6 | 3957 | { |
1f91b4cc | 3958 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 3959 | struct dwc2_hsotg *hsotg = hs_ep->parent; |
5b7d70c6 BD |
3960 | int dir_in = hs_ep->dir_in; |
3961 | int index = hs_ep->index; | |
3962 | unsigned long flags; | |
3963 | u32 epctrl_reg; | |
3964 | u32 ctrl; | |
3965 | ||
1e011293 | 3966 | dev_dbg(hsotg->dev, "%s(ep %p)\n", __func__, ep); |
5b7d70c6 | 3967 | |
c6f5c050 | 3968 | if (ep == &hsotg->eps_out[0]->ep) { |
5b7d70c6 BD |
3969 | dev_err(hsotg->dev, "%s: called for ep0\n", __func__); |
3970 | return -EINVAL; | |
9b481092 JS |
3971 | } |
3972 | ||
3973 | if (hsotg->op_state != OTG_STATE_B_PERIPHERAL) { | |
3974 | dev_err(hsotg->dev, "%s: called in host mode?\n", __func__); | |
3975 | return -EINVAL; | |
5b7d70c6 BD |
3976 | } |
3977 | ||
94cb8fd6 | 3978 | epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index); |
5b7d70c6 | 3979 | |
5ad1d316 | 3980 | spin_lock_irqsave(&hsotg->lock, flags); |
5b7d70c6 | 3981 | |
95c8bc36 | 3982 | ctrl = dwc2_readl(hsotg->regs + epctrl_reg); |
a4f82771 VA |
3983 | |
3984 | if (ctrl & DXEPCTL_EPENA) | |
3985 | dwc2_hsotg_ep_stop_xfr(hsotg, hs_ep); | |
3986 | ||
47a1685f DN |
3987 | ctrl &= ~DXEPCTL_EPENA; |
3988 | ctrl &= ~DXEPCTL_USBACTEP; | |
3989 | ctrl |= DXEPCTL_SNAK; | |
5b7d70c6 BD |
3990 | |
3991 | dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl); | |
95c8bc36 | 3992 | dwc2_writel(ctrl, hsotg->regs + epctrl_reg); |
5b7d70c6 BD |
3993 | |
3994 | /* disable endpoint interrupts */ | |
1f91b4cc | 3995 | dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 0); |
5b7d70c6 | 3996 | |
1141ea01 MYK |
3997 | /* terminate all requests with shutdown */ |
3998 | kill_all_requests(hsotg, hs_ep, -ESHUTDOWN); | |
3999 | ||
1c07b20e RB |
4000 | hsotg->fifo_map &= ~(1 << hs_ep->fifo_index); |
4001 | hs_ep->fifo_index = 0; | |
4002 | hs_ep->fifo_size = 0; | |
4003 | ||
22258f49 | 4004 | spin_unlock_irqrestore(&hsotg->lock, flags); |
5b7d70c6 BD |
4005 | return 0; |
4006 | } | |
4007 | ||
4008 | /** | |
4009 | * on_list - check request is on the given endpoint | |
4010 | * @ep: The endpoint to check. | |
4011 | * @test: The request to test if it is on the endpoint. | |
8b9bc460 | 4012 | */ |
1f91b4cc | 4013 | static bool on_list(struct dwc2_hsotg_ep *ep, struct dwc2_hsotg_req *test) |
5b7d70c6 | 4014 | { |
1f91b4cc | 4015 | struct dwc2_hsotg_req *req, *treq; |
5b7d70c6 BD |
4016 | |
4017 | list_for_each_entry_safe(req, treq, &ep->queue, queue) { | |
4018 | if (req == test) | |
4019 | return true; | |
4020 | } | |
4021 | ||
4022 | return false; | |
4023 | } | |
4024 | ||
8b9bc460 | 4025 | /** |
1f91b4cc | 4026 | * dwc2_hsotg_ep_dequeue - dequeue given endpoint |
8b9bc460 LM |
4027 | * @ep: The endpoint to dequeue. |
4028 | * @req: The request to be removed from a queue. | |
4029 | */ | |
1f91b4cc | 4030 | static int dwc2_hsotg_ep_dequeue(struct usb_ep *ep, struct usb_request *req) |
5b7d70c6 | 4031 | { |
1f91b4cc FB |
4032 | struct dwc2_hsotg_req *hs_req = our_req(req); |
4033 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); | |
941fcce4 | 4034 | struct dwc2_hsotg *hs = hs_ep->parent; |
5b7d70c6 BD |
4035 | unsigned long flags; |
4036 | ||
1e011293 | 4037 | dev_dbg(hs->dev, "ep_dequeue(%p,%p)\n", ep, req); |
5b7d70c6 | 4038 | |
22258f49 | 4039 | spin_lock_irqsave(&hs->lock, flags); |
5b7d70c6 BD |
4040 | |
4041 | if (!on_list(hs_ep, hs_req)) { | |
22258f49 | 4042 | spin_unlock_irqrestore(&hs->lock, flags); |
5b7d70c6 BD |
4043 | return -EINVAL; |
4044 | } | |
4045 | ||
c524dd5f MYK |
4046 | /* Dequeue already started request */ |
4047 | if (req == &hs_ep->req->req) | |
4048 | dwc2_hsotg_ep_stop_xfr(hs, hs_ep); | |
4049 | ||
1f91b4cc | 4050 | dwc2_hsotg_complete_request(hs, hs_ep, hs_req, -ECONNRESET); |
22258f49 | 4051 | spin_unlock_irqrestore(&hs->lock, flags); |
5b7d70c6 BD |
4052 | |
4053 | return 0; | |
4054 | } | |
4055 | ||
8b9bc460 | 4056 | /** |
1f91b4cc | 4057 | * dwc2_hsotg_ep_sethalt - set halt on a given endpoint |
8b9bc460 LM |
4058 | * @ep: The endpoint to set halt. |
4059 | * @value: Set or unset the halt. | |
51da43b5 VA |
4060 | * @now: If true, stall the endpoint now. Otherwise return -EAGAIN if |
4061 | * the endpoint is busy processing requests. | |
4062 | * | |
4063 | * We need to stall the endpoint immediately if request comes from set_feature | |
4064 | * protocol command handler. | |
8b9bc460 | 4065 | */ |
51da43b5 | 4066 | static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now) |
5b7d70c6 | 4067 | { |
1f91b4cc | 4068 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 4069 | struct dwc2_hsotg *hs = hs_ep->parent; |
5b7d70c6 | 4070 | int index = hs_ep->index; |
5b7d70c6 BD |
4071 | u32 epreg; |
4072 | u32 epctl; | |
9c39ddc6 | 4073 | u32 xfertype; |
5b7d70c6 BD |
4074 | |
4075 | dev_info(hs->dev, "%s(ep %p %s, %d)\n", __func__, ep, ep->name, value); | |
4076 | ||
c9f721b2 RB |
4077 | if (index == 0) { |
4078 | if (value) | |
1f91b4cc | 4079 | dwc2_hsotg_stall_ep0(hs); |
c9f721b2 RB |
4080 | else |
4081 | dev_warn(hs->dev, | |
4082 | "%s: can't clear halt on ep0\n", __func__); | |
4083 | return 0; | |
4084 | } | |
4085 | ||
15186f10 VA |
4086 | if (hs_ep->isochronous) { |
4087 | dev_err(hs->dev, "%s is Isochronous Endpoint\n", ep->name); | |
4088 | return -EINVAL; | |
4089 | } | |
4090 | ||
51da43b5 VA |
4091 | if (!now && value && !list_empty(&hs_ep->queue)) { |
4092 | dev_dbg(hs->dev, "%s request is pending, cannot halt\n", | |
4093 | ep->name); | |
4094 | return -EAGAIN; | |
4095 | } | |
4096 | ||
c6f5c050 MYK |
4097 | if (hs_ep->dir_in) { |
4098 | epreg = DIEPCTL(index); | |
95c8bc36 | 4099 | epctl = dwc2_readl(hs->regs + epreg); |
c6f5c050 MYK |
4100 | |
4101 | if (value) { | |
5a350d53 | 4102 | epctl |= DXEPCTL_STALL | DXEPCTL_SNAK; |
c6f5c050 MYK |
4103 | if (epctl & DXEPCTL_EPENA) |
4104 | epctl |= DXEPCTL_EPDIS; | |
4105 | } else { | |
4106 | epctl &= ~DXEPCTL_STALL; | |
4107 | xfertype = epctl & DXEPCTL_EPTYPE_MASK; | |
4108 | if (xfertype == DXEPCTL_EPTYPE_BULK || | |
9da51974 | 4109 | xfertype == DXEPCTL_EPTYPE_INTERRUPT) |
77b6200e | 4110 | epctl |= DXEPCTL_SETD0PID; |
c6f5c050 | 4111 | } |
95c8bc36 | 4112 | dwc2_writel(epctl, hs->regs + epreg); |
9c39ddc6 | 4113 | } else { |
c6f5c050 | 4114 | epreg = DOEPCTL(index); |
95c8bc36 | 4115 | epctl = dwc2_readl(hs->regs + epreg); |
5b7d70c6 | 4116 | |
34c0887f | 4117 | if (value) { |
c6f5c050 | 4118 | epctl |= DXEPCTL_STALL; |
34c0887f | 4119 | } else { |
c6f5c050 MYK |
4120 | epctl &= ~DXEPCTL_STALL; |
4121 | xfertype = epctl & DXEPCTL_EPTYPE_MASK; | |
4122 | if (xfertype == DXEPCTL_EPTYPE_BULK || | |
9da51974 | 4123 | xfertype == DXEPCTL_EPTYPE_INTERRUPT) |
77b6200e | 4124 | epctl |= DXEPCTL_SETD0PID; |
c6f5c050 | 4125 | } |
95c8bc36 | 4126 | dwc2_writel(epctl, hs->regs + epreg); |
9c39ddc6 | 4127 | } |
5b7d70c6 | 4128 | |
a18ed7b0 RB |
4129 | hs_ep->halted = value; |
4130 | ||
5b7d70c6 BD |
4131 | return 0; |
4132 | } | |
4133 | ||
5ad1d316 | 4134 | /** |
1f91b4cc | 4135 | * dwc2_hsotg_ep_sethalt_lock - set halt on a given endpoint with lock held |
5ad1d316 LM |
4136 | * @ep: The endpoint to set halt. |
4137 | * @value: Set or unset the halt. | |
4138 | */ | |
1f91b4cc | 4139 | static int dwc2_hsotg_ep_sethalt_lock(struct usb_ep *ep, int value) |
5ad1d316 | 4140 | { |
1f91b4cc | 4141 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 4142 | struct dwc2_hsotg *hs = hs_ep->parent; |
5ad1d316 LM |
4143 | unsigned long flags = 0; |
4144 | int ret = 0; | |
4145 | ||
4146 | spin_lock_irqsave(&hs->lock, flags); | |
51da43b5 | 4147 | ret = dwc2_hsotg_ep_sethalt(ep, value, false); |
5ad1d316 LM |
4148 | spin_unlock_irqrestore(&hs->lock, flags); |
4149 | ||
4150 | return ret; | |
4151 | } | |
4152 | ||
ebce561a | 4153 | static const struct usb_ep_ops dwc2_hsotg_ep_ops = { |
1f91b4cc FB |
4154 | .enable = dwc2_hsotg_ep_enable, |
4155 | .disable = dwc2_hsotg_ep_disable, | |
4156 | .alloc_request = dwc2_hsotg_ep_alloc_request, | |
4157 | .free_request = dwc2_hsotg_ep_free_request, | |
4158 | .queue = dwc2_hsotg_ep_queue_lock, | |
4159 | .dequeue = dwc2_hsotg_ep_dequeue, | |
4160 | .set_halt = dwc2_hsotg_ep_sethalt_lock, | |
25985edc | 4161 | /* note, don't believe we have any call for the fifo routines */ |
5b7d70c6 BD |
4162 | }; |
4163 | ||
8b9bc460 | 4164 | /** |
9da51974 | 4165 | * dwc2_hsotg_init - initialize the usb core |
8b9bc460 LM |
4166 | * @hsotg: The driver state |
4167 | */ | |
1f91b4cc | 4168 | static void dwc2_hsotg_init(struct dwc2_hsotg *hsotg) |
b3f489b2 | 4169 | { |
fa4a8d72 | 4170 | u32 trdtim; |
ecd9a7ad | 4171 | u32 usbcfg; |
b3f489b2 LM |
4172 | /* unmask subset of endpoint interrupts */ |
4173 | ||
95c8bc36 AS |
4174 | dwc2_writel(DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK | |
4175 | DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK, | |
4176 | hsotg->regs + DIEPMSK); | |
b3f489b2 | 4177 | |
95c8bc36 AS |
4178 | dwc2_writel(DOEPMSK_SETUPMSK | DOEPMSK_AHBERRMSK | |
4179 | DOEPMSK_EPDISBLDMSK | DOEPMSK_XFERCOMPLMSK, | |
4180 | hsotg->regs + DOEPMSK); | |
b3f489b2 | 4181 | |
95c8bc36 | 4182 | dwc2_writel(0, hsotg->regs + DAINTMSK); |
b3f489b2 LM |
4183 | |
4184 | /* Be in disconnected state until gadget is registered */ | |
abd064a1 | 4185 | dwc2_set_bit(hsotg->regs + DCTL, DCTL_SFTDISCON); |
b3f489b2 | 4186 | |
b3f489b2 LM |
4187 | /* setup fifos */ |
4188 | ||
4189 | dev_dbg(hsotg->dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n", | |
95c8bc36 AS |
4190 | dwc2_readl(hsotg->regs + GRXFSIZ), |
4191 | dwc2_readl(hsotg->regs + GNPTXFSIZ)); | |
b3f489b2 | 4192 | |
1f91b4cc | 4193 | dwc2_hsotg_init_fifo(hsotg); |
b3f489b2 | 4194 | |
ecd9a7ad PR |
4195 | /* keep other bits untouched (so e.g. forced modes are not lost) */ |
4196 | usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); | |
4197 | usbcfg &= ~(GUSBCFG_TOUTCAL_MASK | GUSBCFG_PHYIF16 | GUSBCFG_SRPCAP | | |
ca02954a | 4198 | GUSBCFG_HNPCAP | GUSBCFG_USBTRDTIM_MASK); |
ecd9a7ad | 4199 | |
b3f489b2 | 4200 | /* set the PLL on, remove the HNP/SRP and set the PHY */ |
fa4a8d72 | 4201 | trdtim = (hsotg->phyif == GUSBCFG_PHYIF8) ? 9 : 5; |
ecd9a7ad PR |
4202 | usbcfg |= hsotg->phyif | GUSBCFG_TOUTCAL(7) | |
4203 | (trdtim << GUSBCFG_USBTRDTIM_SHIFT); | |
4204 | dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); | |
b3f489b2 | 4205 | |
f5090044 | 4206 | if (using_dma(hsotg)) |
abd064a1 | 4207 | dwc2_set_bit(hsotg->regs + GAHBCFG, GAHBCFG_DMA_EN); |
b3f489b2 LM |
4208 | } |
4209 | ||
8b9bc460 | 4210 | /** |
1f91b4cc | 4211 | * dwc2_hsotg_udc_start - prepare the udc for work |
8b9bc460 LM |
4212 | * @gadget: The usb gadget state |
4213 | * @driver: The usb gadget driver | |
4214 | * | |
4215 | * Perform initialization to prepare udc device and driver | |
4216 | * to work. | |
4217 | */ | |
1f91b4cc | 4218 | static int dwc2_hsotg_udc_start(struct usb_gadget *gadget, |
9da51974 | 4219 | struct usb_gadget_driver *driver) |
5b7d70c6 | 4220 | { |
941fcce4 | 4221 | struct dwc2_hsotg *hsotg = to_hsotg(gadget); |
5b9451f8 | 4222 | unsigned long flags; |
5b7d70c6 BD |
4223 | int ret; |
4224 | ||
4225 | if (!hsotg) { | |
a023da33 | 4226 | pr_err("%s: called with no device\n", __func__); |
5b7d70c6 BD |
4227 | return -ENODEV; |
4228 | } | |
4229 | ||
4230 | if (!driver) { | |
4231 | dev_err(hsotg->dev, "%s: no driver\n", __func__); | |
4232 | return -EINVAL; | |
4233 | } | |
4234 | ||
7177aed4 | 4235 | if (driver->max_speed < USB_SPEED_FULL) |
5b7d70c6 | 4236 | dev_err(hsotg->dev, "%s: bad speed\n", __func__); |
5b7d70c6 | 4237 | |
f65f0f10 | 4238 | if (!driver->setup) { |
5b7d70c6 BD |
4239 | dev_err(hsotg->dev, "%s: missing entry points\n", __func__); |
4240 | return -EINVAL; | |
4241 | } | |
4242 | ||
4243 | WARN_ON(hsotg->driver); | |
4244 | ||
4245 | driver->driver.bus = NULL; | |
4246 | hsotg->driver = driver; | |
7d7b2292 | 4247 | hsotg->gadget.dev.of_node = hsotg->dev->of_node; |
5b7d70c6 BD |
4248 | hsotg->gadget.speed = USB_SPEED_UNKNOWN; |
4249 | ||
09a75e85 MS |
4250 | if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) { |
4251 | ret = dwc2_lowlevel_hw_enable(hsotg); | |
4252 | if (ret) | |
4253 | goto err; | |
5b7d70c6 BD |
4254 | } |
4255 | ||
f6c01592 GH |
4256 | if (!IS_ERR_OR_NULL(hsotg->uphy)) |
4257 | otg_set_peripheral(hsotg->uphy->otg, &hsotg->gadget); | |
c816c47f | 4258 | |
5b9451f8 | 4259 | spin_lock_irqsave(&hsotg->lock, flags); |
d0f0ac56 JY |
4260 | if (dwc2_hw_is_device(hsotg)) { |
4261 | dwc2_hsotg_init(hsotg); | |
4262 | dwc2_hsotg_core_init_disconnected(hsotg, false); | |
4263 | } | |
4264 | ||
dc6e69e6 | 4265 | hsotg->enabled = 0; |
5b9451f8 MS |
4266 | spin_unlock_irqrestore(&hsotg->lock, flags); |
4267 | ||
5b7d70c6 | 4268 | dev_info(hsotg->dev, "bound driver %s\n", driver->driver.name); |
5b9451f8 | 4269 | |
5b7d70c6 BD |
4270 | return 0; |
4271 | ||
4272 | err: | |
4273 | hsotg->driver = NULL; | |
5b7d70c6 BD |
4274 | return ret; |
4275 | } | |
4276 | ||
8b9bc460 | 4277 | /** |
1f91b4cc | 4278 | * dwc2_hsotg_udc_stop - stop the udc |
8b9bc460 LM |
4279 | * @gadget: The usb gadget state |
4280 | * @driver: The usb gadget driver | |
4281 | * | |
4282 | * Stop udc hw block and stay tunned for future transmissions | |
4283 | */ | |
1f91b4cc | 4284 | static int dwc2_hsotg_udc_stop(struct usb_gadget *gadget) |
5b7d70c6 | 4285 | { |
941fcce4 | 4286 | struct dwc2_hsotg *hsotg = to_hsotg(gadget); |
2b19a52c | 4287 | unsigned long flags = 0; |
5b7d70c6 BD |
4288 | int ep; |
4289 | ||
4290 | if (!hsotg) | |
4291 | return -ENODEV; | |
4292 | ||
5b7d70c6 | 4293 | /* all endpoints should be shutdown */ |
c6f5c050 MYK |
4294 | for (ep = 1; ep < hsotg->num_of_eps; ep++) { |
4295 | if (hsotg->eps_in[ep]) | |
1f91b4cc | 4296 | dwc2_hsotg_ep_disable(&hsotg->eps_in[ep]->ep); |
c6f5c050 | 4297 | if (hsotg->eps_out[ep]) |
1f91b4cc | 4298 | dwc2_hsotg_ep_disable(&hsotg->eps_out[ep]->ep); |
c6f5c050 | 4299 | } |
5b7d70c6 | 4300 | |
2b19a52c LM |
4301 | spin_lock_irqsave(&hsotg->lock, flags); |
4302 | ||
32805c35 | 4303 | hsotg->driver = NULL; |
5b7d70c6 | 4304 | hsotg->gadget.speed = USB_SPEED_UNKNOWN; |
dc6e69e6 | 4305 | hsotg->enabled = 0; |
5b7d70c6 | 4306 | |
2b19a52c LM |
4307 | spin_unlock_irqrestore(&hsotg->lock, flags); |
4308 | ||
f6c01592 GH |
4309 | if (!IS_ERR_OR_NULL(hsotg->uphy)) |
4310 | otg_set_peripheral(hsotg->uphy->otg, NULL); | |
c816c47f | 4311 | |
09a75e85 MS |
4312 | if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) |
4313 | dwc2_lowlevel_hw_disable(hsotg); | |
5b7d70c6 BD |
4314 | |
4315 | return 0; | |
4316 | } | |
5b7d70c6 | 4317 | |
8b9bc460 | 4318 | /** |
1f91b4cc | 4319 | * dwc2_hsotg_gadget_getframe - read the frame number |
8b9bc460 LM |
4320 | * @gadget: The usb gadget state |
4321 | * | |
4322 | * Read the {micro} frame number | |
4323 | */ | |
1f91b4cc | 4324 | static int dwc2_hsotg_gadget_getframe(struct usb_gadget *gadget) |
5b7d70c6 | 4325 | { |
1f91b4cc | 4326 | return dwc2_hsotg_read_frameno(to_hsotg(gadget)); |
5b7d70c6 BD |
4327 | } |
4328 | ||
a188b689 | 4329 | /** |
1f91b4cc | 4330 | * dwc2_hsotg_pullup - connect/disconnect the USB PHY |
a188b689 LM |
4331 | * @gadget: The usb gadget state |
4332 | * @is_on: Current state of the USB PHY | |
4333 | * | |
4334 | * Connect/Disconnect the USB PHY pullup | |
4335 | */ | |
1f91b4cc | 4336 | static int dwc2_hsotg_pullup(struct usb_gadget *gadget, int is_on) |
a188b689 | 4337 | { |
941fcce4 | 4338 | struct dwc2_hsotg *hsotg = to_hsotg(gadget); |
a188b689 LM |
4339 | unsigned long flags = 0; |
4340 | ||
77ba9119 | 4341 | dev_dbg(hsotg->dev, "%s: is_on: %d op_state: %d\n", __func__, is_on, |
9da51974 | 4342 | hsotg->op_state); |
77ba9119 GH |
4343 | |
4344 | /* Don't modify pullup state while in host mode */ | |
4345 | if (hsotg->op_state != OTG_STATE_B_PERIPHERAL) { | |
4346 | hsotg->enabled = is_on; | |
4347 | return 0; | |
4348 | } | |
a188b689 LM |
4349 | |
4350 | spin_lock_irqsave(&hsotg->lock, flags); | |
4351 | if (is_on) { | |
dc6e69e6 | 4352 | hsotg->enabled = 1; |
1f91b4cc | 4353 | dwc2_hsotg_core_init_disconnected(hsotg, false); |
66e77a24 RK |
4354 | /* Enable ACG feature in device mode,if supported */ |
4355 | dwc2_enable_acg(hsotg); | |
1f91b4cc | 4356 | dwc2_hsotg_core_connect(hsotg); |
a188b689 | 4357 | } else { |
1f91b4cc FB |
4358 | dwc2_hsotg_core_disconnect(hsotg); |
4359 | dwc2_hsotg_disconnect(hsotg); | |
dc6e69e6 | 4360 | hsotg->enabled = 0; |
a188b689 LM |
4361 | } |
4362 | ||
4363 | hsotg->gadget.speed = USB_SPEED_UNKNOWN; | |
4364 | spin_unlock_irqrestore(&hsotg->lock, flags); | |
4365 | ||
4366 | return 0; | |
4367 | } | |
4368 | ||
1f91b4cc | 4369 | static int dwc2_hsotg_vbus_session(struct usb_gadget *gadget, int is_active) |
83d98223 GH |
4370 | { |
4371 | struct dwc2_hsotg *hsotg = to_hsotg(gadget); | |
4372 | unsigned long flags; | |
4373 | ||
4374 | dev_dbg(hsotg->dev, "%s: is_active: %d\n", __func__, is_active); | |
4375 | spin_lock_irqsave(&hsotg->lock, flags); | |
4376 | ||
61f7223b | 4377 | /* |
41ba9b9b | 4378 | * If controller is hibernated, it must exit from power_down |
61f7223b GH |
4379 | * before being initialized / de-initialized |
4380 | */ | |
4381 | if (hsotg->lx_state == DWC2_L2) | |
41ba9b9b | 4382 | dwc2_exit_partial_power_down(hsotg, false); |
61f7223b | 4383 | |
83d98223 | 4384 | if (is_active) { |
cd0e641c | 4385 | hsotg->op_state = OTG_STATE_B_PERIPHERAL; |
065d3931 | 4386 | |
1f91b4cc | 4387 | dwc2_hsotg_core_init_disconnected(hsotg, false); |
66e77a24 RK |
4388 | if (hsotg->enabled) { |
4389 | /* Enable ACG feature in device mode,if supported */ | |
4390 | dwc2_enable_acg(hsotg); | |
1f91b4cc | 4391 | dwc2_hsotg_core_connect(hsotg); |
66e77a24 | 4392 | } |
83d98223 | 4393 | } else { |
1f91b4cc FB |
4394 | dwc2_hsotg_core_disconnect(hsotg); |
4395 | dwc2_hsotg_disconnect(hsotg); | |
83d98223 GH |
4396 | } |
4397 | ||
4398 | spin_unlock_irqrestore(&hsotg->lock, flags); | |
4399 | return 0; | |
4400 | } | |
4401 | ||
596d696a | 4402 | /** |
1f91b4cc | 4403 | * dwc2_hsotg_vbus_draw - report bMaxPower field |
596d696a GH |
4404 | * @gadget: The usb gadget state |
4405 | * @mA: Amount of current | |
4406 | * | |
4407 | * Report how much power the device may consume to the phy. | |
4408 | */ | |
9da51974 | 4409 | static int dwc2_hsotg_vbus_draw(struct usb_gadget *gadget, unsigned int mA) |
596d696a GH |
4410 | { |
4411 | struct dwc2_hsotg *hsotg = to_hsotg(gadget); | |
4412 | ||
4413 | if (IS_ERR_OR_NULL(hsotg->uphy)) | |
4414 | return -ENOTSUPP; | |
4415 | return usb_phy_set_power(hsotg->uphy, mA); | |
4416 | } | |
4417 | ||
1f91b4cc FB |
4418 | static const struct usb_gadget_ops dwc2_hsotg_gadget_ops = { |
4419 | .get_frame = dwc2_hsotg_gadget_getframe, | |
4420 | .udc_start = dwc2_hsotg_udc_start, | |
4421 | .udc_stop = dwc2_hsotg_udc_stop, | |
4422 | .pullup = dwc2_hsotg_pullup, | |
4423 | .vbus_session = dwc2_hsotg_vbus_session, | |
4424 | .vbus_draw = dwc2_hsotg_vbus_draw, | |
5b7d70c6 BD |
4425 | }; |
4426 | ||
4427 | /** | |
1f91b4cc | 4428 | * dwc2_hsotg_initep - initialise a single endpoint |
5b7d70c6 BD |
4429 | * @hsotg: The device state. |
4430 | * @hs_ep: The endpoint to be initialised. | |
4431 | * @epnum: The endpoint number | |
4432 | * | |
4433 | * Initialise the given endpoint (as part of the probe and device state | |
4434 | * creation) to give to the gadget driver. Setup the endpoint name, any | |
4435 | * direction information and other state that may be required. | |
4436 | */ | |
1f91b4cc | 4437 | static void dwc2_hsotg_initep(struct dwc2_hsotg *hsotg, |
9da51974 | 4438 | struct dwc2_hsotg_ep *hs_ep, |
c6f5c050 MYK |
4439 | int epnum, |
4440 | bool dir_in) | |
5b7d70c6 | 4441 | { |
5b7d70c6 BD |
4442 | char *dir; |
4443 | ||
4444 | if (epnum == 0) | |
4445 | dir = ""; | |
c6f5c050 | 4446 | else if (dir_in) |
5b7d70c6 | 4447 | dir = "in"; |
c6f5c050 MYK |
4448 | else |
4449 | dir = "out"; | |
5b7d70c6 | 4450 | |
c6f5c050 | 4451 | hs_ep->dir_in = dir_in; |
5b7d70c6 BD |
4452 | hs_ep->index = epnum; |
4453 | ||
4454 | snprintf(hs_ep->name, sizeof(hs_ep->name), "ep%d%s", epnum, dir); | |
4455 | ||
4456 | INIT_LIST_HEAD(&hs_ep->queue); | |
4457 | INIT_LIST_HEAD(&hs_ep->ep.ep_list); | |
4458 | ||
5b7d70c6 BD |
4459 | /* add to the list of endpoints known by the gadget driver */ |
4460 | if (epnum) | |
4461 | list_add_tail(&hs_ep->ep.ep_list, &hsotg->gadget.ep_list); | |
4462 | ||
4463 | hs_ep->parent = hsotg; | |
4464 | hs_ep->ep.name = hs_ep->name; | |
38e9002b VM |
4465 | |
4466 | if (hsotg->params.speed == DWC2_SPEED_PARAM_LOW) | |
4467 | usb_ep_set_maxpacket_limit(&hs_ep->ep, 8); | |
4468 | else | |
4469 | usb_ep_set_maxpacket_limit(&hs_ep->ep, | |
4470 | epnum ? 1024 : EP0_MPS_LIMIT); | |
1f91b4cc | 4471 | hs_ep->ep.ops = &dwc2_hsotg_ep_ops; |
5b7d70c6 | 4472 | |
2954522f RB |
4473 | if (epnum == 0) { |
4474 | hs_ep->ep.caps.type_control = true; | |
4475 | } else { | |
38e9002b VM |
4476 | if (hsotg->params.speed != DWC2_SPEED_PARAM_LOW) { |
4477 | hs_ep->ep.caps.type_iso = true; | |
4478 | hs_ep->ep.caps.type_bulk = true; | |
4479 | } | |
2954522f RB |
4480 | hs_ep->ep.caps.type_int = true; |
4481 | } | |
4482 | ||
4483 | if (dir_in) | |
4484 | hs_ep->ep.caps.dir_in = true; | |
4485 | else | |
4486 | hs_ep->ep.caps.dir_out = true; | |
4487 | ||
8b9bc460 LM |
4488 | /* |
4489 | * if we're using dma, we need to set the next-endpoint pointer | |
5b7d70c6 BD |
4490 | * to be something valid. |
4491 | */ | |
4492 | ||
4493 | if (using_dma(hsotg)) { | |
47a1685f | 4494 | u32 next = DXEPCTL_NEXTEP((epnum + 1) % 15); |
9da51974 | 4495 | |
c6f5c050 | 4496 | if (dir_in) |
95c8bc36 | 4497 | dwc2_writel(next, hsotg->regs + DIEPCTL(epnum)); |
c6f5c050 | 4498 | else |
95c8bc36 | 4499 | dwc2_writel(next, hsotg->regs + DOEPCTL(epnum)); |
5b7d70c6 BD |
4500 | } |
4501 | } | |
4502 | ||
b3f489b2 | 4503 | /** |
1f91b4cc | 4504 | * dwc2_hsotg_hw_cfg - read HW configuration registers |
b3f489b2 LM |
4505 | * @param: The device state |
4506 | * | |
4507 | * Read the USB core HW configuration registers | |
4508 | */ | |
1f91b4cc | 4509 | static int dwc2_hsotg_hw_cfg(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 4510 | { |
c6f5c050 MYK |
4511 | u32 cfg; |
4512 | u32 ep_type; | |
4513 | u32 i; | |
4514 | ||
b3f489b2 | 4515 | /* check hardware configuration */ |
5b7d70c6 | 4516 | |
43e90349 JY |
4517 | hsotg->num_of_eps = hsotg->hw_params.num_dev_ep; |
4518 | ||
c6f5c050 MYK |
4519 | /* Add ep0 */ |
4520 | hsotg->num_of_eps++; | |
10aebc77 | 4521 | |
b98866c2 JY |
4522 | hsotg->eps_in[0] = devm_kzalloc(hsotg->dev, |
4523 | sizeof(struct dwc2_hsotg_ep), | |
4524 | GFP_KERNEL); | |
c6f5c050 MYK |
4525 | if (!hsotg->eps_in[0]) |
4526 | return -ENOMEM; | |
1f91b4cc | 4527 | /* Same dwc2_hsotg_ep is used in both directions for ep0 */ |
c6f5c050 MYK |
4528 | hsotg->eps_out[0] = hsotg->eps_in[0]; |
4529 | ||
43e90349 | 4530 | cfg = hsotg->hw_params.dev_ep_dirs; |
251a17f5 | 4531 | for (i = 1, cfg >>= 2; i < hsotg->num_of_eps; i++, cfg >>= 2) { |
c6f5c050 MYK |
4532 | ep_type = cfg & 3; |
4533 | /* Direction in or both */ | |
4534 | if (!(ep_type & 2)) { | |
4535 | hsotg->eps_in[i] = devm_kzalloc(hsotg->dev, | |
1f91b4cc | 4536 | sizeof(struct dwc2_hsotg_ep), GFP_KERNEL); |
c6f5c050 MYK |
4537 | if (!hsotg->eps_in[i]) |
4538 | return -ENOMEM; | |
4539 | } | |
4540 | /* Direction out or both */ | |
4541 | if (!(ep_type & 1)) { | |
4542 | hsotg->eps_out[i] = devm_kzalloc(hsotg->dev, | |
1f91b4cc | 4543 | sizeof(struct dwc2_hsotg_ep), GFP_KERNEL); |
c6f5c050 MYK |
4544 | if (!hsotg->eps_out[i]) |
4545 | return -ENOMEM; | |
4546 | } | |
4547 | } | |
4548 | ||
43e90349 JY |
4549 | hsotg->fifo_mem = hsotg->hw_params.total_fifo_size; |
4550 | hsotg->dedicated_fifos = hsotg->hw_params.en_multiple_tx_fifo; | |
10aebc77 | 4551 | |
cff9eb75 MS |
4552 | dev_info(hsotg->dev, "EPs: %d, %s fifos, %d entries in SPRAM\n", |
4553 | hsotg->num_of_eps, | |
4554 | hsotg->dedicated_fifos ? "dedicated" : "shared", | |
4555 | hsotg->fifo_mem); | |
c6f5c050 | 4556 | return 0; |
5b7d70c6 BD |
4557 | } |
4558 | ||
8b9bc460 | 4559 | /** |
1f91b4cc | 4560 | * dwc2_hsotg_dump - dump state of the udc |
8b9bc460 LM |
4561 | * @param: The device state |
4562 | */ | |
1f91b4cc | 4563 | static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 4564 | { |
83a01804 | 4565 | #ifdef DEBUG |
5b7d70c6 BD |
4566 | struct device *dev = hsotg->dev; |
4567 | void __iomem *regs = hsotg->regs; | |
4568 | u32 val; | |
4569 | int idx; | |
4570 | ||
4571 | dev_info(dev, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n", | |
95c8bc36 AS |
4572 | dwc2_readl(regs + DCFG), dwc2_readl(regs + DCTL), |
4573 | dwc2_readl(regs + DIEPMSK)); | |
5b7d70c6 | 4574 | |
f889f23d | 4575 | dev_info(dev, "GAHBCFG=0x%08x, GHWCFG1=0x%08x\n", |
95c8bc36 | 4576 | dwc2_readl(regs + GAHBCFG), dwc2_readl(regs + GHWCFG1)); |
5b7d70c6 BD |
4577 | |
4578 | dev_info(dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n", | |
95c8bc36 | 4579 | dwc2_readl(regs + GRXFSIZ), dwc2_readl(regs + GNPTXFSIZ)); |
5b7d70c6 BD |
4580 | |
4581 | /* show periodic fifo settings */ | |
4582 | ||
364f8e93 | 4583 | for (idx = 1; idx < hsotg->num_of_eps; idx++) { |
95c8bc36 | 4584 | val = dwc2_readl(regs + DPTXFSIZN(idx)); |
5b7d70c6 | 4585 | dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx, |
47a1685f DN |
4586 | val >> FIFOSIZE_DEPTH_SHIFT, |
4587 | val & FIFOSIZE_STARTADDR_MASK); | |
5b7d70c6 BD |
4588 | } |
4589 | ||
364f8e93 | 4590 | for (idx = 0; idx < hsotg->num_of_eps; idx++) { |
5b7d70c6 BD |
4591 | dev_info(dev, |
4592 | "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx, | |
95c8bc36 AS |
4593 | dwc2_readl(regs + DIEPCTL(idx)), |
4594 | dwc2_readl(regs + DIEPTSIZ(idx)), | |
4595 | dwc2_readl(regs + DIEPDMA(idx))); | |
5b7d70c6 | 4596 | |
95c8bc36 | 4597 | val = dwc2_readl(regs + DOEPCTL(idx)); |
5b7d70c6 BD |
4598 | dev_info(dev, |
4599 | "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", | |
95c8bc36 AS |
4600 | idx, dwc2_readl(regs + DOEPCTL(idx)), |
4601 | dwc2_readl(regs + DOEPTSIZ(idx)), | |
4602 | dwc2_readl(regs + DOEPDMA(idx))); | |
5b7d70c6 BD |
4603 | } |
4604 | ||
4605 | dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n", | |
95c8bc36 | 4606 | dwc2_readl(regs + DVBUSDIS), dwc2_readl(regs + DVBUSPULSE)); |
83a01804 | 4607 | #endif |
5b7d70c6 BD |
4608 | } |
4609 | ||
8b9bc460 | 4610 | /** |
117777b2 DN |
4611 | * dwc2_gadget_init - init function for gadget |
4612 | * @dwc2: The data structure for the DWC2 driver. | |
8b9bc460 | 4613 | */ |
f3768997 | 4614 | int dwc2_gadget_init(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 4615 | { |
117777b2 | 4616 | struct device *dev = hsotg->dev; |
5b7d70c6 BD |
4617 | int epnum; |
4618 | int ret; | |
43e90349 | 4619 | |
0a176279 GH |
4620 | /* Dump fifo information */ |
4621 | dev_dbg(dev, "NonPeriodic TXFIFO size: %d\n", | |
05ee799f JY |
4622 | hsotg->params.g_np_tx_fifo_size); |
4623 | dev_dbg(dev, "RXFIFO size: %d\n", hsotg->params.g_rx_fifo_size); | |
5b7d70c6 | 4624 | |
d327ab5b | 4625 | hsotg->gadget.max_speed = USB_SPEED_HIGH; |
1f91b4cc | 4626 | hsotg->gadget.ops = &dwc2_hsotg_gadget_ops; |
5b7d70c6 | 4627 | hsotg->gadget.name = dev_name(dev); |
fa389a6d | 4628 | hsotg->remote_wakeup_allowed = 0; |
7455f8b7 JY |
4629 | |
4630 | if (hsotg->params.lpm) | |
4631 | hsotg->gadget.lpm_capable = true; | |
4632 | ||
097ee662 GH |
4633 | if (hsotg->dr_mode == USB_DR_MODE_OTG) |
4634 | hsotg->gadget.is_otg = 1; | |
ec4cc657 MYK |
4635 | else if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) |
4636 | hsotg->op_state = OTG_STATE_B_PERIPHERAL; | |
5b7d70c6 | 4637 | |
1f91b4cc | 4638 | ret = dwc2_hsotg_hw_cfg(hsotg); |
c6f5c050 MYK |
4639 | if (ret) { |
4640 | dev_err(hsotg->dev, "Hardware configuration failed: %d\n", ret); | |
09a75e85 | 4641 | return ret; |
c6f5c050 MYK |
4642 | } |
4643 | ||
3f95001d MYK |
4644 | hsotg->ctrl_buff = devm_kzalloc(hsotg->dev, |
4645 | DWC2_CTRL_BUFF_SIZE, GFP_KERNEL); | |
8bae0f8c | 4646 | if (!hsotg->ctrl_buff) |
09a75e85 | 4647 | return -ENOMEM; |
3f95001d MYK |
4648 | |
4649 | hsotg->ep0_buff = devm_kzalloc(hsotg->dev, | |
4650 | DWC2_CTRL_BUFF_SIZE, GFP_KERNEL); | |
8bae0f8c | 4651 | if (!hsotg->ep0_buff) |
09a75e85 | 4652 | return -ENOMEM; |
3f95001d | 4653 | |
0f6b80c0 VA |
4654 | if (using_desc_dma(hsotg)) { |
4655 | ret = dwc2_gadget_alloc_ctrl_desc_chains(hsotg); | |
4656 | if (ret < 0) | |
4657 | return ret; | |
4658 | } | |
4659 | ||
f3768997 VM |
4660 | ret = devm_request_irq(hsotg->dev, hsotg->irq, dwc2_hsotg_irq, |
4661 | IRQF_SHARED, dev_name(hsotg->dev), hsotg); | |
eb3c56c5 | 4662 | if (ret < 0) { |
db8178c3 | 4663 | dev_err(dev, "cannot claim IRQ for gadget\n"); |
09a75e85 | 4664 | return ret; |
eb3c56c5 MS |
4665 | } |
4666 | ||
b3f489b2 LM |
4667 | /* hsotg->num_of_eps holds number of EPs other than ep0 */ |
4668 | ||
4669 | if (hsotg->num_of_eps == 0) { | |
4670 | dev_err(dev, "wrong number of EPs (zero)\n"); | |
09a75e85 | 4671 | return -EINVAL; |
b3f489b2 LM |
4672 | } |
4673 | ||
b3f489b2 LM |
4674 | /* setup endpoint information */ |
4675 | ||
4676 | INIT_LIST_HEAD(&hsotg->gadget.ep_list); | |
c6f5c050 | 4677 | hsotg->gadget.ep0 = &hsotg->eps_out[0]->ep; |
b3f489b2 LM |
4678 | |
4679 | /* allocate EP0 request */ | |
4680 | ||
1f91b4cc | 4681 | hsotg->ctrl_req = dwc2_hsotg_ep_alloc_request(&hsotg->eps_out[0]->ep, |
b3f489b2 LM |
4682 | GFP_KERNEL); |
4683 | if (!hsotg->ctrl_req) { | |
4684 | dev_err(dev, "failed to allocate ctrl req\n"); | |
09a75e85 | 4685 | return -ENOMEM; |
b3f489b2 | 4686 | } |
5b7d70c6 BD |
4687 | |
4688 | /* initialise the endpoints now the core has been initialised */ | |
c6f5c050 MYK |
4689 | for (epnum = 0; epnum < hsotg->num_of_eps; epnum++) { |
4690 | if (hsotg->eps_in[epnum]) | |
1f91b4cc | 4691 | dwc2_hsotg_initep(hsotg, hsotg->eps_in[epnum], |
9da51974 | 4692 | epnum, 1); |
c6f5c050 | 4693 | if (hsotg->eps_out[epnum]) |
1f91b4cc | 4694 | dwc2_hsotg_initep(hsotg, hsotg->eps_out[epnum], |
9da51974 | 4695 | epnum, 0); |
c6f5c050 | 4696 | } |
5b7d70c6 | 4697 | |
117777b2 | 4698 | ret = usb_add_gadget_udc(dev, &hsotg->gadget); |
0f91349b | 4699 | if (ret) |
09a75e85 | 4700 | return ret; |
0f91349b | 4701 | |
1f91b4cc | 4702 | dwc2_hsotg_dump(hsotg); |
5b7d70c6 | 4703 | |
5b7d70c6 | 4704 | return 0; |
5b7d70c6 BD |
4705 | } |
4706 | ||
8b9bc460 | 4707 | /** |
1f91b4cc | 4708 | * dwc2_hsotg_remove - remove function for hsotg driver |
8b9bc460 LM |
4709 | * @pdev: The platform information for the driver |
4710 | */ | |
1f91b4cc | 4711 | int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 4712 | { |
0f91349b | 4713 | usb_del_gadget_udc(&hsotg->gadget); |
31ee04de | 4714 | |
5b7d70c6 BD |
4715 | return 0; |
4716 | } | |
4717 | ||
1f91b4cc | 4718 | int dwc2_hsotg_suspend(struct dwc2_hsotg *hsotg) |
b83e333a | 4719 | { |
b83e333a | 4720 | unsigned long flags; |
b83e333a | 4721 | |
9e779778 | 4722 | if (hsotg->lx_state != DWC2_L0) |
09a75e85 | 4723 | return 0; |
9e779778 | 4724 | |
dc6e69e6 MS |
4725 | if (hsotg->driver) { |
4726 | int ep; | |
4727 | ||
b83e333a MS |
4728 | dev_info(hsotg->dev, "suspending usb gadget %s\n", |
4729 | hsotg->driver->driver.name); | |
4730 | ||
dc6e69e6 MS |
4731 | spin_lock_irqsave(&hsotg->lock, flags); |
4732 | if (hsotg->enabled) | |
1f91b4cc FB |
4733 | dwc2_hsotg_core_disconnect(hsotg); |
4734 | dwc2_hsotg_disconnect(hsotg); | |
dc6e69e6 MS |
4735 | hsotg->gadget.speed = USB_SPEED_UNKNOWN; |
4736 | spin_unlock_irqrestore(&hsotg->lock, flags); | |
b83e333a | 4737 | |
c6f5c050 MYK |
4738 | for (ep = 0; ep < hsotg->num_of_eps; ep++) { |
4739 | if (hsotg->eps_in[ep]) | |
1f91b4cc | 4740 | dwc2_hsotg_ep_disable(&hsotg->eps_in[ep]->ep); |
c6f5c050 | 4741 | if (hsotg->eps_out[ep]) |
1f91b4cc | 4742 | dwc2_hsotg_ep_disable(&hsotg->eps_out[ep]->ep); |
c6f5c050 | 4743 | } |
b83e333a MS |
4744 | } |
4745 | ||
09a75e85 | 4746 | return 0; |
b83e333a MS |
4747 | } |
4748 | ||
1f91b4cc | 4749 | int dwc2_hsotg_resume(struct dwc2_hsotg *hsotg) |
b83e333a | 4750 | { |
b83e333a | 4751 | unsigned long flags; |
b83e333a | 4752 | |
9e779778 | 4753 | if (hsotg->lx_state == DWC2_L2) |
09a75e85 | 4754 | return 0; |
9e779778 | 4755 | |
b83e333a MS |
4756 | if (hsotg->driver) { |
4757 | dev_info(hsotg->dev, "resuming usb gadget %s\n", | |
4758 | hsotg->driver->driver.name); | |
d00b4142 | 4759 | |
dc6e69e6 | 4760 | spin_lock_irqsave(&hsotg->lock, flags); |
1f91b4cc | 4761 | dwc2_hsotg_core_init_disconnected(hsotg, false); |
66e77a24 RK |
4762 | if (hsotg->enabled) { |
4763 | /* Enable ACG feature in device mode,if supported */ | |
4764 | dwc2_enable_acg(hsotg); | |
1f91b4cc | 4765 | dwc2_hsotg_core_connect(hsotg); |
66e77a24 | 4766 | } |
dc6e69e6 MS |
4767 | spin_unlock_irqrestore(&hsotg->lock, flags); |
4768 | } | |
b83e333a | 4769 | |
09a75e85 | 4770 | return 0; |
b83e333a | 4771 | } |
58e52ff6 JY |
4772 | |
4773 | /** | |
4774 | * dwc2_backup_device_registers() - Backup controller device registers. | |
4775 | * When suspending usb bus, registers needs to be backuped | |
4776 | * if controller power is disabled once suspended. | |
4777 | * | |
4778 | * @hsotg: Programming view of the DWC_otg controller | |
4779 | */ | |
4780 | int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg) | |
4781 | { | |
4782 | struct dwc2_dregs_backup *dr; | |
4783 | int i; | |
4784 | ||
4785 | dev_dbg(hsotg->dev, "%s\n", __func__); | |
4786 | ||
4787 | /* Backup dev regs */ | |
4788 | dr = &hsotg->dr_backup; | |
4789 | ||
4790 | dr->dcfg = dwc2_readl(hsotg->regs + DCFG); | |
4791 | dr->dctl = dwc2_readl(hsotg->regs + DCTL); | |
4792 | dr->daintmsk = dwc2_readl(hsotg->regs + DAINTMSK); | |
4793 | dr->diepmsk = dwc2_readl(hsotg->regs + DIEPMSK); | |
4794 | dr->doepmsk = dwc2_readl(hsotg->regs + DOEPMSK); | |
4795 | ||
4796 | for (i = 0; i < hsotg->num_of_eps; i++) { | |
4797 | /* Backup IN EPs */ | |
4798 | dr->diepctl[i] = dwc2_readl(hsotg->regs + DIEPCTL(i)); | |
4799 | ||
4800 | /* Ensure DATA PID is correctly configured */ | |
4801 | if (dr->diepctl[i] & DXEPCTL_DPID) | |
4802 | dr->diepctl[i] |= DXEPCTL_SETD1PID; | |
4803 | else | |
4804 | dr->diepctl[i] |= DXEPCTL_SETD0PID; | |
4805 | ||
4806 | dr->dieptsiz[i] = dwc2_readl(hsotg->regs + DIEPTSIZ(i)); | |
4807 | dr->diepdma[i] = dwc2_readl(hsotg->regs + DIEPDMA(i)); | |
4808 | ||
4809 | /* Backup OUT EPs */ | |
4810 | dr->doepctl[i] = dwc2_readl(hsotg->regs + DOEPCTL(i)); | |
4811 | ||
4812 | /* Ensure DATA PID is correctly configured */ | |
4813 | if (dr->doepctl[i] & DXEPCTL_DPID) | |
4814 | dr->doepctl[i] |= DXEPCTL_SETD1PID; | |
4815 | else | |
4816 | dr->doepctl[i] |= DXEPCTL_SETD0PID; | |
4817 | ||
4818 | dr->doeptsiz[i] = dwc2_readl(hsotg->regs + DOEPTSIZ(i)); | |
4819 | dr->doepdma[i] = dwc2_readl(hsotg->regs + DOEPDMA(i)); | |
af7c2bd3 | 4820 | dr->dtxfsiz[i] = dwc2_readl(hsotg->regs + DPTXFSIZN(i)); |
58e52ff6 JY |
4821 | } |
4822 | dr->valid = true; | |
4823 | return 0; | |
4824 | } | |
4825 | ||
4826 | /** | |
4827 | * dwc2_restore_device_registers() - Restore controller device registers. | |
4828 | * When resuming usb bus, device registers needs to be restored | |
4829 | * if controller power were disabled. | |
4830 | * | |
4831 | * @hsotg: Programming view of the DWC_otg controller | |
9a5d2816 VM |
4832 | * @remote_wakeup: Indicates whether resume is initiated by Device or Host. |
4833 | * | |
4834 | * Return: 0 if successful, negative error code otherwise | |
58e52ff6 | 4835 | */ |
9a5d2816 | 4836 | int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg, int remote_wakeup) |
58e52ff6 JY |
4837 | { |
4838 | struct dwc2_dregs_backup *dr; | |
58e52ff6 JY |
4839 | int i; |
4840 | ||
4841 | dev_dbg(hsotg->dev, "%s\n", __func__); | |
4842 | ||
4843 | /* Restore dev regs */ | |
4844 | dr = &hsotg->dr_backup; | |
4845 | if (!dr->valid) { | |
4846 | dev_err(hsotg->dev, "%s: no device registers to restore\n", | |
4847 | __func__); | |
4848 | return -EINVAL; | |
4849 | } | |
4850 | dr->valid = false; | |
4851 | ||
9a5d2816 VM |
4852 | if (!remote_wakeup) |
4853 | dwc2_writel(dr->dctl, hsotg->regs + DCTL); | |
4854 | ||
58e52ff6 JY |
4855 | dwc2_writel(dr->daintmsk, hsotg->regs + DAINTMSK); |
4856 | dwc2_writel(dr->diepmsk, hsotg->regs + DIEPMSK); | |
4857 | dwc2_writel(dr->doepmsk, hsotg->regs + DOEPMSK); | |
4858 | ||
4859 | for (i = 0; i < hsotg->num_of_eps; i++) { | |
4860 | /* Restore IN EPs */ | |
58e52ff6 JY |
4861 | dwc2_writel(dr->dieptsiz[i], hsotg->regs + DIEPTSIZ(i)); |
4862 | dwc2_writel(dr->diepdma[i], hsotg->regs + DIEPDMA(i)); | |
9a5d2816 VM |
4863 | dwc2_writel(dr->doeptsiz[i], hsotg->regs + DOEPTSIZ(i)); |
4864 | /** WA for enabled EPx's IN in DDMA mode. On entering to | |
4865 | * hibernation wrong value read and saved from DIEPDMAx, | |
4866 | * as result BNA interrupt asserted on hibernation exit | |
4867 | * by restoring from saved area. | |
4868 | */ | |
4869 | if (hsotg->params.g_dma_desc && | |
4870 | (dr->diepctl[i] & DXEPCTL_EPENA)) | |
4871 | dr->diepdma[i] = hsotg->eps_in[i]->desc_list_dma; | |
af7c2bd3 | 4872 | dwc2_writel(dr->dtxfsiz[i], hsotg->regs + DPTXFSIZN(i)); |
9a5d2816 | 4873 | dwc2_writel(dr->diepctl[i], hsotg->regs + DIEPCTL(i)); |
58e52ff6 | 4874 | /* Restore OUT EPs */ |
58e52ff6 | 4875 | dwc2_writel(dr->doeptsiz[i], hsotg->regs + DOEPTSIZ(i)); |
9a5d2816 VM |
4876 | /* WA for enabled EPx's OUT in DDMA mode. On entering to |
4877 | * hibernation wrong value read and saved from DOEPDMAx, | |
4878 | * as result BNA interrupt asserted on hibernation exit | |
4879 | * by restoring from saved area. | |
4880 | */ | |
4881 | if (hsotg->params.g_dma_desc && | |
4882 | (dr->doepctl[i] & DXEPCTL_EPENA)) | |
4883 | dr->doepdma[i] = hsotg->eps_out[i]->desc_list_dma; | |
58e52ff6 | 4884 | dwc2_writel(dr->doepdma[i], hsotg->regs + DOEPDMA(i)); |
9a5d2816 | 4885 | dwc2_writel(dr->doepctl[i], hsotg->regs + DOEPCTL(i)); |
58e52ff6 JY |
4886 | } |
4887 | ||
58e52ff6 JY |
4888 | return 0; |
4889 | } | |
21b03405 SA |
4890 | |
4891 | /** | |
4892 | * dwc2_gadget_init_lpm - Configure the core to support LPM in device mode | |
4893 | * | |
4894 | * @hsotg: Programming view of DWC_otg controller | |
4895 | * | |
4896 | */ | |
4897 | void dwc2_gadget_init_lpm(struct dwc2_hsotg *hsotg) | |
4898 | { | |
4899 | u32 val; | |
4900 | ||
4901 | if (!hsotg->params.lpm) | |
4902 | return; | |
4903 | ||
4904 | val = GLPMCFG_LPMCAP | GLPMCFG_APPL1RES; | |
4905 | val |= hsotg->params.hird_threshold_en ? GLPMCFG_HIRD_THRES_EN : 0; | |
4906 | val |= hsotg->params.lpm_clock_gating ? GLPMCFG_ENBLSLPM : 0; | |
4907 | val |= hsotg->params.hird_threshold << GLPMCFG_HIRD_THRES_SHIFT; | |
4908 | val |= hsotg->params.besl ? GLPMCFG_ENBESL : 0; | |
4909 | dwc2_writel(val, hsotg->regs + GLPMCFG); | |
4910 | dev_dbg(hsotg->dev, "GLPMCFG=0x%08x\n", dwc2_readl(hsotg->regs | |
4911 | + GLPMCFG)); | |
4912 | } | |
c5c403dc VM |
4913 | |
4914 | /** | |
4915 | * dwc2_gadget_enter_hibernation() - Put controller in Hibernation. | |
4916 | * | |
4917 | * @hsotg: Programming view of the DWC_otg controller | |
4918 | * | |
4919 | * Return non-zero if failed to enter to hibernation. | |
4920 | */ | |
4921 | int dwc2_gadget_enter_hibernation(struct dwc2_hsotg *hsotg) | |
4922 | { | |
4923 | u32 gpwrdn; | |
4924 | int ret = 0; | |
4925 | ||
4926 | /* Change to L2(suspend) state */ | |
4927 | hsotg->lx_state = DWC2_L2; | |
4928 | dev_dbg(hsotg->dev, "Start of hibernation completed\n"); | |
4929 | ret = dwc2_backup_global_registers(hsotg); | |
4930 | if (ret) { | |
4931 | dev_err(hsotg->dev, "%s: failed to backup global registers\n", | |
4932 | __func__); | |
4933 | return ret; | |
4934 | } | |
4935 | ret = dwc2_backup_device_registers(hsotg); | |
4936 | if (ret) { | |
4937 | dev_err(hsotg->dev, "%s: failed to backup device registers\n", | |
4938 | __func__); | |
4939 | return ret; | |
4940 | } | |
4941 | ||
4942 | gpwrdn = GPWRDN_PWRDNRSTN; | |
4943 | gpwrdn |= GPWRDN_PMUACTV; | |
4944 | dwc2_writel(gpwrdn, hsotg->regs + GPWRDN); | |
4945 | udelay(10); | |
4946 | ||
4947 | /* Set flag to indicate that we are in hibernation */ | |
4948 | hsotg->hibernated = 1; | |
4949 | ||
4950 | /* Enable interrupts from wake up logic */ | |
4951 | gpwrdn = dwc2_readl(hsotg->regs + GPWRDN); | |
4952 | gpwrdn |= GPWRDN_PMUINTSEL; | |
4953 | dwc2_writel(gpwrdn, hsotg->regs + GPWRDN); | |
4954 | udelay(10); | |
4955 | ||
4956 | /* Unmask device mode interrupts in GPWRDN */ | |
4957 | gpwrdn = dwc2_readl(hsotg->regs + GPWRDN); | |
4958 | gpwrdn |= GPWRDN_RST_DET_MSK; | |
4959 | gpwrdn |= GPWRDN_LNSTSCHG_MSK; | |
4960 | gpwrdn |= GPWRDN_STS_CHGINT_MSK; | |
4961 | dwc2_writel(gpwrdn, hsotg->regs + GPWRDN); | |
4962 | udelay(10); | |
4963 | ||
4964 | /* Enable Power Down Clamp */ | |
4965 | gpwrdn = dwc2_readl(hsotg->regs + GPWRDN); | |
4966 | gpwrdn |= GPWRDN_PWRDNCLMP; | |
4967 | dwc2_writel(gpwrdn, hsotg->regs + GPWRDN); | |
4968 | udelay(10); | |
4969 | ||
4970 | /* Switch off VDD */ | |
4971 | gpwrdn = dwc2_readl(hsotg->regs + GPWRDN); | |
4972 | gpwrdn |= GPWRDN_PWRDNSWTCH; | |
4973 | dwc2_writel(gpwrdn, hsotg->regs + GPWRDN); | |
4974 | udelay(10); | |
4975 | ||
4976 | /* Save gpwrdn register for further usage if stschng interrupt */ | |
4977 | hsotg->gr_backup.gpwrdn = dwc2_readl(hsotg->regs + GPWRDN); | |
4978 | dev_dbg(hsotg->dev, "Hibernation completed\n"); | |
4979 | ||
4980 | return ret; | |
4981 | } | |
4982 | ||
4983 | /** | |
4984 | * dwc2_gadget_exit_hibernation() | |
4985 | * This function is for exiting from Device mode hibernation by host initiated | |
4986 | * resume/reset and device initiated remote-wakeup. | |
4987 | * | |
4988 | * @hsotg: Programming view of the DWC_otg controller | |
4989 | * @rem_wakeup: indicates whether resume is initiated by Device or Host. | |
4990 | * @param reset: indicates whether resume is initiated by Reset. | |
4991 | * | |
4992 | * Return non-zero if failed to exit from hibernation. | |
4993 | */ | |
4994 | int dwc2_gadget_exit_hibernation(struct dwc2_hsotg *hsotg, | |
4995 | int rem_wakeup, int reset) | |
4996 | { | |
4997 | u32 pcgcctl; | |
4998 | u32 gpwrdn; | |
4999 | u32 dctl; | |
5000 | int ret = 0; | |
5001 | struct dwc2_gregs_backup *gr; | |
5002 | struct dwc2_dregs_backup *dr; | |
5003 | ||
5004 | gr = &hsotg->gr_backup; | |
5005 | dr = &hsotg->dr_backup; | |
5006 | ||
5007 | if (!hsotg->hibernated) { | |
5008 | dev_dbg(hsotg->dev, "Already exited from Hibernation\n"); | |
5009 | return 1; | |
5010 | } | |
5011 | dev_dbg(hsotg->dev, | |
5012 | "%s: called with rem_wakeup = %d reset = %d\n", | |
5013 | __func__, rem_wakeup, reset); | |
5014 | ||
5015 | dwc2_hib_restore_common(hsotg, rem_wakeup, 0); | |
5016 | ||
5017 | if (!reset) { | |
5018 | /* Clear all pending interupts */ | |
5019 | dwc2_writel(0xffffffff, hsotg->regs + GINTSTS); | |
5020 | } | |
5021 | ||
5022 | /* De-assert Restore */ | |
5023 | gpwrdn = dwc2_readl(hsotg->regs + GPWRDN); | |
5024 | gpwrdn &= ~GPWRDN_RESTORE; | |
5025 | dwc2_writel(gpwrdn, hsotg->regs + GPWRDN); | |
5026 | udelay(10); | |
5027 | ||
5028 | if (!rem_wakeup) { | |
5029 | pcgcctl = dwc2_readl(hsotg->regs + PCGCTL); | |
5030 | pcgcctl &= ~PCGCTL_RSTPDWNMODULE; | |
5031 | dwc2_writel(pcgcctl, hsotg->regs + PCGCTL); | |
5032 | } | |
5033 | ||
5034 | /* Restore GUSBCFG, DCFG and DCTL */ | |
5035 | dwc2_writel(gr->gusbcfg, hsotg->regs + GUSBCFG); | |
5036 | dwc2_writel(dr->dcfg, hsotg->regs + DCFG); | |
5037 | dwc2_writel(dr->dctl, hsotg->regs + DCTL); | |
5038 | ||
5039 | /* De-assert Wakeup Logic */ | |
5040 | gpwrdn = dwc2_readl(hsotg->regs + GPWRDN); | |
5041 | gpwrdn &= ~GPWRDN_PMUACTV; | |
5042 | dwc2_writel(gpwrdn, hsotg->regs + GPWRDN); | |
5043 | ||
5044 | if (rem_wakeup) { | |
5045 | udelay(10); | |
5046 | /* Start Remote Wakeup Signaling */ | |
5047 | dwc2_writel(dr->dctl | DCTL_RMTWKUPSIG, hsotg->regs + DCTL); | |
5048 | } else { | |
5049 | udelay(50); | |
5050 | /* Set Device programming done bit */ | |
5051 | dctl = dwc2_readl(hsotg->regs + DCTL); | |
5052 | dctl |= DCTL_PWRONPRGDONE; | |
5053 | dwc2_writel(dctl, hsotg->regs + DCTL); | |
5054 | } | |
5055 | /* Wait for interrupts which must be cleared */ | |
5056 | mdelay(2); | |
5057 | /* Clear all pending interupts */ | |
5058 | dwc2_writel(0xffffffff, hsotg->regs + GINTSTS); | |
5059 | ||
5060 | /* Restore global registers */ | |
5061 | ret = dwc2_restore_global_registers(hsotg); | |
5062 | if (ret) { | |
5063 | dev_err(hsotg->dev, "%s: failed to restore registers\n", | |
5064 | __func__); | |
5065 | return ret; | |
5066 | } | |
5067 | ||
5068 | /* Restore device registers */ | |
5069 | ret = dwc2_restore_device_registers(hsotg, rem_wakeup); | |
5070 | if (ret) { | |
5071 | dev_err(hsotg->dev, "%s: failed to restore device registers\n", | |
5072 | __func__); | |
5073 | return ret; | |
5074 | } | |
5075 | ||
5076 | if (rem_wakeup) { | |
5077 | mdelay(10); | |
5078 | dctl = dwc2_readl(hsotg->regs + DCTL); | |
5079 | dctl &= ~DCTL_RMTWKUPSIG; | |
5080 | dwc2_writel(dctl, hsotg->regs + DCTL); | |
5081 | } | |
5082 | ||
5083 | hsotg->hibernated = 0; | |
5084 | hsotg->lx_state = DWC2_L0; | |
5085 | dev_dbg(hsotg->dev, "Hibernation recovery completes here\n"); | |
5086 | ||
5087 | return ret; | |
5088 | } |