projects / linux-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
usb: dwc2: gadget: Corrected interval calculation
[linux-block.git] / drivers / usb / dwc2 / gadget.c
CommitLineData
8b9bc460 1/**
dfbc6fa3
AT		 2 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
5b7d70c6
BD		 4 *
5 * Copyright 2008 Openmoko, Inc.
6 * Copyright 2008 Simtec Electronics
7 * Ben Dooks <ben@simtec.co.uk>
8 * http://armlinux.simtec.co.uk/
9 *
10 * S3C USB2.0 High-speed / OtG driver
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
8b9bc460 15 */
5b7d70c6
BD		 16
17#include <linux/kernel.h>
18#include <linux/module.h>
19#include <linux/spinlock.h>
20#include <linux/interrupt.h>
21#include <linux/platform_device.h>
22#include <linux/dma-mapping.h>
7ad8096e 23#include <linux/mutex.h>
5b7d70c6
BD		 24#include <linux/seq_file.h>
25#include <linux/delay.h>
26#include <linux/io.h>
5a0e3ad6 27#include <linux/slab.h>
c50f056c 28#include <linux/of_platform.h>
5b7d70c6
BD		 29
30#include <linux/usb/ch9.h>
31#include <linux/usb/gadget.h>
b2e587db 32#include <linux/usb/phy.h>
5b7d70c6 33
f7c0b143 34#include "core.h"
941fcce4 35#include "hw.h"
5b7d70c6
BD		 36
37/* conversion functions */
1f91b4cc 38static inline struct dwc2_hsotg_req *our_req(struct usb_request *req)
5b7d70c6 39{
1f91b4cc 40 return container_of(req, struct dwc2_hsotg_req, req);
5b7d70c6
BD		 41}
42
1f91b4cc 43static inline struct dwc2_hsotg_ep *our_ep(struct usb_ep *ep)
5b7d70c6 44{
1f91b4cc 45 return container_of(ep, struct dwc2_hsotg_ep, ep);
5b7d70c6
BD		 46}
47
941fcce4 48static inline struct dwc2_hsotg *to_hsotg(struct usb_gadget *gadget)
5b7d70c6 49{
941fcce4 50 return container_of(gadget, struct dwc2_hsotg, gadget);
5b7d70c6
BD		 51}
52
53static inline void __orr32(void __iomem *ptr, u32 val)
54{
95c8bc36 55 dwc2_writel(dwc2_readl(ptr) | val, ptr);
5b7d70c6
BD		 56}
57
58static inline void __bic32(void __iomem *ptr, u32 val)
59{
95c8bc36 60 dwc2_writel(dwc2_readl(ptr) & ~val, ptr);
5b7d70c6
BD		 61}
62
1f91b4cc 63static inline struct dwc2_hsotg_ep *index_to_ep(struct dwc2_hsotg *hsotg,
c6f5c050
MYK		 64 u32 ep_index, u32 dir_in)
65{
66 if (dir_in)
67 return hsotg->eps_in[ep_index];
68 else
69 return hsotg->eps_out[ep_index];
70}
71
997f4f81 72/* forward declaration of functions */
1f91b4cc 73static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg);
5b7d70c6
BD		 74
75/**
76 * using_dma - return the DMA status of the driver.
77 * @hsotg: The driver state.
78 *
79 * Return true if we're using DMA.
80 *
81 * Currently, we have the DMA support code worked into everywhere
82 * that needs it, but the AMBA DMA implementation in the hardware can
83 * only DMA from 32bit aligned addresses. This means that gadgets such
84 * as the CDC Ethernet cannot work as they often pass packets which are
85 * not 32bit aligned.
86 *
87 * Unfortunately the choice to use DMA or not is global to the controller
88 * and seems to be only settable when the controller is being put through
89 * a core reset. This means we either need to fix the gadgets to take
90 * account of DMA alignment, or add bounce buffers (yuerk).
91 *
edd74be8 92 * g_using_dma is set depending on dts flag.
5b7d70c6 93 */
941fcce4 94static inline bool using_dma(struct dwc2_hsotg *hsotg)
5b7d70c6 95{
edd74be8 96 return hsotg->g_using_dma;
5b7d70c6
BD		 97}
98
92d1635d
VM		 99/**
100 * dwc2_gadget_incr_frame_num - Increments the targeted frame number.
101 * @hs_ep: The endpoint
102 * @increment: The value to increment by
103 *
104 * This function will also check if the frame number overruns DSTS_SOFFN_LIMIT.
105 * If an overrun occurs it will wrap the value and set the frame_overrun flag.
106 */
107static inline void dwc2_gadget_incr_frame_num(struct dwc2_hsotg_ep *hs_ep)
108{
109 hs_ep->target_frame += hs_ep->interval;
110 if (hs_ep->target_frame > DSTS_SOFFN_LIMIT) {
111 hs_ep->frame_overrun = 1;
112 hs_ep->target_frame &= DSTS_SOFFN_LIMIT;
113 } else {
114 hs_ep->frame_overrun = 0;
115 }
116}
117
5b7d70c6 118/**
1f91b4cc 119 * dwc2_hsotg_en_gsint - enable one or more of the general interrupt
5b7d70c6
BD		 120 * @hsotg: The device state
121 * @ints: A bitmask of the interrupts to enable
122 */
1f91b4cc 123static void dwc2_hsotg_en_gsint(struct dwc2_hsotg *hsotg, u32 ints)
5b7d70c6 124{
95c8bc36 125 u32 gsintmsk = dwc2_readl(hsotg->regs + GINTMSK);
5b7d70c6
BD		 126 u32 new_gsintmsk;
127
128 new_gsintmsk = gsintmsk | ints;
129
130 if (new_gsintmsk != gsintmsk) {
131 dev_dbg(hsotg->dev, "gsintmsk now 0x%08x\n", new_gsintmsk);
95c8bc36 132 dwc2_writel(new_gsintmsk, hsotg->regs + GINTMSK);
5b7d70c6
BD		 133 }
134}
135
136/**
1f91b4cc 137 * dwc2_hsotg_disable_gsint - disable one or more of the general interrupt
5b7d70c6
BD		 138 * @hsotg: The device state
139 * @ints: A bitmask of the interrupts to enable
140 */
1f91b4cc 141static void dwc2_hsotg_disable_gsint(struct dwc2_hsotg *hsotg, u32 ints)
5b7d70c6 142{
95c8bc36 143 u32 gsintmsk = dwc2_readl(hsotg->regs + GINTMSK);
5b7d70c6
BD		 144 u32 new_gsintmsk;
145
146 new_gsintmsk = gsintmsk & ~ints;
147
148 if (new_gsintmsk != gsintmsk)
95c8bc36 149 dwc2_writel(new_gsintmsk, hsotg->regs + GINTMSK);
5b7d70c6
BD		 150}
151
152/**
1f91b4cc 153 * dwc2_hsotg_ctrl_epint - enable/disable an endpoint irq
5b7d70c6
BD		 154 * @hsotg: The device state
155 * @ep: The endpoint index
156 * @dir_in: True if direction is in.
157 * @en: The enable value, true to enable
158 *
159 * Set or clear the mask for an individual endpoint's interrupt
160 * request.
161 */
1f91b4cc 162static void dwc2_hsotg_ctrl_epint(struct dwc2_hsotg *hsotg,
5b7d70c6
BD		 163 unsigned int ep, unsigned int dir_in,
164 unsigned int en)
165{
166 unsigned long flags;
167 u32 bit = 1 << ep;
168 u32 daint;
169
170 if (!dir_in)
171 bit <<= 16;
172
173 local_irq_save(flags);
95c8bc36 174 daint = dwc2_readl(hsotg->regs + DAINTMSK);
5b7d70c6
BD		 175 if (en)
176 daint |= bit;
177 else
178 daint &= ~bit;
95c8bc36 179 dwc2_writel(daint, hsotg->regs + DAINTMSK);
5b7d70c6
BD		 180 local_irq_restore(flags);
181}
182
183/**
1f91b4cc 184 * dwc2_hsotg_init_fifo - initialise non-periodic FIFOs
5b7d70c6
BD		 185 * @hsotg: The device instance.
186 */
1f91b4cc 187static void dwc2_hsotg_init_fifo(struct dwc2_hsotg *hsotg)
5b7d70c6 188{
0f002d20
BD		 189 unsigned int ep;
190 unsigned int addr;
1703a6d3 191 int timeout;
0f002d20
BD		 192 u32 val;
193
7fcbc95c
GH		 194 /* Reset fifo map if not correctly cleared during previous session */
195 WARN_ON(hsotg->fifo_map);
196 hsotg->fifo_map = 0;
197
0a176279 198 /* set RX/NPTX FIFO sizes */
95c8bc36
AS		 199 dwc2_writel(hsotg->g_rx_fifo_sz, hsotg->regs + GRXFSIZ);
200 dwc2_writel((hsotg->g_rx_fifo_sz << FIFOSIZE_STARTADDR_SHIFT) |
0a176279
GH		 201 (hsotg->g_np_g_tx_fifo_sz << FIFOSIZE_DEPTH_SHIFT),
202 hsotg->regs + GNPTXFSIZ);
0f002d20 203
8b9bc460
LM		 204 /*
205 * arange all the rest of the TX FIFOs, as some versions of this
0f002d20
BD		 206 * block have overlapping default addresses. This also ensures
207 * that if the settings have been changed, then they are set to
8b9bc460
LM		 208 * known values.
209 */
0f002d20
BD		 210
211 /* start at the end of the GNPTXFSIZ, rounded up */
0a176279 212 addr = hsotg->g_rx_fifo_sz + hsotg->g_np_g_tx_fifo_sz;
0f002d20 213
8b9bc460 214 /*
0a176279 215 * Configure fifos sizes from provided configuration and assign
b203d0a2
RB		 216 * them to endpoints dynamically according to maxpacket size value of
217 * given endpoint.
8b9bc460 218 */
0a176279
GH		 219 for (ep = 1; ep < MAX_EPS_CHANNELS; ep++) {
220 if (!hsotg->g_tx_fifo_sz[ep])
221 continue;
0f002d20 222 val = addr;
0a176279
GH		 223 val |= hsotg->g_tx_fifo_sz[ep] << FIFOSIZE_DEPTH_SHIFT;
224 WARN_ONCE(addr + hsotg->g_tx_fifo_sz[ep] > hsotg->fifo_mem,
cff9eb75 225 "insufficient fifo memory");
0a176279 226 addr += hsotg->g_tx_fifo_sz[ep];
0f002d20 227
95c8bc36 228 dwc2_writel(val, hsotg->regs + DPTXFSIZN(ep));
0f002d20 229 }
1703a6d3 230
8b9bc460
LM		 231 /*
232 * according to p428 of the design guide, we need to ensure that
233 * all fifos are flushed before continuing
234 */
1703a6d3 235
95c8bc36 236 dwc2_writel(GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH |
47a1685f 237 GRSTCTL_RXFFLSH, hsotg->regs + GRSTCTL);
1703a6d3
BD		 238
239 /* wait until the fifos are both flushed */
240 timeout = 100;
241 while (1) {
95c8bc36 242 val = dwc2_readl(hsotg->regs + GRSTCTL);
1703a6d3 243
47a1685f 244 if ((val & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH)) == 0)
1703a6d3
BD		 245 break;
246
247 if (--timeout == 0) {
248 dev_err(hsotg->dev,
249 "%s: timeout flushing fifos (GRSTCTL=%08x)\n",
250 __func__, val);
48b20bcb 251 break;
1703a6d3
BD		 252 }
253
254 udelay(1);
255 }
256
257 dev_dbg(hsotg->dev, "FIFOs reset, timeout at %d\n", timeout);
5b7d70c6
BD		 258}
259
260/**
261 * @ep: USB endpoint to allocate request for.
262 * @flags: Allocation flags
263 *
264 * Allocate a new USB request structure appropriate for the specified endpoint
265 */
1f91b4cc 266static struct usb_request *dwc2_hsotg_ep_alloc_request(struct usb_ep *ep,
0978f8c5 267 gfp_t flags)
5b7d70c6 268{
1f91b4cc 269 struct dwc2_hsotg_req *req;
5b7d70c6 270
1f91b4cc 271 req = kzalloc(sizeof(struct dwc2_hsotg_req), flags);
5b7d70c6
BD		 272 if (!req)
273 return NULL;
274
275 INIT_LIST_HEAD(&req->queue);
276
5b7d70c6
BD		 277 return &req->req;
278}
279
280/**
281 * is_ep_periodic - return true if the endpoint is in periodic mode.
282 * @hs_ep: The endpoint to query.
283 *
284 * Returns true if the endpoint is in periodic mode, meaning it is being
285 * used for an Interrupt or ISO transfer.
286 */
1f91b4cc 287static inline int is_ep_periodic(struct dwc2_hsotg_ep *hs_ep)
5b7d70c6
BD		 288{
289 return hs_ep->periodic;
290}
291
292/**
1f91b4cc 293 * dwc2_hsotg_unmap_dma - unmap the DMA memory being used for the request
5b7d70c6
BD		 294 * @hsotg: The device state.
295 * @hs_ep: The endpoint for the request
296 * @hs_req: The request being processed.
297 *
1f91b4cc 298 * This is the reverse of dwc2_hsotg_map_dma(), called for the completion
5b7d70c6 299 * of a request to ensure the buffer is ready for access by the caller.
8b9bc460 300 */
1f91b4cc
FB		 301static void dwc2_hsotg_unmap_dma(struct dwc2_hsotg *hsotg,
302 struct dwc2_hsotg_ep *hs_ep,
303 struct dwc2_hsotg_req *hs_req)
5b7d70c6
BD		 304{
305 struct usb_request *req = &hs_req->req;
5b7d70c6
BD		 306
307 /* ignore this if we're not moving any data */
308 if (hs_req->req.length == 0)
309 return;
310
17d966a3 311 usb_gadget_unmap_request(&hsotg->gadget, req, hs_ep->dir_in);
5b7d70c6
BD		 312}
313
314/**
1f91b4cc 315 * dwc2_hsotg_write_fifo - write packet Data to the TxFIFO
5b7d70c6
BD		 316 * @hsotg: The controller state.
317 * @hs_ep: The endpoint we're going to write for.
318 * @hs_req: The request to write data for.
319 *
320 * This is called when the TxFIFO has some space in it to hold a new
321 * transmission and we have something to give it. The actual setup of
322 * the data size is done elsewhere, so all we have to do is to actually
323 * write the data.
324 *
325 * The return value is zero if there is more space (or nothing was done)
326 * otherwise -ENOSPC is returned if the FIFO space was used up.
327 *
328 * This routine is only needed for PIO
8b9bc460 329 */
1f91b4cc
FB		 330static int dwc2_hsotg_write_fifo(struct dwc2_hsotg *hsotg,
331 struct dwc2_hsotg_ep *hs_ep,
332 struct dwc2_hsotg_req *hs_req)
5b7d70c6
BD		 333{
334 bool periodic = is_ep_periodic(hs_ep);
95c8bc36 335 u32 gnptxsts = dwc2_readl(hsotg->regs + GNPTXSTS);
5b7d70c6
BD		 336 int buf_pos = hs_req->req.actual;
337 int to_write = hs_ep->size_loaded;
338 void *data;
339 int can_write;
340 int pkt_round;
4fca54aa 341 int max_transfer;
5b7d70c6
BD		 342
343 to_write -= (buf_pos - hs_ep->last_load);
344
345 /* if there's nothing to write, get out early */
346 if (to_write == 0)
347 return 0;
348
10aebc77 349 if (periodic && !hsotg->dedicated_fifos) {
95c8bc36 350 u32 epsize = dwc2_readl(hsotg->regs + DIEPTSIZ(hs_ep->index));
5b7d70c6
BD		 351 int size_left;
352 int size_done;
353
8b9bc460
LM		 354 /*
355 * work out how much data was loaded so we can calculate
356 * how much data is left in the fifo.
357 */
5b7d70c6 358
47a1685f 359 size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
5b7d70c6 360
8b9bc460
LM		 361 /*
362 * if shared fifo, we cannot write anything until the
e7a9ff54
BD		 363 * previous data has been completely sent.
364 */
365 if (hs_ep->fifo_load != 0) {
1f91b4cc 366 dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP);
e7a9ff54
BD		 367 return -ENOSPC;
368 }
369
5b7d70c6
BD		 370 dev_dbg(hsotg->dev, "%s: left=%d, load=%d, fifo=%d, size %d\n",
371 __func__, size_left,
372 hs_ep->size_loaded, hs_ep->fifo_load, hs_ep->fifo_size);
373
374 /* how much of the data has moved */
375 size_done = hs_ep->size_loaded - size_left;
376
377 /* how much data is left in the fifo */
378 can_write = hs_ep->fifo_load - size_done;
379 dev_dbg(hsotg->dev, "%s: => can_write1=%d\n",
380 __func__, can_write);
381
382 can_write = hs_ep->fifo_size - can_write;
383 dev_dbg(hsotg->dev, "%s: => can_write2=%d\n",
384 __func__, can_write);
385
386 if (can_write <= 0) {
1f91b4cc 387 dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP);
5b7d70c6
BD		 388 return -ENOSPC;
389 }
10aebc77 390 } else if (hsotg->dedicated_fifos && hs_ep->index != 0) {
95c8bc36 391 can_write = dwc2_readl(hsotg->regs + DTXFSTS(hs_ep->index));
10aebc77
BD		 392
393 can_write &= 0xffff;
394 can_write *= 4;
5b7d70c6 395 } else {
47a1685f 396 if (GNPTXSTS_NP_TXQ_SPC_AVAIL_GET(gnptxsts) == 0) {
5b7d70c6
BD		 397 dev_dbg(hsotg->dev,
398 "%s: no queue slots available (0x%08x)\n",
399 __func__, gnptxsts);
400
1f91b4cc 401 dwc2_hsotg_en_gsint(hsotg, GINTSTS_NPTXFEMP);
5b7d70c6
BD		 402 return -ENOSPC;
403 }
404
47a1685f 405 can_write = GNPTXSTS_NP_TXF_SPC_AVAIL_GET(gnptxsts);
679f9b7c 406 can_write *= 4; /* fifo size is in 32bit quantities. */
5b7d70c6
BD		 407 }
408
4fca54aa
RB		 409 max_transfer = hs_ep->ep.maxpacket * hs_ep->mc;
410
411 dev_dbg(hsotg->dev, "%s: GNPTXSTS=%08x, can=%d, to=%d, max_transfer %d\n",
412 __func__, gnptxsts, can_write, to_write, max_transfer);
5b7d70c6 413
8b9bc460
LM		 414 /*
415 * limit to 512 bytes of data, it seems at least on the non-periodic
5b7d70c6
BD		 416 * FIFO, requests of >512 cause the endpoint to get stuck with a
417 * fragment of the end of the transfer in it.
418 */
811f3303 419 if (can_write > 512 && !periodic)
5b7d70c6
BD		 420 can_write = 512;
421
8b9bc460
LM		 422 /*
423 * limit the write to one max-packet size worth of data, but allow
03e10e5a 424 * the transfer to return that it did not run out of fifo space
8b9bc460
LM		 425 * doing it.
426 */
4fca54aa
RB		 427 if (to_write > max_transfer) {
428 to_write = max_transfer;
03e10e5a 429
5cb2ff0c
RB		 430 /* it's needed only when we do not use dedicated fifos */
431 if (!hsotg->dedicated_fifos)
1f91b4cc 432 dwc2_hsotg_en_gsint(hsotg,
47a1685f
DN		 433 periodic ? GINTSTS_PTXFEMP :
434 GINTSTS_NPTXFEMP);
03e10e5a
BD		 435 }
436
5b7d70c6
BD		 437 /* see if we can write data */
438
439 if (to_write > can_write) {
440 to_write = can_write;
4fca54aa 441 pkt_round = to_write % max_transfer;
5b7d70c6 442
8b9bc460
LM		 443 /*
444 * Round the write down to an
5b7d70c6
BD		 445 * exact number of packets.
446 *
447 * Note, we do not currently check to see if we can ever
448 * write a full packet or not to the FIFO.
449 */
450
451 if (pkt_round)
452 to_write -= pkt_round;
453
8b9bc460
LM		 454 /*
455 * enable correct FIFO interrupt to alert us when there
456 * is more room left.
457 */
5b7d70c6 458
5cb2ff0c
RB		 459 /* it's needed only when we do not use dedicated fifos */
460 if (!hsotg->dedicated_fifos)
1f91b4cc 461 dwc2_hsotg_en_gsint(hsotg,
47a1685f
DN		 462 periodic ? GINTSTS_PTXFEMP :
463 GINTSTS_NPTXFEMP);
5b7d70c6
BD		 464 }
465
466 dev_dbg(hsotg->dev, "write %d/%d, can_write %d, done %d\n",
467 to_write, hs_req->req.length, can_write, buf_pos);
468
469 if (to_write <= 0)
470 return -ENOSPC;
471
472 hs_req->req.actual = buf_pos + to_write;
473 hs_ep->total_data += to_write;
474
475 if (periodic)
476 hs_ep->fifo_load += to_write;
477
478 to_write = DIV_ROUND_UP(to_write, 4);
479 data = hs_req->req.buf + buf_pos;
480
1a7ed5be 481 iowrite32_rep(hsotg->regs + EPFIFO(hs_ep->index), data, to_write);
5b7d70c6
BD		 482
483 return (to_write >= can_write) ? -ENOSPC : 0;
484}
485
486/**
487 * get_ep_limit - get the maximum data legnth for this endpoint
488 * @hs_ep: The endpoint
489 *
490 * Return the maximum data that can be queued in one go on a given endpoint
491 * so that transfers that are too long can be split.
492 */
1f91b4cc 493static unsigned get_ep_limit(struct dwc2_hsotg_ep *hs_ep)
5b7d70c6
BD		 494{
495 int index = hs_ep->index;
496 unsigned maxsize;
497 unsigned maxpkt;
498
499 if (index != 0) {
47a1685f
DN		 500 maxsize = DXEPTSIZ_XFERSIZE_LIMIT + 1;
501 maxpkt = DXEPTSIZ_PKTCNT_LIMIT + 1;
5b7d70c6 502 } else {
b05ca580 503 maxsize = 64+64;
66e5c643 504 if (hs_ep->dir_in)
47a1685f 505 maxpkt = DIEPTSIZ0_PKTCNT_LIMIT + 1;
66e5c643 506 else
5b7d70c6 507 maxpkt = 2;
5b7d70c6
BD		 508 }
509
510 /* we made the constant loading easier above by using +1 */
511 maxpkt--;
512 maxsize--;
513
8b9bc460
LM		 514 /*
515 * constrain by packet count if maxpkts*pktsize is greater
516 * than the length register size.
517 */
5b7d70c6
BD		 518
519 if ((maxpkt * hs_ep->ep.maxpacket) < maxsize)
520 maxsize = maxpkt * hs_ep->ep.maxpacket;
521
522 return maxsize;
523}
524
525/**
1f91b4cc 526 * dwc2_hsotg_start_req - start a USB request from an endpoint's queue
5b7d70c6
BD		 527 * @hsotg: The controller state.
528 * @hs_ep: The endpoint to process a request for
529 * @hs_req: The request to start.
530 * @continuing: True if we are doing more for the current request.
531 *
532 * Start the given request running by setting the endpoint registers
533 * appropriately, and writing any data to the FIFOs.
534 */
1f91b4cc
FB		 535static void dwc2_hsotg_start_req(struct dwc2_hsotg *hsotg,
536 struct dwc2_hsotg_ep *hs_ep,
537 struct dwc2_hsotg_req *hs_req,
5b7d70c6
BD		 538 bool continuing)
539{
540 struct usb_request *ureq = &hs_req->req;
541 int index = hs_ep->index;
542 int dir_in = hs_ep->dir_in;
543 u32 epctrl_reg;
544 u32 epsize_reg;
545 u32 epsize;
546 u32 ctrl;
547 unsigned length;
548 unsigned packets;
549 unsigned maxreq;
550
551 if (index != 0) {
552 if (hs_ep->req && !continuing) {
553 dev_err(hsotg->dev, "%s: active request\n", __func__);
554 WARN_ON(1);
555 return;
556 } else if (hs_ep->req != hs_req && continuing) {
557 dev_err(hsotg->dev,
558 "%s: continue different req\n", __func__);
559 WARN_ON(1);
560 return;
561 }
562 }
563
94cb8fd6
LM		 564 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
565 epsize_reg = dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index);
5b7d70c6
BD		 566
567 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n",
95c8bc36 568 __func__, dwc2_readl(hsotg->regs + epctrl_reg), index,
5b7d70c6
BD		 569 hs_ep->dir_in ? "in" : "out");
570
9c39ddc6 571 /* If endpoint is stalled, we will restart request later */
95c8bc36 572 ctrl = dwc2_readl(hsotg->regs + epctrl_reg);
9c39ddc6 573
b2d4c54e 574 if (index && ctrl & DXEPCTL_STALL) {
9c39ddc6
AT		 575 dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index);
576 return;
577 }
578
5b7d70c6 579 length = ureq->length - ureq->actual;
71225bee
LM		 580 dev_dbg(hsotg->dev, "ureq->length:%d ureq->actual:%d\n",
581 ureq->length, ureq->actual);
5b7d70c6
BD		 582
583 maxreq = get_ep_limit(hs_ep);
584 if (length > maxreq) {
585 int round = maxreq % hs_ep->ep.maxpacket;
586
587 dev_dbg(hsotg->dev, "%s: length %d, max-req %d, r %d\n",
588 __func__, length, maxreq, round);
589
590 /* round down to multiple of packets */
591 if (round)
592 maxreq -= round;
593
594 length = maxreq;
595 }
596
597 if (length)
598 packets = DIV_ROUND_UP(length, hs_ep->ep.maxpacket);
599 else
600 packets = 1; /* send one packet if length is zero. */
601
4fca54aa
RB		 602 if (hs_ep->isochronous && length > (hs_ep->mc * hs_ep->ep.maxpacket)) {
603 dev_err(hsotg->dev, "req length > maxpacket*mc\n");
604 return;
605 }
606
5b7d70c6 607 if (dir_in && index != 0)
4fca54aa 608 if (hs_ep->isochronous)
47a1685f 609 epsize = DXEPTSIZ_MC(packets);
4fca54aa 610 else
47a1685f 611 epsize = DXEPTSIZ_MC(1);
5b7d70c6
BD		 612 else
613 epsize = 0;
614
f71b5e25
MYK		 615 /*
616 * zero length packet should be programmed on its own and should not
617 * be counted in DIEPTSIZ.PktCnt with other packets.
618 */
619 if (dir_in && ureq->zero && !continuing) {
620 /* Test if zlp is actually required. */
621 if ((ureq->length >= hs_ep->ep.maxpacket) &&
622 !(ureq->length % hs_ep->ep.maxpacket))
8a20fa45 623 hs_ep->send_zlp = 1;
5b7d70c6
BD		 624 }
625
47a1685f
DN		 626 epsize |= DXEPTSIZ_PKTCNT(packets);
627 epsize |= DXEPTSIZ_XFERSIZE(length);
5b7d70c6
BD		 628
629 dev_dbg(hsotg->dev, "%s: %d@%d/%d, 0x%08x => 0x%08x\n",
630 __func__, packets, length, ureq->length, epsize, epsize_reg);
631
632 /* store the request as the current one we're doing */
633 hs_ep->req = hs_req;
634
635 /* write size / packets */
95c8bc36 636 dwc2_writel(epsize, hsotg->regs + epsize_reg);
5b7d70c6 637
db1d8ba3 638 if (using_dma(hsotg) && !continuing) {
5b7d70c6
BD		 639 unsigned int dma_reg;
640
8b9bc460
LM		 641 /*
642 * write DMA address to control register, buffer already
1f91b4cc 643 * synced by dwc2_hsotg_ep_queue().
8b9bc460 644 */
5b7d70c6 645
94cb8fd6 646 dma_reg = dir_in ? DIEPDMA(index) : DOEPDMA(index);
95c8bc36 647 dwc2_writel(ureq->dma, hsotg->regs + dma_reg);
5b7d70c6 648
0cc4cf6f 649 dev_dbg(hsotg->dev, "%s: %pad => 0x%08x\n",
8b3bc14f 650 __func__, &ureq->dma, dma_reg);
5b7d70c6
BD		 651 }
652
47a1685f 653 ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */
71225bee 654
fe0b94ab 655 dev_dbg(hsotg->dev, "ep0 state:%d\n", hsotg->ep0_state);
71225bee
LM		 656
657 /* For Setup request do not clear NAK */
fe0b94ab 658 if (!(index == 0 && hsotg->ep0_state == DWC2_EP0_SETUP))
47a1685f 659 ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */
71225bee 660
5b7d70c6 661 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
95c8bc36 662 dwc2_writel(ctrl, hsotg->regs + epctrl_reg);
5b7d70c6 663
8b9bc460
LM		 664 /*
665 * set these, it seems that DMA support increments past the end
5b7d70c6 666 * of the packet buffer so we need to calculate the length from
8b9bc460
LM		 667 * this information.
668 */
5b7d70c6
BD		 669 hs_ep->size_loaded = length;
670 hs_ep->last_load = ureq->actual;
671
672 if (dir_in && !using_dma(hsotg)) {
673 /* set these anyway, we may need them for non-periodic in */
674 hs_ep->fifo_load = 0;
675
1f91b4cc 676 dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req);
5b7d70c6
BD		 677 }
678
8b9bc460
LM		 679 /*
680 * Note, trying to clear the NAK here causes problems with transmit
681 * on the S3C6400 ending up with the TXFIFO becoming full.
682 */
5b7d70c6
BD		 683
684 /* check ep is enabled */
95c8bc36 685 if (!(dwc2_readl(hsotg->regs + epctrl_reg) & DXEPCTL_EPENA))
1a0ed863 686 dev_dbg(hsotg->dev,
47a1685f 687 "ep%d: failed to become enabled (DXEPCTL=0x%08x)?\n",
95c8bc36 688 index, dwc2_readl(hsotg->regs + epctrl_reg));
5b7d70c6 689
47a1685f 690 dev_dbg(hsotg->dev, "%s: DXEPCTL=0x%08x\n",
95c8bc36 691 __func__, dwc2_readl(hsotg->regs + epctrl_reg));
afcf4169
RB		 692
693 /* enable ep interrupts */
1f91b4cc 694 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 1);
5b7d70c6
BD		 695}
696
697/**
1f91b4cc 698 * dwc2_hsotg_map_dma - map the DMA memory being used for the request
5b7d70c6
BD		 699 * @hsotg: The device state.
700 * @hs_ep: The endpoint the request is on.
701 * @req: The request being processed.
702 *
703 * We've been asked to queue a request, so ensure that the memory buffer
704 * is correctly setup for DMA. If we've been passed an extant DMA address
705 * then ensure the buffer has been synced to memory. If our buffer has no
706 * DMA memory, then we map the memory and mark our request to allow us to
707 * cleanup on completion.
8b9bc460 708 */
1f91b4cc
FB		 709static int dwc2_hsotg_map_dma(struct dwc2_hsotg *hsotg,
710 struct dwc2_hsotg_ep *hs_ep,
5b7d70c6
BD		 711 struct usb_request *req)
712{
1f91b4cc 713 struct dwc2_hsotg_req *hs_req = our_req(req);
e58ebcd1 714 int ret;
5b7d70c6
BD		 715
716 /* if the length is zero, ignore the DMA data */
717 if (hs_req->req.length == 0)
718 return 0;
719
e58ebcd1
FB		 720 ret = usb_gadget_map_request(&hsotg->gadget, req, hs_ep->dir_in);
721 if (ret)
722 goto dma_error;
5b7d70c6
BD		 723
724 return 0;
725
726dma_error:
727 dev_err(hsotg->dev, "%s: failed to map buffer %p, %d bytes\n",
728 __func__, req->buf, req->length);
729
730 return -EIO;
731}
732
1f91b4cc
FB		 733static int dwc2_hsotg_handle_unaligned_buf_start(struct dwc2_hsotg *hsotg,
734 struct dwc2_hsotg_ep *hs_ep, struct dwc2_hsotg_req *hs_req)
7d24c1b5
MYK		 735{
736 void *req_buf = hs_req->req.buf;
737
738 /* If dma is not being used or buffer is aligned */
739 if (!using_dma(hsotg) || !((long)req_buf & 3))
740 return 0;
741
742 WARN_ON(hs_req->saved_req_buf);
743
744 dev_dbg(hsotg->dev, "%s: %s: buf=%p length=%d\n", __func__,
745 hs_ep->ep.name, req_buf, hs_req->req.length);
746
747 hs_req->req.buf = kmalloc(hs_req->req.length, GFP_ATOMIC);
748 if (!hs_req->req.buf) {
749 hs_req->req.buf = req_buf;
750 dev_err(hsotg->dev,
751 "%s: unable to allocate memory for bounce buffer\n",
752 __func__);
753 return -ENOMEM;
754 }
755
756 /* Save actual buffer */
757 hs_req->saved_req_buf = req_buf;
758
759 if (hs_ep->dir_in)
760 memcpy(hs_req->req.buf, req_buf, hs_req->req.length);
761 return 0;
762}
763
1f91b4cc
FB		 764static void dwc2_hsotg_handle_unaligned_buf_complete(struct dwc2_hsotg *hsotg,
765 struct dwc2_hsotg_ep *hs_ep, struct dwc2_hsotg_req *hs_req)
7d24c1b5
MYK		 766{
767 /* If dma is not being used or buffer was aligned */
768 if (!using_dma(hsotg) || !hs_req->saved_req_buf)
769 return;
770
771 dev_dbg(hsotg->dev, "%s: %s: status=%d actual-length=%d\n", __func__,
772 hs_ep->ep.name, hs_req->req.status, hs_req->req.actual);
773
774 /* Copy data from bounce buffer on successful out transfer */
775 if (!hs_ep->dir_in && !hs_req->req.status)
776 memcpy(hs_req->saved_req_buf, hs_req->req.buf,
777 hs_req->req.actual);
778
779 /* Free bounce buffer */
780 kfree(hs_req->req.buf);
781
782 hs_req->req.buf = hs_req->saved_req_buf;
783 hs_req->saved_req_buf = NULL;
784}
785
1f91b4cc 786static int dwc2_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req,
5b7d70c6
BD		 787 gfp_t gfp_flags)
788{
1f91b4cc
FB		 789 struct dwc2_hsotg_req *hs_req = our_req(req);
790 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
941fcce4 791 struct dwc2_hsotg *hs = hs_ep->parent;
5b7d70c6 792 bool first;
7d24c1b5 793 int ret;
5b7d70c6
BD		 794
795 dev_dbg(hs->dev, "%s: req %p: %d@%p, noi=%d, zero=%d, snok=%d\n",
796 ep->name, req, req->length, req->buf, req->no_interrupt,
797 req->zero, req->short_not_ok);
798
7ababa92
GH		 799 /* Prevent new request submission when controller is suspended */
800 if (hs->lx_state == DWC2_L2) {
801 dev_dbg(hs->dev, "%s: don't submit request while suspended\n",
802 __func__);
803 return -EAGAIN;
804 }
805
5b7d70c6
BD		 806 /* initialise status of the request */
807 INIT_LIST_HEAD(&hs_req->queue);
808 req->actual = 0;
809 req->status = -EINPROGRESS;
810
1f91b4cc 811 ret = dwc2_hsotg_handle_unaligned_buf_start(hs, hs_ep, hs_req);
7d24c1b5
MYK		 812 if (ret)
813 return ret;
814
5b7d70c6
BD		 815 /* if we're using DMA, sync the buffers as necessary */
816 if (using_dma(hs)) {
1f91b4cc 817 ret = dwc2_hsotg_map_dma(hs, hs_ep, req);
5b7d70c6
BD		 818 if (ret)
819 return ret;
820 }
821
5b7d70c6
BD		 822 first = list_empty(&hs_ep->queue);
823 list_add_tail(&hs_req->queue, &hs_ep->queue);
824
825 if (first)
1f91b4cc 826 dwc2_hsotg_start_req(hs, hs_ep, hs_req, false);
5b7d70c6 827
5b7d70c6
BD		 828 return 0;
829}
830
1f91b4cc 831static int dwc2_hsotg_ep_queue_lock(struct usb_ep *ep, struct usb_request *req,
5ad1d316
LM		 832 gfp_t gfp_flags)
833{
1f91b4cc 834 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
941fcce4 835 struct dwc2_hsotg *hs = hs_ep->parent;
5ad1d316
LM		 836 unsigned long flags = 0;
837 int ret = 0;
838
839 spin_lock_irqsave(&hs->lock, flags);
1f91b4cc 840 ret = dwc2_hsotg_ep_queue(ep, req, gfp_flags);
5ad1d316
LM		 841 spin_unlock_irqrestore(&hs->lock, flags);
842
843 return ret;
844}
845
1f91b4cc 846static void dwc2_hsotg_ep_free_request(struct usb_ep *ep,
5b7d70c6
BD		 847 struct usb_request *req)
848{
1f91b4cc 849 struct dwc2_hsotg_req *hs_req = our_req(req);
5b7d70c6
BD		 850
851 kfree(hs_req);
852}
853
854/**
1f91b4cc 855 * dwc2_hsotg_complete_oursetup - setup completion callback
5b7d70c6
BD		 856 * @ep: The endpoint the request was on.
857 * @req: The request completed.
858 *
859 * Called on completion of any requests the driver itself
860 * submitted that need cleaning up.
861 */
1f91b4cc 862static void dwc2_hsotg_complete_oursetup(struct usb_ep *ep,
5b7d70c6
BD		 863 struct usb_request *req)
864{
1f91b4cc 865 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
941fcce4 866 struct dwc2_hsotg *hsotg = hs_ep->parent;
5b7d70c6
BD		 867
868 dev_dbg(hsotg->dev, "%s: ep %p, req %p\n", __func__, ep, req);
869
1f91b4cc 870 dwc2_hsotg_ep_free_request(ep, req);
5b7d70c6
BD		 871}
872
873/**
874 * ep_from_windex - convert control wIndex value to endpoint
875 * @hsotg: The driver state.
876 * @windex: The control request wIndex field (in host order).
877 *
878 * Convert the given wIndex into a pointer to an driver endpoint
879 * structure, or return NULL if it is not a valid endpoint.
8b9bc460 880 */
1f91b4cc 881static struct dwc2_hsotg_ep *ep_from_windex(struct dwc2_hsotg *hsotg,
5b7d70c6
BD		 882 u32 windex)
883{
1f91b4cc 884 struct dwc2_hsotg_ep *ep;
5b7d70c6
BD		 885 int dir = (windex & USB_DIR_IN) ? 1 : 0;
886 int idx = windex & 0x7F;
887
888 if (windex >= 0x100)
889 return NULL;
890
b3f489b2 891 if (idx > hsotg->num_of_eps)
5b7d70c6
BD		 892 return NULL;
893
c6f5c050
MYK		 894 ep = index_to_ep(hsotg, idx, dir);
895
5b7d70c6
BD		 896 if (idx && ep->dir_in != dir)
897 return NULL;
898
899 return ep;
900}
901
9e14d0a5 902/**
1f91b4cc 903 * dwc2_hsotg_set_test_mode - Enable usb Test Modes
9e14d0a5
GH		 904 * @hsotg: The driver state.
905 * @testmode: requested usb test mode
906 * Enable usb Test Mode requested by the Host.
907 */
1f91b4cc 908int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode)
9e14d0a5 909{
95c8bc36 910 int dctl = dwc2_readl(hsotg->regs + DCTL);
9e14d0a5
GH		 911
912 dctl &= ~DCTL_TSTCTL_MASK;
913 switch (testmode) {
914 case TEST_J:
915 case TEST_K:
916 case TEST_SE0_NAK:
917 case TEST_PACKET:
918 case TEST_FORCE_EN:
919 dctl |= testmode << DCTL_TSTCTL_SHIFT;
920 break;
921 default:
922 return -EINVAL;
923 }
95c8bc36 924 dwc2_writel(dctl, hsotg->regs + DCTL);
9e14d0a5
GH		 925 return 0;
926}
927
5b7d70c6 928/**
1f91b4cc 929 * dwc2_hsotg_send_reply - send reply to control request
5b7d70c6
BD		 930 * @hsotg: The device state
931 * @ep: Endpoint 0
932 * @buff: Buffer for request
933 * @length: Length of reply.
934 *
935 * Create a request and queue it on the given endpoint. This is useful as
936 * an internal method of sending replies to certain control requests, etc.
937 */
1f91b4cc
FB		 938static int dwc2_hsotg_send_reply(struct dwc2_hsotg *hsotg,
939 struct dwc2_hsotg_ep *ep,
5b7d70c6
BD		 940 void *buff,
941 int length)
942{
943 struct usb_request *req;
944 int ret;
945
946 dev_dbg(hsotg->dev, "%s: buff %p, len %d\n", __func__, buff, length);
947
1f91b4cc 948 req = dwc2_hsotg_ep_alloc_request(&ep->ep, GFP_ATOMIC);
5b7d70c6
BD		 949 hsotg->ep0_reply = req;
950 if (!req) {
951 dev_warn(hsotg->dev, "%s: cannot alloc req\n", __func__);
952 return -ENOMEM;
953 }
954
955 req->buf = hsotg->ep0_buff;
956 req->length = length;
f71b5e25
MYK		 957 /*
958 * zero flag is for sending zlp in DATA IN stage. It has no impact on
959 * STATUS stage.
960 */
961 req->zero = 0;
1f91b4cc 962 req->complete = dwc2_hsotg_complete_oursetup;
5b7d70c6
BD		 963
964 if (length)
965 memcpy(req->buf, buff, length);
5b7d70c6 966
1f91b4cc 967 ret = dwc2_hsotg_ep_queue(&ep->ep, req, GFP_ATOMIC);
5b7d70c6
BD		 968 if (ret) {
969 dev_warn(hsotg->dev, "%s: cannot queue req\n", __func__);
970 return ret;
971 }
972
973 return 0;
974}
975
976/**
1f91b4cc 977 * dwc2_hsotg_process_req_status - process request GET_STATUS
5b7d70c6
BD		 978 * @hsotg: The device state
979 * @ctrl: USB control request
980 */
1f91b4cc 981static int dwc2_hsotg_process_req_status(struct dwc2_hsotg *hsotg,
5b7d70c6
BD		 982 struct usb_ctrlrequest *ctrl)
983{
1f91b4cc
FB		 984 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
985 struct dwc2_hsotg_ep *ep;
5b7d70c6
BD		 986 __le16 reply;
987 int ret;
988
989 dev_dbg(hsotg->dev, "%s: USB_REQ_GET_STATUS\n", __func__);
990
991 if (!ep0->dir_in) {
992 dev_warn(hsotg->dev, "%s: direction out?\n", __func__);
993 return -EINVAL;
994 }
995
996 switch (ctrl->bRequestType & USB_RECIP_MASK) {
997 case USB_RECIP_DEVICE:
998 reply = cpu_to_le16(0); /* bit 0 => self powered,
999 * bit 1 => remote wakeup */
1000 break;
1001
1002 case USB_RECIP_INTERFACE:
1003 /* currently, the data result should be zero */
1004 reply = cpu_to_le16(0);
1005 break;
1006
1007 case USB_RECIP_ENDPOINT:
1008 ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex));
1009 if (!ep)
1010 return -ENOENT;
1011
1012 reply = cpu_to_le16(ep->halted ? 1 : 0);
1013 break;
1014
1015 default:
1016 return 0;
1017 }
1018
1019 if (le16_to_cpu(ctrl->wLength) != 2)
1020 return -EINVAL;
1021
1f91b4cc 1022 ret = dwc2_hsotg_send_reply(hsotg, ep0, &reply, 2);
5b7d70c6
BD		 1023 if (ret) {
1024 dev_err(hsotg->dev, "%s: failed to send reply\n", __func__);
1025 return ret;
1026 }
1027
1028 return 1;
1029}
1030
51da43b5 1031static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now);
5b7d70c6 1032
9c39ddc6
AT		 1033/**
1034 * get_ep_head - return the first request on the endpoint
1035 * @hs_ep: The controller endpoint to get
1036 *
1037 * Get the first request on the endpoint.
1038 */
1f91b4cc 1039static struct dwc2_hsotg_req *get_ep_head(struct dwc2_hsotg_ep *hs_ep)
9c39ddc6
AT		 1040{
1041 if (list_empty(&hs_ep->queue))
1042 return NULL;
1043
1f91b4cc 1044 return list_first_entry(&hs_ep->queue, struct dwc2_hsotg_req, queue);
9c39ddc6
AT		 1045}
1046
5b7d70c6 1047/**
1f91b4cc 1048 * dwc2_hsotg_process_req_feature - process request {SET,CLEAR}_FEATURE
5b7d70c6
BD		 1049 * @hsotg: The device state
1050 * @ctrl: USB control request
1051 */
1f91b4cc 1052static int dwc2_hsotg_process_req_feature(struct dwc2_hsotg *hsotg,
5b7d70c6
BD		 1053 struct usb_ctrlrequest *ctrl)
1054{
1f91b4cc
FB		 1055 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1056 struct dwc2_hsotg_req *hs_req;
9c39ddc6 1057 bool restart;
5b7d70c6 1058 bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE);
1f91b4cc 1059 struct dwc2_hsotg_ep *ep;
26ab3d0c 1060 int ret;
bd9ef7bf 1061 bool halted;
9e14d0a5
GH		 1062 u32 recip;
1063 u32 wValue;
1064 u32 wIndex;
5b7d70c6
BD		 1065
1066 dev_dbg(hsotg->dev, "%s: %s_FEATURE\n",
1067 __func__, set ? "SET" : "CLEAR");
1068
9e14d0a5
GH		 1069 wValue = le16_to_cpu(ctrl->wValue);
1070 wIndex = le16_to_cpu(ctrl->wIndex);
1071 recip = ctrl->bRequestType & USB_RECIP_MASK;
1072
1073 switch (recip) {
1074 case USB_RECIP_DEVICE:
1075 switch (wValue) {
1076 case USB_DEVICE_TEST_MODE:
1077 if ((wIndex & 0xff) != 0)
1078 return -EINVAL;
1079 if (!set)
1080 return -EINVAL;
1081
1082 hsotg->test_mode = wIndex >> 8;
1f91b4cc 1083 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
9e14d0a5
GH		 1084 if (ret) {
1085 dev_err(hsotg->dev,
1086 "%s: failed to send reply\n", __func__);
1087 return ret;
1088 }
1089 break;
1090 default:
1091 return -ENOENT;
1092 }
1093 break;
1094
1095 case USB_RECIP_ENDPOINT:
1096 ep = ep_from_windex(hsotg, wIndex);
5b7d70c6
BD		 1097 if (!ep) {
1098 dev_dbg(hsotg->dev, "%s: no endpoint for 0x%04x\n",
9e14d0a5 1099 __func__, wIndex);
5b7d70c6
BD		 1100 return -ENOENT;
1101 }
1102
9e14d0a5 1103 switch (wValue) {
5b7d70c6 1104 case USB_ENDPOINT_HALT:
bd9ef7bf
RB		 1105 halted = ep->halted;
1106
51da43b5 1107 dwc2_hsotg_ep_sethalt(&ep->ep, set, true);
26ab3d0c 1108
1f91b4cc 1109 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
26ab3d0c
AT		 1110 if (ret) {
1111 dev_err(hsotg->dev,
1112 "%s: failed to send reply\n", __func__);
1113 return ret;
1114 }
9c39ddc6 1115
bd9ef7bf
RB		 1116 /*
1117 * we have to complete all requests for ep if it was
1118 * halted, and the halt was cleared by CLEAR_FEATURE
1119 */
1120
1121 if (!set && halted) {
9c39ddc6
AT		 1122 /*
1123 * If we have request in progress,
1124 * then complete it
1125 */
1126 if (ep->req) {
1127 hs_req = ep->req;
1128 ep->req = NULL;
1129 list_del_init(&hs_req->queue);
c00dd4a6
GH		 1130 if (hs_req->req.complete) {
1131 spin_unlock(&hsotg->lock);
1132 usb_gadget_giveback_request(
1133 &ep->ep, &hs_req->req);
1134 spin_lock(&hsotg->lock);
1135 }
9c39ddc6
AT		 1136 }
1137
1138 /* If we have pending request, then start it */
c00dd4a6
GH		 1139 if (!ep->req) {
1140 restart = !list_empty(&ep->queue);
1141 if (restart) {
1142 hs_req = get_ep_head(ep);
1f91b4cc 1143 dwc2_hsotg_start_req(hsotg, ep,
c00dd4a6
GH		 1144 hs_req, false);
1145 }
9c39ddc6
AT		 1146 }
1147 }
1148
5b7d70c6
BD		 1149 break;
1150
1151 default:
1152 return -ENOENT;
1153 }
9e14d0a5
GH		 1154 break;
1155 default:
1156 return -ENOENT;
1157 }
5b7d70c6
BD		 1158 return 1;
1159}
1160
1f91b4cc 1161static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg);
ab93e014 1162
c9f721b2 1163/**
1f91b4cc 1164 * dwc2_hsotg_stall_ep0 - stall ep0
c9f721b2
RB		 1165 * @hsotg: The device state
1166 *
1167 * Set stall for ep0 as response for setup request.
1168 */
1f91b4cc 1169static void dwc2_hsotg_stall_ep0(struct dwc2_hsotg *hsotg)
e9ebe7c3 1170{
1f91b4cc 1171 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
c9f721b2
RB		 1172 u32 reg;
1173 u32 ctrl;
1174
1175 dev_dbg(hsotg->dev, "ep0 stall (dir=%d)\n", ep0->dir_in);
1176 reg = (ep0->dir_in) ? DIEPCTL0 : DOEPCTL0;
1177
1178 /*
1179 * DxEPCTL_Stall will be cleared by EP once it has
1180 * taken effect, so no need to clear later.
1181 */
1182
95c8bc36 1183 ctrl = dwc2_readl(hsotg->regs + reg);
47a1685f
DN		 1184 ctrl |= DXEPCTL_STALL;
1185 ctrl |= DXEPCTL_CNAK;
95c8bc36 1186 dwc2_writel(ctrl, hsotg->regs + reg);
c9f721b2
RB		 1187
1188 dev_dbg(hsotg->dev,
47a1685f 1189 "written DXEPCTL=0x%08x to %08x (DXEPCTL=0x%08x)\n",
95c8bc36 1190 ctrl, reg, dwc2_readl(hsotg->regs + reg));
c9f721b2
RB		 1191
1192 /*
1193 * complete won't be called, so we enqueue
1194 * setup request here
1195 */
1f91b4cc 1196 dwc2_hsotg_enqueue_setup(hsotg);
c9f721b2
RB		 1197}
1198
5b7d70c6 1199/**
1f91b4cc 1200 * dwc2_hsotg_process_control - process a control request
5b7d70c6
BD		 1201 * @hsotg: The device state
1202 * @ctrl: The control request received
1203 *
1204 * The controller has received the SETUP phase of a control request, and
1205 * needs to work out what to do next (and whether to pass it on to the
1206 * gadget driver).
1207 */
1f91b4cc 1208static void dwc2_hsotg_process_control(struct dwc2_hsotg *hsotg,
5b7d70c6
BD		 1209 struct usb_ctrlrequest *ctrl)
1210{
1f91b4cc 1211 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
5b7d70c6
BD		 1212 int ret = 0;
1213 u32 dcfg;
1214
e525e743
MYK		 1215 dev_dbg(hsotg->dev,
1216 "ctrl Type=%02x, Req=%02x, V=%04x, I=%04x, L=%04x\n",
1217 ctrl->bRequestType, ctrl->bRequest, ctrl->wValue,
1218 ctrl->wIndex, ctrl->wLength);
5b7d70c6 1219
fe0b94ab
MYK		 1220 if (ctrl->wLength == 0) {
1221 ep0->dir_in = 1;
1222 hsotg->ep0_state = DWC2_EP0_STATUS_IN;
1223 } else if (ctrl->bRequestType & USB_DIR_IN) {
5b7d70c6 1224 ep0->dir_in = 1;
fe0b94ab
MYK		 1225 hsotg->ep0_state = DWC2_EP0_DATA_IN;
1226 } else {
1227 ep0->dir_in = 0;
1228 hsotg->ep0_state = DWC2_EP0_DATA_OUT;
1229 }
5b7d70c6
BD		 1230
1231 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
1232 switch (ctrl->bRequest) {
1233 case USB_REQ_SET_ADDRESS:
6d713c15 1234 hsotg->connected = 1;
95c8bc36 1235 dcfg = dwc2_readl(hsotg->regs + DCFG);
47a1685f 1236 dcfg &= ~DCFG_DEVADDR_MASK;
d5dbd3f7
PZ		 1237 dcfg |= (le16_to_cpu(ctrl->wValue) <<
1238 DCFG_DEVADDR_SHIFT) & DCFG_DEVADDR_MASK;
95c8bc36 1239 dwc2_writel(dcfg, hsotg->regs + DCFG);
5b7d70c6
BD		 1240
1241 dev_info(hsotg->dev, "new address %d\n", ctrl->wValue);
1242
1f91b4cc 1243 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
5b7d70c6
BD		 1244 return;
1245
1246 case USB_REQ_GET_STATUS:
1f91b4cc 1247 ret = dwc2_hsotg_process_req_status(hsotg, ctrl);
5b7d70c6
BD		 1248 break;
1249
1250 case USB_REQ_CLEAR_FEATURE:
1251 case USB_REQ_SET_FEATURE:
1f91b4cc 1252 ret = dwc2_hsotg_process_req_feature(hsotg, ctrl);
5b7d70c6
BD		 1253 break;
1254 }
1255 }
1256
1257 /* as a fallback, try delivering it to the driver to deal with */
1258
1259 if (ret == 0 && hsotg->driver) {
93f599f2 1260 spin_unlock(&hsotg->lock);
5b7d70c6 1261 ret = hsotg->driver->setup(&hsotg->gadget, ctrl);
93f599f2 1262 spin_lock(&hsotg->lock);
5b7d70c6
BD		 1263 if (ret < 0)
1264 dev_dbg(hsotg->dev, "driver->setup() ret %d\n", ret);
1265 }
1266
8b9bc460
LM		 1267 /*
1268 * the request is either unhandlable, or is not formatted correctly
5b7d70c6
BD		 1269 * so respond with a STALL for the status stage to indicate failure.
1270 */
1271
c9f721b2 1272 if (ret < 0)
1f91b4cc 1273 dwc2_hsotg_stall_ep0(hsotg);
5b7d70c6
BD		 1274}
1275
5b7d70c6 1276/**
1f91b4cc 1277 * dwc2_hsotg_complete_setup - completion of a setup transfer
5b7d70c6
BD		 1278 * @ep: The endpoint the request was on.
1279 * @req: The request completed.
1280 *
1281 * Called on completion of any requests the driver itself submitted for
1282 * EP0 setup packets
1283 */
1f91b4cc 1284static void dwc2_hsotg_complete_setup(struct usb_ep *ep,
5b7d70c6
BD		 1285 struct usb_request *req)
1286{
1f91b4cc 1287 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
941fcce4 1288 struct dwc2_hsotg *hsotg = hs_ep->parent;
5b7d70c6
BD		 1289
1290 if (req->status < 0) {
1291 dev_dbg(hsotg->dev, "%s: failed %d\n", __func__, req->status);
1292 return;
1293 }
1294
93f599f2 1295 spin_lock(&hsotg->lock);
5b7d70c6 1296 if (req->actual == 0)
1f91b4cc 1297 dwc2_hsotg_enqueue_setup(hsotg);
5b7d70c6 1298 else
1f91b4cc 1299 dwc2_hsotg_process_control(hsotg, req->buf);
93f599f2 1300 spin_unlock(&hsotg->lock);
5b7d70c6
BD		 1301}
1302
1303/**
1f91b4cc 1304 * dwc2_hsotg_enqueue_setup - start a request for EP0 packets
5b7d70c6
BD		 1305 * @hsotg: The device state.
1306 *
1307 * Enqueue a request on EP0 if necessary to received any SETUP packets
1308 * received from the host.
1309 */
1f91b4cc 1310static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg)
5b7d70c6
BD		 1311{
1312 struct usb_request *req = hsotg->ctrl_req;
1f91b4cc 1313 struct dwc2_hsotg_req *hs_req = our_req(req);
5b7d70c6
BD		 1314 int ret;
1315
1316 dev_dbg(hsotg->dev, "%s: queueing setup request\n", __func__);
1317
1318 req->zero = 0;
1319 req->length = 8;
1320 req->buf = hsotg->ctrl_buff;
1f91b4cc 1321 req->complete = dwc2_hsotg_complete_setup;
5b7d70c6
BD		 1322
1323 if (!list_empty(&hs_req->queue)) {
1324 dev_dbg(hsotg->dev, "%s already queued???\n", __func__);
1325 return;
1326 }
1327
c6f5c050 1328 hsotg->eps_out[0]->dir_in = 0;
8a20fa45 1329 hsotg->eps_out[0]->send_zlp = 0;
fe0b94ab 1330 hsotg->ep0_state = DWC2_EP0_SETUP;
5b7d70c6 1331
1f91b4cc 1332 ret = dwc2_hsotg_ep_queue(&hsotg->eps_out[0]->ep, req, GFP_ATOMIC);
5b7d70c6
BD		 1333 if (ret < 0) {
1334 dev_err(hsotg->dev, "%s: failed queue (%d)\n", __func__, ret);
8b9bc460
LM		 1335 /*
1336 * Don't think there's much we can do other than watch the
1337 * driver fail.
1338 */
5b7d70c6
BD		 1339 }
1340}
1341
1f91b4cc
FB		 1342static void dwc2_hsotg_program_zlp(struct dwc2_hsotg *hsotg,
1343 struct dwc2_hsotg_ep *hs_ep)
fe0b94ab
MYK		 1344{
1345 u32 ctrl;
1346 u8 index = hs_ep->index;
1347 u32 epctl_reg = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index);
1348 u32 epsiz_reg = hs_ep->dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index);
1349
ccb34a91
MYK		 1350 if (hs_ep->dir_in)
1351 dev_dbg(hsotg->dev, "Sending zero-length packet on ep%d\n",
1352 index);
1353 else
1354 dev_dbg(hsotg->dev, "Receiving zero-length packet on ep%d\n",
1355 index);
fe0b94ab 1356
95c8bc36
AS		 1357 dwc2_writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
1358 DXEPTSIZ_XFERSIZE(0), hsotg->regs +
1359 epsiz_reg);
fe0b94ab 1360
95c8bc36 1361 ctrl = dwc2_readl(hsotg->regs + epctl_reg);
fe0b94ab
MYK		 1362 ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */
1363 ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */
1364 ctrl |= DXEPCTL_USBACTEP;
95c8bc36 1365 dwc2_writel(ctrl, hsotg->regs + epctl_reg);
fe0b94ab
MYK		 1366}
1367
5b7d70c6 1368/**
1f91b4cc 1369 * dwc2_hsotg_complete_request - complete a request given to us
5b7d70c6
BD		 1370 * @hsotg: The device state.
1371 * @hs_ep: The endpoint the request was on.
1372 * @hs_req: The request to complete.
1373 * @result: The result code (0 => Ok, otherwise errno)
1374 *
1375 * The given request has finished, so call the necessary completion
1376 * if it has one and then look to see if we can start a new request
1377 * on the endpoint.
1378 *
1379 * Note, expects the ep to already be locked as appropriate.
8b9bc460 1380 */
1f91b4cc
FB		 1381static void dwc2_hsotg_complete_request(struct dwc2_hsotg *hsotg,
1382 struct dwc2_hsotg_ep *hs_ep,
1383 struct dwc2_hsotg_req *hs_req,
5b7d70c6
BD		 1384 int result)
1385{
1386 bool restart;
1387
1388 if (!hs_req) {
1389 dev_dbg(hsotg->dev, "%s: nothing to complete?\n", __func__);
1390 return;
1391 }
1392
1393 dev_dbg(hsotg->dev, "complete: ep %p %s, req %p, %d => %p\n",
1394 hs_ep, hs_ep->ep.name, hs_req, result, hs_req->req.complete);
1395
8b9bc460
LM		 1396 /*
1397 * only replace the status if we've not already set an error
1398 * from a previous transaction
1399 */
5b7d70c6
BD		 1400
1401 if (hs_req->req.status == -EINPROGRESS)
1402 hs_req->req.status = result;
1403
44583fec
YL		 1404 if (using_dma(hsotg))
1405 dwc2_hsotg_unmap_dma(hsotg, hs_ep, hs_req);
1406
1f91b4cc 1407 dwc2_hsotg_handle_unaligned_buf_complete(hsotg, hs_ep, hs_req);
7d24c1b5 1408
5b7d70c6
BD		 1409 hs_ep->req = NULL;
1410 list_del_init(&hs_req->queue);
1411
8b9bc460
LM		 1412 /*
1413 * call the complete request with the locks off, just in case the
1414 * request tries to queue more work for this endpoint.
1415 */
5b7d70c6
BD		 1416
1417 if (hs_req->req.complete) {
22258f49 1418 spin_unlock(&hsotg->lock);
304f7e5e 1419 usb_gadget_giveback_request(&hs_ep->ep, &hs_req->req);
22258f49 1420 spin_lock(&hsotg->lock);
5b7d70c6
BD		 1421 }
1422
8b9bc460
LM		 1423 /*
1424 * Look to see if there is anything else to do. Note, the completion
5b7d70c6 1425 * of the previous request may have caused a new request to be started
8b9bc460
LM		 1426 * so be careful when doing this.
1427 */
5b7d70c6
BD		 1428
1429 if (!hs_ep->req && result >= 0) {
1430 restart = !list_empty(&hs_ep->queue);
1431 if (restart) {
1432 hs_req = get_ep_head(hs_ep);
1f91b4cc 1433 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, false);
5b7d70c6
BD		 1434 }
1435 }
1436}
1437
5b7d70c6 1438/**
1f91b4cc 1439 * dwc2_hsotg_rx_data - receive data from the FIFO for an endpoint
5b7d70c6
BD		 1440 * @hsotg: The device state.
1441 * @ep_idx: The endpoint index for the data
1442 * @size: The size of data in the fifo, in bytes
1443 *
1444 * The FIFO status shows there is data to read from the FIFO for a given
1445 * endpoint, so sort out whether we need to read the data into a request
1446 * that has been made for that endpoint.
1447 */
1f91b4cc 1448static void dwc2_hsotg_rx_data(struct dwc2_hsotg *hsotg, int ep_idx, int size)
5b7d70c6 1449{
1f91b4cc
FB		 1450 struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[ep_idx];
1451 struct dwc2_hsotg_req *hs_req = hs_ep->req;
94cb8fd6 1452 void __iomem *fifo = hsotg->regs + EPFIFO(ep_idx);
5b7d70c6
BD		 1453 int to_read;
1454 int max_req;
1455 int read_ptr;
1456
22258f49 1457
5b7d70c6 1458 if (!hs_req) {
95c8bc36 1459 u32 epctl = dwc2_readl(hsotg->regs + DOEPCTL(ep_idx));
5b7d70c6
BD		 1460 int ptr;
1461
6b448af4 1462 dev_dbg(hsotg->dev,
47a1685f 1463 "%s: FIFO %d bytes on ep%d but no req (DXEPCTl=0x%08x)\n",
5b7d70c6
BD		 1464 __func__, size, ep_idx, epctl);
1465
1466 /* dump the data from the FIFO, we've nothing we can do */
1467 for (ptr = 0; ptr < size; ptr += 4)
95c8bc36 1468 (void)dwc2_readl(fifo);
5b7d70c6
BD		 1469
1470 return;
1471 }
1472
5b7d70c6
BD		 1473 to_read = size;
1474 read_ptr = hs_req->req.actual;
1475 max_req = hs_req->req.length - read_ptr;
1476
a33e7136
BD		 1477 dev_dbg(hsotg->dev, "%s: read %d/%d, done %d/%d\n",
1478 __func__, to_read, max_req, read_ptr, hs_req->req.length);
1479
5b7d70c6 1480 if (to_read > max_req) {
8b9bc460
LM		 1481 /*
1482 * more data appeared than we where willing
5b7d70c6
BD		 1483 * to deal with in this request.
1484 */
1485
1486 /* currently we don't deal this */
1487 WARN_ON_ONCE(1);
1488 }
1489
5b7d70c6
BD		 1490 hs_ep->total_data += to_read;
1491 hs_req->req.actual += to_read;
1492 to_read = DIV_ROUND_UP(to_read, 4);
1493
8b9bc460
LM		 1494 /*
1495 * note, we might over-write the buffer end by 3 bytes depending on
1496 * alignment of the data.
1497 */
1a7ed5be 1498 ioread32_rep(fifo, hs_req->req.buf + read_ptr, to_read);
5b7d70c6
BD		 1499}
1500
1501/**
1f91b4cc 1502 * dwc2_hsotg_ep0_zlp - send/receive zero-length packet on control endpoint
5b7d70c6 1503 * @hsotg: The device instance
fe0b94ab 1504 * @dir_in: If IN zlp
5b7d70c6
BD		 1505 *
1506 * Generate a zero-length IN packet request for terminating a SETUP
1507 * transaction.
1508 *
1509 * Note, since we don't write any data to the TxFIFO, then it is
25985edc 1510 * currently believed that we do not need to wait for any space in
5b7d70c6
BD		 1511 * the TxFIFO.
1512 */
1f91b4cc 1513static void dwc2_hsotg_ep0_zlp(struct dwc2_hsotg *hsotg, bool dir_in)
5b7d70c6 1514{
c6f5c050 1515 /* eps_out[0] is used in both directions */
fe0b94ab
MYK		 1516 hsotg->eps_out[0]->dir_in = dir_in;
1517 hsotg->ep0_state = dir_in ? DWC2_EP0_STATUS_IN : DWC2_EP0_STATUS_OUT;
5b7d70c6 1518
1f91b4cc 1519 dwc2_hsotg_program_zlp(hsotg, hsotg->eps_out[0]);
5b7d70c6
BD		 1520}
1521
ec1f9d9f
RB		 1522static void dwc2_hsotg_change_ep_iso_parity(struct dwc2_hsotg *hsotg,
1523 u32 epctl_reg)
1524{
1525 u32 ctrl;
1526
1527 ctrl = dwc2_readl(hsotg->regs + epctl_reg);
1528 if (ctrl & DXEPCTL_EOFRNUM)
1529 ctrl |= DXEPCTL_SETEVENFR;
1530 else
1531 ctrl |= DXEPCTL_SETODDFR;
1532 dwc2_writel(ctrl, hsotg->regs + epctl_reg);
1533}
1534
5b7d70c6 1535/**
1f91b4cc 1536 * dwc2_hsotg_handle_outdone - handle receiving OutDone/SetupDone from RXFIFO
5b7d70c6
BD		 1537 * @hsotg: The device instance
1538 * @epnum: The endpoint received from
5b7d70c6
BD		 1539 *
1540 * The RXFIFO has delivered an OutDone event, which means that the data
1541 * transfer for an OUT endpoint has been completed, either by a short
1542 * packet or by the finish of a transfer.
8b9bc460 1543 */
1f91b4cc 1544static void dwc2_hsotg_handle_outdone(struct dwc2_hsotg *hsotg, int epnum)
5b7d70c6 1545{
95c8bc36 1546 u32 epsize = dwc2_readl(hsotg->regs + DOEPTSIZ(epnum));
1f91b4cc
FB		 1547 struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[epnum];
1548 struct dwc2_hsotg_req *hs_req = hs_ep->req;
5b7d70c6 1549 struct usb_request *req = &hs_req->req;
47a1685f 1550 unsigned size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
5b7d70c6
BD		 1551 int result = 0;
1552
1553 if (!hs_req) {
1554 dev_dbg(hsotg->dev, "%s: no request active\n", __func__);
1555 return;
1556 }
1557
fe0b94ab
MYK		 1558 if (epnum == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_OUT) {
1559 dev_dbg(hsotg->dev, "zlp packet received\n");
1f91b4cc
FB		 1560 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
1561 dwc2_hsotg_enqueue_setup(hsotg);
fe0b94ab
MYK		 1562 return;
1563 }
1564
5b7d70c6 1565 if (using_dma(hsotg)) {
5b7d70c6 1566 unsigned size_done;
5b7d70c6 1567
8b9bc460
LM		 1568 /*
1569 * Calculate the size of the transfer by checking how much
5b7d70c6
BD		 1570 * is left in the endpoint size register and then working it
1571 * out from the amount we loaded for the transfer.
1572 *
1573 * We need to do this as DMA pointers are always 32bit aligned
1574 * so may overshoot/undershoot the transfer.
1575 */
1576
5b7d70c6
BD		 1577 size_done = hs_ep->size_loaded - size_left;
1578 size_done += hs_ep->last_load;
1579
1580 req->actual = size_done;
1581 }
1582
a33e7136
BD		 1583 /* if there is more request to do, schedule new transfer */
1584 if (req->actual < req->length && size_left == 0) {
1f91b4cc 1585 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true);
a33e7136
BD		 1586 return;
1587 }
1588
5b7d70c6
BD		 1589 if (req->actual < req->length && req->short_not_ok) {
1590 dev_dbg(hsotg->dev, "%s: got %d/%d (short not ok) => error\n",
1591 __func__, req->actual, req->length);
1592
8b9bc460
LM		 1593 /*
1594 * todo - what should we return here? there's no one else
1595 * even bothering to check the status.
1596 */
5b7d70c6
BD		 1597 }
1598
fe0b94ab
MYK		 1599 if (epnum == 0 && hsotg->ep0_state == DWC2_EP0_DATA_OUT) {
1600 /* Move to STATUS IN */
1f91b4cc 1601 dwc2_hsotg_ep0_zlp(hsotg, true);
fe0b94ab 1602 return;
5b7d70c6
BD		 1603 }
1604
ec1f9d9f
RB		 1605 /*
1606 * Slave mode OUT transfers do not go through XferComplete so
1607 * adjust the ISOC parity here.
1608 */
1609 if (!using_dma(hsotg)) {
1610 hs_ep->has_correct_parity = 1;
1611 if (hs_ep->isochronous && hs_ep->interval == 1)
1612 dwc2_hsotg_change_ep_iso_parity(hsotg, DOEPCTL(epnum));
1613 }
1614
1f91b4cc 1615 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, result);
5b7d70c6
BD		 1616}
1617
1618/**
1f91b4cc 1619 * dwc2_hsotg_read_frameno - read current frame number
5b7d70c6
BD		 1620 * @hsotg: The device instance
1621 *
1622 * Return the current frame number
8b9bc460 1623 */
1f91b4cc 1624static u32 dwc2_hsotg_read_frameno(struct dwc2_hsotg *hsotg)
5b7d70c6
BD		 1625{
1626 u32 dsts;
1627
95c8bc36 1628 dsts = dwc2_readl(hsotg->regs + DSTS);
94cb8fd6
LM		 1629 dsts &= DSTS_SOFFN_MASK;
1630 dsts >>= DSTS_SOFFN_SHIFT;
5b7d70c6
BD		 1631
1632 return dsts;
1633}
1634
1635/**
1f91b4cc 1636 * dwc2_hsotg_handle_rx - RX FIFO has data
5b7d70c6
BD		 1637 * @hsotg: The device instance
1638 *
1639 * The IRQ handler has detected that the RX FIFO has some data in it
1640 * that requires processing, so find out what is in there and do the
1641 * appropriate read.
1642 *
25985edc 1643 * The RXFIFO is a true FIFO, the packets coming out are still in packet
5b7d70c6
BD		 1644 * chunks, so if you have x packets received on an endpoint you'll get x
1645 * FIFO events delivered, each with a packet's worth of data in it.
1646 *
1647 * When using DMA, we should not be processing events from the RXFIFO
1648 * as the actual data should be sent to the memory directly and we turn
1649 * on the completion interrupts to get notifications of transfer completion.
1650 */
1f91b4cc 1651static void dwc2_hsotg_handle_rx(struct dwc2_hsotg *hsotg)
5b7d70c6 1652{
95c8bc36 1653 u32 grxstsr = dwc2_readl(hsotg->regs + GRXSTSP);
5b7d70c6
BD		 1654 u32 epnum, status, size;
1655
1656 WARN_ON(using_dma(hsotg));
1657
47a1685f
DN		 1658 epnum = grxstsr & GRXSTS_EPNUM_MASK;
1659 status = grxstsr & GRXSTS_PKTSTS_MASK;
5b7d70c6 1660
47a1685f
DN		 1661 size = grxstsr & GRXSTS_BYTECNT_MASK;
1662 size >>= GRXSTS_BYTECNT_SHIFT;
5b7d70c6 1663
d7c747c5 1664 dev_dbg(hsotg->dev, "%s: GRXSTSP=0x%08x (%d@%d)\n",
5b7d70c6
BD		 1665 __func__, grxstsr, size, epnum);
1666
47a1685f
DN		 1667 switch ((status & GRXSTS_PKTSTS_MASK) >> GRXSTS_PKTSTS_SHIFT) {
1668 case GRXSTS_PKTSTS_GLOBALOUTNAK:
1669 dev_dbg(hsotg->dev, "GLOBALOUTNAK\n");
5b7d70c6
BD		 1670 break;
1671
47a1685f 1672 case GRXSTS_PKTSTS_OUTDONE:
5b7d70c6 1673 dev_dbg(hsotg->dev, "OutDone (Frame=0x%08x)\n",
1f91b4cc 1674 dwc2_hsotg_read_frameno(hsotg));
5b7d70c6
BD		 1675
1676 if (!using_dma(hsotg))
1f91b4cc 1677 dwc2_hsotg_handle_outdone(hsotg, epnum);
5b7d70c6
BD		 1678 break;
1679
47a1685f 1680 case GRXSTS_PKTSTS_SETUPDONE:
5b7d70c6
BD		 1681 dev_dbg(hsotg->dev,
1682 "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
1f91b4cc 1683 dwc2_hsotg_read_frameno(hsotg),
95c8bc36 1684 dwc2_readl(hsotg->regs + DOEPCTL(0)));
fe0b94ab 1685 /*
1f91b4cc 1686 * Call dwc2_hsotg_handle_outdone here if it was not called from
fe0b94ab
MYK		 1687 * GRXSTS_PKTSTS_OUTDONE. That is, if the core didn't
1688 * generate GRXSTS_PKTSTS_OUTDONE for setup packet.
1689 */
1690 if (hsotg->ep0_state == DWC2_EP0_SETUP)
1f91b4cc 1691 dwc2_hsotg_handle_outdone(hsotg, epnum);
5b7d70c6
BD		 1692 break;
1693
47a1685f 1694 case GRXSTS_PKTSTS_OUTRX:
1f91b4cc 1695 dwc2_hsotg_rx_data(hsotg, epnum, size);
5b7d70c6
BD		 1696 break;
1697
47a1685f 1698 case GRXSTS_PKTSTS_SETUPRX:
5b7d70c6
BD		 1699 dev_dbg(hsotg->dev,
1700 "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
1f91b4cc 1701 dwc2_hsotg_read_frameno(hsotg),
95c8bc36 1702 dwc2_readl(hsotg->regs + DOEPCTL(0)));
5b7d70c6 1703
fe0b94ab
MYK		 1704 WARN_ON(hsotg->ep0_state != DWC2_EP0_SETUP);
1705
1f91b4cc 1706 dwc2_hsotg_rx_data(hsotg, epnum, size);
5b7d70c6
BD		 1707 break;
1708
1709 default:
1710 dev_warn(hsotg->dev, "%s: unknown status %08x\n",
1711 __func__, grxstsr);
1712
1f91b4cc 1713 dwc2_hsotg_dump(hsotg);
5b7d70c6
BD		 1714 break;
1715 }
1716}
1717
1718/**
1f91b4cc 1719 * dwc2_hsotg_ep0_mps - turn max packet size into register setting
5b7d70c6 1720 * @mps: The maximum packet size in bytes.
8b9bc460 1721 */
1f91b4cc 1722static u32 dwc2_hsotg_ep0_mps(unsigned int mps)
5b7d70c6
BD		 1723{
1724 switch (mps) {
1725 case 64:
94cb8fd6 1726 return D0EPCTL_MPS_64;
5b7d70c6 1727 case 32:
94cb8fd6 1728 return D0EPCTL_MPS_32;
5b7d70c6 1729 case 16:
94cb8fd6 1730 return D0EPCTL_MPS_16;
5b7d70c6 1731 case 8:
94cb8fd6 1732 return D0EPCTL_MPS_8;
5b7d70c6
BD		 1733 }
1734
1735 /* bad max packet size, warn and return invalid result */
1736 WARN_ON(1);
1737 return (u32)-1;
1738}
1739
1740/**
1f91b4cc 1741 * dwc2_hsotg_set_ep_maxpacket - set endpoint's max-packet field
5b7d70c6
BD		 1742 * @hsotg: The driver state.
1743 * @ep: The index number of the endpoint
1744 * @mps: The maximum packet size in bytes
1745 *
1746 * Configure the maximum packet size for the given endpoint, updating
1747 * the hardware control registers to reflect this.
1748 */
1f91b4cc 1749static void dwc2_hsotg_set_ep_maxpacket(struct dwc2_hsotg *hsotg,
c6f5c050 1750 unsigned int ep, unsigned int mps, unsigned int dir_in)
5b7d70c6 1751{
1f91b4cc 1752 struct dwc2_hsotg_ep *hs_ep;
5b7d70c6
BD		 1753 void __iomem *regs = hsotg->regs;
1754 u32 mpsval;
4fca54aa 1755 u32 mcval;
5b7d70c6
BD		 1756 u32 reg;
1757
c6f5c050
MYK		 1758 hs_ep = index_to_ep(hsotg, ep, dir_in);
1759 if (!hs_ep)
1760 return;
1761
5b7d70c6
BD		 1762 if (ep == 0) {
1763 /* EP0 is a special case */
1f91b4cc 1764 mpsval = dwc2_hsotg_ep0_mps(mps);
5b7d70c6
BD		 1765 if (mpsval > 3)
1766 goto bad_mps;
e9edd199 1767 hs_ep->ep.maxpacket = mps;
4fca54aa 1768 hs_ep->mc = 1;
5b7d70c6 1769 } else {
47a1685f 1770 mpsval = mps & DXEPCTL_MPS_MASK;
e9edd199 1771 if (mpsval > 1024)
5b7d70c6 1772 goto bad_mps;
4fca54aa
RB		 1773 mcval = ((mps >> 11) & 0x3) + 1;
1774 hs_ep->mc = mcval;
1775 if (mcval > 3)
1776 goto bad_mps;
e9edd199 1777 hs_ep->ep.maxpacket = mpsval;
5b7d70c6
BD		 1778 }
1779
c6f5c050 1780 if (dir_in) {
95c8bc36 1781 reg = dwc2_readl(regs + DIEPCTL(ep));
c6f5c050
MYK		 1782 reg &= ~DXEPCTL_MPS_MASK;
1783 reg |= mpsval;
95c8bc36 1784 dwc2_writel(reg, regs + DIEPCTL(ep));
c6f5c050 1785 } else {
95c8bc36 1786 reg = dwc2_readl(regs + DOEPCTL(ep));
47a1685f 1787 reg &= ~DXEPCTL_MPS_MASK;
659ad60c 1788 reg |= mpsval;
95c8bc36 1789 dwc2_writel(reg, regs + DOEPCTL(ep));
659ad60c 1790 }
5b7d70c6
BD		 1791
1792 return;
1793
1794bad_mps:
1795 dev_err(hsotg->dev, "ep%d: bad mps of %d\n", ep, mps);
1796}
1797
9c39ddc6 1798/**
1f91b4cc 1799 * dwc2_hsotg_txfifo_flush - flush Tx FIFO
9c39ddc6
AT		 1800 * @hsotg: The driver state
1801 * @idx: The index for the endpoint (0..15)
1802 */
1f91b4cc 1803static void dwc2_hsotg_txfifo_flush(struct dwc2_hsotg *hsotg, unsigned int idx)
9c39ddc6
AT		 1804{
1805 int timeout;
1806 int val;
1807
95c8bc36
AS		 1808 dwc2_writel(GRSTCTL_TXFNUM(idx) | GRSTCTL_TXFFLSH,
1809 hsotg->regs + GRSTCTL);
9c39ddc6
AT		 1810
1811 /* wait until the fifo is flushed */
1812 timeout = 100;
1813
1814 while (1) {
95c8bc36 1815 val = dwc2_readl(hsotg->regs + GRSTCTL);
9c39ddc6 1816
47a1685f 1817 if ((val & (GRSTCTL_TXFFLSH)) == 0)
9c39ddc6
AT		 1818 break;
1819
1820 if (--timeout == 0) {
1821 dev_err(hsotg->dev,
1822 "%s: timeout flushing fifo (GRSTCTL=%08x)\n",
1823 __func__, val);
e0cbe595 1824 break;
9c39ddc6
AT		 1825 }
1826
1827 udelay(1);
1828 }
1829}
5b7d70c6
BD		 1830
1831/**
1f91b4cc 1832 * dwc2_hsotg_trytx - check to see if anything needs transmitting
5b7d70c6
BD		 1833 * @hsotg: The driver state
1834 * @hs_ep: The driver endpoint to check.
1835 *
1836 * Check to see if there is a request that has data to send, and if so
1837 * make an attempt to write data into the FIFO.
1838 */
1f91b4cc
FB		 1839static int dwc2_hsotg_trytx(struct dwc2_hsotg *hsotg,
1840 struct dwc2_hsotg_ep *hs_ep)
5b7d70c6 1841{
1f91b4cc 1842 struct dwc2_hsotg_req *hs_req = hs_ep->req;
5b7d70c6 1843
afcf4169
RB		 1844 if (!hs_ep->dir_in || !hs_req) {
1845 /**
1846 * if request is not enqueued, we disable interrupts
1847 * for endpoints, excepting ep0
1848 */
1849 if (hs_ep->index != 0)
1f91b4cc 1850 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index,
afcf4169 1851 hs_ep->dir_in, 0);
5b7d70c6 1852 return 0;
afcf4169 1853 }
5b7d70c6
BD		 1854
1855 if (hs_req->req.actual < hs_req->req.length) {
1856 dev_dbg(hsotg->dev, "trying to write more for ep%d\n",
1857 hs_ep->index);
1f91b4cc 1858 return dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req);
5b7d70c6
BD		 1859 }
1860
1861 return 0;
1862}
1863
1864/**
1f91b4cc 1865 * dwc2_hsotg_complete_in - complete IN transfer
5b7d70c6
BD		 1866 * @hsotg: The device state.
1867 * @hs_ep: The endpoint that has just completed.
1868 *
1869 * An IN transfer has been completed, update the transfer's state and then
1870 * call the relevant completion routines.
1871 */
1f91b4cc
FB		 1872static void dwc2_hsotg_complete_in(struct dwc2_hsotg *hsotg,
1873 struct dwc2_hsotg_ep *hs_ep)
5b7d70c6 1874{
1f91b4cc 1875 struct dwc2_hsotg_req *hs_req = hs_ep->req;
95c8bc36 1876 u32 epsize = dwc2_readl(hsotg->regs + DIEPTSIZ(hs_ep->index));
5b7d70c6
BD		 1877 int size_left, size_done;
1878
1879 if (!hs_req) {
1880 dev_dbg(hsotg->dev, "XferCompl but no req\n");
1881 return;
1882 }
1883
d3ca0259 1884 /* Finish ZLP handling for IN EP0 transactions */
fe0b94ab
MYK		 1885 if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_IN) {
1886 dev_dbg(hsotg->dev, "zlp packet sent\n");
1f91b4cc 1887 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
9e14d0a5
GH		 1888 if (hsotg->test_mode) {
1889 int ret;
1890
1f91b4cc 1891 ret = dwc2_hsotg_set_test_mode(hsotg, hsotg->test_mode);
9e14d0a5
GH		 1892 if (ret < 0) {
1893 dev_dbg(hsotg->dev, "Invalid Test #%d\n",
1894 hsotg->test_mode);
1f91b4cc 1895 dwc2_hsotg_stall_ep0(hsotg);
9e14d0a5
GH		 1896 return;
1897 }
1898 }
1f91b4cc 1899 dwc2_hsotg_enqueue_setup(hsotg);
d3ca0259
LM		 1900 return;
1901 }
1902
8b9bc460
LM		 1903 /*
1904 * Calculate the size of the transfer by checking how much is left
5b7d70c6
BD		 1905 * in the endpoint size register and then working it out from
1906 * the amount we loaded for the transfer.
1907 *
1908 * We do this even for DMA, as the transfer may have incremented
1909 * past the end of the buffer (DMA transfers are always 32bit
1910 * aligned).
1911 */
1912
47a1685f 1913 size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
5b7d70c6
BD		 1914
1915 size_done = hs_ep->size_loaded - size_left;
1916 size_done += hs_ep->last_load;
1917
1918 if (hs_req->req.actual != size_done)
1919 dev_dbg(hsotg->dev, "%s: adjusting size done %d => %d\n",
1920 __func__, hs_req->req.actual, size_done);
1921
1922 hs_req->req.actual = size_done;
d3ca0259
LM		 1923 dev_dbg(hsotg->dev, "req->length:%d req->actual:%d req->zero:%d\n",
1924 hs_req->req.length, hs_req->req.actual, hs_req->req.zero);
1925
5b7d70c6
BD		 1926 if (!size_left && hs_req->req.actual < hs_req->req.length) {
1927 dev_dbg(hsotg->dev, "%s trying more for req...\n", __func__);
1f91b4cc 1928 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true);
fe0b94ab
MYK		 1929 return;
1930 }
1931
f71b5e25 1932 /* Zlp for all endpoints, for ep0 only in DATA IN stage */
8a20fa45 1933 if (hs_ep->send_zlp) {
1f91b4cc 1934 dwc2_hsotg_program_zlp(hsotg, hs_ep);
8a20fa45 1935 hs_ep->send_zlp = 0;
f71b5e25
MYK		 1936 /* transfer will be completed on next complete interrupt */
1937 return;
1938 }
1939
fe0b94ab
MYK		 1940 if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_DATA_IN) {
1941 /* Move to STATUS OUT */
1f91b4cc 1942 dwc2_hsotg_ep0_zlp(hsotg, false);
fe0b94ab
MYK		 1943 return;
1944 }
1945
1f91b4cc 1946 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
5b7d70c6
BD		 1947}
1948
1949/**
1f91b4cc 1950 * dwc2_hsotg_epint - handle an in/out endpoint interrupt
5b7d70c6
BD		 1951 * @hsotg: The driver state
1952 * @idx: The index for the endpoint (0..15)
1953 * @dir_in: Set if this is an IN endpoint
1954 *
1955 * Process and clear any interrupt pending for an individual endpoint
8b9bc460 1956 */
1f91b4cc 1957static void dwc2_hsotg_epint(struct dwc2_hsotg *hsotg, unsigned int idx,
5b7d70c6
BD		 1958 int dir_in)
1959{
1f91b4cc 1960 struct dwc2_hsotg_ep *hs_ep = index_to_ep(hsotg, idx, dir_in);
94cb8fd6
LM		 1961 u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx);
1962 u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx);
1963 u32 epsiz_reg = dir_in ? DIEPTSIZ(idx) : DOEPTSIZ(idx);
5b7d70c6 1964 u32 ints;
1479e841 1965 u32 ctrl;
5b7d70c6 1966
95c8bc36
AS		 1967 ints = dwc2_readl(hsotg->regs + epint_reg);
1968 ctrl = dwc2_readl(hsotg->regs + epctl_reg);
5b7d70c6 1969
a3395f0d 1970 /* Clear endpoint interrupts */
95c8bc36 1971 dwc2_writel(ints, hsotg->regs + epint_reg);
a3395f0d 1972
c6f5c050
MYK		 1973 if (!hs_ep) {
1974 dev_err(hsotg->dev, "%s:Interrupt for unconfigured ep%d(%s)\n",
1975 __func__, idx, dir_in ? "in" : "out");
1976 return;
1977 }
1978
5b7d70c6
BD		 1979 dev_dbg(hsotg->dev, "%s: ep%d(%s) DxEPINT=0x%08x\n",
1980 __func__, idx, dir_in ? "in" : "out", ints);
1981
b787d755
MYK		 1982 /* Don't process XferCompl interrupt if it is a setup packet */
1983 if (idx == 0 && (ints & (DXEPINT_SETUP | DXEPINT_SETUP_RCVD)))
1984 ints &= ~DXEPINT_XFERCOMPL;
1985
47a1685f 1986 if (ints & DXEPINT_XFERCOMPL) {
ec1f9d9f
RB		 1987 hs_ep->has_correct_parity = 1;
1988 if (hs_ep->isochronous && hs_ep->interval == 1)
1989 dwc2_hsotg_change_ep_iso_parity(hsotg, epctl_reg);
1479e841 1990
5b7d70c6 1991 dev_dbg(hsotg->dev,
47a1685f 1992 "%s: XferCompl: DxEPCTL=0x%08x, DXEPTSIZ=%08x\n",
95c8bc36
AS		 1993 __func__, dwc2_readl(hsotg->regs + epctl_reg),
1994 dwc2_readl(hsotg->regs + epsiz_reg));
5b7d70c6 1995
8b9bc460
LM		 1996 /*
1997 * we get OutDone from the FIFO, so we only need to look
1998 * at completing IN requests here
1999 */
5b7d70c6 2000 if (dir_in) {
1f91b4cc 2001 dwc2_hsotg_complete_in(hsotg, hs_ep);
5b7d70c6 2002
c9a64ea8 2003 if (idx == 0 && !hs_ep->req)
1f91b4cc 2004 dwc2_hsotg_enqueue_setup(hsotg);
5b7d70c6 2005 } else if (using_dma(hsotg)) {
8b9bc460
LM		 2006 /*
2007 * We're using DMA, we need to fire an OutDone here
2008 * as we ignore the RXFIFO.
2009 */
5b7d70c6 2010
1f91b4cc 2011 dwc2_hsotg_handle_outdone(hsotg, idx);
5b7d70c6 2012 }
5b7d70c6
BD		 2013 }
2014
47a1685f 2015 if (ints & DXEPINT_EPDISBLD) {
5b7d70c6 2016 dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__);
5b7d70c6 2017
9c39ddc6 2018 if (dir_in) {
95c8bc36 2019 int epctl = dwc2_readl(hsotg->regs + epctl_reg);
9c39ddc6 2020
1f91b4cc 2021 dwc2_hsotg_txfifo_flush(hsotg, hs_ep->fifo_index);
9c39ddc6 2022
47a1685f
DN		 2023 if ((epctl & DXEPCTL_STALL) &&
2024 (epctl & DXEPCTL_EPTYPE_BULK)) {
95c8bc36 2025 int dctl = dwc2_readl(hsotg->regs + DCTL);
9c39ddc6 2026
47a1685f 2027 dctl |= DCTL_CGNPINNAK;
95c8bc36 2028 dwc2_writel(dctl, hsotg->regs + DCTL);
9c39ddc6
AT		 2029 }
2030 }
2031 }
2032
47a1685f 2033 if (ints & DXEPINT_AHBERR)
5b7d70c6 2034 dev_dbg(hsotg->dev, "%s: AHBErr\n", __func__);
5b7d70c6 2035
47a1685f 2036 if (ints & DXEPINT_SETUP) { /* Setup or Timeout */
5b7d70c6
BD		 2037 dev_dbg(hsotg->dev, "%s: Setup/Timeout\n", __func__);
2038
2039 if (using_dma(hsotg) && idx == 0) {
8b9bc460
LM		 2040 /*
2041 * this is the notification we've received a
5b7d70c6
BD		 2042 * setup packet. In non-DMA mode we'd get this
2043 * from the RXFIFO, instead we need to process
8b9bc460
LM		 2044 * the setup here.
2045 */
5b7d70c6
BD		 2046
2047 if (dir_in)
2048 WARN_ON_ONCE(1);
2049 else
1f91b4cc 2050 dwc2_hsotg_handle_outdone(hsotg, 0);
5b7d70c6 2051 }
5b7d70c6
BD		 2052 }
2053
47a1685f 2054 if (ints & DXEPINT_BACK2BACKSETUP)
5b7d70c6 2055 dev_dbg(hsotg->dev, "%s: B2BSetup/INEPNakEff\n", __func__);
5b7d70c6 2056
1479e841 2057 if (dir_in && !hs_ep->isochronous) {
8b9bc460 2058 /* not sure if this is important, but we'll clear it anyway */
26ddef5d 2059 if (ints & DXEPINT_INTKNTXFEMP) {
5b7d70c6
BD		 2060 dev_dbg(hsotg->dev, "%s: ep%d: INTknTXFEmpMsk\n",
2061 __func__, idx);
5b7d70c6
BD		 2062 }
2063
2064 /* this probably means something bad is happening */
26ddef5d 2065 if (ints & DXEPINT_INTKNEPMIS) {
5b7d70c6
BD		 2066 dev_warn(hsotg->dev, "%s: ep%d: INTknEP\n",
2067 __func__, idx);
5b7d70c6 2068 }
10aebc77
BD		 2069
2070 /* FIFO has space or is empty (see GAHBCFG) */
2071 if (hsotg->dedicated_fifos &&
26ddef5d 2072 ints & DXEPINT_TXFEMP) {
10aebc77
BD		 2073 dev_dbg(hsotg->dev, "%s: ep%d: TxFIFOEmpty\n",
2074 __func__, idx);
70fa030f 2075 if (!using_dma(hsotg))
1f91b4cc 2076 dwc2_hsotg_trytx(hsotg, hs_ep);
10aebc77 2077 }
5b7d70c6 2078 }
5b7d70c6
BD		 2079}
2080
2081/**
1f91b4cc 2082 * dwc2_hsotg_irq_enumdone - Handle EnumDone interrupt (enumeration done)
5b7d70c6
BD		 2083 * @hsotg: The device state.
2084 *
2085 * Handle updating the device settings after the enumeration phase has
2086 * been completed.
8b9bc460 2087 */
1f91b4cc 2088static void dwc2_hsotg_irq_enumdone(struct dwc2_hsotg *hsotg)
5b7d70c6 2089{
95c8bc36 2090 u32 dsts = dwc2_readl(hsotg->regs + DSTS);
9b2667f1 2091 int ep0_mps = 0, ep_mps = 8;
5b7d70c6 2092
8b9bc460
LM		 2093 /*
2094 * This should signal the finish of the enumeration phase
5b7d70c6 2095 * of the USB handshaking, so we should now know what rate
8b9bc460
LM		 2096 * we connected at.
2097 */
5b7d70c6
BD		 2098
2099 dev_dbg(hsotg->dev, "EnumDone (DSTS=0x%08x)\n", dsts);
2100
8b9bc460
LM		 2101 /*
2102 * note, since we're limited by the size of transfer on EP0, and
5b7d70c6 2103 * it seems IN transfers must be a even number of packets we do
8b9bc460
LM		 2104 * not advertise a 64byte MPS on EP0.
2105 */
5b7d70c6
BD		 2106
2107 /* catch both EnumSpd_FS and EnumSpd_FS48 */
6d76c92c 2108 switch ((dsts & DSTS_ENUMSPD_MASK) >> DSTS_ENUMSPD_SHIFT) {
47a1685f
DN		 2109 case DSTS_ENUMSPD_FS:
2110 case DSTS_ENUMSPD_FS48:
5b7d70c6 2111 hsotg->gadget.speed = USB_SPEED_FULL;
5b7d70c6 2112 ep0_mps = EP0_MPS_LIMIT;
295538ff 2113 ep_mps = 1023;
5b7d70c6
BD		 2114 break;
2115
47a1685f 2116 case DSTS_ENUMSPD_HS:
5b7d70c6 2117 hsotg->gadget.speed = USB_SPEED_HIGH;
5b7d70c6 2118 ep0_mps = EP0_MPS_LIMIT;
295538ff 2119 ep_mps = 1024;
5b7d70c6
BD		 2120 break;
2121
47a1685f 2122 case DSTS_ENUMSPD_LS:
5b7d70c6 2123 hsotg->gadget.speed = USB_SPEED_LOW;
8b9bc460
LM		 2124 /*
2125 * note, we don't actually support LS in this driver at the
5b7d70c6
BD		 2126 * moment, and the documentation seems to imply that it isn't
2127 * supported by the PHYs on some of the devices.
2128 */
2129 break;
2130 }
e538dfda
MN		 2131 dev_info(hsotg->dev, "new device is %s\n",
2132 usb_speed_string(hsotg->gadget.speed));
5b7d70c6 2133
8b9bc460
LM		 2134 /*
2135 * we should now know the maximum packet size for an
2136 * endpoint, so set the endpoints to a default value.
2137 */
5b7d70c6
BD		 2138
2139 if (ep0_mps) {
2140 int i;
c6f5c050 2141 /* Initialize ep0 for both in and out directions */
1f91b4cc
FB		 2142 dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 1);
2143 dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 0);
c6f5c050
MYK		 2144 for (i = 1; i < hsotg->num_of_eps; i++) {
2145 if (hsotg->eps_in[i])
1f91b4cc 2146 dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps, 1);
c6f5c050 2147 if (hsotg->eps_out[i])
1f91b4cc 2148 dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps, 0);
c6f5c050 2149 }
5b7d70c6
BD		 2150 }
2151
2152 /* ensure after enumeration our EP0 is active */
2153
1f91b4cc 2154 dwc2_hsotg_enqueue_setup(hsotg);
5b7d70c6
BD		 2155
2156 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
95c8bc36
AS		 2157 dwc2_readl(hsotg->regs + DIEPCTL0),
2158 dwc2_readl(hsotg->regs + DOEPCTL0));
5b7d70c6
BD		 2159}
2160
2161/**
2162 * kill_all_requests - remove all requests from the endpoint's queue
2163 * @hsotg: The device state.
2164 * @ep: The endpoint the requests may be on.
2165 * @result: The result code to use.
5b7d70c6
BD		 2166 *
2167 * Go through the requests on the given endpoint and mark them
2168 * completed with the given result code.
2169 */
941fcce4 2170static void kill_all_requests(struct dwc2_hsotg *hsotg,
1f91b4cc 2171 struct dwc2_hsotg_ep *ep,
6b448af4 2172 int result)
5b7d70c6 2173{
1f91b4cc 2174 struct dwc2_hsotg_req *req, *treq;
b203d0a2 2175 unsigned size;
5b7d70c6 2176
6b448af4 2177 ep->req = NULL;
5b7d70c6 2178
6b448af4 2179 list_for_each_entry_safe(req, treq, &ep->queue, queue)
1f91b4cc 2180 dwc2_hsotg_complete_request(hsotg, ep, req,
5b7d70c6 2181 result);
6b448af4 2182
b203d0a2
RB		 2183 if (!hsotg->dedicated_fifos)
2184 return;
95c8bc36 2185 size = (dwc2_readl(hsotg->regs + DTXFSTS(ep->index)) & 0xffff) * 4;
b203d0a2 2186 if (size < ep->fifo_size)
1f91b4cc 2187 dwc2_hsotg_txfifo_flush(hsotg, ep->fifo_index);
5b7d70c6
BD		 2188}
2189
5b7d70c6 2190/**
1f91b4cc 2191 * dwc2_hsotg_disconnect - disconnect service
5b7d70c6
BD		 2192 * @hsotg: The device state.
2193 *
5e891342
LM		 2194 * The device has been disconnected. Remove all current
2195 * transactions and signal the gadget driver that this
2196 * has happened.
8b9bc460 2197 */
1f91b4cc 2198void dwc2_hsotg_disconnect(struct dwc2_hsotg *hsotg)
5b7d70c6
BD		 2199{
2200 unsigned ep;
2201
4ace06e8
MS		 2202 if (!hsotg->connected)
2203 return;
2204
2205 hsotg->connected = 0;
9e14d0a5 2206 hsotg->test_mode = 0;
c6f5c050
MYK		 2207
2208 for (ep = 0; ep < hsotg->num_of_eps; ep++) {
2209 if (hsotg->eps_in[ep])
2210 kill_all_requests(hsotg, hsotg->eps_in[ep],
2211 -ESHUTDOWN);
2212 if (hsotg->eps_out[ep])
2213 kill_all_requests(hsotg, hsotg->eps_out[ep],
2214 -ESHUTDOWN);
2215 }
5b7d70c6
BD		 2216
2217 call_gadget(hsotg, disconnect);
065d3931 2218 hsotg->lx_state = DWC2_L3;
5b7d70c6
BD		 2219}
2220
2221/**
1f91b4cc 2222 * dwc2_hsotg_irq_fifoempty - TX FIFO empty interrupt handler
5b7d70c6
BD		 2223 * @hsotg: The device state:
2224 * @periodic: True if this is a periodic FIFO interrupt
2225 */
1f91b4cc 2226static void dwc2_hsotg_irq_fifoempty(struct dwc2_hsotg *hsotg, bool periodic)
5b7d70c6 2227{
1f91b4cc 2228 struct dwc2_hsotg_ep *ep;
5b7d70c6
BD		 2229 int epno, ret;
2230
2231 /* look through for any more data to transmit */
b3f489b2 2232 for (epno = 0; epno < hsotg->num_of_eps; epno++) {
c6f5c050
MYK		 2233 ep = index_to_ep(hsotg, epno, 1);
2234
2235 if (!ep)
2236 continue;
5b7d70c6
BD		 2237
2238 if (!ep->dir_in)
2239 continue;
2240
2241 if ((periodic && !ep->periodic) ||
2242 (!periodic && ep->periodic))
2243 continue;
2244
1f91b4cc 2245 ret = dwc2_hsotg_trytx(hsotg, ep);
5b7d70c6
BD		 2246 if (ret < 0)
2247 break;
2248 }
2249}
2250
5b7d70c6 2251/* IRQ flags which will trigger a retry around the IRQ loop */
47a1685f
DN		 2252#define IRQ_RETRY_MASK (GINTSTS_NPTXFEMP | \
2253 GINTSTS_PTXFEMP | \
2254 GINTSTS_RXFLVL)
5b7d70c6 2255
8b9bc460 2256/**
1f91b4cc 2257 * dwc2_hsotg_core_init - issue softreset to the core
8b9bc460
LM		 2258 * @hsotg: The device state
2259 *
2260 * Issue a soft reset to the core, and await the core finishing it.
2261 */
1f91b4cc 2262void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg,
643cc4de 2263 bool is_usb_reset)
308d734e 2264{
1ee6903b 2265 u32 intmsk;
643cc4de 2266 u32 val;
ecd9a7ad 2267 u32 usbcfg;
643cc4de 2268
5390d438
MYK		 2269 /* Kill any ep0 requests as controller will be reinitialized */
2270 kill_all_requests(hsotg, hsotg->eps_out[0], -ECONNRESET);
2271
643cc4de 2272 if (!is_usb_reset)
241729ba 2273 if (dwc2_core_reset(hsotg))
86de4895 2274 return;
308d734e
LM		 2275
2276 /*
2277 * we must now enable ep0 ready for host detection and then
2278 * set configuration.
2279 */
2280
ecd9a7ad
PR		 2281 /* keep other bits untouched (so e.g. forced modes are not lost) */
2282 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
2283 usbcfg &= ~(GUSBCFG_TOUTCAL_MASK | GUSBCFG_PHYIF16 | GUSBCFG_SRPCAP |
2284 GUSBCFG_HNPCAP);
2285
308d734e 2286 /* set the PLL on, remove the HNP/SRP and set the PHY */
fa4a8d72 2287 val = (hsotg->phyif == GUSBCFG_PHYIF8) ? 9 : 5;
ecd9a7ad
PR		 2288 usbcfg |= hsotg->phyif | GUSBCFG_TOUTCAL(7) |
2289 (val << GUSBCFG_USBTRDTIM_SHIFT);
2290 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
308d734e 2291
1f91b4cc 2292 dwc2_hsotg_init_fifo(hsotg);
308d734e 2293
643cc4de
GH		 2294 if (!is_usb_reset)
2295 __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON);
308d734e 2296
95c8bc36 2297 dwc2_writel(DCFG_EPMISCNT(1) | DCFG_DEVSPD_HS, hsotg->regs + DCFG);
308d734e
LM		 2298
2299 /* Clear any pending OTG interrupts */
95c8bc36 2300 dwc2_writel(0xffffffff, hsotg->regs + GOTGINT);
308d734e
LM		 2301
2302 /* Clear any pending interrupts */
95c8bc36 2303 dwc2_writel(0xffffffff, hsotg->regs + GINTSTS);
1ee6903b 2304 intmsk = GINTSTS_ERLYSUSP | GINTSTS_SESSREQINT |
47a1685f 2305 GINTSTS_GOUTNAKEFF | GINTSTS_GINNAKEFF |
1ee6903b
GH		 2306 GINTSTS_USBRST | GINTSTS_RESETDET |
2307 GINTSTS_ENUMDONE | GINTSTS_OTGINT |
ec1f9d9f
RB		 2308 GINTSTS_USBSUSP | GINTSTS_WKUPINT |
2309 GINTSTS_INCOMPL_SOIN | GINTSTS_INCOMPL_SOOUT;
1ee6903b
GH		 2310
2311 if (hsotg->core_params->external_id_pin_ctl <= 0)
2312 intmsk |= GINTSTS_CONIDSTSCHNG;
2313
2314 dwc2_writel(intmsk, hsotg->regs + GINTMSK);
308d734e
LM		 2315
2316 if (using_dma(hsotg))
95c8bc36
AS		 2317 dwc2_writel(GAHBCFG_GLBL_INTR_EN | GAHBCFG_DMA_EN |
2318 (GAHBCFG_HBSTLEN_INCR4 << GAHBCFG_HBSTLEN_SHIFT),
2319 hsotg->regs + GAHBCFG);
308d734e 2320 else
95c8bc36
AS		 2321 dwc2_writel(((hsotg->dedicated_fifos) ?
2322 (GAHBCFG_NP_TXF_EMP_LVL |
2323 GAHBCFG_P_TXF_EMP_LVL) : 0) |
2324 GAHBCFG_GLBL_INTR_EN, hsotg->regs + GAHBCFG);
308d734e
LM		 2325
2326 /*
8acc8296
RB		 2327 * If INTknTXFEmpMsk is enabled, it's important to disable ep interrupts
2328 * when we have no data to transfer. Otherwise we get being flooded by
2329 * interrupts.
308d734e
LM		 2330 */
2331
95c8bc36 2332 dwc2_writel(((hsotg->dedicated_fifos && !using_dma(hsotg)) ?
6ff2e832 2333 DIEPMSK_TXFIFOEMPTY | DIEPMSK_INTKNTXFEMPMSK : 0) |
47a1685f
DN		 2334 DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK |
2335 DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK |
2336 DIEPMSK_INTKNEPMISMSK,
2337 hsotg->regs + DIEPMSK);
308d734e
LM		 2338
2339 /*
2340 * don't need XferCompl, we get that from RXFIFO in slave mode. In
2341 * DMA mode we may need this.
2342 */
95c8bc36 2343 dwc2_writel((using_dma(hsotg) ? (DIEPMSK_XFERCOMPLMSK |
47a1685f
DN		 2344 DIEPMSK_TIMEOUTMSK) : 0) |
2345 DOEPMSK_EPDISBLDMSK | DOEPMSK_AHBERRMSK |
2346 DOEPMSK_SETUPMSK,
2347 hsotg->regs + DOEPMSK);
308d734e 2348
95c8bc36 2349 dwc2_writel(0, hsotg->regs + DAINTMSK);
308d734e
LM		 2350
2351 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
95c8bc36
AS		 2352 dwc2_readl(hsotg->regs + DIEPCTL0),
2353 dwc2_readl(hsotg->regs + DOEPCTL0));
308d734e
LM		 2354
2355 /* enable in and out endpoint interrupts */
1f91b4cc 2356 dwc2_hsotg_en_gsint(hsotg, GINTSTS_OEPINT | GINTSTS_IEPINT);
308d734e
LM		 2357
2358 /*
2359 * Enable the RXFIFO when in slave mode, as this is how we collect
2360 * the data. In DMA mode, we get events from the FIFO but also
2361 * things we cannot process, so do not use it.
2362 */
2363 if (!using_dma(hsotg))
1f91b4cc 2364 dwc2_hsotg_en_gsint(hsotg, GINTSTS_RXFLVL);
308d734e
LM		 2365
2366 /* Enable interrupts for EP0 in and out */
1f91b4cc
FB		 2367 dwc2_hsotg_ctrl_epint(hsotg, 0, 0, 1);
2368 dwc2_hsotg_ctrl_epint(hsotg, 0, 1, 1);
308d734e 2369
643cc4de
GH		 2370 if (!is_usb_reset) {
2371 __orr32(hsotg->regs + DCTL, DCTL_PWRONPRGDONE);
2372 udelay(10); /* see openiboot */
2373 __bic32(hsotg->regs + DCTL, DCTL_PWRONPRGDONE);
2374 }
308d734e 2375
95c8bc36 2376 dev_dbg(hsotg->dev, "DCTL=0x%08x\n", dwc2_readl(hsotg->regs + DCTL));
308d734e
LM		 2377
2378 /*
94cb8fd6 2379 * DxEPCTL_USBActEp says RO in manual, but seems to be set by
308d734e
LM		 2380 * writing to the EPCTL register..
2381 */
2382
2383 /* set to read 1 8byte packet */
95c8bc36 2384 dwc2_writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
47a1685f 2385 DXEPTSIZ_XFERSIZE(8), hsotg->regs + DOEPTSIZ0);
308d734e 2386
95c8bc36 2387 dwc2_writel(dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) |
47a1685f
DN		 2388 DXEPCTL_CNAK | DXEPCTL_EPENA |
2389 DXEPCTL_USBACTEP,
94cb8fd6 2390 hsotg->regs + DOEPCTL0);
308d734e
LM		 2391
2392 /* enable, but don't activate EP0in */
95c8bc36 2393 dwc2_writel(dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) |
47a1685f 2394 DXEPCTL_USBACTEP, hsotg->regs + DIEPCTL0);
308d734e 2395
1f91b4cc 2396 dwc2_hsotg_enqueue_setup(hsotg);
308d734e
LM		 2397
2398 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
95c8bc36
AS		 2399 dwc2_readl(hsotg->regs + DIEPCTL0),
2400 dwc2_readl(hsotg->regs + DOEPCTL0));
308d734e
LM		 2401
2402 /* clear global NAKs */
643cc4de
GH		 2403 val = DCTL_CGOUTNAK | DCTL_CGNPINNAK;
2404 if (!is_usb_reset)
2405 val |= DCTL_SFTDISCON;
2406 __orr32(hsotg->regs + DCTL, val);
308d734e
LM		 2407
2408 /* must be at-least 3ms to allow bus to see disconnect */
2409 mdelay(3);
2410
065d3931 2411 hsotg->lx_state = DWC2_L0;
ad38dc5d
MS		 2412}
2413
1f91b4cc 2414static void dwc2_hsotg_core_disconnect(struct dwc2_hsotg *hsotg)
ad38dc5d
MS		 2415{
2416 /* set the soft-disconnect bit */
2417 __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON);
2418}
ac3c81f3 2419
1f91b4cc 2420void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg)
ad38dc5d 2421{
308d734e 2422 /* remove the soft-disconnect and let's go */
47a1685f 2423 __bic32(hsotg->regs + DCTL, DCTL_SFTDISCON);
308d734e
LM		 2424}
2425
5b7d70c6 2426/**
1f91b4cc 2427 * dwc2_hsotg_irq - handle device interrupt
5b7d70c6
BD		 2428 * @irq: The IRQ number triggered
2429 * @pw: The pw value when registered the handler.
2430 */
1f91b4cc 2431static irqreturn_t dwc2_hsotg_irq(int irq, void *pw)
5b7d70c6 2432{
941fcce4 2433 struct dwc2_hsotg *hsotg = pw;
5b7d70c6
BD		 2434 int retry_count = 8;
2435 u32 gintsts;
2436 u32 gintmsk;
2437
ee3de8d7
VM		 2438 if (!dwc2_is_device_mode(hsotg))
2439 return IRQ_NONE;
2440
5ad1d316 2441 spin_lock(&hsotg->lock);
5b7d70c6 2442irq_retry:
95c8bc36
AS		 2443 gintsts = dwc2_readl(hsotg->regs + GINTSTS);
2444 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
5b7d70c6
BD		 2445
2446 dev_dbg(hsotg->dev, "%s: %08x %08x (%08x) retry %d\n",
2447 __func__, gintsts, gintsts & gintmsk, gintmsk, retry_count);
2448
2449 gintsts &= gintmsk;
2450
8fc37b82
MYK		 2451 if (gintsts & GINTSTS_RESETDET) {
2452 dev_dbg(hsotg->dev, "%s: USBRstDet\n", __func__);
2453
2454 dwc2_writel(GINTSTS_RESETDET, hsotg->regs + GINTSTS);
2455
2456 /* This event must be used only if controller is suspended */
2457 if (hsotg->lx_state == DWC2_L2) {
2458 dwc2_exit_hibernation(hsotg, true);
2459 hsotg->lx_state = DWC2_L0;
2460 }
2461 }
2462
2463 if (gintsts & (GINTSTS_USBRST | GINTSTS_RESETDET)) {
2464
2465 u32 usb_status = dwc2_readl(hsotg->regs + GOTGCTL);
2466 u32 connected = hsotg->connected;
2467
2468 dev_dbg(hsotg->dev, "%s: USBRst\n", __func__);
2469 dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n",
2470 dwc2_readl(hsotg->regs + GNPTXSTS));
2471
2472 dwc2_writel(GINTSTS_USBRST, hsotg->regs + GINTSTS);
2473
2474 /* Report disconnection if it is not already done. */
2475 dwc2_hsotg_disconnect(hsotg);
2476
2477 if (usb_status & GOTGCTL_BSESVLD && connected)
2478 dwc2_hsotg_core_init_disconnected(hsotg, true);
2479 }
2480
47a1685f 2481 if (gintsts & GINTSTS_ENUMDONE) {
95c8bc36 2482 dwc2_writel(GINTSTS_ENUMDONE, hsotg->regs + GINTSTS);
a3395f0d 2483
1f91b4cc 2484 dwc2_hsotg_irq_enumdone(hsotg);
5b7d70c6
BD		 2485 }
2486
47a1685f 2487 if (gintsts & (GINTSTS_OEPINT | GINTSTS_IEPINT)) {
95c8bc36
AS		 2488 u32 daint = dwc2_readl(hsotg->regs + DAINT);
2489 u32 daintmsk = dwc2_readl(hsotg->regs + DAINTMSK);
7e804650 2490 u32 daint_out, daint_in;
5b7d70c6
BD		 2491 int ep;
2492
7e804650 2493 daint &= daintmsk;
47a1685f
DN		 2494 daint_out = daint >> DAINT_OUTEP_SHIFT;
2495 daint_in = daint & ~(daint_out << DAINT_OUTEP_SHIFT);
7e804650 2496
5b7d70c6
BD		 2497 dev_dbg(hsotg->dev, "%s: daint=%08x\n", __func__, daint);
2498
cec87f1d
MYK		 2499 for (ep = 0; ep < hsotg->num_of_eps && daint_out;
2500 ep++, daint_out >>= 1) {
5b7d70c6 2501 if (daint_out & 1)
1f91b4cc 2502 dwc2_hsotg_epint(hsotg, ep, 0);
5b7d70c6
BD		 2503 }
2504
cec87f1d
MYK		 2505 for (ep = 0; ep < hsotg->num_of_eps && daint_in;
2506 ep++, daint_in >>= 1) {
5b7d70c6 2507 if (daint_in & 1)
1f91b4cc 2508 dwc2_hsotg_epint(hsotg, ep, 1);
5b7d70c6 2509 }
5b7d70c6
BD		 2510 }
2511
5b7d70c6
BD		 2512 /* check both FIFOs */
2513
47a1685f 2514 if (gintsts & GINTSTS_NPTXFEMP) {
5b7d70c6
BD		 2515 dev_dbg(hsotg->dev, "NPTxFEmp\n");
2516
8b9bc460
LM		 2517 /*
2518 * Disable the interrupt to stop it happening again
5b7d70c6 2519 * unless one of these endpoint routines decides that
8b9bc460
LM		 2520 * it needs re-enabling
2521 */
5b7d70c6 2522
1f91b4cc
FB		 2523 dwc2_hsotg_disable_gsint(hsotg, GINTSTS_NPTXFEMP);
2524 dwc2_hsotg_irq_fifoempty(hsotg, false);
5b7d70c6
BD		 2525 }
2526
47a1685f 2527 if (gintsts & GINTSTS_PTXFEMP) {
5b7d70c6
BD		 2528 dev_dbg(hsotg->dev, "PTxFEmp\n");
2529
94cb8fd6 2530 /* See note in GINTSTS_NPTxFEmp */
5b7d70c6 2531
1f91b4cc
FB		 2532 dwc2_hsotg_disable_gsint(hsotg, GINTSTS_PTXFEMP);
2533 dwc2_hsotg_irq_fifoempty(hsotg, true);
5b7d70c6
BD		 2534 }
2535
47a1685f 2536 if (gintsts & GINTSTS_RXFLVL) {
8b9bc460
LM		 2537 /*
2538 * note, since GINTSTS_RxFLvl doubles as FIFO-not-empty,
1f91b4cc 2539 * we need to retry dwc2_hsotg_handle_rx if this is still
8b9bc460
LM		 2540 * set.
2541 */
5b7d70c6 2542
1f91b4cc 2543 dwc2_hsotg_handle_rx(hsotg);
5b7d70c6
BD		 2544 }
2545
47a1685f 2546 if (gintsts & GINTSTS_ERLYSUSP) {
94cb8fd6 2547 dev_dbg(hsotg->dev, "GINTSTS_ErlySusp\n");
95c8bc36 2548 dwc2_writel(GINTSTS_ERLYSUSP, hsotg->regs + GINTSTS);
5b7d70c6
BD		 2549 }
2550
8b9bc460
LM		 2551 /*
2552 * these next two seem to crop-up occasionally causing the core
5b7d70c6 2553 * to shutdown the USB transfer, so try clearing them and logging
8b9bc460
LM		 2554 * the occurrence.
2555 */
5b7d70c6 2556
47a1685f 2557 if (gintsts & GINTSTS_GOUTNAKEFF) {
5b7d70c6
BD		 2558 dev_info(hsotg->dev, "GOUTNakEff triggered\n");
2559
3be99cd0 2560 __orr32(hsotg->regs + DCTL, DCTL_CGOUTNAK);
a3395f0d 2561
1f91b4cc 2562 dwc2_hsotg_dump(hsotg);
5b7d70c6
BD		 2563 }
2564
47a1685f 2565 if (gintsts & GINTSTS_GINNAKEFF) {
5b7d70c6
BD		 2566 dev_info(hsotg->dev, "GINNakEff triggered\n");
2567
3be99cd0 2568 __orr32(hsotg->regs + DCTL, DCTL_CGNPINNAK);
a3395f0d 2569
1f91b4cc 2570 dwc2_hsotg_dump(hsotg);
5b7d70c6
BD		 2571 }
2572
ec1f9d9f
RB		 2573 if (gintsts & GINTSTS_INCOMPL_SOIN) {
2574 u32 idx, epctl_reg;
2575 struct dwc2_hsotg_ep *hs_ep;
2576
2577 dev_dbg(hsotg->dev, "%s: GINTSTS_INCOMPL_SOIN\n", __func__);
2578 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
2579 hs_ep = hsotg->eps_in[idx];
2580
2581 if (!hs_ep->isochronous || hs_ep->has_correct_parity)
2582 continue;
2583
2584 epctl_reg = DIEPCTL(idx);
2585 dwc2_hsotg_change_ep_iso_parity(hsotg, epctl_reg);
2586 }
2587 dwc2_writel(GINTSTS_INCOMPL_SOIN, hsotg->regs + GINTSTS);
2588 }
2589
2590 if (gintsts & GINTSTS_INCOMPL_SOOUT) {
2591 u32 idx, epctl_reg;
2592 struct dwc2_hsotg_ep *hs_ep;
2593
2594 dev_dbg(hsotg->dev, "%s: GINTSTS_INCOMPL_SOOUT\n", __func__);
2595 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
2596 hs_ep = hsotg->eps_out[idx];
2597
2598 if (!hs_ep->isochronous || hs_ep->has_correct_parity)
2599 continue;
2600
2601 epctl_reg = DOEPCTL(idx);
2602 dwc2_hsotg_change_ep_iso_parity(hsotg, epctl_reg);
2603 }
2604 dwc2_writel(GINTSTS_INCOMPL_SOOUT, hsotg->regs + GINTSTS);
2605 }
2606
8b9bc460
LM		 2607 /*
2608 * if we've had fifo events, we should try and go around the
2609 * loop again to see if there's any point in returning yet.
2610 */
5b7d70c6
BD		 2611
2612 if (gintsts & IRQ_RETRY_MASK && --retry_count > 0)
2613 goto irq_retry;
2614
5ad1d316
LM		 2615 spin_unlock(&hsotg->lock);
2616
5b7d70c6
BD		 2617 return IRQ_HANDLED;
2618}
2619
2620/**
1f91b4cc 2621 * dwc2_hsotg_ep_enable - enable the given endpoint
5b7d70c6
BD		 2622 * @ep: The USB endpint to configure
2623 * @desc: The USB endpoint descriptor to configure with.
2624 *
2625 * This is called from the USB gadget code's usb_ep_enable().
8b9bc460 2626 */
1f91b4cc 2627static int dwc2_hsotg_ep_enable(struct usb_ep *ep,
5b7d70c6
BD		 2628 const struct usb_endpoint_descriptor *desc)
2629{
1f91b4cc 2630 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
941fcce4 2631 struct dwc2_hsotg *hsotg = hs_ep->parent;
5b7d70c6 2632 unsigned long flags;
ca4c55ad 2633 unsigned int index = hs_ep->index;
5b7d70c6
BD		 2634 u32 epctrl_reg;
2635 u32 epctrl;
2636 u32 mps;
ca4c55ad
MYK		 2637 unsigned int dir_in;
2638 unsigned int i, val, size;
19c190f9 2639 int ret = 0;
5b7d70c6
BD		 2640
2641 dev_dbg(hsotg->dev,
2642 "%s: ep %s: a 0x%02x, attr 0x%02x, mps 0x%04x, intr %d\n",
2643 __func__, ep->name, desc->bEndpointAddress, desc->bmAttributes,
2644 desc->wMaxPacketSize, desc->bInterval);
2645
2646 /* not to be called for EP0 */
8c3d6092
VA		 2647 if (index == 0) {
2648 dev_err(hsotg->dev, "%s: called for EP 0\n", __func__);
2649 return -EINVAL;
2650 }
5b7d70c6
BD		 2651
2652 dir_in = (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) ? 1 : 0;
2653 if (dir_in != hs_ep->dir_in) {
2654 dev_err(hsotg->dev, "%s: direction mismatch!\n", __func__);
2655 return -EINVAL;
2656 }
2657
29cc8897 2658 mps = usb_endpoint_maxp(desc);
5b7d70c6 2659
1f91b4cc 2660 /* note, we handle this here instead of dwc2_hsotg_set_ep_maxpacket */
5b7d70c6 2661
94cb8fd6 2662 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
95c8bc36 2663 epctrl = dwc2_readl(hsotg->regs + epctrl_reg);
5b7d70c6
BD		 2664
2665 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x from 0x%08x\n",
2666 __func__, epctrl, epctrl_reg);
2667
22258f49 2668 spin_lock_irqsave(&hsotg->lock, flags);
5b7d70c6 2669
47a1685f
DN		 2670 epctrl &= ~(DXEPCTL_EPTYPE_MASK | DXEPCTL_MPS_MASK);
2671 epctrl |= DXEPCTL_MPS(mps);
5b7d70c6 2672
8b9bc460
LM		 2673 /*
2674 * mark the endpoint as active, otherwise the core may ignore
2675 * transactions entirely for this endpoint
2676 */
47a1685f 2677 epctrl |= DXEPCTL_USBACTEP;
5b7d70c6 2678
8b9bc460
LM		 2679 /*
2680 * set the NAK status on the endpoint, otherwise we might try and
5b7d70c6
BD		 2681 * do something with data that we've yet got a request to process
2682 * since the RXFIFO will take data for an endpoint even if the
2683 * size register hasn't been set.
2684 */
2685
47a1685f 2686 epctrl |= DXEPCTL_SNAK;
5b7d70c6
BD		 2687
2688 /* update the endpoint state */
1f91b4cc 2689 dwc2_hsotg_set_ep_maxpacket(hsotg, hs_ep->index, mps, dir_in);
5b7d70c6
BD		 2690
2691 /* default, set to non-periodic */
1479e841 2692 hs_ep->isochronous = 0;
5b7d70c6 2693 hs_ep->periodic = 0;
a18ed7b0 2694 hs_ep->halted = 0;
1479e841 2695 hs_ep->interval = desc->bInterval;
4fca54aa 2696
5b7d70c6
BD		 2697 switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
2698 case USB_ENDPOINT_XFER_ISOC:
47a1685f
DN		 2699 epctrl |= DXEPCTL_EPTYPE_ISO;
2700 epctrl |= DXEPCTL_SETEVENFR;
1479e841 2701 hs_ep->isochronous = 1;
142bd33f 2702 hs_ep->interval = 1 << (desc->bInterval - 1);
1479e841
RB		 2703 if (dir_in)
2704 hs_ep->periodic = 1;
2705 break;
5b7d70c6
BD		 2706
2707 case USB_ENDPOINT_XFER_BULK:
47a1685f 2708 epctrl |= DXEPCTL_EPTYPE_BULK;
5b7d70c6
BD		 2709 break;
2710
2711 case USB_ENDPOINT_XFER_INT:
b203d0a2 2712 if (dir_in)
5b7d70c6 2713 hs_ep->periodic = 1;
5b7d70c6 2714
142bd33f
VM		 2715 if (hsotg->gadget.speed == USB_SPEED_HIGH)
2716 hs_ep->interval = 1 << (desc->bInterval - 1);
2717
47a1685f 2718 epctrl |= DXEPCTL_EPTYPE_INTERRUPT;
5b7d70c6
BD		 2719 break;
2720
2721 case USB_ENDPOINT_XFER_CONTROL:
47a1685f 2722 epctrl |= DXEPCTL_EPTYPE_CONTROL;
5b7d70c6
BD		 2723 break;
2724 }
2725
4556e12c
MYK		 2726 /* If fifo is already allocated for this ep */
2727 if (hs_ep->fifo_index) {
2728 size = hs_ep->ep.maxpacket * hs_ep->mc;
2729 /* If bigger fifo is required deallocate current one */
2730 if (size > hs_ep->fifo_size) {
2731 hsotg->fifo_map &= ~(1 << hs_ep->fifo_index);
2732 hs_ep->fifo_index = 0;
2733 hs_ep->fifo_size = 0;
2734 }
2735 }
2736
8b9bc460
LM		 2737 /*
2738 * if the hardware has dedicated fifos, we must give each IN EP
10aebc77
BD		 2739 * a unique tx-fifo even if it is non-periodic.
2740 */
4556e12c 2741 if (dir_in && hsotg->dedicated_fifos && !hs_ep->fifo_index) {
ca4c55ad
MYK		 2742 u32 fifo_index = 0;
2743 u32 fifo_size = UINT_MAX;
b203d0a2 2744 size = hs_ep->ep.maxpacket*hs_ep->mc;
5f2196bd 2745 for (i = 1; i < hsotg->num_of_eps; ++i) {
b203d0a2
RB		 2746 if (hsotg->fifo_map & (1<<i))
2747 continue;
95c8bc36 2748 val = dwc2_readl(hsotg->regs + DPTXFSIZN(i));
b203d0a2
RB		 2749 val = (val >> FIFOSIZE_DEPTH_SHIFT)*4;
2750 if (val < size)
2751 continue;
ca4c55ad
MYK		 2752 /* Search for smallest acceptable fifo */
2753 if (val < fifo_size) {
2754 fifo_size = val;
2755 fifo_index = i;
2756 }
b203d0a2 2757 }
ca4c55ad 2758 if (!fifo_index) {
5f2196bd
MYK		 2759 dev_err(hsotg->dev,
2760 "%s: No suitable fifo found\n", __func__);
b585a48b
SM		 2761 ret = -ENOMEM;
2762 goto error;
2763 }
ca4c55ad
MYK		 2764 hsotg->fifo_map |= 1 << fifo_index;
2765 epctrl |= DXEPCTL_TXFNUM(fifo_index);
2766 hs_ep->fifo_index = fifo_index;
2767 hs_ep->fifo_size = fifo_size;
b203d0a2 2768 }
10aebc77 2769
5b7d70c6
BD		 2770 /* for non control endpoints, set PID to D0 */
2771 if (index)
47a1685f 2772 epctrl |= DXEPCTL_SETD0PID;
5b7d70c6
BD		 2773
2774 dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n",
2775 __func__, epctrl);
2776
95c8bc36 2777 dwc2_writel(epctrl, hsotg->regs + epctrl_reg);
5b7d70c6 2778 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x\n",
95c8bc36 2779 __func__, dwc2_readl(hsotg->regs + epctrl_reg));
5b7d70c6
BD		 2780
2781 /* enable the endpoint interrupt */
1f91b4cc 2782 dwc2_hsotg_ctrl_epint(hsotg, index, dir_in, 1);
5b7d70c6 2783
b585a48b 2784error:
22258f49 2785 spin_unlock_irqrestore(&hsotg->lock, flags);
19c190f9 2786 return ret;
5b7d70c6
BD		 2787}
2788
8b9bc460 2789/**
1f91b4cc 2790 * dwc2_hsotg_ep_disable - disable given endpoint
8b9bc460
LM		 2791 * @ep: The endpoint to disable.
2792 */
1f91b4cc 2793static int dwc2_hsotg_ep_disable(struct usb_ep *ep)
5b7d70c6 2794{
1f91b4cc 2795 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
941fcce4 2796 struct dwc2_hsotg *hsotg = hs_ep->parent;
5b7d70c6
BD		 2797 int dir_in = hs_ep->dir_in;
2798 int index = hs_ep->index;
2799 unsigned long flags;
2800 u32 epctrl_reg;
2801 u32 ctrl;
2802
1e011293 2803 dev_dbg(hsotg->dev, "%s(ep %p)\n", __func__, ep);
5b7d70c6 2804
c6f5c050 2805 if (ep == &hsotg->eps_out[0]->ep) {
5b7d70c6
BD		 2806 dev_err(hsotg->dev, "%s: called for ep0\n", __func__);
2807 return -EINVAL;
2808 }
2809
94cb8fd6 2810 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
5b7d70c6 2811
5ad1d316 2812 spin_lock_irqsave(&hsotg->lock, flags);
5b7d70c6 2813
b203d0a2
RB		 2814 hsotg->fifo_map &= ~(1<<hs_ep->fifo_index);
2815 hs_ep->fifo_index = 0;
2816 hs_ep->fifo_size = 0;
5b7d70c6 2817
95c8bc36 2818 ctrl = dwc2_readl(hsotg->regs + epctrl_reg);
47a1685f
DN		 2819 ctrl &= ~DXEPCTL_EPENA;
2820 ctrl &= ~DXEPCTL_USBACTEP;
2821 ctrl |= DXEPCTL_SNAK;
5b7d70c6
BD		 2822
2823 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
95c8bc36 2824 dwc2_writel(ctrl, hsotg->regs + epctrl_reg);
5b7d70c6
BD		 2825
2826 /* disable endpoint interrupts */
1f91b4cc 2827 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 0);
5b7d70c6 2828
1141ea01
MYK		 2829 /* terminate all requests with shutdown */
2830 kill_all_requests(hsotg, hs_ep, -ESHUTDOWN);
2831
22258f49 2832 spin_unlock_irqrestore(&hsotg->lock, flags);
5b7d70c6
BD		 2833 return 0;
2834}
2835
2836/**
2837 * on_list - check request is on the given endpoint
2838 * @ep: The endpoint to check.
2839 * @test: The request to test if it is on the endpoint.
8b9bc460 2840 */
1f91b4cc 2841static bool on_list(struct dwc2_hsotg_ep *ep, struct dwc2_hsotg_req *test)
5b7d70c6 2842{
1f91b4cc 2843 struct dwc2_hsotg_req *req, *treq;
5b7d70c6
BD		 2844
2845 list_for_each_entry_safe(req, treq, &ep->queue, queue) {
2846 if (req == test)
2847 return true;
2848 }
2849
2850 return false;
2851}
2852
c524dd5f
MYK		 2853static int dwc2_hsotg_wait_bit_set(struct dwc2_hsotg *hs_otg, u32 reg,
2854 u32 bit, u32 timeout)
2855{
2856 u32 i;
2857
2858 for (i = 0; i < timeout; i++) {
2859 if (dwc2_readl(hs_otg->regs + reg) & bit)
2860 return 0;
2861 udelay(1);
2862 }
2863
2864 return -ETIMEDOUT;
2865}
2866
2867static void dwc2_hsotg_ep_stop_xfr(struct dwc2_hsotg *hsotg,
2868 struct dwc2_hsotg_ep *hs_ep)
2869{
2870 u32 epctrl_reg;
2871 u32 epint_reg;
2872
2873 epctrl_reg = hs_ep->dir_in ? DIEPCTL(hs_ep->index) :
2874 DOEPCTL(hs_ep->index);
2875 epint_reg = hs_ep->dir_in ? DIEPINT(hs_ep->index) :
2876 DOEPINT(hs_ep->index);
2877
2878 dev_dbg(hsotg->dev, "%s: stopping transfer on %s\n", __func__,
2879 hs_ep->name);
2880 if (hs_ep->dir_in) {
2881 __orr32(hsotg->regs + epctrl_reg, DXEPCTL_SNAK);
2882 /* Wait for Nak effect */
2883 if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg,
2884 DXEPINT_INEPNAKEFF, 100))
2885 dev_warn(hsotg->dev,
2886 "%s: timeout DIEPINT.NAKEFF\n", __func__);
2887 } else {
6b58cb07
VM		 2888 if (!(dwc2_readl(hsotg->regs + GINTSTS) & GINTSTS_GOUTNAKEFF))
2889 __orr32(hsotg->regs + DCTL, DCTL_SGOUTNAK);
c524dd5f
MYK		 2890
2891 /* Wait for global nak to take effect */
2892 if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS,
0676c7e7 2893 GINTSTS_GOUTNAKEFF, 100))
c524dd5f 2894 dev_warn(hsotg->dev,
0676c7e7 2895 "%s: timeout GINTSTS.GOUTNAKEFF\n", __func__);
c524dd5f
MYK		 2896 }
2897
2898 /* Disable ep */
2899 __orr32(hsotg->regs + epctrl_reg, DXEPCTL_EPDIS | DXEPCTL_SNAK);
2900
2901 /* Wait for ep to be disabled */
2902 if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg, DXEPINT_EPDISBLD, 100))
2903 dev_warn(hsotg->dev,
2904 "%s: timeout DOEPCTL.EPDisable\n", __func__);
2905
2906 if (hs_ep->dir_in) {
2907 if (hsotg->dedicated_fifos) {
2908 dwc2_writel(GRSTCTL_TXFNUM(hs_ep->fifo_index) |
2909 GRSTCTL_TXFFLSH, hsotg->regs + GRSTCTL);
2910 /* Wait for fifo flush */
2911 if (dwc2_hsotg_wait_bit_set(hsotg, GRSTCTL,
2912 GRSTCTL_TXFFLSH, 100))
2913 dev_warn(hsotg->dev,
2914 "%s: timeout flushing fifos\n",
2915 __func__);
2916 }
2917 /* TODO: Flush shared tx fifo */
2918 } else {
2919 /* Remove global NAKs */
0676c7e7 2920 __bic32(hsotg->regs + DCTL, DCTL_SGOUTNAK);
c524dd5f
MYK		 2921 }
2922}
2923
8b9bc460 2924/**
1f91b4cc 2925 * dwc2_hsotg_ep_dequeue - dequeue given endpoint
8b9bc460
LM		 2926 * @ep: The endpoint to dequeue.
2927 * @req: The request to be removed from a queue.
2928 */
1f91b4cc 2929static int dwc2_hsotg_ep_dequeue(struct usb_ep *ep, struct usb_request *req)
5b7d70c6 2930{
1f91b4cc
FB		 2931 struct dwc2_hsotg_req *hs_req = our_req(req);
2932 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
941fcce4 2933 struct dwc2_hsotg *hs = hs_ep->parent;
5b7d70c6
BD		 2934 unsigned long flags;
2935
1e011293 2936 dev_dbg(hs->dev, "ep_dequeue(%p,%p)\n", ep, req);
5b7d70c6 2937
22258f49 2938 spin_lock_irqsave(&hs->lock, flags);
5b7d70c6
BD		 2939
2940 if (!on_list(hs_ep, hs_req)) {
22258f49 2941 spin_unlock_irqrestore(&hs->lock, flags);
5b7d70c6
BD		 2942 return -EINVAL;
2943 }
2944
c524dd5f
MYK		 2945 /* Dequeue already started request */
2946 if (req == &hs_ep->req->req)
2947 dwc2_hsotg_ep_stop_xfr(hs, hs_ep);
2948
1f91b4cc 2949 dwc2_hsotg_complete_request(hs, hs_ep, hs_req, -ECONNRESET);
22258f49 2950 spin_unlock_irqrestore(&hs->lock, flags);
5b7d70c6
BD		 2951
2952 return 0;
2953}
2954
8b9bc460 2955/**
1f91b4cc 2956 * dwc2_hsotg_ep_sethalt - set halt on a given endpoint
8b9bc460
LM		 2957 * @ep: The endpoint to set halt.
2958 * @value: Set or unset the halt.
51da43b5
VA		 2959 * @now: If true, stall the endpoint now. Otherwise return -EAGAIN if
2960 * the endpoint is busy processing requests.
2961 *
2962 * We need to stall the endpoint immediately if request comes from set_feature
2963 * protocol command handler.
8b9bc460 2964 */
51da43b5 2965static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now)
5b7d70c6 2966{
1f91b4cc 2967 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
941fcce4 2968 struct dwc2_hsotg *hs = hs_ep->parent;
5b7d70c6 2969 int index = hs_ep->index;
5b7d70c6
BD		 2970 u32 epreg;
2971 u32 epctl;
9c39ddc6 2972 u32 xfertype;
5b7d70c6
BD		 2973
2974 dev_info(hs->dev, "%s(ep %p %s, %d)\n", __func__, ep, ep->name, value);
2975
c9f721b2
RB		 2976 if (index == 0) {
2977 if (value)
1f91b4cc 2978 dwc2_hsotg_stall_ep0(hs);
c9f721b2
RB		 2979 else
2980 dev_warn(hs->dev,
2981 "%s: can't clear halt on ep0\n", __func__);
2982 return 0;
2983 }
2984
15186f10
VA		 2985 if (hs_ep->isochronous) {
2986 dev_err(hs->dev, "%s is Isochronous Endpoint\n", ep->name);
2987 return -EINVAL;
2988 }
2989
51da43b5
VA		 2990 if (!now && value && !list_empty(&hs_ep->queue)) {
2991 dev_dbg(hs->dev, "%s request is pending, cannot halt\n",
2992 ep->name);
2993 return -EAGAIN;
2994 }
2995
c6f5c050
MYK		 2996 if (hs_ep->dir_in) {
2997 epreg = DIEPCTL(index);
95c8bc36 2998 epctl = dwc2_readl(hs->regs + epreg);
c6f5c050
MYK		 2999
3000 if (value) {
5a350d53 3001 epctl |= DXEPCTL_STALL | DXEPCTL_SNAK;
c6f5c050
MYK		 3002 if (epctl & DXEPCTL_EPENA)
3003 epctl |= DXEPCTL_EPDIS;
3004 } else {
3005 epctl &= ~DXEPCTL_STALL;
3006 xfertype = epctl & DXEPCTL_EPTYPE_MASK;
3007 if (xfertype == DXEPCTL_EPTYPE_BULK ||
3008 xfertype == DXEPCTL_EPTYPE_INTERRUPT)
3009 epctl |= DXEPCTL_SETD0PID;
3010 }
95c8bc36 3011 dwc2_writel(epctl, hs->regs + epreg);
9c39ddc6 3012 } else {
5b7d70c6 3013
c6f5c050 3014 epreg = DOEPCTL(index);
95c8bc36 3015 epctl = dwc2_readl(hs->regs + epreg);
5b7d70c6 3016
c6f5c050
MYK		 3017 if (value)
3018 epctl |= DXEPCTL_STALL;
3019 else {
3020 epctl &= ~DXEPCTL_STALL;
3021 xfertype = epctl & DXEPCTL_EPTYPE_MASK;
3022 if (xfertype == DXEPCTL_EPTYPE_BULK ||
3023 xfertype == DXEPCTL_EPTYPE_INTERRUPT)
3024 epctl |= DXEPCTL_SETD0PID;
3025 }
95c8bc36 3026 dwc2_writel(epctl, hs->regs + epreg);
9c39ddc6 3027 }
5b7d70c6 3028
a18ed7b0
RB		 3029 hs_ep->halted = value;
3030
5b7d70c6
BD		 3031 return 0;
3032}
3033
5ad1d316 3034/**
1f91b4cc 3035 * dwc2_hsotg_ep_sethalt_lock - set halt on a given endpoint with lock held
5ad1d316
LM		 3036 * @ep: The endpoint to set halt.
3037 * @value: Set or unset the halt.
3038 */
1f91b4cc 3039static int dwc2_hsotg_ep_sethalt_lock(struct usb_ep *ep, int value)
5ad1d316 3040{
1f91b4cc 3041 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
941fcce4 3042 struct dwc2_hsotg *hs = hs_ep->parent;
5ad1d316
LM		 3043 unsigned long flags = 0;
3044 int ret = 0;
3045
3046 spin_lock_irqsave(&hs->lock, flags);
51da43b5 3047 ret = dwc2_hsotg_ep_sethalt(ep, value, false);
5ad1d316
LM		 3048 spin_unlock_irqrestore(&hs->lock, flags);
3049
3050 return ret;
3051}
3052
1f91b4cc
FB		 3053static struct usb_ep_ops dwc2_hsotg_ep_ops = {
3054 .enable = dwc2_hsotg_ep_enable,
3055 .disable = dwc2_hsotg_ep_disable,
3056 .alloc_request = dwc2_hsotg_ep_alloc_request,
3057 .free_request = dwc2_hsotg_ep_free_request,
3058 .queue = dwc2_hsotg_ep_queue_lock,
3059 .dequeue = dwc2_hsotg_ep_dequeue,
3060 .set_halt = dwc2_hsotg_ep_sethalt_lock,
25985edc 3061 /* note, don't believe we have any call for the fifo routines */
5b7d70c6
BD		 3062};
3063
8b9bc460 3064/**
1f91b4cc 3065 * dwc2_hsotg_init - initalize the usb core
8b9bc460
LM		 3066 * @hsotg: The driver state
3067 */
1f91b4cc 3068static void dwc2_hsotg_init(struct dwc2_hsotg *hsotg)
b3f489b2 3069{
fa4a8d72 3070 u32 trdtim;
ecd9a7ad 3071 u32 usbcfg;
b3f489b2
LM		 3072 /* unmask subset of endpoint interrupts */
3073
95c8bc36
AS		 3074 dwc2_writel(DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK |
3075 DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK,
3076 hsotg->regs + DIEPMSK);
b3f489b2 3077
95c8bc36
AS		 3078 dwc2_writel(DOEPMSK_SETUPMSK | DOEPMSK_AHBERRMSK |
3079 DOEPMSK_EPDISBLDMSK | DOEPMSK_XFERCOMPLMSK,
3080 hsotg->regs + DOEPMSK);
b3f489b2 3081
95c8bc36 3082 dwc2_writel(0, hsotg->regs + DAINTMSK);
b3f489b2
LM		 3083
3084 /* Be in disconnected state until gadget is registered */
47a1685f 3085 __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON);
b3f489b2 3086
b3f489b2
LM		 3087 /* setup fifos */
3088
3089 dev_dbg(hsotg->dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
95c8bc36
AS		 3090 dwc2_readl(hsotg->regs + GRXFSIZ),
3091 dwc2_readl(hsotg->regs + GNPTXFSIZ));
b3f489b2 3092
1f91b4cc 3093 dwc2_hsotg_init_fifo(hsotg);
b3f489b2 3094
ecd9a7ad
PR		 3095 /* keep other bits untouched (so e.g. forced modes are not lost) */
3096 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
3097 usbcfg &= ~(GUSBCFG_TOUTCAL_MASK | GUSBCFG_PHYIF16 | GUSBCFG_SRPCAP |
3098 GUSBCFG_HNPCAP);
3099
b3f489b2 3100 /* set the PLL on, remove the HNP/SRP and set the PHY */
fa4a8d72 3101 trdtim = (hsotg->phyif == GUSBCFG_PHYIF8) ? 9 : 5;
ecd9a7ad
PR		 3102 usbcfg |= hsotg->phyif | GUSBCFG_TOUTCAL(7) |
3103 (trdtim << GUSBCFG_USBTRDTIM_SHIFT);
3104 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
b3f489b2 3105
f5090044
GH		 3106 if (using_dma(hsotg))
3107 __orr32(hsotg->regs + GAHBCFG, GAHBCFG_DMA_EN);
b3f489b2
LM		 3108}
3109
8b9bc460 3110/**
1f91b4cc 3111 * dwc2_hsotg_udc_start - prepare the udc for work
8b9bc460
LM		 3112 * @gadget: The usb gadget state
3113 * @driver: The usb gadget driver
3114 *
3115 * Perform initialization to prepare udc device and driver
3116 * to work.
3117 */
1f91b4cc 3118static int dwc2_hsotg_udc_start(struct usb_gadget *gadget,
f65f0f10 3119 struct usb_gadget_driver *driver)
5b7d70c6 3120{
941fcce4 3121 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
5b9451f8 3122 unsigned long flags;
5b7d70c6
BD		 3123 int ret;
3124
3125 if (!hsotg) {
a023da33 3126 pr_err("%s: called with no device\n", __func__);
5b7d70c6
BD		 3127 return -ENODEV;
3128 }
3129
3130 if (!driver) {
3131 dev_err(hsotg->dev, "%s: no driver\n", __func__);
3132 return -EINVAL;
3133 }
3134
7177aed4 3135 if (driver->max_speed < USB_SPEED_FULL)
5b7d70c6 3136 dev_err(hsotg->dev, "%s: bad speed\n", __func__);
5b7d70c6 3137
f65f0f10 3138 if (!driver->setup) {
5b7d70c6
BD		 3139 dev_err(hsotg->dev, "%s: missing entry points\n", __func__);
3140 return -EINVAL;
3141 }
3142
3143 WARN_ON(hsotg->driver);
3144
3145 driver->driver.bus = NULL;
3146 hsotg->driver = driver;
7d7b2292 3147 hsotg->gadget.dev.of_node = hsotg->dev->of_node;
5b7d70c6
BD		 3148 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
3149
09a75e85
MS		 3150 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) {
3151 ret = dwc2_lowlevel_hw_enable(hsotg);
3152 if (ret)
3153 goto err;
5b7d70c6
BD		 3154 }
3155
f6c01592
GH		 3156 if (!IS_ERR_OR_NULL(hsotg->uphy))
3157 otg_set_peripheral(hsotg->uphy->otg, &hsotg->gadget);
c816c47f 3158
5b9451f8 3159 spin_lock_irqsave(&hsotg->lock, flags);
1f91b4cc
FB		 3160 dwc2_hsotg_init(hsotg);
3161 dwc2_hsotg_core_init_disconnected(hsotg, false);
dc6e69e6 3162 hsotg->enabled = 0;
5b9451f8
MS		 3163 spin_unlock_irqrestore(&hsotg->lock, flags);
3164
5b7d70c6 3165 dev_info(hsotg->dev, "bound driver %s\n", driver->driver.name);
5b9451f8 3166
5b7d70c6
BD		 3167 return 0;
3168
3169err:
3170 hsotg->driver = NULL;
5b7d70c6
BD		 3171 return ret;
3172}
3173
8b9bc460 3174/**
1f91b4cc 3175 * dwc2_hsotg_udc_stop - stop the udc
8b9bc460
LM		 3176 * @gadget: The usb gadget state
3177 * @driver: The usb gadget driver
3178 *
3179 * Stop udc hw block and stay tunned for future transmissions
3180 */
1f91b4cc 3181static int dwc2_hsotg_udc_stop(struct usb_gadget *gadget)
5b7d70c6 3182{
941fcce4 3183 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
2b19a52c 3184 unsigned long flags = 0;
5b7d70c6
BD		 3185 int ep;
3186
3187 if (!hsotg)
3188 return -ENODEV;
3189
5b7d70c6 3190 /* all endpoints should be shutdown */
c6f5c050
MYK		 3191 for (ep = 1; ep < hsotg->num_of_eps; ep++) {
3192 if (hsotg->eps_in[ep])
1f91b4cc 3193 dwc2_hsotg_ep_disable(&hsotg->eps_in[ep]->ep);
c6f5c050 3194 if (hsotg->eps_out[ep])
1f91b4cc 3195 dwc2_hsotg_ep_disable(&hsotg->eps_out[ep]->ep);
c6f5c050 3196 }
5b7d70c6 3197
2b19a52c
LM		 3198 spin_lock_irqsave(&hsotg->lock, flags);
3199
32805c35 3200 hsotg->driver = NULL;
5b7d70c6 3201 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
dc6e69e6 3202 hsotg->enabled = 0;
5b7d70c6 3203
2b19a52c
LM		 3204 spin_unlock_irqrestore(&hsotg->lock, flags);
3205
f6c01592
GH		 3206 if (!IS_ERR_OR_NULL(hsotg->uphy))
3207 otg_set_peripheral(hsotg->uphy->otg, NULL);
c816c47f 3208
09a75e85
MS		 3209 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
3210 dwc2_lowlevel_hw_disable(hsotg);
5b7d70c6
BD		 3211
3212 return 0;
3213}
5b7d70c6 3214
8b9bc460 3215/**
1f91b4cc 3216 * dwc2_hsotg_gadget_getframe - read the frame number
8b9bc460
LM		 3217 * @gadget: The usb gadget state
3218 *
3219 * Read the {micro} frame number
3220 */
1f91b4cc 3221static int dwc2_hsotg_gadget_getframe(struct usb_gadget *gadget)
5b7d70c6 3222{
1f91b4cc 3223 return dwc2_hsotg_read_frameno(to_hsotg(gadget));
5b7d70c6
BD		 3224}
3225
a188b689 3226/**
1f91b4cc 3227 * dwc2_hsotg_pullup - connect/disconnect the USB PHY
a188b689
LM		 3228 * @gadget: The usb gadget state
3229 * @is_on: Current state of the USB PHY
3230 *
3231 * Connect/Disconnect the USB PHY pullup
3232 */
1f91b4cc 3233static int dwc2_hsotg_pullup(struct usb_gadget *gadget, int is_on)
a188b689 3234{
941fcce4 3235 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
a188b689
LM		 3236 unsigned long flags = 0;
3237
77ba9119
GH		 3238 dev_dbg(hsotg->dev, "%s: is_on: %d op_state: %d\n", __func__, is_on,
3239 hsotg->op_state);
3240
3241 /* Don't modify pullup state while in host mode */
3242 if (hsotg->op_state != OTG_STATE_B_PERIPHERAL) {
3243 hsotg->enabled = is_on;
3244 return 0;
3245 }
a188b689
LM		 3246
3247 spin_lock_irqsave(&hsotg->lock, flags);
3248 if (is_on) {
dc6e69e6 3249 hsotg->enabled = 1;
1f91b4cc
FB		 3250 dwc2_hsotg_core_init_disconnected(hsotg, false);
3251 dwc2_hsotg_core_connect(hsotg);
a188b689 3252 } else {
1f91b4cc
FB		 3253 dwc2_hsotg_core_disconnect(hsotg);
3254 dwc2_hsotg_disconnect(hsotg);
dc6e69e6 3255 hsotg->enabled = 0;
a188b689
LM		 3256 }
3257
3258 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
3259 spin_unlock_irqrestore(&hsotg->lock, flags);
3260
3261 return 0;
3262}
3263
1f91b4cc 3264static int dwc2_hsotg_vbus_session(struct usb_gadget *gadget, int is_active)
83d98223
GH		 3265{
3266 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
3267 unsigned long flags;
3268
3269 dev_dbg(hsotg->dev, "%s: is_active: %d\n", __func__, is_active);
3270 spin_lock_irqsave(&hsotg->lock, flags);
3271
61f7223b
GH		 3272 /*
3273 * If controller is hibernated, it must exit from hibernation
3274 * before being initialized / de-initialized
3275 */
3276 if (hsotg->lx_state == DWC2_L2)
3277 dwc2_exit_hibernation(hsotg, false);
3278
83d98223 3279 if (is_active) {
cd0e641c 3280 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
065d3931 3281
1f91b4cc 3282 dwc2_hsotg_core_init_disconnected(hsotg, false);
83d98223 3283 if (hsotg->enabled)
1f91b4cc 3284 dwc2_hsotg_core_connect(hsotg);
83d98223 3285 } else {
1f91b4cc
FB		 3286 dwc2_hsotg_core_disconnect(hsotg);
3287 dwc2_hsotg_disconnect(hsotg);
83d98223
GH		 3288 }
3289
3290 spin_unlock_irqrestore(&hsotg->lock, flags);
3291 return 0;
3292}
3293
596d696a 3294/**
1f91b4cc 3295 * dwc2_hsotg_vbus_draw - report bMaxPower field
596d696a
GH		 3296 * @gadget: The usb gadget state
3297 * @mA: Amount of current
3298 *
3299 * Report how much power the device may consume to the phy.
3300 */
1f91b4cc 3301static int dwc2_hsotg_vbus_draw(struct usb_gadget *gadget, unsigned mA)
596d696a
GH		 3302{
3303 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
3304
3305 if (IS_ERR_OR_NULL(hsotg->uphy))
3306 return -ENOTSUPP;
3307 return usb_phy_set_power(hsotg->uphy, mA);
3308}
3309
1f91b4cc
FB		 3310static const struct usb_gadget_ops dwc2_hsotg_gadget_ops = {
3311 .get_frame = dwc2_hsotg_gadget_getframe,
3312 .udc_start = dwc2_hsotg_udc_start,
3313 .udc_stop = dwc2_hsotg_udc_stop,
3314 .pullup = dwc2_hsotg_pullup,
3315 .vbus_session = dwc2_hsotg_vbus_session,
3316 .vbus_draw = dwc2_hsotg_vbus_draw,
5b7d70c6
BD		 3317};
3318
3319/**
1f91b4cc 3320 * dwc2_hsotg_initep - initialise a single endpoint
5b7d70c6
BD		 3321 * @hsotg: The device state.
3322 * @hs_ep: The endpoint to be initialised.
3323 * @epnum: The endpoint number
3324 *
3325 * Initialise the given endpoint (as part of the probe and device state
3326 * creation) to give to the gadget driver. Setup the endpoint name, any
3327 * direction information and other state that may be required.
3328 */
1f91b4cc
FB		 3329static void dwc2_hsotg_initep(struct dwc2_hsotg *hsotg,
3330 struct dwc2_hsotg_ep *hs_ep,
c6f5c050
MYK		 3331 int epnum,
3332 bool dir_in)
5b7d70c6 3333{
5b7d70c6
BD		 3334 char *dir;
3335
3336 if (epnum == 0)
3337 dir = "";
c6f5c050 3338 else if (dir_in)
5b7d70c6 3339 dir = "in";
c6f5c050
MYK		 3340 else
3341 dir = "out";
5b7d70c6 3342
c6f5c050 3343 hs_ep->dir_in = dir_in;
5b7d70c6
BD		 3344 hs_ep->index = epnum;
3345
3346 snprintf(hs_ep->name, sizeof(hs_ep->name), "ep%d%s", epnum, dir);
3347
3348 INIT_LIST_HEAD(&hs_ep->queue);
3349 INIT_LIST_HEAD(&hs_ep->ep.ep_list);
3350
5b7d70c6
BD		 3351 /* add to the list of endpoints known by the gadget driver */
3352 if (epnum)
3353 list_add_tail(&hs_ep->ep.ep_list, &hsotg->gadget.ep_list);
3354
3355 hs_ep->parent = hsotg;
3356 hs_ep->ep.name = hs_ep->name;
e117e742 3357 usb_ep_set_maxpacket_limit(&hs_ep->ep, epnum ? 1024 : EP0_MPS_LIMIT);
1f91b4cc 3358 hs_ep->ep.ops = &dwc2_hsotg_ep_ops;
5b7d70c6 3359
2954522f
RB		 3360 if (epnum == 0) {
3361 hs_ep->ep.caps.type_control = true;
3362 } else {
3363 hs_ep->ep.caps.type_iso = true;
3364 hs_ep->ep.caps.type_bulk = true;
3365 hs_ep->ep.caps.type_int = true;
3366 }
3367
3368 if (dir_in)
3369 hs_ep->ep.caps.dir_in = true;
3370 else
3371 hs_ep->ep.caps.dir_out = true;
3372
8b9bc460
LM		 3373 /*
3374 * if we're using dma, we need to set the next-endpoint pointer
5b7d70c6
BD		 3375 * to be something valid.
3376 */
3377
3378 if (using_dma(hsotg)) {
47a1685f 3379 u32 next = DXEPCTL_NEXTEP((epnum + 1) % 15);
c6f5c050 3380 if (dir_in)
95c8bc36 3381 dwc2_writel(next, hsotg->regs + DIEPCTL(epnum));
c6f5c050 3382 else
95c8bc36 3383 dwc2_writel(next, hsotg->regs + DOEPCTL(epnum));
5b7d70c6
BD		 3384 }
3385}
3386
b3f489b2 3387/**
1f91b4cc 3388 * dwc2_hsotg_hw_cfg - read HW configuration registers
b3f489b2
LM		 3389 * @param: The device state
3390 *
3391 * Read the USB core HW configuration registers
3392 */
1f91b4cc 3393static int dwc2_hsotg_hw_cfg(struct dwc2_hsotg *hsotg)
5b7d70c6 3394{
c6f5c050
MYK		 3395 u32 cfg;
3396 u32 ep_type;
3397 u32 i;
3398
b3f489b2 3399 /* check hardware configuration */
5b7d70c6 3400
43e90349
JY		 3401 hsotg->num_of_eps = hsotg->hw_params.num_dev_ep;
3402
c6f5c050
MYK		 3403 /* Add ep0 */
3404 hsotg->num_of_eps++;
10aebc77 3405
1f91b4cc 3406 hsotg->eps_in[0] = devm_kzalloc(hsotg->dev, sizeof(struct dwc2_hsotg_ep),
c6f5c050
MYK		 3407 GFP_KERNEL);
3408 if (!hsotg->eps_in[0])
3409 return -ENOMEM;
1f91b4cc 3410 /* Same dwc2_hsotg_ep is used in both directions for ep0 */
c6f5c050
MYK		 3411 hsotg->eps_out[0] = hsotg->eps_in[0];
3412
43e90349 3413 cfg = hsotg->hw_params.dev_ep_dirs;
251a17f5 3414 for (i = 1, cfg >>= 2; i < hsotg->num_of_eps; i++, cfg >>= 2) {
c6f5c050
MYK		 3415 ep_type = cfg & 3;
3416 /* Direction in or both */
3417 if (!(ep_type & 2)) {
3418 hsotg->eps_in[i] = devm_kzalloc(hsotg->dev,
1f91b4cc 3419 sizeof(struct dwc2_hsotg_ep), GFP_KERNEL);
c6f5c050
MYK		 3420 if (!hsotg->eps_in[i])
3421 return -ENOMEM;
3422 }
3423 /* Direction out or both */
3424 if (!(ep_type & 1)) {
3425 hsotg->eps_out[i] = devm_kzalloc(hsotg->dev,
1f91b4cc 3426 sizeof(struct dwc2_hsotg_ep), GFP_KERNEL);
c6f5c050
MYK		 3427 if (!hsotg->eps_out[i])
3428 return -ENOMEM;
3429 }
3430 }
3431
43e90349
JY		 3432 hsotg->fifo_mem = hsotg->hw_params.total_fifo_size;
3433 hsotg->dedicated_fifos = hsotg->hw_params.en_multiple_tx_fifo;
10aebc77 3434
cff9eb75
MS		 3435 dev_info(hsotg->dev, "EPs: %d, %s fifos, %d entries in SPRAM\n",
3436 hsotg->num_of_eps,
3437 hsotg->dedicated_fifos ? "dedicated" : "shared",
3438 hsotg->fifo_mem);
c6f5c050 3439 return 0;
5b7d70c6
BD		 3440}
3441
8b9bc460 3442/**
1f91b4cc 3443 * dwc2_hsotg_dump - dump state of the udc
8b9bc460
LM		 3444 * @param: The device state
3445 */
1f91b4cc 3446static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg)
5b7d70c6 3447{
83a01804 3448#ifdef DEBUG
5b7d70c6
BD		 3449 struct device *dev = hsotg->dev;
3450 void __iomem *regs = hsotg->regs;
3451 u32 val;
3452 int idx;
3453
3454 dev_info(dev, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n",
95c8bc36
AS		 3455 dwc2_readl(regs + DCFG), dwc2_readl(regs + DCTL),
3456 dwc2_readl(regs + DIEPMSK));
5b7d70c6 3457
f889f23d 3458 dev_info(dev, "GAHBCFG=0x%08x, GHWCFG1=0x%08x\n",
95c8bc36 3459 dwc2_readl(regs + GAHBCFG), dwc2_readl(regs + GHWCFG1));
5b7d70c6
BD		 3460
3461 dev_info(dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
95c8bc36 3462 dwc2_readl(regs + GRXFSIZ), dwc2_readl(regs + GNPTXFSIZ));
5b7d70c6
BD		 3463
3464 /* show periodic fifo settings */
3465
364f8e93 3466 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
95c8bc36 3467 val = dwc2_readl(regs + DPTXFSIZN(idx));
5b7d70c6 3468 dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx,
47a1685f
DN		 3469 val >> FIFOSIZE_DEPTH_SHIFT,
3470 val & FIFOSIZE_STARTADDR_MASK);
5b7d70c6
BD		 3471 }
3472
364f8e93 3473 for (idx = 0; idx < hsotg->num_of_eps; idx++) {
5b7d70c6
BD		 3474 dev_info(dev,
3475 "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx,
95c8bc36
AS		 3476 dwc2_readl(regs + DIEPCTL(idx)),
3477 dwc2_readl(regs + DIEPTSIZ(idx)),
3478 dwc2_readl(regs + DIEPDMA(idx)));
5b7d70c6 3479
95c8bc36 3480 val = dwc2_readl(regs + DOEPCTL(idx));
5b7d70c6
BD		 3481 dev_info(dev,
3482 "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n",
95c8bc36
AS		 3483 idx, dwc2_readl(regs + DOEPCTL(idx)),
3484 dwc2_readl(regs + DOEPTSIZ(idx)),
3485 dwc2_readl(regs + DOEPDMA(idx)));
5b7d70c6
BD		 3486
3487 }
3488
3489 dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n",
95c8bc36 3490 dwc2_readl(regs + DVBUSDIS), dwc2_readl(regs + DVBUSPULSE));
83a01804 3491#endif
5b7d70c6
BD		 3492}
3493
edd74be8 3494#ifdef CONFIG_OF
1f91b4cc 3495static void dwc2_hsotg_of_probe(struct dwc2_hsotg *hsotg)
edd74be8
GH		 3496{
3497 struct device_node *np = hsotg->dev->of_node;
0a176279
GH		 3498 u32 len = 0;
3499 u32 i = 0;
edd74be8
GH		 3500
3501 /* Enable dma if requested in device tree */
3502 hsotg->g_using_dma = of_property_read_bool(np, "g-use-dma");
0a176279
GH		 3503
3504 /*
3505 * Register TX periodic fifo size per endpoint.
3506 * EP0 is excluded since it has no fifo configuration.
3507 */
3508 if (!of_find_property(np, "g-tx-fifo-size", &len))
3509 goto rx_fifo;
3510
3511 len /= sizeof(u32);
3512
3513 /* Read tx fifo sizes other than ep0 */
3514 if (of_property_read_u32_array(np, "g-tx-fifo-size",
3515 &hsotg->g_tx_fifo_sz[1], len))
3516 goto rx_fifo;
3517
3518 /* Add ep0 */
3519 len++;
3520
3521 /* Make remaining TX fifos unavailable */
3522 if (len < MAX_EPS_CHANNELS) {
3523 for (i = len; i < MAX_EPS_CHANNELS; i++)
3524 hsotg->g_tx_fifo_sz[i] = 0;
3525 }
3526
3527rx_fifo:
3528 /* Register RX fifo size */
3529 of_property_read_u32(np, "g-rx-fifo-size", &hsotg->g_rx_fifo_sz);
3530
3531 /* Register NPTX fifo size */
3532 of_property_read_u32(np, "g-np-tx-fifo-size",
3533 &hsotg->g_np_g_tx_fifo_sz);
edd74be8
GH		 3534}
3535#else
1f91b4cc 3536static inline void dwc2_hsotg_of_probe(struct dwc2_hsotg *hsotg) { }
edd74be8
GH		 3537#endif
3538
8b9bc460 3539/**
117777b2
DN		 3540 * dwc2_gadget_init - init function for gadget
3541 * @dwc2: The data structure for the DWC2 driver.
3542 * @irq: The IRQ number for the controller.
8b9bc460 3543 */
117777b2 3544int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq)
5b7d70c6 3545{
117777b2 3546 struct device *dev = hsotg->dev;
5b7d70c6
BD		 3547 int epnum;
3548 int ret;
fc9a731e 3549 int i;
0a176279 3550 u32 p_tx_fifo[] = DWC2_G_P_LEGACY_TX_FIFO_SIZE;
5b7d70c6 3551
0a176279
GH		 3552 /* Initialize to legacy fifo configuration values */
3553 hsotg->g_rx_fifo_sz = 2048;
3554 hsotg->g_np_g_tx_fifo_sz = 1024;
3555 memcpy(&hsotg->g_tx_fifo_sz[1], p_tx_fifo, sizeof(p_tx_fifo));
3556 /* Device tree specific probe */
1f91b4cc 3557 dwc2_hsotg_of_probe(hsotg);
43e90349
JY		 3558
3559 /* Check against largest possible value. */
3560 if (hsotg->g_np_g_tx_fifo_sz >
3561 hsotg->hw_params.dev_nperio_tx_fifo_size) {
3562 dev_warn(dev, "Specified GNPTXFDEP=%d > %d\n",
3563 hsotg->g_np_g_tx_fifo_sz,
3564 hsotg->hw_params.dev_nperio_tx_fifo_size);
3565 hsotg->g_np_g_tx_fifo_sz =
3566 hsotg->hw_params.dev_nperio_tx_fifo_size;
3567 }
3568
0a176279
GH		 3569 /* Dump fifo information */
3570 dev_dbg(dev, "NonPeriodic TXFIFO size: %d\n",
3571 hsotg->g_np_g_tx_fifo_sz);
3572 dev_dbg(dev, "RXFIFO size: %d\n", hsotg->g_rx_fifo_sz);
3573 for (i = 0; i < MAX_EPS_CHANNELS; i++)
3574 dev_dbg(dev, "Periodic TXFIFO%2d size: %d\n", i,
3575 hsotg->g_tx_fifo_sz[i]);
5b7d70c6 3576
d327ab5b 3577 hsotg->gadget.max_speed = USB_SPEED_HIGH;
1f91b4cc 3578 hsotg->gadget.ops = &dwc2_hsotg_gadget_ops;
5b7d70c6 3579 hsotg->gadget.name = dev_name(dev);
097ee662
GH		 3580 if (hsotg->dr_mode == USB_DR_MODE_OTG)
3581 hsotg->gadget.is_otg = 1;
ec4cc657
MYK		 3582 else if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
3583 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
5b7d70c6 3584
1f91b4cc 3585 ret = dwc2_hsotg_hw_cfg(hsotg);
c6f5c050
MYK		 3586 if (ret) {
3587 dev_err(hsotg->dev, "Hardware configuration failed: %d\n", ret);
09a75e85 3588 return ret;
c6f5c050
MYK		 3589 }
3590
3f95001d
MYK		 3591 hsotg->ctrl_buff = devm_kzalloc(hsotg->dev,
3592 DWC2_CTRL_BUFF_SIZE, GFP_KERNEL);
3593 if (!hsotg->ctrl_buff) {
3594 dev_err(dev, "failed to allocate ctrl request buff\n");
09a75e85 3595 return -ENOMEM;
3f95001d
MYK		 3596 }
3597
3598 hsotg->ep0_buff = devm_kzalloc(hsotg->dev,
3599 DWC2_CTRL_BUFF_SIZE, GFP_KERNEL);
3600 if (!hsotg->ep0_buff) {
3601 dev_err(dev, "failed to allocate ctrl reply buff\n");
09a75e85 3602 return -ENOMEM;
3f95001d
MYK		 3603 }
3604
1f91b4cc 3605 ret = devm_request_irq(hsotg->dev, irq, dwc2_hsotg_irq, IRQF_SHARED,
db8178c3 3606 dev_name(hsotg->dev), hsotg);
eb3c56c5 3607 if (ret < 0) {
db8178c3 3608 dev_err(dev, "cannot claim IRQ for gadget\n");
09a75e85 3609 return ret;
eb3c56c5
MS		 3610 }
3611
b3f489b2
LM		 3612 /* hsotg->num_of_eps holds number of EPs other than ep0 */
3613
3614 if (hsotg->num_of_eps == 0) {
3615 dev_err(dev, "wrong number of EPs (zero)\n");
09a75e85 3616 return -EINVAL;
b3f489b2
LM		 3617 }
3618
b3f489b2
LM		 3619 /* setup endpoint information */
3620
3621 INIT_LIST_HEAD(&hsotg->gadget.ep_list);
c6f5c050 3622 hsotg->gadget.ep0 = &hsotg->eps_out[0]->ep;
b3f489b2
LM		 3623
3624 /* allocate EP0 request */
3625
1f91b4cc 3626 hsotg->ctrl_req = dwc2_hsotg_ep_alloc_request(&hsotg->eps_out[0]->ep,
b3f489b2
LM		 3627 GFP_KERNEL);
3628 if (!hsotg->ctrl_req) {
3629 dev_err(dev, "failed to allocate ctrl req\n");
09a75e85 3630 return -ENOMEM;
b3f489b2 3631 }
5b7d70c6
BD		 3632
3633 /* initialise the endpoints now the core has been initialised */
c6f5c050
MYK		 3634 for (epnum = 0; epnum < hsotg->num_of_eps; epnum++) {
3635 if (hsotg->eps_in[epnum])
1f91b4cc 3636 dwc2_hsotg_initep(hsotg, hsotg->eps_in[epnum],
c6f5c050
MYK		 3637 epnum, 1);
3638 if (hsotg->eps_out[epnum])
1f91b4cc 3639 dwc2_hsotg_initep(hsotg, hsotg->eps_out[epnum],
c6f5c050
MYK		 3640 epnum, 0);
3641 }
5b7d70c6 3642
117777b2 3643 ret = usb_add_gadget_udc(dev, &hsotg->gadget);
0f91349b 3644 if (ret)
09a75e85 3645 return ret;
0f91349b 3646
1f91b4cc 3647 dwc2_hsotg_dump(hsotg);
5b7d70c6 3648
5b7d70c6 3649 return 0;
5b7d70c6
BD		 3650}
3651
8b9bc460 3652/**
1f91b4cc 3653 * dwc2_hsotg_remove - remove function for hsotg driver
8b9bc460
LM		 3654 * @pdev: The platform information for the driver
3655 */
1f91b4cc 3656int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg)
5b7d70c6 3657{
0f91349b 3658 usb_del_gadget_udc(&hsotg->gadget);
31ee04de 3659
5b7d70c6
BD		 3660 return 0;
3661}
3662
1f91b4cc 3663int dwc2_hsotg_suspend(struct dwc2_hsotg *hsotg)
b83e333a 3664{
b83e333a 3665 unsigned long flags;
b83e333a 3666
9e779778 3667 if (hsotg->lx_state != DWC2_L0)
09a75e85 3668 return 0;
9e779778 3669
dc6e69e6
MS		 3670 if (hsotg->driver) {
3671 int ep;
3672
b83e333a
MS		 3673 dev_info(hsotg->dev, "suspending usb gadget %s\n",
3674 hsotg->driver->driver.name);
3675
dc6e69e6
MS		 3676 spin_lock_irqsave(&hsotg->lock, flags);
3677 if (hsotg->enabled)
1f91b4cc
FB		 3678 dwc2_hsotg_core_disconnect(hsotg);
3679 dwc2_hsotg_disconnect(hsotg);
dc6e69e6
MS		 3680 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
3681 spin_unlock_irqrestore(&hsotg->lock, flags);
b83e333a 3682
c6f5c050
MYK		 3683 for (ep = 0; ep < hsotg->num_of_eps; ep++) {
3684 if (hsotg->eps_in[ep])
1f91b4cc 3685 dwc2_hsotg_ep_disable(&hsotg->eps_in[ep]->ep);
c6f5c050 3686 if (hsotg->eps_out[ep])
1f91b4cc 3687 dwc2_hsotg_ep_disable(&hsotg->eps_out[ep]->ep);
c6f5c050 3688 }
b83e333a
MS		 3689 }
3690
09a75e85 3691 return 0;
b83e333a
MS		 3692}
3693
1f91b4cc 3694int dwc2_hsotg_resume(struct dwc2_hsotg *hsotg)
b83e333a 3695{
b83e333a 3696 unsigned long flags;
b83e333a 3697
9e779778 3698 if (hsotg->lx_state == DWC2_L2)
09a75e85 3699 return 0;
9e779778 3700
b83e333a
MS		 3701 if (hsotg->driver) {
3702 dev_info(hsotg->dev, "resuming usb gadget %s\n",
3703 hsotg->driver->driver.name);
d00b4142 3704
dc6e69e6 3705 spin_lock_irqsave(&hsotg->lock, flags);
1f91b4cc 3706 dwc2_hsotg_core_init_disconnected(hsotg, false);
dc6e69e6 3707 if (hsotg->enabled)
1f91b4cc 3708 dwc2_hsotg_core_connect(hsotg);
dc6e69e6
MS		 3709 spin_unlock_irqrestore(&hsotg->lock, flags);
3710 }
b83e333a 3711
09a75e85 3712 return 0;
b83e333a 3713}
58e52ff6
JY		 3714
3715/**
3716 * dwc2_backup_device_registers() - Backup controller device registers.
3717 * When suspending usb bus, registers needs to be backuped
3718 * if controller power is disabled once suspended.
3719 *
3720 * @hsotg: Programming view of the DWC_otg controller
3721 */
3722int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg)
3723{
3724 struct dwc2_dregs_backup *dr;
3725 int i;
3726
3727 dev_dbg(hsotg->dev, "%s\n", __func__);
3728
3729 /* Backup dev regs */
3730 dr = &hsotg->dr_backup;
3731
3732 dr->dcfg = dwc2_readl(hsotg->regs + DCFG);
3733 dr->dctl = dwc2_readl(hsotg->regs + DCTL);
3734 dr->daintmsk = dwc2_readl(hsotg->regs + DAINTMSK);
3735 dr->diepmsk = dwc2_readl(hsotg->regs + DIEPMSK);
3736 dr->doepmsk = dwc2_readl(hsotg->regs + DOEPMSK);
3737
3738 for (i = 0; i < hsotg->num_of_eps; i++) {
3739 /* Backup IN EPs */
3740 dr->diepctl[i] = dwc2_readl(hsotg->regs + DIEPCTL(i));
3741
3742 /* Ensure DATA PID is correctly configured */
3743 if (dr->diepctl[i] & DXEPCTL_DPID)
3744 dr->diepctl[i] |= DXEPCTL_SETD1PID;
3745 else
3746 dr->diepctl[i] |= DXEPCTL_SETD0PID;
3747
3748 dr->dieptsiz[i] = dwc2_readl(hsotg->regs + DIEPTSIZ(i));
3749 dr->diepdma[i] = dwc2_readl(hsotg->regs + DIEPDMA(i));
3750
3751 /* Backup OUT EPs */
3752 dr->doepctl[i] = dwc2_readl(hsotg->regs + DOEPCTL(i));
3753
3754 /* Ensure DATA PID is correctly configured */
3755 if (dr->doepctl[i] & DXEPCTL_DPID)
3756 dr->doepctl[i] |= DXEPCTL_SETD1PID;
3757 else
3758 dr->doepctl[i] |= DXEPCTL_SETD0PID;
3759
3760 dr->doeptsiz[i] = dwc2_readl(hsotg->regs + DOEPTSIZ(i));
3761 dr->doepdma[i] = dwc2_readl(hsotg->regs + DOEPDMA(i));
3762 }
3763 dr->valid = true;
3764 return 0;
3765}
3766
3767/**
3768 * dwc2_restore_device_registers() - Restore controller device registers.
3769 * When resuming usb bus, device registers needs to be restored
3770 * if controller power were disabled.
3771 *
3772 * @hsotg: Programming view of the DWC_otg controller
3773 */
3774int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg)
3775{
3776 struct dwc2_dregs_backup *dr;
3777 u32 dctl;
3778 int i;
3779
3780 dev_dbg(hsotg->dev, "%s\n", __func__);
3781
3782 /* Restore dev regs */
3783 dr = &hsotg->dr_backup;
3784 if (!dr->valid) {
3785 dev_err(hsotg->dev, "%s: no device registers to restore\n",
3786 __func__);
3787 return -EINVAL;
3788 }
3789 dr->valid = false;
3790
3791 dwc2_writel(dr->dcfg, hsotg->regs + DCFG);
3792 dwc2_writel(dr->dctl, hsotg->regs + DCTL);
3793 dwc2_writel(dr->daintmsk, hsotg->regs + DAINTMSK);
3794 dwc2_writel(dr->diepmsk, hsotg->regs + DIEPMSK);
3795 dwc2_writel(dr->doepmsk, hsotg->regs + DOEPMSK);
3796
3797 for (i = 0; i < hsotg->num_of_eps; i++) {
3798 /* Restore IN EPs */
3799 dwc2_writel(dr->diepctl[i], hsotg->regs + DIEPCTL(i));
3800 dwc2_writel(dr->dieptsiz[i], hsotg->regs + DIEPTSIZ(i));
3801 dwc2_writel(dr->diepdma[i], hsotg->regs + DIEPDMA(i));
3802
3803 /* Restore OUT EPs */
3804 dwc2_writel(dr->doepctl[i], hsotg->regs + DOEPCTL(i));
3805 dwc2_writel(dr->doeptsiz[i], hsotg->regs + DOEPTSIZ(i));
3806 dwc2_writel(dr->doepdma[i], hsotg->regs + DOEPDMA(i));
3807 }
3808
3809 /* Set the Power-On Programming done bit */
3810 dctl = dwc2_readl(hsotg->regs + DCTL);
3811 dctl |= DCTL_PWRONPRGDONE;
3812 dwc2_writel(dctl, hsotg->regs + DCTL);
3813
3814 return 0;
3815}
Linux 6.x block layer and io_uring tree(s)