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5fd54ace | 1 | // SPDX-License-Identifier: GPL-2.0 |
6fb914d7 | 2 | /* |
dfbc6fa3 AT |
3 | * Copyright (c) 2011 Samsung Electronics Co., Ltd. |
4 | * http://www.samsung.com | |
5b7d70c6 BD |
5 | * |
6 | * Copyright 2008 Openmoko, Inc. | |
7 | * Copyright 2008 Simtec Electronics | |
8 | * Ben Dooks <ben@simtec.co.uk> | |
9 | * http://armlinux.simtec.co.uk/ | |
10 | * | |
11 | * S3C USB2.0 High-speed / OtG driver | |
8b9bc460 | 12 | */ |
5b7d70c6 BD |
13 | |
14 | #include <linux/kernel.h> | |
15 | #include <linux/module.h> | |
16 | #include <linux/spinlock.h> | |
17 | #include <linux/interrupt.h> | |
18 | #include <linux/platform_device.h> | |
19 | #include <linux/dma-mapping.h> | |
7ad8096e | 20 | #include <linux/mutex.h> |
5b7d70c6 BD |
21 | #include <linux/seq_file.h> |
22 | #include <linux/delay.h> | |
23 | #include <linux/io.h> | |
5a0e3ad6 | 24 | #include <linux/slab.h> |
c50f056c | 25 | #include <linux/of_platform.h> |
5b7d70c6 BD |
26 | |
27 | #include <linux/usb/ch9.h> | |
28 | #include <linux/usb/gadget.h> | |
b2e587db | 29 | #include <linux/usb/phy.h> |
b4c53b4a MH |
30 | #include <linux/usb/composite.h> |
31 | ||
5b7d70c6 | 32 | |
f7c0b143 | 33 | #include "core.h" |
941fcce4 | 34 | #include "hw.h" |
5b7d70c6 BD |
35 | |
36 | /* conversion functions */ | |
1f91b4cc | 37 | static inline struct dwc2_hsotg_req *our_req(struct usb_request *req) |
5b7d70c6 | 38 | { |
1f91b4cc | 39 | return container_of(req, struct dwc2_hsotg_req, req); |
5b7d70c6 BD |
40 | } |
41 | ||
1f91b4cc | 42 | static inline struct dwc2_hsotg_ep *our_ep(struct usb_ep *ep) |
5b7d70c6 | 43 | { |
1f91b4cc | 44 | return container_of(ep, struct dwc2_hsotg_ep, ep); |
5b7d70c6 BD |
45 | } |
46 | ||
941fcce4 | 47 | static inline struct dwc2_hsotg *to_hsotg(struct usb_gadget *gadget) |
5b7d70c6 | 48 | { |
941fcce4 | 49 | return container_of(gadget, struct dwc2_hsotg, gadget); |
5b7d70c6 BD |
50 | } |
51 | ||
f25c42b8 | 52 | static inline void dwc2_set_bit(struct dwc2_hsotg *hsotg, u32 offset, u32 val) |
5b7d70c6 | 53 | { |
f25c42b8 | 54 | dwc2_writel(hsotg, dwc2_readl(hsotg, offset) | val, offset); |
5b7d70c6 BD |
55 | } |
56 | ||
f25c42b8 | 57 | static inline void dwc2_clear_bit(struct dwc2_hsotg *hsotg, u32 offset, u32 val) |
5b7d70c6 | 58 | { |
f25c42b8 | 59 | dwc2_writel(hsotg, dwc2_readl(hsotg, offset) & ~val, offset); |
5b7d70c6 BD |
60 | } |
61 | ||
1f91b4cc | 62 | static inline struct dwc2_hsotg_ep *index_to_ep(struct dwc2_hsotg *hsotg, |
c6f5c050 MYK |
63 | u32 ep_index, u32 dir_in) |
64 | { | |
65 | if (dir_in) | |
66 | return hsotg->eps_in[ep_index]; | |
67 | else | |
68 | return hsotg->eps_out[ep_index]; | |
69 | } | |
70 | ||
997f4f81 | 71 | /* forward declaration of functions */ |
1f91b4cc | 72 | static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg); |
5b7d70c6 BD |
73 | |
74 | /** | |
75 | * using_dma - return the DMA status of the driver. | |
76 | * @hsotg: The driver state. | |
77 | * | |
78 | * Return true if we're using DMA. | |
79 | * | |
80 | * Currently, we have the DMA support code worked into everywhere | |
81 | * that needs it, but the AMBA DMA implementation in the hardware can | |
82 | * only DMA from 32bit aligned addresses. This means that gadgets such | |
83 | * as the CDC Ethernet cannot work as they often pass packets which are | |
84 | * not 32bit aligned. | |
85 | * | |
86 | * Unfortunately the choice to use DMA or not is global to the controller | |
87 | * and seems to be only settable when the controller is being put through | |
88 | * a core reset. This means we either need to fix the gadgets to take | |
89 | * account of DMA alignment, or add bounce buffers (yuerk). | |
90 | * | |
edd74be8 | 91 | * g_using_dma is set depending on dts flag. |
5b7d70c6 | 92 | */ |
941fcce4 | 93 | static inline bool using_dma(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 94 | { |
05ee799f | 95 | return hsotg->params.g_dma; |
5b7d70c6 BD |
96 | } |
97 | ||
dec4b556 VA |
98 | /* |
99 | * using_desc_dma - return the descriptor DMA status of the driver. | |
100 | * @hsotg: The driver state. | |
101 | * | |
102 | * Return true if we're using descriptor DMA. | |
103 | */ | |
104 | static inline bool using_desc_dma(struct dwc2_hsotg *hsotg) | |
105 | { | |
106 | return hsotg->params.g_dma_desc; | |
107 | } | |
108 | ||
92d1635d VM |
109 | /** |
110 | * dwc2_gadget_incr_frame_num - Increments the targeted frame number. | |
111 | * @hs_ep: The endpoint | |
92d1635d VM |
112 | * |
113 | * This function will also check if the frame number overruns DSTS_SOFFN_LIMIT. | |
114 | * If an overrun occurs it will wrap the value and set the frame_overrun flag. | |
115 | */ | |
116 | static inline void dwc2_gadget_incr_frame_num(struct dwc2_hsotg_ep *hs_ep) | |
117 | { | |
91bb163e MH |
118 | struct dwc2_hsotg *hsotg = hs_ep->parent; |
119 | u16 limit = DSTS_SOFFN_LIMIT; | |
120 | ||
121 | if (hsotg->gadget.speed != USB_SPEED_HIGH) | |
122 | limit >>= 3; | |
123 | ||
92d1635d | 124 | hs_ep->target_frame += hs_ep->interval; |
91bb163e | 125 | if (hs_ep->target_frame > limit) { |
c1d5df69 | 126 | hs_ep->frame_overrun = true; |
91bb163e | 127 | hs_ep->target_frame &= limit; |
92d1635d | 128 | } else { |
c1d5df69 | 129 | hs_ep->frame_overrun = false; |
92d1635d VM |
130 | } |
131 | } | |
132 | ||
9d630b9c GT |
133 | /** |
134 | * dwc2_gadget_dec_frame_num_by_one - Decrements the targeted frame number | |
135 | * by one. | |
136 | * @hs_ep: The endpoint. | |
137 | * | |
138 | * This function used in service interval based scheduling flow to calculate | |
139 | * descriptor frame number filed value. For service interval mode frame | |
140 | * number in descriptor should point to last (u)frame in the interval. | |
141 | * | |
142 | */ | |
143 | static inline void dwc2_gadget_dec_frame_num_by_one(struct dwc2_hsotg_ep *hs_ep) | |
144 | { | |
91bb163e MH |
145 | struct dwc2_hsotg *hsotg = hs_ep->parent; |
146 | u16 limit = DSTS_SOFFN_LIMIT; | |
147 | ||
148 | if (hsotg->gadget.speed != USB_SPEED_HIGH) | |
149 | limit >>= 3; | |
150 | ||
9d630b9c GT |
151 | if (hs_ep->target_frame) |
152 | hs_ep->target_frame -= 1; | |
153 | else | |
91bb163e | 154 | hs_ep->target_frame = limit; |
9d630b9c GT |
155 | } |
156 | ||
5b7d70c6 | 157 | /** |
1f91b4cc | 158 | * dwc2_hsotg_en_gsint - enable one or more of the general interrupt |
5b7d70c6 BD |
159 | * @hsotg: The device state |
160 | * @ints: A bitmask of the interrupts to enable | |
161 | */ | |
1f91b4cc | 162 | static void dwc2_hsotg_en_gsint(struct dwc2_hsotg *hsotg, u32 ints) |
5b7d70c6 | 163 | { |
f25c42b8 | 164 | u32 gsintmsk = dwc2_readl(hsotg, GINTMSK); |
5b7d70c6 BD |
165 | u32 new_gsintmsk; |
166 | ||
167 | new_gsintmsk = gsintmsk | ints; | |
168 | ||
169 | if (new_gsintmsk != gsintmsk) { | |
170 | dev_dbg(hsotg->dev, "gsintmsk now 0x%08x\n", new_gsintmsk); | |
f25c42b8 | 171 | dwc2_writel(hsotg, new_gsintmsk, GINTMSK); |
5b7d70c6 BD |
172 | } |
173 | } | |
174 | ||
175 | /** | |
1f91b4cc | 176 | * dwc2_hsotg_disable_gsint - disable one or more of the general interrupt |
5b7d70c6 BD |
177 | * @hsotg: The device state |
178 | * @ints: A bitmask of the interrupts to enable | |
179 | */ | |
1f91b4cc | 180 | static void dwc2_hsotg_disable_gsint(struct dwc2_hsotg *hsotg, u32 ints) |
5b7d70c6 | 181 | { |
f25c42b8 | 182 | u32 gsintmsk = dwc2_readl(hsotg, GINTMSK); |
5b7d70c6 BD |
183 | u32 new_gsintmsk; |
184 | ||
185 | new_gsintmsk = gsintmsk & ~ints; | |
186 | ||
187 | if (new_gsintmsk != gsintmsk) | |
f25c42b8 | 188 | dwc2_writel(hsotg, new_gsintmsk, GINTMSK); |
5b7d70c6 BD |
189 | } |
190 | ||
191 | /** | |
1f91b4cc | 192 | * dwc2_hsotg_ctrl_epint - enable/disable an endpoint irq |
5b7d70c6 BD |
193 | * @hsotg: The device state |
194 | * @ep: The endpoint index | |
195 | * @dir_in: True if direction is in. | |
196 | * @en: The enable value, true to enable | |
197 | * | |
198 | * Set or clear the mask for an individual endpoint's interrupt | |
199 | * request. | |
200 | */ | |
1f91b4cc | 201 | static void dwc2_hsotg_ctrl_epint(struct dwc2_hsotg *hsotg, |
9da51974 | 202 | unsigned int ep, unsigned int dir_in, |
5b7d70c6 BD |
203 | unsigned int en) |
204 | { | |
205 | unsigned long flags; | |
206 | u32 bit = 1 << ep; | |
207 | u32 daint; | |
208 | ||
209 | if (!dir_in) | |
210 | bit <<= 16; | |
211 | ||
212 | local_irq_save(flags); | |
f25c42b8 | 213 | daint = dwc2_readl(hsotg, DAINTMSK); |
5b7d70c6 BD |
214 | if (en) |
215 | daint |= bit; | |
216 | else | |
217 | daint &= ~bit; | |
f25c42b8 | 218 | dwc2_writel(hsotg, daint, DAINTMSK); |
5b7d70c6 BD |
219 | local_irq_restore(flags); |
220 | } | |
221 | ||
c138ecfa SA |
222 | /** |
223 | * dwc2_hsotg_tx_fifo_count - return count of TX FIFOs in device mode | |
6fb914d7 GT |
224 | * |
225 | * @hsotg: Programming view of the DWC_otg controller | |
c138ecfa SA |
226 | */ |
227 | int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg *hsotg) | |
228 | { | |
229 | if (hsotg->hw_params.en_multiple_tx_fifo) | |
230 | /* In dedicated FIFO mode we need count of IN EPs */ | |
9273083a | 231 | return hsotg->hw_params.num_dev_in_eps; |
c138ecfa SA |
232 | else |
233 | /* In shared FIFO mode we need count of Periodic IN EPs */ | |
234 | return hsotg->hw_params.num_dev_perio_in_ep; | |
235 | } | |
236 | ||
c138ecfa SA |
237 | /** |
238 | * dwc2_hsotg_tx_fifo_total_depth - return total FIFO depth available for | |
239 | * device mode TX FIFOs | |
6fb914d7 GT |
240 | * |
241 | * @hsotg: Programming view of the DWC_otg controller | |
c138ecfa SA |
242 | */ |
243 | int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg) | |
244 | { | |
c138ecfa SA |
245 | int addr; |
246 | int tx_addr_max; | |
247 | u32 np_tx_fifo_size; | |
248 | ||
249 | np_tx_fifo_size = min_t(u32, hsotg->hw_params.dev_nperio_tx_fifo_size, | |
250 | hsotg->params.g_np_tx_fifo_size); | |
251 | ||
252 | /* Get Endpoint Info Control block size in DWORDs. */ | |
9273083a | 253 | tx_addr_max = hsotg->hw_params.total_fifo_size; |
c138ecfa SA |
254 | |
255 | addr = hsotg->params.g_rx_fifo_size + np_tx_fifo_size; | |
256 | if (tx_addr_max <= addr) | |
257 | return 0; | |
258 | ||
259 | return tx_addr_max - addr; | |
260 | } | |
261 | ||
187c5298 GT |
262 | /** |
263 | * dwc2_gadget_wkup_alert_handler - Handler for WKUP_ALERT interrupt | |
264 | * | |
265 | * @hsotg: Programming view of the DWC_otg controller | |
266 | * | |
267 | */ | |
268 | static void dwc2_gadget_wkup_alert_handler(struct dwc2_hsotg *hsotg) | |
269 | { | |
270 | u32 gintsts2; | |
271 | u32 gintmsk2; | |
272 | ||
273 | gintsts2 = dwc2_readl(hsotg, GINTSTS2); | |
274 | gintmsk2 = dwc2_readl(hsotg, GINTMSK2); | |
9607f3cd | 275 | gintsts2 &= gintmsk2; |
187c5298 GT |
276 | |
277 | if (gintsts2 & GINTSTS2_WKUP_ALERT_INT) { | |
278 | dev_dbg(hsotg->dev, "%s: Wkup_Alert_Int\n", __func__); | |
87b6d2c5 | 279 | dwc2_set_bit(hsotg, GINTSTS2, GINTSTS2_WKUP_ALERT_INT); |
d64bc8ee | 280 | dwc2_set_bit(hsotg, DCTL, DCTL_RMTWKUPSIG); |
187c5298 GT |
281 | } |
282 | } | |
283 | ||
c138ecfa SA |
284 | /** |
285 | * dwc2_hsotg_tx_fifo_average_depth - returns average depth of device mode | |
286 | * TX FIFOs | |
6fb914d7 GT |
287 | * |
288 | * @hsotg: Programming view of the DWC_otg controller | |
c138ecfa SA |
289 | */ |
290 | int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg *hsotg) | |
291 | { | |
292 | int tx_fifo_count; | |
293 | int tx_fifo_depth; | |
294 | ||
295 | tx_fifo_depth = dwc2_hsotg_tx_fifo_total_depth(hsotg); | |
296 | ||
297 | tx_fifo_count = dwc2_hsotg_tx_fifo_count(hsotg); | |
298 | ||
299 | if (!tx_fifo_count) | |
300 | return tx_fifo_depth; | |
301 | else | |
302 | return tx_fifo_depth / tx_fifo_count; | |
303 | } | |
304 | ||
5b7d70c6 | 305 | /** |
1f91b4cc | 306 | * dwc2_hsotg_init_fifo - initialise non-periodic FIFOs |
5b7d70c6 BD |
307 | * @hsotg: The device instance. |
308 | */ | |
1f91b4cc | 309 | static void dwc2_hsotg_init_fifo(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 310 | { |
2317eacd | 311 | unsigned int ep; |
0f002d20 | 312 | unsigned int addr; |
1703a6d3 | 313 | int timeout; |
79d6b8c5 | 314 | |
0f002d20 | 315 | u32 val; |
05ee799f | 316 | u32 *txfsz = hsotg->params.g_tx_fifo_size; |
0f002d20 | 317 | |
7fcbc95c GH |
318 | /* Reset fifo map if not correctly cleared during previous session */ |
319 | WARN_ON(hsotg->fifo_map); | |
320 | hsotg->fifo_map = 0; | |
321 | ||
0a176279 | 322 | /* set RX/NPTX FIFO sizes */ |
f25c42b8 GS |
323 | dwc2_writel(hsotg, hsotg->params.g_rx_fifo_size, GRXFSIZ); |
324 | dwc2_writel(hsotg, (hsotg->params.g_rx_fifo_size << | |
325 | FIFOSIZE_STARTADDR_SHIFT) | | |
05ee799f | 326 | (hsotg->params.g_np_tx_fifo_size << FIFOSIZE_DEPTH_SHIFT), |
f25c42b8 | 327 | GNPTXFSIZ); |
0f002d20 | 328 | |
8b9bc460 LM |
329 | /* |
330 | * arange all the rest of the TX FIFOs, as some versions of this | |
0f002d20 BD |
331 | * block have overlapping default addresses. This also ensures |
332 | * that if the settings have been changed, then they are set to | |
8b9bc460 LM |
333 | * known values. |
334 | */ | |
0f002d20 BD |
335 | |
336 | /* start at the end of the GNPTXFSIZ, rounded up */ | |
05ee799f | 337 | addr = hsotg->params.g_rx_fifo_size + hsotg->params.g_np_tx_fifo_size; |
0f002d20 | 338 | |
8b9bc460 | 339 | /* |
0a176279 | 340 | * Configure fifos sizes from provided configuration and assign |
b203d0a2 RB |
341 | * them to endpoints dynamically according to maxpacket size value of |
342 | * given endpoint. | |
8b9bc460 | 343 | */ |
2317eacd | 344 | for (ep = 1; ep < MAX_EPS_CHANNELS; ep++) { |
05ee799f | 345 | if (!txfsz[ep]) |
3fa95385 JY |
346 | continue; |
347 | val = addr; | |
05ee799f JY |
348 | val |= txfsz[ep] << FIFOSIZE_DEPTH_SHIFT; |
349 | WARN_ONCE(addr + txfsz[ep] > hsotg->fifo_mem, | |
3fa95385 | 350 | "insufficient fifo memory"); |
05ee799f | 351 | addr += txfsz[ep]; |
0f002d20 | 352 | |
f25c42b8 GS |
353 | dwc2_writel(hsotg, val, DPTXFSIZN(ep)); |
354 | val = dwc2_readl(hsotg, DPTXFSIZN(ep)); | |
0f002d20 | 355 | } |
1703a6d3 | 356 | |
f25c42b8 | 357 | dwc2_writel(hsotg, hsotg->hw_params.total_fifo_size | |
f87c842f | 358 | addr << GDFIFOCFG_EPINFOBASE_SHIFT, |
f25c42b8 | 359 | GDFIFOCFG); |
8b9bc460 LM |
360 | /* |
361 | * according to p428 of the design guide, we need to ensure that | |
362 | * all fifos are flushed before continuing | |
363 | */ | |
1703a6d3 | 364 | |
f25c42b8 GS |
365 | dwc2_writel(hsotg, GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH | |
366 | GRSTCTL_RXFFLSH, GRSTCTL); | |
1703a6d3 BD |
367 | |
368 | /* wait until the fifos are both flushed */ | |
369 | timeout = 100; | |
370 | while (1) { | |
f25c42b8 | 371 | val = dwc2_readl(hsotg, GRSTCTL); |
1703a6d3 | 372 | |
47a1685f | 373 | if ((val & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH)) == 0) |
1703a6d3 BD |
374 | break; |
375 | ||
376 | if (--timeout == 0) { | |
377 | dev_err(hsotg->dev, | |
378 | "%s: timeout flushing fifos (GRSTCTL=%08x)\n", | |
379 | __func__, val); | |
48b20bcb | 380 | break; |
1703a6d3 BD |
381 | } |
382 | ||
383 | udelay(1); | |
384 | } | |
385 | ||
386 | dev_dbg(hsotg->dev, "FIFOs reset, timeout at %d\n", timeout); | |
5b7d70c6 BD |
387 | } |
388 | ||
389 | /** | |
6fb914d7 | 390 | * dwc2_hsotg_ep_alloc_request - allocate USB rerequest structure |
5b7d70c6 BD |
391 | * @ep: USB endpoint to allocate request for. |
392 | * @flags: Allocation flags | |
393 | * | |
394 | * Allocate a new USB request structure appropriate for the specified endpoint | |
395 | */ | |
1f91b4cc | 396 | static struct usb_request *dwc2_hsotg_ep_alloc_request(struct usb_ep *ep, |
9da51974 | 397 | gfp_t flags) |
5b7d70c6 | 398 | { |
1f91b4cc | 399 | struct dwc2_hsotg_req *req; |
5b7d70c6 | 400 | |
ec33efe2 | 401 | req = kzalloc(sizeof(*req), flags); |
5b7d70c6 BD |
402 | if (!req) |
403 | return NULL; | |
404 | ||
405 | INIT_LIST_HEAD(&req->queue); | |
406 | ||
5b7d70c6 BD |
407 | return &req->req; |
408 | } | |
409 | ||
410 | /** | |
411 | * is_ep_periodic - return true if the endpoint is in periodic mode. | |
412 | * @hs_ep: The endpoint to query. | |
413 | * | |
414 | * Returns true if the endpoint is in periodic mode, meaning it is being | |
415 | * used for an Interrupt or ISO transfer. | |
416 | */ | |
1f91b4cc | 417 | static inline int is_ep_periodic(struct dwc2_hsotg_ep *hs_ep) |
5b7d70c6 BD |
418 | { |
419 | return hs_ep->periodic; | |
420 | } | |
421 | ||
422 | /** | |
1f91b4cc | 423 | * dwc2_hsotg_unmap_dma - unmap the DMA memory being used for the request |
5b7d70c6 BD |
424 | * @hsotg: The device state. |
425 | * @hs_ep: The endpoint for the request | |
426 | * @hs_req: The request being processed. | |
427 | * | |
1f91b4cc | 428 | * This is the reverse of dwc2_hsotg_map_dma(), called for the completion |
5b7d70c6 | 429 | * of a request to ensure the buffer is ready for access by the caller. |
8b9bc460 | 430 | */ |
1f91b4cc | 431 | static void dwc2_hsotg_unmap_dma(struct dwc2_hsotg *hsotg, |
9da51974 | 432 | struct dwc2_hsotg_ep *hs_ep, |
1f91b4cc | 433 | struct dwc2_hsotg_req *hs_req) |
5b7d70c6 BD |
434 | { |
435 | struct usb_request *req = &hs_req->req; | |
9da51974 | 436 | |
75a41ce4 | 437 | usb_gadget_unmap_request(&hsotg->gadget, req, hs_ep->map_dir); |
5b7d70c6 BD |
438 | } |
439 | ||
0f6b80c0 VA |
440 | /* |
441 | * dwc2_gadget_alloc_ctrl_desc_chains - allocate DMA descriptor chains | |
442 | * for Control endpoint | |
443 | * @hsotg: The device state. | |
444 | * | |
445 | * This function will allocate 4 descriptor chains for EP 0: 2 for | |
446 | * Setup stage, per one for IN and OUT data/status transactions. | |
447 | */ | |
448 | static int dwc2_gadget_alloc_ctrl_desc_chains(struct dwc2_hsotg *hsotg) | |
449 | { | |
450 | hsotg->setup_desc[0] = | |
451 | dmam_alloc_coherent(hsotg->dev, | |
452 | sizeof(struct dwc2_dma_desc), | |
453 | &hsotg->setup_desc_dma[0], | |
454 | GFP_KERNEL); | |
455 | if (!hsotg->setup_desc[0]) | |
456 | goto fail; | |
457 | ||
458 | hsotg->setup_desc[1] = | |
459 | dmam_alloc_coherent(hsotg->dev, | |
460 | sizeof(struct dwc2_dma_desc), | |
461 | &hsotg->setup_desc_dma[1], | |
462 | GFP_KERNEL); | |
463 | if (!hsotg->setup_desc[1]) | |
464 | goto fail; | |
465 | ||
466 | hsotg->ctrl_in_desc = | |
467 | dmam_alloc_coherent(hsotg->dev, | |
468 | sizeof(struct dwc2_dma_desc), | |
469 | &hsotg->ctrl_in_desc_dma, | |
470 | GFP_KERNEL); | |
471 | if (!hsotg->ctrl_in_desc) | |
472 | goto fail; | |
473 | ||
474 | hsotg->ctrl_out_desc = | |
475 | dmam_alloc_coherent(hsotg->dev, | |
476 | sizeof(struct dwc2_dma_desc), | |
477 | &hsotg->ctrl_out_desc_dma, | |
478 | GFP_KERNEL); | |
479 | if (!hsotg->ctrl_out_desc) | |
480 | goto fail; | |
481 | ||
482 | return 0; | |
483 | ||
484 | fail: | |
485 | return -ENOMEM; | |
486 | } | |
487 | ||
5b7d70c6 | 488 | /** |
1f91b4cc | 489 | * dwc2_hsotg_write_fifo - write packet Data to the TxFIFO |
5b7d70c6 BD |
490 | * @hsotg: The controller state. |
491 | * @hs_ep: The endpoint we're going to write for. | |
492 | * @hs_req: The request to write data for. | |
493 | * | |
494 | * This is called when the TxFIFO has some space in it to hold a new | |
495 | * transmission and we have something to give it. The actual setup of | |
496 | * the data size is done elsewhere, so all we have to do is to actually | |
497 | * write the data. | |
498 | * | |
499 | * The return value is zero if there is more space (or nothing was done) | |
500 | * otherwise -ENOSPC is returned if the FIFO space was used up. | |
501 | * | |
502 | * This routine is only needed for PIO | |
8b9bc460 | 503 | */ |
1f91b4cc | 504 | static int dwc2_hsotg_write_fifo(struct dwc2_hsotg *hsotg, |
9da51974 | 505 | struct dwc2_hsotg_ep *hs_ep, |
1f91b4cc | 506 | struct dwc2_hsotg_req *hs_req) |
5b7d70c6 BD |
507 | { |
508 | bool periodic = is_ep_periodic(hs_ep); | |
f25c42b8 | 509 | u32 gnptxsts = dwc2_readl(hsotg, GNPTXSTS); |
5b7d70c6 BD |
510 | int buf_pos = hs_req->req.actual; |
511 | int to_write = hs_ep->size_loaded; | |
512 | void *data; | |
513 | int can_write; | |
514 | int pkt_round; | |
4fca54aa | 515 | int max_transfer; |
5b7d70c6 BD |
516 | |
517 | to_write -= (buf_pos - hs_ep->last_load); | |
518 | ||
519 | /* if there's nothing to write, get out early */ | |
520 | if (to_write == 0) | |
521 | return 0; | |
522 | ||
10aebc77 | 523 | if (periodic && !hsotg->dedicated_fifos) { |
f25c42b8 | 524 | u32 epsize = dwc2_readl(hsotg, DIEPTSIZ(hs_ep->index)); |
5b7d70c6 BD |
525 | int size_left; |
526 | int size_done; | |
527 | ||
8b9bc460 LM |
528 | /* |
529 | * work out how much data was loaded so we can calculate | |
530 | * how much data is left in the fifo. | |
531 | */ | |
5b7d70c6 | 532 | |
47a1685f | 533 | size_left = DXEPTSIZ_XFERSIZE_GET(epsize); |
5b7d70c6 | 534 | |
8b9bc460 LM |
535 | /* |
536 | * if shared fifo, we cannot write anything until the | |
e7a9ff54 BD |
537 | * previous data has been completely sent. |
538 | */ | |
539 | if (hs_ep->fifo_load != 0) { | |
1f91b4cc | 540 | dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP); |
e7a9ff54 BD |
541 | return -ENOSPC; |
542 | } | |
543 | ||
5b7d70c6 BD |
544 | dev_dbg(hsotg->dev, "%s: left=%d, load=%d, fifo=%d, size %d\n", |
545 | __func__, size_left, | |
546 | hs_ep->size_loaded, hs_ep->fifo_load, hs_ep->fifo_size); | |
547 | ||
548 | /* how much of the data has moved */ | |
549 | size_done = hs_ep->size_loaded - size_left; | |
550 | ||
551 | /* how much data is left in the fifo */ | |
552 | can_write = hs_ep->fifo_load - size_done; | |
553 | dev_dbg(hsotg->dev, "%s: => can_write1=%d\n", | |
554 | __func__, can_write); | |
555 | ||
556 | can_write = hs_ep->fifo_size - can_write; | |
557 | dev_dbg(hsotg->dev, "%s: => can_write2=%d\n", | |
558 | __func__, can_write); | |
559 | ||
560 | if (can_write <= 0) { | |
1f91b4cc | 561 | dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP); |
5b7d70c6 BD |
562 | return -ENOSPC; |
563 | } | |
10aebc77 | 564 | } else if (hsotg->dedicated_fifos && hs_ep->index != 0) { |
f25c42b8 GS |
565 | can_write = dwc2_readl(hsotg, |
566 | DTXFSTS(hs_ep->fifo_index)); | |
10aebc77 BD |
567 | |
568 | can_write &= 0xffff; | |
569 | can_write *= 4; | |
5b7d70c6 | 570 | } else { |
47a1685f | 571 | if (GNPTXSTS_NP_TXQ_SPC_AVAIL_GET(gnptxsts) == 0) { |
5b7d70c6 BD |
572 | dev_dbg(hsotg->dev, |
573 | "%s: no queue slots available (0x%08x)\n", | |
574 | __func__, gnptxsts); | |
575 | ||
1f91b4cc | 576 | dwc2_hsotg_en_gsint(hsotg, GINTSTS_NPTXFEMP); |
5b7d70c6 BD |
577 | return -ENOSPC; |
578 | } | |
579 | ||
47a1685f | 580 | can_write = GNPTXSTS_NP_TXF_SPC_AVAIL_GET(gnptxsts); |
679f9b7c | 581 | can_write *= 4; /* fifo size is in 32bit quantities. */ |
5b7d70c6 BD |
582 | } |
583 | ||
4fca54aa RB |
584 | max_transfer = hs_ep->ep.maxpacket * hs_ep->mc; |
585 | ||
586 | dev_dbg(hsotg->dev, "%s: GNPTXSTS=%08x, can=%d, to=%d, max_transfer %d\n", | |
9da51974 | 587 | __func__, gnptxsts, can_write, to_write, max_transfer); |
5b7d70c6 | 588 | |
8b9bc460 LM |
589 | /* |
590 | * limit to 512 bytes of data, it seems at least on the non-periodic | |
5b7d70c6 BD |
591 | * FIFO, requests of >512 cause the endpoint to get stuck with a |
592 | * fragment of the end of the transfer in it. | |
593 | */ | |
811f3303 | 594 | if (can_write > 512 && !periodic) |
5b7d70c6 BD |
595 | can_write = 512; |
596 | ||
8b9bc460 LM |
597 | /* |
598 | * limit the write to one max-packet size worth of data, but allow | |
03e10e5a | 599 | * the transfer to return that it did not run out of fifo space |
8b9bc460 LM |
600 | * doing it. |
601 | */ | |
4fca54aa RB |
602 | if (to_write > max_transfer) { |
603 | to_write = max_transfer; | |
03e10e5a | 604 | |
5cb2ff0c RB |
605 | /* it's needed only when we do not use dedicated fifos */ |
606 | if (!hsotg->dedicated_fifos) | |
1f91b4cc | 607 | dwc2_hsotg_en_gsint(hsotg, |
9da51974 | 608 | periodic ? GINTSTS_PTXFEMP : |
47a1685f | 609 | GINTSTS_NPTXFEMP); |
03e10e5a BD |
610 | } |
611 | ||
5b7d70c6 BD |
612 | /* see if we can write data */ |
613 | ||
614 | if (to_write > can_write) { | |
615 | to_write = can_write; | |
4fca54aa | 616 | pkt_round = to_write % max_transfer; |
5b7d70c6 | 617 | |
8b9bc460 LM |
618 | /* |
619 | * Round the write down to an | |
5b7d70c6 BD |
620 | * exact number of packets. |
621 | * | |
622 | * Note, we do not currently check to see if we can ever | |
623 | * write a full packet or not to the FIFO. | |
624 | */ | |
625 | ||
626 | if (pkt_round) | |
627 | to_write -= pkt_round; | |
628 | ||
8b9bc460 LM |
629 | /* |
630 | * enable correct FIFO interrupt to alert us when there | |
631 | * is more room left. | |
632 | */ | |
5b7d70c6 | 633 | |
5cb2ff0c RB |
634 | /* it's needed only when we do not use dedicated fifos */ |
635 | if (!hsotg->dedicated_fifos) | |
1f91b4cc | 636 | dwc2_hsotg_en_gsint(hsotg, |
9da51974 | 637 | periodic ? GINTSTS_PTXFEMP : |
47a1685f | 638 | GINTSTS_NPTXFEMP); |
5b7d70c6 BD |
639 | } |
640 | ||
641 | dev_dbg(hsotg->dev, "write %d/%d, can_write %d, done %d\n", | |
9da51974 | 642 | to_write, hs_req->req.length, can_write, buf_pos); |
5b7d70c6 BD |
643 | |
644 | if (to_write <= 0) | |
645 | return -ENOSPC; | |
646 | ||
647 | hs_req->req.actual = buf_pos + to_write; | |
648 | hs_ep->total_data += to_write; | |
649 | ||
650 | if (periodic) | |
651 | hs_ep->fifo_load += to_write; | |
652 | ||
653 | to_write = DIV_ROUND_UP(to_write, 4); | |
654 | data = hs_req->req.buf + buf_pos; | |
655 | ||
342ccce1 | 656 | dwc2_writel_rep(hsotg, EPFIFO(hs_ep->index), data, to_write); |
5b7d70c6 BD |
657 | |
658 | return (to_write >= can_write) ? -ENOSPC : 0; | |
659 | } | |
660 | ||
661 | /** | |
662 | * get_ep_limit - get the maximum data legnth for this endpoint | |
663 | * @hs_ep: The endpoint | |
664 | * | |
665 | * Return the maximum data that can be queued in one go on a given endpoint | |
666 | * so that transfers that are too long can be split. | |
667 | */ | |
9da51974 | 668 | static unsigned int get_ep_limit(struct dwc2_hsotg_ep *hs_ep) |
5b7d70c6 BD |
669 | { |
670 | int index = hs_ep->index; | |
9da51974 JY |
671 | unsigned int maxsize; |
672 | unsigned int maxpkt; | |
5b7d70c6 BD |
673 | |
674 | if (index != 0) { | |
47a1685f DN |
675 | maxsize = DXEPTSIZ_XFERSIZE_LIMIT + 1; |
676 | maxpkt = DXEPTSIZ_PKTCNT_LIMIT + 1; | |
5b7d70c6 | 677 | } else { |
9da51974 | 678 | maxsize = 64 + 64; |
66e5c643 | 679 | if (hs_ep->dir_in) |
47a1685f | 680 | maxpkt = DIEPTSIZ0_PKTCNT_LIMIT + 1; |
66e5c643 | 681 | else |
5b7d70c6 | 682 | maxpkt = 2; |
5b7d70c6 BD |
683 | } |
684 | ||
685 | /* we made the constant loading easier above by using +1 */ | |
686 | maxpkt--; | |
687 | maxsize--; | |
688 | ||
8b9bc460 LM |
689 | /* |
690 | * constrain by packet count if maxpkts*pktsize is greater | |
691 | * than the length register size. | |
692 | */ | |
5b7d70c6 BD |
693 | |
694 | if ((maxpkt * hs_ep->ep.maxpacket) < maxsize) | |
695 | maxsize = maxpkt * hs_ep->ep.maxpacket; | |
696 | ||
697 | return maxsize; | |
698 | } | |
699 | ||
381fc8f8 | 700 | /** |
38beaec6 JY |
701 | * dwc2_hsotg_read_frameno - read current frame number |
702 | * @hsotg: The device instance | |
703 | * | |
704 | * Return the current frame number | |
705 | */ | |
381fc8f8 VM |
706 | static u32 dwc2_hsotg_read_frameno(struct dwc2_hsotg *hsotg) |
707 | { | |
708 | u32 dsts; | |
709 | ||
f25c42b8 | 710 | dsts = dwc2_readl(hsotg, DSTS); |
381fc8f8 VM |
711 | dsts &= DSTS_SOFFN_MASK; |
712 | dsts >>= DSTS_SOFFN_SHIFT; | |
713 | ||
714 | return dsts; | |
715 | } | |
716 | ||
cf77b5fb VA |
717 | /** |
718 | * dwc2_gadget_get_chain_limit - get the maximum data payload value of the | |
719 | * DMA descriptor chain prepared for specific endpoint | |
720 | * @hs_ep: The endpoint | |
721 | * | |
722 | * Return the maximum data that can be queued in one go on a given endpoint | |
723 | * depending on its descriptor chain capacity so that transfers that | |
724 | * are too long can be split. | |
725 | */ | |
726 | static unsigned int dwc2_gadget_get_chain_limit(struct dwc2_hsotg_ep *hs_ep) | |
727 | { | |
b2c586eb | 728 | const struct usb_endpoint_descriptor *ep_desc = hs_ep->ep.desc; |
cf77b5fb VA |
729 | int is_isoc = hs_ep->isochronous; |
730 | unsigned int maxsize; | |
b2c586eb MH |
731 | u32 mps = hs_ep->ep.maxpacket; |
732 | int dir_in = hs_ep->dir_in; | |
cf77b5fb VA |
733 | |
734 | if (is_isoc) | |
54f37f56 MH |
735 | maxsize = (hs_ep->dir_in ? DEV_DMA_ISOC_TX_NBYTES_LIMIT : |
736 | DEV_DMA_ISOC_RX_NBYTES_LIMIT) * | |
737 | MAX_DMA_DESC_NUM_HS_ISOC; | |
cf77b5fb | 738 | else |
54f37f56 | 739 | maxsize = DEV_DMA_NBYTES_LIMIT * MAX_DMA_DESC_NUM_GENERIC; |
cf77b5fb | 740 | |
b2c586eb MH |
741 | /* Interrupt OUT EP with mps not multiple of 4 */ |
742 | if (hs_ep->index) | |
743 | if (usb_endpoint_xfer_int(ep_desc) && !dir_in && (mps % 4)) | |
744 | maxsize = mps * MAX_DMA_DESC_NUM_GENERIC; | |
745 | ||
cf77b5fb VA |
746 | return maxsize; |
747 | } | |
748 | ||
e02f9aa6 VA |
749 | /* |
750 | * dwc2_gadget_get_desc_params - get DMA descriptor parameters. | |
751 | * @hs_ep: The endpoint | |
752 | * @mask: RX/TX bytes mask to be defined | |
753 | * | |
754 | * Returns maximum data payload for one descriptor after analyzing endpoint | |
755 | * characteristics. | |
756 | * DMA descriptor transfer bytes limit depends on EP type: | |
757 | * Control out - MPS, | |
758 | * Isochronous - descriptor rx/tx bytes bitfield limit, | |
759 | * Control In/Bulk/Interrupt - multiple of mps. This will allow to not | |
760 | * have concatenations from various descriptors within one packet. | |
b2c586eb MH |
761 | * Interrupt OUT - if mps not multiple of 4 then a single packet corresponds |
762 | * to a single descriptor. | |
e02f9aa6 VA |
763 | * |
764 | * Selects corresponding mask for RX/TX bytes as well. | |
765 | */ | |
766 | static u32 dwc2_gadget_get_desc_params(struct dwc2_hsotg_ep *hs_ep, u32 *mask) | |
767 | { | |
b2c586eb | 768 | const struct usb_endpoint_descriptor *ep_desc = hs_ep->ep.desc; |
e02f9aa6 VA |
769 | u32 mps = hs_ep->ep.maxpacket; |
770 | int dir_in = hs_ep->dir_in; | |
771 | u32 desc_size = 0; | |
772 | ||
773 | if (!hs_ep->index && !dir_in) { | |
774 | desc_size = mps; | |
775 | *mask = DEV_DMA_NBYTES_MASK; | |
776 | } else if (hs_ep->isochronous) { | |
777 | if (dir_in) { | |
778 | desc_size = DEV_DMA_ISOC_TX_NBYTES_LIMIT; | |
779 | *mask = DEV_DMA_ISOC_TX_NBYTES_MASK; | |
780 | } else { | |
781 | desc_size = DEV_DMA_ISOC_RX_NBYTES_LIMIT; | |
782 | *mask = DEV_DMA_ISOC_RX_NBYTES_MASK; | |
783 | } | |
784 | } else { | |
785 | desc_size = DEV_DMA_NBYTES_LIMIT; | |
786 | *mask = DEV_DMA_NBYTES_MASK; | |
787 | ||
788 | /* Round down desc_size to be mps multiple */ | |
789 | desc_size -= desc_size % mps; | |
790 | } | |
791 | ||
b2c586eb MH |
792 | /* Interrupt OUT EP with mps not multiple of 4 */ |
793 | if (hs_ep->index) | |
794 | if (usb_endpoint_xfer_int(ep_desc) && !dir_in && (mps % 4)) { | |
795 | desc_size = mps; | |
796 | *mask = DEV_DMA_NBYTES_MASK; | |
797 | } | |
798 | ||
e02f9aa6 VA |
799 | return desc_size; |
800 | } | |
801 | ||
10209abe AP |
802 | static void dwc2_gadget_fill_nonisoc_xfer_ddma_one(struct dwc2_hsotg_ep *hs_ep, |
803 | struct dwc2_dma_desc **desc, | |
e02f9aa6 | 804 | dma_addr_t dma_buff, |
10209abe AP |
805 | unsigned int len, |
806 | bool true_last) | |
e02f9aa6 | 807 | { |
e02f9aa6 | 808 | int dir_in = hs_ep->dir_in; |
e02f9aa6 VA |
809 | u32 mps = hs_ep->ep.maxpacket; |
810 | u32 maxsize = 0; | |
811 | u32 offset = 0; | |
812 | u32 mask = 0; | |
813 | int i; | |
814 | ||
815 | maxsize = dwc2_gadget_get_desc_params(hs_ep, &mask); | |
816 | ||
817 | hs_ep->desc_count = (len / maxsize) + | |
818 | ((len % maxsize) ? 1 : 0); | |
819 | if (len == 0) | |
820 | hs_ep->desc_count = 1; | |
821 | ||
822 | for (i = 0; i < hs_ep->desc_count; ++i) { | |
10209abe AP |
823 | (*desc)->status = 0; |
824 | (*desc)->status |= (DEV_DMA_BUFF_STS_HBUSY | |
e02f9aa6 VA |
825 | << DEV_DMA_BUFF_STS_SHIFT); |
826 | ||
827 | if (len > maxsize) { | |
828 | if (!hs_ep->index && !dir_in) | |
10209abe | 829 | (*desc)->status |= (DEV_DMA_L | DEV_DMA_IOC); |
e02f9aa6 | 830 | |
10209abe AP |
831 | (*desc)->status |= |
832 | maxsize << DEV_DMA_NBYTES_SHIFT & mask; | |
833 | (*desc)->buf = dma_buff + offset; | |
e02f9aa6 VA |
834 | |
835 | len -= maxsize; | |
836 | offset += maxsize; | |
837 | } else { | |
10209abe AP |
838 | if (true_last) |
839 | (*desc)->status |= (DEV_DMA_L | DEV_DMA_IOC); | |
e02f9aa6 VA |
840 | |
841 | if (dir_in) | |
10209abe AP |
842 | (*desc)->status |= (len % mps) ? DEV_DMA_SHORT : |
843 | ((hs_ep->send_zlp && true_last) ? | |
844 | DEV_DMA_SHORT : 0); | |
e02f9aa6 | 845 | |
10209abe | 846 | (*desc)->status |= |
e02f9aa6 | 847 | len << DEV_DMA_NBYTES_SHIFT & mask; |
10209abe | 848 | (*desc)->buf = dma_buff + offset; |
e02f9aa6 VA |
849 | } |
850 | ||
10209abe AP |
851 | (*desc)->status &= ~DEV_DMA_BUFF_STS_MASK; |
852 | (*desc)->status |= (DEV_DMA_BUFF_STS_HREADY | |
e02f9aa6 | 853 | << DEV_DMA_BUFF_STS_SHIFT); |
10209abe AP |
854 | (*desc)++; |
855 | } | |
856 | } | |
857 | ||
858 | /* | |
859 | * dwc2_gadget_config_nonisoc_xfer_ddma - prepare non ISOC DMA desc chain. | |
860 | * @hs_ep: The endpoint | |
861 | * @ureq: Request to transfer | |
862 | * @offset: offset in bytes | |
863 | * @len: Length of the transfer | |
864 | * | |
865 | * This function will iterate over descriptor chain and fill its entries | |
866 | * with corresponding information based on transfer data. | |
867 | */ | |
868 | static void dwc2_gadget_config_nonisoc_xfer_ddma(struct dwc2_hsotg_ep *hs_ep, | |
066cfd07 | 869 | dma_addr_t dma_buff, |
10209abe AP |
870 | unsigned int len) |
871 | { | |
066cfd07 | 872 | struct usb_request *ureq = NULL; |
10209abe AP |
873 | struct dwc2_dma_desc *desc = hs_ep->desc_list; |
874 | struct scatterlist *sg; | |
875 | int i; | |
876 | u8 desc_count = 0; | |
877 | ||
066cfd07 AP |
878 | if (hs_ep->req) |
879 | ureq = &hs_ep->req->req; | |
880 | ||
10209abe | 881 | /* non-DMA sg buffer */ |
066cfd07 | 882 | if (!ureq || !ureq->num_sgs) { |
10209abe | 883 | dwc2_gadget_fill_nonisoc_xfer_ddma_one(hs_ep, &desc, |
066cfd07 | 884 | dma_buff, len, true); |
10209abe | 885 | return; |
e02f9aa6 | 886 | } |
10209abe AP |
887 | |
888 | /* DMA sg buffer */ | |
889 | for_each_sg(ureq->sg, sg, ureq->num_sgs, i) { | |
890 | dwc2_gadget_fill_nonisoc_xfer_ddma_one(hs_ep, &desc, | |
891 | sg_dma_address(sg) + sg->offset, sg_dma_len(sg), | |
892 | sg_is_last(sg)); | |
893 | desc_count += hs_ep->desc_count; | |
894 | } | |
895 | ||
896 | hs_ep->desc_count = desc_count; | |
e02f9aa6 VA |
897 | } |
898 | ||
540ccba0 VA |
899 | /* |
900 | * dwc2_gadget_fill_isoc_desc - fills next isochronous descriptor in chain. | |
901 | * @hs_ep: The isochronous endpoint. | |
902 | * @dma_buff: usb requests dma buffer. | |
903 | * @len: usb request transfer length. | |
904 | * | |
729cac69 | 905 | * Fills next free descriptor with the data of the arrived usb request, |
540ccba0 VA |
906 | * frame info, sets Last and IOC bits increments next_desc. If filled |
907 | * descriptor is not the first one, removes L bit from the previous descriptor | |
908 | * status. | |
909 | */ | |
910 | static int dwc2_gadget_fill_isoc_desc(struct dwc2_hsotg_ep *hs_ep, | |
911 | dma_addr_t dma_buff, unsigned int len) | |
912 | { | |
913 | struct dwc2_dma_desc *desc; | |
914 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
915 | u32 index; | |
540ccba0 | 916 | u32 mask = 0; |
1d8e5c00 | 917 | u8 pid = 0; |
540ccba0 | 918 | |
768a0741 | 919 | dwc2_gadget_get_desc_params(hs_ep, &mask); |
540ccba0 | 920 | |
729cac69 MH |
921 | index = hs_ep->next_desc; |
922 | desc = &hs_ep->desc_list[index]; | |
540ccba0 | 923 | |
729cac69 MH |
924 | /* Check if descriptor chain full */ |
925 | if ((desc->status >> DEV_DMA_BUFF_STS_SHIFT) == | |
926 | DEV_DMA_BUFF_STS_HREADY) { | |
927 | dev_dbg(hsotg->dev, "%s: desc chain full\n", __func__); | |
928 | return 1; | |
540ccba0 VA |
929 | } |
930 | ||
540ccba0 VA |
931 | /* Clear L bit of previous desc if more than one entries in the chain */ |
932 | if (hs_ep->next_desc) | |
933 | hs_ep->desc_list[index - 1].status &= ~DEV_DMA_L; | |
934 | ||
935 | dev_dbg(hsotg->dev, "%s: Filling ep %d, dir %s isoc desc # %d\n", | |
936 | __func__, hs_ep->index, hs_ep->dir_in ? "in" : "out", index); | |
937 | ||
938 | desc->status = 0; | |
939 | desc->status |= (DEV_DMA_BUFF_STS_HBUSY << DEV_DMA_BUFF_STS_SHIFT); | |
940 | ||
941 | desc->buf = dma_buff; | |
942 | desc->status |= (DEV_DMA_L | DEV_DMA_IOC | | |
943 | ((len << DEV_DMA_NBYTES_SHIFT) & mask)); | |
944 | ||
945 | if (hs_ep->dir_in) { | |
1d8e5c00 MH |
946 | if (len) |
947 | pid = DIV_ROUND_UP(len, hs_ep->ep.maxpacket); | |
948 | else | |
949 | pid = 1; | |
950 | desc->status |= ((pid << DEV_DMA_ISOC_PID_SHIFT) & | |
540ccba0 VA |
951 | DEV_DMA_ISOC_PID_MASK) | |
952 | ((len % hs_ep->ep.maxpacket) ? | |
953 | DEV_DMA_SHORT : 0) | | |
954 | ((hs_ep->target_frame << | |
955 | DEV_DMA_ISOC_FRNUM_SHIFT) & | |
956 | DEV_DMA_ISOC_FRNUM_MASK); | |
957 | } | |
958 | ||
959 | desc->status &= ~DEV_DMA_BUFF_STS_MASK; | |
960 | desc->status |= (DEV_DMA_BUFF_STS_HREADY << DEV_DMA_BUFF_STS_SHIFT); | |
961 | ||
729cac69 MH |
962 | /* Increment frame number by interval for IN */ |
963 | if (hs_ep->dir_in) | |
964 | dwc2_gadget_incr_frame_num(hs_ep); | |
965 | ||
540ccba0 VA |
966 | /* Update index of last configured entry in the chain */ |
967 | hs_ep->next_desc++; | |
54f37f56 | 968 | if (hs_ep->next_desc >= MAX_DMA_DESC_NUM_HS_ISOC) |
729cac69 | 969 | hs_ep->next_desc = 0; |
540ccba0 VA |
970 | |
971 | return 0; | |
972 | } | |
973 | ||
974 | /* | |
975 | * dwc2_gadget_start_isoc_ddma - start isochronous transfer in DDMA | |
976 | * @hs_ep: The isochronous endpoint. | |
977 | * | |
729cac69 | 978 | * Prepare descriptor chain for isochronous endpoints. Afterwards |
540ccba0 | 979 | * write DMA address to HW and enable the endpoint. |
540ccba0 VA |
980 | */ |
981 | static void dwc2_gadget_start_isoc_ddma(struct dwc2_hsotg_ep *hs_ep) | |
982 | { | |
983 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
984 | struct dwc2_hsotg_req *hs_req, *treq; | |
985 | int index = hs_ep->index; | |
986 | int ret; | |
729cac69 | 987 | int i; |
540ccba0 VA |
988 | u32 dma_reg; |
989 | u32 depctl; | |
990 | u32 ctrl; | |
729cac69 | 991 | struct dwc2_dma_desc *desc; |
540ccba0 VA |
992 | |
993 | if (list_empty(&hs_ep->queue)) { | |
1ffba905 | 994 | hs_ep->target_frame = TARGET_FRAME_INITIAL; |
540ccba0 VA |
995 | dev_dbg(hsotg->dev, "%s: No requests in queue\n", __func__); |
996 | return; | |
997 | } | |
998 | ||
729cac69 | 999 | /* Initialize descriptor chain by Host Busy status */ |
54f37f56 | 1000 | for (i = 0; i < MAX_DMA_DESC_NUM_HS_ISOC; i++) { |
729cac69 MH |
1001 | desc = &hs_ep->desc_list[i]; |
1002 | desc->status = 0; | |
1003 | desc->status |= (DEV_DMA_BUFF_STS_HBUSY | |
1004 | << DEV_DMA_BUFF_STS_SHIFT); | |
1005 | } | |
1006 | ||
1007 | hs_ep->next_desc = 0; | |
540ccba0 | 1008 | list_for_each_entry_safe(hs_req, treq, &hs_ep->queue, queue) { |
10209abe AP |
1009 | dma_addr_t dma_addr = hs_req->req.dma; |
1010 | ||
1011 | if (hs_req->req.num_sgs) { | |
1012 | WARN_ON(hs_req->req.num_sgs > 1); | |
1013 | dma_addr = sg_dma_address(hs_req->req.sg); | |
1014 | } | |
1015 | ret = dwc2_gadget_fill_isoc_desc(hs_ep, dma_addr, | |
540ccba0 | 1016 | hs_req->req.length); |
729cac69 | 1017 | if (ret) |
540ccba0 | 1018 | break; |
540ccba0 VA |
1019 | } |
1020 | ||
729cac69 | 1021 | hs_ep->compl_desc = 0; |
540ccba0 VA |
1022 | depctl = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index); |
1023 | dma_reg = hs_ep->dir_in ? DIEPDMA(index) : DOEPDMA(index); | |
1024 | ||
1025 | /* write descriptor chain address to control register */ | |
f25c42b8 | 1026 | dwc2_writel(hsotg, hs_ep->desc_list_dma, dma_reg); |
540ccba0 | 1027 | |
f25c42b8 | 1028 | ctrl = dwc2_readl(hsotg, depctl); |
540ccba0 | 1029 | ctrl |= DXEPCTL_EPENA | DXEPCTL_CNAK; |
f25c42b8 | 1030 | dwc2_writel(hsotg, ctrl, depctl); |
540ccba0 VA |
1031 | } |
1032 | ||
91bb163e MH |
1033 | static bool dwc2_gadget_target_frame_elapsed(struct dwc2_hsotg_ep *hs_ep); |
1034 | static void dwc2_hsotg_complete_request(struct dwc2_hsotg *hsotg, | |
1035 | struct dwc2_hsotg_ep *hs_ep, | |
1036 | struct dwc2_hsotg_req *hs_req, | |
1037 | int result); | |
1038 | ||
5b7d70c6 | 1039 | /** |
1f91b4cc | 1040 | * dwc2_hsotg_start_req - start a USB request from an endpoint's queue |
5b7d70c6 BD |
1041 | * @hsotg: The controller state. |
1042 | * @hs_ep: The endpoint to process a request for | |
1043 | * @hs_req: The request to start. | |
1044 | * @continuing: True if we are doing more for the current request. | |
1045 | * | |
1046 | * Start the given request running by setting the endpoint registers | |
1047 | * appropriately, and writing any data to the FIFOs. | |
1048 | */ | |
1f91b4cc | 1049 | static void dwc2_hsotg_start_req(struct dwc2_hsotg *hsotg, |
9da51974 | 1050 | struct dwc2_hsotg_ep *hs_ep, |
1f91b4cc | 1051 | struct dwc2_hsotg_req *hs_req, |
5b7d70c6 BD |
1052 | bool continuing) |
1053 | { | |
1054 | struct usb_request *ureq = &hs_req->req; | |
1055 | int index = hs_ep->index; | |
1056 | int dir_in = hs_ep->dir_in; | |
1057 | u32 epctrl_reg; | |
1058 | u32 epsize_reg; | |
1059 | u32 epsize; | |
1060 | u32 ctrl; | |
9da51974 JY |
1061 | unsigned int length; |
1062 | unsigned int packets; | |
1063 | unsigned int maxreq; | |
aa3e8bc8 | 1064 | unsigned int dma_reg; |
5b7d70c6 BD |
1065 | |
1066 | if (index != 0) { | |
1067 | if (hs_ep->req && !continuing) { | |
1068 | dev_err(hsotg->dev, "%s: active request\n", __func__); | |
1069 | WARN_ON(1); | |
1070 | return; | |
1071 | } else if (hs_ep->req != hs_req && continuing) { | |
1072 | dev_err(hsotg->dev, | |
1073 | "%s: continue different req\n", __func__); | |
1074 | WARN_ON(1); | |
1075 | return; | |
1076 | } | |
1077 | } | |
1078 | ||
aa3e8bc8 | 1079 | dma_reg = dir_in ? DIEPDMA(index) : DOEPDMA(index); |
94cb8fd6 LM |
1080 | epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index); |
1081 | epsize_reg = dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index); | |
5b7d70c6 BD |
1082 | |
1083 | dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n", | |
f25c42b8 | 1084 | __func__, dwc2_readl(hsotg, epctrl_reg), index, |
5b7d70c6 BD |
1085 | hs_ep->dir_in ? "in" : "out"); |
1086 | ||
9c39ddc6 | 1087 | /* If endpoint is stalled, we will restart request later */ |
f25c42b8 | 1088 | ctrl = dwc2_readl(hsotg, epctrl_reg); |
9c39ddc6 | 1089 | |
b2d4c54e | 1090 | if (index && ctrl & DXEPCTL_STALL) { |
9c39ddc6 AT |
1091 | dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index); |
1092 | return; | |
1093 | } | |
1094 | ||
5b7d70c6 | 1095 | length = ureq->length - ureq->actual; |
71225bee LM |
1096 | dev_dbg(hsotg->dev, "ureq->length:%d ureq->actual:%d\n", |
1097 | ureq->length, ureq->actual); | |
5b7d70c6 | 1098 | |
cf77b5fb VA |
1099 | if (!using_desc_dma(hsotg)) |
1100 | maxreq = get_ep_limit(hs_ep); | |
1101 | else | |
1102 | maxreq = dwc2_gadget_get_chain_limit(hs_ep); | |
1103 | ||
5b7d70c6 BD |
1104 | if (length > maxreq) { |
1105 | int round = maxreq % hs_ep->ep.maxpacket; | |
1106 | ||
1107 | dev_dbg(hsotg->dev, "%s: length %d, max-req %d, r %d\n", | |
1108 | __func__, length, maxreq, round); | |
1109 | ||
1110 | /* round down to multiple of packets */ | |
1111 | if (round) | |
1112 | maxreq -= round; | |
1113 | ||
1114 | length = maxreq; | |
1115 | } | |
1116 | ||
1117 | if (length) | |
1118 | packets = DIV_ROUND_UP(length, hs_ep->ep.maxpacket); | |
1119 | else | |
1120 | packets = 1; /* send one packet if length is zero. */ | |
1121 | ||
1122 | if (dir_in && index != 0) | |
4fca54aa | 1123 | if (hs_ep->isochronous) |
47a1685f | 1124 | epsize = DXEPTSIZ_MC(packets); |
4fca54aa | 1125 | else |
47a1685f | 1126 | epsize = DXEPTSIZ_MC(1); |
5b7d70c6 BD |
1127 | else |
1128 | epsize = 0; | |
1129 | ||
f71b5e25 MYK |
1130 | /* |
1131 | * zero length packet should be programmed on its own and should not | |
1132 | * be counted in DIEPTSIZ.PktCnt with other packets. | |
1133 | */ | |
1134 | if (dir_in && ureq->zero && !continuing) { | |
1135 | /* Test if zlp is actually required. */ | |
1136 | if ((ureq->length >= hs_ep->ep.maxpacket) && | |
9da51974 | 1137 | !(ureq->length % hs_ep->ep.maxpacket)) |
8a20fa45 | 1138 | hs_ep->send_zlp = 1; |
5b7d70c6 BD |
1139 | } |
1140 | ||
47a1685f DN |
1141 | epsize |= DXEPTSIZ_PKTCNT(packets); |
1142 | epsize |= DXEPTSIZ_XFERSIZE(length); | |
5b7d70c6 BD |
1143 | |
1144 | dev_dbg(hsotg->dev, "%s: %d@%d/%d, 0x%08x => 0x%08x\n", | |
1145 | __func__, packets, length, ureq->length, epsize, epsize_reg); | |
1146 | ||
1147 | /* store the request as the current one we're doing */ | |
1148 | hs_ep->req = hs_req; | |
1149 | ||
aa3e8bc8 VA |
1150 | if (using_desc_dma(hsotg)) { |
1151 | u32 offset = 0; | |
1152 | u32 mps = hs_ep->ep.maxpacket; | |
1153 | ||
1154 | /* Adjust length: EP0 - MPS, other OUT EPs - multiple of MPS */ | |
1155 | if (!dir_in) { | |
1156 | if (!index) | |
1157 | length = mps; | |
1158 | else if (length % mps) | |
1159 | length += (mps - (length % mps)); | |
1160 | } | |
5b7d70c6 | 1161 | |
b2c586eb | 1162 | if (continuing) |
aa3e8bc8 VA |
1163 | offset = ureq->actual; |
1164 | ||
1165 | /* Fill DDMA chain entries */ | |
066cfd07 | 1166 | dwc2_gadget_config_nonisoc_xfer_ddma(hs_ep, ureq->dma + offset, |
aa3e8bc8 VA |
1167 | length); |
1168 | ||
1169 | /* write descriptor chain address to control register */ | |
f25c42b8 | 1170 | dwc2_writel(hsotg, hs_ep->desc_list_dma, dma_reg); |
5b7d70c6 | 1171 | |
aa3e8bc8 VA |
1172 | dev_dbg(hsotg->dev, "%s: %08x pad => 0x%08x\n", |
1173 | __func__, (u32)hs_ep->desc_list_dma, dma_reg); | |
1174 | } else { | |
1175 | /* write size / packets */ | |
f25c42b8 | 1176 | dwc2_writel(hsotg, epsize, epsize_reg); |
aa3e8bc8 | 1177 | |
729e6574 | 1178 | if (using_dma(hsotg) && !continuing && (length != 0)) { |
aa3e8bc8 VA |
1179 | /* |
1180 | * write DMA address to control register, buffer | |
1181 | * already synced by dwc2_hsotg_ep_queue(). | |
1182 | */ | |
5b7d70c6 | 1183 | |
f25c42b8 | 1184 | dwc2_writel(hsotg, ureq->dma, dma_reg); |
aa3e8bc8 VA |
1185 | |
1186 | dev_dbg(hsotg->dev, "%s: %pad => 0x%08x\n", | |
1187 | __func__, &ureq->dma, dma_reg); | |
1188 | } | |
5b7d70c6 BD |
1189 | } |
1190 | ||
91bb163e MH |
1191 | if (hs_ep->isochronous) { |
1192 | if (!dwc2_gadget_target_frame_elapsed(hs_ep)) { | |
1193 | if (hs_ep->interval == 1) { | |
1194 | if (hs_ep->target_frame & 0x1) | |
1195 | ctrl |= DXEPCTL_SETODDFR; | |
1196 | else | |
1197 | ctrl |= DXEPCTL_SETEVENFR; | |
1198 | } | |
1199 | ctrl |= DXEPCTL_CNAK; | |
1200 | } else { | |
7ad4a0b1 MH |
1201 | hs_req->req.frame_number = hs_ep->target_frame; |
1202 | hs_req->req.actual = 0; | |
91bb163e MH |
1203 | dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, -ENODATA); |
1204 | return; | |
1205 | } | |
837e9f00 VM |
1206 | } |
1207 | ||
47a1685f | 1208 | ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */ |
71225bee | 1209 | |
fe0b94ab | 1210 | dev_dbg(hsotg->dev, "ep0 state:%d\n", hsotg->ep0_state); |
71225bee LM |
1211 | |
1212 | /* For Setup request do not clear NAK */ | |
fe0b94ab | 1213 | if (!(index == 0 && hsotg->ep0_state == DWC2_EP0_SETUP)) |
47a1685f | 1214 | ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */ |
71225bee | 1215 | |
5b7d70c6 | 1216 | dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl); |
f25c42b8 | 1217 | dwc2_writel(hsotg, ctrl, epctrl_reg); |
5b7d70c6 | 1218 | |
8b9bc460 LM |
1219 | /* |
1220 | * set these, it seems that DMA support increments past the end | |
5b7d70c6 | 1221 | * of the packet buffer so we need to calculate the length from |
8b9bc460 LM |
1222 | * this information. |
1223 | */ | |
5b7d70c6 BD |
1224 | hs_ep->size_loaded = length; |
1225 | hs_ep->last_load = ureq->actual; | |
1226 | ||
1227 | if (dir_in && !using_dma(hsotg)) { | |
1228 | /* set these anyway, we may need them for non-periodic in */ | |
1229 | hs_ep->fifo_load = 0; | |
1230 | ||
1f91b4cc | 1231 | dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req); |
5b7d70c6 BD |
1232 | } |
1233 | ||
8b9bc460 LM |
1234 | /* |
1235 | * Note, trying to clear the NAK here causes problems with transmit | |
1236 | * on the S3C6400 ending up with the TXFIFO becoming full. | |
1237 | */ | |
5b7d70c6 BD |
1238 | |
1239 | /* check ep is enabled */ | |
f25c42b8 | 1240 | if (!(dwc2_readl(hsotg, epctrl_reg) & DXEPCTL_EPENA)) |
1a0ed863 | 1241 | dev_dbg(hsotg->dev, |
9da51974 | 1242 | "ep%d: failed to become enabled (DXEPCTL=0x%08x)?\n", |
f25c42b8 | 1243 | index, dwc2_readl(hsotg, epctrl_reg)); |
5b7d70c6 | 1244 | |
47a1685f | 1245 | dev_dbg(hsotg->dev, "%s: DXEPCTL=0x%08x\n", |
f25c42b8 | 1246 | __func__, dwc2_readl(hsotg, epctrl_reg)); |
afcf4169 RB |
1247 | |
1248 | /* enable ep interrupts */ | |
1f91b4cc | 1249 | dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 1); |
5b7d70c6 BD |
1250 | } |
1251 | ||
1252 | /** | |
1f91b4cc | 1253 | * dwc2_hsotg_map_dma - map the DMA memory being used for the request |
5b7d70c6 BD |
1254 | * @hsotg: The device state. |
1255 | * @hs_ep: The endpoint the request is on. | |
1256 | * @req: The request being processed. | |
1257 | * | |
1258 | * We've been asked to queue a request, so ensure that the memory buffer | |
1259 | * is correctly setup for DMA. If we've been passed an extant DMA address | |
1260 | * then ensure the buffer has been synced to memory. If our buffer has no | |
1261 | * DMA memory, then we map the memory and mark our request to allow us to | |
1262 | * cleanup on completion. | |
8b9bc460 | 1263 | */ |
1f91b4cc | 1264 | static int dwc2_hsotg_map_dma(struct dwc2_hsotg *hsotg, |
9da51974 | 1265 | struct dwc2_hsotg_ep *hs_ep, |
5b7d70c6 BD |
1266 | struct usb_request *req) |
1267 | { | |
e58ebcd1 | 1268 | int ret; |
5b7d70c6 | 1269 | |
75a41ce4 | 1270 | hs_ep->map_dir = hs_ep->dir_in; |
e58ebcd1 FB |
1271 | ret = usb_gadget_map_request(&hsotg->gadget, req, hs_ep->dir_in); |
1272 | if (ret) | |
1273 | goto dma_error; | |
5b7d70c6 BD |
1274 | |
1275 | return 0; | |
1276 | ||
1277 | dma_error: | |
1278 | dev_err(hsotg->dev, "%s: failed to map buffer %p, %d bytes\n", | |
1279 | __func__, req->buf, req->length); | |
1280 | ||
1281 | return -EIO; | |
1282 | } | |
1283 | ||
1f91b4cc | 1284 | static int dwc2_hsotg_handle_unaligned_buf_start(struct dwc2_hsotg *hsotg, |
b98866c2 JY |
1285 | struct dwc2_hsotg_ep *hs_ep, |
1286 | struct dwc2_hsotg_req *hs_req) | |
7d24c1b5 MYK |
1287 | { |
1288 | void *req_buf = hs_req->req.buf; | |
1289 | ||
1290 | /* If dma is not being used or buffer is aligned */ | |
1291 | if (!using_dma(hsotg) || !((long)req_buf & 3)) | |
1292 | return 0; | |
1293 | ||
1294 | WARN_ON(hs_req->saved_req_buf); | |
1295 | ||
1296 | dev_dbg(hsotg->dev, "%s: %s: buf=%p length=%d\n", __func__, | |
9da51974 | 1297 | hs_ep->ep.name, req_buf, hs_req->req.length); |
7d24c1b5 MYK |
1298 | |
1299 | hs_req->req.buf = kmalloc(hs_req->req.length, GFP_ATOMIC); | |
1300 | if (!hs_req->req.buf) { | |
1301 | hs_req->req.buf = req_buf; | |
1302 | dev_err(hsotg->dev, | |
1303 | "%s: unable to allocate memory for bounce buffer\n", | |
1304 | __func__); | |
1305 | return -ENOMEM; | |
1306 | } | |
1307 | ||
1308 | /* Save actual buffer */ | |
1309 | hs_req->saved_req_buf = req_buf; | |
1310 | ||
1311 | if (hs_ep->dir_in) | |
1312 | memcpy(hs_req->req.buf, req_buf, hs_req->req.length); | |
1313 | return 0; | |
1314 | } | |
1315 | ||
b98866c2 JY |
1316 | static void |
1317 | dwc2_hsotg_handle_unaligned_buf_complete(struct dwc2_hsotg *hsotg, | |
1318 | struct dwc2_hsotg_ep *hs_ep, | |
1319 | struct dwc2_hsotg_req *hs_req) | |
7d24c1b5 MYK |
1320 | { |
1321 | /* If dma is not being used or buffer was aligned */ | |
1322 | if (!using_dma(hsotg) || !hs_req->saved_req_buf) | |
1323 | return; | |
1324 | ||
1325 | dev_dbg(hsotg->dev, "%s: %s: status=%d actual-length=%d\n", __func__, | |
1326 | hs_ep->ep.name, hs_req->req.status, hs_req->req.actual); | |
1327 | ||
1328 | /* Copy data from bounce buffer on successful out transfer */ | |
1329 | if (!hs_ep->dir_in && !hs_req->req.status) | |
1330 | memcpy(hs_req->saved_req_buf, hs_req->req.buf, | |
9da51974 | 1331 | hs_req->req.actual); |
7d24c1b5 MYK |
1332 | |
1333 | /* Free bounce buffer */ | |
1334 | kfree(hs_req->req.buf); | |
1335 | ||
1336 | hs_req->req.buf = hs_req->saved_req_buf; | |
1337 | hs_req->saved_req_buf = NULL; | |
1338 | } | |
1339 | ||
381fc8f8 VM |
1340 | /** |
1341 | * dwc2_gadget_target_frame_elapsed - Checks target frame | |
1342 | * @hs_ep: The driver endpoint to check | |
1343 | * | |
1344 | * Returns 1 if targeted frame elapsed. If returned 1 then we need to drop | |
1345 | * corresponding transfer. | |
1346 | */ | |
1347 | static bool dwc2_gadget_target_frame_elapsed(struct dwc2_hsotg_ep *hs_ep) | |
1348 | { | |
1349 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
1350 | u32 target_frame = hs_ep->target_frame; | |
c7c24e7a | 1351 | u32 current_frame = hsotg->frame_number; |
381fc8f8 | 1352 | bool frame_overrun = hs_ep->frame_overrun; |
91bb163e MH |
1353 | u16 limit = DSTS_SOFFN_LIMIT; |
1354 | ||
1355 | if (hsotg->gadget.speed != USB_SPEED_HIGH) | |
1356 | limit >>= 3; | |
381fc8f8 VM |
1357 | |
1358 | if (!frame_overrun && current_frame >= target_frame) | |
1359 | return true; | |
1360 | ||
1361 | if (frame_overrun && current_frame >= target_frame && | |
91bb163e | 1362 | ((current_frame - target_frame) < limit / 2)) |
381fc8f8 VM |
1363 | return true; |
1364 | ||
1365 | return false; | |
1366 | } | |
1367 | ||
e02f9aa6 VA |
1368 | /* |
1369 | * dwc2_gadget_set_ep0_desc_chain - Set EP's desc chain pointers | |
1370 | * @hsotg: The driver state | |
1371 | * @hs_ep: the ep descriptor chain is for | |
1372 | * | |
1373 | * Called to update EP0 structure's pointers depend on stage of | |
1374 | * control transfer. | |
1375 | */ | |
1376 | static int dwc2_gadget_set_ep0_desc_chain(struct dwc2_hsotg *hsotg, | |
1377 | struct dwc2_hsotg_ep *hs_ep) | |
1378 | { | |
1379 | switch (hsotg->ep0_state) { | |
1380 | case DWC2_EP0_SETUP: | |
1381 | case DWC2_EP0_STATUS_OUT: | |
1382 | hs_ep->desc_list = hsotg->setup_desc[0]; | |
1383 | hs_ep->desc_list_dma = hsotg->setup_desc_dma[0]; | |
1384 | break; | |
1385 | case DWC2_EP0_DATA_IN: | |
1386 | case DWC2_EP0_STATUS_IN: | |
1387 | hs_ep->desc_list = hsotg->ctrl_in_desc; | |
1388 | hs_ep->desc_list_dma = hsotg->ctrl_in_desc_dma; | |
1389 | break; | |
1390 | case DWC2_EP0_DATA_OUT: | |
1391 | hs_ep->desc_list = hsotg->ctrl_out_desc; | |
1392 | hs_ep->desc_list_dma = hsotg->ctrl_out_desc_dma; | |
1393 | break; | |
1394 | default: | |
1395 | dev_err(hsotg->dev, "invalid EP 0 state in queue %d\n", | |
1396 | hsotg->ep0_state); | |
1397 | return -EINVAL; | |
1398 | } | |
1399 | ||
1400 | return 0; | |
1401 | } | |
1402 | ||
1f91b4cc | 1403 | static int dwc2_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req, |
9da51974 | 1404 | gfp_t gfp_flags) |
5b7d70c6 | 1405 | { |
1f91b4cc FB |
1406 | struct dwc2_hsotg_req *hs_req = our_req(req); |
1407 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); | |
941fcce4 | 1408 | struct dwc2_hsotg *hs = hs_ep->parent; |
5b7d70c6 | 1409 | bool first; |
7d24c1b5 | 1410 | int ret; |
729cac69 MH |
1411 | u32 maxsize = 0; |
1412 | u32 mask = 0; | |
1413 | ||
5b7d70c6 BD |
1414 | |
1415 | dev_dbg(hs->dev, "%s: req %p: %d@%p, noi=%d, zero=%d, snok=%d\n", | |
1416 | ep->name, req, req->length, req->buf, req->no_interrupt, | |
1417 | req->zero, req->short_not_ok); | |
1418 | ||
7ababa92 | 1419 | /* Prevent new request submission when controller is suspended */ |
88b02f2c GT |
1420 | if (hs->lx_state != DWC2_L0) { |
1421 | dev_dbg(hs->dev, "%s: submit request only in active state\n", | |
9da51974 | 1422 | __func__); |
7ababa92 GH |
1423 | return -EAGAIN; |
1424 | } | |
1425 | ||
5b7d70c6 BD |
1426 | /* initialise status of the request */ |
1427 | INIT_LIST_HEAD(&hs_req->queue); | |
1428 | req->actual = 0; | |
1429 | req->status = -EINPROGRESS; | |
1430 | ||
860ef6cd MH |
1431 | /* Don't queue ISOC request if length greater than mps*mc */ |
1432 | if (hs_ep->isochronous && | |
1433 | req->length > (hs_ep->mc * hs_ep->ep.maxpacket)) { | |
1434 | dev_err(hs->dev, "req length > maxpacket*mc\n"); | |
1435 | return -EINVAL; | |
1436 | } | |
1437 | ||
729cac69 MH |
1438 | /* In DDMA mode for ISOC's don't queue request if length greater |
1439 | * than descriptor limits. | |
1440 | */ | |
1441 | if (using_desc_dma(hs) && hs_ep->isochronous) { | |
1442 | maxsize = dwc2_gadget_get_desc_params(hs_ep, &mask); | |
1443 | if (hs_ep->dir_in && req->length > maxsize) { | |
1444 | dev_err(hs->dev, "wrong length %d (maxsize=%d)\n", | |
1445 | req->length, maxsize); | |
1446 | return -EINVAL; | |
1447 | } | |
1448 | ||
1449 | if (!hs_ep->dir_in && req->length > hs_ep->ep.maxpacket) { | |
1450 | dev_err(hs->dev, "ISOC OUT: wrong length %d (mps=%d)\n", | |
1451 | req->length, hs_ep->ep.maxpacket); | |
1452 | return -EINVAL; | |
1453 | } | |
1454 | } | |
1455 | ||
1f91b4cc | 1456 | ret = dwc2_hsotg_handle_unaligned_buf_start(hs, hs_ep, hs_req); |
7d24c1b5 MYK |
1457 | if (ret) |
1458 | return ret; | |
1459 | ||
5b7d70c6 BD |
1460 | /* if we're using DMA, sync the buffers as necessary */ |
1461 | if (using_dma(hs)) { | |
1f91b4cc | 1462 | ret = dwc2_hsotg_map_dma(hs, hs_ep, req); |
5b7d70c6 BD |
1463 | if (ret) |
1464 | return ret; | |
1465 | } | |
e02f9aa6 VA |
1466 | /* If using descriptor DMA configure EP0 descriptor chain pointers */ |
1467 | if (using_desc_dma(hs) && !hs_ep->index) { | |
1468 | ret = dwc2_gadget_set_ep0_desc_chain(hs, hs_ep); | |
1469 | if (ret) | |
1470 | return ret; | |
1471 | } | |
5b7d70c6 | 1472 | |
5b7d70c6 BD |
1473 | first = list_empty(&hs_ep->queue); |
1474 | list_add_tail(&hs_req->queue, &hs_ep->queue); | |
1475 | ||
540ccba0 VA |
1476 | /* |
1477 | * Handle DDMA isochronous transfers separately - just add new entry | |
729cac69 | 1478 | * to the descriptor chain. |
540ccba0 VA |
1479 | * Transfer will be started once SW gets either one of NAK or |
1480 | * OutTknEpDis interrupts. | |
1481 | */ | |
729cac69 MH |
1482 | if (using_desc_dma(hs) && hs_ep->isochronous) { |
1483 | if (hs_ep->target_frame != TARGET_FRAME_INITIAL) { | |
10209abe AP |
1484 | dma_addr_t dma_addr = hs_req->req.dma; |
1485 | ||
1486 | if (hs_req->req.num_sgs) { | |
1487 | WARN_ON(hs_req->req.num_sgs > 1); | |
1488 | dma_addr = sg_dma_address(hs_req->req.sg); | |
1489 | } | |
1490 | dwc2_gadget_fill_isoc_desc(hs_ep, dma_addr, | |
729cac69 MH |
1491 | hs_req->req.length); |
1492 | } | |
540ccba0 VA |
1493 | return 0; |
1494 | } | |
1495 | ||
b4c53b4a MH |
1496 | /* Change EP direction if status phase request is after data out */ |
1497 | if (!hs_ep->index && !req->length && !hs_ep->dir_in && | |
1498 | hs->ep0_state == DWC2_EP0_DATA_OUT) | |
1499 | hs_ep->dir_in = 1; | |
1500 | ||
837e9f00 VM |
1501 | if (first) { |
1502 | if (!hs_ep->isochronous) { | |
1503 | dwc2_hsotg_start_req(hs, hs_ep, hs_req, false); | |
1504 | return 0; | |
1505 | } | |
1506 | ||
c7c24e7a AP |
1507 | /* Update current frame number value. */ |
1508 | hs->frame_number = dwc2_hsotg_read_frameno(hs); | |
1509 | while (dwc2_gadget_target_frame_elapsed(hs_ep)) { | |
837e9f00 | 1510 | dwc2_gadget_incr_frame_num(hs_ep); |
c7c24e7a AP |
1511 | /* Update current frame number value once more as it |
1512 | * changes here. | |
1513 | */ | |
1514 | hs->frame_number = dwc2_hsotg_read_frameno(hs); | |
1515 | } | |
5b7d70c6 | 1516 | |
837e9f00 VM |
1517 | if (hs_ep->target_frame != TARGET_FRAME_INITIAL) |
1518 | dwc2_hsotg_start_req(hs, hs_ep, hs_req, false); | |
1519 | } | |
5b7d70c6 BD |
1520 | return 0; |
1521 | } | |
1522 | ||
1f91b4cc | 1523 | static int dwc2_hsotg_ep_queue_lock(struct usb_ep *ep, struct usb_request *req, |
9da51974 | 1524 | gfp_t gfp_flags) |
5ad1d316 | 1525 | { |
1f91b4cc | 1526 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 1527 | struct dwc2_hsotg *hs = hs_ep->parent; |
8879904b JH |
1528 | unsigned long flags; |
1529 | int ret; | |
5ad1d316 LM |
1530 | |
1531 | spin_lock_irqsave(&hs->lock, flags); | |
1f91b4cc | 1532 | ret = dwc2_hsotg_ep_queue(ep, req, gfp_flags); |
5ad1d316 LM |
1533 | spin_unlock_irqrestore(&hs->lock, flags); |
1534 | ||
1535 | return ret; | |
1536 | } | |
1537 | ||
1f91b4cc | 1538 | static void dwc2_hsotg_ep_free_request(struct usb_ep *ep, |
9da51974 | 1539 | struct usb_request *req) |
5b7d70c6 | 1540 | { |
1f91b4cc | 1541 | struct dwc2_hsotg_req *hs_req = our_req(req); |
5b7d70c6 BD |
1542 | |
1543 | kfree(hs_req); | |
1544 | } | |
1545 | ||
1546 | /** | |
1f91b4cc | 1547 | * dwc2_hsotg_complete_oursetup - setup completion callback |
5b7d70c6 BD |
1548 | * @ep: The endpoint the request was on. |
1549 | * @req: The request completed. | |
1550 | * | |
1551 | * Called on completion of any requests the driver itself | |
1552 | * submitted that need cleaning up. | |
1553 | */ | |
1f91b4cc | 1554 | static void dwc2_hsotg_complete_oursetup(struct usb_ep *ep, |
9da51974 | 1555 | struct usb_request *req) |
5b7d70c6 | 1556 | { |
1f91b4cc | 1557 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 1558 | struct dwc2_hsotg *hsotg = hs_ep->parent; |
5b7d70c6 BD |
1559 | |
1560 | dev_dbg(hsotg->dev, "%s: ep %p, req %p\n", __func__, ep, req); | |
1561 | ||
1f91b4cc | 1562 | dwc2_hsotg_ep_free_request(ep, req); |
5b7d70c6 BD |
1563 | } |
1564 | ||
1565 | /** | |
1566 | * ep_from_windex - convert control wIndex value to endpoint | |
1567 | * @hsotg: The driver state. | |
1568 | * @windex: The control request wIndex field (in host order). | |
1569 | * | |
1570 | * Convert the given wIndex into a pointer to an driver endpoint | |
1571 | * structure, or return NULL if it is not a valid endpoint. | |
8b9bc460 | 1572 | */ |
1f91b4cc | 1573 | static struct dwc2_hsotg_ep *ep_from_windex(struct dwc2_hsotg *hsotg, |
9da51974 | 1574 | u32 windex) |
5b7d70c6 | 1575 | { |
5b7d70c6 BD |
1576 | int dir = (windex & USB_DIR_IN) ? 1 : 0; |
1577 | int idx = windex & 0x7F; | |
1578 | ||
1579 | if (windex >= 0x100) | |
1580 | return NULL; | |
1581 | ||
b3f489b2 | 1582 | if (idx > hsotg->num_of_eps) |
5b7d70c6 BD |
1583 | return NULL; |
1584 | ||
f670e9f9 | 1585 | return index_to_ep(hsotg, idx, dir); |
5b7d70c6 BD |
1586 | } |
1587 | ||
9e14d0a5 | 1588 | /** |
1f91b4cc | 1589 | * dwc2_hsotg_set_test_mode - Enable usb Test Modes |
9e14d0a5 GH |
1590 | * @hsotg: The driver state. |
1591 | * @testmode: requested usb test mode | |
1592 | * Enable usb Test Mode requested by the Host. | |
1593 | */ | |
1f91b4cc | 1594 | int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode) |
9e14d0a5 | 1595 | { |
f25c42b8 | 1596 | int dctl = dwc2_readl(hsotg, DCTL); |
9e14d0a5 GH |
1597 | |
1598 | dctl &= ~DCTL_TSTCTL_MASK; | |
1599 | switch (testmode) { | |
62fb45d3 GKH |
1600 | case USB_TEST_J: |
1601 | case USB_TEST_K: | |
1602 | case USB_TEST_SE0_NAK: | |
1603 | case USB_TEST_PACKET: | |
1604 | case USB_TEST_FORCE_ENABLE: | |
9e14d0a5 GH |
1605 | dctl |= testmode << DCTL_TSTCTL_SHIFT; |
1606 | break; | |
1607 | default: | |
1608 | return -EINVAL; | |
1609 | } | |
f25c42b8 | 1610 | dwc2_writel(hsotg, dctl, DCTL); |
9e14d0a5 GH |
1611 | return 0; |
1612 | } | |
1613 | ||
5b7d70c6 | 1614 | /** |
1f91b4cc | 1615 | * dwc2_hsotg_send_reply - send reply to control request |
5b7d70c6 BD |
1616 | * @hsotg: The device state |
1617 | * @ep: Endpoint 0 | |
1618 | * @buff: Buffer for request | |
1619 | * @length: Length of reply. | |
1620 | * | |
1621 | * Create a request and queue it on the given endpoint. This is useful as | |
1622 | * an internal method of sending replies to certain control requests, etc. | |
1623 | */ | |
1f91b4cc | 1624 | static int dwc2_hsotg_send_reply(struct dwc2_hsotg *hsotg, |
9da51974 | 1625 | struct dwc2_hsotg_ep *ep, |
5b7d70c6 BD |
1626 | void *buff, |
1627 | int length) | |
1628 | { | |
1629 | struct usb_request *req; | |
1630 | int ret; | |
1631 | ||
1632 | dev_dbg(hsotg->dev, "%s: buff %p, len %d\n", __func__, buff, length); | |
1633 | ||
1f91b4cc | 1634 | req = dwc2_hsotg_ep_alloc_request(&ep->ep, GFP_ATOMIC); |
5b7d70c6 BD |
1635 | hsotg->ep0_reply = req; |
1636 | if (!req) { | |
1637 | dev_warn(hsotg->dev, "%s: cannot alloc req\n", __func__); | |
1638 | return -ENOMEM; | |
1639 | } | |
1640 | ||
1641 | req->buf = hsotg->ep0_buff; | |
1642 | req->length = length; | |
f71b5e25 MYK |
1643 | /* |
1644 | * zero flag is for sending zlp in DATA IN stage. It has no impact on | |
1645 | * STATUS stage. | |
1646 | */ | |
1647 | req->zero = 0; | |
1f91b4cc | 1648 | req->complete = dwc2_hsotg_complete_oursetup; |
5b7d70c6 BD |
1649 | |
1650 | if (length) | |
1651 | memcpy(req->buf, buff, length); | |
5b7d70c6 | 1652 | |
1f91b4cc | 1653 | ret = dwc2_hsotg_ep_queue(&ep->ep, req, GFP_ATOMIC); |
5b7d70c6 BD |
1654 | if (ret) { |
1655 | dev_warn(hsotg->dev, "%s: cannot queue req\n", __func__); | |
1656 | return ret; | |
1657 | } | |
1658 | ||
1659 | return 0; | |
1660 | } | |
1661 | ||
1662 | /** | |
1f91b4cc | 1663 | * dwc2_hsotg_process_req_status - process request GET_STATUS |
5b7d70c6 BD |
1664 | * @hsotg: The device state |
1665 | * @ctrl: USB control request | |
1666 | */ | |
1f91b4cc | 1667 | static int dwc2_hsotg_process_req_status(struct dwc2_hsotg *hsotg, |
9da51974 | 1668 | struct usb_ctrlrequest *ctrl) |
5b7d70c6 | 1669 | { |
1f91b4cc FB |
1670 | struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0]; |
1671 | struct dwc2_hsotg_ep *ep; | |
5b7d70c6 | 1672 | __le16 reply; |
9a0d6f7c | 1673 | u16 status; |
5b7d70c6 BD |
1674 | int ret; |
1675 | ||
1676 | dev_dbg(hsotg->dev, "%s: USB_REQ_GET_STATUS\n", __func__); | |
1677 | ||
1678 | if (!ep0->dir_in) { | |
1679 | dev_warn(hsotg->dev, "%s: direction out?\n", __func__); | |
1680 | return -EINVAL; | |
1681 | } | |
1682 | ||
1683 | switch (ctrl->bRequestType & USB_RECIP_MASK) { | |
1684 | case USB_RECIP_DEVICE: | |
1a0808cb JK |
1685 | status = hsotg->gadget.is_selfpowered << |
1686 | USB_DEVICE_SELF_POWERED; | |
9a0d6f7c MH |
1687 | status |= hsotg->remote_wakeup_allowed << |
1688 | USB_DEVICE_REMOTE_WAKEUP; | |
1689 | reply = cpu_to_le16(status); | |
5b7d70c6 BD |
1690 | break; |
1691 | ||
1692 | case USB_RECIP_INTERFACE: | |
1693 | /* currently, the data result should be zero */ | |
1694 | reply = cpu_to_le16(0); | |
1695 | break; | |
1696 | ||
1697 | case USB_RECIP_ENDPOINT: | |
1698 | ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex)); | |
1699 | if (!ep) | |
1700 | return -ENOENT; | |
1701 | ||
1702 | reply = cpu_to_le16(ep->halted ? 1 : 0); | |
1703 | break; | |
1704 | ||
1705 | default: | |
1706 | return 0; | |
1707 | } | |
1708 | ||
1709 | if (le16_to_cpu(ctrl->wLength) != 2) | |
1710 | return -EINVAL; | |
1711 | ||
1f91b4cc | 1712 | ret = dwc2_hsotg_send_reply(hsotg, ep0, &reply, 2); |
5b7d70c6 BD |
1713 | if (ret) { |
1714 | dev_err(hsotg->dev, "%s: failed to send reply\n", __func__); | |
1715 | return ret; | |
1716 | } | |
1717 | ||
1718 | return 1; | |
1719 | } | |
1720 | ||
51da43b5 | 1721 | static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now); |
5b7d70c6 | 1722 | |
9c39ddc6 AT |
1723 | /** |
1724 | * get_ep_head - return the first request on the endpoint | |
1725 | * @hs_ep: The controller endpoint to get | |
1726 | * | |
1727 | * Get the first request on the endpoint. | |
1728 | */ | |
1f91b4cc | 1729 | static struct dwc2_hsotg_req *get_ep_head(struct dwc2_hsotg_ep *hs_ep) |
9c39ddc6 | 1730 | { |
ffc4b406 MY |
1731 | return list_first_entry_or_null(&hs_ep->queue, struct dwc2_hsotg_req, |
1732 | queue); | |
9c39ddc6 AT |
1733 | } |
1734 | ||
41cc4cd2 VM |
1735 | /** |
1736 | * dwc2_gadget_start_next_request - Starts next request from ep queue | |
1737 | * @hs_ep: Endpoint structure | |
1738 | * | |
1739 | * If queue is empty and EP is ISOC-OUT - unmasks OUTTKNEPDIS which is masked | |
1740 | * in its handler. Hence we need to unmask it here to be able to do | |
1741 | * resynchronization. | |
1742 | */ | |
1743 | static void dwc2_gadget_start_next_request(struct dwc2_hsotg_ep *hs_ep) | |
1744 | { | |
41cc4cd2 VM |
1745 | struct dwc2_hsotg *hsotg = hs_ep->parent; |
1746 | int dir_in = hs_ep->dir_in; | |
1747 | struct dwc2_hsotg_req *hs_req; | |
41cc4cd2 VM |
1748 | |
1749 | if (!list_empty(&hs_ep->queue)) { | |
1750 | hs_req = get_ep_head(hs_ep); | |
1751 | dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, false); | |
1752 | return; | |
1753 | } | |
1754 | if (!hs_ep->isochronous) | |
1755 | return; | |
1756 | ||
1757 | if (dir_in) { | |
1758 | dev_dbg(hsotg->dev, "%s: No more ISOC-IN requests\n", | |
1759 | __func__); | |
1760 | } else { | |
1761 | dev_dbg(hsotg->dev, "%s: No more ISOC-OUT requests\n", | |
1762 | __func__); | |
41cc4cd2 VM |
1763 | } |
1764 | } | |
1765 | ||
5b7d70c6 | 1766 | /** |
1f91b4cc | 1767 | * dwc2_hsotg_process_req_feature - process request {SET,CLEAR}_FEATURE |
5b7d70c6 BD |
1768 | * @hsotg: The device state |
1769 | * @ctrl: USB control request | |
1770 | */ | |
1f91b4cc | 1771 | static int dwc2_hsotg_process_req_feature(struct dwc2_hsotg *hsotg, |
9da51974 | 1772 | struct usb_ctrlrequest *ctrl) |
5b7d70c6 | 1773 | { |
1f91b4cc FB |
1774 | struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0]; |
1775 | struct dwc2_hsotg_req *hs_req; | |
5b7d70c6 | 1776 | bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE); |
1f91b4cc | 1777 | struct dwc2_hsotg_ep *ep; |
26ab3d0c | 1778 | int ret; |
bd9ef7bf | 1779 | bool halted; |
9e14d0a5 GH |
1780 | u32 recip; |
1781 | u32 wValue; | |
1782 | u32 wIndex; | |
5b7d70c6 BD |
1783 | |
1784 | dev_dbg(hsotg->dev, "%s: %s_FEATURE\n", | |
1785 | __func__, set ? "SET" : "CLEAR"); | |
1786 | ||
9e14d0a5 GH |
1787 | wValue = le16_to_cpu(ctrl->wValue); |
1788 | wIndex = le16_to_cpu(ctrl->wIndex); | |
1789 | recip = ctrl->bRequestType & USB_RECIP_MASK; | |
1790 | ||
1791 | switch (recip) { | |
1792 | case USB_RECIP_DEVICE: | |
1793 | switch (wValue) { | |
fa389a6d | 1794 | case USB_DEVICE_REMOTE_WAKEUP: |
9a0d6f7c MH |
1795 | if (set) |
1796 | hsotg->remote_wakeup_allowed = 1; | |
1797 | else | |
1798 | hsotg->remote_wakeup_allowed = 0; | |
fa389a6d VM |
1799 | break; |
1800 | ||
9e14d0a5 GH |
1801 | case USB_DEVICE_TEST_MODE: |
1802 | if ((wIndex & 0xff) != 0) | |
1803 | return -EINVAL; | |
1804 | if (!set) | |
1805 | return -EINVAL; | |
1806 | ||
1807 | hsotg->test_mode = wIndex >> 8; | |
9e14d0a5 GH |
1808 | break; |
1809 | default: | |
1810 | return -ENOENT; | |
1811 | } | |
9a0d6f7c MH |
1812 | |
1813 | ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0); | |
1814 | if (ret) { | |
1815 | dev_err(hsotg->dev, | |
1816 | "%s: failed to send reply\n", __func__); | |
1817 | return ret; | |
1818 | } | |
9e14d0a5 GH |
1819 | break; |
1820 | ||
1821 | case USB_RECIP_ENDPOINT: | |
1822 | ep = ep_from_windex(hsotg, wIndex); | |
5b7d70c6 BD |
1823 | if (!ep) { |
1824 | dev_dbg(hsotg->dev, "%s: no endpoint for 0x%04x\n", | |
9e14d0a5 | 1825 | __func__, wIndex); |
5b7d70c6 BD |
1826 | return -ENOENT; |
1827 | } | |
1828 | ||
9e14d0a5 | 1829 | switch (wValue) { |
5b7d70c6 | 1830 | case USB_ENDPOINT_HALT: |
bd9ef7bf RB |
1831 | halted = ep->halted; |
1832 | ||
b833ce15 MH |
1833 | if (!ep->wedged) |
1834 | dwc2_hsotg_ep_sethalt(&ep->ep, set, true); | |
26ab3d0c | 1835 | |
1f91b4cc | 1836 | ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0); |
26ab3d0c AT |
1837 | if (ret) { |
1838 | dev_err(hsotg->dev, | |
1839 | "%s: failed to send reply\n", __func__); | |
1840 | return ret; | |
1841 | } | |
9c39ddc6 | 1842 | |
bd9ef7bf RB |
1843 | /* |
1844 | * we have to complete all requests for ep if it was | |
1845 | * halted, and the halt was cleared by CLEAR_FEATURE | |
1846 | */ | |
1847 | ||
1848 | if (!set && halted) { | |
9c39ddc6 AT |
1849 | /* |
1850 | * If we have request in progress, | |
1851 | * then complete it | |
1852 | */ | |
1853 | if (ep->req) { | |
1854 | hs_req = ep->req; | |
1855 | ep->req = NULL; | |
1856 | list_del_init(&hs_req->queue); | |
c00dd4a6 GH |
1857 | if (hs_req->req.complete) { |
1858 | spin_unlock(&hsotg->lock); | |
1859 | usb_gadget_giveback_request( | |
1860 | &ep->ep, &hs_req->req); | |
1861 | spin_lock(&hsotg->lock); | |
1862 | } | |
9c39ddc6 AT |
1863 | } |
1864 | ||
1865 | /* If we have pending request, then start it */ | |
34c0887f | 1866 | if (!ep->req) |
41cc4cd2 | 1867 | dwc2_gadget_start_next_request(ep); |
9c39ddc6 AT |
1868 | } |
1869 | ||
5b7d70c6 BD |
1870 | break; |
1871 | ||
1872 | default: | |
1873 | return -ENOENT; | |
1874 | } | |
9e14d0a5 GH |
1875 | break; |
1876 | default: | |
1877 | return -ENOENT; | |
1878 | } | |
5b7d70c6 BD |
1879 | return 1; |
1880 | } | |
1881 | ||
1f91b4cc | 1882 | static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg); |
ab93e014 | 1883 | |
c9f721b2 | 1884 | /** |
1f91b4cc | 1885 | * dwc2_hsotg_stall_ep0 - stall ep0 |
c9f721b2 RB |
1886 | * @hsotg: The device state |
1887 | * | |
1888 | * Set stall for ep0 as response for setup request. | |
1889 | */ | |
1f91b4cc | 1890 | static void dwc2_hsotg_stall_ep0(struct dwc2_hsotg *hsotg) |
e9ebe7c3 | 1891 | { |
1f91b4cc | 1892 | struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0]; |
c9f721b2 RB |
1893 | u32 reg; |
1894 | u32 ctrl; | |
1895 | ||
1896 | dev_dbg(hsotg->dev, "ep0 stall (dir=%d)\n", ep0->dir_in); | |
1897 | reg = (ep0->dir_in) ? DIEPCTL0 : DOEPCTL0; | |
1898 | ||
1899 | /* | |
1900 | * DxEPCTL_Stall will be cleared by EP once it has | |
1901 | * taken effect, so no need to clear later. | |
1902 | */ | |
1903 | ||
f25c42b8 | 1904 | ctrl = dwc2_readl(hsotg, reg); |
47a1685f DN |
1905 | ctrl |= DXEPCTL_STALL; |
1906 | ctrl |= DXEPCTL_CNAK; | |
f25c42b8 | 1907 | dwc2_writel(hsotg, ctrl, reg); |
c9f721b2 RB |
1908 | |
1909 | dev_dbg(hsotg->dev, | |
47a1685f | 1910 | "written DXEPCTL=0x%08x to %08x (DXEPCTL=0x%08x)\n", |
f25c42b8 | 1911 | ctrl, reg, dwc2_readl(hsotg, reg)); |
c9f721b2 RB |
1912 | |
1913 | /* | |
1914 | * complete won't be called, so we enqueue | |
1915 | * setup request here | |
1916 | */ | |
1f91b4cc | 1917 | dwc2_hsotg_enqueue_setup(hsotg); |
c9f721b2 RB |
1918 | } |
1919 | ||
5b7d70c6 | 1920 | /** |
1f91b4cc | 1921 | * dwc2_hsotg_process_control - process a control request |
5b7d70c6 BD |
1922 | * @hsotg: The device state |
1923 | * @ctrl: The control request received | |
1924 | * | |
1925 | * The controller has received the SETUP phase of a control request, and | |
1926 | * needs to work out what to do next (and whether to pass it on to the | |
1927 | * gadget driver). | |
1928 | */ | |
1f91b4cc | 1929 | static void dwc2_hsotg_process_control(struct dwc2_hsotg *hsotg, |
9da51974 | 1930 | struct usb_ctrlrequest *ctrl) |
5b7d70c6 | 1931 | { |
1f91b4cc | 1932 | struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0]; |
5b7d70c6 BD |
1933 | int ret = 0; |
1934 | u32 dcfg; | |
1935 | ||
e525e743 MYK |
1936 | dev_dbg(hsotg->dev, |
1937 | "ctrl Type=%02x, Req=%02x, V=%04x, I=%04x, L=%04x\n", | |
1938 | ctrl->bRequestType, ctrl->bRequest, ctrl->wValue, | |
1939 | ctrl->wIndex, ctrl->wLength); | |
5b7d70c6 | 1940 | |
fe0b94ab MYK |
1941 | if (ctrl->wLength == 0) { |
1942 | ep0->dir_in = 1; | |
1943 | hsotg->ep0_state = DWC2_EP0_STATUS_IN; | |
1944 | } else if (ctrl->bRequestType & USB_DIR_IN) { | |
5b7d70c6 | 1945 | ep0->dir_in = 1; |
fe0b94ab MYK |
1946 | hsotg->ep0_state = DWC2_EP0_DATA_IN; |
1947 | } else { | |
1948 | ep0->dir_in = 0; | |
1949 | hsotg->ep0_state = DWC2_EP0_DATA_OUT; | |
1950 | } | |
5b7d70c6 BD |
1951 | |
1952 | if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) { | |
1953 | switch (ctrl->bRequest) { | |
1954 | case USB_REQ_SET_ADDRESS: | |
6d713c15 | 1955 | hsotg->connected = 1; |
f25c42b8 | 1956 | dcfg = dwc2_readl(hsotg, DCFG); |
47a1685f | 1957 | dcfg &= ~DCFG_DEVADDR_MASK; |
d5dbd3f7 PZ |
1958 | dcfg |= (le16_to_cpu(ctrl->wValue) << |
1959 | DCFG_DEVADDR_SHIFT) & DCFG_DEVADDR_MASK; | |
f25c42b8 | 1960 | dwc2_writel(hsotg, dcfg, DCFG); |
5b7d70c6 BD |
1961 | |
1962 | dev_info(hsotg->dev, "new address %d\n", ctrl->wValue); | |
1963 | ||
1f91b4cc | 1964 | ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0); |
5b7d70c6 BD |
1965 | return; |
1966 | ||
1967 | case USB_REQ_GET_STATUS: | |
1f91b4cc | 1968 | ret = dwc2_hsotg_process_req_status(hsotg, ctrl); |
5b7d70c6 BD |
1969 | break; |
1970 | ||
1971 | case USB_REQ_CLEAR_FEATURE: | |
1972 | case USB_REQ_SET_FEATURE: | |
1f91b4cc | 1973 | ret = dwc2_hsotg_process_req_feature(hsotg, ctrl); |
5b7d70c6 BD |
1974 | break; |
1975 | } | |
1976 | } | |
1977 | ||
1978 | /* as a fallback, try delivering it to the driver to deal with */ | |
1979 | ||
1980 | if (ret == 0 && hsotg->driver) { | |
93f599f2 | 1981 | spin_unlock(&hsotg->lock); |
5b7d70c6 | 1982 | ret = hsotg->driver->setup(&hsotg->gadget, ctrl); |
93f599f2 | 1983 | spin_lock(&hsotg->lock); |
5b7d70c6 BD |
1984 | if (ret < 0) |
1985 | dev_dbg(hsotg->dev, "driver->setup() ret %d\n", ret); | |
1986 | } | |
1987 | ||
b4c53b4a MH |
1988 | hsotg->delayed_status = false; |
1989 | if (ret == USB_GADGET_DELAYED_STATUS) | |
1990 | hsotg->delayed_status = true; | |
1991 | ||
8b9bc460 LM |
1992 | /* |
1993 | * the request is either unhandlable, or is not formatted correctly | |
5b7d70c6 BD |
1994 | * so respond with a STALL for the status stage to indicate failure. |
1995 | */ | |
1996 | ||
c9f721b2 | 1997 | if (ret < 0) |
1f91b4cc | 1998 | dwc2_hsotg_stall_ep0(hsotg); |
5b7d70c6 BD |
1999 | } |
2000 | ||
5b7d70c6 | 2001 | /** |
1f91b4cc | 2002 | * dwc2_hsotg_complete_setup - completion of a setup transfer |
5b7d70c6 BD |
2003 | * @ep: The endpoint the request was on. |
2004 | * @req: The request completed. | |
2005 | * | |
2006 | * Called on completion of any requests the driver itself submitted for | |
2007 | * EP0 setup packets | |
2008 | */ | |
1f91b4cc | 2009 | static void dwc2_hsotg_complete_setup(struct usb_ep *ep, |
9da51974 | 2010 | struct usb_request *req) |
5b7d70c6 | 2011 | { |
1f91b4cc | 2012 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 2013 | struct dwc2_hsotg *hsotg = hs_ep->parent; |
5b7d70c6 BD |
2014 | |
2015 | if (req->status < 0) { | |
2016 | dev_dbg(hsotg->dev, "%s: failed %d\n", __func__, req->status); | |
2017 | return; | |
2018 | } | |
2019 | ||
93f599f2 | 2020 | spin_lock(&hsotg->lock); |
5b7d70c6 | 2021 | if (req->actual == 0) |
1f91b4cc | 2022 | dwc2_hsotg_enqueue_setup(hsotg); |
5b7d70c6 | 2023 | else |
1f91b4cc | 2024 | dwc2_hsotg_process_control(hsotg, req->buf); |
93f599f2 | 2025 | spin_unlock(&hsotg->lock); |
5b7d70c6 BD |
2026 | } |
2027 | ||
2028 | /** | |
1f91b4cc | 2029 | * dwc2_hsotg_enqueue_setup - start a request for EP0 packets |
5b7d70c6 BD |
2030 | * @hsotg: The device state. |
2031 | * | |
2032 | * Enqueue a request on EP0 if necessary to received any SETUP packets | |
2033 | * received from the host. | |
2034 | */ | |
1f91b4cc | 2035 | static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg) |
5b7d70c6 BD |
2036 | { |
2037 | struct usb_request *req = hsotg->ctrl_req; | |
1f91b4cc | 2038 | struct dwc2_hsotg_req *hs_req = our_req(req); |
5b7d70c6 BD |
2039 | int ret; |
2040 | ||
2041 | dev_dbg(hsotg->dev, "%s: queueing setup request\n", __func__); | |
2042 | ||
2043 | req->zero = 0; | |
2044 | req->length = 8; | |
2045 | req->buf = hsotg->ctrl_buff; | |
1f91b4cc | 2046 | req->complete = dwc2_hsotg_complete_setup; |
5b7d70c6 BD |
2047 | |
2048 | if (!list_empty(&hs_req->queue)) { | |
2049 | dev_dbg(hsotg->dev, "%s already queued???\n", __func__); | |
2050 | return; | |
2051 | } | |
2052 | ||
c6f5c050 | 2053 | hsotg->eps_out[0]->dir_in = 0; |
8a20fa45 | 2054 | hsotg->eps_out[0]->send_zlp = 0; |
fe0b94ab | 2055 | hsotg->ep0_state = DWC2_EP0_SETUP; |
5b7d70c6 | 2056 | |
1f91b4cc | 2057 | ret = dwc2_hsotg_ep_queue(&hsotg->eps_out[0]->ep, req, GFP_ATOMIC); |
5b7d70c6 BD |
2058 | if (ret < 0) { |
2059 | dev_err(hsotg->dev, "%s: failed queue (%d)\n", __func__, ret); | |
8b9bc460 LM |
2060 | /* |
2061 | * Don't think there's much we can do other than watch the | |
2062 | * driver fail. | |
2063 | */ | |
5b7d70c6 BD |
2064 | } |
2065 | } | |
2066 | ||
1f91b4cc | 2067 | static void dwc2_hsotg_program_zlp(struct dwc2_hsotg *hsotg, |
9da51974 | 2068 | struct dwc2_hsotg_ep *hs_ep) |
fe0b94ab MYK |
2069 | { |
2070 | u32 ctrl; | |
2071 | u8 index = hs_ep->index; | |
2072 | u32 epctl_reg = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index); | |
2073 | u32 epsiz_reg = hs_ep->dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index); | |
2074 | ||
ccb34a91 MYK |
2075 | if (hs_ep->dir_in) |
2076 | dev_dbg(hsotg->dev, "Sending zero-length packet on ep%d\n", | |
e02f9aa6 | 2077 | index); |
ccb34a91 MYK |
2078 | else |
2079 | dev_dbg(hsotg->dev, "Receiving zero-length packet on ep%d\n", | |
e02f9aa6 VA |
2080 | index); |
2081 | if (using_desc_dma(hsotg)) { | |
066cfd07 AP |
2082 | /* Not specific buffer needed for ep0 ZLP */ |
2083 | dma_addr_t dma = hs_ep->desc_list_dma; | |
2084 | ||
201ec568 MH |
2085 | if (!index) |
2086 | dwc2_gadget_set_ep0_desc_chain(hsotg, hs_ep); | |
2087 | ||
066cfd07 | 2088 | dwc2_gadget_config_nonisoc_xfer_ddma(hs_ep, dma, 0); |
e02f9aa6 | 2089 | } else { |
f25c42b8 GS |
2090 | dwc2_writel(hsotg, DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) | |
2091 | DXEPTSIZ_XFERSIZE(0), | |
e02f9aa6 VA |
2092 | epsiz_reg); |
2093 | } | |
fe0b94ab | 2094 | |
f25c42b8 | 2095 | ctrl = dwc2_readl(hsotg, epctl_reg); |
fe0b94ab MYK |
2096 | ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */ |
2097 | ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */ | |
2098 | ctrl |= DXEPCTL_USBACTEP; | |
f25c42b8 | 2099 | dwc2_writel(hsotg, ctrl, epctl_reg); |
fe0b94ab MYK |
2100 | } |
2101 | ||
5b7d70c6 | 2102 | /** |
1f91b4cc | 2103 | * dwc2_hsotg_complete_request - complete a request given to us |
5b7d70c6 BD |
2104 | * @hsotg: The device state. |
2105 | * @hs_ep: The endpoint the request was on. | |
2106 | * @hs_req: The request to complete. | |
2107 | * @result: The result code (0 => Ok, otherwise errno) | |
2108 | * | |
2109 | * The given request has finished, so call the necessary completion | |
2110 | * if it has one and then look to see if we can start a new request | |
2111 | * on the endpoint. | |
2112 | * | |
2113 | * Note, expects the ep to already be locked as appropriate. | |
8b9bc460 | 2114 | */ |
1f91b4cc | 2115 | static void dwc2_hsotg_complete_request(struct dwc2_hsotg *hsotg, |
9da51974 | 2116 | struct dwc2_hsotg_ep *hs_ep, |
1f91b4cc | 2117 | struct dwc2_hsotg_req *hs_req, |
5b7d70c6 BD |
2118 | int result) |
2119 | { | |
5b7d70c6 BD |
2120 | if (!hs_req) { |
2121 | dev_dbg(hsotg->dev, "%s: nothing to complete?\n", __func__); | |
2122 | return; | |
2123 | } | |
2124 | ||
2125 | dev_dbg(hsotg->dev, "complete: ep %p %s, req %p, %d => %p\n", | |
2126 | hs_ep, hs_ep->ep.name, hs_req, result, hs_req->req.complete); | |
2127 | ||
8b9bc460 LM |
2128 | /* |
2129 | * only replace the status if we've not already set an error | |
2130 | * from a previous transaction | |
2131 | */ | |
5b7d70c6 BD |
2132 | |
2133 | if (hs_req->req.status == -EINPROGRESS) | |
2134 | hs_req->req.status = result; | |
2135 | ||
44583fec YL |
2136 | if (using_dma(hsotg)) |
2137 | dwc2_hsotg_unmap_dma(hsotg, hs_ep, hs_req); | |
2138 | ||
1f91b4cc | 2139 | dwc2_hsotg_handle_unaligned_buf_complete(hsotg, hs_ep, hs_req); |
7d24c1b5 | 2140 | |
5b7d70c6 BD |
2141 | hs_ep->req = NULL; |
2142 | list_del_init(&hs_req->queue); | |
2143 | ||
8b9bc460 LM |
2144 | /* |
2145 | * call the complete request with the locks off, just in case the | |
2146 | * request tries to queue more work for this endpoint. | |
2147 | */ | |
5b7d70c6 BD |
2148 | |
2149 | if (hs_req->req.complete) { | |
22258f49 | 2150 | spin_unlock(&hsotg->lock); |
304f7e5e | 2151 | usb_gadget_giveback_request(&hs_ep->ep, &hs_req->req); |
22258f49 | 2152 | spin_lock(&hsotg->lock); |
5b7d70c6 BD |
2153 | } |
2154 | ||
540ccba0 VA |
2155 | /* In DDMA don't need to proceed to starting of next ISOC request */ |
2156 | if (using_desc_dma(hsotg) && hs_ep->isochronous) | |
2157 | return; | |
2158 | ||
8b9bc460 LM |
2159 | /* |
2160 | * Look to see if there is anything else to do. Note, the completion | |
5b7d70c6 | 2161 | * of the previous request may have caused a new request to be started |
8b9bc460 LM |
2162 | * so be careful when doing this. |
2163 | */ | |
5b7d70c6 | 2164 | |
34c0887f | 2165 | if (!hs_ep->req && result >= 0) |
41cc4cd2 | 2166 | dwc2_gadget_start_next_request(hs_ep); |
5b7d70c6 BD |
2167 | } |
2168 | ||
540ccba0 VA |
2169 | /* |
2170 | * dwc2_gadget_complete_isoc_request_ddma - complete an isoc request in DDMA | |
2171 | * @hs_ep: The endpoint the request was on. | |
2172 | * | |
2173 | * Get first request from the ep queue, determine descriptor on which complete | |
729cac69 MH |
2174 | * happened. SW discovers which descriptor currently in use by HW, adjusts |
2175 | * dma_address and calculates index of completed descriptor based on the value | |
2176 | * of DEPDMA register. Update actual length of request, giveback to gadget. | |
540ccba0 VA |
2177 | */ |
2178 | static void dwc2_gadget_complete_isoc_request_ddma(struct dwc2_hsotg_ep *hs_ep) | |
2179 | { | |
2180 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
2181 | struct dwc2_hsotg_req *hs_req; | |
2182 | struct usb_request *ureq; | |
540ccba0 VA |
2183 | u32 desc_sts; |
2184 | u32 mask; | |
2185 | ||
729cac69 | 2186 | desc_sts = hs_ep->desc_list[hs_ep->compl_desc].status; |
540ccba0 | 2187 | |
729cac69 MH |
2188 | /* Process only descriptors with buffer status set to DMA done */ |
2189 | while ((desc_sts & DEV_DMA_BUFF_STS_MASK) >> | |
2190 | DEV_DMA_BUFF_STS_SHIFT == DEV_DMA_BUFF_STS_DMADONE) { | |
540ccba0 | 2191 | |
729cac69 MH |
2192 | hs_req = get_ep_head(hs_ep); |
2193 | if (!hs_req) { | |
2194 | dev_warn(hsotg->dev, "%s: ISOC EP queue empty\n", __func__); | |
2195 | return; | |
2196 | } | |
2197 | ureq = &hs_req->req; | |
2198 | ||
2199 | /* Check completion status */ | |
2200 | if ((desc_sts & DEV_DMA_STS_MASK) >> DEV_DMA_STS_SHIFT == | |
2201 | DEV_DMA_STS_SUCC) { | |
2202 | mask = hs_ep->dir_in ? DEV_DMA_ISOC_TX_NBYTES_MASK : | |
2203 | DEV_DMA_ISOC_RX_NBYTES_MASK; | |
2204 | ureq->actual = ureq->length - ((desc_sts & mask) >> | |
2205 | DEV_DMA_ISOC_NBYTES_SHIFT); | |
2206 | ||
2207 | /* Adjust actual len for ISOC Out if len is | |
2208 | * not align of 4 | |
2209 | */ | |
2210 | if (!hs_ep->dir_in && ureq->length & 0x3) | |
2211 | ureq->actual += 4 - (ureq->length & 0x3); | |
c8006f67 MH |
2212 | |
2213 | /* Set actual frame number for completed transfers */ | |
2214 | ureq->frame_number = | |
2215 | (desc_sts & DEV_DMA_ISOC_FRNUM_MASK) >> | |
2216 | DEV_DMA_ISOC_FRNUM_SHIFT; | |
729cac69 | 2217 | } |
540ccba0 | 2218 | |
729cac69 | 2219 | dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0); |
95d2b037 | 2220 | |
729cac69 | 2221 | hs_ep->compl_desc++; |
54f37f56 | 2222 | if (hs_ep->compl_desc > (MAX_DMA_DESC_NUM_HS_ISOC - 1)) |
729cac69 MH |
2223 | hs_ep->compl_desc = 0; |
2224 | desc_sts = hs_ep->desc_list[hs_ep->compl_desc].status; | |
2225 | } | |
540ccba0 VA |
2226 | } |
2227 | ||
2228 | /* | |
729cac69 MH |
2229 | * dwc2_gadget_handle_isoc_bna - handle BNA interrupt for ISOC. |
2230 | * @hs_ep: The isochronous endpoint. | |
540ccba0 | 2231 | * |
729cac69 MH |
2232 | * If EP ISOC OUT then need to flush RX FIFO to remove source of BNA |
2233 | * interrupt. Reset target frame and next_desc to allow to start | |
2234 | * ISOC's on NAK interrupt for IN direction or on OUTTKNEPDIS | |
2235 | * interrupt for OUT direction. | |
540ccba0 | 2236 | */ |
729cac69 | 2237 | static void dwc2_gadget_handle_isoc_bna(struct dwc2_hsotg_ep *hs_ep) |
540ccba0 VA |
2238 | { |
2239 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
540ccba0 | 2240 | |
729cac69 MH |
2241 | if (!hs_ep->dir_in) |
2242 | dwc2_flush_rx_fifo(hsotg); | |
2243 | dwc2_hsotg_complete_request(hsotg, hs_ep, get_ep_head(hs_ep), 0); | |
540ccba0 | 2244 | |
729cac69 MH |
2245 | hs_ep->target_frame = TARGET_FRAME_INITIAL; |
2246 | hs_ep->next_desc = 0; | |
2247 | hs_ep->compl_desc = 0; | |
540ccba0 VA |
2248 | } |
2249 | ||
5b7d70c6 | 2250 | /** |
1f91b4cc | 2251 | * dwc2_hsotg_rx_data - receive data from the FIFO for an endpoint |
5b7d70c6 BD |
2252 | * @hsotg: The device state. |
2253 | * @ep_idx: The endpoint index for the data | |
2254 | * @size: The size of data in the fifo, in bytes | |
2255 | * | |
2256 | * The FIFO status shows there is data to read from the FIFO for a given | |
2257 | * endpoint, so sort out whether we need to read the data into a request | |
2258 | * that has been made for that endpoint. | |
2259 | */ | |
1f91b4cc | 2260 | static void dwc2_hsotg_rx_data(struct dwc2_hsotg *hsotg, int ep_idx, int size) |
5b7d70c6 | 2261 | { |
1f91b4cc FB |
2262 | struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[ep_idx]; |
2263 | struct dwc2_hsotg_req *hs_req = hs_ep->req; | |
5b7d70c6 BD |
2264 | int to_read; |
2265 | int max_req; | |
2266 | int read_ptr; | |
2267 | ||
2268 | if (!hs_req) { | |
f25c42b8 | 2269 | u32 epctl = dwc2_readl(hsotg, DOEPCTL(ep_idx)); |
5b7d70c6 BD |
2270 | int ptr; |
2271 | ||
6b448af4 | 2272 | dev_dbg(hsotg->dev, |
9da51974 | 2273 | "%s: FIFO %d bytes on ep%d but no req (DXEPCTl=0x%08x)\n", |
5b7d70c6 BD |
2274 | __func__, size, ep_idx, epctl); |
2275 | ||
2276 | /* dump the data from the FIFO, we've nothing we can do */ | |
2277 | for (ptr = 0; ptr < size; ptr += 4) | |
f25c42b8 | 2278 | (void)dwc2_readl(hsotg, EPFIFO(ep_idx)); |
5b7d70c6 BD |
2279 | |
2280 | return; | |
2281 | } | |
2282 | ||
5b7d70c6 BD |
2283 | to_read = size; |
2284 | read_ptr = hs_req->req.actual; | |
2285 | max_req = hs_req->req.length - read_ptr; | |
2286 | ||
a33e7136 BD |
2287 | dev_dbg(hsotg->dev, "%s: read %d/%d, done %d/%d\n", |
2288 | __func__, to_read, max_req, read_ptr, hs_req->req.length); | |
2289 | ||
5b7d70c6 | 2290 | if (to_read > max_req) { |
8b9bc460 LM |
2291 | /* |
2292 | * more data appeared than we where willing | |
5b7d70c6 BD |
2293 | * to deal with in this request. |
2294 | */ | |
2295 | ||
2296 | /* currently we don't deal this */ | |
2297 | WARN_ON_ONCE(1); | |
2298 | } | |
2299 | ||
5b7d70c6 BD |
2300 | hs_ep->total_data += to_read; |
2301 | hs_req->req.actual += to_read; | |
2302 | to_read = DIV_ROUND_UP(to_read, 4); | |
2303 | ||
8b9bc460 LM |
2304 | /* |
2305 | * note, we might over-write the buffer end by 3 bytes depending on | |
2306 | * alignment of the data. | |
2307 | */ | |
342ccce1 GS |
2308 | dwc2_readl_rep(hsotg, EPFIFO(ep_idx), |
2309 | hs_req->req.buf + read_ptr, to_read); | |
5b7d70c6 BD |
2310 | } |
2311 | ||
2312 | /** | |
1f91b4cc | 2313 | * dwc2_hsotg_ep0_zlp - send/receive zero-length packet on control endpoint |
5b7d70c6 | 2314 | * @hsotg: The device instance |
fe0b94ab | 2315 | * @dir_in: If IN zlp |
5b7d70c6 BD |
2316 | * |
2317 | * Generate a zero-length IN packet request for terminating a SETUP | |
2318 | * transaction. | |
2319 | * | |
2320 | * Note, since we don't write any data to the TxFIFO, then it is | |
25985edc | 2321 | * currently believed that we do not need to wait for any space in |
5b7d70c6 BD |
2322 | * the TxFIFO. |
2323 | */ | |
1f91b4cc | 2324 | static void dwc2_hsotg_ep0_zlp(struct dwc2_hsotg *hsotg, bool dir_in) |
5b7d70c6 | 2325 | { |
c6f5c050 | 2326 | /* eps_out[0] is used in both directions */ |
fe0b94ab MYK |
2327 | hsotg->eps_out[0]->dir_in = dir_in; |
2328 | hsotg->ep0_state = dir_in ? DWC2_EP0_STATUS_IN : DWC2_EP0_STATUS_OUT; | |
5b7d70c6 | 2329 | |
1f91b4cc | 2330 | dwc2_hsotg_program_zlp(hsotg, hsotg->eps_out[0]); |
5b7d70c6 BD |
2331 | } |
2332 | ||
aa3e8bc8 VA |
2333 | /* |
2334 | * dwc2_gadget_get_xfersize_ddma - get transferred bytes amount from desc | |
2335 | * @hs_ep - The endpoint on which transfer went | |
2336 | * | |
2337 | * Iterate over endpoints descriptor chain and get info on bytes remained | |
2338 | * in DMA descriptors after transfer has completed. Used for non isoc EPs. | |
2339 | */ | |
2340 | static unsigned int dwc2_gadget_get_xfersize_ddma(struct dwc2_hsotg_ep *hs_ep) | |
2341 | { | |
b2c586eb | 2342 | const struct usb_endpoint_descriptor *ep_desc = hs_ep->ep.desc; |
aa3e8bc8 VA |
2343 | struct dwc2_hsotg *hsotg = hs_ep->parent; |
2344 | unsigned int bytes_rem = 0; | |
b2c586eb | 2345 | unsigned int bytes_rem_correction = 0; |
aa3e8bc8 VA |
2346 | struct dwc2_dma_desc *desc = hs_ep->desc_list; |
2347 | int i; | |
2348 | u32 status; | |
b2c586eb MH |
2349 | u32 mps = hs_ep->ep.maxpacket; |
2350 | int dir_in = hs_ep->dir_in; | |
aa3e8bc8 VA |
2351 | |
2352 | if (!desc) | |
2353 | return -EINVAL; | |
2354 | ||
b2c586eb MH |
2355 | /* Interrupt OUT EP with mps not multiple of 4 */ |
2356 | if (hs_ep->index) | |
2357 | if (usb_endpoint_xfer_int(ep_desc) && !dir_in && (mps % 4)) | |
2358 | bytes_rem_correction = 4 - (mps % 4); | |
2359 | ||
aa3e8bc8 VA |
2360 | for (i = 0; i < hs_ep->desc_count; ++i) { |
2361 | status = desc->status; | |
2362 | bytes_rem += status & DEV_DMA_NBYTES_MASK; | |
b2c586eb | 2363 | bytes_rem -= bytes_rem_correction; |
aa3e8bc8 VA |
2364 | |
2365 | if (status & DEV_DMA_STS_MASK) | |
2366 | dev_err(hsotg->dev, "descriptor %d closed with %x\n", | |
2367 | i, status & DEV_DMA_STS_MASK); | |
b2c586eb MH |
2368 | |
2369 | if (status & DEV_DMA_L) | |
2370 | break; | |
2371 | ||
5acb4b97 | 2372 | desc++; |
aa3e8bc8 VA |
2373 | } |
2374 | ||
2375 | return bytes_rem; | |
2376 | } | |
2377 | ||
5b7d70c6 | 2378 | /** |
1f91b4cc | 2379 | * dwc2_hsotg_handle_outdone - handle receiving OutDone/SetupDone from RXFIFO |
5b7d70c6 BD |
2380 | * @hsotg: The device instance |
2381 | * @epnum: The endpoint received from | |
5b7d70c6 BD |
2382 | * |
2383 | * The RXFIFO has delivered an OutDone event, which means that the data | |
2384 | * transfer for an OUT endpoint has been completed, either by a short | |
2385 | * packet or by the finish of a transfer. | |
8b9bc460 | 2386 | */ |
1f91b4cc | 2387 | static void dwc2_hsotg_handle_outdone(struct dwc2_hsotg *hsotg, int epnum) |
5b7d70c6 | 2388 | { |
f25c42b8 | 2389 | u32 epsize = dwc2_readl(hsotg, DOEPTSIZ(epnum)); |
1f91b4cc FB |
2390 | struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[epnum]; |
2391 | struct dwc2_hsotg_req *hs_req = hs_ep->req; | |
5b7d70c6 | 2392 | struct usb_request *req = &hs_req->req; |
9da51974 | 2393 | unsigned int size_left = DXEPTSIZ_XFERSIZE_GET(epsize); |
5b7d70c6 BD |
2394 | int result = 0; |
2395 | ||
2396 | if (!hs_req) { | |
2397 | dev_dbg(hsotg->dev, "%s: no request active\n", __func__); | |
2398 | return; | |
2399 | } | |
2400 | ||
fe0b94ab MYK |
2401 | if (epnum == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_OUT) { |
2402 | dev_dbg(hsotg->dev, "zlp packet received\n"); | |
1f91b4cc FB |
2403 | dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0); |
2404 | dwc2_hsotg_enqueue_setup(hsotg); | |
fe0b94ab MYK |
2405 | return; |
2406 | } | |
2407 | ||
aa3e8bc8 VA |
2408 | if (using_desc_dma(hsotg)) |
2409 | size_left = dwc2_gadget_get_xfersize_ddma(hs_ep); | |
2410 | ||
5b7d70c6 | 2411 | if (using_dma(hsotg)) { |
9da51974 | 2412 | unsigned int size_done; |
5b7d70c6 | 2413 | |
8b9bc460 LM |
2414 | /* |
2415 | * Calculate the size of the transfer by checking how much | |
5b7d70c6 BD |
2416 | * is left in the endpoint size register and then working it |
2417 | * out from the amount we loaded for the transfer. | |
2418 | * | |
2419 | * We need to do this as DMA pointers are always 32bit aligned | |
2420 | * so may overshoot/undershoot the transfer. | |
2421 | */ | |
2422 | ||
5b7d70c6 BD |
2423 | size_done = hs_ep->size_loaded - size_left; |
2424 | size_done += hs_ep->last_load; | |
2425 | ||
2426 | req->actual = size_done; | |
2427 | } | |
2428 | ||
a33e7136 BD |
2429 | /* if there is more request to do, schedule new transfer */ |
2430 | if (req->actual < req->length && size_left == 0) { | |
1f91b4cc | 2431 | dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true); |
a33e7136 BD |
2432 | return; |
2433 | } | |
2434 | ||
5b7d70c6 BD |
2435 | if (req->actual < req->length && req->short_not_ok) { |
2436 | dev_dbg(hsotg->dev, "%s: got %d/%d (short not ok) => error\n", | |
2437 | __func__, req->actual, req->length); | |
2438 | ||
8b9bc460 LM |
2439 | /* |
2440 | * todo - what should we return here? there's no one else | |
2441 | * even bothering to check the status. | |
2442 | */ | |
5b7d70c6 BD |
2443 | } |
2444 | ||
ef750c71 VA |
2445 | /* DDMA IN status phase will start from StsPhseRcvd interrupt */ |
2446 | if (!using_desc_dma(hsotg) && epnum == 0 && | |
2447 | hsotg->ep0_state == DWC2_EP0_DATA_OUT) { | |
fe0b94ab | 2448 | /* Move to STATUS IN */ |
b4c53b4a MH |
2449 | if (!hsotg->delayed_status) |
2450 | dwc2_hsotg_ep0_zlp(hsotg, true); | |
5b7d70c6 BD |
2451 | } |
2452 | ||
4faf3b36 | 2453 | /* Set actual frame number for completed transfers */ |
91bb163e MH |
2454 | if (!using_desc_dma(hsotg) && hs_ep->isochronous) { |
2455 | req->frame_number = hs_ep->target_frame; | |
2456 | dwc2_gadget_incr_frame_num(hs_ep); | |
2457 | } | |
4faf3b36 | 2458 | |
1f91b4cc | 2459 | dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, result); |
5b7d70c6 BD |
2460 | } |
2461 | ||
5b7d70c6 | 2462 | /** |
1f91b4cc | 2463 | * dwc2_hsotg_handle_rx - RX FIFO has data |
5b7d70c6 BD |
2464 | * @hsotg: The device instance |
2465 | * | |
2466 | * The IRQ handler has detected that the RX FIFO has some data in it | |
2467 | * that requires processing, so find out what is in there and do the | |
2468 | * appropriate read. | |
2469 | * | |
25985edc | 2470 | * The RXFIFO is a true FIFO, the packets coming out are still in packet |
5b7d70c6 BD |
2471 | * chunks, so if you have x packets received on an endpoint you'll get x |
2472 | * FIFO events delivered, each with a packet's worth of data in it. | |
2473 | * | |
2474 | * When using DMA, we should not be processing events from the RXFIFO | |
2475 | * as the actual data should be sent to the memory directly and we turn | |
2476 | * on the completion interrupts to get notifications of transfer completion. | |
2477 | */ | |
1f91b4cc | 2478 | static void dwc2_hsotg_handle_rx(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 2479 | { |
f25c42b8 | 2480 | u32 grxstsr = dwc2_readl(hsotg, GRXSTSP); |
5b7d70c6 BD |
2481 | u32 epnum, status, size; |
2482 | ||
2483 | WARN_ON(using_dma(hsotg)); | |
2484 | ||
47a1685f DN |
2485 | epnum = grxstsr & GRXSTS_EPNUM_MASK; |
2486 | status = grxstsr & GRXSTS_PKTSTS_MASK; | |
5b7d70c6 | 2487 | |
47a1685f DN |
2488 | size = grxstsr & GRXSTS_BYTECNT_MASK; |
2489 | size >>= GRXSTS_BYTECNT_SHIFT; | |
5b7d70c6 | 2490 | |
d7c747c5 | 2491 | dev_dbg(hsotg->dev, "%s: GRXSTSP=0x%08x (%d@%d)\n", |
9da51974 | 2492 | __func__, grxstsr, size, epnum); |
5b7d70c6 | 2493 | |
47a1685f DN |
2494 | switch ((status & GRXSTS_PKTSTS_MASK) >> GRXSTS_PKTSTS_SHIFT) { |
2495 | case GRXSTS_PKTSTS_GLOBALOUTNAK: | |
2496 | dev_dbg(hsotg->dev, "GLOBALOUTNAK\n"); | |
5b7d70c6 BD |
2497 | break; |
2498 | ||
47a1685f | 2499 | case GRXSTS_PKTSTS_OUTDONE: |
5b7d70c6 | 2500 | dev_dbg(hsotg->dev, "OutDone (Frame=0x%08x)\n", |
1f91b4cc | 2501 | dwc2_hsotg_read_frameno(hsotg)); |
5b7d70c6 BD |
2502 | |
2503 | if (!using_dma(hsotg)) | |
1f91b4cc | 2504 | dwc2_hsotg_handle_outdone(hsotg, epnum); |
5b7d70c6 BD |
2505 | break; |
2506 | ||
47a1685f | 2507 | case GRXSTS_PKTSTS_SETUPDONE: |
5b7d70c6 BD |
2508 | dev_dbg(hsotg->dev, |
2509 | "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n", | |
1f91b4cc | 2510 | dwc2_hsotg_read_frameno(hsotg), |
f25c42b8 | 2511 | dwc2_readl(hsotg, DOEPCTL(0))); |
fe0b94ab | 2512 | /* |
1f91b4cc | 2513 | * Call dwc2_hsotg_handle_outdone here if it was not called from |
fe0b94ab MYK |
2514 | * GRXSTS_PKTSTS_OUTDONE. That is, if the core didn't |
2515 | * generate GRXSTS_PKTSTS_OUTDONE for setup packet. | |
2516 | */ | |
2517 | if (hsotg->ep0_state == DWC2_EP0_SETUP) | |
1f91b4cc | 2518 | dwc2_hsotg_handle_outdone(hsotg, epnum); |
5b7d70c6 BD |
2519 | break; |
2520 | ||
47a1685f | 2521 | case GRXSTS_PKTSTS_OUTRX: |
1f91b4cc | 2522 | dwc2_hsotg_rx_data(hsotg, epnum, size); |
5b7d70c6 BD |
2523 | break; |
2524 | ||
47a1685f | 2525 | case GRXSTS_PKTSTS_SETUPRX: |
5b7d70c6 BD |
2526 | dev_dbg(hsotg->dev, |
2527 | "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n", | |
1f91b4cc | 2528 | dwc2_hsotg_read_frameno(hsotg), |
f25c42b8 | 2529 | dwc2_readl(hsotg, DOEPCTL(0))); |
5b7d70c6 | 2530 | |
fe0b94ab MYK |
2531 | WARN_ON(hsotg->ep0_state != DWC2_EP0_SETUP); |
2532 | ||
1f91b4cc | 2533 | dwc2_hsotg_rx_data(hsotg, epnum, size); |
5b7d70c6 BD |
2534 | break; |
2535 | ||
2536 | default: | |
2537 | dev_warn(hsotg->dev, "%s: unknown status %08x\n", | |
2538 | __func__, grxstsr); | |
2539 | ||
1f91b4cc | 2540 | dwc2_hsotg_dump(hsotg); |
5b7d70c6 BD |
2541 | break; |
2542 | } | |
2543 | } | |
2544 | ||
2545 | /** | |
1f91b4cc | 2546 | * dwc2_hsotg_ep0_mps - turn max packet size into register setting |
5b7d70c6 | 2547 | * @mps: The maximum packet size in bytes. |
8b9bc460 | 2548 | */ |
1f91b4cc | 2549 | static u32 dwc2_hsotg_ep0_mps(unsigned int mps) |
5b7d70c6 BD |
2550 | { |
2551 | switch (mps) { | |
2552 | case 64: | |
94cb8fd6 | 2553 | return D0EPCTL_MPS_64; |
5b7d70c6 | 2554 | case 32: |
94cb8fd6 | 2555 | return D0EPCTL_MPS_32; |
5b7d70c6 | 2556 | case 16: |
94cb8fd6 | 2557 | return D0EPCTL_MPS_16; |
5b7d70c6 | 2558 | case 8: |
94cb8fd6 | 2559 | return D0EPCTL_MPS_8; |
5b7d70c6 BD |
2560 | } |
2561 | ||
2562 | /* bad max packet size, warn and return invalid result */ | |
2563 | WARN_ON(1); | |
2564 | return (u32)-1; | |
2565 | } | |
2566 | ||
2567 | /** | |
1f91b4cc | 2568 | * dwc2_hsotg_set_ep_maxpacket - set endpoint's max-packet field |
5b7d70c6 BD |
2569 | * @hsotg: The driver state. |
2570 | * @ep: The index number of the endpoint | |
2571 | * @mps: The maximum packet size in bytes | |
ee2c40de | 2572 | * @mc: The multicount value |
6fb914d7 | 2573 | * @dir_in: True if direction is in. |
5b7d70c6 BD |
2574 | * |
2575 | * Configure the maximum packet size for the given endpoint, updating | |
2576 | * the hardware control registers to reflect this. | |
2577 | */ | |
1f91b4cc | 2578 | static void dwc2_hsotg_set_ep_maxpacket(struct dwc2_hsotg *hsotg, |
ee2c40de VM |
2579 | unsigned int ep, unsigned int mps, |
2580 | unsigned int mc, unsigned int dir_in) | |
5b7d70c6 | 2581 | { |
1f91b4cc | 2582 | struct dwc2_hsotg_ep *hs_ep; |
5b7d70c6 BD |
2583 | u32 reg; |
2584 | ||
c6f5c050 MYK |
2585 | hs_ep = index_to_ep(hsotg, ep, dir_in); |
2586 | if (!hs_ep) | |
2587 | return; | |
2588 | ||
5b7d70c6 | 2589 | if (ep == 0) { |
ee2c40de VM |
2590 | u32 mps_bytes = mps; |
2591 | ||
5b7d70c6 | 2592 | /* EP0 is a special case */ |
ee2c40de VM |
2593 | mps = dwc2_hsotg_ep0_mps(mps_bytes); |
2594 | if (mps > 3) | |
5b7d70c6 | 2595 | goto bad_mps; |
ee2c40de | 2596 | hs_ep->ep.maxpacket = mps_bytes; |
4fca54aa | 2597 | hs_ep->mc = 1; |
5b7d70c6 | 2598 | } else { |
ee2c40de | 2599 | if (mps > 1024) |
5b7d70c6 | 2600 | goto bad_mps; |
ee2c40de VM |
2601 | hs_ep->mc = mc; |
2602 | if (mc > 3) | |
4fca54aa | 2603 | goto bad_mps; |
ee2c40de | 2604 | hs_ep->ep.maxpacket = mps; |
5b7d70c6 BD |
2605 | } |
2606 | ||
c6f5c050 | 2607 | if (dir_in) { |
f25c42b8 | 2608 | reg = dwc2_readl(hsotg, DIEPCTL(ep)); |
c6f5c050 | 2609 | reg &= ~DXEPCTL_MPS_MASK; |
ee2c40de | 2610 | reg |= mps; |
f25c42b8 | 2611 | dwc2_writel(hsotg, reg, DIEPCTL(ep)); |
c6f5c050 | 2612 | } else { |
f25c42b8 | 2613 | reg = dwc2_readl(hsotg, DOEPCTL(ep)); |
47a1685f | 2614 | reg &= ~DXEPCTL_MPS_MASK; |
ee2c40de | 2615 | reg |= mps; |
f25c42b8 | 2616 | dwc2_writel(hsotg, reg, DOEPCTL(ep)); |
659ad60c | 2617 | } |
5b7d70c6 BD |
2618 | |
2619 | return; | |
2620 | ||
2621 | bad_mps: | |
2622 | dev_err(hsotg->dev, "ep%d: bad mps of %d\n", ep, mps); | |
2623 | } | |
2624 | ||
9c39ddc6 | 2625 | /** |
1f91b4cc | 2626 | * dwc2_hsotg_txfifo_flush - flush Tx FIFO |
9c39ddc6 AT |
2627 | * @hsotg: The driver state |
2628 | * @idx: The index for the endpoint (0..15) | |
2629 | */ | |
1f91b4cc | 2630 | static void dwc2_hsotg_txfifo_flush(struct dwc2_hsotg *hsotg, unsigned int idx) |
9c39ddc6 | 2631 | { |
f25c42b8 GS |
2632 | dwc2_writel(hsotg, GRSTCTL_TXFNUM(idx) | GRSTCTL_TXFFLSH, |
2633 | GRSTCTL); | |
9c39ddc6 AT |
2634 | |
2635 | /* wait until the fifo is flushed */ | |
79d6b8c5 SA |
2636 | if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL, GRSTCTL_TXFFLSH, 100)) |
2637 | dev_warn(hsotg->dev, "%s: timeout flushing fifo GRSTCTL_TXFFLSH\n", | |
2638 | __func__); | |
9c39ddc6 | 2639 | } |
5b7d70c6 BD |
2640 | |
2641 | /** | |
1f91b4cc | 2642 | * dwc2_hsotg_trytx - check to see if anything needs transmitting |
5b7d70c6 BD |
2643 | * @hsotg: The driver state |
2644 | * @hs_ep: The driver endpoint to check. | |
2645 | * | |
2646 | * Check to see if there is a request that has data to send, and if so | |
2647 | * make an attempt to write data into the FIFO. | |
2648 | */ | |
1f91b4cc | 2649 | static int dwc2_hsotg_trytx(struct dwc2_hsotg *hsotg, |
9da51974 | 2650 | struct dwc2_hsotg_ep *hs_ep) |
5b7d70c6 | 2651 | { |
1f91b4cc | 2652 | struct dwc2_hsotg_req *hs_req = hs_ep->req; |
5b7d70c6 | 2653 | |
afcf4169 RB |
2654 | if (!hs_ep->dir_in || !hs_req) { |
2655 | /** | |
2656 | * if request is not enqueued, we disable interrupts | |
2657 | * for endpoints, excepting ep0 | |
2658 | */ | |
2659 | if (hs_ep->index != 0) | |
1f91b4cc | 2660 | dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, |
9da51974 | 2661 | hs_ep->dir_in, 0); |
5b7d70c6 | 2662 | return 0; |
afcf4169 | 2663 | } |
5b7d70c6 BD |
2664 | |
2665 | if (hs_req->req.actual < hs_req->req.length) { | |
2666 | dev_dbg(hsotg->dev, "trying to write more for ep%d\n", | |
2667 | hs_ep->index); | |
1f91b4cc | 2668 | return dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req); |
5b7d70c6 BD |
2669 | } |
2670 | ||
2671 | return 0; | |
2672 | } | |
2673 | ||
2674 | /** | |
1f91b4cc | 2675 | * dwc2_hsotg_complete_in - complete IN transfer |
5b7d70c6 BD |
2676 | * @hsotg: The device state. |
2677 | * @hs_ep: The endpoint that has just completed. | |
2678 | * | |
2679 | * An IN transfer has been completed, update the transfer's state and then | |
2680 | * call the relevant completion routines. | |
2681 | */ | |
1f91b4cc | 2682 | static void dwc2_hsotg_complete_in(struct dwc2_hsotg *hsotg, |
9da51974 | 2683 | struct dwc2_hsotg_ep *hs_ep) |
5b7d70c6 | 2684 | { |
1f91b4cc | 2685 | struct dwc2_hsotg_req *hs_req = hs_ep->req; |
f25c42b8 | 2686 | u32 epsize = dwc2_readl(hsotg, DIEPTSIZ(hs_ep->index)); |
5b7d70c6 BD |
2687 | int size_left, size_done; |
2688 | ||
2689 | if (!hs_req) { | |
2690 | dev_dbg(hsotg->dev, "XferCompl but no req\n"); | |
2691 | return; | |
2692 | } | |
2693 | ||
d3ca0259 | 2694 | /* Finish ZLP handling for IN EP0 transactions */ |
fe0b94ab MYK |
2695 | if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_IN) { |
2696 | dev_dbg(hsotg->dev, "zlp packet sent\n"); | |
c3b22fe2 RK |
2697 | |
2698 | /* | |
2699 | * While send zlp for DWC2_EP0_STATUS_IN EP direction was | |
2700 | * changed to IN. Change back to complete OUT transfer request | |
2701 | */ | |
2702 | hs_ep->dir_in = 0; | |
2703 | ||
1f91b4cc | 2704 | dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0); |
9e14d0a5 GH |
2705 | if (hsotg->test_mode) { |
2706 | int ret; | |
2707 | ||
1f91b4cc | 2708 | ret = dwc2_hsotg_set_test_mode(hsotg, hsotg->test_mode); |
9e14d0a5 GH |
2709 | if (ret < 0) { |
2710 | dev_dbg(hsotg->dev, "Invalid Test #%d\n", | |
9da51974 | 2711 | hsotg->test_mode); |
1f91b4cc | 2712 | dwc2_hsotg_stall_ep0(hsotg); |
9e14d0a5 GH |
2713 | return; |
2714 | } | |
2715 | } | |
1f91b4cc | 2716 | dwc2_hsotg_enqueue_setup(hsotg); |
d3ca0259 LM |
2717 | return; |
2718 | } | |
2719 | ||
8b9bc460 LM |
2720 | /* |
2721 | * Calculate the size of the transfer by checking how much is left | |
5b7d70c6 BD |
2722 | * in the endpoint size register and then working it out from |
2723 | * the amount we loaded for the transfer. | |
2724 | * | |
2725 | * We do this even for DMA, as the transfer may have incremented | |
2726 | * past the end of the buffer (DMA transfers are always 32bit | |
2727 | * aligned). | |
2728 | */ | |
aa3e8bc8 VA |
2729 | if (using_desc_dma(hsotg)) { |
2730 | size_left = dwc2_gadget_get_xfersize_ddma(hs_ep); | |
2731 | if (size_left < 0) | |
2732 | dev_err(hsotg->dev, "error parsing DDMA results %d\n", | |
2733 | size_left); | |
2734 | } else { | |
2735 | size_left = DXEPTSIZ_XFERSIZE_GET(epsize); | |
2736 | } | |
5b7d70c6 BD |
2737 | |
2738 | size_done = hs_ep->size_loaded - size_left; | |
2739 | size_done += hs_ep->last_load; | |
2740 | ||
2741 | if (hs_req->req.actual != size_done) | |
2742 | dev_dbg(hsotg->dev, "%s: adjusting size done %d => %d\n", | |
2743 | __func__, hs_req->req.actual, size_done); | |
2744 | ||
2745 | hs_req->req.actual = size_done; | |
d3ca0259 LM |
2746 | dev_dbg(hsotg->dev, "req->length:%d req->actual:%d req->zero:%d\n", |
2747 | hs_req->req.length, hs_req->req.actual, hs_req->req.zero); | |
2748 | ||
5b7d70c6 BD |
2749 | if (!size_left && hs_req->req.actual < hs_req->req.length) { |
2750 | dev_dbg(hsotg->dev, "%s trying more for req...\n", __func__); | |
1f91b4cc | 2751 | dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true); |
fe0b94ab MYK |
2752 | return; |
2753 | } | |
2754 | ||
d53dc388 | 2755 | /* Zlp for all endpoints in non DDMA, for ep0 only in DATA IN stage */ |
8a20fa45 | 2756 | if (hs_ep->send_zlp) { |
8a20fa45 | 2757 | hs_ep->send_zlp = 0; |
d53dc388 MH |
2758 | if (!using_desc_dma(hsotg)) { |
2759 | dwc2_hsotg_program_zlp(hsotg, hs_ep); | |
2760 | /* transfer will be completed on next complete interrupt */ | |
2761 | return; | |
2762 | } | |
f71b5e25 MYK |
2763 | } |
2764 | ||
fe0b94ab MYK |
2765 | if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_DATA_IN) { |
2766 | /* Move to STATUS OUT */ | |
1f91b4cc | 2767 | dwc2_hsotg_ep0_zlp(hsotg, false); |
fe0b94ab MYK |
2768 | return; |
2769 | } | |
2770 | ||
91bb163e MH |
2771 | /* Set actual frame number for completed transfers */ |
2772 | if (!using_desc_dma(hsotg) && hs_ep->isochronous) { | |
2773 | hs_req->req.frame_number = hs_ep->target_frame; | |
2774 | dwc2_gadget_incr_frame_num(hs_ep); | |
2775 | } | |
2776 | ||
1f91b4cc | 2777 | dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0); |
5b7d70c6 BD |
2778 | } |
2779 | ||
32601588 VM |
2780 | /** |
2781 | * dwc2_gadget_read_ep_interrupts - reads interrupts for given ep | |
2782 | * @hsotg: The device state. | |
2783 | * @idx: Index of ep. | |
2784 | * @dir_in: Endpoint direction 1-in 0-out. | |
2785 | * | |
2786 | * Reads for endpoint with given index and direction, by masking | |
2787 | * epint_reg with coresponding mask. | |
2788 | */ | |
2789 | static u32 dwc2_gadget_read_ep_interrupts(struct dwc2_hsotg *hsotg, | |
2790 | unsigned int idx, int dir_in) | |
2791 | { | |
2792 | u32 epmsk_reg = dir_in ? DIEPMSK : DOEPMSK; | |
2793 | u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx); | |
2794 | u32 ints; | |
2795 | u32 mask; | |
2796 | u32 diepempmsk; | |
2797 | ||
f25c42b8 GS |
2798 | mask = dwc2_readl(hsotg, epmsk_reg); |
2799 | diepempmsk = dwc2_readl(hsotg, DIEPEMPMSK); | |
32601588 VM |
2800 | mask |= ((diepempmsk >> idx) & 0x1) ? DIEPMSK_TXFIFOEMPTY : 0; |
2801 | mask |= DXEPINT_SETUP_RCVD; | |
2802 | ||
f25c42b8 | 2803 | ints = dwc2_readl(hsotg, epint_reg); |
32601588 VM |
2804 | ints &= mask; |
2805 | return ints; | |
2806 | } | |
2807 | ||
bd9971f0 VM |
2808 | /** |
2809 | * dwc2_gadget_handle_ep_disabled - handle DXEPINT_EPDISBLD | |
2810 | * @hs_ep: The endpoint on which interrupt is asserted. | |
2811 | * | |
2812 | * This interrupt indicates that the endpoint has been disabled per the | |
2813 | * application's request. | |
2814 | * | |
2815 | * For IN endpoints flushes txfifo, in case of BULK clears DCTL_CGNPINNAK, | |
2816 | * in case of ISOC completes current request. | |
2817 | * | |
2818 | * For ISOC-OUT endpoints completes expired requests. If there is remaining | |
2819 | * request starts it. | |
2820 | */ | |
2821 | static void dwc2_gadget_handle_ep_disabled(struct dwc2_hsotg_ep *hs_ep) | |
2822 | { | |
2823 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
2824 | struct dwc2_hsotg_req *hs_req; | |
2825 | unsigned char idx = hs_ep->index; | |
2826 | int dir_in = hs_ep->dir_in; | |
2827 | u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx); | |
f25c42b8 | 2828 | int dctl = dwc2_readl(hsotg, DCTL); |
bd9971f0 VM |
2829 | |
2830 | dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__); | |
2831 | ||
2832 | if (dir_in) { | |
f25c42b8 | 2833 | int epctl = dwc2_readl(hsotg, epctl_reg); |
bd9971f0 VM |
2834 | |
2835 | dwc2_hsotg_txfifo_flush(hsotg, hs_ep->fifo_index); | |
2836 | ||
bd9971f0 | 2837 | if ((epctl & DXEPCTL_STALL) && (epctl & DXEPCTL_EPTYPE_BULK)) { |
f25c42b8 | 2838 | int dctl = dwc2_readl(hsotg, DCTL); |
bd9971f0 VM |
2839 | |
2840 | dctl |= DCTL_CGNPINNAK; | |
f25c42b8 | 2841 | dwc2_writel(hsotg, dctl, DCTL); |
bd9971f0 | 2842 | } |
91bb163e | 2843 | } else { |
bd9971f0 | 2844 | |
91bb163e MH |
2845 | if (dctl & DCTL_GOUTNAKSTS) { |
2846 | dctl |= DCTL_CGOUTNAK; | |
2847 | dwc2_writel(hsotg, dctl, DCTL); | |
2848 | } | |
bd9971f0 VM |
2849 | } |
2850 | ||
2851 | if (!hs_ep->isochronous) | |
2852 | return; | |
2853 | ||
2854 | if (list_empty(&hs_ep->queue)) { | |
2855 | dev_dbg(hsotg->dev, "%s: complete_ep 0x%p, ep->queue empty!\n", | |
2856 | __func__, hs_ep); | |
2857 | return; | |
2858 | } | |
2859 | ||
2860 | do { | |
2861 | hs_req = get_ep_head(hs_ep); | |
7ad4a0b1 MH |
2862 | if (hs_req) { |
2863 | hs_req->req.frame_number = hs_ep->target_frame; | |
2864 | hs_req->req.actual = 0; | |
bd9971f0 VM |
2865 | dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, |
2866 | -ENODATA); | |
7ad4a0b1 | 2867 | } |
bd9971f0 | 2868 | dwc2_gadget_incr_frame_num(hs_ep); |
c7c24e7a AP |
2869 | /* Update current frame number value. */ |
2870 | hsotg->frame_number = dwc2_hsotg_read_frameno(hsotg); | |
bd9971f0 | 2871 | } while (dwc2_gadget_target_frame_elapsed(hs_ep)); |
bd9971f0 VM |
2872 | } |
2873 | ||
5321922c VM |
2874 | /** |
2875 | * dwc2_gadget_handle_out_token_ep_disabled - handle DXEPINT_OUTTKNEPDIS | |
6fb914d7 | 2876 | * @ep: The endpoint on which interrupt is asserted. |
5321922c VM |
2877 | * |
2878 | * This is starting point for ISOC-OUT transfer, synchronization done with | |
2879 | * first out token received from host while corresponding EP is disabled. | |
2880 | * | |
2881 | * Device does not know initial frame in which out token will come. For this | |
2882 | * HW generates OUTTKNEPDIS - out token is received while EP is disabled. Upon | |
2883 | * getting this interrupt SW starts calculation for next transfer frame. | |
2884 | */ | |
2885 | static void dwc2_gadget_handle_out_token_ep_disabled(struct dwc2_hsotg_ep *ep) | |
2886 | { | |
2887 | struct dwc2_hsotg *hsotg = ep->parent; | |
91bb163e | 2888 | struct dwc2_hsotg_req *hs_req; |
5321922c | 2889 | int dir_in = ep->dir_in; |
5321922c VM |
2890 | |
2891 | if (dir_in || !ep->isochronous) | |
2892 | return; | |
2893 | ||
540ccba0 VA |
2894 | if (using_desc_dma(hsotg)) { |
2895 | if (ep->target_frame == TARGET_FRAME_INITIAL) { | |
2896 | /* Start first ISO Out */ | |
4d4f1e79 | 2897 | ep->target_frame = hsotg->frame_number; |
540ccba0 VA |
2898 | dwc2_gadget_start_isoc_ddma(ep); |
2899 | } | |
2900 | return; | |
2901 | } | |
2902 | ||
91bb163e | 2903 | if (ep->target_frame == TARGET_FRAME_INITIAL) { |
5321922c VM |
2904 | u32 ctrl; |
2905 | ||
4d4f1e79 | 2906 | ep->target_frame = hsotg->frame_number; |
91bb163e MH |
2907 | if (ep->interval > 1) { |
2908 | ctrl = dwc2_readl(hsotg, DOEPCTL(ep->index)); | |
2909 | if (ep->target_frame & 0x1) | |
2910 | ctrl |= DXEPCTL_SETODDFR; | |
2911 | else | |
2912 | ctrl |= DXEPCTL_SETEVENFR; | |
5321922c | 2913 | |
91bb163e MH |
2914 | dwc2_writel(hsotg, ctrl, DOEPCTL(ep->index)); |
2915 | } | |
2916 | } | |
2917 | ||
2918 | while (dwc2_gadget_target_frame_elapsed(ep)) { | |
2919 | hs_req = get_ep_head(ep); | |
7ad4a0b1 MH |
2920 | if (hs_req) { |
2921 | hs_req->req.frame_number = ep->target_frame; | |
2922 | hs_req->req.actual = 0; | |
91bb163e | 2923 | dwc2_hsotg_complete_request(hsotg, ep, hs_req, -ENODATA); |
7ad4a0b1 | 2924 | } |
5321922c | 2925 | |
91bb163e MH |
2926 | dwc2_gadget_incr_frame_num(ep); |
2927 | /* Update current frame number value. */ | |
2928 | hsotg->frame_number = dwc2_hsotg_read_frameno(hsotg); | |
5321922c VM |
2929 | } |
2930 | ||
91bb163e MH |
2931 | if (!ep->req) |
2932 | dwc2_gadget_start_next_request(ep); | |
2933 | ||
5321922c VM |
2934 | } |
2935 | ||
91bb163e MH |
2936 | static void dwc2_hsotg_ep_stop_xfr(struct dwc2_hsotg *hsotg, |
2937 | struct dwc2_hsotg_ep *hs_ep); | |
2938 | ||
5321922c | 2939 | /** |
38beaec6 JY |
2940 | * dwc2_gadget_handle_nak - handle NAK interrupt |
2941 | * @hs_ep: The endpoint on which interrupt is asserted. | |
2942 | * | |
2943 | * This is starting point for ISOC-IN transfer, synchronization done with | |
2944 | * first IN token received from host while corresponding EP is disabled. | |
2945 | * | |
2946 | * Device does not know when first one token will arrive from host. On first | |
2947 | * token arrival HW generates 2 interrupts: 'in token received while FIFO empty' | |
2948 | * and 'NAK'. NAK interrupt for ISOC-IN means that token has arrived and ZLP was | |
2949 | * sent in response to that as there was no data in FIFO. SW is basing on this | |
2950 | * interrupt to obtain frame in which token has come and then based on the | |
2951 | * interval calculates next frame for transfer. | |
2952 | */ | |
5321922c VM |
2953 | static void dwc2_gadget_handle_nak(struct dwc2_hsotg_ep *hs_ep) |
2954 | { | |
2955 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
91bb163e | 2956 | struct dwc2_hsotg_req *hs_req; |
5321922c | 2957 | int dir_in = hs_ep->dir_in; |
91bb163e | 2958 | u32 ctrl; |
5321922c VM |
2959 | |
2960 | if (!dir_in || !hs_ep->isochronous) | |
2961 | return; | |
2962 | ||
2963 | if (hs_ep->target_frame == TARGET_FRAME_INITIAL) { | |
540ccba0 VA |
2964 | |
2965 | if (using_desc_dma(hsotg)) { | |
4d4f1e79 | 2966 | hs_ep->target_frame = hsotg->frame_number; |
729cac69 | 2967 | dwc2_gadget_incr_frame_num(hs_ep); |
48dac4e4 GT |
2968 | |
2969 | /* In service interval mode target_frame must | |
2970 | * be set to last (u)frame of the service interval. | |
2971 | */ | |
2972 | if (hsotg->params.service_interval) { | |
2973 | /* Set target_frame to the first (u)frame of | |
2974 | * the service interval | |
2975 | */ | |
2976 | hs_ep->target_frame &= ~hs_ep->interval + 1; | |
2977 | ||
2978 | /* Set target_frame to the last (u)frame of | |
2979 | * the service interval | |
2980 | */ | |
2981 | dwc2_gadget_incr_frame_num(hs_ep); | |
2982 | dwc2_gadget_dec_frame_num_by_one(hs_ep); | |
2983 | } | |
2984 | ||
540ccba0 VA |
2985 | dwc2_gadget_start_isoc_ddma(hs_ep); |
2986 | return; | |
2987 | } | |
2988 | ||
4d4f1e79 | 2989 | hs_ep->target_frame = hsotg->frame_number; |
5321922c | 2990 | if (hs_ep->interval > 1) { |
f25c42b8 | 2991 | u32 ctrl = dwc2_readl(hsotg, |
5321922c VM |
2992 | DIEPCTL(hs_ep->index)); |
2993 | if (hs_ep->target_frame & 0x1) | |
2994 | ctrl |= DXEPCTL_SETODDFR; | |
2995 | else | |
2996 | ctrl |= DXEPCTL_SETEVENFR; | |
2997 | ||
f25c42b8 | 2998 | dwc2_writel(hsotg, ctrl, DIEPCTL(hs_ep->index)); |
5321922c | 2999 | } |
5321922c VM |
3000 | } |
3001 | ||
91bb163e MH |
3002 | if (using_desc_dma(hsotg)) |
3003 | return; | |
3004 | ||
3005 | ctrl = dwc2_readl(hsotg, DIEPCTL(hs_ep->index)); | |
3006 | if (ctrl & DXEPCTL_EPENA) | |
3007 | dwc2_hsotg_ep_stop_xfr(hsotg, hs_ep); | |
3008 | else | |
3009 | dwc2_hsotg_txfifo_flush(hsotg, hs_ep->fifo_index); | |
3010 | ||
3011 | while (dwc2_gadget_target_frame_elapsed(hs_ep)) { | |
3012 | hs_req = get_ep_head(hs_ep); | |
7ad4a0b1 MH |
3013 | if (hs_req) { |
3014 | hs_req->req.frame_number = hs_ep->target_frame; | |
3015 | hs_req->req.actual = 0; | |
91bb163e | 3016 | dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, -ENODATA); |
7ad4a0b1 | 3017 | } |
91bb163e | 3018 | |
729cac69 | 3019 | dwc2_gadget_incr_frame_num(hs_ep); |
91bb163e MH |
3020 | /* Update current frame number value. */ |
3021 | hsotg->frame_number = dwc2_hsotg_read_frameno(hsotg); | |
3022 | } | |
3023 | ||
3024 | if (!hs_ep->req) | |
3025 | dwc2_gadget_start_next_request(hs_ep); | |
5321922c VM |
3026 | } |
3027 | ||
5b7d70c6 | 3028 | /** |
1f91b4cc | 3029 | * dwc2_hsotg_epint - handle an in/out endpoint interrupt |
5b7d70c6 BD |
3030 | * @hsotg: The driver state |
3031 | * @idx: The index for the endpoint (0..15) | |
3032 | * @dir_in: Set if this is an IN endpoint | |
3033 | * | |
3034 | * Process and clear any interrupt pending for an individual endpoint | |
8b9bc460 | 3035 | */ |
1f91b4cc | 3036 | static void dwc2_hsotg_epint(struct dwc2_hsotg *hsotg, unsigned int idx, |
9da51974 | 3037 | int dir_in) |
5b7d70c6 | 3038 | { |
1f91b4cc | 3039 | struct dwc2_hsotg_ep *hs_ep = index_to_ep(hsotg, idx, dir_in); |
94cb8fd6 LM |
3040 | u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx); |
3041 | u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx); | |
3042 | u32 epsiz_reg = dir_in ? DIEPTSIZ(idx) : DOEPTSIZ(idx); | |
5b7d70c6 | 3043 | u32 ints; |
5b7d70c6 | 3044 | |
32601588 | 3045 | ints = dwc2_gadget_read_ep_interrupts(hsotg, idx, dir_in); |
5b7d70c6 | 3046 | |
a3395f0d | 3047 | /* Clear endpoint interrupts */ |
f25c42b8 | 3048 | dwc2_writel(hsotg, ints, epint_reg); |
a3395f0d | 3049 | |
c6f5c050 MYK |
3050 | if (!hs_ep) { |
3051 | dev_err(hsotg->dev, "%s:Interrupt for unconfigured ep%d(%s)\n", | |
9da51974 | 3052 | __func__, idx, dir_in ? "in" : "out"); |
c6f5c050 MYK |
3053 | return; |
3054 | } | |
3055 | ||
5b7d70c6 BD |
3056 | dev_dbg(hsotg->dev, "%s: ep%d(%s) DxEPINT=0x%08x\n", |
3057 | __func__, idx, dir_in ? "in" : "out", ints); | |
3058 | ||
b787d755 MYK |
3059 | /* Don't process XferCompl interrupt if it is a setup packet */ |
3060 | if (idx == 0 && (ints & (DXEPINT_SETUP | DXEPINT_SETUP_RCVD))) | |
3061 | ints &= ~DXEPINT_XFERCOMPL; | |
3062 | ||
f0afdb42 VA |
3063 | /* |
3064 | * Don't process XferCompl interrupt in DDMA if EP0 is still in SETUP | |
3065 | * stage and xfercomplete was generated without SETUP phase done | |
3066 | * interrupt. SW should parse received setup packet only after host's | |
3067 | * exit from setup phase of control transfer. | |
3068 | */ | |
3069 | if (using_desc_dma(hsotg) && idx == 0 && !hs_ep->dir_in && | |
3070 | hsotg->ep0_state == DWC2_EP0_SETUP && !(ints & DXEPINT_SETUP)) | |
3071 | ints &= ~DXEPINT_XFERCOMPL; | |
3072 | ||
837e9f00 | 3073 | if (ints & DXEPINT_XFERCOMPL) { |
5b7d70c6 | 3074 | dev_dbg(hsotg->dev, |
47a1685f | 3075 | "%s: XferCompl: DxEPCTL=0x%08x, DXEPTSIZ=%08x\n", |
f25c42b8 GS |
3076 | __func__, dwc2_readl(hsotg, epctl_reg), |
3077 | dwc2_readl(hsotg, epsiz_reg)); | |
5b7d70c6 | 3078 | |
540ccba0 VA |
3079 | /* In DDMA handle isochronous requests separately */ |
3080 | if (using_desc_dma(hsotg) && hs_ep->isochronous) { | |
dbe2518b | 3081 | dwc2_gadget_complete_isoc_request_ddma(hs_ep); |
540ccba0 VA |
3082 | } else if (dir_in) { |
3083 | /* | |
3084 | * We get OutDone from the FIFO, so we only | |
3085 | * need to look at completing IN requests here | |
3086 | * if operating slave mode | |
3087 | */ | |
91bb163e MH |
3088 | if (!hs_ep->isochronous || !(ints & DXEPINT_NAKINTRPT)) |
3089 | dwc2_hsotg_complete_in(hsotg, hs_ep); | |
5b7d70c6 | 3090 | |
c9a64ea8 | 3091 | if (idx == 0 && !hs_ep->req) |
1f91b4cc | 3092 | dwc2_hsotg_enqueue_setup(hsotg); |
5b7d70c6 | 3093 | } else if (using_dma(hsotg)) { |
8b9bc460 LM |
3094 | /* |
3095 | * We're using DMA, we need to fire an OutDone here | |
3096 | * as we ignore the RXFIFO. | |
3097 | */ | |
91bb163e MH |
3098 | if (!hs_ep->isochronous || !(ints & DXEPINT_OUTTKNEPDIS)) |
3099 | dwc2_hsotg_handle_outdone(hsotg, idx); | |
5b7d70c6 | 3100 | } |
5b7d70c6 BD |
3101 | } |
3102 | ||
bd9971f0 VM |
3103 | if (ints & DXEPINT_EPDISBLD) |
3104 | dwc2_gadget_handle_ep_disabled(hs_ep); | |
9c39ddc6 | 3105 | |
5321922c VM |
3106 | if (ints & DXEPINT_OUTTKNEPDIS) |
3107 | dwc2_gadget_handle_out_token_ep_disabled(hs_ep); | |
3108 | ||
3109 | if (ints & DXEPINT_NAKINTRPT) | |
3110 | dwc2_gadget_handle_nak(hs_ep); | |
3111 | ||
47a1685f | 3112 | if (ints & DXEPINT_AHBERR) |
5b7d70c6 | 3113 | dev_dbg(hsotg->dev, "%s: AHBErr\n", __func__); |
5b7d70c6 | 3114 | |
47a1685f | 3115 | if (ints & DXEPINT_SETUP) { /* Setup or Timeout */ |
5b7d70c6 BD |
3116 | dev_dbg(hsotg->dev, "%s: Setup/Timeout\n", __func__); |
3117 | ||
3118 | if (using_dma(hsotg) && idx == 0) { | |
8b9bc460 LM |
3119 | /* |
3120 | * this is the notification we've received a | |
5b7d70c6 BD |
3121 | * setup packet. In non-DMA mode we'd get this |
3122 | * from the RXFIFO, instead we need to process | |
8b9bc460 LM |
3123 | * the setup here. |
3124 | */ | |
5b7d70c6 BD |
3125 | |
3126 | if (dir_in) | |
3127 | WARN_ON_ONCE(1); | |
3128 | else | |
1f91b4cc | 3129 | dwc2_hsotg_handle_outdone(hsotg, 0); |
5b7d70c6 | 3130 | } |
5b7d70c6 BD |
3131 | } |
3132 | ||
ef750c71 | 3133 | if (ints & DXEPINT_STSPHSERCVD) { |
9d9a6b07 VA |
3134 | dev_dbg(hsotg->dev, "%s: StsPhseRcvd\n", __func__); |
3135 | ||
9e95a66c MH |
3136 | /* Safety check EP0 state when STSPHSERCVD asserted */ |
3137 | if (hsotg->ep0_state == DWC2_EP0_DATA_OUT) { | |
3138 | /* Move to STATUS IN for DDMA */ | |
b4c53b4a MH |
3139 | if (using_desc_dma(hsotg)) { |
3140 | if (!hsotg->delayed_status) | |
3141 | dwc2_hsotg_ep0_zlp(hsotg, true); | |
3142 | else | |
3143 | /* In case of 3 stage Control Write with delayed | |
3144 | * status, when Status IN transfer started | |
3145 | * before STSPHSERCVD asserted, NAKSTS bit not | |
3146 | * cleared by CNAK in dwc2_hsotg_start_req() | |
3147 | * function. Clear now NAKSTS to allow complete | |
3148 | * transfer. | |
3149 | */ | |
3150 | dwc2_set_bit(hsotg, DIEPCTL(0), | |
3151 | DXEPCTL_CNAK); | |
3152 | } | |
9e95a66c MH |
3153 | } |
3154 | ||
ef750c71 VA |
3155 | } |
3156 | ||
47a1685f | 3157 | if (ints & DXEPINT_BACK2BACKSETUP) |
5b7d70c6 | 3158 | dev_dbg(hsotg->dev, "%s: B2BSetup/INEPNakEff\n", __func__); |
5b7d70c6 | 3159 | |
540ccba0 VA |
3160 | if (ints & DXEPINT_BNAINTR) { |
3161 | dev_dbg(hsotg->dev, "%s: BNA interrupt\n", __func__); | |
540ccba0 | 3162 | if (hs_ep->isochronous) |
729cac69 | 3163 | dwc2_gadget_handle_isoc_bna(hs_ep); |
540ccba0 VA |
3164 | } |
3165 | ||
1479e841 | 3166 | if (dir_in && !hs_ep->isochronous) { |
8b9bc460 | 3167 | /* not sure if this is important, but we'll clear it anyway */ |
26ddef5d | 3168 | if (ints & DXEPINT_INTKNTXFEMP) { |
5b7d70c6 BD |
3169 | dev_dbg(hsotg->dev, "%s: ep%d: INTknTXFEmpMsk\n", |
3170 | __func__, idx); | |
5b7d70c6 BD |
3171 | } |
3172 | ||
3173 | /* this probably means something bad is happening */ | |
26ddef5d | 3174 | if (ints & DXEPINT_INTKNEPMIS) { |
5b7d70c6 BD |
3175 | dev_warn(hsotg->dev, "%s: ep%d: INTknEP\n", |
3176 | __func__, idx); | |
5b7d70c6 | 3177 | } |
10aebc77 BD |
3178 | |
3179 | /* FIFO has space or is empty (see GAHBCFG) */ | |
3180 | if (hsotg->dedicated_fifos && | |
26ddef5d | 3181 | ints & DXEPINT_TXFEMP) { |
10aebc77 BD |
3182 | dev_dbg(hsotg->dev, "%s: ep%d: TxFIFOEmpty\n", |
3183 | __func__, idx); | |
70fa030f | 3184 | if (!using_dma(hsotg)) |
1f91b4cc | 3185 | dwc2_hsotg_trytx(hsotg, hs_ep); |
10aebc77 | 3186 | } |
5b7d70c6 | 3187 | } |
5b7d70c6 BD |
3188 | } |
3189 | ||
3190 | /** | |
1f91b4cc | 3191 | * dwc2_hsotg_irq_enumdone - Handle EnumDone interrupt (enumeration done) |
5b7d70c6 BD |
3192 | * @hsotg: The device state. |
3193 | * | |
3194 | * Handle updating the device settings after the enumeration phase has | |
3195 | * been completed. | |
8b9bc460 | 3196 | */ |
1f91b4cc | 3197 | static void dwc2_hsotg_irq_enumdone(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 3198 | { |
f25c42b8 | 3199 | u32 dsts = dwc2_readl(hsotg, DSTS); |
9b2667f1 | 3200 | int ep0_mps = 0, ep_mps = 8; |
5b7d70c6 | 3201 | |
8b9bc460 LM |
3202 | /* |
3203 | * This should signal the finish of the enumeration phase | |
5b7d70c6 | 3204 | * of the USB handshaking, so we should now know what rate |
8b9bc460 LM |
3205 | * we connected at. |
3206 | */ | |
5b7d70c6 BD |
3207 | |
3208 | dev_dbg(hsotg->dev, "EnumDone (DSTS=0x%08x)\n", dsts); | |
3209 | ||
8b9bc460 LM |
3210 | /* |
3211 | * note, since we're limited by the size of transfer on EP0, and | |
5b7d70c6 | 3212 | * it seems IN transfers must be a even number of packets we do |
8b9bc460 LM |
3213 | * not advertise a 64byte MPS on EP0. |
3214 | */ | |
5b7d70c6 BD |
3215 | |
3216 | /* catch both EnumSpd_FS and EnumSpd_FS48 */ | |
6d76c92c | 3217 | switch ((dsts & DSTS_ENUMSPD_MASK) >> DSTS_ENUMSPD_SHIFT) { |
47a1685f DN |
3218 | case DSTS_ENUMSPD_FS: |
3219 | case DSTS_ENUMSPD_FS48: | |
5b7d70c6 | 3220 | hsotg->gadget.speed = USB_SPEED_FULL; |
5b7d70c6 | 3221 | ep0_mps = EP0_MPS_LIMIT; |
295538ff | 3222 | ep_mps = 1023; |
5b7d70c6 BD |
3223 | break; |
3224 | ||
47a1685f | 3225 | case DSTS_ENUMSPD_HS: |
5b7d70c6 | 3226 | hsotg->gadget.speed = USB_SPEED_HIGH; |
5b7d70c6 | 3227 | ep0_mps = EP0_MPS_LIMIT; |
295538ff | 3228 | ep_mps = 1024; |
5b7d70c6 BD |
3229 | break; |
3230 | ||
47a1685f | 3231 | case DSTS_ENUMSPD_LS: |
5b7d70c6 | 3232 | hsotg->gadget.speed = USB_SPEED_LOW; |
552d940f VM |
3233 | ep0_mps = 8; |
3234 | ep_mps = 8; | |
8b9bc460 LM |
3235 | /* |
3236 | * note, we don't actually support LS in this driver at the | |
5b7d70c6 BD |
3237 | * moment, and the documentation seems to imply that it isn't |
3238 | * supported by the PHYs on some of the devices. | |
3239 | */ | |
3240 | break; | |
3241 | } | |
e538dfda MN |
3242 | dev_info(hsotg->dev, "new device is %s\n", |
3243 | usb_speed_string(hsotg->gadget.speed)); | |
5b7d70c6 | 3244 | |
8b9bc460 LM |
3245 | /* |
3246 | * we should now know the maximum packet size for an | |
3247 | * endpoint, so set the endpoints to a default value. | |
3248 | */ | |
5b7d70c6 BD |
3249 | |
3250 | if (ep0_mps) { | |
3251 | int i; | |
c6f5c050 | 3252 | /* Initialize ep0 for both in and out directions */ |
ee2c40de VM |
3253 | dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 0, 1); |
3254 | dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 0, 0); | |
c6f5c050 MYK |
3255 | for (i = 1; i < hsotg->num_of_eps; i++) { |
3256 | if (hsotg->eps_in[i]) | |
ee2c40de VM |
3257 | dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps, |
3258 | 0, 1); | |
c6f5c050 | 3259 | if (hsotg->eps_out[i]) |
ee2c40de VM |
3260 | dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps, |
3261 | 0, 0); | |
c6f5c050 | 3262 | } |
5b7d70c6 BD |
3263 | } |
3264 | ||
3265 | /* ensure after enumeration our EP0 is active */ | |
3266 | ||
1f91b4cc | 3267 | dwc2_hsotg_enqueue_setup(hsotg); |
5b7d70c6 BD |
3268 | |
3269 | dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n", | |
f25c42b8 GS |
3270 | dwc2_readl(hsotg, DIEPCTL0), |
3271 | dwc2_readl(hsotg, DOEPCTL0)); | |
5b7d70c6 BD |
3272 | } |
3273 | ||
3274 | /** | |
3275 | * kill_all_requests - remove all requests from the endpoint's queue | |
3276 | * @hsotg: The device state. | |
3277 | * @ep: The endpoint the requests may be on. | |
3278 | * @result: The result code to use. | |
5b7d70c6 BD |
3279 | * |
3280 | * Go through the requests on the given endpoint and mark them | |
3281 | * completed with the given result code. | |
3282 | */ | |
941fcce4 | 3283 | static void kill_all_requests(struct dwc2_hsotg *hsotg, |
1f91b4cc | 3284 | struct dwc2_hsotg_ep *ep, |
6b448af4 | 3285 | int result) |
5b7d70c6 | 3286 | { |
9da51974 | 3287 | unsigned int size; |
5b7d70c6 | 3288 | |
6b448af4 | 3289 | ep->req = NULL; |
5b7d70c6 | 3290 | |
37bea42f JK |
3291 | while (!list_empty(&ep->queue)) { |
3292 | struct dwc2_hsotg_req *req = get_ep_head(ep); | |
3293 | ||
3294 | dwc2_hsotg_complete_request(hsotg, ep, req, result); | |
3295 | } | |
6b448af4 | 3296 | |
b203d0a2 RB |
3297 | if (!hsotg->dedicated_fifos) |
3298 | return; | |
f25c42b8 | 3299 | size = (dwc2_readl(hsotg, DTXFSTS(ep->fifo_index)) & 0xffff) * 4; |
b203d0a2 | 3300 | if (size < ep->fifo_size) |
1f91b4cc | 3301 | dwc2_hsotg_txfifo_flush(hsotg, ep->fifo_index); |
5b7d70c6 BD |
3302 | } |
3303 | ||
5b7d70c6 | 3304 | /** |
1f91b4cc | 3305 | * dwc2_hsotg_disconnect - disconnect service |
5b7d70c6 BD |
3306 | * @hsotg: The device state. |
3307 | * | |
5e891342 LM |
3308 | * The device has been disconnected. Remove all current |
3309 | * transactions and signal the gadget driver that this | |
3310 | * has happened. | |
8b9bc460 | 3311 | */ |
1f91b4cc | 3312 | void dwc2_hsotg_disconnect(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 3313 | { |
9da51974 | 3314 | unsigned int ep; |
5b7d70c6 | 3315 | |
4ace06e8 MS |
3316 | if (!hsotg->connected) |
3317 | return; | |
3318 | ||
3319 | hsotg->connected = 0; | |
9e14d0a5 | 3320 | hsotg->test_mode = 0; |
c6f5c050 | 3321 | |
dccf1bad | 3322 | /* all endpoints should be shutdown */ |
c6f5c050 MYK |
3323 | for (ep = 0; ep < hsotg->num_of_eps; ep++) { |
3324 | if (hsotg->eps_in[ep]) | |
4fe4f9fe MH |
3325 | kill_all_requests(hsotg, hsotg->eps_in[ep], |
3326 | -ESHUTDOWN); | |
c6f5c050 | 3327 | if (hsotg->eps_out[ep]) |
4fe4f9fe MH |
3328 | kill_all_requests(hsotg, hsotg->eps_out[ep], |
3329 | -ESHUTDOWN); | |
c6f5c050 | 3330 | } |
5b7d70c6 BD |
3331 | |
3332 | call_gadget(hsotg, disconnect); | |
065d3931 | 3333 | hsotg->lx_state = DWC2_L3; |
ce2b21a4 JS |
3334 | |
3335 | usb_gadget_set_state(&hsotg->gadget, USB_STATE_NOTATTACHED); | |
5b7d70c6 BD |
3336 | } |
3337 | ||
3338 | /** | |
1f91b4cc | 3339 | * dwc2_hsotg_irq_fifoempty - TX FIFO empty interrupt handler |
5b7d70c6 BD |
3340 | * @hsotg: The device state: |
3341 | * @periodic: True if this is a periodic FIFO interrupt | |
3342 | */ | |
1f91b4cc | 3343 | static void dwc2_hsotg_irq_fifoempty(struct dwc2_hsotg *hsotg, bool periodic) |
5b7d70c6 | 3344 | { |
1f91b4cc | 3345 | struct dwc2_hsotg_ep *ep; |
5b7d70c6 BD |
3346 | int epno, ret; |
3347 | ||
3348 | /* look through for any more data to transmit */ | |
b3f489b2 | 3349 | for (epno = 0; epno < hsotg->num_of_eps; epno++) { |
c6f5c050 MYK |
3350 | ep = index_to_ep(hsotg, epno, 1); |
3351 | ||
3352 | if (!ep) | |
3353 | continue; | |
5b7d70c6 BD |
3354 | |
3355 | if (!ep->dir_in) | |
3356 | continue; | |
3357 | ||
3358 | if ((periodic && !ep->periodic) || | |
3359 | (!periodic && ep->periodic)) | |
3360 | continue; | |
3361 | ||
1f91b4cc | 3362 | ret = dwc2_hsotg_trytx(hsotg, ep); |
5b7d70c6 BD |
3363 | if (ret < 0) |
3364 | break; | |
3365 | } | |
3366 | } | |
3367 | ||
5b7d70c6 | 3368 | /* IRQ flags which will trigger a retry around the IRQ loop */ |
47a1685f DN |
3369 | #define IRQ_RETRY_MASK (GINTSTS_NPTXFEMP | \ |
3370 | GINTSTS_PTXFEMP | \ | |
3371 | GINTSTS_RXFLVL) | |
5b7d70c6 | 3372 | |
4fe4f9fe | 3373 | static int dwc2_hsotg_ep_disable(struct usb_ep *ep); |
8b9bc460 | 3374 | /** |
58aff959 | 3375 | * dwc2_hsotg_core_init_disconnected - issue softreset to the core |
8b9bc460 | 3376 | * @hsotg: The device state |
6fb914d7 | 3377 | * @is_usb_reset: Usb resetting flag |
8b9bc460 LM |
3378 | * |
3379 | * Issue a soft reset to the core, and await the core finishing it. | |
3380 | */ | |
1f91b4cc | 3381 | void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg, |
9da51974 | 3382 | bool is_usb_reset) |
308d734e | 3383 | { |
1ee6903b | 3384 | u32 intmsk; |
643cc4de | 3385 | u32 val; |
ecd9a7ad | 3386 | u32 usbcfg; |
79c3b5bb | 3387 | u32 dcfg = 0; |
dccf1bad | 3388 | int ep; |
643cc4de | 3389 | |
5390d438 MYK |
3390 | /* Kill any ep0 requests as controller will be reinitialized */ |
3391 | kill_all_requests(hsotg, hsotg->eps_out[0], -ECONNRESET); | |
3392 | ||
dccf1bad | 3393 | if (!is_usb_reset) { |
6e6360b6 | 3394 | if (dwc2_core_reset(hsotg, true)) |
86de4895 | 3395 | return; |
dccf1bad MH |
3396 | } else { |
3397 | /* all endpoints should be shutdown */ | |
3398 | for (ep = 1; ep < hsotg->num_of_eps; ep++) { | |
3399 | if (hsotg->eps_in[ep]) | |
3400 | dwc2_hsotg_ep_disable(&hsotg->eps_in[ep]->ep); | |
3401 | if (hsotg->eps_out[ep]) | |
3402 | dwc2_hsotg_ep_disable(&hsotg->eps_out[ep]->ep); | |
3403 | } | |
3404 | } | |
308d734e LM |
3405 | |
3406 | /* | |
3407 | * we must now enable ep0 ready for host detection and then | |
3408 | * set configuration. | |
3409 | */ | |
3410 | ||
ecd9a7ad | 3411 | /* keep other bits untouched (so e.g. forced modes are not lost) */ |
f25c42b8 | 3412 | usbcfg = dwc2_readl(hsotg, GUSBCFG); |
1e868545 | 3413 | usbcfg &= ~GUSBCFG_TOUTCAL_MASK; |
707d80f0 | 3414 | usbcfg |= GUSBCFG_TOUTCAL(7); |
ecd9a7ad | 3415 | |
1e868545 JM |
3416 | /* remove the HNP/SRP and set the PHY */ |
3417 | usbcfg &= ~(GUSBCFG_SRPCAP | GUSBCFG_HNPCAP); | |
3418 | dwc2_writel(hsotg, usbcfg, GUSBCFG); | |
707d80f0 | 3419 | |
1e868545 | 3420 | dwc2_phy_init(hsotg, true); |
308d734e | 3421 | |
1f91b4cc | 3422 | dwc2_hsotg_init_fifo(hsotg); |
308d734e | 3423 | |
643cc4de | 3424 | if (!is_usb_reset) |
f25c42b8 | 3425 | dwc2_set_bit(hsotg, DCTL, DCTL_SFTDISCON); |
308d734e | 3426 | |
79c3b5bb | 3427 | dcfg |= DCFG_EPMISCNT(1); |
38e9002b VM |
3428 | |
3429 | switch (hsotg->params.speed) { | |
3430 | case DWC2_SPEED_PARAM_LOW: | |
3431 | dcfg |= DCFG_DEVSPD_LS; | |
3432 | break; | |
3433 | case DWC2_SPEED_PARAM_FULL: | |
79c3b5bb VA |
3434 | if (hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS) |
3435 | dcfg |= DCFG_DEVSPD_FS48; | |
3436 | else | |
3437 | dcfg |= DCFG_DEVSPD_FS; | |
38e9002b VM |
3438 | break; |
3439 | default: | |
79c3b5bb VA |
3440 | dcfg |= DCFG_DEVSPD_HS; |
3441 | } | |
38e9002b | 3442 | |
b43ebc96 GT |
3443 | if (hsotg->params.ipg_isoc_en) |
3444 | dcfg |= DCFG_IPG_ISOC_SUPPORDED; | |
3445 | ||
f25c42b8 | 3446 | dwc2_writel(hsotg, dcfg, DCFG); |
308d734e LM |
3447 | |
3448 | /* Clear any pending OTG interrupts */ | |
f25c42b8 | 3449 | dwc2_writel(hsotg, 0xffffffff, GOTGINT); |
308d734e LM |
3450 | |
3451 | /* Clear any pending interrupts */ | |
f25c42b8 | 3452 | dwc2_writel(hsotg, 0xffffffff, GINTSTS); |
1ee6903b | 3453 | intmsk = GINTSTS_ERLYSUSP | GINTSTS_SESSREQINT | |
47a1685f | 3454 | GINTSTS_GOUTNAKEFF | GINTSTS_GINNAKEFF | |
1ee6903b GH |
3455 | GINTSTS_USBRST | GINTSTS_RESETDET | |
3456 | GINTSTS_ENUMDONE | GINTSTS_OTGINT | | |
376f0401 SA |
3457 | GINTSTS_USBSUSP | GINTSTS_WKUPINT | |
3458 | GINTSTS_LPMTRANRCVD; | |
f4736701 VA |
3459 | |
3460 | if (!using_desc_dma(hsotg)) | |
3461 | intmsk |= GINTSTS_INCOMPL_SOIN | GINTSTS_INCOMPL_SOOUT; | |
1ee6903b | 3462 | |
95832c00 | 3463 | if (!hsotg->params.external_id_pin_ctl) |
1ee6903b GH |
3464 | intmsk |= GINTSTS_CONIDSTSCHNG; |
3465 | ||
f25c42b8 | 3466 | dwc2_writel(hsotg, intmsk, GINTMSK); |
308d734e | 3467 | |
a5c18f11 | 3468 | if (using_dma(hsotg)) { |
f25c42b8 | 3469 | dwc2_writel(hsotg, GAHBCFG_GLBL_INTR_EN | GAHBCFG_DMA_EN | |
d1ac8c80 | 3470 | hsotg->params.ahbcfg, |
f25c42b8 | 3471 | GAHBCFG); |
a5c18f11 VA |
3472 | |
3473 | /* Set DDMA mode support in the core if needed */ | |
3474 | if (using_desc_dma(hsotg)) | |
f25c42b8 | 3475 | dwc2_set_bit(hsotg, DCFG, DCFG_DESCDMA_EN); |
a5c18f11 VA |
3476 | |
3477 | } else { | |
f25c42b8 | 3478 | dwc2_writel(hsotg, ((hsotg->dedicated_fifos) ? |
95c8bc36 AS |
3479 | (GAHBCFG_NP_TXF_EMP_LVL | |
3480 | GAHBCFG_P_TXF_EMP_LVL) : 0) | | |
f25c42b8 | 3481 | GAHBCFG_GLBL_INTR_EN, GAHBCFG); |
a5c18f11 | 3482 | } |
308d734e LM |
3483 | |
3484 | /* | |
8acc8296 RB |
3485 | * If INTknTXFEmpMsk is enabled, it's important to disable ep interrupts |
3486 | * when we have no data to transfer. Otherwise we get being flooded by | |
3487 | * interrupts. | |
308d734e LM |
3488 | */ |
3489 | ||
f25c42b8 | 3490 | dwc2_writel(hsotg, ((hsotg->dedicated_fifos && !using_dma(hsotg)) ? |
6ff2e832 | 3491 | DIEPMSK_TXFIFOEMPTY | DIEPMSK_INTKNTXFEMPMSK : 0) | |
47a1685f | 3492 | DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK | |
837e9f00 | 3493 | DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK, |
f25c42b8 | 3494 | DIEPMSK); |
308d734e LM |
3495 | |
3496 | /* | |
3497 | * don't need XferCompl, we get that from RXFIFO in slave mode. In | |
9d9a6b07 | 3498 | * DMA mode we may need this and StsPhseRcvd. |
308d734e | 3499 | */ |
f25c42b8 | 3500 | dwc2_writel(hsotg, (using_dma(hsotg) ? (DIEPMSK_XFERCOMPLMSK | |
9d9a6b07 | 3501 | DOEPMSK_STSPHSERCVDMSK) : 0) | |
47a1685f | 3502 | DOEPMSK_EPDISBLDMSK | DOEPMSK_AHBERRMSK | |
9d9a6b07 | 3503 | DOEPMSK_SETUPMSK, |
f25c42b8 | 3504 | DOEPMSK); |
308d734e | 3505 | |
ec01f0b2 | 3506 | /* Enable BNA interrupt for DDMA */ |
37981e00 | 3507 | if (using_desc_dma(hsotg)) { |
f25c42b8 GS |
3508 | dwc2_set_bit(hsotg, DOEPMSK, DOEPMSK_BNAMSK); |
3509 | dwc2_set_bit(hsotg, DIEPMSK, DIEPMSK_BNAININTRMSK); | |
37981e00 | 3510 | } |
ec01f0b2 | 3511 | |
ca531bc2 GT |
3512 | /* Enable Service Interval mode if supported */ |
3513 | if (using_desc_dma(hsotg) && hsotg->params.service_interval) | |
3514 | dwc2_set_bit(hsotg, DCTL, DCTL_SERVICE_INTERVAL_SUPPORTED); | |
3515 | ||
f25c42b8 | 3516 | dwc2_writel(hsotg, 0, DAINTMSK); |
308d734e LM |
3517 | |
3518 | dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n", | |
f25c42b8 GS |
3519 | dwc2_readl(hsotg, DIEPCTL0), |
3520 | dwc2_readl(hsotg, DOEPCTL0)); | |
308d734e LM |
3521 | |
3522 | /* enable in and out endpoint interrupts */ | |
1f91b4cc | 3523 | dwc2_hsotg_en_gsint(hsotg, GINTSTS_OEPINT | GINTSTS_IEPINT); |
308d734e LM |
3524 | |
3525 | /* | |
3526 | * Enable the RXFIFO when in slave mode, as this is how we collect | |
3527 | * the data. In DMA mode, we get events from the FIFO but also | |
3528 | * things we cannot process, so do not use it. | |
3529 | */ | |
3530 | if (!using_dma(hsotg)) | |
1f91b4cc | 3531 | dwc2_hsotg_en_gsint(hsotg, GINTSTS_RXFLVL); |
308d734e LM |
3532 | |
3533 | /* Enable interrupts for EP0 in and out */ | |
1f91b4cc FB |
3534 | dwc2_hsotg_ctrl_epint(hsotg, 0, 0, 1); |
3535 | dwc2_hsotg_ctrl_epint(hsotg, 0, 1, 1); | |
308d734e | 3536 | |
643cc4de | 3537 | if (!is_usb_reset) { |
f25c42b8 | 3538 | dwc2_set_bit(hsotg, DCTL, DCTL_PWRONPRGDONE); |
643cc4de | 3539 | udelay(10); /* see openiboot */ |
f25c42b8 | 3540 | dwc2_clear_bit(hsotg, DCTL, DCTL_PWRONPRGDONE); |
643cc4de | 3541 | } |
308d734e | 3542 | |
f25c42b8 | 3543 | dev_dbg(hsotg->dev, "DCTL=0x%08x\n", dwc2_readl(hsotg, DCTL)); |
308d734e LM |
3544 | |
3545 | /* | |
94cb8fd6 | 3546 | * DxEPCTL_USBActEp says RO in manual, but seems to be set by |
308d734e LM |
3547 | * writing to the EPCTL register.. |
3548 | */ | |
3549 | ||
3550 | /* set to read 1 8byte packet */ | |
f25c42b8 GS |
3551 | dwc2_writel(hsotg, DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) | |
3552 | DXEPTSIZ_XFERSIZE(8), DOEPTSIZ0); | |
308d734e | 3553 | |
f25c42b8 | 3554 | dwc2_writel(hsotg, dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) | |
47a1685f DN |
3555 | DXEPCTL_CNAK | DXEPCTL_EPENA | |
3556 | DXEPCTL_USBACTEP, | |
f25c42b8 | 3557 | DOEPCTL0); |
308d734e LM |
3558 | |
3559 | /* enable, but don't activate EP0in */ | |
f25c42b8 GS |
3560 | dwc2_writel(hsotg, dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) | |
3561 | DXEPCTL_USBACTEP, DIEPCTL0); | |
308d734e | 3562 | |
308d734e | 3563 | /* clear global NAKs */ |
643cc4de GH |
3564 | val = DCTL_CGOUTNAK | DCTL_CGNPINNAK; |
3565 | if (!is_usb_reset) | |
3566 | val |= DCTL_SFTDISCON; | |
f25c42b8 | 3567 | dwc2_set_bit(hsotg, DCTL, val); |
308d734e | 3568 | |
21b03405 SA |
3569 | /* configure the core to support LPM */ |
3570 | dwc2_gadget_init_lpm(hsotg); | |
3571 | ||
15d9dbf8 GT |
3572 | /* program GREFCLK register if needed */ |
3573 | if (using_desc_dma(hsotg) && hsotg->params.service_interval) | |
3574 | dwc2_gadget_program_ref_clk(hsotg); | |
3575 | ||
308d734e LM |
3576 | /* must be at-least 3ms to allow bus to see disconnect */ |
3577 | mdelay(3); | |
3578 | ||
065d3931 | 3579 | hsotg->lx_state = DWC2_L0; |
755d7395 VM |
3580 | |
3581 | dwc2_hsotg_enqueue_setup(hsotg); | |
3582 | ||
3583 | dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n", | |
f25c42b8 GS |
3584 | dwc2_readl(hsotg, DIEPCTL0), |
3585 | dwc2_readl(hsotg, DOEPCTL0)); | |
ad38dc5d MS |
3586 | } |
3587 | ||
17f93402 | 3588 | void dwc2_hsotg_core_disconnect(struct dwc2_hsotg *hsotg) |
ad38dc5d MS |
3589 | { |
3590 | /* set the soft-disconnect bit */ | |
f25c42b8 | 3591 | dwc2_set_bit(hsotg, DCTL, DCTL_SFTDISCON); |
ad38dc5d | 3592 | } |
ac3c81f3 | 3593 | |
1f91b4cc | 3594 | void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg) |
ad38dc5d | 3595 | { |
308d734e | 3596 | /* remove the soft-disconnect and let's go */ |
db638c65 AD |
3597 | if (!hsotg->role_sw || (dwc2_readl(hsotg, GOTGCTL) & GOTGCTL_BSESVLD)) |
3598 | dwc2_clear_bit(hsotg, DCTL, DCTL_SFTDISCON); | |
308d734e LM |
3599 | } |
3600 | ||
381fc8f8 VM |
3601 | /** |
3602 | * dwc2_gadget_handle_incomplete_isoc_in - handle incomplete ISO IN Interrupt. | |
3603 | * @hsotg: The device state: | |
3604 | * | |
3605 | * This interrupt indicates one of the following conditions occurred while | |
3606 | * transmitting an ISOC transaction. | |
3607 | * - Corrupted IN Token for ISOC EP. | |
3608 | * - Packet not complete in FIFO. | |
3609 | * | |
3610 | * The following actions will be taken: | |
3611 | * - Determine the EP | |
3612 | * - Disable EP; when 'Endpoint Disabled' interrupt is received Flush FIFO | |
3613 | */ | |
3614 | static void dwc2_gadget_handle_incomplete_isoc_in(struct dwc2_hsotg *hsotg) | |
3615 | { | |
3616 | struct dwc2_hsotg_ep *hs_ep; | |
3617 | u32 epctrl; | |
1b4977c7 | 3618 | u32 daintmsk; |
381fc8f8 VM |
3619 | u32 idx; |
3620 | ||
3621 | dev_dbg(hsotg->dev, "Incomplete isoc in interrupt received:\n"); | |
3622 | ||
f25c42b8 | 3623 | daintmsk = dwc2_readl(hsotg, DAINTMSK); |
1b4977c7 | 3624 | |
d5d5f079 | 3625 | for (idx = 1; idx < hsotg->num_of_eps; idx++) { |
381fc8f8 | 3626 | hs_ep = hsotg->eps_in[idx]; |
1b4977c7 | 3627 | /* Proceed only unmasked ISOC EPs */ |
89066b36 | 3628 | if ((BIT(idx) & ~daintmsk) || !hs_ep->isochronous) |
1b4977c7 RK |
3629 | continue; |
3630 | ||
f25c42b8 | 3631 | epctrl = dwc2_readl(hsotg, DIEPCTL(idx)); |
1b4977c7 | 3632 | if ((epctrl & DXEPCTL_EPENA) && |
381fc8f8 VM |
3633 | dwc2_gadget_target_frame_elapsed(hs_ep)) { |
3634 | epctrl |= DXEPCTL_SNAK; | |
3635 | epctrl |= DXEPCTL_EPDIS; | |
f25c42b8 | 3636 | dwc2_writel(hsotg, epctrl, DIEPCTL(idx)); |
381fc8f8 VM |
3637 | } |
3638 | } | |
3639 | ||
3640 | /* Clear interrupt */ | |
f25c42b8 | 3641 | dwc2_writel(hsotg, GINTSTS_INCOMPL_SOIN, GINTSTS); |
381fc8f8 VM |
3642 | } |
3643 | ||
3644 | /** | |
3645 | * dwc2_gadget_handle_incomplete_isoc_out - handle incomplete ISO OUT Interrupt | |
3646 | * @hsotg: The device state: | |
3647 | * | |
3648 | * This interrupt indicates one of the following conditions occurred while | |
3649 | * transmitting an ISOC transaction. | |
3650 | * - Corrupted OUT Token for ISOC EP. | |
3651 | * - Packet not complete in FIFO. | |
3652 | * | |
3653 | * The following actions will be taken: | |
3654 | * - Determine the EP | |
3655 | * - Set DCTL_SGOUTNAK and unmask GOUTNAKEFF if target frame elapsed. | |
3656 | */ | |
3657 | static void dwc2_gadget_handle_incomplete_isoc_out(struct dwc2_hsotg *hsotg) | |
3658 | { | |
3659 | u32 gintsts; | |
3660 | u32 gintmsk; | |
689efb26 | 3661 | u32 daintmsk; |
381fc8f8 VM |
3662 | u32 epctrl; |
3663 | struct dwc2_hsotg_ep *hs_ep; | |
3664 | int idx; | |
3665 | ||
3666 | dev_dbg(hsotg->dev, "%s: GINTSTS_INCOMPL_SOOUT\n", __func__); | |
3667 | ||
f25c42b8 | 3668 | daintmsk = dwc2_readl(hsotg, DAINTMSK); |
689efb26 RK |
3669 | daintmsk >>= DAINT_OUTEP_SHIFT; |
3670 | ||
d5d5f079 | 3671 | for (idx = 1; idx < hsotg->num_of_eps; idx++) { |
381fc8f8 | 3672 | hs_ep = hsotg->eps_out[idx]; |
689efb26 | 3673 | /* Proceed only unmasked ISOC EPs */ |
89066b36 | 3674 | if ((BIT(idx) & ~daintmsk) || !hs_ep->isochronous) |
689efb26 RK |
3675 | continue; |
3676 | ||
f25c42b8 | 3677 | epctrl = dwc2_readl(hsotg, DOEPCTL(idx)); |
689efb26 | 3678 | if ((epctrl & DXEPCTL_EPENA) && |
381fc8f8 VM |
3679 | dwc2_gadget_target_frame_elapsed(hs_ep)) { |
3680 | /* Unmask GOUTNAKEFF interrupt */ | |
f25c42b8 | 3681 | gintmsk = dwc2_readl(hsotg, GINTMSK); |
381fc8f8 | 3682 | gintmsk |= GINTSTS_GOUTNAKEFF; |
f25c42b8 | 3683 | dwc2_writel(hsotg, gintmsk, GINTMSK); |
381fc8f8 | 3684 | |
f25c42b8 | 3685 | gintsts = dwc2_readl(hsotg, GINTSTS); |
689efb26 | 3686 | if (!(gintsts & GINTSTS_GOUTNAKEFF)) { |
f25c42b8 | 3687 | dwc2_set_bit(hsotg, DCTL, DCTL_SGOUTNAK); |
689efb26 RK |
3688 | break; |
3689 | } | |
381fc8f8 VM |
3690 | } |
3691 | } | |
3692 | ||
3693 | /* Clear interrupt */ | |
f25c42b8 | 3694 | dwc2_writel(hsotg, GINTSTS_INCOMPL_SOOUT, GINTSTS); |
381fc8f8 VM |
3695 | } |
3696 | ||
5b7d70c6 | 3697 | /** |
1f91b4cc | 3698 | * dwc2_hsotg_irq - handle device interrupt |
5b7d70c6 BD |
3699 | * @irq: The IRQ number triggered |
3700 | * @pw: The pw value when registered the handler. | |
3701 | */ | |
1f91b4cc | 3702 | static irqreturn_t dwc2_hsotg_irq(int irq, void *pw) |
5b7d70c6 | 3703 | { |
941fcce4 | 3704 | struct dwc2_hsotg *hsotg = pw; |
5b7d70c6 BD |
3705 | int retry_count = 8; |
3706 | u32 gintsts; | |
3707 | u32 gintmsk; | |
3708 | ||
ee3de8d7 VM |
3709 | if (!dwc2_is_device_mode(hsotg)) |
3710 | return IRQ_NONE; | |
3711 | ||
5ad1d316 | 3712 | spin_lock(&hsotg->lock); |
5b7d70c6 | 3713 | irq_retry: |
f25c42b8 GS |
3714 | gintsts = dwc2_readl(hsotg, GINTSTS); |
3715 | gintmsk = dwc2_readl(hsotg, GINTMSK); | |
5b7d70c6 BD |
3716 | |
3717 | dev_dbg(hsotg->dev, "%s: %08x %08x (%08x) retry %d\n", | |
3718 | __func__, gintsts, gintsts & gintmsk, gintmsk, retry_count); | |
3719 | ||
3720 | gintsts &= gintmsk; | |
3721 | ||
8fc37b82 MYK |
3722 | if (gintsts & GINTSTS_RESETDET) { |
3723 | dev_dbg(hsotg->dev, "%s: USBRstDet\n", __func__); | |
3724 | ||
f25c42b8 | 3725 | dwc2_writel(hsotg, GINTSTS_RESETDET, GINTSTS); |
8fc37b82 MYK |
3726 | |
3727 | /* This event must be used only if controller is suspended */ | |
c9c394ab AP |
3728 | if (hsotg->in_ppd && hsotg->lx_state == DWC2_L2) |
3729 | dwc2_exit_partial_power_down(hsotg, 0, true); | |
3730 | ||
3731 | hsotg->lx_state = DWC2_L0; | |
8fc37b82 MYK |
3732 | } |
3733 | ||
3734 | if (gintsts & (GINTSTS_USBRST | GINTSTS_RESETDET)) { | |
f25c42b8 | 3735 | u32 usb_status = dwc2_readl(hsotg, GOTGCTL); |
8fc37b82 MYK |
3736 | u32 connected = hsotg->connected; |
3737 | ||
3738 | dev_dbg(hsotg->dev, "%s: USBRst\n", __func__); | |
3739 | dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n", | |
f25c42b8 | 3740 | dwc2_readl(hsotg, GNPTXSTS)); |
8fc37b82 | 3741 | |
f25c42b8 | 3742 | dwc2_writel(hsotg, GINTSTS_USBRST, GINTSTS); |
8fc37b82 MYK |
3743 | |
3744 | /* Report disconnection if it is not already done. */ | |
3745 | dwc2_hsotg_disconnect(hsotg); | |
3746 | ||
307bc11f | 3747 | /* Reset device address to zero */ |
f25c42b8 | 3748 | dwc2_clear_bit(hsotg, DCFG, DCFG_DEVADDR_MASK); |
307bc11f | 3749 | |
8fc37b82 MYK |
3750 | if (usb_status & GOTGCTL_BSESVLD && connected) |
3751 | dwc2_hsotg_core_init_disconnected(hsotg, true); | |
3752 | } | |
3753 | ||
47a1685f | 3754 | if (gintsts & GINTSTS_ENUMDONE) { |
f25c42b8 | 3755 | dwc2_writel(hsotg, GINTSTS_ENUMDONE, GINTSTS); |
a3395f0d | 3756 | |
1f91b4cc | 3757 | dwc2_hsotg_irq_enumdone(hsotg); |
5b7d70c6 BD |
3758 | } |
3759 | ||
47a1685f | 3760 | if (gintsts & (GINTSTS_OEPINT | GINTSTS_IEPINT)) { |
f25c42b8 GS |
3761 | u32 daint = dwc2_readl(hsotg, DAINT); |
3762 | u32 daintmsk = dwc2_readl(hsotg, DAINTMSK); | |
7e804650 | 3763 | u32 daint_out, daint_in; |
5b7d70c6 BD |
3764 | int ep; |
3765 | ||
7e804650 | 3766 | daint &= daintmsk; |
47a1685f DN |
3767 | daint_out = daint >> DAINT_OUTEP_SHIFT; |
3768 | daint_in = daint & ~(daint_out << DAINT_OUTEP_SHIFT); | |
7e804650 | 3769 | |
5b7d70c6 BD |
3770 | dev_dbg(hsotg->dev, "%s: daint=%08x\n", __func__, daint); |
3771 | ||
cec87f1d MYK |
3772 | for (ep = 0; ep < hsotg->num_of_eps && daint_out; |
3773 | ep++, daint_out >>= 1) { | |
5b7d70c6 | 3774 | if (daint_out & 1) |
1f91b4cc | 3775 | dwc2_hsotg_epint(hsotg, ep, 0); |
5b7d70c6 BD |
3776 | } |
3777 | ||
cec87f1d MYK |
3778 | for (ep = 0; ep < hsotg->num_of_eps && daint_in; |
3779 | ep++, daint_in >>= 1) { | |
5b7d70c6 | 3780 | if (daint_in & 1) |
1f91b4cc | 3781 | dwc2_hsotg_epint(hsotg, ep, 1); |
5b7d70c6 | 3782 | } |
5b7d70c6 BD |
3783 | } |
3784 | ||
5b7d70c6 BD |
3785 | /* check both FIFOs */ |
3786 | ||
47a1685f | 3787 | if (gintsts & GINTSTS_NPTXFEMP) { |
5b7d70c6 BD |
3788 | dev_dbg(hsotg->dev, "NPTxFEmp\n"); |
3789 | ||
8b9bc460 LM |
3790 | /* |
3791 | * Disable the interrupt to stop it happening again | |
5b7d70c6 | 3792 | * unless one of these endpoint routines decides that |
8b9bc460 LM |
3793 | * it needs re-enabling |
3794 | */ | |
5b7d70c6 | 3795 | |
1f91b4cc FB |
3796 | dwc2_hsotg_disable_gsint(hsotg, GINTSTS_NPTXFEMP); |
3797 | dwc2_hsotg_irq_fifoempty(hsotg, false); | |
5b7d70c6 BD |
3798 | } |
3799 | ||
47a1685f | 3800 | if (gintsts & GINTSTS_PTXFEMP) { |
5b7d70c6 BD |
3801 | dev_dbg(hsotg->dev, "PTxFEmp\n"); |
3802 | ||
94cb8fd6 | 3803 | /* See note in GINTSTS_NPTxFEmp */ |
5b7d70c6 | 3804 | |
1f91b4cc FB |
3805 | dwc2_hsotg_disable_gsint(hsotg, GINTSTS_PTXFEMP); |
3806 | dwc2_hsotg_irq_fifoempty(hsotg, true); | |
5b7d70c6 BD |
3807 | } |
3808 | ||
47a1685f | 3809 | if (gintsts & GINTSTS_RXFLVL) { |
8b9bc460 LM |
3810 | /* |
3811 | * note, since GINTSTS_RxFLvl doubles as FIFO-not-empty, | |
1f91b4cc | 3812 | * we need to retry dwc2_hsotg_handle_rx if this is still |
8b9bc460 LM |
3813 | * set. |
3814 | */ | |
5b7d70c6 | 3815 | |
1f91b4cc | 3816 | dwc2_hsotg_handle_rx(hsotg); |
5b7d70c6 BD |
3817 | } |
3818 | ||
47a1685f | 3819 | if (gintsts & GINTSTS_ERLYSUSP) { |
94cb8fd6 | 3820 | dev_dbg(hsotg->dev, "GINTSTS_ErlySusp\n"); |
f25c42b8 | 3821 | dwc2_writel(hsotg, GINTSTS_ERLYSUSP, GINTSTS); |
5b7d70c6 BD |
3822 | } |
3823 | ||
8b9bc460 LM |
3824 | /* |
3825 | * these next two seem to crop-up occasionally causing the core | |
5b7d70c6 | 3826 | * to shutdown the USB transfer, so try clearing them and logging |
8b9bc460 LM |
3827 | * the occurrence. |
3828 | */ | |
5b7d70c6 | 3829 | |
47a1685f | 3830 | if (gintsts & GINTSTS_GOUTNAKEFF) { |
837e9f00 VM |
3831 | u8 idx; |
3832 | u32 epctrl; | |
3833 | u32 gintmsk; | |
d8484552 | 3834 | u32 daintmsk; |
837e9f00 VM |
3835 | struct dwc2_hsotg_ep *hs_ep; |
3836 | ||
f25c42b8 | 3837 | daintmsk = dwc2_readl(hsotg, DAINTMSK); |
d8484552 | 3838 | daintmsk >>= DAINT_OUTEP_SHIFT; |
837e9f00 | 3839 | /* Mask this interrupt */ |
f25c42b8 | 3840 | gintmsk = dwc2_readl(hsotg, GINTMSK); |
837e9f00 | 3841 | gintmsk &= ~GINTSTS_GOUTNAKEFF; |
f25c42b8 | 3842 | dwc2_writel(hsotg, gintmsk, GINTMSK); |
837e9f00 VM |
3843 | |
3844 | dev_dbg(hsotg->dev, "GOUTNakEff triggered\n"); | |
d5d5f079 | 3845 | for (idx = 1; idx < hsotg->num_of_eps; idx++) { |
837e9f00 | 3846 | hs_ep = hsotg->eps_out[idx]; |
d8484552 | 3847 | /* Proceed only unmasked ISOC EPs */ |
6070636c | 3848 | if (BIT(idx) & ~daintmsk) |
d8484552 RK |
3849 | continue; |
3850 | ||
f25c42b8 | 3851 | epctrl = dwc2_readl(hsotg, DOEPCTL(idx)); |
837e9f00 | 3852 | |
6070636c MH |
3853 | //ISOC Ep's only |
3854 | if ((epctrl & DXEPCTL_EPENA) && hs_ep->isochronous) { | |
837e9f00 VM |
3855 | epctrl |= DXEPCTL_SNAK; |
3856 | epctrl |= DXEPCTL_EPDIS; | |
f25c42b8 | 3857 | dwc2_writel(hsotg, epctrl, DOEPCTL(idx)); |
6070636c MH |
3858 | continue; |
3859 | } | |
3860 | ||
3861 | //Non-ISOC EP's | |
3862 | if (hs_ep->halted) { | |
3863 | if (!(epctrl & DXEPCTL_EPENA)) | |
3864 | epctrl |= DXEPCTL_EPENA; | |
3865 | epctrl |= DXEPCTL_EPDIS; | |
3866 | epctrl |= DXEPCTL_STALL; | |
3867 | dwc2_writel(hsotg, epctrl, DOEPCTL(idx)); | |
837e9f00 VM |
3868 | } |
3869 | } | |
a3395f0d | 3870 | |
837e9f00 | 3871 | /* This interrupt bit is cleared in DXEPINT_EPDISBLD handler */ |
5b7d70c6 BD |
3872 | } |
3873 | ||
47a1685f | 3874 | if (gintsts & GINTSTS_GINNAKEFF) { |
5b7d70c6 BD |
3875 | dev_info(hsotg->dev, "GINNakEff triggered\n"); |
3876 | ||
f25c42b8 | 3877 | dwc2_set_bit(hsotg, DCTL, DCTL_CGNPINNAK); |
a3395f0d | 3878 | |
1f91b4cc | 3879 | dwc2_hsotg_dump(hsotg); |
5b7d70c6 BD |
3880 | } |
3881 | ||
381fc8f8 VM |
3882 | if (gintsts & GINTSTS_INCOMPL_SOIN) |
3883 | dwc2_gadget_handle_incomplete_isoc_in(hsotg); | |
ec1f9d9f | 3884 | |
381fc8f8 VM |
3885 | if (gintsts & GINTSTS_INCOMPL_SOOUT) |
3886 | dwc2_gadget_handle_incomplete_isoc_out(hsotg); | |
ec1f9d9f | 3887 | |
8b9bc460 LM |
3888 | /* |
3889 | * if we've had fifo events, we should try and go around the | |
3890 | * loop again to see if there's any point in returning yet. | |
3891 | */ | |
5b7d70c6 BD |
3892 | |
3893 | if (gintsts & IRQ_RETRY_MASK && --retry_count > 0) | |
77b6200e | 3894 | goto irq_retry; |
5b7d70c6 | 3895 | |
187c5298 GT |
3896 | /* Check WKUP_ALERT interrupt*/ |
3897 | if (hsotg->params.service_interval) | |
3898 | dwc2_gadget_wkup_alert_handler(hsotg); | |
3899 | ||
5ad1d316 LM |
3900 | spin_unlock(&hsotg->lock); |
3901 | ||
5b7d70c6 BD |
3902 | return IRQ_HANDLED; |
3903 | } | |
3904 | ||
a4f82771 VA |
3905 | static void dwc2_hsotg_ep_stop_xfr(struct dwc2_hsotg *hsotg, |
3906 | struct dwc2_hsotg_ep *hs_ep) | |
3907 | { | |
3908 | u32 epctrl_reg; | |
3909 | u32 epint_reg; | |
3910 | ||
3911 | epctrl_reg = hs_ep->dir_in ? DIEPCTL(hs_ep->index) : | |
3912 | DOEPCTL(hs_ep->index); | |
3913 | epint_reg = hs_ep->dir_in ? DIEPINT(hs_ep->index) : | |
3914 | DOEPINT(hs_ep->index); | |
3915 | ||
3916 | dev_dbg(hsotg->dev, "%s: stopping transfer on %s\n", __func__, | |
3917 | hs_ep->name); | |
3918 | ||
3919 | if (hs_ep->dir_in) { | |
3920 | if (hsotg->dedicated_fifos || hs_ep->periodic) { | |
f25c42b8 | 3921 | dwc2_set_bit(hsotg, epctrl_reg, DXEPCTL_SNAK); |
a4f82771 VA |
3922 | /* Wait for Nak effect */ |
3923 | if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg, | |
3924 | DXEPINT_INEPNAKEFF, 100)) | |
3925 | dev_warn(hsotg->dev, | |
3926 | "%s: timeout DIEPINT.NAKEFF\n", | |
3927 | __func__); | |
3928 | } else { | |
f25c42b8 | 3929 | dwc2_set_bit(hsotg, DCTL, DCTL_SGNPINNAK); |
a4f82771 VA |
3930 | /* Wait for Nak effect */ |
3931 | if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS, | |
3932 | GINTSTS_GINNAKEFF, 100)) | |
3933 | dev_warn(hsotg->dev, | |
3934 | "%s: timeout GINTSTS.GINNAKEFF\n", | |
3935 | __func__); | |
3936 | } | |
3937 | } else { | |
fecb3a17 MH |
3938 | /* Mask GINTSTS_GOUTNAKEFF interrupt */ |
3939 | dwc2_hsotg_disable_gsint(hsotg, GINTSTS_GOUTNAKEFF); | |
3940 | ||
f25c42b8 GS |
3941 | if (!(dwc2_readl(hsotg, GINTSTS) & GINTSTS_GOUTNAKEFF)) |
3942 | dwc2_set_bit(hsotg, DCTL, DCTL_SGOUTNAK); | |
a4f82771 | 3943 | |
fecb3a17 MH |
3944 | if (!using_dma(hsotg)) { |
3945 | /* Wait for GINTSTS_RXFLVL interrupt */ | |
3946 | if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS, | |
3947 | GINTSTS_RXFLVL, 100)) { | |
3948 | dev_warn(hsotg->dev, "%s: timeout GINTSTS.RXFLVL\n", | |
3949 | __func__); | |
3950 | } else { | |
3951 | /* | |
3952 | * Pop GLOBAL OUT NAK status packet from RxFIFO | |
3953 | * to assert GOUTNAKEFF interrupt | |
3954 | */ | |
3955 | dwc2_readl(hsotg, GRXSTSP); | |
3956 | } | |
3957 | } | |
3958 | ||
a4f82771 VA |
3959 | /* Wait for global nak to take effect */ |
3960 | if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS, | |
3961 | GINTSTS_GOUTNAKEFF, 100)) | |
3962 | dev_warn(hsotg->dev, "%s: timeout GINTSTS.GOUTNAKEFF\n", | |
3963 | __func__); | |
3964 | } | |
3965 | ||
3966 | /* Disable ep */ | |
f25c42b8 | 3967 | dwc2_set_bit(hsotg, epctrl_reg, DXEPCTL_EPDIS | DXEPCTL_SNAK); |
a4f82771 VA |
3968 | |
3969 | /* Wait for ep to be disabled */ | |
3970 | if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg, DXEPINT_EPDISBLD, 100)) | |
3971 | dev_warn(hsotg->dev, | |
3972 | "%s: timeout DOEPCTL.EPDisable\n", __func__); | |
3973 | ||
3974 | /* Clear EPDISBLD interrupt */ | |
f25c42b8 | 3975 | dwc2_set_bit(hsotg, epint_reg, DXEPINT_EPDISBLD); |
a4f82771 VA |
3976 | |
3977 | if (hs_ep->dir_in) { | |
3978 | unsigned short fifo_index; | |
3979 | ||
3980 | if (hsotg->dedicated_fifos || hs_ep->periodic) | |
3981 | fifo_index = hs_ep->fifo_index; | |
3982 | else | |
3983 | fifo_index = 0; | |
3984 | ||
3985 | /* Flush TX FIFO */ | |
3986 | dwc2_flush_tx_fifo(hsotg, fifo_index); | |
3987 | ||
3988 | /* Clear Global In NP NAK in Shared FIFO for non periodic ep */ | |
3989 | if (!hsotg->dedicated_fifos && !hs_ep->periodic) | |
f25c42b8 | 3990 | dwc2_set_bit(hsotg, DCTL, DCTL_CGNPINNAK); |
a4f82771 VA |
3991 | |
3992 | } else { | |
3993 | /* Remove global NAKs */ | |
f25c42b8 | 3994 | dwc2_set_bit(hsotg, DCTL, DCTL_CGOUTNAK); |
a4f82771 VA |
3995 | } |
3996 | } | |
3997 | ||
5b7d70c6 | 3998 | /** |
1f91b4cc | 3999 | * dwc2_hsotg_ep_enable - enable the given endpoint |
5b7d70c6 BD |
4000 | * @ep: The USB endpint to configure |
4001 | * @desc: The USB endpoint descriptor to configure with. | |
4002 | * | |
4003 | * This is called from the USB gadget code's usb_ep_enable(). | |
8b9bc460 | 4004 | */ |
1f91b4cc | 4005 | static int dwc2_hsotg_ep_enable(struct usb_ep *ep, |
9da51974 | 4006 | const struct usb_endpoint_descriptor *desc) |
5b7d70c6 | 4007 | { |
1f91b4cc | 4008 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 4009 | struct dwc2_hsotg *hsotg = hs_ep->parent; |
5b7d70c6 | 4010 | unsigned long flags; |
ca4c55ad | 4011 | unsigned int index = hs_ep->index; |
5b7d70c6 BD |
4012 | u32 epctrl_reg; |
4013 | u32 epctrl; | |
4014 | u32 mps; | |
ee2c40de | 4015 | u32 mc; |
837e9f00 | 4016 | u32 mask; |
ca4c55ad MYK |
4017 | unsigned int dir_in; |
4018 | unsigned int i, val, size; | |
19c190f9 | 4019 | int ret = 0; |
729cac69 | 4020 | unsigned char ep_type; |
54f37f56 | 4021 | int desc_num; |
5b7d70c6 BD |
4022 | |
4023 | dev_dbg(hsotg->dev, | |
4024 | "%s: ep %s: a 0x%02x, attr 0x%02x, mps 0x%04x, intr %d\n", | |
4025 | __func__, ep->name, desc->bEndpointAddress, desc->bmAttributes, | |
4026 | desc->wMaxPacketSize, desc->bInterval); | |
4027 | ||
4028 | /* not to be called for EP0 */ | |
8c3d6092 VA |
4029 | if (index == 0) { |
4030 | dev_err(hsotg->dev, "%s: called for EP 0\n", __func__); | |
4031 | return -EINVAL; | |
4032 | } | |
5b7d70c6 BD |
4033 | |
4034 | dir_in = (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) ? 1 : 0; | |
4035 | if (dir_in != hs_ep->dir_in) { | |
4036 | dev_err(hsotg->dev, "%s: direction mismatch!\n", __func__); | |
4037 | return -EINVAL; | |
4038 | } | |
4039 | ||
729cac69 | 4040 | ep_type = desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK; |
29cc8897 | 4041 | mps = usb_endpoint_maxp(desc); |
ee2c40de | 4042 | mc = usb_endpoint_maxp_mult(desc); |
5b7d70c6 | 4043 | |
729cac69 MH |
4044 | /* ISOC IN in DDMA supported bInterval up to 10 */ |
4045 | if (using_desc_dma(hsotg) && ep_type == USB_ENDPOINT_XFER_ISOC && | |
4046 | dir_in && desc->bInterval > 10) { | |
4047 | dev_err(hsotg->dev, | |
4048 | "%s: ISOC IN, DDMA: bInterval>10 not supported!\n", __func__); | |
4049 | return -EINVAL; | |
4050 | } | |
4051 | ||
4052 | /* High bandwidth ISOC OUT in DDMA not supported */ | |
4053 | if (using_desc_dma(hsotg) && ep_type == USB_ENDPOINT_XFER_ISOC && | |
4054 | !dir_in && mc > 1) { | |
4055 | dev_err(hsotg->dev, | |
4056 | "%s: ISOC OUT, DDMA: HB not supported!\n", __func__); | |
4057 | return -EINVAL; | |
4058 | } | |
4059 | ||
1f91b4cc | 4060 | /* note, we handle this here instead of dwc2_hsotg_set_ep_maxpacket */ |
5b7d70c6 | 4061 | |
94cb8fd6 | 4062 | epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index); |
f25c42b8 | 4063 | epctrl = dwc2_readl(hsotg, epctrl_reg); |
5b7d70c6 BD |
4064 | |
4065 | dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x from 0x%08x\n", | |
4066 | __func__, epctrl, epctrl_reg); | |
4067 | ||
54f37f56 MH |
4068 | if (using_desc_dma(hsotg) && ep_type == USB_ENDPOINT_XFER_ISOC) |
4069 | desc_num = MAX_DMA_DESC_NUM_HS_ISOC; | |
4070 | else | |
4071 | desc_num = MAX_DMA_DESC_NUM_GENERIC; | |
4072 | ||
5f54c54b | 4073 | /* Allocate DMA descriptor chain for non-ctrl endpoints */ |
9383e084 VM |
4074 | if (using_desc_dma(hsotg) && !hs_ep->desc_list) { |
4075 | hs_ep->desc_list = dmam_alloc_coherent(hsotg->dev, | |
54f37f56 | 4076 | desc_num * sizeof(struct dwc2_dma_desc), |
86e881e7 | 4077 | &hs_ep->desc_list_dma, GFP_ATOMIC); |
5f54c54b VA |
4078 | if (!hs_ep->desc_list) { |
4079 | ret = -ENOMEM; | |
4080 | goto error2; | |
4081 | } | |
4082 | } | |
4083 | ||
22258f49 | 4084 | spin_lock_irqsave(&hsotg->lock, flags); |
5b7d70c6 | 4085 | |
47a1685f DN |
4086 | epctrl &= ~(DXEPCTL_EPTYPE_MASK | DXEPCTL_MPS_MASK); |
4087 | epctrl |= DXEPCTL_MPS(mps); | |
5b7d70c6 | 4088 | |
8b9bc460 LM |
4089 | /* |
4090 | * mark the endpoint as active, otherwise the core may ignore | |
4091 | * transactions entirely for this endpoint | |
4092 | */ | |
47a1685f | 4093 | epctrl |= DXEPCTL_USBACTEP; |
5b7d70c6 | 4094 | |
5b7d70c6 | 4095 | /* update the endpoint state */ |
ee2c40de | 4096 | dwc2_hsotg_set_ep_maxpacket(hsotg, hs_ep->index, mps, mc, dir_in); |
5b7d70c6 BD |
4097 | |
4098 | /* default, set to non-periodic */ | |
1479e841 | 4099 | hs_ep->isochronous = 0; |
5b7d70c6 | 4100 | hs_ep->periodic = 0; |
a18ed7b0 | 4101 | hs_ep->halted = 0; |
b833ce15 | 4102 | hs_ep->wedged = 0; |
1479e841 | 4103 | hs_ep->interval = desc->bInterval; |
4fca54aa | 4104 | |
729cac69 | 4105 | switch (ep_type) { |
5b7d70c6 | 4106 | case USB_ENDPOINT_XFER_ISOC: |
47a1685f DN |
4107 | epctrl |= DXEPCTL_EPTYPE_ISO; |
4108 | epctrl |= DXEPCTL_SETEVENFR; | |
1479e841 | 4109 | hs_ep->isochronous = 1; |
142bd33f | 4110 | hs_ep->interval = 1 << (desc->bInterval - 1); |
837e9f00 | 4111 | hs_ep->target_frame = TARGET_FRAME_INITIAL; |
ab7d2192 | 4112 | hs_ep->next_desc = 0; |
729cac69 | 4113 | hs_ep->compl_desc = 0; |
837e9f00 | 4114 | if (dir_in) { |
1479e841 | 4115 | hs_ep->periodic = 1; |
f25c42b8 | 4116 | mask = dwc2_readl(hsotg, DIEPMSK); |
837e9f00 | 4117 | mask |= DIEPMSK_NAKMSK; |
f25c42b8 | 4118 | dwc2_writel(hsotg, mask, DIEPMSK); |
837e9f00 | 4119 | } else { |
91bb163e | 4120 | epctrl |= DXEPCTL_SNAK; |
f25c42b8 | 4121 | mask = dwc2_readl(hsotg, DOEPMSK); |
837e9f00 | 4122 | mask |= DOEPMSK_OUTTKNEPDISMSK; |
f25c42b8 | 4123 | dwc2_writel(hsotg, mask, DOEPMSK); |
837e9f00 | 4124 | } |
1479e841 | 4125 | break; |
5b7d70c6 BD |
4126 | |
4127 | case USB_ENDPOINT_XFER_BULK: | |
47a1685f | 4128 | epctrl |= DXEPCTL_EPTYPE_BULK; |
5b7d70c6 BD |
4129 | break; |
4130 | ||
4131 | case USB_ENDPOINT_XFER_INT: | |
b203d0a2 | 4132 | if (dir_in) |
5b7d70c6 | 4133 | hs_ep->periodic = 1; |
5b7d70c6 | 4134 | |
142bd33f VM |
4135 | if (hsotg->gadget.speed == USB_SPEED_HIGH) |
4136 | hs_ep->interval = 1 << (desc->bInterval - 1); | |
4137 | ||
47a1685f | 4138 | epctrl |= DXEPCTL_EPTYPE_INTERRUPT; |
5b7d70c6 BD |
4139 | break; |
4140 | ||
4141 | case USB_ENDPOINT_XFER_CONTROL: | |
47a1685f | 4142 | epctrl |= DXEPCTL_EPTYPE_CONTROL; |
5b7d70c6 BD |
4143 | break; |
4144 | } | |
4145 | ||
8b9bc460 LM |
4146 | /* |
4147 | * if the hardware has dedicated fifos, we must give each IN EP | |
10aebc77 BD |
4148 | * a unique tx-fifo even if it is non-periodic. |
4149 | */ | |
21f3bb52 | 4150 | if (dir_in && hsotg->dedicated_fifos) { |
644139f8 | 4151 | unsigned fifo_count = dwc2_hsotg_tx_fifo_count(hsotg); |
ca4c55ad MYK |
4152 | u32 fifo_index = 0; |
4153 | u32 fifo_size = UINT_MAX; | |
9da51974 JY |
4154 | |
4155 | size = hs_ep->ep.maxpacket * hs_ep->mc; | |
644139f8 | 4156 | for (i = 1; i <= fifo_count; ++i) { |
9da51974 | 4157 | if (hsotg->fifo_map & (1 << i)) |
b203d0a2 | 4158 | continue; |
f25c42b8 | 4159 | val = dwc2_readl(hsotg, DPTXFSIZN(i)); |
9da51974 | 4160 | val = (val >> FIFOSIZE_DEPTH_SHIFT) * 4; |
b203d0a2 RB |
4161 | if (val < size) |
4162 | continue; | |
ca4c55ad MYK |
4163 | /* Search for smallest acceptable fifo */ |
4164 | if (val < fifo_size) { | |
4165 | fifo_size = val; | |
4166 | fifo_index = i; | |
4167 | } | |
b203d0a2 | 4168 | } |
ca4c55ad | 4169 | if (!fifo_index) { |
5f2196bd MYK |
4170 | dev_err(hsotg->dev, |
4171 | "%s: No suitable fifo found\n", __func__); | |
b585a48b | 4172 | ret = -ENOMEM; |
5f54c54b | 4173 | goto error1; |
b585a48b | 4174 | } |
97311c8f | 4175 | epctrl &= ~(DXEPCTL_TXFNUM_LIMIT << DXEPCTL_TXFNUM_SHIFT); |
ca4c55ad MYK |
4176 | hsotg->fifo_map |= 1 << fifo_index; |
4177 | epctrl |= DXEPCTL_TXFNUM(fifo_index); | |
4178 | hs_ep->fifo_index = fifo_index; | |
4179 | hs_ep->fifo_size = fifo_size; | |
b203d0a2 | 4180 | } |
10aebc77 | 4181 | |
5b7d70c6 | 4182 | /* for non control endpoints, set PID to D0 */ |
837e9f00 | 4183 | if (index && !hs_ep->isochronous) |
47a1685f | 4184 | epctrl |= DXEPCTL_SETD0PID; |
5b7d70c6 | 4185 | |
5295322a AP |
4186 | /* WA for Full speed ISOC IN in DDMA mode. |
4187 | * By Clear NAK status of EP, core will send ZLP | |
4188 | * to IN token and assert NAK interrupt relying | |
4189 | * on TxFIFO status only | |
4190 | */ | |
4191 | ||
4192 | if (hsotg->gadget.speed == USB_SPEED_FULL && | |
4193 | hs_ep->isochronous && dir_in) { | |
4194 | /* The WA applies only to core versions from 2.72a | |
4195 | * to 4.00a (including both). Also for FS_IOT_1.00a | |
4196 | * and HS_IOT_1.00a. | |
4197 | */ | |
f25c42b8 | 4198 | u32 gsnpsid = dwc2_readl(hsotg, GSNPSID); |
5295322a AP |
4199 | |
4200 | if ((gsnpsid >= DWC2_CORE_REV_2_72a && | |
4201 | gsnpsid <= DWC2_CORE_REV_4_00a) || | |
4202 | gsnpsid == DWC2_FS_IOT_REV_1_00a || | |
4203 | gsnpsid == DWC2_HS_IOT_REV_1_00a) | |
4204 | epctrl |= DXEPCTL_CNAK; | |
4205 | } | |
4206 | ||
5b7d70c6 BD |
4207 | dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n", |
4208 | __func__, epctrl); | |
4209 | ||
f25c42b8 | 4210 | dwc2_writel(hsotg, epctrl, epctrl_reg); |
5b7d70c6 | 4211 | dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x\n", |
f25c42b8 | 4212 | __func__, dwc2_readl(hsotg, epctrl_reg)); |
5b7d70c6 BD |
4213 | |
4214 | /* enable the endpoint interrupt */ | |
1f91b4cc | 4215 | dwc2_hsotg_ctrl_epint(hsotg, index, dir_in, 1); |
5b7d70c6 | 4216 | |
5f54c54b | 4217 | error1: |
22258f49 | 4218 | spin_unlock_irqrestore(&hsotg->lock, flags); |
5f54c54b VA |
4219 | |
4220 | error2: | |
4221 | if (ret && using_desc_dma(hsotg) && hs_ep->desc_list) { | |
54f37f56 | 4222 | dmam_free_coherent(hsotg->dev, desc_num * |
5f54c54b VA |
4223 | sizeof(struct dwc2_dma_desc), |
4224 | hs_ep->desc_list, hs_ep->desc_list_dma); | |
4225 | hs_ep->desc_list = NULL; | |
4226 | } | |
4227 | ||
19c190f9 | 4228 | return ret; |
5b7d70c6 BD |
4229 | } |
4230 | ||
8b9bc460 | 4231 | /** |
1f91b4cc | 4232 | * dwc2_hsotg_ep_disable - disable given endpoint |
8b9bc460 LM |
4233 | * @ep: The endpoint to disable. |
4234 | */ | |
1f91b4cc | 4235 | static int dwc2_hsotg_ep_disable(struct usb_ep *ep) |
5b7d70c6 | 4236 | { |
1f91b4cc | 4237 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 4238 | struct dwc2_hsotg *hsotg = hs_ep->parent; |
5b7d70c6 BD |
4239 | int dir_in = hs_ep->dir_in; |
4240 | int index = hs_ep->index; | |
5b7d70c6 BD |
4241 | u32 epctrl_reg; |
4242 | u32 ctrl; | |
4243 | ||
1e011293 | 4244 | dev_dbg(hsotg->dev, "%s(ep %p)\n", __func__, ep); |
5b7d70c6 | 4245 | |
c6f5c050 | 4246 | if (ep == &hsotg->eps_out[0]->ep) { |
5b7d70c6 BD |
4247 | dev_err(hsotg->dev, "%s: called for ep0\n", __func__); |
4248 | return -EINVAL; | |
9b481092 JS |
4249 | } |
4250 | ||
4251 | if (hsotg->op_state != OTG_STATE_B_PERIPHERAL) { | |
4252 | dev_err(hsotg->dev, "%s: called in host mode?\n", __func__); | |
4253 | return -EINVAL; | |
5b7d70c6 BD |
4254 | } |
4255 | ||
94cb8fd6 | 4256 | epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index); |
5b7d70c6 | 4257 | |
f25c42b8 | 4258 | ctrl = dwc2_readl(hsotg, epctrl_reg); |
a4f82771 VA |
4259 | |
4260 | if (ctrl & DXEPCTL_EPENA) | |
4261 | dwc2_hsotg_ep_stop_xfr(hsotg, hs_ep); | |
4262 | ||
47a1685f DN |
4263 | ctrl &= ~DXEPCTL_EPENA; |
4264 | ctrl &= ~DXEPCTL_USBACTEP; | |
4265 | ctrl |= DXEPCTL_SNAK; | |
5b7d70c6 BD |
4266 | |
4267 | dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl); | |
f25c42b8 | 4268 | dwc2_writel(hsotg, ctrl, epctrl_reg); |
5b7d70c6 BD |
4269 | |
4270 | /* disable endpoint interrupts */ | |
1f91b4cc | 4271 | dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 0); |
5b7d70c6 | 4272 | |
1141ea01 MYK |
4273 | /* terminate all requests with shutdown */ |
4274 | kill_all_requests(hsotg, hs_ep, -ESHUTDOWN); | |
4275 | ||
1c07b20e RB |
4276 | hsotg->fifo_map &= ~(1 << hs_ep->fifo_index); |
4277 | hs_ep->fifo_index = 0; | |
4278 | hs_ep->fifo_size = 0; | |
4279 | ||
5b7d70c6 BD |
4280 | return 0; |
4281 | } | |
4282 | ||
4fe4f9fe MH |
4283 | static int dwc2_hsotg_ep_disable_lock(struct usb_ep *ep) |
4284 | { | |
4285 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); | |
4286 | struct dwc2_hsotg *hsotg = hs_ep->parent; | |
4287 | unsigned long flags; | |
4288 | int ret; | |
4289 | ||
4290 | spin_lock_irqsave(&hsotg->lock, flags); | |
4291 | ret = dwc2_hsotg_ep_disable(ep); | |
4292 | spin_unlock_irqrestore(&hsotg->lock, flags); | |
4293 | return ret; | |
4294 | } | |
4295 | ||
5b7d70c6 BD |
4296 | /** |
4297 | * on_list - check request is on the given endpoint | |
4298 | * @ep: The endpoint to check. | |
4299 | * @test: The request to test if it is on the endpoint. | |
8b9bc460 | 4300 | */ |
1f91b4cc | 4301 | static bool on_list(struct dwc2_hsotg_ep *ep, struct dwc2_hsotg_req *test) |
5b7d70c6 | 4302 | { |
1f91b4cc | 4303 | struct dwc2_hsotg_req *req, *treq; |
5b7d70c6 BD |
4304 | |
4305 | list_for_each_entry_safe(req, treq, &ep->queue, queue) { | |
4306 | if (req == test) | |
4307 | return true; | |
4308 | } | |
4309 | ||
4310 | return false; | |
4311 | } | |
4312 | ||
8b9bc460 | 4313 | /** |
1f91b4cc | 4314 | * dwc2_hsotg_ep_dequeue - dequeue given endpoint |
8b9bc460 LM |
4315 | * @ep: The endpoint to dequeue. |
4316 | * @req: The request to be removed from a queue. | |
4317 | */ | |
1f91b4cc | 4318 | static int dwc2_hsotg_ep_dequeue(struct usb_ep *ep, struct usb_request *req) |
5b7d70c6 | 4319 | { |
1f91b4cc FB |
4320 | struct dwc2_hsotg_req *hs_req = our_req(req); |
4321 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); | |
941fcce4 | 4322 | struct dwc2_hsotg *hs = hs_ep->parent; |
5b7d70c6 BD |
4323 | unsigned long flags; |
4324 | ||
1e011293 | 4325 | dev_dbg(hs->dev, "ep_dequeue(%p,%p)\n", ep, req); |
5b7d70c6 | 4326 | |
22258f49 | 4327 | spin_lock_irqsave(&hs->lock, flags); |
5b7d70c6 BD |
4328 | |
4329 | if (!on_list(hs_ep, hs_req)) { | |
22258f49 | 4330 | spin_unlock_irqrestore(&hs->lock, flags); |
5b7d70c6 BD |
4331 | return -EINVAL; |
4332 | } | |
4333 | ||
c524dd5f MYK |
4334 | /* Dequeue already started request */ |
4335 | if (req == &hs_ep->req->req) | |
4336 | dwc2_hsotg_ep_stop_xfr(hs, hs_ep); | |
4337 | ||
1f91b4cc | 4338 | dwc2_hsotg_complete_request(hs, hs_ep, hs_req, -ECONNRESET); |
22258f49 | 4339 | spin_unlock_irqrestore(&hs->lock, flags); |
5b7d70c6 BD |
4340 | |
4341 | return 0; | |
4342 | } | |
4343 | ||
b833ce15 MH |
4344 | /** |
4345 | * dwc2_gadget_ep_set_wedge - set wedge on a given endpoint | |
4346 | * @ep: The endpoint to be wedged. | |
4347 | * | |
4348 | */ | |
4349 | static int dwc2_gadget_ep_set_wedge(struct usb_ep *ep) | |
4350 | { | |
4351 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); | |
4352 | struct dwc2_hsotg *hs = hs_ep->parent; | |
4353 | ||
4354 | unsigned long flags; | |
4355 | int ret; | |
4356 | ||
4357 | spin_lock_irqsave(&hs->lock, flags); | |
4358 | hs_ep->wedged = 1; | |
4359 | ret = dwc2_hsotg_ep_sethalt(ep, 1, false); | |
4360 | spin_unlock_irqrestore(&hs->lock, flags); | |
4361 | ||
4362 | return ret; | |
4363 | } | |
4364 | ||
8b9bc460 | 4365 | /** |
1f91b4cc | 4366 | * dwc2_hsotg_ep_sethalt - set halt on a given endpoint |
8b9bc460 LM |
4367 | * @ep: The endpoint to set halt. |
4368 | * @value: Set or unset the halt. | |
51da43b5 VA |
4369 | * @now: If true, stall the endpoint now. Otherwise return -EAGAIN if |
4370 | * the endpoint is busy processing requests. | |
4371 | * | |
4372 | * We need to stall the endpoint immediately if request comes from set_feature | |
4373 | * protocol command handler. | |
8b9bc460 | 4374 | */ |
51da43b5 | 4375 | static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now) |
5b7d70c6 | 4376 | { |
1f91b4cc | 4377 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 4378 | struct dwc2_hsotg *hs = hs_ep->parent; |
5b7d70c6 | 4379 | int index = hs_ep->index; |
5b7d70c6 BD |
4380 | u32 epreg; |
4381 | u32 epctl; | |
9c39ddc6 | 4382 | u32 xfertype; |
5b7d70c6 BD |
4383 | |
4384 | dev_info(hs->dev, "%s(ep %p %s, %d)\n", __func__, ep, ep->name, value); | |
4385 | ||
c9f721b2 RB |
4386 | if (index == 0) { |
4387 | if (value) | |
1f91b4cc | 4388 | dwc2_hsotg_stall_ep0(hs); |
c9f721b2 RB |
4389 | else |
4390 | dev_warn(hs->dev, | |
4391 | "%s: can't clear halt on ep0\n", __func__); | |
4392 | return 0; | |
4393 | } | |
4394 | ||
15186f10 VA |
4395 | if (hs_ep->isochronous) { |
4396 | dev_err(hs->dev, "%s is Isochronous Endpoint\n", ep->name); | |
4397 | return -EINVAL; | |
4398 | } | |
4399 | ||
51da43b5 VA |
4400 | if (!now && value && !list_empty(&hs_ep->queue)) { |
4401 | dev_dbg(hs->dev, "%s request is pending, cannot halt\n", | |
4402 | ep->name); | |
4403 | return -EAGAIN; | |
4404 | } | |
4405 | ||
c6f5c050 MYK |
4406 | if (hs_ep->dir_in) { |
4407 | epreg = DIEPCTL(index); | |
f25c42b8 | 4408 | epctl = dwc2_readl(hs, epreg); |
c6f5c050 MYK |
4409 | |
4410 | if (value) { | |
5a350d53 | 4411 | epctl |= DXEPCTL_STALL | DXEPCTL_SNAK; |
c6f5c050 MYK |
4412 | if (epctl & DXEPCTL_EPENA) |
4413 | epctl |= DXEPCTL_EPDIS; | |
4414 | } else { | |
4415 | epctl &= ~DXEPCTL_STALL; | |
b833ce15 | 4416 | hs_ep->wedged = 0; |
c6f5c050 MYK |
4417 | xfertype = epctl & DXEPCTL_EPTYPE_MASK; |
4418 | if (xfertype == DXEPCTL_EPTYPE_BULK || | |
9da51974 | 4419 | xfertype == DXEPCTL_EPTYPE_INTERRUPT) |
77b6200e | 4420 | epctl |= DXEPCTL_SETD0PID; |
c6f5c050 | 4421 | } |
f25c42b8 | 4422 | dwc2_writel(hs, epctl, epreg); |
9c39ddc6 | 4423 | } else { |
c6f5c050 | 4424 | epreg = DOEPCTL(index); |
f25c42b8 | 4425 | epctl = dwc2_readl(hs, epreg); |
5b7d70c6 | 4426 | |
34c0887f | 4427 | if (value) { |
fecb3a17 MH |
4428 | /* Unmask GOUTNAKEFF interrupt */ |
4429 | dwc2_hsotg_en_gsint(hs, GINTSTS_GOUTNAKEFF); | |
4430 | ||
6070636c MH |
4431 | if (!(dwc2_readl(hs, GINTSTS) & GINTSTS_GOUTNAKEFF)) |
4432 | dwc2_set_bit(hs, DCTL, DCTL_SGOUTNAK); | |
4433 | // STALL bit will be set in GOUTNAKEFF interrupt handler | |
34c0887f | 4434 | } else { |
c6f5c050 | 4435 | epctl &= ~DXEPCTL_STALL; |
b833ce15 | 4436 | hs_ep->wedged = 0; |
c6f5c050 MYK |
4437 | xfertype = epctl & DXEPCTL_EPTYPE_MASK; |
4438 | if (xfertype == DXEPCTL_EPTYPE_BULK || | |
9da51974 | 4439 | xfertype == DXEPCTL_EPTYPE_INTERRUPT) |
77b6200e | 4440 | epctl |= DXEPCTL_SETD0PID; |
6070636c | 4441 | dwc2_writel(hs, epctl, epreg); |
c6f5c050 | 4442 | } |
9c39ddc6 | 4443 | } |
5b7d70c6 | 4444 | |
a18ed7b0 | 4445 | hs_ep->halted = value; |
5b7d70c6 BD |
4446 | return 0; |
4447 | } | |
4448 | ||
5ad1d316 | 4449 | /** |
1f91b4cc | 4450 | * dwc2_hsotg_ep_sethalt_lock - set halt on a given endpoint with lock held |
5ad1d316 LM |
4451 | * @ep: The endpoint to set halt. |
4452 | * @value: Set or unset the halt. | |
4453 | */ | |
1f91b4cc | 4454 | static int dwc2_hsotg_ep_sethalt_lock(struct usb_ep *ep, int value) |
5ad1d316 | 4455 | { |
1f91b4cc | 4456 | struct dwc2_hsotg_ep *hs_ep = our_ep(ep); |
941fcce4 | 4457 | struct dwc2_hsotg *hs = hs_ep->parent; |
8879904b JH |
4458 | unsigned long flags; |
4459 | int ret; | |
5ad1d316 LM |
4460 | |
4461 | spin_lock_irqsave(&hs->lock, flags); | |
51da43b5 | 4462 | ret = dwc2_hsotg_ep_sethalt(ep, value, false); |
5ad1d316 LM |
4463 | spin_unlock_irqrestore(&hs->lock, flags); |
4464 | ||
4465 | return ret; | |
4466 | } | |
4467 | ||
ebce561a | 4468 | static const struct usb_ep_ops dwc2_hsotg_ep_ops = { |
1f91b4cc | 4469 | .enable = dwc2_hsotg_ep_enable, |
4fe4f9fe | 4470 | .disable = dwc2_hsotg_ep_disable_lock, |
1f91b4cc FB |
4471 | .alloc_request = dwc2_hsotg_ep_alloc_request, |
4472 | .free_request = dwc2_hsotg_ep_free_request, | |
4473 | .queue = dwc2_hsotg_ep_queue_lock, | |
4474 | .dequeue = dwc2_hsotg_ep_dequeue, | |
4475 | .set_halt = dwc2_hsotg_ep_sethalt_lock, | |
b833ce15 | 4476 | .set_wedge = dwc2_gadget_ep_set_wedge, |
25985edc | 4477 | /* note, don't believe we have any call for the fifo routines */ |
5b7d70c6 BD |
4478 | }; |
4479 | ||
8b9bc460 | 4480 | /** |
9da51974 | 4481 | * dwc2_hsotg_init - initialize the usb core |
8b9bc460 LM |
4482 | * @hsotg: The driver state |
4483 | */ | |
1f91b4cc | 4484 | static void dwc2_hsotg_init(struct dwc2_hsotg *hsotg) |
b3f489b2 LM |
4485 | { |
4486 | /* unmask subset of endpoint interrupts */ | |
4487 | ||
f25c42b8 | 4488 | dwc2_writel(hsotg, DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK | |
95c8bc36 | 4489 | DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK, |
f25c42b8 | 4490 | DIEPMSK); |
b3f489b2 | 4491 | |
f25c42b8 | 4492 | dwc2_writel(hsotg, DOEPMSK_SETUPMSK | DOEPMSK_AHBERRMSK | |
95c8bc36 | 4493 | DOEPMSK_EPDISBLDMSK | DOEPMSK_XFERCOMPLMSK, |
f25c42b8 | 4494 | DOEPMSK); |
b3f489b2 | 4495 | |
f25c42b8 | 4496 | dwc2_writel(hsotg, 0, DAINTMSK); |
b3f489b2 LM |
4497 | |
4498 | /* Be in disconnected state until gadget is registered */ | |
f25c42b8 | 4499 | dwc2_set_bit(hsotg, DCTL, DCTL_SFTDISCON); |
b3f489b2 | 4500 | |
b3f489b2 LM |
4501 | /* setup fifos */ |
4502 | ||
4503 | dev_dbg(hsotg->dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n", | |
f25c42b8 GS |
4504 | dwc2_readl(hsotg, GRXFSIZ), |
4505 | dwc2_readl(hsotg, GNPTXFSIZ)); | |
b3f489b2 | 4506 | |
1f91b4cc | 4507 | dwc2_hsotg_init_fifo(hsotg); |
b3f489b2 | 4508 | |
f5090044 | 4509 | if (using_dma(hsotg)) |
f25c42b8 | 4510 | dwc2_set_bit(hsotg, GAHBCFG, GAHBCFG_DMA_EN); |
b3f489b2 LM |
4511 | } |
4512 | ||
8b9bc460 | 4513 | /** |
1f91b4cc | 4514 | * dwc2_hsotg_udc_start - prepare the udc for work |
8b9bc460 LM |
4515 | * @gadget: The usb gadget state |
4516 | * @driver: The usb gadget driver | |
4517 | * | |
4518 | * Perform initialization to prepare udc device and driver | |
4519 | * to work. | |
4520 | */ | |
1f91b4cc | 4521 | static int dwc2_hsotg_udc_start(struct usb_gadget *gadget, |
9da51974 | 4522 | struct usb_gadget_driver *driver) |
5b7d70c6 | 4523 | { |
941fcce4 | 4524 | struct dwc2_hsotg *hsotg = to_hsotg(gadget); |
5b9451f8 | 4525 | unsigned long flags; |
5b7d70c6 BD |
4526 | int ret; |
4527 | ||
4528 | if (!hsotg) { | |
a023da33 | 4529 | pr_err("%s: called with no device\n", __func__); |
5b7d70c6 BD |
4530 | return -ENODEV; |
4531 | } | |
4532 | ||
4533 | if (!driver) { | |
4534 | dev_err(hsotg->dev, "%s: no driver\n", __func__); | |
4535 | return -EINVAL; | |
4536 | } | |
4537 | ||
7177aed4 | 4538 | if (driver->max_speed < USB_SPEED_FULL) |
5b7d70c6 | 4539 | dev_err(hsotg->dev, "%s: bad speed\n", __func__); |
5b7d70c6 | 4540 | |
f65f0f10 | 4541 | if (!driver->setup) { |
5b7d70c6 BD |
4542 | dev_err(hsotg->dev, "%s: missing entry points\n", __func__); |
4543 | return -EINVAL; | |
4544 | } | |
4545 | ||
4546 | WARN_ON(hsotg->driver); | |
4547 | ||
5b7d70c6 | 4548 | hsotg->driver = driver; |
7d7b2292 | 4549 | hsotg->gadget.dev.of_node = hsotg->dev->of_node; |
5b7d70c6 BD |
4550 | hsotg->gadget.speed = USB_SPEED_UNKNOWN; |
4551 | ||
09a75e85 MS |
4552 | if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) { |
4553 | ret = dwc2_lowlevel_hw_enable(hsotg); | |
4554 | if (ret) | |
4555 | goto err; | |
5b7d70c6 BD |
4556 | } |
4557 | ||
f6c01592 GH |
4558 | if (!IS_ERR_OR_NULL(hsotg->uphy)) |
4559 | otg_set_peripheral(hsotg->uphy->otg, &hsotg->gadget); | |
c816c47f | 4560 | |
5b9451f8 | 4561 | spin_lock_irqsave(&hsotg->lock, flags); |
d0f0ac56 JY |
4562 | if (dwc2_hw_is_device(hsotg)) { |
4563 | dwc2_hsotg_init(hsotg); | |
4564 | dwc2_hsotg_core_init_disconnected(hsotg, false); | |
4565 | } | |
4566 | ||
dc6e69e6 | 4567 | hsotg->enabled = 0; |
5b9451f8 MS |
4568 | spin_unlock_irqrestore(&hsotg->lock, flags); |
4569 | ||
10209abe | 4570 | gadget->sg_supported = using_desc_dma(hsotg); |
5b7d70c6 | 4571 | dev_info(hsotg->dev, "bound driver %s\n", driver->driver.name); |
5b9451f8 | 4572 | |
5b7d70c6 BD |
4573 | return 0; |
4574 | ||
4575 | err: | |
4576 | hsotg->driver = NULL; | |
5b7d70c6 BD |
4577 | return ret; |
4578 | } | |
4579 | ||
8b9bc460 | 4580 | /** |
1f91b4cc | 4581 | * dwc2_hsotg_udc_stop - stop the udc |
8b9bc460 | 4582 | * @gadget: The usb gadget state |
8b9bc460 LM |
4583 | * |
4584 | * Stop udc hw block and stay tunned for future transmissions | |
4585 | */ | |
1f91b4cc | 4586 | static int dwc2_hsotg_udc_stop(struct usb_gadget *gadget) |
5b7d70c6 | 4587 | { |
941fcce4 | 4588 | struct dwc2_hsotg *hsotg = to_hsotg(gadget); |
8879904b | 4589 | unsigned long flags; |
5b7d70c6 BD |
4590 | int ep; |
4591 | ||
4592 | if (!hsotg) | |
4593 | return -ENODEV; | |
4594 | ||
5b7d70c6 | 4595 | /* all endpoints should be shutdown */ |
c6f5c050 MYK |
4596 | for (ep = 1; ep < hsotg->num_of_eps; ep++) { |
4597 | if (hsotg->eps_in[ep]) | |
4fe4f9fe | 4598 | dwc2_hsotg_ep_disable_lock(&hsotg->eps_in[ep]->ep); |
c6f5c050 | 4599 | if (hsotg->eps_out[ep]) |
4fe4f9fe | 4600 | dwc2_hsotg_ep_disable_lock(&hsotg->eps_out[ep]->ep); |
c6f5c050 | 4601 | } |
5b7d70c6 | 4602 | |
2b19a52c LM |
4603 | spin_lock_irqsave(&hsotg->lock, flags); |
4604 | ||
32805c35 | 4605 | hsotg->driver = NULL; |
5b7d70c6 | 4606 | hsotg->gadget.speed = USB_SPEED_UNKNOWN; |
dc6e69e6 | 4607 | hsotg->enabled = 0; |
5b7d70c6 | 4608 | |
2b19a52c LM |
4609 | spin_unlock_irqrestore(&hsotg->lock, flags); |
4610 | ||
f6c01592 GH |
4611 | if (!IS_ERR_OR_NULL(hsotg->uphy)) |
4612 | otg_set_peripheral(hsotg->uphy->otg, NULL); | |
c816c47f | 4613 | |
09a75e85 MS |
4614 | if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) |
4615 | dwc2_lowlevel_hw_disable(hsotg); | |
5b7d70c6 BD |
4616 | |
4617 | return 0; | |
4618 | } | |
5b7d70c6 | 4619 | |
8b9bc460 | 4620 | /** |
1f91b4cc | 4621 | * dwc2_hsotg_gadget_getframe - read the frame number |
8b9bc460 LM |
4622 | * @gadget: The usb gadget state |
4623 | * | |
4624 | * Read the {micro} frame number | |
4625 | */ | |
1f91b4cc | 4626 | static int dwc2_hsotg_gadget_getframe(struct usb_gadget *gadget) |
5b7d70c6 | 4627 | { |
1f91b4cc | 4628 | return dwc2_hsotg_read_frameno(to_hsotg(gadget)); |
5b7d70c6 BD |
4629 | } |
4630 | ||
1a0808cb JK |
4631 | /** |
4632 | * dwc2_hsotg_set_selfpowered - set if device is self/bus powered | |
4633 | * @gadget: The usb gadget state | |
4634 | * @is_selfpowered: Whether the device is self-powered | |
4635 | * | |
4636 | * Set if the device is self or bus powered. | |
4637 | */ | |
4638 | static int dwc2_hsotg_set_selfpowered(struct usb_gadget *gadget, | |
4639 | int is_selfpowered) | |
4640 | { | |
4641 | struct dwc2_hsotg *hsotg = to_hsotg(gadget); | |
4642 | unsigned long flags; | |
4643 | ||
4644 | spin_lock_irqsave(&hsotg->lock, flags); | |
4645 | gadget->is_selfpowered = !!is_selfpowered; | |
4646 | spin_unlock_irqrestore(&hsotg->lock, flags); | |
4647 | ||
4648 | return 0; | |
4649 | } | |
4650 | ||
a188b689 | 4651 | /** |
1f91b4cc | 4652 | * dwc2_hsotg_pullup - connect/disconnect the USB PHY |
a188b689 LM |
4653 | * @gadget: The usb gadget state |
4654 | * @is_on: Current state of the USB PHY | |
4655 | * | |
4656 | * Connect/Disconnect the USB PHY pullup | |
4657 | */ | |
1f91b4cc | 4658 | static int dwc2_hsotg_pullup(struct usb_gadget *gadget, int is_on) |
a188b689 | 4659 | { |
941fcce4 | 4660 | struct dwc2_hsotg *hsotg = to_hsotg(gadget); |
8879904b | 4661 | unsigned long flags; |
a188b689 | 4662 | |
77ba9119 | 4663 | dev_dbg(hsotg->dev, "%s: is_on: %d op_state: %d\n", __func__, is_on, |
9da51974 | 4664 | hsotg->op_state); |
77ba9119 GH |
4665 | |
4666 | /* Don't modify pullup state while in host mode */ | |
4667 | if (hsotg->op_state != OTG_STATE_B_PERIPHERAL) { | |
4668 | hsotg->enabled = is_on; | |
4669 | return 0; | |
4670 | } | |
a188b689 LM |
4671 | |
4672 | spin_lock_irqsave(&hsotg->lock, flags); | |
4673 | if (is_on) { | |
dc6e69e6 | 4674 | hsotg->enabled = 1; |
1f91b4cc | 4675 | dwc2_hsotg_core_init_disconnected(hsotg, false); |
66e77a24 RK |
4676 | /* Enable ACG feature in device mode,if supported */ |
4677 | dwc2_enable_acg(hsotg); | |
1f91b4cc | 4678 | dwc2_hsotg_core_connect(hsotg); |
a188b689 | 4679 | } else { |
1f91b4cc FB |
4680 | dwc2_hsotg_core_disconnect(hsotg); |
4681 | dwc2_hsotg_disconnect(hsotg); | |
dc6e69e6 | 4682 | hsotg->enabled = 0; |
a188b689 LM |
4683 | } |
4684 | ||
4685 | hsotg->gadget.speed = USB_SPEED_UNKNOWN; | |
4686 | spin_unlock_irqrestore(&hsotg->lock, flags); | |
4687 | ||
4688 | return 0; | |
4689 | } | |
4690 | ||
1f91b4cc | 4691 | static int dwc2_hsotg_vbus_session(struct usb_gadget *gadget, int is_active) |
83d98223 GH |
4692 | { |
4693 | struct dwc2_hsotg *hsotg = to_hsotg(gadget); | |
4694 | unsigned long flags; | |
4695 | ||
4696 | dev_dbg(hsotg->dev, "%s: is_active: %d\n", __func__, is_active); | |
4697 | spin_lock_irqsave(&hsotg->lock, flags); | |
4698 | ||
61f7223b | 4699 | /* |
c9c394ab AP |
4700 | * If controller is in partial power down state, it must exit from |
4701 | * that state before being initialized / de-initialized | |
61f7223b | 4702 | */ |
c9c394ab AP |
4703 | if (hsotg->lx_state == DWC2_L2 && hsotg->in_ppd) |
4704 | /* | |
4705 | * No need to check the return value as | |
4706 | * registers are not being restored. | |
4707 | */ | |
4708 | dwc2_exit_partial_power_down(hsotg, 0, false); | |
61f7223b | 4709 | |
83d98223 | 4710 | if (is_active) { |
cd0e641c | 4711 | hsotg->op_state = OTG_STATE_B_PERIPHERAL; |
065d3931 | 4712 | |
1f91b4cc | 4713 | dwc2_hsotg_core_init_disconnected(hsotg, false); |
66e77a24 RK |
4714 | if (hsotg->enabled) { |
4715 | /* Enable ACG feature in device mode,if supported */ | |
4716 | dwc2_enable_acg(hsotg); | |
1f91b4cc | 4717 | dwc2_hsotg_core_connect(hsotg); |
66e77a24 | 4718 | } |
83d98223 | 4719 | } else { |
1f91b4cc FB |
4720 | dwc2_hsotg_core_disconnect(hsotg); |
4721 | dwc2_hsotg_disconnect(hsotg); | |
83d98223 GH |
4722 | } |
4723 | ||
4724 | spin_unlock_irqrestore(&hsotg->lock, flags); | |
4725 | return 0; | |
4726 | } | |
4727 | ||
596d696a | 4728 | /** |
1f91b4cc | 4729 | * dwc2_hsotg_vbus_draw - report bMaxPower field |
596d696a GH |
4730 | * @gadget: The usb gadget state |
4731 | * @mA: Amount of current | |
4732 | * | |
4733 | * Report how much power the device may consume to the phy. | |
4734 | */ | |
9da51974 | 4735 | static int dwc2_hsotg_vbus_draw(struct usb_gadget *gadget, unsigned int mA) |
596d696a GH |
4736 | { |
4737 | struct dwc2_hsotg *hsotg = to_hsotg(gadget); | |
4738 | ||
4739 | if (IS_ERR_OR_NULL(hsotg->uphy)) | |
4740 | return -ENOTSUPP; | |
4741 | return usb_phy_set_power(hsotg->uphy, mA); | |
4742 | } | |
4743 | ||
5324bad6 AA |
4744 | static void dwc2_gadget_set_speed(struct usb_gadget *g, enum usb_device_speed speed) |
4745 | { | |
4746 | struct dwc2_hsotg *hsotg = to_hsotg(g); | |
4747 | unsigned long flags; | |
4748 | ||
4749 | spin_lock_irqsave(&hsotg->lock, flags); | |
4750 | switch (speed) { | |
4751 | case USB_SPEED_HIGH: | |
4752 | hsotg->params.speed = DWC2_SPEED_PARAM_HIGH; | |
4753 | break; | |
4754 | case USB_SPEED_FULL: | |
4755 | hsotg->params.speed = DWC2_SPEED_PARAM_FULL; | |
4756 | break; | |
4757 | case USB_SPEED_LOW: | |
4758 | hsotg->params.speed = DWC2_SPEED_PARAM_LOW; | |
4759 | break; | |
4760 | default: | |
4761 | dev_err(hsotg->dev, "invalid speed (%d)\n", speed); | |
4762 | } | |
4763 | spin_unlock_irqrestore(&hsotg->lock, flags); | |
4764 | } | |
4765 | ||
1f91b4cc FB |
4766 | static const struct usb_gadget_ops dwc2_hsotg_gadget_ops = { |
4767 | .get_frame = dwc2_hsotg_gadget_getframe, | |
1a0808cb | 4768 | .set_selfpowered = dwc2_hsotg_set_selfpowered, |
1f91b4cc FB |
4769 | .udc_start = dwc2_hsotg_udc_start, |
4770 | .udc_stop = dwc2_hsotg_udc_stop, | |
4771 | .pullup = dwc2_hsotg_pullup, | |
5324bad6 | 4772 | .udc_set_speed = dwc2_gadget_set_speed, |
1f91b4cc FB |
4773 | .vbus_session = dwc2_hsotg_vbus_session, |
4774 | .vbus_draw = dwc2_hsotg_vbus_draw, | |
5b7d70c6 BD |
4775 | }; |
4776 | ||
4777 | /** | |
1f91b4cc | 4778 | * dwc2_hsotg_initep - initialise a single endpoint |
5b7d70c6 BD |
4779 | * @hsotg: The device state. |
4780 | * @hs_ep: The endpoint to be initialised. | |
4781 | * @epnum: The endpoint number | |
6fb914d7 | 4782 | * @dir_in: True if direction is in. |
5b7d70c6 BD |
4783 | * |
4784 | * Initialise the given endpoint (as part of the probe and device state | |
4785 | * creation) to give to the gadget driver. Setup the endpoint name, any | |
4786 | * direction information and other state that may be required. | |
4787 | */ | |
1f91b4cc | 4788 | static void dwc2_hsotg_initep(struct dwc2_hsotg *hsotg, |
9da51974 | 4789 | struct dwc2_hsotg_ep *hs_ep, |
c6f5c050 MYK |
4790 | int epnum, |
4791 | bool dir_in) | |
5b7d70c6 | 4792 | { |
5b7d70c6 BD |
4793 | char *dir; |
4794 | ||
4795 | if (epnum == 0) | |
4796 | dir = ""; | |
c6f5c050 | 4797 | else if (dir_in) |
5b7d70c6 | 4798 | dir = "in"; |
c6f5c050 MYK |
4799 | else |
4800 | dir = "out"; | |
5b7d70c6 | 4801 | |
c6f5c050 | 4802 | hs_ep->dir_in = dir_in; |
5b7d70c6 BD |
4803 | hs_ep->index = epnum; |
4804 | ||
4805 | snprintf(hs_ep->name, sizeof(hs_ep->name), "ep%d%s", epnum, dir); | |
4806 | ||
4807 | INIT_LIST_HEAD(&hs_ep->queue); | |
4808 | INIT_LIST_HEAD(&hs_ep->ep.ep_list); | |
4809 | ||
5b7d70c6 BD |
4810 | /* add to the list of endpoints known by the gadget driver */ |
4811 | if (epnum) | |
4812 | list_add_tail(&hs_ep->ep.ep_list, &hsotg->gadget.ep_list); | |
4813 | ||
4814 | hs_ep->parent = hsotg; | |
4815 | hs_ep->ep.name = hs_ep->name; | |
38e9002b VM |
4816 | |
4817 | if (hsotg->params.speed == DWC2_SPEED_PARAM_LOW) | |
4818 | usb_ep_set_maxpacket_limit(&hs_ep->ep, 8); | |
4819 | else | |
4820 | usb_ep_set_maxpacket_limit(&hs_ep->ep, | |
4821 | epnum ? 1024 : EP0_MPS_LIMIT); | |
1f91b4cc | 4822 | hs_ep->ep.ops = &dwc2_hsotg_ep_ops; |
5b7d70c6 | 4823 | |
2954522f RB |
4824 | if (epnum == 0) { |
4825 | hs_ep->ep.caps.type_control = true; | |
4826 | } else { | |
38e9002b VM |
4827 | if (hsotg->params.speed != DWC2_SPEED_PARAM_LOW) { |
4828 | hs_ep->ep.caps.type_iso = true; | |
4829 | hs_ep->ep.caps.type_bulk = true; | |
4830 | } | |
2954522f RB |
4831 | hs_ep->ep.caps.type_int = true; |
4832 | } | |
4833 | ||
4834 | if (dir_in) | |
4835 | hs_ep->ep.caps.dir_in = true; | |
4836 | else | |
4837 | hs_ep->ep.caps.dir_out = true; | |
4838 | ||
8b9bc460 LM |
4839 | /* |
4840 | * if we're using dma, we need to set the next-endpoint pointer | |
5b7d70c6 BD |
4841 | * to be something valid. |
4842 | */ | |
4843 | ||
4844 | if (using_dma(hsotg)) { | |
47a1685f | 4845 | u32 next = DXEPCTL_NEXTEP((epnum + 1) % 15); |
9da51974 | 4846 | |
c6f5c050 | 4847 | if (dir_in) |
f25c42b8 | 4848 | dwc2_writel(hsotg, next, DIEPCTL(epnum)); |
c6f5c050 | 4849 | else |
f25c42b8 | 4850 | dwc2_writel(hsotg, next, DOEPCTL(epnum)); |
5b7d70c6 BD |
4851 | } |
4852 | } | |
4853 | ||
b3f489b2 | 4854 | /** |
1f91b4cc | 4855 | * dwc2_hsotg_hw_cfg - read HW configuration registers |
6fb914d7 | 4856 | * @hsotg: Programming view of the DWC_otg controller |
b3f489b2 LM |
4857 | * |
4858 | * Read the USB core HW configuration registers | |
4859 | */ | |
1f91b4cc | 4860 | static int dwc2_hsotg_hw_cfg(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 4861 | { |
c6f5c050 MYK |
4862 | u32 cfg; |
4863 | u32 ep_type; | |
4864 | u32 i; | |
4865 | ||
b3f489b2 | 4866 | /* check hardware configuration */ |
5b7d70c6 | 4867 | |
43e90349 JY |
4868 | hsotg->num_of_eps = hsotg->hw_params.num_dev_ep; |
4869 | ||
c6f5c050 MYK |
4870 | /* Add ep0 */ |
4871 | hsotg->num_of_eps++; | |
10aebc77 | 4872 | |
b98866c2 JY |
4873 | hsotg->eps_in[0] = devm_kzalloc(hsotg->dev, |
4874 | sizeof(struct dwc2_hsotg_ep), | |
4875 | GFP_KERNEL); | |
c6f5c050 MYK |
4876 | if (!hsotg->eps_in[0]) |
4877 | return -ENOMEM; | |
1f91b4cc | 4878 | /* Same dwc2_hsotg_ep is used in both directions for ep0 */ |
c6f5c050 MYK |
4879 | hsotg->eps_out[0] = hsotg->eps_in[0]; |
4880 | ||
43e90349 | 4881 | cfg = hsotg->hw_params.dev_ep_dirs; |
251a17f5 | 4882 | for (i = 1, cfg >>= 2; i < hsotg->num_of_eps; i++, cfg >>= 2) { |
c6f5c050 MYK |
4883 | ep_type = cfg & 3; |
4884 | /* Direction in or both */ | |
4885 | if (!(ep_type & 2)) { | |
4886 | hsotg->eps_in[i] = devm_kzalloc(hsotg->dev, | |
1f91b4cc | 4887 | sizeof(struct dwc2_hsotg_ep), GFP_KERNEL); |
c6f5c050 MYK |
4888 | if (!hsotg->eps_in[i]) |
4889 | return -ENOMEM; | |
4890 | } | |
4891 | /* Direction out or both */ | |
4892 | if (!(ep_type & 1)) { | |
4893 | hsotg->eps_out[i] = devm_kzalloc(hsotg->dev, | |
1f91b4cc | 4894 | sizeof(struct dwc2_hsotg_ep), GFP_KERNEL); |
c6f5c050 MYK |
4895 | if (!hsotg->eps_out[i]) |
4896 | return -ENOMEM; | |
4897 | } | |
4898 | } | |
4899 | ||
43e90349 JY |
4900 | hsotg->fifo_mem = hsotg->hw_params.total_fifo_size; |
4901 | hsotg->dedicated_fifos = hsotg->hw_params.en_multiple_tx_fifo; | |
10aebc77 | 4902 | |
cff9eb75 MS |
4903 | dev_info(hsotg->dev, "EPs: %d, %s fifos, %d entries in SPRAM\n", |
4904 | hsotg->num_of_eps, | |
4905 | hsotg->dedicated_fifos ? "dedicated" : "shared", | |
4906 | hsotg->fifo_mem); | |
c6f5c050 | 4907 | return 0; |
5b7d70c6 BD |
4908 | } |
4909 | ||
8b9bc460 | 4910 | /** |
1f91b4cc | 4911 | * dwc2_hsotg_dump - dump state of the udc |
6fb914d7 GT |
4912 | * @hsotg: Programming view of the DWC_otg controller |
4913 | * | |
8b9bc460 | 4914 | */ |
1f91b4cc | 4915 | static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 4916 | { |
83a01804 | 4917 | #ifdef DEBUG |
5b7d70c6 | 4918 | struct device *dev = hsotg->dev; |
5b7d70c6 BD |
4919 | u32 val; |
4920 | int idx; | |
4921 | ||
4922 | dev_info(dev, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n", | |
f25c42b8 GS |
4923 | dwc2_readl(hsotg, DCFG), dwc2_readl(hsotg, DCTL), |
4924 | dwc2_readl(hsotg, DIEPMSK)); | |
5b7d70c6 | 4925 | |
f889f23d | 4926 | dev_info(dev, "GAHBCFG=0x%08x, GHWCFG1=0x%08x\n", |
f25c42b8 | 4927 | dwc2_readl(hsotg, GAHBCFG), dwc2_readl(hsotg, GHWCFG1)); |
5b7d70c6 BD |
4928 | |
4929 | dev_info(dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n", | |
f25c42b8 | 4930 | dwc2_readl(hsotg, GRXFSIZ), dwc2_readl(hsotg, GNPTXFSIZ)); |
5b7d70c6 BD |
4931 | |
4932 | /* show periodic fifo settings */ | |
4933 | ||
364f8e93 | 4934 | for (idx = 1; idx < hsotg->num_of_eps; idx++) { |
f25c42b8 | 4935 | val = dwc2_readl(hsotg, DPTXFSIZN(idx)); |
5b7d70c6 | 4936 | dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx, |
47a1685f DN |
4937 | val >> FIFOSIZE_DEPTH_SHIFT, |
4938 | val & FIFOSIZE_STARTADDR_MASK); | |
5b7d70c6 BD |
4939 | } |
4940 | ||
364f8e93 | 4941 | for (idx = 0; idx < hsotg->num_of_eps; idx++) { |
5b7d70c6 BD |
4942 | dev_info(dev, |
4943 | "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx, | |
f25c42b8 GS |
4944 | dwc2_readl(hsotg, DIEPCTL(idx)), |
4945 | dwc2_readl(hsotg, DIEPTSIZ(idx)), | |
4946 | dwc2_readl(hsotg, DIEPDMA(idx))); | |
5b7d70c6 | 4947 | |
f25c42b8 | 4948 | val = dwc2_readl(hsotg, DOEPCTL(idx)); |
5b7d70c6 BD |
4949 | dev_info(dev, |
4950 | "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", | |
f25c42b8 GS |
4951 | idx, dwc2_readl(hsotg, DOEPCTL(idx)), |
4952 | dwc2_readl(hsotg, DOEPTSIZ(idx)), | |
4953 | dwc2_readl(hsotg, DOEPDMA(idx))); | |
5b7d70c6 BD |
4954 | } |
4955 | ||
4956 | dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n", | |
f25c42b8 | 4957 | dwc2_readl(hsotg, DVBUSDIS), dwc2_readl(hsotg, DVBUSPULSE)); |
83a01804 | 4958 | #endif |
5b7d70c6 BD |
4959 | } |
4960 | ||
8b9bc460 | 4961 | /** |
117777b2 | 4962 | * dwc2_gadget_init - init function for gadget |
6fb914d7 GT |
4963 | * @hsotg: Programming view of the DWC_otg controller |
4964 | * | |
8b9bc460 | 4965 | */ |
f3768997 | 4966 | int dwc2_gadget_init(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 4967 | { |
117777b2 | 4968 | struct device *dev = hsotg->dev; |
5b7d70c6 BD |
4969 | int epnum; |
4970 | int ret; | |
43e90349 | 4971 | |
0a176279 GH |
4972 | /* Dump fifo information */ |
4973 | dev_dbg(dev, "NonPeriodic TXFIFO size: %d\n", | |
05ee799f JY |
4974 | hsotg->params.g_np_tx_fifo_size); |
4975 | dev_dbg(dev, "RXFIFO size: %d\n", hsotg->params.g_rx_fifo_size); | |
5b7d70c6 | 4976 | |
92ef98a4 JK |
4977 | switch (hsotg->params.speed) { |
4978 | case DWC2_SPEED_PARAM_LOW: | |
4979 | hsotg->gadget.max_speed = USB_SPEED_LOW; | |
4980 | break; | |
4981 | case DWC2_SPEED_PARAM_FULL: | |
4982 | hsotg->gadget.max_speed = USB_SPEED_FULL; | |
4983 | break; | |
4984 | default: | |
4985 | hsotg->gadget.max_speed = USB_SPEED_HIGH; | |
4986 | break; | |
4987 | } | |
4988 | ||
1f91b4cc | 4989 | hsotg->gadget.ops = &dwc2_hsotg_gadget_ops; |
5b7d70c6 | 4990 | hsotg->gadget.name = dev_name(dev); |
f5c8a6cb | 4991 | hsotg->gadget.otg_caps = &hsotg->params.otg_caps; |
fa389a6d | 4992 | hsotg->remote_wakeup_allowed = 0; |
7455f8b7 JY |
4993 | |
4994 | if (hsotg->params.lpm) | |
4995 | hsotg->gadget.lpm_capable = true; | |
4996 | ||
097ee662 GH |
4997 | if (hsotg->dr_mode == USB_DR_MODE_OTG) |
4998 | hsotg->gadget.is_otg = 1; | |
ec4cc657 MYK |
4999 | else if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) |
5000 | hsotg->op_state = OTG_STATE_B_PERIPHERAL; | |
5b7d70c6 | 5001 | |
1f91b4cc | 5002 | ret = dwc2_hsotg_hw_cfg(hsotg); |
c6f5c050 MYK |
5003 | if (ret) { |
5004 | dev_err(hsotg->dev, "Hardware configuration failed: %d\n", ret); | |
09a75e85 | 5005 | return ret; |
c6f5c050 MYK |
5006 | } |
5007 | ||
3f95001d MYK |
5008 | hsotg->ctrl_buff = devm_kzalloc(hsotg->dev, |
5009 | DWC2_CTRL_BUFF_SIZE, GFP_KERNEL); | |
8bae0f8c | 5010 | if (!hsotg->ctrl_buff) |
09a75e85 | 5011 | return -ENOMEM; |
3f95001d MYK |
5012 | |
5013 | hsotg->ep0_buff = devm_kzalloc(hsotg->dev, | |
5014 | DWC2_CTRL_BUFF_SIZE, GFP_KERNEL); | |
8bae0f8c | 5015 | if (!hsotg->ep0_buff) |
09a75e85 | 5016 | return -ENOMEM; |
3f95001d | 5017 | |
0f6b80c0 VA |
5018 | if (using_desc_dma(hsotg)) { |
5019 | ret = dwc2_gadget_alloc_ctrl_desc_chains(hsotg); | |
5020 | if (ret < 0) | |
5021 | return ret; | |
5022 | } | |
5023 | ||
f3768997 VM |
5024 | ret = devm_request_irq(hsotg->dev, hsotg->irq, dwc2_hsotg_irq, |
5025 | IRQF_SHARED, dev_name(hsotg->dev), hsotg); | |
eb3c56c5 | 5026 | if (ret < 0) { |
db8178c3 | 5027 | dev_err(dev, "cannot claim IRQ for gadget\n"); |
09a75e85 | 5028 | return ret; |
eb3c56c5 MS |
5029 | } |
5030 | ||
b3f489b2 LM |
5031 | /* hsotg->num_of_eps holds number of EPs other than ep0 */ |
5032 | ||
5033 | if (hsotg->num_of_eps == 0) { | |
5034 | dev_err(dev, "wrong number of EPs (zero)\n"); | |
09a75e85 | 5035 | return -EINVAL; |
b3f489b2 LM |
5036 | } |
5037 | ||
b3f489b2 LM |
5038 | /* setup endpoint information */ |
5039 | ||
5040 | INIT_LIST_HEAD(&hsotg->gadget.ep_list); | |
c6f5c050 | 5041 | hsotg->gadget.ep0 = &hsotg->eps_out[0]->ep; |
b3f489b2 LM |
5042 | |
5043 | /* allocate EP0 request */ | |
5044 | ||
1f91b4cc | 5045 | hsotg->ctrl_req = dwc2_hsotg_ep_alloc_request(&hsotg->eps_out[0]->ep, |
b3f489b2 LM |
5046 | GFP_KERNEL); |
5047 | if (!hsotg->ctrl_req) { | |
5048 | dev_err(dev, "failed to allocate ctrl req\n"); | |
09a75e85 | 5049 | return -ENOMEM; |
b3f489b2 | 5050 | } |
5b7d70c6 BD |
5051 | |
5052 | /* initialise the endpoints now the core has been initialised */ | |
c6f5c050 MYK |
5053 | for (epnum = 0; epnum < hsotg->num_of_eps; epnum++) { |
5054 | if (hsotg->eps_in[epnum]) | |
1f91b4cc | 5055 | dwc2_hsotg_initep(hsotg, hsotg->eps_in[epnum], |
9da51974 | 5056 | epnum, 1); |
c6f5c050 | 5057 | if (hsotg->eps_out[epnum]) |
1f91b4cc | 5058 | dwc2_hsotg_initep(hsotg, hsotg->eps_out[epnum], |
9da51974 | 5059 | epnum, 0); |
c6f5c050 | 5060 | } |
5b7d70c6 | 5061 | |
1f91b4cc | 5062 | dwc2_hsotg_dump(hsotg); |
5b7d70c6 | 5063 | |
5b7d70c6 | 5064 | return 0; |
5b7d70c6 BD |
5065 | } |
5066 | ||
8b9bc460 | 5067 | /** |
1f91b4cc | 5068 | * dwc2_hsotg_remove - remove function for hsotg driver |
6fb914d7 GT |
5069 | * @hsotg: Programming view of the DWC_otg controller |
5070 | * | |
8b9bc460 | 5071 | */ |
1f91b4cc | 5072 | int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg) |
5b7d70c6 | 5073 | { |
0f91349b | 5074 | usb_del_gadget_udc(&hsotg->gadget); |
9bb073a0 | 5075 | dwc2_hsotg_ep_free_request(&hsotg->eps_out[0]->ep, hsotg->ctrl_req); |
31ee04de | 5076 | |
5b7d70c6 BD |
5077 | return 0; |
5078 | } | |
5079 | ||
1f91b4cc | 5080 | int dwc2_hsotg_suspend(struct dwc2_hsotg *hsotg) |
b83e333a | 5081 | { |
b83e333a | 5082 | unsigned long flags; |
b83e333a | 5083 | |
9e779778 | 5084 | if (hsotg->lx_state != DWC2_L0) |
09a75e85 | 5085 | return 0; |
9e779778 | 5086 | |
dc6e69e6 MS |
5087 | if (hsotg->driver) { |
5088 | int ep; | |
5089 | ||
b83e333a MS |
5090 | dev_info(hsotg->dev, "suspending usb gadget %s\n", |
5091 | hsotg->driver->driver.name); | |
5092 | ||
dc6e69e6 MS |
5093 | spin_lock_irqsave(&hsotg->lock, flags); |
5094 | if (hsotg->enabled) | |
1f91b4cc FB |
5095 | dwc2_hsotg_core_disconnect(hsotg); |
5096 | dwc2_hsotg_disconnect(hsotg); | |
dc6e69e6 MS |
5097 | hsotg->gadget.speed = USB_SPEED_UNKNOWN; |
5098 | spin_unlock_irqrestore(&hsotg->lock, flags); | |
b83e333a | 5099 | |
ac55d163 | 5100 | for (ep = 1; ep < hsotg->num_of_eps; ep++) { |
c6f5c050 | 5101 | if (hsotg->eps_in[ep]) |
4fe4f9fe | 5102 | dwc2_hsotg_ep_disable_lock(&hsotg->eps_in[ep]->ep); |
c6f5c050 | 5103 | if (hsotg->eps_out[ep]) |
4fe4f9fe | 5104 | dwc2_hsotg_ep_disable_lock(&hsotg->eps_out[ep]->ep); |
c6f5c050 | 5105 | } |
b83e333a MS |
5106 | } |
5107 | ||
09a75e85 | 5108 | return 0; |
b83e333a MS |
5109 | } |
5110 | ||
1f91b4cc | 5111 | int dwc2_hsotg_resume(struct dwc2_hsotg *hsotg) |
b83e333a | 5112 | { |
b83e333a | 5113 | unsigned long flags; |
b83e333a | 5114 | |
9e779778 | 5115 | if (hsotg->lx_state == DWC2_L2) |
09a75e85 | 5116 | return 0; |
9e779778 | 5117 | |
b83e333a MS |
5118 | if (hsotg->driver) { |
5119 | dev_info(hsotg->dev, "resuming usb gadget %s\n", | |
5120 | hsotg->driver->driver.name); | |
d00b4142 | 5121 | |
dc6e69e6 | 5122 | spin_lock_irqsave(&hsotg->lock, flags); |
1f91b4cc | 5123 | dwc2_hsotg_core_init_disconnected(hsotg, false); |
66e77a24 RK |
5124 | if (hsotg->enabled) { |
5125 | /* Enable ACG feature in device mode,if supported */ | |
5126 | dwc2_enable_acg(hsotg); | |
1f91b4cc | 5127 | dwc2_hsotg_core_connect(hsotg); |
66e77a24 | 5128 | } |
dc6e69e6 MS |
5129 | spin_unlock_irqrestore(&hsotg->lock, flags); |
5130 | } | |
b83e333a | 5131 | |
09a75e85 | 5132 | return 0; |
b83e333a | 5133 | } |
58e52ff6 JY |
5134 | |
5135 | /** | |
5136 | * dwc2_backup_device_registers() - Backup controller device registers. | |
5137 | * When suspending usb bus, registers needs to be backuped | |
5138 | * if controller power is disabled once suspended. | |
5139 | * | |
5140 | * @hsotg: Programming view of the DWC_otg controller | |
5141 | */ | |
5142 | int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg) | |
5143 | { | |
5144 | struct dwc2_dregs_backup *dr; | |
5145 | int i; | |
5146 | ||
5147 | dev_dbg(hsotg->dev, "%s\n", __func__); | |
5148 | ||
5149 | /* Backup dev regs */ | |
5150 | dr = &hsotg->dr_backup; | |
5151 | ||
f25c42b8 GS |
5152 | dr->dcfg = dwc2_readl(hsotg, DCFG); |
5153 | dr->dctl = dwc2_readl(hsotg, DCTL); | |
5154 | dr->daintmsk = dwc2_readl(hsotg, DAINTMSK); | |
5155 | dr->diepmsk = dwc2_readl(hsotg, DIEPMSK); | |
5156 | dr->doepmsk = dwc2_readl(hsotg, DOEPMSK); | |
58e52ff6 JY |
5157 | |
5158 | for (i = 0; i < hsotg->num_of_eps; i++) { | |
5159 | /* Backup IN EPs */ | |
f25c42b8 | 5160 | dr->diepctl[i] = dwc2_readl(hsotg, DIEPCTL(i)); |
58e52ff6 JY |
5161 | |
5162 | /* Ensure DATA PID is correctly configured */ | |
5163 | if (dr->diepctl[i] & DXEPCTL_DPID) | |
5164 | dr->diepctl[i] |= DXEPCTL_SETD1PID; | |
5165 | else | |
5166 | dr->diepctl[i] |= DXEPCTL_SETD0PID; | |
5167 | ||
f25c42b8 GS |
5168 | dr->dieptsiz[i] = dwc2_readl(hsotg, DIEPTSIZ(i)); |
5169 | dr->diepdma[i] = dwc2_readl(hsotg, DIEPDMA(i)); | |
58e52ff6 JY |
5170 | |
5171 | /* Backup OUT EPs */ | |
f25c42b8 | 5172 | dr->doepctl[i] = dwc2_readl(hsotg, DOEPCTL(i)); |
58e52ff6 JY |
5173 | |
5174 | /* Ensure DATA PID is correctly configured */ | |
5175 | if (dr->doepctl[i] & DXEPCTL_DPID) | |
5176 | dr->doepctl[i] |= DXEPCTL_SETD1PID; | |
5177 | else | |
5178 | dr->doepctl[i] |= DXEPCTL_SETD0PID; | |
5179 | ||
f25c42b8 GS |
5180 | dr->doeptsiz[i] = dwc2_readl(hsotg, DOEPTSIZ(i)); |
5181 | dr->doepdma[i] = dwc2_readl(hsotg, DOEPDMA(i)); | |
5182 | dr->dtxfsiz[i] = dwc2_readl(hsotg, DPTXFSIZN(i)); | |
58e52ff6 JY |
5183 | } |
5184 | dr->valid = true; | |
5185 | return 0; | |
5186 | } | |
5187 | ||
5188 | /** | |
5189 | * dwc2_restore_device_registers() - Restore controller device registers. | |
5190 | * When resuming usb bus, device registers needs to be restored | |
5191 | * if controller power were disabled. | |
5192 | * | |
5193 | * @hsotg: Programming view of the DWC_otg controller | |
9a5d2816 VM |
5194 | * @remote_wakeup: Indicates whether resume is initiated by Device or Host. |
5195 | * | |
5196 | * Return: 0 if successful, negative error code otherwise | |
58e52ff6 | 5197 | */ |
9a5d2816 | 5198 | int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg, int remote_wakeup) |
58e52ff6 JY |
5199 | { |
5200 | struct dwc2_dregs_backup *dr; | |
58e52ff6 JY |
5201 | int i; |
5202 | ||
5203 | dev_dbg(hsotg->dev, "%s\n", __func__); | |
5204 | ||
5205 | /* Restore dev regs */ | |
5206 | dr = &hsotg->dr_backup; | |
5207 | if (!dr->valid) { | |
5208 | dev_err(hsotg->dev, "%s: no device registers to restore\n", | |
5209 | __func__); | |
5210 | return -EINVAL; | |
5211 | } | |
5212 | dr->valid = false; | |
5213 | ||
9a5d2816 | 5214 | if (!remote_wakeup) |
f25c42b8 | 5215 | dwc2_writel(hsotg, dr->dctl, DCTL); |
9a5d2816 | 5216 | |
f25c42b8 GS |
5217 | dwc2_writel(hsotg, dr->daintmsk, DAINTMSK); |
5218 | dwc2_writel(hsotg, dr->diepmsk, DIEPMSK); | |
5219 | dwc2_writel(hsotg, dr->doepmsk, DOEPMSK); | |
58e52ff6 JY |
5220 | |
5221 | for (i = 0; i < hsotg->num_of_eps; i++) { | |
5222 | /* Restore IN EPs */ | |
f25c42b8 GS |
5223 | dwc2_writel(hsotg, dr->dieptsiz[i], DIEPTSIZ(i)); |
5224 | dwc2_writel(hsotg, dr->diepdma[i], DIEPDMA(i)); | |
5225 | dwc2_writel(hsotg, dr->doeptsiz[i], DOEPTSIZ(i)); | |
9a5d2816 VM |
5226 | /** WA for enabled EPx's IN in DDMA mode. On entering to |
5227 | * hibernation wrong value read and saved from DIEPDMAx, | |
5228 | * as result BNA interrupt asserted on hibernation exit | |
5229 | * by restoring from saved area. | |
5230 | */ | |
c4bc515d | 5231 | if (using_desc_dma(hsotg) && |
9a5d2816 VM |
5232 | (dr->diepctl[i] & DXEPCTL_EPENA)) |
5233 | dr->diepdma[i] = hsotg->eps_in[i]->desc_list_dma; | |
f25c42b8 GS |
5234 | dwc2_writel(hsotg, dr->dtxfsiz[i], DPTXFSIZN(i)); |
5235 | dwc2_writel(hsotg, dr->diepctl[i], DIEPCTL(i)); | |
58e52ff6 | 5236 | /* Restore OUT EPs */ |
f25c42b8 | 5237 | dwc2_writel(hsotg, dr->doeptsiz[i], DOEPTSIZ(i)); |
9a5d2816 VM |
5238 | /* WA for enabled EPx's OUT in DDMA mode. On entering to |
5239 | * hibernation wrong value read and saved from DOEPDMAx, | |
5240 | * as result BNA interrupt asserted on hibernation exit | |
5241 | * by restoring from saved area. | |
5242 | */ | |
c4bc515d | 5243 | if (using_desc_dma(hsotg) && |
9a5d2816 VM |
5244 | (dr->doepctl[i] & DXEPCTL_EPENA)) |
5245 | dr->doepdma[i] = hsotg->eps_out[i]->desc_list_dma; | |
f25c42b8 GS |
5246 | dwc2_writel(hsotg, dr->doepdma[i], DOEPDMA(i)); |
5247 | dwc2_writel(hsotg, dr->doepctl[i], DOEPCTL(i)); | |
58e52ff6 JY |
5248 | } |
5249 | ||
58e52ff6 JY |
5250 | return 0; |
5251 | } | |
21b03405 SA |
5252 | |
5253 | /** | |
5254 | * dwc2_gadget_init_lpm - Configure the core to support LPM in device mode | |
5255 | * | |
5256 | * @hsotg: Programming view of DWC_otg controller | |
5257 | * | |
5258 | */ | |
5259 | void dwc2_gadget_init_lpm(struct dwc2_hsotg *hsotg) | |
5260 | { | |
5261 | u32 val; | |
5262 | ||
5263 | if (!hsotg->params.lpm) | |
5264 | return; | |
5265 | ||
5266 | val = GLPMCFG_LPMCAP | GLPMCFG_APPL1RES; | |
5267 | val |= hsotg->params.hird_threshold_en ? GLPMCFG_HIRD_THRES_EN : 0; | |
5268 | val |= hsotg->params.lpm_clock_gating ? GLPMCFG_ENBLSLPM : 0; | |
5269 | val |= hsotg->params.hird_threshold << GLPMCFG_HIRD_THRES_SHIFT; | |
5270 | val |= hsotg->params.besl ? GLPMCFG_ENBESL : 0; | |
46637565 | 5271 | val |= GLPMCFG_LPM_REJECT_CTRL_CONTROL; |
9aed8c08 | 5272 | val |= GLPMCFG_LPM_ACCEPT_CTRL_ISOC; |
f25c42b8 GS |
5273 | dwc2_writel(hsotg, val, GLPMCFG); |
5274 | dev_dbg(hsotg->dev, "GLPMCFG=0x%08x\n", dwc2_readl(hsotg, GLPMCFG)); | |
4abe4537 GT |
5275 | |
5276 | /* Unmask WKUP_ALERT Interrupt */ | |
5277 | if (hsotg->params.service_interval) | |
5278 | dwc2_set_bit(hsotg, GINTMSK2, GINTMSK2_WKUP_ALERT_INT_MSK); | |
21b03405 | 5279 | } |
c5c403dc | 5280 | |
15d9dbf8 GT |
5281 | /** |
5282 | * dwc2_gadget_program_ref_clk - Program GREFCLK register in device mode | |
5283 | * | |
5284 | * @hsotg: Programming view of DWC_otg controller | |
5285 | * | |
5286 | */ | |
5287 | void dwc2_gadget_program_ref_clk(struct dwc2_hsotg *hsotg) | |
5288 | { | |
5289 | u32 val = 0; | |
5290 | ||
5291 | val |= GREFCLK_REF_CLK_MODE; | |
5292 | val |= hsotg->params.ref_clk_per << GREFCLK_REFCLKPER_SHIFT; | |
5293 | val |= hsotg->params.sof_cnt_wkup_alert << | |
5294 | GREFCLK_SOF_CNT_WKUP_ALERT_SHIFT; | |
5295 | ||
5296 | dwc2_writel(hsotg, val, GREFCLK); | |
5297 | dev_dbg(hsotg->dev, "GREFCLK=0x%08x\n", dwc2_readl(hsotg, GREFCLK)); | |
5298 | } | |
5299 | ||
c5c403dc VM |
5300 | /** |
5301 | * dwc2_gadget_enter_hibernation() - Put controller in Hibernation. | |
5302 | * | |
5303 | * @hsotg: Programming view of the DWC_otg controller | |
5304 | * | |
5305 | * Return non-zero if failed to enter to hibernation. | |
5306 | */ | |
5307 | int dwc2_gadget_enter_hibernation(struct dwc2_hsotg *hsotg) | |
5308 | { | |
5309 | u32 gpwrdn; | |
5310 | int ret = 0; | |
5311 | ||
5312 | /* Change to L2(suspend) state */ | |
5313 | hsotg->lx_state = DWC2_L2; | |
5314 | dev_dbg(hsotg->dev, "Start of hibernation completed\n"); | |
5315 | ret = dwc2_backup_global_registers(hsotg); | |
5316 | if (ret) { | |
5317 | dev_err(hsotg->dev, "%s: failed to backup global registers\n", | |
5318 | __func__); | |
5319 | return ret; | |
5320 | } | |
5321 | ret = dwc2_backup_device_registers(hsotg); | |
5322 | if (ret) { | |
5323 | dev_err(hsotg->dev, "%s: failed to backup device registers\n", | |
5324 | __func__); | |
5325 | return ret; | |
5326 | } | |
5327 | ||
5328 | gpwrdn = GPWRDN_PWRDNRSTN; | |
5329 | gpwrdn |= GPWRDN_PMUACTV; | |
f25c42b8 | 5330 | dwc2_writel(hsotg, gpwrdn, GPWRDN); |
c5c403dc VM |
5331 | udelay(10); |
5332 | ||
5333 | /* Set flag to indicate that we are in hibernation */ | |
5334 | hsotg->hibernated = 1; | |
5335 | ||
5336 | /* Enable interrupts from wake up logic */ | |
f25c42b8 | 5337 | gpwrdn = dwc2_readl(hsotg, GPWRDN); |
c5c403dc | 5338 | gpwrdn |= GPWRDN_PMUINTSEL; |
f25c42b8 | 5339 | dwc2_writel(hsotg, gpwrdn, GPWRDN); |
c5c403dc VM |
5340 | udelay(10); |
5341 | ||
5342 | /* Unmask device mode interrupts in GPWRDN */ | |
f25c42b8 | 5343 | gpwrdn = dwc2_readl(hsotg, GPWRDN); |
c5c403dc VM |
5344 | gpwrdn |= GPWRDN_RST_DET_MSK; |
5345 | gpwrdn |= GPWRDN_LNSTSCHG_MSK; | |
5346 | gpwrdn |= GPWRDN_STS_CHGINT_MSK; | |
f25c42b8 | 5347 | dwc2_writel(hsotg, gpwrdn, GPWRDN); |
c5c403dc VM |
5348 | udelay(10); |
5349 | ||
5350 | /* Enable Power Down Clamp */ | |
f25c42b8 | 5351 | gpwrdn = dwc2_readl(hsotg, GPWRDN); |
c5c403dc | 5352 | gpwrdn |= GPWRDN_PWRDNCLMP; |
f25c42b8 | 5353 | dwc2_writel(hsotg, gpwrdn, GPWRDN); |
c5c403dc VM |
5354 | udelay(10); |
5355 | ||
5356 | /* Switch off VDD */ | |
f25c42b8 | 5357 | gpwrdn = dwc2_readl(hsotg, GPWRDN); |
c5c403dc | 5358 | gpwrdn |= GPWRDN_PWRDNSWTCH; |
f25c42b8 | 5359 | dwc2_writel(hsotg, gpwrdn, GPWRDN); |
c5c403dc VM |
5360 | udelay(10); |
5361 | ||
5362 | /* Save gpwrdn register for further usage if stschng interrupt */ | |
f25c42b8 | 5363 | hsotg->gr_backup.gpwrdn = dwc2_readl(hsotg, GPWRDN); |
c5c403dc VM |
5364 | dev_dbg(hsotg->dev, "Hibernation completed\n"); |
5365 | ||
5366 | return ret; | |
5367 | } | |
5368 | ||
5369 | /** | |
5370 | * dwc2_gadget_exit_hibernation() | |
5371 | * This function is for exiting from Device mode hibernation by host initiated | |
5372 | * resume/reset and device initiated remote-wakeup. | |
5373 | * | |
5374 | * @hsotg: Programming view of the DWC_otg controller | |
5375 | * @rem_wakeup: indicates whether resume is initiated by Device or Host. | |
6fb914d7 | 5376 | * @reset: indicates whether resume is initiated by Reset. |
c5c403dc VM |
5377 | * |
5378 | * Return non-zero if failed to exit from hibernation. | |
5379 | */ | |
5380 | int dwc2_gadget_exit_hibernation(struct dwc2_hsotg *hsotg, | |
5381 | int rem_wakeup, int reset) | |
5382 | { | |
5383 | u32 pcgcctl; | |
5384 | u32 gpwrdn; | |
5385 | u32 dctl; | |
5386 | int ret = 0; | |
5387 | struct dwc2_gregs_backup *gr; | |
5388 | struct dwc2_dregs_backup *dr; | |
5389 | ||
5390 | gr = &hsotg->gr_backup; | |
5391 | dr = &hsotg->dr_backup; | |
5392 | ||
5393 | if (!hsotg->hibernated) { | |
5394 | dev_dbg(hsotg->dev, "Already exited from Hibernation\n"); | |
5395 | return 1; | |
5396 | } | |
5397 | dev_dbg(hsotg->dev, | |
5398 | "%s: called with rem_wakeup = %d reset = %d\n", | |
5399 | __func__, rem_wakeup, reset); | |
5400 | ||
5401 | dwc2_hib_restore_common(hsotg, rem_wakeup, 0); | |
5402 | ||
5403 | if (!reset) { | |
5404 | /* Clear all pending interupts */ | |
f25c42b8 | 5405 | dwc2_writel(hsotg, 0xffffffff, GINTSTS); |
c5c403dc VM |
5406 | } |
5407 | ||
5408 | /* De-assert Restore */ | |
f25c42b8 | 5409 | gpwrdn = dwc2_readl(hsotg, GPWRDN); |
c5c403dc | 5410 | gpwrdn &= ~GPWRDN_RESTORE; |
f25c42b8 | 5411 | dwc2_writel(hsotg, gpwrdn, GPWRDN); |
c5c403dc VM |
5412 | udelay(10); |
5413 | ||
5414 | if (!rem_wakeup) { | |
f25c42b8 | 5415 | pcgcctl = dwc2_readl(hsotg, PCGCTL); |
c5c403dc | 5416 | pcgcctl &= ~PCGCTL_RSTPDWNMODULE; |
f25c42b8 | 5417 | dwc2_writel(hsotg, pcgcctl, PCGCTL); |
c5c403dc VM |
5418 | } |
5419 | ||
5420 | /* Restore GUSBCFG, DCFG and DCTL */ | |
f25c42b8 GS |
5421 | dwc2_writel(hsotg, gr->gusbcfg, GUSBCFG); |
5422 | dwc2_writel(hsotg, dr->dcfg, DCFG); | |
5423 | dwc2_writel(hsotg, dr->dctl, DCTL); | |
c5c403dc | 5424 | |
b29b494b AP |
5425 | /* On USB Reset, reset device address to zero */ |
5426 | if (reset) | |
5427 | dwc2_clear_bit(hsotg, DCFG, DCFG_DEVADDR_MASK); | |
5428 | ||
c5c403dc | 5429 | /* De-assert Wakeup Logic */ |
f25c42b8 | 5430 | gpwrdn = dwc2_readl(hsotg, GPWRDN); |
c5c403dc | 5431 | gpwrdn &= ~GPWRDN_PMUACTV; |
f25c42b8 | 5432 | dwc2_writel(hsotg, gpwrdn, GPWRDN); |
c5c403dc VM |
5433 | |
5434 | if (rem_wakeup) { | |
5435 | udelay(10); | |
5436 | /* Start Remote Wakeup Signaling */ | |
f25c42b8 | 5437 | dwc2_writel(hsotg, dr->dctl | DCTL_RMTWKUPSIG, DCTL); |
c5c403dc VM |
5438 | } else { |
5439 | udelay(50); | |
5440 | /* Set Device programming done bit */ | |
f25c42b8 | 5441 | dctl = dwc2_readl(hsotg, DCTL); |
c5c403dc | 5442 | dctl |= DCTL_PWRONPRGDONE; |
f25c42b8 | 5443 | dwc2_writel(hsotg, dctl, DCTL); |
c5c403dc VM |
5444 | } |
5445 | /* Wait for interrupts which must be cleared */ | |
5446 | mdelay(2); | |
5447 | /* Clear all pending interupts */ | |
f25c42b8 | 5448 | dwc2_writel(hsotg, 0xffffffff, GINTSTS); |
c5c403dc VM |
5449 | |
5450 | /* Restore global registers */ | |
5451 | ret = dwc2_restore_global_registers(hsotg); | |
5452 | if (ret) { | |
5453 | dev_err(hsotg->dev, "%s: failed to restore registers\n", | |
5454 | __func__); | |
5455 | return ret; | |
5456 | } | |
5457 | ||
5458 | /* Restore device registers */ | |
5459 | ret = dwc2_restore_device_registers(hsotg, rem_wakeup); | |
5460 | if (ret) { | |
5461 | dev_err(hsotg->dev, "%s: failed to restore device registers\n", | |
5462 | __func__); | |
5463 | return ret; | |
5464 | } | |
5465 | ||
5466 | if (rem_wakeup) { | |
5467 | mdelay(10); | |
f25c42b8 | 5468 | dctl = dwc2_readl(hsotg, DCTL); |
c5c403dc | 5469 | dctl &= ~DCTL_RMTWKUPSIG; |
f25c42b8 | 5470 | dwc2_writel(hsotg, dctl, DCTL); |
c5c403dc VM |
5471 | } |
5472 | ||
5473 | hsotg->hibernated = 0; | |
5474 | hsotg->lx_state = DWC2_L0; | |
5475 | dev_dbg(hsotg->dev, "Hibernation recovery completes here\n"); | |
5476 | ||
5477 | return ret; | |
5478 | } | |
be2b960e AP |
5479 | |
5480 | /** | |
5481 | * dwc2_gadget_enter_partial_power_down() - Put controller in partial | |
5482 | * power down. | |
5483 | * | |
5484 | * @hsotg: Programming view of the DWC_otg controller | |
5485 | * | |
5486 | * Return: non-zero if failed to enter device partial power down. | |
5487 | * | |
5488 | * This function is for entering device mode partial power down. | |
5489 | */ | |
5490 | int dwc2_gadget_enter_partial_power_down(struct dwc2_hsotg *hsotg) | |
5491 | { | |
5492 | u32 pcgcctl; | |
5493 | int ret = 0; | |
5494 | ||
5495 | dev_dbg(hsotg->dev, "Entering device partial power down started.\n"); | |
5496 | ||
5497 | /* Backup all registers */ | |
5498 | ret = dwc2_backup_global_registers(hsotg); | |
5499 | if (ret) { | |
5500 | dev_err(hsotg->dev, "%s: failed to backup global registers\n", | |
5501 | __func__); | |
5502 | return ret; | |
5503 | } | |
5504 | ||
5505 | ret = dwc2_backup_device_registers(hsotg); | |
5506 | if (ret) { | |
5507 | dev_err(hsotg->dev, "%s: failed to backup device registers\n", | |
5508 | __func__); | |
5509 | return ret; | |
5510 | } | |
5511 | ||
5512 | /* | |
5513 | * Clear any pending interrupts since dwc2 will not be able to | |
5514 | * clear them after entering partial_power_down. | |
5515 | */ | |
5516 | dwc2_writel(hsotg, 0xffffffff, GINTSTS); | |
5517 | ||
5518 | /* Put the controller in low power state */ | |
5519 | pcgcctl = dwc2_readl(hsotg, PCGCTL); | |
5520 | ||
5521 | pcgcctl |= PCGCTL_PWRCLMP; | |
5522 | dwc2_writel(hsotg, pcgcctl, PCGCTL); | |
5523 | udelay(5); | |
5524 | ||
5525 | pcgcctl |= PCGCTL_RSTPDWNMODULE; | |
5526 | dwc2_writel(hsotg, pcgcctl, PCGCTL); | |
5527 | udelay(5); | |
5528 | ||
5529 | pcgcctl |= PCGCTL_STOPPCLK; | |
5530 | dwc2_writel(hsotg, pcgcctl, PCGCTL); | |
5531 | ||
5532 | /* Set in_ppd flag to 1 as here core enters suspend. */ | |
5533 | hsotg->in_ppd = 1; | |
5534 | hsotg->lx_state = DWC2_L2; | |
5535 | ||
5536 | dev_dbg(hsotg->dev, "Entering device partial power down completed.\n"); | |
5537 | ||
5538 | return ret; | |
5539 | } | |
5540 | ||
5541 | /* | |
5542 | * dwc2_gadget_exit_partial_power_down() - Exit controller from device partial | |
5543 | * power down. | |
5544 | * | |
5545 | * @hsotg: Programming view of the DWC_otg controller | |
5546 | * @restore: indicates whether need to restore the registers or not. | |
5547 | * | |
5548 | * Return: non-zero if failed to exit device partial power down. | |
5549 | * | |
5550 | * This function is for exiting from device mode partial power down. | |
5551 | */ | |
5552 | int dwc2_gadget_exit_partial_power_down(struct dwc2_hsotg *hsotg, | |
5553 | bool restore) | |
5554 | { | |
5555 | u32 pcgcctl; | |
5556 | u32 dctl; | |
5557 | struct dwc2_dregs_backup *dr; | |
5558 | int ret = 0; | |
5559 | ||
5560 | dr = &hsotg->dr_backup; | |
5561 | ||
5562 | dev_dbg(hsotg->dev, "Exiting device partial Power Down started.\n"); | |
5563 | ||
5564 | pcgcctl = dwc2_readl(hsotg, PCGCTL); | |
5565 | pcgcctl &= ~PCGCTL_STOPPCLK; | |
5566 | dwc2_writel(hsotg, pcgcctl, PCGCTL); | |
5567 | ||
5568 | pcgcctl = dwc2_readl(hsotg, PCGCTL); | |
5569 | pcgcctl &= ~PCGCTL_PWRCLMP; | |
5570 | dwc2_writel(hsotg, pcgcctl, PCGCTL); | |
5571 | ||
5572 | pcgcctl = dwc2_readl(hsotg, PCGCTL); | |
5573 | pcgcctl &= ~PCGCTL_RSTPDWNMODULE; | |
5574 | dwc2_writel(hsotg, pcgcctl, PCGCTL); | |
5575 | ||
5576 | udelay(100); | |
5577 | if (restore) { | |
5578 | ret = dwc2_restore_global_registers(hsotg); | |
5579 | if (ret) { | |
5580 | dev_err(hsotg->dev, "%s: failed to restore registers\n", | |
5581 | __func__); | |
5582 | return ret; | |
5583 | } | |
5584 | /* Restore DCFG */ | |
5585 | dwc2_writel(hsotg, dr->dcfg, DCFG); | |
5586 | ||
5587 | ret = dwc2_restore_device_registers(hsotg, 0); | |
5588 | if (ret) { | |
5589 | dev_err(hsotg->dev, "%s: failed to restore device registers\n", | |
5590 | __func__); | |
5591 | return ret; | |
5592 | } | |
5593 | } | |
5594 | ||
5595 | /* Set the Power-On Programming done bit */ | |
5596 | dctl = dwc2_readl(hsotg, DCTL); | |
5597 | dctl |= DCTL_PWRONPRGDONE; | |
5598 | dwc2_writel(hsotg, dctl, DCTL); | |
5599 | ||
5600 | /* Set in_ppd flag to 0 as here core exits from suspend. */ | |
5601 | hsotg->in_ppd = 0; | |
5602 | hsotg->lx_state = DWC2_L0; | |
5603 | ||
5604 | dev_dbg(hsotg->dev, "Exiting device partial Power Down completed.\n"); | |
5605 | return ret; | |
5606 | } | |
012466fc AP |
5607 | |
5608 | /** | |
5609 | * dwc2_gadget_enter_clock_gating() - Put controller in clock gating. | |
5610 | * | |
5611 | * @hsotg: Programming view of the DWC_otg controller | |
5612 | * | |
5613 | * Return: non-zero if failed to enter device partial power down. | |
5614 | * | |
5615 | * This function is for entering device mode clock gating. | |
5616 | */ | |
5617 | void dwc2_gadget_enter_clock_gating(struct dwc2_hsotg *hsotg) | |
5618 | { | |
5619 | u32 pcgctl; | |
5620 | ||
5621 | dev_dbg(hsotg->dev, "Entering device clock gating.\n"); | |
5622 | ||
5623 | /* Set the Phy Clock bit as suspend is received. */ | |
5624 | pcgctl = dwc2_readl(hsotg, PCGCTL); | |
5625 | pcgctl |= PCGCTL_STOPPCLK; | |
5626 | dwc2_writel(hsotg, pcgctl, PCGCTL); | |
5627 | udelay(5); | |
5628 | ||
5629 | /* Set the Gate hclk as suspend is received. */ | |
5630 | pcgctl = dwc2_readl(hsotg, PCGCTL); | |
5631 | pcgctl |= PCGCTL_GATEHCLK; | |
5632 | dwc2_writel(hsotg, pcgctl, PCGCTL); | |
5633 | udelay(5); | |
5634 | ||
5635 | hsotg->lx_state = DWC2_L2; | |
5636 | hsotg->bus_suspended = true; | |
5637 | } | |
5638 | ||
5639 | /* | |
5640 | * dwc2_gadget_exit_clock_gating() - Exit controller from device clock gating. | |
5641 | * | |
5642 | * @hsotg: Programming view of the DWC_otg controller | |
5643 | * @rem_wakeup: indicates whether remote wake up is enabled. | |
5644 | * | |
5645 | * This function is for exiting from device mode clock gating. | |
5646 | */ | |
5647 | void dwc2_gadget_exit_clock_gating(struct dwc2_hsotg *hsotg, int rem_wakeup) | |
5648 | { | |
5649 | u32 pcgctl; | |
5650 | u32 dctl; | |
5651 | ||
5652 | dev_dbg(hsotg->dev, "Exiting device clock gating.\n"); | |
5653 | ||
5654 | /* Clear the Gate hclk. */ | |
5655 | pcgctl = dwc2_readl(hsotg, PCGCTL); | |
5656 | pcgctl &= ~PCGCTL_GATEHCLK; | |
5657 | dwc2_writel(hsotg, pcgctl, PCGCTL); | |
5658 | udelay(5); | |
5659 | ||
5660 | /* Phy Clock bit. */ | |
5661 | pcgctl = dwc2_readl(hsotg, PCGCTL); | |
5662 | pcgctl &= ~PCGCTL_STOPPCLK; | |
5663 | dwc2_writel(hsotg, pcgctl, PCGCTL); | |
5664 | udelay(5); | |
5665 | ||
5666 | if (rem_wakeup) { | |
5667 | /* Set Remote Wakeup Signaling */ | |
5668 | dctl = dwc2_readl(hsotg, DCTL); | |
5669 | dctl |= DCTL_RMTWKUPSIG; | |
5670 | dwc2_writel(hsotg, dctl, DCTL); | |
5671 | } | |
5672 | ||
5673 | /* Change to L0 state */ | |
5674 | call_gadget(hsotg, resume); | |
5675 | hsotg->lx_state = DWC2_L0; | |
5676 | hsotg->bus_suspended = false; | |
5677 | } |