projects / linux-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
usb: renesas_usbhs: mod_host: fix typo: "connecte" -> "connected"
[linux-block.git] / drivers / usb / dwc2 / core.h
CommitLineData
56f5b1cf
PZ		 1/*
2 * core.h - DesignWare HS OTG Controller common declarations
3 *
4 * Copyright (C) 2004-2013 Synopsys, Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions, and the following disclaimer,
11 * without modification.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The names of the above-listed copyright holders may not be used
16 * to endorse or promote products derived from this software without
17 * specific prior written permission.
18 *
19 * ALTERNATIVELY, this software may be distributed under the terms of the
20 * GNU General Public License ("GPL") as published by the Free Software
21 * Foundation; either version 2 of the License, or (at your option) any
22 * later version.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
25 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
28 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
29 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
30 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
31 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
32 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
33 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
34 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 */
36
37#ifndef __DWC2_CORE_H__
38#define __DWC2_CORE_H__
39
f7c0b143
DN		 40#include <linux/phy/phy.h>
41#include <linux/regulator/consumer.h>
42#include <linux/usb/gadget.h>
43#include <linux/usb/otg.h>
56f5b1cf
PZ		 44#include <linux/usb/phy.h>
45#include "hw.h"
46
74fc4a75
DA		 47/*
48 * Suggested defines for tracers:
49 * - no_printk: Disable tracing
50 * - pr_info: Print this info to the console
51 * - trace_printk: Print this info to trace buffer (good for verbose logging)
52 */
53
54#define DWC2_TRACE_SCHEDULER no_printk
55#define DWC2_TRACE_SCHEDULER_VB no_printk
56
57/* Detailed scheduler tracing, but won't overwhelm console */
58#define dwc2_sch_dbg(hsotg, fmt, ...) \
59 DWC2_TRACE_SCHEDULER(pr_fmt("%s: SCH: " fmt), \
60 dev_name(hsotg->dev), ##__VA_ARGS__)
61
62/* Verbose scheduler tracing */
63#define dwc2_sch_vdbg(hsotg, fmt, ...) \
64 DWC2_TRACE_SCHEDULER_VB(pr_fmt("%s: SCH: " fmt), \
65 dev_name(hsotg->dev), ##__VA_ARGS__)
66
23e34392
AB		 67#ifdef CONFIG_MIPS
68/*
69 * There are some MIPS machines that can run in either big-endian
70 * or little-endian mode and that use the dwc2 register without
71 * a byteswap in both ways.
72 * Unlike other architectures, MIPS apparently does not require a
73 * barrier before the __raw_writel() to synchronize with DMA but does
74 * require the barrier after the __raw_writel() to serialize a set of
75 * writes. This set of operations was added specifically for MIPS and
76 * should only be used there.
77 */
95c8bc36 78static inline u32 dwc2_readl(const void __iomem *addr)
56f5b1cf 79{
95c8bc36
AS		 80 u32 value = __raw_readl(addr);
81
82 /* In order to preserve endianness __raw_* operation is used. Therefore
83 * a barrier is needed to ensure IO access is not re-ordered across
84 * reads or writes
85 */
86 mb();
87 return value;
56f5b1cf
PZ		 88}
89
95c8bc36
AS		 90static inline void dwc2_writel(u32 value, void __iomem *addr)
91{
92 __raw_writel(value, addr);
93
94 /*
95 * In order to preserve endianness __raw_* operation is used. Therefore
96 * a barrier is needed to ensure IO access is not re-ordered across
97 * reads or writes
98 */
99 mb();
100#ifdef DWC2_LOG_WRITES
101 pr_info("INFO:: wrote %08x to %p\n", value, addr);
56f5b1cf 102#endif
95c8bc36 103}
23e34392
AB		 104#else
105/* Normal architectures just use readl/write */
106static inline u32 dwc2_readl(const void __iomem *addr)
107{
108 return readl(addr);
109}
110
111static inline void dwc2_writel(u32 value, void __iomem *addr)
112{
113 writel(value, addr);
114
115#ifdef DWC2_LOG_WRITES
116 pr_info("info:: wrote %08x to %p\n", value, addr);
117#endif
118}
119#endif
56f5b1cf
PZ		 120
121/* Maximum number of Endpoints/HostChannels */
122#define MAX_EPS_CHANNELS 16
123
1f91b4cc
FB		 124/* dwc2-hsotg declarations */
125static const char * const dwc2_hsotg_supply_names[] = {
f7c0b143
DN		 126 "vusb_d", /* digital USB supply, 1.2V */
127 "vusb_a", /* analog USB supply, 1.1V */
128};
129
130/*
131 * EP0_MPS_LIMIT
132 *
133 * Unfortunately there seems to be a limit of the amount of data that can
134 * be transferred by IN transactions on EP0. This is either 127 bytes or 3
135 * packets (which practically means 1 packet and 63 bytes of data) when the
136 * MPS is set to 64.
137 *
138 * This means if we are wanting to move >127 bytes of data, we need to
139 * split the transactions up, but just doing one packet at a time does
140 * not work (this may be an implicit DATA0 PID on first packet of the
141 * transaction) and doing 2 packets is outside the controller's limits.
142 *
143 * If we try to lower the MPS size for EP0, then no transfers work properly
144 * for EP0, and the system will fail basic enumeration. As no cause for this
145 * has currently been found, we cannot support any large IN transfers for
146 * EP0.
147 */
148#define EP0_MPS_LIMIT 64
149
941fcce4 150struct dwc2_hsotg;
1f91b4cc 151struct dwc2_hsotg_req;
f7c0b143
DN		 152
153/**
1f91b4cc 154 * struct dwc2_hsotg_ep - driver endpoint definition.
f7c0b143
DN		 155 * @ep: The gadget layer representation of the endpoint.
156 * @name: The driver generated name for the endpoint.
157 * @queue: Queue of requests for this endpoint.
158 * @parent: Reference back to the parent device structure.
159 * @req: The current request that the endpoint is processing. This is
160 * used to indicate an request has been loaded onto the endpoint
161 * and has yet to be completed (maybe due to data move, or simply
162 * awaiting an ack from the core all the data has been completed).
163 * @debugfs: File entry for debugfs file for this endpoint.
164 * @lock: State lock to protect contents of endpoint.
165 * @dir_in: Set to true if this endpoint is of the IN direction, which
166 * means that it is sending data to the Host.
167 * @index: The index for the endpoint registers.
168 * @mc: Multi Count - number of transactions per microframe
142bd33f 169 * @interval - Interval for periodic endpoints, in frames or microframes.
f7c0b143
DN		 170 * @name: The name array passed to the USB core.
171 * @halted: Set if the endpoint has been halted.
172 * @periodic: Set if this is a periodic ep, such as Interrupt
173 * @isochronous: Set if this is a isochronous ep
8a20fa45 174 * @send_zlp: Set if we need to send a zero-length packet.
5f54c54b
VA		 175 * @desc_list_dma: The DMA address of descriptor chain currently in use.
176 * @desc_list: Pointer to descriptor DMA chain head currently in use.
177 * @desc_count: Count of entries within the DMA descriptor chain of EP.
ab7d2192
VA		 178 * @isoc_chain_num: Number of ISOC chain currently in use - either 0 or 1.
179 * @next_desc: index of next free descriptor in the ISOC chain under SW control.
f7c0b143
DN		 180 * @total_data: The total number of data bytes done.
181 * @fifo_size: The size of the FIFO (for periodic IN endpoints)
182 * @fifo_load: The amount of data loaded into the FIFO (periodic IN)
183 * @last_load: The offset of data for the last start of request.
184 * @size_loaded: The last loaded size for DxEPTSIZE for periodic IN
92d1635d
VM		 185 * @target_frame: Targeted frame num to setup next ISOC transfer
186 * @frame_overrun: Indicates SOF number overrun in DSTS
f7c0b143
DN		 187 *
188 * This is the driver's state for each registered enpoint, allowing it
189 * to keep track of transactions that need doing. Each endpoint has a
190 * lock to protect the state, to try and avoid using an overall lock
191 * for the host controller as much as possible.
192 *
193 * For periodic IN endpoints, we have fifo_size and fifo_load to try
194 * and keep track of the amount of data in the periodic FIFO for each
195 * of these as we don't have a status register that tells us how much
196 * is in each of them. (note, this may actually be useless information
197 * as in shared-fifo mode periodic in acts like a single-frame packet
198 * buffer than a fifo)
199 */
1f91b4cc 200struct dwc2_hsotg_ep {
f7c0b143
DN		 201 struct usb_ep ep;
202 struct list_head queue;
941fcce4 203 struct dwc2_hsotg *parent;
1f91b4cc 204 struct dwc2_hsotg_req *req;
f7c0b143
DN		 205 struct dentry *debugfs;
206
207 unsigned long total_data;
208 unsigned int size_loaded;
209 unsigned int last_load;
210 unsigned int fifo_load;
211 unsigned short fifo_size;
b203d0a2 212 unsigned short fifo_index;
f7c0b143
DN		 213
214 unsigned char dir_in;
215 unsigned char index;
216 unsigned char mc;
217 unsigned char interval;
218
219 unsigned int halted:1;
220 unsigned int periodic:1;
221 unsigned int isochronous:1;
8a20fa45 222 unsigned int send_zlp:1;
92d1635d
VM		 223 unsigned int target_frame;
224#define TARGET_FRAME_INITIAL 0xFFFFFFFF
225 bool frame_overrun;
f7c0b143 226
5f54c54b
VA		 227 dma_addr_t desc_list_dma;
228 struct dwc2_dma_desc *desc_list;
229 u8 desc_count;
230
ab7d2192
VA		 231 unsigned char isoc_chain_num;
232 unsigned int next_desc;
233
f7c0b143
DN		 234 char name[10];
235};
236
f7c0b143 237/**
1f91b4cc 238 * struct dwc2_hsotg_req - data transfer request
f7c0b143
DN		 239 * @req: The USB gadget request
240 * @queue: The list of requests for the endpoint this is queued for.
7d24c1b5 241 * @saved_req_buf: variable to save req.buf when bounce buffers are used.
f7c0b143 242 */
1f91b4cc 243struct dwc2_hsotg_req {
f7c0b143
DN		 244 struct usb_request req;
245 struct list_head queue;
7d24c1b5 246 void *saved_req_buf;
f7c0b143
DN		 247};
248
941fcce4 249#if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
f7c0b143
DN		 250#define call_gadget(_hs, _entry) \
251do { \
252 if ((_hs)->gadget.speed != USB_SPEED_UNKNOWN && \
253 (_hs)->driver && (_hs)->driver->_entry) { \
254 spin_unlock(&_hs->lock); \
255 (_hs)->driver->_entry(&(_hs)->gadget); \
256 spin_lock(&_hs->lock); \
257 } \
258} while (0)
941fcce4
DN		 259#else
260#define call_gadget(_hs, _entry) do {} while (0)
261#endif
f7c0b143 262
56f5b1cf
PZ		 263struct dwc2_hsotg;
264struct dwc2_host_chan;
265
266/* Device States */
267enum dwc2_lx_state {
268 DWC2_L0, /* On state */
269 DWC2_L1, /* LPM sleep state */
270 DWC2_L2, /* USB suspend state */
271 DWC2_L3, /* Off state */
272};
273
3fa95385
JY		 274/*
275 * Gadget periodic tx fifo sizes as used by legacy driver
276 * EP0 is not included
277 */
278#define DWC2_G_P_LEGACY_TX_FIFO_SIZE {256, 256, 256, 256, 768, 768, 768, \
279 768, 0, 0, 0, 0, 0, 0, 0}
280
fe0b94ab
MYK		 281/* Gadget ep0 states */
282enum dwc2_ep0_state {
283 DWC2_EP0_SETUP,
284 DWC2_EP0_DATA_IN,
285 DWC2_EP0_DATA_OUT,
286 DWC2_EP0_STATUS_IN,
287 DWC2_EP0_STATUS_OUT,
288};
289
56f5b1cf
PZ		 290/**
291 * struct dwc2_core_params - Parameters for configuring the core
292 *
91121c10
MK		 293 * @otg_cap: Specifies the OTG capabilities.
294 * 0 - HNP and SRP capable
56f5b1cf 295 * 1 - SRP Only capable
91121c10
MK		 296 * 2 - No HNP/SRP capable (always available)
297 * Defaults to best available option (0, 1, then 2)
725acc86 298 * @otg_ver: OTG version supported
91121c10 299 * 0 - 1.3 (default)
725acc86 300 * 1 - 2.0
e7839f99 301 * @host_dma: Specifies whether to use slave or DMA mode for accessing
56f5b1cf
PZ		 302 * the data FIFOs. The driver will automatically detect the
303 * value for this parameter if none is specified.
91121c10 304 * 0 - Slave (always available)
56f5b1cf
PZ		 305 * 1 - DMA (default, if available)
306 * @dma_desc_enable: When DMA mode is enabled, specifies whether to use
307 * address DMA mode or descriptor DMA mode for accessing
308 * the data FIFOs. The driver will automatically detect the
309 * value for this if none is specified.
310 * 0 - Address DMA
311 * 1 - Descriptor DMA (default, if available)
fbb9e22b
MYK		 312 * @dma_desc_fs_enable: When DMA mode is enabled, specifies whether to use
313 * address DMA mode or descriptor DMA mode for accessing
314 * the data FIFOs in Full Speed mode only. The driver
315 * will automatically detect the value for this if none is
316 * specified.
317 * 0 - Address DMA
318 * 1 - Descriptor DMA in FS (default, if available)
56f5b1cf
PZ		 319 * @speed: Specifies the maximum speed of operation in host and
320 * device mode. The actual speed depends on the speed of
321 * the attached device and the value of phy_type.
91121c10
MK		 322 * 0 - High Speed
323 * (default when phy_type is UTMI+ or ULPI)
56f5b1cf 324 * 1 - Full Speed
91121c10 325 * (default when phy_type is Full Speed)
56f5b1cf 326 * @enable_dynamic_fifo: 0 - Use coreConsultant-specified FIFO size parameters
91121c10 327 * 1 - Allow dynamic FIFO sizing (default, if available)
725acc86 328 * @en_multiple_tx_fifo: Specifies whether dedicated per-endpoint transmit FIFOs
c1d286cf
JY		 329 * are enabled for non-periodic IN endpoints in device
330 * mode.
56f5b1cf
PZ		 331 * @host_rx_fifo_size: Number of 4-byte words in the Rx FIFO in host mode when
332 * dynamic FIFO sizing is enabled
91121c10
MK		 333 * 16 to 32768
334 * Actual maximum value is autodetected and also
335 * the default.
56f5b1cf
PZ		 336 * @host_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO
337 * in host mode when dynamic FIFO sizing is enabled
91121c10
MK		 338 * 16 to 32768
339 * Actual maximum value is autodetected and also
340 * the default.
56f5b1cf
PZ		 341 * @host_perio_tx_fifo_size: Number of 4-byte words in the periodic Tx FIFO in
342 * host mode when dynamic FIFO sizing is enabled
91121c10
MK		 343 * 16 to 32768
344 * Actual maximum value is autodetected and also
345 * the default.
56f5b1cf 346 * @max_transfer_size: The maximum transfer size supported, in bytes
91121c10
MK		 347 * 2047 to 65,535
348 * Actual maximum value is autodetected and also
349 * the default.
56f5b1cf 350 * @max_packet_count: The maximum number of packets in a transfer
91121c10
MK		 351 * 15 to 511
352 * Actual maximum value is autodetected and also
353 * the default.
56f5b1cf 354 * @host_channels: The number of host channel registers to use
91121c10
MK		 355 * 1 to 16
356 * Actual maximum value is autodetected and also
357 * the default.
56f5b1cf
PZ		 358 * @phy_type: Specifies the type of PHY interface to use. By default,
359 * the driver will automatically detect the phy_type.
91121c10
MK		 360 * 0 - Full Speed Phy
361 * 1 - UTMI+ Phy
362 * 2 - ULPI Phy
363 * Defaults to best available option (2, 1, then 0)
56f5b1cf
PZ		 364 * @phy_utmi_width: Specifies the UTMI+ Data Width (in bits). This parameter
365 * is applicable for a phy_type of UTMI+ or ULPI. (For a
366 * ULPI phy_type, this parameter indicates the data width
367 * between the MAC and the ULPI Wrapper.) Also, this
368 * parameter is applicable only if the OTG_HSPHY_WIDTH cC
369 * parameter was set to "8 and 16 bits", meaning that the
370 * core has been configured to work at either data path
371 * width.
91121c10 372 * 8 or 16 (default 16 if available)
56f5b1cf
PZ		 373 * @phy_ulpi_ddr: Specifies whether the ULPI operates at double or single
374 * data rate. This parameter is only applicable if phy_type
375 * is ULPI.
376 * 0 - single data rate ULPI interface with 8 bit wide
377 * data bus (default)
378 * 1 - double data rate ULPI interface with 4 bit wide
379 * data bus
380 * @phy_ulpi_ext_vbus: For a ULPI phy, specifies whether to use the internal or
381 * external supply to drive the VBus
91121c10
MK		 382 * 0 - Internal supply (default)
383 * 1 - External supply
56f5b1cf
PZ		 384 * @i2c_enable: Specifies whether to use the I2Cinterface for a full
385 * speed PHY. This parameter is only applicable if phy_type
386 * is FS.
387 * 0 - No (default)
388 * 1 - Yes
91121c10
MK		 389 * @ulpi_fs_ls: Make ULPI phy operate in FS/LS mode only
390 * 0 - No (default)
391 * 1 - Yes
725acc86
PZ		 392 * @host_support_fs_ls_low_power: Specifies whether low power mode is supported
393 * when attached to a Full Speed or Low Speed device in
394 * host mode.
395 * 0 - Don't support low power mode (default)
396 * 1 - Support low power mode
397 * @host_ls_low_power_phy_clk: Specifies the PHY clock rate in low power mode
91121c10
MK		 398 * when connected to a Low Speed device in host
399 * mode. This parameter is applicable only if
400 * host_support_fs_ls_low_power is enabled.
725acc86 401 * 0 - 48 MHz
91121c10 402 * (default when phy_type is UTMI+ or ULPI)
725acc86 403 * 1 - 6 MHz
91121c10
MK		 404 * (default when phy_type is Full Speed)
405 * @ts_dline: Enable Term Select Dline pulsing
406 * 0 - No (default)
407 * 1 - Yes
408 * @reload_ctl: Allow dynamic reloading of HFIR register during runtime
409 * 0 - No (default for core < 2.92a)
410 * 1 - Yes (default for core >= 2.92a)
4d3190e1
PZ		 411 * @ahbcfg: This field allows the default value of the GAHBCFG
412 * register to be overridden
91121c10
MK		 413 * -1 - GAHBCFG value will be set to 0x06
414 * (INCR4, default)
4d3190e1
PZ		 415 * all others - GAHBCFG value will be overridden with
416 * this value
91121c10
MK		 417 * Not all bits can be controlled like this, the
418 * bits defined by GAHBCFG_CTRL_MASK are controlled
419 * by the driver and are ignored in this
420 * configuration value.
20f2eb9c 421 * @uframe_sched: True to enable the microframe scheduler
a6d249d8
GH		 422 * @external_id_pin_ctl: Specifies whether ID pin is handled externally.
423 * Disable CONIDSTSCHNG controller interrupt in such
424 * case.
425 * 0 - No (default)
426 * 1 - Yes
285046aa
GH		 427 * @hibernation: Specifies whether the controller support hibernation.
428 * If hibernation is enabled, the controller will enter
429 * hibernation in both peripheral and host mode when
430 * needed.
431 * 0 - No (default)
432 * 1 - Yes
9962b62f 433 * @g_dma: Enables gadget dma usage (default: autodetect).
dec4b556 434 * @g_dma_desc: Enables gadget descriptor DMA (default: autodetect).
05ee799f
JY		 435 * @g_rx_fifo_size: The periodic rx fifo size for the device, in
436 * DWORDS from 16-32768 (default: 2048 if
437 * possible, otherwise autodetect).
438 * @g_np_tx_fifo_size: The non-periodic tx fifo size for the device in
439 * DWORDS from 16-32768 (default: 1024 if
440 * possible, otherwise autodetect).
441 * @g_tx_fifo_size: An array of TX fifo sizes in dedicated fifo
442 * mode. Each value corresponds to one EP
443 * starting from EP1 (max 15 values). Sizes are
444 * in DWORDS with possible values from from
445 * 16-32768 (default: 256, 256, 256, 256, 768,
446 * 768, 768, 768, 0, 0, 0, 0, 0, 0, 0).
56f5b1cf
PZ		 447 *
448 * The following parameters may be specified when starting the module. These
91121c10
MK		 449 * parameters define how the DWC_otg controller should be configured. A
450 * value of -1 (or any other out of range value) for any parameter means
451 * to read the value from hardware (if possible) or use the builtin
452 * default described above.
56f5b1cf
PZ		 453 */
454struct dwc2_core_params {
8284f93b
MK		 455 /*
456 * Don't add any non-int members here, this will break
457 * dwc2_set_all_params!
458 */
56f5b1cf 459 int otg_cap;
c1d286cf
JY		 460#define DWC2_CAP_PARAM_HNP_SRP_CAPABLE 0
461#define DWC2_CAP_PARAM_SRP_ONLY_CAPABLE 1
462#define DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE 2
463
56f5b1cf 464 int otg_ver;
56f5b1cf 465 int dma_desc_enable;
fbb9e22b 466 int dma_desc_fs_enable;
56f5b1cf 467 int speed;
c1d286cf
JY		 468#define DWC2_SPEED_PARAM_HIGH 0
469#define DWC2_SPEED_PARAM_FULL 1
38e9002b 470#define DWC2_SPEED_PARAM_LOW 2
c1d286cf 471
56f5b1cf
PZ		 472 int enable_dynamic_fifo;
473 int en_multiple_tx_fifo;
474 int host_rx_fifo_size;
475 int host_nperio_tx_fifo_size;
476 int host_perio_tx_fifo_size;
477 int max_transfer_size;
478 int max_packet_count;
479 int host_channels;
480 int phy_type;
c1d286cf
JY		 481#define DWC2_PHY_TYPE_PARAM_FS 0
482#define DWC2_PHY_TYPE_PARAM_UTMI 1
483#define DWC2_PHY_TYPE_PARAM_ULPI 2
484
56f5b1cf
PZ		 485 int phy_utmi_width;
486 int phy_ulpi_ddr;
487 int phy_ulpi_ext_vbus;
c1d286cf
JY		 488#define DWC2_PHY_ULPI_INTERNAL_VBUS 0
489#define DWC2_PHY_ULPI_EXTERNAL_VBUS 1
490
56f5b1cf
PZ		 491 int i2c_enable;
492 int ulpi_fs_ls;
493 int host_support_fs_ls_low_power;
494 int host_ls_low_power_phy_clk;
c1d286cf
JY		 495#define DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ 0
496#define DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ 1
497
56f5b1cf
PZ		 498 int ts_dline;
499 int reload_ctl;
4d3190e1 500 int ahbcfg;
20f2eb9c 501 int uframe_sched;
a6d249d8 502 int external_id_pin_ctl;
285046aa 503 int hibernation;
05ee799f
JY		 504
505 /*
506 * The following parameters are *only* set via device
507 * properties and cannot be set directly in this structure.
508 */
6b66ce51
JY		 509
510 /* Host parameters */
511 bool host_dma;
512
513 /* Gadget parameters */
05ee799f 514 bool g_dma;
dec4b556 515 bool g_dma_desc;
05ee799f
JY		 516 u16 g_rx_fifo_size;
517 u16 g_np_tx_fifo_size;
518 u32 g_tx_fifo_size[MAX_EPS_CHANNELS];
56f5b1cf
PZ		 519};
520
9badec2f
MK		 521/**
522 * struct dwc2_hw_params - Autodetected parameters.
523 *
524 * These parameters are the various parameters read from hardware
525 * registers during initialization. They typically contain the best
526 * supported or maximum value that can be configured in the
527 * corresponding dwc2_core_params value.
528 *
529 * The values that are not in dwc2_core_params are documented below.
530 *
531 * @op_mode Mode of Operation
532 * 0 - HNP- and SRP-Capable OTG (Host & Device)
533 * 1 - SRP-Capable OTG (Host & Device)
534 * 2 - Non-HNP and Non-SRP Capable OTG (Host & Device)
535 * 3 - SRP-Capable Device
536 * 4 - Non-OTG Device
537 * 5 - SRP-Capable Host
538 * 6 - Non-OTG Host
539 * @arch Architecture
540 * 0 - Slave only
541 * 1 - External DMA
542 * 2 - Internal DMA
543 * @power_optimized Are power optimizations enabled?
544 * @num_dev_ep Number of device endpoints available
545 * @num_dev_perio_in_ep Number of device periodic IN endpoints
997f4f81 546 * available
9badec2f
MK		 547 * @dev_token_q_depth Device Mode IN Token Sequence Learning Queue
548 * Depth
549 * 0 to 30
550 * @host_perio_tx_q_depth
551 * Host Mode Periodic Request Queue Depth
552 * 2, 4 or 8
553 * @nperio_tx_q_depth
554 * Non-Periodic Request Queue Depth
555 * 2, 4 or 8
556 * @hs_phy_type High-speed PHY interface type
557 * 0 - High-speed interface not supported
558 * 1 - UTMI+
559 * 2 - ULPI
560 * 3 - UTMI+ and ULPI
561 * @fs_phy_type Full-speed PHY interface type
562 * 0 - Full speed interface not supported
563 * 1 - Dedicated full speed interface
564 * 2 - FS pins shared with UTMI+ pins
565 * 3 - FS pins shared with ULPI pins
566 * @total_fifo_size: Total internal RAM for FIFOs (bytes)
de4a1931
MK		 567 * @utmi_phy_data_width UTMI+ PHY data width
568 * 0 - 8 bits
569 * 1 - 16 bits
570 * 2 - 8 or 16 bits
9badec2f 571 * @snpsid: Value from SNPSID register
55e1040e 572 * @dev_ep_dirs: Direction of device endpoints (GHWCFG1)
9badec2f
MK		 573 */
574struct dwc2_hw_params {
575 unsigned op_mode:3;
576 unsigned arch:2;
577 unsigned dma_desc_enable:1;
578 unsigned enable_dynamic_fifo:1;
579 unsigned en_multiple_tx_fifo:1;
d1531319 580 unsigned rx_fifo_size:16;
9badec2f 581 unsigned host_nperio_tx_fifo_size:16;
55e1040e 582 unsigned dev_nperio_tx_fifo_size:16;
9badec2f
MK		 583 unsigned host_perio_tx_fifo_size:16;
584 unsigned nperio_tx_q_depth:3;
585 unsigned host_perio_tx_q_depth:3;
586 unsigned dev_token_q_depth:5;
587 unsigned max_transfer_size:26;
588 unsigned max_packet_count:11;
2d115547 589 unsigned host_channels:5;
9badec2f
MK		 590 unsigned hs_phy_type:2;
591 unsigned fs_phy_type:2;
592 unsigned i2c_enable:1;
593 unsigned num_dev_ep:4;
594 unsigned num_dev_perio_in_ep:4;
595 unsigned total_fifo_size:16;
596 unsigned power_optimized:1;
de4a1931 597 unsigned utmi_phy_data_width:2;
9badec2f 598 u32 snpsid;
55e1040e 599 u32 dev_ep_dirs;
9badec2f
MK		 600};
601
3f95001d
MYK		 602/* Size of control and EP0 buffers */
603#define DWC2_CTRL_BUFF_SIZE 8
604
d17ee77b
GH		 605/**
606 * struct dwc2_gregs_backup - Holds global registers state before entering partial
607 * power down
608 * @gotgctl: Backup of GOTGCTL register
609 * @gintmsk: Backup of GINTMSK register
610 * @gahbcfg: Backup of GAHBCFG register
611 * @gusbcfg: Backup of GUSBCFG register
612 * @grxfsiz: Backup of GRXFSIZ register
613 * @gnptxfsiz: Backup of GNPTXFSIZ register
614 * @gi2cctl: Backup of GI2CCTL register
615 * @hptxfsiz: Backup of HPTXFSIZ register
616 * @gdfifocfg: Backup of GDFIFOCFG register
617 * @dtxfsiz: Backup of DTXFSIZ registers for each endpoint
618 * @gpwrdn: Backup of GPWRDN register
619 */
620struct dwc2_gregs_backup {
621 u32 gotgctl;
622 u32 gintmsk;
623 u32 gahbcfg;
624 u32 gusbcfg;
625 u32 grxfsiz;
626 u32 gnptxfsiz;
627 u32 gi2cctl;
628 u32 hptxfsiz;
629 u32 pcgcctl;
630 u32 gdfifocfg;
631 u32 dtxfsiz[MAX_EPS_CHANNELS];
632 u32 gpwrdn;
cc1e204c 633 bool valid;
d17ee77b
GH		 634};
635
636/**
637 * struct dwc2_dregs_backup - Holds device registers state before entering partial
638 * power down
639 * @dcfg: Backup of DCFG register
640 * @dctl: Backup of DCTL register
641 * @daintmsk: Backup of DAINTMSK register
642 * @diepmsk: Backup of DIEPMSK register
643 * @doepmsk: Backup of DOEPMSK register
644 * @diepctl: Backup of DIEPCTL register
645 * @dieptsiz: Backup of DIEPTSIZ register
646 * @diepdma: Backup of DIEPDMA register
647 * @doepctl: Backup of DOEPCTL register
648 * @doeptsiz: Backup of DOEPTSIZ register
649 * @doepdma: Backup of DOEPDMA register
650 */
651struct dwc2_dregs_backup {
652 u32 dcfg;
653 u32 dctl;
654 u32 daintmsk;
655 u32 diepmsk;
656 u32 doepmsk;
657 u32 diepctl[MAX_EPS_CHANNELS];
658 u32 dieptsiz[MAX_EPS_CHANNELS];
659 u32 diepdma[MAX_EPS_CHANNELS];
660 u32 doepctl[MAX_EPS_CHANNELS];
661 u32 doeptsiz[MAX_EPS_CHANNELS];
662 u32 doepdma[MAX_EPS_CHANNELS];
cc1e204c 663 bool valid;
d17ee77b
GH		 664};
665
666/**
667 * struct dwc2_hregs_backup - Holds host registers state before entering partial
668 * power down
669 * @hcfg: Backup of HCFG register
670 * @haintmsk: Backup of HAINTMSK register
671 * @hcintmsk: Backup of HCINTMSK register
672 * @hptr0: Backup of HPTR0 register
673 * @hfir: Backup of HFIR register
674 */
675struct dwc2_hregs_backup {
676 u32 hcfg;
677 u32 haintmsk;
678 u32 hcintmsk[MAX_EPS_CHANNELS];
679 u32 hprt0;
680 u32 hfir;
cc1e204c 681 bool valid;
d17ee77b
GH		 682};
683
9f9f09b0
DA		 684/*
685 * Constants related to high speed periodic scheduling
686 *
687 * We have a periodic schedule that is DWC2_HS_SCHEDULE_UFRAMES long. From a
688 * reservation point of view it's assumed that the schedule goes right back to
689 * the beginning after the end of the schedule.
690 *
691 * What does that mean for scheduling things with a long interval? It means
692 * we'll reserve time for them in every possible microframe that they could
693 * ever be scheduled in. ...but we'll still only actually schedule them as
694 * often as they were requested.
695 *
696 * We keep our schedule in a "bitmap" structure. This simplifies having
697 * to keep track of and merge intervals: we just let the bitmap code do most
698 * of the heavy lifting. In a way scheduling is much like memory allocation.
699 *
700 * We schedule 100us per uframe or 80% of 125us (the maximum amount you're
701 * supposed to schedule for periodic transfers). That's according to spec.
702 *
703 * Note that though we only schedule 80% of each microframe, the bitmap that we
704 * keep the schedule in is tightly packed (AKA it doesn't have 100us worth of
705 * space for each uFrame).
706 *
707 * Requirements:
708 * - DWC2_HS_SCHEDULE_UFRAMES must even divide 0x4000 (HFNUM_MAX_FRNUM + 1)
709 * - DWC2_HS_SCHEDULE_UFRAMES must be 8 times DWC2_LS_SCHEDULE_FRAMES (probably
710 * could be any multiple of 8 times DWC2_LS_SCHEDULE_FRAMES, but there might
711 * be bugs). The 8 comes from the USB spec: number of microframes per frame.
712 */
713#define DWC2_US_PER_UFRAME 125
714#define DWC2_HS_PERIODIC_US_PER_UFRAME 100
715
716#define DWC2_HS_SCHEDULE_UFRAMES 8
717#define DWC2_HS_SCHEDULE_US (DWC2_HS_SCHEDULE_UFRAMES * \
718 DWC2_HS_PERIODIC_US_PER_UFRAME)
719
720/*
721 * Constants related to low speed scheduling
722 *
723 * For high speed we schedule every 1us. For low speed that's a bit overkill,
724 * so we make up a unit called a "slice" that's worth 25us. There are 40
725 * slices in a full frame and we can schedule 36 of those (90%) for periodic
726 * transfers.
727 *
728 * Our low speed schedule can be as short as 1 frame or could be longer. When
729 * we only schedule 1 frame it means that we'll need to reserve a time every
730 * frame even for things that only transfer very rarely, so something that runs
731 * every 2048 frames will get time reserved in every frame. Our low speed
732 * schedule can be longer and we'll be able to handle more overlap, but that
733 * will come at increased memory cost and increased time to schedule.
734 *
735 * Note: one other advantage of a short low speed schedule is that if we mess
736 * up and miss scheduling we can jump in and use any of the slots that we
737 * happened to reserve.
738 *
739 * With 25 us per slice and 1 frame in the schedule, we only need 4 bytes for
740 * the schedule. There will be one schedule per TT.
741 *
742 * Requirements:
743 * - DWC2_US_PER_SLICE must evenly divide DWC2_LS_PERIODIC_US_PER_FRAME.
744 */
745#define DWC2_US_PER_SLICE 25
746#define DWC2_SLICES_PER_UFRAME (DWC2_US_PER_UFRAME / DWC2_US_PER_SLICE)
747
748#define DWC2_ROUND_US_TO_SLICE(us) \
749 (DIV_ROUND_UP((us), DWC2_US_PER_SLICE) * \
750 DWC2_US_PER_SLICE)
751
752#define DWC2_LS_PERIODIC_US_PER_FRAME \
753 900
754#define DWC2_LS_PERIODIC_SLICES_PER_FRAME \
755 (DWC2_LS_PERIODIC_US_PER_FRAME / \
756 DWC2_US_PER_SLICE)
757
758#define DWC2_LS_SCHEDULE_FRAMES 1
759#define DWC2_LS_SCHEDULE_SLICES (DWC2_LS_SCHEDULE_FRAMES * \
760 DWC2_LS_PERIODIC_SLICES_PER_FRAME)
761
56f5b1cf
PZ		 762/**
763 * struct dwc2_hsotg - Holds the state of the driver, including the non-periodic
764 * and periodic schedules
765 *
941fcce4
DN		 766 * These are common for both host and peripheral modes:
767 *
56f5b1cf
PZ		 768 * @dev: The struct device pointer
769 * @regs: Pointer to controller regs
9badec2f
MK		 770 * @hw_params: Parameters that were autodetected from the
771 * hardware registers
941fcce4 772 * @core_params: Parameters that define how the core should be configured
56f5b1cf
PZ		 773 * @op_state: The operational State, during transitions (a_host=>
774 * a_peripheral and b_device=>b_host) this may not match
775 * the core, but allows the software to determine
776 * transitions
c0155b9d
KY		 777 * @dr_mode: Requested mode of operation, one of following:
778 * - USB_DR_MODE_PERIPHERAL
779 * - USB_DR_MODE_HOST
780 * - USB_DR_MODE_OTG
09a75e85
MS		 781 * @hcd_enabled Host mode sub-driver initialization indicator.
782 * @gadget_enabled Peripheral mode sub-driver initialization indicator.
783 * @ll_hw_enabled Status of low-level hardware resources.
784 * @phy: The otg phy transceiver structure for phy control.
785 * @uphy: The otg phy transceiver structure for old USB phy control.
786 * @plat: The platform specific configuration data. This can be removed once
787 * all SoCs support usb transceiver.
788 * @supplies: Definition of USB power supplies
789 * @phyif: PHY interface width
941fcce4
DN		 790 * @lock: Spinlock that protects all the driver data structures
791 * @priv: Stores a pointer to the struct usb_hcd
56f5b1cf
PZ		 792 * @queuing_high_bandwidth: True if multiple packets of a high-bandwidth
793 * transfer are in process of being queued
794 * @srp_success: Stores status of SRP request in the case of a FS PHY
795 * with an I2C interface
796 * @wq_otg: Workqueue object used for handling of some interrupts
797 * @wf_otg: Work object for handling Connector ID Status Change
798 * interrupt
799 * @wkp_timer: Timer object for handling Wakeup Detected interrupt
800 * @lx_state: Lx state of connected device
d17ee77b
GH		 801 * @gregs_backup: Backup of global registers during suspend
802 * @dregs_backup: Backup of device registers during suspend
803 * @hregs_backup: Backup of host registers during suspend
941fcce4
DN		 804 *
805 * These are for host mode:
806 *
56f5b1cf
PZ		 807 * @flags: Flags for handling root port state changes
808 * @non_periodic_sched_inactive: Inactive QHs in the non-periodic schedule.
809 * Transfers associated with these QHs are not currently
810 * assigned to a host channel.
811 * @non_periodic_sched_active: Active QHs in the non-periodic schedule.
812 * Transfers associated with these QHs are currently
813 * assigned to a host channel.
814 * @non_periodic_qh_ptr: Pointer to next QH to process in the active
815 * non-periodic schedule
816 * @periodic_sched_inactive: Inactive QHs in the periodic schedule. This is a
817 * list of QHs for periodic transfers that are _not_
818 * scheduled for the next frame. Each QH in the list has an
819 * interval counter that determines when it needs to be
820 * scheduled for execution. This scheduling mechanism
821 * allows only a simple calculation for periodic bandwidth
822 * used (i.e. must assume that all periodic transfers may
823 * need to execute in the same frame). However, it greatly
824 * simplifies scheduling and should be sufficient for the
825 * vast majority of OTG hosts, which need to connect to a
826 * small number of peripherals at one time. Items move from
827 * this list to periodic_sched_ready when the QH interval
828 * counter is 0 at SOF.
829 * @periodic_sched_ready: List of periodic QHs that are ready for execution in
830 * the next frame, but have not yet been assigned to host
831 * channels. Items move from this list to
832 * periodic_sched_assigned as host channels become
833 * available during the current frame.
834 * @periodic_sched_assigned: List of periodic QHs to be executed in the next
835 * frame that are assigned to host channels. Items move
836 * from this list to periodic_sched_queued as the
837 * transactions for the QH are queued to the DWC_otg
838 * controller.
839 * @periodic_sched_queued: List of periodic QHs that have been queued for
840 * execution. Items move from this list to either
841 * periodic_sched_inactive or periodic_sched_ready when the
842 * channel associated with the transfer is released. If the
843 * interval for the QH is 1, the item moves to
844 * periodic_sched_ready because it must be rescheduled for
845 * the next frame. Otherwise, the item moves to
846 * periodic_sched_inactive.
c9c8ac01 847 * @split_order: List keeping track of channels doing splits, in order.
56f5b1cf
PZ		 848 * @periodic_usecs: Total bandwidth claimed so far for periodic transfers.
849 * This value is in microseconds per (micro)frame. The
850 * assumption is that all periodic transfers may occur in
851 * the same (micro)frame.
9f9f09b0
DA		 852 * @hs_periodic_bitmap: Bitmap used by the microframe scheduler any time the
853 * host is in high speed mode; low speed schedules are
854 * stored elsewhere since we need one per TT.
56f5b1cf
PZ		 855 * @frame_number: Frame number read from the core at SOF. The value ranges
856 * from 0 to HFNUM_MAX_FRNUM.
857 * @periodic_qh_count: Count of periodic QHs, if using several eps. Used for
858 * SOF enable/disable.
859 * @free_hc_list: Free host channels in the controller. This is a list of
860 * struct dwc2_host_chan items.
861 * @periodic_channels: Number of host channels assigned to periodic transfers.
862 * Currently assuming that there is a dedicated host
863 * channel for each periodic transaction and at least one
864 * host channel is available for non-periodic transactions.
865 * @non_periodic_channels: Number of host channels assigned to non-periodic
866 * transfers
20f2eb9c
DC		 867 * @available_host_channels Number of host channels available for the microframe
868 * scheduler to use
56f5b1cf
PZ		 869 * @hc_ptr_array: Array of pointers to the host channel descriptors.
870 * Allows accessing a host channel descriptor given the
871 * host channel number. This is useful in interrupt
872 * handlers.
873 * @status_buf: Buffer used for data received during the status phase of
874 * a control transfer.
875 * @status_buf_dma: DMA address for status_buf
876 * @start_work: Delayed work for handling host A-cable connection
877 * @reset_work: Delayed work for handling a port reset
56f5b1cf
PZ		 878 * @otg_port: OTG port number
879 * @frame_list: Frame list
880 * @frame_list_dma: Frame list DMA address
95105a99 881 * @frame_list_sz: Frame list size
3b5fcc9a
GH		 882 * @desc_gen_cache: Kmem cache for generic descriptors
883 * @desc_hsisoc_cache: Kmem cache for hs isochronous descriptors
941fcce4
DN		 884 *
885 * These are for peripheral mode:
886 *
887 * @driver: USB gadget driver
941fcce4
DN		 888 * @dedicated_fifos: Set if the hardware has dedicated IN-EP fifos.
889 * @num_of_eps: Number of available EPs (excluding EP0)
890 * @debug_root: Root directrory for debugfs.
891 * @debug_file: Main status file for debugfs.
9e14d0a5 892 * @debug_testmode: Testmode status file for debugfs.
941fcce4
DN		 893 * @debug_fifo: FIFO status file for debugfs.
894 * @ep0_reply: Request used for ep0 reply.
895 * @ep0_buff: Buffer for EP0 reply data, if needed.
896 * @ctrl_buff: Buffer for EP0 control requests.
897 * @ctrl_req: Request for EP0 control packets.
fe0b94ab 898 * @ep0_state: EP0 control transfers state
9e14d0a5 899 * @test_mode: USB test mode requested by the host
0f6b80c0
VA		 900 * @setup_desc_dma: EP0 setup stage desc chain DMA address
901 * @setup_desc: EP0 setup stage desc chain pointer
902 * @ctrl_in_desc_dma: EP0 IN data phase desc chain DMA address
903 * @ctrl_in_desc: EP0 IN data phase desc chain pointer
904 * @ctrl_out_desc_dma: EP0 OUT data phase desc chain DMA address
905 * @ctrl_out_desc: EP0 OUT data phase desc chain pointer
941fcce4 906 * @eps: The endpoints being supplied to the gadget framework
56f5b1cf
PZ		 907 */
908struct dwc2_hsotg {
909 struct device *dev;
910 void __iomem *regs;
9badec2f
MK		 911 /** Params detected from hardware */
912 struct dwc2_hw_params hw_params;
913 /** Params to actually use */
bea8e86c 914 struct dwc2_core_params params;
56f5b1cf 915 enum usb_otg_state op_state;
c0155b9d 916 enum usb_dr_mode dr_mode;
e39af88f
MS		 917 unsigned int hcd_enabled:1;
918 unsigned int gadget_enabled:1;
09a75e85 919 unsigned int ll_hw_enabled:1;
56f5b1cf 920
941fcce4
DN		 921 struct phy *phy;
922 struct usb_phy *uphy;
09a75e85 923 struct dwc2_hsotg_plat *plat;
1f91b4cc 924 struct regulator_bulk_data supplies[ARRAY_SIZE(dwc2_hsotg_supply_names)];
09a75e85 925 u32 phyif;
941fcce4
DN		 926
927 spinlock_t lock;
928 void *priv;
929 int irq;
930 struct clk *clk;
83f8da56 931 struct reset_control *reset;
941fcce4 932
56f5b1cf
PZ		 933 unsigned int queuing_high_bandwidth:1;
934 unsigned int srp_success:1;
935
936 struct workqueue_struct *wq_otg;
937 struct work_struct wf_otg;
938 struct timer_list wkp_timer;
939 enum dwc2_lx_state lx_state;
cc1e204c
MYK		 940 struct dwc2_gregs_backup gr_backup;
941 struct dwc2_dregs_backup dr_backup;
942 struct dwc2_hregs_backup hr_backup;
56f5b1cf 943
941fcce4 944 struct dentry *debug_root;
563cf017 945 struct debugfs_regset32 *regset;
941fcce4
DN		 946
947 /* DWC OTG HW Release versions */
948#define DWC2_CORE_REV_2_71a 0x4f54271a
949#define DWC2_CORE_REV_2_90a 0x4f54290a
950#define DWC2_CORE_REV_2_92a 0x4f54292a
951#define DWC2_CORE_REV_2_94a 0x4f54294a
952#define DWC2_CORE_REV_3_00a 0x4f54300a
fef6bc37 953#define DWC2_CORE_REV_3_10a 0x4f54310a
1e6b98eb
VM		 954#define DWC2_FS_IOT_REV_1_00a 0x5531100a
955#define DWC2_HS_IOT_REV_1_00a 0x5532100a
941fcce4
DN		 956
957#if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
56f5b1cf
PZ		 958 union dwc2_hcd_internal_flags {
959 u32 d32;
960 struct {
961 unsigned port_connect_status_change:1;
962 unsigned port_connect_status:1;
963 unsigned port_reset_change:1;
964 unsigned port_enable_change:1;
965 unsigned port_suspend_change:1;
966 unsigned port_over_current_change:1;
967 unsigned port_l1_change:1;
fd4850cf 968 unsigned reserved:25;
56f5b1cf
PZ		 969 } b;
970 } flags;
971
972 struct list_head non_periodic_sched_inactive;
973 struct list_head non_periodic_sched_active;
974 struct list_head *non_periodic_qh_ptr;
975 struct list_head periodic_sched_inactive;
976 struct list_head periodic_sched_ready;
977 struct list_head periodic_sched_assigned;
978 struct list_head periodic_sched_queued;
c9c8ac01 979 struct list_head split_order;
56f5b1cf 980 u16 periodic_usecs;
9f9f09b0
DA		 981 unsigned long hs_periodic_bitmap[
982 DIV_ROUND_UP(DWC2_HS_SCHEDULE_US, BITS_PER_LONG)];
56f5b1cf
PZ		 983 u16 frame_number;
984 u16 periodic_qh_count;
734643df 985 bool bus_suspended;
fbb9e22b 986 bool new_connection;
56f5b1cf 987
483bb254
DA		 988 u16 last_frame_num;
989
56f5b1cf
PZ		 990#ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
991#define FRAME_NUM_ARRAY_SIZE 1000
56f5b1cf
PZ		 992 u16 *frame_num_array;
993 u16 *last_frame_num_array;
994 int frame_num_idx;
995 int dumped_frame_num_array;
996#endif
997
998 struct list_head free_hc_list;
999 int periodic_channels;
1000 int non_periodic_channels;
20f2eb9c 1001 int available_host_channels;
56f5b1cf
PZ		 1002 struct dwc2_host_chan *hc_ptr_array[MAX_EPS_CHANNELS];
1003 u8 *status_buf;
1004 dma_addr_t status_buf_dma;
1005#define DWC2_HCD_STATUS_BUF_SIZE 64
1006
1007 struct delayed_work start_work;
1008 struct delayed_work reset_work;
56f5b1cf
PZ		 1009 u8 otg_port;
1010 u32 *frame_list;
1011 dma_addr_t frame_list_dma;
95105a99 1012 u32 frame_list_sz;
3b5fcc9a
GH		 1013 struct kmem_cache *desc_gen_cache;
1014 struct kmem_cache *desc_hsisoc_cache;
56f5b1cf 1015
56f5b1cf
PZ		 1016#ifdef DEBUG
1017 u32 frrem_samples;
1018 u64 frrem_accum;
1019
1020 u32 hfnum_7_samples_a;
1021 u64 hfnum_7_frrem_accum_a;
1022 u32 hfnum_0_samples_a;
1023 u64 hfnum_0_frrem_accum_a;
1024 u32 hfnum_other_samples_a;
1025 u64 hfnum_other_frrem_accum_a;
1026
1027 u32 hfnum_7_samples_b;
1028 u64 hfnum_7_frrem_accum_b;
1029 u32 hfnum_0_samples_b;
1030 u64 hfnum_0_frrem_accum_b;
1031 u32 hfnum_other_samples_b;
1032 u64 hfnum_other_frrem_accum_b;
1033#endif
941fcce4
DN		 1034#endif /* CONFIG_USB_DWC2_HOST || CONFIG_USB_DWC2_DUAL_ROLE */
1035
1036#if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
1037 /* Gadget structures */
1038 struct usb_gadget_driver *driver;
941fcce4
DN		 1039 int fifo_mem;
1040 unsigned int dedicated_fifos:1;
1041 unsigned char num_of_eps;
1042 u32 fifo_map;
1043
1044 struct usb_request *ep0_reply;
1045 struct usb_request *ctrl_req;
3f95001d
MYK		 1046 void *ep0_buff;
1047 void *ctrl_buff;
fe0b94ab 1048 enum dwc2_ep0_state ep0_state;
9e14d0a5 1049 u8 test_mode;
941fcce4 1050
0f6b80c0
VA		 1051 dma_addr_t setup_desc_dma[2];
1052 struct dwc2_dma_desc *setup_desc[2];
1053 dma_addr_t ctrl_in_desc_dma;
1054 struct dwc2_dma_desc *ctrl_in_desc;
1055 dma_addr_t ctrl_out_desc_dma;
1056 struct dwc2_dma_desc *ctrl_out_desc;
1057
941fcce4 1058 struct usb_gadget gadget;
dc6e69e6 1059 unsigned int enabled:1;
4ace06e8 1060 unsigned int connected:1;
1f91b4cc
FB		 1061 struct dwc2_hsotg_ep *eps_in[MAX_EPS_CHANNELS];
1062 struct dwc2_hsotg_ep *eps_out[MAX_EPS_CHANNELS];
941fcce4 1063#endif /* CONFIG_USB_DWC2_PERIPHERAL || CONFIG_USB_DWC2_DUAL_ROLE */
56f5b1cf
PZ		 1064};
1065
1066/* Reasons for halting a host channel */
1067enum dwc2_halt_status {
1068 DWC2_HC_XFER_NO_HALT_STATUS,
1069 DWC2_HC_XFER_COMPLETE,
1070 DWC2_HC_XFER_URB_COMPLETE,
1071 DWC2_HC_XFER_ACK,
1072 DWC2_HC_XFER_NAK,
1073 DWC2_HC_XFER_NYET,
1074 DWC2_HC_XFER_STALL,
1075 DWC2_HC_XFER_XACT_ERR,
1076 DWC2_HC_XFER_FRAME_OVERRUN,
1077 DWC2_HC_XFER_BABBLE_ERR,
1078 DWC2_HC_XFER_DATA_TOGGLE_ERR,
1079 DWC2_HC_XFER_AHB_ERR,
1080 DWC2_HC_XFER_PERIODIC_INCOMPLETE,
1081 DWC2_HC_XFER_URB_DEQUEUE,
1082};
1083
1e6b98eb
VM		 1084/* Core version information */
1085static inline bool dwc2_is_iot(struct dwc2_hsotg *hsotg)
1086{
1087 return (hsotg->hw_params.snpsid & 0xfff00000) == 0x55300000;
1088}
1089
1090static inline bool dwc2_is_fs_iot(struct dwc2_hsotg *hsotg)
1091{
1092 return (hsotg->hw_params.snpsid & 0xffff0000) == 0x55310000;
1093}
1094
1095static inline bool dwc2_is_hs_iot(struct dwc2_hsotg *hsotg)
1096{
1097 return (hsotg->hw_params.snpsid & 0xffff0000) == 0x55320000;
1098}
1099
56f5b1cf
PZ		 1100/*
1101 * The following functions support initialization of the core driver component
1102 * and the DWC_otg controller
1103 */
b5d308ab 1104extern int dwc2_core_reset(struct dwc2_hsotg *hsotg);
6d58f346 1105extern int dwc2_core_reset_and_force_dr_mode(struct dwc2_hsotg *hsotg);
d17ee77b
GH		 1106extern int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg);
1107extern int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, bool restore);
56f5b1cf 1108
323230ef
JY		 1109bool dwc2_force_mode_if_needed(struct dwc2_hsotg *hsotg, bool host);
1110void dwc2_clear_force_mode(struct dwc2_hsotg *hsotg);
09c96980
JY		 1111void dwc2_force_dr_mode(struct dwc2_hsotg *hsotg);
1112
057715f2 1113extern bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg);
56f5b1cf
PZ		 1114
1115/*
1116 * Common core Functions.
1117 * The following functions support managing the DWC_otg controller in either
1118 * device or host mode.
1119 */
1120extern void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes);
1121extern void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num);
1122extern void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg);
1123
56f5b1cf
PZ		 1124extern void dwc2_enable_global_interrupts(struct dwc2_hsotg *hcd);
1125extern void dwc2_disable_global_interrupts(struct dwc2_hsotg *hcd);
1126
1127/* This function should be called on every hardware interrupt. */
1128extern irqreturn_t dwc2_handle_common_intr(int irq, void *dev);
1129
323230ef
JY		 1130/* The device ID match table */
1131extern const struct of_device_id dwc2_of_match_table[];
1132
09a75e85
MS		 1133extern int dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg);
1134extern int dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg);
ecb176c6 1135
334bbd4e 1136/* Parameters */
c1d286cf 1137int dwc2_get_hwparams(struct dwc2_hsotg *hsotg);
334bbd4e
JY		 1138int dwc2_init_params(struct dwc2_hsotg *hsotg);
1139
6bea9620
JY		 1140/*
1141 * The following functions check the controller's OTG operation mode
1142 * capability (GHWCFG2.OTG_MODE).
1143 *
1144 * These functions can be used before the internal hsotg->hw_params
1145 * are read in and cached so they always read directly from the
1146 * GHWCFG2 register.
1147 */
1148unsigned dwc2_op_mode(struct dwc2_hsotg *hsotg);
1149bool dwc2_hw_is_otg(struct dwc2_hsotg *hsotg);
1150bool dwc2_hw_is_host(struct dwc2_hsotg *hsotg);
1151bool dwc2_hw_is_device(struct dwc2_hsotg *hsotg);
1152
1696d5ab
JY		 1153/*
1154 * Returns the mode of operation, host or device
1155 */
1156static inline int dwc2_is_host_mode(struct dwc2_hsotg *hsotg)
1157{
1158 return (dwc2_readl(hsotg->regs + GINTSTS) & GINTSTS_CURMODE_HOST) != 0;
1159}
1160static inline int dwc2_is_device_mode(struct dwc2_hsotg *hsotg)
1161{
1162 return (dwc2_readl(hsotg->regs + GINTSTS) & GINTSTS_CURMODE_HOST) == 0;
1163}
1164
56f5b1cf
PZ		 1165/*
1166 * Dump core registers and SPRAM
1167 */
1168extern void dwc2_dump_dev_registers(struct dwc2_hsotg *hsotg);
1169extern void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg);
1170extern void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg);
1171
1172/*
1173 * Return OTG version - either 1.3 or 2.0
1174 */
1175extern u16 dwc2_get_otg_version(struct dwc2_hsotg *hsotg);
1176
117777b2
DN		 1177/* Gadget defines */
1178#if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
1f91b4cc
FB		 1179extern int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg);
1180extern int dwc2_hsotg_suspend(struct dwc2_hsotg *dwc2);
1181extern int dwc2_hsotg_resume(struct dwc2_hsotg *dwc2);
117777b2 1182extern int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq);
1f91b4cc 1183extern void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2,
643cc4de 1184 bool reset);
1f91b4cc
FB		 1185extern void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg);
1186extern void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2);
1187extern int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode);
f81f46e1 1188#define dwc2_is_device_connected(hsotg) (hsotg->connected)
58e52ff6
JY		 1189int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg);
1190int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg);
117777b2 1191#else
1f91b4cc 1192static inline int dwc2_hsotg_remove(struct dwc2_hsotg *dwc2)
117777b2 1193{ return 0; }
1f91b4cc 1194static inline int dwc2_hsotg_suspend(struct dwc2_hsotg *dwc2)
117777b2 1195{ return 0; }
1f91b4cc 1196static inline int dwc2_hsotg_resume(struct dwc2_hsotg *dwc2)
117777b2
DN		 1197{ return 0; }
1198static inline int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq)
1199{ return 0; }
1f91b4cc 1200static inline void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2,
643cc4de 1201 bool reset) {}
1f91b4cc
FB		 1202static inline void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg) {}
1203static inline void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2) {}
1204static inline int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg,
f91eea44
MYK		 1205 int testmode)
1206{ return 0; }
f81f46e1 1207#define dwc2_is_device_connected(hsotg) (0)
58e52ff6
JY		 1208static inline int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg)
1209{ return 0; }
1210static inline int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg)
1211{ return 0; }
117777b2
DN		 1212#endif
1213
1214#if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
1215extern int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg);
fae4e826 1216extern int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg, int us);
6a659531
DA		 1217extern void dwc2_hcd_connect(struct dwc2_hsotg *hsotg);
1218extern void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force);
117777b2 1219extern void dwc2_hcd_start(struct dwc2_hsotg *hsotg);
58e52ff6
JY		 1220int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg);
1221int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg);
117777b2 1222#else
117777b2
DN		 1223static inline int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg)
1224{ return 0; }
fae4e826
DA		 1225static inline int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg,
1226 int us)
1227{ return 0; }
6a659531
DA		 1228static inline void dwc2_hcd_connect(struct dwc2_hsotg *hsotg) {}
1229static inline void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force) {}
117777b2
DN		 1230static inline void dwc2_hcd_start(struct dwc2_hsotg *hsotg) {}
1231static inline void dwc2_hcd_remove(struct dwc2_hsotg *hsotg) {}
ecb176c6 1232static inline int dwc2_hcd_init(struct dwc2_hsotg *hsotg, int irq)
117777b2 1233{ return 0; }
58e52ff6
JY		 1234static inline int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg)
1235{ return 0; }
1236static inline int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg)
1237{ return 0; }
1238
117777b2
DN		 1239#endif
1240
56f5b1cf 1241#endif /* __DWC2_CORE_H__ */
Linux 6.x block layer and io_uring tree(s)