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USB: dwc2: Add OTG support for Ingenic SoCs.
[linux-block.git] / drivers / usb / dwc2 / core.h
CommitLineData
bdefa3ba 1/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
56f5b1cf
PZ		 2/*
3 * core.h - DesignWare HS OTG Controller common declarations
4 *
5 * Copyright (C) 2004-2013 Synopsys, Inc.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions, and the following disclaimer,
12 * without modification.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. The names of the above-listed copyright holders may not be used
17 * to endorse or promote products derived from this software without
18 * specific prior written permission.
19 *
20 * ALTERNATIVELY, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") as published by the Free Software
22 * Foundation; either version 2 of the License, or (at your option) any
23 * later version.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
26 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
27 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
29 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
30 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
31 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
32 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
33 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
34 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
35 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 */
37
38#ifndef __DWC2_CORE_H__
39#define __DWC2_CORE_H__
40
2e5db2c0 41#include <linux/acpi.h>
f7c0b143
DN		 42#include <linux/phy/phy.h>
43#include <linux/regulator/consumer.h>
44#include <linux/usb/gadget.h>
45#include <linux/usb/otg.h>
56f5b1cf
PZ		 46#include <linux/usb/phy.h>
47#include "hw.h"
48
74fc4a75
DA		 49/*
50 * Suggested defines for tracers:
51 * - no_printk: Disable tracing
52 * - pr_info: Print this info to the console
53 * - trace_printk: Print this info to trace buffer (good for verbose logging)
54 */
55
56#define DWC2_TRACE_SCHEDULER no_printk
57#define DWC2_TRACE_SCHEDULER_VB no_printk
58
59/* Detailed scheduler tracing, but won't overwhelm console */
60#define dwc2_sch_dbg(hsotg, fmt, ...) \
61 DWC2_TRACE_SCHEDULER(pr_fmt("%s: SCH: " fmt), \
62 dev_name(hsotg->dev), ##__VA_ARGS__)
63
64/* Verbose scheduler tracing */
65#define dwc2_sch_vdbg(hsotg, fmt, ...) \
66 DWC2_TRACE_SCHEDULER_VB(pr_fmt("%s: SCH: " fmt), \
67 dev_name(hsotg->dev), ##__VA_ARGS__)
68
56f5b1cf
PZ		 69/* Maximum number of Endpoints/HostChannels */
70#define MAX_EPS_CHANNELS 16
71
1f91b4cc
FB		 72/* dwc2-hsotg declarations */
73static const char * const dwc2_hsotg_supply_names[] = {
f7c0b143
DN		 74 "vusb_d", /* digital USB supply, 1.2V */
75 "vusb_a", /* analog USB supply, 1.1V */
76};
77
b98866c2
JY		 78#define DWC2_NUM_SUPPLIES ARRAY_SIZE(dwc2_hsotg_supply_names)
79
f7c0b143
DN		 80/*
81 * EP0_MPS_LIMIT
82 *
83 * Unfortunately there seems to be a limit of the amount of data that can
84 * be transferred by IN transactions on EP0. This is either 127 bytes or 3
85 * packets (which practically means 1 packet and 63 bytes of data) when the
86 * MPS is set to 64.
87 *
88 * This means if we are wanting to move >127 bytes of data, we need to
89 * split the transactions up, but just doing one packet at a time does
90 * not work (this may be an implicit DATA0 PID on first packet of the
91 * transaction) and doing 2 packets is outside the controller's limits.
92 *
93 * If we try to lower the MPS size for EP0, then no transfers work properly
94 * for EP0, and the system will fail basic enumeration. As no cause for this
95 * has currently been found, we cannot support any large IN transfers for
96 * EP0.
97 */
98#define EP0_MPS_LIMIT 64
99
941fcce4 100struct dwc2_hsotg;
1f91b4cc 101struct dwc2_hsotg_req;
f7c0b143
DN		 102
103/**
1f91b4cc 104 * struct dwc2_hsotg_ep - driver endpoint definition.
f7c0b143
DN		 105 * @ep: The gadget layer representation of the endpoint.
106 * @name: The driver generated name for the endpoint.
107 * @queue: Queue of requests for this endpoint.
108 * @parent: Reference back to the parent device structure.
109 * @req: The current request that the endpoint is processing. This is
110 * used to indicate an request has been loaded onto the endpoint
111 * and has yet to be completed (maybe due to data move, or simply
112 * awaiting an ack from the core all the data has been completed).
113 * @debugfs: File entry for debugfs file for this endpoint.
f7c0b143
DN		 114 * @dir_in: Set to true if this endpoint is of the IN direction, which
115 * means that it is sending data to the Host.
75a41ce4 116 * @map_dir: Set to the value of dir_in when the DMA buffer is mapped.
f7c0b143
DN		 117 * @index: The index for the endpoint registers.
118 * @mc: Multi Count - number of transactions per microframe
6fb914d7 119 * @interval: Interval for periodic endpoints, in frames or microframes.
f7c0b143
DN		 120 * @name: The name array passed to the USB core.
121 * @halted: Set if the endpoint has been halted.
122 * @periodic: Set if this is a periodic ep, such as Interrupt
123 * @isochronous: Set if this is a isochronous ep
8a20fa45 124 * @send_zlp: Set if we need to send a zero-length packet.
b833ce15 125 * @wedged: Set if ep is wedged.
5f54c54b
VA		 126 * @desc_list_dma: The DMA address of descriptor chain currently in use.
127 * @desc_list: Pointer to descriptor DMA chain head currently in use.
128 * @desc_count: Count of entries within the DMA descriptor chain of EP.
ab7d2192 129 * @next_desc: index of next free descriptor in the ISOC chain under SW control.
729cac69 130 * @compl_desc: index of next descriptor to be completed by xFerComplete
f7c0b143
DN		 131 * @total_data: The total number of data bytes done.
132 * @fifo_size: The size of the FIFO (for periodic IN endpoints)
6fb914d7 133 * @fifo_index: For Dedicated FIFO operation, only FIFO0 can be used for EP0.
f7c0b143
DN		 134 * @fifo_load: The amount of data loaded into the FIFO (periodic IN)
135 * @last_load: The offset of data for the last start of request.
136 * @size_loaded: The last loaded size for DxEPTSIZE for periodic IN
92d1635d
VM		 137 * @target_frame: Targeted frame num to setup next ISOC transfer
138 * @frame_overrun: Indicates SOF number overrun in DSTS
f7c0b143 139 *
c1aa81da 140 * This is the driver's state for each registered endpoint, allowing it
f7c0b143
DN		 141 * to keep track of transactions that need doing. Each endpoint has a
142 * lock to protect the state, to try and avoid using an overall lock
143 * for the host controller as much as possible.
144 *
145 * For periodic IN endpoints, we have fifo_size and fifo_load to try
146 * and keep track of the amount of data in the periodic FIFO for each
147 * of these as we don't have a status register that tells us how much
148 * is in each of them. (note, this may actually be useless information
149 * as in shared-fifo mode periodic in acts like a single-frame packet
150 * buffer than a fifo)
151 */
1f91b4cc 152struct dwc2_hsotg_ep {
f7c0b143
DN		 153 struct usb_ep ep;
154 struct list_head queue;
941fcce4 155 struct dwc2_hsotg *parent;
1f91b4cc 156 struct dwc2_hsotg_req *req;
f7c0b143
DN		 157 struct dentry *debugfs;
158
159 unsigned long total_data;
160 unsigned int size_loaded;
161 unsigned int last_load;
162 unsigned int fifo_load;
163 unsigned short fifo_size;
b203d0a2 164 unsigned short fifo_index;
f7c0b143
DN		 165
166 unsigned char dir_in;
75a41ce4 167 unsigned char map_dir;
f7c0b143
DN		 168 unsigned char index;
169 unsigned char mc;
12814a3f 170 u16 interval;
f7c0b143
DN		 171
172 unsigned int halted:1;
173 unsigned int periodic:1;
174 unsigned int isochronous:1;
8a20fa45 175 unsigned int send_zlp:1;
b833ce15 176 unsigned int wedged:1;
92d1635d
VM		 177 unsigned int target_frame;
178#define TARGET_FRAME_INITIAL 0xFFFFFFFF
179 bool frame_overrun;
f7c0b143 180
5f54c54b
VA		 181 dma_addr_t desc_list_dma;
182 struct dwc2_dma_desc *desc_list;
183 u8 desc_count;
184
ab7d2192 185 unsigned int next_desc;
729cac69 186 unsigned int compl_desc;
ab7d2192 187
f7c0b143
DN		 188 char name[10];
189};
190
f7c0b143 191/**
1f91b4cc 192 * struct dwc2_hsotg_req - data transfer request
f7c0b143
DN		 193 * @req: The USB gadget request
194 * @queue: The list of requests for the endpoint this is queued for.
7d24c1b5 195 * @saved_req_buf: variable to save req.buf when bounce buffers are used.
f7c0b143 196 */
1f91b4cc 197struct dwc2_hsotg_req {
f7c0b143
DN		 198 struct usb_request req;
199 struct list_head queue;
7d24c1b5 200 void *saved_req_buf;
f7c0b143
DN		 201};
202
b98866c2
JY		 203#if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \
204 IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
f7c0b143
DN		 205#define call_gadget(_hs, _entry) \
206do { \
207 if ((_hs)->gadget.speed != USB_SPEED_UNKNOWN && \
208 (_hs)->driver && (_hs)->driver->_entry) { \
209 spin_unlock(&_hs->lock); \
210 (_hs)->driver->_entry(&(_hs)->gadget); \
211 spin_lock(&_hs->lock); \
212 } \
213} while (0)
941fcce4
DN		 214#else
215#define call_gadget(_hs, _entry) do {} while (0)
216#endif
f7c0b143 217
56f5b1cf
PZ		 218struct dwc2_hsotg;
219struct dwc2_host_chan;
220
221/* Device States */
222enum dwc2_lx_state {
223 DWC2_L0, /* On state */
224 DWC2_L1, /* LPM sleep state */
225 DWC2_L2, /* USB suspend state */
226 DWC2_L3, /* Off state */
227};
228
fe0b94ab
MYK		 229/* Gadget ep0 states */
230enum dwc2_ep0_state {
231 DWC2_EP0_SETUP,
232 DWC2_EP0_DATA_IN,
233 DWC2_EP0_DATA_OUT,
234 DWC2_EP0_STATUS_IN,
235 DWC2_EP0_STATUS_OUT,
236};
237
56f5b1cf
PZ		 238/**
239 * struct dwc2_core_params - Parameters for configuring the core
240 *
f5c8a6cb
FG		 241 * @otg_caps: Specifies the OTG capabilities. OTG caps from the platform parameters,
242 * used to setup the:
243 * - HNP and SRP capable
244 * - SRP Only capable
245 * - No HNP/SRP capable (always available)
246 * Defaults to best available option
247 * - OTG revision number the device is compliant with, in binary-coded
248 * decimal (i.e. 2.0 is 0200H). (see struct usb_otg_caps)
e7839f99 249 * @host_dma: Specifies whether to use slave or DMA mode for accessing
56f5b1cf
PZ		 250 * the data FIFOs. The driver will automatically detect the
251 * value for this parameter if none is specified.
91121c10 252 * 0 - Slave (always available)
56f5b1cf
PZ		 253 * 1 - DMA (default, if available)
254 * @dma_desc_enable: When DMA mode is enabled, specifies whether to use
255 * address DMA mode or descriptor DMA mode for accessing
256 * the data FIFOs. The driver will automatically detect the
257 * value for this if none is specified.
258 * 0 - Address DMA
259 * 1 - Descriptor DMA (default, if available)
fbb9e22b
MYK		 260 * @dma_desc_fs_enable: When DMA mode is enabled, specifies whether to use
261 * address DMA mode or descriptor DMA mode for accessing
262 * the data FIFOs in Full Speed mode only. The driver
263 * will automatically detect the value for this if none is
264 * specified.
265 * 0 - Address DMA
266 * 1 - Descriptor DMA in FS (default, if available)
56f5b1cf
PZ		 267 * @speed: Specifies the maximum speed of operation in host and
268 * device mode. The actual speed depends on the speed of
269 * the attached device and the value of phy_type.
91121c10
MK		 270 * 0 - High Speed
271 * (default when phy_type is UTMI+ or ULPI)
56f5b1cf 272 * 1 - Full Speed
91121c10 273 * (default when phy_type is Full Speed)
56f5b1cf 274 * @enable_dynamic_fifo: 0 - Use coreConsultant-specified FIFO size parameters
91121c10 275 * 1 - Allow dynamic FIFO sizing (default, if available)
725acc86 276 * @en_multiple_tx_fifo: Specifies whether dedicated per-endpoint transmit FIFOs
c1d286cf
JY		 277 * are enabled for non-periodic IN endpoints in device
278 * mode.
56f5b1cf
PZ		 279 * @host_rx_fifo_size: Number of 4-byte words in the Rx FIFO in host mode when
280 * dynamic FIFO sizing is enabled
91121c10
MK		 281 * 16 to 32768
282 * Actual maximum value is autodetected and also
283 * the default.
56f5b1cf
PZ		 284 * @host_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO
285 * in host mode when dynamic FIFO sizing is enabled
91121c10
MK		 286 * 16 to 32768
287 * Actual maximum value is autodetected and also
288 * the default.
56f5b1cf
PZ		 289 * @host_perio_tx_fifo_size: Number of 4-byte words in the periodic Tx FIFO in
290 * host mode when dynamic FIFO sizing is enabled
91121c10
MK		 291 * 16 to 32768
292 * Actual maximum value is autodetected and also
293 * the default.
56f5b1cf 294 * @max_transfer_size: The maximum transfer size supported, in bytes
91121c10
MK		 295 * 2047 to 65,535
296 * Actual maximum value is autodetected and also
297 * the default.
56f5b1cf 298 * @max_packet_count: The maximum number of packets in a transfer
91121c10
MK		 299 * 15 to 511
300 * Actual maximum value is autodetected and also
301 * the default.
56f5b1cf 302 * @host_channels: The number of host channel registers to use
91121c10
MK		 303 * 1 to 16
304 * Actual maximum value is autodetected and also
305 * the default.
56f5b1cf
PZ		 306 * @phy_type: Specifies the type of PHY interface to use. By default,
307 * the driver will automatically detect the phy_type.
91121c10
MK		 308 * 0 - Full Speed Phy
309 * 1 - UTMI+ Phy
310 * 2 - ULPI Phy
311 * Defaults to best available option (2, 1, then 0)
56f5b1cf
PZ		 312 * @phy_utmi_width: Specifies the UTMI+ Data Width (in bits). This parameter
313 * is applicable for a phy_type of UTMI+ or ULPI. (For a
314 * ULPI phy_type, this parameter indicates the data width
315 * between the MAC and the ULPI Wrapper.) Also, this
316 * parameter is applicable only if the OTG_HSPHY_WIDTH cC
317 * parameter was set to "8 and 16 bits", meaning that the
318 * core has been configured to work at either data path
319 * width.
91121c10 320 * 8 or 16 (default 16 if available)
56f5b1cf
PZ		 321 * @phy_ulpi_ddr: Specifies whether the ULPI operates at double or single
322 * data rate. This parameter is only applicable if phy_type
323 * is ULPI.
324 * 0 - single data rate ULPI interface with 8 bit wide
325 * data bus (default)
326 * 1 - double data rate ULPI interface with 4 bit wide
327 * data bus
328 * @phy_ulpi_ext_vbus: For a ULPI phy, specifies whether to use the internal or
329 * external supply to drive the VBus
91121c10
MK		 330 * 0 - Internal supply (default)
331 * 1 - External supply
56f5b1cf
PZ		 332 * @i2c_enable: Specifies whether to use the I2Cinterface for a full
333 * speed PHY. This parameter is only applicable if phy_type
334 * is FS.
335 * 0 - No (default)
336 * 1 - Yes
6fb914d7 337 * @ipg_isoc_en: Indicates the IPG supports is enabled or disabled.
b43ebc96
GT		 338 * 0 - Disable (default)
339 * 1 - Enable
6fb914d7
GT		 340 * @acg_enable: For enabling Active Clock Gating in the controller
341 * 0 - No
342 * 1 - Yes
91121c10
MK		 343 * @ulpi_fs_ls: Make ULPI phy operate in FS/LS mode only
344 * 0 - No (default)
345 * 1 - Yes
725acc86
PZ		 346 * @host_support_fs_ls_low_power: Specifies whether low power mode is supported
347 * when attached to a Full Speed or Low Speed device in
348 * host mode.
349 * 0 - Don't support low power mode (default)
350 * 1 - Support low power mode
351 * @host_ls_low_power_phy_clk: Specifies the PHY clock rate in low power mode
91121c10
MK		 352 * when connected to a Low Speed device in host
353 * mode. This parameter is applicable only if
354 * host_support_fs_ls_low_power is enabled.
725acc86 355 * 0 - 48 MHz
91121c10 356 * (default when phy_type is UTMI+ or ULPI)
725acc86 357 * 1 - 6 MHz
91121c10 358 * (default when phy_type is Full Speed)
b11633c4
DN		 359 * @oc_disable: Flag to disable overcurrent condition.
360 * 0 - Allow overcurrent condition to get detected
361 * 1 - Disable overcurrent condtion to get detected
91121c10
MK		 362 * @ts_dline: Enable Term Select Dline pulsing
363 * 0 - No (default)
364 * 1 - Yes
365 * @reload_ctl: Allow dynamic reloading of HFIR register during runtime
366 * 0 - No (default for core < 2.92a)
367 * 1 - Yes (default for core >= 2.92a)
4d3190e1
PZ		 368 * @ahbcfg: This field allows the default value of the GAHBCFG
369 * register to be overridden
91121c10 370 * -1 - GAHBCFG value will be set to 0x06
1b52d2fa 371 * (INCR, default)
4d3190e1
PZ		 372 * all others - GAHBCFG value will be overridden with
373 * this value
91121c10
MK		 374 * Not all bits can be controlled like this, the
375 * bits defined by GAHBCFG_CTRL_MASK are controlled
376 * by the driver and are ignored in this
377 * configuration value.
20f2eb9c 378 * @uframe_sched: True to enable the microframe scheduler
a6d249d8
GH		 379 * @external_id_pin_ctl: Specifies whether ID pin is handled externally.
380 * Disable CONIDSTSCHNG controller interrupt in such
381 * case.
382 * 0 - No (default)
383 * 1 - Yes
41ba9b9b
VM		 384 * @power_down: Specifies whether the controller support power_down.
385 * If power_down is enabled, the controller will enter
386 * power_down in both peripheral and host mode when
285046aa
GH		 387 * needed.
388 * 0 - No (default)
631a2310
VM		 389 * 1 - Partial power down
390 * 2 - Hibernation
c4a0f7a6
MS		 391 * @no_clock_gating: Specifies whether to avoid clock gating feature.
392 * 0 - No (use clock gating)
393 * 1 - Yes (avoid it)
6f80b6de
SA		 394 * @lpm: Enable LPM support.
395 * 0 - No
396 * 1 - Yes
397 * @lpm_clock_gating: Enable core PHY clock gating.
398 * 0 - No
399 * 1 - Yes
400 * @besl: Enable LPM Errata support.
401 * 0 - No
402 * 1 - Yes
403 * @hird_threshold_en: HIRD or HIRD Threshold enable.
404 * 0 - No
405 * 1 - Yes
406 * @hird_threshold: Value of BESL or HIRD Threshold.
f3a61e4e
GT		 407 * @ref_clk_per: Indicates in terms of pico seconds the period
408 * of ref_clk.
409 * 62500 - 16MHz
410 * 58823 - 17MHz
411 * 52083 - 19.2MHz
412 * 50000 - 20MHz
413 * 41666 - 24MHz
414 * 33333 - 30MHz (default)
415 * 25000 - 40MHz
416 * @sof_cnt_wkup_alert: Indicates in term of number of SOF's after which
417 * the controller should generate an interrupt if the
418 * device had been in L1 state until that period.
419 * This is used by SW to initiate Remote WakeUp in the
420 * controller so as to sync to the uF number from the host.
e35b1350
BH		 421 * @activate_stm_fs_transceiver: Activate internal transceiver using GGPIO
422 * register.
423 * 0 - Deactivate the transceiver (default)
424 * 1 - Activate the transceiver
a415083a
AD		 425 * @activate_stm_id_vb_detection: Activate external ID pin and Vbus level
426 * detection using GGPIO register.
427 * 0 - Deactivate the external level detection (default)
428 * 1 - Activate the external level detection
d712b725
ZY		 429 * @activate_ingenic_overcurrent_detection: Activate Ingenic overcurrent
430 * detection.
431 * 0 - Deactivate the overcurrent detection
432 * 1 - Activate the overcurrent detection (default)
9962b62f 433 * @g_dma: Enables gadget dma usage (default: autodetect).
dec4b556 434 * @g_dma_desc: Enables gadget descriptor DMA (default: autodetect).
05ee799f
JY		 435 * @g_rx_fifo_size: The periodic rx fifo size for the device, in
436 * DWORDS from 16-32768 (default: 2048 if
437 * possible, otherwise autodetect).
438 * @g_np_tx_fifo_size: The non-periodic tx fifo size for the device in
439 * DWORDS from 16-32768 (default: 1024 if
440 * possible, otherwise autodetect).
441 * @g_tx_fifo_size: An array of TX fifo sizes in dedicated fifo
442 * mode. Each value corresponds to one EP
443 * starting from EP1 (max 15 values). Sizes are
f8590006 444 * in DWORDS with possible values from
05ee799f
JY		 445 * 16-32768 (default: 256, 256, 256, 256, 768,
446 * 768, 768, 768, 0, 0, 0, 0, 0, 0, 0).
ca8b0332
CY		 447 * @change_speed_quirk: Change speed configuration to DWC2_SPEED_PARAM_FULL
448 * while full&low speed device connect. And change speed
449 * back to DWC2_SPEED_PARAM_HIGH while device is gone.
450 * 0 - No (default)
451 * 1 - Yes
ca531bc2
GT		 452 * @service_interval: Enable service interval based scheduling.
453 * 0 - No
454 * 1 - Yes
56f5b1cf
PZ		 455 *
456 * The following parameters may be specified when starting the module. These
91121c10
MK		 457 * parameters define how the DWC_otg controller should be configured. A
458 * value of -1 (or any other out of range value) for any parameter means
459 * to read the value from hardware (if possible) or use the builtin
460 * default described above.
56f5b1cf
PZ		 461 */
462struct dwc2_core_params {
f5c8a6cb 463 struct usb_otg_caps otg_caps;
d21bcc3f 464 u8 phy_type;
c1d286cf
JY		 465#define DWC2_PHY_TYPE_PARAM_FS 0
466#define DWC2_PHY_TYPE_PARAM_UTMI 1
467#define DWC2_PHY_TYPE_PARAM_ULPI 2
468
57b8e235
JY		 469 u8 speed;
470#define DWC2_SPEED_PARAM_HIGH 0
471#define DWC2_SPEED_PARAM_FULL 1
472#define DWC2_SPEED_PARAM_LOW 2
473
d21bcc3f
JY		 474 u8 phy_utmi_width;
475 bool phy_ulpi_ddr;
476 bool phy_ulpi_ext_vbus;
57b8e235
JY		 477 bool enable_dynamic_fifo;
478 bool en_multiple_tx_fifo;
d21bcc3f 479 bool i2c_enable;
66e77a24 480 bool acg_enable;
d21bcc3f 481 bool ulpi_fs_ls;
d21bcc3f
JY		 482 bool ts_dline;
483 bool reload_ctl;
d21bcc3f
JY		 484 bool uframe_sched;
485 bool external_id_pin_ctl;
631a2310
VM		 486
487 int power_down;
488#define DWC2_POWER_DOWN_PARAM_NONE 0
489#define DWC2_POWER_DOWN_PARAM_PARTIAL 1
490#define DWC2_POWER_DOWN_PARAM_HIBERNATION 2
c4a0f7a6 491 bool no_clock_gating;
631a2310 492
6f80b6de
SA		 493 bool lpm;
494 bool lpm_clock_gating;
495 bool besl;
496 bool hird_threshold_en;
ca531bc2 497 bool service_interval;
6f80b6de 498 u8 hird_threshold;
e35b1350 499 bool activate_stm_fs_transceiver;
a415083a 500 bool activate_stm_id_vb_detection;
d712b725 501 bool activate_ingenic_overcurrent_detection;
b43ebc96 502 bool ipg_isoc_en;
57b8e235
JY		 503 u16 max_packet_count;
504 u32 max_transfer_size;
505 u32 ahbcfg;
6b66ce51 506
f3a61e4e
GT		 507 /* GREFCLK parameters */
508 u32 ref_clk_per;
509 u16 sof_cnt_wkup_alert;
510
6b66ce51
JY		 511 /* Host parameters */
512 bool host_dma;
57b8e235
JY		 513 bool dma_desc_enable;
514 bool dma_desc_fs_enable;
515 bool host_support_fs_ls_low_power;
516 bool host_ls_low_power_phy_clk;
b11633c4 517 bool oc_disable;
57b8e235
JY		 518
519 u8 host_channels;
520 u16 host_rx_fifo_size;
521 u16 host_nperio_tx_fifo_size;
522 u16 host_perio_tx_fifo_size;
6b66ce51
JY		 523
524 /* Gadget parameters */
05ee799f 525 bool g_dma;
dec4b556 526 bool g_dma_desc;
00c704cc
LY		 527 u32 g_rx_fifo_size;
528 u32 g_np_tx_fifo_size;
05ee799f 529 u32 g_tx_fifo_size[MAX_EPS_CHANNELS];
ca8b0332
CY		 530
531 bool change_speed_quirk;
56f5b1cf
PZ		 532};
533
9badec2f
MK		 534/**
535 * struct dwc2_hw_params - Autodetected parameters.
536 *
537 * These parameters are the various parameters read from hardware
538 * registers during initialization. They typically contain the best
539 * supported or maximum value that can be configured in the
540 * corresponding dwc2_core_params value.
541 *
542 * The values that are not in dwc2_core_params are documented below.
543 *
6fb914d7 544 * @op_mode: Mode of Operation
9badec2f
MK		 545 * 0 - HNP- and SRP-Capable OTG (Host & Device)
546 * 1 - SRP-Capable OTG (Host & Device)
547 * 2 - Non-HNP and Non-SRP Capable OTG (Host & Device)
548 * 3 - SRP-Capable Device
549 * 4 - Non-OTG Device
550 * 5 - SRP-Capable Host
551 * 6 - Non-OTG Host
6fb914d7 552 * @arch: Architecture
9badec2f
MK		 553 * 0 - Slave only
554 * 1 - External DMA
555 * 2 - Internal DMA
6fb914d7 556 * @ipg_isoc_en: This feature indicates that the controller supports
b43ebc96
GT		 557 * the worst-case scenario of Rx followed by Rx
558 * Interpacket Gap (IPG) (32 bitTimes) as per the utmi
559 * specification for any token following ISOC OUT token.
560 * 0 - Don't support
561 * 1 - Support
6fb914d7
GT		 562 * @power_optimized: Are power optimizations enabled?
563 * @num_dev_ep: Number of device endpoints available
564 * @num_dev_in_eps: Number of device IN endpoints available
565 * @num_dev_perio_in_ep: Number of device periodic IN endpoints
566 * available
567 * @dev_token_q_depth: Device Mode IN Token Sequence Learning Queue
9badec2f
MK		 568 * Depth
569 * 0 to 30
6fb914d7 570 * @host_perio_tx_q_depth:
9badec2f
MK		 571 * Host Mode Periodic Request Queue Depth
572 * 2, 4 or 8
6fb914d7 573 * @nperio_tx_q_depth:
9badec2f
MK		 574 * Non-Periodic Request Queue Depth
575 * 2, 4 or 8
6fb914d7 576 * @hs_phy_type: High-speed PHY interface type
9badec2f
MK		 577 * 0 - High-speed interface not supported
578 * 1 - UTMI+
579 * 2 - ULPI
580 * 3 - UTMI+ and ULPI
6fb914d7 581 * @fs_phy_type: Full-speed PHY interface type
9badec2f
MK		 582 * 0 - Full speed interface not supported
583 * 1 - Dedicated full speed interface
584 * 2 - FS pins shared with UTMI+ pins
585 * 3 - FS pins shared with ULPI pins
586 * @total_fifo_size: Total internal RAM for FIFOs (bytes)
6fb914d7
GT		 587 * @hibernation: Is hibernation enabled?
588 * @utmi_phy_data_width: UTMI+ PHY data width
de4a1931
MK		 589 * 0 - 8 bits
590 * 1 - 16 bits
591 * 2 - 8 or 16 bits
9badec2f 592 * @snpsid: Value from SNPSID register
55e1040e 593 * @dev_ep_dirs: Direction of device endpoints (GHWCFG1)
6fb914d7
GT		 594 * @g_tx_fifo_size: Power-on values of TxFIFO sizes
595 * @dma_desc_enable: When DMA mode is enabled, specifies whether to use
596 * address DMA mode or descriptor DMA mode for accessing
597 * the data FIFOs. The driver will automatically detect the
598 * value for this if none is specified.
599 * 0 - Address DMA
600 * 1 - Descriptor DMA (default, if available)
601 * @enable_dynamic_fifo: 0 - Use coreConsultant-specified FIFO size parameters
602 * 1 - Allow dynamic FIFO sizing (default, if available)
603 * @en_multiple_tx_fifo: Specifies whether dedicated per-endpoint transmit FIFOs
604 * are enabled for non-periodic IN endpoints in device
605 * mode.
606 * @host_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO
607 * in host mode when dynamic FIFO sizing is enabled
608 * 16 to 32768
609 * Actual maximum value is autodetected and also
610 * the default.
611 * @host_perio_tx_fifo_size: Number of 4-byte words in the periodic Tx FIFO in
612 * host mode when dynamic FIFO sizing is enabled
613 * 16 to 32768
614 * Actual maximum value is autodetected and also
615 * the default.
616 * @max_transfer_size: The maximum transfer size supported, in bytes
617 * 2047 to 65,535
618 * Actual maximum value is autodetected and also
619 * the default.
620 * @max_packet_count: The maximum number of packets in a transfer
621 * 15 to 511
622 * Actual maximum value is autodetected and also
623 * the default.
624 * @host_channels: The number of host channel registers to use
625 * 1 to 16
626 * Actual maximum value is autodetected and also
627 * the default.
628 * @dev_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO
629 * in device mode when dynamic FIFO sizing is enabled
630 * 16 to 32768
631 * Actual maximum value is autodetected and also
632 * the default.
633 * @i2c_enable: Specifies whether to use the I2Cinterface for a full
634 * speed PHY. This parameter is only applicable if phy_type
635 * is FS.
636 * 0 - No (default)
637 * 1 - Yes
638 * @acg_enable: For enabling Active Clock Gating in the controller
639 * 0 - Disable
640 * 1 - Enable
641 * @lpm_mode: For enabling Link Power Management in the controller
642 * 0 - Disable
643 * 1 - Enable
644 * @rx_fifo_size: Number of 4-byte words in the Rx FIFO when dynamic
645 * FIFO sizing is enabled 16 to 32768
646 * Actual maximum value is autodetected and also
647 * the default.
ca531bc2
GT		 648 * @service_interval_mode: For enabling service interval based scheduling in the
649 * controller.
650 * 0 - Disable
651 * 1 - Enable
9badec2f
MK		 652 */
653struct dwc2_hw_params {
654 unsigned op_mode:3;
655 unsigned arch:2;
656 unsigned dma_desc_enable:1;
657 unsigned enable_dynamic_fifo:1;
658 unsigned en_multiple_tx_fifo:1;
d1531319 659 unsigned rx_fifo_size:16;
9badec2f 660 unsigned host_nperio_tx_fifo_size:16;
55e1040e 661 unsigned dev_nperio_tx_fifo_size:16;
9badec2f
MK		 662 unsigned host_perio_tx_fifo_size:16;
663 unsigned nperio_tx_q_depth:3;
664 unsigned host_perio_tx_q_depth:3;
665 unsigned dev_token_q_depth:5;
666 unsigned max_transfer_size:26;
667 unsigned max_packet_count:11;
2d115547 668 unsigned host_channels:5;
9badec2f
MK		 669 unsigned hs_phy_type:2;
670 unsigned fs_phy_type:2;
671 unsigned i2c_enable:1;
66e77a24 672 unsigned acg_enable:1;
9badec2f 673 unsigned num_dev_ep:4;
9273083a 674 unsigned num_dev_in_eps : 4;
9badec2f
MK		 675 unsigned num_dev_perio_in_ep:4;
676 unsigned total_fifo_size:16;
677 unsigned power_optimized:1;
631a2310 678 unsigned hibernation:1;
de4a1931 679 unsigned utmi_phy_data_width:2;
6f80b6de 680 unsigned lpm_mode:1;
b43ebc96 681 unsigned ipg_isoc_en:1;
ca531bc2 682 unsigned service_interval_mode:1;
9badec2f 683 u32 snpsid;
55e1040e 684 u32 dev_ep_dirs;
9273083a 685 u32 g_tx_fifo_size[MAX_EPS_CHANNELS];
9badec2f
MK		 686};
687
3f95001d
MYK		 688/* Size of control and EP0 buffers */
689#define DWC2_CTRL_BUFF_SIZE 8
690
d17ee77b 691/**
38beaec6
JY		 692 * struct dwc2_gregs_backup - Holds global registers state before
693 * entering partial power down
d17ee77b
GH		 694 * @gotgctl: Backup of GOTGCTL register
695 * @gintmsk: Backup of GINTMSK register
696 * @gahbcfg: Backup of GAHBCFG register
697 * @gusbcfg: Backup of GUSBCFG register
698 * @grxfsiz: Backup of GRXFSIZ register
699 * @gnptxfsiz: Backup of GNPTXFSIZ register
700 * @gi2cctl: Backup of GI2CCTL register
66a36096 701 * @glpmcfg: Backup of GLPMCFG register
d17ee77b 702 * @gdfifocfg: Backup of GDFIFOCFG register
6fb914d7
GT		 703 * @pcgcctl: Backup of PCGCCTL register
704 * @pcgcctl1: Backup of PCGCCTL1 register
705 * @dtxfsiz: Backup of DTXFSIZ registers for each endpoint
d17ee77b 706 * @gpwrdn: Backup of GPWRDN register
6fb914d7 707 * @valid: True if registers values backuped.
d17ee77b
GH		 708 */
709struct dwc2_gregs_backup {
710 u32 gotgctl;
711 u32 gintmsk;
712 u32 gahbcfg;
713 u32 gusbcfg;
714 u32 grxfsiz;
715 u32 gnptxfsiz;
716 u32 gi2cctl;
66a36096 717 u32 glpmcfg;
d17ee77b 718 u32 pcgcctl;
600a490e 719 u32 pcgcctl1;
d17ee77b 720 u32 gdfifocfg;
d17ee77b 721 u32 gpwrdn;
cc1e204c 722 bool valid;
d17ee77b
GH		 723};
724
725/**
38beaec6
JY		 726 * struct dwc2_dregs_backup - Holds device registers state before
727 * entering partial power down
d17ee77b
GH		 728 * @dcfg: Backup of DCFG register
729 * @dctl: Backup of DCTL register
730 * @daintmsk: Backup of DAINTMSK register
731 * @diepmsk: Backup of DIEPMSK register
732 * @doepmsk: Backup of DOEPMSK register
733 * @diepctl: Backup of DIEPCTL register
734 * @dieptsiz: Backup of DIEPTSIZ register
735 * @diepdma: Backup of DIEPDMA register
736 * @doepctl: Backup of DOEPCTL register
737 * @doeptsiz: Backup of DOEPTSIZ register
738 * @doepdma: Backup of DOEPDMA register
af7c2bd3 739 * @dtxfsiz: Backup of DTXFSIZ registers for each endpoint
6fb914d7 740 * @valid: True if registers values backuped.
d17ee77b
GH		 741 */
742struct dwc2_dregs_backup {
743 u32 dcfg;
744 u32 dctl;
745 u32 daintmsk;
746 u32 diepmsk;
747 u32 doepmsk;
748 u32 diepctl[MAX_EPS_CHANNELS];
749 u32 dieptsiz[MAX_EPS_CHANNELS];
750 u32 diepdma[MAX_EPS_CHANNELS];
751 u32 doepctl[MAX_EPS_CHANNELS];
752 u32 doeptsiz[MAX_EPS_CHANNELS];
753 u32 doepdma[MAX_EPS_CHANNELS];
af7c2bd3 754 u32 dtxfsiz[MAX_EPS_CHANNELS];
cc1e204c 755 bool valid;
d17ee77b
GH		 756};
757
758/**
38beaec6
JY		 759 * struct dwc2_hregs_backup - Holds host registers state before
760 * entering partial power down
d17ee77b
GH		 761 * @hcfg: Backup of HCFG register
762 * @haintmsk: Backup of HAINTMSK register
763 * @hcintmsk: Backup of HCINTMSK register
6fb914d7 764 * @hprt0: Backup of HPTR0 register
d17ee77b 765 * @hfir: Backup of HFIR register
66a36096 766 * @hptxfsiz: Backup of HPTXFSIZ register
6fb914d7 767 * @valid: True if registers values backuped.
d17ee77b
GH		 768 */
769struct dwc2_hregs_backup {
770 u32 hcfg;
771 u32 haintmsk;
772 u32 hcintmsk[MAX_EPS_CHANNELS];
773 u32 hprt0;
774 u32 hfir;
66a36096 775 u32 hptxfsiz;
cc1e204c 776 bool valid;
d17ee77b
GH		 777};
778
9f9f09b0
DA		 779/*
780 * Constants related to high speed periodic scheduling
781 *
782 * We have a periodic schedule that is DWC2_HS_SCHEDULE_UFRAMES long. From a
783 * reservation point of view it's assumed that the schedule goes right back to
784 * the beginning after the end of the schedule.
785 *
786 * What does that mean for scheduling things with a long interval? It means
787 * we'll reserve time for them in every possible microframe that they could
788 * ever be scheduled in. ...but we'll still only actually schedule them as
789 * often as they were requested.
790 *
791 * We keep our schedule in a "bitmap" structure. This simplifies having
792 * to keep track of and merge intervals: we just let the bitmap code do most
793 * of the heavy lifting. In a way scheduling is much like memory allocation.
794 *
795 * We schedule 100us per uframe or 80% of 125us (the maximum amount you're
796 * supposed to schedule for periodic transfers). That's according to spec.
797 *
798 * Note that though we only schedule 80% of each microframe, the bitmap that we
799 * keep the schedule in is tightly packed (AKA it doesn't have 100us worth of
800 * space for each uFrame).
801 *
802 * Requirements:
803 * - DWC2_HS_SCHEDULE_UFRAMES must even divide 0x4000 (HFNUM_MAX_FRNUM + 1)
804 * - DWC2_HS_SCHEDULE_UFRAMES must be 8 times DWC2_LS_SCHEDULE_FRAMES (probably
805 * could be any multiple of 8 times DWC2_LS_SCHEDULE_FRAMES, but there might
806 * be bugs). The 8 comes from the USB spec: number of microframes per frame.
807 */
808#define DWC2_US_PER_UFRAME 125
809#define DWC2_HS_PERIODIC_US_PER_UFRAME 100
810
811#define DWC2_HS_SCHEDULE_UFRAMES 8
812#define DWC2_HS_SCHEDULE_US (DWC2_HS_SCHEDULE_UFRAMES * \
813 DWC2_HS_PERIODIC_US_PER_UFRAME)
814
815/*
816 * Constants related to low speed scheduling
817 *
818 * For high speed we schedule every 1us. For low speed that's a bit overkill,
819 * so we make up a unit called a "slice" that's worth 25us. There are 40
820 * slices in a full frame and we can schedule 36 of those (90%) for periodic
821 * transfers.
822 *
823 * Our low speed schedule can be as short as 1 frame or could be longer. When
824 * we only schedule 1 frame it means that we'll need to reserve a time every
825 * frame even for things that only transfer very rarely, so something that runs
826 * every 2048 frames will get time reserved in every frame. Our low speed
827 * schedule can be longer and we'll be able to handle more overlap, but that
828 * will come at increased memory cost and increased time to schedule.
829 *
830 * Note: one other advantage of a short low speed schedule is that if we mess
831 * up and miss scheduling we can jump in and use any of the slots that we
832 * happened to reserve.
833 *
834 * With 25 us per slice and 1 frame in the schedule, we only need 4 bytes for
835 * the schedule. There will be one schedule per TT.
836 *
837 * Requirements:
838 * - DWC2_US_PER_SLICE must evenly divide DWC2_LS_PERIODIC_US_PER_FRAME.
839 */
840#define DWC2_US_PER_SLICE 25
841#define DWC2_SLICES_PER_UFRAME (DWC2_US_PER_UFRAME / DWC2_US_PER_SLICE)
842
843#define DWC2_ROUND_US_TO_SLICE(us) \
844 (DIV_ROUND_UP((us), DWC2_US_PER_SLICE) * \
845 DWC2_US_PER_SLICE)
846
847#define DWC2_LS_PERIODIC_US_PER_FRAME \
848 900
849#define DWC2_LS_PERIODIC_SLICES_PER_FRAME \
850 (DWC2_LS_PERIODIC_US_PER_FRAME / \
851 DWC2_US_PER_SLICE)
852
853#define DWC2_LS_SCHEDULE_FRAMES 1
854#define DWC2_LS_SCHEDULE_SLICES (DWC2_LS_SCHEDULE_FRAMES * \
855 DWC2_LS_PERIODIC_SLICES_PER_FRAME)
856
56f5b1cf
PZ		 857/**
858 * struct dwc2_hsotg - Holds the state of the driver, including the non-periodic
859 * and periodic schedules
860 *
941fcce4
DN		 861 * These are common for both host and peripheral modes:
862 *
56f5b1cf
PZ		 863 * @dev: The struct device pointer
864 * @regs: Pointer to controller regs
9badec2f
MK		 865 * @hw_params: Parameters that were autodetected from the
866 * hardware registers
6fb914d7 867 * @params: Parameters that define how the core should be configured
56f5b1cf
PZ		 868 * @op_state: The operational State, during transitions (a_host=>
869 * a_peripheral and b_device=>b_host) this may not match
870 * the core, but allows the software to determine
871 * transitions
c0155b9d
KY		 872 * @dr_mode: Requested mode of operation, one of following:
873 * - USB_DR_MODE_PERIPHERAL
874 * - USB_DR_MODE_HOST
875 * - USB_DR_MODE_OTG
17f93402 876 * @role_sw: usb_role_switch handle
e14acb87
FG		 877 * @role_sw_default_mode: default operation mode of controller while usb role
878 * is USB_ROLE_NONE
6fb914d7
GT		 879 * @hcd_enabled: Host mode sub-driver initialization indicator.
880 * @gadget_enabled: Peripheral mode sub-driver initialization indicator.
881 * @ll_hw_enabled: Status of low-level hardware resources.
20fe4409 882 * @hibernated: True if core is hibernated
be2b960e 883 * @in_ppd: True if core is partial power down mode.
012466fc 884 * @bus_suspended: True if bus is suspended
c40cf770
DA		 885 * @reset_phy_on_wake: Quirk saying that we should assert PHY reset on a
886 * remote wakeup.
c846b03f
DA		 887 * @phy_off_for_suspend: Status of whether we turned the PHY off at suspend.
888 * @need_phy_for_wake: Quirk saying that we should keep the PHY on at
889 * suspend if we need USB to wake us up.
c7c24e7a
AP		 890 * @frame_number: Frame number read from the core. For both device
891 * and host modes. The value ranges are from 0
892 * to HFNUM_MAX_FRNUM.
09a75e85 893 * @phy: The otg phy transceiver structure for phy control.
38beaec6
JY		 894 * @uphy: The otg phy transceiver structure for old USB phy
895 * control.
896 * @plat: The platform specific configuration data. This can be
897 * removed once all SoCs support usb transceiver.
09a75e85 898 * @supplies: Definition of USB power supplies
531ef5eb 899 * @vbus_supply: Regulator supplying vbus.
a415083a
AD		 900 * @usb33d: Optional 3.3v regulator used on some stm32 devices to
901 * supply ID and VBUS detection hardware.
941fcce4
DN		 902 * @lock: Spinlock that protects all the driver data structures
903 * @priv: Stores a pointer to the struct usb_hcd
56f5b1cf
PZ		 904 * @queuing_high_bandwidth: True if multiple packets of a high-bandwidth
905 * transfer are in process of being queued
906 * @srp_success: Stores status of SRP request in the case of a FS PHY
907 * with an I2C interface
908 * @wq_otg: Workqueue object used for handling of some interrupts
909 * @wf_otg: Work object for handling Connector ID Status Change
910 * interrupt
911 * @wkp_timer: Timer object for handling Wakeup Detected interrupt
912 * @lx_state: Lx state of connected device
6fb914d7
GT		 913 * @gr_backup: Backup of global registers during suspend
914 * @dr_backup: Backup of device registers during suspend
915 * @hr_backup: Backup of host registers during suspend
fe369e18 916 * @needs_byte_swap: Specifies whether the opposite endianness.
941fcce4
DN		 917 *
918 * These are for host mode:
919 *
56f5b1cf 920 * @flags: Flags for handling root port state changes
6fb914d7
GT		 921 * @flags.d32: Contain all root port flags
922 * @flags.b: Separate root port flags from each other
923 * @flags.b.port_connect_status_change: True if root port connect status
924 * changed
925 * @flags.b.port_connect_status: True if device connected to root port
926 * @flags.b.port_reset_change: True if root port reset status changed
927 * @flags.b.port_enable_change: True if root port enable status changed
928 * @flags.b.port_suspend_change: True if root port suspend status changed
929 * @flags.b.port_over_current_change: True if root port over current state
930 * changed.
931 * @flags.b.port_l1_change: True if root port l1 status changed
932 * @flags.b.reserved: Reserved bits of root port register
56f5b1cf
PZ		 933 * @non_periodic_sched_inactive: Inactive QHs in the non-periodic schedule.
934 * Transfers associated with these QHs are not currently
935 * assigned to a host channel.
936 * @non_periodic_sched_active: Active QHs in the non-periodic schedule.
937 * Transfers associated with these QHs are currently
938 * assigned to a host channel.
939 * @non_periodic_qh_ptr: Pointer to next QH to process in the active
940 * non-periodic schedule
6fb914d7
GT		 941 * @non_periodic_sched_waiting: Waiting QHs in the non-periodic schedule.
942 * Transfers associated with these QHs are not currently
943 * assigned to a host channel.
56f5b1cf
PZ		 944 * @periodic_sched_inactive: Inactive QHs in the periodic schedule. This is a
945 * list of QHs for periodic transfers that are _not_
946 * scheduled for the next frame. Each QH in the list has an
947 * interval counter that determines when it needs to be
948 * scheduled for execution. This scheduling mechanism
949 * allows only a simple calculation for periodic bandwidth
950 * used (i.e. must assume that all periodic transfers may
951 * need to execute in the same frame). However, it greatly
952 * simplifies scheduling and should be sufficient for the
953 * vast majority of OTG hosts, which need to connect to a
954 * small number of peripherals at one time. Items move from
955 * this list to periodic_sched_ready when the QH interval
956 * counter is 0 at SOF.
957 * @periodic_sched_ready: List of periodic QHs that are ready for execution in
958 * the next frame, but have not yet been assigned to host
959 * channels. Items move from this list to
960 * periodic_sched_assigned as host channels become
961 * available during the current frame.
962 * @periodic_sched_assigned: List of periodic QHs to be executed in the next
963 * frame that are assigned to host channels. Items move
964 * from this list to periodic_sched_queued as the
965 * transactions for the QH are queued to the DWC_otg
966 * controller.
967 * @periodic_sched_queued: List of periodic QHs that have been queued for
968 * execution. Items move from this list to either
969 * periodic_sched_inactive or periodic_sched_ready when the
970 * channel associated with the transfer is released. If the
971 * interval for the QH is 1, the item moves to
972 * periodic_sched_ready because it must be rescheduled for
973 * the next frame. Otherwise, the item moves to
974 * periodic_sched_inactive.
c9c8ac01 975 * @split_order: List keeping track of channels doing splits, in order.
56f5b1cf
PZ		 976 * @periodic_usecs: Total bandwidth claimed so far for periodic transfers.
977 * This value is in microseconds per (micro)frame. The
978 * assumption is that all periodic transfers may occur in
979 * the same (micro)frame.
9f9f09b0
DA		 980 * @hs_periodic_bitmap: Bitmap used by the microframe scheduler any time the
981 * host is in high speed mode; low speed schedules are
982 * stored elsewhere since we need one per TT.
56f5b1cf
PZ		 983 * @periodic_qh_count: Count of periodic QHs, if using several eps. Used for
984 * SOF enable/disable.
985 * @free_hc_list: Free host channels in the controller. This is a list of
986 * struct dwc2_host_chan items.
987 * @periodic_channels: Number of host channels assigned to periodic transfers.
988 * Currently assuming that there is a dedicated host
989 * channel for each periodic transaction and at least one
990 * host channel is available for non-periodic transactions.
991 * @non_periodic_channels: Number of host channels assigned to non-periodic
992 * transfers
6fb914d7
GT		 993 * @available_host_channels: Number of host channels available for the
994 * microframe scheduler to use
56f5b1cf
PZ		 995 * @hc_ptr_array: Array of pointers to the host channel descriptors.
996 * Allows accessing a host channel descriptor given the
997 * host channel number. This is useful in interrupt
998 * handlers.
999 * @status_buf: Buffer used for data received during the status phase of
1000 * a control transfer.
1001 * @status_buf_dma: DMA address for status_buf
1002 * @start_work: Delayed work for handling host A-cable connection
1003 * @reset_work: Delayed work for handling a port reset
c40cf770 1004 * @phy_reset_work: Work structure for doing a PHY reset
56f5b1cf
PZ		 1005 * @otg_port: OTG port number
1006 * @frame_list: Frame list
1007 * @frame_list_dma: Frame list DMA address
95105a99 1008 * @frame_list_sz: Frame list size
3b5fcc9a
GH		 1009 * @desc_gen_cache: Kmem cache for generic descriptors
1010 * @desc_hsisoc_cache: Kmem cache for hs isochronous descriptors
af424a41 1011 * @unaligned_cache: Kmem cache for DMA mode to handle non-aligned buf
941fcce4
DN		 1012 *
1013 * These are for peripheral mode:
1014 *
1015 * @driver: USB gadget driver
941fcce4
DN		 1016 * @dedicated_fifos: Set if the hardware has dedicated IN-EP fifos.
1017 * @num_of_eps: Number of available EPs (excluding EP0)
1018 * @debug_root: Root directrory for debugfs.
941fcce4
DN		 1019 * @ep0_reply: Request used for ep0 reply.
1020 * @ep0_buff: Buffer for EP0 reply data, if needed.
1021 * @ctrl_buff: Buffer for EP0 control requests.
1022 * @ctrl_req: Request for EP0 control packets.
fe0b94ab 1023 * @ep0_state: EP0 control transfers state
b4c53b4a 1024 * @delayed_status: true when gadget driver asks for delayed status
9e14d0a5 1025 * @test_mode: USB test mode requested by the host
fa389a6d
VM		 1026 * @remote_wakeup_allowed: True if device is allowed to wake-up host by
1027 * remote-wakeup signalling
0f6b80c0
VA		 1028 * @setup_desc_dma: EP0 setup stage desc chain DMA address
1029 * @setup_desc: EP0 setup stage desc chain pointer
1030 * @ctrl_in_desc_dma: EP0 IN data phase desc chain DMA address
1031 * @ctrl_in_desc: EP0 IN data phase desc chain pointer
1032 * @ctrl_out_desc_dma: EP0 OUT data phase desc chain DMA address
1033 * @ctrl_out_desc: EP0 OUT data phase desc chain pointer
6fb914d7
GT		 1034 * @irq: Interrupt request line number
1035 * @clk: Pointer to otg clock
1036 * @reset: Pointer to dwc2 reset controller
1037 * @reset_ecc: Pointer to dwc2 optional reset controller in Stratix10.
1038 * @regset: A pointer to a struct debugfs_regset32, which contains
1039 * a pointer to an array of register definitions, the
1040 * array size and the base address where the register bank
1041 * is to be found.
6fb914d7
GT		 1042 * @last_frame_num: Number of last frame. Range from 0 to 32768
1043 * @frame_num_array: Used only if CONFIG_USB_DWC2_TRACK_MISSED_SOFS is
1044 * defined, for missed SOFs tracking. Array holds that
1045 * frame numbers, which not equal to last_frame_num +1
1046 * @last_frame_num_array: Used only if CONFIG_USB_DWC2_TRACK_MISSED_SOFS is
1047 * defined, for missed SOFs tracking.
1048 * If current_frame_number != last_frame_num+1
1049 * then last_frame_num added to this array
1050 * @frame_num_idx: Actual size of frame_num_array and last_frame_num_array
1051 * @dumped_frame_num_array: 1 - if missed SOFs frame numbers dumbed
1052 * 0 - if missed SOFs frame numbers not dumbed
1053 * @fifo_mem: Total internal RAM for FIFOs (bytes)
1054 * @fifo_map: Each bit intend for concrete fifo. If that bit is set,
1055 * then that fifo is used
b9b70170 1056 * @gadget: Represents a usb gadget device
6fb914d7
GT		 1057 * @connected: Used in slave mode. True if device connected with host
1058 * @eps_in: The IN endpoints being supplied to the gadget framework
1059 * @eps_out: The OUT endpoints being supplied to the gadget framework
1060 * @new_connection: Used in host mode. True if there are new connected
1061 * device
1062 * @enabled: Indicates the enabling state of controller
1063 *
56f5b1cf
PZ		 1064 */
1065struct dwc2_hsotg {
1066 struct device *dev;
1067 void __iomem *regs;
9badec2f
MK		 1068 /** Params detected from hardware */
1069 struct dwc2_hw_params hw_params;
1070 /** Params to actually use */
bea8e86c 1071 struct dwc2_core_params params;
56f5b1cf 1072 enum usb_otg_state op_state;
c0155b9d 1073 enum usb_dr_mode dr_mode;
17f93402 1074 struct usb_role_switch *role_sw;
e14acb87 1075 enum usb_dr_mode role_sw_default_mode;
e39af88f
MS		 1076 unsigned int hcd_enabled:1;
1077 unsigned int gadget_enabled:1;
09a75e85 1078 unsigned int ll_hw_enabled:1;
20fe4409 1079 unsigned int hibernated:1;
be2b960e 1080 unsigned int in_ppd:1;
012466fc 1081 bool bus_suspended;
c40cf770 1082 unsigned int reset_phy_on_wake:1;
c846b03f
DA		 1083 unsigned int need_phy_for_wake:1;
1084 unsigned int phy_off_for_suspend:1;
c7c24e7a 1085 u16 frame_number;
56f5b1cf 1086
941fcce4
DN		 1087 struct phy *phy;
1088 struct usb_phy *uphy;
09a75e85 1089 struct dwc2_hsotg_plat *plat;
b98866c2 1090 struct regulator_bulk_data supplies[DWC2_NUM_SUPPLIES];
531ef5eb 1091 struct regulator *vbus_supply;
a415083a 1092 struct regulator *usb33d;
941fcce4
DN		 1093
1094 spinlock_t lock;
1095 void *priv;
1096 int irq;
1097 struct clk *clk;
83f8da56 1098 struct reset_control *reset;
f2830ad4 1099 struct reset_control *reset_ecc;
941fcce4 1100
56f5b1cf
PZ		 1101 unsigned int queuing_high_bandwidth:1;
1102 unsigned int srp_success:1;
1103
1104 struct workqueue_struct *wq_otg;
1105 struct work_struct wf_otg;
1106 struct timer_list wkp_timer;
1107 enum dwc2_lx_state lx_state;
cc1e204c
MYK		 1108 struct dwc2_gregs_backup gr_backup;
1109 struct dwc2_dregs_backup dr_backup;
1110 struct dwc2_hregs_backup hr_backup;
56f5b1cf 1111
941fcce4 1112 struct dentry *debug_root;
563cf017 1113 struct debugfs_regset32 *regset;
fe369e18 1114 bool needs_byte_swap;
941fcce4
DN		 1115
1116 /* DWC OTG HW Release versions */
1117#define DWC2_CORE_REV_2_71a 0x4f54271a
5295322a 1118#define DWC2_CORE_REV_2_72a 0x4f54272a
6f80b6de 1119#define DWC2_CORE_REV_2_80a 0x4f54280a
941fcce4 1120#define DWC2_CORE_REV_2_90a 0x4f54290a
e1f411d1 1121#define DWC2_CORE_REV_2_91a 0x4f54291a
941fcce4
DN		 1122#define DWC2_CORE_REV_2_92a 0x4f54292a
1123#define DWC2_CORE_REV_2_94a 0x4f54294a
1124#define DWC2_CORE_REV_3_00a 0x4f54300a
fef6bc37 1125#define DWC2_CORE_REV_3_10a 0x4f54310a
5295322a 1126#define DWC2_CORE_REV_4_00a 0x4f54400a
65dc2e72 1127#define DWC2_CORE_REV_4_20a 0x4f54420a
1e6b98eb
VM		 1128#define DWC2_FS_IOT_REV_1_00a 0x5531100a
1129#define DWC2_HS_IOT_REV_1_00a 0x5532100a
65dc2e72 1130#define DWC2_CORE_REV_MASK 0x0000ffff
941fcce4 1131
d14ccaba
GS		 1132 /* DWC OTG HW Core ID */
1133#define DWC2_OTG_ID 0x4f540000
1134#define DWC2_FS_IOT_ID 0x55310000
1135#define DWC2_HS_IOT_ID 0x55320000
1136
941fcce4 1137#if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
56f5b1cf
PZ		 1138 union dwc2_hcd_internal_flags {
1139 u32 d32;
1140 struct {
1141 unsigned port_connect_status_change:1;
1142 unsigned port_connect_status:1;
1143 unsigned port_reset_change:1;
1144 unsigned port_enable_change:1;
1145 unsigned port_suspend_change:1;
1146 unsigned port_over_current_change:1;
1147 unsigned port_l1_change:1;
fd4850cf 1148 unsigned reserved:25;
56f5b1cf
PZ		 1149 } b;
1150 } flags;
1151
1152 struct list_head non_periodic_sched_inactive;
38d2b5fb 1153 struct list_head non_periodic_sched_waiting;
56f5b1cf
PZ		 1154 struct list_head non_periodic_sched_active;
1155 struct list_head *non_periodic_qh_ptr;
1156 struct list_head periodic_sched_inactive;
1157 struct list_head periodic_sched_ready;
1158 struct list_head periodic_sched_assigned;
1159 struct list_head periodic_sched_queued;
c9c8ac01 1160 struct list_head split_order;
56f5b1cf 1161 u16 periodic_usecs;
db3e8244 1162 DECLARE_BITMAP(hs_periodic_bitmap, DWC2_HS_SCHEDULE_US);
56f5b1cf 1163 u16 periodic_qh_count;
fbb9e22b 1164 bool new_connection;
56f5b1cf 1165
483bb254
DA		 1166 u16 last_frame_num;
1167
56f5b1cf
PZ		 1168#ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
1169#define FRAME_NUM_ARRAY_SIZE 1000
56f5b1cf
PZ		 1170 u16 *frame_num_array;
1171 u16 *last_frame_num_array;
1172 int frame_num_idx;
1173 int dumped_frame_num_array;
1174#endif
1175
1176 struct list_head free_hc_list;
1177 int periodic_channels;
1178 int non_periodic_channels;
20f2eb9c 1179 int available_host_channels;
56f5b1cf
PZ		 1180 struct dwc2_host_chan *hc_ptr_array[MAX_EPS_CHANNELS];
1181 u8 *status_buf;
1182 dma_addr_t status_buf_dma;
1183#define DWC2_HCD_STATUS_BUF_SIZE 64
1184
1185 struct delayed_work start_work;
1186 struct delayed_work reset_work;
c40cf770 1187 struct work_struct phy_reset_work;
56f5b1cf
PZ		 1188 u8 otg_port;
1189 u32 *frame_list;
1190 dma_addr_t frame_list_dma;
95105a99 1191 u32 frame_list_sz;
3b5fcc9a
GH		 1192 struct kmem_cache *desc_gen_cache;
1193 struct kmem_cache *desc_hsisoc_cache;
af424a41
WW		 1194 struct kmem_cache *unaligned_cache;
1195#define DWC2_KMEM_UNALIGNED_BUF_SIZE 1024
56f5b1cf 1196
941fcce4
DN		 1197#endif /* CONFIG_USB_DWC2_HOST || CONFIG_USB_DWC2_DUAL_ROLE */
1198
b98866c2
JY		 1199#if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \
1200 IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
941fcce4
DN		 1201 /* Gadget structures */
1202 struct usb_gadget_driver *driver;
941fcce4
DN		 1203 int fifo_mem;
1204 unsigned int dedicated_fifos:1;
1205 unsigned char num_of_eps;
1206 u32 fifo_map;
1207
1208 struct usb_request *ep0_reply;
1209 struct usb_request *ctrl_req;
3f95001d
MYK		 1210 void *ep0_buff;
1211 void *ctrl_buff;
fe0b94ab 1212 enum dwc2_ep0_state ep0_state;
b4c53b4a 1213 unsigned delayed_status : 1;
9e14d0a5 1214 u8 test_mode;
941fcce4 1215
0f6b80c0
VA		 1216 dma_addr_t setup_desc_dma[2];
1217 struct dwc2_dma_desc *setup_desc[2];
1218 dma_addr_t ctrl_in_desc_dma;
1219 struct dwc2_dma_desc *ctrl_in_desc;
1220 dma_addr_t ctrl_out_desc_dma;
1221 struct dwc2_dma_desc *ctrl_out_desc;
1222
941fcce4 1223 struct usb_gadget gadget;
dc6e69e6 1224 unsigned int enabled:1;
4ace06e8 1225 unsigned int connected:1;
fa389a6d 1226 unsigned int remote_wakeup_allowed:1;
1f91b4cc
FB		 1227 struct dwc2_hsotg_ep *eps_in[MAX_EPS_CHANNELS];
1228 struct dwc2_hsotg_ep *eps_out[MAX_EPS_CHANNELS];
941fcce4 1229#endif /* CONFIG_USB_DWC2_PERIPHERAL || CONFIG_USB_DWC2_DUAL_ROLE */
56f5b1cf
PZ		 1230};
1231
342ccce1 1232/* Normal architectures just use readl/write */
f25c42b8 1233static inline u32 dwc2_readl(struct dwc2_hsotg *hsotg, u32 offset)
0f548098 1234{
fe369e18
GS		 1235 u32 val;
1236
1237 val = readl(hsotg->regs + offset);
1238 if (hsotg->needs_byte_swap)
1239 return swab32(val);
1240 else
1241 return val;
0f548098
GS		 1242}
1243
f25c42b8 1244static inline void dwc2_writel(struct dwc2_hsotg *hsotg, u32 value, u32 offset)
0f548098 1245{
fe369e18
GS		 1246 if (hsotg->needs_byte_swap)
1247 writel(swab32(value), hsotg->regs + offset);
1248 else
1249 writel(value, hsotg->regs + offset);
342ccce1 1250
0f548098 1251#ifdef DWC2_LOG_WRITES
342ccce1 1252 pr_info("info:: wrote %08x to %p\n", value, hsotg->regs + offset);
0f548098
GS		 1253#endif
1254}
f25c42b8 1255
342ccce1
GS		 1256static inline void dwc2_readl_rep(struct dwc2_hsotg *hsotg, u32 offset,
1257 void *buffer, unsigned int count)
0f548098 1258{
342ccce1
GS		 1259 if (count) {
1260 u32 *buf = buffer;
1261
1262 do {
1263 u32 x = dwc2_readl(hsotg, offset);
1264 *buf++ = x;
1265 } while (--count);
1266 }
0f548098
GS		 1267}
1268
342ccce1
GS		 1269static inline void dwc2_writel_rep(struct dwc2_hsotg *hsotg, u32 offset,
1270 const void *buffer, unsigned int count)
0f548098 1271{
342ccce1
GS		 1272 if (count) {
1273 const u32 *buf = buffer;
0f548098 1274
342ccce1
GS		 1275 do {
1276 dwc2_writel(hsotg, *buf++, offset);
1277 } while (--count);
1278 }
0f548098 1279}
0f548098 1280
56f5b1cf
PZ		 1281/* Reasons for halting a host channel */
1282enum dwc2_halt_status {
1283 DWC2_HC_XFER_NO_HALT_STATUS,
1284 DWC2_HC_XFER_COMPLETE,
1285 DWC2_HC_XFER_URB_COMPLETE,
1286 DWC2_HC_XFER_ACK,
1287 DWC2_HC_XFER_NAK,
1288 DWC2_HC_XFER_NYET,
1289 DWC2_HC_XFER_STALL,
1290 DWC2_HC_XFER_XACT_ERR,
1291 DWC2_HC_XFER_FRAME_OVERRUN,
1292 DWC2_HC_XFER_BABBLE_ERR,
1293 DWC2_HC_XFER_DATA_TOGGLE_ERR,
1294 DWC2_HC_XFER_AHB_ERR,
1295 DWC2_HC_XFER_PERIODIC_INCOMPLETE,
1296 DWC2_HC_XFER_URB_DEQUEUE,
1297};
1298
1e6b98eb
VM		 1299/* Core version information */
1300static inline bool dwc2_is_iot(struct dwc2_hsotg *hsotg)
1301{
1302 return (hsotg->hw_params.snpsid & 0xfff00000) == 0x55300000;
1303}
1304
1305static inline bool dwc2_is_fs_iot(struct dwc2_hsotg *hsotg)
1306{
1307 return (hsotg->hw_params.snpsid & 0xffff0000) == 0x55310000;
1308}
1309
1310static inline bool dwc2_is_hs_iot(struct dwc2_hsotg *hsotg)
1311{
1312 return (hsotg->hw_params.snpsid & 0xffff0000) == 0x55320000;
1313}
1314
56f5b1cf
PZ		 1315/*
1316 * The following functions support initialization of the core driver component
1317 * and the DWC_otg controller
1318 */
6e6360b6 1319int dwc2_core_reset(struct dwc2_hsotg *hsotg, bool skip_wait);
41ba9b9b 1320int dwc2_enter_partial_power_down(struct dwc2_hsotg *hsotg);
c9c394ab
AP		 1321int dwc2_exit_partial_power_down(struct dwc2_hsotg *hsotg, int rem_wakeup,
1322 bool restore);
624815ce
VM		 1323int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg, int is_host);
1324int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, int rem_wakeup,
13b1f8e2 1325 int reset, int is_host);
059d8d52
JM		 1326void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg *hsotg);
1327int dwc2_phy_init(struct dwc2_hsotg *hsotg, bool select_phy);
56f5b1cf 1328
13b1f8e2 1329void dwc2_force_mode(struct dwc2_hsotg *hsotg, bool host);
09c96980
JY		 1330void dwc2_force_dr_mode(struct dwc2_hsotg *hsotg);
1331
9da51974 1332bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg);
56f5b1cf 1333
65dc2e72
MH		 1334int dwc2_check_core_version(struct dwc2_hsotg *hsotg);
1335
56f5b1cf
PZ		 1336/*
1337 * Common core Functions.
1338 * The following functions support managing the DWC_otg controller in either
1339 * device or host mode.
1340 */
9da51974
JY		 1341void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes);
1342void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num);
1343void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg);
56f5b1cf 1344
9da51974
JY		 1345void dwc2_enable_global_interrupts(struct dwc2_hsotg *hcd);
1346void dwc2_disable_global_interrupts(struct dwc2_hsotg *hcd);
56f5b1cf 1347
94d2666c
VM		 1348void dwc2_hib_restore_common(struct dwc2_hsotg *hsotg, int rem_wakeup,
1349 int is_host);
c5c403dc
VM		 1350int dwc2_backup_global_registers(struct dwc2_hsotg *hsotg);
1351int dwc2_restore_global_registers(struct dwc2_hsotg *hsotg);
94d2666c 1352
66e77a24
RK		 1353void dwc2_enable_acg(struct dwc2_hsotg *hsotg);
1354
56f5b1cf 1355/* This function should be called on every hardware interrupt. */
9da51974 1356irqreturn_t dwc2_handle_common_intr(int irq, void *dev);
56f5b1cf 1357
323230ef
JY		 1358/* The device ID match table */
1359extern const struct of_device_id dwc2_of_match_table[];
2e5db2c0 1360extern const struct acpi_device_id dwc2_acpi_match[];
323230ef 1361
9da51974
JY		 1362int dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg);
1363int dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg);
ecb176c6 1364
79d6b8c5
SA		 1365/* Common polling functions */
1366int dwc2_hsotg_wait_bit_set(struct dwc2_hsotg *hs_otg, u32 reg, u32 bit,
1367 u32 timeout);
1368int dwc2_hsotg_wait_bit_clear(struct dwc2_hsotg *hs_otg, u32 reg, u32 bit,
1369 u32 timeout);
334bbd4e 1370/* Parameters */
c1d286cf 1371int dwc2_get_hwparams(struct dwc2_hsotg *hsotg);
334bbd4e
JY		 1372int dwc2_init_params(struct dwc2_hsotg *hsotg);
1373
6bea9620
JY		 1374/*
1375 * The following functions check the controller's OTG operation mode
1376 * capability (GHWCFG2.OTG_MODE).
1377 *
1378 * These functions can be used before the internal hsotg->hw_params
1379 * are read in and cached so they always read directly from the
1380 * GHWCFG2 register.
1381 */
9da51974 1382unsigned int dwc2_op_mode(struct dwc2_hsotg *hsotg);
6bea9620
JY		 1383bool dwc2_hw_is_otg(struct dwc2_hsotg *hsotg);
1384bool dwc2_hw_is_host(struct dwc2_hsotg *hsotg);
1385bool dwc2_hw_is_device(struct dwc2_hsotg *hsotg);
1386
1696d5ab
JY		 1387/*
1388 * Returns the mode of operation, host or device
1389 */
1390static inline int dwc2_is_host_mode(struct dwc2_hsotg *hsotg)
1391{
f25c42b8 1392 return (dwc2_readl(hsotg, GINTSTS) & GINTSTS_CURMODE_HOST) != 0;
1696d5ab 1393}
9da51974 1394
1696d5ab
JY		 1395static inline int dwc2_is_device_mode(struct dwc2_hsotg *hsotg)
1396{
f25c42b8 1397 return (dwc2_readl(hsotg, GINTSTS) & GINTSTS_CURMODE_HOST) == 0;
1696d5ab
JY		 1398}
1399
17f93402
AD		 1400int dwc2_drd_init(struct dwc2_hsotg *hsotg);
1401void dwc2_drd_suspend(struct dwc2_hsotg *hsotg);
1402void dwc2_drd_resume(struct dwc2_hsotg *hsotg);
1403void dwc2_drd_exit(struct dwc2_hsotg *hsotg);
1404
56f5b1cf
PZ		 1405/*
1406 * Dump core registers and SPRAM
1407 */
9da51974
JY		 1408void dwc2_dump_dev_registers(struct dwc2_hsotg *hsotg);
1409void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg);
1410void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg);
56f5b1cf 1411
117777b2 1412/* Gadget defines */
b98866c2
JY		 1413#if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \
1414 IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
9da51974
JY		 1415int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg);
1416int dwc2_hsotg_suspend(struct dwc2_hsotg *dwc2);
1417int dwc2_hsotg_resume(struct dwc2_hsotg *dwc2);
f3768997 1418int dwc2_gadget_init(struct dwc2_hsotg *hsotg);
9da51974
JY		 1419void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2,
1420 bool reset);
17f93402 1421void dwc2_hsotg_core_disconnect(struct dwc2_hsotg *hsotg);
9da51974
JY		 1422void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg);
1423void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2);
1424int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode);
f81f46e1 1425#define dwc2_is_device_connected(hsotg) (hsotg->connected)
32fde843 1426#define dwc2_is_device_enabled(hsotg) (hsotg->enabled)
58e52ff6 1427int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg);
9a5d2816 1428int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg, int remote_wakeup);
c5c403dc
VM		 1429int dwc2_gadget_enter_hibernation(struct dwc2_hsotg *hsotg);
1430int dwc2_gadget_exit_hibernation(struct dwc2_hsotg *hsotg,
1431 int rem_wakeup, int reset);
be2b960e
AP		 1432int dwc2_gadget_enter_partial_power_down(struct dwc2_hsotg *hsotg);
1433int dwc2_gadget_exit_partial_power_down(struct dwc2_hsotg *hsotg,
1434 bool restore);
012466fc
AP		 1435void dwc2_gadget_enter_clock_gating(struct dwc2_hsotg *hsotg);
1436void dwc2_gadget_exit_clock_gating(struct dwc2_hsotg *hsotg,
1437 int rem_wakeup);
c138ecfa
SA		 1438int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg *hsotg);
1439int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg);
1440int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg *hsotg);
21b03405 1441void dwc2_gadget_init_lpm(struct dwc2_hsotg *hsotg);
15d9dbf8 1442void dwc2_gadget_program_ref_clk(struct dwc2_hsotg *hsotg);
238f65ae
AP		 1443static inline void dwc2_clear_fifo_map(struct dwc2_hsotg *hsotg)
1444{ hsotg->fifo_map = 0; }
117777b2 1445#else
1f91b4cc 1446static inline int dwc2_hsotg_remove(struct dwc2_hsotg *dwc2)
117777b2 1447{ return 0; }
1f91b4cc 1448static inline int dwc2_hsotg_suspend(struct dwc2_hsotg *dwc2)
117777b2 1449{ return 0; }
1f91b4cc 1450static inline int dwc2_hsotg_resume(struct dwc2_hsotg *dwc2)
117777b2 1451{ return 0; }
f3768997 1452static inline int dwc2_gadget_init(struct dwc2_hsotg *hsotg)
117777b2 1453{ return 0; }
1f91b4cc 1454static inline void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2,
9da51974 1455 bool reset) {}
17f93402 1456static inline void dwc2_hsotg_core_disconnect(struct dwc2_hsotg *hsotg) {}
1f91b4cc
FB		 1457static inline void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg) {}
1458static inline void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2) {}
1459static inline int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg,
9da51974 1460 int testmode)
f91eea44 1461{ return 0; }
f81f46e1 1462#define dwc2_is_device_connected(hsotg) (0)
32fde843 1463#define dwc2_is_device_enabled(hsotg) (0)
58e52ff6
JY		 1464static inline int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg)
1465{ return 0; }
9a5d2816
VM		 1466static inline int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg,
1467 int remote_wakeup)
58e52ff6 1468{ return 0; }
c5c403dc
VM		 1469static inline int dwc2_gadget_enter_hibernation(struct dwc2_hsotg *hsotg)
1470{ return 0; }
1471static inline int dwc2_gadget_exit_hibernation(struct dwc2_hsotg *hsotg,
1472 int rem_wakeup, int reset)
1473{ return 0; }
be2b960e
AP		 1474static inline int dwc2_gadget_enter_partial_power_down(struct dwc2_hsotg *hsotg)
1475{ return 0; }
1476static inline int dwc2_gadget_exit_partial_power_down(struct dwc2_hsotg *hsotg,
1477 bool restore)
1478{ return 0; }
012466fc
AP		 1479static inline void dwc2_gadget_enter_clock_gating(struct dwc2_hsotg *hsotg) {}
1480static inline void dwc2_gadget_exit_clock_gating(struct dwc2_hsotg *hsotg,
1481 int rem_wakeup) {}
c138ecfa
SA		 1482static inline int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg *hsotg)
1483{ return 0; }
1484static inline int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg)
1485{ return 0; }
1486static inline int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg *hsotg)
1487{ return 0; }
21b03405 1488static inline void dwc2_gadget_init_lpm(struct dwc2_hsotg *hsotg) {}
15d9dbf8 1489static inline void dwc2_gadget_program_ref_clk(struct dwc2_hsotg *hsotg) {}
238f65ae 1490static inline void dwc2_clear_fifo_map(struct dwc2_hsotg *hsotg) {}
117777b2
DN		 1491#endif
1492
1493#if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
9da51974
JY		 1494int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg);
1495int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg, int us);
1496void dwc2_hcd_connect(struct dwc2_hsotg *hsotg);
1497void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force);
1498void dwc2_hcd_start(struct dwc2_hsotg *hsotg);
65c9c4c6 1499int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup);
22ff0c8e 1500int dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex);
1e0890eb 1501int dwc2_port_resume(struct dwc2_hsotg *hsotg);
58e52ff6
JY		 1502int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg);
1503int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg);
c5c403dc
VM		 1504int dwc2_host_enter_hibernation(struct dwc2_hsotg *hsotg);
1505int dwc2_host_exit_hibernation(struct dwc2_hsotg *hsotg,
1506 int rem_wakeup, int reset);
9ce9e5ad
AP		 1507int dwc2_host_enter_partial_power_down(struct dwc2_hsotg *hsotg);
1508int dwc2_host_exit_partial_power_down(struct dwc2_hsotg *hsotg,
1509 int rem_wakeup, bool restore);
79c87c3c
AP		 1510void dwc2_host_enter_clock_gating(struct dwc2_hsotg *hsotg);
1511void dwc2_host_exit_clock_gating(struct dwc2_hsotg *hsotg, int rem_wakeup);
c846b03f 1512bool dwc2_host_can_poweroff_phy(struct dwc2_hsotg *dwc2);
c40cf770
DA		 1513static inline void dwc2_host_schedule_phy_reset(struct dwc2_hsotg *hsotg)
1514{ schedule_work(&hsotg->phy_reset_work); }
117777b2 1515#else
117777b2
DN		 1516static inline int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg)
1517{ return 0; }
fae4e826
DA		 1518static inline int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg,
1519 int us)
1520{ return 0; }
6a659531
DA		 1521static inline void dwc2_hcd_connect(struct dwc2_hsotg *hsotg) {}
1522static inline void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force) {}
117777b2
DN		 1523static inline void dwc2_hcd_start(struct dwc2_hsotg *hsotg) {}
1524static inline void dwc2_hcd_remove(struct dwc2_hsotg *hsotg) {}
65c9c4c6
VM		 1525static inline int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup)
1526{ return 0; }
22ff0c8e
AP		 1527static inline int dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex)
1528{ return 0; }
1e0890eb
AP		 1529static inline int dwc2_port_resume(struct dwc2_hsotg *hsotg)
1530{ return 0; }
4fe160d5 1531static inline int dwc2_hcd_init(struct dwc2_hsotg *hsotg)
117777b2 1532{ return 0; }
58e52ff6
JY		 1533static inline int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg)
1534{ return 0; }
1535static inline int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg)
1536{ return 0; }
c5c403dc
VM		 1537static inline int dwc2_host_enter_hibernation(struct dwc2_hsotg *hsotg)
1538{ return 0; }
1539static inline int dwc2_host_exit_hibernation(struct dwc2_hsotg *hsotg,
1540 int rem_wakeup, int reset)
1541{ return 0; }
9ce9e5ad
AP		 1542static inline int dwc2_host_enter_partial_power_down(struct dwc2_hsotg *hsotg)
1543{ return 0; }
1544static inline int dwc2_host_exit_partial_power_down(struct dwc2_hsotg *hsotg,
1545 int rem_wakeup, bool restore)
1546{ return 0; }
79c87c3c
AP		 1547static inline void dwc2_host_enter_clock_gating(struct dwc2_hsotg *hsotg) {}
1548static inline void dwc2_host_exit_clock_gating(struct dwc2_hsotg *hsotg,
1549 int rem_wakeup) {}
c846b03f
DA		 1550static inline bool dwc2_host_can_poweroff_phy(struct dwc2_hsotg *dwc2)
1551{ return false; }
c40cf770 1552static inline void dwc2_host_schedule_phy_reset(struct dwc2_hsotg *hsotg) {}
58e52ff6 1553
117777b2
DN		 1554#endif
1555
56f5b1cf 1556#endif /* __DWC2_CORE_H__ */
Linux 6.x block layer and io_uring tree(s)