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usb: dwc2: Update parameter types
[linux-2.6-block.git] / drivers / usb / dwc2 / core.h
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56f5b1cf
PZ		 1/*
2 * core.h - DesignWare HS OTG Controller common declarations
3 *
4 * Copyright (C) 2004-2013 Synopsys, Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions, and the following disclaimer,
11 * without modification.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The names of the above-listed copyright holders may not be used
16 * to endorse or promote products derived from this software without
17 * specific prior written permission.
18 *
19 * ALTERNATIVELY, this software may be distributed under the terms of the
20 * GNU General Public License ("GPL") as published by the Free Software
21 * Foundation; either version 2 of the License, or (at your option) any
22 * later version.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
25 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
28 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
29 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
30 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
31 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
32 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
33 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
34 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 */
36
37#ifndef __DWC2_CORE_H__
38#define __DWC2_CORE_H__
39
f7c0b143
DN		 40#include <linux/phy/phy.h>
41#include <linux/regulator/consumer.h>
42#include <linux/usb/gadget.h>
43#include <linux/usb/otg.h>
56f5b1cf
PZ		 44#include <linux/usb/phy.h>
45#include "hw.h"
46
74fc4a75
DA		 47/*
48 * Suggested defines for tracers:
49 * - no_printk: Disable tracing
50 * - pr_info: Print this info to the console
51 * - trace_printk: Print this info to trace buffer (good for verbose logging)
52 */
53
54#define DWC2_TRACE_SCHEDULER no_printk
55#define DWC2_TRACE_SCHEDULER_VB no_printk
56
57/* Detailed scheduler tracing, but won't overwhelm console */
58#define dwc2_sch_dbg(hsotg, fmt, ...) \
59 DWC2_TRACE_SCHEDULER(pr_fmt("%s: SCH: " fmt), \
60 dev_name(hsotg->dev), ##__VA_ARGS__)
61
62/* Verbose scheduler tracing */
63#define dwc2_sch_vdbg(hsotg, fmt, ...) \
64 DWC2_TRACE_SCHEDULER_VB(pr_fmt("%s: SCH: " fmt), \
65 dev_name(hsotg->dev), ##__VA_ARGS__)
66
23e34392
AB		 67#ifdef CONFIG_MIPS
68/*
69 * There are some MIPS machines that can run in either big-endian
70 * or little-endian mode and that use the dwc2 register without
71 * a byteswap in both ways.
72 * Unlike other architectures, MIPS apparently does not require a
73 * barrier before the __raw_writel() to synchronize with DMA but does
74 * require the barrier after the __raw_writel() to serialize a set of
75 * writes. This set of operations was added specifically for MIPS and
76 * should only be used there.
77 */
95c8bc36 78static inline u32 dwc2_readl(const void __iomem *addr)
56f5b1cf 79{
95c8bc36
AS		 80 u32 value = __raw_readl(addr);
81
82 /* In order to preserve endianness __raw_* operation is used. Therefore
83 * a barrier is needed to ensure IO access is not re-ordered across
84 * reads or writes
85 */
86 mb();
87 return value;
56f5b1cf
PZ		 88}
89
95c8bc36
AS		 90static inline void dwc2_writel(u32 value, void __iomem *addr)
91{
92 __raw_writel(value, addr);
93
94 /*
95 * In order to preserve endianness __raw_* operation is used. Therefore
96 * a barrier is needed to ensure IO access is not re-ordered across
97 * reads or writes
98 */
99 mb();
100#ifdef DWC2_LOG_WRITES
101 pr_info("INFO:: wrote %08x to %p\n", value, addr);
56f5b1cf 102#endif
95c8bc36 103}
23e34392
AB		 104#else
105/* Normal architectures just use readl/write */
106static inline u32 dwc2_readl(const void __iomem *addr)
107{
108 return readl(addr);
109}
110
111static inline void dwc2_writel(u32 value, void __iomem *addr)
112{
113 writel(value, addr);
114
115#ifdef DWC2_LOG_WRITES
116 pr_info("info:: wrote %08x to %p\n", value, addr);
117#endif
118}
119#endif
56f5b1cf
PZ		 120
121/* Maximum number of Endpoints/HostChannels */
122#define MAX_EPS_CHANNELS 16
123
1f91b4cc
FB		 124/* dwc2-hsotg declarations */
125static const char * const dwc2_hsotg_supply_names[] = {
f7c0b143
DN		 126 "vusb_d", /* digital USB supply, 1.2V */
127 "vusb_a", /* analog USB supply, 1.1V */
128};
129
b98866c2
JY		 130#define DWC2_NUM_SUPPLIES ARRAY_SIZE(dwc2_hsotg_supply_names)
131
f7c0b143
DN		 132/*
133 * EP0_MPS_LIMIT
134 *
135 * Unfortunately there seems to be a limit of the amount of data that can
136 * be transferred by IN transactions on EP0. This is either 127 bytes or 3
137 * packets (which practically means 1 packet and 63 bytes of data) when the
138 * MPS is set to 64.
139 *
140 * This means if we are wanting to move >127 bytes of data, we need to
141 * split the transactions up, but just doing one packet at a time does
142 * not work (this may be an implicit DATA0 PID on first packet of the
143 * transaction) and doing 2 packets is outside the controller's limits.
144 *
145 * If we try to lower the MPS size for EP0, then no transfers work properly
146 * for EP0, and the system will fail basic enumeration. As no cause for this
147 * has currently been found, we cannot support any large IN transfers for
148 * EP0.
149 */
150#define EP0_MPS_LIMIT 64
151
941fcce4 152struct dwc2_hsotg;
1f91b4cc 153struct dwc2_hsotg_req;
f7c0b143
DN		 154
155/**
1f91b4cc 156 * struct dwc2_hsotg_ep - driver endpoint definition.
f7c0b143
DN		 157 * @ep: The gadget layer representation of the endpoint.
158 * @name: The driver generated name for the endpoint.
159 * @queue: Queue of requests for this endpoint.
160 * @parent: Reference back to the parent device structure.
161 * @req: The current request that the endpoint is processing. This is
162 * used to indicate an request has been loaded onto the endpoint
163 * and has yet to be completed (maybe due to data move, or simply
164 * awaiting an ack from the core all the data has been completed).
165 * @debugfs: File entry for debugfs file for this endpoint.
166 * @lock: State lock to protect contents of endpoint.
167 * @dir_in: Set to true if this endpoint is of the IN direction, which
168 * means that it is sending data to the Host.
169 * @index: The index for the endpoint registers.
170 * @mc: Multi Count - number of transactions per microframe
142bd33f 171 * @interval - Interval for periodic endpoints, in frames or microframes.
f7c0b143
DN		 172 * @name: The name array passed to the USB core.
173 * @halted: Set if the endpoint has been halted.
174 * @periodic: Set if this is a periodic ep, such as Interrupt
175 * @isochronous: Set if this is a isochronous ep
8a20fa45 176 * @send_zlp: Set if we need to send a zero-length packet.
5f54c54b
VA		 177 * @desc_list_dma: The DMA address of descriptor chain currently in use.
178 * @desc_list: Pointer to descriptor DMA chain head currently in use.
179 * @desc_count: Count of entries within the DMA descriptor chain of EP.
ab7d2192
VA		 180 * @isoc_chain_num: Number of ISOC chain currently in use - either 0 or 1.
181 * @next_desc: index of next free descriptor in the ISOC chain under SW control.
f7c0b143
DN		 182 * @total_data: The total number of data bytes done.
183 * @fifo_size: The size of the FIFO (for periodic IN endpoints)
184 * @fifo_load: The amount of data loaded into the FIFO (periodic IN)
185 * @last_load: The offset of data for the last start of request.
186 * @size_loaded: The last loaded size for DxEPTSIZE for periodic IN
92d1635d
VM		 187 * @target_frame: Targeted frame num to setup next ISOC transfer
188 * @frame_overrun: Indicates SOF number overrun in DSTS
f7c0b143
DN		 189 *
190 * This is the driver's state for each registered enpoint, allowing it
191 * to keep track of transactions that need doing. Each endpoint has a
192 * lock to protect the state, to try and avoid using an overall lock
193 * for the host controller as much as possible.
194 *
195 * For periodic IN endpoints, we have fifo_size and fifo_load to try
196 * and keep track of the amount of data in the periodic FIFO for each
197 * of these as we don't have a status register that tells us how much
198 * is in each of them. (note, this may actually be useless information
199 * as in shared-fifo mode periodic in acts like a single-frame packet
200 * buffer than a fifo)
201 */
1f91b4cc 202struct dwc2_hsotg_ep {
f7c0b143
DN		 203 struct usb_ep ep;
204 struct list_head queue;
941fcce4 205 struct dwc2_hsotg *parent;
1f91b4cc 206 struct dwc2_hsotg_req *req;
f7c0b143
DN		 207 struct dentry *debugfs;
208
209 unsigned long total_data;
210 unsigned int size_loaded;
211 unsigned int last_load;
212 unsigned int fifo_load;
213 unsigned short fifo_size;
b203d0a2 214 unsigned short fifo_index;
f7c0b143
DN		 215
216 unsigned char dir_in;
217 unsigned char index;
218 unsigned char mc;
219 unsigned char interval;
220
221 unsigned int halted:1;
222 unsigned int periodic:1;
223 unsigned int isochronous:1;
8a20fa45 224 unsigned int send_zlp:1;
92d1635d
VM		 225 unsigned int target_frame;
226#define TARGET_FRAME_INITIAL 0xFFFFFFFF
227 bool frame_overrun;
f7c0b143 228
5f54c54b
VA		 229 dma_addr_t desc_list_dma;
230 struct dwc2_dma_desc *desc_list;
231 u8 desc_count;
232
ab7d2192
VA		 233 unsigned char isoc_chain_num;
234 unsigned int next_desc;
235
f7c0b143
DN		 236 char name[10];
237};
238
f7c0b143 239/**
1f91b4cc 240 * struct dwc2_hsotg_req - data transfer request
f7c0b143
DN		 241 * @req: The USB gadget request
242 * @queue: The list of requests for the endpoint this is queued for.
7d24c1b5 243 * @saved_req_buf: variable to save req.buf when bounce buffers are used.
f7c0b143 244 */
1f91b4cc 245struct dwc2_hsotg_req {
f7c0b143
DN		 246 struct usb_request req;
247 struct list_head queue;
7d24c1b5 248 void *saved_req_buf;
f7c0b143
DN		 249};
250
b98866c2
JY		 251#if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \
252 IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
f7c0b143
DN		 253#define call_gadget(_hs, _entry) \
254do { \
255 if ((_hs)->gadget.speed != USB_SPEED_UNKNOWN && \
256 (_hs)->driver && (_hs)->driver->_entry) { \
257 spin_unlock(&_hs->lock); \
258 (_hs)->driver->_entry(&(_hs)->gadget); \
259 spin_lock(&_hs->lock); \
260 } \
261} while (0)
941fcce4
DN		 262#else
263#define call_gadget(_hs, _entry) do {} while (0)
264#endif
f7c0b143 265
56f5b1cf
PZ		 266struct dwc2_hsotg;
267struct dwc2_host_chan;
268
269/* Device States */
270enum dwc2_lx_state {
271 DWC2_L0, /* On state */
272 DWC2_L1, /* LPM sleep state */
273 DWC2_L2, /* USB suspend state */
274 DWC2_L3, /* Off state */
275};
276
3fa95385
JY		 277/*
278 * Gadget periodic tx fifo sizes as used by legacy driver
279 * EP0 is not included
280 */
281#define DWC2_G_P_LEGACY_TX_FIFO_SIZE {256, 256, 256, 256, 768, 768, 768, \
282 768, 0, 0, 0, 0, 0, 0, 0}
283
fe0b94ab
MYK		 284/* Gadget ep0 states */
285enum dwc2_ep0_state {
286 DWC2_EP0_SETUP,
287 DWC2_EP0_DATA_IN,
288 DWC2_EP0_DATA_OUT,
289 DWC2_EP0_STATUS_IN,
290 DWC2_EP0_STATUS_OUT,
291};
292
56f5b1cf
PZ		 293/**
294 * struct dwc2_core_params - Parameters for configuring the core
295 *
91121c10
MK		 296 * @otg_cap: Specifies the OTG capabilities.
297 * 0 - HNP and SRP capable
56f5b1cf 298 * 1 - SRP Only capable
91121c10
MK		 299 * 2 - No HNP/SRP capable (always available)
300 * Defaults to best available option (0, 1, then 2)
e7839f99 301 * @host_dma: Specifies whether to use slave or DMA mode for accessing
56f5b1cf
PZ		 302 * the data FIFOs. The driver will automatically detect the
303 * value for this parameter if none is specified.
91121c10 304 * 0 - Slave (always available)
56f5b1cf
PZ		 305 * 1 - DMA (default, if available)
306 * @dma_desc_enable: When DMA mode is enabled, specifies whether to use
307 * address DMA mode or descriptor DMA mode for accessing
308 * the data FIFOs. The driver will automatically detect the
309 * value for this if none is specified.
310 * 0 - Address DMA
311 * 1 - Descriptor DMA (default, if available)
fbb9e22b
MYK		 312 * @dma_desc_fs_enable: When DMA mode is enabled, specifies whether to use
313 * address DMA mode or descriptor DMA mode for accessing
314 * the data FIFOs in Full Speed mode only. The driver
315 * will automatically detect the value for this if none is
316 * specified.
317 * 0 - Address DMA
318 * 1 - Descriptor DMA in FS (default, if available)
56f5b1cf
PZ		 319 * @speed: Specifies the maximum speed of operation in host and
320 * device mode. The actual speed depends on the speed of
321 * the attached device and the value of phy_type.
91121c10
MK		 322 * 0 - High Speed
323 * (default when phy_type is UTMI+ or ULPI)
56f5b1cf 324 * 1 - Full Speed
91121c10 325 * (default when phy_type is Full Speed)
56f5b1cf 326 * @enable_dynamic_fifo: 0 - Use coreConsultant-specified FIFO size parameters
91121c10 327 * 1 - Allow dynamic FIFO sizing (default, if available)
725acc86 328 * @en_multiple_tx_fifo: Specifies whether dedicated per-endpoint transmit FIFOs
c1d286cf
JY		 329 * are enabled for non-periodic IN endpoints in device
330 * mode.
56f5b1cf
PZ		 331 * @host_rx_fifo_size: Number of 4-byte words in the Rx FIFO in host mode when
332 * dynamic FIFO sizing is enabled
91121c10
MK		 333 * 16 to 32768
334 * Actual maximum value is autodetected and also
335 * the default.
56f5b1cf
PZ		 336 * @host_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO
337 * in host mode when dynamic FIFO sizing is enabled
91121c10
MK		 338 * 16 to 32768
339 * Actual maximum value is autodetected and also
340 * the default.
56f5b1cf
PZ		 341 * @host_perio_tx_fifo_size: Number of 4-byte words in the periodic Tx FIFO in
342 * host mode when dynamic FIFO sizing is enabled
91121c10
MK		 343 * 16 to 32768
344 * Actual maximum value is autodetected and also
345 * the default.
56f5b1cf 346 * @max_transfer_size: The maximum transfer size supported, in bytes
91121c10
MK		 347 * 2047 to 65,535
348 * Actual maximum value is autodetected and also
349 * the default.
56f5b1cf 350 * @max_packet_count: The maximum number of packets in a transfer
91121c10
MK		 351 * 15 to 511
352 * Actual maximum value is autodetected and also
353 * the default.
56f5b1cf 354 * @host_channels: The number of host channel registers to use
91121c10
MK		 355 * 1 to 16
356 * Actual maximum value is autodetected and also
357 * the default.
56f5b1cf
PZ		 358 * @phy_type: Specifies the type of PHY interface to use. By default,
359 * the driver will automatically detect the phy_type.
91121c10
MK		 360 * 0 - Full Speed Phy
361 * 1 - UTMI+ Phy
362 * 2 - ULPI Phy
363 * Defaults to best available option (2, 1, then 0)
56f5b1cf
PZ		 364 * @phy_utmi_width: Specifies the UTMI+ Data Width (in bits). This parameter
365 * is applicable for a phy_type of UTMI+ or ULPI. (For a
366 * ULPI phy_type, this parameter indicates the data width
367 * between the MAC and the ULPI Wrapper.) Also, this
368 * parameter is applicable only if the OTG_HSPHY_WIDTH cC
369 * parameter was set to "8 and 16 bits", meaning that the
370 * core has been configured to work at either data path
371 * width.
91121c10 372 * 8 or 16 (default 16 if available)
56f5b1cf
PZ		 373 * @phy_ulpi_ddr: Specifies whether the ULPI operates at double or single
374 * data rate. This parameter is only applicable if phy_type
375 * is ULPI.
376 * 0 - single data rate ULPI interface with 8 bit wide
377 * data bus (default)
378 * 1 - double data rate ULPI interface with 4 bit wide
379 * data bus
380 * @phy_ulpi_ext_vbus: For a ULPI phy, specifies whether to use the internal or
381 * external supply to drive the VBus
91121c10
MK		 382 * 0 - Internal supply (default)
383 * 1 - External supply
56f5b1cf
PZ		 384 * @i2c_enable: Specifies whether to use the I2Cinterface for a full
385 * speed PHY. This parameter is only applicable if phy_type
386 * is FS.
387 * 0 - No (default)
388 * 1 - Yes
91121c10
MK		 389 * @ulpi_fs_ls: Make ULPI phy operate in FS/LS mode only
390 * 0 - No (default)
391 * 1 - Yes
725acc86
PZ		 392 * @host_support_fs_ls_low_power: Specifies whether low power mode is supported
393 * when attached to a Full Speed or Low Speed device in
394 * host mode.
395 * 0 - Don't support low power mode (default)
396 * 1 - Support low power mode
397 * @host_ls_low_power_phy_clk: Specifies the PHY clock rate in low power mode
91121c10
MK		 398 * when connected to a Low Speed device in host
399 * mode. This parameter is applicable only if
400 * host_support_fs_ls_low_power is enabled.
725acc86 401 * 0 - 48 MHz
91121c10 402 * (default when phy_type is UTMI+ or ULPI)
725acc86 403 * 1 - 6 MHz
91121c10
MK		 404 * (default when phy_type is Full Speed)
405 * @ts_dline: Enable Term Select Dline pulsing
406 * 0 - No (default)
407 * 1 - Yes
408 * @reload_ctl: Allow dynamic reloading of HFIR register during runtime
409 * 0 - No (default for core < 2.92a)
410 * 1 - Yes (default for core >= 2.92a)
4d3190e1
PZ		 411 * @ahbcfg: This field allows the default value of the GAHBCFG
412 * register to be overridden
91121c10
MK		 413 * -1 - GAHBCFG value will be set to 0x06
414 * (INCR4, default)
4d3190e1
PZ		 415 * all others - GAHBCFG value will be overridden with
416 * this value
91121c10
MK		 417 * Not all bits can be controlled like this, the
418 * bits defined by GAHBCFG_CTRL_MASK are controlled
419 * by the driver and are ignored in this
420 * configuration value.
20f2eb9c 421 * @uframe_sched: True to enable the microframe scheduler
a6d249d8
GH		 422 * @external_id_pin_ctl: Specifies whether ID pin is handled externally.
423 * Disable CONIDSTSCHNG controller interrupt in such
424 * case.
425 * 0 - No (default)
426 * 1 - Yes
285046aa
GH		 427 * @hibernation: Specifies whether the controller support hibernation.
428 * If hibernation is enabled, the controller will enter
429 * hibernation in both peripheral and host mode when
430 * needed.
431 * 0 - No (default)
432 * 1 - Yes
9962b62f 433 * @g_dma: Enables gadget dma usage (default: autodetect).
dec4b556 434 * @g_dma_desc: Enables gadget descriptor DMA (default: autodetect).
05ee799f
JY		 435 * @g_rx_fifo_size: The periodic rx fifo size for the device, in
436 * DWORDS from 16-32768 (default: 2048 if
437 * possible, otherwise autodetect).
438 * @g_np_tx_fifo_size: The non-periodic tx fifo size for the device in
439 * DWORDS from 16-32768 (default: 1024 if
440 * possible, otherwise autodetect).
441 * @g_tx_fifo_size: An array of TX fifo sizes in dedicated fifo
442 * mode. Each value corresponds to one EP
443 * starting from EP1 (max 15 values). Sizes are
444 * in DWORDS with possible values from from
445 * 16-32768 (default: 256, 256, 256, 256, 768,
446 * 768, 768, 768, 0, 0, 0, 0, 0, 0, 0).
56f5b1cf
PZ		 447 *
448 * The following parameters may be specified when starting the module. These
91121c10
MK		 449 * parameters define how the DWC_otg controller should be configured. A
450 * value of -1 (or any other out of range value) for any parameter means
451 * to read the value from hardware (if possible) or use the builtin
452 * default described above.
56f5b1cf
PZ		 453 */
454struct dwc2_core_params {
d21bcc3f 455 u8 otg_cap;
c1d286cf
JY		 456#define DWC2_CAP_PARAM_HNP_SRP_CAPABLE 0
457#define DWC2_CAP_PARAM_SRP_ONLY_CAPABLE 1
458#define DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE 2
459
d21bcc3f
JY		 460 bool dma_desc_enable;
461 bool dma_desc_fs_enable;
462 u8 speed;
c1d286cf
JY		 463#define DWC2_SPEED_PARAM_HIGH 0
464#define DWC2_SPEED_PARAM_FULL 1
38e9002b 465#define DWC2_SPEED_PARAM_LOW 2
c1d286cf 466
d21bcc3f
JY		 467 bool enable_dynamic_fifo;
468 bool en_multiple_tx_fifo;
469 u16 host_rx_fifo_size;
470 u16 host_nperio_tx_fifo_size;
471 u16 host_perio_tx_fifo_size;
472 u32 max_transfer_size;
473 u16 max_packet_count;
474 u8 host_channels;
475 u8 phy_type;
c1d286cf
JY		 476#define DWC2_PHY_TYPE_PARAM_FS 0
477#define DWC2_PHY_TYPE_PARAM_UTMI 1
478#define DWC2_PHY_TYPE_PARAM_ULPI 2
479
d21bcc3f
JY		 480 u8 phy_utmi_width;
481 bool phy_ulpi_ddr;
482 bool phy_ulpi_ext_vbus;
c1d286cf
JY		 483#define DWC2_PHY_ULPI_INTERNAL_VBUS 0
484#define DWC2_PHY_ULPI_EXTERNAL_VBUS 1
485
d21bcc3f
JY		 486 bool i2c_enable;
487 bool ulpi_fs_ls;
488 bool host_support_fs_ls_low_power;
489 bool host_ls_low_power_phy_clk;
c1d286cf
JY		 490#define DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ 0
491#define DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ 1
492
d21bcc3f
JY		 493 bool ts_dline;
494 bool reload_ctl;
495 u32 ahbcfg;
496 bool uframe_sched;
497 bool external_id_pin_ctl;
498 bool hibernation;
05ee799f
JY		 499
500 /*
501 * The following parameters are *only* set via device
502 * properties and cannot be set directly in this structure.
503 */
6b66ce51
JY		 504
505 /* Host parameters */
506 bool host_dma;
507
508 /* Gadget parameters */
05ee799f 509 bool g_dma;
dec4b556 510 bool g_dma_desc;
00c704cc
LY		 511 u32 g_rx_fifo_size;
512 u32 g_np_tx_fifo_size;
05ee799f 513 u32 g_tx_fifo_size[MAX_EPS_CHANNELS];
56f5b1cf
PZ		 514};
515
9badec2f
MK		 516/**
517 * struct dwc2_hw_params - Autodetected parameters.
518 *
519 * These parameters are the various parameters read from hardware
520 * registers during initialization. They typically contain the best
521 * supported or maximum value that can be configured in the
522 * corresponding dwc2_core_params value.
523 *
524 * The values that are not in dwc2_core_params are documented below.
525 *
526 * @op_mode Mode of Operation
527 * 0 - HNP- and SRP-Capable OTG (Host & Device)
528 * 1 - SRP-Capable OTG (Host & Device)
529 * 2 - Non-HNP and Non-SRP Capable OTG (Host & Device)
530 * 3 - SRP-Capable Device
531 * 4 - Non-OTG Device
532 * 5 - SRP-Capable Host
533 * 6 - Non-OTG Host
534 * @arch Architecture
535 * 0 - Slave only
536 * 1 - External DMA
537 * 2 - Internal DMA
538 * @power_optimized Are power optimizations enabled?
539 * @num_dev_ep Number of device endpoints available
540 * @num_dev_perio_in_ep Number of device periodic IN endpoints
997f4f81 541 * available
9badec2f
MK		 542 * @dev_token_q_depth Device Mode IN Token Sequence Learning Queue
543 * Depth
544 * 0 to 30
545 * @host_perio_tx_q_depth
546 * Host Mode Periodic Request Queue Depth
547 * 2, 4 or 8
548 * @nperio_tx_q_depth
549 * Non-Periodic Request Queue Depth
550 * 2, 4 or 8
551 * @hs_phy_type High-speed PHY interface type
552 * 0 - High-speed interface not supported
553 * 1 - UTMI+
554 * 2 - ULPI
555 * 3 - UTMI+ and ULPI
556 * @fs_phy_type Full-speed PHY interface type
557 * 0 - Full speed interface not supported
558 * 1 - Dedicated full speed interface
559 * 2 - FS pins shared with UTMI+ pins
560 * 3 - FS pins shared with ULPI pins
561 * @total_fifo_size: Total internal RAM for FIFOs (bytes)
de4a1931
MK		 562 * @utmi_phy_data_width UTMI+ PHY data width
563 * 0 - 8 bits
564 * 1 - 16 bits
565 * 2 - 8 or 16 bits
9badec2f 566 * @snpsid: Value from SNPSID register
55e1040e 567 * @dev_ep_dirs: Direction of device endpoints (GHWCFG1)
9badec2f
MK		 568 */
569struct dwc2_hw_params {
570 unsigned op_mode:3;
571 unsigned arch:2;
572 unsigned dma_desc_enable:1;
573 unsigned enable_dynamic_fifo:1;
574 unsigned en_multiple_tx_fifo:1;
d1531319 575 unsigned rx_fifo_size:16;
9badec2f 576 unsigned host_nperio_tx_fifo_size:16;
55e1040e 577 unsigned dev_nperio_tx_fifo_size:16;
9badec2f
MK		 578 unsigned host_perio_tx_fifo_size:16;
579 unsigned nperio_tx_q_depth:3;
580 unsigned host_perio_tx_q_depth:3;
581 unsigned dev_token_q_depth:5;
582 unsigned max_transfer_size:26;
583 unsigned max_packet_count:11;
2d115547 584 unsigned host_channels:5;
9badec2f
MK		 585 unsigned hs_phy_type:2;
586 unsigned fs_phy_type:2;
587 unsigned i2c_enable:1;
588 unsigned num_dev_ep:4;
589 unsigned num_dev_perio_in_ep:4;
590 unsigned total_fifo_size:16;
591 unsigned power_optimized:1;
de4a1931 592 unsigned utmi_phy_data_width:2;
9badec2f 593 u32 snpsid;
55e1040e 594 u32 dev_ep_dirs;
9badec2f
MK		 595};
596
3f95001d
MYK		 597/* Size of control and EP0 buffers */
598#define DWC2_CTRL_BUFF_SIZE 8
599
d17ee77b 600/**
38beaec6
JY		 601 * struct dwc2_gregs_backup - Holds global registers state before
602 * entering partial power down
d17ee77b
GH		 603 * @gotgctl: Backup of GOTGCTL register
604 * @gintmsk: Backup of GINTMSK register
605 * @gahbcfg: Backup of GAHBCFG register
606 * @gusbcfg: Backup of GUSBCFG register
607 * @grxfsiz: Backup of GRXFSIZ register
608 * @gnptxfsiz: Backup of GNPTXFSIZ register
609 * @gi2cctl: Backup of GI2CCTL register
610 * @hptxfsiz: Backup of HPTXFSIZ register
611 * @gdfifocfg: Backup of GDFIFOCFG register
612 * @dtxfsiz: Backup of DTXFSIZ registers for each endpoint
613 * @gpwrdn: Backup of GPWRDN register
614 */
615struct dwc2_gregs_backup {
616 u32 gotgctl;
617 u32 gintmsk;
618 u32 gahbcfg;
619 u32 gusbcfg;
620 u32 grxfsiz;
621 u32 gnptxfsiz;
622 u32 gi2cctl;
623 u32 hptxfsiz;
624 u32 pcgcctl;
625 u32 gdfifocfg;
626 u32 dtxfsiz[MAX_EPS_CHANNELS];
627 u32 gpwrdn;
cc1e204c 628 bool valid;
d17ee77b
GH		 629};
630
631/**
38beaec6
JY		 632 * struct dwc2_dregs_backup - Holds device registers state before
633 * entering partial power down
d17ee77b
GH		 634 * @dcfg: Backup of DCFG register
635 * @dctl: Backup of DCTL register
636 * @daintmsk: Backup of DAINTMSK register
637 * @diepmsk: Backup of DIEPMSK register
638 * @doepmsk: Backup of DOEPMSK register
639 * @diepctl: Backup of DIEPCTL register
640 * @dieptsiz: Backup of DIEPTSIZ register
641 * @diepdma: Backup of DIEPDMA register
642 * @doepctl: Backup of DOEPCTL register
643 * @doeptsiz: Backup of DOEPTSIZ register
644 * @doepdma: Backup of DOEPDMA register
645 */
646struct dwc2_dregs_backup {
647 u32 dcfg;
648 u32 dctl;
649 u32 daintmsk;
650 u32 diepmsk;
651 u32 doepmsk;
652 u32 diepctl[MAX_EPS_CHANNELS];
653 u32 dieptsiz[MAX_EPS_CHANNELS];
654 u32 diepdma[MAX_EPS_CHANNELS];
655 u32 doepctl[MAX_EPS_CHANNELS];
656 u32 doeptsiz[MAX_EPS_CHANNELS];
657 u32 doepdma[MAX_EPS_CHANNELS];
cc1e204c 658 bool valid;
d17ee77b
GH		 659};
660
661/**
38beaec6
JY		 662 * struct dwc2_hregs_backup - Holds host registers state before
663 * entering partial power down
d17ee77b
GH		 664 * @hcfg: Backup of HCFG register
665 * @haintmsk: Backup of HAINTMSK register
666 * @hcintmsk: Backup of HCINTMSK register
667 * @hptr0: Backup of HPTR0 register
668 * @hfir: Backup of HFIR register
669 */
670struct dwc2_hregs_backup {
671 u32 hcfg;
672 u32 haintmsk;
673 u32 hcintmsk[MAX_EPS_CHANNELS];
674 u32 hprt0;
675 u32 hfir;
cc1e204c 676 bool valid;
d17ee77b
GH		 677};
678
9f9f09b0
DA		 679/*
680 * Constants related to high speed periodic scheduling
681 *
682 * We have a periodic schedule that is DWC2_HS_SCHEDULE_UFRAMES long. From a
683 * reservation point of view it's assumed that the schedule goes right back to
684 * the beginning after the end of the schedule.
685 *
686 * What does that mean for scheduling things with a long interval? It means
687 * we'll reserve time for them in every possible microframe that they could
688 * ever be scheduled in. ...but we'll still only actually schedule them as
689 * often as they were requested.
690 *
691 * We keep our schedule in a "bitmap" structure. This simplifies having
692 * to keep track of and merge intervals: we just let the bitmap code do most
693 * of the heavy lifting. In a way scheduling is much like memory allocation.
694 *
695 * We schedule 100us per uframe or 80% of 125us (the maximum amount you're
696 * supposed to schedule for periodic transfers). That's according to spec.
697 *
698 * Note that though we only schedule 80% of each microframe, the bitmap that we
699 * keep the schedule in is tightly packed (AKA it doesn't have 100us worth of
700 * space for each uFrame).
701 *
702 * Requirements:
703 * - DWC2_HS_SCHEDULE_UFRAMES must even divide 0x4000 (HFNUM_MAX_FRNUM + 1)
704 * - DWC2_HS_SCHEDULE_UFRAMES must be 8 times DWC2_LS_SCHEDULE_FRAMES (probably
705 * could be any multiple of 8 times DWC2_LS_SCHEDULE_FRAMES, but there might
706 * be bugs). The 8 comes from the USB spec: number of microframes per frame.
707 */
708#define DWC2_US_PER_UFRAME 125
709#define DWC2_HS_PERIODIC_US_PER_UFRAME 100
710
711#define DWC2_HS_SCHEDULE_UFRAMES 8
712#define DWC2_HS_SCHEDULE_US (DWC2_HS_SCHEDULE_UFRAMES * \
713 DWC2_HS_PERIODIC_US_PER_UFRAME)
714
715/*
716 * Constants related to low speed scheduling
717 *
718 * For high speed we schedule every 1us. For low speed that's a bit overkill,
719 * so we make up a unit called a "slice" that's worth 25us. There are 40
720 * slices in a full frame and we can schedule 36 of those (90%) for periodic
721 * transfers.
722 *
723 * Our low speed schedule can be as short as 1 frame or could be longer. When
724 * we only schedule 1 frame it means that we'll need to reserve a time every
725 * frame even for things that only transfer very rarely, so something that runs
726 * every 2048 frames will get time reserved in every frame. Our low speed
727 * schedule can be longer and we'll be able to handle more overlap, but that
728 * will come at increased memory cost and increased time to schedule.
729 *
730 * Note: one other advantage of a short low speed schedule is that if we mess
731 * up and miss scheduling we can jump in and use any of the slots that we
732 * happened to reserve.
733 *
734 * With 25 us per slice and 1 frame in the schedule, we only need 4 bytes for
735 * the schedule. There will be one schedule per TT.
736 *
737 * Requirements:
738 * - DWC2_US_PER_SLICE must evenly divide DWC2_LS_PERIODIC_US_PER_FRAME.
739 */
740#define DWC2_US_PER_SLICE 25
741#define DWC2_SLICES_PER_UFRAME (DWC2_US_PER_UFRAME / DWC2_US_PER_SLICE)
742
743#define DWC2_ROUND_US_TO_SLICE(us) \
744 (DIV_ROUND_UP((us), DWC2_US_PER_SLICE) * \
745 DWC2_US_PER_SLICE)
746
747#define DWC2_LS_PERIODIC_US_PER_FRAME \
748 900
749#define DWC2_LS_PERIODIC_SLICES_PER_FRAME \
750 (DWC2_LS_PERIODIC_US_PER_FRAME / \
751 DWC2_US_PER_SLICE)
752
753#define DWC2_LS_SCHEDULE_FRAMES 1
754#define DWC2_LS_SCHEDULE_SLICES (DWC2_LS_SCHEDULE_FRAMES * \
755 DWC2_LS_PERIODIC_SLICES_PER_FRAME)
756
56f5b1cf
PZ		 757/**
758 * struct dwc2_hsotg - Holds the state of the driver, including the non-periodic
759 * and periodic schedules
760 *
941fcce4
DN		 761 * These are common for both host and peripheral modes:
762 *
56f5b1cf
PZ		 763 * @dev: The struct device pointer
764 * @regs: Pointer to controller regs
9badec2f
MK		 765 * @hw_params: Parameters that were autodetected from the
766 * hardware registers
941fcce4 767 * @core_params: Parameters that define how the core should be configured
56f5b1cf
PZ		 768 * @op_state: The operational State, during transitions (a_host=>
769 * a_peripheral and b_device=>b_host) this may not match
770 * the core, but allows the software to determine
771 * transitions
c0155b9d
KY		 772 * @dr_mode: Requested mode of operation, one of following:
773 * - USB_DR_MODE_PERIPHERAL
774 * - USB_DR_MODE_HOST
775 * - USB_DR_MODE_OTG
09a75e85
MS		 776 * @hcd_enabled Host mode sub-driver initialization indicator.
777 * @gadget_enabled Peripheral mode sub-driver initialization indicator.
778 * @ll_hw_enabled Status of low-level hardware resources.
779 * @phy: The otg phy transceiver structure for phy control.
38beaec6
JY		 780 * @uphy: The otg phy transceiver structure for old USB phy
781 * control.
782 * @plat: The platform specific configuration data. This can be
783 * removed once all SoCs support usb transceiver.
09a75e85
MS		 784 * @supplies: Definition of USB power supplies
785 * @phyif: PHY interface width
941fcce4
DN		 786 * @lock: Spinlock that protects all the driver data structures
787 * @priv: Stores a pointer to the struct usb_hcd
56f5b1cf
PZ		 788 * @queuing_high_bandwidth: True if multiple packets of a high-bandwidth
789 * transfer are in process of being queued
790 * @srp_success: Stores status of SRP request in the case of a FS PHY
791 * with an I2C interface
792 * @wq_otg: Workqueue object used for handling of some interrupts
793 * @wf_otg: Work object for handling Connector ID Status Change
794 * interrupt
795 * @wkp_timer: Timer object for handling Wakeup Detected interrupt
796 * @lx_state: Lx state of connected device
d17ee77b
GH		 797 * @gregs_backup: Backup of global registers during suspend
798 * @dregs_backup: Backup of device registers during suspend
799 * @hregs_backup: Backup of host registers during suspend
941fcce4
DN		 800 *
801 * These are for host mode:
802 *
56f5b1cf
PZ		 803 * @flags: Flags for handling root port state changes
804 * @non_periodic_sched_inactive: Inactive QHs in the non-periodic schedule.
805 * Transfers associated with these QHs are not currently
806 * assigned to a host channel.
807 * @non_periodic_sched_active: Active QHs in the non-periodic schedule.
808 * Transfers associated with these QHs are currently
809 * assigned to a host channel.
810 * @non_periodic_qh_ptr: Pointer to next QH to process in the active
811 * non-periodic schedule
812 * @periodic_sched_inactive: Inactive QHs in the periodic schedule. This is a
813 * list of QHs for periodic transfers that are _not_
814 * scheduled for the next frame. Each QH in the list has an
815 * interval counter that determines when it needs to be
816 * scheduled for execution. This scheduling mechanism
817 * allows only a simple calculation for periodic bandwidth
818 * used (i.e. must assume that all periodic transfers may
819 * need to execute in the same frame). However, it greatly
820 * simplifies scheduling and should be sufficient for the
821 * vast majority of OTG hosts, which need to connect to a
822 * small number of peripherals at one time. Items move from
823 * this list to periodic_sched_ready when the QH interval
824 * counter is 0 at SOF.
825 * @periodic_sched_ready: List of periodic QHs that are ready for execution in
826 * the next frame, but have not yet been assigned to host
827 * channels. Items move from this list to
828 * periodic_sched_assigned as host channels become
829 * available during the current frame.
830 * @periodic_sched_assigned: List of periodic QHs to be executed in the next
831 * frame that are assigned to host channels. Items move
832 * from this list to periodic_sched_queued as the
833 * transactions for the QH are queued to the DWC_otg
834 * controller.
835 * @periodic_sched_queued: List of periodic QHs that have been queued for
836 * execution. Items move from this list to either
837 * periodic_sched_inactive or periodic_sched_ready when the
838 * channel associated with the transfer is released. If the
839 * interval for the QH is 1, the item moves to
840 * periodic_sched_ready because it must be rescheduled for
841 * the next frame. Otherwise, the item moves to
842 * periodic_sched_inactive.
c9c8ac01 843 * @split_order: List keeping track of channels doing splits, in order.
56f5b1cf
PZ		 844 * @periodic_usecs: Total bandwidth claimed so far for periodic transfers.
845 * This value is in microseconds per (micro)frame. The
846 * assumption is that all periodic transfers may occur in
847 * the same (micro)frame.
9f9f09b0
DA		 848 * @hs_periodic_bitmap: Bitmap used by the microframe scheduler any time the
849 * host is in high speed mode; low speed schedules are
850 * stored elsewhere since we need one per TT.
56f5b1cf
PZ		 851 * @frame_number: Frame number read from the core at SOF. The value ranges
852 * from 0 to HFNUM_MAX_FRNUM.
853 * @periodic_qh_count: Count of periodic QHs, if using several eps. Used for
854 * SOF enable/disable.
855 * @free_hc_list: Free host channels in the controller. This is a list of
856 * struct dwc2_host_chan items.
857 * @periodic_channels: Number of host channels assigned to periodic transfers.
858 * Currently assuming that there is a dedicated host
859 * channel for each periodic transaction and at least one
860 * host channel is available for non-periodic transactions.
861 * @non_periodic_channels: Number of host channels assigned to non-periodic
862 * transfers
20f2eb9c
DC		 863 * @available_host_channels Number of host channels available for the microframe
864 * scheduler to use
56f5b1cf
PZ		 865 * @hc_ptr_array: Array of pointers to the host channel descriptors.
866 * Allows accessing a host channel descriptor given the
867 * host channel number. This is useful in interrupt
868 * handlers.
869 * @status_buf: Buffer used for data received during the status phase of
870 * a control transfer.
871 * @status_buf_dma: DMA address for status_buf
872 * @start_work: Delayed work for handling host A-cable connection
873 * @reset_work: Delayed work for handling a port reset
56f5b1cf
PZ		 874 * @otg_port: OTG port number
875 * @frame_list: Frame list
876 * @frame_list_dma: Frame list DMA address
95105a99 877 * @frame_list_sz: Frame list size
3b5fcc9a
GH		 878 * @desc_gen_cache: Kmem cache for generic descriptors
879 * @desc_hsisoc_cache: Kmem cache for hs isochronous descriptors
941fcce4
DN		 880 *
881 * These are for peripheral mode:
882 *
883 * @driver: USB gadget driver
941fcce4
DN		 884 * @dedicated_fifos: Set if the hardware has dedicated IN-EP fifos.
885 * @num_of_eps: Number of available EPs (excluding EP0)
886 * @debug_root: Root directrory for debugfs.
887 * @debug_file: Main status file for debugfs.
9e14d0a5 888 * @debug_testmode: Testmode status file for debugfs.
941fcce4
DN		 889 * @debug_fifo: FIFO status file for debugfs.
890 * @ep0_reply: Request used for ep0 reply.
891 * @ep0_buff: Buffer for EP0 reply data, if needed.
892 * @ctrl_buff: Buffer for EP0 control requests.
893 * @ctrl_req: Request for EP0 control packets.
fe0b94ab 894 * @ep0_state: EP0 control transfers state
9e14d0a5 895 * @test_mode: USB test mode requested by the host
0f6b80c0
VA		 896 * @setup_desc_dma: EP0 setup stage desc chain DMA address
897 * @setup_desc: EP0 setup stage desc chain pointer
898 * @ctrl_in_desc_dma: EP0 IN data phase desc chain DMA address
899 * @ctrl_in_desc: EP0 IN data phase desc chain pointer
900 * @ctrl_out_desc_dma: EP0 OUT data phase desc chain DMA address
901 * @ctrl_out_desc: EP0 OUT data phase desc chain pointer
941fcce4 902 * @eps: The endpoints being supplied to the gadget framework
56f5b1cf
PZ		 903 */
904struct dwc2_hsotg {
905 struct device *dev;
906 void __iomem *regs;
9badec2f
MK		 907 /** Params detected from hardware */
908 struct dwc2_hw_params hw_params;
909 /** Params to actually use */
bea8e86c 910 struct dwc2_core_params params;
56f5b1cf 911 enum usb_otg_state op_state;
c0155b9d 912 enum usb_dr_mode dr_mode;
e39af88f
MS		 913 unsigned int hcd_enabled:1;
914 unsigned int gadget_enabled:1;
09a75e85 915 unsigned int ll_hw_enabled:1;
56f5b1cf 916
941fcce4
DN		 917 struct phy *phy;
918 struct usb_phy *uphy;
09a75e85 919 struct dwc2_hsotg_plat *plat;
b98866c2 920 struct regulator_bulk_data supplies[DWC2_NUM_SUPPLIES];
09a75e85 921 u32 phyif;
941fcce4
DN		 922
923 spinlock_t lock;
924 void *priv;
925 int irq;
926 struct clk *clk;
83f8da56 927 struct reset_control *reset;
941fcce4 928
56f5b1cf
PZ		 929 unsigned int queuing_high_bandwidth:1;
930 unsigned int srp_success:1;
931
932 struct workqueue_struct *wq_otg;
933 struct work_struct wf_otg;
934 struct timer_list wkp_timer;
935 enum dwc2_lx_state lx_state;
cc1e204c
MYK		 936 struct dwc2_gregs_backup gr_backup;
937 struct dwc2_dregs_backup dr_backup;
938 struct dwc2_hregs_backup hr_backup;
56f5b1cf 939
941fcce4 940 struct dentry *debug_root;
563cf017 941 struct debugfs_regset32 *regset;
941fcce4
DN		 942
943 /* DWC OTG HW Release versions */
944#define DWC2_CORE_REV_2_71a 0x4f54271a
945#define DWC2_CORE_REV_2_90a 0x4f54290a
946#define DWC2_CORE_REV_2_92a 0x4f54292a
947#define DWC2_CORE_REV_2_94a 0x4f54294a
948#define DWC2_CORE_REV_3_00a 0x4f54300a
fef6bc37 949#define DWC2_CORE_REV_3_10a 0x4f54310a
1e6b98eb
VM		 950#define DWC2_FS_IOT_REV_1_00a 0x5531100a
951#define DWC2_HS_IOT_REV_1_00a 0x5532100a
941fcce4
DN		 952
953#if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
56f5b1cf
PZ		 954 union dwc2_hcd_internal_flags {
955 u32 d32;
956 struct {
957 unsigned port_connect_status_change:1;
958 unsigned port_connect_status:1;
959 unsigned port_reset_change:1;
960 unsigned port_enable_change:1;
961 unsigned port_suspend_change:1;
962 unsigned port_over_current_change:1;
963 unsigned port_l1_change:1;
fd4850cf 964 unsigned reserved:25;
56f5b1cf
PZ		 965 } b;
966 } flags;
967
968 struct list_head non_periodic_sched_inactive;
969 struct list_head non_periodic_sched_active;
970 struct list_head *non_periodic_qh_ptr;
971 struct list_head periodic_sched_inactive;
972 struct list_head periodic_sched_ready;
973 struct list_head periodic_sched_assigned;
974 struct list_head periodic_sched_queued;
c9c8ac01 975 struct list_head split_order;
56f5b1cf 976 u16 periodic_usecs;
9f9f09b0
DA		 977 unsigned long hs_periodic_bitmap[
978 DIV_ROUND_UP(DWC2_HS_SCHEDULE_US, BITS_PER_LONG)];
56f5b1cf
PZ		 979 u16 frame_number;
980 u16 periodic_qh_count;
734643df 981 bool bus_suspended;
fbb9e22b 982 bool new_connection;
56f5b1cf 983
483bb254
DA		 984 u16 last_frame_num;
985
56f5b1cf
PZ		 986#ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
987#define FRAME_NUM_ARRAY_SIZE 1000
56f5b1cf
PZ		 988 u16 *frame_num_array;
989 u16 *last_frame_num_array;
990 int frame_num_idx;
991 int dumped_frame_num_array;
992#endif
993
994 struct list_head free_hc_list;
995 int periodic_channels;
996 int non_periodic_channels;
20f2eb9c 997 int available_host_channels;
56f5b1cf
PZ		 998 struct dwc2_host_chan *hc_ptr_array[MAX_EPS_CHANNELS];
999 u8 *status_buf;
1000 dma_addr_t status_buf_dma;
1001#define DWC2_HCD_STATUS_BUF_SIZE 64
1002
1003 struct delayed_work start_work;
1004 struct delayed_work reset_work;
56f5b1cf
PZ		 1005 u8 otg_port;
1006 u32 *frame_list;
1007 dma_addr_t frame_list_dma;
95105a99 1008 u32 frame_list_sz;
3b5fcc9a
GH		 1009 struct kmem_cache *desc_gen_cache;
1010 struct kmem_cache *desc_hsisoc_cache;
56f5b1cf 1011
56f5b1cf
PZ		 1012#ifdef DEBUG
1013 u32 frrem_samples;
1014 u64 frrem_accum;
1015
1016 u32 hfnum_7_samples_a;
1017 u64 hfnum_7_frrem_accum_a;
1018 u32 hfnum_0_samples_a;
1019 u64 hfnum_0_frrem_accum_a;
1020 u32 hfnum_other_samples_a;
1021 u64 hfnum_other_frrem_accum_a;
1022
1023 u32 hfnum_7_samples_b;
1024 u64 hfnum_7_frrem_accum_b;
1025 u32 hfnum_0_samples_b;
1026 u64 hfnum_0_frrem_accum_b;
1027 u32 hfnum_other_samples_b;
1028 u64 hfnum_other_frrem_accum_b;
1029#endif
941fcce4
DN		 1030#endif /* CONFIG_USB_DWC2_HOST || CONFIG_USB_DWC2_DUAL_ROLE */
1031
b98866c2
JY		 1032#if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \
1033 IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
941fcce4
DN		 1034 /* Gadget structures */
1035 struct usb_gadget_driver *driver;
941fcce4
DN		 1036 int fifo_mem;
1037 unsigned int dedicated_fifos:1;
1038 unsigned char num_of_eps;
1039 u32 fifo_map;
1040
1041 struct usb_request *ep0_reply;
1042 struct usb_request *ctrl_req;
3f95001d
MYK		 1043 void *ep0_buff;
1044 void *ctrl_buff;
fe0b94ab 1045 enum dwc2_ep0_state ep0_state;
9e14d0a5 1046 u8 test_mode;
941fcce4 1047
0f6b80c0
VA		 1048 dma_addr_t setup_desc_dma[2];
1049 struct dwc2_dma_desc *setup_desc[2];
1050 dma_addr_t ctrl_in_desc_dma;
1051 struct dwc2_dma_desc *ctrl_in_desc;
1052 dma_addr_t ctrl_out_desc_dma;
1053 struct dwc2_dma_desc *ctrl_out_desc;
1054
941fcce4 1055 struct usb_gadget gadget;
dc6e69e6 1056 unsigned int enabled:1;
4ace06e8 1057 unsigned int connected:1;
1f91b4cc
FB		 1058 struct dwc2_hsotg_ep *eps_in[MAX_EPS_CHANNELS];
1059 struct dwc2_hsotg_ep *eps_out[MAX_EPS_CHANNELS];
941fcce4 1060#endif /* CONFIG_USB_DWC2_PERIPHERAL || CONFIG_USB_DWC2_DUAL_ROLE */
56f5b1cf
PZ		 1061};
1062
1063/* Reasons for halting a host channel */
1064enum dwc2_halt_status {
1065 DWC2_HC_XFER_NO_HALT_STATUS,
1066 DWC2_HC_XFER_COMPLETE,
1067 DWC2_HC_XFER_URB_COMPLETE,
1068 DWC2_HC_XFER_ACK,
1069 DWC2_HC_XFER_NAK,
1070 DWC2_HC_XFER_NYET,
1071 DWC2_HC_XFER_STALL,
1072 DWC2_HC_XFER_XACT_ERR,
1073 DWC2_HC_XFER_FRAME_OVERRUN,
1074 DWC2_HC_XFER_BABBLE_ERR,
1075 DWC2_HC_XFER_DATA_TOGGLE_ERR,
1076 DWC2_HC_XFER_AHB_ERR,
1077 DWC2_HC_XFER_PERIODIC_INCOMPLETE,
1078 DWC2_HC_XFER_URB_DEQUEUE,
1079};
1080
1e6b98eb
VM		 1081/* Core version information */
1082static inline bool dwc2_is_iot(struct dwc2_hsotg *hsotg)
1083{
1084 return (hsotg->hw_params.snpsid & 0xfff00000) == 0x55300000;
1085}
1086
1087static inline bool dwc2_is_fs_iot(struct dwc2_hsotg *hsotg)
1088{
1089 return (hsotg->hw_params.snpsid & 0xffff0000) == 0x55310000;
1090}
1091
1092static inline bool dwc2_is_hs_iot(struct dwc2_hsotg *hsotg)
1093{
1094 return (hsotg->hw_params.snpsid & 0xffff0000) == 0x55320000;
1095}
1096
56f5b1cf
PZ		 1097/*
1098 * The following functions support initialization of the core driver component
1099 * and the DWC_otg controller
1100 */
9da51974
JY		 1101int dwc2_core_reset(struct dwc2_hsotg *hsotg);
1102int dwc2_core_reset_and_force_dr_mode(struct dwc2_hsotg *hsotg);
1103int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg);
1104int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, bool restore);
56f5b1cf 1105
323230ef
JY		 1106bool dwc2_force_mode_if_needed(struct dwc2_hsotg *hsotg, bool host);
1107void dwc2_clear_force_mode(struct dwc2_hsotg *hsotg);
09c96980
JY		 1108void dwc2_force_dr_mode(struct dwc2_hsotg *hsotg);
1109
9da51974 1110bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg);
56f5b1cf
PZ		 1111
1112/*
1113 * Common core Functions.
1114 * The following functions support managing the DWC_otg controller in either
1115 * device or host mode.
1116 */
9da51974
JY		 1117void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes);
1118void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num);
1119void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg);
56f5b1cf 1120
9da51974
JY		 1121void dwc2_enable_global_interrupts(struct dwc2_hsotg *hcd);
1122void dwc2_disable_global_interrupts(struct dwc2_hsotg *hcd);
56f5b1cf
PZ		 1123
1124/* This function should be called on every hardware interrupt. */
9da51974 1125irqreturn_t dwc2_handle_common_intr(int irq, void *dev);
56f5b1cf 1126
323230ef
JY		 1127/* The device ID match table */
1128extern const struct of_device_id dwc2_of_match_table[];
1129
9da51974
JY		 1130int dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg);
1131int dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg);
ecb176c6 1132
334bbd4e 1133/* Parameters */
c1d286cf 1134int dwc2_get_hwparams(struct dwc2_hsotg *hsotg);
334bbd4e
JY		 1135int dwc2_init_params(struct dwc2_hsotg *hsotg);
1136
6bea9620
JY		 1137/*
1138 * The following functions check the controller's OTG operation mode
1139 * capability (GHWCFG2.OTG_MODE).
1140 *
1141 * These functions can be used before the internal hsotg->hw_params
1142 * are read in and cached so they always read directly from the
1143 * GHWCFG2 register.
1144 */
9da51974 1145unsigned int dwc2_op_mode(struct dwc2_hsotg *hsotg);
6bea9620
JY		 1146bool dwc2_hw_is_otg(struct dwc2_hsotg *hsotg);
1147bool dwc2_hw_is_host(struct dwc2_hsotg *hsotg);
1148bool dwc2_hw_is_device(struct dwc2_hsotg *hsotg);
1149
1696d5ab
JY		 1150/*
1151 * Returns the mode of operation, host or device
1152 */
1153static inline int dwc2_is_host_mode(struct dwc2_hsotg *hsotg)
1154{
1155 return (dwc2_readl(hsotg->regs + GINTSTS) & GINTSTS_CURMODE_HOST) != 0;
1156}
9da51974 1157
1696d5ab
JY		 1158static inline int dwc2_is_device_mode(struct dwc2_hsotg *hsotg)
1159{
1160 return (dwc2_readl(hsotg->regs + GINTSTS) & GINTSTS_CURMODE_HOST) == 0;
1161}
1162
56f5b1cf
PZ		 1163/*
1164 * Dump core registers and SPRAM
1165 */
9da51974
JY		 1166void dwc2_dump_dev_registers(struct dwc2_hsotg *hsotg);
1167void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg);
1168void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg);
56f5b1cf 1169
117777b2 1170/* Gadget defines */
b98866c2
JY		 1171#if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \
1172 IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
9da51974
JY		 1173int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg);
1174int dwc2_hsotg_suspend(struct dwc2_hsotg *dwc2);
1175int dwc2_hsotg_resume(struct dwc2_hsotg *dwc2);
1176int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq);
1177void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2,
1178 bool reset);
1179void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg);
1180void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2);
1181int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode);
f81f46e1 1182#define dwc2_is_device_connected(hsotg) (hsotg->connected)
58e52ff6
JY		 1183int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg);
1184int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg);
117777b2 1185#else
1f91b4cc 1186static inline int dwc2_hsotg_remove(struct dwc2_hsotg *dwc2)
117777b2 1187{ return 0; }
1f91b4cc 1188static inline int dwc2_hsotg_suspend(struct dwc2_hsotg *dwc2)
117777b2 1189{ return 0; }
1f91b4cc 1190static inline int dwc2_hsotg_resume(struct dwc2_hsotg *dwc2)
117777b2
DN		 1191{ return 0; }
1192static inline int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq)
1193{ return 0; }
1f91b4cc 1194static inline void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2,
9da51974 1195 bool reset) {}
1f91b4cc
FB		 1196static inline void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg) {}
1197static inline void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2) {}
1198static inline int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg,
9da51974 1199 int testmode)
f91eea44 1200{ return 0; }
f81f46e1 1201#define dwc2_is_device_connected(hsotg) (0)
58e52ff6
JY		 1202static inline int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg)
1203{ return 0; }
1204static inline int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg)
1205{ return 0; }
117777b2
DN		 1206#endif
1207
1208#if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
9da51974
JY		 1209int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg);
1210int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg, int us);
1211void dwc2_hcd_connect(struct dwc2_hsotg *hsotg);
1212void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force);
1213void dwc2_hcd_start(struct dwc2_hsotg *hsotg);
58e52ff6
JY		 1214int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg);
1215int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg);
117777b2 1216#else
117777b2
DN		 1217static inline int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg)
1218{ return 0; }
fae4e826
DA		 1219static inline int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg,
1220 int us)
1221{ return 0; }
6a659531
DA		 1222static inline void dwc2_hcd_connect(struct dwc2_hsotg *hsotg) {}
1223static inline void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force) {}
117777b2
DN		 1224static inline void dwc2_hcd_start(struct dwc2_hsotg *hsotg) {}
1225static inline void dwc2_hcd_remove(struct dwc2_hsotg *hsotg) {}
ecb176c6 1226static inline int dwc2_hcd_init(struct dwc2_hsotg *hsotg, int irq)
117777b2 1227{ return 0; }
58e52ff6
JY		 1228static inline int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg)
1229{ return 0; }
1230static inline int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg)
1231{ return 0; }
1232
117777b2
DN		 1233#endif
1234
56f5b1cf 1235#endif /* __DWC2_CORE_H__ */
Linux 6.x block layer and io_uring tree(s)