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5fd54ace | 1 | // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) |
56f5b1cf PZ |
2 | /* |
3 | * core.h - DesignWare HS OTG Controller common declarations | |
4 | * | |
5 | * Copyright (C) 2004-2013 Synopsys, Inc. | |
6 | * | |
7 | * Redistribution and use in source and binary forms, with or without | |
8 | * modification, are permitted provided that the following conditions | |
9 | * are met: | |
10 | * 1. Redistributions of source code must retain the above copyright | |
11 | * notice, this list of conditions, and the following disclaimer, | |
12 | * without modification. | |
13 | * 2. Redistributions in binary form must reproduce the above copyright | |
14 | * notice, this list of conditions and the following disclaimer in the | |
15 | * documentation and/or other materials provided with the distribution. | |
16 | * 3. The names of the above-listed copyright holders may not be used | |
17 | * to endorse or promote products derived from this software without | |
18 | * specific prior written permission. | |
19 | * | |
20 | * ALTERNATIVELY, this software may be distributed under the terms of the | |
21 | * GNU General Public License ("GPL") as published by the Free Software | |
22 | * Foundation; either version 2 of the License, or (at your option) any | |
23 | * later version. | |
24 | * | |
25 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS | |
26 | * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, | |
27 | * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR | |
28 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR | |
29 | * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, | |
30 | * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, | |
31 | * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR | |
32 | * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF | |
33 | * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING | |
34 | * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS | |
35 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
36 | */ | |
37 | ||
38 | #ifndef __DWC2_CORE_H__ | |
39 | #define __DWC2_CORE_H__ | |
40 | ||
f7c0b143 DN |
41 | #include <linux/phy/phy.h> |
42 | #include <linux/regulator/consumer.h> | |
43 | #include <linux/usb/gadget.h> | |
44 | #include <linux/usb/otg.h> | |
56f5b1cf PZ |
45 | #include <linux/usb/phy.h> |
46 | #include "hw.h" | |
47 | ||
74fc4a75 DA |
48 | /* |
49 | * Suggested defines for tracers: | |
50 | * - no_printk: Disable tracing | |
51 | * - pr_info: Print this info to the console | |
52 | * - trace_printk: Print this info to trace buffer (good for verbose logging) | |
53 | */ | |
54 | ||
55 | #define DWC2_TRACE_SCHEDULER no_printk | |
56 | #define DWC2_TRACE_SCHEDULER_VB no_printk | |
57 | ||
58 | /* Detailed scheduler tracing, but won't overwhelm console */ | |
59 | #define dwc2_sch_dbg(hsotg, fmt, ...) \ | |
60 | DWC2_TRACE_SCHEDULER(pr_fmt("%s: SCH: " fmt), \ | |
61 | dev_name(hsotg->dev), ##__VA_ARGS__) | |
62 | ||
63 | /* Verbose scheduler tracing */ | |
64 | #define dwc2_sch_vdbg(hsotg, fmt, ...) \ | |
65 | DWC2_TRACE_SCHEDULER_VB(pr_fmt("%s: SCH: " fmt), \ | |
66 | dev_name(hsotg->dev), ##__VA_ARGS__) | |
67 | ||
23e34392 AB |
68 | #ifdef CONFIG_MIPS |
69 | /* | |
70 | * There are some MIPS machines that can run in either big-endian | |
71 | * or little-endian mode and that use the dwc2 register without | |
72 | * a byteswap in both ways. | |
73 | * Unlike other architectures, MIPS apparently does not require a | |
74 | * barrier before the __raw_writel() to synchronize with DMA but does | |
75 | * require the barrier after the __raw_writel() to serialize a set of | |
76 | * writes. This set of operations was added specifically for MIPS and | |
77 | * should only be used there. | |
78 | */ | |
95c8bc36 | 79 | static inline u32 dwc2_readl(const void __iomem *addr) |
56f5b1cf | 80 | { |
95c8bc36 AS |
81 | u32 value = __raw_readl(addr); |
82 | ||
83 | /* In order to preserve endianness __raw_* operation is used. Therefore | |
84 | * a barrier is needed to ensure IO access is not re-ordered across | |
85 | * reads or writes | |
86 | */ | |
87 | mb(); | |
88 | return value; | |
56f5b1cf PZ |
89 | } |
90 | ||
95c8bc36 AS |
91 | static inline void dwc2_writel(u32 value, void __iomem *addr) |
92 | { | |
93 | __raw_writel(value, addr); | |
94 | ||
95 | /* | |
96 | * In order to preserve endianness __raw_* operation is used. Therefore | |
97 | * a barrier is needed to ensure IO access is not re-ordered across | |
98 | * reads or writes | |
99 | */ | |
100 | mb(); | |
101 | #ifdef DWC2_LOG_WRITES | |
102 | pr_info("INFO:: wrote %08x to %p\n", value, addr); | |
56f5b1cf | 103 | #endif |
95c8bc36 | 104 | } |
23e34392 AB |
105 | #else |
106 | /* Normal architectures just use readl/write */ | |
107 | static inline u32 dwc2_readl(const void __iomem *addr) | |
108 | { | |
109 | return readl(addr); | |
110 | } | |
111 | ||
112 | static inline void dwc2_writel(u32 value, void __iomem *addr) | |
113 | { | |
114 | writel(value, addr); | |
115 | ||
116 | #ifdef DWC2_LOG_WRITES | |
117 | pr_info("info:: wrote %08x to %p\n", value, addr); | |
118 | #endif | |
119 | } | |
120 | #endif | |
56f5b1cf PZ |
121 | |
122 | /* Maximum number of Endpoints/HostChannels */ | |
123 | #define MAX_EPS_CHANNELS 16 | |
124 | ||
1f91b4cc FB |
125 | /* dwc2-hsotg declarations */ |
126 | static const char * const dwc2_hsotg_supply_names[] = { | |
f7c0b143 DN |
127 | "vusb_d", /* digital USB supply, 1.2V */ |
128 | "vusb_a", /* analog USB supply, 1.1V */ | |
129 | }; | |
130 | ||
b98866c2 JY |
131 | #define DWC2_NUM_SUPPLIES ARRAY_SIZE(dwc2_hsotg_supply_names) |
132 | ||
f7c0b143 DN |
133 | /* |
134 | * EP0_MPS_LIMIT | |
135 | * | |
136 | * Unfortunately there seems to be a limit of the amount of data that can | |
137 | * be transferred by IN transactions on EP0. This is either 127 bytes or 3 | |
138 | * packets (which practically means 1 packet and 63 bytes of data) when the | |
139 | * MPS is set to 64. | |
140 | * | |
141 | * This means if we are wanting to move >127 bytes of data, we need to | |
142 | * split the transactions up, but just doing one packet at a time does | |
143 | * not work (this may be an implicit DATA0 PID on first packet of the | |
144 | * transaction) and doing 2 packets is outside the controller's limits. | |
145 | * | |
146 | * If we try to lower the MPS size for EP0, then no transfers work properly | |
147 | * for EP0, and the system will fail basic enumeration. As no cause for this | |
148 | * has currently been found, we cannot support any large IN transfers for | |
149 | * EP0. | |
150 | */ | |
151 | #define EP0_MPS_LIMIT 64 | |
152 | ||
941fcce4 | 153 | struct dwc2_hsotg; |
1f91b4cc | 154 | struct dwc2_hsotg_req; |
f7c0b143 DN |
155 | |
156 | /** | |
1f91b4cc | 157 | * struct dwc2_hsotg_ep - driver endpoint definition. |
f7c0b143 DN |
158 | * @ep: The gadget layer representation of the endpoint. |
159 | * @name: The driver generated name for the endpoint. | |
160 | * @queue: Queue of requests for this endpoint. | |
161 | * @parent: Reference back to the parent device structure. | |
162 | * @req: The current request that the endpoint is processing. This is | |
163 | * used to indicate an request has been loaded onto the endpoint | |
164 | * and has yet to be completed (maybe due to data move, or simply | |
165 | * awaiting an ack from the core all the data has been completed). | |
166 | * @debugfs: File entry for debugfs file for this endpoint. | |
167 | * @lock: State lock to protect contents of endpoint. | |
168 | * @dir_in: Set to true if this endpoint is of the IN direction, which | |
169 | * means that it is sending data to the Host. | |
170 | * @index: The index for the endpoint registers. | |
171 | * @mc: Multi Count - number of transactions per microframe | |
142bd33f | 172 | * @interval - Interval for periodic endpoints, in frames or microframes. |
f7c0b143 DN |
173 | * @name: The name array passed to the USB core. |
174 | * @halted: Set if the endpoint has been halted. | |
175 | * @periodic: Set if this is a periodic ep, such as Interrupt | |
176 | * @isochronous: Set if this is a isochronous ep | |
8a20fa45 | 177 | * @send_zlp: Set if we need to send a zero-length packet. |
5f54c54b VA |
178 | * @desc_list_dma: The DMA address of descriptor chain currently in use. |
179 | * @desc_list: Pointer to descriptor DMA chain head currently in use. | |
180 | * @desc_count: Count of entries within the DMA descriptor chain of EP. | |
ab7d2192 VA |
181 | * @isoc_chain_num: Number of ISOC chain currently in use - either 0 or 1. |
182 | * @next_desc: index of next free descriptor in the ISOC chain under SW control. | |
f7c0b143 DN |
183 | * @total_data: The total number of data bytes done. |
184 | * @fifo_size: The size of the FIFO (for periodic IN endpoints) | |
185 | * @fifo_load: The amount of data loaded into the FIFO (periodic IN) | |
186 | * @last_load: The offset of data for the last start of request. | |
187 | * @size_loaded: The last loaded size for DxEPTSIZE for periodic IN | |
92d1635d VM |
188 | * @target_frame: Targeted frame num to setup next ISOC transfer |
189 | * @frame_overrun: Indicates SOF number overrun in DSTS | |
f7c0b143 DN |
190 | * |
191 | * This is the driver's state for each registered enpoint, allowing it | |
192 | * to keep track of transactions that need doing. Each endpoint has a | |
193 | * lock to protect the state, to try and avoid using an overall lock | |
194 | * for the host controller as much as possible. | |
195 | * | |
196 | * For periodic IN endpoints, we have fifo_size and fifo_load to try | |
197 | * and keep track of the amount of data in the periodic FIFO for each | |
198 | * of these as we don't have a status register that tells us how much | |
199 | * is in each of them. (note, this may actually be useless information | |
200 | * as in shared-fifo mode periodic in acts like a single-frame packet | |
201 | * buffer than a fifo) | |
202 | */ | |
1f91b4cc | 203 | struct dwc2_hsotg_ep { |
f7c0b143 DN |
204 | struct usb_ep ep; |
205 | struct list_head queue; | |
941fcce4 | 206 | struct dwc2_hsotg *parent; |
1f91b4cc | 207 | struct dwc2_hsotg_req *req; |
f7c0b143 DN |
208 | struct dentry *debugfs; |
209 | ||
210 | unsigned long total_data; | |
211 | unsigned int size_loaded; | |
212 | unsigned int last_load; | |
213 | unsigned int fifo_load; | |
214 | unsigned short fifo_size; | |
b203d0a2 | 215 | unsigned short fifo_index; |
f7c0b143 DN |
216 | |
217 | unsigned char dir_in; | |
218 | unsigned char index; | |
219 | unsigned char mc; | |
220 | unsigned char interval; | |
221 | ||
222 | unsigned int halted:1; | |
223 | unsigned int periodic:1; | |
224 | unsigned int isochronous:1; | |
8a20fa45 | 225 | unsigned int send_zlp:1; |
92d1635d VM |
226 | unsigned int target_frame; |
227 | #define TARGET_FRAME_INITIAL 0xFFFFFFFF | |
228 | bool frame_overrun; | |
f7c0b143 | 229 | |
5f54c54b VA |
230 | dma_addr_t desc_list_dma; |
231 | struct dwc2_dma_desc *desc_list; | |
232 | u8 desc_count; | |
233 | ||
ab7d2192 VA |
234 | unsigned char isoc_chain_num; |
235 | unsigned int next_desc; | |
236 | ||
f7c0b143 DN |
237 | char name[10]; |
238 | }; | |
239 | ||
f7c0b143 | 240 | /** |
1f91b4cc | 241 | * struct dwc2_hsotg_req - data transfer request |
f7c0b143 DN |
242 | * @req: The USB gadget request |
243 | * @queue: The list of requests for the endpoint this is queued for. | |
7d24c1b5 | 244 | * @saved_req_buf: variable to save req.buf when bounce buffers are used. |
f7c0b143 | 245 | */ |
1f91b4cc | 246 | struct dwc2_hsotg_req { |
f7c0b143 DN |
247 | struct usb_request req; |
248 | struct list_head queue; | |
7d24c1b5 | 249 | void *saved_req_buf; |
f7c0b143 DN |
250 | }; |
251 | ||
b98866c2 JY |
252 | #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \ |
253 | IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) | |
f7c0b143 DN |
254 | #define call_gadget(_hs, _entry) \ |
255 | do { \ | |
256 | if ((_hs)->gadget.speed != USB_SPEED_UNKNOWN && \ | |
257 | (_hs)->driver && (_hs)->driver->_entry) { \ | |
258 | spin_unlock(&_hs->lock); \ | |
259 | (_hs)->driver->_entry(&(_hs)->gadget); \ | |
260 | spin_lock(&_hs->lock); \ | |
261 | } \ | |
262 | } while (0) | |
941fcce4 DN |
263 | #else |
264 | #define call_gadget(_hs, _entry) do {} while (0) | |
265 | #endif | |
f7c0b143 | 266 | |
56f5b1cf PZ |
267 | struct dwc2_hsotg; |
268 | struct dwc2_host_chan; | |
269 | ||
270 | /* Device States */ | |
271 | enum dwc2_lx_state { | |
272 | DWC2_L0, /* On state */ | |
273 | DWC2_L1, /* LPM sleep state */ | |
274 | DWC2_L2, /* USB suspend state */ | |
275 | DWC2_L3, /* Off state */ | |
276 | }; | |
277 | ||
fe0b94ab MYK |
278 | /* Gadget ep0 states */ |
279 | enum dwc2_ep0_state { | |
280 | DWC2_EP0_SETUP, | |
281 | DWC2_EP0_DATA_IN, | |
282 | DWC2_EP0_DATA_OUT, | |
283 | DWC2_EP0_STATUS_IN, | |
284 | DWC2_EP0_STATUS_OUT, | |
285 | }; | |
286 | ||
56f5b1cf PZ |
287 | /** |
288 | * struct dwc2_core_params - Parameters for configuring the core | |
289 | * | |
91121c10 MK |
290 | * @otg_cap: Specifies the OTG capabilities. |
291 | * 0 - HNP and SRP capable | |
56f5b1cf | 292 | * 1 - SRP Only capable |
91121c10 MK |
293 | * 2 - No HNP/SRP capable (always available) |
294 | * Defaults to best available option (0, 1, then 2) | |
e7839f99 | 295 | * @host_dma: Specifies whether to use slave or DMA mode for accessing |
56f5b1cf PZ |
296 | * the data FIFOs. The driver will automatically detect the |
297 | * value for this parameter if none is specified. | |
91121c10 | 298 | * 0 - Slave (always available) |
56f5b1cf PZ |
299 | * 1 - DMA (default, if available) |
300 | * @dma_desc_enable: When DMA mode is enabled, specifies whether to use | |
301 | * address DMA mode or descriptor DMA mode for accessing | |
302 | * the data FIFOs. The driver will automatically detect the | |
303 | * value for this if none is specified. | |
304 | * 0 - Address DMA | |
305 | * 1 - Descriptor DMA (default, if available) | |
fbb9e22b MYK |
306 | * @dma_desc_fs_enable: When DMA mode is enabled, specifies whether to use |
307 | * address DMA mode or descriptor DMA mode for accessing | |
308 | * the data FIFOs in Full Speed mode only. The driver | |
309 | * will automatically detect the value for this if none is | |
310 | * specified. | |
311 | * 0 - Address DMA | |
312 | * 1 - Descriptor DMA in FS (default, if available) | |
56f5b1cf PZ |
313 | * @speed: Specifies the maximum speed of operation in host and |
314 | * device mode. The actual speed depends on the speed of | |
315 | * the attached device and the value of phy_type. | |
91121c10 MK |
316 | * 0 - High Speed |
317 | * (default when phy_type is UTMI+ or ULPI) | |
56f5b1cf | 318 | * 1 - Full Speed |
91121c10 | 319 | * (default when phy_type is Full Speed) |
56f5b1cf | 320 | * @enable_dynamic_fifo: 0 - Use coreConsultant-specified FIFO size parameters |
91121c10 | 321 | * 1 - Allow dynamic FIFO sizing (default, if available) |
725acc86 | 322 | * @en_multiple_tx_fifo: Specifies whether dedicated per-endpoint transmit FIFOs |
c1d286cf JY |
323 | * are enabled for non-periodic IN endpoints in device |
324 | * mode. | |
56f5b1cf PZ |
325 | * @host_rx_fifo_size: Number of 4-byte words in the Rx FIFO in host mode when |
326 | * dynamic FIFO sizing is enabled | |
91121c10 MK |
327 | * 16 to 32768 |
328 | * Actual maximum value is autodetected and also | |
329 | * the default. | |
56f5b1cf PZ |
330 | * @host_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO |
331 | * in host mode when dynamic FIFO sizing is enabled | |
91121c10 MK |
332 | * 16 to 32768 |
333 | * Actual maximum value is autodetected and also | |
334 | * the default. | |
56f5b1cf PZ |
335 | * @host_perio_tx_fifo_size: Number of 4-byte words in the periodic Tx FIFO in |
336 | * host mode when dynamic FIFO sizing is enabled | |
91121c10 MK |
337 | * 16 to 32768 |
338 | * Actual maximum value is autodetected and also | |
339 | * the default. | |
56f5b1cf | 340 | * @max_transfer_size: The maximum transfer size supported, in bytes |
91121c10 MK |
341 | * 2047 to 65,535 |
342 | * Actual maximum value is autodetected and also | |
343 | * the default. | |
56f5b1cf | 344 | * @max_packet_count: The maximum number of packets in a transfer |
91121c10 MK |
345 | * 15 to 511 |
346 | * Actual maximum value is autodetected and also | |
347 | * the default. | |
56f5b1cf | 348 | * @host_channels: The number of host channel registers to use |
91121c10 MK |
349 | * 1 to 16 |
350 | * Actual maximum value is autodetected and also | |
351 | * the default. | |
56f5b1cf PZ |
352 | * @phy_type: Specifies the type of PHY interface to use. By default, |
353 | * the driver will automatically detect the phy_type. | |
91121c10 MK |
354 | * 0 - Full Speed Phy |
355 | * 1 - UTMI+ Phy | |
356 | * 2 - ULPI Phy | |
357 | * Defaults to best available option (2, 1, then 0) | |
56f5b1cf PZ |
358 | * @phy_utmi_width: Specifies the UTMI+ Data Width (in bits). This parameter |
359 | * is applicable for a phy_type of UTMI+ or ULPI. (For a | |
360 | * ULPI phy_type, this parameter indicates the data width | |
361 | * between the MAC and the ULPI Wrapper.) Also, this | |
362 | * parameter is applicable only if the OTG_HSPHY_WIDTH cC | |
363 | * parameter was set to "8 and 16 bits", meaning that the | |
364 | * core has been configured to work at either data path | |
365 | * width. | |
91121c10 | 366 | * 8 or 16 (default 16 if available) |
56f5b1cf PZ |
367 | * @phy_ulpi_ddr: Specifies whether the ULPI operates at double or single |
368 | * data rate. This parameter is only applicable if phy_type | |
369 | * is ULPI. | |
370 | * 0 - single data rate ULPI interface with 8 bit wide | |
371 | * data bus (default) | |
372 | * 1 - double data rate ULPI interface with 4 bit wide | |
373 | * data bus | |
374 | * @phy_ulpi_ext_vbus: For a ULPI phy, specifies whether to use the internal or | |
375 | * external supply to drive the VBus | |
91121c10 MK |
376 | * 0 - Internal supply (default) |
377 | * 1 - External supply | |
56f5b1cf PZ |
378 | * @i2c_enable: Specifies whether to use the I2Cinterface for a full |
379 | * speed PHY. This parameter is only applicable if phy_type | |
380 | * is FS. | |
381 | * 0 - No (default) | |
382 | * 1 - Yes | |
91121c10 MK |
383 | * @ulpi_fs_ls: Make ULPI phy operate in FS/LS mode only |
384 | * 0 - No (default) | |
385 | * 1 - Yes | |
725acc86 PZ |
386 | * @host_support_fs_ls_low_power: Specifies whether low power mode is supported |
387 | * when attached to a Full Speed or Low Speed device in | |
388 | * host mode. | |
389 | * 0 - Don't support low power mode (default) | |
390 | * 1 - Support low power mode | |
391 | * @host_ls_low_power_phy_clk: Specifies the PHY clock rate in low power mode | |
91121c10 MK |
392 | * when connected to a Low Speed device in host |
393 | * mode. This parameter is applicable only if | |
394 | * host_support_fs_ls_low_power is enabled. | |
725acc86 | 395 | * 0 - 48 MHz |
91121c10 | 396 | * (default when phy_type is UTMI+ or ULPI) |
725acc86 | 397 | * 1 - 6 MHz |
91121c10 | 398 | * (default when phy_type is Full Speed) |
b11633c4 DN |
399 | * @oc_disable: Flag to disable overcurrent condition. |
400 | * 0 - Allow overcurrent condition to get detected | |
401 | * 1 - Disable overcurrent condtion to get detected | |
91121c10 MK |
402 | * @ts_dline: Enable Term Select Dline pulsing |
403 | * 0 - No (default) | |
404 | * 1 - Yes | |
405 | * @reload_ctl: Allow dynamic reloading of HFIR register during runtime | |
406 | * 0 - No (default for core < 2.92a) | |
407 | * 1 - Yes (default for core >= 2.92a) | |
4d3190e1 PZ |
408 | * @ahbcfg: This field allows the default value of the GAHBCFG |
409 | * register to be overridden | |
91121c10 MK |
410 | * -1 - GAHBCFG value will be set to 0x06 |
411 | * (INCR4, default) | |
4d3190e1 PZ |
412 | * all others - GAHBCFG value will be overridden with |
413 | * this value | |
91121c10 MK |
414 | * Not all bits can be controlled like this, the |
415 | * bits defined by GAHBCFG_CTRL_MASK are controlled | |
416 | * by the driver and are ignored in this | |
417 | * configuration value. | |
20f2eb9c | 418 | * @uframe_sched: True to enable the microframe scheduler |
a6d249d8 GH |
419 | * @external_id_pin_ctl: Specifies whether ID pin is handled externally. |
420 | * Disable CONIDSTSCHNG controller interrupt in such | |
421 | * case. | |
422 | * 0 - No (default) | |
423 | * 1 - Yes | |
285046aa GH |
424 | * @hibernation: Specifies whether the controller support hibernation. |
425 | * If hibernation is enabled, the controller will enter | |
426 | * hibernation in both peripheral and host mode when | |
427 | * needed. | |
428 | * 0 - No (default) | |
429 | * 1 - Yes | |
e35b1350 BH |
430 | * @activate_stm_fs_transceiver: Activate internal transceiver using GGPIO |
431 | * register. | |
432 | * 0 - Deactivate the transceiver (default) | |
433 | * 1 - Activate the transceiver | |
9962b62f | 434 | * @g_dma: Enables gadget dma usage (default: autodetect). |
dec4b556 | 435 | * @g_dma_desc: Enables gadget descriptor DMA (default: autodetect). |
05ee799f JY |
436 | * @g_rx_fifo_size: The periodic rx fifo size for the device, in |
437 | * DWORDS from 16-32768 (default: 2048 if | |
438 | * possible, otherwise autodetect). | |
439 | * @g_np_tx_fifo_size: The non-periodic tx fifo size for the device in | |
440 | * DWORDS from 16-32768 (default: 1024 if | |
441 | * possible, otherwise autodetect). | |
442 | * @g_tx_fifo_size: An array of TX fifo sizes in dedicated fifo | |
443 | * mode. Each value corresponds to one EP | |
444 | * starting from EP1 (max 15 values). Sizes are | |
445 | * in DWORDS with possible values from from | |
446 | * 16-32768 (default: 256, 256, 256, 256, 768, | |
447 | * 768, 768, 768, 0, 0, 0, 0, 0, 0, 0). | |
ca8b0332 CY |
448 | * @change_speed_quirk: Change speed configuration to DWC2_SPEED_PARAM_FULL |
449 | * while full&low speed device connect. And change speed | |
450 | * back to DWC2_SPEED_PARAM_HIGH while device is gone. | |
451 | * 0 - No (default) | |
452 | * 1 - Yes | |
56f5b1cf PZ |
453 | * |
454 | * The following parameters may be specified when starting the module. These | |
91121c10 MK |
455 | * parameters define how the DWC_otg controller should be configured. A |
456 | * value of -1 (or any other out of range value) for any parameter means | |
457 | * to read the value from hardware (if possible) or use the builtin | |
458 | * default described above. | |
56f5b1cf PZ |
459 | */ |
460 | struct dwc2_core_params { | |
d21bcc3f | 461 | u8 otg_cap; |
c1d286cf JY |
462 | #define DWC2_CAP_PARAM_HNP_SRP_CAPABLE 0 |
463 | #define DWC2_CAP_PARAM_SRP_ONLY_CAPABLE 1 | |
464 | #define DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE 2 | |
465 | ||
d21bcc3f | 466 | u8 phy_type; |
c1d286cf JY |
467 | #define DWC2_PHY_TYPE_PARAM_FS 0 |
468 | #define DWC2_PHY_TYPE_PARAM_UTMI 1 | |
469 | #define DWC2_PHY_TYPE_PARAM_ULPI 2 | |
470 | ||
57b8e235 JY |
471 | u8 speed; |
472 | #define DWC2_SPEED_PARAM_HIGH 0 | |
473 | #define DWC2_SPEED_PARAM_FULL 1 | |
474 | #define DWC2_SPEED_PARAM_LOW 2 | |
475 | ||
d21bcc3f JY |
476 | u8 phy_utmi_width; |
477 | bool phy_ulpi_ddr; | |
478 | bool phy_ulpi_ext_vbus; | |
57b8e235 JY |
479 | bool enable_dynamic_fifo; |
480 | bool en_multiple_tx_fifo; | |
d21bcc3f JY |
481 | bool i2c_enable; |
482 | bool ulpi_fs_ls; | |
d21bcc3f JY |
483 | bool ts_dline; |
484 | bool reload_ctl; | |
d21bcc3f JY |
485 | bool uframe_sched; |
486 | bool external_id_pin_ctl; | |
487 | bool hibernation; | |
e35b1350 | 488 | bool activate_stm_fs_transceiver; |
57b8e235 JY |
489 | u16 max_packet_count; |
490 | u32 max_transfer_size; | |
491 | u32 ahbcfg; | |
6b66ce51 JY |
492 | |
493 | /* Host parameters */ | |
494 | bool host_dma; | |
57b8e235 JY |
495 | bool dma_desc_enable; |
496 | bool dma_desc_fs_enable; | |
497 | bool host_support_fs_ls_low_power; | |
498 | bool host_ls_low_power_phy_clk; | |
b11633c4 | 499 | bool oc_disable; |
57b8e235 JY |
500 | |
501 | u8 host_channels; | |
502 | u16 host_rx_fifo_size; | |
503 | u16 host_nperio_tx_fifo_size; | |
504 | u16 host_perio_tx_fifo_size; | |
6b66ce51 JY |
505 | |
506 | /* Gadget parameters */ | |
05ee799f | 507 | bool g_dma; |
dec4b556 | 508 | bool g_dma_desc; |
00c704cc LY |
509 | u32 g_rx_fifo_size; |
510 | u32 g_np_tx_fifo_size; | |
05ee799f | 511 | u32 g_tx_fifo_size[MAX_EPS_CHANNELS]; |
ca8b0332 CY |
512 | |
513 | bool change_speed_quirk; | |
56f5b1cf PZ |
514 | }; |
515 | ||
9badec2f MK |
516 | /** |
517 | * struct dwc2_hw_params - Autodetected parameters. | |
518 | * | |
519 | * These parameters are the various parameters read from hardware | |
520 | * registers during initialization. They typically contain the best | |
521 | * supported or maximum value that can be configured in the | |
522 | * corresponding dwc2_core_params value. | |
523 | * | |
524 | * The values that are not in dwc2_core_params are documented below. | |
525 | * | |
526 | * @op_mode Mode of Operation | |
527 | * 0 - HNP- and SRP-Capable OTG (Host & Device) | |
528 | * 1 - SRP-Capable OTG (Host & Device) | |
529 | * 2 - Non-HNP and Non-SRP Capable OTG (Host & Device) | |
530 | * 3 - SRP-Capable Device | |
531 | * 4 - Non-OTG Device | |
532 | * 5 - SRP-Capable Host | |
533 | * 6 - Non-OTG Host | |
534 | * @arch Architecture | |
535 | * 0 - Slave only | |
536 | * 1 - External DMA | |
537 | * 2 - Internal DMA | |
538 | * @power_optimized Are power optimizations enabled? | |
539 | * @num_dev_ep Number of device endpoints available | |
9273083a | 540 | * @num_dev_in_eps Number of device IN endpoints available |
9badec2f | 541 | * @num_dev_perio_in_ep Number of device periodic IN endpoints |
997f4f81 | 542 | * available |
9badec2f MK |
543 | * @dev_token_q_depth Device Mode IN Token Sequence Learning Queue |
544 | * Depth | |
545 | * 0 to 30 | |
546 | * @host_perio_tx_q_depth | |
547 | * Host Mode Periodic Request Queue Depth | |
548 | * 2, 4 or 8 | |
549 | * @nperio_tx_q_depth | |
550 | * Non-Periodic Request Queue Depth | |
551 | * 2, 4 or 8 | |
552 | * @hs_phy_type High-speed PHY interface type | |
553 | * 0 - High-speed interface not supported | |
554 | * 1 - UTMI+ | |
555 | * 2 - ULPI | |
556 | * 3 - UTMI+ and ULPI | |
557 | * @fs_phy_type Full-speed PHY interface type | |
558 | * 0 - Full speed interface not supported | |
559 | * 1 - Dedicated full speed interface | |
560 | * 2 - FS pins shared with UTMI+ pins | |
561 | * 3 - FS pins shared with ULPI pins | |
562 | * @total_fifo_size: Total internal RAM for FIFOs (bytes) | |
de4a1931 MK |
563 | * @utmi_phy_data_width UTMI+ PHY data width |
564 | * 0 - 8 bits | |
565 | * 1 - 16 bits | |
566 | * 2 - 8 or 16 bits | |
9badec2f | 567 | * @snpsid: Value from SNPSID register |
55e1040e | 568 | * @dev_ep_dirs: Direction of device endpoints (GHWCFG1) |
9273083a | 569 | * @g_tx_fifo_size[] Power-on values of TxFIFO sizes |
9badec2f MK |
570 | */ |
571 | struct dwc2_hw_params { | |
572 | unsigned op_mode:3; | |
573 | unsigned arch:2; | |
574 | unsigned dma_desc_enable:1; | |
575 | unsigned enable_dynamic_fifo:1; | |
576 | unsigned en_multiple_tx_fifo:1; | |
d1531319 | 577 | unsigned rx_fifo_size:16; |
9badec2f | 578 | unsigned host_nperio_tx_fifo_size:16; |
55e1040e | 579 | unsigned dev_nperio_tx_fifo_size:16; |
9badec2f MK |
580 | unsigned host_perio_tx_fifo_size:16; |
581 | unsigned nperio_tx_q_depth:3; | |
582 | unsigned host_perio_tx_q_depth:3; | |
583 | unsigned dev_token_q_depth:5; | |
584 | unsigned max_transfer_size:26; | |
585 | unsigned max_packet_count:11; | |
2d115547 | 586 | unsigned host_channels:5; |
9badec2f MK |
587 | unsigned hs_phy_type:2; |
588 | unsigned fs_phy_type:2; | |
589 | unsigned i2c_enable:1; | |
590 | unsigned num_dev_ep:4; | |
9273083a | 591 | unsigned num_dev_in_eps : 4; |
9badec2f MK |
592 | unsigned num_dev_perio_in_ep:4; |
593 | unsigned total_fifo_size:16; | |
594 | unsigned power_optimized:1; | |
de4a1931 | 595 | unsigned utmi_phy_data_width:2; |
9badec2f | 596 | u32 snpsid; |
55e1040e | 597 | u32 dev_ep_dirs; |
9273083a | 598 | u32 g_tx_fifo_size[MAX_EPS_CHANNELS]; |
9badec2f MK |
599 | }; |
600 | ||
3f95001d MYK |
601 | /* Size of control and EP0 buffers */ |
602 | #define DWC2_CTRL_BUFF_SIZE 8 | |
603 | ||
d17ee77b | 604 | /** |
38beaec6 JY |
605 | * struct dwc2_gregs_backup - Holds global registers state before |
606 | * entering partial power down | |
d17ee77b GH |
607 | * @gotgctl: Backup of GOTGCTL register |
608 | * @gintmsk: Backup of GINTMSK register | |
609 | * @gahbcfg: Backup of GAHBCFG register | |
610 | * @gusbcfg: Backup of GUSBCFG register | |
611 | * @grxfsiz: Backup of GRXFSIZ register | |
612 | * @gnptxfsiz: Backup of GNPTXFSIZ register | |
613 | * @gi2cctl: Backup of GI2CCTL register | |
614 | * @hptxfsiz: Backup of HPTXFSIZ register | |
615 | * @gdfifocfg: Backup of GDFIFOCFG register | |
616 | * @dtxfsiz: Backup of DTXFSIZ registers for each endpoint | |
617 | * @gpwrdn: Backup of GPWRDN register | |
618 | */ | |
619 | struct dwc2_gregs_backup { | |
620 | u32 gotgctl; | |
621 | u32 gintmsk; | |
622 | u32 gahbcfg; | |
623 | u32 gusbcfg; | |
624 | u32 grxfsiz; | |
625 | u32 gnptxfsiz; | |
626 | u32 gi2cctl; | |
627 | u32 hptxfsiz; | |
628 | u32 pcgcctl; | |
629 | u32 gdfifocfg; | |
630 | u32 dtxfsiz[MAX_EPS_CHANNELS]; | |
631 | u32 gpwrdn; | |
cc1e204c | 632 | bool valid; |
d17ee77b GH |
633 | }; |
634 | ||
635 | /** | |
38beaec6 JY |
636 | * struct dwc2_dregs_backup - Holds device registers state before |
637 | * entering partial power down | |
d17ee77b GH |
638 | * @dcfg: Backup of DCFG register |
639 | * @dctl: Backup of DCTL register | |
640 | * @daintmsk: Backup of DAINTMSK register | |
641 | * @diepmsk: Backup of DIEPMSK register | |
642 | * @doepmsk: Backup of DOEPMSK register | |
643 | * @diepctl: Backup of DIEPCTL register | |
644 | * @dieptsiz: Backup of DIEPTSIZ register | |
645 | * @diepdma: Backup of DIEPDMA register | |
646 | * @doepctl: Backup of DOEPCTL register | |
647 | * @doeptsiz: Backup of DOEPTSIZ register | |
648 | * @doepdma: Backup of DOEPDMA register | |
649 | */ | |
650 | struct dwc2_dregs_backup { | |
651 | u32 dcfg; | |
652 | u32 dctl; | |
653 | u32 daintmsk; | |
654 | u32 diepmsk; | |
655 | u32 doepmsk; | |
656 | u32 diepctl[MAX_EPS_CHANNELS]; | |
657 | u32 dieptsiz[MAX_EPS_CHANNELS]; | |
658 | u32 diepdma[MAX_EPS_CHANNELS]; | |
659 | u32 doepctl[MAX_EPS_CHANNELS]; | |
660 | u32 doeptsiz[MAX_EPS_CHANNELS]; | |
661 | u32 doepdma[MAX_EPS_CHANNELS]; | |
cc1e204c | 662 | bool valid; |
d17ee77b GH |
663 | }; |
664 | ||
665 | /** | |
38beaec6 JY |
666 | * struct dwc2_hregs_backup - Holds host registers state before |
667 | * entering partial power down | |
d17ee77b GH |
668 | * @hcfg: Backup of HCFG register |
669 | * @haintmsk: Backup of HAINTMSK register | |
670 | * @hcintmsk: Backup of HCINTMSK register | |
671 | * @hptr0: Backup of HPTR0 register | |
672 | * @hfir: Backup of HFIR register | |
673 | */ | |
674 | struct dwc2_hregs_backup { | |
675 | u32 hcfg; | |
676 | u32 haintmsk; | |
677 | u32 hcintmsk[MAX_EPS_CHANNELS]; | |
678 | u32 hprt0; | |
679 | u32 hfir; | |
cc1e204c | 680 | bool valid; |
d17ee77b GH |
681 | }; |
682 | ||
9f9f09b0 DA |
683 | /* |
684 | * Constants related to high speed periodic scheduling | |
685 | * | |
686 | * We have a periodic schedule that is DWC2_HS_SCHEDULE_UFRAMES long. From a | |
687 | * reservation point of view it's assumed that the schedule goes right back to | |
688 | * the beginning after the end of the schedule. | |
689 | * | |
690 | * What does that mean for scheduling things with a long interval? It means | |
691 | * we'll reserve time for them in every possible microframe that they could | |
692 | * ever be scheduled in. ...but we'll still only actually schedule them as | |
693 | * often as they were requested. | |
694 | * | |
695 | * We keep our schedule in a "bitmap" structure. This simplifies having | |
696 | * to keep track of and merge intervals: we just let the bitmap code do most | |
697 | * of the heavy lifting. In a way scheduling is much like memory allocation. | |
698 | * | |
699 | * We schedule 100us per uframe or 80% of 125us (the maximum amount you're | |
700 | * supposed to schedule for periodic transfers). That's according to spec. | |
701 | * | |
702 | * Note that though we only schedule 80% of each microframe, the bitmap that we | |
703 | * keep the schedule in is tightly packed (AKA it doesn't have 100us worth of | |
704 | * space for each uFrame). | |
705 | * | |
706 | * Requirements: | |
707 | * - DWC2_HS_SCHEDULE_UFRAMES must even divide 0x4000 (HFNUM_MAX_FRNUM + 1) | |
708 | * - DWC2_HS_SCHEDULE_UFRAMES must be 8 times DWC2_LS_SCHEDULE_FRAMES (probably | |
709 | * could be any multiple of 8 times DWC2_LS_SCHEDULE_FRAMES, but there might | |
710 | * be bugs). The 8 comes from the USB spec: number of microframes per frame. | |
711 | */ | |
712 | #define DWC2_US_PER_UFRAME 125 | |
713 | #define DWC2_HS_PERIODIC_US_PER_UFRAME 100 | |
714 | ||
715 | #define DWC2_HS_SCHEDULE_UFRAMES 8 | |
716 | #define DWC2_HS_SCHEDULE_US (DWC2_HS_SCHEDULE_UFRAMES * \ | |
717 | DWC2_HS_PERIODIC_US_PER_UFRAME) | |
718 | ||
719 | /* | |
720 | * Constants related to low speed scheduling | |
721 | * | |
722 | * For high speed we schedule every 1us. For low speed that's a bit overkill, | |
723 | * so we make up a unit called a "slice" that's worth 25us. There are 40 | |
724 | * slices in a full frame and we can schedule 36 of those (90%) for periodic | |
725 | * transfers. | |
726 | * | |
727 | * Our low speed schedule can be as short as 1 frame or could be longer. When | |
728 | * we only schedule 1 frame it means that we'll need to reserve a time every | |
729 | * frame even for things that only transfer very rarely, so something that runs | |
730 | * every 2048 frames will get time reserved in every frame. Our low speed | |
731 | * schedule can be longer and we'll be able to handle more overlap, but that | |
732 | * will come at increased memory cost and increased time to schedule. | |
733 | * | |
734 | * Note: one other advantage of a short low speed schedule is that if we mess | |
735 | * up and miss scheduling we can jump in and use any of the slots that we | |
736 | * happened to reserve. | |
737 | * | |
738 | * With 25 us per slice and 1 frame in the schedule, we only need 4 bytes for | |
739 | * the schedule. There will be one schedule per TT. | |
740 | * | |
741 | * Requirements: | |
742 | * - DWC2_US_PER_SLICE must evenly divide DWC2_LS_PERIODIC_US_PER_FRAME. | |
743 | */ | |
744 | #define DWC2_US_PER_SLICE 25 | |
745 | #define DWC2_SLICES_PER_UFRAME (DWC2_US_PER_UFRAME / DWC2_US_PER_SLICE) | |
746 | ||
747 | #define DWC2_ROUND_US_TO_SLICE(us) \ | |
748 | (DIV_ROUND_UP((us), DWC2_US_PER_SLICE) * \ | |
749 | DWC2_US_PER_SLICE) | |
750 | ||
751 | #define DWC2_LS_PERIODIC_US_PER_FRAME \ | |
752 | 900 | |
753 | #define DWC2_LS_PERIODIC_SLICES_PER_FRAME \ | |
754 | (DWC2_LS_PERIODIC_US_PER_FRAME / \ | |
755 | DWC2_US_PER_SLICE) | |
756 | ||
757 | #define DWC2_LS_SCHEDULE_FRAMES 1 | |
758 | #define DWC2_LS_SCHEDULE_SLICES (DWC2_LS_SCHEDULE_FRAMES * \ | |
759 | DWC2_LS_PERIODIC_SLICES_PER_FRAME) | |
760 | ||
56f5b1cf PZ |
761 | /** |
762 | * struct dwc2_hsotg - Holds the state of the driver, including the non-periodic | |
763 | * and periodic schedules | |
764 | * | |
941fcce4 DN |
765 | * These are common for both host and peripheral modes: |
766 | * | |
56f5b1cf PZ |
767 | * @dev: The struct device pointer |
768 | * @regs: Pointer to controller regs | |
9badec2f MK |
769 | * @hw_params: Parameters that were autodetected from the |
770 | * hardware registers | |
941fcce4 | 771 | * @core_params: Parameters that define how the core should be configured |
56f5b1cf PZ |
772 | * @op_state: The operational State, during transitions (a_host=> |
773 | * a_peripheral and b_device=>b_host) this may not match | |
774 | * the core, but allows the software to determine | |
775 | * transitions | |
c0155b9d KY |
776 | * @dr_mode: Requested mode of operation, one of following: |
777 | * - USB_DR_MODE_PERIPHERAL | |
778 | * - USB_DR_MODE_HOST | |
779 | * - USB_DR_MODE_OTG | |
09a75e85 MS |
780 | * @hcd_enabled Host mode sub-driver initialization indicator. |
781 | * @gadget_enabled Peripheral mode sub-driver initialization indicator. | |
782 | * @ll_hw_enabled Status of low-level hardware resources. | |
783 | * @phy: The otg phy transceiver structure for phy control. | |
38beaec6 JY |
784 | * @uphy: The otg phy transceiver structure for old USB phy |
785 | * control. | |
786 | * @plat: The platform specific configuration data. This can be | |
787 | * removed once all SoCs support usb transceiver. | |
09a75e85 MS |
788 | * @supplies: Definition of USB power supplies |
789 | * @phyif: PHY interface width | |
941fcce4 DN |
790 | * @lock: Spinlock that protects all the driver data structures |
791 | * @priv: Stores a pointer to the struct usb_hcd | |
56f5b1cf PZ |
792 | * @queuing_high_bandwidth: True if multiple packets of a high-bandwidth |
793 | * transfer are in process of being queued | |
794 | * @srp_success: Stores status of SRP request in the case of a FS PHY | |
795 | * with an I2C interface | |
796 | * @wq_otg: Workqueue object used for handling of some interrupts | |
797 | * @wf_otg: Work object for handling Connector ID Status Change | |
798 | * interrupt | |
799 | * @wkp_timer: Timer object for handling Wakeup Detected interrupt | |
800 | * @lx_state: Lx state of connected device | |
d17ee77b GH |
801 | * @gregs_backup: Backup of global registers during suspend |
802 | * @dregs_backup: Backup of device registers during suspend | |
803 | * @hregs_backup: Backup of host registers during suspend | |
941fcce4 DN |
804 | * |
805 | * These are for host mode: | |
806 | * | |
56f5b1cf PZ |
807 | * @flags: Flags for handling root port state changes |
808 | * @non_periodic_sched_inactive: Inactive QHs in the non-periodic schedule. | |
809 | * Transfers associated with these QHs are not currently | |
810 | * assigned to a host channel. | |
811 | * @non_periodic_sched_active: Active QHs in the non-periodic schedule. | |
812 | * Transfers associated with these QHs are currently | |
813 | * assigned to a host channel. | |
814 | * @non_periodic_qh_ptr: Pointer to next QH to process in the active | |
815 | * non-periodic schedule | |
816 | * @periodic_sched_inactive: Inactive QHs in the periodic schedule. This is a | |
817 | * list of QHs for periodic transfers that are _not_ | |
818 | * scheduled for the next frame. Each QH in the list has an | |
819 | * interval counter that determines when it needs to be | |
820 | * scheduled for execution. This scheduling mechanism | |
821 | * allows only a simple calculation for periodic bandwidth | |
822 | * used (i.e. must assume that all periodic transfers may | |
823 | * need to execute in the same frame). However, it greatly | |
824 | * simplifies scheduling and should be sufficient for the | |
825 | * vast majority of OTG hosts, which need to connect to a | |
826 | * small number of peripherals at one time. Items move from | |
827 | * this list to periodic_sched_ready when the QH interval | |
828 | * counter is 0 at SOF. | |
829 | * @periodic_sched_ready: List of periodic QHs that are ready for execution in | |
830 | * the next frame, but have not yet been assigned to host | |
831 | * channels. Items move from this list to | |
832 | * periodic_sched_assigned as host channels become | |
833 | * available during the current frame. | |
834 | * @periodic_sched_assigned: List of periodic QHs to be executed in the next | |
835 | * frame that are assigned to host channels. Items move | |
836 | * from this list to periodic_sched_queued as the | |
837 | * transactions for the QH are queued to the DWC_otg | |
838 | * controller. | |
839 | * @periodic_sched_queued: List of periodic QHs that have been queued for | |
840 | * execution. Items move from this list to either | |
841 | * periodic_sched_inactive or periodic_sched_ready when the | |
842 | * channel associated with the transfer is released. If the | |
843 | * interval for the QH is 1, the item moves to | |
844 | * periodic_sched_ready because it must be rescheduled for | |
845 | * the next frame. Otherwise, the item moves to | |
846 | * periodic_sched_inactive. | |
c9c8ac01 | 847 | * @split_order: List keeping track of channels doing splits, in order. |
56f5b1cf PZ |
848 | * @periodic_usecs: Total bandwidth claimed so far for periodic transfers. |
849 | * This value is in microseconds per (micro)frame. The | |
850 | * assumption is that all periodic transfers may occur in | |
851 | * the same (micro)frame. | |
9f9f09b0 DA |
852 | * @hs_periodic_bitmap: Bitmap used by the microframe scheduler any time the |
853 | * host is in high speed mode; low speed schedules are | |
854 | * stored elsewhere since we need one per TT. | |
56f5b1cf PZ |
855 | * @frame_number: Frame number read from the core at SOF. The value ranges |
856 | * from 0 to HFNUM_MAX_FRNUM. | |
857 | * @periodic_qh_count: Count of periodic QHs, if using several eps. Used for | |
858 | * SOF enable/disable. | |
859 | * @free_hc_list: Free host channels in the controller. This is a list of | |
860 | * struct dwc2_host_chan items. | |
861 | * @periodic_channels: Number of host channels assigned to periodic transfers. | |
862 | * Currently assuming that there is a dedicated host | |
863 | * channel for each periodic transaction and at least one | |
864 | * host channel is available for non-periodic transactions. | |
865 | * @non_periodic_channels: Number of host channels assigned to non-periodic | |
866 | * transfers | |
20f2eb9c DC |
867 | * @available_host_channels Number of host channels available for the microframe |
868 | * scheduler to use | |
56f5b1cf PZ |
869 | * @hc_ptr_array: Array of pointers to the host channel descriptors. |
870 | * Allows accessing a host channel descriptor given the | |
871 | * host channel number. This is useful in interrupt | |
872 | * handlers. | |
873 | * @status_buf: Buffer used for data received during the status phase of | |
874 | * a control transfer. | |
875 | * @status_buf_dma: DMA address for status_buf | |
876 | * @start_work: Delayed work for handling host A-cable connection | |
877 | * @reset_work: Delayed work for handling a port reset | |
56f5b1cf PZ |
878 | * @otg_port: OTG port number |
879 | * @frame_list: Frame list | |
880 | * @frame_list_dma: Frame list DMA address | |
95105a99 | 881 | * @frame_list_sz: Frame list size |
3b5fcc9a GH |
882 | * @desc_gen_cache: Kmem cache for generic descriptors |
883 | * @desc_hsisoc_cache: Kmem cache for hs isochronous descriptors | |
941fcce4 DN |
884 | * |
885 | * These are for peripheral mode: | |
886 | * | |
887 | * @driver: USB gadget driver | |
941fcce4 DN |
888 | * @dedicated_fifos: Set if the hardware has dedicated IN-EP fifos. |
889 | * @num_of_eps: Number of available EPs (excluding EP0) | |
890 | * @debug_root: Root directrory for debugfs. | |
891 | * @debug_file: Main status file for debugfs. | |
9e14d0a5 | 892 | * @debug_testmode: Testmode status file for debugfs. |
941fcce4 DN |
893 | * @debug_fifo: FIFO status file for debugfs. |
894 | * @ep0_reply: Request used for ep0 reply. | |
895 | * @ep0_buff: Buffer for EP0 reply data, if needed. | |
896 | * @ctrl_buff: Buffer for EP0 control requests. | |
897 | * @ctrl_req: Request for EP0 control packets. | |
fe0b94ab | 898 | * @ep0_state: EP0 control transfers state |
9e14d0a5 | 899 | * @test_mode: USB test mode requested by the host |
0f6b80c0 VA |
900 | * @setup_desc_dma: EP0 setup stage desc chain DMA address |
901 | * @setup_desc: EP0 setup stage desc chain pointer | |
902 | * @ctrl_in_desc_dma: EP0 IN data phase desc chain DMA address | |
903 | * @ctrl_in_desc: EP0 IN data phase desc chain pointer | |
904 | * @ctrl_out_desc_dma: EP0 OUT data phase desc chain DMA address | |
905 | * @ctrl_out_desc: EP0 OUT data phase desc chain pointer | |
941fcce4 | 906 | * @eps: The endpoints being supplied to the gadget framework |
56f5b1cf PZ |
907 | */ |
908 | struct dwc2_hsotg { | |
909 | struct device *dev; | |
910 | void __iomem *regs; | |
9badec2f MK |
911 | /** Params detected from hardware */ |
912 | struct dwc2_hw_params hw_params; | |
913 | /** Params to actually use */ | |
bea8e86c | 914 | struct dwc2_core_params params; |
56f5b1cf | 915 | enum usb_otg_state op_state; |
c0155b9d | 916 | enum usb_dr_mode dr_mode; |
e39af88f MS |
917 | unsigned int hcd_enabled:1; |
918 | unsigned int gadget_enabled:1; | |
09a75e85 | 919 | unsigned int ll_hw_enabled:1; |
56f5b1cf | 920 | |
941fcce4 DN |
921 | struct phy *phy; |
922 | struct usb_phy *uphy; | |
09a75e85 | 923 | struct dwc2_hsotg_plat *plat; |
b98866c2 | 924 | struct regulator_bulk_data supplies[DWC2_NUM_SUPPLIES]; |
09a75e85 | 925 | u32 phyif; |
941fcce4 DN |
926 | |
927 | spinlock_t lock; | |
928 | void *priv; | |
929 | int irq; | |
930 | struct clk *clk; | |
83f8da56 | 931 | struct reset_control *reset; |
f2830ad4 | 932 | struct reset_control *reset_ecc; |
941fcce4 | 933 | |
56f5b1cf PZ |
934 | unsigned int queuing_high_bandwidth:1; |
935 | unsigned int srp_success:1; | |
936 | ||
937 | struct workqueue_struct *wq_otg; | |
938 | struct work_struct wf_otg; | |
939 | struct timer_list wkp_timer; | |
940 | enum dwc2_lx_state lx_state; | |
cc1e204c MYK |
941 | struct dwc2_gregs_backup gr_backup; |
942 | struct dwc2_dregs_backup dr_backup; | |
943 | struct dwc2_hregs_backup hr_backup; | |
56f5b1cf | 944 | |
941fcce4 | 945 | struct dentry *debug_root; |
563cf017 | 946 | struct debugfs_regset32 *regset; |
941fcce4 DN |
947 | |
948 | /* DWC OTG HW Release versions */ | |
949 | #define DWC2_CORE_REV_2_71a 0x4f54271a | |
950 | #define DWC2_CORE_REV_2_90a 0x4f54290a | |
e1f411d1 | 951 | #define DWC2_CORE_REV_2_91a 0x4f54291a |
941fcce4 DN |
952 | #define DWC2_CORE_REV_2_92a 0x4f54292a |
953 | #define DWC2_CORE_REV_2_94a 0x4f54294a | |
954 | #define DWC2_CORE_REV_3_00a 0x4f54300a | |
fef6bc37 | 955 | #define DWC2_CORE_REV_3_10a 0x4f54310a |
1e6b98eb VM |
956 | #define DWC2_FS_IOT_REV_1_00a 0x5531100a |
957 | #define DWC2_HS_IOT_REV_1_00a 0x5532100a | |
941fcce4 | 958 | |
d14ccaba GS |
959 | /* DWC OTG HW Core ID */ |
960 | #define DWC2_OTG_ID 0x4f540000 | |
961 | #define DWC2_FS_IOT_ID 0x55310000 | |
962 | #define DWC2_HS_IOT_ID 0x55320000 | |
963 | ||
941fcce4 | 964 | #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) |
56f5b1cf PZ |
965 | union dwc2_hcd_internal_flags { |
966 | u32 d32; | |
967 | struct { | |
968 | unsigned port_connect_status_change:1; | |
969 | unsigned port_connect_status:1; | |
970 | unsigned port_reset_change:1; | |
971 | unsigned port_enable_change:1; | |
972 | unsigned port_suspend_change:1; | |
973 | unsigned port_over_current_change:1; | |
974 | unsigned port_l1_change:1; | |
fd4850cf | 975 | unsigned reserved:25; |
56f5b1cf PZ |
976 | } b; |
977 | } flags; | |
978 | ||
979 | struct list_head non_periodic_sched_inactive; | |
38d2b5fb | 980 | struct list_head non_periodic_sched_waiting; |
56f5b1cf PZ |
981 | struct list_head non_periodic_sched_active; |
982 | struct list_head *non_periodic_qh_ptr; | |
983 | struct list_head periodic_sched_inactive; | |
984 | struct list_head periodic_sched_ready; | |
985 | struct list_head periodic_sched_assigned; | |
986 | struct list_head periodic_sched_queued; | |
c9c8ac01 | 987 | struct list_head split_order; |
56f5b1cf | 988 | u16 periodic_usecs; |
9f9f09b0 DA |
989 | unsigned long hs_periodic_bitmap[ |
990 | DIV_ROUND_UP(DWC2_HS_SCHEDULE_US, BITS_PER_LONG)]; | |
56f5b1cf PZ |
991 | u16 frame_number; |
992 | u16 periodic_qh_count; | |
734643df | 993 | bool bus_suspended; |
fbb9e22b | 994 | bool new_connection; |
56f5b1cf | 995 | |
483bb254 DA |
996 | u16 last_frame_num; |
997 | ||
56f5b1cf PZ |
998 | #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS |
999 | #define FRAME_NUM_ARRAY_SIZE 1000 | |
56f5b1cf PZ |
1000 | u16 *frame_num_array; |
1001 | u16 *last_frame_num_array; | |
1002 | int frame_num_idx; | |
1003 | int dumped_frame_num_array; | |
1004 | #endif | |
1005 | ||
1006 | struct list_head free_hc_list; | |
1007 | int periodic_channels; | |
1008 | int non_periodic_channels; | |
20f2eb9c | 1009 | int available_host_channels; |
56f5b1cf PZ |
1010 | struct dwc2_host_chan *hc_ptr_array[MAX_EPS_CHANNELS]; |
1011 | u8 *status_buf; | |
1012 | dma_addr_t status_buf_dma; | |
1013 | #define DWC2_HCD_STATUS_BUF_SIZE 64 | |
1014 | ||
1015 | struct delayed_work start_work; | |
1016 | struct delayed_work reset_work; | |
56f5b1cf PZ |
1017 | u8 otg_port; |
1018 | u32 *frame_list; | |
1019 | dma_addr_t frame_list_dma; | |
95105a99 | 1020 | u32 frame_list_sz; |
3b5fcc9a GH |
1021 | struct kmem_cache *desc_gen_cache; |
1022 | struct kmem_cache *desc_hsisoc_cache; | |
56f5b1cf | 1023 | |
56f5b1cf PZ |
1024 | #ifdef DEBUG |
1025 | u32 frrem_samples; | |
1026 | u64 frrem_accum; | |
1027 | ||
1028 | u32 hfnum_7_samples_a; | |
1029 | u64 hfnum_7_frrem_accum_a; | |
1030 | u32 hfnum_0_samples_a; | |
1031 | u64 hfnum_0_frrem_accum_a; | |
1032 | u32 hfnum_other_samples_a; | |
1033 | u64 hfnum_other_frrem_accum_a; | |
1034 | ||
1035 | u32 hfnum_7_samples_b; | |
1036 | u64 hfnum_7_frrem_accum_b; | |
1037 | u32 hfnum_0_samples_b; | |
1038 | u64 hfnum_0_frrem_accum_b; | |
1039 | u32 hfnum_other_samples_b; | |
1040 | u64 hfnum_other_frrem_accum_b; | |
1041 | #endif | |
941fcce4 DN |
1042 | #endif /* CONFIG_USB_DWC2_HOST || CONFIG_USB_DWC2_DUAL_ROLE */ |
1043 | ||
b98866c2 JY |
1044 | #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \ |
1045 | IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) | |
941fcce4 DN |
1046 | /* Gadget structures */ |
1047 | struct usb_gadget_driver *driver; | |
941fcce4 DN |
1048 | int fifo_mem; |
1049 | unsigned int dedicated_fifos:1; | |
1050 | unsigned char num_of_eps; | |
1051 | u32 fifo_map; | |
1052 | ||
1053 | struct usb_request *ep0_reply; | |
1054 | struct usb_request *ctrl_req; | |
3f95001d MYK |
1055 | void *ep0_buff; |
1056 | void *ctrl_buff; | |
fe0b94ab | 1057 | enum dwc2_ep0_state ep0_state; |
9e14d0a5 | 1058 | u8 test_mode; |
941fcce4 | 1059 | |
0f6b80c0 VA |
1060 | dma_addr_t setup_desc_dma[2]; |
1061 | struct dwc2_dma_desc *setup_desc[2]; | |
1062 | dma_addr_t ctrl_in_desc_dma; | |
1063 | struct dwc2_dma_desc *ctrl_in_desc; | |
1064 | dma_addr_t ctrl_out_desc_dma; | |
1065 | struct dwc2_dma_desc *ctrl_out_desc; | |
1066 | ||
941fcce4 | 1067 | struct usb_gadget gadget; |
dc6e69e6 | 1068 | unsigned int enabled:1; |
4ace06e8 | 1069 | unsigned int connected:1; |
1f91b4cc FB |
1070 | struct dwc2_hsotg_ep *eps_in[MAX_EPS_CHANNELS]; |
1071 | struct dwc2_hsotg_ep *eps_out[MAX_EPS_CHANNELS]; | |
941fcce4 | 1072 | #endif /* CONFIG_USB_DWC2_PERIPHERAL || CONFIG_USB_DWC2_DUAL_ROLE */ |
56f5b1cf PZ |
1073 | }; |
1074 | ||
1075 | /* Reasons for halting a host channel */ | |
1076 | enum dwc2_halt_status { | |
1077 | DWC2_HC_XFER_NO_HALT_STATUS, | |
1078 | DWC2_HC_XFER_COMPLETE, | |
1079 | DWC2_HC_XFER_URB_COMPLETE, | |
1080 | DWC2_HC_XFER_ACK, | |
1081 | DWC2_HC_XFER_NAK, | |
1082 | DWC2_HC_XFER_NYET, | |
1083 | DWC2_HC_XFER_STALL, | |
1084 | DWC2_HC_XFER_XACT_ERR, | |
1085 | DWC2_HC_XFER_FRAME_OVERRUN, | |
1086 | DWC2_HC_XFER_BABBLE_ERR, | |
1087 | DWC2_HC_XFER_DATA_TOGGLE_ERR, | |
1088 | DWC2_HC_XFER_AHB_ERR, | |
1089 | DWC2_HC_XFER_PERIODIC_INCOMPLETE, | |
1090 | DWC2_HC_XFER_URB_DEQUEUE, | |
1091 | }; | |
1092 | ||
1e6b98eb VM |
1093 | /* Core version information */ |
1094 | static inline bool dwc2_is_iot(struct dwc2_hsotg *hsotg) | |
1095 | { | |
1096 | return (hsotg->hw_params.snpsid & 0xfff00000) == 0x55300000; | |
1097 | } | |
1098 | ||
1099 | static inline bool dwc2_is_fs_iot(struct dwc2_hsotg *hsotg) | |
1100 | { | |
1101 | return (hsotg->hw_params.snpsid & 0xffff0000) == 0x55310000; | |
1102 | } | |
1103 | ||
1104 | static inline bool dwc2_is_hs_iot(struct dwc2_hsotg *hsotg) | |
1105 | { | |
1106 | return (hsotg->hw_params.snpsid & 0xffff0000) == 0x55320000; | |
1107 | } | |
1108 | ||
56f5b1cf PZ |
1109 | /* |
1110 | * The following functions support initialization of the core driver component | |
1111 | * and the DWC_otg controller | |
1112 | */ | |
6e6360b6 | 1113 | int dwc2_core_reset(struct dwc2_hsotg *hsotg, bool skip_wait); |
9da51974 JY |
1114 | int dwc2_core_reset_and_force_dr_mode(struct dwc2_hsotg *hsotg); |
1115 | int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg); | |
1116 | int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, bool restore); | |
56f5b1cf | 1117 | |
323230ef JY |
1118 | bool dwc2_force_mode_if_needed(struct dwc2_hsotg *hsotg, bool host); |
1119 | void dwc2_clear_force_mode(struct dwc2_hsotg *hsotg); | |
09c96980 JY |
1120 | void dwc2_force_dr_mode(struct dwc2_hsotg *hsotg); |
1121 | ||
9da51974 | 1122 | bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg); |
56f5b1cf PZ |
1123 | |
1124 | /* | |
1125 | * Common core Functions. | |
1126 | * The following functions support managing the DWC_otg controller in either | |
1127 | * device or host mode. | |
1128 | */ | |
9da51974 JY |
1129 | void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes); |
1130 | void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num); | |
1131 | void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg); | |
56f5b1cf | 1132 | |
9da51974 JY |
1133 | void dwc2_enable_global_interrupts(struct dwc2_hsotg *hcd); |
1134 | void dwc2_disable_global_interrupts(struct dwc2_hsotg *hcd); | |
56f5b1cf PZ |
1135 | |
1136 | /* This function should be called on every hardware interrupt. */ | |
9da51974 | 1137 | irqreturn_t dwc2_handle_common_intr(int irq, void *dev); |
56f5b1cf | 1138 | |
323230ef JY |
1139 | /* The device ID match table */ |
1140 | extern const struct of_device_id dwc2_of_match_table[]; | |
1141 | ||
9da51974 JY |
1142 | int dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg); |
1143 | int dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg); | |
ecb176c6 | 1144 | |
334bbd4e | 1145 | /* Parameters */ |
c1d286cf | 1146 | int dwc2_get_hwparams(struct dwc2_hsotg *hsotg); |
334bbd4e JY |
1147 | int dwc2_init_params(struct dwc2_hsotg *hsotg); |
1148 | ||
6bea9620 JY |
1149 | /* |
1150 | * The following functions check the controller's OTG operation mode | |
1151 | * capability (GHWCFG2.OTG_MODE). | |
1152 | * | |
1153 | * These functions can be used before the internal hsotg->hw_params | |
1154 | * are read in and cached so they always read directly from the | |
1155 | * GHWCFG2 register. | |
1156 | */ | |
9da51974 | 1157 | unsigned int dwc2_op_mode(struct dwc2_hsotg *hsotg); |
6bea9620 JY |
1158 | bool dwc2_hw_is_otg(struct dwc2_hsotg *hsotg); |
1159 | bool dwc2_hw_is_host(struct dwc2_hsotg *hsotg); | |
1160 | bool dwc2_hw_is_device(struct dwc2_hsotg *hsotg); | |
1161 | ||
1696d5ab JY |
1162 | /* |
1163 | * Returns the mode of operation, host or device | |
1164 | */ | |
1165 | static inline int dwc2_is_host_mode(struct dwc2_hsotg *hsotg) | |
1166 | { | |
1167 | return (dwc2_readl(hsotg->regs + GINTSTS) & GINTSTS_CURMODE_HOST) != 0; | |
1168 | } | |
9da51974 | 1169 | |
1696d5ab JY |
1170 | static inline int dwc2_is_device_mode(struct dwc2_hsotg *hsotg) |
1171 | { | |
1172 | return (dwc2_readl(hsotg->regs + GINTSTS) & GINTSTS_CURMODE_HOST) == 0; | |
1173 | } | |
1174 | ||
56f5b1cf PZ |
1175 | /* |
1176 | * Dump core registers and SPRAM | |
1177 | */ | |
9da51974 JY |
1178 | void dwc2_dump_dev_registers(struct dwc2_hsotg *hsotg); |
1179 | void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg); | |
1180 | void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg); | |
56f5b1cf | 1181 | |
117777b2 | 1182 | /* Gadget defines */ |
b98866c2 JY |
1183 | #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \ |
1184 | IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) | |
9da51974 JY |
1185 | int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg); |
1186 | int dwc2_hsotg_suspend(struct dwc2_hsotg *dwc2); | |
1187 | int dwc2_hsotg_resume(struct dwc2_hsotg *dwc2); | |
f3768997 | 1188 | int dwc2_gadget_init(struct dwc2_hsotg *hsotg); |
9da51974 JY |
1189 | void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2, |
1190 | bool reset); | |
1191 | void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg); | |
1192 | void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2); | |
1193 | int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode); | |
f81f46e1 | 1194 | #define dwc2_is_device_connected(hsotg) (hsotg->connected) |
58e52ff6 JY |
1195 | int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg); |
1196 | int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg); | |
c138ecfa SA |
1197 | int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg *hsotg); |
1198 | int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg); | |
1199 | int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg *hsotg); | |
117777b2 | 1200 | #else |
1f91b4cc | 1201 | static inline int dwc2_hsotg_remove(struct dwc2_hsotg *dwc2) |
117777b2 | 1202 | { return 0; } |
1f91b4cc | 1203 | static inline int dwc2_hsotg_suspend(struct dwc2_hsotg *dwc2) |
117777b2 | 1204 | { return 0; } |
1f91b4cc | 1205 | static inline int dwc2_hsotg_resume(struct dwc2_hsotg *dwc2) |
117777b2 | 1206 | { return 0; } |
f3768997 | 1207 | static inline int dwc2_gadget_init(struct dwc2_hsotg *hsotg) |
117777b2 | 1208 | { return 0; } |
1f91b4cc | 1209 | static inline void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2, |
9da51974 | 1210 | bool reset) {} |
1f91b4cc FB |
1211 | static inline void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg) {} |
1212 | static inline void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2) {} | |
1213 | static inline int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, | |
9da51974 | 1214 | int testmode) |
f91eea44 | 1215 | { return 0; } |
f81f46e1 | 1216 | #define dwc2_is_device_connected(hsotg) (0) |
58e52ff6 JY |
1217 | static inline int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg) |
1218 | { return 0; } | |
1219 | static inline int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg) | |
1220 | { return 0; } | |
c138ecfa SA |
1221 | static inline int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg *hsotg) |
1222 | { return 0; } | |
1223 | static inline int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg) | |
1224 | { return 0; } | |
1225 | static inline int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg *hsotg) | |
1226 | { return 0; } | |
117777b2 DN |
1227 | #endif |
1228 | ||
1229 | #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) | |
9da51974 JY |
1230 | int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg); |
1231 | int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg, int us); | |
1232 | void dwc2_hcd_connect(struct dwc2_hsotg *hsotg); | |
1233 | void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force); | |
1234 | void dwc2_hcd_start(struct dwc2_hsotg *hsotg); | |
58e52ff6 JY |
1235 | int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg); |
1236 | int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg); | |
117777b2 | 1237 | #else |
117777b2 DN |
1238 | static inline int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg) |
1239 | { return 0; } | |
fae4e826 DA |
1240 | static inline int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg, |
1241 | int us) | |
1242 | { return 0; } | |
6a659531 DA |
1243 | static inline void dwc2_hcd_connect(struct dwc2_hsotg *hsotg) {} |
1244 | static inline void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force) {} | |
117777b2 DN |
1245 | static inline void dwc2_hcd_start(struct dwc2_hsotg *hsotg) {} |
1246 | static inline void dwc2_hcd_remove(struct dwc2_hsotg *hsotg) {} | |
4fe160d5 | 1247 | static inline int dwc2_hcd_init(struct dwc2_hsotg *hsotg) |
117777b2 | 1248 | { return 0; } |
58e52ff6 JY |
1249 | static inline int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg) |
1250 | { return 0; } | |
1251 | static inline int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg) | |
1252 | { return 0; } | |
1253 | ||
117777b2 DN |
1254 | #endif |
1255 | ||
56f5b1cf | 1256 | #endif /* __DWC2_CORE_H__ */ |