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usb: dwc2: gadget: Transfer length limit checking for DDMA
[linux-block.git] / drivers / usb / dwc2 / core.h
CommitLineData
56f5b1cf
PZ		 1/*
2 * core.h - DesignWare HS OTG Controller common declarations
3 *
4 * Copyright (C) 2004-2013 Synopsys, Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions, and the following disclaimer,
11 * without modification.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The names of the above-listed copyright holders may not be used
16 * to endorse or promote products derived from this software without
17 * specific prior written permission.
18 *
19 * ALTERNATIVELY, this software may be distributed under the terms of the
20 * GNU General Public License ("GPL") as published by the Free Software
21 * Foundation; either version 2 of the License, or (at your option) any
22 * later version.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
25 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
28 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
29 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
30 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
31 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
32 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
33 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
34 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 */
36
37#ifndef __DWC2_CORE_H__
38#define __DWC2_CORE_H__
39
f7c0b143
DN		 40#include <linux/phy/phy.h>
41#include <linux/regulator/consumer.h>
42#include <linux/usb/gadget.h>
43#include <linux/usb/otg.h>
56f5b1cf
PZ		 44#include <linux/usb/phy.h>
45#include "hw.h"
46
74fc4a75
DA		 47/*
48 * Suggested defines for tracers:
49 * - no_printk: Disable tracing
50 * - pr_info: Print this info to the console
51 * - trace_printk: Print this info to trace buffer (good for verbose logging)
52 */
53
54#define DWC2_TRACE_SCHEDULER no_printk
55#define DWC2_TRACE_SCHEDULER_VB no_printk
56
57/* Detailed scheduler tracing, but won't overwhelm console */
58#define dwc2_sch_dbg(hsotg, fmt, ...) \
59 DWC2_TRACE_SCHEDULER(pr_fmt("%s: SCH: " fmt), \
60 dev_name(hsotg->dev), ##__VA_ARGS__)
61
62/* Verbose scheduler tracing */
63#define dwc2_sch_vdbg(hsotg, fmt, ...) \
64 DWC2_TRACE_SCHEDULER_VB(pr_fmt("%s: SCH: " fmt), \
65 dev_name(hsotg->dev), ##__VA_ARGS__)
66
23e34392
AB		 67#ifdef CONFIG_MIPS
68/*
69 * There are some MIPS machines that can run in either big-endian
70 * or little-endian mode and that use the dwc2 register without
71 * a byteswap in both ways.
72 * Unlike other architectures, MIPS apparently does not require a
73 * barrier before the __raw_writel() to synchronize with DMA but does
74 * require the barrier after the __raw_writel() to serialize a set of
75 * writes. This set of operations was added specifically for MIPS and
76 * should only be used there.
77 */
95c8bc36 78static inline u32 dwc2_readl(const void __iomem *addr)
56f5b1cf 79{
95c8bc36
AS		 80 u32 value = __raw_readl(addr);
81
82 /* In order to preserve endianness __raw_* operation is used. Therefore
83 * a barrier is needed to ensure IO access is not re-ordered across
84 * reads or writes
85 */
86 mb();
87 return value;
56f5b1cf
PZ		 88}
89
95c8bc36
AS		 90static inline void dwc2_writel(u32 value, void __iomem *addr)
91{
92 __raw_writel(value, addr);
93
94 /*
95 * In order to preserve endianness __raw_* operation is used. Therefore
96 * a barrier is needed to ensure IO access is not re-ordered across
97 * reads or writes
98 */
99 mb();
100#ifdef DWC2_LOG_WRITES
101 pr_info("INFO:: wrote %08x to %p\n", value, addr);
56f5b1cf 102#endif
95c8bc36 103}
23e34392
AB		 104#else
105/* Normal architectures just use readl/write */
106static inline u32 dwc2_readl(const void __iomem *addr)
107{
108 return readl(addr);
109}
110
111static inline void dwc2_writel(u32 value, void __iomem *addr)
112{
113 writel(value, addr);
114
115#ifdef DWC2_LOG_WRITES
116 pr_info("info:: wrote %08x to %p\n", value, addr);
117#endif
118}
119#endif
56f5b1cf
PZ		 120
121/* Maximum number of Endpoints/HostChannels */
122#define MAX_EPS_CHANNELS 16
123
1f91b4cc
FB		 124/* dwc2-hsotg declarations */
125static const char * const dwc2_hsotg_supply_names[] = {
f7c0b143
DN		 126 "vusb_d", /* digital USB supply, 1.2V */
127 "vusb_a", /* analog USB supply, 1.1V */
128};
129
130/*
131 * EP0_MPS_LIMIT
132 *
133 * Unfortunately there seems to be a limit of the amount of data that can
134 * be transferred by IN transactions on EP0. This is either 127 bytes or 3
135 * packets (which practically means 1 packet and 63 bytes of data) when the
136 * MPS is set to 64.
137 *
138 * This means if we are wanting to move >127 bytes of data, we need to
139 * split the transactions up, but just doing one packet at a time does
140 * not work (this may be an implicit DATA0 PID on first packet of the
141 * transaction) and doing 2 packets is outside the controller's limits.
142 *
143 * If we try to lower the MPS size for EP0, then no transfers work properly
144 * for EP0, and the system will fail basic enumeration. As no cause for this
145 * has currently been found, we cannot support any large IN transfers for
146 * EP0.
147 */
148#define EP0_MPS_LIMIT 64
149
941fcce4 150struct dwc2_hsotg;
1f91b4cc 151struct dwc2_hsotg_req;
f7c0b143
DN		 152
153/**
1f91b4cc 154 * struct dwc2_hsotg_ep - driver endpoint definition.
f7c0b143
DN		 155 * @ep: The gadget layer representation of the endpoint.
156 * @name: The driver generated name for the endpoint.
157 * @queue: Queue of requests for this endpoint.
158 * @parent: Reference back to the parent device structure.
159 * @req: The current request that the endpoint is processing. This is
160 * used to indicate an request has been loaded onto the endpoint
161 * and has yet to be completed (maybe due to data move, or simply
162 * awaiting an ack from the core all the data has been completed).
163 * @debugfs: File entry for debugfs file for this endpoint.
164 * @lock: State lock to protect contents of endpoint.
165 * @dir_in: Set to true if this endpoint is of the IN direction, which
166 * means that it is sending data to the Host.
167 * @index: The index for the endpoint registers.
168 * @mc: Multi Count - number of transactions per microframe
142bd33f 169 * @interval - Interval for periodic endpoints, in frames or microframes.
f7c0b143
DN		 170 * @name: The name array passed to the USB core.
171 * @halted: Set if the endpoint has been halted.
172 * @periodic: Set if this is a periodic ep, such as Interrupt
173 * @isochronous: Set if this is a isochronous ep
8a20fa45 174 * @send_zlp: Set if we need to send a zero-length packet.
f7c0b143
DN		 175 * @total_data: The total number of data bytes done.
176 * @fifo_size: The size of the FIFO (for periodic IN endpoints)
177 * @fifo_load: The amount of data loaded into the FIFO (periodic IN)
178 * @last_load: The offset of data for the last start of request.
179 * @size_loaded: The last loaded size for DxEPTSIZE for periodic IN
92d1635d
VM		 180 * @target_frame: Targeted frame num to setup next ISOC transfer
181 * @frame_overrun: Indicates SOF number overrun in DSTS
f7c0b143
DN		 182 *
183 * This is the driver's state for each registered enpoint, allowing it
184 * to keep track of transactions that need doing. Each endpoint has a
185 * lock to protect the state, to try and avoid using an overall lock
186 * for the host controller as much as possible.
187 *
188 * For periodic IN endpoints, we have fifo_size and fifo_load to try
189 * and keep track of the amount of data in the periodic FIFO for each
190 * of these as we don't have a status register that tells us how much
191 * is in each of them. (note, this may actually be useless information
192 * as in shared-fifo mode periodic in acts like a single-frame packet
193 * buffer than a fifo)
194 */
1f91b4cc 195struct dwc2_hsotg_ep {
f7c0b143
DN		 196 struct usb_ep ep;
197 struct list_head queue;
941fcce4 198 struct dwc2_hsotg *parent;
1f91b4cc 199 struct dwc2_hsotg_req *req;
f7c0b143
DN		 200 struct dentry *debugfs;
201
202 unsigned long total_data;
203 unsigned int size_loaded;
204 unsigned int last_load;
205 unsigned int fifo_load;
206 unsigned short fifo_size;
b203d0a2 207 unsigned short fifo_index;
f7c0b143
DN		 208
209 unsigned char dir_in;
210 unsigned char index;
211 unsigned char mc;
212 unsigned char interval;
213
214 unsigned int halted:1;
215 unsigned int periodic:1;
216 unsigned int isochronous:1;
8a20fa45 217 unsigned int send_zlp:1;
92d1635d
VM		 218 unsigned int target_frame;
219#define TARGET_FRAME_INITIAL 0xFFFFFFFF
220 bool frame_overrun;
f7c0b143
DN		 221
222 char name[10];
223};
224
f7c0b143 225/**
1f91b4cc 226 * struct dwc2_hsotg_req - data transfer request
f7c0b143
DN		 227 * @req: The USB gadget request
228 * @queue: The list of requests for the endpoint this is queued for.
7d24c1b5 229 * @saved_req_buf: variable to save req.buf when bounce buffers are used.
f7c0b143 230 */
1f91b4cc 231struct dwc2_hsotg_req {
f7c0b143
DN		 232 struct usb_request req;
233 struct list_head queue;
7d24c1b5 234 void *saved_req_buf;
f7c0b143
DN		 235};
236
941fcce4 237#if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
f7c0b143
DN		 238#define call_gadget(_hs, _entry) \
239do { \
240 if ((_hs)->gadget.speed != USB_SPEED_UNKNOWN && \
241 (_hs)->driver && (_hs)->driver->_entry) { \
242 spin_unlock(&_hs->lock); \
243 (_hs)->driver->_entry(&(_hs)->gadget); \
244 spin_lock(&_hs->lock); \
245 } \
246} while (0)
941fcce4
DN		 247#else
248#define call_gadget(_hs, _entry) do {} while (0)
249#endif
f7c0b143 250
56f5b1cf
PZ		 251struct dwc2_hsotg;
252struct dwc2_host_chan;
253
254/* Device States */
255enum dwc2_lx_state {
256 DWC2_L0, /* On state */
257 DWC2_L1, /* LPM sleep state */
258 DWC2_L2, /* USB suspend state */
259 DWC2_L3, /* Off state */
260};
261
3fa95385
JY		 262/*
263 * Gadget periodic tx fifo sizes as used by legacy driver
264 * EP0 is not included
265 */
266#define DWC2_G_P_LEGACY_TX_FIFO_SIZE {256, 256, 256, 256, 768, 768, 768, \
267 768, 0, 0, 0, 0, 0, 0, 0}
268
fe0b94ab
MYK		 269/* Gadget ep0 states */
270enum dwc2_ep0_state {
271 DWC2_EP0_SETUP,
272 DWC2_EP0_DATA_IN,
273 DWC2_EP0_DATA_OUT,
274 DWC2_EP0_STATUS_IN,
275 DWC2_EP0_STATUS_OUT,
276};
277
56f5b1cf
PZ		 278/**
279 * struct dwc2_core_params - Parameters for configuring the core
280 *
91121c10
MK		 281 * @otg_cap: Specifies the OTG capabilities.
282 * 0 - HNP and SRP capable
56f5b1cf 283 * 1 - SRP Only capable
91121c10
MK		 284 * 2 - No HNP/SRP capable (always available)
285 * Defaults to best available option (0, 1, then 2)
725acc86 286 * @otg_ver: OTG version supported
91121c10 287 * 0 - 1.3 (default)
725acc86 288 * 1 - 2.0
e7839f99 289 * @host_dma: Specifies whether to use slave or DMA mode for accessing
56f5b1cf
PZ		 290 * the data FIFOs. The driver will automatically detect the
291 * value for this parameter if none is specified.
91121c10 292 * 0 - Slave (always available)
56f5b1cf
PZ		 293 * 1 - DMA (default, if available)
294 * @dma_desc_enable: When DMA mode is enabled, specifies whether to use
295 * address DMA mode or descriptor DMA mode for accessing
296 * the data FIFOs. The driver will automatically detect the
297 * value for this if none is specified.
298 * 0 - Address DMA
299 * 1 - Descriptor DMA (default, if available)
fbb9e22b
MYK		 300 * @dma_desc_fs_enable: When DMA mode is enabled, specifies whether to use
301 * address DMA mode or descriptor DMA mode for accessing
302 * the data FIFOs in Full Speed mode only. The driver
303 * will automatically detect the value for this if none is
304 * specified.
305 * 0 - Address DMA
306 * 1 - Descriptor DMA in FS (default, if available)
56f5b1cf
PZ		 307 * @speed: Specifies the maximum speed of operation in host and
308 * device mode. The actual speed depends on the speed of
309 * the attached device and the value of phy_type.
91121c10
MK		 310 * 0 - High Speed
311 * (default when phy_type is UTMI+ or ULPI)
56f5b1cf 312 * 1 - Full Speed
91121c10 313 * (default when phy_type is Full Speed)
56f5b1cf 314 * @enable_dynamic_fifo: 0 - Use coreConsultant-specified FIFO size parameters
91121c10 315 * 1 - Allow dynamic FIFO sizing (default, if available)
725acc86 316 * @en_multiple_tx_fifo: Specifies whether dedicated per-endpoint transmit FIFOs
c1d286cf
JY		 317 * are enabled for non-periodic IN endpoints in device
318 * mode.
56f5b1cf
PZ		 319 * @host_rx_fifo_size: Number of 4-byte words in the Rx FIFO in host mode when
320 * dynamic FIFO sizing is enabled
91121c10
MK		 321 * 16 to 32768
322 * Actual maximum value is autodetected and also
323 * the default.
56f5b1cf
PZ		 324 * @host_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO
325 * in host mode when dynamic FIFO sizing is enabled
91121c10
MK		 326 * 16 to 32768
327 * Actual maximum value is autodetected and also
328 * the default.
56f5b1cf
PZ		 329 * @host_perio_tx_fifo_size: Number of 4-byte words in the periodic Tx FIFO in
330 * host mode when dynamic FIFO sizing is enabled
91121c10
MK		 331 * 16 to 32768
332 * Actual maximum value is autodetected and also
333 * the default.
56f5b1cf 334 * @max_transfer_size: The maximum transfer size supported, in bytes
91121c10
MK		 335 * 2047 to 65,535
336 * Actual maximum value is autodetected and also
337 * the default.
56f5b1cf 338 * @max_packet_count: The maximum number of packets in a transfer
91121c10
MK		 339 * 15 to 511
340 * Actual maximum value is autodetected and also
341 * the default.
56f5b1cf 342 * @host_channels: The number of host channel registers to use
91121c10
MK		 343 * 1 to 16
344 * Actual maximum value is autodetected and also
345 * the default.
56f5b1cf
PZ		 346 * @phy_type: Specifies the type of PHY interface to use. By default,
347 * the driver will automatically detect the phy_type.
91121c10
MK		 348 * 0 - Full Speed Phy
349 * 1 - UTMI+ Phy
350 * 2 - ULPI Phy
351 * Defaults to best available option (2, 1, then 0)
56f5b1cf
PZ		 352 * @phy_utmi_width: Specifies the UTMI+ Data Width (in bits). This parameter
353 * is applicable for a phy_type of UTMI+ or ULPI. (For a
354 * ULPI phy_type, this parameter indicates the data width
355 * between the MAC and the ULPI Wrapper.) Also, this
356 * parameter is applicable only if the OTG_HSPHY_WIDTH cC
357 * parameter was set to "8 and 16 bits", meaning that the
358 * core has been configured to work at either data path
359 * width.
91121c10 360 * 8 or 16 (default 16 if available)
56f5b1cf
PZ		 361 * @phy_ulpi_ddr: Specifies whether the ULPI operates at double or single
362 * data rate. This parameter is only applicable if phy_type
363 * is ULPI.
364 * 0 - single data rate ULPI interface with 8 bit wide
365 * data bus (default)
366 * 1 - double data rate ULPI interface with 4 bit wide
367 * data bus
368 * @phy_ulpi_ext_vbus: For a ULPI phy, specifies whether to use the internal or
369 * external supply to drive the VBus
91121c10
MK		 370 * 0 - Internal supply (default)
371 * 1 - External supply
56f5b1cf
PZ		 372 * @i2c_enable: Specifies whether to use the I2Cinterface for a full
373 * speed PHY. This parameter is only applicable if phy_type
374 * is FS.
375 * 0 - No (default)
376 * 1 - Yes
91121c10
MK		 377 * @ulpi_fs_ls: Make ULPI phy operate in FS/LS mode only
378 * 0 - No (default)
379 * 1 - Yes
725acc86
PZ		 380 * @host_support_fs_ls_low_power: Specifies whether low power mode is supported
381 * when attached to a Full Speed or Low Speed device in
382 * host mode.
383 * 0 - Don't support low power mode (default)
384 * 1 - Support low power mode
385 * @host_ls_low_power_phy_clk: Specifies the PHY clock rate in low power mode
91121c10
MK		 386 * when connected to a Low Speed device in host
387 * mode. This parameter is applicable only if
388 * host_support_fs_ls_low_power is enabled.
725acc86 389 * 0 - 48 MHz
91121c10 390 * (default when phy_type is UTMI+ or ULPI)
725acc86 391 * 1 - 6 MHz
91121c10
MK		 392 * (default when phy_type is Full Speed)
393 * @ts_dline: Enable Term Select Dline pulsing
394 * 0 - No (default)
395 * 1 - Yes
396 * @reload_ctl: Allow dynamic reloading of HFIR register during runtime
397 * 0 - No (default for core < 2.92a)
398 * 1 - Yes (default for core >= 2.92a)
4d3190e1
PZ		 399 * @ahbcfg: This field allows the default value of the GAHBCFG
400 * register to be overridden
91121c10
MK		 401 * -1 - GAHBCFG value will be set to 0x06
402 * (INCR4, default)
4d3190e1
PZ		 403 * all others - GAHBCFG value will be overridden with
404 * this value
91121c10
MK		 405 * Not all bits can be controlled like this, the
406 * bits defined by GAHBCFG_CTRL_MASK are controlled
407 * by the driver and are ignored in this
408 * configuration value.
20f2eb9c 409 * @uframe_sched: True to enable the microframe scheduler
a6d249d8
GH		 410 * @external_id_pin_ctl: Specifies whether ID pin is handled externally.
411 * Disable CONIDSTSCHNG controller interrupt in such
412 * case.
413 * 0 - No (default)
414 * 1 - Yes
285046aa
GH		 415 * @hibernation: Specifies whether the controller support hibernation.
416 * If hibernation is enabled, the controller will enter
417 * hibernation in both peripheral and host mode when
418 * needed.
419 * 0 - No (default)
420 * 1 - Yes
9962b62f 421 * @g_dma: Enables gadget dma usage (default: autodetect).
dec4b556 422 * @g_dma_desc: Enables gadget descriptor DMA (default: autodetect).
05ee799f
JY		 423 * @g_rx_fifo_size: The periodic rx fifo size for the device, in
424 * DWORDS from 16-32768 (default: 2048 if
425 * possible, otherwise autodetect).
426 * @g_np_tx_fifo_size: The non-periodic tx fifo size for the device in
427 * DWORDS from 16-32768 (default: 1024 if
428 * possible, otherwise autodetect).
429 * @g_tx_fifo_size: An array of TX fifo sizes in dedicated fifo
430 * mode. Each value corresponds to one EP
431 * starting from EP1 (max 15 values). Sizes are
432 * in DWORDS with possible values from from
433 * 16-32768 (default: 256, 256, 256, 256, 768,
434 * 768, 768, 768, 0, 0, 0, 0, 0, 0, 0).
56f5b1cf
PZ		 435 *
436 * The following parameters may be specified when starting the module. These
91121c10
MK		 437 * parameters define how the DWC_otg controller should be configured. A
438 * value of -1 (or any other out of range value) for any parameter means
439 * to read the value from hardware (if possible) or use the builtin
440 * default described above.
56f5b1cf
PZ		 441 */
442struct dwc2_core_params {
8284f93b
MK		 443 /*
444 * Don't add any non-int members here, this will break
445 * dwc2_set_all_params!
446 */
56f5b1cf 447 int otg_cap;
c1d286cf
JY		 448#define DWC2_CAP_PARAM_HNP_SRP_CAPABLE 0
449#define DWC2_CAP_PARAM_SRP_ONLY_CAPABLE 1
450#define DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE 2
451
56f5b1cf 452 int otg_ver;
56f5b1cf 453 int dma_desc_enable;
fbb9e22b 454 int dma_desc_fs_enable;
56f5b1cf 455 int speed;
c1d286cf
JY		 456#define DWC2_SPEED_PARAM_HIGH 0
457#define DWC2_SPEED_PARAM_FULL 1
458
56f5b1cf
PZ		 459 int enable_dynamic_fifo;
460 int en_multiple_tx_fifo;
461 int host_rx_fifo_size;
462 int host_nperio_tx_fifo_size;
463 int host_perio_tx_fifo_size;
464 int max_transfer_size;
465 int max_packet_count;
466 int host_channels;
467 int phy_type;
c1d286cf
JY		 468#define DWC2_PHY_TYPE_PARAM_FS 0
469#define DWC2_PHY_TYPE_PARAM_UTMI 1
470#define DWC2_PHY_TYPE_PARAM_ULPI 2
471
56f5b1cf
PZ		 472 int phy_utmi_width;
473 int phy_ulpi_ddr;
474 int phy_ulpi_ext_vbus;
c1d286cf
JY		 475#define DWC2_PHY_ULPI_INTERNAL_VBUS 0
476#define DWC2_PHY_ULPI_EXTERNAL_VBUS 1
477
56f5b1cf
PZ		 478 int i2c_enable;
479 int ulpi_fs_ls;
480 int host_support_fs_ls_low_power;
481 int host_ls_low_power_phy_clk;
c1d286cf
JY		 482#define DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ 0
483#define DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ 1
484
56f5b1cf
PZ		 485 int ts_dline;
486 int reload_ctl;
4d3190e1 487 int ahbcfg;
20f2eb9c 488 int uframe_sched;
a6d249d8 489 int external_id_pin_ctl;
285046aa 490 int hibernation;
05ee799f
JY		 491
492 /*
493 * The following parameters are *only* set via device
494 * properties and cannot be set directly in this structure.
495 */
6b66ce51
JY		 496
497 /* Host parameters */
498 bool host_dma;
499
500 /* Gadget parameters */
05ee799f 501 bool g_dma;
dec4b556 502 bool g_dma_desc;
05ee799f
JY		 503 u16 g_rx_fifo_size;
504 u16 g_np_tx_fifo_size;
505 u32 g_tx_fifo_size[MAX_EPS_CHANNELS];
56f5b1cf
PZ		 506};
507
9badec2f
MK		 508/**
509 * struct dwc2_hw_params - Autodetected parameters.
510 *
511 * These parameters are the various parameters read from hardware
512 * registers during initialization. They typically contain the best
513 * supported or maximum value that can be configured in the
514 * corresponding dwc2_core_params value.
515 *
516 * The values that are not in dwc2_core_params are documented below.
517 *
518 * @op_mode Mode of Operation
519 * 0 - HNP- and SRP-Capable OTG (Host & Device)
520 * 1 - SRP-Capable OTG (Host & Device)
521 * 2 - Non-HNP and Non-SRP Capable OTG (Host & Device)
522 * 3 - SRP-Capable Device
523 * 4 - Non-OTG Device
524 * 5 - SRP-Capable Host
525 * 6 - Non-OTG Host
526 * @arch Architecture
527 * 0 - Slave only
528 * 1 - External DMA
529 * 2 - Internal DMA
530 * @power_optimized Are power optimizations enabled?
531 * @num_dev_ep Number of device endpoints available
532 * @num_dev_perio_in_ep Number of device periodic IN endpoints
997f4f81 533 * available
9badec2f
MK		 534 * @dev_token_q_depth Device Mode IN Token Sequence Learning Queue
535 * Depth
536 * 0 to 30
537 * @host_perio_tx_q_depth
538 * Host Mode Periodic Request Queue Depth
539 * 2, 4 or 8
540 * @nperio_tx_q_depth
541 * Non-Periodic Request Queue Depth
542 * 2, 4 or 8
543 * @hs_phy_type High-speed PHY interface type
544 * 0 - High-speed interface not supported
545 * 1 - UTMI+
546 * 2 - ULPI
547 * 3 - UTMI+ and ULPI
548 * @fs_phy_type Full-speed PHY interface type
549 * 0 - Full speed interface not supported
550 * 1 - Dedicated full speed interface
551 * 2 - FS pins shared with UTMI+ pins
552 * 3 - FS pins shared with ULPI pins
553 * @total_fifo_size: Total internal RAM for FIFOs (bytes)
de4a1931
MK		 554 * @utmi_phy_data_width UTMI+ PHY data width
555 * 0 - 8 bits
556 * 1 - 16 bits
557 * 2 - 8 or 16 bits
9badec2f 558 * @snpsid: Value from SNPSID register
55e1040e 559 * @dev_ep_dirs: Direction of device endpoints (GHWCFG1)
9badec2f
MK		 560 */
561struct dwc2_hw_params {
562 unsigned op_mode:3;
563 unsigned arch:2;
564 unsigned dma_desc_enable:1;
565 unsigned enable_dynamic_fifo:1;
566 unsigned en_multiple_tx_fifo:1;
d1531319 567 unsigned rx_fifo_size:16;
9badec2f 568 unsigned host_nperio_tx_fifo_size:16;
55e1040e 569 unsigned dev_nperio_tx_fifo_size:16;
9badec2f
MK		 570 unsigned host_perio_tx_fifo_size:16;
571 unsigned nperio_tx_q_depth:3;
572 unsigned host_perio_tx_q_depth:3;
573 unsigned dev_token_q_depth:5;
574 unsigned max_transfer_size:26;
575 unsigned max_packet_count:11;
2d115547 576 unsigned host_channels:5;
9badec2f
MK		 577 unsigned hs_phy_type:2;
578 unsigned fs_phy_type:2;
579 unsigned i2c_enable:1;
580 unsigned num_dev_ep:4;
581 unsigned num_dev_perio_in_ep:4;
582 unsigned total_fifo_size:16;
583 unsigned power_optimized:1;
de4a1931 584 unsigned utmi_phy_data_width:2;
9badec2f 585 u32 snpsid;
55e1040e 586 u32 dev_ep_dirs;
9badec2f
MK		 587};
588
3f95001d
MYK		 589/* Size of control and EP0 buffers */
590#define DWC2_CTRL_BUFF_SIZE 8
591
d17ee77b
GH		 592/**
593 * struct dwc2_gregs_backup - Holds global registers state before entering partial
594 * power down
595 * @gotgctl: Backup of GOTGCTL register
596 * @gintmsk: Backup of GINTMSK register
597 * @gahbcfg: Backup of GAHBCFG register
598 * @gusbcfg: Backup of GUSBCFG register
599 * @grxfsiz: Backup of GRXFSIZ register
600 * @gnptxfsiz: Backup of GNPTXFSIZ register
601 * @gi2cctl: Backup of GI2CCTL register
602 * @hptxfsiz: Backup of HPTXFSIZ register
603 * @gdfifocfg: Backup of GDFIFOCFG register
604 * @dtxfsiz: Backup of DTXFSIZ registers for each endpoint
605 * @gpwrdn: Backup of GPWRDN register
606 */
607struct dwc2_gregs_backup {
608 u32 gotgctl;
609 u32 gintmsk;
610 u32 gahbcfg;
611 u32 gusbcfg;
612 u32 grxfsiz;
613 u32 gnptxfsiz;
614 u32 gi2cctl;
615 u32 hptxfsiz;
616 u32 pcgcctl;
617 u32 gdfifocfg;
618 u32 dtxfsiz[MAX_EPS_CHANNELS];
619 u32 gpwrdn;
cc1e204c 620 bool valid;
d17ee77b
GH		 621};
622
623/**
624 * struct dwc2_dregs_backup - Holds device registers state before entering partial
625 * power down
626 * @dcfg: Backup of DCFG register
627 * @dctl: Backup of DCTL register
628 * @daintmsk: Backup of DAINTMSK register
629 * @diepmsk: Backup of DIEPMSK register
630 * @doepmsk: Backup of DOEPMSK register
631 * @diepctl: Backup of DIEPCTL register
632 * @dieptsiz: Backup of DIEPTSIZ register
633 * @diepdma: Backup of DIEPDMA register
634 * @doepctl: Backup of DOEPCTL register
635 * @doeptsiz: Backup of DOEPTSIZ register
636 * @doepdma: Backup of DOEPDMA register
637 */
638struct dwc2_dregs_backup {
639 u32 dcfg;
640 u32 dctl;
641 u32 daintmsk;
642 u32 diepmsk;
643 u32 doepmsk;
644 u32 diepctl[MAX_EPS_CHANNELS];
645 u32 dieptsiz[MAX_EPS_CHANNELS];
646 u32 diepdma[MAX_EPS_CHANNELS];
647 u32 doepctl[MAX_EPS_CHANNELS];
648 u32 doeptsiz[MAX_EPS_CHANNELS];
649 u32 doepdma[MAX_EPS_CHANNELS];
cc1e204c 650 bool valid;
d17ee77b
GH		 651};
652
653/**
654 * struct dwc2_hregs_backup - Holds host registers state before entering partial
655 * power down
656 * @hcfg: Backup of HCFG register
657 * @haintmsk: Backup of HAINTMSK register
658 * @hcintmsk: Backup of HCINTMSK register
659 * @hptr0: Backup of HPTR0 register
660 * @hfir: Backup of HFIR register
661 */
662struct dwc2_hregs_backup {
663 u32 hcfg;
664 u32 haintmsk;
665 u32 hcintmsk[MAX_EPS_CHANNELS];
666 u32 hprt0;
667 u32 hfir;
cc1e204c 668 bool valid;
d17ee77b
GH		 669};
670
9f9f09b0
DA		 671/*
672 * Constants related to high speed periodic scheduling
673 *
674 * We have a periodic schedule that is DWC2_HS_SCHEDULE_UFRAMES long. From a
675 * reservation point of view it's assumed that the schedule goes right back to
676 * the beginning after the end of the schedule.
677 *
678 * What does that mean for scheduling things with a long interval? It means
679 * we'll reserve time for them in every possible microframe that they could
680 * ever be scheduled in. ...but we'll still only actually schedule them as
681 * often as they were requested.
682 *
683 * We keep our schedule in a "bitmap" structure. This simplifies having
684 * to keep track of and merge intervals: we just let the bitmap code do most
685 * of the heavy lifting. In a way scheduling is much like memory allocation.
686 *
687 * We schedule 100us per uframe or 80% of 125us (the maximum amount you're
688 * supposed to schedule for periodic transfers). That's according to spec.
689 *
690 * Note that though we only schedule 80% of each microframe, the bitmap that we
691 * keep the schedule in is tightly packed (AKA it doesn't have 100us worth of
692 * space for each uFrame).
693 *
694 * Requirements:
695 * - DWC2_HS_SCHEDULE_UFRAMES must even divide 0x4000 (HFNUM_MAX_FRNUM + 1)
696 * - DWC2_HS_SCHEDULE_UFRAMES must be 8 times DWC2_LS_SCHEDULE_FRAMES (probably
697 * could be any multiple of 8 times DWC2_LS_SCHEDULE_FRAMES, but there might
698 * be bugs). The 8 comes from the USB spec: number of microframes per frame.
699 */
700#define DWC2_US_PER_UFRAME 125
701#define DWC2_HS_PERIODIC_US_PER_UFRAME 100
702
703#define DWC2_HS_SCHEDULE_UFRAMES 8
704#define DWC2_HS_SCHEDULE_US (DWC2_HS_SCHEDULE_UFRAMES * \
705 DWC2_HS_PERIODIC_US_PER_UFRAME)
706
707/*
708 * Constants related to low speed scheduling
709 *
710 * For high speed we schedule every 1us. For low speed that's a bit overkill,
711 * so we make up a unit called a "slice" that's worth 25us. There are 40
712 * slices in a full frame and we can schedule 36 of those (90%) for periodic
713 * transfers.
714 *
715 * Our low speed schedule can be as short as 1 frame or could be longer. When
716 * we only schedule 1 frame it means that we'll need to reserve a time every
717 * frame even for things that only transfer very rarely, so something that runs
718 * every 2048 frames will get time reserved in every frame. Our low speed
719 * schedule can be longer and we'll be able to handle more overlap, but that
720 * will come at increased memory cost and increased time to schedule.
721 *
722 * Note: one other advantage of a short low speed schedule is that if we mess
723 * up and miss scheduling we can jump in and use any of the slots that we
724 * happened to reserve.
725 *
726 * With 25 us per slice and 1 frame in the schedule, we only need 4 bytes for
727 * the schedule. There will be one schedule per TT.
728 *
729 * Requirements:
730 * - DWC2_US_PER_SLICE must evenly divide DWC2_LS_PERIODIC_US_PER_FRAME.
731 */
732#define DWC2_US_PER_SLICE 25
733#define DWC2_SLICES_PER_UFRAME (DWC2_US_PER_UFRAME / DWC2_US_PER_SLICE)
734
735#define DWC2_ROUND_US_TO_SLICE(us) \
736 (DIV_ROUND_UP((us), DWC2_US_PER_SLICE) * \
737 DWC2_US_PER_SLICE)
738
739#define DWC2_LS_PERIODIC_US_PER_FRAME \
740 900
741#define DWC2_LS_PERIODIC_SLICES_PER_FRAME \
742 (DWC2_LS_PERIODIC_US_PER_FRAME / \
743 DWC2_US_PER_SLICE)
744
745#define DWC2_LS_SCHEDULE_FRAMES 1
746#define DWC2_LS_SCHEDULE_SLICES (DWC2_LS_SCHEDULE_FRAMES * \
747 DWC2_LS_PERIODIC_SLICES_PER_FRAME)
748
56f5b1cf
PZ		 749/**
750 * struct dwc2_hsotg - Holds the state of the driver, including the non-periodic
751 * and periodic schedules
752 *
941fcce4
DN		 753 * These are common for both host and peripheral modes:
754 *
56f5b1cf
PZ		 755 * @dev: The struct device pointer
756 * @regs: Pointer to controller regs
9badec2f
MK		 757 * @hw_params: Parameters that were autodetected from the
758 * hardware registers
941fcce4 759 * @core_params: Parameters that define how the core should be configured
56f5b1cf
PZ		 760 * @op_state: The operational State, during transitions (a_host=>
761 * a_peripheral and b_device=>b_host) this may not match
762 * the core, but allows the software to determine
763 * transitions
c0155b9d
KY		 764 * @dr_mode: Requested mode of operation, one of following:
765 * - USB_DR_MODE_PERIPHERAL
766 * - USB_DR_MODE_HOST
767 * - USB_DR_MODE_OTG
09a75e85
MS		 768 * @hcd_enabled Host mode sub-driver initialization indicator.
769 * @gadget_enabled Peripheral mode sub-driver initialization indicator.
770 * @ll_hw_enabled Status of low-level hardware resources.
771 * @phy: The otg phy transceiver structure for phy control.
772 * @uphy: The otg phy transceiver structure for old USB phy control.
773 * @plat: The platform specific configuration data. This can be removed once
774 * all SoCs support usb transceiver.
775 * @supplies: Definition of USB power supplies
776 * @phyif: PHY interface width
941fcce4
DN		 777 * @lock: Spinlock that protects all the driver data structures
778 * @priv: Stores a pointer to the struct usb_hcd
56f5b1cf
PZ		 779 * @queuing_high_bandwidth: True if multiple packets of a high-bandwidth
780 * transfer are in process of being queued
781 * @srp_success: Stores status of SRP request in the case of a FS PHY
782 * with an I2C interface
783 * @wq_otg: Workqueue object used for handling of some interrupts
784 * @wf_otg: Work object for handling Connector ID Status Change
785 * interrupt
786 * @wkp_timer: Timer object for handling Wakeup Detected interrupt
787 * @lx_state: Lx state of connected device
d17ee77b
GH		 788 * @gregs_backup: Backup of global registers during suspend
789 * @dregs_backup: Backup of device registers during suspend
790 * @hregs_backup: Backup of host registers during suspend
941fcce4
DN		 791 *
792 * These are for host mode:
793 *
56f5b1cf
PZ		 794 * @flags: Flags for handling root port state changes
795 * @non_periodic_sched_inactive: Inactive QHs in the non-periodic schedule.
796 * Transfers associated with these QHs are not currently
797 * assigned to a host channel.
798 * @non_periodic_sched_active: Active QHs in the non-periodic schedule.
799 * Transfers associated with these QHs are currently
800 * assigned to a host channel.
801 * @non_periodic_qh_ptr: Pointer to next QH to process in the active
802 * non-periodic schedule
803 * @periodic_sched_inactive: Inactive QHs in the periodic schedule. This is a
804 * list of QHs for periodic transfers that are _not_
805 * scheduled for the next frame. Each QH in the list has an
806 * interval counter that determines when it needs to be
807 * scheduled for execution. This scheduling mechanism
808 * allows only a simple calculation for periodic bandwidth
809 * used (i.e. must assume that all periodic transfers may
810 * need to execute in the same frame). However, it greatly
811 * simplifies scheduling and should be sufficient for the
812 * vast majority of OTG hosts, which need to connect to a
813 * small number of peripherals at one time. Items move from
814 * this list to periodic_sched_ready when the QH interval
815 * counter is 0 at SOF.
816 * @periodic_sched_ready: List of periodic QHs that are ready for execution in
817 * the next frame, but have not yet been assigned to host
818 * channels. Items move from this list to
819 * periodic_sched_assigned as host channels become
820 * available during the current frame.
821 * @periodic_sched_assigned: List of periodic QHs to be executed in the next
822 * frame that are assigned to host channels. Items move
823 * from this list to periodic_sched_queued as the
824 * transactions for the QH are queued to the DWC_otg
825 * controller.
826 * @periodic_sched_queued: List of periodic QHs that have been queued for
827 * execution. Items move from this list to either
828 * periodic_sched_inactive or periodic_sched_ready when the
829 * channel associated with the transfer is released. If the
830 * interval for the QH is 1, the item moves to
831 * periodic_sched_ready because it must be rescheduled for
832 * the next frame. Otherwise, the item moves to
833 * periodic_sched_inactive.
c9c8ac01 834 * @split_order: List keeping track of channels doing splits, in order.
56f5b1cf
PZ		 835 * @periodic_usecs: Total bandwidth claimed so far for periodic transfers.
836 * This value is in microseconds per (micro)frame. The
837 * assumption is that all periodic transfers may occur in
838 * the same (micro)frame.
9f9f09b0
DA		 839 * @hs_periodic_bitmap: Bitmap used by the microframe scheduler any time the
840 * host is in high speed mode; low speed schedules are
841 * stored elsewhere since we need one per TT.
56f5b1cf
PZ		 842 * @frame_number: Frame number read from the core at SOF. The value ranges
843 * from 0 to HFNUM_MAX_FRNUM.
844 * @periodic_qh_count: Count of periodic QHs, if using several eps. Used for
845 * SOF enable/disable.
846 * @free_hc_list: Free host channels in the controller. This is a list of
847 * struct dwc2_host_chan items.
848 * @periodic_channels: Number of host channels assigned to periodic transfers.
849 * Currently assuming that there is a dedicated host
850 * channel for each periodic transaction and at least one
851 * host channel is available for non-periodic transactions.
852 * @non_periodic_channels: Number of host channels assigned to non-periodic
853 * transfers
20f2eb9c
DC		 854 * @available_host_channels Number of host channels available for the microframe
855 * scheduler to use
56f5b1cf
PZ		 856 * @hc_ptr_array: Array of pointers to the host channel descriptors.
857 * Allows accessing a host channel descriptor given the
858 * host channel number. This is useful in interrupt
859 * handlers.
860 * @status_buf: Buffer used for data received during the status phase of
861 * a control transfer.
862 * @status_buf_dma: DMA address for status_buf
863 * @start_work: Delayed work for handling host A-cable connection
864 * @reset_work: Delayed work for handling a port reset
56f5b1cf
PZ		 865 * @otg_port: OTG port number
866 * @frame_list: Frame list
867 * @frame_list_dma: Frame list DMA address
95105a99 868 * @frame_list_sz: Frame list size
3b5fcc9a
GH		 869 * @desc_gen_cache: Kmem cache for generic descriptors
870 * @desc_hsisoc_cache: Kmem cache for hs isochronous descriptors
941fcce4
DN		 871 *
872 * These are for peripheral mode:
873 *
874 * @driver: USB gadget driver
941fcce4
DN		 875 * @dedicated_fifos: Set if the hardware has dedicated IN-EP fifos.
876 * @num_of_eps: Number of available EPs (excluding EP0)
877 * @debug_root: Root directrory for debugfs.
878 * @debug_file: Main status file for debugfs.
9e14d0a5 879 * @debug_testmode: Testmode status file for debugfs.
941fcce4
DN		 880 * @debug_fifo: FIFO status file for debugfs.
881 * @ep0_reply: Request used for ep0 reply.
882 * @ep0_buff: Buffer for EP0 reply data, if needed.
883 * @ctrl_buff: Buffer for EP0 control requests.
884 * @ctrl_req: Request for EP0 control packets.
fe0b94ab 885 * @ep0_state: EP0 control transfers state
9e14d0a5 886 * @test_mode: USB test mode requested by the host
0f6b80c0
VA		 887 * @setup_desc_dma: EP0 setup stage desc chain DMA address
888 * @setup_desc: EP0 setup stage desc chain pointer
889 * @ctrl_in_desc_dma: EP0 IN data phase desc chain DMA address
890 * @ctrl_in_desc: EP0 IN data phase desc chain pointer
891 * @ctrl_out_desc_dma: EP0 OUT data phase desc chain DMA address
892 * @ctrl_out_desc: EP0 OUT data phase desc chain pointer
941fcce4 893 * @eps: The endpoints being supplied to the gadget framework
56f5b1cf
PZ		 894 */
895struct dwc2_hsotg {
896 struct device *dev;
897 void __iomem *regs;
9badec2f
MK		 898 /** Params detected from hardware */
899 struct dwc2_hw_params hw_params;
900 /** Params to actually use */
bea8e86c 901 struct dwc2_core_params params;
56f5b1cf 902 enum usb_otg_state op_state;
c0155b9d 903 enum usb_dr_mode dr_mode;
e39af88f
MS		 904 unsigned int hcd_enabled:1;
905 unsigned int gadget_enabled:1;
09a75e85 906 unsigned int ll_hw_enabled:1;
56f5b1cf 907
941fcce4
DN		 908 struct phy *phy;
909 struct usb_phy *uphy;
09a75e85 910 struct dwc2_hsotg_plat *plat;
1f91b4cc 911 struct regulator_bulk_data supplies[ARRAY_SIZE(dwc2_hsotg_supply_names)];
09a75e85 912 u32 phyif;
941fcce4
DN		 913
914 spinlock_t lock;
915 void *priv;
916 int irq;
917 struct clk *clk;
83f8da56 918 struct reset_control *reset;
941fcce4 919
56f5b1cf
PZ		 920 unsigned int queuing_high_bandwidth:1;
921 unsigned int srp_success:1;
922
923 struct workqueue_struct *wq_otg;
924 struct work_struct wf_otg;
925 struct timer_list wkp_timer;
926 enum dwc2_lx_state lx_state;
cc1e204c
MYK		 927 struct dwc2_gregs_backup gr_backup;
928 struct dwc2_dregs_backup dr_backup;
929 struct dwc2_hregs_backup hr_backup;
56f5b1cf 930
941fcce4 931 struct dentry *debug_root;
563cf017 932 struct debugfs_regset32 *regset;
941fcce4
DN		 933
934 /* DWC OTG HW Release versions */
935#define DWC2_CORE_REV_2_71a 0x4f54271a
936#define DWC2_CORE_REV_2_90a 0x4f54290a
937#define DWC2_CORE_REV_2_92a 0x4f54292a
938#define DWC2_CORE_REV_2_94a 0x4f54294a
939#define DWC2_CORE_REV_3_00a 0x4f54300a
fef6bc37 940#define DWC2_CORE_REV_3_10a 0x4f54310a
941fcce4
DN		 941
942#if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
56f5b1cf
PZ		 943 union dwc2_hcd_internal_flags {
944 u32 d32;
945 struct {
946 unsigned port_connect_status_change:1;
947 unsigned port_connect_status:1;
948 unsigned port_reset_change:1;
949 unsigned port_enable_change:1;
950 unsigned port_suspend_change:1;
951 unsigned port_over_current_change:1;
952 unsigned port_l1_change:1;
fd4850cf 953 unsigned reserved:25;
56f5b1cf
PZ		 954 } b;
955 } flags;
956
957 struct list_head non_periodic_sched_inactive;
958 struct list_head non_periodic_sched_active;
959 struct list_head *non_periodic_qh_ptr;
960 struct list_head periodic_sched_inactive;
961 struct list_head periodic_sched_ready;
962 struct list_head periodic_sched_assigned;
963 struct list_head periodic_sched_queued;
c9c8ac01 964 struct list_head split_order;
56f5b1cf 965 u16 periodic_usecs;
9f9f09b0
DA		 966 unsigned long hs_periodic_bitmap[
967 DIV_ROUND_UP(DWC2_HS_SCHEDULE_US, BITS_PER_LONG)];
56f5b1cf
PZ		 968 u16 frame_number;
969 u16 periodic_qh_count;
734643df 970 bool bus_suspended;
fbb9e22b 971 bool new_connection;
56f5b1cf 972
483bb254
DA		 973 u16 last_frame_num;
974
56f5b1cf
PZ		 975#ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
976#define FRAME_NUM_ARRAY_SIZE 1000
56f5b1cf
PZ		 977 u16 *frame_num_array;
978 u16 *last_frame_num_array;
979 int frame_num_idx;
980 int dumped_frame_num_array;
981#endif
982
983 struct list_head free_hc_list;
984 int periodic_channels;
985 int non_periodic_channels;
20f2eb9c 986 int available_host_channels;
56f5b1cf
PZ		 987 struct dwc2_host_chan *hc_ptr_array[MAX_EPS_CHANNELS];
988 u8 *status_buf;
989 dma_addr_t status_buf_dma;
990#define DWC2_HCD_STATUS_BUF_SIZE 64
991
992 struct delayed_work start_work;
993 struct delayed_work reset_work;
56f5b1cf
PZ		 994 u8 otg_port;
995 u32 *frame_list;
996 dma_addr_t frame_list_dma;
95105a99 997 u32 frame_list_sz;
3b5fcc9a
GH		 998 struct kmem_cache *desc_gen_cache;
999 struct kmem_cache *desc_hsisoc_cache;
56f5b1cf 1000
56f5b1cf
PZ		 1001#ifdef DEBUG
1002 u32 frrem_samples;
1003 u64 frrem_accum;
1004
1005 u32 hfnum_7_samples_a;
1006 u64 hfnum_7_frrem_accum_a;
1007 u32 hfnum_0_samples_a;
1008 u64 hfnum_0_frrem_accum_a;
1009 u32 hfnum_other_samples_a;
1010 u64 hfnum_other_frrem_accum_a;
1011
1012 u32 hfnum_7_samples_b;
1013 u64 hfnum_7_frrem_accum_b;
1014 u32 hfnum_0_samples_b;
1015 u64 hfnum_0_frrem_accum_b;
1016 u32 hfnum_other_samples_b;
1017 u64 hfnum_other_frrem_accum_b;
1018#endif
941fcce4
DN		 1019#endif /* CONFIG_USB_DWC2_HOST || CONFIG_USB_DWC2_DUAL_ROLE */
1020
1021#if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
1022 /* Gadget structures */
1023 struct usb_gadget_driver *driver;
941fcce4
DN		 1024 int fifo_mem;
1025 unsigned int dedicated_fifos:1;
1026 unsigned char num_of_eps;
1027 u32 fifo_map;
1028
1029 struct usb_request *ep0_reply;
1030 struct usb_request *ctrl_req;
3f95001d
MYK		 1031 void *ep0_buff;
1032 void *ctrl_buff;
fe0b94ab 1033 enum dwc2_ep0_state ep0_state;
9e14d0a5 1034 u8 test_mode;
941fcce4 1035
0f6b80c0
VA		 1036 dma_addr_t setup_desc_dma[2];
1037 struct dwc2_dma_desc *setup_desc[2];
1038 dma_addr_t ctrl_in_desc_dma;
1039 struct dwc2_dma_desc *ctrl_in_desc;
1040 dma_addr_t ctrl_out_desc_dma;
1041 struct dwc2_dma_desc *ctrl_out_desc;
1042
941fcce4 1043 struct usb_gadget gadget;
dc6e69e6 1044 unsigned int enabled:1;
4ace06e8 1045 unsigned int connected:1;
1f91b4cc
FB		 1046 struct dwc2_hsotg_ep *eps_in[MAX_EPS_CHANNELS];
1047 struct dwc2_hsotg_ep *eps_out[MAX_EPS_CHANNELS];
941fcce4 1048#endif /* CONFIG_USB_DWC2_PERIPHERAL || CONFIG_USB_DWC2_DUAL_ROLE */
56f5b1cf
PZ		 1049};
1050
1051/* Reasons for halting a host channel */
1052enum dwc2_halt_status {
1053 DWC2_HC_XFER_NO_HALT_STATUS,
1054 DWC2_HC_XFER_COMPLETE,
1055 DWC2_HC_XFER_URB_COMPLETE,
1056 DWC2_HC_XFER_ACK,
1057 DWC2_HC_XFER_NAK,
1058 DWC2_HC_XFER_NYET,
1059 DWC2_HC_XFER_STALL,
1060 DWC2_HC_XFER_XACT_ERR,
1061 DWC2_HC_XFER_FRAME_OVERRUN,
1062 DWC2_HC_XFER_BABBLE_ERR,
1063 DWC2_HC_XFER_DATA_TOGGLE_ERR,
1064 DWC2_HC_XFER_AHB_ERR,
1065 DWC2_HC_XFER_PERIODIC_INCOMPLETE,
1066 DWC2_HC_XFER_URB_DEQUEUE,
1067};
1068
1069/*
1070 * The following functions support initialization of the core driver component
1071 * and the DWC_otg controller
1072 */
b5d308ab 1073extern int dwc2_core_reset(struct dwc2_hsotg *hsotg);
6d58f346 1074extern int dwc2_core_reset_and_force_dr_mode(struct dwc2_hsotg *hsotg);
d17ee77b
GH		 1075extern int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg);
1076extern int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, bool restore);
56f5b1cf 1077
323230ef
JY		 1078bool dwc2_force_mode_if_needed(struct dwc2_hsotg *hsotg, bool host);
1079void dwc2_clear_force_mode(struct dwc2_hsotg *hsotg);
09c96980
JY		 1080void dwc2_force_dr_mode(struct dwc2_hsotg *hsotg);
1081
057715f2 1082extern bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg);
56f5b1cf
PZ		 1083
1084/*
1085 * Common core Functions.
1086 * The following functions support managing the DWC_otg controller in either
1087 * device or host mode.
1088 */
1089extern void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes);
1090extern void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num);
1091extern void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg);
1092
56f5b1cf
PZ		 1093extern void dwc2_enable_global_interrupts(struct dwc2_hsotg *hcd);
1094extern void dwc2_disable_global_interrupts(struct dwc2_hsotg *hcd);
1095
1096/* This function should be called on every hardware interrupt. */
1097extern irqreturn_t dwc2_handle_common_intr(int irq, void *dev);
1098
323230ef
JY		 1099/* The device ID match table */
1100extern const struct of_device_id dwc2_of_match_table[];
1101
09a75e85
MS		 1102extern int dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg);
1103extern int dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg);
ecb176c6 1104
334bbd4e 1105/* Parameters */
c1d286cf 1106int dwc2_get_hwparams(struct dwc2_hsotg *hsotg);
334bbd4e
JY		 1107int dwc2_init_params(struct dwc2_hsotg *hsotg);
1108
6bea9620
JY		 1109/*
1110 * The following functions check the controller's OTG operation mode
1111 * capability (GHWCFG2.OTG_MODE).
1112 *
1113 * These functions can be used before the internal hsotg->hw_params
1114 * are read in and cached so they always read directly from the
1115 * GHWCFG2 register.
1116 */
1117unsigned dwc2_op_mode(struct dwc2_hsotg *hsotg);
1118bool dwc2_hw_is_otg(struct dwc2_hsotg *hsotg);
1119bool dwc2_hw_is_host(struct dwc2_hsotg *hsotg);
1120bool dwc2_hw_is_device(struct dwc2_hsotg *hsotg);
1121
1696d5ab
JY		 1122/*
1123 * Returns the mode of operation, host or device
1124 */
1125static inline int dwc2_is_host_mode(struct dwc2_hsotg *hsotg)
1126{
1127 return (dwc2_readl(hsotg->regs + GINTSTS) & GINTSTS_CURMODE_HOST) != 0;
1128}
1129static inline int dwc2_is_device_mode(struct dwc2_hsotg *hsotg)
1130{
1131 return (dwc2_readl(hsotg->regs + GINTSTS) & GINTSTS_CURMODE_HOST) == 0;
1132}
1133
56f5b1cf
PZ		 1134/*
1135 * Dump core registers and SPRAM
1136 */
1137extern void dwc2_dump_dev_registers(struct dwc2_hsotg *hsotg);
1138extern void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg);
1139extern void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg);
1140
1141/*
1142 * Return OTG version - either 1.3 or 2.0
1143 */
1144extern u16 dwc2_get_otg_version(struct dwc2_hsotg *hsotg);
1145
117777b2
DN		 1146/* Gadget defines */
1147#if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
1f91b4cc
FB		 1148extern int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg);
1149extern int dwc2_hsotg_suspend(struct dwc2_hsotg *dwc2);
1150extern int dwc2_hsotg_resume(struct dwc2_hsotg *dwc2);
117777b2 1151extern int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq);
1f91b4cc 1152extern void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2,
643cc4de 1153 bool reset);
1f91b4cc
FB		 1154extern void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg);
1155extern void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2);
1156extern int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode);
f81f46e1 1157#define dwc2_is_device_connected(hsotg) (hsotg->connected)
58e52ff6
JY		 1158int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg);
1159int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg);
117777b2 1160#else
1f91b4cc 1161static inline int dwc2_hsotg_remove(struct dwc2_hsotg *dwc2)
117777b2 1162{ return 0; }
1f91b4cc 1163static inline int dwc2_hsotg_suspend(struct dwc2_hsotg *dwc2)
117777b2 1164{ return 0; }
1f91b4cc 1165static inline int dwc2_hsotg_resume(struct dwc2_hsotg *dwc2)
117777b2
DN		 1166{ return 0; }
1167static inline int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq)
1168{ return 0; }
1f91b4cc 1169static inline void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2,
643cc4de 1170 bool reset) {}
1f91b4cc
FB		 1171static inline void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg) {}
1172static inline void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2) {}
1173static inline int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg,
f91eea44
MYK		 1174 int testmode)
1175{ return 0; }
f81f46e1 1176#define dwc2_is_device_connected(hsotg) (0)
58e52ff6
JY		 1177static inline int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg)
1178{ return 0; }
1179static inline int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg)
1180{ return 0; }
117777b2
DN		 1181#endif
1182
1183#if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
1184extern int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg);
fae4e826 1185extern int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg, int us);
6a659531
DA		 1186extern void dwc2_hcd_connect(struct dwc2_hsotg *hsotg);
1187extern void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force);
117777b2 1188extern void dwc2_hcd_start(struct dwc2_hsotg *hsotg);
58e52ff6
JY		 1189int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg);
1190int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg);
117777b2 1191#else
117777b2
DN		 1192static inline int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg)
1193{ return 0; }
fae4e826
DA		 1194static inline int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg,
1195 int us)
1196{ return 0; }
6a659531
DA		 1197static inline void dwc2_hcd_connect(struct dwc2_hsotg *hsotg) {}
1198static inline void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force) {}
117777b2
DN		 1199static inline void dwc2_hcd_start(struct dwc2_hsotg *hsotg) {}
1200static inline void dwc2_hcd_remove(struct dwc2_hsotg *hsotg) {}
ecb176c6 1201static inline int dwc2_hcd_init(struct dwc2_hsotg *hsotg, int irq)
117777b2 1202{ return 0; }
58e52ff6
JY		 1203static inline int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg)
1204{ return 0; }
1205static inline int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg)
1206{ return 0; }
1207
117777b2
DN		 1208#endif
1209
56f5b1cf 1210#endif /* __DWC2_CORE_H__ */
Linux 6.x block layer and io_uring tree(s)