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usb: dwc2: host: fix split transfer schedule sequence
[linux-block.git] / drivers / usb / dwc2 / core.h
CommitLineData
56f5b1cf
PZ		 1/*
2 * core.h - DesignWare HS OTG Controller common declarations
3 *
4 * Copyright (C) 2004-2013 Synopsys, Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions, and the following disclaimer,
11 * without modification.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The names of the above-listed copyright holders may not be used
16 * to endorse or promote products derived from this software without
17 * specific prior written permission.
18 *
19 * ALTERNATIVELY, this software may be distributed under the terms of the
20 * GNU General Public License ("GPL") as published by the Free Software
21 * Foundation; either version 2 of the License, or (at your option) any
22 * later version.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
25 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
28 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
29 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
30 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
31 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
32 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
33 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
34 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 */
36
37#ifndef __DWC2_CORE_H__
38#define __DWC2_CORE_H__
39
f7c0b143
DN		 40#include <linux/phy/phy.h>
41#include <linux/regulator/consumer.h>
42#include <linux/usb/gadget.h>
43#include <linux/usb/otg.h>
56f5b1cf
PZ		 44#include <linux/usb/phy.h>
45#include "hw.h"
46
95c8bc36 47static inline u32 dwc2_readl(const void __iomem *addr)
56f5b1cf 48{
95c8bc36
AS		 49 u32 value = __raw_readl(addr);
50
51 /* In order to preserve endianness __raw_* operation is used. Therefore
52 * a barrier is needed to ensure IO access is not re-ordered across
53 * reads or writes
54 */
55 mb();
56 return value;
56f5b1cf
PZ		 57}
58
95c8bc36
AS		 59static inline void dwc2_writel(u32 value, void __iomem *addr)
60{
61 __raw_writel(value, addr);
62
63 /*
64 * In order to preserve endianness __raw_* operation is used. Therefore
65 * a barrier is needed to ensure IO access is not re-ordered across
66 * reads or writes
67 */
68 mb();
69#ifdef DWC2_LOG_WRITES
70 pr_info("INFO:: wrote %08x to %p\n", value, addr);
56f5b1cf 71#endif
95c8bc36 72}
56f5b1cf
PZ		 73
74/* Maximum number of Endpoints/HostChannels */
75#define MAX_EPS_CHANNELS 16
76
1f91b4cc
FB		 77/* dwc2-hsotg declarations */
78static const char * const dwc2_hsotg_supply_names[] = {
f7c0b143
DN		 79 "vusb_d", /* digital USB supply, 1.2V */
80 "vusb_a", /* analog USB supply, 1.1V */
81};
82
83/*
84 * EP0_MPS_LIMIT
85 *
86 * Unfortunately there seems to be a limit of the amount of data that can
87 * be transferred by IN transactions on EP0. This is either 127 bytes or 3
88 * packets (which practically means 1 packet and 63 bytes of data) when the
89 * MPS is set to 64.
90 *
91 * This means if we are wanting to move >127 bytes of data, we need to
92 * split the transactions up, but just doing one packet at a time does
93 * not work (this may be an implicit DATA0 PID on first packet of the
94 * transaction) and doing 2 packets is outside the controller's limits.
95 *
96 * If we try to lower the MPS size for EP0, then no transfers work properly
97 * for EP0, and the system will fail basic enumeration. As no cause for this
98 * has currently been found, we cannot support any large IN transfers for
99 * EP0.
100 */
101#define EP0_MPS_LIMIT 64
102
941fcce4 103struct dwc2_hsotg;
1f91b4cc 104struct dwc2_hsotg_req;
f7c0b143
DN		 105
106/**
1f91b4cc 107 * struct dwc2_hsotg_ep - driver endpoint definition.
f7c0b143
DN		 108 * @ep: The gadget layer representation of the endpoint.
109 * @name: The driver generated name for the endpoint.
110 * @queue: Queue of requests for this endpoint.
111 * @parent: Reference back to the parent device structure.
112 * @req: The current request that the endpoint is processing. This is
113 * used to indicate an request has been loaded onto the endpoint
114 * and has yet to be completed (maybe due to data move, or simply
115 * awaiting an ack from the core all the data has been completed).
116 * @debugfs: File entry for debugfs file for this endpoint.
117 * @lock: State lock to protect contents of endpoint.
118 * @dir_in: Set to true if this endpoint is of the IN direction, which
119 * means that it is sending data to the Host.
120 * @index: The index for the endpoint registers.
121 * @mc: Multi Count - number of transactions per microframe
122 * @interval - Interval for periodic endpoints
123 * @name: The name array passed to the USB core.
124 * @halted: Set if the endpoint has been halted.
125 * @periodic: Set if this is a periodic ep, such as Interrupt
126 * @isochronous: Set if this is a isochronous ep
8a20fa45 127 * @send_zlp: Set if we need to send a zero-length packet.
f7c0b143
DN		 128 * @total_data: The total number of data bytes done.
129 * @fifo_size: The size of the FIFO (for periodic IN endpoints)
130 * @fifo_load: The amount of data loaded into the FIFO (periodic IN)
131 * @last_load: The offset of data for the last start of request.
132 * @size_loaded: The last loaded size for DxEPTSIZE for periodic IN
133 *
134 * This is the driver's state for each registered enpoint, allowing it
135 * to keep track of transactions that need doing. Each endpoint has a
136 * lock to protect the state, to try and avoid using an overall lock
137 * for the host controller as much as possible.
138 *
139 * For periodic IN endpoints, we have fifo_size and fifo_load to try
140 * and keep track of the amount of data in the periodic FIFO for each
141 * of these as we don't have a status register that tells us how much
142 * is in each of them. (note, this may actually be useless information
143 * as in shared-fifo mode periodic in acts like a single-frame packet
144 * buffer than a fifo)
145 */
1f91b4cc 146struct dwc2_hsotg_ep {
f7c0b143
DN		 147 struct usb_ep ep;
148 struct list_head queue;
941fcce4 149 struct dwc2_hsotg *parent;
1f91b4cc 150 struct dwc2_hsotg_req *req;
f7c0b143
DN		 151 struct dentry *debugfs;
152
153 unsigned long total_data;
154 unsigned int size_loaded;
155 unsigned int last_load;
156 unsigned int fifo_load;
157 unsigned short fifo_size;
b203d0a2 158 unsigned short fifo_index;
f7c0b143
DN		 159
160 unsigned char dir_in;
161 unsigned char index;
162 unsigned char mc;
163 unsigned char interval;
164
165 unsigned int halted:1;
166 unsigned int periodic:1;
167 unsigned int isochronous:1;
8a20fa45 168 unsigned int send_zlp:1;
ec1f9d9f 169 unsigned int has_correct_parity:1;
f7c0b143
DN		 170
171 char name[10];
172};
173
f7c0b143 174/**
1f91b4cc 175 * struct dwc2_hsotg_req - data transfer request
f7c0b143
DN		 176 * @req: The USB gadget request
177 * @queue: The list of requests for the endpoint this is queued for.
7d24c1b5 178 * @saved_req_buf: variable to save req.buf when bounce buffers are used.
f7c0b143 179 */
1f91b4cc 180struct dwc2_hsotg_req {
f7c0b143
DN		 181 struct usb_request req;
182 struct list_head queue;
7d24c1b5 183 void *saved_req_buf;
f7c0b143
DN		 184};
185
941fcce4 186#if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
f7c0b143
DN		 187#define call_gadget(_hs, _entry) \
188do { \
189 if ((_hs)->gadget.speed != USB_SPEED_UNKNOWN && \
190 (_hs)->driver && (_hs)->driver->_entry) { \
191 spin_unlock(&_hs->lock); \
192 (_hs)->driver->_entry(&(_hs)->gadget); \
193 spin_lock(&_hs->lock); \
194 } \
195} while (0)
941fcce4
DN		 196#else
197#define call_gadget(_hs, _entry) do {} while (0)
198#endif
f7c0b143 199
56f5b1cf
PZ		 200struct dwc2_hsotg;
201struct dwc2_host_chan;
202
203/* Device States */
204enum dwc2_lx_state {
205 DWC2_L0, /* On state */
206 DWC2_L1, /* LPM sleep state */
207 DWC2_L2, /* USB suspend state */
208 DWC2_L3, /* Off state */
209};
210
0a176279
GH		 211/*
212 * Gadget periodic tx fifo sizes as used by legacy driver
213 * EP0 is not included
214 */
215#define DWC2_G_P_LEGACY_TX_FIFO_SIZE {256, 256, 256, 256, 768, 768, 768, \
216 768, 0, 0, 0, 0, 0, 0, 0}
217
fe0b94ab
MYK		 218/* Gadget ep0 states */
219enum dwc2_ep0_state {
220 DWC2_EP0_SETUP,
221 DWC2_EP0_DATA_IN,
222 DWC2_EP0_DATA_OUT,
223 DWC2_EP0_STATUS_IN,
224 DWC2_EP0_STATUS_OUT,
225};
226
56f5b1cf
PZ		 227/**
228 * struct dwc2_core_params - Parameters for configuring the core
229 *
91121c10
MK		 230 * @otg_cap: Specifies the OTG capabilities.
231 * 0 - HNP and SRP capable
56f5b1cf 232 * 1 - SRP Only capable
91121c10
MK		 233 * 2 - No HNP/SRP capable (always available)
234 * Defaults to best available option (0, 1, then 2)
725acc86 235 * @otg_ver: OTG version supported
91121c10 236 * 0 - 1.3 (default)
725acc86 237 * 1 - 2.0
56f5b1cf
PZ		 238 * @dma_enable: Specifies whether to use slave or DMA mode for accessing
239 * the data FIFOs. The driver will automatically detect the
240 * value for this parameter if none is specified.
91121c10 241 * 0 - Slave (always available)
56f5b1cf
PZ		 242 * 1 - DMA (default, if available)
243 * @dma_desc_enable: When DMA mode is enabled, specifies whether to use
244 * address DMA mode or descriptor DMA mode for accessing
245 * the data FIFOs. The driver will automatically detect the
246 * value for this if none is specified.
247 * 0 - Address DMA
248 * 1 - Descriptor DMA (default, if available)
fbb9e22b
MYK		 249 * @dma_desc_fs_enable: When DMA mode is enabled, specifies whether to use
250 * address DMA mode or descriptor DMA mode for accessing
251 * the data FIFOs in Full Speed mode only. The driver
252 * will automatically detect the value for this if none is
253 * specified.
254 * 0 - Address DMA
255 * 1 - Descriptor DMA in FS (default, if available)
56f5b1cf
PZ		 256 * @speed: Specifies the maximum speed of operation in host and
257 * device mode. The actual speed depends on the speed of
258 * the attached device and the value of phy_type.
91121c10
MK		 259 * 0 - High Speed
260 * (default when phy_type is UTMI+ or ULPI)
56f5b1cf 261 * 1 - Full Speed
91121c10 262 * (default when phy_type is Full Speed)
56f5b1cf 263 * @enable_dynamic_fifo: 0 - Use coreConsultant-specified FIFO size parameters
91121c10 264 * 1 - Allow dynamic FIFO sizing (default, if available)
725acc86
PZ		 265 * @en_multiple_tx_fifo: Specifies whether dedicated per-endpoint transmit FIFOs
266 * are enabled
56f5b1cf
PZ		 267 * @host_rx_fifo_size: Number of 4-byte words in the Rx FIFO in host mode when
268 * dynamic FIFO sizing is enabled
91121c10
MK		 269 * 16 to 32768
270 * Actual maximum value is autodetected and also
271 * the default.
56f5b1cf
PZ		 272 * @host_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO
273 * in host mode when dynamic FIFO sizing is enabled
91121c10
MK		 274 * 16 to 32768
275 * Actual maximum value is autodetected and also
276 * the default.
56f5b1cf
PZ		 277 * @host_perio_tx_fifo_size: Number of 4-byte words in the periodic Tx FIFO in
278 * host mode when dynamic FIFO sizing is enabled
91121c10
MK		 279 * 16 to 32768
280 * Actual maximum value is autodetected and also
281 * the default.
56f5b1cf 282 * @max_transfer_size: The maximum transfer size supported, in bytes
91121c10
MK		 283 * 2047 to 65,535
284 * Actual maximum value is autodetected and also
285 * the default.
56f5b1cf 286 * @max_packet_count: The maximum number of packets in a transfer
91121c10
MK		 287 * 15 to 511
288 * Actual maximum value is autodetected and also
289 * the default.
56f5b1cf 290 * @host_channels: The number of host channel registers to use
91121c10
MK		 291 * 1 to 16
292 * Actual maximum value is autodetected and also
293 * the default.
56f5b1cf
PZ		 294 * @phy_type: Specifies the type of PHY interface to use. By default,
295 * the driver will automatically detect the phy_type.
91121c10
MK		 296 * 0 - Full Speed Phy
297 * 1 - UTMI+ Phy
298 * 2 - ULPI Phy
299 * Defaults to best available option (2, 1, then 0)
56f5b1cf
PZ		 300 * @phy_utmi_width: Specifies the UTMI+ Data Width (in bits). This parameter
301 * is applicable for a phy_type of UTMI+ or ULPI. (For a
302 * ULPI phy_type, this parameter indicates the data width
303 * between the MAC and the ULPI Wrapper.) Also, this
304 * parameter is applicable only if the OTG_HSPHY_WIDTH cC
305 * parameter was set to "8 and 16 bits", meaning that the
306 * core has been configured to work at either data path
307 * width.
91121c10 308 * 8 or 16 (default 16 if available)
56f5b1cf
PZ		 309 * @phy_ulpi_ddr: Specifies whether the ULPI operates at double or single
310 * data rate. This parameter is only applicable if phy_type
311 * is ULPI.
312 * 0 - single data rate ULPI interface with 8 bit wide
313 * data bus (default)
314 * 1 - double data rate ULPI interface with 4 bit wide
315 * data bus
316 * @phy_ulpi_ext_vbus: For a ULPI phy, specifies whether to use the internal or
317 * external supply to drive the VBus
91121c10
MK		 318 * 0 - Internal supply (default)
319 * 1 - External supply
56f5b1cf
PZ		 320 * @i2c_enable: Specifies whether to use the I2Cinterface for a full
321 * speed PHY. This parameter is only applicable if phy_type
322 * is FS.
323 * 0 - No (default)
324 * 1 - Yes
91121c10
MK		 325 * @ulpi_fs_ls: Make ULPI phy operate in FS/LS mode only
326 * 0 - No (default)
327 * 1 - Yes
725acc86
PZ		 328 * @host_support_fs_ls_low_power: Specifies whether low power mode is supported
329 * when attached to a Full Speed or Low Speed device in
330 * host mode.
331 * 0 - Don't support low power mode (default)
332 * 1 - Support low power mode
333 * @host_ls_low_power_phy_clk: Specifies the PHY clock rate in low power mode
91121c10
MK		 334 * when connected to a Low Speed device in host
335 * mode. This parameter is applicable only if
336 * host_support_fs_ls_low_power is enabled.
725acc86 337 * 0 - 48 MHz
91121c10 338 * (default when phy_type is UTMI+ or ULPI)
725acc86 339 * 1 - 6 MHz
91121c10
MK		 340 * (default when phy_type is Full Speed)
341 * @ts_dline: Enable Term Select Dline pulsing
342 * 0 - No (default)
343 * 1 - Yes
344 * @reload_ctl: Allow dynamic reloading of HFIR register during runtime
345 * 0 - No (default for core < 2.92a)
346 * 1 - Yes (default for core >= 2.92a)
4d3190e1
PZ		 347 * @ahbcfg: This field allows the default value of the GAHBCFG
348 * register to be overridden
91121c10
MK		 349 * -1 - GAHBCFG value will be set to 0x06
350 * (INCR4, default)
4d3190e1
PZ		 351 * all others - GAHBCFG value will be overridden with
352 * this value
91121c10
MK		 353 * Not all bits can be controlled like this, the
354 * bits defined by GAHBCFG_CTRL_MASK are controlled
355 * by the driver and are ignored in this
356 * configuration value.
20f2eb9c 357 * @uframe_sched: True to enable the microframe scheduler
a6d249d8
GH		 358 * @external_id_pin_ctl: Specifies whether ID pin is handled externally.
359 * Disable CONIDSTSCHNG controller interrupt in such
360 * case.
361 * 0 - No (default)
362 * 1 - Yes
285046aa
GH		 363 * @hibernation: Specifies whether the controller support hibernation.
364 * If hibernation is enabled, the controller will enter
365 * hibernation in both peripheral and host mode when
366 * needed.
367 * 0 - No (default)
368 * 1 - Yes
56f5b1cf
PZ		 369 *
370 * The following parameters may be specified when starting the module. These
91121c10
MK		 371 * parameters define how the DWC_otg controller should be configured. A
372 * value of -1 (or any other out of range value) for any parameter means
373 * to read the value from hardware (if possible) or use the builtin
374 * default described above.
56f5b1cf
PZ		 375 */
376struct dwc2_core_params {
8284f93b
MK		 377 /*
378 * Don't add any non-int members here, this will break
379 * dwc2_set_all_params!
380 */
56f5b1cf
PZ		 381 int otg_cap;
382 int otg_ver;
383 int dma_enable;
384 int dma_desc_enable;
fbb9e22b 385 int dma_desc_fs_enable;
56f5b1cf
PZ		 386 int speed;
387 int enable_dynamic_fifo;
388 int en_multiple_tx_fifo;
389 int host_rx_fifo_size;
390 int host_nperio_tx_fifo_size;
391 int host_perio_tx_fifo_size;
392 int max_transfer_size;
393 int max_packet_count;
394 int host_channels;
395 int phy_type;
396 int phy_utmi_width;
397 int phy_ulpi_ddr;
398 int phy_ulpi_ext_vbus;
399 int i2c_enable;
400 int ulpi_fs_ls;
401 int host_support_fs_ls_low_power;
402 int host_ls_low_power_phy_clk;
403 int ts_dline;
404 int reload_ctl;
4d3190e1 405 int ahbcfg;
20f2eb9c 406 int uframe_sched;
a6d249d8 407 int external_id_pin_ctl;
285046aa 408 int hibernation;
56f5b1cf
PZ		 409};
410
9badec2f
MK		 411/**
412 * struct dwc2_hw_params - Autodetected parameters.
413 *
414 * These parameters are the various parameters read from hardware
415 * registers during initialization. They typically contain the best
416 * supported or maximum value that can be configured in the
417 * corresponding dwc2_core_params value.
418 *
419 * The values that are not in dwc2_core_params are documented below.
420 *
421 * @op_mode Mode of Operation
422 * 0 - HNP- and SRP-Capable OTG (Host & Device)
423 * 1 - SRP-Capable OTG (Host & Device)
424 * 2 - Non-HNP and Non-SRP Capable OTG (Host & Device)
425 * 3 - SRP-Capable Device
426 * 4 - Non-OTG Device
427 * 5 - SRP-Capable Host
428 * 6 - Non-OTG Host
429 * @arch Architecture
430 * 0 - Slave only
431 * 1 - External DMA
432 * 2 - Internal DMA
433 * @power_optimized Are power optimizations enabled?
434 * @num_dev_ep Number of device endpoints available
435 * @num_dev_perio_in_ep Number of device periodic IN endpoints
997f4f81 436 * available
9badec2f
MK		 437 * @dev_token_q_depth Device Mode IN Token Sequence Learning Queue
438 * Depth
439 * 0 to 30
440 * @host_perio_tx_q_depth
441 * Host Mode Periodic Request Queue Depth
442 * 2, 4 or 8
443 * @nperio_tx_q_depth
444 * Non-Periodic Request Queue Depth
445 * 2, 4 or 8
446 * @hs_phy_type High-speed PHY interface type
447 * 0 - High-speed interface not supported
448 * 1 - UTMI+
449 * 2 - ULPI
450 * 3 - UTMI+ and ULPI
451 * @fs_phy_type Full-speed PHY interface type
452 * 0 - Full speed interface not supported
453 * 1 - Dedicated full speed interface
454 * 2 - FS pins shared with UTMI+ pins
455 * 3 - FS pins shared with ULPI pins
456 * @total_fifo_size: Total internal RAM for FIFOs (bytes)
de4a1931
MK		 457 * @utmi_phy_data_width UTMI+ PHY data width
458 * 0 - 8 bits
459 * 1 - 16 bits
460 * 2 - 8 or 16 bits
9badec2f 461 * @snpsid: Value from SNPSID register
55e1040e 462 * @dev_ep_dirs: Direction of device endpoints (GHWCFG1)
9badec2f
MK		 463 */
464struct dwc2_hw_params {
465 unsigned op_mode:3;
466 unsigned arch:2;
467 unsigned dma_desc_enable:1;
fbb9e22b 468 unsigned dma_desc_fs_enable:1;
9badec2f
MK		 469 unsigned enable_dynamic_fifo:1;
470 unsigned en_multiple_tx_fifo:1;
471 unsigned host_rx_fifo_size:16;
472 unsigned host_nperio_tx_fifo_size:16;
55e1040e 473 unsigned dev_nperio_tx_fifo_size:16;
9badec2f
MK		 474 unsigned host_perio_tx_fifo_size:16;
475 unsigned nperio_tx_q_depth:3;
476 unsigned host_perio_tx_q_depth:3;
477 unsigned dev_token_q_depth:5;
478 unsigned max_transfer_size:26;
479 unsigned max_packet_count:11;
2d115547 480 unsigned host_channels:5;
9badec2f
MK		 481 unsigned hs_phy_type:2;
482 unsigned fs_phy_type:2;
483 unsigned i2c_enable:1;
484 unsigned num_dev_ep:4;
485 unsigned num_dev_perio_in_ep:4;
486 unsigned total_fifo_size:16;
487 unsigned power_optimized:1;
de4a1931 488 unsigned utmi_phy_data_width:2;
9badec2f 489 u32 snpsid;
55e1040e 490 u32 dev_ep_dirs;
9badec2f
MK		 491};
492
3f95001d
MYK		 493/* Size of control and EP0 buffers */
494#define DWC2_CTRL_BUFF_SIZE 8
495
d17ee77b
GH		 496/**
497 * struct dwc2_gregs_backup - Holds global registers state before entering partial
498 * power down
499 * @gotgctl: Backup of GOTGCTL register
500 * @gintmsk: Backup of GINTMSK register
501 * @gahbcfg: Backup of GAHBCFG register
502 * @gusbcfg: Backup of GUSBCFG register
503 * @grxfsiz: Backup of GRXFSIZ register
504 * @gnptxfsiz: Backup of GNPTXFSIZ register
505 * @gi2cctl: Backup of GI2CCTL register
506 * @hptxfsiz: Backup of HPTXFSIZ register
507 * @gdfifocfg: Backup of GDFIFOCFG register
508 * @dtxfsiz: Backup of DTXFSIZ registers for each endpoint
509 * @gpwrdn: Backup of GPWRDN register
510 */
511struct dwc2_gregs_backup {
512 u32 gotgctl;
513 u32 gintmsk;
514 u32 gahbcfg;
515 u32 gusbcfg;
516 u32 grxfsiz;
517 u32 gnptxfsiz;
518 u32 gi2cctl;
519 u32 hptxfsiz;
520 u32 pcgcctl;
521 u32 gdfifocfg;
522 u32 dtxfsiz[MAX_EPS_CHANNELS];
523 u32 gpwrdn;
cc1e204c 524 bool valid;
d17ee77b
GH		 525};
526
527/**
528 * struct dwc2_dregs_backup - Holds device registers state before entering partial
529 * power down
530 * @dcfg: Backup of DCFG register
531 * @dctl: Backup of DCTL register
532 * @daintmsk: Backup of DAINTMSK register
533 * @diepmsk: Backup of DIEPMSK register
534 * @doepmsk: Backup of DOEPMSK register
535 * @diepctl: Backup of DIEPCTL register
536 * @dieptsiz: Backup of DIEPTSIZ register
537 * @diepdma: Backup of DIEPDMA register
538 * @doepctl: Backup of DOEPCTL register
539 * @doeptsiz: Backup of DOEPTSIZ register
540 * @doepdma: Backup of DOEPDMA register
541 */
542struct dwc2_dregs_backup {
543 u32 dcfg;
544 u32 dctl;
545 u32 daintmsk;
546 u32 diepmsk;
547 u32 doepmsk;
548 u32 diepctl[MAX_EPS_CHANNELS];
549 u32 dieptsiz[MAX_EPS_CHANNELS];
550 u32 diepdma[MAX_EPS_CHANNELS];
551 u32 doepctl[MAX_EPS_CHANNELS];
552 u32 doeptsiz[MAX_EPS_CHANNELS];
553 u32 doepdma[MAX_EPS_CHANNELS];
cc1e204c 554 bool valid;
d17ee77b
GH		 555};
556
557/**
558 * struct dwc2_hregs_backup - Holds host registers state before entering partial
559 * power down
560 * @hcfg: Backup of HCFG register
561 * @haintmsk: Backup of HAINTMSK register
562 * @hcintmsk: Backup of HCINTMSK register
563 * @hptr0: Backup of HPTR0 register
564 * @hfir: Backup of HFIR register
565 */
566struct dwc2_hregs_backup {
567 u32 hcfg;
568 u32 haintmsk;
569 u32 hcintmsk[MAX_EPS_CHANNELS];
570 u32 hprt0;
571 u32 hfir;
cc1e204c 572 bool valid;
d17ee77b
GH		 573};
574
56f5b1cf
PZ		 575/**
576 * struct dwc2_hsotg - Holds the state of the driver, including the non-periodic
577 * and periodic schedules
578 *
941fcce4
DN		 579 * These are common for both host and peripheral modes:
580 *
56f5b1cf
PZ		 581 * @dev: The struct device pointer
582 * @regs: Pointer to controller regs
9badec2f
MK		 583 * @hw_params: Parameters that were autodetected from the
584 * hardware registers
941fcce4 585 * @core_params: Parameters that define how the core should be configured
56f5b1cf
PZ		 586 * @op_state: The operational State, during transitions (a_host=>
587 * a_peripheral and b_device=>b_host) this may not match
588 * the core, but allows the software to determine
589 * transitions
c0155b9d
KY		 590 * @dr_mode: Requested mode of operation, one of following:
591 * - USB_DR_MODE_PERIPHERAL
592 * - USB_DR_MODE_HOST
593 * - USB_DR_MODE_OTG
09a75e85
MS		 594 * @hcd_enabled Host mode sub-driver initialization indicator.
595 * @gadget_enabled Peripheral mode sub-driver initialization indicator.
596 * @ll_hw_enabled Status of low-level hardware resources.
597 * @phy: The otg phy transceiver structure for phy control.
598 * @uphy: The otg phy transceiver structure for old USB phy control.
599 * @plat: The platform specific configuration data. This can be removed once
600 * all SoCs support usb transceiver.
601 * @supplies: Definition of USB power supplies
602 * @phyif: PHY interface width
941fcce4
DN		 603 * @lock: Spinlock that protects all the driver data structures
604 * @priv: Stores a pointer to the struct usb_hcd
56f5b1cf
PZ		 605 * @queuing_high_bandwidth: True if multiple packets of a high-bandwidth
606 * transfer are in process of being queued
607 * @srp_success: Stores status of SRP request in the case of a FS PHY
608 * with an I2C interface
609 * @wq_otg: Workqueue object used for handling of some interrupts
610 * @wf_otg: Work object for handling Connector ID Status Change
611 * interrupt
612 * @wkp_timer: Timer object for handling Wakeup Detected interrupt
613 * @lx_state: Lx state of connected device
d17ee77b
GH		 614 * @gregs_backup: Backup of global registers during suspend
615 * @dregs_backup: Backup of device registers during suspend
616 * @hregs_backup: Backup of host registers during suspend
941fcce4
DN		 617 *
618 * These are for host mode:
619 *
56f5b1cf
PZ		 620 * @flags: Flags for handling root port state changes
621 * @non_periodic_sched_inactive: Inactive QHs in the non-periodic schedule.
622 * Transfers associated with these QHs are not currently
623 * assigned to a host channel.
624 * @non_periodic_sched_active: Active QHs in the non-periodic schedule.
625 * Transfers associated with these QHs are currently
626 * assigned to a host channel.
627 * @non_periodic_qh_ptr: Pointer to next QH to process in the active
628 * non-periodic schedule
629 * @periodic_sched_inactive: Inactive QHs in the periodic schedule. This is a
630 * list of QHs for periodic transfers that are _not_
631 * scheduled for the next frame. Each QH in the list has an
632 * interval counter that determines when it needs to be
633 * scheduled for execution. This scheduling mechanism
634 * allows only a simple calculation for periodic bandwidth
635 * used (i.e. must assume that all periodic transfers may
636 * need to execute in the same frame). However, it greatly
637 * simplifies scheduling and should be sufficient for the
638 * vast majority of OTG hosts, which need to connect to a
639 * small number of peripherals at one time. Items move from
640 * this list to periodic_sched_ready when the QH interval
641 * counter is 0 at SOF.
642 * @periodic_sched_ready: List of periodic QHs that are ready for execution in
643 * the next frame, but have not yet been assigned to host
644 * channels. Items move from this list to
645 * periodic_sched_assigned as host channels become
646 * available during the current frame.
647 * @periodic_sched_assigned: List of periodic QHs to be executed in the next
648 * frame that are assigned to host channels. Items move
649 * from this list to periodic_sched_queued as the
650 * transactions for the QH are queued to the DWC_otg
651 * controller.
652 * @periodic_sched_queued: List of periodic QHs that have been queued for
653 * execution. Items move from this list to either
654 * periodic_sched_inactive or periodic_sched_ready when the
655 * channel associated with the transfer is released. If the
656 * interval for the QH is 1, the item moves to
657 * periodic_sched_ready because it must be rescheduled for
658 * the next frame. Otherwise, the item moves to
659 * periodic_sched_inactive.
c9c8ac01 660 * @split_order: List keeping track of channels doing splits, in order.
56f5b1cf
PZ		 661 * @periodic_usecs: Total bandwidth claimed so far for periodic transfers.
662 * This value is in microseconds per (micro)frame. The
663 * assumption is that all periodic transfers may occur in
664 * the same (micro)frame.
20f2eb9c 665 * @frame_usecs: Internal variable used by the microframe scheduler
56f5b1cf
PZ		 666 * @frame_number: Frame number read from the core at SOF. The value ranges
667 * from 0 to HFNUM_MAX_FRNUM.
668 * @periodic_qh_count: Count of periodic QHs, if using several eps. Used for
669 * SOF enable/disable.
670 * @free_hc_list: Free host channels in the controller. This is a list of
671 * struct dwc2_host_chan items.
672 * @periodic_channels: Number of host channels assigned to periodic transfers.
673 * Currently assuming that there is a dedicated host
674 * channel for each periodic transaction and at least one
675 * host channel is available for non-periodic transactions.
676 * @non_periodic_channels: Number of host channels assigned to non-periodic
677 * transfers
20f2eb9c
DC		 678 * @available_host_channels Number of host channels available for the microframe
679 * scheduler to use
56f5b1cf
PZ		 680 * @hc_ptr_array: Array of pointers to the host channel descriptors.
681 * Allows accessing a host channel descriptor given the
682 * host channel number. This is useful in interrupt
683 * handlers.
684 * @status_buf: Buffer used for data received during the status phase of
685 * a control transfer.
686 * @status_buf_dma: DMA address for status_buf
687 * @start_work: Delayed work for handling host A-cable connection
688 * @reset_work: Delayed work for handling a port reset
56f5b1cf
PZ		 689 * @otg_port: OTG port number
690 * @frame_list: Frame list
691 * @frame_list_dma: Frame list DMA address
95105a99 692 * @frame_list_sz: Frame list size
3b5fcc9a
GH		 693 * @desc_gen_cache: Kmem cache for generic descriptors
694 * @desc_hsisoc_cache: Kmem cache for hs isochronous descriptors
941fcce4
DN		 695 *
696 * These are for peripheral mode:
697 *
698 * @driver: USB gadget driver
941fcce4
DN		 699 * @dedicated_fifos: Set if the hardware has dedicated IN-EP fifos.
700 * @num_of_eps: Number of available EPs (excluding EP0)
701 * @debug_root: Root directrory for debugfs.
702 * @debug_file: Main status file for debugfs.
9e14d0a5 703 * @debug_testmode: Testmode status file for debugfs.
941fcce4
DN		 704 * @debug_fifo: FIFO status file for debugfs.
705 * @ep0_reply: Request used for ep0 reply.
706 * @ep0_buff: Buffer for EP0 reply data, if needed.
707 * @ctrl_buff: Buffer for EP0 control requests.
708 * @ctrl_req: Request for EP0 control packets.
fe0b94ab 709 * @ep0_state: EP0 control transfers state
9e14d0a5 710 * @test_mode: USB test mode requested by the host
941fcce4 711 * @eps: The endpoints being supplied to the gadget framework
edd74be8 712 * @g_using_dma: Indicate if dma usage is enabled
0a176279
GH		 713 * @g_rx_fifo_sz: Contains rx fifo size value
714 * @g_np_g_tx_fifo_sz: Contains Non-Periodic tx fifo size value
715 * @g_tx_fifo_sz: Contains tx fifo size value per endpoints
56f5b1cf
PZ		 716 */
717struct dwc2_hsotg {
718 struct device *dev;
719 void __iomem *regs;
9badec2f
MK		 720 /** Params detected from hardware */
721 struct dwc2_hw_params hw_params;
722 /** Params to actually use */
56f5b1cf 723 struct dwc2_core_params *core_params;
56f5b1cf 724 enum usb_otg_state op_state;
c0155b9d 725 enum usb_dr_mode dr_mode;
e39af88f
MS		 726 unsigned int hcd_enabled:1;
727 unsigned int gadget_enabled:1;
09a75e85 728 unsigned int ll_hw_enabled:1;
56f5b1cf 729
941fcce4
DN		 730 struct phy *phy;
731 struct usb_phy *uphy;
09a75e85 732 struct dwc2_hsotg_plat *plat;
1f91b4cc 733 struct regulator_bulk_data supplies[ARRAY_SIZE(dwc2_hsotg_supply_names)];
09a75e85 734 u32 phyif;
941fcce4
DN		 735
736 spinlock_t lock;
737 void *priv;
738 int irq;
739 struct clk *clk;
740
56f5b1cf
PZ		 741 unsigned int queuing_high_bandwidth:1;
742 unsigned int srp_success:1;
743
744 struct workqueue_struct *wq_otg;
745 struct work_struct wf_otg;
746 struct timer_list wkp_timer;
747 enum dwc2_lx_state lx_state;
cc1e204c
MYK		 748 struct dwc2_gregs_backup gr_backup;
749 struct dwc2_dregs_backup dr_backup;
750 struct dwc2_hregs_backup hr_backup;
56f5b1cf 751
941fcce4 752 struct dentry *debug_root;
563cf017 753 struct debugfs_regset32 *regset;
941fcce4
DN		 754
755 /* DWC OTG HW Release versions */
756#define DWC2_CORE_REV_2_71a 0x4f54271a
757#define DWC2_CORE_REV_2_90a 0x4f54290a
758#define DWC2_CORE_REV_2_92a 0x4f54292a
759#define DWC2_CORE_REV_2_94a 0x4f54294a
760#define DWC2_CORE_REV_3_00a 0x4f54300a
761
762#if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
56f5b1cf
PZ		 763 union dwc2_hcd_internal_flags {
764 u32 d32;
765 struct {
766 unsigned port_connect_status_change:1;
767 unsigned port_connect_status:1;
768 unsigned port_reset_change:1;
769 unsigned port_enable_change:1;
770 unsigned port_suspend_change:1;
771 unsigned port_over_current_change:1;
772 unsigned port_l1_change:1;
fd4850cf 773 unsigned reserved:25;
56f5b1cf
PZ		 774 } b;
775 } flags;
776
777 struct list_head non_periodic_sched_inactive;
778 struct list_head non_periodic_sched_active;
779 struct list_head *non_periodic_qh_ptr;
780 struct list_head periodic_sched_inactive;
781 struct list_head periodic_sched_ready;
782 struct list_head periodic_sched_assigned;
783 struct list_head periodic_sched_queued;
c9c8ac01 784 struct list_head split_order;
56f5b1cf 785 u16 periodic_usecs;
20f2eb9c 786 u16 frame_usecs[8];
56f5b1cf
PZ		 787 u16 frame_number;
788 u16 periodic_qh_count;
734643df 789 bool bus_suspended;
fbb9e22b 790 bool new_connection;
56f5b1cf
PZ		 791
792#ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
793#define FRAME_NUM_ARRAY_SIZE 1000
794 u16 last_frame_num;
795 u16 *frame_num_array;
796 u16 *last_frame_num_array;
797 int frame_num_idx;
798 int dumped_frame_num_array;
799#endif
800
801 struct list_head free_hc_list;
802 int periodic_channels;
803 int non_periodic_channels;
20f2eb9c 804 int available_host_channels;
56f5b1cf
PZ		 805 struct dwc2_host_chan *hc_ptr_array[MAX_EPS_CHANNELS];
806 u8 *status_buf;
807 dma_addr_t status_buf_dma;
808#define DWC2_HCD_STATUS_BUF_SIZE 64
809
810 struct delayed_work start_work;
811 struct delayed_work reset_work;
56f5b1cf
PZ		 812 u8 otg_port;
813 u32 *frame_list;
814 dma_addr_t frame_list_dma;
95105a99 815 u32 frame_list_sz;
3b5fcc9a
GH		 816 struct kmem_cache *desc_gen_cache;
817 struct kmem_cache *desc_hsisoc_cache;
56f5b1cf 818
56f5b1cf
PZ		 819#ifdef DEBUG
820 u32 frrem_samples;
821 u64 frrem_accum;
822
823 u32 hfnum_7_samples_a;
824 u64 hfnum_7_frrem_accum_a;
825 u32 hfnum_0_samples_a;
826 u64 hfnum_0_frrem_accum_a;
827 u32 hfnum_other_samples_a;
828 u64 hfnum_other_frrem_accum_a;
829
830 u32 hfnum_7_samples_b;
831 u64 hfnum_7_frrem_accum_b;
832 u32 hfnum_0_samples_b;
833 u64 hfnum_0_frrem_accum_b;
834 u32 hfnum_other_samples_b;
835 u64 hfnum_other_frrem_accum_b;
836#endif
941fcce4
DN		 837#endif /* CONFIG_USB_DWC2_HOST || CONFIG_USB_DWC2_DUAL_ROLE */
838
839#if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
840 /* Gadget structures */
841 struct usb_gadget_driver *driver;
941fcce4
DN		 842 int fifo_mem;
843 unsigned int dedicated_fifos:1;
844 unsigned char num_of_eps;
845 u32 fifo_map;
846
847 struct usb_request *ep0_reply;
848 struct usb_request *ctrl_req;
3f95001d
MYK		 849 void *ep0_buff;
850 void *ctrl_buff;
fe0b94ab 851 enum dwc2_ep0_state ep0_state;
9e14d0a5 852 u8 test_mode;
941fcce4
DN		 853
854 struct usb_gadget gadget;
dc6e69e6 855 unsigned int enabled:1;
4ace06e8 856 unsigned int connected:1;
1f91b4cc
FB		 857 struct dwc2_hsotg_ep *eps_in[MAX_EPS_CHANNELS];
858 struct dwc2_hsotg_ep *eps_out[MAX_EPS_CHANNELS];
edd74be8 859 u32 g_using_dma;
0a176279
GH		 860 u32 g_rx_fifo_sz;
861 u32 g_np_g_tx_fifo_sz;
862 u32 g_tx_fifo_sz[MAX_EPS_CHANNELS];
941fcce4 863#endif /* CONFIG_USB_DWC2_PERIPHERAL || CONFIG_USB_DWC2_DUAL_ROLE */
56f5b1cf
PZ		 864};
865
866/* Reasons for halting a host channel */
867enum dwc2_halt_status {
868 DWC2_HC_XFER_NO_HALT_STATUS,
869 DWC2_HC_XFER_COMPLETE,
870 DWC2_HC_XFER_URB_COMPLETE,
871 DWC2_HC_XFER_ACK,
872 DWC2_HC_XFER_NAK,
873 DWC2_HC_XFER_NYET,
874 DWC2_HC_XFER_STALL,
875 DWC2_HC_XFER_XACT_ERR,
876 DWC2_HC_XFER_FRAME_OVERRUN,
877 DWC2_HC_XFER_BABBLE_ERR,
878 DWC2_HC_XFER_DATA_TOGGLE_ERR,
879 DWC2_HC_XFER_AHB_ERR,
880 DWC2_HC_XFER_PERIODIC_INCOMPLETE,
881 DWC2_HC_XFER_URB_DEQUEUE,
882};
883
884/*
885 * The following functions support initialization of the core driver component
886 * and the DWC_otg controller
887 */
b5d308ab 888extern int dwc2_core_reset(struct dwc2_hsotg *hsotg);
6d58f346 889extern int dwc2_core_reset_and_force_dr_mode(struct dwc2_hsotg *hsotg);
56f5b1cf 890extern void dwc2_core_host_init(struct dwc2_hsotg *hsotg);
d17ee77b
GH		 891extern int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg);
892extern int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, bool restore);
56f5b1cf 893
09c96980
JY		 894void dwc2_force_dr_mode(struct dwc2_hsotg *hsotg);
895
56f5b1cf
PZ		 896/*
897 * Host core Functions.
898 * The following functions support managing the DWC_otg controller in host
899 * mode.
900 */
901extern void dwc2_hc_init(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan);
902extern void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan,
903 enum dwc2_halt_status halt_status);
904extern void dwc2_hc_cleanup(struct dwc2_hsotg *hsotg,
905 struct dwc2_host_chan *chan);
906extern void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg,
907 struct dwc2_host_chan *chan);
908extern void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg,
909 struct dwc2_host_chan *chan);
910extern int dwc2_hc_continue_transfer(struct dwc2_hsotg *hsotg,
911 struct dwc2_host_chan *chan);
912extern void dwc2_hc_do_ping(struct dwc2_hsotg *hsotg,
913 struct dwc2_host_chan *chan);
914extern void dwc2_enable_host_interrupts(struct dwc2_hsotg *hsotg);
915extern void dwc2_disable_host_interrupts(struct dwc2_hsotg *hsotg);
916
917extern u32 dwc2_calc_frame_interval(struct dwc2_hsotg *hsotg);
057715f2 918extern bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg);
56f5b1cf
PZ		 919
920/*
921 * Common core Functions.
922 * The following functions support managing the DWC_otg controller in either
923 * device or host mode.
924 */
925extern void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes);
926extern void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num);
927extern void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg);
928
0fe239bc 929extern int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup);
56f5b1cf
PZ		 930extern void dwc2_enable_global_interrupts(struct dwc2_hsotg *hcd);
931extern void dwc2_disable_global_interrupts(struct dwc2_hsotg *hcd);
932
933/* This function should be called on every hardware interrupt. */
934extern irqreturn_t dwc2_handle_common_intr(int irq, void *dev);
935
936/* OTG Core Parameters */
937
938/*
939 * Specifies the OTG capabilities. The driver will automatically
940 * detect the value for this parameter if none is specified.
941 * 0 - HNP and SRP capable (default)
942 * 1 - SRP Only capable
943 * 2 - No HNP/SRP capable
944 */
7218dae7 945extern void dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg, int val);
56f5b1cf
PZ		 946#define DWC2_CAP_PARAM_HNP_SRP_CAPABLE 0
947#define DWC2_CAP_PARAM_SRP_ONLY_CAPABLE 1
948#define DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE 2
949
950/*
951 * Specifies whether to use slave or DMA mode for accessing the data
952 * FIFOs. The driver will automatically detect the value for this
953 * parameter if none is specified.
954 * 0 - Slave
955 * 1 - DMA (default, if available)
956 */
7218dae7 957extern void dwc2_set_param_dma_enable(struct dwc2_hsotg *hsotg, int val);
56f5b1cf
PZ		 958
959/*
960 * When DMA mode is enabled specifies whether to use
961 * address DMA or DMA Descritor mode for accessing the data
962 * FIFOs in device mode. The driver will automatically detect
963 * the value for this parameter if none is specified.
964 * 0 - address DMA
965 * 1 - DMA Descriptor(default, if available)
966 */
7218dae7 967extern void dwc2_set_param_dma_desc_enable(struct dwc2_hsotg *hsotg, int val);
56f5b1cf 968
fbb9e22b
MYK		 969/*
970 * When DMA mode is enabled specifies whether to use
971 * address DMA or DMA Descritor mode with full speed devices
972 * for accessing the data FIFOs in host mode.
973 * 0 - address DMA
974 * 1 - FS DMA Descriptor(default, if available)
975 */
976extern void dwc2_set_param_dma_desc_fs_enable(struct dwc2_hsotg *hsotg,
977 int val);
978
56f5b1cf
PZ		 979/*
980 * Specifies the maximum speed of operation in host and device mode.
981 * The actual speed depends on the speed of the attached device and
982 * the value of phy_type. The actual speed depends on the speed of the
983 * attached device.
984 * 0 - High Speed (default)
985 * 1 - Full Speed
986 */
7218dae7 987extern void dwc2_set_param_speed(struct dwc2_hsotg *hsotg, int val);
56f5b1cf
PZ		 988#define DWC2_SPEED_PARAM_HIGH 0
989#define DWC2_SPEED_PARAM_FULL 1
990
991/*
992 * Specifies whether low power mode is supported when attached
993 * to a Full Speed or Low Speed device in host mode.
994 *
995 * 0 - Don't support low power mode (default)
996 * 1 - Support low power mode
997 */
7218dae7
PZ		 998extern void dwc2_set_param_host_support_fs_ls_low_power(
999 struct dwc2_hsotg *hsotg, int val);
56f5b1cf
PZ		 1000
1001/*
1002 * Specifies the PHY clock rate in low power mode when connected to a
1003 * Low Speed device in host mode. This parameter is applicable only if
1004 * HOST_SUPPORT_FS_LS_LOW_POWER is enabled. If PHY_TYPE is set to FS
1005 * then defaults to 6 MHZ otherwise 48 MHZ.
1006 *
1007 * 0 - 48 MHz
1008 * 1 - 6 MHz
1009 */
7218dae7
PZ		 1010extern void dwc2_set_param_host_ls_low_power_phy_clk(struct dwc2_hsotg *hsotg,
1011 int val);
56f5b1cf
PZ		 1012#define DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ 0
1013#define DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ 1
1014
1015/*
1016 * 0 - Use cC FIFO size parameters
1017 * 1 - Allow dynamic FIFO sizing (default)
1018 */
7218dae7
PZ		 1019extern void dwc2_set_param_enable_dynamic_fifo(struct dwc2_hsotg *hsotg,
1020 int val);
56f5b1cf
PZ		 1021
1022/*
1023 * Number of 4-byte words in the Rx FIFO in host mode when dynamic
1024 * FIFO sizing is enabled.
1025 * 16 to 32768 (default 1024)
1026 */
7218dae7 1027extern void dwc2_set_param_host_rx_fifo_size(struct dwc2_hsotg *hsotg, int val);
56f5b1cf
PZ		 1028
1029/*
1030 * Number of 4-byte words in the non-periodic Tx FIFO in host mode
1031 * when Dynamic FIFO sizing is enabled in the core.
1032 * 16 to 32768 (default 256)
1033 */
7218dae7
PZ		 1034extern void dwc2_set_param_host_nperio_tx_fifo_size(struct dwc2_hsotg *hsotg,
1035 int val);
56f5b1cf
PZ		 1036
1037/*
1038 * Number of 4-byte words in the host periodic Tx FIFO when dynamic
1039 * FIFO sizing is enabled.
1040 * 16 to 32768 (default 256)
1041 */
7218dae7
PZ		 1042extern void dwc2_set_param_host_perio_tx_fifo_size(struct dwc2_hsotg *hsotg,
1043 int val);
56f5b1cf
PZ		 1044
1045/*
1046 * The maximum transfer size supported in bytes.
1047 * 2047 to 65,535 (default 65,535)
1048 */
7218dae7 1049extern void dwc2_set_param_max_transfer_size(struct dwc2_hsotg *hsotg, int val);
56f5b1cf
PZ		 1050
1051/*
1052 * The maximum number of packets in a transfer.
1053 * 15 to 511 (default 511)
1054 */
7218dae7 1055extern void dwc2_set_param_max_packet_count(struct dwc2_hsotg *hsotg, int val);
56f5b1cf
PZ		 1056
1057/*
1058 * The number of host channel registers to use.
1059 * 1 to 16 (default 11)
1060 * Note: The FPGA configuration supports a maximum of 11 host channels.
1061 */
7218dae7 1062extern void dwc2_set_param_host_channels(struct dwc2_hsotg *hsotg, int val);
56f5b1cf
PZ		 1063
1064/*
1065 * Specifies the type of PHY interface to use. By default, the driver
1066 * will automatically detect the phy_type.
1067 *
1068 * 0 - Full Speed PHY
1069 * 1 - UTMI+ (default)
1070 * 2 - ULPI
1071 */
7218dae7 1072extern void dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg, int val);
56f5b1cf
PZ		 1073#define DWC2_PHY_TYPE_PARAM_FS 0
1074#define DWC2_PHY_TYPE_PARAM_UTMI 1
1075#define DWC2_PHY_TYPE_PARAM_ULPI 2
1076
1077/*
1078 * Specifies the UTMI+ Data Width. This parameter is
1079 * applicable for a PHY_TYPE of UTMI+ or ULPI. (For a ULPI
1080 * PHY_TYPE, this parameter indicates the data width between
1081 * the MAC and the ULPI Wrapper.) Also, this parameter is
1082 * applicable only if the OTG_HSPHY_WIDTH cC parameter was set
1083 * to "8 and 16 bits", meaning that the core has been
1084 * configured to work at either data path width.
1085 *
1086 * 8 or 16 bits (default 16)
1087 */
7218dae7 1088extern void dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg, int val);
56f5b1cf
PZ		 1089
1090/*
1091 * Specifies whether the ULPI operates at double or single
1092 * data rate. This parameter is only applicable if PHY_TYPE is
1093 * ULPI.
1094 *
1095 * 0 - single data rate ULPI interface with 8 bit wide data
1096 * bus (default)
1097 * 1 - double data rate ULPI interface with 4 bit wide data
1098 * bus
1099 */
7218dae7 1100extern void dwc2_set_param_phy_ulpi_ddr(struct dwc2_hsotg *hsotg, int val);
56f5b1cf
PZ		 1101
1102/*
1103 * Specifies whether to use the internal or external supply to
1104 * drive the vbus with a ULPI phy.
1105 */
7218dae7 1106extern void dwc2_set_param_phy_ulpi_ext_vbus(struct dwc2_hsotg *hsotg, int val);
56f5b1cf
PZ		 1107#define DWC2_PHY_ULPI_INTERNAL_VBUS 0
1108#define DWC2_PHY_ULPI_EXTERNAL_VBUS 1
1109
1110/*
1111 * Specifies whether to use the I2Cinterface for full speed PHY. This
1112 * parameter is only applicable if PHY_TYPE is FS.
1113 * 0 - No (default)
1114 * 1 - Yes
1115 */
7218dae7 1116extern void dwc2_set_param_i2c_enable(struct dwc2_hsotg *hsotg, int val);
56f5b1cf 1117
7218dae7 1118extern void dwc2_set_param_ulpi_fs_ls(struct dwc2_hsotg *hsotg, int val);
56f5b1cf 1119
7218dae7 1120extern void dwc2_set_param_ts_dline(struct dwc2_hsotg *hsotg, int val);
56f5b1cf
PZ		 1121
1122/*
1123 * Specifies whether dedicated transmit FIFOs are
1124 * enabled for non periodic IN endpoints in device mode
1125 * 0 - No
1126 * 1 - Yes
1127 */
7218dae7
PZ		 1128extern void dwc2_set_param_en_multiple_tx_fifo(struct dwc2_hsotg *hsotg,
1129 int val);
56f5b1cf 1130
7218dae7 1131extern void dwc2_set_param_reload_ctl(struct dwc2_hsotg *hsotg, int val);
56f5b1cf 1132
7218dae7 1133extern void dwc2_set_param_ahbcfg(struct dwc2_hsotg *hsotg, int val);
56f5b1cf 1134
7218dae7 1135extern void dwc2_set_param_otg_ver(struct dwc2_hsotg *hsotg, int val);
56f5b1cf 1136
ecb176c6
MYK		 1137extern void dwc2_set_parameters(struct dwc2_hsotg *hsotg,
1138 const struct dwc2_core_params *params);
1139
1140extern void dwc2_set_all_params(struct dwc2_core_params *params, int value);
1141
1142extern int dwc2_get_hwparams(struct dwc2_hsotg *hsotg);
1143
09a75e85
MS		 1144extern int dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg);
1145extern int dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg);
ecb176c6 1146
6bea9620
JY		 1147/*
1148 * The following functions check the controller's OTG operation mode
1149 * capability (GHWCFG2.OTG_MODE).
1150 *
1151 * These functions can be used before the internal hsotg->hw_params
1152 * are read in and cached so they always read directly from the
1153 * GHWCFG2 register.
1154 */
1155unsigned dwc2_op_mode(struct dwc2_hsotg *hsotg);
1156bool dwc2_hw_is_otg(struct dwc2_hsotg *hsotg);
1157bool dwc2_hw_is_host(struct dwc2_hsotg *hsotg);
1158bool dwc2_hw_is_device(struct dwc2_hsotg *hsotg);
1159
1696d5ab
JY		 1160/*
1161 * Returns the mode of operation, host or device
1162 */
1163static inline int dwc2_is_host_mode(struct dwc2_hsotg *hsotg)
1164{
1165 return (dwc2_readl(hsotg->regs + GINTSTS) & GINTSTS_CURMODE_HOST) != 0;
1166}
1167static inline int dwc2_is_device_mode(struct dwc2_hsotg *hsotg)
1168{
1169 return (dwc2_readl(hsotg->regs + GINTSTS) & GINTSTS_CURMODE_HOST) == 0;
1170}
1171
56f5b1cf
PZ		 1172/*
1173 * Dump core registers and SPRAM
1174 */
1175extern void dwc2_dump_dev_registers(struct dwc2_hsotg *hsotg);
1176extern void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg);
1177extern void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg);
1178
1179/*
1180 * Return OTG version - either 1.3 or 2.0
1181 */
1182extern u16 dwc2_get_otg_version(struct dwc2_hsotg *hsotg);
1183
117777b2
DN		 1184/* Gadget defines */
1185#if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
1f91b4cc
FB		 1186extern int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg);
1187extern int dwc2_hsotg_suspend(struct dwc2_hsotg *dwc2);
1188extern int dwc2_hsotg_resume(struct dwc2_hsotg *dwc2);
117777b2 1189extern int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq);
1f91b4cc 1190extern void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2,
643cc4de 1191 bool reset);
1f91b4cc
FB		 1192extern void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg);
1193extern void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2);
1194extern int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode);
f81f46e1 1195#define dwc2_is_device_connected(hsotg) (hsotg->connected)
117777b2 1196#else
1f91b4cc 1197static inline int dwc2_hsotg_remove(struct dwc2_hsotg *dwc2)
117777b2 1198{ return 0; }
1f91b4cc 1199static inline int dwc2_hsotg_suspend(struct dwc2_hsotg *dwc2)
117777b2 1200{ return 0; }
1f91b4cc 1201static inline int dwc2_hsotg_resume(struct dwc2_hsotg *dwc2)
117777b2
DN		 1202{ return 0; }
1203static inline int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq)
1204{ return 0; }
1f91b4cc 1205static inline void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2,
643cc4de 1206 bool reset) {}
1f91b4cc
FB		 1207static inline void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg) {}
1208static inline void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2) {}
1209static inline int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg,
f91eea44
MYK		 1210 int testmode)
1211{ return 0; }
f81f46e1 1212#define dwc2_is_device_connected(hsotg) (0)
117777b2
DN		 1213#endif
1214
1215#if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
1216extern int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg);
6a659531
DA		 1217extern void dwc2_hcd_connect(struct dwc2_hsotg *hsotg);
1218extern void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force);
117777b2
DN		 1219extern void dwc2_hcd_start(struct dwc2_hsotg *hsotg);
1220#else
117777b2
DN		 1221static inline int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg)
1222{ return 0; }
6a659531
DA		 1223static inline void dwc2_hcd_connect(struct dwc2_hsotg *hsotg) {}
1224static inline void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force) {}
117777b2
DN		 1225static inline void dwc2_hcd_start(struct dwc2_hsotg *hsotg) {}
1226static inline void dwc2_hcd_remove(struct dwc2_hsotg *hsotg) {}
ecb176c6 1227static inline int dwc2_hcd_init(struct dwc2_hsotg *hsotg, int irq)
117777b2
DN		 1228{ return 0; }
1229#endif
1230
56f5b1cf 1231#endif /* __DWC2_CORE_H__ */
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