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56f5b1cf PZ |
1 | /* |
2 | * core.h - DesignWare HS OTG Controller common declarations | |
3 | * | |
4 | * Copyright (C) 2004-2013 Synopsys, Inc. | |
5 | * | |
6 | * Redistribution and use in source and binary forms, with or without | |
7 | * modification, are permitted provided that the following conditions | |
8 | * are met: | |
9 | * 1. Redistributions of source code must retain the above copyright | |
10 | * notice, this list of conditions, and the following disclaimer, | |
11 | * without modification. | |
12 | * 2. Redistributions in binary form must reproduce the above copyright | |
13 | * notice, this list of conditions and the following disclaimer in the | |
14 | * documentation and/or other materials provided with the distribution. | |
15 | * 3. The names of the above-listed copyright holders may not be used | |
16 | * to endorse or promote products derived from this software without | |
17 | * specific prior written permission. | |
18 | * | |
19 | * ALTERNATIVELY, this software may be distributed under the terms of the | |
20 | * GNU General Public License ("GPL") as published by the Free Software | |
21 | * Foundation; either version 2 of the License, or (at your option) any | |
22 | * later version. | |
23 | * | |
24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS | |
25 | * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, | |
26 | * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR | |
27 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR | |
28 | * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, | |
29 | * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, | |
30 | * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR | |
31 | * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF | |
32 | * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING | |
33 | * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS | |
34 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
35 | */ | |
36 | ||
37 | #ifndef __DWC2_CORE_H__ | |
38 | #define __DWC2_CORE_H__ | |
39 | ||
f7c0b143 DN |
40 | #include <linux/phy/phy.h> |
41 | #include <linux/regulator/consumer.h> | |
42 | #include <linux/usb/gadget.h> | |
43 | #include <linux/usb/otg.h> | |
56f5b1cf PZ |
44 | #include <linux/usb/phy.h> |
45 | #include "hw.h" | |
46 | ||
74fc4a75 DA |
47 | /* |
48 | * Suggested defines for tracers: | |
49 | * - no_printk: Disable tracing | |
50 | * - pr_info: Print this info to the console | |
51 | * - trace_printk: Print this info to trace buffer (good for verbose logging) | |
52 | */ | |
53 | ||
54 | #define DWC2_TRACE_SCHEDULER no_printk | |
55 | #define DWC2_TRACE_SCHEDULER_VB no_printk | |
56 | ||
57 | /* Detailed scheduler tracing, but won't overwhelm console */ | |
58 | #define dwc2_sch_dbg(hsotg, fmt, ...) \ | |
59 | DWC2_TRACE_SCHEDULER(pr_fmt("%s: SCH: " fmt), \ | |
60 | dev_name(hsotg->dev), ##__VA_ARGS__) | |
61 | ||
62 | /* Verbose scheduler tracing */ | |
63 | #define dwc2_sch_vdbg(hsotg, fmt, ...) \ | |
64 | DWC2_TRACE_SCHEDULER_VB(pr_fmt("%s: SCH: " fmt), \ | |
65 | dev_name(hsotg->dev), ##__VA_ARGS__) | |
66 | ||
23e34392 AB |
67 | #ifdef CONFIG_MIPS |
68 | /* | |
69 | * There are some MIPS machines that can run in either big-endian | |
70 | * or little-endian mode and that use the dwc2 register without | |
71 | * a byteswap in both ways. | |
72 | * Unlike other architectures, MIPS apparently does not require a | |
73 | * barrier before the __raw_writel() to synchronize with DMA but does | |
74 | * require the barrier after the __raw_writel() to serialize a set of | |
75 | * writes. This set of operations was added specifically for MIPS and | |
76 | * should only be used there. | |
77 | */ | |
95c8bc36 | 78 | static inline u32 dwc2_readl(const void __iomem *addr) |
56f5b1cf | 79 | { |
95c8bc36 AS |
80 | u32 value = __raw_readl(addr); |
81 | ||
82 | /* In order to preserve endianness __raw_* operation is used. Therefore | |
83 | * a barrier is needed to ensure IO access is not re-ordered across | |
84 | * reads or writes | |
85 | */ | |
86 | mb(); | |
87 | return value; | |
56f5b1cf PZ |
88 | } |
89 | ||
95c8bc36 AS |
90 | static inline void dwc2_writel(u32 value, void __iomem *addr) |
91 | { | |
92 | __raw_writel(value, addr); | |
93 | ||
94 | /* | |
95 | * In order to preserve endianness __raw_* operation is used. Therefore | |
96 | * a barrier is needed to ensure IO access is not re-ordered across | |
97 | * reads or writes | |
98 | */ | |
99 | mb(); | |
100 | #ifdef DWC2_LOG_WRITES | |
101 | pr_info("INFO:: wrote %08x to %p\n", value, addr); | |
56f5b1cf | 102 | #endif |
95c8bc36 | 103 | } |
23e34392 AB |
104 | #else |
105 | /* Normal architectures just use readl/write */ | |
106 | static inline u32 dwc2_readl(const void __iomem *addr) | |
107 | { | |
108 | return readl(addr); | |
109 | } | |
110 | ||
111 | static inline void dwc2_writel(u32 value, void __iomem *addr) | |
112 | { | |
113 | writel(value, addr); | |
114 | ||
115 | #ifdef DWC2_LOG_WRITES | |
116 | pr_info("info:: wrote %08x to %p\n", value, addr); | |
117 | #endif | |
118 | } | |
119 | #endif | |
56f5b1cf PZ |
120 | |
121 | /* Maximum number of Endpoints/HostChannels */ | |
122 | #define MAX_EPS_CHANNELS 16 | |
123 | ||
1f91b4cc FB |
124 | /* dwc2-hsotg declarations */ |
125 | static const char * const dwc2_hsotg_supply_names[] = { | |
f7c0b143 DN |
126 | "vusb_d", /* digital USB supply, 1.2V */ |
127 | "vusb_a", /* analog USB supply, 1.1V */ | |
128 | }; | |
129 | ||
130 | /* | |
131 | * EP0_MPS_LIMIT | |
132 | * | |
133 | * Unfortunately there seems to be a limit of the amount of data that can | |
134 | * be transferred by IN transactions on EP0. This is either 127 bytes or 3 | |
135 | * packets (which practically means 1 packet and 63 bytes of data) when the | |
136 | * MPS is set to 64. | |
137 | * | |
138 | * This means if we are wanting to move >127 bytes of data, we need to | |
139 | * split the transactions up, but just doing one packet at a time does | |
140 | * not work (this may be an implicit DATA0 PID on first packet of the | |
141 | * transaction) and doing 2 packets is outside the controller's limits. | |
142 | * | |
143 | * If we try to lower the MPS size for EP0, then no transfers work properly | |
144 | * for EP0, and the system will fail basic enumeration. As no cause for this | |
145 | * has currently been found, we cannot support any large IN transfers for | |
146 | * EP0. | |
147 | */ | |
148 | #define EP0_MPS_LIMIT 64 | |
149 | ||
941fcce4 | 150 | struct dwc2_hsotg; |
1f91b4cc | 151 | struct dwc2_hsotg_req; |
f7c0b143 DN |
152 | |
153 | /** | |
1f91b4cc | 154 | * struct dwc2_hsotg_ep - driver endpoint definition. |
f7c0b143 DN |
155 | * @ep: The gadget layer representation of the endpoint. |
156 | * @name: The driver generated name for the endpoint. | |
157 | * @queue: Queue of requests for this endpoint. | |
158 | * @parent: Reference back to the parent device structure. | |
159 | * @req: The current request that the endpoint is processing. This is | |
160 | * used to indicate an request has been loaded onto the endpoint | |
161 | * and has yet to be completed (maybe due to data move, or simply | |
162 | * awaiting an ack from the core all the data has been completed). | |
163 | * @debugfs: File entry for debugfs file for this endpoint. | |
164 | * @lock: State lock to protect contents of endpoint. | |
165 | * @dir_in: Set to true if this endpoint is of the IN direction, which | |
166 | * means that it is sending data to the Host. | |
167 | * @index: The index for the endpoint registers. | |
168 | * @mc: Multi Count - number of transactions per microframe | |
169 | * @interval - Interval for periodic endpoints | |
170 | * @name: The name array passed to the USB core. | |
171 | * @halted: Set if the endpoint has been halted. | |
172 | * @periodic: Set if this is a periodic ep, such as Interrupt | |
173 | * @isochronous: Set if this is a isochronous ep | |
8a20fa45 | 174 | * @send_zlp: Set if we need to send a zero-length packet. |
f7c0b143 DN |
175 | * @total_data: The total number of data bytes done. |
176 | * @fifo_size: The size of the FIFO (for periodic IN endpoints) | |
177 | * @fifo_load: The amount of data loaded into the FIFO (periodic IN) | |
178 | * @last_load: The offset of data for the last start of request. | |
179 | * @size_loaded: The last loaded size for DxEPTSIZE for periodic IN | |
180 | * | |
181 | * This is the driver's state for each registered enpoint, allowing it | |
182 | * to keep track of transactions that need doing. Each endpoint has a | |
183 | * lock to protect the state, to try and avoid using an overall lock | |
184 | * for the host controller as much as possible. | |
185 | * | |
186 | * For periodic IN endpoints, we have fifo_size and fifo_load to try | |
187 | * and keep track of the amount of data in the periodic FIFO for each | |
188 | * of these as we don't have a status register that tells us how much | |
189 | * is in each of them. (note, this may actually be useless information | |
190 | * as in shared-fifo mode periodic in acts like a single-frame packet | |
191 | * buffer than a fifo) | |
192 | */ | |
1f91b4cc | 193 | struct dwc2_hsotg_ep { |
f7c0b143 DN |
194 | struct usb_ep ep; |
195 | struct list_head queue; | |
941fcce4 | 196 | struct dwc2_hsotg *parent; |
1f91b4cc | 197 | struct dwc2_hsotg_req *req; |
f7c0b143 DN |
198 | struct dentry *debugfs; |
199 | ||
200 | unsigned long total_data; | |
201 | unsigned int size_loaded; | |
202 | unsigned int last_load; | |
203 | unsigned int fifo_load; | |
204 | unsigned short fifo_size; | |
b203d0a2 | 205 | unsigned short fifo_index; |
f7c0b143 DN |
206 | |
207 | unsigned char dir_in; | |
208 | unsigned char index; | |
209 | unsigned char mc; | |
210 | unsigned char interval; | |
211 | ||
212 | unsigned int halted:1; | |
213 | unsigned int periodic:1; | |
214 | unsigned int isochronous:1; | |
8a20fa45 | 215 | unsigned int send_zlp:1; |
ec1f9d9f | 216 | unsigned int has_correct_parity:1; |
f7c0b143 DN |
217 | |
218 | char name[10]; | |
219 | }; | |
220 | ||
f7c0b143 | 221 | /** |
1f91b4cc | 222 | * struct dwc2_hsotg_req - data transfer request |
f7c0b143 DN |
223 | * @req: The USB gadget request |
224 | * @queue: The list of requests for the endpoint this is queued for. | |
7d24c1b5 | 225 | * @saved_req_buf: variable to save req.buf when bounce buffers are used. |
f7c0b143 | 226 | */ |
1f91b4cc | 227 | struct dwc2_hsotg_req { |
f7c0b143 DN |
228 | struct usb_request req; |
229 | struct list_head queue; | |
7d24c1b5 | 230 | void *saved_req_buf; |
f7c0b143 DN |
231 | }; |
232 | ||
941fcce4 | 233 | #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) |
f7c0b143 DN |
234 | #define call_gadget(_hs, _entry) \ |
235 | do { \ | |
236 | if ((_hs)->gadget.speed != USB_SPEED_UNKNOWN && \ | |
237 | (_hs)->driver && (_hs)->driver->_entry) { \ | |
238 | spin_unlock(&_hs->lock); \ | |
239 | (_hs)->driver->_entry(&(_hs)->gadget); \ | |
240 | spin_lock(&_hs->lock); \ | |
241 | } \ | |
242 | } while (0) | |
941fcce4 DN |
243 | #else |
244 | #define call_gadget(_hs, _entry) do {} while (0) | |
245 | #endif | |
f7c0b143 | 246 | |
56f5b1cf PZ |
247 | struct dwc2_hsotg; |
248 | struct dwc2_host_chan; | |
249 | ||
250 | /* Device States */ | |
251 | enum dwc2_lx_state { | |
252 | DWC2_L0, /* On state */ | |
253 | DWC2_L1, /* LPM sleep state */ | |
254 | DWC2_L2, /* USB suspend state */ | |
255 | DWC2_L3, /* Off state */ | |
256 | }; | |
257 | ||
0a176279 GH |
258 | /* |
259 | * Gadget periodic tx fifo sizes as used by legacy driver | |
260 | * EP0 is not included | |
261 | */ | |
262 | #define DWC2_G_P_LEGACY_TX_FIFO_SIZE {256, 256, 256, 256, 768, 768, 768, \ | |
263 | 768, 0, 0, 0, 0, 0, 0, 0} | |
264 | ||
fe0b94ab MYK |
265 | /* Gadget ep0 states */ |
266 | enum dwc2_ep0_state { | |
267 | DWC2_EP0_SETUP, | |
268 | DWC2_EP0_DATA_IN, | |
269 | DWC2_EP0_DATA_OUT, | |
270 | DWC2_EP0_STATUS_IN, | |
271 | DWC2_EP0_STATUS_OUT, | |
272 | }; | |
273 | ||
56f5b1cf PZ |
274 | /** |
275 | * struct dwc2_core_params - Parameters for configuring the core | |
276 | * | |
91121c10 MK |
277 | * @otg_cap: Specifies the OTG capabilities. |
278 | * 0 - HNP and SRP capable | |
56f5b1cf | 279 | * 1 - SRP Only capable |
91121c10 MK |
280 | * 2 - No HNP/SRP capable (always available) |
281 | * Defaults to best available option (0, 1, then 2) | |
725acc86 | 282 | * @otg_ver: OTG version supported |
91121c10 | 283 | * 0 - 1.3 (default) |
725acc86 | 284 | * 1 - 2.0 |
56f5b1cf PZ |
285 | * @dma_enable: Specifies whether to use slave or DMA mode for accessing |
286 | * the data FIFOs. The driver will automatically detect the | |
287 | * value for this parameter if none is specified. | |
91121c10 | 288 | * 0 - Slave (always available) |
56f5b1cf PZ |
289 | * 1 - DMA (default, if available) |
290 | * @dma_desc_enable: When DMA mode is enabled, specifies whether to use | |
291 | * address DMA mode or descriptor DMA mode for accessing | |
292 | * the data FIFOs. The driver will automatically detect the | |
293 | * value for this if none is specified. | |
294 | * 0 - Address DMA | |
295 | * 1 - Descriptor DMA (default, if available) | |
fbb9e22b MYK |
296 | * @dma_desc_fs_enable: When DMA mode is enabled, specifies whether to use |
297 | * address DMA mode or descriptor DMA mode for accessing | |
298 | * the data FIFOs in Full Speed mode only. The driver | |
299 | * will automatically detect the value for this if none is | |
300 | * specified. | |
301 | * 0 - Address DMA | |
302 | * 1 - Descriptor DMA in FS (default, if available) | |
56f5b1cf PZ |
303 | * @speed: Specifies the maximum speed of operation in host and |
304 | * device mode. The actual speed depends on the speed of | |
305 | * the attached device and the value of phy_type. | |
91121c10 MK |
306 | * 0 - High Speed |
307 | * (default when phy_type is UTMI+ or ULPI) | |
56f5b1cf | 308 | * 1 - Full Speed |
91121c10 | 309 | * (default when phy_type is Full Speed) |
56f5b1cf | 310 | * @enable_dynamic_fifo: 0 - Use coreConsultant-specified FIFO size parameters |
91121c10 | 311 | * 1 - Allow dynamic FIFO sizing (default, if available) |
725acc86 PZ |
312 | * @en_multiple_tx_fifo: Specifies whether dedicated per-endpoint transmit FIFOs |
313 | * are enabled | |
56f5b1cf PZ |
314 | * @host_rx_fifo_size: Number of 4-byte words in the Rx FIFO in host mode when |
315 | * dynamic FIFO sizing is enabled | |
91121c10 MK |
316 | * 16 to 32768 |
317 | * Actual maximum value is autodetected and also | |
318 | * the default. | |
56f5b1cf PZ |
319 | * @host_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO |
320 | * in host mode when dynamic FIFO sizing is enabled | |
91121c10 MK |
321 | * 16 to 32768 |
322 | * Actual maximum value is autodetected and also | |
323 | * the default. | |
56f5b1cf PZ |
324 | * @host_perio_tx_fifo_size: Number of 4-byte words in the periodic Tx FIFO in |
325 | * host mode when dynamic FIFO sizing is enabled | |
91121c10 MK |
326 | * 16 to 32768 |
327 | * Actual maximum value is autodetected and also | |
328 | * the default. | |
56f5b1cf | 329 | * @max_transfer_size: The maximum transfer size supported, in bytes |
91121c10 MK |
330 | * 2047 to 65,535 |
331 | * Actual maximum value is autodetected and also | |
332 | * the default. | |
56f5b1cf | 333 | * @max_packet_count: The maximum number of packets in a transfer |
91121c10 MK |
334 | * 15 to 511 |
335 | * Actual maximum value is autodetected and also | |
336 | * the default. | |
56f5b1cf | 337 | * @host_channels: The number of host channel registers to use |
91121c10 MK |
338 | * 1 to 16 |
339 | * Actual maximum value is autodetected and also | |
340 | * the default. | |
56f5b1cf PZ |
341 | * @phy_type: Specifies the type of PHY interface to use. By default, |
342 | * the driver will automatically detect the phy_type. | |
91121c10 MK |
343 | * 0 - Full Speed Phy |
344 | * 1 - UTMI+ Phy | |
345 | * 2 - ULPI Phy | |
346 | * Defaults to best available option (2, 1, then 0) | |
56f5b1cf PZ |
347 | * @phy_utmi_width: Specifies the UTMI+ Data Width (in bits). This parameter |
348 | * is applicable for a phy_type of UTMI+ or ULPI. (For a | |
349 | * ULPI phy_type, this parameter indicates the data width | |
350 | * between the MAC and the ULPI Wrapper.) Also, this | |
351 | * parameter is applicable only if the OTG_HSPHY_WIDTH cC | |
352 | * parameter was set to "8 and 16 bits", meaning that the | |
353 | * core has been configured to work at either data path | |
354 | * width. | |
91121c10 | 355 | * 8 or 16 (default 16 if available) |
56f5b1cf PZ |
356 | * @phy_ulpi_ddr: Specifies whether the ULPI operates at double or single |
357 | * data rate. This parameter is only applicable if phy_type | |
358 | * is ULPI. | |
359 | * 0 - single data rate ULPI interface with 8 bit wide | |
360 | * data bus (default) | |
361 | * 1 - double data rate ULPI interface with 4 bit wide | |
362 | * data bus | |
363 | * @phy_ulpi_ext_vbus: For a ULPI phy, specifies whether to use the internal or | |
364 | * external supply to drive the VBus | |
91121c10 MK |
365 | * 0 - Internal supply (default) |
366 | * 1 - External supply | |
56f5b1cf PZ |
367 | * @i2c_enable: Specifies whether to use the I2Cinterface for a full |
368 | * speed PHY. This parameter is only applicable if phy_type | |
369 | * is FS. | |
370 | * 0 - No (default) | |
371 | * 1 - Yes | |
91121c10 MK |
372 | * @ulpi_fs_ls: Make ULPI phy operate in FS/LS mode only |
373 | * 0 - No (default) | |
374 | * 1 - Yes | |
725acc86 PZ |
375 | * @host_support_fs_ls_low_power: Specifies whether low power mode is supported |
376 | * when attached to a Full Speed or Low Speed device in | |
377 | * host mode. | |
378 | * 0 - Don't support low power mode (default) | |
379 | * 1 - Support low power mode | |
380 | * @host_ls_low_power_phy_clk: Specifies the PHY clock rate in low power mode | |
91121c10 MK |
381 | * when connected to a Low Speed device in host |
382 | * mode. This parameter is applicable only if | |
383 | * host_support_fs_ls_low_power is enabled. | |
725acc86 | 384 | * 0 - 48 MHz |
91121c10 | 385 | * (default when phy_type is UTMI+ or ULPI) |
725acc86 | 386 | * 1 - 6 MHz |
91121c10 MK |
387 | * (default when phy_type is Full Speed) |
388 | * @ts_dline: Enable Term Select Dline pulsing | |
389 | * 0 - No (default) | |
390 | * 1 - Yes | |
391 | * @reload_ctl: Allow dynamic reloading of HFIR register during runtime | |
392 | * 0 - No (default for core < 2.92a) | |
393 | * 1 - Yes (default for core >= 2.92a) | |
4d3190e1 PZ |
394 | * @ahbcfg: This field allows the default value of the GAHBCFG |
395 | * register to be overridden | |
91121c10 MK |
396 | * -1 - GAHBCFG value will be set to 0x06 |
397 | * (INCR4, default) | |
4d3190e1 PZ |
398 | * all others - GAHBCFG value will be overridden with |
399 | * this value | |
91121c10 MK |
400 | * Not all bits can be controlled like this, the |
401 | * bits defined by GAHBCFG_CTRL_MASK are controlled | |
402 | * by the driver and are ignored in this | |
403 | * configuration value. | |
20f2eb9c | 404 | * @uframe_sched: True to enable the microframe scheduler |
a6d249d8 GH |
405 | * @external_id_pin_ctl: Specifies whether ID pin is handled externally. |
406 | * Disable CONIDSTSCHNG controller interrupt in such | |
407 | * case. | |
408 | * 0 - No (default) | |
409 | * 1 - Yes | |
285046aa GH |
410 | * @hibernation: Specifies whether the controller support hibernation. |
411 | * If hibernation is enabled, the controller will enter | |
412 | * hibernation in both peripheral and host mode when | |
413 | * needed. | |
414 | * 0 - No (default) | |
415 | * 1 - Yes | |
56f5b1cf PZ |
416 | * |
417 | * The following parameters may be specified when starting the module. These | |
91121c10 MK |
418 | * parameters define how the DWC_otg controller should be configured. A |
419 | * value of -1 (or any other out of range value) for any parameter means | |
420 | * to read the value from hardware (if possible) or use the builtin | |
421 | * default described above. | |
56f5b1cf PZ |
422 | */ |
423 | struct dwc2_core_params { | |
8284f93b MK |
424 | /* |
425 | * Don't add any non-int members here, this will break | |
426 | * dwc2_set_all_params! | |
427 | */ | |
56f5b1cf PZ |
428 | int otg_cap; |
429 | int otg_ver; | |
430 | int dma_enable; | |
431 | int dma_desc_enable; | |
fbb9e22b | 432 | int dma_desc_fs_enable; |
56f5b1cf PZ |
433 | int speed; |
434 | int enable_dynamic_fifo; | |
435 | int en_multiple_tx_fifo; | |
436 | int host_rx_fifo_size; | |
437 | int host_nperio_tx_fifo_size; | |
438 | int host_perio_tx_fifo_size; | |
439 | int max_transfer_size; | |
440 | int max_packet_count; | |
441 | int host_channels; | |
442 | int phy_type; | |
443 | int phy_utmi_width; | |
444 | int phy_ulpi_ddr; | |
445 | int phy_ulpi_ext_vbus; | |
446 | int i2c_enable; | |
447 | int ulpi_fs_ls; | |
448 | int host_support_fs_ls_low_power; | |
449 | int host_ls_low_power_phy_clk; | |
450 | int ts_dline; | |
451 | int reload_ctl; | |
4d3190e1 | 452 | int ahbcfg; |
20f2eb9c | 453 | int uframe_sched; |
a6d249d8 | 454 | int external_id_pin_ctl; |
285046aa | 455 | int hibernation; |
56f5b1cf PZ |
456 | }; |
457 | ||
9badec2f MK |
458 | /** |
459 | * struct dwc2_hw_params - Autodetected parameters. | |
460 | * | |
461 | * These parameters are the various parameters read from hardware | |
462 | * registers during initialization. They typically contain the best | |
463 | * supported or maximum value that can be configured in the | |
464 | * corresponding dwc2_core_params value. | |
465 | * | |
466 | * The values that are not in dwc2_core_params are documented below. | |
467 | * | |
468 | * @op_mode Mode of Operation | |
469 | * 0 - HNP- and SRP-Capable OTG (Host & Device) | |
470 | * 1 - SRP-Capable OTG (Host & Device) | |
471 | * 2 - Non-HNP and Non-SRP Capable OTG (Host & Device) | |
472 | * 3 - SRP-Capable Device | |
473 | * 4 - Non-OTG Device | |
474 | * 5 - SRP-Capable Host | |
475 | * 6 - Non-OTG Host | |
476 | * @arch Architecture | |
477 | * 0 - Slave only | |
478 | * 1 - External DMA | |
479 | * 2 - Internal DMA | |
480 | * @power_optimized Are power optimizations enabled? | |
481 | * @num_dev_ep Number of device endpoints available | |
482 | * @num_dev_perio_in_ep Number of device periodic IN endpoints | |
997f4f81 | 483 | * available |
9badec2f MK |
484 | * @dev_token_q_depth Device Mode IN Token Sequence Learning Queue |
485 | * Depth | |
486 | * 0 to 30 | |
487 | * @host_perio_tx_q_depth | |
488 | * Host Mode Periodic Request Queue Depth | |
489 | * 2, 4 or 8 | |
490 | * @nperio_tx_q_depth | |
491 | * Non-Periodic Request Queue Depth | |
492 | * 2, 4 or 8 | |
493 | * @hs_phy_type High-speed PHY interface type | |
494 | * 0 - High-speed interface not supported | |
495 | * 1 - UTMI+ | |
496 | * 2 - ULPI | |
497 | * 3 - UTMI+ and ULPI | |
498 | * @fs_phy_type Full-speed PHY interface type | |
499 | * 0 - Full speed interface not supported | |
500 | * 1 - Dedicated full speed interface | |
501 | * 2 - FS pins shared with UTMI+ pins | |
502 | * 3 - FS pins shared with ULPI pins | |
503 | * @total_fifo_size: Total internal RAM for FIFOs (bytes) | |
de4a1931 MK |
504 | * @utmi_phy_data_width UTMI+ PHY data width |
505 | * 0 - 8 bits | |
506 | * 1 - 16 bits | |
507 | * 2 - 8 or 16 bits | |
9badec2f | 508 | * @snpsid: Value from SNPSID register |
55e1040e | 509 | * @dev_ep_dirs: Direction of device endpoints (GHWCFG1) |
9badec2f MK |
510 | */ |
511 | struct dwc2_hw_params { | |
512 | unsigned op_mode:3; | |
513 | unsigned arch:2; | |
514 | unsigned dma_desc_enable:1; | |
fbb9e22b | 515 | unsigned dma_desc_fs_enable:1; |
9badec2f MK |
516 | unsigned enable_dynamic_fifo:1; |
517 | unsigned en_multiple_tx_fifo:1; | |
518 | unsigned host_rx_fifo_size:16; | |
519 | unsigned host_nperio_tx_fifo_size:16; | |
55e1040e | 520 | unsigned dev_nperio_tx_fifo_size:16; |
9badec2f MK |
521 | unsigned host_perio_tx_fifo_size:16; |
522 | unsigned nperio_tx_q_depth:3; | |
523 | unsigned host_perio_tx_q_depth:3; | |
524 | unsigned dev_token_q_depth:5; | |
525 | unsigned max_transfer_size:26; | |
526 | unsigned max_packet_count:11; | |
2d115547 | 527 | unsigned host_channels:5; |
9badec2f MK |
528 | unsigned hs_phy_type:2; |
529 | unsigned fs_phy_type:2; | |
530 | unsigned i2c_enable:1; | |
531 | unsigned num_dev_ep:4; | |
532 | unsigned num_dev_perio_in_ep:4; | |
533 | unsigned total_fifo_size:16; | |
534 | unsigned power_optimized:1; | |
de4a1931 | 535 | unsigned utmi_phy_data_width:2; |
9badec2f | 536 | u32 snpsid; |
55e1040e | 537 | u32 dev_ep_dirs; |
9badec2f MK |
538 | }; |
539 | ||
3f95001d MYK |
540 | /* Size of control and EP0 buffers */ |
541 | #define DWC2_CTRL_BUFF_SIZE 8 | |
542 | ||
d17ee77b GH |
543 | /** |
544 | * struct dwc2_gregs_backup - Holds global registers state before entering partial | |
545 | * power down | |
546 | * @gotgctl: Backup of GOTGCTL register | |
547 | * @gintmsk: Backup of GINTMSK register | |
548 | * @gahbcfg: Backup of GAHBCFG register | |
549 | * @gusbcfg: Backup of GUSBCFG register | |
550 | * @grxfsiz: Backup of GRXFSIZ register | |
551 | * @gnptxfsiz: Backup of GNPTXFSIZ register | |
552 | * @gi2cctl: Backup of GI2CCTL register | |
553 | * @hptxfsiz: Backup of HPTXFSIZ register | |
554 | * @gdfifocfg: Backup of GDFIFOCFG register | |
555 | * @dtxfsiz: Backup of DTXFSIZ registers for each endpoint | |
556 | * @gpwrdn: Backup of GPWRDN register | |
557 | */ | |
558 | struct dwc2_gregs_backup { | |
559 | u32 gotgctl; | |
560 | u32 gintmsk; | |
561 | u32 gahbcfg; | |
562 | u32 gusbcfg; | |
563 | u32 grxfsiz; | |
564 | u32 gnptxfsiz; | |
565 | u32 gi2cctl; | |
566 | u32 hptxfsiz; | |
567 | u32 pcgcctl; | |
568 | u32 gdfifocfg; | |
569 | u32 dtxfsiz[MAX_EPS_CHANNELS]; | |
570 | u32 gpwrdn; | |
cc1e204c | 571 | bool valid; |
d17ee77b GH |
572 | }; |
573 | ||
574 | /** | |
575 | * struct dwc2_dregs_backup - Holds device registers state before entering partial | |
576 | * power down | |
577 | * @dcfg: Backup of DCFG register | |
578 | * @dctl: Backup of DCTL register | |
579 | * @daintmsk: Backup of DAINTMSK register | |
580 | * @diepmsk: Backup of DIEPMSK register | |
581 | * @doepmsk: Backup of DOEPMSK register | |
582 | * @diepctl: Backup of DIEPCTL register | |
583 | * @dieptsiz: Backup of DIEPTSIZ register | |
584 | * @diepdma: Backup of DIEPDMA register | |
585 | * @doepctl: Backup of DOEPCTL register | |
586 | * @doeptsiz: Backup of DOEPTSIZ register | |
587 | * @doepdma: Backup of DOEPDMA register | |
588 | */ | |
589 | struct dwc2_dregs_backup { | |
590 | u32 dcfg; | |
591 | u32 dctl; | |
592 | u32 daintmsk; | |
593 | u32 diepmsk; | |
594 | u32 doepmsk; | |
595 | u32 diepctl[MAX_EPS_CHANNELS]; | |
596 | u32 dieptsiz[MAX_EPS_CHANNELS]; | |
597 | u32 diepdma[MAX_EPS_CHANNELS]; | |
598 | u32 doepctl[MAX_EPS_CHANNELS]; | |
599 | u32 doeptsiz[MAX_EPS_CHANNELS]; | |
600 | u32 doepdma[MAX_EPS_CHANNELS]; | |
cc1e204c | 601 | bool valid; |
d17ee77b GH |
602 | }; |
603 | ||
604 | /** | |
605 | * struct dwc2_hregs_backup - Holds host registers state before entering partial | |
606 | * power down | |
607 | * @hcfg: Backup of HCFG register | |
608 | * @haintmsk: Backup of HAINTMSK register | |
609 | * @hcintmsk: Backup of HCINTMSK register | |
610 | * @hptr0: Backup of HPTR0 register | |
611 | * @hfir: Backup of HFIR register | |
612 | */ | |
613 | struct dwc2_hregs_backup { | |
614 | u32 hcfg; | |
615 | u32 haintmsk; | |
616 | u32 hcintmsk[MAX_EPS_CHANNELS]; | |
617 | u32 hprt0; | |
618 | u32 hfir; | |
cc1e204c | 619 | bool valid; |
d17ee77b GH |
620 | }; |
621 | ||
9f9f09b0 DA |
622 | /* |
623 | * Constants related to high speed periodic scheduling | |
624 | * | |
625 | * We have a periodic schedule that is DWC2_HS_SCHEDULE_UFRAMES long. From a | |
626 | * reservation point of view it's assumed that the schedule goes right back to | |
627 | * the beginning after the end of the schedule. | |
628 | * | |
629 | * What does that mean for scheduling things with a long interval? It means | |
630 | * we'll reserve time for them in every possible microframe that they could | |
631 | * ever be scheduled in. ...but we'll still only actually schedule them as | |
632 | * often as they were requested. | |
633 | * | |
634 | * We keep our schedule in a "bitmap" structure. This simplifies having | |
635 | * to keep track of and merge intervals: we just let the bitmap code do most | |
636 | * of the heavy lifting. In a way scheduling is much like memory allocation. | |
637 | * | |
638 | * We schedule 100us per uframe or 80% of 125us (the maximum amount you're | |
639 | * supposed to schedule for periodic transfers). That's according to spec. | |
640 | * | |
641 | * Note that though we only schedule 80% of each microframe, the bitmap that we | |
642 | * keep the schedule in is tightly packed (AKA it doesn't have 100us worth of | |
643 | * space for each uFrame). | |
644 | * | |
645 | * Requirements: | |
646 | * - DWC2_HS_SCHEDULE_UFRAMES must even divide 0x4000 (HFNUM_MAX_FRNUM + 1) | |
647 | * - DWC2_HS_SCHEDULE_UFRAMES must be 8 times DWC2_LS_SCHEDULE_FRAMES (probably | |
648 | * could be any multiple of 8 times DWC2_LS_SCHEDULE_FRAMES, but there might | |
649 | * be bugs). The 8 comes from the USB spec: number of microframes per frame. | |
650 | */ | |
651 | #define DWC2_US_PER_UFRAME 125 | |
652 | #define DWC2_HS_PERIODIC_US_PER_UFRAME 100 | |
653 | ||
654 | #define DWC2_HS_SCHEDULE_UFRAMES 8 | |
655 | #define DWC2_HS_SCHEDULE_US (DWC2_HS_SCHEDULE_UFRAMES * \ | |
656 | DWC2_HS_PERIODIC_US_PER_UFRAME) | |
657 | ||
658 | /* | |
659 | * Constants related to low speed scheduling | |
660 | * | |
661 | * For high speed we schedule every 1us. For low speed that's a bit overkill, | |
662 | * so we make up a unit called a "slice" that's worth 25us. There are 40 | |
663 | * slices in a full frame and we can schedule 36 of those (90%) for periodic | |
664 | * transfers. | |
665 | * | |
666 | * Our low speed schedule can be as short as 1 frame or could be longer. When | |
667 | * we only schedule 1 frame it means that we'll need to reserve a time every | |
668 | * frame even for things that only transfer very rarely, so something that runs | |
669 | * every 2048 frames will get time reserved in every frame. Our low speed | |
670 | * schedule can be longer and we'll be able to handle more overlap, but that | |
671 | * will come at increased memory cost and increased time to schedule. | |
672 | * | |
673 | * Note: one other advantage of a short low speed schedule is that if we mess | |
674 | * up and miss scheduling we can jump in and use any of the slots that we | |
675 | * happened to reserve. | |
676 | * | |
677 | * With 25 us per slice and 1 frame in the schedule, we only need 4 bytes for | |
678 | * the schedule. There will be one schedule per TT. | |
679 | * | |
680 | * Requirements: | |
681 | * - DWC2_US_PER_SLICE must evenly divide DWC2_LS_PERIODIC_US_PER_FRAME. | |
682 | */ | |
683 | #define DWC2_US_PER_SLICE 25 | |
684 | #define DWC2_SLICES_PER_UFRAME (DWC2_US_PER_UFRAME / DWC2_US_PER_SLICE) | |
685 | ||
686 | #define DWC2_ROUND_US_TO_SLICE(us) \ | |
687 | (DIV_ROUND_UP((us), DWC2_US_PER_SLICE) * \ | |
688 | DWC2_US_PER_SLICE) | |
689 | ||
690 | #define DWC2_LS_PERIODIC_US_PER_FRAME \ | |
691 | 900 | |
692 | #define DWC2_LS_PERIODIC_SLICES_PER_FRAME \ | |
693 | (DWC2_LS_PERIODIC_US_PER_FRAME / \ | |
694 | DWC2_US_PER_SLICE) | |
695 | ||
696 | #define DWC2_LS_SCHEDULE_FRAMES 1 | |
697 | #define DWC2_LS_SCHEDULE_SLICES (DWC2_LS_SCHEDULE_FRAMES * \ | |
698 | DWC2_LS_PERIODIC_SLICES_PER_FRAME) | |
699 | ||
56f5b1cf PZ |
700 | /** |
701 | * struct dwc2_hsotg - Holds the state of the driver, including the non-periodic | |
702 | * and periodic schedules | |
703 | * | |
941fcce4 DN |
704 | * These are common for both host and peripheral modes: |
705 | * | |
56f5b1cf PZ |
706 | * @dev: The struct device pointer |
707 | * @regs: Pointer to controller regs | |
9badec2f MK |
708 | * @hw_params: Parameters that were autodetected from the |
709 | * hardware registers | |
941fcce4 | 710 | * @core_params: Parameters that define how the core should be configured |
56f5b1cf PZ |
711 | * @op_state: The operational State, during transitions (a_host=> |
712 | * a_peripheral and b_device=>b_host) this may not match | |
713 | * the core, but allows the software to determine | |
714 | * transitions | |
c0155b9d KY |
715 | * @dr_mode: Requested mode of operation, one of following: |
716 | * - USB_DR_MODE_PERIPHERAL | |
717 | * - USB_DR_MODE_HOST | |
718 | * - USB_DR_MODE_OTG | |
09a75e85 MS |
719 | * @hcd_enabled Host mode sub-driver initialization indicator. |
720 | * @gadget_enabled Peripheral mode sub-driver initialization indicator. | |
721 | * @ll_hw_enabled Status of low-level hardware resources. | |
722 | * @phy: The otg phy transceiver structure for phy control. | |
723 | * @uphy: The otg phy transceiver structure for old USB phy control. | |
724 | * @plat: The platform specific configuration data. This can be removed once | |
725 | * all SoCs support usb transceiver. | |
726 | * @supplies: Definition of USB power supplies | |
727 | * @phyif: PHY interface width | |
941fcce4 DN |
728 | * @lock: Spinlock that protects all the driver data structures |
729 | * @priv: Stores a pointer to the struct usb_hcd | |
56f5b1cf PZ |
730 | * @queuing_high_bandwidth: True if multiple packets of a high-bandwidth |
731 | * transfer are in process of being queued | |
732 | * @srp_success: Stores status of SRP request in the case of a FS PHY | |
733 | * with an I2C interface | |
734 | * @wq_otg: Workqueue object used for handling of some interrupts | |
735 | * @wf_otg: Work object for handling Connector ID Status Change | |
736 | * interrupt | |
737 | * @wkp_timer: Timer object for handling Wakeup Detected interrupt | |
738 | * @lx_state: Lx state of connected device | |
d17ee77b GH |
739 | * @gregs_backup: Backup of global registers during suspend |
740 | * @dregs_backup: Backup of device registers during suspend | |
741 | * @hregs_backup: Backup of host registers during suspend | |
941fcce4 DN |
742 | * |
743 | * These are for host mode: | |
744 | * | |
56f5b1cf PZ |
745 | * @flags: Flags for handling root port state changes |
746 | * @non_periodic_sched_inactive: Inactive QHs in the non-periodic schedule. | |
747 | * Transfers associated with these QHs are not currently | |
748 | * assigned to a host channel. | |
749 | * @non_periodic_sched_active: Active QHs in the non-periodic schedule. | |
750 | * Transfers associated with these QHs are currently | |
751 | * assigned to a host channel. | |
752 | * @non_periodic_qh_ptr: Pointer to next QH to process in the active | |
753 | * non-periodic schedule | |
754 | * @periodic_sched_inactive: Inactive QHs in the periodic schedule. This is a | |
755 | * list of QHs for periodic transfers that are _not_ | |
756 | * scheduled for the next frame. Each QH in the list has an | |
757 | * interval counter that determines when it needs to be | |
758 | * scheduled for execution. This scheduling mechanism | |
759 | * allows only a simple calculation for periodic bandwidth | |
760 | * used (i.e. must assume that all periodic transfers may | |
761 | * need to execute in the same frame). However, it greatly | |
762 | * simplifies scheduling and should be sufficient for the | |
763 | * vast majority of OTG hosts, which need to connect to a | |
764 | * small number of peripherals at one time. Items move from | |
765 | * this list to periodic_sched_ready when the QH interval | |
766 | * counter is 0 at SOF. | |
767 | * @periodic_sched_ready: List of periodic QHs that are ready for execution in | |
768 | * the next frame, but have not yet been assigned to host | |
769 | * channels. Items move from this list to | |
770 | * periodic_sched_assigned as host channels become | |
771 | * available during the current frame. | |
772 | * @periodic_sched_assigned: List of periodic QHs to be executed in the next | |
773 | * frame that are assigned to host channels. Items move | |
774 | * from this list to periodic_sched_queued as the | |
775 | * transactions for the QH are queued to the DWC_otg | |
776 | * controller. | |
777 | * @periodic_sched_queued: List of periodic QHs that have been queued for | |
778 | * execution. Items move from this list to either | |
779 | * periodic_sched_inactive or periodic_sched_ready when the | |
780 | * channel associated with the transfer is released. If the | |
781 | * interval for the QH is 1, the item moves to | |
782 | * periodic_sched_ready because it must be rescheduled for | |
783 | * the next frame. Otherwise, the item moves to | |
784 | * periodic_sched_inactive. | |
c9c8ac01 | 785 | * @split_order: List keeping track of channels doing splits, in order. |
56f5b1cf PZ |
786 | * @periodic_usecs: Total bandwidth claimed so far for periodic transfers. |
787 | * This value is in microseconds per (micro)frame. The | |
788 | * assumption is that all periodic transfers may occur in | |
789 | * the same (micro)frame. | |
9f9f09b0 DA |
790 | * @hs_periodic_bitmap: Bitmap used by the microframe scheduler any time the |
791 | * host is in high speed mode; low speed schedules are | |
792 | * stored elsewhere since we need one per TT. | |
56f5b1cf PZ |
793 | * @frame_number: Frame number read from the core at SOF. The value ranges |
794 | * from 0 to HFNUM_MAX_FRNUM. | |
795 | * @periodic_qh_count: Count of periodic QHs, if using several eps. Used for | |
796 | * SOF enable/disable. | |
797 | * @free_hc_list: Free host channels in the controller. This is a list of | |
798 | * struct dwc2_host_chan items. | |
799 | * @periodic_channels: Number of host channels assigned to periodic transfers. | |
800 | * Currently assuming that there is a dedicated host | |
801 | * channel for each periodic transaction and at least one | |
802 | * host channel is available for non-periodic transactions. | |
803 | * @non_periodic_channels: Number of host channels assigned to non-periodic | |
804 | * transfers | |
20f2eb9c DC |
805 | * @available_host_channels Number of host channels available for the microframe |
806 | * scheduler to use | |
56f5b1cf PZ |
807 | * @hc_ptr_array: Array of pointers to the host channel descriptors. |
808 | * Allows accessing a host channel descriptor given the | |
809 | * host channel number. This is useful in interrupt | |
810 | * handlers. | |
811 | * @status_buf: Buffer used for data received during the status phase of | |
812 | * a control transfer. | |
813 | * @status_buf_dma: DMA address for status_buf | |
814 | * @start_work: Delayed work for handling host A-cable connection | |
815 | * @reset_work: Delayed work for handling a port reset | |
56f5b1cf PZ |
816 | * @otg_port: OTG port number |
817 | * @frame_list: Frame list | |
818 | * @frame_list_dma: Frame list DMA address | |
95105a99 | 819 | * @frame_list_sz: Frame list size |
3b5fcc9a GH |
820 | * @desc_gen_cache: Kmem cache for generic descriptors |
821 | * @desc_hsisoc_cache: Kmem cache for hs isochronous descriptors | |
941fcce4 DN |
822 | * |
823 | * These are for peripheral mode: | |
824 | * | |
825 | * @driver: USB gadget driver | |
941fcce4 DN |
826 | * @dedicated_fifos: Set if the hardware has dedicated IN-EP fifos. |
827 | * @num_of_eps: Number of available EPs (excluding EP0) | |
828 | * @debug_root: Root directrory for debugfs. | |
829 | * @debug_file: Main status file for debugfs. | |
9e14d0a5 | 830 | * @debug_testmode: Testmode status file for debugfs. |
941fcce4 DN |
831 | * @debug_fifo: FIFO status file for debugfs. |
832 | * @ep0_reply: Request used for ep0 reply. | |
833 | * @ep0_buff: Buffer for EP0 reply data, if needed. | |
834 | * @ctrl_buff: Buffer for EP0 control requests. | |
835 | * @ctrl_req: Request for EP0 control packets. | |
fe0b94ab | 836 | * @ep0_state: EP0 control transfers state |
9e14d0a5 | 837 | * @test_mode: USB test mode requested by the host |
941fcce4 | 838 | * @eps: The endpoints being supplied to the gadget framework |
edd74be8 | 839 | * @g_using_dma: Indicate if dma usage is enabled |
0a176279 GH |
840 | * @g_rx_fifo_sz: Contains rx fifo size value |
841 | * @g_np_g_tx_fifo_sz: Contains Non-Periodic tx fifo size value | |
842 | * @g_tx_fifo_sz: Contains tx fifo size value per endpoints | |
56f5b1cf PZ |
843 | */ |
844 | struct dwc2_hsotg { | |
845 | struct device *dev; | |
846 | void __iomem *regs; | |
9badec2f MK |
847 | /** Params detected from hardware */ |
848 | struct dwc2_hw_params hw_params; | |
849 | /** Params to actually use */ | |
56f5b1cf | 850 | struct dwc2_core_params *core_params; |
56f5b1cf | 851 | enum usb_otg_state op_state; |
c0155b9d | 852 | enum usb_dr_mode dr_mode; |
e39af88f MS |
853 | unsigned int hcd_enabled:1; |
854 | unsigned int gadget_enabled:1; | |
09a75e85 | 855 | unsigned int ll_hw_enabled:1; |
56f5b1cf | 856 | |
941fcce4 DN |
857 | struct phy *phy; |
858 | struct usb_phy *uphy; | |
09a75e85 | 859 | struct dwc2_hsotg_plat *plat; |
1f91b4cc | 860 | struct regulator_bulk_data supplies[ARRAY_SIZE(dwc2_hsotg_supply_names)]; |
09a75e85 | 861 | u32 phyif; |
941fcce4 DN |
862 | |
863 | spinlock_t lock; | |
864 | void *priv; | |
865 | int irq; | |
866 | struct clk *clk; | |
867 | ||
56f5b1cf PZ |
868 | unsigned int queuing_high_bandwidth:1; |
869 | unsigned int srp_success:1; | |
870 | ||
871 | struct workqueue_struct *wq_otg; | |
872 | struct work_struct wf_otg; | |
873 | struct timer_list wkp_timer; | |
874 | enum dwc2_lx_state lx_state; | |
cc1e204c MYK |
875 | struct dwc2_gregs_backup gr_backup; |
876 | struct dwc2_dregs_backup dr_backup; | |
877 | struct dwc2_hregs_backup hr_backup; | |
56f5b1cf | 878 | |
941fcce4 | 879 | struct dentry *debug_root; |
563cf017 | 880 | struct debugfs_regset32 *regset; |
941fcce4 DN |
881 | |
882 | /* DWC OTG HW Release versions */ | |
883 | #define DWC2_CORE_REV_2_71a 0x4f54271a | |
884 | #define DWC2_CORE_REV_2_90a 0x4f54290a | |
885 | #define DWC2_CORE_REV_2_92a 0x4f54292a | |
886 | #define DWC2_CORE_REV_2_94a 0x4f54294a | |
887 | #define DWC2_CORE_REV_3_00a 0x4f54300a | |
888 | ||
889 | #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) | |
56f5b1cf PZ |
890 | union dwc2_hcd_internal_flags { |
891 | u32 d32; | |
892 | struct { | |
893 | unsigned port_connect_status_change:1; | |
894 | unsigned port_connect_status:1; | |
895 | unsigned port_reset_change:1; | |
896 | unsigned port_enable_change:1; | |
897 | unsigned port_suspend_change:1; | |
898 | unsigned port_over_current_change:1; | |
899 | unsigned port_l1_change:1; | |
fd4850cf | 900 | unsigned reserved:25; |
56f5b1cf PZ |
901 | } b; |
902 | } flags; | |
903 | ||
904 | struct list_head non_periodic_sched_inactive; | |
905 | struct list_head non_periodic_sched_active; | |
906 | struct list_head *non_periodic_qh_ptr; | |
907 | struct list_head periodic_sched_inactive; | |
908 | struct list_head periodic_sched_ready; | |
909 | struct list_head periodic_sched_assigned; | |
910 | struct list_head periodic_sched_queued; | |
c9c8ac01 | 911 | struct list_head split_order; |
56f5b1cf | 912 | u16 periodic_usecs; |
9f9f09b0 DA |
913 | unsigned long hs_periodic_bitmap[ |
914 | DIV_ROUND_UP(DWC2_HS_SCHEDULE_US, BITS_PER_LONG)]; | |
56f5b1cf PZ |
915 | u16 frame_number; |
916 | u16 periodic_qh_count; | |
734643df | 917 | bool bus_suspended; |
fbb9e22b | 918 | bool new_connection; |
56f5b1cf | 919 | |
483bb254 DA |
920 | u16 last_frame_num; |
921 | ||
56f5b1cf PZ |
922 | #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS |
923 | #define FRAME_NUM_ARRAY_SIZE 1000 | |
56f5b1cf PZ |
924 | u16 *frame_num_array; |
925 | u16 *last_frame_num_array; | |
926 | int frame_num_idx; | |
927 | int dumped_frame_num_array; | |
928 | #endif | |
929 | ||
930 | struct list_head free_hc_list; | |
931 | int periodic_channels; | |
932 | int non_periodic_channels; | |
20f2eb9c | 933 | int available_host_channels; |
56f5b1cf PZ |
934 | struct dwc2_host_chan *hc_ptr_array[MAX_EPS_CHANNELS]; |
935 | u8 *status_buf; | |
936 | dma_addr_t status_buf_dma; | |
937 | #define DWC2_HCD_STATUS_BUF_SIZE 64 | |
938 | ||
939 | struct delayed_work start_work; | |
940 | struct delayed_work reset_work; | |
56f5b1cf PZ |
941 | u8 otg_port; |
942 | u32 *frame_list; | |
943 | dma_addr_t frame_list_dma; | |
95105a99 | 944 | u32 frame_list_sz; |
3b5fcc9a GH |
945 | struct kmem_cache *desc_gen_cache; |
946 | struct kmem_cache *desc_hsisoc_cache; | |
56f5b1cf | 947 | |
56f5b1cf PZ |
948 | #ifdef DEBUG |
949 | u32 frrem_samples; | |
950 | u64 frrem_accum; | |
951 | ||
952 | u32 hfnum_7_samples_a; | |
953 | u64 hfnum_7_frrem_accum_a; | |
954 | u32 hfnum_0_samples_a; | |
955 | u64 hfnum_0_frrem_accum_a; | |
956 | u32 hfnum_other_samples_a; | |
957 | u64 hfnum_other_frrem_accum_a; | |
958 | ||
959 | u32 hfnum_7_samples_b; | |
960 | u64 hfnum_7_frrem_accum_b; | |
961 | u32 hfnum_0_samples_b; | |
962 | u64 hfnum_0_frrem_accum_b; | |
963 | u32 hfnum_other_samples_b; | |
964 | u64 hfnum_other_frrem_accum_b; | |
965 | #endif | |
941fcce4 DN |
966 | #endif /* CONFIG_USB_DWC2_HOST || CONFIG_USB_DWC2_DUAL_ROLE */ |
967 | ||
968 | #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) | |
969 | /* Gadget structures */ | |
970 | struct usb_gadget_driver *driver; | |
941fcce4 DN |
971 | int fifo_mem; |
972 | unsigned int dedicated_fifos:1; | |
973 | unsigned char num_of_eps; | |
974 | u32 fifo_map; | |
975 | ||
976 | struct usb_request *ep0_reply; | |
977 | struct usb_request *ctrl_req; | |
3f95001d MYK |
978 | void *ep0_buff; |
979 | void *ctrl_buff; | |
fe0b94ab | 980 | enum dwc2_ep0_state ep0_state; |
9e14d0a5 | 981 | u8 test_mode; |
941fcce4 DN |
982 | |
983 | struct usb_gadget gadget; | |
dc6e69e6 | 984 | unsigned int enabled:1; |
4ace06e8 | 985 | unsigned int connected:1; |
1f91b4cc FB |
986 | struct dwc2_hsotg_ep *eps_in[MAX_EPS_CHANNELS]; |
987 | struct dwc2_hsotg_ep *eps_out[MAX_EPS_CHANNELS]; | |
edd74be8 | 988 | u32 g_using_dma; |
0a176279 GH |
989 | u32 g_rx_fifo_sz; |
990 | u32 g_np_g_tx_fifo_sz; | |
991 | u32 g_tx_fifo_sz[MAX_EPS_CHANNELS]; | |
941fcce4 | 992 | #endif /* CONFIG_USB_DWC2_PERIPHERAL || CONFIG_USB_DWC2_DUAL_ROLE */ |
56f5b1cf PZ |
993 | }; |
994 | ||
995 | /* Reasons for halting a host channel */ | |
996 | enum dwc2_halt_status { | |
997 | DWC2_HC_XFER_NO_HALT_STATUS, | |
998 | DWC2_HC_XFER_COMPLETE, | |
999 | DWC2_HC_XFER_URB_COMPLETE, | |
1000 | DWC2_HC_XFER_ACK, | |
1001 | DWC2_HC_XFER_NAK, | |
1002 | DWC2_HC_XFER_NYET, | |
1003 | DWC2_HC_XFER_STALL, | |
1004 | DWC2_HC_XFER_XACT_ERR, | |
1005 | DWC2_HC_XFER_FRAME_OVERRUN, | |
1006 | DWC2_HC_XFER_BABBLE_ERR, | |
1007 | DWC2_HC_XFER_DATA_TOGGLE_ERR, | |
1008 | DWC2_HC_XFER_AHB_ERR, | |
1009 | DWC2_HC_XFER_PERIODIC_INCOMPLETE, | |
1010 | DWC2_HC_XFER_URB_DEQUEUE, | |
1011 | }; | |
1012 | ||
1013 | /* | |
1014 | * The following functions support initialization of the core driver component | |
1015 | * and the DWC_otg controller | |
1016 | */ | |
b5d308ab | 1017 | extern int dwc2_core_reset(struct dwc2_hsotg *hsotg); |
6d58f346 | 1018 | extern int dwc2_core_reset_and_force_dr_mode(struct dwc2_hsotg *hsotg); |
d17ee77b GH |
1019 | extern int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg); |
1020 | extern int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, bool restore); | |
56f5b1cf | 1021 | |
09c96980 JY |
1022 | void dwc2_force_dr_mode(struct dwc2_hsotg *hsotg); |
1023 | ||
057715f2 | 1024 | extern bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg); |
56f5b1cf PZ |
1025 | |
1026 | /* | |
1027 | * Common core Functions. | |
1028 | * The following functions support managing the DWC_otg controller in either | |
1029 | * device or host mode. | |
1030 | */ | |
1031 | extern void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes); | |
1032 | extern void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num); | |
1033 | extern void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg); | |
1034 | ||
56f5b1cf PZ |
1035 | extern void dwc2_enable_global_interrupts(struct dwc2_hsotg *hcd); |
1036 | extern void dwc2_disable_global_interrupts(struct dwc2_hsotg *hcd); | |
1037 | ||
1038 | /* This function should be called on every hardware interrupt. */ | |
1039 | extern irqreturn_t dwc2_handle_common_intr(int irq, void *dev); | |
1040 | ||
1041 | /* OTG Core Parameters */ | |
1042 | ||
1043 | /* | |
1044 | * Specifies the OTG capabilities. The driver will automatically | |
1045 | * detect the value for this parameter if none is specified. | |
1046 | * 0 - HNP and SRP capable (default) | |
1047 | * 1 - SRP Only capable | |
1048 | * 2 - No HNP/SRP capable | |
1049 | */ | |
7218dae7 | 1050 | extern void dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg, int val); |
56f5b1cf PZ |
1051 | #define DWC2_CAP_PARAM_HNP_SRP_CAPABLE 0 |
1052 | #define DWC2_CAP_PARAM_SRP_ONLY_CAPABLE 1 | |
1053 | #define DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE 2 | |
1054 | ||
1055 | /* | |
1056 | * Specifies whether to use slave or DMA mode for accessing the data | |
1057 | * FIFOs. The driver will automatically detect the value for this | |
1058 | * parameter if none is specified. | |
1059 | * 0 - Slave | |
1060 | * 1 - DMA (default, if available) | |
1061 | */ | |
7218dae7 | 1062 | extern void dwc2_set_param_dma_enable(struct dwc2_hsotg *hsotg, int val); |
56f5b1cf PZ |
1063 | |
1064 | /* | |
1065 | * When DMA mode is enabled specifies whether to use | |
1066 | * address DMA or DMA Descritor mode for accessing the data | |
1067 | * FIFOs in device mode. The driver will automatically detect | |
1068 | * the value for this parameter if none is specified. | |
1069 | * 0 - address DMA | |
1070 | * 1 - DMA Descriptor(default, if available) | |
1071 | */ | |
7218dae7 | 1072 | extern void dwc2_set_param_dma_desc_enable(struct dwc2_hsotg *hsotg, int val); |
56f5b1cf | 1073 | |
fbb9e22b MYK |
1074 | /* |
1075 | * When DMA mode is enabled specifies whether to use | |
1076 | * address DMA or DMA Descritor mode with full speed devices | |
1077 | * for accessing the data FIFOs in host mode. | |
1078 | * 0 - address DMA | |
1079 | * 1 - FS DMA Descriptor(default, if available) | |
1080 | */ | |
1081 | extern void dwc2_set_param_dma_desc_fs_enable(struct dwc2_hsotg *hsotg, | |
1082 | int val); | |
1083 | ||
56f5b1cf PZ |
1084 | /* |
1085 | * Specifies the maximum speed of operation in host and device mode. | |
1086 | * The actual speed depends on the speed of the attached device and | |
1087 | * the value of phy_type. The actual speed depends on the speed of the | |
1088 | * attached device. | |
1089 | * 0 - High Speed (default) | |
1090 | * 1 - Full Speed | |
1091 | */ | |
7218dae7 | 1092 | extern void dwc2_set_param_speed(struct dwc2_hsotg *hsotg, int val); |
56f5b1cf PZ |
1093 | #define DWC2_SPEED_PARAM_HIGH 0 |
1094 | #define DWC2_SPEED_PARAM_FULL 1 | |
1095 | ||
1096 | /* | |
1097 | * Specifies whether low power mode is supported when attached | |
1098 | * to a Full Speed or Low Speed device in host mode. | |
1099 | * | |
1100 | * 0 - Don't support low power mode (default) | |
1101 | * 1 - Support low power mode | |
1102 | */ | |
7218dae7 PZ |
1103 | extern void dwc2_set_param_host_support_fs_ls_low_power( |
1104 | struct dwc2_hsotg *hsotg, int val); | |
56f5b1cf PZ |
1105 | |
1106 | /* | |
1107 | * Specifies the PHY clock rate in low power mode when connected to a | |
1108 | * Low Speed device in host mode. This parameter is applicable only if | |
1109 | * HOST_SUPPORT_FS_LS_LOW_POWER is enabled. If PHY_TYPE is set to FS | |
1110 | * then defaults to 6 MHZ otherwise 48 MHZ. | |
1111 | * | |
1112 | * 0 - 48 MHz | |
1113 | * 1 - 6 MHz | |
1114 | */ | |
7218dae7 PZ |
1115 | extern void dwc2_set_param_host_ls_low_power_phy_clk(struct dwc2_hsotg *hsotg, |
1116 | int val); | |
56f5b1cf PZ |
1117 | #define DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ 0 |
1118 | #define DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ 1 | |
1119 | ||
1120 | /* | |
1121 | * 0 - Use cC FIFO size parameters | |
1122 | * 1 - Allow dynamic FIFO sizing (default) | |
1123 | */ | |
7218dae7 PZ |
1124 | extern void dwc2_set_param_enable_dynamic_fifo(struct dwc2_hsotg *hsotg, |
1125 | int val); | |
56f5b1cf PZ |
1126 | |
1127 | /* | |
1128 | * Number of 4-byte words in the Rx FIFO in host mode when dynamic | |
1129 | * FIFO sizing is enabled. | |
1130 | * 16 to 32768 (default 1024) | |
1131 | */ | |
7218dae7 | 1132 | extern void dwc2_set_param_host_rx_fifo_size(struct dwc2_hsotg *hsotg, int val); |
56f5b1cf PZ |
1133 | |
1134 | /* | |
1135 | * Number of 4-byte words in the non-periodic Tx FIFO in host mode | |
1136 | * when Dynamic FIFO sizing is enabled in the core. | |
1137 | * 16 to 32768 (default 256) | |
1138 | */ | |
7218dae7 PZ |
1139 | extern void dwc2_set_param_host_nperio_tx_fifo_size(struct dwc2_hsotg *hsotg, |
1140 | int val); | |
56f5b1cf PZ |
1141 | |
1142 | /* | |
1143 | * Number of 4-byte words in the host periodic Tx FIFO when dynamic | |
1144 | * FIFO sizing is enabled. | |
1145 | * 16 to 32768 (default 256) | |
1146 | */ | |
7218dae7 PZ |
1147 | extern void dwc2_set_param_host_perio_tx_fifo_size(struct dwc2_hsotg *hsotg, |
1148 | int val); | |
56f5b1cf PZ |
1149 | |
1150 | /* | |
1151 | * The maximum transfer size supported in bytes. | |
1152 | * 2047 to 65,535 (default 65,535) | |
1153 | */ | |
7218dae7 | 1154 | extern void dwc2_set_param_max_transfer_size(struct dwc2_hsotg *hsotg, int val); |
56f5b1cf PZ |
1155 | |
1156 | /* | |
1157 | * The maximum number of packets in a transfer. | |
1158 | * 15 to 511 (default 511) | |
1159 | */ | |
7218dae7 | 1160 | extern void dwc2_set_param_max_packet_count(struct dwc2_hsotg *hsotg, int val); |
56f5b1cf PZ |
1161 | |
1162 | /* | |
1163 | * The number of host channel registers to use. | |
1164 | * 1 to 16 (default 11) | |
1165 | * Note: The FPGA configuration supports a maximum of 11 host channels. | |
1166 | */ | |
7218dae7 | 1167 | extern void dwc2_set_param_host_channels(struct dwc2_hsotg *hsotg, int val); |
56f5b1cf PZ |
1168 | |
1169 | /* | |
1170 | * Specifies the type of PHY interface to use. By default, the driver | |
1171 | * will automatically detect the phy_type. | |
1172 | * | |
1173 | * 0 - Full Speed PHY | |
1174 | * 1 - UTMI+ (default) | |
1175 | * 2 - ULPI | |
1176 | */ | |
7218dae7 | 1177 | extern void dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg, int val); |
56f5b1cf PZ |
1178 | #define DWC2_PHY_TYPE_PARAM_FS 0 |
1179 | #define DWC2_PHY_TYPE_PARAM_UTMI 1 | |
1180 | #define DWC2_PHY_TYPE_PARAM_ULPI 2 | |
1181 | ||
1182 | /* | |
1183 | * Specifies the UTMI+ Data Width. This parameter is | |
1184 | * applicable for a PHY_TYPE of UTMI+ or ULPI. (For a ULPI | |
1185 | * PHY_TYPE, this parameter indicates the data width between | |
1186 | * the MAC and the ULPI Wrapper.) Also, this parameter is | |
1187 | * applicable only if the OTG_HSPHY_WIDTH cC parameter was set | |
1188 | * to "8 and 16 bits", meaning that the core has been | |
1189 | * configured to work at either data path width. | |
1190 | * | |
1191 | * 8 or 16 bits (default 16) | |
1192 | */ | |
7218dae7 | 1193 | extern void dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg, int val); |
56f5b1cf PZ |
1194 | |
1195 | /* | |
1196 | * Specifies whether the ULPI operates at double or single | |
1197 | * data rate. This parameter is only applicable if PHY_TYPE is | |
1198 | * ULPI. | |
1199 | * | |
1200 | * 0 - single data rate ULPI interface with 8 bit wide data | |
1201 | * bus (default) | |
1202 | * 1 - double data rate ULPI interface with 4 bit wide data | |
1203 | * bus | |
1204 | */ | |
7218dae7 | 1205 | extern void dwc2_set_param_phy_ulpi_ddr(struct dwc2_hsotg *hsotg, int val); |
56f5b1cf PZ |
1206 | |
1207 | /* | |
1208 | * Specifies whether to use the internal or external supply to | |
1209 | * drive the vbus with a ULPI phy. | |
1210 | */ | |
7218dae7 | 1211 | extern void dwc2_set_param_phy_ulpi_ext_vbus(struct dwc2_hsotg *hsotg, int val); |
56f5b1cf PZ |
1212 | #define DWC2_PHY_ULPI_INTERNAL_VBUS 0 |
1213 | #define DWC2_PHY_ULPI_EXTERNAL_VBUS 1 | |
1214 | ||
1215 | /* | |
1216 | * Specifies whether to use the I2Cinterface for full speed PHY. This | |
1217 | * parameter is only applicable if PHY_TYPE is FS. | |
1218 | * 0 - No (default) | |
1219 | * 1 - Yes | |
1220 | */ | |
7218dae7 | 1221 | extern void dwc2_set_param_i2c_enable(struct dwc2_hsotg *hsotg, int val); |
56f5b1cf | 1222 | |
7218dae7 | 1223 | extern void dwc2_set_param_ulpi_fs_ls(struct dwc2_hsotg *hsotg, int val); |
56f5b1cf | 1224 | |
7218dae7 | 1225 | extern void dwc2_set_param_ts_dline(struct dwc2_hsotg *hsotg, int val); |
56f5b1cf PZ |
1226 | |
1227 | /* | |
1228 | * Specifies whether dedicated transmit FIFOs are | |
1229 | * enabled for non periodic IN endpoints in device mode | |
1230 | * 0 - No | |
1231 | * 1 - Yes | |
1232 | */ | |
7218dae7 PZ |
1233 | extern void dwc2_set_param_en_multiple_tx_fifo(struct dwc2_hsotg *hsotg, |
1234 | int val); | |
56f5b1cf | 1235 | |
7218dae7 | 1236 | extern void dwc2_set_param_reload_ctl(struct dwc2_hsotg *hsotg, int val); |
56f5b1cf | 1237 | |
7218dae7 | 1238 | extern void dwc2_set_param_ahbcfg(struct dwc2_hsotg *hsotg, int val); |
56f5b1cf | 1239 | |
7218dae7 | 1240 | extern void dwc2_set_param_otg_ver(struct dwc2_hsotg *hsotg, int val); |
56f5b1cf | 1241 | |
ecb176c6 MYK |
1242 | extern void dwc2_set_parameters(struct dwc2_hsotg *hsotg, |
1243 | const struct dwc2_core_params *params); | |
1244 | ||
1245 | extern void dwc2_set_all_params(struct dwc2_core_params *params, int value); | |
1246 | ||
1247 | extern int dwc2_get_hwparams(struct dwc2_hsotg *hsotg); | |
1248 | ||
09a75e85 MS |
1249 | extern int dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg); |
1250 | extern int dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg); | |
ecb176c6 | 1251 | |
6bea9620 JY |
1252 | /* |
1253 | * The following functions check the controller's OTG operation mode | |
1254 | * capability (GHWCFG2.OTG_MODE). | |
1255 | * | |
1256 | * These functions can be used before the internal hsotg->hw_params | |
1257 | * are read in and cached so they always read directly from the | |
1258 | * GHWCFG2 register. | |
1259 | */ | |
1260 | unsigned dwc2_op_mode(struct dwc2_hsotg *hsotg); | |
1261 | bool dwc2_hw_is_otg(struct dwc2_hsotg *hsotg); | |
1262 | bool dwc2_hw_is_host(struct dwc2_hsotg *hsotg); | |
1263 | bool dwc2_hw_is_device(struct dwc2_hsotg *hsotg); | |
1264 | ||
1696d5ab JY |
1265 | /* |
1266 | * Returns the mode of operation, host or device | |
1267 | */ | |
1268 | static inline int dwc2_is_host_mode(struct dwc2_hsotg *hsotg) | |
1269 | { | |
1270 | return (dwc2_readl(hsotg->regs + GINTSTS) & GINTSTS_CURMODE_HOST) != 0; | |
1271 | } | |
1272 | static inline int dwc2_is_device_mode(struct dwc2_hsotg *hsotg) | |
1273 | { | |
1274 | return (dwc2_readl(hsotg->regs + GINTSTS) & GINTSTS_CURMODE_HOST) == 0; | |
1275 | } | |
1276 | ||
56f5b1cf PZ |
1277 | /* |
1278 | * Dump core registers and SPRAM | |
1279 | */ | |
1280 | extern void dwc2_dump_dev_registers(struct dwc2_hsotg *hsotg); | |
1281 | extern void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg); | |
1282 | extern void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg); | |
1283 | ||
1284 | /* | |
1285 | * Return OTG version - either 1.3 or 2.0 | |
1286 | */ | |
1287 | extern u16 dwc2_get_otg_version(struct dwc2_hsotg *hsotg); | |
1288 | ||
117777b2 DN |
1289 | /* Gadget defines */ |
1290 | #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) | |
1f91b4cc FB |
1291 | extern int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg); |
1292 | extern int dwc2_hsotg_suspend(struct dwc2_hsotg *dwc2); | |
1293 | extern int dwc2_hsotg_resume(struct dwc2_hsotg *dwc2); | |
117777b2 | 1294 | extern int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq); |
1f91b4cc | 1295 | extern void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2, |
643cc4de | 1296 | bool reset); |
1f91b4cc FB |
1297 | extern void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg); |
1298 | extern void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2); | |
1299 | extern int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode); | |
f81f46e1 | 1300 | #define dwc2_is_device_connected(hsotg) (hsotg->connected) |
58e52ff6 JY |
1301 | int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg); |
1302 | int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg); | |
117777b2 | 1303 | #else |
1f91b4cc | 1304 | static inline int dwc2_hsotg_remove(struct dwc2_hsotg *dwc2) |
117777b2 | 1305 | { return 0; } |
1f91b4cc | 1306 | static inline int dwc2_hsotg_suspend(struct dwc2_hsotg *dwc2) |
117777b2 | 1307 | { return 0; } |
1f91b4cc | 1308 | static inline int dwc2_hsotg_resume(struct dwc2_hsotg *dwc2) |
117777b2 DN |
1309 | { return 0; } |
1310 | static inline int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq) | |
1311 | { return 0; } | |
1f91b4cc | 1312 | static inline void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2, |
643cc4de | 1313 | bool reset) {} |
1f91b4cc FB |
1314 | static inline void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg) {} |
1315 | static inline void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2) {} | |
1316 | static inline int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, | |
f91eea44 MYK |
1317 | int testmode) |
1318 | { return 0; } | |
f81f46e1 | 1319 | #define dwc2_is_device_connected(hsotg) (0) |
58e52ff6 JY |
1320 | static inline int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg) |
1321 | { return 0; } | |
1322 | static inline int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg) | |
1323 | { return 0; } | |
117777b2 DN |
1324 | #endif |
1325 | ||
1326 | #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) | |
1327 | extern int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg); | |
fae4e826 | 1328 | extern int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg, int us); |
6a659531 DA |
1329 | extern void dwc2_hcd_connect(struct dwc2_hsotg *hsotg); |
1330 | extern void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force); | |
117777b2 | 1331 | extern void dwc2_hcd_start(struct dwc2_hsotg *hsotg); |
58e52ff6 JY |
1332 | int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg); |
1333 | int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg); | |
117777b2 | 1334 | #else |
117777b2 DN |
1335 | static inline int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg) |
1336 | { return 0; } | |
fae4e826 DA |
1337 | static inline int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg, |
1338 | int us) | |
1339 | { return 0; } | |
6a659531 DA |
1340 | static inline void dwc2_hcd_connect(struct dwc2_hsotg *hsotg) {} |
1341 | static inline void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force) {} | |
117777b2 DN |
1342 | static inline void dwc2_hcd_start(struct dwc2_hsotg *hsotg) {} |
1343 | static inline void dwc2_hcd_remove(struct dwc2_hsotg *hsotg) {} | |
ecb176c6 | 1344 | static inline int dwc2_hcd_init(struct dwc2_hsotg *hsotg, int irq) |
117777b2 | 1345 | { return 0; } |
58e52ff6 JY |
1346 | static inline int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg) |
1347 | { return 0; } | |
1348 | static inline int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg) | |
1349 | { return 0; } | |
1350 | ||
117777b2 DN |
1351 | #endif |
1352 | ||
56f5b1cf | 1353 | #endif /* __DWC2_CORE_H__ */ |