projects / linux-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
usb: dwc2: gadget: Enable descriptor DMA mode
[linux-block.git] / drivers / usb / dwc2 / core.h
CommitLineData
56f5b1cf
PZ		 1/*
2 * core.h - DesignWare HS OTG Controller common declarations
3 *
4 * Copyright (C) 2004-2013 Synopsys, Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions, and the following disclaimer,
11 * without modification.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The names of the above-listed copyright holders may not be used
16 * to endorse or promote products derived from this software without
17 * specific prior written permission.
18 *
19 * ALTERNATIVELY, this software may be distributed under the terms of the
20 * GNU General Public License ("GPL") as published by the Free Software
21 * Foundation; either version 2 of the License, or (at your option) any
22 * later version.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
25 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
28 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
29 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
30 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
31 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
32 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
33 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
34 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 */
36
37#ifndef __DWC2_CORE_H__
38#define __DWC2_CORE_H__
39
f7c0b143
DN		 40#include <linux/phy/phy.h>
41#include <linux/regulator/consumer.h>
42#include <linux/usb/gadget.h>
43#include <linux/usb/otg.h>
56f5b1cf
PZ		 44#include <linux/usb/phy.h>
45#include "hw.h"
46
74fc4a75
DA		 47/*
48 * Suggested defines for tracers:
49 * - no_printk: Disable tracing
50 * - pr_info: Print this info to the console
51 * - trace_printk: Print this info to trace buffer (good for verbose logging)
52 */
53
54#define DWC2_TRACE_SCHEDULER no_printk
55#define DWC2_TRACE_SCHEDULER_VB no_printk
56
57/* Detailed scheduler tracing, but won't overwhelm console */
58#define dwc2_sch_dbg(hsotg, fmt, ...) \
59 DWC2_TRACE_SCHEDULER(pr_fmt("%s: SCH: " fmt), \
60 dev_name(hsotg->dev), ##__VA_ARGS__)
61
62/* Verbose scheduler tracing */
63#define dwc2_sch_vdbg(hsotg, fmt, ...) \
64 DWC2_TRACE_SCHEDULER_VB(pr_fmt("%s: SCH: " fmt), \
65 dev_name(hsotg->dev), ##__VA_ARGS__)
66
23e34392
AB		 67#ifdef CONFIG_MIPS
68/*
69 * There are some MIPS machines that can run in either big-endian
70 * or little-endian mode and that use the dwc2 register without
71 * a byteswap in both ways.
72 * Unlike other architectures, MIPS apparently does not require a
73 * barrier before the __raw_writel() to synchronize with DMA but does
74 * require the barrier after the __raw_writel() to serialize a set of
75 * writes. This set of operations was added specifically for MIPS and
76 * should only be used there.
77 */
95c8bc36 78static inline u32 dwc2_readl(const void __iomem *addr)
56f5b1cf 79{
95c8bc36
AS		 80 u32 value = __raw_readl(addr);
81
82 /* In order to preserve endianness __raw_* operation is used. Therefore
83 * a barrier is needed to ensure IO access is not re-ordered across
84 * reads or writes
85 */
86 mb();
87 return value;
56f5b1cf
PZ		 88}
89
95c8bc36
AS		 90static inline void dwc2_writel(u32 value, void __iomem *addr)
91{
92 __raw_writel(value, addr);
93
94 /*
95 * In order to preserve endianness __raw_* operation is used. Therefore
96 * a barrier is needed to ensure IO access is not re-ordered across
97 * reads or writes
98 */
99 mb();
100#ifdef DWC2_LOG_WRITES
101 pr_info("INFO:: wrote %08x to %p\n", value, addr);
56f5b1cf 102#endif
95c8bc36 103}
23e34392
AB		 104#else
105/* Normal architectures just use readl/write */
106static inline u32 dwc2_readl(const void __iomem *addr)
107{
108 return readl(addr);
109}
110
111static inline void dwc2_writel(u32 value, void __iomem *addr)
112{
113 writel(value, addr);
114
115#ifdef DWC2_LOG_WRITES
116 pr_info("info:: wrote %08x to %p\n", value, addr);
117#endif
118}
119#endif
56f5b1cf
PZ		 120
121/* Maximum number of Endpoints/HostChannels */
122#define MAX_EPS_CHANNELS 16
123
1f91b4cc
FB		 124/* dwc2-hsotg declarations */
125static const char * const dwc2_hsotg_supply_names[] = {
f7c0b143
DN		 126 "vusb_d", /* digital USB supply, 1.2V */
127 "vusb_a", /* analog USB supply, 1.1V */
128};
129
130/*
131 * EP0_MPS_LIMIT
132 *
133 * Unfortunately there seems to be a limit of the amount of data that can
134 * be transferred by IN transactions on EP0. This is either 127 bytes or 3
135 * packets (which practically means 1 packet and 63 bytes of data) when the
136 * MPS is set to 64.
137 *
138 * This means if we are wanting to move >127 bytes of data, we need to
139 * split the transactions up, but just doing one packet at a time does
140 * not work (this may be an implicit DATA0 PID on first packet of the
141 * transaction) and doing 2 packets is outside the controller's limits.
142 *
143 * If we try to lower the MPS size for EP0, then no transfers work properly
144 * for EP0, and the system will fail basic enumeration. As no cause for this
145 * has currently been found, we cannot support any large IN transfers for
146 * EP0.
147 */
148#define EP0_MPS_LIMIT 64
149
941fcce4 150struct dwc2_hsotg;
1f91b4cc 151struct dwc2_hsotg_req;
f7c0b143
DN		 152
153/**
1f91b4cc 154 * struct dwc2_hsotg_ep - driver endpoint definition.
f7c0b143
DN		 155 * @ep: The gadget layer representation of the endpoint.
156 * @name: The driver generated name for the endpoint.
157 * @queue: Queue of requests for this endpoint.
158 * @parent: Reference back to the parent device structure.
159 * @req: The current request that the endpoint is processing. This is
160 * used to indicate an request has been loaded onto the endpoint
161 * and has yet to be completed (maybe due to data move, or simply
162 * awaiting an ack from the core all the data has been completed).
163 * @debugfs: File entry for debugfs file for this endpoint.
164 * @lock: State lock to protect contents of endpoint.
165 * @dir_in: Set to true if this endpoint is of the IN direction, which
166 * means that it is sending data to the Host.
167 * @index: The index for the endpoint registers.
168 * @mc: Multi Count - number of transactions per microframe
142bd33f 169 * @interval - Interval for periodic endpoints, in frames or microframes.
f7c0b143
DN		 170 * @name: The name array passed to the USB core.
171 * @halted: Set if the endpoint has been halted.
172 * @periodic: Set if this is a periodic ep, such as Interrupt
173 * @isochronous: Set if this is a isochronous ep
8a20fa45 174 * @send_zlp: Set if we need to send a zero-length packet.
5f54c54b
VA		 175 * @desc_list_dma: The DMA address of descriptor chain currently in use.
176 * @desc_list: Pointer to descriptor DMA chain head currently in use.
177 * @desc_count: Count of entries within the DMA descriptor chain of EP.
f7c0b143
DN		 178 * @total_data: The total number of data bytes done.
179 * @fifo_size: The size of the FIFO (for periodic IN endpoints)
180 * @fifo_load: The amount of data loaded into the FIFO (periodic IN)
181 * @last_load: The offset of data for the last start of request.
182 * @size_loaded: The last loaded size for DxEPTSIZE for periodic IN
92d1635d
VM		 183 * @target_frame: Targeted frame num to setup next ISOC transfer
184 * @frame_overrun: Indicates SOF number overrun in DSTS
f7c0b143
DN		 185 *
186 * This is the driver's state for each registered enpoint, allowing it
187 * to keep track of transactions that need doing. Each endpoint has a
188 * lock to protect the state, to try and avoid using an overall lock
189 * for the host controller as much as possible.
190 *
191 * For periodic IN endpoints, we have fifo_size and fifo_load to try
192 * and keep track of the amount of data in the periodic FIFO for each
193 * of these as we don't have a status register that tells us how much
194 * is in each of them. (note, this may actually be useless information
195 * as in shared-fifo mode periodic in acts like a single-frame packet
196 * buffer than a fifo)
197 */
1f91b4cc 198struct dwc2_hsotg_ep {
f7c0b143
DN		 199 struct usb_ep ep;
200 struct list_head queue;
941fcce4 201 struct dwc2_hsotg *parent;
1f91b4cc 202 struct dwc2_hsotg_req *req;
f7c0b143
DN		 203 struct dentry *debugfs;
204
205 unsigned long total_data;
206 unsigned int size_loaded;
207 unsigned int last_load;
208 unsigned int fifo_load;
209 unsigned short fifo_size;
b203d0a2 210 unsigned short fifo_index;
f7c0b143
DN		 211
212 unsigned char dir_in;
213 unsigned char index;
214 unsigned char mc;
215 unsigned char interval;
216
217 unsigned int halted:1;
218 unsigned int periodic:1;
219 unsigned int isochronous:1;
8a20fa45 220 unsigned int send_zlp:1;
92d1635d
VM		 221 unsigned int target_frame;
222#define TARGET_FRAME_INITIAL 0xFFFFFFFF
223 bool frame_overrun;
f7c0b143 224
5f54c54b
VA		 225 dma_addr_t desc_list_dma;
226 struct dwc2_dma_desc *desc_list;
227 u8 desc_count;
228
f7c0b143
DN		 229 char name[10];
230};
231
f7c0b143 232/**
1f91b4cc 233 * struct dwc2_hsotg_req - data transfer request
f7c0b143
DN		 234 * @req: The USB gadget request
235 * @queue: The list of requests for the endpoint this is queued for.
7d24c1b5 236 * @saved_req_buf: variable to save req.buf when bounce buffers are used.
f7c0b143 237 */
1f91b4cc 238struct dwc2_hsotg_req {
f7c0b143
DN		 239 struct usb_request req;
240 struct list_head queue;
7d24c1b5 241 void *saved_req_buf;
f7c0b143
DN		 242};
243
941fcce4 244#if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
f7c0b143
DN		 245#define call_gadget(_hs, _entry) \
246do { \
247 if ((_hs)->gadget.speed != USB_SPEED_UNKNOWN && \
248 (_hs)->driver && (_hs)->driver->_entry) { \
249 spin_unlock(&_hs->lock); \
250 (_hs)->driver->_entry(&(_hs)->gadget); \
251 spin_lock(&_hs->lock); \
252 } \
253} while (0)
941fcce4
DN		 254#else
255#define call_gadget(_hs, _entry) do {} while (0)
256#endif
f7c0b143 257
56f5b1cf
PZ		 258struct dwc2_hsotg;
259struct dwc2_host_chan;
260
261/* Device States */
262enum dwc2_lx_state {
263 DWC2_L0, /* On state */
264 DWC2_L1, /* LPM sleep state */
265 DWC2_L2, /* USB suspend state */
266 DWC2_L3, /* Off state */
267};
268
3fa95385
JY		 269/*
270 * Gadget periodic tx fifo sizes as used by legacy driver
271 * EP0 is not included
272 */
273#define DWC2_G_P_LEGACY_TX_FIFO_SIZE {256, 256, 256, 256, 768, 768, 768, \
274 768, 0, 0, 0, 0, 0, 0, 0}
275
fe0b94ab
MYK		 276/* Gadget ep0 states */
277enum dwc2_ep0_state {
278 DWC2_EP0_SETUP,
279 DWC2_EP0_DATA_IN,
280 DWC2_EP0_DATA_OUT,
281 DWC2_EP0_STATUS_IN,
282 DWC2_EP0_STATUS_OUT,
283};
284
56f5b1cf
PZ		 285/**
286 * struct dwc2_core_params - Parameters for configuring the core
287 *
91121c10
MK		 288 * @otg_cap: Specifies the OTG capabilities.
289 * 0 - HNP and SRP capable
56f5b1cf 290 * 1 - SRP Only capable
91121c10
MK		 291 * 2 - No HNP/SRP capable (always available)
292 * Defaults to best available option (0, 1, then 2)
725acc86 293 * @otg_ver: OTG version supported
91121c10 294 * 0 - 1.3 (default)
725acc86 295 * 1 - 2.0
e7839f99 296 * @host_dma: Specifies whether to use slave or DMA mode for accessing
56f5b1cf
PZ		 297 * the data FIFOs. The driver will automatically detect the
298 * value for this parameter if none is specified.
91121c10 299 * 0 - Slave (always available)
56f5b1cf
PZ		 300 * 1 - DMA (default, if available)
301 * @dma_desc_enable: When DMA mode is enabled, specifies whether to use
302 * address DMA mode or descriptor DMA mode for accessing
303 * the data FIFOs. The driver will automatically detect the
304 * value for this if none is specified.
305 * 0 - Address DMA
306 * 1 - Descriptor DMA (default, if available)
fbb9e22b
MYK		 307 * @dma_desc_fs_enable: When DMA mode is enabled, specifies whether to use
308 * address DMA mode or descriptor DMA mode for accessing
309 * the data FIFOs in Full Speed mode only. The driver
310 * will automatically detect the value for this if none is
311 * specified.
312 * 0 - Address DMA
313 * 1 - Descriptor DMA in FS (default, if available)
56f5b1cf
PZ		 314 * @speed: Specifies the maximum speed of operation in host and
315 * device mode. The actual speed depends on the speed of
316 * the attached device and the value of phy_type.
91121c10
MK		 317 * 0 - High Speed
318 * (default when phy_type is UTMI+ or ULPI)
56f5b1cf 319 * 1 - Full Speed
91121c10 320 * (default when phy_type is Full Speed)
56f5b1cf 321 * @enable_dynamic_fifo: 0 - Use coreConsultant-specified FIFO size parameters
91121c10 322 * 1 - Allow dynamic FIFO sizing (default, if available)
725acc86 323 * @en_multiple_tx_fifo: Specifies whether dedicated per-endpoint transmit FIFOs
c1d286cf
JY		 324 * are enabled for non-periodic IN endpoints in device
325 * mode.
56f5b1cf
PZ		 326 * @host_rx_fifo_size: Number of 4-byte words in the Rx FIFO in host mode when
327 * dynamic FIFO sizing is enabled
91121c10
MK		 328 * 16 to 32768
329 * Actual maximum value is autodetected and also
330 * the default.
56f5b1cf
PZ		 331 * @host_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO
332 * in host mode when dynamic FIFO sizing is enabled
91121c10
MK		 333 * 16 to 32768
334 * Actual maximum value is autodetected and also
335 * the default.
56f5b1cf
PZ		 336 * @host_perio_tx_fifo_size: Number of 4-byte words in the periodic Tx FIFO in
337 * host mode when dynamic FIFO sizing is enabled
91121c10
MK		 338 * 16 to 32768
339 * Actual maximum value is autodetected and also
340 * the default.
56f5b1cf 341 * @max_transfer_size: The maximum transfer size supported, in bytes
91121c10
MK		 342 * 2047 to 65,535
343 * Actual maximum value is autodetected and also
344 * the default.
56f5b1cf 345 * @max_packet_count: The maximum number of packets in a transfer
91121c10
MK		 346 * 15 to 511
347 * Actual maximum value is autodetected and also
348 * the default.
56f5b1cf 349 * @host_channels: The number of host channel registers to use
91121c10
MK		 350 * 1 to 16
351 * Actual maximum value is autodetected and also
352 * the default.
56f5b1cf
PZ		 353 * @phy_type: Specifies the type of PHY interface to use. By default,
354 * the driver will automatically detect the phy_type.
91121c10
MK		 355 * 0 - Full Speed Phy
356 * 1 - UTMI+ Phy
357 * 2 - ULPI Phy
358 * Defaults to best available option (2, 1, then 0)
56f5b1cf
PZ		 359 * @phy_utmi_width: Specifies the UTMI+ Data Width (in bits). This parameter
360 * is applicable for a phy_type of UTMI+ or ULPI. (For a
361 * ULPI phy_type, this parameter indicates the data width
362 * between the MAC and the ULPI Wrapper.) Also, this
363 * parameter is applicable only if the OTG_HSPHY_WIDTH cC
364 * parameter was set to "8 and 16 bits", meaning that the
365 * core has been configured to work at either data path
366 * width.
91121c10 367 * 8 or 16 (default 16 if available)
56f5b1cf
PZ		 368 * @phy_ulpi_ddr: Specifies whether the ULPI operates at double or single
369 * data rate. This parameter is only applicable if phy_type
370 * is ULPI.
371 * 0 - single data rate ULPI interface with 8 bit wide
372 * data bus (default)
373 * 1 - double data rate ULPI interface with 4 bit wide
374 * data bus
375 * @phy_ulpi_ext_vbus: For a ULPI phy, specifies whether to use the internal or
376 * external supply to drive the VBus
91121c10
MK		 377 * 0 - Internal supply (default)
378 * 1 - External supply
56f5b1cf
PZ		 379 * @i2c_enable: Specifies whether to use the I2Cinterface for a full
380 * speed PHY. This parameter is only applicable if phy_type
381 * is FS.
382 * 0 - No (default)
383 * 1 - Yes
91121c10
MK		 384 * @ulpi_fs_ls: Make ULPI phy operate in FS/LS mode only
385 * 0 - No (default)
386 * 1 - Yes
725acc86
PZ		 387 * @host_support_fs_ls_low_power: Specifies whether low power mode is supported
388 * when attached to a Full Speed or Low Speed device in
389 * host mode.
390 * 0 - Don't support low power mode (default)
391 * 1 - Support low power mode
392 * @host_ls_low_power_phy_clk: Specifies the PHY clock rate in low power mode
91121c10
MK		 393 * when connected to a Low Speed device in host
394 * mode. This parameter is applicable only if
395 * host_support_fs_ls_low_power is enabled.
725acc86 396 * 0 - 48 MHz
91121c10 397 * (default when phy_type is UTMI+ or ULPI)
725acc86 398 * 1 - 6 MHz
91121c10
MK		 399 * (default when phy_type is Full Speed)
400 * @ts_dline: Enable Term Select Dline pulsing
401 * 0 - No (default)
402 * 1 - Yes
403 * @reload_ctl: Allow dynamic reloading of HFIR register during runtime
404 * 0 - No (default for core < 2.92a)
405 * 1 - Yes (default for core >= 2.92a)
4d3190e1
PZ		 406 * @ahbcfg: This field allows the default value of the GAHBCFG
407 * register to be overridden
91121c10
MK		 408 * -1 - GAHBCFG value will be set to 0x06
409 * (INCR4, default)
4d3190e1
PZ		 410 * all others - GAHBCFG value will be overridden with
411 * this value
91121c10
MK		 412 * Not all bits can be controlled like this, the
413 * bits defined by GAHBCFG_CTRL_MASK are controlled
414 * by the driver and are ignored in this
415 * configuration value.
20f2eb9c 416 * @uframe_sched: True to enable the microframe scheduler
a6d249d8
GH		 417 * @external_id_pin_ctl: Specifies whether ID pin is handled externally.
418 * Disable CONIDSTSCHNG controller interrupt in such
419 * case.
420 * 0 - No (default)
421 * 1 - Yes
285046aa
GH		 422 * @hibernation: Specifies whether the controller support hibernation.
423 * If hibernation is enabled, the controller will enter
424 * hibernation in both peripheral and host mode when
425 * needed.
426 * 0 - No (default)
427 * 1 - Yes
9962b62f 428 * @g_dma: Enables gadget dma usage (default: autodetect).
dec4b556 429 * @g_dma_desc: Enables gadget descriptor DMA (default: autodetect).
05ee799f
JY		 430 * @g_rx_fifo_size: The periodic rx fifo size for the device, in
431 * DWORDS from 16-32768 (default: 2048 if
432 * possible, otherwise autodetect).
433 * @g_np_tx_fifo_size: The non-periodic tx fifo size for the device in
434 * DWORDS from 16-32768 (default: 1024 if
435 * possible, otherwise autodetect).
436 * @g_tx_fifo_size: An array of TX fifo sizes in dedicated fifo
437 * mode. Each value corresponds to one EP
438 * starting from EP1 (max 15 values). Sizes are
439 * in DWORDS with possible values from from
440 * 16-32768 (default: 256, 256, 256, 256, 768,
441 * 768, 768, 768, 0, 0, 0, 0, 0, 0, 0).
56f5b1cf
PZ		 442 *
443 * The following parameters may be specified when starting the module. These
91121c10
MK		 444 * parameters define how the DWC_otg controller should be configured. A
445 * value of -1 (or any other out of range value) for any parameter means
446 * to read the value from hardware (if possible) or use the builtin
447 * default described above.
56f5b1cf
PZ		 448 */
449struct dwc2_core_params {
8284f93b
MK		 450 /*
451 * Don't add any non-int members here, this will break
452 * dwc2_set_all_params!
453 */
56f5b1cf 454 int otg_cap;
c1d286cf
JY		 455#define DWC2_CAP_PARAM_HNP_SRP_CAPABLE 0
456#define DWC2_CAP_PARAM_SRP_ONLY_CAPABLE 1
457#define DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE 2
458
56f5b1cf 459 int otg_ver;
56f5b1cf 460 int dma_desc_enable;
fbb9e22b 461 int dma_desc_fs_enable;
56f5b1cf 462 int speed;
c1d286cf
JY		 463#define DWC2_SPEED_PARAM_HIGH 0
464#define DWC2_SPEED_PARAM_FULL 1
465
56f5b1cf
PZ		 466 int enable_dynamic_fifo;
467 int en_multiple_tx_fifo;
468 int host_rx_fifo_size;
469 int host_nperio_tx_fifo_size;
470 int host_perio_tx_fifo_size;
471 int max_transfer_size;
472 int max_packet_count;
473 int host_channels;
474 int phy_type;
c1d286cf
JY		 475#define DWC2_PHY_TYPE_PARAM_FS 0
476#define DWC2_PHY_TYPE_PARAM_UTMI 1
477#define DWC2_PHY_TYPE_PARAM_ULPI 2
478
56f5b1cf
PZ		 479 int phy_utmi_width;
480 int phy_ulpi_ddr;
481 int phy_ulpi_ext_vbus;
c1d286cf
JY		 482#define DWC2_PHY_ULPI_INTERNAL_VBUS 0
483#define DWC2_PHY_ULPI_EXTERNAL_VBUS 1
484
56f5b1cf
PZ		 485 int i2c_enable;
486 int ulpi_fs_ls;
487 int host_support_fs_ls_low_power;
488 int host_ls_low_power_phy_clk;
c1d286cf
JY		 489#define DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ 0
490#define DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ 1
491
56f5b1cf
PZ		 492 int ts_dline;
493 int reload_ctl;
4d3190e1 494 int ahbcfg;
20f2eb9c 495 int uframe_sched;
a6d249d8 496 int external_id_pin_ctl;
285046aa 497 int hibernation;
05ee799f
JY		 498
499 /*
500 * The following parameters are *only* set via device
501 * properties and cannot be set directly in this structure.
502 */
6b66ce51
JY		 503
504 /* Host parameters */
505 bool host_dma;
506
507 /* Gadget parameters */
05ee799f 508 bool g_dma;
dec4b556 509 bool g_dma_desc;
05ee799f
JY		 510 u16 g_rx_fifo_size;
511 u16 g_np_tx_fifo_size;
512 u32 g_tx_fifo_size[MAX_EPS_CHANNELS];
56f5b1cf
PZ		 513};
514
9badec2f
MK		 515/**
516 * struct dwc2_hw_params - Autodetected parameters.
517 *
518 * These parameters are the various parameters read from hardware
519 * registers during initialization. They typically contain the best
520 * supported or maximum value that can be configured in the
521 * corresponding dwc2_core_params value.
522 *
523 * The values that are not in dwc2_core_params are documented below.
524 *
525 * @op_mode Mode of Operation
526 * 0 - HNP- and SRP-Capable OTG (Host & Device)
527 * 1 - SRP-Capable OTG (Host & Device)
528 * 2 - Non-HNP and Non-SRP Capable OTG (Host & Device)
529 * 3 - SRP-Capable Device
530 * 4 - Non-OTG Device
531 * 5 - SRP-Capable Host
532 * 6 - Non-OTG Host
533 * @arch Architecture
534 * 0 - Slave only
535 * 1 - External DMA
536 * 2 - Internal DMA
537 * @power_optimized Are power optimizations enabled?
538 * @num_dev_ep Number of device endpoints available
539 * @num_dev_perio_in_ep Number of device periodic IN endpoints
997f4f81 540 * available
9badec2f
MK		 541 * @dev_token_q_depth Device Mode IN Token Sequence Learning Queue
542 * Depth
543 * 0 to 30
544 * @host_perio_tx_q_depth
545 * Host Mode Periodic Request Queue Depth
546 * 2, 4 or 8
547 * @nperio_tx_q_depth
548 * Non-Periodic Request Queue Depth
549 * 2, 4 or 8
550 * @hs_phy_type High-speed PHY interface type
551 * 0 - High-speed interface not supported
552 * 1 - UTMI+
553 * 2 - ULPI
554 * 3 - UTMI+ and ULPI
555 * @fs_phy_type Full-speed PHY interface type
556 * 0 - Full speed interface not supported
557 * 1 - Dedicated full speed interface
558 * 2 - FS pins shared with UTMI+ pins
559 * 3 - FS pins shared with ULPI pins
560 * @total_fifo_size: Total internal RAM for FIFOs (bytes)
de4a1931
MK		 561 * @utmi_phy_data_width UTMI+ PHY data width
562 * 0 - 8 bits
563 * 1 - 16 bits
564 * 2 - 8 or 16 bits
9badec2f 565 * @snpsid: Value from SNPSID register
55e1040e 566 * @dev_ep_dirs: Direction of device endpoints (GHWCFG1)
9badec2f
MK		 567 */
568struct dwc2_hw_params {
569 unsigned op_mode:3;
570 unsigned arch:2;
571 unsigned dma_desc_enable:1;
572 unsigned enable_dynamic_fifo:1;
573 unsigned en_multiple_tx_fifo:1;
d1531319 574 unsigned rx_fifo_size:16;
9badec2f 575 unsigned host_nperio_tx_fifo_size:16;
55e1040e 576 unsigned dev_nperio_tx_fifo_size:16;
9badec2f
MK		 577 unsigned host_perio_tx_fifo_size:16;
578 unsigned nperio_tx_q_depth:3;
579 unsigned host_perio_tx_q_depth:3;
580 unsigned dev_token_q_depth:5;
581 unsigned max_transfer_size:26;
582 unsigned max_packet_count:11;
2d115547 583 unsigned host_channels:5;
9badec2f
MK		 584 unsigned hs_phy_type:2;
585 unsigned fs_phy_type:2;
586 unsigned i2c_enable:1;
587 unsigned num_dev_ep:4;
588 unsigned num_dev_perio_in_ep:4;
589 unsigned total_fifo_size:16;
590 unsigned power_optimized:1;
de4a1931 591 unsigned utmi_phy_data_width:2;
9badec2f 592 u32 snpsid;
55e1040e 593 u32 dev_ep_dirs;
9badec2f
MK		 594};
595
3f95001d
MYK		 596/* Size of control and EP0 buffers */
597#define DWC2_CTRL_BUFF_SIZE 8
598
d17ee77b
GH		 599/**
600 * struct dwc2_gregs_backup - Holds global registers state before entering partial
601 * power down
602 * @gotgctl: Backup of GOTGCTL register
603 * @gintmsk: Backup of GINTMSK register
604 * @gahbcfg: Backup of GAHBCFG register
605 * @gusbcfg: Backup of GUSBCFG register
606 * @grxfsiz: Backup of GRXFSIZ register
607 * @gnptxfsiz: Backup of GNPTXFSIZ register
608 * @gi2cctl: Backup of GI2CCTL register
609 * @hptxfsiz: Backup of HPTXFSIZ register
610 * @gdfifocfg: Backup of GDFIFOCFG register
611 * @dtxfsiz: Backup of DTXFSIZ registers for each endpoint
612 * @gpwrdn: Backup of GPWRDN register
613 */
614struct dwc2_gregs_backup {
615 u32 gotgctl;
616 u32 gintmsk;
617 u32 gahbcfg;
618 u32 gusbcfg;
619 u32 grxfsiz;
620 u32 gnptxfsiz;
621 u32 gi2cctl;
622 u32 hptxfsiz;
623 u32 pcgcctl;
624 u32 gdfifocfg;
625 u32 dtxfsiz[MAX_EPS_CHANNELS];
626 u32 gpwrdn;
cc1e204c 627 bool valid;
d17ee77b
GH		 628};
629
630/**
631 * struct dwc2_dregs_backup - Holds device registers state before entering partial
632 * power down
633 * @dcfg: Backup of DCFG register
634 * @dctl: Backup of DCTL register
635 * @daintmsk: Backup of DAINTMSK register
636 * @diepmsk: Backup of DIEPMSK register
637 * @doepmsk: Backup of DOEPMSK register
638 * @diepctl: Backup of DIEPCTL register
639 * @dieptsiz: Backup of DIEPTSIZ register
640 * @diepdma: Backup of DIEPDMA register
641 * @doepctl: Backup of DOEPCTL register
642 * @doeptsiz: Backup of DOEPTSIZ register
643 * @doepdma: Backup of DOEPDMA register
644 */
645struct dwc2_dregs_backup {
646 u32 dcfg;
647 u32 dctl;
648 u32 daintmsk;
649 u32 diepmsk;
650 u32 doepmsk;
651 u32 diepctl[MAX_EPS_CHANNELS];
652 u32 dieptsiz[MAX_EPS_CHANNELS];
653 u32 diepdma[MAX_EPS_CHANNELS];
654 u32 doepctl[MAX_EPS_CHANNELS];
655 u32 doeptsiz[MAX_EPS_CHANNELS];
656 u32 doepdma[MAX_EPS_CHANNELS];
cc1e204c 657 bool valid;
d17ee77b
GH		 658};
659
660/**
661 * struct dwc2_hregs_backup - Holds host registers state before entering partial
662 * power down
663 * @hcfg: Backup of HCFG register
664 * @haintmsk: Backup of HAINTMSK register
665 * @hcintmsk: Backup of HCINTMSK register
666 * @hptr0: Backup of HPTR0 register
667 * @hfir: Backup of HFIR register
668 */
669struct dwc2_hregs_backup {
670 u32 hcfg;
671 u32 haintmsk;
672 u32 hcintmsk[MAX_EPS_CHANNELS];
673 u32 hprt0;
674 u32 hfir;
cc1e204c 675 bool valid;
d17ee77b
GH		 676};
677
9f9f09b0
DA		 678/*
679 * Constants related to high speed periodic scheduling
680 *
681 * We have a periodic schedule that is DWC2_HS_SCHEDULE_UFRAMES long. From a
682 * reservation point of view it's assumed that the schedule goes right back to
683 * the beginning after the end of the schedule.
684 *
685 * What does that mean for scheduling things with a long interval? It means
686 * we'll reserve time for them in every possible microframe that they could
687 * ever be scheduled in. ...but we'll still only actually schedule them as
688 * often as they were requested.
689 *
690 * We keep our schedule in a "bitmap" structure. This simplifies having
691 * to keep track of and merge intervals: we just let the bitmap code do most
692 * of the heavy lifting. In a way scheduling is much like memory allocation.
693 *
694 * We schedule 100us per uframe or 80% of 125us (the maximum amount you're
695 * supposed to schedule for periodic transfers). That's according to spec.
696 *
697 * Note that though we only schedule 80% of each microframe, the bitmap that we
698 * keep the schedule in is tightly packed (AKA it doesn't have 100us worth of
699 * space for each uFrame).
700 *
701 * Requirements:
702 * - DWC2_HS_SCHEDULE_UFRAMES must even divide 0x4000 (HFNUM_MAX_FRNUM + 1)
703 * - DWC2_HS_SCHEDULE_UFRAMES must be 8 times DWC2_LS_SCHEDULE_FRAMES (probably
704 * could be any multiple of 8 times DWC2_LS_SCHEDULE_FRAMES, but there might
705 * be bugs). The 8 comes from the USB spec: number of microframes per frame.
706 */
707#define DWC2_US_PER_UFRAME 125
708#define DWC2_HS_PERIODIC_US_PER_UFRAME 100
709
710#define DWC2_HS_SCHEDULE_UFRAMES 8
711#define DWC2_HS_SCHEDULE_US (DWC2_HS_SCHEDULE_UFRAMES * \
712 DWC2_HS_PERIODIC_US_PER_UFRAME)
713
714/*
715 * Constants related to low speed scheduling
716 *
717 * For high speed we schedule every 1us. For low speed that's a bit overkill,
718 * so we make up a unit called a "slice" that's worth 25us. There are 40
719 * slices in a full frame and we can schedule 36 of those (90%) for periodic
720 * transfers.
721 *
722 * Our low speed schedule can be as short as 1 frame or could be longer. When
723 * we only schedule 1 frame it means that we'll need to reserve a time every
724 * frame even for things that only transfer very rarely, so something that runs
725 * every 2048 frames will get time reserved in every frame. Our low speed
726 * schedule can be longer and we'll be able to handle more overlap, but that
727 * will come at increased memory cost and increased time to schedule.
728 *
729 * Note: one other advantage of a short low speed schedule is that if we mess
730 * up and miss scheduling we can jump in and use any of the slots that we
731 * happened to reserve.
732 *
733 * With 25 us per slice and 1 frame in the schedule, we only need 4 bytes for
734 * the schedule. There will be one schedule per TT.
735 *
736 * Requirements:
737 * - DWC2_US_PER_SLICE must evenly divide DWC2_LS_PERIODIC_US_PER_FRAME.
738 */
739#define DWC2_US_PER_SLICE 25
740#define DWC2_SLICES_PER_UFRAME (DWC2_US_PER_UFRAME / DWC2_US_PER_SLICE)
741
742#define DWC2_ROUND_US_TO_SLICE(us) \
743 (DIV_ROUND_UP((us), DWC2_US_PER_SLICE) * \
744 DWC2_US_PER_SLICE)
745
746#define DWC2_LS_PERIODIC_US_PER_FRAME \
747 900
748#define DWC2_LS_PERIODIC_SLICES_PER_FRAME \
749 (DWC2_LS_PERIODIC_US_PER_FRAME / \
750 DWC2_US_PER_SLICE)
751
752#define DWC2_LS_SCHEDULE_FRAMES 1
753#define DWC2_LS_SCHEDULE_SLICES (DWC2_LS_SCHEDULE_FRAMES * \
754 DWC2_LS_PERIODIC_SLICES_PER_FRAME)
755
56f5b1cf
PZ		 756/**
757 * struct dwc2_hsotg - Holds the state of the driver, including the non-periodic
758 * and periodic schedules
759 *
941fcce4
DN		 760 * These are common for both host and peripheral modes:
761 *
56f5b1cf
PZ		 762 * @dev: The struct device pointer
763 * @regs: Pointer to controller regs
9badec2f
MK		 764 * @hw_params: Parameters that were autodetected from the
765 * hardware registers
941fcce4 766 * @core_params: Parameters that define how the core should be configured
56f5b1cf
PZ		 767 * @op_state: The operational State, during transitions (a_host=>
768 * a_peripheral and b_device=>b_host) this may not match
769 * the core, but allows the software to determine
770 * transitions
c0155b9d
KY		 771 * @dr_mode: Requested mode of operation, one of following:
772 * - USB_DR_MODE_PERIPHERAL
773 * - USB_DR_MODE_HOST
774 * - USB_DR_MODE_OTG
09a75e85
MS		 775 * @hcd_enabled Host mode sub-driver initialization indicator.
776 * @gadget_enabled Peripheral mode sub-driver initialization indicator.
777 * @ll_hw_enabled Status of low-level hardware resources.
778 * @phy: The otg phy transceiver structure for phy control.
779 * @uphy: The otg phy transceiver structure for old USB phy control.
780 * @plat: The platform specific configuration data. This can be removed once
781 * all SoCs support usb transceiver.
782 * @supplies: Definition of USB power supplies
783 * @phyif: PHY interface width
941fcce4
DN		 784 * @lock: Spinlock that protects all the driver data structures
785 * @priv: Stores a pointer to the struct usb_hcd
56f5b1cf
PZ		 786 * @queuing_high_bandwidth: True if multiple packets of a high-bandwidth
787 * transfer are in process of being queued
788 * @srp_success: Stores status of SRP request in the case of a FS PHY
789 * with an I2C interface
790 * @wq_otg: Workqueue object used for handling of some interrupts
791 * @wf_otg: Work object for handling Connector ID Status Change
792 * interrupt
793 * @wkp_timer: Timer object for handling Wakeup Detected interrupt
794 * @lx_state: Lx state of connected device
d17ee77b
GH		 795 * @gregs_backup: Backup of global registers during suspend
796 * @dregs_backup: Backup of device registers during suspend
797 * @hregs_backup: Backup of host registers during suspend
941fcce4
DN		 798 *
799 * These are for host mode:
800 *
56f5b1cf
PZ		 801 * @flags: Flags for handling root port state changes
802 * @non_periodic_sched_inactive: Inactive QHs in the non-periodic schedule.
803 * Transfers associated with these QHs are not currently
804 * assigned to a host channel.
805 * @non_periodic_sched_active: Active QHs in the non-periodic schedule.
806 * Transfers associated with these QHs are currently
807 * assigned to a host channel.
808 * @non_periodic_qh_ptr: Pointer to next QH to process in the active
809 * non-periodic schedule
810 * @periodic_sched_inactive: Inactive QHs in the periodic schedule. This is a
811 * list of QHs for periodic transfers that are _not_
812 * scheduled for the next frame. Each QH in the list has an
813 * interval counter that determines when it needs to be
814 * scheduled for execution. This scheduling mechanism
815 * allows only a simple calculation for periodic bandwidth
816 * used (i.e. must assume that all periodic transfers may
817 * need to execute in the same frame). However, it greatly
818 * simplifies scheduling and should be sufficient for the
819 * vast majority of OTG hosts, which need to connect to a
820 * small number of peripherals at one time. Items move from
821 * this list to periodic_sched_ready when the QH interval
822 * counter is 0 at SOF.
823 * @periodic_sched_ready: List of periodic QHs that are ready for execution in
824 * the next frame, but have not yet been assigned to host
825 * channels. Items move from this list to
826 * periodic_sched_assigned as host channels become
827 * available during the current frame.
828 * @periodic_sched_assigned: List of periodic QHs to be executed in the next
829 * frame that are assigned to host channels. Items move
830 * from this list to periodic_sched_queued as the
831 * transactions for the QH are queued to the DWC_otg
832 * controller.
833 * @periodic_sched_queued: List of periodic QHs that have been queued for
834 * execution. Items move from this list to either
835 * periodic_sched_inactive or periodic_sched_ready when the
836 * channel associated with the transfer is released. If the
837 * interval for the QH is 1, the item moves to
838 * periodic_sched_ready because it must be rescheduled for
839 * the next frame. Otherwise, the item moves to
840 * periodic_sched_inactive.
c9c8ac01 841 * @split_order: List keeping track of channels doing splits, in order.
56f5b1cf
PZ		 842 * @periodic_usecs: Total bandwidth claimed so far for periodic transfers.
843 * This value is in microseconds per (micro)frame. The
844 * assumption is that all periodic transfers may occur in
845 * the same (micro)frame.
9f9f09b0
DA		 846 * @hs_periodic_bitmap: Bitmap used by the microframe scheduler any time the
847 * host is in high speed mode; low speed schedules are
848 * stored elsewhere since we need one per TT.
56f5b1cf
PZ		 849 * @frame_number: Frame number read from the core at SOF. The value ranges
850 * from 0 to HFNUM_MAX_FRNUM.
851 * @periodic_qh_count: Count of periodic QHs, if using several eps. Used for
852 * SOF enable/disable.
853 * @free_hc_list: Free host channels in the controller. This is a list of
854 * struct dwc2_host_chan items.
855 * @periodic_channels: Number of host channels assigned to periodic transfers.
856 * Currently assuming that there is a dedicated host
857 * channel for each periodic transaction and at least one
858 * host channel is available for non-periodic transactions.
859 * @non_periodic_channels: Number of host channels assigned to non-periodic
860 * transfers
20f2eb9c
DC		 861 * @available_host_channels Number of host channels available for the microframe
862 * scheduler to use
56f5b1cf
PZ		 863 * @hc_ptr_array: Array of pointers to the host channel descriptors.
864 * Allows accessing a host channel descriptor given the
865 * host channel number. This is useful in interrupt
866 * handlers.
867 * @status_buf: Buffer used for data received during the status phase of
868 * a control transfer.
869 * @status_buf_dma: DMA address for status_buf
870 * @start_work: Delayed work for handling host A-cable connection
871 * @reset_work: Delayed work for handling a port reset
56f5b1cf
PZ		 872 * @otg_port: OTG port number
873 * @frame_list: Frame list
874 * @frame_list_dma: Frame list DMA address
95105a99 875 * @frame_list_sz: Frame list size
3b5fcc9a
GH		 876 * @desc_gen_cache: Kmem cache for generic descriptors
877 * @desc_hsisoc_cache: Kmem cache for hs isochronous descriptors
941fcce4
DN		 878 *
879 * These are for peripheral mode:
880 *
881 * @driver: USB gadget driver
941fcce4
DN		 882 * @dedicated_fifos: Set if the hardware has dedicated IN-EP fifos.
883 * @num_of_eps: Number of available EPs (excluding EP0)
884 * @debug_root: Root directrory for debugfs.
885 * @debug_file: Main status file for debugfs.
9e14d0a5 886 * @debug_testmode: Testmode status file for debugfs.
941fcce4
DN		 887 * @debug_fifo: FIFO status file for debugfs.
888 * @ep0_reply: Request used for ep0 reply.
889 * @ep0_buff: Buffer for EP0 reply data, if needed.
890 * @ctrl_buff: Buffer for EP0 control requests.
891 * @ctrl_req: Request for EP0 control packets.
fe0b94ab 892 * @ep0_state: EP0 control transfers state
9e14d0a5 893 * @test_mode: USB test mode requested by the host
0f6b80c0
VA		 894 * @setup_desc_dma: EP0 setup stage desc chain DMA address
895 * @setup_desc: EP0 setup stage desc chain pointer
896 * @ctrl_in_desc_dma: EP0 IN data phase desc chain DMA address
897 * @ctrl_in_desc: EP0 IN data phase desc chain pointer
898 * @ctrl_out_desc_dma: EP0 OUT data phase desc chain DMA address
899 * @ctrl_out_desc: EP0 OUT data phase desc chain pointer
941fcce4 900 * @eps: The endpoints being supplied to the gadget framework
56f5b1cf
PZ		 901 */
902struct dwc2_hsotg {
903 struct device *dev;
904 void __iomem *regs;
9badec2f
MK		 905 /** Params detected from hardware */
906 struct dwc2_hw_params hw_params;
907 /** Params to actually use */
bea8e86c 908 struct dwc2_core_params params;
56f5b1cf 909 enum usb_otg_state op_state;
c0155b9d 910 enum usb_dr_mode dr_mode;
e39af88f
MS		 911 unsigned int hcd_enabled:1;
912 unsigned int gadget_enabled:1;
09a75e85 913 unsigned int ll_hw_enabled:1;
56f5b1cf 914
941fcce4
DN		 915 struct phy *phy;
916 struct usb_phy *uphy;
09a75e85 917 struct dwc2_hsotg_plat *plat;
1f91b4cc 918 struct regulator_bulk_data supplies[ARRAY_SIZE(dwc2_hsotg_supply_names)];
09a75e85 919 u32 phyif;
941fcce4
DN		 920
921 spinlock_t lock;
922 void *priv;
923 int irq;
924 struct clk *clk;
83f8da56 925 struct reset_control *reset;
941fcce4 926
56f5b1cf
PZ		 927 unsigned int queuing_high_bandwidth:1;
928 unsigned int srp_success:1;
929
930 struct workqueue_struct *wq_otg;
931 struct work_struct wf_otg;
932 struct timer_list wkp_timer;
933 enum dwc2_lx_state lx_state;
cc1e204c
MYK		 934 struct dwc2_gregs_backup gr_backup;
935 struct dwc2_dregs_backup dr_backup;
936 struct dwc2_hregs_backup hr_backup;
56f5b1cf 937
941fcce4 938 struct dentry *debug_root;
563cf017 939 struct debugfs_regset32 *regset;
941fcce4
DN		 940
941 /* DWC OTG HW Release versions */
942#define DWC2_CORE_REV_2_71a 0x4f54271a
943#define DWC2_CORE_REV_2_90a 0x4f54290a
944#define DWC2_CORE_REV_2_92a 0x4f54292a
945#define DWC2_CORE_REV_2_94a 0x4f54294a
946#define DWC2_CORE_REV_3_00a 0x4f54300a
fef6bc37 947#define DWC2_CORE_REV_3_10a 0x4f54310a
941fcce4
DN		 948
949#if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
56f5b1cf
PZ		 950 union dwc2_hcd_internal_flags {
951 u32 d32;
952 struct {
953 unsigned port_connect_status_change:1;
954 unsigned port_connect_status:1;
955 unsigned port_reset_change:1;
956 unsigned port_enable_change:1;
957 unsigned port_suspend_change:1;
958 unsigned port_over_current_change:1;
959 unsigned port_l1_change:1;
fd4850cf 960 unsigned reserved:25;
56f5b1cf
PZ		 961 } b;
962 } flags;
963
964 struct list_head non_periodic_sched_inactive;
965 struct list_head non_periodic_sched_active;
966 struct list_head *non_periodic_qh_ptr;
967 struct list_head periodic_sched_inactive;
968 struct list_head periodic_sched_ready;
969 struct list_head periodic_sched_assigned;
970 struct list_head periodic_sched_queued;
c9c8ac01 971 struct list_head split_order;
56f5b1cf 972 u16 periodic_usecs;
9f9f09b0
DA		 973 unsigned long hs_periodic_bitmap[
974 DIV_ROUND_UP(DWC2_HS_SCHEDULE_US, BITS_PER_LONG)];
56f5b1cf
PZ		 975 u16 frame_number;
976 u16 periodic_qh_count;
734643df 977 bool bus_suspended;
fbb9e22b 978 bool new_connection;
56f5b1cf 979
483bb254
DA		 980 u16 last_frame_num;
981
56f5b1cf
PZ		 982#ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
983#define FRAME_NUM_ARRAY_SIZE 1000
56f5b1cf
PZ		 984 u16 *frame_num_array;
985 u16 *last_frame_num_array;
986 int frame_num_idx;
987 int dumped_frame_num_array;
988#endif
989
990 struct list_head free_hc_list;
991 int periodic_channels;
992 int non_periodic_channels;
20f2eb9c 993 int available_host_channels;
56f5b1cf
PZ		 994 struct dwc2_host_chan *hc_ptr_array[MAX_EPS_CHANNELS];
995 u8 *status_buf;
996 dma_addr_t status_buf_dma;
997#define DWC2_HCD_STATUS_BUF_SIZE 64
998
999 struct delayed_work start_work;
1000 struct delayed_work reset_work;
56f5b1cf
PZ		 1001 u8 otg_port;
1002 u32 *frame_list;
1003 dma_addr_t frame_list_dma;
95105a99 1004 u32 frame_list_sz;
3b5fcc9a
GH		 1005 struct kmem_cache *desc_gen_cache;
1006 struct kmem_cache *desc_hsisoc_cache;
56f5b1cf 1007
56f5b1cf
PZ		 1008#ifdef DEBUG
1009 u32 frrem_samples;
1010 u64 frrem_accum;
1011
1012 u32 hfnum_7_samples_a;
1013 u64 hfnum_7_frrem_accum_a;
1014 u32 hfnum_0_samples_a;
1015 u64 hfnum_0_frrem_accum_a;
1016 u32 hfnum_other_samples_a;
1017 u64 hfnum_other_frrem_accum_a;
1018
1019 u32 hfnum_7_samples_b;
1020 u64 hfnum_7_frrem_accum_b;
1021 u32 hfnum_0_samples_b;
1022 u64 hfnum_0_frrem_accum_b;
1023 u32 hfnum_other_samples_b;
1024 u64 hfnum_other_frrem_accum_b;
1025#endif
941fcce4
DN		 1026#endif /* CONFIG_USB_DWC2_HOST || CONFIG_USB_DWC2_DUAL_ROLE */
1027
1028#if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
1029 /* Gadget structures */
1030 struct usb_gadget_driver *driver;
941fcce4
DN		 1031 int fifo_mem;
1032 unsigned int dedicated_fifos:1;
1033 unsigned char num_of_eps;
1034 u32 fifo_map;
1035
1036 struct usb_request *ep0_reply;
1037 struct usb_request *ctrl_req;
3f95001d
MYK		 1038 void *ep0_buff;
1039 void *ctrl_buff;
fe0b94ab 1040 enum dwc2_ep0_state ep0_state;
9e14d0a5 1041 u8 test_mode;
941fcce4 1042
0f6b80c0
VA		 1043 dma_addr_t setup_desc_dma[2];
1044 struct dwc2_dma_desc *setup_desc[2];
1045 dma_addr_t ctrl_in_desc_dma;
1046 struct dwc2_dma_desc *ctrl_in_desc;
1047 dma_addr_t ctrl_out_desc_dma;
1048 struct dwc2_dma_desc *ctrl_out_desc;
1049
941fcce4 1050 struct usb_gadget gadget;
dc6e69e6 1051 unsigned int enabled:1;
4ace06e8 1052 unsigned int connected:1;
1f91b4cc
FB		 1053 struct dwc2_hsotg_ep *eps_in[MAX_EPS_CHANNELS];
1054 struct dwc2_hsotg_ep *eps_out[MAX_EPS_CHANNELS];
941fcce4 1055#endif /* CONFIG_USB_DWC2_PERIPHERAL || CONFIG_USB_DWC2_DUAL_ROLE */
56f5b1cf
PZ		 1056};
1057
1058/* Reasons for halting a host channel */
1059enum dwc2_halt_status {
1060 DWC2_HC_XFER_NO_HALT_STATUS,
1061 DWC2_HC_XFER_COMPLETE,
1062 DWC2_HC_XFER_URB_COMPLETE,
1063 DWC2_HC_XFER_ACK,
1064 DWC2_HC_XFER_NAK,
1065 DWC2_HC_XFER_NYET,
1066 DWC2_HC_XFER_STALL,
1067 DWC2_HC_XFER_XACT_ERR,
1068 DWC2_HC_XFER_FRAME_OVERRUN,
1069 DWC2_HC_XFER_BABBLE_ERR,
1070 DWC2_HC_XFER_DATA_TOGGLE_ERR,
1071 DWC2_HC_XFER_AHB_ERR,
1072 DWC2_HC_XFER_PERIODIC_INCOMPLETE,
1073 DWC2_HC_XFER_URB_DEQUEUE,
1074};
1075
1076/*
1077 * The following functions support initialization of the core driver component
1078 * and the DWC_otg controller
1079 */
b5d308ab 1080extern int dwc2_core_reset(struct dwc2_hsotg *hsotg);
6d58f346 1081extern int dwc2_core_reset_and_force_dr_mode(struct dwc2_hsotg *hsotg);
d17ee77b
GH		 1082extern int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg);
1083extern int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, bool restore);
56f5b1cf 1084
323230ef
JY		 1085bool dwc2_force_mode_if_needed(struct dwc2_hsotg *hsotg, bool host);
1086void dwc2_clear_force_mode(struct dwc2_hsotg *hsotg);
09c96980
JY		 1087void dwc2_force_dr_mode(struct dwc2_hsotg *hsotg);
1088
057715f2 1089extern bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg);
56f5b1cf
PZ		 1090
1091/*
1092 * Common core Functions.
1093 * The following functions support managing the DWC_otg controller in either
1094 * device or host mode.
1095 */
1096extern void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes);
1097extern void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num);
1098extern void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg);
1099
56f5b1cf
PZ		 1100extern void dwc2_enable_global_interrupts(struct dwc2_hsotg *hcd);
1101extern void dwc2_disable_global_interrupts(struct dwc2_hsotg *hcd);
1102
1103/* This function should be called on every hardware interrupt. */
1104extern irqreturn_t dwc2_handle_common_intr(int irq, void *dev);
1105
323230ef
JY		 1106/* The device ID match table */
1107extern const struct of_device_id dwc2_of_match_table[];
1108
09a75e85
MS		 1109extern int dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg);
1110extern int dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg);
ecb176c6 1111
334bbd4e 1112/* Parameters */
c1d286cf 1113int dwc2_get_hwparams(struct dwc2_hsotg *hsotg);
334bbd4e
JY		 1114int dwc2_init_params(struct dwc2_hsotg *hsotg);
1115
6bea9620
JY		 1116/*
1117 * The following functions check the controller's OTG operation mode
1118 * capability (GHWCFG2.OTG_MODE).
1119 *
1120 * These functions can be used before the internal hsotg->hw_params
1121 * are read in and cached so they always read directly from the
1122 * GHWCFG2 register.
1123 */
1124unsigned dwc2_op_mode(struct dwc2_hsotg *hsotg);
1125bool dwc2_hw_is_otg(struct dwc2_hsotg *hsotg);
1126bool dwc2_hw_is_host(struct dwc2_hsotg *hsotg);
1127bool dwc2_hw_is_device(struct dwc2_hsotg *hsotg);
1128
1696d5ab
JY		 1129/*
1130 * Returns the mode of operation, host or device
1131 */
1132static inline int dwc2_is_host_mode(struct dwc2_hsotg *hsotg)
1133{
1134 return (dwc2_readl(hsotg->regs + GINTSTS) & GINTSTS_CURMODE_HOST) != 0;
1135}
1136static inline int dwc2_is_device_mode(struct dwc2_hsotg *hsotg)
1137{
1138 return (dwc2_readl(hsotg->regs + GINTSTS) & GINTSTS_CURMODE_HOST) == 0;
1139}
1140
56f5b1cf
PZ		 1141/*
1142 * Dump core registers and SPRAM
1143 */
1144extern void dwc2_dump_dev_registers(struct dwc2_hsotg *hsotg);
1145extern void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg);
1146extern void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg);
1147
1148/*
1149 * Return OTG version - either 1.3 or 2.0
1150 */
1151extern u16 dwc2_get_otg_version(struct dwc2_hsotg *hsotg);
1152
117777b2
DN		 1153/* Gadget defines */
1154#if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
1f91b4cc
FB		 1155extern int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg);
1156extern int dwc2_hsotg_suspend(struct dwc2_hsotg *dwc2);
1157extern int dwc2_hsotg_resume(struct dwc2_hsotg *dwc2);
117777b2 1158extern int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq);
1f91b4cc 1159extern void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2,
643cc4de 1160 bool reset);
1f91b4cc
FB		 1161extern void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg);
1162extern void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2);
1163extern int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode);
f81f46e1 1164#define dwc2_is_device_connected(hsotg) (hsotg->connected)
58e52ff6
JY		 1165int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg);
1166int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg);
117777b2 1167#else
1f91b4cc 1168static inline int dwc2_hsotg_remove(struct dwc2_hsotg *dwc2)
117777b2 1169{ return 0; }
1f91b4cc 1170static inline int dwc2_hsotg_suspend(struct dwc2_hsotg *dwc2)
117777b2 1171{ return 0; }
1f91b4cc 1172static inline int dwc2_hsotg_resume(struct dwc2_hsotg *dwc2)
117777b2
DN		 1173{ return 0; }
1174static inline int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq)
1175{ return 0; }
1f91b4cc 1176static inline void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2,
643cc4de 1177 bool reset) {}
1f91b4cc
FB		 1178static inline void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg) {}
1179static inline void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2) {}
1180static inline int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg,
f91eea44
MYK		 1181 int testmode)
1182{ return 0; }
f81f46e1 1183#define dwc2_is_device_connected(hsotg) (0)
58e52ff6
JY		 1184static inline int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg)
1185{ return 0; }
1186static inline int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg)
1187{ return 0; }
117777b2
DN		 1188#endif
1189
1190#if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
1191extern int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg);
fae4e826 1192extern int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg, int us);
6a659531
DA		 1193extern void dwc2_hcd_connect(struct dwc2_hsotg *hsotg);
1194extern void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force);
117777b2 1195extern void dwc2_hcd_start(struct dwc2_hsotg *hsotg);
58e52ff6
JY		 1196int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg);
1197int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg);
117777b2 1198#else
117777b2
DN		 1199static inline int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg)
1200{ return 0; }
fae4e826
DA		 1201static inline int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg,
1202 int us)
1203{ return 0; }
6a659531
DA		 1204static inline void dwc2_hcd_connect(struct dwc2_hsotg *hsotg) {}
1205static inline void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force) {}
117777b2
DN		 1206static inline void dwc2_hcd_start(struct dwc2_hsotg *hsotg) {}
1207static inline void dwc2_hcd_remove(struct dwc2_hsotg *hsotg) {}
ecb176c6 1208static inline int dwc2_hcd_init(struct dwc2_hsotg *hsotg, int irq)
117777b2 1209{ return 0; }
58e52ff6
JY		 1210static inline int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg)
1211{ return 0; }
1212static inline int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg)
1213{ return 0; }
1214
117777b2
DN		 1215#endif
1216
56f5b1cf 1217#endif /* __DWC2_CORE_H__ */
Linux 6.x block layer and io_uring tree(s)