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usb: dwc2: Add host partial power down functions
[linux-block.git] / drivers / usb / dwc2 / core.h
CommitLineData
bdefa3ba 1/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
56f5b1cf
PZ		 2/*
3 * core.h - DesignWare HS OTG Controller common declarations
4 *
5 * Copyright (C) 2004-2013 Synopsys, Inc.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions, and the following disclaimer,
12 * without modification.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. The names of the above-listed copyright holders may not be used
17 * to endorse or promote products derived from this software without
18 * specific prior written permission.
19 *
20 * ALTERNATIVELY, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") as published by the Free Software
22 * Foundation; either version 2 of the License, or (at your option) any
23 * later version.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
26 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
27 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
29 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
30 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
31 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
32 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
33 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
34 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
35 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 */
37
38#ifndef __DWC2_CORE_H__
39#define __DWC2_CORE_H__
40
f7c0b143
DN		 41#include <linux/phy/phy.h>
42#include <linux/regulator/consumer.h>
43#include <linux/usb/gadget.h>
44#include <linux/usb/otg.h>
56f5b1cf
PZ		 45#include <linux/usb/phy.h>
46#include "hw.h"
47
74fc4a75
DA		 48/*
49 * Suggested defines for tracers:
50 * - no_printk: Disable tracing
51 * - pr_info: Print this info to the console
52 * - trace_printk: Print this info to trace buffer (good for verbose logging)
53 */
54
55#define DWC2_TRACE_SCHEDULER no_printk
56#define DWC2_TRACE_SCHEDULER_VB no_printk
57
58/* Detailed scheduler tracing, but won't overwhelm console */
59#define dwc2_sch_dbg(hsotg, fmt, ...) \
60 DWC2_TRACE_SCHEDULER(pr_fmt("%s: SCH: " fmt), \
61 dev_name(hsotg->dev), ##__VA_ARGS__)
62
63/* Verbose scheduler tracing */
64#define dwc2_sch_vdbg(hsotg, fmt, ...) \
65 DWC2_TRACE_SCHEDULER_VB(pr_fmt("%s: SCH: " fmt), \
66 dev_name(hsotg->dev), ##__VA_ARGS__)
67
56f5b1cf
PZ		 68/* Maximum number of Endpoints/HostChannels */
69#define MAX_EPS_CHANNELS 16
70
1f91b4cc
FB		 71/* dwc2-hsotg declarations */
72static const char * const dwc2_hsotg_supply_names[] = {
f7c0b143
DN		 73 "vusb_d", /* digital USB supply, 1.2V */
74 "vusb_a", /* analog USB supply, 1.1V */
75};
76
b98866c2
JY		 77#define DWC2_NUM_SUPPLIES ARRAY_SIZE(dwc2_hsotg_supply_names)
78
f7c0b143
DN		 79/*
80 * EP0_MPS_LIMIT
81 *
82 * Unfortunately there seems to be a limit of the amount of data that can
83 * be transferred by IN transactions on EP0. This is either 127 bytes or 3
84 * packets (which practically means 1 packet and 63 bytes of data) when the
85 * MPS is set to 64.
86 *
87 * This means if we are wanting to move >127 bytes of data, we need to
88 * split the transactions up, but just doing one packet at a time does
89 * not work (this may be an implicit DATA0 PID on first packet of the
90 * transaction) and doing 2 packets is outside the controller's limits.
91 *
92 * If we try to lower the MPS size for EP0, then no transfers work properly
93 * for EP0, and the system will fail basic enumeration. As no cause for this
94 * has currently been found, we cannot support any large IN transfers for
95 * EP0.
96 */
97#define EP0_MPS_LIMIT 64
98
941fcce4 99struct dwc2_hsotg;
1f91b4cc 100struct dwc2_hsotg_req;
f7c0b143
DN		 101
102/**
1f91b4cc 103 * struct dwc2_hsotg_ep - driver endpoint definition.
f7c0b143
DN		 104 * @ep: The gadget layer representation of the endpoint.
105 * @name: The driver generated name for the endpoint.
106 * @queue: Queue of requests for this endpoint.
107 * @parent: Reference back to the parent device structure.
108 * @req: The current request that the endpoint is processing. This is
109 * used to indicate an request has been loaded onto the endpoint
110 * and has yet to be completed (maybe due to data move, or simply
111 * awaiting an ack from the core all the data has been completed).
112 * @debugfs: File entry for debugfs file for this endpoint.
f7c0b143
DN		 113 * @dir_in: Set to true if this endpoint is of the IN direction, which
114 * means that it is sending data to the Host.
115 * @index: The index for the endpoint registers.
116 * @mc: Multi Count - number of transactions per microframe
6fb914d7 117 * @interval: Interval for periodic endpoints, in frames or microframes.
f7c0b143
DN		 118 * @name: The name array passed to the USB core.
119 * @halted: Set if the endpoint has been halted.
120 * @periodic: Set if this is a periodic ep, such as Interrupt
121 * @isochronous: Set if this is a isochronous ep
8a20fa45 122 * @send_zlp: Set if we need to send a zero-length packet.
5f54c54b
VA		 123 * @desc_list_dma: The DMA address of descriptor chain currently in use.
124 * @desc_list: Pointer to descriptor DMA chain head currently in use.
125 * @desc_count: Count of entries within the DMA descriptor chain of EP.
ab7d2192 126 * @next_desc: index of next free descriptor in the ISOC chain under SW control.
729cac69 127 * @compl_desc: index of next descriptor to be completed by xFerComplete
f7c0b143
DN		 128 * @total_data: The total number of data bytes done.
129 * @fifo_size: The size of the FIFO (for periodic IN endpoints)
6fb914d7 130 * @fifo_index: For Dedicated FIFO operation, only FIFO0 can be used for EP0.
f7c0b143
DN		 131 * @fifo_load: The amount of data loaded into the FIFO (periodic IN)
132 * @last_load: The offset of data for the last start of request.
133 * @size_loaded: The last loaded size for DxEPTSIZE for periodic IN
92d1635d
VM		 134 * @target_frame: Targeted frame num to setup next ISOC transfer
135 * @frame_overrun: Indicates SOF number overrun in DSTS
f7c0b143 136 *
c1aa81da 137 * This is the driver's state for each registered endpoint, allowing it
f7c0b143
DN		 138 * to keep track of transactions that need doing. Each endpoint has a
139 * lock to protect the state, to try and avoid using an overall lock
140 * for the host controller as much as possible.
141 *
142 * For periodic IN endpoints, we have fifo_size and fifo_load to try
143 * and keep track of the amount of data in the periodic FIFO for each
144 * of these as we don't have a status register that tells us how much
145 * is in each of them. (note, this may actually be useless information
146 * as in shared-fifo mode periodic in acts like a single-frame packet
147 * buffer than a fifo)
148 */
1f91b4cc 149struct dwc2_hsotg_ep {
f7c0b143
DN		 150 struct usb_ep ep;
151 struct list_head queue;
941fcce4 152 struct dwc2_hsotg *parent;
1f91b4cc 153 struct dwc2_hsotg_req *req;
f7c0b143
DN		 154 struct dentry *debugfs;
155
156 unsigned long total_data;
157 unsigned int size_loaded;
158 unsigned int last_load;
159 unsigned int fifo_load;
160 unsigned short fifo_size;
b203d0a2 161 unsigned short fifo_index;
f7c0b143
DN		 162
163 unsigned char dir_in;
164 unsigned char index;
165 unsigned char mc;
12814a3f 166 u16 interval;
f7c0b143
DN		 167
168 unsigned int halted:1;
169 unsigned int periodic:1;
170 unsigned int isochronous:1;
8a20fa45 171 unsigned int send_zlp:1;
92d1635d
VM		 172 unsigned int target_frame;
173#define TARGET_FRAME_INITIAL 0xFFFFFFFF
174 bool frame_overrun;
f7c0b143 175
5f54c54b
VA		 176 dma_addr_t desc_list_dma;
177 struct dwc2_dma_desc *desc_list;
178 u8 desc_count;
179
ab7d2192 180 unsigned int next_desc;
729cac69 181 unsigned int compl_desc;
ab7d2192 182
f7c0b143
DN		 183 char name[10];
184};
185
f7c0b143 186/**
1f91b4cc 187 * struct dwc2_hsotg_req - data transfer request
f7c0b143
DN		 188 * @req: The USB gadget request
189 * @queue: The list of requests for the endpoint this is queued for.
7d24c1b5 190 * @saved_req_buf: variable to save req.buf when bounce buffers are used.
f7c0b143 191 */
1f91b4cc 192struct dwc2_hsotg_req {
f7c0b143
DN		 193 struct usb_request req;
194 struct list_head queue;
7d24c1b5 195 void *saved_req_buf;
f7c0b143
DN		 196};
197
b98866c2
JY		 198#if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \
199 IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
f7c0b143
DN		 200#define call_gadget(_hs, _entry) \
201do { \
202 if ((_hs)->gadget.speed != USB_SPEED_UNKNOWN && \
203 (_hs)->driver && (_hs)->driver->_entry) { \
204 spin_unlock(&_hs->lock); \
205 (_hs)->driver->_entry(&(_hs)->gadget); \
206 spin_lock(&_hs->lock); \
207 } \
208} while (0)
941fcce4
DN		 209#else
210#define call_gadget(_hs, _entry) do {} while (0)
211#endif
f7c0b143 212
56f5b1cf
PZ		 213struct dwc2_hsotg;
214struct dwc2_host_chan;
215
216/* Device States */
217enum dwc2_lx_state {
218 DWC2_L0, /* On state */
219 DWC2_L1, /* LPM sleep state */
220 DWC2_L2, /* USB suspend state */
221 DWC2_L3, /* Off state */
222};
223
fe0b94ab
MYK		 224/* Gadget ep0 states */
225enum dwc2_ep0_state {
226 DWC2_EP0_SETUP,
227 DWC2_EP0_DATA_IN,
228 DWC2_EP0_DATA_OUT,
229 DWC2_EP0_STATUS_IN,
230 DWC2_EP0_STATUS_OUT,
231};
232
56f5b1cf
PZ		 233/**
234 * struct dwc2_core_params - Parameters for configuring the core
235 *
91121c10
MK		 236 * @otg_cap: Specifies the OTG capabilities.
237 * 0 - HNP and SRP capable
56f5b1cf 238 * 1 - SRP Only capable
91121c10
MK		 239 * 2 - No HNP/SRP capable (always available)
240 * Defaults to best available option (0, 1, then 2)
e7839f99 241 * @host_dma: Specifies whether to use slave or DMA mode for accessing
56f5b1cf
PZ		 242 * the data FIFOs. The driver will automatically detect the
243 * value for this parameter if none is specified.
91121c10 244 * 0 - Slave (always available)
56f5b1cf
PZ		 245 * 1 - DMA (default, if available)
246 * @dma_desc_enable: When DMA mode is enabled, specifies whether to use
247 * address DMA mode or descriptor DMA mode for accessing
248 * the data FIFOs. The driver will automatically detect the
249 * value for this if none is specified.
250 * 0 - Address DMA
251 * 1 - Descriptor DMA (default, if available)
fbb9e22b
MYK		 252 * @dma_desc_fs_enable: When DMA mode is enabled, specifies whether to use
253 * address DMA mode or descriptor DMA mode for accessing
254 * the data FIFOs in Full Speed mode only. The driver
255 * will automatically detect the value for this if none is
256 * specified.
257 * 0 - Address DMA
258 * 1 - Descriptor DMA in FS (default, if available)
56f5b1cf
PZ		 259 * @speed: Specifies the maximum speed of operation in host and
260 * device mode. The actual speed depends on the speed of
261 * the attached device and the value of phy_type.
91121c10
MK		 262 * 0 - High Speed
263 * (default when phy_type is UTMI+ or ULPI)
56f5b1cf 264 * 1 - Full Speed
91121c10 265 * (default when phy_type is Full Speed)
56f5b1cf 266 * @enable_dynamic_fifo: 0 - Use coreConsultant-specified FIFO size parameters
91121c10 267 * 1 - Allow dynamic FIFO sizing (default, if available)
725acc86 268 * @en_multiple_tx_fifo: Specifies whether dedicated per-endpoint transmit FIFOs
c1d286cf
JY		 269 * are enabled for non-periodic IN endpoints in device
270 * mode.
56f5b1cf
PZ		 271 * @host_rx_fifo_size: Number of 4-byte words in the Rx FIFO in host mode when
272 * dynamic FIFO sizing is enabled
91121c10
MK		 273 * 16 to 32768
274 * Actual maximum value is autodetected and also
275 * the default.
56f5b1cf
PZ		 276 * @host_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO
277 * in host mode when dynamic FIFO sizing is enabled
91121c10
MK		 278 * 16 to 32768
279 * Actual maximum value is autodetected and also
280 * the default.
56f5b1cf
PZ		 281 * @host_perio_tx_fifo_size: Number of 4-byte words in the periodic Tx FIFO in
282 * host mode when dynamic FIFO sizing is enabled
91121c10
MK		 283 * 16 to 32768
284 * Actual maximum value is autodetected and also
285 * the default.
56f5b1cf 286 * @max_transfer_size: The maximum transfer size supported, in bytes
91121c10
MK		 287 * 2047 to 65,535
288 * Actual maximum value is autodetected and also
289 * the default.
56f5b1cf 290 * @max_packet_count: The maximum number of packets in a transfer
91121c10
MK		 291 * 15 to 511
292 * Actual maximum value is autodetected and also
293 * the default.
56f5b1cf 294 * @host_channels: The number of host channel registers to use
91121c10
MK		 295 * 1 to 16
296 * Actual maximum value is autodetected and also
297 * the default.
56f5b1cf
PZ		 298 * @phy_type: Specifies the type of PHY interface to use. By default,
299 * the driver will automatically detect the phy_type.
91121c10
MK		 300 * 0 - Full Speed Phy
301 * 1 - UTMI+ Phy
302 * 2 - ULPI Phy
303 * Defaults to best available option (2, 1, then 0)
56f5b1cf
PZ		 304 * @phy_utmi_width: Specifies the UTMI+ Data Width (in bits). This parameter
305 * is applicable for a phy_type of UTMI+ or ULPI. (For a
306 * ULPI phy_type, this parameter indicates the data width
307 * between the MAC and the ULPI Wrapper.) Also, this
308 * parameter is applicable only if the OTG_HSPHY_WIDTH cC
309 * parameter was set to "8 and 16 bits", meaning that the
310 * core has been configured to work at either data path
311 * width.
91121c10 312 * 8 or 16 (default 16 if available)
56f5b1cf
PZ		 313 * @phy_ulpi_ddr: Specifies whether the ULPI operates at double or single
314 * data rate. This parameter is only applicable if phy_type
315 * is ULPI.
316 * 0 - single data rate ULPI interface with 8 bit wide
317 * data bus (default)
318 * 1 - double data rate ULPI interface with 4 bit wide
319 * data bus
320 * @phy_ulpi_ext_vbus: For a ULPI phy, specifies whether to use the internal or
321 * external supply to drive the VBus
91121c10
MK		 322 * 0 - Internal supply (default)
323 * 1 - External supply
56f5b1cf
PZ		 324 * @i2c_enable: Specifies whether to use the I2Cinterface for a full
325 * speed PHY. This parameter is only applicable if phy_type
326 * is FS.
327 * 0 - No (default)
328 * 1 - Yes
6fb914d7 329 * @ipg_isoc_en: Indicates the IPG supports is enabled or disabled.
b43ebc96
GT		 330 * 0 - Disable (default)
331 * 1 - Enable
6fb914d7
GT		 332 * @acg_enable: For enabling Active Clock Gating in the controller
333 * 0 - No
334 * 1 - Yes
91121c10
MK		 335 * @ulpi_fs_ls: Make ULPI phy operate in FS/LS mode only
336 * 0 - No (default)
337 * 1 - Yes
725acc86
PZ		 338 * @host_support_fs_ls_low_power: Specifies whether low power mode is supported
339 * when attached to a Full Speed or Low Speed device in
340 * host mode.
341 * 0 - Don't support low power mode (default)
342 * 1 - Support low power mode
343 * @host_ls_low_power_phy_clk: Specifies the PHY clock rate in low power mode
91121c10
MK		 344 * when connected to a Low Speed device in host
345 * mode. This parameter is applicable only if
346 * host_support_fs_ls_low_power is enabled.
725acc86 347 * 0 - 48 MHz
91121c10 348 * (default when phy_type is UTMI+ or ULPI)
725acc86 349 * 1 - 6 MHz
91121c10 350 * (default when phy_type is Full Speed)
b11633c4
DN		 351 * @oc_disable: Flag to disable overcurrent condition.
352 * 0 - Allow overcurrent condition to get detected
353 * 1 - Disable overcurrent condtion to get detected
91121c10
MK		 354 * @ts_dline: Enable Term Select Dline pulsing
355 * 0 - No (default)
356 * 1 - Yes
357 * @reload_ctl: Allow dynamic reloading of HFIR register during runtime
358 * 0 - No (default for core < 2.92a)
359 * 1 - Yes (default for core >= 2.92a)
4d3190e1
PZ		 360 * @ahbcfg: This field allows the default value of the GAHBCFG
361 * register to be overridden
91121c10 362 * -1 - GAHBCFG value will be set to 0x06
1b52d2fa 363 * (INCR, default)
4d3190e1
PZ		 364 * all others - GAHBCFG value will be overridden with
365 * this value
91121c10
MK		 366 * Not all bits can be controlled like this, the
367 * bits defined by GAHBCFG_CTRL_MASK are controlled
368 * by the driver and are ignored in this
369 * configuration value.
20f2eb9c 370 * @uframe_sched: True to enable the microframe scheduler
a6d249d8
GH		 371 * @external_id_pin_ctl: Specifies whether ID pin is handled externally.
372 * Disable CONIDSTSCHNG controller interrupt in such
373 * case.
374 * 0 - No (default)
375 * 1 - Yes
41ba9b9b
VM		 376 * @power_down: Specifies whether the controller support power_down.
377 * If power_down is enabled, the controller will enter
378 * power_down in both peripheral and host mode when
285046aa
GH		 379 * needed.
380 * 0 - No (default)
631a2310
VM		 381 * 1 - Partial power down
382 * 2 - Hibernation
6f80b6de
SA		 383 * @lpm: Enable LPM support.
384 * 0 - No
385 * 1 - Yes
386 * @lpm_clock_gating: Enable core PHY clock gating.
387 * 0 - No
388 * 1 - Yes
389 * @besl: Enable LPM Errata support.
390 * 0 - No
391 * 1 - Yes
392 * @hird_threshold_en: HIRD or HIRD Threshold enable.
393 * 0 - No
394 * 1 - Yes
395 * @hird_threshold: Value of BESL or HIRD Threshold.
f3a61e4e
GT		 396 * @ref_clk_per: Indicates in terms of pico seconds the period
397 * of ref_clk.
398 * 62500 - 16MHz
399 * 58823 - 17MHz
400 * 52083 - 19.2MHz
401 * 50000 - 20MHz
402 * 41666 - 24MHz
403 * 33333 - 30MHz (default)
404 * 25000 - 40MHz
405 * @sof_cnt_wkup_alert: Indicates in term of number of SOF's after which
406 * the controller should generate an interrupt if the
407 * device had been in L1 state until that period.
408 * This is used by SW to initiate Remote WakeUp in the
409 * controller so as to sync to the uF number from the host.
e35b1350
BH		 410 * @activate_stm_fs_transceiver: Activate internal transceiver using GGPIO
411 * register.
412 * 0 - Deactivate the transceiver (default)
413 * 1 - Activate the transceiver
a415083a
AD		 414 * @activate_stm_id_vb_detection: Activate external ID pin and Vbus level
415 * detection using GGPIO register.
416 * 0 - Deactivate the external level detection (default)
417 * 1 - Activate the external level detection
9962b62f 418 * @g_dma: Enables gadget dma usage (default: autodetect).
dec4b556 419 * @g_dma_desc: Enables gadget descriptor DMA (default: autodetect).
05ee799f
JY		 420 * @g_rx_fifo_size: The periodic rx fifo size for the device, in
421 * DWORDS from 16-32768 (default: 2048 if
422 * possible, otherwise autodetect).
423 * @g_np_tx_fifo_size: The non-periodic tx fifo size for the device in
424 * DWORDS from 16-32768 (default: 1024 if
425 * possible, otherwise autodetect).
426 * @g_tx_fifo_size: An array of TX fifo sizes in dedicated fifo
427 * mode. Each value corresponds to one EP
428 * starting from EP1 (max 15 values). Sizes are
f8590006 429 * in DWORDS with possible values from
05ee799f
JY		 430 * 16-32768 (default: 256, 256, 256, 256, 768,
431 * 768, 768, 768, 0, 0, 0, 0, 0, 0, 0).
ca8b0332
CY		 432 * @change_speed_quirk: Change speed configuration to DWC2_SPEED_PARAM_FULL
433 * while full&low speed device connect. And change speed
434 * back to DWC2_SPEED_PARAM_HIGH while device is gone.
435 * 0 - No (default)
436 * 1 - Yes
ca531bc2
GT		 437 * @service_interval: Enable service interval based scheduling.
438 * 0 - No
439 * 1 - Yes
56f5b1cf
PZ		 440 *
441 * The following parameters may be specified when starting the module. These
91121c10
MK		 442 * parameters define how the DWC_otg controller should be configured. A
443 * value of -1 (or any other out of range value) for any parameter means
444 * to read the value from hardware (if possible) or use the builtin
445 * default described above.
56f5b1cf
PZ		 446 */
447struct dwc2_core_params {
d21bcc3f 448 u8 otg_cap;
c1d286cf
JY		 449#define DWC2_CAP_PARAM_HNP_SRP_CAPABLE 0
450#define DWC2_CAP_PARAM_SRP_ONLY_CAPABLE 1
451#define DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE 2
452
d21bcc3f 453 u8 phy_type;
c1d286cf
JY		 454#define DWC2_PHY_TYPE_PARAM_FS 0
455#define DWC2_PHY_TYPE_PARAM_UTMI 1
456#define DWC2_PHY_TYPE_PARAM_ULPI 2
457
57b8e235
JY		 458 u8 speed;
459#define DWC2_SPEED_PARAM_HIGH 0
460#define DWC2_SPEED_PARAM_FULL 1
461#define DWC2_SPEED_PARAM_LOW 2
462
d21bcc3f
JY		 463 u8 phy_utmi_width;
464 bool phy_ulpi_ddr;
465 bool phy_ulpi_ext_vbus;
57b8e235
JY		 466 bool enable_dynamic_fifo;
467 bool en_multiple_tx_fifo;
d21bcc3f 468 bool i2c_enable;
66e77a24 469 bool acg_enable;
d21bcc3f 470 bool ulpi_fs_ls;
d21bcc3f
JY		 471 bool ts_dline;
472 bool reload_ctl;
d21bcc3f
JY		 473 bool uframe_sched;
474 bool external_id_pin_ctl;
631a2310
VM		 475
476 int power_down;
477#define DWC2_POWER_DOWN_PARAM_NONE 0
478#define DWC2_POWER_DOWN_PARAM_PARTIAL 1
479#define DWC2_POWER_DOWN_PARAM_HIBERNATION 2
480
6f80b6de
SA		 481 bool lpm;
482 bool lpm_clock_gating;
483 bool besl;
484 bool hird_threshold_en;
ca531bc2 485 bool service_interval;
6f80b6de 486 u8 hird_threshold;
e35b1350 487 bool activate_stm_fs_transceiver;
a415083a 488 bool activate_stm_id_vb_detection;
b43ebc96 489 bool ipg_isoc_en;
57b8e235
JY		 490 u16 max_packet_count;
491 u32 max_transfer_size;
492 u32 ahbcfg;
6b66ce51 493
f3a61e4e
GT		 494 /* GREFCLK parameters */
495 u32 ref_clk_per;
496 u16 sof_cnt_wkup_alert;
497
6b66ce51
JY		 498 /* Host parameters */
499 bool host_dma;
57b8e235
JY		 500 bool dma_desc_enable;
501 bool dma_desc_fs_enable;
502 bool host_support_fs_ls_low_power;
503 bool host_ls_low_power_phy_clk;
b11633c4 504 bool oc_disable;
57b8e235
JY		 505
506 u8 host_channels;
507 u16 host_rx_fifo_size;
508 u16 host_nperio_tx_fifo_size;
509 u16 host_perio_tx_fifo_size;
6b66ce51
JY		 510
511 /* Gadget parameters */
05ee799f 512 bool g_dma;
dec4b556 513 bool g_dma_desc;
00c704cc
LY		 514 u32 g_rx_fifo_size;
515 u32 g_np_tx_fifo_size;
05ee799f 516 u32 g_tx_fifo_size[MAX_EPS_CHANNELS];
ca8b0332
CY		 517
518 bool change_speed_quirk;
56f5b1cf
PZ		 519};
520
9badec2f
MK		 521/**
522 * struct dwc2_hw_params - Autodetected parameters.
523 *
524 * These parameters are the various parameters read from hardware
525 * registers during initialization. They typically contain the best
526 * supported or maximum value that can be configured in the
527 * corresponding dwc2_core_params value.
528 *
529 * The values that are not in dwc2_core_params are documented below.
530 *
6fb914d7 531 * @op_mode: Mode of Operation
9badec2f
MK		 532 * 0 - HNP- and SRP-Capable OTG (Host & Device)
533 * 1 - SRP-Capable OTG (Host & Device)
534 * 2 - Non-HNP and Non-SRP Capable OTG (Host & Device)
535 * 3 - SRP-Capable Device
536 * 4 - Non-OTG Device
537 * 5 - SRP-Capable Host
538 * 6 - Non-OTG Host
6fb914d7 539 * @arch: Architecture
9badec2f
MK		 540 * 0 - Slave only
541 * 1 - External DMA
542 * 2 - Internal DMA
6fb914d7 543 * @ipg_isoc_en: This feature indicates that the controller supports
b43ebc96
GT		 544 * the worst-case scenario of Rx followed by Rx
545 * Interpacket Gap (IPG) (32 bitTimes) as per the utmi
546 * specification for any token following ISOC OUT token.
547 * 0 - Don't support
548 * 1 - Support
6fb914d7
GT		 549 * @power_optimized: Are power optimizations enabled?
550 * @num_dev_ep: Number of device endpoints available
551 * @num_dev_in_eps: Number of device IN endpoints available
552 * @num_dev_perio_in_ep: Number of device periodic IN endpoints
553 * available
554 * @dev_token_q_depth: Device Mode IN Token Sequence Learning Queue
9badec2f
MK		 555 * Depth
556 * 0 to 30
6fb914d7 557 * @host_perio_tx_q_depth:
9badec2f
MK		 558 * Host Mode Periodic Request Queue Depth
559 * 2, 4 or 8
6fb914d7 560 * @nperio_tx_q_depth:
9badec2f
MK		 561 * Non-Periodic Request Queue Depth
562 * 2, 4 or 8
6fb914d7 563 * @hs_phy_type: High-speed PHY interface type
9badec2f
MK		 564 * 0 - High-speed interface not supported
565 * 1 - UTMI+
566 * 2 - ULPI
567 * 3 - UTMI+ and ULPI
6fb914d7 568 * @fs_phy_type: Full-speed PHY interface type
9badec2f
MK		 569 * 0 - Full speed interface not supported
570 * 1 - Dedicated full speed interface
571 * 2 - FS pins shared with UTMI+ pins
572 * 3 - FS pins shared with ULPI pins
573 * @total_fifo_size: Total internal RAM for FIFOs (bytes)
6fb914d7
GT		 574 * @hibernation: Is hibernation enabled?
575 * @utmi_phy_data_width: UTMI+ PHY data width
de4a1931
MK		 576 * 0 - 8 bits
577 * 1 - 16 bits
578 * 2 - 8 or 16 bits
9badec2f 579 * @snpsid: Value from SNPSID register
55e1040e 580 * @dev_ep_dirs: Direction of device endpoints (GHWCFG1)
6fb914d7
GT		 581 * @g_tx_fifo_size: Power-on values of TxFIFO sizes
582 * @dma_desc_enable: When DMA mode is enabled, specifies whether to use
583 * address DMA mode or descriptor DMA mode for accessing
584 * the data FIFOs. The driver will automatically detect the
585 * value for this if none is specified.
586 * 0 - Address DMA
587 * 1 - Descriptor DMA (default, if available)
588 * @enable_dynamic_fifo: 0 - Use coreConsultant-specified FIFO size parameters
589 * 1 - Allow dynamic FIFO sizing (default, if available)
590 * @en_multiple_tx_fifo: Specifies whether dedicated per-endpoint transmit FIFOs
591 * are enabled for non-periodic IN endpoints in device
592 * mode.
593 * @host_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO
594 * in host mode when dynamic FIFO sizing is enabled
595 * 16 to 32768
596 * Actual maximum value is autodetected and also
597 * the default.
598 * @host_perio_tx_fifo_size: Number of 4-byte words in the periodic Tx FIFO in
599 * host mode when dynamic FIFO sizing is enabled
600 * 16 to 32768
601 * Actual maximum value is autodetected and also
602 * the default.
603 * @max_transfer_size: The maximum transfer size supported, in bytes
604 * 2047 to 65,535
605 * Actual maximum value is autodetected and also
606 * the default.
607 * @max_packet_count: The maximum number of packets in a transfer
608 * 15 to 511
609 * Actual maximum value is autodetected and also
610 * the default.
611 * @host_channels: The number of host channel registers to use
612 * 1 to 16
613 * Actual maximum value is autodetected and also
614 * the default.
615 * @dev_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO
616 * in device mode when dynamic FIFO sizing is enabled
617 * 16 to 32768
618 * Actual maximum value is autodetected and also
619 * the default.
620 * @i2c_enable: Specifies whether to use the I2Cinterface for a full
621 * speed PHY. This parameter is only applicable if phy_type
622 * is FS.
623 * 0 - No (default)
624 * 1 - Yes
625 * @acg_enable: For enabling Active Clock Gating in the controller
626 * 0 - Disable
627 * 1 - Enable
628 * @lpm_mode: For enabling Link Power Management in the controller
629 * 0 - Disable
630 * 1 - Enable
631 * @rx_fifo_size: Number of 4-byte words in the Rx FIFO when dynamic
632 * FIFO sizing is enabled 16 to 32768
633 * Actual maximum value is autodetected and also
634 * the default.
ca531bc2
GT		 635 * @service_interval_mode: For enabling service interval based scheduling in the
636 * controller.
637 * 0 - Disable
638 * 1 - Enable
9badec2f
MK		 639 */
640struct dwc2_hw_params {
641 unsigned op_mode:3;
642 unsigned arch:2;
643 unsigned dma_desc_enable:1;
644 unsigned enable_dynamic_fifo:1;
645 unsigned en_multiple_tx_fifo:1;
d1531319 646 unsigned rx_fifo_size:16;
9badec2f 647 unsigned host_nperio_tx_fifo_size:16;
55e1040e 648 unsigned dev_nperio_tx_fifo_size:16;
9badec2f
MK		 649 unsigned host_perio_tx_fifo_size:16;
650 unsigned nperio_tx_q_depth:3;
651 unsigned host_perio_tx_q_depth:3;
652 unsigned dev_token_q_depth:5;
653 unsigned max_transfer_size:26;
654 unsigned max_packet_count:11;
2d115547 655 unsigned host_channels:5;
9badec2f
MK		 656 unsigned hs_phy_type:2;
657 unsigned fs_phy_type:2;
658 unsigned i2c_enable:1;
66e77a24 659 unsigned acg_enable:1;
9badec2f 660 unsigned num_dev_ep:4;
9273083a 661 unsigned num_dev_in_eps : 4;
9badec2f
MK		 662 unsigned num_dev_perio_in_ep:4;
663 unsigned total_fifo_size:16;
664 unsigned power_optimized:1;
631a2310 665 unsigned hibernation:1;
de4a1931 666 unsigned utmi_phy_data_width:2;
6f80b6de 667 unsigned lpm_mode:1;
b43ebc96 668 unsigned ipg_isoc_en:1;
ca531bc2 669 unsigned service_interval_mode:1;
9badec2f 670 u32 snpsid;
55e1040e 671 u32 dev_ep_dirs;
9273083a 672 u32 g_tx_fifo_size[MAX_EPS_CHANNELS];
9badec2f
MK		 673};
674
3f95001d
MYK		 675/* Size of control and EP0 buffers */
676#define DWC2_CTRL_BUFF_SIZE 8
677
d17ee77b 678/**
38beaec6
JY		 679 * struct dwc2_gregs_backup - Holds global registers state before
680 * entering partial power down
d17ee77b
GH		 681 * @gotgctl: Backup of GOTGCTL register
682 * @gintmsk: Backup of GINTMSK register
683 * @gahbcfg: Backup of GAHBCFG register
684 * @gusbcfg: Backup of GUSBCFG register
685 * @grxfsiz: Backup of GRXFSIZ register
686 * @gnptxfsiz: Backup of GNPTXFSIZ register
687 * @gi2cctl: Backup of GI2CCTL register
66a36096 688 * @glpmcfg: Backup of GLPMCFG register
d17ee77b 689 * @gdfifocfg: Backup of GDFIFOCFG register
6fb914d7
GT		 690 * @pcgcctl: Backup of PCGCCTL register
691 * @pcgcctl1: Backup of PCGCCTL1 register
692 * @dtxfsiz: Backup of DTXFSIZ registers for each endpoint
d17ee77b 693 * @gpwrdn: Backup of GPWRDN register
6fb914d7 694 * @valid: True if registers values backuped.
d17ee77b
GH		 695 */
696struct dwc2_gregs_backup {
697 u32 gotgctl;
698 u32 gintmsk;
699 u32 gahbcfg;
700 u32 gusbcfg;
701 u32 grxfsiz;
702 u32 gnptxfsiz;
703 u32 gi2cctl;
66a36096 704 u32 glpmcfg;
d17ee77b 705 u32 pcgcctl;
600a490e 706 u32 pcgcctl1;
d17ee77b 707 u32 gdfifocfg;
d17ee77b 708 u32 gpwrdn;
cc1e204c 709 bool valid;
d17ee77b
GH		 710};
711
712/**
38beaec6
JY		 713 * struct dwc2_dregs_backup - Holds device registers state before
714 * entering partial power down
d17ee77b
GH		 715 * @dcfg: Backup of DCFG register
716 * @dctl: Backup of DCTL register
717 * @daintmsk: Backup of DAINTMSK register
718 * @diepmsk: Backup of DIEPMSK register
719 * @doepmsk: Backup of DOEPMSK register
720 * @diepctl: Backup of DIEPCTL register
721 * @dieptsiz: Backup of DIEPTSIZ register
722 * @diepdma: Backup of DIEPDMA register
723 * @doepctl: Backup of DOEPCTL register
724 * @doeptsiz: Backup of DOEPTSIZ register
725 * @doepdma: Backup of DOEPDMA register
af7c2bd3 726 * @dtxfsiz: Backup of DTXFSIZ registers for each endpoint
6fb914d7 727 * @valid: True if registers values backuped.
d17ee77b
GH		 728 */
729struct dwc2_dregs_backup {
730 u32 dcfg;
731 u32 dctl;
732 u32 daintmsk;
733 u32 diepmsk;
734 u32 doepmsk;
735 u32 diepctl[MAX_EPS_CHANNELS];
736 u32 dieptsiz[MAX_EPS_CHANNELS];
737 u32 diepdma[MAX_EPS_CHANNELS];
738 u32 doepctl[MAX_EPS_CHANNELS];
739 u32 doeptsiz[MAX_EPS_CHANNELS];
740 u32 doepdma[MAX_EPS_CHANNELS];
af7c2bd3 741 u32 dtxfsiz[MAX_EPS_CHANNELS];
cc1e204c 742 bool valid;
d17ee77b
GH		 743};
744
745/**
38beaec6
JY		 746 * struct dwc2_hregs_backup - Holds host registers state before
747 * entering partial power down
d17ee77b
GH		 748 * @hcfg: Backup of HCFG register
749 * @haintmsk: Backup of HAINTMSK register
750 * @hcintmsk: Backup of HCINTMSK register
6fb914d7 751 * @hprt0: Backup of HPTR0 register
d17ee77b 752 * @hfir: Backup of HFIR register
66a36096 753 * @hptxfsiz: Backup of HPTXFSIZ register
6fb914d7 754 * @valid: True if registers values backuped.
d17ee77b
GH		 755 */
756struct dwc2_hregs_backup {
757 u32 hcfg;
758 u32 haintmsk;
759 u32 hcintmsk[MAX_EPS_CHANNELS];
760 u32 hprt0;
761 u32 hfir;
66a36096 762 u32 hptxfsiz;
cc1e204c 763 bool valid;
d17ee77b
GH		 764};
765
9f9f09b0
DA		 766/*
767 * Constants related to high speed periodic scheduling
768 *
769 * We have a periodic schedule that is DWC2_HS_SCHEDULE_UFRAMES long. From a
770 * reservation point of view it's assumed that the schedule goes right back to
771 * the beginning after the end of the schedule.
772 *
773 * What does that mean for scheduling things with a long interval? It means
774 * we'll reserve time for them in every possible microframe that they could
775 * ever be scheduled in. ...but we'll still only actually schedule them as
776 * often as they were requested.
777 *
778 * We keep our schedule in a "bitmap" structure. This simplifies having
779 * to keep track of and merge intervals: we just let the bitmap code do most
780 * of the heavy lifting. In a way scheduling is much like memory allocation.
781 *
782 * We schedule 100us per uframe or 80% of 125us (the maximum amount you're
783 * supposed to schedule for periodic transfers). That's according to spec.
784 *
785 * Note that though we only schedule 80% of each microframe, the bitmap that we
786 * keep the schedule in is tightly packed (AKA it doesn't have 100us worth of
787 * space for each uFrame).
788 *
789 * Requirements:
790 * - DWC2_HS_SCHEDULE_UFRAMES must even divide 0x4000 (HFNUM_MAX_FRNUM + 1)
791 * - DWC2_HS_SCHEDULE_UFRAMES must be 8 times DWC2_LS_SCHEDULE_FRAMES (probably
792 * could be any multiple of 8 times DWC2_LS_SCHEDULE_FRAMES, but there might
793 * be bugs). The 8 comes from the USB spec: number of microframes per frame.
794 */
795#define DWC2_US_PER_UFRAME 125
796#define DWC2_HS_PERIODIC_US_PER_UFRAME 100
797
798#define DWC2_HS_SCHEDULE_UFRAMES 8
799#define DWC2_HS_SCHEDULE_US (DWC2_HS_SCHEDULE_UFRAMES * \
800 DWC2_HS_PERIODIC_US_PER_UFRAME)
801
802/*
803 * Constants related to low speed scheduling
804 *
805 * For high speed we schedule every 1us. For low speed that's a bit overkill,
806 * so we make up a unit called a "slice" that's worth 25us. There are 40
807 * slices in a full frame and we can schedule 36 of those (90%) for periodic
808 * transfers.
809 *
810 * Our low speed schedule can be as short as 1 frame or could be longer. When
811 * we only schedule 1 frame it means that we'll need to reserve a time every
812 * frame even for things that only transfer very rarely, so something that runs
813 * every 2048 frames will get time reserved in every frame. Our low speed
814 * schedule can be longer and we'll be able to handle more overlap, but that
815 * will come at increased memory cost and increased time to schedule.
816 *
817 * Note: one other advantage of a short low speed schedule is that if we mess
818 * up and miss scheduling we can jump in and use any of the slots that we
819 * happened to reserve.
820 *
821 * With 25 us per slice and 1 frame in the schedule, we only need 4 bytes for
822 * the schedule. There will be one schedule per TT.
823 *
824 * Requirements:
825 * - DWC2_US_PER_SLICE must evenly divide DWC2_LS_PERIODIC_US_PER_FRAME.
826 */
827#define DWC2_US_PER_SLICE 25
828#define DWC2_SLICES_PER_UFRAME (DWC2_US_PER_UFRAME / DWC2_US_PER_SLICE)
829
830#define DWC2_ROUND_US_TO_SLICE(us) \
831 (DIV_ROUND_UP((us), DWC2_US_PER_SLICE) * \
832 DWC2_US_PER_SLICE)
833
834#define DWC2_LS_PERIODIC_US_PER_FRAME \
835 900
836#define DWC2_LS_PERIODIC_SLICES_PER_FRAME \
837 (DWC2_LS_PERIODIC_US_PER_FRAME / \
838 DWC2_US_PER_SLICE)
839
840#define DWC2_LS_SCHEDULE_FRAMES 1
841#define DWC2_LS_SCHEDULE_SLICES (DWC2_LS_SCHEDULE_FRAMES * \
842 DWC2_LS_PERIODIC_SLICES_PER_FRAME)
843
56f5b1cf
PZ		 844/**
845 * struct dwc2_hsotg - Holds the state of the driver, including the non-periodic
846 * and periodic schedules
847 *
941fcce4
DN		 848 * These are common for both host and peripheral modes:
849 *
56f5b1cf
PZ		 850 * @dev: The struct device pointer
851 * @regs: Pointer to controller regs
9badec2f
MK		 852 * @hw_params: Parameters that were autodetected from the
853 * hardware registers
6fb914d7 854 * @params: Parameters that define how the core should be configured
56f5b1cf
PZ		 855 * @op_state: The operational State, during transitions (a_host=>
856 * a_peripheral and b_device=>b_host) this may not match
857 * the core, but allows the software to determine
858 * transitions
c0155b9d
KY		 859 * @dr_mode: Requested mode of operation, one of following:
860 * - USB_DR_MODE_PERIPHERAL
861 * - USB_DR_MODE_HOST
862 * - USB_DR_MODE_OTG
17f93402 863 * @role_sw: usb_role_switch handle
6fb914d7
GT		 864 * @hcd_enabled: Host mode sub-driver initialization indicator.
865 * @gadget_enabled: Peripheral mode sub-driver initialization indicator.
866 * @ll_hw_enabled: Status of low-level hardware resources.
20fe4409 867 * @hibernated: True if core is hibernated
be2b960e 868 * @in_ppd: True if core is partial power down mode.
c40cf770
DA		 869 * @reset_phy_on_wake: Quirk saying that we should assert PHY reset on a
870 * remote wakeup.
c846b03f
DA		 871 * @phy_off_for_suspend: Status of whether we turned the PHY off at suspend.
872 * @need_phy_for_wake: Quirk saying that we should keep the PHY on at
873 * suspend if we need USB to wake us up.
c7c24e7a
AP		 874 * @frame_number: Frame number read from the core. For both device
875 * and host modes. The value ranges are from 0
876 * to HFNUM_MAX_FRNUM.
09a75e85 877 * @phy: The otg phy transceiver structure for phy control.
38beaec6
JY		 878 * @uphy: The otg phy transceiver structure for old USB phy
879 * control.
880 * @plat: The platform specific configuration data. This can be
881 * removed once all SoCs support usb transceiver.
09a75e85 882 * @supplies: Definition of USB power supplies
531ef5eb 883 * @vbus_supply: Regulator supplying vbus.
a415083a
AD		 884 * @usb33d: Optional 3.3v regulator used on some stm32 devices to
885 * supply ID and VBUS detection hardware.
941fcce4
DN		 886 * @lock: Spinlock that protects all the driver data structures
887 * @priv: Stores a pointer to the struct usb_hcd
56f5b1cf
PZ		 888 * @queuing_high_bandwidth: True if multiple packets of a high-bandwidth
889 * transfer are in process of being queued
890 * @srp_success: Stores status of SRP request in the case of a FS PHY
891 * with an I2C interface
892 * @wq_otg: Workqueue object used for handling of some interrupts
893 * @wf_otg: Work object for handling Connector ID Status Change
894 * interrupt
895 * @wkp_timer: Timer object for handling Wakeup Detected interrupt
896 * @lx_state: Lx state of connected device
6fb914d7
GT		 897 * @gr_backup: Backup of global registers during suspend
898 * @dr_backup: Backup of device registers during suspend
899 * @hr_backup: Backup of host registers during suspend
fe369e18 900 * @needs_byte_swap: Specifies whether the opposite endianness.
941fcce4
DN		 901 *
902 * These are for host mode:
903 *
56f5b1cf 904 * @flags: Flags for handling root port state changes
6fb914d7
GT		 905 * @flags.d32: Contain all root port flags
906 * @flags.b: Separate root port flags from each other
907 * @flags.b.port_connect_status_change: True if root port connect status
908 * changed
909 * @flags.b.port_connect_status: True if device connected to root port
910 * @flags.b.port_reset_change: True if root port reset status changed
911 * @flags.b.port_enable_change: True if root port enable status changed
912 * @flags.b.port_suspend_change: True if root port suspend status changed
913 * @flags.b.port_over_current_change: True if root port over current state
914 * changed.
915 * @flags.b.port_l1_change: True if root port l1 status changed
916 * @flags.b.reserved: Reserved bits of root port register
56f5b1cf
PZ		 917 * @non_periodic_sched_inactive: Inactive QHs in the non-periodic schedule.
918 * Transfers associated with these QHs are not currently
919 * assigned to a host channel.
920 * @non_periodic_sched_active: Active QHs in the non-periodic schedule.
921 * Transfers associated with these QHs are currently
922 * assigned to a host channel.
923 * @non_periodic_qh_ptr: Pointer to next QH to process in the active
924 * non-periodic schedule
6fb914d7
GT		 925 * @non_periodic_sched_waiting: Waiting QHs in the non-periodic schedule.
926 * Transfers associated with these QHs are not currently
927 * assigned to a host channel.
56f5b1cf
PZ		 928 * @periodic_sched_inactive: Inactive QHs in the periodic schedule. This is a
929 * list of QHs for periodic transfers that are _not_
930 * scheduled for the next frame. Each QH in the list has an
931 * interval counter that determines when it needs to be
932 * scheduled for execution. This scheduling mechanism
933 * allows only a simple calculation for periodic bandwidth
934 * used (i.e. must assume that all periodic transfers may
935 * need to execute in the same frame). However, it greatly
936 * simplifies scheduling and should be sufficient for the
937 * vast majority of OTG hosts, which need to connect to a
938 * small number of peripherals at one time. Items move from
939 * this list to periodic_sched_ready when the QH interval
940 * counter is 0 at SOF.
941 * @periodic_sched_ready: List of periodic QHs that are ready for execution in
942 * the next frame, but have not yet been assigned to host
943 * channels. Items move from this list to
944 * periodic_sched_assigned as host channels become
945 * available during the current frame.
946 * @periodic_sched_assigned: List of periodic QHs to be executed in the next
947 * frame that are assigned to host channels. Items move
948 * from this list to periodic_sched_queued as the
949 * transactions for the QH are queued to the DWC_otg
950 * controller.
951 * @periodic_sched_queued: List of periodic QHs that have been queued for
952 * execution. Items move from this list to either
953 * periodic_sched_inactive or periodic_sched_ready when the
954 * channel associated with the transfer is released. If the
955 * interval for the QH is 1, the item moves to
956 * periodic_sched_ready because it must be rescheduled for
957 * the next frame. Otherwise, the item moves to
958 * periodic_sched_inactive.
c9c8ac01 959 * @split_order: List keeping track of channels doing splits, in order.
56f5b1cf
PZ		 960 * @periodic_usecs: Total bandwidth claimed so far for periodic transfers.
961 * This value is in microseconds per (micro)frame. The
962 * assumption is that all periodic transfers may occur in
963 * the same (micro)frame.
9f9f09b0
DA		 964 * @hs_periodic_bitmap: Bitmap used by the microframe scheduler any time the
965 * host is in high speed mode; low speed schedules are
966 * stored elsewhere since we need one per TT.
56f5b1cf
PZ		 967 * @periodic_qh_count: Count of periodic QHs, if using several eps. Used for
968 * SOF enable/disable.
969 * @free_hc_list: Free host channels in the controller. This is a list of
970 * struct dwc2_host_chan items.
971 * @periodic_channels: Number of host channels assigned to periodic transfers.
972 * Currently assuming that there is a dedicated host
973 * channel for each periodic transaction and at least one
974 * host channel is available for non-periodic transactions.
975 * @non_periodic_channels: Number of host channels assigned to non-periodic
976 * transfers
6fb914d7
GT		 977 * @available_host_channels: Number of host channels available for the
978 * microframe scheduler to use
56f5b1cf
PZ		 979 * @hc_ptr_array: Array of pointers to the host channel descriptors.
980 * Allows accessing a host channel descriptor given the
981 * host channel number. This is useful in interrupt
982 * handlers.
983 * @status_buf: Buffer used for data received during the status phase of
984 * a control transfer.
985 * @status_buf_dma: DMA address for status_buf
986 * @start_work: Delayed work for handling host A-cable connection
987 * @reset_work: Delayed work for handling a port reset
c40cf770 988 * @phy_reset_work: Work structure for doing a PHY reset
56f5b1cf
PZ		 989 * @otg_port: OTG port number
990 * @frame_list: Frame list
991 * @frame_list_dma: Frame list DMA address
95105a99 992 * @frame_list_sz: Frame list size
3b5fcc9a
GH		 993 * @desc_gen_cache: Kmem cache for generic descriptors
994 * @desc_hsisoc_cache: Kmem cache for hs isochronous descriptors
af424a41 995 * @unaligned_cache: Kmem cache for DMA mode to handle non-aligned buf
941fcce4
DN		 996 *
997 * These are for peripheral mode:
998 *
999 * @driver: USB gadget driver
941fcce4
DN		 1000 * @dedicated_fifos: Set if the hardware has dedicated IN-EP fifos.
1001 * @num_of_eps: Number of available EPs (excluding EP0)
1002 * @debug_root: Root directrory for debugfs.
941fcce4
DN		 1003 * @ep0_reply: Request used for ep0 reply.
1004 * @ep0_buff: Buffer for EP0 reply data, if needed.
1005 * @ctrl_buff: Buffer for EP0 control requests.
1006 * @ctrl_req: Request for EP0 control packets.
fe0b94ab 1007 * @ep0_state: EP0 control transfers state
b4c53b4a 1008 * @delayed_status: true when gadget driver asks for delayed status
9e14d0a5 1009 * @test_mode: USB test mode requested by the host
fa389a6d
VM		 1010 * @remote_wakeup_allowed: True if device is allowed to wake-up host by
1011 * remote-wakeup signalling
0f6b80c0
VA		 1012 * @setup_desc_dma: EP0 setup stage desc chain DMA address
1013 * @setup_desc: EP0 setup stage desc chain pointer
1014 * @ctrl_in_desc_dma: EP0 IN data phase desc chain DMA address
1015 * @ctrl_in_desc: EP0 IN data phase desc chain pointer
1016 * @ctrl_out_desc_dma: EP0 OUT data phase desc chain DMA address
1017 * @ctrl_out_desc: EP0 OUT data phase desc chain pointer
6fb914d7
GT		 1018 * @irq: Interrupt request line number
1019 * @clk: Pointer to otg clock
1020 * @reset: Pointer to dwc2 reset controller
1021 * @reset_ecc: Pointer to dwc2 optional reset controller in Stratix10.
1022 * @regset: A pointer to a struct debugfs_regset32, which contains
1023 * a pointer to an array of register definitions, the
1024 * array size and the base address where the register bank
1025 * is to be found.
1026 * @bus_suspended: True if bus is suspended
1027 * @last_frame_num: Number of last frame. Range from 0 to 32768
1028 * @frame_num_array: Used only if CONFIG_USB_DWC2_TRACK_MISSED_SOFS is
1029 * defined, for missed SOFs tracking. Array holds that
1030 * frame numbers, which not equal to last_frame_num +1
1031 * @last_frame_num_array: Used only if CONFIG_USB_DWC2_TRACK_MISSED_SOFS is
1032 * defined, for missed SOFs tracking.
1033 * If current_frame_number != last_frame_num+1
1034 * then last_frame_num added to this array
1035 * @frame_num_idx: Actual size of frame_num_array and last_frame_num_array
1036 * @dumped_frame_num_array: 1 - if missed SOFs frame numbers dumbed
1037 * 0 - if missed SOFs frame numbers not dumbed
1038 * @fifo_mem: Total internal RAM for FIFOs (bytes)
1039 * @fifo_map: Each bit intend for concrete fifo. If that bit is set,
1040 * then that fifo is used
b9b70170 1041 * @gadget: Represents a usb gadget device
6fb914d7
GT		 1042 * @connected: Used in slave mode. True if device connected with host
1043 * @eps_in: The IN endpoints being supplied to the gadget framework
1044 * @eps_out: The OUT endpoints being supplied to the gadget framework
1045 * @new_connection: Used in host mode. True if there are new connected
1046 * device
1047 * @enabled: Indicates the enabling state of controller
1048 *
56f5b1cf
PZ		 1049 */
1050struct dwc2_hsotg {
1051 struct device *dev;
1052 void __iomem *regs;
9badec2f
MK		 1053 /** Params detected from hardware */
1054 struct dwc2_hw_params hw_params;
1055 /** Params to actually use */
bea8e86c 1056 struct dwc2_core_params params;
56f5b1cf 1057 enum usb_otg_state op_state;
c0155b9d 1058 enum usb_dr_mode dr_mode;
17f93402 1059 struct usb_role_switch *role_sw;
e39af88f
MS		 1060 unsigned int hcd_enabled:1;
1061 unsigned int gadget_enabled:1;
09a75e85 1062 unsigned int ll_hw_enabled:1;
20fe4409 1063 unsigned int hibernated:1;
be2b960e 1064 unsigned int in_ppd:1;
c40cf770 1065 unsigned int reset_phy_on_wake:1;
c846b03f
DA		 1066 unsigned int need_phy_for_wake:1;
1067 unsigned int phy_off_for_suspend:1;
c7c24e7a 1068 u16 frame_number;
56f5b1cf 1069
941fcce4
DN		 1070 struct phy *phy;
1071 struct usb_phy *uphy;
09a75e85 1072 struct dwc2_hsotg_plat *plat;
b98866c2 1073 struct regulator_bulk_data supplies[DWC2_NUM_SUPPLIES];
531ef5eb 1074 struct regulator *vbus_supply;
a415083a 1075 struct regulator *usb33d;
941fcce4
DN		 1076
1077 spinlock_t lock;
1078 void *priv;
1079 int irq;
1080 struct clk *clk;
83f8da56 1081 struct reset_control *reset;
f2830ad4 1082 struct reset_control *reset_ecc;
941fcce4 1083
56f5b1cf
PZ		 1084 unsigned int queuing_high_bandwidth:1;
1085 unsigned int srp_success:1;
1086
1087 struct workqueue_struct *wq_otg;
1088 struct work_struct wf_otg;
1089 struct timer_list wkp_timer;
1090 enum dwc2_lx_state lx_state;
cc1e204c
MYK		 1091 struct dwc2_gregs_backup gr_backup;
1092 struct dwc2_dregs_backup dr_backup;
1093 struct dwc2_hregs_backup hr_backup;
56f5b1cf 1094
941fcce4 1095 struct dentry *debug_root;
563cf017 1096 struct debugfs_regset32 *regset;
fe369e18 1097 bool needs_byte_swap;
941fcce4
DN		 1098
1099 /* DWC OTG HW Release versions */
1100#define DWC2_CORE_REV_2_71a 0x4f54271a
5295322a 1101#define DWC2_CORE_REV_2_72a 0x4f54272a
6f80b6de 1102#define DWC2_CORE_REV_2_80a 0x4f54280a
941fcce4 1103#define DWC2_CORE_REV_2_90a 0x4f54290a
e1f411d1 1104#define DWC2_CORE_REV_2_91a 0x4f54291a
941fcce4
DN		 1105#define DWC2_CORE_REV_2_92a 0x4f54292a
1106#define DWC2_CORE_REV_2_94a 0x4f54294a
1107#define DWC2_CORE_REV_3_00a 0x4f54300a
fef6bc37 1108#define DWC2_CORE_REV_3_10a 0x4f54310a
5295322a 1109#define DWC2_CORE_REV_4_00a 0x4f54400a
65dc2e72 1110#define DWC2_CORE_REV_4_20a 0x4f54420a
1e6b98eb
VM		 1111#define DWC2_FS_IOT_REV_1_00a 0x5531100a
1112#define DWC2_HS_IOT_REV_1_00a 0x5532100a
65dc2e72 1113#define DWC2_CORE_REV_MASK 0x0000ffff
941fcce4 1114
d14ccaba
GS		 1115 /* DWC OTG HW Core ID */
1116#define DWC2_OTG_ID 0x4f540000
1117#define DWC2_FS_IOT_ID 0x55310000
1118#define DWC2_HS_IOT_ID 0x55320000
1119
941fcce4 1120#if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
56f5b1cf
PZ		 1121 union dwc2_hcd_internal_flags {
1122 u32 d32;
1123 struct {
1124 unsigned port_connect_status_change:1;
1125 unsigned port_connect_status:1;
1126 unsigned port_reset_change:1;
1127 unsigned port_enable_change:1;
1128 unsigned port_suspend_change:1;
1129 unsigned port_over_current_change:1;
1130 unsigned port_l1_change:1;
fd4850cf 1131 unsigned reserved:25;
56f5b1cf
PZ		 1132 } b;
1133 } flags;
1134
1135 struct list_head non_periodic_sched_inactive;
38d2b5fb 1136 struct list_head non_periodic_sched_waiting;
56f5b1cf
PZ		 1137 struct list_head non_periodic_sched_active;
1138 struct list_head *non_periodic_qh_ptr;
1139 struct list_head periodic_sched_inactive;
1140 struct list_head periodic_sched_ready;
1141 struct list_head periodic_sched_assigned;
1142 struct list_head periodic_sched_queued;
c9c8ac01 1143 struct list_head split_order;
56f5b1cf 1144 u16 periodic_usecs;
9f9f09b0
DA		 1145 unsigned long hs_periodic_bitmap[
1146 DIV_ROUND_UP(DWC2_HS_SCHEDULE_US, BITS_PER_LONG)];
56f5b1cf 1147 u16 periodic_qh_count;
734643df 1148 bool bus_suspended;
fbb9e22b 1149 bool new_connection;
56f5b1cf 1150
483bb254
DA		 1151 u16 last_frame_num;
1152
56f5b1cf
PZ		 1153#ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
1154#define FRAME_NUM_ARRAY_SIZE 1000
56f5b1cf
PZ		 1155 u16 *frame_num_array;
1156 u16 *last_frame_num_array;
1157 int frame_num_idx;
1158 int dumped_frame_num_array;
1159#endif
1160
1161 struct list_head free_hc_list;
1162 int periodic_channels;
1163 int non_periodic_channels;
20f2eb9c 1164 int available_host_channels;
56f5b1cf
PZ		 1165 struct dwc2_host_chan *hc_ptr_array[MAX_EPS_CHANNELS];
1166 u8 *status_buf;
1167 dma_addr_t status_buf_dma;
1168#define DWC2_HCD_STATUS_BUF_SIZE 64
1169
1170 struct delayed_work start_work;
1171 struct delayed_work reset_work;
c40cf770 1172 struct work_struct phy_reset_work;
56f5b1cf
PZ		 1173 u8 otg_port;
1174 u32 *frame_list;
1175 dma_addr_t frame_list_dma;
95105a99 1176 u32 frame_list_sz;
3b5fcc9a
GH		 1177 struct kmem_cache *desc_gen_cache;
1178 struct kmem_cache *desc_hsisoc_cache;
af424a41
WW		 1179 struct kmem_cache *unaligned_cache;
1180#define DWC2_KMEM_UNALIGNED_BUF_SIZE 1024
56f5b1cf 1181
941fcce4
DN		 1182#endif /* CONFIG_USB_DWC2_HOST || CONFIG_USB_DWC2_DUAL_ROLE */
1183
b98866c2
JY		 1184#if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \
1185 IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
941fcce4
DN		 1186 /* Gadget structures */
1187 struct usb_gadget_driver *driver;
941fcce4
DN		 1188 int fifo_mem;
1189 unsigned int dedicated_fifos:1;
1190 unsigned char num_of_eps;
1191 u32 fifo_map;
1192
1193 struct usb_request *ep0_reply;
1194 struct usb_request *ctrl_req;
3f95001d
MYK		 1195 void *ep0_buff;
1196 void *ctrl_buff;
fe0b94ab 1197 enum dwc2_ep0_state ep0_state;
b4c53b4a 1198 unsigned delayed_status : 1;
9e14d0a5 1199 u8 test_mode;
941fcce4 1200
0f6b80c0
VA		 1201 dma_addr_t setup_desc_dma[2];
1202 struct dwc2_dma_desc *setup_desc[2];
1203 dma_addr_t ctrl_in_desc_dma;
1204 struct dwc2_dma_desc *ctrl_in_desc;
1205 dma_addr_t ctrl_out_desc_dma;
1206 struct dwc2_dma_desc *ctrl_out_desc;
1207
941fcce4 1208 struct usb_gadget gadget;
dc6e69e6 1209 unsigned int enabled:1;
4ace06e8 1210 unsigned int connected:1;
fa389a6d 1211 unsigned int remote_wakeup_allowed:1;
1f91b4cc
FB		 1212 struct dwc2_hsotg_ep *eps_in[MAX_EPS_CHANNELS];
1213 struct dwc2_hsotg_ep *eps_out[MAX_EPS_CHANNELS];
941fcce4 1214#endif /* CONFIG_USB_DWC2_PERIPHERAL || CONFIG_USB_DWC2_DUAL_ROLE */
56f5b1cf
PZ		 1215};
1216
342ccce1 1217/* Normal architectures just use readl/write */
f25c42b8 1218static inline u32 dwc2_readl(struct dwc2_hsotg *hsotg, u32 offset)
0f548098 1219{
fe369e18
GS		 1220 u32 val;
1221
1222 val = readl(hsotg->regs + offset);
1223 if (hsotg->needs_byte_swap)
1224 return swab32(val);
1225 else
1226 return val;
0f548098
GS		 1227}
1228
f25c42b8 1229static inline void dwc2_writel(struct dwc2_hsotg *hsotg, u32 value, u32 offset)
0f548098 1230{
fe369e18
GS		 1231 if (hsotg->needs_byte_swap)
1232 writel(swab32(value), hsotg->regs + offset);
1233 else
1234 writel(value, hsotg->regs + offset);
342ccce1 1235
0f548098 1236#ifdef DWC2_LOG_WRITES
342ccce1 1237 pr_info("info:: wrote %08x to %p\n", value, hsotg->regs + offset);
0f548098
GS		 1238#endif
1239}
f25c42b8 1240
342ccce1
GS		 1241static inline void dwc2_readl_rep(struct dwc2_hsotg *hsotg, u32 offset,
1242 void *buffer, unsigned int count)
0f548098 1243{
342ccce1
GS		 1244 if (count) {
1245 u32 *buf = buffer;
1246
1247 do {
1248 u32 x = dwc2_readl(hsotg, offset);
1249 *buf++ = x;
1250 } while (--count);
1251 }
0f548098
GS		 1252}
1253
342ccce1
GS		 1254static inline void dwc2_writel_rep(struct dwc2_hsotg *hsotg, u32 offset,
1255 const void *buffer, unsigned int count)
0f548098 1256{
342ccce1
GS		 1257 if (count) {
1258 const u32 *buf = buffer;
0f548098 1259
342ccce1
GS		 1260 do {
1261 dwc2_writel(hsotg, *buf++, offset);
1262 } while (--count);
1263 }
0f548098 1264}
0f548098 1265
56f5b1cf
PZ		 1266/* Reasons for halting a host channel */
1267enum dwc2_halt_status {
1268 DWC2_HC_XFER_NO_HALT_STATUS,
1269 DWC2_HC_XFER_COMPLETE,
1270 DWC2_HC_XFER_URB_COMPLETE,
1271 DWC2_HC_XFER_ACK,
1272 DWC2_HC_XFER_NAK,
1273 DWC2_HC_XFER_NYET,
1274 DWC2_HC_XFER_STALL,
1275 DWC2_HC_XFER_XACT_ERR,
1276 DWC2_HC_XFER_FRAME_OVERRUN,
1277 DWC2_HC_XFER_BABBLE_ERR,
1278 DWC2_HC_XFER_DATA_TOGGLE_ERR,
1279 DWC2_HC_XFER_AHB_ERR,
1280 DWC2_HC_XFER_PERIODIC_INCOMPLETE,
1281 DWC2_HC_XFER_URB_DEQUEUE,
1282};
1283
1e6b98eb
VM		 1284/* Core version information */
1285static inline bool dwc2_is_iot(struct dwc2_hsotg *hsotg)
1286{
1287 return (hsotg->hw_params.snpsid & 0xfff00000) == 0x55300000;
1288}
1289
1290static inline bool dwc2_is_fs_iot(struct dwc2_hsotg *hsotg)
1291{
1292 return (hsotg->hw_params.snpsid & 0xffff0000) == 0x55310000;
1293}
1294
1295static inline bool dwc2_is_hs_iot(struct dwc2_hsotg *hsotg)
1296{
1297 return (hsotg->hw_params.snpsid & 0xffff0000) == 0x55320000;
1298}
1299
56f5b1cf
PZ		 1300/*
1301 * The following functions support initialization of the core driver component
1302 * and the DWC_otg controller
1303 */
6e6360b6 1304int dwc2_core_reset(struct dwc2_hsotg *hsotg, bool skip_wait);
41ba9b9b
VM		 1305int dwc2_enter_partial_power_down(struct dwc2_hsotg *hsotg);
1306int dwc2_exit_partial_power_down(struct dwc2_hsotg *hsotg, bool restore);
624815ce
VM		 1307int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg, int is_host);
1308int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, int rem_wakeup,
13b1f8e2 1309 int reset, int is_host);
059d8d52
JM		 1310void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg *hsotg);
1311int dwc2_phy_init(struct dwc2_hsotg *hsotg, bool select_phy);
56f5b1cf 1312
13b1f8e2 1313void dwc2_force_mode(struct dwc2_hsotg *hsotg, bool host);
09c96980
JY		 1314void dwc2_force_dr_mode(struct dwc2_hsotg *hsotg);
1315
9da51974 1316bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg);
56f5b1cf 1317
65dc2e72
MH		 1318int dwc2_check_core_version(struct dwc2_hsotg *hsotg);
1319
56f5b1cf
PZ		 1320/*
1321 * Common core Functions.
1322 * The following functions support managing the DWC_otg controller in either
1323 * device or host mode.
1324 */
9da51974
JY		 1325void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes);
1326void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num);
1327void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg);
56f5b1cf 1328
9da51974
JY		 1329void dwc2_enable_global_interrupts(struct dwc2_hsotg *hcd);
1330void dwc2_disable_global_interrupts(struct dwc2_hsotg *hcd);
56f5b1cf 1331
94d2666c
VM		 1332void dwc2_hib_restore_common(struct dwc2_hsotg *hsotg, int rem_wakeup,
1333 int is_host);
c5c403dc
VM		 1334int dwc2_backup_global_registers(struct dwc2_hsotg *hsotg);
1335int dwc2_restore_global_registers(struct dwc2_hsotg *hsotg);
94d2666c 1336
66e77a24
RK		 1337void dwc2_enable_acg(struct dwc2_hsotg *hsotg);
1338
56f5b1cf 1339/* This function should be called on every hardware interrupt. */
9da51974 1340irqreturn_t dwc2_handle_common_intr(int irq, void *dev);
56f5b1cf 1341
323230ef
JY		 1342/* The device ID match table */
1343extern const struct of_device_id dwc2_of_match_table[];
1344
9da51974
JY		 1345int dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg);
1346int dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg);
ecb176c6 1347
79d6b8c5
SA		 1348/* Common polling functions */
1349int dwc2_hsotg_wait_bit_set(struct dwc2_hsotg *hs_otg, u32 reg, u32 bit,
1350 u32 timeout);
1351int dwc2_hsotg_wait_bit_clear(struct dwc2_hsotg *hs_otg, u32 reg, u32 bit,
1352 u32 timeout);
334bbd4e 1353/* Parameters */
c1d286cf 1354int dwc2_get_hwparams(struct dwc2_hsotg *hsotg);
334bbd4e
JY		 1355int dwc2_init_params(struct dwc2_hsotg *hsotg);
1356
6bea9620
JY		 1357/*
1358 * The following functions check the controller's OTG operation mode
1359 * capability (GHWCFG2.OTG_MODE).
1360 *
1361 * These functions can be used before the internal hsotg->hw_params
1362 * are read in and cached so they always read directly from the
1363 * GHWCFG2 register.
1364 */
9da51974 1365unsigned int dwc2_op_mode(struct dwc2_hsotg *hsotg);
6bea9620
JY		 1366bool dwc2_hw_is_otg(struct dwc2_hsotg *hsotg);
1367bool dwc2_hw_is_host(struct dwc2_hsotg *hsotg);
1368bool dwc2_hw_is_device(struct dwc2_hsotg *hsotg);
1369
1696d5ab
JY		 1370/*
1371 * Returns the mode of operation, host or device
1372 */
1373static inline int dwc2_is_host_mode(struct dwc2_hsotg *hsotg)
1374{
f25c42b8 1375 return (dwc2_readl(hsotg, GINTSTS) & GINTSTS_CURMODE_HOST) != 0;
1696d5ab 1376}
9da51974 1377
1696d5ab
JY		 1378static inline int dwc2_is_device_mode(struct dwc2_hsotg *hsotg)
1379{
f25c42b8 1380 return (dwc2_readl(hsotg, GINTSTS) & GINTSTS_CURMODE_HOST) == 0;
1696d5ab
JY		 1381}
1382
17f93402
AD		 1383int dwc2_drd_init(struct dwc2_hsotg *hsotg);
1384void dwc2_drd_suspend(struct dwc2_hsotg *hsotg);
1385void dwc2_drd_resume(struct dwc2_hsotg *hsotg);
1386void dwc2_drd_exit(struct dwc2_hsotg *hsotg);
1387
56f5b1cf
PZ		 1388/*
1389 * Dump core registers and SPRAM
1390 */
9da51974
JY		 1391void dwc2_dump_dev_registers(struct dwc2_hsotg *hsotg);
1392void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg);
1393void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg);
56f5b1cf 1394
117777b2 1395/* Gadget defines */
b98866c2
JY		 1396#if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \
1397 IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
9da51974
JY		 1398int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg);
1399int dwc2_hsotg_suspend(struct dwc2_hsotg *dwc2);
1400int dwc2_hsotg_resume(struct dwc2_hsotg *dwc2);
f3768997 1401int dwc2_gadget_init(struct dwc2_hsotg *hsotg);
9da51974
JY		 1402void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2,
1403 bool reset);
17f93402 1404void dwc2_hsotg_core_disconnect(struct dwc2_hsotg *hsotg);
9da51974
JY		 1405void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg);
1406void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2);
1407int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode);
f81f46e1 1408#define dwc2_is_device_connected(hsotg) (hsotg->connected)
58e52ff6 1409int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg);
9a5d2816 1410int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg, int remote_wakeup);
c5c403dc
VM		 1411int dwc2_gadget_enter_hibernation(struct dwc2_hsotg *hsotg);
1412int dwc2_gadget_exit_hibernation(struct dwc2_hsotg *hsotg,
1413 int rem_wakeup, int reset);
be2b960e
AP		 1414int dwc2_gadget_enter_partial_power_down(struct dwc2_hsotg *hsotg);
1415int dwc2_gadget_exit_partial_power_down(struct dwc2_hsotg *hsotg,
1416 bool restore);
c138ecfa
SA		 1417int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg *hsotg);
1418int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg);
1419int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg *hsotg);
21b03405 1420void dwc2_gadget_init_lpm(struct dwc2_hsotg *hsotg);
15d9dbf8 1421void dwc2_gadget_program_ref_clk(struct dwc2_hsotg *hsotg);
117777b2 1422#else
1f91b4cc 1423static inline int dwc2_hsotg_remove(struct dwc2_hsotg *dwc2)
117777b2 1424{ return 0; }
1f91b4cc 1425static inline int dwc2_hsotg_suspend(struct dwc2_hsotg *dwc2)
117777b2 1426{ return 0; }
1f91b4cc 1427static inline int dwc2_hsotg_resume(struct dwc2_hsotg *dwc2)
117777b2 1428{ return 0; }
f3768997 1429static inline int dwc2_gadget_init(struct dwc2_hsotg *hsotg)
117777b2 1430{ return 0; }
1f91b4cc 1431static inline void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2,
9da51974 1432 bool reset) {}
17f93402 1433static inline void dwc2_hsotg_core_disconnect(struct dwc2_hsotg *hsotg) {}
1f91b4cc
FB		 1434static inline void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg) {}
1435static inline void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2) {}
1436static inline int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg,
9da51974 1437 int testmode)
f91eea44 1438{ return 0; }
f81f46e1 1439#define dwc2_is_device_connected(hsotg) (0)
58e52ff6
JY		 1440static inline int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg)
1441{ return 0; }
9a5d2816
VM		 1442static inline int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg,
1443 int remote_wakeup)
58e52ff6 1444{ return 0; }
c5c403dc
VM		 1445static inline int dwc2_gadget_enter_hibernation(struct dwc2_hsotg *hsotg)
1446{ return 0; }
1447static inline int dwc2_gadget_exit_hibernation(struct dwc2_hsotg *hsotg,
1448 int rem_wakeup, int reset)
1449{ return 0; }
be2b960e
AP		 1450static inline int dwc2_gadget_enter_partial_power_down(struct dwc2_hsotg *hsotg)
1451{ return 0; }
1452static inline int dwc2_gadget_exit_partial_power_down(struct dwc2_hsotg *hsotg,
1453 bool restore)
1454{ return 0; }
c138ecfa
SA		 1455static inline int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg *hsotg)
1456{ return 0; }
1457static inline int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg)
1458{ return 0; }
1459static inline int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg *hsotg)
1460{ return 0; }
21b03405 1461static inline void dwc2_gadget_init_lpm(struct dwc2_hsotg *hsotg) {}
15d9dbf8 1462static inline void dwc2_gadget_program_ref_clk(struct dwc2_hsotg *hsotg) {}
117777b2
DN		 1463#endif
1464
1465#if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
9da51974
JY		 1466int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg);
1467int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg, int us);
1468void dwc2_hcd_connect(struct dwc2_hsotg *hsotg);
1469void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force);
1470void dwc2_hcd_start(struct dwc2_hsotg *hsotg);
65c9c4c6 1471int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup);
58e52ff6
JY		 1472int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg);
1473int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg);
c5c403dc
VM		 1474int dwc2_host_enter_hibernation(struct dwc2_hsotg *hsotg);
1475int dwc2_host_exit_hibernation(struct dwc2_hsotg *hsotg,
1476 int rem_wakeup, int reset);
9ce9e5ad
AP		 1477int dwc2_host_enter_partial_power_down(struct dwc2_hsotg *hsotg);
1478int dwc2_host_exit_partial_power_down(struct dwc2_hsotg *hsotg,
1479 int rem_wakeup, bool restore);
c846b03f 1480bool dwc2_host_can_poweroff_phy(struct dwc2_hsotg *dwc2);
c40cf770
DA		 1481static inline void dwc2_host_schedule_phy_reset(struct dwc2_hsotg *hsotg)
1482{ schedule_work(&hsotg->phy_reset_work); }
117777b2 1483#else
117777b2
DN		 1484static inline int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg)
1485{ return 0; }
fae4e826
DA		 1486static inline int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg,
1487 int us)
1488{ return 0; }
6a659531
DA		 1489static inline void dwc2_hcd_connect(struct dwc2_hsotg *hsotg) {}
1490static inline void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force) {}
117777b2
DN		 1491static inline void dwc2_hcd_start(struct dwc2_hsotg *hsotg) {}
1492static inline void dwc2_hcd_remove(struct dwc2_hsotg *hsotg) {}
65c9c4c6
VM		 1493static inline int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup)
1494{ return 0; }
4fe160d5 1495static inline int dwc2_hcd_init(struct dwc2_hsotg *hsotg)
117777b2 1496{ return 0; }
58e52ff6
JY		 1497static inline int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg)
1498{ return 0; }
1499static inline int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg)
1500{ return 0; }
c5c403dc
VM		 1501static inline int dwc2_host_enter_hibernation(struct dwc2_hsotg *hsotg)
1502{ return 0; }
1503static inline int dwc2_host_exit_hibernation(struct dwc2_hsotg *hsotg,
1504 int rem_wakeup, int reset)
1505{ return 0; }
9ce9e5ad
AP		 1506static inline int dwc2_host_enter_partial_power_down(struct dwc2_hsotg *hsotg)
1507{ return 0; }
1508static inline int dwc2_host_exit_partial_power_down(struct dwc2_hsotg *hsotg,
1509 int rem_wakeup, bool restore)
1510{ return 0; }
c846b03f
DA		 1511static inline bool dwc2_host_can_poweroff_phy(struct dwc2_hsotg *dwc2)
1512{ return false; }
c40cf770 1513static inline void dwc2_host_schedule_phy_reset(struct dwc2_hsotg *hsotg) {}
58e52ff6 1514
117777b2
DN		 1515#endif
1516
56f5b1cf 1517#endif /* __DWC2_CORE_H__ */
Linux 6.x block layer and io_uring tree(s)