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usb: dwc2: Use kmem_cache_free()
[linux-block.git] / drivers / usb / dwc2 / core.h
CommitLineData
56f5b1cf
PZ		 1/*
2 * core.h - DesignWare HS OTG Controller common declarations
3 *
4 * Copyright (C) 2004-2013 Synopsys, Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions, and the following disclaimer,
11 * without modification.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The names of the above-listed copyright holders may not be used
16 * to endorse or promote products derived from this software without
17 * specific prior written permission.
18 *
19 * ALTERNATIVELY, this software may be distributed under the terms of the
20 * GNU General Public License ("GPL") as published by the Free Software
21 * Foundation; either version 2 of the License, or (at your option) any
22 * later version.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
25 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
28 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
29 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
30 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
31 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
32 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
33 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
34 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 */
36
37#ifndef __DWC2_CORE_H__
38#define __DWC2_CORE_H__
39
f7c0b143
DN		 40#include <linux/phy/phy.h>
41#include <linux/regulator/consumer.h>
42#include <linux/usb/gadget.h>
43#include <linux/usb/otg.h>
56f5b1cf
PZ		 44#include <linux/usb/phy.h>
45#include "hw.h"
46
74fc4a75
DA		 47/*
48 * Suggested defines for tracers:
49 * - no_printk: Disable tracing
50 * - pr_info: Print this info to the console
51 * - trace_printk: Print this info to trace buffer (good for verbose logging)
52 */
53
54#define DWC2_TRACE_SCHEDULER no_printk
55#define DWC2_TRACE_SCHEDULER_VB no_printk
56
57/* Detailed scheduler tracing, but won't overwhelm console */
58#define dwc2_sch_dbg(hsotg, fmt, ...) \
59 DWC2_TRACE_SCHEDULER(pr_fmt("%s: SCH: " fmt), \
60 dev_name(hsotg->dev), ##__VA_ARGS__)
61
62/* Verbose scheduler tracing */
63#define dwc2_sch_vdbg(hsotg, fmt, ...) \
64 DWC2_TRACE_SCHEDULER_VB(pr_fmt("%s: SCH: " fmt), \
65 dev_name(hsotg->dev), ##__VA_ARGS__)
66
95c8bc36 67static inline u32 dwc2_readl(const void __iomem *addr)
56f5b1cf 68{
95c8bc36
AS		 69 u32 value = __raw_readl(addr);
70
71 /* In order to preserve endianness __raw_* operation is used. Therefore
72 * a barrier is needed to ensure IO access is not re-ordered across
73 * reads or writes
74 */
75 mb();
76 return value;
56f5b1cf
PZ		 77}
78
95c8bc36
AS		 79static inline void dwc2_writel(u32 value, void __iomem *addr)
80{
81 __raw_writel(value, addr);
82
83 /*
84 * In order to preserve endianness __raw_* operation is used. Therefore
85 * a barrier is needed to ensure IO access is not re-ordered across
86 * reads or writes
87 */
88 mb();
89#ifdef DWC2_LOG_WRITES
90 pr_info("INFO:: wrote %08x to %p\n", value, addr);
56f5b1cf 91#endif
95c8bc36 92}
56f5b1cf
PZ		 93
94/* Maximum number of Endpoints/HostChannels */
95#define MAX_EPS_CHANNELS 16
96
1f91b4cc
FB		 97/* dwc2-hsotg declarations */
98static const char * const dwc2_hsotg_supply_names[] = {
f7c0b143
DN		 99 "vusb_d", /* digital USB supply, 1.2V */
100 "vusb_a", /* analog USB supply, 1.1V */
101};
102
103/*
104 * EP0_MPS_LIMIT
105 *
106 * Unfortunately there seems to be a limit of the amount of data that can
107 * be transferred by IN transactions on EP0. This is either 127 bytes or 3
108 * packets (which practically means 1 packet and 63 bytes of data) when the
109 * MPS is set to 64.
110 *
111 * This means if we are wanting to move >127 bytes of data, we need to
112 * split the transactions up, but just doing one packet at a time does
113 * not work (this may be an implicit DATA0 PID on first packet of the
114 * transaction) and doing 2 packets is outside the controller's limits.
115 *
116 * If we try to lower the MPS size for EP0, then no transfers work properly
117 * for EP0, and the system will fail basic enumeration. As no cause for this
118 * has currently been found, we cannot support any large IN transfers for
119 * EP0.
120 */
121#define EP0_MPS_LIMIT 64
122
941fcce4 123struct dwc2_hsotg;
1f91b4cc 124struct dwc2_hsotg_req;
f7c0b143
DN		 125
126/**
1f91b4cc 127 * struct dwc2_hsotg_ep - driver endpoint definition.
f7c0b143
DN		 128 * @ep: The gadget layer representation of the endpoint.
129 * @name: The driver generated name for the endpoint.
130 * @queue: Queue of requests for this endpoint.
131 * @parent: Reference back to the parent device structure.
132 * @req: The current request that the endpoint is processing. This is
133 * used to indicate an request has been loaded onto the endpoint
134 * and has yet to be completed (maybe due to data move, or simply
135 * awaiting an ack from the core all the data has been completed).
136 * @debugfs: File entry for debugfs file for this endpoint.
137 * @lock: State lock to protect contents of endpoint.
138 * @dir_in: Set to true if this endpoint is of the IN direction, which
139 * means that it is sending data to the Host.
140 * @index: The index for the endpoint registers.
141 * @mc: Multi Count - number of transactions per microframe
142 * @interval - Interval for periodic endpoints
143 * @name: The name array passed to the USB core.
144 * @halted: Set if the endpoint has been halted.
145 * @periodic: Set if this is a periodic ep, such as Interrupt
146 * @isochronous: Set if this is a isochronous ep
8a20fa45 147 * @send_zlp: Set if we need to send a zero-length packet.
f7c0b143
DN		 148 * @total_data: The total number of data bytes done.
149 * @fifo_size: The size of the FIFO (for periodic IN endpoints)
150 * @fifo_load: The amount of data loaded into the FIFO (periodic IN)
151 * @last_load: The offset of data for the last start of request.
152 * @size_loaded: The last loaded size for DxEPTSIZE for periodic IN
153 *
154 * This is the driver's state for each registered enpoint, allowing it
155 * to keep track of transactions that need doing. Each endpoint has a
156 * lock to protect the state, to try and avoid using an overall lock
157 * for the host controller as much as possible.
158 *
159 * For periodic IN endpoints, we have fifo_size and fifo_load to try
160 * and keep track of the amount of data in the periodic FIFO for each
161 * of these as we don't have a status register that tells us how much
162 * is in each of them. (note, this may actually be useless information
163 * as in shared-fifo mode periodic in acts like a single-frame packet
164 * buffer than a fifo)
165 */
1f91b4cc 166struct dwc2_hsotg_ep {
f7c0b143
DN		 167 struct usb_ep ep;
168 struct list_head queue;
941fcce4 169 struct dwc2_hsotg *parent;
1f91b4cc 170 struct dwc2_hsotg_req *req;
f7c0b143
DN		 171 struct dentry *debugfs;
172
173 unsigned long total_data;
174 unsigned int size_loaded;
175 unsigned int last_load;
176 unsigned int fifo_load;
177 unsigned short fifo_size;
b203d0a2 178 unsigned short fifo_index;
f7c0b143
DN		 179
180 unsigned char dir_in;
181 unsigned char index;
182 unsigned char mc;
183 unsigned char interval;
184
185 unsigned int halted:1;
186 unsigned int periodic:1;
187 unsigned int isochronous:1;
8a20fa45 188 unsigned int send_zlp:1;
ec1f9d9f 189 unsigned int has_correct_parity:1;
f7c0b143
DN		 190
191 char name[10];
192};
193
f7c0b143 194/**
1f91b4cc 195 * struct dwc2_hsotg_req - data transfer request
f7c0b143
DN		 196 * @req: The USB gadget request
197 * @queue: The list of requests for the endpoint this is queued for.
7d24c1b5 198 * @saved_req_buf: variable to save req.buf when bounce buffers are used.
f7c0b143 199 */
1f91b4cc 200struct dwc2_hsotg_req {
f7c0b143
DN		 201 struct usb_request req;
202 struct list_head queue;
7d24c1b5 203 void *saved_req_buf;
f7c0b143
DN		 204};
205
941fcce4 206#if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
f7c0b143
DN		 207#define call_gadget(_hs, _entry) \
208do { \
209 if ((_hs)->gadget.speed != USB_SPEED_UNKNOWN && \
210 (_hs)->driver && (_hs)->driver->_entry) { \
211 spin_unlock(&_hs->lock); \
212 (_hs)->driver->_entry(&(_hs)->gadget); \
213 spin_lock(&_hs->lock); \
214 } \
215} while (0)
941fcce4
DN		 216#else
217#define call_gadget(_hs, _entry) do {} while (0)
218#endif
f7c0b143 219
56f5b1cf
PZ		 220struct dwc2_hsotg;
221struct dwc2_host_chan;
222
223/* Device States */
224enum dwc2_lx_state {
225 DWC2_L0, /* On state */
226 DWC2_L1, /* LPM sleep state */
227 DWC2_L2, /* USB suspend state */
228 DWC2_L3, /* Off state */
229};
230
0a176279
GH		 231/*
232 * Gadget periodic tx fifo sizes as used by legacy driver
233 * EP0 is not included
234 */
235#define DWC2_G_P_LEGACY_TX_FIFO_SIZE {256, 256, 256, 256, 768, 768, 768, \
236 768, 0, 0, 0, 0, 0, 0, 0}
237
fe0b94ab
MYK		 238/* Gadget ep0 states */
239enum dwc2_ep0_state {
240 DWC2_EP0_SETUP,
241 DWC2_EP0_DATA_IN,
242 DWC2_EP0_DATA_OUT,
243 DWC2_EP0_STATUS_IN,
244 DWC2_EP0_STATUS_OUT,
245};
246
56f5b1cf
PZ		 247/**
248 * struct dwc2_core_params - Parameters for configuring the core
249 *
91121c10
MK		 250 * @otg_cap: Specifies the OTG capabilities.
251 * 0 - HNP and SRP capable
56f5b1cf 252 * 1 - SRP Only capable
91121c10
MK		 253 * 2 - No HNP/SRP capable (always available)
254 * Defaults to best available option (0, 1, then 2)
725acc86 255 * @otg_ver: OTG version supported
91121c10 256 * 0 - 1.3 (default)
725acc86 257 * 1 - 2.0
56f5b1cf
PZ		 258 * @dma_enable: Specifies whether to use slave or DMA mode for accessing
259 * the data FIFOs. The driver will automatically detect the
260 * value for this parameter if none is specified.
91121c10 261 * 0 - Slave (always available)
56f5b1cf
PZ		 262 * 1 - DMA (default, if available)
263 * @dma_desc_enable: When DMA mode is enabled, specifies whether to use
264 * address DMA mode or descriptor DMA mode for accessing
265 * the data FIFOs. The driver will automatically detect the
266 * value for this if none is specified.
267 * 0 - Address DMA
268 * 1 - Descriptor DMA (default, if available)
fbb9e22b
MYK		 269 * @dma_desc_fs_enable: When DMA mode is enabled, specifies whether to use
270 * address DMA mode or descriptor DMA mode for accessing
271 * the data FIFOs in Full Speed mode only. The driver
272 * will automatically detect the value for this if none is
273 * specified.
274 * 0 - Address DMA
275 * 1 - Descriptor DMA in FS (default, if available)
56f5b1cf
PZ		 276 * @speed: Specifies the maximum speed of operation in host and
277 * device mode. The actual speed depends on the speed of
278 * the attached device and the value of phy_type.
91121c10
MK		 279 * 0 - High Speed
280 * (default when phy_type is UTMI+ or ULPI)
56f5b1cf 281 * 1 - Full Speed
91121c10 282 * (default when phy_type is Full Speed)
56f5b1cf 283 * @enable_dynamic_fifo: 0 - Use coreConsultant-specified FIFO size parameters
91121c10 284 * 1 - Allow dynamic FIFO sizing (default, if available)
725acc86
PZ		 285 * @en_multiple_tx_fifo: Specifies whether dedicated per-endpoint transmit FIFOs
286 * are enabled
56f5b1cf
PZ		 287 * @host_rx_fifo_size: Number of 4-byte words in the Rx FIFO in host mode when
288 * dynamic FIFO sizing is enabled
91121c10
MK		 289 * 16 to 32768
290 * Actual maximum value is autodetected and also
291 * the default.
56f5b1cf
PZ		 292 * @host_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO
293 * in host mode when dynamic FIFO sizing is enabled
91121c10
MK		 294 * 16 to 32768
295 * Actual maximum value is autodetected and also
296 * the default.
56f5b1cf
PZ		 297 * @host_perio_tx_fifo_size: Number of 4-byte words in the periodic Tx FIFO in
298 * host mode when dynamic FIFO sizing is enabled
91121c10
MK		 299 * 16 to 32768
300 * Actual maximum value is autodetected and also
301 * the default.
56f5b1cf 302 * @max_transfer_size: The maximum transfer size supported, in bytes
91121c10
MK		 303 * 2047 to 65,535
304 * Actual maximum value is autodetected and also
305 * the default.
56f5b1cf 306 * @max_packet_count: The maximum number of packets in a transfer
91121c10
MK		 307 * 15 to 511
308 * Actual maximum value is autodetected and also
309 * the default.
56f5b1cf 310 * @host_channels: The number of host channel registers to use
91121c10
MK		 311 * 1 to 16
312 * Actual maximum value is autodetected and also
313 * the default.
56f5b1cf
PZ		 314 * @phy_type: Specifies the type of PHY interface to use. By default,
315 * the driver will automatically detect the phy_type.
91121c10
MK		 316 * 0 - Full Speed Phy
317 * 1 - UTMI+ Phy
318 * 2 - ULPI Phy
319 * Defaults to best available option (2, 1, then 0)
56f5b1cf
PZ		 320 * @phy_utmi_width: Specifies the UTMI+ Data Width (in bits). This parameter
321 * is applicable for a phy_type of UTMI+ or ULPI. (For a
322 * ULPI phy_type, this parameter indicates the data width
323 * between the MAC and the ULPI Wrapper.) Also, this
324 * parameter is applicable only if the OTG_HSPHY_WIDTH cC
325 * parameter was set to "8 and 16 bits", meaning that the
326 * core has been configured to work at either data path
327 * width.
91121c10 328 * 8 or 16 (default 16 if available)
56f5b1cf
PZ		 329 * @phy_ulpi_ddr: Specifies whether the ULPI operates at double or single
330 * data rate. This parameter is only applicable if phy_type
331 * is ULPI.
332 * 0 - single data rate ULPI interface with 8 bit wide
333 * data bus (default)
334 * 1 - double data rate ULPI interface with 4 bit wide
335 * data bus
336 * @phy_ulpi_ext_vbus: For a ULPI phy, specifies whether to use the internal or
337 * external supply to drive the VBus
91121c10
MK		 338 * 0 - Internal supply (default)
339 * 1 - External supply
56f5b1cf
PZ		 340 * @i2c_enable: Specifies whether to use the I2Cinterface for a full
341 * speed PHY. This parameter is only applicable if phy_type
342 * is FS.
343 * 0 - No (default)
344 * 1 - Yes
91121c10
MK		 345 * @ulpi_fs_ls: Make ULPI phy operate in FS/LS mode only
346 * 0 - No (default)
347 * 1 - Yes
725acc86
PZ		 348 * @host_support_fs_ls_low_power: Specifies whether low power mode is supported
349 * when attached to a Full Speed or Low Speed device in
350 * host mode.
351 * 0 - Don't support low power mode (default)
352 * 1 - Support low power mode
353 * @host_ls_low_power_phy_clk: Specifies the PHY clock rate in low power mode
91121c10
MK		 354 * when connected to a Low Speed device in host
355 * mode. This parameter is applicable only if
356 * host_support_fs_ls_low_power is enabled.
725acc86 357 * 0 - 48 MHz
91121c10 358 * (default when phy_type is UTMI+ or ULPI)
725acc86 359 * 1 - 6 MHz
91121c10
MK		 360 * (default when phy_type is Full Speed)
361 * @ts_dline: Enable Term Select Dline pulsing
362 * 0 - No (default)
363 * 1 - Yes
364 * @reload_ctl: Allow dynamic reloading of HFIR register during runtime
365 * 0 - No (default for core < 2.92a)
366 * 1 - Yes (default for core >= 2.92a)
4d3190e1
PZ		 367 * @ahbcfg: This field allows the default value of the GAHBCFG
368 * register to be overridden
91121c10
MK		 369 * -1 - GAHBCFG value will be set to 0x06
370 * (INCR4, default)
4d3190e1
PZ		 371 * all others - GAHBCFG value will be overridden with
372 * this value
91121c10
MK		 373 * Not all bits can be controlled like this, the
374 * bits defined by GAHBCFG_CTRL_MASK are controlled
375 * by the driver and are ignored in this
376 * configuration value.
20f2eb9c 377 * @uframe_sched: True to enable the microframe scheduler
a6d249d8
GH		 378 * @external_id_pin_ctl: Specifies whether ID pin is handled externally.
379 * Disable CONIDSTSCHNG controller interrupt in such
380 * case.
381 * 0 - No (default)
382 * 1 - Yes
285046aa
GH		 383 * @hibernation: Specifies whether the controller support hibernation.
384 * If hibernation is enabled, the controller will enter
385 * hibernation in both peripheral and host mode when
386 * needed.
387 * 0 - No (default)
388 * 1 - Yes
56f5b1cf
PZ		 389 *
390 * The following parameters may be specified when starting the module. These
91121c10
MK		 391 * parameters define how the DWC_otg controller should be configured. A
392 * value of -1 (or any other out of range value) for any parameter means
393 * to read the value from hardware (if possible) or use the builtin
394 * default described above.
56f5b1cf
PZ		 395 */
396struct dwc2_core_params {
8284f93b
MK		 397 /*
398 * Don't add any non-int members here, this will break
399 * dwc2_set_all_params!
400 */
56f5b1cf
PZ		 401 int otg_cap;
402 int otg_ver;
403 int dma_enable;
404 int dma_desc_enable;
fbb9e22b 405 int dma_desc_fs_enable;
56f5b1cf
PZ		 406 int speed;
407 int enable_dynamic_fifo;
408 int en_multiple_tx_fifo;
409 int host_rx_fifo_size;
410 int host_nperio_tx_fifo_size;
411 int host_perio_tx_fifo_size;
412 int max_transfer_size;
413 int max_packet_count;
414 int host_channels;
415 int phy_type;
416 int phy_utmi_width;
417 int phy_ulpi_ddr;
418 int phy_ulpi_ext_vbus;
419 int i2c_enable;
420 int ulpi_fs_ls;
421 int host_support_fs_ls_low_power;
422 int host_ls_low_power_phy_clk;
423 int ts_dline;
424 int reload_ctl;
4d3190e1 425 int ahbcfg;
20f2eb9c 426 int uframe_sched;
a6d249d8 427 int external_id_pin_ctl;
285046aa 428 int hibernation;
56f5b1cf
PZ		 429};
430
9badec2f
MK		 431/**
432 * struct dwc2_hw_params - Autodetected parameters.
433 *
434 * These parameters are the various parameters read from hardware
435 * registers during initialization. They typically contain the best
436 * supported or maximum value that can be configured in the
437 * corresponding dwc2_core_params value.
438 *
439 * The values that are not in dwc2_core_params are documented below.
440 *
441 * @op_mode Mode of Operation
442 * 0 - HNP- and SRP-Capable OTG (Host & Device)
443 * 1 - SRP-Capable OTG (Host & Device)
444 * 2 - Non-HNP and Non-SRP Capable OTG (Host & Device)
445 * 3 - SRP-Capable Device
446 * 4 - Non-OTG Device
447 * 5 - SRP-Capable Host
448 * 6 - Non-OTG Host
449 * @arch Architecture
450 * 0 - Slave only
451 * 1 - External DMA
452 * 2 - Internal DMA
453 * @power_optimized Are power optimizations enabled?
454 * @num_dev_ep Number of device endpoints available
455 * @num_dev_perio_in_ep Number of device periodic IN endpoints
997f4f81 456 * available
9badec2f
MK		 457 * @dev_token_q_depth Device Mode IN Token Sequence Learning Queue
458 * Depth
459 * 0 to 30
460 * @host_perio_tx_q_depth
461 * Host Mode Periodic Request Queue Depth
462 * 2, 4 or 8
463 * @nperio_tx_q_depth
464 * Non-Periodic Request Queue Depth
465 * 2, 4 or 8
466 * @hs_phy_type High-speed PHY interface type
467 * 0 - High-speed interface not supported
468 * 1 - UTMI+
469 * 2 - ULPI
470 * 3 - UTMI+ and ULPI
471 * @fs_phy_type Full-speed PHY interface type
472 * 0 - Full speed interface not supported
473 * 1 - Dedicated full speed interface
474 * 2 - FS pins shared with UTMI+ pins
475 * 3 - FS pins shared with ULPI pins
476 * @total_fifo_size: Total internal RAM for FIFOs (bytes)
de4a1931
MK		 477 * @utmi_phy_data_width UTMI+ PHY data width
478 * 0 - 8 bits
479 * 1 - 16 bits
480 * 2 - 8 or 16 bits
9badec2f 481 * @snpsid: Value from SNPSID register
55e1040e 482 * @dev_ep_dirs: Direction of device endpoints (GHWCFG1)
9badec2f
MK		 483 */
484struct dwc2_hw_params {
485 unsigned op_mode:3;
486 unsigned arch:2;
487 unsigned dma_desc_enable:1;
fbb9e22b 488 unsigned dma_desc_fs_enable:1;
9badec2f
MK		 489 unsigned enable_dynamic_fifo:1;
490 unsigned en_multiple_tx_fifo:1;
491 unsigned host_rx_fifo_size:16;
492 unsigned host_nperio_tx_fifo_size:16;
55e1040e 493 unsigned dev_nperio_tx_fifo_size:16;
9badec2f
MK		 494 unsigned host_perio_tx_fifo_size:16;
495 unsigned nperio_tx_q_depth:3;
496 unsigned host_perio_tx_q_depth:3;
497 unsigned dev_token_q_depth:5;
498 unsigned max_transfer_size:26;
499 unsigned max_packet_count:11;
2d115547 500 unsigned host_channels:5;
9badec2f
MK		 501 unsigned hs_phy_type:2;
502 unsigned fs_phy_type:2;
503 unsigned i2c_enable:1;
504 unsigned num_dev_ep:4;
505 unsigned num_dev_perio_in_ep:4;
506 unsigned total_fifo_size:16;
507 unsigned power_optimized:1;
de4a1931 508 unsigned utmi_phy_data_width:2;
9badec2f 509 u32 snpsid;
55e1040e 510 u32 dev_ep_dirs;
9badec2f
MK		 511};
512
3f95001d
MYK		 513/* Size of control and EP0 buffers */
514#define DWC2_CTRL_BUFF_SIZE 8
515
d17ee77b
GH		 516/**
517 * struct dwc2_gregs_backup - Holds global registers state before entering partial
518 * power down
519 * @gotgctl: Backup of GOTGCTL register
520 * @gintmsk: Backup of GINTMSK register
521 * @gahbcfg: Backup of GAHBCFG register
522 * @gusbcfg: Backup of GUSBCFG register
523 * @grxfsiz: Backup of GRXFSIZ register
524 * @gnptxfsiz: Backup of GNPTXFSIZ register
525 * @gi2cctl: Backup of GI2CCTL register
526 * @hptxfsiz: Backup of HPTXFSIZ register
527 * @gdfifocfg: Backup of GDFIFOCFG register
528 * @dtxfsiz: Backup of DTXFSIZ registers for each endpoint
529 * @gpwrdn: Backup of GPWRDN register
530 */
531struct dwc2_gregs_backup {
532 u32 gotgctl;
533 u32 gintmsk;
534 u32 gahbcfg;
535 u32 gusbcfg;
536 u32 grxfsiz;
537 u32 gnptxfsiz;
538 u32 gi2cctl;
539 u32 hptxfsiz;
540 u32 pcgcctl;
541 u32 gdfifocfg;
542 u32 dtxfsiz[MAX_EPS_CHANNELS];
543 u32 gpwrdn;
cc1e204c 544 bool valid;
d17ee77b
GH		 545};
546
547/**
548 * struct dwc2_dregs_backup - Holds device registers state before entering partial
549 * power down
550 * @dcfg: Backup of DCFG register
551 * @dctl: Backup of DCTL register
552 * @daintmsk: Backup of DAINTMSK register
553 * @diepmsk: Backup of DIEPMSK register
554 * @doepmsk: Backup of DOEPMSK register
555 * @diepctl: Backup of DIEPCTL register
556 * @dieptsiz: Backup of DIEPTSIZ register
557 * @diepdma: Backup of DIEPDMA register
558 * @doepctl: Backup of DOEPCTL register
559 * @doeptsiz: Backup of DOEPTSIZ register
560 * @doepdma: Backup of DOEPDMA register
561 */
562struct dwc2_dregs_backup {
563 u32 dcfg;
564 u32 dctl;
565 u32 daintmsk;
566 u32 diepmsk;
567 u32 doepmsk;
568 u32 diepctl[MAX_EPS_CHANNELS];
569 u32 dieptsiz[MAX_EPS_CHANNELS];
570 u32 diepdma[MAX_EPS_CHANNELS];
571 u32 doepctl[MAX_EPS_CHANNELS];
572 u32 doeptsiz[MAX_EPS_CHANNELS];
573 u32 doepdma[MAX_EPS_CHANNELS];
cc1e204c 574 bool valid;
d17ee77b
GH		 575};
576
577/**
578 * struct dwc2_hregs_backup - Holds host registers state before entering partial
579 * power down
580 * @hcfg: Backup of HCFG register
581 * @haintmsk: Backup of HAINTMSK register
582 * @hcintmsk: Backup of HCINTMSK register
583 * @hptr0: Backup of HPTR0 register
584 * @hfir: Backup of HFIR register
585 */
586struct dwc2_hregs_backup {
587 u32 hcfg;
588 u32 haintmsk;
589 u32 hcintmsk[MAX_EPS_CHANNELS];
590 u32 hprt0;
591 u32 hfir;
cc1e204c 592 bool valid;
d17ee77b
GH		 593};
594
9f9f09b0
DA		 595/*
596 * Constants related to high speed periodic scheduling
597 *
598 * We have a periodic schedule that is DWC2_HS_SCHEDULE_UFRAMES long. From a
599 * reservation point of view it's assumed that the schedule goes right back to
600 * the beginning after the end of the schedule.
601 *
602 * What does that mean for scheduling things with a long interval? It means
603 * we'll reserve time for them in every possible microframe that they could
604 * ever be scheduled in. ...but we'll still only actually schedule them as
605 * often as they were requested.
606 *
607 * We keep our schedule in a "bitmap" structure. This simplifies having
608 * to keep track of and merge intervals: we just let the bitmap code do most
609 * of the heavy lifting. In a way scheduling is much like memory allocation.
610 *
611 * We schedule 100us per uframe or 80% of 125us (the maximum amount you're
612 * supposed to schedule for periodic transfers). That's according to spec.
613 *
614 * Note that though we only schedule 80% of each microframe, the bitmap that we
615 * keep the schedule in is tightly packed (AKA it doesn't have 100us worth of
616 * space for each uFrame).
617 *
618 * Requirements:
619 * - DWC2_HS_SCHEDULE_UFRAMES must even divide 0x4000 (HFNUM_MAX_FRNUM + 1)
620 * - DWC2_HS_SCHEDULE_UFRAMES must be 8 times DWC2_LS_SCHEDULE_FRAMES (probably
621 * could be any multiple of 8 times DWC2_LS_SCHEDULE_FRAMES, but there might
622 * be bugs). The 8 comes from the USB spec: number of microframes per frame.
623 */
624#define DWC2_US_PER_UFRAME 125
625#define DWC2_HS_PERIODIC_US_PER_UFRAME 100
626
627#define DWC2_HS_SCHEDULE_UFRAMES 8
628#define DWC2_HS_SCHEDULE_US (DWC2_HS_SCHEDULE_UFRAMES * \
629 DWC2_HS_PERIODIC_US_PER_UFRAME)
630
631/*
632 * Constants related to low speed scheduling
633 *
634 * For high speed we schedule every 1us. For low speed that's a bit overkill,
635 * so we make up a unit called a "slice" that's worth 25us. There are 40
636 * slices in a full frame and we can schedule 36 of those (90%) for periodic
637 * transfers.
638 *
639 * Our low speed schedule can be as short as 1 frame or could be longer. When
640 * we only schedule 1 frame it means that we'll need to reserve a time every
641 * frame even for things that only transfer very rarely, so something that runs
642 * every 2048 frames will get time reserved in every frame. Our low speed
643 * schedule can be longer and we'll be able to handle more overlap, but that
644 * will come at increased memory cost and increased time to schedule.
645 *
646 * Note: one other advantage of a short low speed schedule is that if we mess
647 * up and miss scheduling we can jump in and use any of the slots that we
648 * happened to reserve.
649 *
650 * With 25 us per slice and 1 frame in the schedule, we only need 4 bytes for
651 * the schedule. There will be one schedule per TT.
652 *
653 * Requirements:
654 * - DWC2_US_PER_SLICE must evenly divide DWC2_LS_PERIODIC_US_PER_FRAME.
655 */
656#define DWC2_US_PER_SLICE 25
657#define DWC2_SLICES_PER_UFRAME (DWC2_US_PER_UFRAME / DWC2_US_PER_SLICE)
658
659#define DWC2_ROUND_US_TO_SLICE(us) \
660 (DIV_ROUND_UP((us), DWC2_US_PER_SLICE) * \
661 DWC2_US_PER_SLICE)
662
663#define DWC2_LS_PERIODIC_US_PER_FRAME \
664 900
665#define DWC2_LS_PERIODIC_SLICES_PER_FRAME \
666 (DWC2_LS_PERIODIC_US_PER_FRAME / \
667 DWC2_US_PER_SLICE)
668
669#define DWC2_LS_SCHEDULE_FRAMES 1
670#define DWC2_LS_SCHEDULE_SLICES (DWC2_LS_SCHEDULE_FRAMES * \
671 DWC2_LS_PERIODIC_SLICES_PER_FRAME)
672
56f5b1cf
PZ		 673/**
674 * struct dwc2_hsotg - Holds the state of the driver, including the non-periodic
675 * and periodic schedules
676 *
941fcce4
DN		 677 * These are common for both host and peripheral modes:
678 *
56f5b1cf
PZ		 679 * @dev: The struct device pointer
680 * @regs: Pointer to controller regs
9badec2f
MK		 681 * @hw_params: Parameters that were autodetected from the
682 * hardware registers
941fcce4 683 * @core_params: Parameters that define how the core should be configured
56f5b1cf
PZ		 684 * @op_state: The operational State, during transitions (a_host=>
685 * a_peripheral and b_device=>b_host) this may not match
686 * the core, but allows the software to determine
687 * transitions
c0155b9d
KY		 688 * @dr_mode: Requested mode of operation, one of following:
689 * - USB_DR_MODE_PERIPHERAL
690 * - USB_DR_MODE_HOST
691 * - USB_DR_MODE_OTG
09a75e85
MS		 692 * @hcd_enabled Host mode sub-driver initialization indicator.
693 * @gadget_enabled Peripheral mode sub-driver initialization indicator.
694 * @ll_hw_enabled Status of low-level hardware resources.
695 * @phy: The otg phy transceiver structure for phy control.
696 * @uphy: The otg phy transceiver structure for old USB phy control.
697 * @plat: The platform specific configuration data. This can be removed once
698 * all SoCs support usb transceiver.
699 * @supplies: Definition of USB power supplies
700 * @phyif: PHY interface width
941fcce4
DN		 701 * @lock: Spinlock that protects all the driver data structures
702 * @priv: Stores a pointer to the struct usb_hcd
56f5b1cf
PZ		 703 * @queuing_high_bandwidth: True if multiple packets of a high-bandwidth
704 * transfer are in process of being queued
705 * @srp_success: Stores status of SRP request in the case of a FS PHY
706 * with an I2C interface
707 * @wq_otg: Workqueue object used for handling of some interrupts
708 * @wf_otg: Work object for handling Connector ID Status Change
709 * interrupt
710 * @wkp_timer: Timer object for handling Wakeup Detected interrupt
711 * @lx_state: Lx state of connected device
d17ee77b
GH		 712 * @gregs_backup: Backup of global registers during suspend
713 * @dregs_backup: Backup of device registers during suspend
714 * @hregs_backup: Backup of host registers during suspend
941fcce4
DN		 715 *
716 * These are for host mode:
717 *
56f5b1cf
PZ		 718 * @flags: Flags for handling root port state changes
719 * @non_periodic_sched_inactive: Inactive QHs in the non-periodic schedule.
720 * Transfers associated with these QHs are not currently
721 * assigned to a host channel.
722 * @non_periodic_sched_active: Active QHs in the non-periodic schedule.
723 * Transfers associated with these QHs are currently
724 * assigned to a host channel.
725 * @non_periodic_qh_ptr: Pointer to next QH to process in the active
726 * non-periodic schedule
727 * @periodic_sched_inactive: Inactive QHs in the periodic schedule. This is a
728 * list of QHs for periodic transfers that are _not_
729 * scheduled for the next frame. Each QH in the list has an
730 * interval counter that determines when it needs to be
731 * scheduled for execution. This scheduling mechanism
732 * allows only a simple calculation for periodic bandwidth
733 * used (i.e. must assume that all periodic transfers may
734 * need to execute in the same frame). However, it greatly
735 * simplifies scheduling and should be sufficient for the
736 * vast majority of OTG hosts, which need to connect to a
737 * small number of peripherals at one time. Items move from
738 * this list to periodic_sched_ready when the QH interval
739 * counter is 0 at SOF.
740 * @periodic_sched_ready: List of periodic QHs that are ready for execution in
741 * the next frame, but have not yet been assigned to host
742 * channels. Items move from this list to
743 * periodic_sched_assigned as host channels become
744 * available during the current frame.
745 * @periodic_sched_assigned: List of periodic QHs to be executed in the next
746 * frame that are assigned to host channels. Items move
747 * from this list to periodic_sched_queued as the
748 * transactions for the QH are queued to the DWC_otg
749 * controller.
750 * @periodic_sched_queued: List of periodic QHs that have been queued for
751 * execution. Items move from this list to either
752 * periodic_sched_inactive or periodic_sched_ready when the
753 * channel associated with the transfer is released. If the
754 * interval for the QH is 1, the item moves to
755 * periodic_sched_ready because it must be rescheduled for
756 * the next frame. Otherwise, the item moves to
757 * periodic_sched_inactive.
c9c8ac01 758 * @split_order: List keeping track of channels doing splits, in order.
56f5b1cf
PZ		 759 * @periodic_usecs: Total bandwidth claimed so far for periodic transfers.
760 * This value is in microseconds per (micro)frame. The
761 * assumption is that all periodic transfers may occur in
762 * the same (micro)frame.
9f9f09b0
DA		 763 * @hs_periodic_bitmap: Bitmap used by the microframe scheduler any time the
764 * host is in high speed mode; low speed schedules are
765 * stored elsewhere since we need one per TT.
56f5b1cf
PZ		 766 * @frame_number: Frame number read from the core at SOF. The value ranges
767 * from 0 to HFNUM_MAX_FRNUM.
768 * @periodic_qh_count: Count of periodic QHs, if using several eps. Used for
769 * SOF enable/disable.
770 * @free_hc_list: Free host channels in the controller. This is a list of
771 * struct dwc2_host_chan items.
772 * @periodic_channels: Number of host channels assigned to periodic transfers.
773 * Currently assuming that there is a dedicated host
774 * channel for each periodic transaction and at least one
775 * host channel is available for non-periodic transactions.
776 * @non_periodic_channels: Number of host channels assigned to non-periodic
777 * transfers
20f2eb9c
DC		 778 * @available_host_channels Number of host channels available for the microframe
779 * scheduler to use
56f5b1cf
PZ		 780 * @hc_ptr_array: Array of pointers to the host channel descriptors.
781 * Allows accessing a host channel descriptor given the
782 * host channel number. This is useful in interrupt
783 * handlers.
784 * @status_buf: Buffer used for data received during the status phase of
785 * a control transfer.
786 * @status_buf_dma: DMA address for status_buf
787 * @start_work: Delayed work for handling host A-cable connection
788 * @reset_work: Delayed work for handling a port reset
56f5b1cf
PZ		 789 * @otg_port: OTG port number
790 * @frame_list: Frame list
791 * @frame_list_dma: Frame list DMA address
95105a99 792 * @frame_list_sz: Frame list size
3b5fcc9a
GH		 793 * @desc_gen_cache: Kmem cache for generic descriptors
794 * @desc_hsisoc_cache: Kmem cache for hs isochronous descriptors
941fcce4
DN		 795 *
796 * These are for peripheral mode:
797 *
798 * @driver: USB gadget driver
941fcce4
DN		 799 * @dedicated_fifos: Set if the hardware has dedicated IN-EP fifos.
800 * @num_of_eps: Number of available EPs (excluding EP0)
801 * @debug_root: Root directrory for debugfs.
802 * @debug_file: Main status file for debugfs.
9e14d0a5 803 * @debug_testmode: Testmode status file for debugfs.
941fcce4
DN		 804 * @debug_fifo: FIFO status file for debugfs.
805 * @ep0_reply: Request used for ep0 reply.
806 * @ep0_buff: Buffer for EP0 reply data, if needed.
807 * @ctrl_buff: Buffer for EP0 control requests.
808 * @ctrl_req: Request for EP0 control packets.
fe0b94ab 809 * @ep0_state: EP0 control transfers state
9e14d0a5 810 * @test_mode: USB test mode requested by the host
941fcce4 811 * @eps: The endpoints being supplied to the gadget framework
edd74be8 812 * @g_using_dma: Indicate if dma usage is enabled
0a176279
GH		 813 * @g_rx_fifo_sz: Contains rx fifo size value
814 * @g_np_g_tx_fifo_sz: Contains Non-Periodic tx fifo size value
815 * @g_tx_fifo_sz: Contains tx fifo size value per endpoints
56f5b1cf
PZ		 816 */
817struct dwc2_hsotg {
818 struct device *dev;
819 void __iomem *regs;
9badec2f
MK		 820 /** Params detected from hardware */
821 struct dwc2_hw_params hw_params;
822 /** Params to actually use */
56f5b1cf 823 struct dwc2_core_params *core_params;
56f5b1cf 824 enum usb_otg_state op_state;
c0155b9d 825 enum usb_dr_mode dr_mode;
e39af88f
MS		 826 unsigned int hcd_enabled:1;
827 unsigned int gadget_enabled:1;
09a75e85 828 unsigned int ll_hw_enabled:1;
56f5b1cf 829
941fcce4
DN		 830 struct phy *phy;
831 struct usb_phy *uphy;
09a75e85 832 struct dwc2_hsotg_plat *plat;
1f91b4cc 833 struct regulator_bulk_data supplies[ARRAY_SIZE(dwc2_hsotg_supply_names)];
09a75e85 834 u32 phyif;
941fcce4
DN		 835
836 spinlock_t lock;
837 void *priv;
838 int irq;
839 struct clk *clk;
840
56f5b1cf
PZ		 841 unsigned int queuing_high_bandwidth:1;
842 unsigned int srp_success:1;
843
844 struct workqueue_struct *wq_otg;
845 struct work_struct wf_otg;
846 struct timer_list wkp_timer;
847 enum dwc2_lx_state lx_state;
cc1e204c
MYK		 848 struct dwc2_gregs_backup gr_backup;
849 struct dwc2_dregs_backup dr_backup;
850 struct dwc2_hregs_backup hr_backup;
56f5b1cf 851
941fcce4 852 struct dentry *debug_root;
563cf017 853 struct debugfs_regset32 *regset;
941fcce4
DN		 854
855 /* DWC OTG HW Release versions */
856#define DWC2_CORE_REV_2_71a 0x4f54271a
857#define DWC2_CORE_REV_2_90a 0x4f54290a
858#define DWC2_CORE_REV_2_92a 0x4f54292a
859#define DWC2_CORE_REV_2_94a 0x4f54294a
860#define DWC2_CORE_REV_3_00a 0x4f54300a
861
862#if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
56f5b1cf
PZ		 863 union dwc2_hcd_internal_flags {
864 u32 d32;
865 struct {
866 unsigned port_connect_status_change:1;
867 unsigned port_connect_status:1;
868 unsigned port_reset_change:1;
869 unsigned port_enable_change:1;
870 unsigned port_suspend_change:1;
871 unsigned port_over_current_change:1;
872 unsigned port_l1_change:1;
fd4850cf 873 unsigned reserved:25;
56f5b1cf
PZ		 874 } b;
875 } flags;
876
877 struct list_head non_periodic_sched_inactive;
878 struct list_head non_periodic_sched_active;
879 struct list_head *non_periodic_qh_ptr;
880 struct list_head periodic_sched_inactive;
881 struct list_head periodic_sched_ready;
882 struct list_head periodic_sched_assigned;
883 struct list_head periodic_sched_queued;
c9c8ac01 884 struct list_head split_order;
56f5b1cf 885 u16 periodic_usecs;
9f9f09b0
DA		 886 unsigned long hs_periodic_bitmap[
887 DIV_ROUND_UP(DWC2_HS_SCHEDULE_US, BITS_PER_LONG)];
56f5b1cf
PZ		 888 u16 frame_number;
889 u16 periodic_qh_count;
734643df 890 bool bus_suspended;
fbb9e22b 891 bool new_connection;
56f5b1cf 892
483bb254
DA		 893 u16 last_frame_num;
894
56f5b1cf
PZ		 895#ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
896#define FRAME_NUM_ARRAY_SIZE 1000
56f5b1cf
PZ		 897 u16 *frame_num_array;
898 u16 *last_frame_num_array;
899 int frame_num_idx;
900 int dumped_frame_num_array;
901#endif
902
903 struct list_head free_hc_list;
904 int periodic_channels;
905 int non_periodic_channels;
20f2eb9c 906 int available_host_channels;
56f5b1cf
PZ		 907 struct dwc2_host_chan *hc_ptr_array[MAX_EPS_CHANNELS];
908 u8 *status_buf;
909 dma_addr_t status_buf_dma;
910#define DWC2_HCD_STATUS_BUF_SIZE 64
911
912 struct delayed_work start_work;
913 struct delayed_work reset_work;
56f5b1cf
PZ		 914 u8 otg_port;
915 u32 *frame_list;
916 dma_addr_t frame_list_dma;
95105a99 917 u32 frame_list_sz;
3b5fcc9a
GH		 918 struct kmem_cache *desc_gen_cache;
919 struct kmem_cache *desc_hsisoc_cache;
56f5b1cf 920
56f5b1cf
PZ		 921#ifdef DEBUG
922 u32 frrem_samples;
923 u64 frrem_accum;
924
925 u32 hfnum_7_samples_a;
926 u64 hfnum_7_frrem_accum_a;
927 u32 hfnum_0_samples_a;
928 u64 hfnum_0_frrem_accum_a;
929 u32 hfnum_other_samples_a;
930 u64 hfnum_other_frrem_accum_a;
931
932 u32 hfnum_7_samples_b;
933 u64 hfnum_7_frrem_accum_b;
934 u32 hfnum_0_samples_b;
935 u64 hfnum_0_frrem_accum_b;
936 u32 hfnum_other_samples_b;
937 u64 hfnum_other_frrem_accum_b;
938#endif
941fcce4
DN		 939#endif /* CONFIG_USB_DWC2_HOST || CONFIG_USB_DWC2_DUAL_ROLE */
940
941#if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
942 /* Gadget structures */
943 struct usb_gadget_driver *driver;
941fcce4
DN		 944 int fifo_mem;
945 unsigned int dedicated_fifos:1;
946 unsigned char num_of_eps;
947 u32 fifo_map;
948
949 struct usb_request *ep0_reply;
950 struct usb_request *ctrl_req;
3f95001d
MYK		 951 void *ep0_buff;
952 void *ctrl_buff;
fe0b94ab 953 enum dwc2_ep0_state ep0_state;
9e14d0a5 954 u8 test_mode;
941fcce4
DN		 955
956 struct usb_gadget gadget;
dc6e69e6 957 unsigned int enabled:1;
4ace06e8 958 unsigned int connected:1;
1f91b4cc
FB		 959 struct dwc2_hsotg_ep *eps_in[MAX_EPS_CHANNELS];
960 struct dwc2_hsotg_ep *eps_out[MAX_EPS_CHANNELS];
edd74be8 961 u32 g_using_dma;
0a176279
GH		 962 u32 g_rx_fifo_sz;
963 u32 g_np_g_tx_fifo_sz;
964 u32 g_tx_fifo_sz[MAX_EPS_CHANNELS];
941fcce4 965#endif /* CONFIG_USB_DWC2_PERIPHERAL || CONFIG_USB_DWC2_DUAL_ROLE */
56f5b1cf
PZ		 966};
967
968/* Reasons for halting a host channel */
969enum dwc2_halt_status {
970 DWC2_HC_XFER_NO_HALT_STATUS,
971 DWC2_HC_XFER_COMPLETE,
972 DWC2_HC_XFER_URB_COMPLETE,
973 DWC2_HC_XFER_ACK,
974 DWC2_HC_XFER_NAK,
975 DWC2_HC_XFER_NYET,
976 DWC2_HC_XFER_STALL,
977 DWC2_HC_XFER_XACT_ERR,
978 DWC2_HC_XFER_FRAME_OVERRUN,
979 DWC2_HC_XFER_BABBLE_ERR,
980 DWC2_HC_XFER_DATA_TOGGLE_ERR,
981 DWC2_HC_XFER_AHB_ERR,
982 DWC2_HC_XFER_PERIODIC_INCOMPLETE,
983 DWC2_HC_XFER_URB_DEQUEUE,
984};
985
986/*
987 * The following functions support initialization of the core driver component
988 * and the DWC_otg controller
989 */
b5d308ab 990extern int dwc2_core_reset(struct dwc2_hsotg *hsotg);
6d58f346 991extern int dwc2_core_reset_and_force_dr_mode(struct dwc2_hsotg *hsotg);
56f5b1cf 992extern void dwc2_core_host_init(struct dwc2_hsotg *hsotg);
d17ee77b
GH		 993extern int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg);
994extern int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, bool restore);
56f5b1cf 995
09c96980
JY		 996void dwc2_force_dr_mode(struct dwc2_hsotg *hsotg);
997
56f5b1cf
PZ		 998/*
999 * Host core Functions.
1000 * The following functions support managing the DWC_otg controller in host
1001 * mode.
1002 */
1003extern void dwc2_hc_init(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan);
1004extern void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan,
1005 enum dwc2_halt_status halt_status);
1006extern void dwc2_hc_cleanup(struct dwc2_hsotg *hsotg,
1007 struct dwc2_host_chan *chan);
1008extern void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg,
1009 struct dwc2_host_chan *chan);
1010extern void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg,
1011 struct dwc2_host_chan *chan);
1012extern int dwc2_hc_continue_transfer(struct dwc2_hsotg *hsotg,
1013 struct dwc2_host_chan *chan);
1014extern void dwc2_hc_do_ping(struct dwc2_hsotg *hsotg,
1015 struct dwc2_host_chan *chan);
1016extern void dwc2_enable_host_interrupts(struct dwc2_hsotg *hsotg);
1017extern void dwc2_disable_host_interrupts(struct dwc2_hsotg *hsotg);
1018
1019extern u32 dwc2_calc_frame_interval(struct dwc2_hsotg *hsotg);
057715f2 1020extern bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg);
56f5b1cf
PZ		 1021
1022/*
1023 * Common core Functions.
1024 * The following functions support managing the DWC_otg controller in either
1025 * device or host mode.
1026 */
1027extern void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes);
1028extern void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num);
1029extern void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg);
1030
0fe239bc 1031extern int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup);
56f5b1cf
PZ		 1032extern void dwc2_enable_global_interrupts(struct dwc2_hsotg *hcd);
1033extern void dwc2_disable_global_interrupts(struct dwc2_hsotg *hcd);
1034
1035/* This function should be called on every hardware interrupt. */
1036extern irqreturn_t dwc2_handle_common_intr(int irq, void *dev);
1037
1038/* OTG Core Parameters */
1039
1040/*
1041 * Specifies the OTG capabilities. The driver will automatically
1042 * detect the value for this parameter if none is specified.
1043 * 0 - HNP and SRP capable (default)
1044 * 1 - SRP Only capable
1045 * 2 - No HNP/SRP capable
1046 */
7218dae7 1047extern void dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg, int val);
56f5b1cf
PZ		 1048#define DWC2_CAP_PARAM_HNP_SRP_CAPABLE 0
1049#define DWC2_CAP_PARAM_SRP_ONLY_CAPABLE 1
1050#define DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE 2
1051
1052/*
1053 * Specifies whether to use slave or DMA mode for accessing the data
1054 * FIFOs. The driver will automatically detect the value for this
1055 * parameter if none is specified.
1056 * 0 - Slave
1057 * 1 - DMA (default, if available)
1058 */
7218dae7 1059extern void dwc2_set_param_dma_enable(struct dwc2_hsotg *hsotg, int val);
56f5b1cf
PZ		 1060
1061/*
1062 * When DMA mode is enabled specifies whether to use
1063 * address DMA or DMA Descritor mode for accessing the data
1064 * FIFOs in device mode. The driver will automatically detect
1065 * the value for this parameter if none is specified.
1066 * 0 - address DMA
1067 * 1 - DMA Descriptor(default, if available)
1068 */
7218dae7 1069extern void dwc2_set_param_dma_desc_enable(struct dwc2_hsotg *hsotg, int val);
56f5b1cf 1070
fbb9e22b
MYK		 1071/*
1072 * When DMA mode is enabled specifies whether to use
1073 * address DMA or DMA Descritor mode with full speed devices
1074 * for accessing the data FIFOs in host mode.
1075 * 0 - address DMA
1076 * 1 - FS DMA Descriptor(default, if available)
1077 */
1078extern void dwc2_set_param_dma_desc_fs_enable(struct dwc2_hsotg *hsotg,
1079 int val);
1080
56f5b1cf
PZ		 1081/*
1082 * Specifies the maximum speed of operation in host and device mode.
1083 * The actual speed depends on the speed of the attached device and
1084 * the value of phy_type. The actual speed depends on the speed of the
1085 * attached device.
1086 * 0 - High Speed (default)
1087 * 1 - Full Speed
1088 */
7218dae7 1089extern void dwc2_set_param_speed(struct dwc2_hsotg *hsotg, int val);
56f5b1cf
PZ		 1090#define DWC2_SPEED_PARAM_HIGH 0
1091#define DWC2_SPEED_PARAM_FULL 1
1092
1093/*
1094 * Specifies whether low power mode is supported when attached
1095 * to a Full Speed or Low Speed device in host mode.
1096 *
1097 * 0 - Don't support low power mode (default)
1098 * 1 - Support low power mode
1099 */
7218dae7
PZ		 1100extern void dwc2_set_param_host_support_fs_ls_low_power(
1101 struct dwc2_hsotg *hsotg, int val);
56f5b1cf
PZ		 1102
1103/*
1104 * Specifies the PHY clock rate in low power mode when connected to a
1105 * Low Speed device in host mode. This parameter is applicable only if
1106 * HOST_SUPPORT_FS_LS_LOW_POWER is enabled. If PHY_TYPE is set to FS
1107 * then defaults to 6 MHZ otherwise 48 MHZ.
1108 *
1109 * 0 - 48 MHz
1110 * 1 - 6 MHz
1111 */
7218dae7
PZ		 1112extern void dwc2_set_param_host_ls_low_power_phy_clk(struct dwc2_hsotg *hsotg,
1113 int val);
56f5b1cf
PZ		 1114#define DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ 0
1115#define DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ 1
1116
1117/*
1118 * 0 - Use cC FIFO size parameters
1119 * 1 - Allow dynamic FIFO sizing (default)
1120 */
7218dae7
PZ		 1121extern void dwc2_set_param_enable_dynamic_fifo(struct dwc2_hsotg *hsotg,
1122 int val);
56f5b1cf
PZ		 1123
1124/*
1125 * Number of 4-byte words in the Rx FIFO in host mode when dynamic
1126 * FIFO sizing is enabled.
1127 * 16 to 32768 (default 1024)
1128 */
7218dae7 1129extern void dwc2_set_param_host_rx_fifo_size(struct dwc2_hsotg *hsotg, int val);
56f5b1cf
PZ		 1130
1131/*
1132 * Number of 4-byte words in the non-periodic Tx FIFO in host mode
1133 * when Dynamic FIFO sizing is enabled in the core.
1134 * 16 to 32768 (default 256)
1135 */
7218dae7
PZ		 1136extern void dwc2_set_param_host_nperio_tx_fifo_size(struct dwc2_hsotg *hsotg,
1137 int val);
56f5b1cf
PZ		 1138
1139/*
1140 * Number of 4-byte words in the host periodic Tx FIFO when dynamic
1141 * FIFO sizing is enabled.
1142 * 16 to 32768 (default 256)
1143 */
7218dae7
PZ		 1144extern void dwc2_set_param_host_perio_tx_fifo_size(struct dwc2_hsotg *hsotg,
1145 int val);
56f5b1cf
PZ		 1146
1147/*
1148 * The maximum transfer size supported in bytes.
1149 * 2047 to 65,535 (default 65,535)
1150 */
7218dae7 1151extern void dwc2_set_param_max_transfer_size(struct dwc2_hsotg *hsotg, int val);
56f5b1cf
PZ		 1152
1153/*
1154 * The maximum number of packets in a transfer.
1155 * 15 to 511 (default 511)
1156 */
7218dae7 1157extern void dwc2_set_param_max_packet_count(struct dwc2_hsotg *hsotg, int val);
56f5b1cf
PZ		 1158
1159/*
1160 * The number of host channel registers to use.
1161 * 1 to 16 (default 11)
1162 * Note: The FPGA configuration supports a maximum of 11 host channels.
1163 */
7218dae7 1164extern void dwc2_set_param_host_channels(struct dwc2_hsotg *hsotg, int val);
56f5b1cf
PZ		 1165
1166/*
1167 * Specifies the type of PHY interface to use. By default, the driver
1168 * will automatically detect the phy_type.
1169 *
1170 * 0 - Full Speed PHY
1171 * 1 - UTMI+ (default)
1172 * 2 - ULPI
1173 */
7218dae7 1174extern void dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg, int val);
56f5b1cf
PZ		 1175#define DWC2_PHY_TYPE_PARAM_FS 0
1176#define DWC2_PHY_TYPE_PARAM_UTMI 1
1177#define DWC2_PHY_TYPE_PARAM_ULPI 2
1178
1179/*
1180 * Specifies the UTMI+ Data Width. This parameter is
1181 * applicable for a PHY_TYPE of UTMI+ or ULPI. (For a ULPI
1182 * PHY_TYPE, this parameter indicates the data width between
1183 * the MAC and the ULPI Wrapper.) Also, this parameter is
1184 * applicable only if the OTG_HSPHY_WIDTH cC parameter was set
1185 * to "8 and 16 bits", meaning that the core has been
1186 * configured to work at either data path width.
1187 *
1188 * 8 or 16 bits (default 16)
1189 */
7218dae7 1190extern void dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg, int val);
56f5b1cf
PZ		 1191
1192/*
1193 * Specifies whether the ULPI operates at double or single
1194 * data rate. This parameter is only applicable if PHY_TYPE is
1195 * ULPI.
1196 *
1197 * 0 - single data rate ULPI interface with 8 bit wide data
1198 * bus (default)
1199 * 1 - double data rate ULPI interface with 4 bit wide data
1200 * bus
1201 */
7218dae7 1202extern void dwc2_set_param_phy_ulpi_ddr(struct dwc2_hsotg *hsotg, int val);
56f5b1cf
PZ		 1203
1204/*
1205 * Specifies whether to use the internal or external supply to
1206 * drive the vbus with a ULPI phy.
1207 */
7218dae7 1208extern void dwc2_set_param_phy_ulpi_ext_vbus(struct dwc2_hsotg *hsotg, int val);
56f5b1cf
PZ		 1209#define DWC2_PHY_ULPI_INTERNAL_VBUS 0
1210#define DWC2_PHY_ULPI_EXTERNAL_VBUS 1
1211
1212/*
1213 * Specifies whether to use the I2Cinterface for full speed PHY. This
1214 * parameter is only applicable if PHY_TYPE is FS.
1215 * 0 - No (default)
1216 * 1 - Yes
1217 */
7218dae7 1218extern void dwc2_set_param_i2c_enable(struct dwc2_hsotg *hsotg, int val);
56f5b1cf 1219
7218dae7 1220extern void dwc2_set_param_ulpi_fs_ls(struct dwc2_hsotg *hsotg, int val);
56f5b1cf 1221
7218dae7 1222extern void dwc2_set_param_ts_dline(struct dwc2_hsotg *hsotg, int val);
56f5b1cf
PZ		 1223
1224/*
1225 * Specifies whether dedicated transmit FIFOs are
1226 * enabled for non periodic IN endpoints in device mode
1227 * 0 - No
1228 * 1 - Yes
1229 */
7218dae7
PZ		 1230extern void dwc2_set_param_en_multiple_tx_fifo(struct dwc2_hsotg *hsotg,
1231 int val);
56f5b1cf 1232
7218dae7 1233extern void dwc2_set_param_reload_ctl(struct dwc2_hsotg *hsotg, int val);
56f5b1cf 1234
7218dae7 1235extern void dwc2_set_param_ahbcfg(struct dwc2_hsotg *hsotg, int val);
56f5b1cf 1236
7218dae7 1237extern void dwc2_set_param_otg_ver(struct dwc2_hsotg *hsotg, int val);
56f5b1cf 1238
ecb176c6
MYK		 1239extern void dwc2_set_parameters(struct dwc2_hsotg *hsotg,
1240 const struct dwc2_core_params *params);
1241
1242extern void dwc2_set_all_params(struct dwc2_core_params *params, int value);
1243
1244extern int dwc2_get_hwparams(struct dwc2_hsotg *hsotg);
1245
09a75e85
MS		 1246extern int dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg);
1247extern int dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg);
ecb176c6 1248
6bea9620
JY		 1249/*
1250 * The following functions check the controller's OTG operation mode
1251 * capability (GHWCFG2.OTG_MODE).
1252 *
1253 * These functions can be used before the internal hsotg->hw_params
1254 * are read in and cached so they always read directly from the
1255 * GHWCFG2 register.
1256 */
1257unsigned dwc2_op_mode(struct dwc2_hsotg *hsotg);
1258bool dwc2_hw_is_otg(struct dwc2_hsotg *hsotg);
1259bool dwc2_hw_is_host(struct dwc2_hsotg *hsotg);
1260bool dwc2_hw_is_device(struct dwc2_hsotg *hsotg);
1261
1696d5ab
JY		 1262/*
1263 * Returns the mode of operation, host or device
1264 */
1265static inline int dwc2_is_host_mode(struct dwc2_hsotg *hsotg)
1266{
1267 return (dwc2_readl(hsotg->regs + GINTSTS) & GINTSTS_CURMODE_HOST) != 0;
1268}
1269static inline int dwc2_is_device_mode(struct dwc2_hsotg *hsotg)
1270{
1271 return (dwc2_readl(hsotg->regs + GINTSTS) & GINTSTS_CURMODE_HOST) == 0;
1272}
1273
56f5b1cf
PZ		 1274/*
1275 * Dump core registers and SPRAM
1276 */
1277extern void dwc2_dump_dev_registers(struct dwc2_hsotg *hsotg);
1278extern void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg);
1279extern void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg);
1280
1281/*
1282 * Return OTG version - either 1.3 or 2.0
1283 */
1284extern u16 dwc2_get_otg_version(struct dwc2_hsotg *hsotg);
1285
117777b2
DN		 1286/* Gadget defines */
1287#if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
1f91b4cc
FB		 1288extern int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg);
1289extern int dwc2_hsotg_suspend(struct dwc2_hsotg *dwc2);
1290extern int dwc2_hsotg_resume(struct dwc2_hsotg *dwc2);
117777b2 1291extern int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq);
1f91b4cc 1292extern void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2,
643cc4de 1293 bool reset);
1f91b4cc
FB		 1294extern void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg);
1295extern void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2);
1296extern int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode);
f81f46e1 1297#define dwc2_is_device_connected(hsotg) (hsotg->connected)
117777b2 1298#else
1f91b4cc 1299static inline int dwc2_hsotg_remove(struct dwc2_hsotg *dwc2)
117777b2 1300{ return 0; }
1f91b4cc 1301static inline int dwc2_hsotg_suspend(struct dwc2_hsotg *dwc2)
117777b2 1302{ return 0; }
1f91b4cc 1303static inline int dwc2_hsotg_resume(struct dwc2_hsotg *dwc2)
117777b2
DN		 1304{ return 0; }
1305static inline int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq)
1306{ return 0; }
1f91b4cc 1307static inline void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2,
643cc4de 1308 bool reset) {}
1f91b4cc
FB		 1309static inline void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg) {}
1310static inline void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2) {}
1311static inline int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg,
f91eea44
MYK		 1312 int testmode)
1313{ return 0; }
f81f46e1 1314#define dwc2_is_device_connected(hsotg) (0)
117777b2
DN		 1315#endif
1316
1317#if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
1318extern int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg);
fae4e826 1319extern int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg, int us);
6a659531
DA		 1320extern void dwc2_hcd_connect(struct dwc2_hsotg *hsotg);
1321extern void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force);
117777b2
DN		 1322extern void dwc2_hcd_start(struct dwc2_hsotg *hsotg);
1323#else
117777b2
DN		 1324static inline int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg)
1325{ return 0; }
fae4e826
DA		 1326static inline int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg,
1327 int us)
1328{ return 0; }
6a659531
DA		 1329static inline void dwc2_hcd_connect(struct dwc2_hsotg *hsotg) {}
1330static inline void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force) {}
117777b2
DN		 1331static inline void dwc2_hcd_start(struct dwc2_hsotg *hsotg) {}
1332static inline void dwc2_hcd_remove(struct dwc2_hsotg *hsotg) {}
ecb176c6 1333static inline int dwc2_hcd_init(struct dwc2_hsotg *hsotg, int irq)
117777b2
DN		 1334{ return 0; }
1335#endif
1336
56f5b1cf 1337#endif /* __DWC2_CORE_H__ */
Linux 6.x block layer and io_uring tree(s)