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usb: dwc2: Update the gadget driver to use common dwc2_hsotg structure
[linux-block.git] / drivers / usb / dwc2 / core.h
CommitLineData
56f5b1cf
PZ		 1/*
2 * core.h - DesignWare HS OTG Controller common declarations
3 *
4 * Copyright (C) 2004-2013 Synopsys, Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions, and the following disclaimer,
11 * without modification.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The names of the above-listed copyright holders may not be used
16 * to endorse or promote products derived from this software without
17 * specific prior written permission.
18 *
19 * ALTERNATIVELY, this software may be distributed under the terms of the
20 * GNU General Public License ("GPL") as published by the Free Software
21 * Foundation; either version 2 of the License, or (at your option) any
22 * later version.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
25 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
28 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
29 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
30 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
31 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
32 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
33 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
34 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 */
36
37#ifndef __DWC2_CORE_H__
38#define __DWC2_CORE_H__
39
f7c0b143
DN		 40#include <linux/phy/phy.h>
41#include <linux/regulator/consumer.h>
42#include <linux/usb/gadget.h>
43#include <linux/usb/otg.h>
56f5b1cf
PZ		 44#include <linux/usb/phy.h>
45#include "hw.h"
46
47#ifdef DWC2_LOG_WRITES
48static inline void do_write(u32 value, void *addr)
49{
50 writel(value, addr);
51 pr_info("INFO:: wrote %08x to %p\n", value, addr);
52}
53
54#undef writel
55#define writel(v, a) do_write(v, a)
56#endif
57
58/* Maximum number of Endpoints/HostChannels */
59#define MAX_EPS_CHANNELS 16
60
f7c0b143
DN		 61/* s3c-hsotg declarations */
62static const char * const s3c_hsotg_supply_names[] = {
63 "vusb_d", /* digital USB supply, 1.2V */
64 "vusb_a", /* analog USB supply, 1.1V */
65};
66
67/*
68 * EP0_MPS_LIMIT
69 *
70 * Unfortunately there seems to be a limit of the amount of data that can
71 * be transferred by IN transactions on EP0. This is either 127 bytes or 3
72 * packets (which practically means 1 packet and 63 bytes of data) when the
73 * MPS is set to 64.
74 *
75 * This means if we are wanting to move >127 bytes of data, we need to
76 * split the transactions up, but just doing one packet at a time does
77 * not work (this may be an implicit DATA0 PID on first packet of the
78 * transaction) and doing 2 packets is outside the controller's limits.
79 *
80 * If we try to lower the MPS size for EP0, then no transfers work properly
81 * for EP0, and the system will fail basic enumeration. As no cause for this
82 * has currently been found, we cannot support any large IN transfers for
83 * EP0.
84 */
85#define EP0_MPS_LIMIT 64
86
941fcce4 87struct dwc2_hsotg;
f7c0b143
DN		 88struct s3c_hsotg_req;
89
90/**
91 * struct s3c_hsotg_ep - driver endpoint definition.
92 * @ep: The gadget layer representation of the endpoint.
93 * @name: The driver generated name for the endpoint.
94 * @queue: Queue of requests for this endpoint.
95 * @parent: Reference back to the parent device structure.
96 * @req: The current request that the endpoint is processing. This is
97 * used to indicate an request has been loaded onto the endpoint
98 * and has yet to be completed (maybe due to data move, or simply
99 * awaiting an ack from the core all the data has been completed).
100 * @debugfs: File entry for debugfs file for this endpoint.
101 * @lock: State lock to protect contents of endpoint.
102 * @dir_in: Set to true if this endpoint is of the IN direction, which
103 * means that it is sending data to the Host.
104 * @index: The index for the endpoint registers.
105 * @mc: Multi Count - number of transactions per microframe
106 * @interval - Interval for periodic endpoints
107 * @name: The name array passed to the USB core.
108 * @halted: Set if the endpoint has been halted.
109 * @periodic: Set if this is a periodic ep, such as Interrupt
110 * @isochronous: Set if this is a isochronous ep
111 * @sent_zlp: Set if we've sent a zero-length packet.
112 * @total_data: The total number of data bytes done.
113 * @fifo_size: The size of the FIFO (for periodic IN endpoints)
114 * @fifo_load: The amount of data loaded into the FIFO (periodic IN)
115 * @last_load: The offset of data for the last start of request.
116 * @size_loaded: The last loaded size for DxEPTSIZE for periodic IN
117 *
118 * This is the driver's state for each registered enpoint, allowing it
119 * to keep track of transactions that need doing. Each endpoint has a
120 * lock to protect the state, to try and avoid using an overall lock
121 * for the host controller as much as possible.
122 *
123 * For periodic IN endpoints, we have fifo_size and fifo_load to try
124 * and keep track of the amount of data in the periodic FIFO for each
125 * of these as we don't have a status register that tells us how much
126 * is in each of them. (note, this may actually be useless information
127 * as in shared-fifo mode periodic in acts like a single-frame packet
128 * buffer than a fifo)
129 */
130struct s3c_hsotg_ep {
131 struct usb_ep ep;
132 struct list_head queue;
941fcce4 133 struct dwc2_hsotg *parent;
f7c0b143
DN		 134 struct s3c_hsotg_req *req;
135 struct dentry *debugfs;
136
137 unsigned long total_data;
138 unsigned int size_loaded;
139 unsigned int last_load;
140 unsigned int fifo_load;
141 unsigned short fifo_size;
b203d0a2 142 unsigned short fifo_index;
f7c0b143
DN		 143
144 unsigned char dir_in;
145 unsigned char index;
146 unsigned char mc;
147 unsigned char interval;
148
149 unsigned int halted:1;
150 unsigned int periodic:1;
151 unsigned int isochronous:1;
152 unsigned int sent_zlp:1;
153
154 char name[10];
155};
156
f7c0b143
DN		 157/**
158 * struct s3c_hsotg_req - data transfer request
159 * @req: The USB gadget request
160 * @queue: The list of requests for the endpoint this is queued for.
161 * @in_progress: Has already had size/packets written to core
162 * @mapped: DMA buffer for this request has been mapped via dma_map_single().
163 */
164struct s3c_hsotg_req {
165 struct usb_request req;
166 struct list_head queue;
167 unsigned char in_progress;
168 unsigned char mapped;
169};
170
941fcce4 171#if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
f7c0b143
DN		 172#define call_gadget(_hs, _entry) \
173do { \
174 if ((_hs)->gadget.speed != USB_SPEED_UNKNOWN && \
175 (_hs)->driver && (_hs)->driver->_entry) { \
176 spin_unlock(&_hs->lock); \
177 (_hs)->driver->_entry(&(_hs)->gadget); \
178 spin_lock(&_hs->lock); \
179 } \
180} while (0)
941fcce4
DN		 181#else
182#define call_gadget(_hs, _entry) do {} while (0)
183#endif
f7c0b143 184
56f5b1cf
PZ		 185struct dwc2_hsotg;
186struct dwc2_host_chan;
187
188/* Device States */
189enum dwc2_lx_state {
190 DWC2_L0, /* On state */
191 DWC2_L1, /* LPM sleep state */
192 DWC2_L2, /* USB suspend state */
193 DWC2_L3, /* Off state */
194};
195
196/**
197 * struct dwc2_core_params - Parameters for configuring the core
198 *
91121c10
MK		 199 * @otg_cap: Specifies the OTG capabilities.
200 * 0 - HNP and SRP capable
56f5b1cf 201 * 1 - SRP Only capable
91121c10
MK		 202 * 2 - No HNP/SRP capable (always available)
203 * Defaults to best available option (0, 1, then 2)
725acc86 204 * @otg_ver: OTG version supported
91121c10 205 * 0 - 1.3 (default)
725acc86 206 * 1 - 2.0
56f5b1cf
PZ		 207 * @dma_enable: Specifies whether to use slave or DMA mode for accessing
208 * the data FIFOs. The driver will automatically detect the
209 * value for this parameter if none is specified.
91121c10 210 * 0 - Slave (always available)
56f5b1cf
PZ		 211 * 1 - DMA (default, if available)
212 * @dma_desc_enable: When DMA mode is enabled, specifies whether to use
213 * address DMA mode or descriptor DMA mode for accessing
214 * the data FIFOs. The driver will automatically detect the
215 * value for this if none is specified.
216 * 0 - Address DMA
217 * 1 - Descriptor DMA (default, if available)
218 * @speed: Specifies the maximum speed of operation in host and
219 * device mode. The actual speed depends on the speed of
220 * the attached device and the value of phy_type.
91121c10
MK		 221 * 0 - High Speed
222 * (default when phy_type is UTMI+ or ULPI)
56f5b1cf 223 * 1 - Full Speed
91121c10 224 * (default when phy_type is Full Speed)
56f5b1cf 225 * @enable_dynamic_fifo: 0 - Use coreConsultant-specified FIFO size parameters
91121c10 226 * 1 - Allow dynamic FIFO sizing (default, if available)
725acc86
PZ		 227 * @en_multiple_tx_fifo: Specifies whether dedicated per-endpoint transmit FIFOs
228 * are enabled
56f5b1cf
PZ		 229 * @host_rx_fifo_size: Number of 4-byte words in the Rx FIFO in host mode when
230 * dynamic FIFO sizing is enabled
91121c10
MK		 231 * 16 to 32768
232 * Actual maximum value is autodetected and also
233 * the default.
56f5b1cf
PZ		 234 * @host_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO
235 * in host mode when dynamic FIFO sizing is enabled
91121c10
MK		 236 * 16 to 32768
237 * Actual maximum value is autodetected and also
238 * the default.
56f5b1cf
PZ		 239 * @host_perio_tx_fifo_size: Number of 4-byte words in the periodic Tx FIFO in
240 * host mode when dynamic FIFO sizing is enabled
91121c10
MK		 241 * 16 to 32768
242 * Actual maximum value is autodetected and also
243 * the default.
56f5b1cf 244 * @max_transfer_size: The maximum transfer size supported, in bytes
91121c10
MK		 245 * 2047 to 65,535
246 * Actual maximum value is autodetected and also
247 * the default.
56f5b1cf 248 * @max_packet_count: The maximum number of packets in a transfer
91121c10
MK		 249 * 15 to 511
250 * Actual maximum value is autodetected and also
251 * the default.
56f5b1cf 252 * @host_channels: The number of host channel registers to use
91121c10
MK		 253 * 1 to 16
254 * Actual maximum value is autodetected and also
255 * the default.
56f5b1cf
PZ		 256 * @phy_type: Specifies the type of PHY interface to use. By default,
257 * the driver will automatically detect the phy_type.
91121c10
MK		 258 * 0 - Full Speed Phy
259 * 1 - UTMI+ Phy
260 * 2 - ULPI Phy
261 * Defaults to best available option (2, 1, then 0)
56f5b1cf
PZ		 262 * @phy_utmi_width: Specifies the UTMI+ Data Width (in bits). This parameter
263 * is applicable for a phy_type of UTMI+ or ULPI. (For a
264 * ULPI phy_type, this parameter indicates the data width
265 * between the MAC and the ULPI Wrapper.) Also, this
266 * parameter is applicable only if the OTG_HSPHY_WIDTH cC
267 * parameter was set to "8 and 16 bits", meaning that the
268 * core has been configured to work at either data path
269 * width.
91121c10 270 * 8 or 16 (default 16 if available)
56f5b1cf
PZ		 271 * @phy_ulpi_ddr: Specifies whether the ULPI operates at double or single
272 * data rate. This parameter is only applicable if phy_type
273 * is ULPI.
274 * 0 - single data rate ULPI interface with 8 bit wide
275 * data bus (default)
276 * 1 - double data rate ULPI interface with 4 bit wide
277 * data bus
278 * @phy_ulpi_ext_vbus: For a ULPI phy, specifies whether to use the internal or
279 * external supply to drive the VBus
91121c10
MK		 280 * 0 - Internal supply (default)
281 * 1 - External supply
56f5b1cf
PZ		 282 * @i2c_enable: Specifies whether to use the I2Cinterface for a full
283 * speed PHY. This parameter is only applicable if phy_type
284 * is FS.
285 * 0 - No (default)
286 * 1 - Yes
91121c10
MK		 287 * @ulpi_fs_ls: Make ULPI phy operate in FS/LS mode only
288 * 0 - No (default)
289 * 1 - Yes
725acc86
PZ		 290 * @host_support_fs_ls_low_power: Specifies whether low power mode is supported
291 * when attached to a Full Speed or Low Speed device in
292 * host mode.
293 * 0 - Don't support low power mode (default)
294 * 1 - Support low power mode
295 * @host_ls_low_power_phy_clk: Specifies the PHY clock rate in low power mode
91121c10
MK		 296 * when connected to a Low Speed device in host
297 * mode. This parameter is applicable only if
298 * host_support_fs_ls_low_power is enabled.
725acc86 299 * 0 - 48 MHz
91121c10 300 * (default when phy_type is UTMI+ or ULPI)
725acc86 301 * 1 - 6 MHz
91121c10
MK		 302 * (default when phy_type is Full Speed)
303 * @ts_dline: Enable Term Select Dline pulsing
304 * 0 - No (default)
305 * 1 - Yes
306 * @reload_ctl: Allow dynamic reloading of HFIR register during runtime
307 * 0 - No (default for core < 2.92a)
308 * 1 - Yes (default for core >= 2.92a)
4d3190e1
PZ		 309 * @ahbcfg: This field allows the default value of the GAHBCFG
310 * register to be overridden
91121c10
MK		 311 * -1 - GAHBCFG value will be set to 0x06
312 * (INCR4, default)
4d3190e1
PZ		 313 * all others - GAHBCFG value will be overridden with
314 * this value
91121c10
MK		 315 * Not all bits can be controlled like this, the
316 * bits defined by GAHBCFG_CTRL_MASK are controlled
317 * by the driver and are ignored in this
318 * configuration value.
20f2eb9c 319 * @uframe_sched: True to enable the microframe scheduler
56f5b1cf
PZ		 320 *
321 * The following parameters may be specified when starting the module. These
91121c10
MK		 322 * parameters define how the DWC_otg controller should be configured. A
323 * value of -1 (or any other out of range value) for any parameter means
324 * to read the value from hardware (if possible) or use the builtin
325 * default described above.
56f5b1cf
PZ		 326 */
327struct dwc2_core_params {
8284f93b
MK		 328 /*
329 * Don't add any non-int members here, this will break
330 * dwc2_set_all_params!
331 */
56f5b1cf
PZ		 332 int otg_cap;
333 int otg_ver;
334 int dma_enable;
335 int dma_desc_enable;
336 int speed;
337 int enable_dynamic_fifo;
338 int en_multiple_tx_fifo;
339 int host_rx_fifo_size;
340 int host_nperio_tx_fifo_size;
341 int host_perio_tx_fifo_size;
342 int max_transfer_size;
343 int max_packet_count;
344 int host_channels;
345 int phy_type;
346 int phy_utmi_width;
347 int phy_ulpi_ddr;
348 int phy_ulpi_ext_vbus;
349 int i2c_enable;
350 int ulpi_fs_ls;
351 int host_support_fs_ls_low_power;
352 int host_ls_low_power_phy_clk;
353 int ts_dline;
354 int reload_ctl;
4d3190e1 355 int ahbcfg;
20f2eb9c 356 int uframe_sched;
56f5b1cf
PZ		 357};
358
9badec2f
MK		 359/**
360 * struct dwc2_hw_params - Autodetected parameters.
361 *
362 * These parameters are the various parameters read from hardware
363 * registers during initialization. They typically contain the best
364 * supported or maximum value that can be configured in the
365 * corresponding dwc2_core_params value.
366 *
367 * The values that are not in dwc2_core_params are documented below.
368 *
369 * @op_mode Mode of Operation
370 * 0 - HNP- and SRP-Capable OTG (Host & Device)
371 * 1 - SRP-Capable OTG (Host & Device)
372 * 2 - Non-HNP and Non-SRP Capable OTG (Host & Device)
373 * 3 - SRP-Capable Device
374 * 4 - Non-OTG Device
375 * 5 - SRP-Capable Host
376 * 6 - Non-OTG Host
377 * @arch Architecture
378 * 0 - Slave only
379 * 1 - External DMA
380 * 2 - Internal DMA
381 * @power_optimized Are power optimizations enabled?
382 * @num_dev_ep Number of device endpoints available
383 * @num_dev_perio_in_ep Number of device periodic IN endpoints
384 * avaialable
385 * @dev_token_q_depth Device Mode IN Token Sequence Learning Queue
386 * Depth
387 * 0 to 30
388 * @host_perio_tx_q_depth
389 * Host Mode Periodic Request Queue Depth
390 * 2, 4 or 8
391 * @nperio_tx_q_depth
392 * Non-Periodic Request Queue Depth
393 * 2, 4 or 8
394 * @hs_phy_type High-speed PHY interface type
395 * 0 - High-speed interface not supported
396 * 1 - UTMI+
397 * 2 - ULPI
398 * 3 - UTMI+ and ULPI
399 * @fs_phy_type Full-speed PHY interface type
400 * 0 - Full speed interface not supported
401 * 1 - Dedicated full speed interface
402 * 2 - FS pins shared with UTMI+ pins
403 * 3 - FS pins shared with ULPI pins
404 * @total_fifo_size: Total internal RAM for FIFOs (bytes)
de4a1931
MK		 405 * @utmi_phy_data_width UTMI+ PHY data width
406 * 0 - 8 bits
407 * 1 - 16 bits
408 * 2 - 8 or 16 bits
9badec2f
MK		 409 * @snpsid: Value from SNPSID register
410 */
411struct dwc2_hw_params {
412 unsigned op_mode:3;
413 unsigned arch:2;
414 unsigned dma_desc_enable:1;
415 unsigned enable_dynamic_fifo:1;
416 unsigned en_multiple_tx_fifo:1;
417 unsigned host_rx_fifo_size:16;
418 unsigned host_nperio_tx_fifo_size:16;
419 unsigned host_perio_tx_fifo_size:16;
420 unsigned nperio_tx_q_depth:3;
421 unsigned host_perio_tx_q_depth:3;
422 unsigned dev_token_q_depth:5;
423 unsigned max_transfer_size:26;
424 unsigned max_packet_count:11;
2d115547 425 unsigned host_channels:5;
9badec2f
MK		 426 unsigned hs_phy_type:2;
427 unsigned fs_phy_type:2;
428 unsigned i2c_enable:1;
429 unsigned num_dev_ep:4;
430 unsigned num_dev_perio_in_ep:4;
431 unsigned total_fifo_size:16;
432 unsigned power_optimized:1;
de4a1931 433 unsigned utmi_phy_data_width:2;
9badec2f
MK		 434 u32 snpsid;
435};
436
56f5b1cf
PZ		 437/**
438 * struct dwc2_hsotg - Holds the state of the driver, including the non-periodic
439 * and periodic schedules
440 *
941fcce4
DN		 441 * These are common for both host and peripheral modes:
442 *
56f5b1cf
PZ		 443 * @dev: The struct device pointer
444 * @regs: Pointer to controller regs
9badec2f
MK		 445 * @hw_params: Parameters that were autodetected from the
446 * hardware registers
941fcce4 447 * @core_params: Parameters that define how the core should be configured
56f5b1cf
PZ		 448 * @op_state: The operational State, during transitions (a_host=>
449 * a_peripheral and b_device=>b_host) this may not match
450 * the core, but allows the software to determine
451 * transitions
c0155b9d
KY		 452 * @dr_mode: Requested mode of operation, one of following:
453 * - USB_DR_MODE_PERIPHERAL
454 * - USB_DR_MODE_HOST
455 * - USB_DR_MODE_OTG
941fcce4
DN		 456 * @lock: Spinlock that protects all the driver data structures
457 * @priv: Stores a pointer to the struct usb_hcd
56f5b1cf
PZ		 458 * @queuing_high_bandwidth: True if multiple packets of a high-bandwidth
459 * transfer are in process of being queued
460 * @srp_success: Stores status of SRP request in the case of a FS PHY
461 * with an I2C interface
462 * @wq_otg: Workqueue object used for handling of some interrupts
463 * @wf_otg: Work object for handling Connector ID Status Change
464 * interrupt
465 * @wkp_timer: Timer object for handling Wakeup Detected interrupt
466 * @lx_state: Lx state of connected device
941fcce4
DN		 467 *
468 * These are for host mode:
469 *
56f5b1cf
PZ		 470 * @flags: Flags for handling root port state changes
471 * @non_periodic_sched_inactive: Inactive QHs in the non-periodic schedule.
472 * Transfers associated with these QHs are not currently
473 * assigned to a host channel.
474 * @non_periodic_sched_active: Active QHs in the non-periodic schedule.
475 * Transfers associated with these QHs are currently
476 * assigned to a host channel.
477 * @non_periodic_qh_ptr: Pointer to next QH to process in the active
478 * non-periodic schedule
479 * @periodic_sched_inactive: Inactive QHs in the periodic schedule. This is a
480 * list of QHs for periodic transfers that are _not_
481 * scheduled for the next frame. Each QH in the list has an
482 * interval counter that determines when it needs to be
483 * scheduled for execution. This scheduling mechanism
484 * allows only a simple calculation for periodic bandwidth
485 * used (i.e. must assume that all periodic transfers may
486 * need to execute in the same frame). However, it greatly
487 * simplifies scheduling and should be sufficient for the
488 * vast majority of OTG hosts, which need to connect to a
489 * small number of peripherals at one time. Items move from
490 * this list to periodic_sched_ready when the QH interval
491 * counter is 0 at SOF.
492 * @periodic_sched_ready: List of periodic QHs that are ready for execution in
493 * the next frame, but have not yet been assigned to host
494 * channels. Items move from this list to
495 * periodic_sched_assigned as host channels become
496 * available during the current frame.
497 * @periodic_sched_assigned: List of periodic QHs to be executed in the next
498 * frame that are assigned to host channels. Items move
499 * from this list to periodic_sched_queued as the
500 * transactions for the QH are queued to the DWC_otg
501 * controller.
502 * @periodic_sched_queued: List of periodic QHs that have been queued for
503 * execution. Items move from this list to either
504 * periodic_sched_inactive or periodic_sched_ready when the
505 * channel associated with the transfer is released. If the
506 * interval for the QH is 1, the item moves to
507 * periodic_sched_ready because it must be rescheduled for
508 * the next frame. Otherwise, the item moves to
509 * periodic_sched_inactive.
510 * @periodic_usecs: Total bandwidth claimed so far for periodic transfers.
511 * This value is in microseconds per (micro)frame. The
512 * assumption is that all periodic transfers may occur in
513 * the same (micro)frame.
20f2eb9c 514 * @frame_usecs: Internal variable used by the microframe scheduler
56f5b1cf
PZ		 515 * @frame_number: Frame number read from the core at SOF. The value ranges
516 * from 0 to HFNUM_MAX_FRNUM.
517 * @periodic_qh_count: Count of periodic QHs, if using several eps. Used for
518 * SOF enable/disable.
519 * @free_hc_list: Free host channels in the controller. This is a list of
520 * struct dwc2_host_chan items.
521 * @periodic_channels: Number of host channels assigned to periodic transfers.
522 * Currently assuming that there is a dedicated host
523 * channel for each periodic transaction and at least one
524 * host channel is available for non-periodic transactions.
525 * @non_periodic_channels: Number of host channels assigned to non-periodic
526 * transfers
20f2eb9c
DC		 527 * @available_host_channels Number of host channels available for the microframe
528 * scheduler to use
56f5b1cf
PZ		 529 * @hc_ptr_array: Array of pointers to the host channel descriptors.
530 * Allows accessing a host channel descriptor given the
531 * host channel number. This is useful in interrupt
532 * handlers.
533 * @status_buf: Buffer used for data received during the status phase of
534 * a control transfer.
535 * @status_buf_dma: DMA address for status_buf
536 * @start_work: Delayed work for handling host A-cable connection
537 * @reset_work: Delayed work for handling a port reset
56f5b1cf
PZ		 538 * @otg_port: OTG port number
539 * @frame_list: Frame list
540 * @frame_list_dma: Frame list DMA address
941fcce4
DN		 541 *
542 * These are for peripheral mode:
543 *
544 * @driver: USB gadget driver
545 * @phy: The otg phy transceiver structure for phy control.
546 * @uphy: The otg phy transceiver structure for old USB phy control.
547 * @plat: The platform specific configuration data. This can be removed once
548 * all SoCs support usb transceiver.
549 * @supplies: Definition of USB power supplies
550 * @phyif: PHY interface width
551 * @dedicated_fifos: Set if the hardware has dedicated IN-EP fifos.
552 * @num_of_eps: Number of available EPs (excluding EP0)
553 * @debug_root: Root directrory for debugfs.
554 * @debug_file: Main status file for debugfs.
555 * @debug_fifo: FIFO status file for debugfs.
556 * @ep0_reply: Request used for ep0 reply.
557 * @ep0_buff: Buffer for EP0 reply data, if needed.
558 * @ctrl_buff: Buffer for EP0 control requests.
559 * @ctrl_req: Request for EP0 control packets.
560 * @setup: NAK management for EP0 SETUP
561 * @last_rst: Time of last reset
562 * @eps: The endpoints being supplied to the gadget framework
56f5b1cf
PZ		 563 */
564struct dwc2_hsotg {
565 struct device *dev;
566 void __iomem *regs;
9badec2f
MK		 567 /** Params detected from hardware */
568 struct dwc2_hw_params hw_params;
569 /** Params to actually use */
56f5b1cf 570 struct dwc2_core_params *core_params;
56f5b1cf 571 enum usb_otg_state op_state;
c0155b9d 572 enum usb_dr_mode dr_mode;
56f5b1cf 573
941fcce4
DN		 574 struct phy *phy;
575 struct usb_phy *uphy;
576 struct regulator_bulk_data supplies[ARRAY_SIZE(s3c_hsotg_supply_names)];
577
578 spinlock_t lock;
579 void *priv;
580 int irq;
581 struct clk *clk;
582
56f5b1cf
PZ		 583 unsigned int queuing_high_bandwidth:1;
584 unsigned int srp_success:1;
585
586 struct workqueue_struct *wq_otg;
587 struct work_struct wf_otg;
588 struct timer_list wkp_timer;
589 enum dwc2_lx_state lx_state;
590
941fcce4
DN		 591 struct dentry *debug_root;
592 struct dentry *debug_file;
593 struct dentry *debug_fifo;
594
595 /* DWC OTG HW Release versions */
596#define DWC2_CORE_REV_2_71a 0x4f54271a
597#define DWC2_CORE_REV_2_90a 0x4f54290a
598#define DWC2_CORE_REV_2_92a 0x4f54292a
599#define DWC2_CORE_REV_2_94a 0x4f54294a
600#define DWC2_CORE_REV_3_00a 0x4f54300a
601
602#if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
56f5b1cf
PZ		 603 union dwc2_hcd_internal_flags {
604 u32 d32;
605 struct {
606 unsigned port_connect_status_change:1;
607 unsigned port_connect_status:1;
608 unsigned port_reset_change:1;
609 unsigned port_enable_change:1;
610 unsigned port_suspend_change:1;
611 unsigned port_over_current_change:1;
612 unsigned port_l1_change:1;
fd4850cf 613 unsigned reserved:25;
56f5b1cf
PZ		 614 } b;
615 } flags;
616
617 struct list_head non_periodic_sched_inactive;
618 struct list_head non_periodic_sched_active;
619 struct list_head *non_periodic_qh_ptr;
620 struct list_head periodic_sched_inactive;
621 struct list_head periodic_sched_ready;
622 struct list_head periodic_sched_assigned;
623 struct list_head periodic_sched_queued;
624 u16 periodic_usecs;
20f2eb9c 625 u16 frame_usecs[8];
56f5b1cf
PZ		 626 u16 frame_number;
627 u16 periodic_qh_count;
628
629#ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
630#define FRAME_NUM_ARRAY_SIZE 1000
631 u16 last_frame_num;
632 u16 *frame_num_array;
633 u16 *last_frame_num_array;
634 int frame_num_idx;
635 int dumped_frame_num_array;
636#endif
637
638 struct list_head free_hc_list;
639 int periodic_channels;
640 int non_periodic_channels;
20f2eb9c 641 int available_host_channels;
56f5b1cf
PZ		 642 struct dwc2_host_chan *hc_ptr_array[MAX_EPS_CHANNELS];
643 u8 *status_buf;
644 dma_addr_t status_buf_dma;
645#define DWC2_HCD_STATUS_BUF_SIZE 64
646
647 struct delayed_work start_work;
648 struct delayed_work reset_work;
56f5b1cf
PZ		 649 u8 otg_port;
650 u32 *frame_list;
651 dma_addr_t frame_list_dma;
652
56f5b1cf
PZ		 653#ifdef DEBUG
654 u32 frrem_samples;
655 u64 frrem_accum;
656
657 u32 hfnum_7_samples_a;
658 u64 hfnum_7_frrem_accum_a;
659 u32 hfnum_0_samples_a;
660 u64 hfnum_0_frrem_accum_a;
661 u32 hfnum_other_samples_a;
662 u64 hfnum_other_frrem_accum_a;
663
664 u32 hfnum_7_samples_b;
665 u64 hfnum_7_frrem_accum_b;
666 u32 hfnum_0_samples_b;
667 u64 hfnum_0_frrem_accum_b;
668 u32 hfnum_other_samples_b;
669 u64 hfnum_other_frrem_accum_b;
670#endif
941fcce4
DN		 671#endif /* CONFIG_USB_DWC2_HOST || CONFIG_USB_DWC2_DUAL_ROLE */
672
673#if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
674 /* Gadget structures */
675 struct usb_gadget_driver *driver;
676 struct s3c_hsotg_plat *plat;
677
678 u32 phyif;
679 int fifo_mem;
680 unsigned int dedicated_fifos:1;
681 unsigned char num_of_eps;
682 u32 fifo_map;
683
684 struct usb_request *ep0_reply;
685 struct usb_request *ctrl_req;
686 u8 ep0_buff[8];
687 u8 ctrl_buff[8];
688
689 struct usb_gadget gadget;
690 unsigned int setup;
691 unsigned long last_rst;
692 struct s3c_hsotg_ep *eps;
693#endif /* CONFIG_USB_DWC2_PERIPHERAL || CONFIG_USB_DWC2_DUAL_ROLE */
56f5b1cf
PZ		 694};
695
696/* Reasons for halting a host channel */
697enum dwc2_halt_status {
698 DWC2_HC_XFER_NO_HALT_STATUS,
699 DWC2_HC_XFER_COMPLETE,
700 DWC2_HC_XFER_URB_COMPLETE,
701 DWC2_HC_XFER_ACK,
702 DWC2_HC_XFER_NAK,
703 DWC2_HC_XFER_NYET,
704 DWC2_HC_XFER_STALL,
705 DWC2_HC_XFER_XACT_ERR,
706 DWC2_HC_XFER_FRAME_OVERRUN,
707 DWC2_HC_XFER_BABBLE_ERR,
708 DWC2_HC_XFER_DATA_TOGGLE_ERR,
709 DWC2_HC_XFER_AHB_ERR,
710 DWC2_HC_XFER_PERIODIC_INCOMPLETE,
711 DWC2_HC_XFER_URB_DEQUEUE,
712};
713
714/*
715 * The following functions support initialization of the core driver component
716 * and the DWC_otg controller
717 */
718extern void dwc2_core_host_init(struct dwc2_hsotg *hsotg);
719
720/*
721 * Host core Functions.
722 * The following functions support managing the DWC_otg controller in host
723 * mode.
724 */
725extern void dwc2_hc_init(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan);
726extern void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan,
727 enum dwc2_halt_status halt_status);
728extern void dwc2_hc_cleanup(struct dwc2_hsotg *hsotg,
729 struct dwc2_host_chan *chan);
730extern void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg,
731 struct dwc2_host_chan *chan);
732extern void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg,
733 struct dwc2_host_chan *chan);
734extern int dwc2_hc_continue_transfer(struct dwc2_hsotg *hsotg,
735 struct dwc2_host_chan *chan);
736extern void dwc2_hc_do_ping(struct dwc2_hsotg *hsotg,
737 struct dwc2_host_chan *chan);
738extern void dwc2_enable_host_interrupts(struct dwc2_hsotg *hsotg);
739extern void dwc2_disable_host_interrupts(struct dwc2_hsotg *hsotg);
740
741extern u32 dwc2_calc_frame_interval(struct dwc2_hsotg *hsotg);
057715f2 742extern bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg);
56f5b1cf
PZ		 743
744/*
745 * Common core Functions.
746 * The following functions support managing the DWC_otg controller in either
747 * device or host mode.
748 */
749extern void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes);
750extern void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num);
751extern void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg);
752
6706c721 753extern int dwc2_core_init(struct dwc2_hsotg *hsotg, bool select_phy, int irq);
56f5b1cf
PZ		 754extern void dwc2_enable_global_interrupts(struct dwc2_hsotg *hcd);
755extern void dwc2_disable_global_interrupts(struct dwc2_hsotg *hcd);
756
757/* This function should be called on every hardware interrupt. */
758extern irqreturn_t dwc2_handle_common_intr(int irq, void *dev);
759
760/* OTG Core Parameters */
761
762/*
763 * Specifies the OTG capabilities. The driver will automatically
764 * detect the value for this parameter if none is specified.
765 * 0 - HNP and SRP capable (default)
766 * 1 - SRP Only capable
767 * 2 - No HNP/SRP capable
768 */
7218dae7 769extern void dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg, int val);
56f5b1cf
PZ		 770#define DWC2_CAP_PARAM_HNP_SRP_CAPABLE 0
771#define DWC2_CAP_PARAM_SRP_ONLY_CAPABLE 1
772#define DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE 2
773
774/*
775 * Specifies whether to use slave or DMA mode for accessing the data
776 * FIFOs. The driver will automatically detect the value for this
777 * parameter if none is specified.
778 * 0 - Slave
779 * 1 - DMA (default, if available)
780 */
7218dae7 781extern void dwc2_set_param_dma_enable(struct dwc2_hsotg *hsotg, int val);
56f5b1cf
PZ		 782
783/*
784 * When DMA mode is enabled specifies whether to use
785 * address DMA or DMA Descritor mode for accessing the data
786 * FIFOs in device mode. The driver will automatically detect
787 * the value for this parameter if none is specified.
788 * 0 - address DMA
789 * 1 - DMA Descriptor(default, if available)
790 */
7218dae7 791extern void dwc2_set_param_dma_desc_enable(struct dwc2_hsotg *hsotg, int val);
56f5b1cf
PZ		 792
793/*
794 * Specifies the maximum speed of operation in host and device mode.
795 * The actual speed depends on the speed of the attached device and
796 * the value of phy_type. The actual speed depends on the speed of the
797 * attached device.
798 * 0 - High Speed (default)
799 * 1 - Full Speed
800 */
7218dae7 801extern void dwc2_set_param_speed(struct dwc2_hsotg *hsotg, int val);
56f5b1cf
PZ		 802#define DWC2_SPEED_PARAM_HIGH 0
803#define DWC2_SPEED_PARAM_FULL 1
804
805/*
806 * Specifies whether low power mode is supported when attached
807 * to a Full Speed or Low Speed device in host mode.
808 *
809 * 0 - Don't support low power mode (default)
810 * 1 - Support low power mode
811 */
7218dae7
PZ		 812extern void dwc2_set_param_host_support_fs_ls_low_power(
813 struct dwc2_hsotg *hsotg, int val);
56f5b1cf
PZ		 814
815/*
816 * Specifies the PHY clock rate in low power mode when connected to a
817 * Low Speed device in host mode. This parameter is applicable only if
818 * HOST_SUPPORT_FS_LS_LOW_POWER is enabled. If PHY_TYPE is set to FS
819 * then defaults to 6 MHZ otherwise 48 MHZ.
820 *
821 * 0 - 48 MHz
822 * 1 - 6 MHz
823 */
7218dae7
PZ		 824extern void dwc2_set_param_host_ls_low_power_phy_clk(struct dwc2_hsotg *hsotg,
825 int val);
56f5b1cf
PZ		 826#define DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ 0
827#define DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ 1
828
829/*
830 * 0 - Use cC FIFO size parameters
831 * 1 - Allow dynamic FIFO sizing (default)
832 */
7218dae7
PZ		 833extern void dwc2_set_param_enable_dynamic_fifo(struct dwc2_hsotg *hsotg,
834 int val);
56f5b1cf
PZ		 835
836/*
837 * Number of 4-byte words in the Rx FIFO in host mode when dynamic
838 * FIFO sizing is enabled.
839 * 16 to 32768 (default 1024)
840 */
7218dae7 841extern void dwc2_set_param_host_rx_fifo_size(struct dwc2_hsotg *hsotg, int val);
56f5b1cf
PZ		 842
843/*
844 * Number of 4-byte words in the non-periodic Tx FIFO in host mode
845 * when Dynamic FIFO sizing is enabled in the core.
846 * 16 to 32768 (default 256)
847 */
7218dae7
PZ		 848extern void dwc2_set_param_host_nperio_tx_fifo_size(struct dwc2_hsotg *hsotg,
849 int val);
56f5b1cf
PZ		 850
851/*
852 * Number of 4-byte words in the host periodic Tx FIFO when dynamic
853 * FIFO sizing is enabled.
854 * 16 to 32768 (default 256)
855 */
7218dae7
PZ		 856extern void dwc2_set_param_host_perio_tx_fifo_size(struct dwc2_hsotg *hsotg,
857 int val);
56f5b1cf
PZ		 858
859/*
860 * The maximum transfer size supported in bytes.
861 * 2047 to 65,535 (default 65,535)
862 */
7218dae7 863extern void dwc2_set_param_max_transfer_size(struct dwc2_hsotg *hsotg, int val);
56f5b1cf
PZ		 864
865/*
866 * The maximum number of packets in a transfer.
867 * 15 to 511 (default 511)
868 */
7218dae7 869extern void dwc2_set_param_max_packet_count(struct dwc2_hsotg *hsotg, int val);
56f5b1cf
PZ		 870
871/*
872 * The number of host channel registers to use.
873 * 1 to 16 (default 11)
874 * Note: The FPGA configuration supports a maximum of 11 host channels.
875 */
7218dae7 876extern void dwc2_set_param_host_channels(struct dwc2_hsotg *hsotg, int val);
56f5b1cf
PZ		 877
878/*
879 * Specifies the type of PHY interface to use. By default, the driver
880 * will automatically detect the phy_type.
881 *
882 * 0 - Full Speed PHY
883 * 1 - UTMI+ (default)
884 * 2 - ULPI
885 */
7218dae7 886extern void dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg, int val);
56f5b1cf
PZ		 887#define DWC2_PHY_TYPE_PARAM_FS 0
888#define DWC2_PHY_TYPE_PARAM_UTMI 1
889#define DWC2_PHY_TYPE_PARAM_ULPI 2
890
891/*
892 * Specifies the UTMI+ Data Width. This parameter is
893 * applicable for a PHY_TYPE of UTMI+ or ULPI. (For a ULPI
894 * PHY_TYPE, this parameter indicates the data width between
895 * the MAC and the ULPI Wrapper.) Also, this parameter is
896 * applicable only if the OTG_HSPHY_WIDTH cC parameter was set
897 * to "8 and 16 bits", meaning that the core has been
898 * configured to work at either data path width.
899 *
900 * 8 or 16 bits (default 16)
901 */
7218dae7 902extern void dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg, int val);
56f5b1cf
PZ		 903
904/*
905 * Specifies whether the ULPI operates at double or single
906 * data rate. This parameter is only applicable if PHY_TYPE is
907 * ULPI.
908 *
909 * 0 - single data rate ULPI interface with 8 bit wide data
910 * bus (default)
911 * 1 - double data rate ULPI interface with 4 bit wide data
912 * bus
913 */
7218dae7 914extern void dwc2_set_param_phy_ulpi_ddr(struct dwc2_hsotg *hsotg, int val);
56f5b1cf
PZ		 915
916/*
917 * Specifies whether to use the internal or external supply to
918 * drive the vbus with a ULPI phy.
919 */
7218dae7 920extern void dwc2_set_param_phy_ulpi_ext_vbus(struct dwc2_hsotg *hsotg, int val);
56f5b1cf
PZ		 921#define DWC2_PHY_ULPI_INTERNAL_VBUS 0
922#define DWC2_PHY_ULPI_EXTERNAL_VBUS 1
923
924/*
925 * Specifies whether to use the I2Cinterface for full speed PHY. This
926 * parameter is only applicable if PHY_TYPE is FS.
927 * 0 - No (default)
928 * 1 - Yes
929 */
7218dae7 930extern void dwc2_set_param_i2c_enable(struct dwc2_hsotg *hsotg, int val);
56f5b1cf 931
7218dae7 932extern void dwc2_set_param_ulpi_fs_ls(struct dwc2_hsotg *hsotg, int val);
56f5b1cf 933
7218dae7 934extern void dwc2_set_param_ts_dline(struct dwc2_hsotg *hsotg, int val);
56f5b1cf
PZ		 935
936/*
937 * Specifies whether dedicated transmit FIFOs are
938 * enabled for non periodic IN endpoints in device mode
939 * 0 - No
940 * 1 - Yes
941 */
7218dae7
PZ		 942extern void dwc2_set_param_en_multiple_tx_fifo(struct dwc2_hsotg *hsotg,
943 int val);
56f5b1cf 944
7218dae7 945extern void dwc2_set_param_reload_ctl(struct dwc2_hsotg *hsotg, int val);
56f5b1cf 946
7218dae7 947extern void dwc2_set_param_ahbcfg(struct dwc2_hsotg *hsotg, int val);
56f5b1cf 948
7218dae7 949extern void dwc2_set_param_otg_ver(struct dwc2_hsotg *hsotg, int val);
56f5b1cf
PZ		 950
951/*
952 * Dump core registers and SPRAM
953 */
954extern void dwc2_dump_dev_registers(struct dwc2_hsotg *hsotg);
955extern void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg);
956extern void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg);
957
958/*
959 * Return OTG version - either 1.3 or 2.0
960 */
961extern u16 dwc2_get_otg_version(struct dwc2_hsotg *hsotg);
962
963#endif /* __DWC2_CORE_H__ */
Linux 6.x block layer and io_uring tree(s)