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usb: dwc2: gadget: add vbus_session support
[linux-2.6-block.git] / drivers / usb / dwc2 / core.h
CommitLineData
56f5b1cf
PZ		 1/*
2 * core.h - DesignWare HS OTG Controller common declarations
3 *
4 * Copyright (C) 2004-2013 Synopsys, Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions, and the following disclaimer,
11 * without modification.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The names of the above-listed copyright holders may not be used
16 * to endorse or promote products derived from this software without
17 * specific prior written permission.
18 *
19 * ALTERNATIVELY, this software may be distributed under the terms of the
20 * GNU General Public License ("GPL") as published by the Free Software
21 * Foundation; either version 2 of the License, or (at your option) any
22 * later version.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
25 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
28 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
29 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
30 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
31 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
32 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
33 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
34 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 */
36
37#ifndef __DWC2_CORE_H__
38#define __DWC2_CORE_H__
39
f7c0b143
DN		 40#include <linux/phy/phy.h>
41#include <linux/regulator/consumer.h>
42#include <linux/usb/gadget.h>
43#include <linux/usb/otg.h>
56f5b1cf
PZ		 44#include <linux/usb/phy.h>
45#include "hw.h"
46
47#ifdef DWC2_LOG_WRITES
48static inline void do_write(u32 value, void *addr)
49{
50 writel(value, addr);
51 pr_info("INFO:: wrote %08x to %p\n", value, addr);
52}
53
54#undef writel
55#define writel(v, a) do_write(v, a)
56#endif
57
58/* Maximum number of Endpoints/HostChannels */
59#define MAX_EPS_CHANNELS 16
60
f7c0b143
DN		 61/* s3c-hsotg declarations */
62static const char * const s3c_hsotg_supply_names[] = {
63 "vusb_d", /* digital USB supply, 1.2V */
64 "vusb_a", /* analog USB supply, 1.1V */
65};
66
67/*
68 * EP0_MPS_LIMIT
69 *
70 * Unfortunately there seems to be a limit of the amount of data that can
71 * be transferred by IN transactions on EP0. This is either 127 bytes or 3
72 * packets (which practically means 1 packet and 63 bytes of data) when the
73 * MPS is set to 64.
74 *
75 * This means if we are wanting to move >127 bytes of data, we need to
76 * split the transactions up, but just doing one packet at a time does
77 * not work (this may be an implicit DATA0 PID on first packet of the
78 * transaction) and doing 2 packets is outside the controller's limits.
79 *
80 * If we try to lower the MPS size for EP0, then no transfers work properly
81 * for EP0, and the system will fail basic enumeration. As no cause for this
82 * has currently been found, we cannot support any large IN transfers for
83 * EP0.
84 */
85#define EP0_MPS_LIMIT 64
86
941fcce4 87struct dwc2_hsotg;
f7c0b143
DN		 88struct s3c_hsotg_req;
89
90/**
91 * struct s3c_hsotg_ep - driver endpoint definition.
92 * @ep: The gadget layer representation of the endpoint.
93 * @name: The driver generated name for the endpoint.
94 * @queue: Queue of requests for this endpoint.
95 * @parent: Reference back to the parent device structure.
96 * @req: The current request that the endpoint is processing. This is
97 * used to indicate an request has been loaded onto the endpoint
98 * and has yet to be completed (maybe due to data move, or simply
99 * awaiting an ack from the core all the data has been completed).
100 * @debugfs: File entry for debugfs file for this endpoint.
101 * @lock: State lock to protect contents of endpoint.
102 * @dir_in: Set to true if this endpoint is of the IN direction, which
103 * means that it is sending data to the Host.
104 * @index: The index for the endpoint registers.
105 * @mc: Multi Count - number of transactions per microframe
106 * @interval - Interval for periodic endpoints
107 * @name: The name array passed to the USB core.
108 * @halted: Set if the endpoint has been halted.
109 * @periodic: Set if this is a periodic ep, such as Interrupt
110 * @isochronous: Set if this is a isochronous ep
111 * @sent_zlp: Set if we've sent a zero-length packet.
112 * @total_data: The total number of data bytes done.
113 * @fifo_size: The size of the FIFO (for periodic IN endpoints)
114 * @fifo_load: The amount of data loaded into the FIFO (periodic IN)
115 * @last_load: The offset of data for the last start of request.
116 * @size_loaded: The last loaded size for DxEPTSIZE for periodic IN
117 *
118 * This is the driver's state for each registered enpoint, allowing it
119 * to keep track of transactions that need doing. Each endpoint has a
120 * lock to protect the state, to try and avoid using an overall lock
121 * for the host controller as much as possible.
122 *
123 * For periodic IN endpoints, we have fifo_size and fifo_load to try
124 * and keep track of the amount of data in the periodic FIFO for each
125 * of these as we don't have a status register that tells us how much
126 * is in each of them. (note, this may actually be useless information
127 * as in shared-fifo mode periodic in acts like a single-frame packet
128 * buffer than a fifo)
129 */
130struct s3c_hsotg_ep {
131 struct usb_ep ep;
132 struct list_head queue;
941fcce4 133 struct dwc2_hsotg *parent;
f7c0b143
DN		 134 struct s3c_hsotg_req *req;
135 struct dentry *debugfs;
136
137 unsigned long total_data;
138 unsigned int size_loaded;
139 unsigned int last_load;
140 unsigned int fifo_load;
141 unsigned short fifo_size;
b203d0a2 142 unsigned short fifo_index;
f7c0b143
DN		 143
144 unsigned char dir_in;
145 unsigned char index;
146 unsigned char mc;
147 unsigned char interval;
148
149 unsigned int halted:1;
150 unsigned int periodic:1;
151 unsigned int isochronous:1;
152 unsigned int sent_zlp:1;
153
154 char name[10];
155};
156
f7c0b143
DN		 157/**
158 * struct s3c_hsotg_req - data transfer request
159 * @req: The USB gadget request
160 * @queue: The list of requests for the endpoint this is queued for.
f7c0b143
DN		 161 */
162struct s3c_hsotg_req {
163 struct usb_request req;
164 struct list_head queue;
f7c0b143
DN		 165};
166
941fcce4 167#if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
f7c0b143
DN		 168#define call_gadget(_hs, _entry) \
169do { \
170 if ((_hs)->gadget.speed != USB_SPEED_UNKNOWN && \
171 (_hs)->driver && (_hs)->driver->_entry) { \
172 spin_unlock(&_hs->lock); \
173 (_hs)->driver->_entry(&(_hs)->gadget); \
174 spin_lock(&_hs->lock); \
175 } \
176} while (0)
941fcce4
DN		 177#else
178#define call_gadget(_hs, _entry) do {} while (0)
179#endif
f7c0b143 180
56f5b1cf
PZ		 181struct dwc2_hsotg;
182struct dwc2_host_chan;
183
184/* Device States */
185enum dwc2_lx_state {
186 DWC2_L0, /* On state */
187 DWC2_L1, /* LPM sleep state */
188 DWC2_L2, /* USB suspend state */
189 DWC2_L3, /* Off state */
190};
191
0a176279
GH		 192/*
193 * Gadget periodic tx fifo sizes as used by legacy driver
194 * EP0 is not included
195 */
196#define DWC2_G_P_LEGACY_TX_FIFO_SIZE {256, 256, 256, 256, 768, 768, 768, \
197 768, 0, 0, 0, 0, 0, 0, 0}
198
fe0b94ab
MYK		 199/* Gadget ep0 states */
200enum dwc2_ep0_state {
201 DWC2_EP0_SETUP,
202 DWC2_EP0_DATA_IN,
203 DWC2_EP0_DATA_OUT,
204 DWC2_EP0_STATUS_IN,
205 DWC2_EP0_STATUS_OUT,
206};
207
56f5b1cf
PZ		 208/**
209 * struct dwc2_core_params - Parameters for configuring the core
210 *
91121c10
MK		 211 * @otg_cap: Specifies the OTG capabilities.
212 * 0 - HNP and SRP capable
56f5b1cf 213 * 1 - SRP Only capable
91121c10
MK		 214 * 2 - No HNP/SRP capable (always available)
215 * Defaults to best available option (0, 1, then 2)
725acc86 216 * @otg_ver: OTG version supported
91121c10 217 * 0 - 1.3 (default)
725acc86 218 * 1 - 2.0
56f5b1cf
PZ		 219 * @dma_enable: Specifies whether to use slave or DMA mode for accessing
220 * the data FIFOs. The driver will automatically detect the
221 * value for this parameter if none is specified.
91121c10 222 * 0 - Slave (always available)
56f5b1cf
PZ		 223 * 1 - DMA (default, if available)
224 * @dma_desc_enable: When DMA mode is enabled, specifies whether to use
225 * address DMA mode or descriptor DMA mode for accessing
226 * the data FIFOs. The driver will automatically detect the
227 * value for this if none is specified.
228 * 0 - Address DMA
229 * 1 - Descriptor DMA (default, if available)
230 * @speed: Specifies the maximum speed of operation in host and
231 * device mode. The actual speed depends on the speed of
232 * the attached device and the value of phy_type.
91121c10
MK		 233 * 0 - High Speed
234 * (default when phy_type is UTMI+ or ULPI)
56f5b1cf 235 * 1 - Full Speed
91121c10 236 * (default when phy_type is Full Speed)
56f5b1cf 237 * @enable_dynamic_fifo: 0 - Use coreConsultant-specified FIFO size parameters
91121c10 238 * 1 - Allow dynamic FIFO sizing (default, if available)
725acc86
PZ		 239 * @en_multiple_tx_fifo: Specifies whether dedicated per-endpoint transmit FIFOs
240 * are enabled
56f5b1cf
PZ		 241 * @host_rx_fifo_size: Number of 4-byte words in the Rx FIFO in host mode when
242 * dynamic FIFO sizing is enabled
91121c10
MK		 243 * 16 to 32768
244 * Actual maximum value is autodetected and also
245 * the default.
56f5b1cf
PZ		 246 * @host_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO
247 * in host mode when dynamic FIFO sizing is enabled
91121c10
MK		 248 * 16 to 32768
249 * Actual maximum value is autodetected and also
250 * the default.
56f5b1cf
PZ		 251 * @host_perio_tx_fifo_size: Number of 4-byte words in the periodic Tx FIFO in
252 * host mode when dynamic FIFO sizing is enabled
91121c10
MK		 253 * 16 to 32768
254 * Actual maximum value is autodetected and also
255 * the default.
56f5b1cf 256 * @max_transfer_size: The maximum transfer size supported, in bytes
91121c10
MK		 257 * 2047 to 65,535
258 * Actual maximum value is autodetected and also
259 * the default.
56f5b1cf 260 * @max_packet_count: The maximum number of packets in a transfer
91121c10
MK		 261 * 15 to 511
262 * Actual maximum value is autodetected and also
263 * the default.
56f5b1cf 264 * @host_channels: The number of host channel registers to use
91121c10
MK		 265 * 1 to 16
266 * Actual maximum value is autodetected and also
267 * the default.
56f5b1cf
PZ		 268 * @phy_type: Specifies the type of PHY interface to use. By default,
269 * the driver will automatically detect the phy_type.
91121c10
MK		 270 * 0 - Full Speed Phy
271 * 1 - UTMI+ Phy
272 * 2 - ULPI Phy
273 * Defaults to best available option (2, 1, then 0)
56f5b1cf
PZ		 274 * @phy_utmi_width: Specifies the UTMI+ Data Width (in bits). This parameter
275 * is applicable for a phy_type of UTMI+ or ULPI. (For a
276 * ULPI phy_type, this parameter indicates the data width
277 * between the MAC and the ULPI Wrapper.) Also, this
278 * parameter is applicable only if the OTG_HSPHY_WIDTH cC
279 * parameter was set to "8 and 16 bits", meaning that the
280 * core has been configured to work at either data path
281 * width.
91121c10 282 * 8 or 16 (default 16 if available)
56f5b1cf
PZ		 283 * @phy_ulpi_ddr: Specifies whether the ULPI operates at double or single
284 * data rate. This parameter is only applicable if phy_type
285 * is ULPI.
286 * 0 - single data rate ULPI interface with 8 bit wide
287 * data bus (default)
288 * 1 - double data rate ULPI interface with 4 bit wide
289 * data bus
290 * @phy_ulpi_ext_vbus: For a ULPI phy, specifies whether to use the internal or
291 * external supply to drive the VBus
91121c10
MK		 292 * 0 - Internal supply (default)
293 * 1 - External supply
56f5b1cf
PZ		 294 * @i2c_enable: Specifies whether to use the I2Cinterface for a full
295 * speed PHY. This parameter is only applicable if phy_type
296 * is FS.
297 * 0 - No (default)
298 * 1 - Yes
91121c10
MK		 299 * @ulpi_fs_ls: Make ULPI phy operate in FS/LS mode only
300 * 0 - No (default)
301 * 1 - Yes
725acc86
PZ		 302 * @host_support_fs_ls_low_power: Specifies whether low power mode is supported
303 * when attached to a Full Speed or Low Speed device in
304 * host mode.
305 * 0 - Don't support low power mode (default)
306 * 1 - Support low power mode
307 * @host_ls_low_power_phy_clk: Specifies the PHY clock rate in low power mode
91121c10
MK		 308 * when connected to a Low Speed device in host
309 * mode. This parameter is applicable only if
310 * host_support_fs_ls_low_power is enabled.
725acc86 311 * 0 - 48 MHz
91121c10 312 * (default when phy_type is UTMI+ or ULPI)
725acc86 313 * 1 - 6 MHz
91121c10
MK		 314 * (default when phy_type is Full Speed)
315 * @ts_dline: Enable Term Select Dline pulsing
316 * 0 - No (default)
317 * 1 - Yes
318 * @reload_ctl: Allow dynamic reloading of HFIR register during runtime
319 * 0 - No (default for core < 2.92a)
320 * 1 - Yes (default for core >= 2.92a)
4d3190e1
PZ		 321 * @ahbcfg: This field allows the default value of the GAHBCFG
322 * register to be overridden
91121c10
MK		 323 * -1 - GAHBCFG value will be set to 0x06
324 * (INCR4, default)
4d3190e1
PZ		 325 * all others - GAHBCFG value will be overridden with
326 * this value
91121c10
MK		 327 * Not all bits can be controlled like this, the
328 * bits defined by GAHBCFG_CTRL_MASK are controlled
329 * by the driver and are ignored in this
330 * configuration value.
20f2eb9c 331 * @uframe_sched: True to enable the microframe scheduler
56f5b1cf
PZ		 332 *
333 * The following parameters may be specified when starting the module. These
91121c10
MK		 334 * parameters define how the DWC_otg controller should be configured. A
335 * value of -1 (or any other out of range value) for any parameter means
336 * to read the value from hardware (if possible) or use the builtin
337 * default described above.
56f5b1cf
PZ		 338 */
339struct dwc2_core_params {
8284f93b
MK		 340 /*
341 * Don't add any non-int members here, this will break
342 * dwc2_set_all_params!
343 */
56f5b1cf
PZ		 344 int otg_cap;
345 int otg_ver;
346 int dma_enable;
347 int dma_desc_enable;
348 int speed;
349 int enable_dynamic_fifo;
350 int en_multiple_tx_fifo;
351 int host_rx_fifo_size;
352 int host_nperio_tx_fifo_size;
353 int host_perio_tx_fifo_size;
354 int max_transfer_size;
355 int max_packet_count;
356 int host_channels;
357 int phy_type;
358 int phy_utmi_width;
359 int phy_ulpi_ddr;
360 int phy_ulpi_ext_vbus;
361 int i2c_enable;
362 int ulpi_fs_ls;
363 int host_support_fs_ls_low_power;
364 int host_ls_low_power_phy_clk;
365 int ts_dline;
366 int reload_ctl;
4d3190e1 367 int ahbcfg;
20f2eb9c 368 int uframe_sched;
56f5b1cf
PZ		 369};
370
9badec2f
MK		 371/**
372 * struct dwc2_hw_params - Autodetected parameters.
373 *
374 * These parameters are the various parameters read from hardware
375 * registers during initialization. They typically contain the best
376 * supported or maximum value that can be configured in the
377 * corresponding dwc2_core_params value.
378 *
379 * The values that are not in dwc2_core_params are documented below.
380 *
381 * @op_mode Mode of Operation
382 * 0 - HNP- and SRP-Capable OTG (Host & Device)
383 * 1 - SRP-Capable OTG (Host & Device)
384 * 2 - Non-HNP and Non-SRP Capable OTG (Host & Device)
385 * 3 - SRP-Capable Device
386 * 4 - Non-OTG Device
387 * 5 - SRP-Capable Host
388 * 6 - Non-OTG Host
389 * @arch Architecture
390 * 0 - Slave only
391 * 1 - External DMA
392 * 2 - Internal DMA
393 * @power_optimized Are power optimizations enabled?
394 * @num_dev_ep Number of device endpoints available
395 * @num_dev_perio_in_ep Number of device periodic IN endpoints
997f4f81 396 * available
9badec2f
MK		 397 * @dev_token_q_depth Device Mode IN Token Sequence Learning Queue
398 * Depth
399 * 0 to 30
400 * @host_perio_tx_q_depth
401 * Host Mode Periodic Request Queue Depth
402 * 2, 4 or 8
403 * @nperio_tx_q_depth
404 * Non-Periodic Request Queue Depth
405 * 2, 4 or 8
406 * @hs_phy_type High-speed PHY interface type
407 * 0 - High-speed interface not supported
408 * 1 - UTMI+
409 * 2 - ULPI
410 * 3 - UTMI+ and ULPI
411 * @fs_phy_type Full-speed PHY interface type
412 * 0 - Full speed interface not supported
413 * 1 - Dedicated full speed interface
414 * 2 - FS pins shared with UTMI+ pins
415 * 3 - FS pins shared with ULPI pins
416 * @total_fifo_size: Total internal RAM for FIFOs (bytes)
de4a1931
MK		 417 * @utmi_phy_data_width UTMI+ PHY data width
418 * 0 - 8 bits
419 * 1 - 16 bits
420 * 2 - 8 or 16 bits
9badec2f
MK		 421 * @snpsid: Value from SNPSID register
422 */
423struct dwc2_hw_params {
424 unsigned op_mode:3;
425 unsigned arch:2;
426 unsigned dma_desc_enable:1;
427 unsigned enable_dynamic_fifo:1;
428 unsigned en_multiple_tx_fifo:1;
429 unsigned host_rx_fifo_size:16;
430 unsigned host_nperio_tx_fifo_size:16;
431 unsigned host_perio_tx_fifo_size:16;
432 unsigned nperio_tx_q_depth:3;
433 unsigned host_perio_tx_q_depth:3;
434 unsigned dev_token_q_depth:5;
435 unsigned max_transfer_size:26;
436 unsigned max_packet_count:11;
2d115547 437 unsigned host_channels:5;
9badec2f
MK		 438 unsigned hs_phy_type:2;
439 unsigned fs_phy_type:2;
440 unsigned i2c_enable:1;
441 unsigned num_dev_ep:4;
442 unsigned num_dev_perio_in_ep:4;
443 unsigned total_fifo_size:16;
444 unsigned power_optimized:1;
de4a1931 445 unsigned utmi_phy_data_width:2;
9badec2f
MK		 446 u32 snpsid;
447};
448
3f95001d
MYK		 449/* Size of control and EP0 buffers */
450#define DWC2_CTRL_BUFF_SIZE 8
451
56f5b1cf
PZ		 452/**
453 * struct dwc2_hsotg - Holds the state of the driver, including the non-periodic
454 * and periodic schedules
455 *
941fcce4
DN		 456 * These are common for both host and peripheral modes:
457 *
56f5b1cf
PZ		 458 * @dev: The struct device pointer
459 * @regs: Pointer to controller regs
9badec2f
MK		 460 * @hw_params: Parameters that were autodetected from the
461 * hardware registers
941fcce4 462 * @core_params: Parameters that define how the core should be configured
56f5b1cf
PZ		 463 * @op_state: The operational State, during transitions (a_host=>
464 * a_peripheral and b_device=>b_host) this may not match
465 * the core, but allows the software to determine
466 * transitions
c0155b9d
KY		 467 * @dr_mode: Requested mode of operation, one of following:
468 * - USB_DR_MODE_PERIPHERAL
469 * - USB_DR_MODE_HOST
470 * - USB_DR_MODE_OTG
941fcce4
DN		 471 * @lock: Spinlock that protects all the driver data structures
472 * @priv: Stores a pointer to the struct usb_hcd
56f5b1cf
PZ		 473 * @queuing_high_bandwidth: True if multiple packets of a high-bandwidth
474 * transfer are in process of being queued
475 * @srp_success: Stores status of SRP request in the case of a FS PHY
476 * with an I2C interface
477 * @wq_otg: Workqueue object used for handling of some interrupts
478 * @wf_otg: Work object for handling Connector ID Status Change
479 * interrupt
480 * @wkp_timer: Timer object for handling Wakeup Detected interrupt
481 * @lx_state: Lx state of connected device
941fcce4
DN		 482 *
483 * These are for host mode:
484 *
56f5b1cf
PZ		 485 * @flags: Flags for handling root port state changes
486 * @non_periodic_sched_inactive: Inactive QHs in the non-periodic schedule.
487 * Transfers associated with these QHs are not currently
488 * assigned to a host channel.
489 * @non_periodic_sched_active: Active QHs in the non-periodic schedule.
490 * Transfers associated with these QHs are currently
491 * assigned to a host channel.
492 * @non_periodic_qh_ptr: Pointer to next QH to process in the active
493 * non-periodic schedule
494 * @periodic_sched_inactive: Inactive QHs in the periodic schedule. This is a
495 * list of QHs for periodic transfers that are _not_
496 * scheduled for the next frame. Each QH in the list has an
497 * interval counter that determines when it needs to be
498 * scheduled for execution. This scheduling mechanism
499 * allows only a simple calculation for periodic bandwidth
500 * used (i.e. must assume that all periodic transfers may
501 * need to execute in the same frame). However, it greatly
502 * simplifies scheduling and should be sufficient for the
503 * vast majority of OTG hosts, which need to connect to a
504 * small number of peripherals at one time. Items move from
505 * this list to periodic_sched_ready when the QH interval
506 * counter is 0 at SOF.
507 * @periodic_sched_ready: List of periodic QHs that are ready for execution in
508 * the next frame, but have not yet been assigned to host
509 * channels. Items move from this list to
510 * periodic_sched_assigned as host channels become
511 * available during the current frame.
512 * @periodic_sched_assigned: List of periodic QHs to be executed in the next
513 * frame that are assigned to host channels. Items move
514 * from this list to periodic_sched_queued as the
515 * transactions for the QH are queued to the DWC_otg
516 * controller.
517 * @periodic_sched_queued: List of periodic QHs that have been queued for
518 * execution. Items move from this list to either
519 * periodic_sched_inactive or periodic_sched_ready when the
520 * channel associated with the transfer is released. If the
521 * interval for the QH is 1, the item moves to
522 * periodic_sched_ready because it must be rescheduled for
523 * the next frame. Otherwise, the item moves to
524 * periodic_sched_inactive.
525 * @periodic_usecs: Total bandwidth claimed so far for periodic transfers.
526 * This value is in microseconds per (micro)frame. The
527 * assumption is that all periodic transfers may occur in
528 * the same (micro)frame.
20f2eb9c 529 * @frame_usecs: Internal variable used by the microframe scheduler
56f5b1cf
PZ		 530 * @frame_number: Frame number read from the core at SOF. The value ranges
531 * from 0 to HFNUM_MAX_FRNUM.
532 * @periodic_qh_count: Count of periodic QHs, if using several eps. Used for
533 * SOF enable/disable.
534 * @free_hc_list: Free host channels in the controller. This is a list of
535 * struct dwc2_host_chan items.
536 * @periodic_channels: Number of host channels assigned to periodic transfers.
537 * Currently assuming that there is a dedicated host
538 * channel for each periodic transaction and at least one
539 * host channel is available for non-periodic transactions.
540 * @non_periodic_channels: Number of host channels assigned to non-periodic
541 * transfers
20f2eb9c
DC		 542 * @available_host_channels Number of host channels available for the microframe
543 * scheduler to use
56f5b1cf
PZ		 544 * @hc_ptr_array: Array of pointers to the host channel descriptors.
545 * Allows accessing a host channel descriptor given the
546 * host channel number. This is useful in interrupt
547 * handlers.
548 * @status_buf: Buffer used for data received during the status phase of
549 * a control transfer.
550 * @status_buf_dma: DMA address for status_buf
551 * @start_work: Delayed work for handling host A-cable connection
552 * @reset_work: Delayed work for handling a port reset
56f5b1cf
PZ		 553 * @otg_port: OTG port number
554 * @frame_list: Frame list
555 * @frame_list_dma: Frame list DMA address
941fcce4
DN		 556 *
557 * These are for peripheral mode:
558 *
559 * @driver: USB gadget driver
560 * @phy: The otg phy transceiver structure for phy control.
561 * @uphy: The otg phy transceiver structure for old USB phy control.
562 * @plat: The platform specific configuration data. This can be removed once
563 * all SoCs support usb transceiver.
564 * @supplies: Definition of USB power supplies
565 * @phyif: PHY interface width
566 * @dedicated_fifos: Set if the hardware has dedicated IN-EP fifos.
567 * @num_of_eps: Number of available EPs (excluding EP0)
568 * @debug_root: Root directrory for debugfs.
569 * @debug_file: Main status file for debugfs.
570 * @debug_fifo: FIFO status file for debugfs.
571 * @ep0_reply: Request used for ep0 reply.
572 * @ep0_buff: Buffer for EP0 reply data, if needed.
573 * @ctrl_buff: Buffer for EP0 control requests.
574 * @ctrl_req: Request for EP0 control packets.
fe0b94ab 575 * @ep0_state: EP0 control transfers state
941fcce4
DN		 576 * @last_rst: Time of last reset
577 * @eps: The endpoints being supplied to the gadget framework
edd74be8 578 * @g_using_dma: Indicate if dma usage is enabled
0a176279
GH		 579 * @g_rx_fifo_sz: Contains rx fifo size value
580 * @g_np_g_tx_fifo_sz: Contains Non-Periodic tx fifo size value
581 * @g_tx_fifo_sz: Contains tx fifo size value per endpoints
56f5b1cf
PZ		 582 */
583struct dwc2_hsotg {
584 struct device *dev;
585 void __iomem *regs;
9badec2f
MK		 586 /** Params detected from hardware */
587 struct dwc2_hw_params hw_params;
588 /** Params to actually use */
56f5b1cf 589 struct dwc2_core_params *core_params;
56f5b1cf 590 enum usb_otg_state op_state;
c0155b9d 591 enum usb_dr_mode dr_mode;
56f5b1cf 592
941fcce4
DN		 593 struct phy *phy;
594 struct usb_phy *uphy;
595 struct regulator_bulk_data supplies[ARRAY_SIZE(s3c_hsotg_supply_names)];
596
597 spinlock_t lock;
7ad8096e 598 struct mutex init_mutex;
941fcce4
DN		 599 void *priv;
600 int irq;
601 struct clk *clk;
602
56f5b1cf
PZ		 603 unsigned int queuing_high_bandwidth:1;
604 unsigned int srp_success:1;
605
606 struct workqueue_struct *wq_otg;
607 struct work_struct wf_otg;
608 struct timer_list wkp_timer;
609 enum dwc2_lx_state lx_state;
610
941fcce4
DN		 611 struct dentry *debug_root;
612 struct dentry *debug_file;
613 struct dentry *debug_fifo;
614
615 /* DWC OTG HW Release versions */
616#define DWC2_CORE_REV_2_71a 0x4f54271a
617#define DWC2_CORE_REV_2_90a 0x4f54290a
618#define DWC2_CORE_REV_2_92a 0x4f54292a
619#define DWC2_CORE_REV_2_94a 0x4f54294a
620#define DWC2_CORE_REV_3_00a 0x4f54300a
621
622#if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
56f5b1cf
PZ		 623 union dwc2_hcd_internal_flags {
624 u32 d32;
625 struct {
626 unsigned port_connect_status_change:1;
627 unsigned port_connect_status:1;
628 unsigned port_reset_change:1;
629 unsigned port_enable_change:1;
630 unsigned port_suspend_change:1;
631 unsigned port_over_current_change:1;
632 unsigned port_l1_change:1;
fd4850cf 633 unsigned reserved:25;
56f5b1cf
PZ		 634 } b;
635 } flags;
636
637 struct list_head non_periodic_sched_inactive;
638 struct list_head non_periodic_sched_active;
639 struct list_head *non_periodic_qh_ptr;
640 struct list_head periodic_sched_inactive;
641 struct list_head periodic_sched_ready;
642 struct list_head periodic_sched_assigned;
643 struct list_head periodic_sched_queued;
644 u16 periodic_usecs;
20f2eb9c 645 u16 frame_usecs[8];
56f5b1cf
PZ		 646 u16 frame_number;
647 u16 periodic_qh_count;
648
649#ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
650#define FRAME_NUM_ARRAY_SIZE 1000
651 u16 last_frame_num;
652 u16 *frame_num_array;
653 u16 *last_frame_num_array;
654 int frame_num_idx;
655 int dumped_frame_num_array;
656#endif
657
658 struct list_head free_hc_list;
659 int periodic_channels;
660 int non_periodic_channels;
20f2eb9c 661 int available_host_channels;
56f5b1cf
PZ		 662 struct dwc2_host_chan *hc_ptr_array[MAX_EPS_CHANNELS];
663 u8 *status_buf;
664 dma_addr_t status_buf_dma;
665#define DWC2_HCD_STATUS_BUF_SIZE 64
666
667 struct delayed_work start_work;
668 struct delayed_work reset_work;
56f5b1cf
PZ		 669 u8 otg_port;
670 u32 *frame_list;
671 dma_addr_t frame_list_dma;
672
56f5b1cf
PZ		 673#ifdef DEBUG
674 u32 frrem_samples;
675 u64 frrem_accum;
676
677 u32 hfnum_7_samples_a;
678 u64 hfnum_7_frrem_accum_a;
679 u32 hfnum_0_samples_a;
680 u64 hfnum_0_frrem_accum_a;
681 u32 hfnum_other_samples_a;
682 u64 hfnum_other_frrem_accum_a;
683
684 u32 hfnum_7_samples_b;
685 u64 hfnum_7_frrem_accum_b;
686 u32 hfnum_0_samples_b;
687 u64 hfnum_0_frrem_accum_b;
688 u32 hfnum_other_samples_b;
689 u64 hfnum_other_frrem_accum_b;
690#endif
941fcce4
DN		 691#endif /* CONFIG_USB_DWC2_HOST || CONFIG_USB_DWC2_DUAL_ROLE */
692
693#if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
694 /* Gadget structures */
695 struct usb_gadget_driver *driver;
696 struct s3c_hsotg_plat *plat;
697
698 u32 phyif;
699 int fifo_mem;
700 unsigned int dedicated_fifos:1;
701 unsigned char num_of_eps;
702 u32 fifo_map;
703
704 struct usb_request *ep0_reply;
705 struct usb_request *ctrl_req;
3f95001d
MYK		 706 void *ep0_buff;
707 void *ctrl_buff;
fe0b94ab 708 enum dwc2_ep0_state ep0_state;
941fcce4
DN		 709
710 struct usb_gadget gadget;
dc6e69e6 711 unsigned int enabled:1;
4ace06e8 712 unsigned int connected:1;
941fcce4 713 unsigned long last_rst;
c6f5c050
MYK		 714 struct s3c_hsotg_ep *eps_in[MAX_EPS_CHANNELS];
715 struct s3c_hsotg_ep *eps_out[MAX_EPS_CHANNELS];
edd74be8 716 u32 g_using_dma;
0a176279
GH		 717 u32 g_rx_fifo_sz;
718 u32 g_np_g_tx_fifo_sz;
719 u32 g_tx_fifo_sz[MAX_EPS_CHANNELS];
941fcce4 720#endif /* CONFIG_USB_DWC2_PERIPHERAL || CONFIG_USB_DWC2_DUAL_ROLE */
56f5b1cf
PZ		 721};
722
723/* Reasons for halting a host channel */
724enum dwc2_halt_status {
725 DWC2_HC_XFER_NO_HALT_STATUS,
726 DWC2_HC_XFER_COMPLETE,
727 DWC2_HC_XFER_URB_COMPLETE,
728 DWC2_HC_XFER_ACK,
729 DWC2_HC_XFER_NAK,
730 DWC2_HC_XFER_NYET,
731 DWC2_HC_XFER_STALL,
732 DWC2_HC_XFER_XACT_ERR,
733 DWC2_HC_XFER_FRAME_OVERRUN,
734 DWC2_HC_XFER_BABBLE_ERR,
735 DWC2_HC_XFER_DATA_TOGGLE_ERR,
736 DWC2_HC_XFER_AHB_ERR,
737 DWC2_HC_XFER_PERIODIC_INCOMPLETE,
738 DWC2_HC_XFER_URB_DEQUEUE,
739};
740
741/*
742 * The following functions support initialization of the core driver component
743 * and the DWC_otg controller
744 */
745extern void dwc2_core_host_init(struct dwc2_hsotg *hsotg);
746
747/*
748 * Host core Functions.
749 * The following functions support managing the DWC_otg controller in host
750 * mode.
751 */
752extern void dwc2_hc_init(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan);
753extern void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan,
754 enum dwc2_halt_status halt_status);
755extern void dwc2_hc_cleanup(struct dwc2_hsotg *hsotg,
756 struct dwc2_host_chan *chan);
757extern void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg,
758 struct dwc2_host_chan *chan);
759extern void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg,
760 struct dwc2_host_chan *chan);
761extern int dwc2_hc_continue_transfer(struct dwc2_hsotg *hsotg,
762 struct dwc2_host_chan *chan);
763extern void dwc2_hc_do_ping(struct dwc2_hsotg *hsotg,
764 struct dwc2_host_chan *chan);
765extern void dwc2_enable_host_interrupts(struct dwc2_hsotg *hsotg);
766extern void dwc2_disable_host_interrupts(struct dwc2_hsotg *hsotg);
767
768extern u32 dwc2_calc_frame_interval(struct dwc2_hsotg *hsotg);
057715f2 769extern bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg);
56f5b1cf
PZ		 770
771/*
772 * Common core Functions.
773 * The following functions support managing the DWC_otg controller in either
774 * device or host mode.
775 */
776extern void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes);
777extern void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num);
778extern void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg);
779
6706c721 780extern int dwc2_core_init(struct dwc2_hsotg *hsotg, bool select_phy, int irq);
56f5b1cf
PZ		 781extern void dwc2_enable_global_interrupts(struct dwc2_hsotg *hcd);
782extern void dwc2_disable_global_interrupts(struct dwc2_hsotg *hcd);
783
784/* This function should be called on every hardware interrupt. */
785extern irqreturn_t dwc2_handle_common_intr(int irq, void *dev);
786
787/* OTG Core Parameters */
788
789/*
790 * Specifies the OTG capabilities. The driver will automatically
791 * detect the value for this parameter if none is specified.
792 * 0 - HNP and SRP capable (default)
793 * 1 - SRP Only capable
794 * 2 - No HNP/SRP capable
795 */
7218dae7 796extern void dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg, int val);
56f5b1cf
PZ		 797#define DWC2_CAP_PARAM_HNP_SRP_CAPABLE 0
798#define DWC2_CAP_PARAM_SRP_ONLY_CAPABLE 1
799#define DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE 2
800
801/*
802 * Specifies whether to use slave or DMA mode for accessing the data
803 * FIFOs. The driver will automatically detect the value for this
804 * parameter if none is specified.
805 * 0 - Slave
806 * 1 - DMA (default, if available)
807 */
7218dae7 808extern void dwc2_set_param_dma_enable(struct dwc2_hsotg *hsotg, int val);
56f5b1cf
PZ		 809
810/*
811 * When DMA mode is enabled specifies whether to use
812 * address DMA or DMA Descritor mode for accessing the data
813 * FIFOs in device mode. The driver will automatically detect
814 * the value for this parameter if none is specified.
815 * 0 - address DMA
816 * 1 - DMA Descriptor(default, if available)
817 */
7218dae7 818extern void dwc2_set_param_dma_desc_enable(struct dwc2_hsotg *hsotg, int val);
56f5b1cf
PZ		 819
820/*
821 * Specifies the maximum speed of operation in host and device mode.
822 * The actual speed depends on the speed of the attached device and
823 * the value of phy_type. The actual speed depends on the speed of the
824 * attached device.
825 * 0 - High Speed (default)
826 * 1 - Full Speed
827 */
7218dae7 828extern void dwc2_set_param_speed(struct dwc2_hsotg *hsotg, int val);
56f5b1cf
PZ		 829#define DWC2_SPEED_PARAM_HIGH 0
830#define DWC2_SPEED_PARAM_FULL 1
831
832/*
833 * Specifies whether low power mode is supported when attached
834 * to a Full Speed or Low Speed device in host mode.
835 *
836 * 0 - Don't support low power mode (default)
837 * 1 - Support low power mode
838 */
7218dae7
PZ		 839extern void dwc2_set_param_host_support_fs_ls_low_power(
840 struct dwc2_hsotg *hsotg, int val);
56f5b1cf
PZ		 841
842/*
843 * Specifies the PHY clock rate in low power mode when connected to a
844 * Low Speed device in host mode. This parameter is applicable only if
845 * HOST_SUPPORT_FS_LS_LOW_POWER is enabled. If PHY_TYPE is set to FS
846 * then defaults to 6 MHZ otherwise 48 MHZ.
847 *
848 * 0 - 48 MHz
849 * 1 - 6 MHz
850 */
7218dae7
PZ		 851extern void dwc2_set_param_host_ls_low_power_phy_clk(struct dwc2_hsotg *hsotg,
852 int val);
56f5b1cf
PZ		 853#define DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ 0
854#define DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ 1
855
856/*
857 * 0 - Use cC FIFO size parameters
858 * 1 - Allow dynamic FIFO sizing (default)
859 */
7218dae7
PZ		 860extern void dwc2_set_param_enable_dynamic_fifo(struct dwc2_hsotg *hsotg,
861 int val);
56f5b1cf
PZ		 862
863/*
864 * Number of 4-byte words in the Rx FIFO in host mode when dynamic
865 * FIFO sizing is enabled.
866 * 16 to 32768 (default 1024)
867 */
7218dae7 868extern void dwc2_set_param_host_rx_fifo_size(struct dwc2_hsotg *hsotg, int val);
56f5b1cf
PZ		 869
870/*
871 * Number of 4-byte words in the non-periodic Tx FIFO in host mode
872 * when Dynamic FIFO sizing is enabled in the core.
873 * 16 to 32768 (default 256)
874 */
7218dae7
PZ		 875extern void dwc2_set_param_host_nperio_tx_fifo_size(struct dwc2_hsotg *hsotg,
876 int val);
56f5b1cf
PZ		 877
878/*
879 * Number of 4-byte words in the host periodic Tx FIFO when dynamic
880 * FIFO sizing is enabled.
881 * 16 to 32768 (default 256)
882 */
7218dae7
PZ		 883extern void dwc2_set_param_host_perio_tx_fifo_size(struct dwc2_hsotg *hsotg,
884 int val);
56f5b1cf
PZ		 885
886/*
887 * The maximum transfer size supported in bytes.
888 * 2047 to 65,535 (default 65,535)
889 */
7218dae7 890extern void dwc2_set_param_max_transfer_size(struct dwc2_hsotg *hsotg, int val);
56f5b1cf
PZ		 891
892/*
893 * The maximum number of packets in a transfer.
894 * 15 to 511 (default 511)
895 */
7218dae7 896extern void dwc2_set_param_max_packet_count(struct dwc2_hsotg *hsotg, int val);
56f5b1cf
PZ		 897
898/*
899 * The number of host channel registers to use.
900 * 1 to 16 (default 11)
901 * Note: The FPGA configuration supports a maximum of 11 host channels.
902 */
7218dae7 903extern void dwc2_set_param_host_channels(struct dwc2_hsotg *hsotg, int val);
56f5b1cf
PZ		 904
905/*
906 * Specifies the type of PHY interface to use. By default, the driver
907 * will automatically detect the phy_type.
908 *
909 * 0 - Full Speed PHY
910 * 1 - UTMI+ (default)
911 * 2 - ULPI
912 */
7218dae7 913extern void dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg, int val);
56f5b1cf
PZ		 914#define DWC2_PHY_TYPE_PARAM_FS 0
915#define DWC2_PHY_TYPE_PARAM_UTMI 1
916#define DWC2_PHY_TYPE_PARAM_ULPI 2
917
918/*
919 * Specifies the UTMI+ Data Width. This parameter is
920 * applicable for a PHY_TYPE of UTMI+ or ULPI. (For a ULPI
921 * PHY_TYPE, this parameter indicates the data width between
922 * the MAC and the ULPI Wrapper.) Also, this parameter is
923 * applicable only if the OTG_HSPHY_WIDTH cC parameter was set
924 * to "8 and 16 bits", meaning that the core has been
925 * configured to work at either data path width.
926 *
927 * 8 or 16 bits (default 16)
928 */
7218dae7 929extern void dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg, int val);
56f5b1cf
PZ		 930
931/*
932 * Specifies whether the ULPI operates at double or single
933 * data rate. This parameter is only applicable if PHY_TYPE is
934 * ULPI.
935 *
936 * 0 - single data rate ULPI interface with 8 bit wide data
937 * bus (default)
938 * 1 - double data rate ULPI interface with 4 bit wide data
939 * bus
940 */
7218dae7 941extern void dwc2_set_param_phy_ulpi_ddr(struct dwc2_hsotg *hsotg, int val);
56f5b1cf
PZ		 942
943/*
944 * Specifies whether to use the internal or external supply to
945 * drive the vbus with a ULPI phy.
946 */
7218dae7 947extern void dwc2_set_param_phy_ulpi_ext_vbus(struct dwc2_hsotg *hsotg, int val);
56f5b1cf
PZ		 948#define DWC2_PHY_ULPI_INTERNAL_VBUS 0
949#define DWC2_PHY_ULPI_EXTERNAL_VBUS 1
950
951/*
952 * Specifies whether to use the I2Cinterface for full speed PHY. This
953 * parameter is only applicable if PHY_TYPE is FS.
954 * 0 - No (default)
955 * 1 - Yes
956 */
7218dae7 957extern void dwc2_set_param_i2c_enable(struct dwc2_hsotg *hsotg, int val);
56f5b1cf 958
7218dae7 959extern void dwc2_set_param_ulpi_fs_ls(struct dwc2_hsotg *hsotg, int val);
56f5b1cf 960
7218dae7 961extern void dwc2_set_param_ts_dline(struct dwc2_hsotg *hsotg, int val);
56f5b1cf
PZ		 962
963/*
964 * Specifies whether dedicated transmit FIFOs are
965 * enabled for non periodic IN endpoints in device mode
966 * 0 - No
967 * 1 - Yes
968 */
7218dae7
PZ		 969extern void dwc2_set_param_en_multiple_tx_fifo(struct dwc2_hsotg *hsotg,
970 int val);
56f5b1cf 971
7218dae7 972extern void dwc2_set_param_reload_ctl(struct dwc2_hsotg *hsotg, int val);
56f5b1cf 973
7218dae7 974extern void dwc2_set_param_ahbcfg(struct dwc2_hsotg *hsotg, int val);
56f5b1cf 975
7218dae7 976extern void dwc2_set_param_otg_ver(struct dwc2_hsotg *hsotg, int val);
56f5b1cf
PZ		 977
978/*
979 * Dump core registers and SPRAM
980 */
981extern void dwc2_dump_dev_registers(struct dwc2_hsotg *hsotg);
982extern void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg);
983extern void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg);
984
985/*
986 * Return OTG version - either 1.3 or 2.0
987 */
988extern u16 dwc2_get_otg_version(struct dwc2_hsotg *hsotg);
989
117777b2
DN		 990/* Gadget defines */
991#if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
992extern int s3c_hsotg_remove(struct dwc2_hsotg *hsotg);
993extern int s3c_hsotg_suspend(struct dwc2_hsotg *dwc2);
994extern int s3c_hsotg_resume(struct dwc2_hsotg *dwc2);
995extern int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq);
510ffaa4
DN		 996extern void s3c_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2);
997extern void s3c_hsotg_core_connect(struct dwc2_hsotg *hsotg);
4ace06e8 998extern void s3c_hsotg_disconnect(struct dwc2_hsotg *dwc2);
117777b2
DN		 999#else
1000static inline int s3c_hsotg_remove(struct dwc2_hsotg *dwc2)
1001{ return 0; }
1002static inline int s3c_hsotg_suspend(struct dwc2_hsotg *dwc2)
1003{ return 0; }
1004static inline int s3c_hsotg_resume(struct dwc2_hsotg *dwc2)
1005{ return 0; }
1006static inline int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq)
1007{ return 0; }
510ffaa4
DN		 1008static inline void s3c_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2) {}
1009static inline void s3c_hsotg_core_connect(struct dwc2_hsotg *hsotg) {}
4ace06e8 1010static inline void s3c_hsotg_disconnect(struct dwc2_hsotg *dwc2) {}
117777b2
DN		 1011#endif
1012
1013#if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
1014extern int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg);
1015extern void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg);
1016extern void dwc2_hcd_start(struct dwc2_hsotg *hsotg);
1017#else
1018static inline void dwc2_set_all_params(struct dwc2_core_params *params, int value) {}
1019static inline int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg)
1020{ return 0; }
1021static inline void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg) {}
1022static inline void dwc2_hcd_start(struct dwc2_hsotg *hsotg) {}
1023static inline void dwc2_hcd_remove(struct dwc2_hsotg *hsotg) {}
1024static inline int dwc2_hcd_init(struct dwc2_hsotg *hsotg, int irq,
1025 const struct dwc2_core_params *params)
1026{ return 0; }
1027#endif
1028
56f5b1cf 1029#endif /* __DWC2_CORE_H__ */
Linux 6.x block layer and io_uring tree(s)