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usb: dwc2: Enable LPM
[linux-2.6-block.git] / drivers / usb / dwc2 / core.h
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5fd54ace 1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
56f5b1cf
PZ		 2/*
3 * core.h - DesignWare HS OTG Controller common declarations
4 *
5 * Copyright (C) 2004-2013 Synopsys, Inc.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions, and the following disclaimer,
12 * without modification.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. The names of the above-listed copyright holders may not be used
17 * to endorse or promote products derived from this software without
18 * specific prior written permission.
19 *
20 * ALTERNATIVELY, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") as published by the Free Software
22 * Foundation; either version 2 of the License, or (at your option) any
23 * later version.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
26 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
27 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
29 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
30 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
31 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
32 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
33 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
34 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
35 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 */
37
38#ifndef __DWC2_CORE_H__
39#define __DWC2_CORE_H__
40
f7c0b143
DN		 41#include <linux/phy/phy.h>
42#include <linux/regulator/consumer.h>
43#include <linux/usb/gadget.h>
44#include <linux/usb/otg.h>
56f5b1cf
PZ		 45#include <linux/usb/phy.h>
46#include "hw.h"
47
74fc4a75
DA		 48/*
49 * Suggested defines for tracers:
50 * - no_printk: Disable tracing
51 * - pr_info: Print this info to the console
52 * - trace_printk: Print this info to trace buffer (good for verbose logging)
53 */
54
55#define DWC2_TRACE_SCHEDULER no_printk
56#define DWC2_TRACE_SCHEDULER_VB no_printk
57
58/* Detailed scheduler tracing, but won't overwhelm console */
59#define dwc2_sch_dbg(hsotg, fmt, ...) \
60 DWC2_TRACE_SCHEDULER(pr_fmt("%s: SCH: " fmt), \
61 dev_name(hsotg->dev), ##__VA_ARGS__)
62
63/* Verbose scheduler tracing */
64#define dwc2_sch_vdbg(hsotg, fmt, ...) \
65 DWC2_TRACE_SCHEDULER_VB(pr_fmt("%s: SCH: " fmt), \
66 dev_name(hsotg->dev), ##__VA_ARGS__)
67
23e34392
AB		 68#ifdef CONFIG_MIPS
69/*
70 * There are some MIPS machines that can run in either big-endian
71 * or little-endian mode and that use the dwc2 register without
72 * a byteswap in both ways.
73 * Unlike other architectures, MIPS apparently does not require a
74 * barrier before the __raw_writel() to synchronize with DMA but does
75 * require the barrier after the __raw_writel() to serialize a set of
76 * writes. This set of operations was added specifically for MIPS and
77 * should only be used there.
78 */
95c8bc36 79static inline u32 dwc2_readl(const void __iomem *addr)
56f5b1cf 80{
95c8bc36
AS		 81 u32 value = __raw_readl(addr);
82
83 /* In order to preserve endianness __raw_* operation is used. Therefore
84 * a barrier is needed to ensure IO access is not re-ordered across
85 * reads or writes
86 */
87 mb();
88 return value;
56f5b1cf
PZ		 89}
90
95c8bc36
AS		 91static inline void dwc2_writel(u32 value, void __iomem *addr)
92{
93 __raw_writel(value, addr);
94
95 /*
96 * In order to preserve endianness __raw_* operation is used. Therefore
97 * a barrier is needed to ensure IO access is not re-ordered across
98 * reads or writes
99 */
100 mb();
101#ifdef DWC2_LOG_WRITES
102 pr_info("INFO:: wrote %08x to %p\n", value, addr);
56f5b1cf 103#endif
95c8bc36 104}
23e34392
AB		 105#else
106/* Normal architectures just use readl/write */
107static inline u32 dwc2_readl(const void __iomem *addr)
108{
109 return readl(addr);
110}
111
112static inline void dwc2_writel(u32 value, void __iomem *addr)
113{
114 writel(value, addr);
115
116#ifdef DWC2_LOG_WRITES
117 pr_info("info:: wrote %08x to %p\n", value, addr);
118#endif
119}
120#endif
56f5b1cf
PZ		 121
122/* Maximum number of Endpoints/HostChannels */
123#define MAX_EPS_CHANNELS 16
124
1f91b4cc
FB		 125/* dwc2-hsotg declarations */
126static const char * const dwc2_hsotg_supply_names[] = {
f7c0b143
DN		 127 "vusb_d", /* digital USB supply, 1.2V */
128 "vusb_a", /* analog USB supply, 1.1V */
129};
130
b98866c2
JY		 131#define DWC2_NUM_SUPPLIES ARRAY_SIZE(dwc2_hsotg_supply_names)
132
f7c0b143
DN		 133/*
134 * EP0_MPS_LIMIT
135 *
136 * Unfortunately there seems to be a limit of the amount of data that can
137 * be transferred by IN transactions on EP0. This is either 127 bytes or 3
138 * packets (which practically means 1 packet and 63 bytes of data) when the
139 * MPS is set to 64.
140 *
141 * This means if we are wanting to move >127 bytes of data, we need to
142 * split the transactions up, but just doing one packet at a time does
143 * not work (this may be an implicit DATA0 PID on first packet of the
144 * transaction) and doing 2 packets is outside the controller's limits.
145 *
146 * If we try to lower the MPS size for EP0, then no transfers work properly
147 * for EP0, and the system will fail basic enumeration. As no cause for this
148 * has currently been found, we cannot support any large IN transfers for
149 * EP0.
150 */
151#define EP0_MPS_LIMIT 64
152
941fcce4 153struct dwc2_hsotg;
1f91b4cc 154struct dwc2_hsotg_req;
f7c0b143
DN		 155
156/**
1f91b4cc 157 * struct dwc2_hsotg_ep - driver endpoint definition.
f7c0b143
DN		 158 * @ep: The gadget layer representation of the endpoint.
159 * @name: The driver generated name for the endpoint.
160 * @queue: Queue of requests for this endpoint.
161 * @parent: Reference back to the parent device structure.
162 * @req: The current request that the endpoint is processing. This is
163 * used to indicate an request has been loaded onto the endpoint
164 * and has yet to be completed (maybe due to data move, or simply
165 * awaiting an ack from the core all the data has been completed).
166 * @debugfs: File entry for debugfs file for this endpoint.
167 * @lock: State lock to protect contents of endpoint.
168 * @dir_in: Set to true if this endpoint is of the IN direction, which
169 * means that it is sending data to the Host.
170 * @index: The index for the endpoint registers.
171 * @mc: Multi Count - number of transactions per microframe
142bd33f 172 * @interval - Interval for periodic endpoints, in frames or microframes.
f7c0b143
DN		 173 * @name: The name array passed to the USB core.
174 * @halted: Set if the endpoint has been halted.
175 * @periodic: Set if this is a periodic ep, such as Interrupt
176 * @isochronous: Set if this is a isochronous ep
8a20fa45 177 * @send_zlp: Set if we need to send a zero-length packet.
5f54c54b
VA		 178 * @desc_list_dma: The DMA address of descriptor chain currently in use.
179 * @desc_list: Pointer to descriptor DMA chain head currently in use.
180 * @desc_count: Count of entries within the DMA descriptor chain of EP.
ab7d2192
VA		 181 * @isoc_chain_num: Number of ISOC chain currently in use - either 0 or 1.
182 * @next_desc: index of next free descriptor in the ISOC chain under SW control.
f7c0b143
DN		 183 * @total_data: The total number of data bytes done.
184 * @fifo_size: The size of the FIFO (for periodic IN endpoints)
185 * @fifo_load: The amount of data loaded into the FIFO (periodic IN)
186 * @last_load: The offset of data for the last start of request.
187 * @size_loaded: The last loaded size for DxEPTSIZE for periodic IN
92d1635d
VM		 188 * @target_frame: Targeted frame num to setup next ISOC transfer
189 * @frame_overrun: Indicates SOF number overrun in DSTS
f7c0b143
DN		 190 *
191 * This is the driver's state for each registered enpoint, allowing it
192 * to keep track of transactions that need doing. Each endpoint has a
193 * lock to protect the state, to try and avoid using an overall lock
194 * for the host controller as much as possible.
195 *
196 * For periodic IN endpoints, we have fifo_size and fifo_load to try
197 * and keep track of the amount of data in the periodic FIFO for each
198 * of these as we don't have a status register that tells us how much
199 * is in each of them. (note, this may actually be useless information
200 * as in shared-fifo mode periodic in acts like a single-frame packet
201 * buffer than a fifo)
202 */
1f91b4cc 203struct dwc2_hsotg_ep {
f7c0b143
DN		 204 struct usb_ep ep;
205 struct list_head queue;
941fcce4 206 struct dwc2_hsotg *parent;
1f91b4cc 207 struct dwc2_hsotg_req *req;
f7c0b143
DN		 208 struct dentry *debugfs;
209
210 unsigned long total_data;
211 unsigned int size_loaded;
212 unsigned int last_load;
213 unsigned int fifo_load;
214 unsigned short fifo_size;
b203d0a2 215 unsigned short fifo_index;
f7c0b143
DN		 216
217 unsigned char dir_in;
218 unsigned char index;
219 unsigned char mc;
12814a3f 220 u16 interval;
f7c0b143
DN		 221
222 unsigned int halted:1;
223 unsigned int periodic:1;
224 unsigned int isochronous:1;
8a20fa45 225 unsigned int send_zlp:1;
92d1635d
VM		 226 unsigned int target_frame;
227#define TARGET_FRAME_INITIAL 0xFFFFFFFF
228 bool frame_overrun;
f7c0b143 229
5f54c54b
VA		 230 dma_addr_t desc_list_dma;
231 struct dwc2_dma_desc *desc_list;
232 u8 desc_count;
233
ab7d2192
VA		 234 unsigned char isoc_chain_num;
235 unsigned int next_desc;
236
f7c0b143
DN		 237 char name[10];
238};
239
f7c0b143 240/**
1f91b4cc 241 * struct dwc2_hsotg_req - data transfer request
f7c0b143
DN		 242 * @req: The USB gadget request
243 * @queue: The list of requests for the endpoint this is queued for.
7d24c1b5 244 * @saved_req_buf: variable to save req.buf when bounce buffers are used.
f7c0b143 245 */
1f91b4cc 246struct dwc2_hsotg_req {
f7c0b143
DN		 247 struct usb_request req;
248 struct list_head queue;
7d24c1b5 249 void *saved_req_buf;
f7c0b143
DN		 250};
251
b98866c2
JY		 252#if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \
253 IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
f7c0b143
DN		 254#define call_gadget(_hs, _entry) \
255do { \
256 if ((_hs)->gadget.speed != USB_SPEED_UNKNOWN && \
257 (_hs)->driver && (_hs)->driver->_entry) { \
258 spin_unlock(&_hs->lock); \
259 (_hs)->driver->_entry(&(_hs)->gadget); \
260 spin_lock(&_hs->lock); \
261 } \
262} while (0)
941fcce4
DN		 263#else
264#define call_gadget(_hs, _entry) do {} while (0)
265#endif
f7c0b143 266
56f5b1cf
PZ		 267struct dwc2_hsotg;
268struct dwc2_host_chan;
269
270/* Device States */
271enum dwc2_lx_state {
272 DWC2_L0, /* On state */
273 DWC2_L1, /* LPM sleep state */
274 DWC2_L2, /* USB suspend state */
275 DWC2_L3, /* Off state */
276};
277
fe0b94ab
MYK		 278/* Gadget ep0 states */
279enum dwc2_ep0_state {
280 DWC2_EP0_SETUP,
281 DWC2_EP0_DATA_IN,
282 DWC2_EP0_DATA_OUT,
283 DWC2_EP0_STATUS_IN,
284 DWC2_EP0_STATUS_OUT,
285};
286
56f5b1cf
PZ		 287/**
288 * struct dwc2_core_params - Parameters for configuring the core
289 *
91121c10
MK		 290 * @otg_cap: Specifies the OTG capabilities.
291 * 0 - HNP and SRP capable
56f5b1cf 292 * 1 - SRP Only capable
91121c10
MK		 293 * 2 - No HNP/SRP capable (always available)
294 * Defaults to best available option (0, 1, then 2)
e7839f99 295 * @host_dma: Specifies whether to use slave or DMA mode for accessing
56f5b1cf
PZ		 296 * the data FIFOs. The driver will automatically detect the
297 * value for this parameter if none is specified.
91121c10 298 * 0 - Slave (always available)
56f5b1cf
PZ		 299 * 1 - DMA (default, if available)
300 * @dma_desc_enable: When DMA mode is enabled, specifies whether to use
301 * address DMA mode or descriptor DMA mode for accessing
302 * the data FIFOs. The driver will automatically detect the
303 * value for this if none is specified.
304 * 0 - Address DMA
305 * 1 - Descriptor DMA (default, if available)
fbb9e22b
MYK		 306 * @dma_desc_fs_enable: When DMA mode is enabled, specifies whether to use
307 * address DMA mode or descriptor DMA mode for accessing
308 * the data FIFOs in Full Speed mode only. The driver
309 * will automatically detect the value for this if none is
310 * specified.
311 * 0 - Address DMA
312 * 1 - Descriptor DMA in FS (default, if available)
56f5b1cf
PZ		 313 * @speed: Specifies the maximum speed of operation in host and
314 * device mode. The actual speed depends on the speed of
315 * the attached device and the value of phy_type.
91121c10
MK		 316 * 0 - High Speed
317 * (default when phy_type is UTMI+ or ULPI)
56f5b1cf 318 * 1 - Full Speed
91121c10 319 * (default when phy_type is Full Speed)
56f5b1cf 320 * @enable_dynamic_fifo: 0 - Use coreConsultant-specified FIFO size parameters
91121c10 321 * 1 - Allow dynamic FIFO sizing (default, if available)
725acc86 322 * @en_multiple_tx_fifo: Specifies whether dedicated per-endpoint transmit FIFOs
c1d286cf
JY		 323 * are enabled for non-periodic IN endpoints in device
324 * mode.
56f5b1cf
PZ		 325 * @host_rx_fifo_size: Number of 4-byte words in the Rx FIFO in host mode when
326 * dynamic FIFO sizing is enabled
91121c10
MK		 327 * 16 to 32768
328 * Actual maximum value is autodetected and also
329 * the default.
56f5b1cf
PZ		 330 * @host_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO
331 * in host mode when dynamic FIFO sizing is enabled
91121c10
MK		 332 * 16 to 32768
333 * Actual maximum value is autodetected and also
334 * the default.
56f5b1cf
PZ		 335 * @host_perio_tx_fifo_size: Number of 4-byte words in the periodic Tx FIFO in
336 * host mode when dynamic FIFO sizing is enabled
91121c10
MK		 337 * 16 to 32768
338 * Actual maximum value is autodetected and also
339 * the default.
56f5b1cf 340 * @max_transfer_size: The maximum transfer size supported, in bytes
91121c10
MK		 341 * 2047 to 65,535
342 * Actual maximum value is autodetected and also
343 * the default.
56f5b1cf 344 * @max_packet_count: The maximum number of packets in a transfer
91121c10
MK		 345 * 15 to 511
346 * Actual maximum value is autodetected and also
347 * the default.
56f5b1cf 348 * @host_channels: The number of host channel registers to use
91121c10
MK		 349 * 1 to 16
350 * Actual maximum value is autodetected and also
351 * the default.
56f5b1cf
PZ		 352 * @phy_type: Specifies the type of PHY interface to use. By default,
353 * the driver will automatically detect the phy_type.
91121c10
MK		 354 * 0 - Full Speed Phy
355 * 1 - UTMI+ Phy
356 * 2 - ULPI Phy
357 * Defaults to best available option (2, 1, then 0)
56f5b1cf
PZ		 358 * @phy_utmi_width: Specifies the UTMI+ Data Width (in bits). This parameter
359 * is applicable for a phy_type of UTMI+ or ULPI. (For a
360 * ULPI phy_type, this parameter indicates the data width
361 * between the MAC and the ULPI Wrapper.) Also, this
362 * parameter is applicable only if the OTG_HSPHY_WIDTH cC
363 * parameter was set to "8 and 16 bits", meaning that the
364 * core has been configured to work at either data path
365 * width.
91121c10 366 * 8 or 16 (default 16 if available)
56f5b1cf
PZ		 367 * @phy_ulpi_ddr: Specifies whether the ULPI operates at double or single
368 * data rate. This parameter is only applicable if phy_type
369 * is ULPI.
370 * 0 - single data rate ULPI interface with 8 bit wide
371 * data bus (default)
372 * 1 - double data rate ULPI interface with 4 bit wide
373 * data bus
374 * @phy_ulpi_ext_vbus: For a ULPI phy, specifies whether to use the internal or
375 * external supply to drive the VBus
91121c10
MK		 376 * 0 - Internal supply (default)
377 * 1 - External supply
56f5b1cf
PZ		 378 * @i2c_enable: Specifies whether to use the I2Cinterface for a full
379 * speed PHY. This parameter is only applicable if phy_type
380 * is FS.
381 * 0 - No (default)
382 * 1 - Yes
91121c10
MK		 383 * @ulpi_fs_ls: Make ULPI phy operate in FS/LS mode only
384 * 0 - No (default)
385 * 1 - Yes
725acc86
PZ		 386 * @host_support_fs_ls_low_power: Specifies whether low power mode is supported
387 * when attached to a Full Speed or Low Speed device in
388 * host mode.
389 * 0 - Don't support low power mode (default)
390 * 1 - Support low power mode
391 * @host_ls_low_power_phy_clk: Specifies the PHY clock rate in low power mode
91121c10
MK		 392 * when connected to a Low Speed device in host
393 * mode. This parameter is applicable only if
394 * host_support_fs_ls_low_power is enabled.
725acc86 395 * 0 - 48 MHz
91121c10 396 * (default when phy_type is UTMI+ or ULPI)
725acc86 397 * 1 - 6 MHz
91121c10 398 * (default when phy_type is Full Speed)
b11633c4
DN		 399 * @oc_disable: Flag to disable overcurrent condition.
400 * 0 - Allow overcurrent condition to get detected
401 * 1 - Disable overcurrent condtion to get detected
91121c10
MK		 402 * @ts_dline: Enable Term Select Dline pulsing
403 * 0 - No (default)
404 * 1 - Yes
405 * @reload_ctl: Allow dynamic reloading of HFIR register during runtime
406 * 0 - No (default for core < 2.92a)
407 * 1 - Yes (default for core >= 2.92a)
4d3190e1
PZ		 408 * @ahbcfg: This field allows the default value of the GAHBCFG
409 * register to be overridden
91121c10 410 * -1 - GAHBCFG value will be set to 0x06
1b52d2fa 411 * (INCR, default)
4d3190e1
PZ		 412 * all others - GAHBCFG value will be overridden with
413 * this value
91121c10
MK		 414 * Not all bits can be controlled like this, the
415 * bits defined by GAHBCFG_CTRL_MASK are controlled
416 * by the driver and are ignored in this
417 * configuration value.
20f2eb9c 418 * @uframe_sched: True to enable the microframe scheduler
a6d249d8
GH		 419 * @external_id_pin_ctl: Specifies whether ID pin is handled externally.
420 * Disable CONIDSTSCHNG controller interrupt in such
421 * case.
422 * 0 - No (default)
423 * 1 - Yes
285046aa
GH		 424 * @hibernation: Specifies whether the controller support hibernation.
425 * If hibernation is enabled, the controller will enter
426 * hibernation in both peripheral and host mode when
427 * needed.
428 * 0 - No (default)
429 * 1 - Yes
6f80b6de
SA		 430 * @lpm: Enable LPM support.
431 * 0 - No
432 * 1 - Yes
433 * @lpm_clock_gating: Enable core PHY clock gating.
434 * 0 - No
435 * 1 - Yes
436 * @besl: Enable LPM Errata support.
437 * 0 - No
438 * 1 - Yes
439 * @hird_threshold_en: HIRD or HIRD Threshold enable.
440 * 0 - No
441 * 1 - Yes
442 * @hird_threshold: Value of BESL or HIRD Threshold.
e35b1350
BH		 443 * @activate_stm_fs_transceiver: Activate internal transceiver using GGPIO
444 * register.
445 * 0 - Deactivate the transceiver (default)
446 * 1 - Activate the transceiver
9962b62f 447 * @g_dma: Enables gadget dma usage (default: autodetect).
dec4b556 448 * @g_dma_desc: Enables gadget descriptor DMA (default: autodetect).
05ee799f
JY		 449 * @g_rx_fifo_size: The periodic rx fifo size for the device, in
450 * DWORDS from 16-32768 (default: 2048 if
451 * possible, otherwise autodetect).
452 * @g_np_tx_fifo_size: The non-periodic tx fifo size for the device in
453 * DWORDS from 16-32768 (default: 1024 if
454 * possible, otherwise autodetect).
455 * @g_tx_fifo_size: An array of TX fifo sizes in dedicated fifo
456 * mode. Each value corresponds to one EP
457 * starting from EP1 (max 15 values). Sizes are
458 * in DWORDS with possible values from from
459 * 16-32768 (default: 256, 256, 256, 256, 768,
460 * 768, 768, 768, 0, 0, 0, 0, 0, 0, 0).
ca8b0332
CY		 461 * @change_speed_quirk: Change speed configuration to DWC2_SPEED_PARAM_FULL
462 * while full&low speed device connect. And change speed
463 * back to DWC2_SPEED_PARAM_HIGH while device is gone.
464 * 0 - No (default)
465 * 1 - Yes
56f5b1cf
PZ		 466 *
467 * The following parameters may be specified when starting the module. These
91121c10
MK		 468 * parameters define how the DWC_otg controller should be configured. A
469 * value of -1 (or any other out of range value) for any parameter means
470 * to read the value from hardware (if possible) or use the builtin
471 * default described above.
56f5b1cf
PZ		 472 */
473struct dwc2_core_params {
d21bcc3f 474 u8 otg_cap;
c1d286cf
JY		 475#define DWC2_CAP_PARAM_HNP_SRP_CAPABLE 0
476#define DWC2_CAP_PARAM_SRP_ONLY_CAPABLE 1
477#define DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE 2
478
d21bcc3f 479 u8 phy_type;
c1d286cf
JY		 480#define DWC2_PHY_TYPE_PARAM_FS 0
481#define DWC2_PHY_TYPE_PARAM_UTMI 1
482#define DWC2_PHY_TYPE_PARAM_ULPI 2
483
57b8e235
JY		 484 u8 speed;
485#define DWC2_SPEED_PARAM_HIGH 0
486#define DWC2_SPEED_PARAM_FULL 1
487#define DWC2_SPEED_PARAM_LOW 2
488
d21bcc3f
JY		 489 u8 phy_utmi_width;
490 bool phy_ulpi_ddr;
491 bool phy_ulpi_ext_vbus;
57b8e235
JY		 492 bool enable_dynamic_fifo;
493 bool en_multiple_tx_fifo;
d21bcc3f 494 bool i2c_enable;
66e77a24 495 bool acg_enable;
d21bcc3f 496 bool ulpi_fs_ls;
d21bcc3f
JY		 497 bool ts_dline;
498 bool reload_ctl;
d21bcc3f
JY		 499 bool uframe_sched;
500 bool external_id_pin_ctl;
501 bool hibernation;
6f80b6de
SA		 502 bool lpm;
503 bool lpm_clock_gating;
504 bool besl;
505 bool hird_threshold_en;
506 u8 hird_threshold;
e35b1350 507 bool activate_stm_fs_transceiver;
57b8e235
JY		 508 u16 max_packet_count;
509 u32 max_transfer_size;
510 u32 ahbcfg;
6b66ce51
JY		 511
512 /* Host parameters */
513 bool host_dma;
57b8e235
JY		 514 bool dma_desc_enable;
515 bool dma_desc_fs_enable;
516 bool host_support_fs_ls_low_power;
517 bool host_ls_low_power_phy_clk;
b11633c4 518 bool oc_disable;
57b8e235
JY		 519
520 u8 host_channels;
521 u16 host_rx_fifo_size;
522 u16 host_nperio_tx_fifo_size;
523 u16 host_perio_tx_fifo_size;
6b66ce51
JY		 524
525 /* Gadget parameters */
05ee799f 526 bool g_dma;
dec4b556 527 bool g_dma_desc;
00c704cc
LY		 528 u32 g_rx_fifo_size;
529 u32 g_np_tx_fifo_size;
05ee799f 530 u32 g_tx_fifo_size[MAX_EPS_CHANNELS];
ca8b0332
CY		 531
532 bool change_speed_quirk;
56f5b1cf
PZ		 533};
534
9badec2f
MK		 535/**
536 * struct dwc2_hw_params - Autodetected parameters.
537 *
538 * These parameters are the various parameters read from hardware
539 * registers during initialization. They typically contain the best
540 * supported or maximum value that can be configured in the
541 * corresponding dwc2_core_params value.
542 *
543 * The values that are not in dwc2_core_params are documented below.
544 *
545 * @op_mode Mode of Operation
546 * 0 - HNP- and SRP-Capable OTG (Host & Device)
547 * 1 - SRP-Capable OTG (Host & Device)
548 * 2 - Non-HNP and Non-SRP Capable OTG (Host & Device)
549 * 3 - SRP-Capable Device
550 * 4 - Non-OTG Device
551 * 5 - SRP-Capable Host
552 * 6 - Non-OTG Host
553 * @arch Architecture
554 * 0 - Slave only
555 * 1 - External DMA
556 * 2 - Internal DMA
557 * @power_optimized Are power optimizations enabled?
558 * @num_dev_ep Number of device endpoints available
9273083a 559 * @num_dev_in_eps Number of device IN endpoints available
9badec2f 560 * @num_dev_perio_in_ep Number of device periodic IN endpoints
997f4f81 561 * available
9badec2f
MK		 562 * @dev_token_q_depth Device Mode IN Token Sequence Learning Queue
563 * Depth
564 * 0 to 30
565 * @host_perio_tx_q_depth
566 * Host Mode Periodic Request Queue Depth
567 * 2, 4 or 8
568 * @nperio_tx_q_depth
569 * Non-Periodic Request Queue Depth
570 * 2, 4 or 8
571 * @hs_phy_type High-speed PHY interface type
572 * 0 - High-speed interface not supported
573 * 1 - UTMI+
574 * 2 - ULPI
575 * 3 - UTMI+ and ULPI
576 * @fs_phy_type Full-speed PHY interface type
577 * 0 - Full speed interface not supported
578 * 1 - Dedicated full speed interface
579 * 2 - FS pins shared with UTMI+ pins
580 * 3 - FS pins shared with ULPI pins
581 * @total_fifo_size: Total internal RAM for FIFOs (bytes)
de4a1931
MK		 582 * @utmi_phy_data_width UTMI+ PHY data width
583 * 0 - 8 bits
584 * 1 - 16 bits
585 * 2 - 8 or 16 bits
9badec2f 586 * @snpsid: Value from SNPSID register
55e1040e 587 * @dev_ep_dirs: Direction of device endpoints (GHWCFG1)
9273083a 588 * @g_tx_fifo_size[] Power-on values of TxFIFO sizes
9badec2f
MK		 589 */
590struct dwc2_hw_params {
591 unsigned op_mode:3;
592 unsigned arch:2;
593 unsigned dma_desc_enable:1;
594 unsigned enable_dynamic_fifo:1;
595 unsigned en_multiple_tx_fifo:1;
d1531319 596 unsigned rx_fifo_size:16;
9badec2f 597 unsigned host_nperio_tx_fifo_size:16;
55e1040e 598 unsigned dev_nperio_tx_fifo_size:16;
9badec2f
MK		 599 unsigned host_perio_tx_fifo_size:16;
600 unsigned nperio_tx_q_depth:3;
601 unsigned host_perio_tx_q_depth:3;
602 unsigned dev_token_q_depth:5;
603 unsigned max_transfer_size:26;
604 unsigned max_packet_count:11;
2d115547 605 unsigned host_channels:5;
9badec2f
MK		 606 unsigned hs_phy_type:2;
607 unsigned fs_phy_type:2;
608 unsigned i2c_enable:1;
66e77a24 609 unsigned acg_enable:1;
9badec2f 610 unsigned num_dev_ep:4;
9273083a 611 unsigned num_dev_in_eps : 4;
9badec2f
MK		 612 unsigned num_dev_perio_in_ep:4;
613 unsigned total_fifo_size:16;
614 unsigned power_optimized:1;
de4a1931 615 unsigned utmi_phy_data_width:2;
6f80b6de 616 unsigned lpm_mode:1;
9badec2f 617 u32 snpsid;
55e1040e 618 u32 dev_ep_dirs;
9273083a 619 u32 g_tx_fifo_size[MAX_EPS_CHANNELS];
9badec2f
MK		 620};
621
3f95001d
MYK		 622/* Size of control and EP0 buffers */
623#define DWC2_CTRL_BUFF_SIZE 8
624
d17ee77b 625/**
38beaec6
JY		 626 * struct dwc2_gregs_backup - Holds global registers state before
627 * entering partial power down
d17ee77b
GH		 628 * @gotgctl: Backup of GOTGCTL register
629 * @gintmsk: Backup of GINTMSK register
630 * @gahbcfg: Backup of GAHBCFG register
631 * @gusbcfg: Backup of GUSBCFG register
632 * @grxfsiz: Backup of GRXFSIZ register
633 * @gnptxfsiz: Backup of GNPTXFSIZ register
634 * @gi2cctl: Backup of GI2CCTL register
635 * @hptxfsiz: Backup of HPTXFSIZ register
636 * @gdfifocfg: Backup of GDFIFOCFG register
637 * @dtxfsiz: Backup of DTXFSIZ registers for each endpoint
638 * @gpwrdn: Backup of GPWRDN register
639 */
640struct dwc2_gregs_backup {
641 u32 gotgctl;
642 u32 gintmsk;
643 u32 gahbcfg;
644 u32 gusbcfg;
645 u32 grxfsiz;
646 u32 gnptxfsiz;
647 u32 gi2cctl;
648 u32 hptxfsiz;
649 u32 pcgcctl;
600a490e 650 u32 pcgcctl1;
d17ee77b
GH		 651 u32 gdfifocfg;
652 u32 dtxfsiz[MAX_EPS_CHANNELS];
653 u32 gpwrdn;
cc1e204c 654 bool valid;
d17ee77b
GH		 655};
656
657/**
38beaec6
JY		 658 * struct dwc2_dregs_backup - Holds device registers state before
659 * entering partial power down
d17ee77b
GH		 660 * @dcfg: Backup of DCFG register
661 * @dctl: Backup of DCTL register
662 * @daintmsk: Backup of DAINTMSK register
663 * @diepmsk: Backup of DIEPMSK register
664 * @doepmsk: Backup of DOEPMSK register
665 * @diepctl: Backup of DIEPCTL register
666 * @dieptsiz: Backup of DIEPTSIZ register
667 * @diepdma: Backup of DIEPDMA register
668 * @doepctl: Backup of DOEPCTL register
669 * @doeptsiz: Backup of DOEPTSIZ register
670 * @doepdma: Backup of DOEPDMA register
671 */
672struct dwc2_dregs_backup {
673 u32 dcfg;
674 u32 dctl;
675 u32 daintmsk;
676 u32 diepmsk;
677 u32 doepmsk;
678 u32 diepctl[MAX_EPS_CHANNELS];
679 u32 dieptsiz[MAX_EPS_CHANNELS];
680 u32 diepdma[MAX_EPS_CHANNELS];
681 u32 doepctl[MAX_EPS_CHANNELS];
682 u32 doeptsiz[MAX_EPS_CHANNELS];
683 u32 doepdma[MAX_EPS_CHANNELS];
cc1e204c 684 bool valid;
d17ee77b
GH		 685};
686
687/**
38beaec6
JY		 688 * struct dwc2_hregs_backup - Holds host registers state before
689 * entering partial power down
d17ee77b
GH		 690 * @hcfg: Backup of HCFG register
691 * @haintmsk: Backup of HAINTMSK register
692 * @hcintmsk: Backup of HCINTMSK register
693 * @hptr0: Backup of HPTR0 register
694 * @hfir: Backup of HFIR register
695 */
696struct dwc2_hregs_backup {
697 u32 hcfg;
698 u32 haintmsk;
699 u32 hcintmsk[MAX_EPS_CHANNELS];
700 u32 hprt0;
701 u32 hfir;
cc1e204c 702 bool valid;
d17ee77b
GH		 703};
704
9f9f09b0
DA		 705/*
706 * Constants related to high speed periodic scheduling
707 *
708 * We have a periodic schedule that is DWC2_HS_SCHEDULE_UFRAMES long. From a
709 * reservation point of view it's assumed that the schedule goes right back to
710 * the beginning after the end of the schedule.
711 *
712 * What does that mean for scheduling things with a long interval? It means
713 * we'll reserve time for them in every possible microframe that they could
714 * ever be scheduled in. ...but we'll still only actually schedule them as
715 * often as they were requested.
716 *
717 * We keep our schedule in a "bitmap" structure. This simplifies having
718 * to keep track of and merge intervals: we just let the bitmap code do most
719 * of the heavy lifting. In a way scheduling is much like memory allocation.
720 *
721 * We schedule 100us per uframe or 80% of 125us (the maximum amount you're
722 * supposed to schedule for periodic transfers). That's according to spec.
723 *
724 * Note that though we only schedule 80% of each microframe, the bitmap that we
725 * keep the schedule in is tightly packed (AKA it doesn't have 100us worth of
726 * space for each uFrame).
727 *
728 * Requirements:
729 * - DWC2_HS_SCHEDULE_UFRAMES must even divide 0x4000 (HFNUM_MAX_FRNUM + 1)
730 * - DWC2_HS_SCHEDULE_UFRAMES must be 8 times DWC2_LS_SCHEDULE_FRAMES (probably
731 * could be any multiple of 8 times DWC2_LS_SCHEDULE_FRAMES, but there might
732 * be bugs). The 8 comes from the USB spec: number of microframes per frame.
733 */
734#define DWC2_US_PER_UFRAME 125
735#define DWC2_HS_PERIODIC_US_PER_UFRAME 100
736
737#define DWC2_HS_SCHEDULE_UFRAMES 8
738#define DWC2_HS_SCHEDULE_US (DWC2_HS_SCHEDULE_UFRAMES * \
739 DWC2_HS_PERIODIC_US_PER_UFRAME)
740
741/*
742 * Constants related to low speed scheduling
743 *
744 * For high speed we schedule every 1us. For low speed that's a bit overkill,
745 * so we make up a unit called a "slice" that's worth 25us. There are 40
746 * slices in a full frame and we can schedule 36 of those (90%) for periodic
747 * transfers.
748 *
749 * Our low speed schedule can be as short as 1 frame or could be longer. When
750 * we only schedule 1 frame it means that we'll need to reserve a time every
751 * frame even for things that only transfer very rarely, so something that runs
752 * every 2048 frames will get time reserved in every frame. Our low speed
753 * schedule can be longer and we'll be able to handle more overlap, but that
754 * will come at increased memory cost and increased time to schedule.
755 *
756 * Note: one other advantage of a short low speed schedule is that if we mess
757 * up and miss scheduling we can jump in and use any of the slots that we
758 * happened to reserve.
759 *
760 * With 25 us per slice and 1 frame in the schedule, we only need 4 bytes for
761 * the schedule. There will be one schedule per TT.
762 *
763 * Requirements:
764 * - DWC2_US_PER_SLICE must evenly divide DWC2_LS_PERIODIC_US_PER_FRAME.
765 */
766#define DWC2_US_PER_SLICE 25
767#define DWC2_SLICES_PER_UFRAME (DWC2_US_PER_UFRAME / DWC2_US_PER_SLICE)
768
769#define DWC2_ROUND_US_TO_SLICE(us) \
770 (DIV_ROUND_UP((us), DWC2_US_PER_SLICE) * \
771 DWC2_US_PER_SLICE)
772
773#define DWC2_LS_PERIODIC_US_PER_FRAME \
774 900
775#define DWC2_LS_PERIODIC_SLICES_PER_FRAME \
776 (DWC2_LS_PERIODIC_US_PER_FRAME / \
777 DWC2_US_PER_SLICE)
778
779#define DWC2_LS_SCHEDULE_FRAMES 1
780#define DWC2_LS_SCHEDULE_SLICES (DWC2_LS_SCHEDULE_FRAMES * \
781 DWC2_LS_PERIODIC_SLICES_PER_FRAME)
782
56f5b1cf
PZ		 783/**
784 * struct dwc2_hsotg - Holds the state of the driver, including the non-periodic
785 * and periodic schedules
786 *
941fcce4
DN		 787 * These are common for both host and peripheral modes:
788 *
56f5b1cf
PZ		 789 * @dev: The struct device pointer
790 * @regs: Pointer to controller regs
9badec2f
MK		 791 * @hw_params: Parameters that were autodetected from the
792 * hardware registers
941fcce4 793 * @core_params: Parameters that define how the core should be configured
56f5b1cf
PZ		 794 * @op_state: The operational State, during transitions (a_host=>
795 * a_peripheral and b_device=>b_host) this may not match
796 * the core, but allows the software to determine
797 * transitions
c0155b9d
KY		 798 * @dr_mode: Requested mode of operation, one of following:
799 * - USB_DR_MODE_PERIPHERAL
800 * - USB_DR_MODE_HOST
801 * - USB_DR_MODE_OTG
09a75e85
MS		 802 * @hcd_enabled Host mode sub-driver initialization indicator.
803 * @gadget_enabled Peripheral mode sub-driver initialization indicator.
804 * @ll_hw_enabled Status of low-level hardware resources.
805 * @phy: The otg phy transceiver structure for phy control.
38beaec6
JY		 806 * @uphy: The otg phy transceiver structure for old USB phy
807 * control.
808 * @plat: The platform specific configuration data. This can be
809 * removed once all SoCs support usb transceiver.
09a75e85
MS		 810 * @supplies: Definition of USB power supplies
811 * @phyif: PHY interface width
941fcce4
DN		 812 * @lock: Spinlock that protects all the driver data structures
813 * @priv: Stores a pointer to the struct usb_hcd
56f5b1cf
PZ		 814 * @queuing_high_bandwidth: True if multiple packets of a high-bandwidth
815 * transfer are in process of being queued
816 * @srp_success: Stores status of SRP request in the case of a FS PHY
817 * with an I2C interface
818 * @wq_otg: Workqueue object used for handling of some interrupts
819 * @wf_otg: Work object for handling Connector ID Status Change
820 * interrupt
821 * @wkp_timer: Timer object for handling Wakeup Detected interrupt
822 * @lx_state: Lx state of connected device
d17ee77b
GH		 823 * @gregs_backup: Backup of global registers during suspend
824 * @dregs_backup: Backup of device registers during suspend
825 * @hregs_backup: Backup of host registers during suspend
941fcce4
DN		 826 *
827 * These are for host mode:
828 *
56f5b1cf
PZ		 829 * @flags: Flags for handling root port state changes
830 * @non_periodic_sched_inactive: Inactive QHs in the non-periodic schedule.
831 * Transfers associated with these QHs are not currently
832 * assigned to a host channel.
833 * @non_periodic_sched_active: Active QHs in the non-periodic schedule.
834 * Transfers associated with these QHs are currently
835 * assigned to a host channel.
836 * @non_periodic_qh_ptr: Pointer to next QH to process in the active
837 * non-periodic schedule
838 * @periodic_sched_inactive: Inactive QHs in the periodic schedule. This is a
839 * list of QHs for periodic transfers that are _not_
840 * scheduled for the next frame. Each QH in the list has an
841 * interval counter that determines when it needs to be
842 * scheduled for execution. This scheduling mechanism
843 * allows only a simple calculation for periodic bandwidth
844 * used (i.e. must assume that all periodic transfers may
845 * need to execute in the same frame). However, it greatly
846 * simplifies scheduling and should be sufficient for the
847 * vast majority of OTG hosts, which need to connect to a
848 * small number of peripherals at one time. Items move from
849 * this list to periodic_sched_ready when the QH interval
850 * counter is 0 at SOF.
851 * @periodic_sched_ready: List of periodic QHs that are ready for execution in
852 * the next frame, but have not yet been assigned to host
853 * channels. Items move from this list to
854 * periodic_sched_assigned as host channels become
855 * available during the current frame.
856 * @periodic_sched_assigned: List of periodic QHs to be executed in the next
857 * frame that are assigned to host channels. Items move
858 * from this list to periodic_sched_queued as the
859 * transactions for the QH are queued to the DWC_otg
860 * controller.
861 * @periodic_sched_queued: List of periodic QHs that have been queued for
862 * execution. Items move from this list to either
863 * periodic_sched_inactive or periodic_sched_ready when the
864 * channel associated with the transfer is released. If the
865 * interval for the QH is 1, the item moves to
866 * periodic_sched_ready because it must be rescheduled for
867 * the next frame. Otherwise, the item moves to
868 * periodic_sched_inactive.
c9c8ac01 869 * @split_order: List keeping track of channels doing splits, in order.
56f5b1cf
PZ		 870 * @periodic_usecs: Total bandwidth claimed so far for periodic transfers.
871 * This value is in microseconds per (micro)frame. The
872 * assumption is that all periodic transfers may occur in
873 * the same (micro)frame.
9f9f09b0
DA		 874 * @hs_periodic_bitmap: Bitmap used by the microframe scheduler any time the
875 * host is in high speed mode; low speed schedules are
876 * stored elsewhere since we need one per TT.
56f5b1cf
PZ		 877 * @frame_number: Frame number read from the core at SOF. The value ranges
878 * from 0 to HFNUM_MAX_FRNUM.
879 * @periodic_qh_count: Count of periodic QHs, if using several eps. Used for
880 * SOF enable/disable.
881 * @free_hc_list: Free host channels in the controller. This is a list of
882 * struct dwc2_host_chan items.
883 * @periodic_channels: Number of host channels assigned to periodic transfers.
884 * Currently assuming that there is a dedicated host
885 * channel for each periodic transaction and at least one
886 * host channel is available for non-periodic transactions.
887 * @non_periodic_channels: Number of host channels assigned to non-periodic
888 * transfers
20f2eb9c
DC		 889 * @available_host_channels Number of host channels available for the microframe
890 * scheduler to use
56f5b1cf
PZ		 891 * @hc_ptr_array: Array of pointers to the host channel descriptors.
892 * Allows accessing a host channel descriptor given the
893 * host channel number. This is useful in interrupt
894 * handlers.
895 * @status_buf: Buffer used for data received during the status phase of
896 * a control transfer.
897 * @status_buf_dma: DMA address for status_buf
898 * @start_work: Delayed work for handling host A-cable connection
899 * @reset_work: Delayed work for handling a port reset
56f5b1cf
PZ		 900 * @otg_port: OTG port number
901 * @frame_list: Frame list
902 * @frame_list_dma: Frame list DMA address
95105a99 903 * @frame_list_sz: Frame list size
3b5fcc9a
GH		 904 * @desc_gen_cache: Kmem cache for generic descriptors
905 * @desc_hsisoc_cache: Kmem cache for hs isochronous descriptors
941fcce4
DN		 906 *
907 * These are for peripheral mode:
908 *
909 * @driver: USB gadget driver
941fcce4
DN		 910 * @dedicated_fifos: Set if the hardware has dedicated IN-EP fifos.
911 * @num_of_eps: Number of available EPs (excluding EP0)
912 * @debug_root: Root directrory for debugfs.
913 * @debug_file: Main status file for debugfs.
9e14d0a5 914 * @debug_testmode: Testmode status file for debugfs.
941fcce4
DN		 915 * @debug_fifo: FIFO status file for debugfs.
916 * @ep0_reply: Request used for ep0 reply.
917 * @ep0_buff: Buffer for EP0 reply data, if needed.
918 * @ctrl_buff: Buffer for EP0 control requests.
919 * @ctrl_req: Request for EP0 control packets.
fe0b94ab 920 * @ep0_state: EP0 control transfers state
9e14d0a5 921 * @test_mode: USB test mode requested by the host
0f6b80c0
VA		 922 * @setup_desc_dma: EP0 setup stage desc chain DMA address
923 * @setup_desc: EP0 setup stage desc chain pointer
924 * @ctrl_in_desc_dma: EP0 IN data phase desc chain DMA address
925 * @ctrl_in_desc: EP0 IN data phase desc chain pointer
926 * @ctrl_out_desc_dma: EP0 OUT data phase desc chain DMA address
927 * @ctrl_out_desc: EP0 OUT data phase desc chain pointer
941fcce4 928 * @eps: The endpoints being supplied to the gadget framework
56f5b1cf
PZ		 929 */
930struct dwc2_hsotg {
931 struct device *dev;
932 void __iomem *regs;
9badec2f
MK		 933 /** Params detected from hardware */
934 struct dwc2_hw_params hw_params;
935 /** Params to actually use */
bea8e86c 936 struct dwc2_core_params params;
56f5b1cf 937 enum usb_otg_state op_state;
c0155b9d 938 enum usb_dr_mode dr_mode;
e39af88f
MS		 939 unsigned int hcd_enabled:1;
940 unsigned int gadget_enabled:1;
09a75e85 941 unsigned int ll_hw_enabled:1;
56f5b1cf 942
941fcce4
DN		 943 struct phy *phy;
944 struct usb_phy *uphy;
09a75e85 945 struct dwc2_hsotg_plat *plat;
b98866c2 946 struct regulator_bulk_data supplies[DWC2_NUM_SUPPLIES];
09a75e85 947 u32 phyif;
941fcce4
DN		 948
949 spinlock_t lock;
950 void *priv;
951 int irq;
952 struct clk *clk;
83f8da56 953 struct reset_control *reset;
f2830ad4 954 struct reset_control *reset_ecc;
941fcce4 955
56f5b1cf
PZ		 956 unsigned int queuing_high_bandwidth:1;
957 unsigned int srp_success:1;
958
959 struct workqueue_struct *wq_otg;
960 struct work_struct wf_otg;
961 struct timer_list wkp_timer;
962 enum dwc2_lx_state lx_state;
cc1e204c
MYK		 963 struct dwc2_gregs_backup gr_backup;
964 struct dwc2_dregs_backup dr_backup;
965 struct dwc2_hregs_backup hr_backup;
56f5b1cf 966
941fcce4 967 struct dentry *debug_root;
563cf017 968 struct debugfs_regset32 *regset;
941fcce4
DN		 969
970 /* DWC OTG HW Release versions */
971#define DWC2_CORE_REV_2_71a 0x4f54271a
6f80b6de 972#define DWC2_CORE_REV_2_80a 0x4f54280a
941fcce4 973#define DWC2_CORE_REV_2_90a 0x4f54290a
e1f411d1 974#define DWC2_CORE_REV_2_91a 0x4f54291a
941fcce4
DN		 975#define DWC2_CORE_REV_2_92a 0x4f54292a
976#define DWC2_CORE_REV_2_94a 0x4f54294a
977#define DWC2_CORE_REV_3_00a 0x4f54300a
fef6bc37 978#define DWC2_CORE_REV_3_10a 0x4f54310a
1e6b98eb
VM		 979#define DWC2_FS_IOT_REV_1_00a 0x5531100a
980#define DWC2_HS_IOT_REV_1_00a 0x5532100a
941fcce4 981
d14ccaba
GS		 982 /* DWC OTG HW Core ID */
983#define DWC2_OTG_ID 0x4f540000
984#define DWC2_FS_IOT_ID 0x55310000
985#define DWC2_HS_IOT_ID 0x55320000
986
941fcce4 987#if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
56f5b1cf
PZ		 988 union dwc2_hcd_internal_flags {
989 u32 d32;
990 struct {
991 unsigned port_connect_status_change:1;
992 unsigned port_connect_status:1;
993 unsigned port_reset_change:1;
994 unsigned port_enable_change:1;
995 unsigned port_suspend_change:1;
996 unsigned port_over_current_change:1;
997 unsigned port_l1_change:1;
fd4850cf 998 unsigned reserved:25;
56f5b1cf
PZ		 999 } b;
1000 } flags;
1001
1002 struct list_head non_periodic_sched_inactive;
38d2b5fb 1003 struct list_head non_periodic_sched_waiting;
56f5b1cf
PZ		 1004 struct list_head non_periodic_sched_active;
1005 struct list_head *non_periodic_qh_ptr;
1006 struct list_head periodic_sched_inactive;
1007 struct list_head periodic_sched_ready;
1008 struct list_head periodic_sched_assigned;
1009 struct list_head periodic_sched_queued;
c9c8ac01 1010 struct list_head split_order;
56f5b1cf 1011 u16 periodic_usecs;
9f9f09b0
DA		 1012 unsigned long hs_periodic_bitmap[
1013 DIV_ROUND_UP(DWC2_HS_SCHEDULE_US, BITS_PER_LONG)];
56f5b1cf
PZ		 1014 u16 frame_number;
1015 u16 periodic_qh_count;
734643df 1016 bool bus_suspended;
fbb9e22b 1017 bool new_connection;
56f5b1cf 1018
483bb254
DA		 1019 u16 last_frame_num;
1020
56f5b1cf
PZ		 1021#ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
1022#define FRAME_NUM_ARRAY_SIZE 1000
56f5b1cf
PZ		 1023 u16 *frame_num_array;
1024 u16 *last_frame_num_array;
1025 int frame_num_idx;
1026 int dumped_frame_num_array;
1027#endif
1028
1029 struct list_head free_hc_list;
1030 int periodic_channels;
1031 int non_periodic_channels;
20f2eb9c 1032 int available_host_channels;
56f5b1cf
PZ		 1033 struct dwc2_host_chan *hc_ptr_array[MAX_EPS_CHANNELS];
1034 u8 *status_buf;
1035 dma_addr_t status_buf_dma;
1036#define DWC2_HCD_STATUS_BUF_SIZE 64
1037
1038 struct delayed_work start_work;
1039 struct delayed_work reset_work;
56f5b1cf
PZ		 1040 u8 otg_port;
1041 u32 *frame_list;
1042 dma_addr_t frame_list_dma;
95105a99 1043 u32 frame_list_sz;
3b5fcc9a
GH		 1044 struct kmem_cache *desc_gen_cache;
1045 struct kmem_cache *desc_hsisoc_cache;
56f5b1cf 1046
941fcce4
DN		 1047#endif /* CONFIG_USB_DWC2_HOST || CONFIG_USB_DWC2_DUAL_ROLE */
1048
b98866c2
JY		 1049#if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \
1050 IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
941fcce4
DN		 1051 /* Gadget structures */
1052 struct usb_gadget_driver *driver;
941fcce4
DN		 1053 int fifo_mem;
1054 unsigned int dedicated_fifos:1;
1055 unsigned char num_of_eps;
1056 u32 fifo_map;
1057
1058 struct usb_request *ep0_reply;
1059 struct usb_request *ctrl_req;
3f95001d
MYK		 1060 void *ep0_buff;
1061 void *ctrl_buff;
fe0b94ab 1062 enum dwc2_ep0_state ep0_state;
9e14d0a5 1063 u8 test_mode;
941fcce4 1064
0f6b80c0
VA		 1065 dma_addr_t setup_desc_dma[2];
1066 struct dwc2_dma_desc *setup_desc[2];
1067 dma_addr_t ctrl_in_desc_dma;
1068 struct dwc2_dma_desc *ctrl_in_desc;
1069 dma_addr_t ctrl_out_desc_dma;
1070 struct dwc2_dma_desc *ctrl_out_desc;
1071
941fcce4 1072 struct usb_gadget gadget;
dc6e69e6 1073 unsigned int enabled:1;
4ace06e8 1074 unsigned int connected:1;
1f91b4cc
FB		 1075 struct dwc2_hsotg_ep *eps_in[MAX_EPS_CHANNELS];
1076 struct dwc2_hsotg_ep *eps_out[MAX_EPS_CHANNELS];
941fcce4 1077#endif /* CONFIG_USB_DWC2_PERIPHERAL || CONFIG_USB_DWC2_DUAL_ROLE */
56f5b1cf
PZ		 1078};
1079
1080/* Reasons for halting a host channel */
1081enum dwc2_halt_status {
1082 DWC2_HC_XFER_NO_HALT_STATUS,
1083 DWC2_HC_XFER_COMPLETE,
1084 DWC2_HC_XFER_URB_COMPLETE,
1085 DWC2_HC_XFER_ACK,
1086 DWC2_HC_XFER_NAK,
1087 DWC2_HC_XFER_NYET,
1088 DWC2_HC_XFER_STALL,
1089 DWC2_HC_XFER_XACT_ERR,
1090 DWC2_HC_XFER_FRAME_OVERRUN,
1091 DWC2_HC_XFER_BABBLE_ERR,
1092 DWC2_HC_XFER_DATA_TOGGLE_ERR,
1093 DWC2_HC_XFER_AHB_ERR,
1094 DWC2_HC_XFER_PERIODIC_INCOMPLETE,
1095 DWC2_HC_XFER_URB_DEQUEUE,
1096};
1097
1e6b98eb
VM		 1098/* Core version information */
1099static inline bool dwc2_is_iot(struct dwc2_hsotg *hsotg)
1100{
1101 return (hsotg->hw_params.snpsid & 0xfff00000) == 0x55300000;
1102}
1103
1104static inline bool dwc2_is_fs_iot(struct dwc2_hsotg *hsotg)
1105{
1106 return (hsotg->hw_params.snpsid & 0xffff0000) == 0x55310000;
1107}
1108
1109static inline bool dwc2_is_hs_iot(struct dwc2_hsotg *hsotg)
1110{
1111 return (hsotg->hw_params.snpsid & 0xffff0000) == 0x55320000;
1112}
1113
56f5b1cf
PZ		 1114/*
1115 * The following functions support initialization of the core driver component
1116 * and the DWC_otg controller
1117 */
6e6360b6 1118int dwc2_core_reset(struct dwc2_hsotg *hsotg, bool skip_wait);
9da51974
JY		 1119int dwc2_core_reset_and_force_dr_mode(struct dwc2_hsotg *hsotg);
1120int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg);
1121int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, bool restore);
56f5b1cf 1122
323230ef
JY		 1123bool dwc2_force_mode_if_needed(struct dwc2_hsotg *hsotg, bool host);
1124void dwc2_clear_force_mode(struct dwc2_hsotg *hsotg);
09c96980
JY		 1125void dwc2_force_dr_mode(struct dwc2_hsotg *hsotg);
1126
9da51974 1127bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg);
56f5b1cf
PZ		 1128
1129/*
1130 * Common core Functions.
1131 * The following functions support managing the DWC_otg controller in either
1132 * device or host mode.
1133 */
9da51974
JY		 1134void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes);
1135void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num);
1136void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg);
56f5b1cf 1137
9da51974
JY		 1138void dwc2_enable_global_interrupts(struct dwc2_hsotg *hcd);
1139void dwc2_disable_global_interrupts(struct dwc2_hsotg *hcd);
56f5b1cf 1140
66e77a24
RK		 1141void dwc2_enable_acg(struct dwc2_hsotg *hsotg);
1142
56f5b1cf 1143/* This function should be called on every hardware interrupt. */
9da51974 1144irqreturn_t dwc2_handle_common_intr(int irq, void *dev);
56f5b1cf 1145
323230ef
JY		 1146/* The device ID match table */
1147extern const struct of_device_id dwc2_of_match_table[];
1148
9da51974
JY		 1149int dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg);
1150int dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg);
ecb176c6 1151
79d6b8c5
SA		 1152/* Common polling functions */
1153int dwc2_hsotg_wait_bit_set(struct dwc2_hsotg *hs_otg, u32 reg, u32 bit,
1154 u32 timeout);
1155int dwc2_hsotg_wait_bit_clear(struct dwc2_hsotg *hs_otg, u32 reg, u32 bit,
1156 u32 timeout);
334bbd4e 1157/* Parameters */
c1d286cf 1158int dwc2_get_hwparams(struct dwc2_hsotg *hsotg);
334bbd4e
JY		 1159int dwc2_init_params(struct dwc2_hsotg *hsotg);
1160
6bea9620
JY		 1161/*
1162 * The following functions check the controller's OTG operation mode
1163 * capability (GHWCFG2.OTG_MODE).
1164 *
1165 * These functions can be used before the internal hsotg->hw_params
1166 * are read in and cached so they always read directly from the
1167 * GHWCFG2 register.
1168 */
9da51974 1169unsigned int dwc2_op_mode(struct dwc2_hsotg *hsotg);
6bea9620
JY		 1170bool dwc2_hw_is_otg(struct dwc2_hsotg *hsotg);
1171bool dwc2_hw_is_host(struct dwc2_hsotg *hsotg);
1172bool dwc2_hw_is_device(struct dwc2_hsotg *hsotg);
1173
1696d5ab
JY		 1174/*
1175 * Returns the mode of operation, host or device
1176 */
1177static inline int dwc2_is_host_mode(struct dwc2_hsotg *hsotg)
1178{
1179 return (dwc2_readl(hsotg->regs + GINTSTS) & GINTSTS_CURMODE_HOST) != 0;
1180}
9da51974 1181
1696d5ab
JY		 1182static inline int dwc2_is_device_mode(struct dwc2_hsotg *hsotg)
1183{
1184 return (dwc2_readl(hsotg->regs + GINTSTS) & GINTSTS_CURMODE_HOST) == 0;
1185}
1186
56f5b1cf
PZ		 1187/*
1188 * Dump core registers and SPRAM
1189 */
9da51974
JY		 1190void dwc2_dump_dev_registers(struct dwc2_hsotg *hsotg);
1191void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg);
1192void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg);
56f5b1cf 1193
117777b2 1194/* Gadget defines */
b98866c2
JY		 1195#if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \
1196 IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
9da51974
JY		 1197int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg);
1198int dwc2_hsotg_suspend(struct dwc2_hsotg *dwc2);
1199int dwc2_hsotg_resume(struct dwc2_hsotg *dwc2);
f3768997 1200int dwc2_gadget_init(struct dwc2_hsotg *hsotg);
9da51974
JY		 1201void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2,
1202 bool reset);
1203void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg);
1204void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2);
1205int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode);
f81f46e1 1206#define dwc2_is_device_connected(hsotg) (hsotg->connected)
58e52ff6
JY		 1207int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg);
1208int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg);
c138ecfa
SA		 1209int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg *hsotg);
1210int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg);
1211int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg *hsotg);
21b03405 1212void dwc2_gadget_init_lpm(struct dwc2_hsotg *hsotg);
117777b2 1213#else
1f91b4cc 1214static inline int dwc2_hsotg_remove(struct dwc2_hsotg *dwc2)
117777b2 1215{ return 0; }
1f91b4cc 1216static inline int dwc2_hsotg_suspend(struct dwc2_hsotg *dwc2)
117777b2 1217{ return 0; }
1f91b4cc 1218static inline int dwc2_hsotg_resume(struct dwc2_hsotg *dwc2)
117777b2 1219{ return 0; }
f3768997 1220static inline int dwc2_gadget_init(struct dwc2_hsotg *hsotg)
117777b2 1221{ return 0; }
1f91b4cc 1222static inline void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2,
9da51974 1223 bool reset) {}
1f91b4cc
FB		 1224static inline void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg) {}
1225static inline void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2) {}
1226static inline int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg,
9da51974 1227 int testmode)
f91eea44 1228{ return 0; }
f81f46e1 1229#define dwc2_is_device_connected(hsotg) (0)
58e52ff6
JY		 1230static inline int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg)
1231{ return 0; }
1232static inline int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg)
1233{ return 0; }
c138ecfa
SA		 1234static inline int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg *hsotg)
1235{ return 0; }
1236static inline int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg)
1237{ return 0; }
1238static inline int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg *hsotg)
1239{ return 0; }
21b03405 1240static inline void dwc2_gadget_init_lpm(struct dwc2_hsotg *hsotg) {}
117777b2
DN		 1241#endif
1242
1243#if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
9da51974
JY		 1244int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg);
1245int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg, int us);
1246void dwc2_hcd_connect(struct dwc2_hsotg *hsotg);
1247void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force);
1248void dwc2_hcd_start(struct dwc2_hsotg *hsotg);
58e52ff6
JY		 1249int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg);
1250int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg);
117777b2 1251#else
117777b2
DN		 1252static inline int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg)
1253{ return 0; }
fae4e826
DA		 1254static inline int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg,
1255 int us)
1256{ return 0; }
6a659531
DA		 1257static inline void dwc2_hcd_connect(struct dwc2_hsotg *hsotg) {}
1258static inline void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force) {}
117777b2
DN		 1259static inline void dwc2_hcd_start(struct dwc2_hsotg *hsotg) {}
1260static inline void dwc2_hcd_remove(struct dwc2_hsotg *hsotg) {}
4fe160d5 1261static inline int dwc2_hcd_init(struct dwc2_hsotg *hsotg)
117777b2 1262{ return 0; }
58e52ff6
JY		 1263static inline int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg)
1264{ return 0; }
1265static inline int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg)
1266{ return 0; }
1267
117777b2
DN		 1268#endif
1269
56f5b1cf 1270#endif /* __DWC2_CORE_H__ */
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