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usb: dwc2: gadget: kill requests after disabling ep
[linux-block.git] / drivers / usb / dwc2 / core.h
CommitLineData
56f5b1cf
PZ		 1/*
2 * core.h - DesignWare HS OTG Controller common declarations
3 *
4 * Copyright (C) 2004-2013 Synopsys, Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions, and the following disclaimer,
11 * without modification.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The names of the above-listed copyright holders may not be used
16 * to endorse or promote products derived from this software without
17 * specific prior written permission.
18 *
19 * ALTERNATIVELY, this software may be distributed under the terms of the
20 * GNU General Public License ("GPL") as published by the Free Software
21 * Foundation; either version 2 of the License, or (at your option) any
22 * later version.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
25 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
28 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
29 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
30 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
31 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
32 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
33 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
34 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 */
36
37#ifndef __DWC2_CORE_H__
38#define __DWC2_CORE_H__
39
f7c0b143
DN		 40#include <linux/phy/phy.h>
41#include <linux/regulator/consumer.h>
42#include <linux/usb/gadget.h>
43#include <linux/usb/otg.h>
56f5b1cf
PZ		 44#include <linux/usb/phy.h>
45#include "hw.h"
46
47#ifdef DWC2_LOG_WRITES
48static inline void do_write(u32 value, void *addr)
49{
50 writel(value, addr);
51 pr_info("INFO:: wrote %08x to %p\n", value, addr);
52}
53
54#undef writel
55#define writel(v, a) do_write(v, a)
56#endif
57
58/* Maximum number of Endpoints/HostChannels */
59#define MAX_EPS_CHANNELS 16
60
f7c0b143
DN		 61/* s3c-hsotg declarations */
62static const char * const s3c_hsotg_supply_names[] = {
63 "vusb_d", /* digital USB supply, 1.2V */
64 "vusb_a", /* analog USB supply, 1.1V */
65};
66
67/*
68 * EP0_MPS_LIMIT
69 *
70 * Unfortunately there seems to be a limit of the amount of data that can
71 * be transferred by IN transactions on EP0. This is either 127 bytes or 3
72 * packets (which practically means 1 packet and 63 bytes of data) when the
73 * MPS is set to 64.
74 *
75 * This means if we are wanting to move >127 bytes of data, we need to
76 * split the transactions up, but just doing one packet at a time does
77 * not work (this may be an implicit DATA0 PID on first packet of the
78 * transaction) and doing 2 packets is outside the controller's limits.
79 *
80 * If we try to lower the MPS size for EP0, then no transfers work properly
81 * for EP0, and the system will fail basic enumeration. As no cause for this
82 * has currently been found, we cannot support any large IN transfers for
83 * EP0.
84 */
85#define EP0_MPS_LIMIT 64
86
941fcce4 87struct dwc2_hsotg;
f7c0b143
DN		 88struct s3c_hsotg_req;
89
90/**
91 * struct s3c_hsotg_ep - driver endpoint definition.
92 * @ep: The gadget layer representation of the endpoint.
93 * @name: The driver generated name for the endpoint.
94 * @queue: Queue of requests for this endpoint.
95 * @parent: Reference back to the parent device structure.
96 * @req: The current request that the endpoint is processing. This is
97 * used to indicate an request has been loaded onto the endpoint
98 * and has yet to be completed (maybe due to data move, or simply
99 * awaiting an ack from the core all the data has been completed).
100 * @debugfs: File entry for debugfs file for this endpoint.
101 * @lock: State lock to protect contents of endpoint.
102 * @dir_in: Set to true if this endpoint is of the IN direction, which
103 * means that it is sending data to the Host.
104 * @index: The index for the endpoint registers.
105 * @mc: Multi Count - number of transactions per microframe
106 * @interval - Interval for periodic endpoints
107 * @name: The name array passed to the USB core.
108 * @halted: Set if the endpoint has been halted.
109 * @periodic: Set if this is a periodic ep, such as Interrupt
110 * @isochronous: Set if this is a isochronous ep
111 * @sent_zlp: Set if we've sent a zero-length packet.
112 * @total_data: The total number of data bytes done.
113 * @fifo_size: The size of the FIFO (for periodic IN endpoints)
114 * @fifo_load: The amount of data loaded into the FIFO (periodic IN)
115 * @last_load: The offset of data for the last start of request.
116 * @size_loaded: The last loaded size for DxEPTSIZE for periodic IN
117 *
118 * This is the driver's state for each registered enpoint, allowing it
119 * to keep track of transactions that need doing. Each endpoint has a
120 * lock to protect the state, to try and avoid using an overall lock
121 * for the host controller as much as possible.
122 *
123 * For periodic IN endpoints, we have fifo_size and fifo_load to try
124 * and keep track of the amount of data in the periodic FIFO for each
125 * of these as we don't have a status register that tells us how much
126 * is in each of them. (note, this may actually be useless information
127 * as in shared-fifo mode periodic in acts like a single-frame packet
128 * buffer than a fifo)
129 */
130struct s3c_hsotg_ep {
131 struct usb_ep ep;
132 struct list_head queue;
941fcce4 133 struct dwc2_hsotg *parent;
f7c0b143
DN		 134 struct s3c_hsotg_req *req;
135 struct dentry *debugfs;
136
137 unsigned long total_data;
138 unsigned int size_loaded;
139 unsigned int last_load;
140 unsigned int fifo_load;
141 unsigned short fifo_size;
b203d0a2 142 unsigned short fifo_index;
f7c0b143
DN		 143
144 unsigned char dir_in;
145 unsigned char index;
146 unsigned char mc;
147 unsigned char interval;
148
149 unsigned int halted:1;
150 unsigned int periodic:1;
151 unsigned int isochronous:1;
152 unsigned int sent_zlp:1;
153
154 char name[10];
155};
156
f7c0b143
DN		 157/**
158 * struct s3c_hsotg_req - data transfer request
159 * @req: The USB gadget request
160 * @queue: The list of requests for the endpoint this is queued for.
f7c0b143
DN		 161 */
162struct s3c_hsotg_req {
163 struct usb_request req;
164 struct list_head queue;
f7c0b143
DN		 165};
166
941fcce4 167#if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
f7c0b143
DN		 168#define call_gadget(_hs, _entry) \
169do { \
170 if ((_hs)->gadget.speed != USB_SPEED_UNKNOWN && \
171 (_hs)->driver && (_hs)->driver->_entry) { \
172 spin_unlock(&_hs->lock); \
173 (_hs)->driver->_entry(&(_hs)->gadget); \
174 spin_lock(&_hs->lock); \
175 } \
176} while (0)
941fcce4
DN		 177#else
178#define call_gadget(_hs, _entry) do {} while (0)
179#endif
f7c0b143 180
56f5b1cf
PZ		 181struct dwc2_hsotg;
182struct dwc2_host_chan;
183
184/* Device States */
185enum dwc2_lx_state {
186 DWC2_L0, /* On state */
187 DWC2_L1, /* LPM sleep state */
188 DWC2_L2, /* USB suspend state */
189 DWC2_L3, /* Off state */
190};
191
0a176279
GH		 192/*
193 * Gadget periodic tx fifo sizes as used by legacy driver
194 * EP0 is not included
195 */
196#define DWC2_G_P_LEGACY_TX_FIFO_SIZE {256, 256, 256, 256, 768, 768, 768, \
197 768, 0, 0, 0, 0, 0, 0, 0}
198
56f5b1cf
PZ		 199/**
200 * struct dwc2_core_params - Parameters for configuring the core
201 *
91121c10
MK		 202 * @otg_cap: Specifies the OTG capabilities.
203 * 0 - HNP and SRP capable
56f5b1cf 204 * 1 - SRP Only capable
91121c10
MK		 205 * 2 - No HNP/SRP capable (always available)
206 * Defaults to best available option (0, 1, then 2)
725acc86 207 * @otg_ver: OTG version supported
91121c10 208 * 0 - 1.3 (default)
725acc86 209 * 1 - 2.0
56f5b1cf
PZ		 210 * @dma_enable: Specifies whether to use slave or DMA mode for accessing
211 * the data FIFOs. The driver will automatically detect the
212 * value for this parameter if none is specified.
91121c10 213 * 0 - Slave (always available)
56f5b1cf
PZ		 214 * 1 - DMA (default, if available)
215 * @dma_desc_enable: When DMA mode is enabled, specifies whether to use
216 * address DMA mode or descriptor DMA mode for accessing
217 * the data FIFOs. The driver will automatically detect the
218 * value for this if none is specified.
219 * 0 - Address DMA
220 * 1 - Descriptor DMA (default, if available)
221 * @speed: Specifies the maximum speed of operation in host and
222 * device mode. The actual speed depends on the speed of
223 * the attached device and the value of phy_type.
91121c10
MK		 224 * 0 - High Speed
225 * (default when phy_type is UTMI+ or ULPI)
56f5b1cf 226 * 1 - Full Speed
91121c10 227 * (default when phy_type is Full Speed)
56f5b1cf 228 * @enable_dynamic_fifo: 0 - Use coreConsultant-specified FIFO size parameters
91121c10 229 * 1 - Allow dynamic FIFO sizing (default, if available)
725acc86
PZ		 230 * @en_multiple_tx_fifo: Specifies whether dedicated per-endpoint transmit FIFOs
231 * are enabled
56f5b1cf
PZ		 232 * @host_rx_fifo_size: Number of 4-byte words in the Rx FIFO in host mode when
233 * dynamic FIFO sizing is enabled
91121c10
MK		 234 * 16 to 32768
235 * Actual maximum value is autodetected and also
236 * the default.
56f5b1cf
PZ		 237 * @host_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO
238 * in host mode when dynamic FIFO sizing is enabled
91121c10
MK		 239 * 16 to 32768
240 * Actual maximum value is autodetected and also
241 * the default.
56f5b1cf
PZ		 242 * @host_perio_tx_fifo_size: Number of 4-byte words in the periodic Tx FIFO in
243 * host mode when dynamic FIFO sizing is enabled
91121c10
MK		 244 * 16 to 32768
245 * Actual maximum value is autodetected and also
246 * the default.
56f5b1cf 247 * @max_transfer_size: The maximum transfer size supported, in bytes
91121c10
MK		 248 * 2047 to 65,535
249 * Actual maximum value is autodetected and also
250 * the default.
56f5b1cf 251 * @max_packet_count: The maximum number of packets in a transfer
91121c10
MK		 252 * 15 to 511
253 * Actual maximum value is autodetected and also
254 * the default.
56f5b1cf 255 * @host_channels: The number of host channel registers to use
91121c10
MK		 256 * 1 to 16
257 * Actual maximum value is autodetected and also
258 * the default.
56f5b1cf
PZ		 259 * @phy_type: Specifies the type of PHY interface to use. By default,
260 * the driver will automatically detect the phy_type.
91121c10
MK		 261 * 0 - Full Speed Phy
262 * 1 - UTMI+ Phy
263 * 2 - ULPI Phy
264 * Defaults to best available option (2, 1, then 0)
56f5b1cf
PZ		 265 * @phy_utmi_width: Specifies the UTMI+ Data Width (in bits). This parameter
266 * is applicable for a phy_type of UTMI+ or ULPI. (For a
267 * ULPI phy_type, this parameter indicates the data width
268 * between the MAC and the ULPI Wrapper.) Also, this
269 * parameter is applicable only if the OTG_HSPHY_WIDTH cC
270 * parameter was set to "8 and 16 bits", meaning that the
271 * core has been configured to work at either data path
272 * width.
91121c10 273 * 8 or 16 (default 16 if available)
56f5b1cf
PZ		 274 * @phy_ulpi_ddr: Specifies whether the ULPI operates at double or single
275 * data rate. This parameter is only applicable if phy_type
276 * is ULPI.
277 * 0 - single data rate ULPI interface with 8 bit wide
278 * data bus (default)
279 * 1 - double data rate ULPI interface with 4 bit wide
280 * data bus
281 * @phy_ulpi_ext_vbus: For a ULPI phy, specifies whether to use the internal or
282 * external supply to drive the VBus
91121c10
MK		 283 * 0 - Internal supply (default)
284 * 1 - External supply
56f5b1cf
PZ		 285 * @i2c_enable: Specifies whether to use the I2Cinterface for a full
286 * speed PHY. This parameter is only applicable if phy_type
287 * is FS.
288 * 0 - No (default)
289 * 1 - Yes
91121c10
MK		 290 * @ulpi_fs_ls: Make ULPI phy operate in FS/LS mode only
291 * 0 - No (default)
292 * 1 - Yes
725acc86
PZ		 293 * @host_support_fs_ls_low_power: Specifies whether low power mode is supported
294 * when attached to a Full Speed or Low Speed device in
295 * host mode.
296 * 0 - Don't support low power mode (default)
297 * 1 - Support low power mode
298 * @host_ls_low_power_phy_clk: Specifies the PHY clock rate in low power mode
91121c10
MK		 299 * when connected to a Low Speed device in host
300 * mode. This parameter is applicable only if
301 * host_support_fs_ls_low_power is enabled.
725acc86 302 * 0 - 48 MHz
91121c10 303 * (default when phy_type is UTMI+ or ULPI)
725acc86 304 * 1 - 6 MHz
91121c10
MK		 305 * (default when phy_type is Full Speed)
306 * @ts_dline: Enable Term Select Dline pulsing
307 * 0 - No (default)
308 * 1 - Yes
309 * @reload_ctl: Allow dynamic reloading of HFIR register during runtime
310 * 0 - No (default for core < 2.92a)
311 * 1 - Yes (default for core >= 2.92a)
4d3190e1
PZ		 312 * @ahbcfg: This field allows the default value of the GAHBCFG
313 * register to be overridden
91121c10
MK		 314 * -1 - GAHBCFG value will be set to 0x06
315 * (INCR4, default)
4d3190e1
PZ		 316 * all others - GAHBCFG value will be overridden with
317 * this value
91121c10
MK		 318 * Not all bits can be controlled like this, the
319 * bits defined by GAHBCFG_CTRL_MASK are controlled
320 * by the driver and are ignored in this
321 * configuration value.
20f2eb9c 322 * @uframe_sched: True to enable the microframe scheduler
56f5b1cf
PZ		 323 *
324 * The following parameters may be specified when starting the module. These
91121c10
MK		 325 * parameters define how the DWC_otg controller should be configured. A
326 * value of -1 (or any other out of range value) for any parameter means
327 * to read the value from hardware (if possible) or use the builtin
328 * default described above.
56f5b1cf
PZ		 329 */
330struct dwc2_core_params {
8284f93b
MK		 331 /*
332 * Don't add any non-int members here, this will break
333 * dwc2_set_all_params!
334 */
56f5b1cf
PZ		 335 int otg_cap;
336 int otg_ver;
337 int dma_enable;
338 int dma_desc_enable;
339 int speed;
340 int enable_dynamic_fifo;
341 int en_multiple_tx_fifo;
342 int host_rx_fifo_size;
343 int host_nperio_tx_fifo_size;
344 int host_perio_tx_fifo_size;
345 int max_transfer_size;
346 int max_packet_count;
347 int host_channels;
348 int phy_type;
349 int phy_utmi_width;
350 int phy_ulpi_ddr;
351 int phy_ulpi_ext_vbus;
352 int i2c_enable;
353 int ulpi_fs_ls;
354 int host_support_fs_ls_low_power;
355 int host_ls_low_power_phy_clk;
356 int ts_dline;
357 int reload_ctl;
4d3190e1 358 int ahbcfg;
20f2eb9c 359 int uframe_sched;
56f5b1cf
PZ		 360};
361
9badec2f
MK		 362/**
363 * struct dwc2_hw_params - Autodetected parameters.
364 *
365 * These parameters are the various parameters read from hardware
366 * registers during initialization. They typically contain the best
367 * supported or maximum value that can be configured in the
368 * corresponding dwc2_core_params value.
369 *
370 * The values that are not in dwc2_core_params are documented below.
371 *
372 * @op_mode Mode of Operation
373 * 0 - HNP- and SRP-Capable OTG (Host & Device)
374 * 1 - SRP-Capable OTG (Host & Device)
375 * 2 - Non-HNP and Non-SRP Capable OTG (Host & Device)
376 * 3 - SRP-Capable Device
377 * 4 - Non-OTG Device
378 * 5 - SRP-Capable Host
379 * 6 - Non-OTG Host
380 * @arch Architecture
381 * 0 - Slave only
382 * 1 - External DMA
383 * 2 - Internal DMA
384 * @power_optimized Are power optimizations enabled?
385 * @num_dev_ep Number of device endpoints available
386 * @num_dev_perio_in_ep Number of device periodic IN endpoints
997f4f81 387 * available
9badec2f
MK		 388 * @dev_token_q_depth Device Mode IN Token Sequence Learning Queue
389 * Depth
390 * 0 to 30
391 * @host_perio_tx_q_depth
392 * Host Mode Periodic Request Queue Depth
393 * 2, 4 or 8
394 * @nperio_tx_q_depth
395 * Non-Periodic Request Queue Depth
396 * 2, 4 or 8
397 * @hs_phy_type High-speed PHY interface type
398 * 0 - High-speed interface not supported
399 * 1 - UTMI+
400 * 2 - ULPI
401 * 3 - UTMI+ and ULPI
402 * @fs_phy_type Full-speed PHY interface type
403 * 0 - Full speed interface not supported
404 * 1 - Dedicated full speed interface
405 * 2 - FS pins shared with UTMI+ pins
406 * 3 - FS pins shared with ULPI pins
407 * @total_fifo_size: Total internal RAM for FIFOs (bytes)
de4a1931
MK		 408 * @utmi_phy_data_width UTMI+ PHY data width
409 * 0 - 8 bits
410 * 1 - 16 bits
411 * 2 - 8 or 16 bits
9badec2f
MK		 412 * @snpsid: Value from SNPSID register
413 */
414struct dwc2_hw_params {
415 unsigned op_mode:3;
416 unsigned arch:2;
417 unsigned dma_desc_enable:1;
418 unsigned enable_dynamic_fifo:1;
419 unsigned en_multiple_tx_fifo:1;
420 unsigned host_rx_fifo_size:16;
421 unsigned host_nperio_tx_fifo_size:16;
422 unsigned host_perio_tx_fifo_size:16;
423 unsigned nperio_tx_q_depth:3;
424 unsigned host_perio_tx_q_depth:3;
425 unsigned dev_token_q_depth:5;
426 unsigned max_transfer_size:26;
427 unsigned max_packet_count:11;
2d115547 428 unsigned host_channels:5;
9badec2f
MK		 429 unsigned hs_phy_type:2;
430 unsigned fs_phy_type:2;
431 unsigned i2c_enable:1;
432 unsigned num_dev_ep:4;
433 unsigned num_dev_perio_in_ep:4;
434 unsigned total_fifo_size:16;
435 unsigned power_optimized:1;
de4a1931 436 unsigned utmi_phy_data_width:2;
9badec2f
MK		 437 u32 snpsid;
438};
439
3f95001d
MYK		 440/* Size of control and EP0 buffers */
441#define DWC2_CTRL_BUFF_SIZE 8
442
56f5b1cf
PZ		 443/**
444 * struct dwc2_hsotg - Holds the state of the driver, including the non-periodic
445 * and periodic schedules
446 *
941fcce4
DN		 447 * These are common for both host and peripheral modes:
448 *
56f5b1cf
PZ		 449 * @dev: The struct device pointer
450 * @regs: Pointer to controller regs
9badec2f
MK		 451 * @hw_params: Parameters that were autodetected from the
452 * hardware registers
941fcce4 453 * @core_params: Parameters that define how the core should be configured
56f5b1cf
PZ		 454 * @op_state: The operational State, during transitions (a_host=>
455 * a_peripheral and b_device=>b_host) this may not match
456 * the core, but allows the software to determine
457 * transitions
c0155b9d
KY		 458 * @dr_mode: Requested mode of operation, one of following:
459 * - USB_DR_MODE_PERIPHERAL
460 * - USB_DR_MODE_HOST
461 * - USB_DR_MODE_OTG
941fcce4
DN		 462 * @lock: Spinlock that protects all the driver data structures
463 * @priv: Stores a pointer to the struct usb_hcd
56f5b1cf
PZ		 464 * @queuing_high_bandwidth: True if multiple packets of a high-bandwidth
465 * transfer are in process of being queued
466 * @srp_success: Stores status of SRP request in the case of a FS PHY
467 * with an I2C interface
468 * @wq_otg: Workqueue object used for handling of some interrupts
469 * @wf_otg: Work object for handling Connector ID Status Change
470 * interrupt
471 * @wkp_timer: Timer object for handling Wakeup Detected interrupt
472 * @lx_state: Lx state of connected device
941fcce4
DN		 473 *
474 * These are for host mode:
475 *
56f5b1cf
PZ		 476 * @flags: Flags for handling root port state changes
477 * @non_periodic_sched_inactive: Inactive QHs in the non-periodic schedule.
478 * Transfers associated with these QHs are not currently
479 * assigned to a host channel.
480 * @non_periodic_sched_active: Active QHs in the non-periodic schedule.
481 * Transfers associated with these QHs are currently
482 * assigned to a host channel.
483 * @non_periodic_qh_ptr: Pointer to next QH to process in the active
484 * non-periodic schedule
485 * @periodic_sched_inactive: Inactive QHs in the periodic schedule. This is a
486 * list of QHs for periodic transfers that are _not_
487 * scheduled for the next frame. Each QH in the list has an
488 * interval counter that determines when it needs to be
489 * scheduled for execution. This scheduling mechanism
490 * allows only a simple calculation for periodic bandwidth
491 * used (i.e. must assume that all periodic transfers may
492 * need to execute in the same frame). However, it greatly
493 * simplifies scheduling and should be sufficient for the
494 * vast majority of OTG hosts, which need to connect to a
495 * small number of peripherals at one time. Items move from
496 * this list to periodic_sched_ready when the QH interval
497 * counter is 0 at SOF.
498 * @periodic_sched_ready: List of periodic QHs that are ready for execution in
499 * the next frame, but have not yet been assigned to host
500 * channels. Items move from this list to
501 * periodic_sched_assigned as host channels become
502 * available during the current frame.
503 * @periodic_sched_assigned: List of periodic QHs to be executed in the next
504 * frame that are assigned to host channels. Items move
505 * from this list to periodic_sched_queued as the
506 * transactions for the QH are queued to the DWC_otg
507 * controller.
508 * @periodic_sched_queued: List of periodic QHs that have been queued for
509 * execution. Items move from this list to either
510 * periodic_sched_inactive or periodic_sched_ready when the
511 * channel associated with the transfer is released. If the
512 * interval for the QH is 1, the item moves to
513 * periodic_sched_ready because it must be rescheduled for
514 * the next frame. Otherwise, the item moves to
515 * periodic_sched_inactive.
516 * @periodic_usecs: Total bandwidth claimed so far for periodic transfers.
517 * This value is in microseconds per (micro)frame. The
518 * assumption is that all periodic transfers may occur in
519 * the same (micro)frame.
20f2eb9c 520 * @frame_usecs: Internal variable used by the microframe scheduler
56f5b1cf
PZ		 521 * @frame_number: Frame number read from the core at SOF. The value ranges
522 * from 0 to HFNUM_MAX_FRNUM.
523 * @periodic_qh_count: Count of periodic QHs, if using several eps. Used for
524 * SOF enable/disable.
525 * @free_hc_list: Free host channels in the controller. This is a list of
526 * struct dwc2_host_chan items.
527 * @periodic_channels: Number of host channels assigned to periodic transfers.
528 * Currently assuming that there is a dedicated host
529 * channel for each periodic transaction and at least one
530 * host channel is available for non-periodic transactions.
531 * @non_periodic_channels: Number of host channels assigned to non-periodic
532 * transfers
20f2eb9c
DC		 533 * @available_host_channels Number of host channels available for the microframe
534 * scheduler to use
56f5b1cf
PZ		 535 * @hc_ptr_array: Array of pointers to the host channel descriptors.
536 * Allows accessing a host channel descriptor given the
537 * host channel number. This is useful in interrupt
538 * handlers.
539 * @status_buf: Buffer used for data received during the status phase of
540 * a control transfer.
541 * @status_buf_dma: DMA address for status_buf
542 * @start_work: Delayed work for handling host A-cable connection
543 * @reset_work: Delayed work for handling a port reset
56f5b1cf
PZ		 544 * @otg_port: OTG port number
545 * @frame_list: Frame list
546 * @frame_list_dma: Frame list DMA address
941fcce4
DN		 547 *
548 * These are for peripheral mode:
549 *
550 * @driver: USB gadget driver
551 * @phy: The otg phy transceiver structure for phy control.
552 * @uphy: The otg phy transceiver structure for old USB phy control.
553 * @plat: The platform specific configuration data. This can be removed once
554 * all SoCs support usb transceiver.
555 * @supplies: Definition of USB power supplies
556 * @phyif: PHY interface width
557 * @dedicated_fifos: Set if the hardware has dedicated IN-EP fifos.
558 * @num_of_eps: Number of available EPs (excluding EP0)
559 * @debug_root: Root directrory for debugfs.
560 * @debug_file: Main status file for debugfs.
561 * @debug_fifo: FIFO status file for debugfs.
562 * @ep0_reply: Request used for ep0 reply.
563 * @ep0_buff: Buffer for EP0 reply data, if needed.
564 * @ctrl_buff: Buffer for EP0 control requests.
565 * @ctrl_req: Request for EP0 control packets.
566 * @setup: NAK management for EP0 SETUP
567 * @last_rst: Time of last reset
568 * @eps: The endpoints being supplied to the gadget framework
edd74be8 569 * @g_using_dma: Indicate if dma usage is enabled
0a176279
GH		 570 * @g_rx_fifo_sz: Contains rx fifo size value
571 * @g_np_g_tx_fifo_sz: Contains Non-Periodic tx fifo size value
572 * @g_tx_fifo_sz: Contains tx fifo size value per endpoints
56f5b1cf
PZ		 573 */
574struct dwc2_hsotg {
575 struct device *dev;
576 void __iomem *regs;
9badec2f
MK		 577 /** Params detected from hardware */
578 struct dwc2_hw_params hw_params;
579 /** Params to actually use */
56f5b1cf 580 struct dwc2_core_params *core_params;
56f5b1cf 581 enum usb_otg_state op_state;
c0155b9d 582 enum usb_dr_mode dr_mode;
56f5b1cf 583
941fcce4
DN		 584 struct phy *phy;
585 struct usb_phy *uphy;
586 struct regulator_bulk_data supplies[ARRAY_SIZE(s3c_hsotg_supply_names)];
587
588 spinlock_t lock;
7ad8096e 589 struct mutex init_mutex;
941fcce4
DN		 590 void *priv;
591 int irq;
592 struct clk *clk;
593
56f5b1cf
PZ		 594 unsigned int queuing_high_bandwidth:1;
595 unsigned int srp_success:1;
596
597 struct workqueue_struct *wq_otg;
598 struct work_struct wf_otg;
599 struct timer_list wkp_timer;
600 enum dwc2_lx_state lx_state;
601
941fcce4
DN		 602 struct dentry *debug_root;
603 struct dentry *debug_file;
604 struct dentry *debug_fifo;
605
606 /* DWC OTG HW Release versions */
607#define DWC2_CORE_REV_2_71a 0x4f54271a
608#define DWC2_CORE_REV_2_90a 0x4f54290a
609#define DWC2_CORE_REV_2_92a 0x4f54292a
610#define DWC2_CORE_REV_2_94a 0x4f54294a
611#define DWC2_CORE_REV_3_00a 0x4f54300a
612
613#if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
56f5b1cf
PZ		 614 union dwc2_hcd_internal_flags {
615 u32 d32;
616 struct {
617 unsigned port_connect_status_change:1;
618 unsigned port_connect_status:1;
619 unsigned port_reset_change:1;
620 unsigned port_enable_change:1;
621 unsigned port_suspend_change:1;
622 unsigned port_over_current_change:1;
623 unsigned port_l1_change:1;
fd4850cf 624 unsigned reserved:25;
56f5b1cf
PZ		 625 } b;
626 } flags;
627
628 struct list_head non_periodic_sched_inactive;
629 struct list_head non_periodic_sched_active;
630 struct list_head *non_periodic_qh_ptr;
631 struct list_head periodic_sched_inactive;
632 struct list_head periodic_sched_ready;
633 struct list_head periodic_sched_assigned;
634 struct list_head periodic_sched_queued;
635 u16 periodic_usecs;
20f2eb9c 636 u16 frame_usecs[8];
56f5b1cf
PZ		 637 u16 frame_number;
638 u16 periodic_qh_count;
639
640#ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
641#define FRAME_NUM_ARRAY_SIZE 1000
642 u16 last_frame_num;
643 u16 *frame_num_array;
644 u16 *last_frame_num_array;
645 int frame_num_idx;
646 int dumped_frame_num_array;
647#endif
648
649 struct list_head free_hc_list;
650 int periodic_channels;
651 int non_periodic_channels;
20f2eb9c 652 int available_host_channels;
56f5b1cf
PZ		 653 struct dwc2_host_chan *hc_ptr_array[MAX_EPS_CHANNELS];
654 u8 *status_buf;
655 dma_addr_t status_buf_dma;
656#define DWC2_HCD_STATUS_BUF_SIZE 64
657
658 struct delayed_work start_work;
659 struct delayed_work reset_work;
56f5b1cf
PZ		 660 u8 otg_port;
661 u32 *frame_list;
662 dma_addr_t frame_list_dma;
663
56f5b1cf
PZ		 664#ifdef DEBUG
665 u32 frrem_samples;
666 u64 frrem_accum;
667
668 u32 hfnum_7_samples_a;
669 u64 hfnum_7_frrem_accum_a;
670 u32 hfnum_0_samples_a;
671 u64 hfnum_0_frrem_accum_a;
672 u32 hfnum_other_samples_a;
673 u64 hfnum_other_frrem_accum_a;
674
675 u32 hfnum_7_samples_b;
676 u64 hfnum_7_frrem_accum_b;
677 u32 hfnum_0_samples_b;
678 u64 hfnum_0_frrem_accum_b;
679 u32 hfnum_other_samples_b;
680 u64 hfnum_other_frrem_accum_b;
681#endif
941fcce4
DN		 682#endif /* CONFIG_USB_DWC2_HOST || CONFIG_USB_DWC2_DUAL_ROLE */
683
684#if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
685 /* Gadget structures */
686 struct usb_gadget_driver *driver;
687 struct s3c_hsotg_plat *plat;
688
689 u32 phyif;
690 int fifo_mem;
691 unsigned int dedicated_fifos:1;
692 unsigned char num_of_eps;
693 u32 fifo_map;
694
695 struct usb_request *ep0_reply;
696 struct usb_request *ctrl_req;
3f95001d
MYK		 697 void *ep0_buff;
698 void *ctrl_buff;
941fcce4
DN		 699
700 struct usb_gadget gadget;
dc6e69e6 701 unsigned int enabled:1;
4ace06e8 702 unsigned int connected:1;
dc6e69e6 703 unsigned int setup:1;
941fcce4 704 unsigned long last_rst;
c6f5c050
MYK		 705 struct s3c_hsotg_ep *eps_in[MAX_EPS_CHANNELS];
706 struct s3c_hsotg_ep *eps_out[MAX_EPS_CHANNELS];
edd74be8 707 u32 g_using_dma;
0a176279
GH		 708 u32 g_rx_fifo_sz;
709 u32 g_np_g_tx_fifo_sz;
710 u32 g_tx_fifo_sz[MAX_EPS_CHANNELS];
941fcce4 711#endif /* CONFIG_USB_DWC2_PERIPHERAL || CONFIG_USB_DWC2_DUAL_ROLE */
56f5b1cf
PZ		 712};
713
714/* Reasons for halting a host channel */
715enum dwc2_halt_status {
716 DWC2_HC_XFER_NO_HALT_STATUS,
717 DWC2_HC_XFER_COMPLETE,
718 DWC2_HC_XFER_URB_COMPLETE,
719 DWC2_HC_XFER_ACK,
720 DWC2_HC_XFER_NAK,
721 DWC2_HC_XFER_NYET,
722 DWC2_HC_XFER_STALL,
723 DWC2_HC_XFER_XACT_ERR,
724 DWC2_HC_XFER_FRAME_OVERRUN,
725 DWC2_HC_XFER_BABBLE_ERR,
726 DWC2_HC_XFER_DATA_TOGGLE_ERR,
727 DWC2_HC_XFER_AHB_ERR,
728 DWC2_HC_XFER_PERIODIC_INCOMPLETE,
729 DWC2_HC_XFER_URB_DEQUEUE,
730};
731
732/*
733 * The following functions support initialization of the core driver component
734 * and the DWC_otg controller
735 */
736extern void dwc2_core_host_init(struct dwc2_hsotg *hsotg);
737
738/*
739 * Host core Functions.
740 * The following functions support managing the DWC_otg controller in host
741 * mode.
742 */
743extern void dwc2_hc_init(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan);
744extern void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan,
745 enum dwc2_halt_status halt_status);
746extern void dwc2_hc_cleanup(struct dwc2_hsotg *hsotg,
747 struct dwc2_host_chan *chan);
748extern void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg,
749 struct dwc2_host_chan *chan);
750extern void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg,
751 struct dwc2_host_chan *chan);
752extern int dwc2_hc_continue_transfer(struct dwc2_hsotg *hsotg,
753 struct dwc2_host_chan *chan);
754extern void dwc2_hc_do_ping(struct dwc2_hsotg *hsotg,
755 struct dwc2_host_chan *chan);
756extern void dwc2_enable_host_interrupts(struct dwc2_hsotg *hsotg);
757extern void dwc2_disable_host_interrupts(struct dwc2_hsotg *hsotg);
758
759extern u32 dwc2_calc_frame_interval(struct dwc2_hsotg *hsotg);
057715f2 760extern bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg);
56f5b1cf
PZ		 761
762/*
763 * Common core Functions.
764 * The following functions support managing the DWC_otg controller in either
765 * device or host mode.
766 */
767extern void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes);
768extern void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num);
769extern void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg);
770
6706c721 771extern int dwc2_core_init(struct dwc2_hsotg *hsotg, bool select_phy, int irq);
56f5b1cf
PZ		 772extern void dwc2_enable_global_interrupts(struct dwc2_hsotg *hcd);
773extern void dwc2_disable_global_interrupts(struct dwc2_hsotg *hcd);
774
775/* This function should be called on every hardware interrupt. */
776extern irqreturn_t dwc2_handle_common_intr(int irq, void *dev);
777
778/* OTG Core Parameters */
779
780/*
781 * Specifies the OTG capabilities. The driver will automatically
782 * detect the value for this parameter if none is specified.
783 * 0 - HNP and SRP capable (default)
784 * 1 - SRP Only capable
785 * 2 - No HNP/SRP capable
786 */
7218dae7 787extern void dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg, int val);
56f5b1cf
PZ		 788#define DWC2_CAP_PARAM_HNP_SRP_CAPABLE 0
789#define DWC2_CAP_PARAM_SRP_ONLY_CAPABLE 1
790#define DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE 2
791
792/*
793 * Specifies whether to use slave or DMA mode for accessing the data
794 * FIFOs. The driver will automatically detect the value for this
795 * parameter if none is specified.
796 * 0 - Slave
797 * 1 - DMA (default, if available)
798 */
7218dae7 799extern void dwc2_set_param_dma_enable(struct dwc2_hsotg *hsotg, int val);
56f5b1cf
PZ		 800
801/*
802 * When DMA mode is enabled specifies whether to use
803 * address DMA or DMA Descritor mode for accessing the data
804 * FIFOs in device mode. The driver will automatically detect
805 * the value for this parameter if none is specified.
806 * 0 - address DMA
807 * 1 - DMA Descriptor(default, if available)
808 */
7218dae7 809extern void dwc2_set_param_dma_desc_enable(struct dwc2_hsotg *hsotg, int val);
56f5b1cf
PZ		 810
811/*
812 * Specifies the maximum speed of operation in host and device mode.
813 * The actual speed depends on the speed of the attached device and
814 * the value of phy_type. The actual speed depends on the speed of the
815 * attached device.
816 * 0 - High Speed (default)
817 * 1 - Full Speed
818 */
7218dae7 819extern void dwc2_set_param_speed(struct dwc2_hsotg *hsotg, int val);
56f5b1cf
PZ		 820#define DWC2_SPEED_PARAM_HIGH 0
821#define DWC2_SPEED_PARAM_FULL 1
822
823/*
824 * Specifies whether low power mode is supported when attached
825 * to a Full Speed or Low Speed device in host mode.
826 *
827 * 0 - Don't support low power mode (default)
828 * 1 - Support low power mode
829 */
7218dae7
PZ		 830extern void dwc2_set_param_host_support_fs_ls_low_power(
831 struct dwc2_hsotg *hsotg, int val);
56f5b1cf
PZ		 832
833/*
834 * Specifies the PHY clock rate in low power mode when connected to a
835 * Low Speed device in host mode. This parameter is applicable only if
836 * HOST_SUPPORT_FS_LS_LOW_POWER is enabled. If PHY_TYPE is set to FS
837 * then defaults to 6 MHZ otherwise 48 MHZ.
838 *
839 * 0 - 48 MHz
840 * 1 - 6 MHz
841 */
7218dae7
PZ		 842extern void dwc2_set_param_host_ls_low_power_phy_clk(struct dwc2_hsotg *hsotg,
843 int val);
56f5b1cf
PZ		 844#define DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ 0
845#define DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ 1
846
847/*
848 * 0 - Use cC FIFO size parameters
849 * 1 - Allow dynamic FIFO sizing (default)
850 */
7218dae7
PZ		 851extern void dwc2_set_param_enable_dynamic_fifo(struct dwc2_hsotg *hsotg,
852 int val);
56f5b1cf
PZ		 853
854/*
855 * Number of 4-byte words in the Rx FIFO in host mode when dynamic
856 * FIFO sizing is enabled.
857 * 16 to 32768 (default 1024)
858 */
7218dae7 859extern void dwc2_set_param_host_rx_fifo_size(struct dwc2_hsotg *hsotg, int val);
56f5b1cf
PZ		 860
861/*
862 * Number of 4-byte words in the non-periodic Tx FIFO in host mode
863 * when Dynamic FIFO sizing is enabled in the core.
864 * 16 to 32768 (default 256)
865 */
7218dae7
PZ		 866extern void dwc2_set_param_host_nperio_tx_fifo_size(struct dwc2_hsotg *hsotg,
867 int val);
56f5b1cf
PZ		 868
869/*
870 * Number of 4-byte words in the host periodic Tx FIFO when dynamic
871 * FIFO sizing is enabled.
872 * 16 to 32768 (default 256)
873 */
7218dae7
PZ		 874extern void dwc2_set_param_host_perio_tx_fifo_size(struct dwc2_hsotg *hsotg,
875 int val);
56f5b1cf
PZ		 876
877/*
878 * The maximum transfer size supported in bytes.
879 * 2047 to 65,535 (default 65,535)
880 */
7218dae7 881extern void dwc2_set_param_max_transfer_size(struct dwc2_hsotg *hsotg, int val);
56f5b1cf
PZ		 882
883/*
884 * The maximum number of packets in a transfer.
885 * 15 to 511 (default 511)
886 */
7218dae7 887extern void dwc2_set_param_max_packet_count(struct dwc2_hsotg *hsotg, int val);
56f5b1cf
PZ		 888
889/*
890 * The number of host channel registers to use.
891 * 1 to 16 (default 11)
892 * Note: The FPGA configuration supports a maximum of 11 host channels.
893 */
7218dae7 894extern void dwc2_set_param_host_channels(struct dwc2_hsotg *hsotg, int val);
56f5b1cf
PZ		 895
896/*
897 * Specifies the type of PHY interface to use. By default, the driver
898 * will automatically detect the phy_type.
899 *
900 * 0 - Full Speed PHY
901 * 1 - UTMI+ (default)
902 * 2 - ULPI
903 */
7218dae7 904extern void dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg, int val);
56f5b1cf
PZ		 905#define DWC2_PHY_TYPE_PARAM_FS 0
906#define DWC2_PHY_TYPE_PARAM_UTMI 1
907#define DWC2_PHY_TYPE_PARAM_ULPI 2
908
909/*
910 * Specifies the UTMI+ Data Width. This parameter is
911 * applicable for a PHY_TYPE of UTMI+ or ULPI. (For a ULPI
912 * PHY_TYPE, this parameter indicates the data width between
913 * the MAC and the ULPI Wrapper.) Also, this parameter is
914 * applicable only if the OTG_HSPHY_WIDTH cC parameter was set
915 * to "8 and 16 bits", meaning that the core has been
916 * configured to work at either data path width.
917 *
918 * 8 or 16 bits (default 16)
919 */
7218dae7 920extern void dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg, int val);
56f5b1cf
PZ		 921
922/*
923 * Specifies whether the ULPI operates at double or single
924 * data rate. This parameter is only applicable if PHY_TYPE is
925 * ULPI.
926 *
927 * 0 - single data rate ULPI interface with 8 bit wide data
928 * bus (default)
929 * 1 - double data rate ULPI interface with 4 bit wide data
930 * bus
931 */
7218dae7 932extern void dwc2_set_param_phy_ulpi_ddr(struct dwc2_hsotg *hsotg, int val);
56f5b1cf
PZ		 933
934/*
935 * Specifies whether to use the internal or external supply to
936 * drive the vbus with a ULPI phy.
937 */
7218dae7 938extern void dwc2_set_param_phy_ulpi_ext_vbus(struct dwc2_hsotg *hsotg, int val);
56f5b1cf
PZ		 939#define DWC2_PHY_ULPI_INTERNAL_VBUS 0
940#define DWC2_PHY_ULPI_EXTERNAL_VBUS 1
941
942/*
943 * Specifies whether to use the I2Cinterface for full speed PHY. This
944 * parameter is only applicable if PHY_TYPE is FS.
945 * 0 - No (default)
946 * 1 - Yes
947 */
7218dae7 948extern void dwc2_set_param_i2c_enable(struct dwc2_hsotg *hsotg, int val);
56f5b1cf 949
7218dae7 950extern void dwc2_set_param_ulpi_fs_ls(struct dwc2_hsotg *hsotg, int val);
56f5b1cf 951
7218dae7 952extern void dwc2_set_param_ts_dline(struct dwc2_hsotg *hsotg, int val);
56f5b1cf
PZ		 953
954/*
955 * Specifies whether dedicated transmit FIFOs are
956 * enabled for non periodic IN endpoints in device mode
957 * 0 - No
958 * 1 - Yes
959 */
7218dae7
PZ		 960extern void dwc2_set_param_en_multiple_tx_fifo(struct dwc2_hsotg *hsotg,
961 int val);
56f5b1cf 962
7218dae7 963extern void dwc2_set_param_reload_ctl(struct dwc2_hsotg *hsotg, int val);
56f5b1cf 964
7218dae7 965extern void dwc2_set_param_ahbcfg(struct dwc2_hsotg *hsotg, int val);
56f5b1cf 966
7218dae7 967extern void dwc2_set_param_otg_ver(struct dwc2_hsotg *hsotg, int val);
56f5b1cf
PZ		 968
969/*
970 * Dump core registers and SPRAM
971 */
972extern void dwc2_dump_dev_registers(struct dwc2_hsotg *hsotg);
973extern void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg);
974extern void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg);
975
976/*
977 * Return OTG version - either 1.3 or 2.0
978 */
979extern u16 dwc2_get_otg_version(struct dwc2_hsotg *hsotg);
980
117777b2
DN		 981/* Gadget defines */
982#if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
983extern int s3c_hsotg_remove(struct dwc2_hsotg *hsotg);
984extern int s3c_hsotg_suspend(struct dwc2_hsotg *dwc2);
985extern int s3c_hsotg_resume(struct dwc2_hsotg *dwc2);
986extern int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq);
510ffaa4
DN		 987extern void s3c_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2);
988extern void s3c_hsotg_core_connect(struct dwc2_hsotg *hsotg);
4ace06e8 989extern void s3c_hsotg_disconnect(struct dwc2_hsotg *dwc2);
117777b2
DN		 990#else
991static inline int s3c_hsotg_remove(struct dwc2_hsotg *dwc2)
992{ return 0; }
993static inline int s3c_hsotg_suspend(struct dwc2_hsotg *dwc2)
994{ return 0; }
995static inline int s3c_hsotg_resume(struct dwc2_hsotg *dwc2)
996{ return 0; }
997static inline int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq)
998{ return 0; }
510ffaa4
DN		 999static inline void s3c_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2) {}
1000static inline void s3c_hsotg_core_connect(struct dwc2_hsotg *hsotg) {}
4ace06e8 1001static inline void s3c_hsotg_disconnect(struct dwc2_hsotg *dwc2) {}
117777b2
DN		 1002#endif
1003
1004#if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
1005extern int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg);
1006extern void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg);
1007extern void dwc2_hcd_start(struct dwc2_hsotg *hsotg);
1008#else
1009static inline void dwc2_set_all_params(struct dwc2_core_params *params, int value) {}
1010static inline int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg)
1011{ return 0; }
1012static inline void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg) {}
1013static inline void dwc2_hcd_start(struct dwc2_hsotg *hsotg) {}
1014static inline void dwc2_hcd_remove(struct dwc2_hsotg *hsotg) {}
1015static inline int dwc2_hcd_init(struct dwc2_hsotg *hsotg, int irq,
1016 const struct dwc2_core_params *params)
1017{ return 0; }
1018#endif
1019
56f5b1cf 1020#endif /* __DWC2_CORE_H__ */
Linux 6.x block layer and io_uring tree(s)