[linux-2.6-block.git] / drivers / usb / chipidea / core.c

/*
 * core.c - ChipIdea USB IP core family device controller
 *
 * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
 *
 * Author: David Lopo
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

/*
 * Description: ChipIdea USB IP core family device controller
 *
 * This driver is composed of several blocks:
 * - HW:     hardware interface
 * - DBG:    debug facilities (optional)
 * - UTIL:   utilities
 * - ISR:    interrupts handling
 * - ENDPT:  endpoint operations (Gadget API)
 * - GADGET: gadget operations (Gadget API)
 * - BUS:    bus glue code, bus abstraction layer
 *
 * Compile Options
 * - CONFIG_USB_GADGET_DEBUG_FILES: enable debug facilities
 * - STALL_IN:  non-empty bulk-in pipes cannot be halted
 *              if defined mass storage compliance succeeds but with warnings
 *              => case 4: Hi >  Dn
 *              => case 5: Hi >  Di
 *              => case 8: Hi <> Do
 *              if undefined usbtest 13 fails
 * - TRACE:     enable function tracing (depends on DEBUG)
 *
 * Main Features
 * - Chapter 9 & Mass Storage Compliance with Gadget File Storage
 * - Chapter 9 Compliance with Gadget Zero (STALL_IN undefined)
 * - Normal & LPM support
 *
 * USBTEST Report
 * - OK: 0-12, 13 (STALL_IN defined) & 14
 * - Not Supported: 15 & 16 (ISO)
 *
 * TODO List
 * - OTG
 * - Isochronous & Interrupt Traffic
 * - Handle requests which spawns into several TDs
 * - GET_STATUS(device) - always reports 0
 * - Gadget API (majority of optional features)
 * - Suspend & Remote Wakeup
 */
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/dmapool.h>
#include <linux/dma-mapping.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/idr.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/pm_runtime.h>
#include <linux/usb/ch9.h>
#include <linux/usb/gadget.h>
#include <linux/usb/otg.h>
#include <linux/usb/chipidea.h>

#include "ci.h"
#include "udc.h"
#include "bits.h"
#include "host.h"
#include "debug.h"

/* Controller register map */
static uintptr_t ci_regs_nolpm[] = {
	[CAP_CAPLENGTH]		= 0x000UL,
	[CAP_HCCPARAMS]		= 0x008UL,
	[CAP_DCCPARAMS]		= 0x024UL,
	[CAP_TESTMODE]		= 0x038UL,
	[OP_USBCMD]		= 0x000UL,
	[OP_USBSTS]		= 0x004UL,
	[OP_USBINTR]		= 0x008UL,
	[OP_DEVICEADDR]		= 0x014UL,
	[OP_ENDPTLISTADDR]	= 0x018UL,
	[OP_PORTSC]		= 0x044UL,
	[OP_DEVLC]		= 0x084UL,
	[OP_OTGSC]		= 0x064UL,
	[OP_USBMODE]		= 0x068UL,
	[OP_ENDPTSETUPSTAT]	= 0x06CUL,
	[OP_ENDPTPRIME]		= 0x070UL,
	[OP_ENDPTFLUSH]		= 0x074UL,
	[OP_ENDPTSTAT]		= 0x078UL,
	[OP_ENDPTCOMPLETE]	= 0x07CUL,
	[OP_ENDPTCTRL]		= 0x080UL,
};

static uintptr_t ci_regs_lpm[] = {
	[CAP_CAPLENGTH]		= 0x000UL,
	[CAP_HCCPARAMS]		= 0x008UL,
	[CAP_DCCPARAMS]		= 0x024UL,
	[CAP_TESTMODE]		= 0x0FCUL,
	[OP_USBCMD]		= 0x000UL,
	[OP_USBSTS]		= 0x004UL,
	[OP_USBINTR]		= 0x008UL,
	[OP_DEVICEADDR]		= 0x014UL,
	[OP_ENDPTLISTADDR]	= 0x018UL,
	[OP_PORTSC]		= 0x044UL,
	[OP_DEVLC]		= 0x084UL,
	[OP_OTGSC]		= 0x0C4UL,
	[OP_USBMODE]		= 0x0C8UL,
	[OP_ENDPTSETUPSTAT]	= 0x0D8UL,
	[OP_ENDPTPRIME]		= 0x0DCUL,
	[OP_ENDPTFLUSH]		= 0x0E0UL,
	[OP_ENDPTSTAT]		= 0x0E4UL,
	[OP_ENDPTCOMPLETE]	= 0x0E8UL,
	[OP_ENDPTCTRL]		= 0x0ECUL,
};

static int hw_alloc_regmap(struct ci13xxx *ci, bool is_lpm)
{
	int i;

	kfree(ci->hw_bank.regmap);

	ci->hw_bank.regmap = kzalloc((OP_LAST + 1) * sizeof(void *),
				     GFP_KERNEL);
	if (!ci->hw_bank.regmap)
		return -ENOMEM;

	for (i = 0; i < OP_ENDPTCTRL; i++)
		ci->hw_bank.regmap[i] =
			(i <= CAP_LAST ? ci->hw_bank.cap : ci->hw_bank.op) +
			(is_lpm ? ci_regs_lpm[i] : ci_regs_nolpm[i]);

	for (; i <= OP_LAST; i++)
		ci->hw_bank.regmap[i] = ci->hw_bank.op +
			4 * (i - OP_ENDPTCTRL) +
			(is_lpm
			 ? ci_regs_lpm[OP_ENDPTCTRL]
			 : ci_regs_nolpm[OP_ENDPTCTRL]);

	return 0;
}

/**
 * hw_port_test_set: writes port test mode (execute without interruption)
 * @mode: new value
 *
 * This function returns an error code
 */
int hw_port_test_set(struct ci13xxx *ci, u8 mode)
{
	const u8 TEST_MODE_MAX = 7;

	if (mode > TEST_MODE_MAX)
		return -EINVAL;

	hw_write(ci, OP_PORTSC, PORTSC_PTC, mode << ffs_nr(PORTSC_PTC));
	return 0;
}

/**
 * hw_port_test_get: reads port test mode value
 *
 * This function returns port test mode value
 */
u8 hw_port_test_get(struct ci13xxx *ci)
{
	return hw_read(ci, OP_PORTSC, PORTSC_PTC) >> ffs_nr(PORTSC_PTC);
}

static int hw_device_init(struct ci13xxx *ci, void __iomem *base)
{
	u32 reg;

	/* bank is a module variable */
	ci->hw_bank.abs = base;

	ci->hw_bank.cap = ci->hw_bank.abs;
	ci->hw_bank.cap += ci->platdata->capoffset;
	ci->hw_bank.op = ci->hw_bank.cap + ioread8(ci->hw_bank.cap);

	hw_alloc_regmap(ci, false);
	reg = hw_read(ci, CAP_HCCPARAMS, HCCPARAMS_LEN) >>
		ffs_nr(HCCPARAMS_LEN);
	ci->hw_bank.lpm  = reg;
	hw_alloc_regmap(ci, !!reg);
	ci->hw_bank.size = ci->hw_bank.op - ci->hw_bank.abs;
	ci->hw_bank.size += OP_LAST;
	ci->hw_bank.size /= sizeof(u32);

	reg = hw_read(ci, CAP_DCCPARAMS, DCCPARAMS_DEN) >>
		ffs_nr(DCCPARAMS_DEN);
	ci->hw_ep_max = reg * 2;   /* cache hw ENDPT_MAX */

	if (ci->hw_ep_max > ENDPT_MAX)
		return -ENODEV;

	dev_dbg(ci->dev, "ChipIdea HDRC found, lpm: %d; cap: %p op: %p\n",
		ci->hw_bank.lpm, ci->hw_bank.cap, ci->hw_bank.op);

	/* setup lock mode ? */

	/* ENDPTSETUPSTAT is '0' by default */

	/* HCSPARAMS.bf.ppc SHOULD BE zero for device */

	return 0;
}

/**
 * hw_device_reset: resets chip (execute without interruption)
 * @ci: the controller
  *
 * This function returns an error code
 */
int hw_device_reset(struct ci13xxx *ci, u32 mode)
{
	/* should flush & stop before reset */
	hw_write(ci, OP_ENDPTFLUSH, ~0, ~0);
	hw_write(ci, OP_USBCMD, USBCMD_RS, 0);

	hw_write(ci, OP_USBCMD, USBCMD_RST, USBCMD_RST);
	while (hw_read(ci, OP_USBCMD, USBCMD_RST))
		udelay(10);		/* not RTOS friendly */


	if (ci->platdata->notify_event)
		ci->platdata->notify_event(ci,
			CI13XXX_CONTROLLER_RESET_EVENT);

	if (ci->platdata->flags & CI13XXX_DISABLE_STREAMING)
		hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS, USBMODE_CI_SDIS);

	/* USBMODE should be configured step by step */
	hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE);
	hw_write(ci, OP_USBMODE, USBMODE_CM, mode);
	/* HW >= 2.3 */
	hw_write(ci, OP_USBMODE, USBMODE_SLOM, USBMODE_SLOM);

	if (hw_read(ci, OP_USBMODE, USBMODE_CM) != mode) {
		pr_err("cannot enter in %s mode", ci_role(ci)->name);
		pr_err("lpm = %i", ci->hw_bank.lpm);
		return -ENODEV;
	}

	return 0;
}

/**
 * ci_otg_role - pick role based on ID pin state
 * @ci: the controller
 */
static enum ci_role ci_otg_role(struct ci13xxx *ci)
{
	u32 sts = hw_read(ci, OP_OTGSC, ~0);
	enum ci_role role = sts & OTGSC_ID
		? CI_ROLE_GADGET
		: CI_ROLE_HOST;

	return role;
}

/**
 * ci_role_work - perform role changing based on ID pin
 * @work: work struct
 */
static void ci_role_work(struct work_struct *work)
{
	struct ci13xxx *ci = container_of(work, struct ci13xxx, work);
	enum ci_role role = ci_otg_role(ci);

	if (role != ci->role) {
		dev_dbg(ci->dev, "switching from %s to %s\n",
			ci_role(ci)->name, ci->roles[role]->name);

		ci_role_stop(ci);
		ci_role_start(ci, role);
		enable_irq(ci->irq);
	}
}

static ssize_t show_role(struct device *dev, struct device_attribute *attr,
			 char *buf)
{
	struct ci13xxx *ci = dev_get_drvdata(dev);

	return sprintf(buf, "%s\n", ci_role(ci)->name);
}

static ssize_t store_role(struct device *dev, struct device_attribute *attr,
			  const char *buf, size_t count)
{
	struct ci13xxx *ci = dev_get_drvdata(dev);
	enum ci_role role;
	int ret;

	for (role = CI_ROLE_HOST; role < CI_ROLE_END; role++)
		if (ci->roles[role] && !strcmp(buf, ci->roles[role]->name))
			break;

	if (role == CI_ROLE_END || role == ci->role)
		return -EINVAL;

	ci_role_stop(ci);
	ret = ci_role_start(ci, role);
	if (ret)
		return ret;

	return count;
}

static DEVICE_ATTR(role, S_IRUSR | S_IWUSR, show_role, store_role);

static irqreturn_t ci_irq(int irq, void *data)
{
	struct ci13xxx *ci = data;
	irqreturn_t ret = IRQ_NONE;
	u32 otgsc = 0;

	if (ci->is_otg)
		otgsc = hw_read(ci, OP_OTGSC, ~0);

	if (ci->role != CI_ROLE_END)
		ret = ci_role(ci)->irq(ci);

	if (ci->is_otg && (otgsc & OTGSC_IDIS)) {
		hw_write(ci, OP_OTGSC, OTGSC_IDIS, OTGSC_IDIS);
		disable_irq_nosync(ci->irq);
		queue_work(ci->wq, &ci->work);
		ret = IRQ_HANDLED;
	}

	return ret;
}

static DEFINE_IDA(ci_ida);

struct platform_device *ci13xxx_add_device(struct device *dev,
			struct resource *res, int nres,
			struct ci13xxx_platform_data *platdata)
{
	struct platform_device *pdev;
	int id, ret;

	id = ida_simple_get(&ci_ida, 0, 0, GFP_KERNEL);
	if (id < 0)
		return ERR_PTR(id);

	pdev = platform_device_alloc("ci_hdrc", id);
	if (!pdev) {
		ret = -ENOMEM;
		goto put_id;
	}

	pdev->dev.parent = dev;
	pdev->dev.dma_mask = dev->dma_mask;
	pdev->dev.dma_parms = dev->dma_parms;
	dma_set_coherent_mask(&pdev->dev, dev->coherent_dma_mask);

	ret = platform_device_add_resources(pdev, res, nres);
	if (ret)
		goto err;

	ret = platform_device_add_data(pdev, platdata, sizeof(*platdata));
	if (ret)
		goto err;

	ret = platform_device_add(pdev);
	if (ret)
		goto err;

	return pdev;

err:
	platform_device_put(pdev);
put_id:
	ida_simple_remove(&ci_ida, id);
	return ERR_PTR(ret);
}
EXPORT_SYMBOL_GPL(ci13xxx_add_device);

void ci13xxx_remove_device(struct platform_device *pdev)
{
	platform_device_unregister(pdev);
	ida_simple_remove(&ci_ida, pdev->id);
}
EXPORT_SYMBOL_GPL(ci13xxx_remove_device);

static int ci_hdrc_probe(struct platform_device *pdev)
{
	struct device	*dev = &pdev->dev;
	struct ci13xxx	*ci;
	struct resource	*res;
	void __iomem	*base;
	int		ret;

	if (!dev->platform_data) {
		dev_err(dev, "platform data missing\n");
		return -ENODEV;
	}

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!res) {
		dev_err(dev, "missing resource\n");
		return -ENODEV;
	}

	base = devm_request_and_ioremap(dev, res);
	if (!res) {
		dev_err(dev, "can't request and ioremap resource\n");
		return -ENOMEM;
	}

	ci = devm_kzalloc(dev, sizeof(*ci), GFP_KERNEL);
	if (!ci) {
		dev_err(dev, "can't allocate device\n");
		return -ENOMEM;
	}

	ci->dev = dev;
	ci->platdata = dev->platform_data;
	if (ci->platdata->phy)
		ci->transceiver = ci->platdata->phy;
	else
		ci->global_phy = true;

	ret = hw_device_init(ci, base);
	if (ret < 0) {
		dev_err(dev, "can't initialize hardware\n");
		return -ENODEV;
	}

	ci->hw_bank.phys = res->start;

	ci->irq = platform_get_irq(pdev, 0);
	if (ci->irq < 0) {
		dev_err(dev, "missing IRQ\n");
		return -ENODEV;
	}

	INIT_WORK(&ci->work, ci_role_work);
	ci->wq = create_singlethread_workqueue("ci_otg");
	if (!ci->wq) {
		dev_err(dev, "can't create workqueue\n");
		return -ENODEV;
	}

	/* initialize role(s) before the interrupt is requested */
	ret = ci_hdrc_host_init(ci);
	if (ret)
		dev_info(dev, "doesn't support host\n");

	ret = ci_hdrc_gadget_init(ci);
	if (ret)
		dev_info(dev, "doesn't support gadget\n");

	if (!ci->roles[CI_ROLE_HOST] && !ci->roles[CI_ROLE_GADGET]) {
		dev_err(dev, "no supported roles\n");
		ret = -ENODEV;
		goto rm_wq;
	}

	if (ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET]) {
		ci->is_otg = true;
		/* ID pin needs 1ms debouce time, we delay 2ms for safe */
		mdelay(2);
		ci->role = ci_otg_role(ci);
	} else {
		ci->role = ci->roles[CI_ROLE_HOST]
			? CI_ROLE_HOST
			: CI_ROLE_GADGET;
	}

	ret = ci_role_start(ci, ci->role);
	if (ret) {
		dev_err(dev, "can't start %s role\n", ci_role(ci)->name);
		ret = -ENODEV;
		goto rm_wq;
	}

	platform_set_drvdata(pdev, ci);
	ret = request_irq(ci->irq, ci_irq, IRQF_SHARED, ci->platdata->name,
			  ci);
	if (ret)
		goto stop;

	ret = device_create_file(dev, &dev_attr_role);
	if (ret)
		goto rm_attr;

	if (ci->is_otg)
		hw_write(ci, OP_OTGSC, OTGSC_IDIE, OTGSC_IDIE);

	return ret;

rm_attr:
	device_remove_file(dev, &dev_attr_role);
stop:
	ci_role_stop(ci);
rm_wq:
	flush_workqueue(ci->wq);
	destroy_workqueue(ci->wq);

	return ret;
}

static int ci_hdrc_remove(struct platform_device *pdev)
{
	struct ci13xxx *ci = platform_get_drvdata(pdev);

	flush_workqueue(ci->wq);
	destroy_workqueue(ci->wq);
	device_remove_file(ci->dev, &dev_attr_role);
	free_irq(ci->irq, ci);
	ci_role_stop(ci);

	return 0;
}

static struct platform_driver ci_hdrc_driver = {
	.probe	= ci_hdrc_probe,
	.remove	= ci_hdrc_remove,
	.driver	= {
		.name	= "ci_hdrc",
	},
};

module_platform_driver(ci_hdrc_driver);

MODULE_ALIAS("platform:ci_hdrc");
MODULE_ALIAS("platform:ci13xxx");
MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("David Lopo <dlopo@chipidea.mips.com>");
MODULE_DESCRIPTION("ChipIdea HDRC Driver");
Commit	Line	Data
e443b333 AS	1	/*
	2	* core.c - ChipIdea USB IP core family device controller
	3	*
	4	* Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
	5	*
	6	* Author: David Lopo
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*/
	12
	13	/*
	14	* Description: ChipIdea USB IP core family device controller
	15	*
	16	* This driver is composed of several blocks:
	17	* - HW: hardware interface
	18	* - DBG: debug facilities (optional)
	19	* - UTIL: utilities
	20	* - ISR: interrupts handling
	21	* - ENDPT: endpoint operations (Gadget API)
	22	* - GADGET: gadget operations (Gadget API)
	23	* - BUS: bus glue code, bus abstraction layer
	24	*
	25	* Compile Options
	26	* - CONFIG_USB_GADGET_DEBUG_FILES: enable debug facilities
	27	* - STALL_IN: non-empty bulk-in pipes cannot be halted
	28	* if defined mass storage compliance succeeds but with warnings
	29	* => case 4: Hi > Dn
	30	* => case 5: Hi > Di
	31	* => case 8: Hi <> Do
	32	* if undefined usbtest 13 fails
	33	* - TRACE: enable function tracing (depends on DEBUG)
	34	*
	35	* Main Features
	36	* - Chapter 9 & Mass Storage Compliance with Gadget File Storage
	37	* - Chapter 9 Compliance with Gadget Zero (STALL_IN undefined)
	38	* - Normal & LPM support
	39	*
	40	* USBTEST Report
	41	* - OK: 0-12, 13 (STALL_IN defined) & 14
	42	* - Not Supported: 15 & 16 (ISO)
	43	*
	44	* TODO List
	45	* - OTG
	46	* - Isochronous & Interrupt Traffic
	47	* - Handle requests which spawns into several TDs
	48	* - GET_STATUS(device) - always reports 0
	49	* - Gadget API (majority of optional features)
	50	* - Suspend & Remote Wakeup
	51	*/
	52	#include <linux/delay.h>
	53	#include <linux/device.h>
	54	#include <linux/dmapool.h>
	55	#include <linux/dma-mapping.h>
	56	#include <linux/init.h>
	57	#include <linux/platform_device.h>
	58	#include <linux/module.h>
fe6e125e	59	#include <linux/idr.h>
e443b333 AS	60	#include <linux/interrupt.h>
	61	#include <linux/io.h>
	62	#include <linux/irq.h>
	63	#include <linux/kernel.h>
	64	#include <linux/slab.h>
	65	#include <linux/pm_runtime.h>
	66	#include <linux/usb/ch9.h>
	67	#include <linux/usb/gadget.h>
	68	#include <linux/usb/otg.h>
	69	#include <linux/usb/chipidea.h>
	70
	71	#include "ci.h"
	72	#include "udc.h"
	73	#include "bits.h"
eb70e5ab	74	#include "host.h"
e443b333 AS	75	#include "debug.h"
e443b333 AS	76
5f36e231	77	/* Controller register map */
e443b333 AS	78	static uintptr_t ci_regs_nolpm[] = {
	79	[CAP_CAPLENGTH] = 0x000UL,
	80	[CAP_HCCPARAMS] = 0x008UL,
	81	[CAP_DCCPARAMS] = 0x024UL,
	82	[CAP_TESTMODE] = 0x038UL,
	83	[OP_USBCMD] = 0x000UL,
	84	[OP_USBSTS] = 0x004UL,
	85	[OP_USBINTR] = 0x008UL,
	86	[OP_DEVICEADDR] = 0x014UL,
	87	[OP_ENDPTLISTADDR] = 0x018UL,
	88	[OP_PORTSC] = 0x044UL,
	89	[OP_DEVLC] = 0x084UL,
5f36e231	90	[OP_OTGSC] = 0x064UL,
e443b333 AS	91	[OP_USBMODE] = 0x068UL,
	92	[OP_ENDPTSETUPSTAT] = 0x06CUL,
	93	[OP_ENDPTPRIME] = 0x070UL,
	94	[OP_ENDPTFLUSH] = 0x074UL,
	95	[OP_ENDPTSTAT] = 0x078UL,
	96	[OP_ENDPTCOMPLETE] = 0x07CUL,
	97	[OP_ENDPTCTRL] = 0x080UL,
	98	};
	99
	100	static uintptr_t ci_regs_lpm[] = {
	101	[CAP_CAPLENGTH] = 0x000UL,
	102	[CAP_HCCPARAMS] = 0x008UL,
	103	[CAP_DCCPARAMS] = 0x024UL,
	104	[CAP_TESTMODE] = 0x0FCUL,
	105	[OP_USBCMD] = 0x000UL,
	106	[OP_USBSTS] = 0x004UL,
	107	[OP_USBINTR] = 0x008UL,
	108	[OP_DEVICEADDR] = 0x014UL,
	109	[OP_ENDPTLISTADDR] = 0x018UL,
	110	[OP_PORTSC] = 0x044UL,
	111	[OP_DEVLC] = 0x084UL,
5f36e231	112	[OP_OTGSC] = 0x0C4UL,
e443b333 AS	113	[OP_USBMODE] = 0x0C8UL,
	114	[OP_ENDPTSETUPSTAT] = 0x0D8UL,
	115	[OP_ENDPTPRIME] = 0x0DCUL,
	116	[OP_ENDPTFLUSH] = 0x0E0UL,
	117	[OP_ENDPTSTAT] = 0x0E4UL,
	118	[OP_ENDPTCOMPLETE] = 0x0E8UL,
	119	[OP_ENDPTCTRL] = 0x0ECUL,
	120	};
	121
5f36e231	122	static int hw_alloc_regmap(struct ci13xxx *ci, bool is_lpm)
e443b333 AS	123	{
	124	int i;
	125
5f36e231	126	kfree(ci->hw_bank.regmap);
e443b333	127
5f36e231 AS	128	ci->hw_bank.regmap = kzalloc((OP_LAST + 1) * sizeof(void *),
	129	GFP_KERNEL);
	130	if (!ci->hw_bank.regmap)
e443b333 AS	131	return -ENOMEM;
	132
	133	for (i = 0; i < OP_ENDPTCTRL; i++)
5f36e231 AS	134	ci->hw_bank.regmap[i] =
5f36e231 AS	135	(i <= CAP_LAST ? ci->hw_bank.cap : ci->hw_bank.op) +
e443b333 AS	136	(is_lpm ? ci_regs_lpm[i] : ci_regs_nolpm[i]);
	137
	138	for (; i <= OP_LAST; i++)
5f36e231	139	ci->hw_bank.regmap[i] = ci->hw_bank.op +
e443b333 AS	140	4 * (i - OP_ENDPTCTRL) +
	141	(is_lpm
	142	? ci_regs_lpm[OP_ENDPTCTRL]
	143	: ci_regs_nolpm[OP_ENDPTCTRL]);
	144
	145	return 0;
	146	}
	147
	148	/**
	149	* hw_port_test_set: writes port test mode (execute without interruption)
	150	* @mode: new value
	151	*
	152	* This function returns an error code
	153	*/
	154	int hw_port_test_set(struct ci13xxx *ci, u8 mode)
	155	{
	156	const u8 TEST_MODE_MAX = 7;
	157
	158	if (mode > TEST_MODE_MAX)
	159	return -EINVAL;
	160
	161	hw_write(ci, OP_PORTSC, PORTSC_PTC, mode << ffs_nr(PORTSC_PTC));
	162	return 0;
	163	}
	164
	165	/**
	166	* hw_port_test_get: reads port test mode value
	167	*
	168	* This function returns port test mode value
	169	*/
	170	u8 hw_port_test_get(struct ci13xxx *ci)
	171	{
	172	return hw_read(ci, OP_PORTSC, PORTSC_PTC) >> ffs_nr(PORTSC_PTC);
	173	}
	174
5f36e231	175	static int hw_device_init(struct ci13xxx ci, void __iomem base)
e443b333 AS	176	{
	177	u32 reg;
	178
	179	/* bank is a module variable */
5f36e231	180	ci->hw_bank.abs = base;
e443b333	181
5f36e231	182	ci->hw_bank.cap = ci->hw_bank.abs;
77c4400f	183	ci->hw_bank.cap += ci->platdata->capoffset;
5f36e231	184	ci->hw_bank.op = ci->hw_bank.cap + ioread8(ci->hw_bank.cap);
e443b333	185
5f36e231 AS	186	hw_alloc_regmap(ci, false);
5f36e231 AS	187	reg = hw_read(ci, CAP_HCCPARAMS, HCCPARAMS_LEN) >>
e443b333	188	ffs_nr(HCCPARAMS_LEN);
5f36e231 AS	189	ci->hw_bank.lpm = reg;
	190	hw_alloc_regmap(ci, !!reg);
	191	ci->hw_bank.size = ci->hw_bank.op - ci->hw_bank.abs;
	192	ci->hw_bank.size += OP_LAST;
	193	ci->hw_bank.size /= sizeof(u32);
e443b333	194
5f36e231	195	reg = hw_read(ci, CAP_DCCPARAMS, DCCPARAMS_DEN) >>
e443b333	196	ffs_nr(DCCPARAMS_DEN);
5f36e231	197	ci->hw_ep_max = reg * 2; /* cache hw ENDPT_MAX */
e443b333	198
09c94e62	199	if (ci->hw_ep_max > ENDPT_MAX)
e443b333 AS	200	return -ENODEV;
e443b333 AS	201
5f36e231 AS	202	dev_dbg(ci->dev, "ChipIdea HDRC found, lpm: %d; cap: %p op: %p\n",
5f36e231 AS	203	ci->hw_bank.lpm, ci->hw_bank.cap, ci->hw_bank.op);
e443b333 AS	204
	205	/* setup lock mode ? */
	206
	207	/* ENDPTSETUPSTAT is '0' by default */
	208
	209	/* HCSPARAMS.bf.ppc SHOULD BE zero for device */
	210
	211	return 0;
	212	}
	213
	214	/**
	215	* hw_device_reset: resets chip (execute without interruption)
	216	* @ci: the controller
	217	*
	218	* This function returns an error code
	219	*/
eb70e5ab	220	int hw_device_reset(struct ci13xxx *ci, u32 mode)
e443b333 AS	221	{
	222	/* should flush & stop before reset */
	223	hw_write(ci, OP_ENDPTFLUSH, ~0, ~0);
	224	hw_write(ci, OP_USBCMD, USBCMD_RS, 0);
	225
	226	hw_write(ci, OP_USBCMD, USBCMD_RST, USBCMD_RST);
	227	while (hw_read(ci, OP_USBCMD, USBCMD_RST))
	228	udelay(10); /* not RTOS friendly */
	229
	230
77c4400f RZ	231	if (ci->platdata->notify_event)
77c4400f RZ	232	ci->platdata->notify_event(ci,
e443b333 AS	233	CI13XXX_CONTROLLER_RESET_EVENT);
e443b333 AS	234
77c4400f	235	if (ci->platdata->flags & CI13XXX_DISABLE_STREAMING)
758fc986	236	hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS, USBMODE_CI_SDIS);
e443b333 AS	237
	238	/* USBMODE should be configured step by step */
	239	hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE);
eb70e5ab	240	hw_write(ci, OP_USBMODE, USBMODE_CM, mode);
e443b333 AS	241	/* HW >= 2.3 */
	242	hw_write(ci, OP_USBMODE, USBMODE_SLOM, USBMODE_SLOM);
	243
eb70e5ab AS	244	if (hw_read(ci, OP_USBMODE, USBMODE_CM) != mode) {
eb70e5ab AS	245	pr_err("cannot enter in %s mode", ci_role(ci)->name);
e443b333 AS	246	pr_err("lpm = %i", ci->hw_bank.lpm);
	247	return -ENODEV;
	248	}
	249
	250	return 0;
	251	}
	252
5f36e231 AS	253	/**
	254	* ci_otg_role - pick role based on ID pin state
	255	* @ci: the controller
	256	*/
	257	static enum ci_role ci_otg_role(struct ci13xxx *ci)
	258	{
	259	u32 sts = hw_read(ci, OP_OTGSC, ~0);
	260	enum ci_role role = sts & OTGSC_ID
	261	? CI_ROLE_GADGET
	262	: CI_ROLE_HOST;
	263
	264	return role;
	265	}
	266
	267	/**
	268	* ci_role_work - perform role changing based on ID pin
	269	* @work: work struct
	270	*/
	271	static void ci_role_work(struct work_struct *work)
	272	{
	273	struct ci13xxx *ci = container_of(work, struct ci13xxx, work);
	274	enum ci_role role = ci_otg_role(ci);
	275
5f36e231 AS	276	if (role != ci->role) {
	277	dev_dbg(ci->dev, "switching from %s to %s\n",
	278	ci_role(ci)->name, ci->roles[role]->name);
	279
	280	ci_role_stop(ci);
	281	ci_role_start(ci, role);
b183c19f	282	enable_irq(ci->irq);
5f36e231 AS	283	}
	284	}
	285
	286	static ssize_t show_role(struct device dev, struct device_attribute attr,
	287	char *buf)
	288	{
	289	struct ci13xxx *ci = dev_get_drvdata(dev);
	290
	291	return sprintf(buf, "%s\n", ci_role(ci)->name);
	292	}
	293
	294	static ssize_t store_role(struct device dev, struct device_attribute attr,
	295	const char *buf, size_t count)
	296	{
	297	struct ci13xxx *ci = dev_get_drvdata(dev);
	298	enum ci_role role;
	299	int ret;
	300
	301	for (role = CI_ROLE_HOST; role < CI_ROLE_END; role++)
	302	if (ci->roles[role] && !strcmp(buf, ci->roles[role]->name))
	303	break;
	304
	305	if (role == CI_ROLE_END \|\| role == ci->role)
	306	return -EINVAL;
	307
	308	ci_role_stop(ci);
	309	ret = ci_role_start(ci, role);
	310	if (ret)
	311	return ret;
	312
	313	return count;
	314	}
	315
	316	static DEVICE_ATTR(role, S_IRUSR \| S_IWUSR, show_role, store_role);
	317
	318	static irqreturn_t ci_irq(int irq, void *data)
	319	{
	320	struct ci13xxx *ci = data;
	321	irqreturn_t ret = IRQ_NONE;
b183c19f	322	u32 otgsc = 0;
5f36e231	323
b183c19f RZ	324	if (ci->is_otg)
b183c19f RZ	325	otgsc = hw_read(ci, OP_OTGSC, ~0);
5f36e231	326
b183c19f RZ	327	if (ci->role != CI_ROLE_END)
	328	ret = ci_role(ci)->irq(ci);
	329
	330	if (ci->is_otg && (otgsc & OTGSC_IDIS)) {
	331	hw_write(ci, OP_OTGSC, OTGSC_IDIS, OTGSC_IDIS);
	332	disable_irq_nosync(ci->irq);
	333	queue_work(ci->wq, &ci->work);
	334	ret = IRQ_HANDLED;
5f36e231 AS	335	}
5f36e231 AS	336
b183c19f	337	return ret;
5f36e231 AS	338	}
5f36e231 AS	339
fe6e125e RZ	340	static DEFINE_IDA(ci_ida);
fe6e125e RZ	341
cbc6dc2a RZ	342	struct platform_device ci13xxx_add_device(struct device dev,
	343	struct resource *res, int nres,
	344	struct ci13xxx_platform_data *platdata)
	345	{
	346	struct platform_device *pdev;
fe6e125e	347	int id, ret;
cbc6dc2a	348
fe6e125e RZ	349	id = ida_simple_get(&ci_ida, 0, 0, GFP_KERNEL);
	350	if (id < 0)
	351	return ERR_PTR(id);
	352
	353	pdev = platform_device_alloc("ci_hdrc", id);
	354	if (!pdev) {
	355	ret = -ENOMEM;
	356	goto put_id;
	357	}
cbc6dc2a RZ	358
	359	pdev->dev.parent = dev;
	360	pdev->dev.dma_mask = dev->dma_mask;
	361	pdev->dev.dma_parms = dev->dma_parms;
	362	dma_set_coherent_mask(&pdev->dev, dev->coherent_dma_mask);
	363
	364	ret = platform_device_add_resources(pdev, res, nres);
	365	if (ret)
	366	goto err;
	367
	368	ret = platform_device_add_data(pdev, platdata, sizeof(*platdata));
	369	if (ret)
	370	goto err;
	371
	372	ret = platform_device_add(pdev);
	373	if (ret)
	374	goto err;
	375
	376	return pdev;
	377
	378	err:
	379	platform_device_put(pdev);
fe6e125e RZ	380	put_id:
fe6e125e RZ	381	ida_simple_remove(&ci_ida, id);
cbc6dc2a RZ	382	return ERR_PTR(ret);
	383	}
	384	EXPORT_SYMBOL_GPL(ci13xxx_add_device);
	385
	386	void ci13xxx_remove_device(struct platform_device *pdev)
	387	{
	388	platform_device_unregister(pdev);
fe6e125e	389	ida_simple_remove(&ci_ida, pdev->id);
cbc6dc2a RZ	390	}
	391	EXPORT_SYMBOL_GPL(ci13xxx_remove_device);
	392
41ac7b3a	393	static int ci_hdrc_probe(struct platform_device *pdev)
e443b333 AS	394	{
e443b333 AS	395	struct device *dev = &pdev->dev;
5f36e231	396	struct ci13xxx *ci;
e443b333 AS	397	struct resource *res;
	398	void __iomem *base;
	399	int ret;
	400
5f36e231	401	if (!dev->platform_data) {
e443b333 AS	402	dev_err(dev, "platform data missing\n");
	403	return -ENODEV;
	404	}
	405
	406	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	407	if (!res) {
	408	dev_err(dev, "missing resource\n");
	409	return -ENODEV;
	410	}
	411
	412	base = devm_request_and_ioremap(dev, res);
	413	if (!res) {
	414	dev_err(dev, "can't request and ioremap resource\n");
	415	return -ENOMEM;
	416	}
	417
5f36e231 AS	418	ci = devm_kzalloc(dev, sizeof(*ci), GFP_KERNEL);
	419	if (!ci) {
	420	dev_err(dev, "can't allocate device\n");
	421	return -ENOMEM;
	422	}
	423
	424	ci->dev = dev;
77c4400f	425	ci->platdata = dev->platform_data;
a2c3d690 RZ	426	if (ci->platdata->phy)
	427	ci->transceiver = ci->platdata->phy;
	428	else
	429	ci->global_phy = true;
5f36e231 AS	430
	431	ret = hw_device_init(ci, base);
	432	if (ret < 0) {
	433	dev_err(dev, "can't initialize hardware\n");
	434	return -ENODEV;
	435	}
e443b333	436
eb70e5ab AS	437	ci->hw_bank.phys = res->start;
eb70e5ab AS	438
5f36e231 AS	439	ci->irq = platform_get_irq(pdev, 0);
5f36e231 AS	440	if (ci->irq < 0) {
e443b333	441	dev_err(dev, "missing IRQ\n");
5f36e231 AS	442	return -ENODEV;
	443	}
	444
	445	INIT_WORK(&ci->work, ci_role_work);
	446	ci->wq = create_singlethread_workqueue("ci_otg");
	447	if (!ci->wq) {
	448	dev_err(dev, "can't create workqueue\n");
	449	return -ENODEV;
	450	}
	451
	452	/* initialize role(s) before the interrupt is requested */
eb70e5ab AS	453	ret = ci_hdrc_host_init(ci);
	454	if (ret)
	455	dev_info(dev, "doesn't support host\n");
	456
5f36e231 AS	457	ret = ci_hdrc_gadget_init(ci);
	458	if (ret)
	459	dev_info(dev, "doesn't support gadget\n");
	460
	461	if (!ci->roles[CI_ROLE_HOST] && !ci->roles[CI_ROLE_GADGET]) {
	462	dev_err(dev, "no supported roles\n");
	463	ret = -ENODEV;
	464	goto rm_wq;
	465	}
	466
	467	if (ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET]) {
	468	ci->is_otg = true;
86ad01a9 RZ	469	/* ID pin needs 1ms debouce time, we delay 2ms for safe */
86ad01a9 RZ	470	mdelay(2);
5f36e231 AS	471	ci->role = ci_otg_role(ci);
	472	} else {
	473	ci->role = ci->roles[CI_ROLE_HOST]
	474	? CI_ROLE_HOST
	475	: CI_ROLE_GADGET;
	476	}
	477
	478	ret = ci_role_start(ci, ci->role);
	479	if (ret) {
	480	dev_err(dev, "can't start %s role\n", ci_role(ci)->name);
e443b333	481	ret = -ENODEV;
5f36e231	482	goto rm_wq;
e443b333 AS	483	}
e443b333 AS	484
5f36e231	485	platform_set_drvdata(pdev, ci);
77c4400f	486	ret = request_irq(ci->irq, ci_irq, IRQF_SHARED, ci->platdata->name,
5f36e231 AS	487	ci);
	488	if (ret)
	489	goto stop;
e443b333	490
5f36e231	491	ret = device_create_file(dev, &dev_attr_role);
e443b333	492	if (ret)
5f36e231 AS	493	goto rm_attr;
	494
	495	if (ci->is_otg)
	496	hw_write(ci, OP_OTGSC, OTGSC_IDIE, OTGSC_IDIE);
	497
	498	return ret;
	499
	500	rm_attr:
	501	device_remove_file(dev, &dev_attr_role);
	502	stop:
	503	ci_role_stop(ci);
	504	rm_wq:
	505	flush_workqueue(ci->wq);
	506	destroy_workqueue(ci->wq);
e443b333 AS	507
	508	return ret;
	509	}
	510
fb4e98ab	511	static int ci_hdrc_remove(struct platform_device *pdev)
e443b333	512	{
5f36e231	513	struct ci13xxx *ci = platform_get_drvdata(pdev);
e443b333	514
5f36e231 AS	515	flush_workqueue(ci->wq);
	516	destroy_workqueue(ci->wq);
	517	device_remove_file(ci->dev, &dev_attr_role);
	518	free_irq(ci->irq, ci);
	519	ci_role_stop(ci);
e443b333 AS	520
	521	return 0;
	522	}
	523
5f36e231 AS	524	static struct platform_driver ci_hdrc_driver = {
5f36e231 AS	525	.probe = ci_hdrc_probe,
7690417d	526	.remove = ci_hdrc_remove,
e443b333	527	.driver = {
5f36e231	528	.name = "ci_hdrc",
e443b333 AS	529	},
	530	};
	531
5f36e231	532	module_platform_driver(ci_hdrc_driver);
e443b333	533
5f36e231	534	MODULE_ALIAS("platform:ci_hdrc");
e443b333 AS	535	MODULE_ALIAS("platform:ci13xxx");
	536	MODULE_LICENSE("GPL v2");
	537	MODULE_AUTHOR("David Lopo <dlopo@chipidea.mips.com>");
5f36e231	538	MODULE_DESCRIPTION("ChipIdea HDRC Driver");