[linux-2.6-block.git] / drivers / usb / chipidea / core.c

/*
 * core.c - ChipIdea USB IP core family device controller
 *
 * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
 *
 * Author: David Lopo
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

/*
 * Description: ChipIdea USB IP core family device controller
 *
 * This driver is composed of several blocks:
 * - HW:     hardware interface
 * - DBG:    debug facilities (optional)
 * - UTIL:   utilities
 * - ISR:    interrupts handling
 * - ENDPT:  endpoint operations (Gadget API)
 * - GADGET: gadget operations (Gadget API)
 * - BUS:    bus glue code, bus abstraction layer
 *
 * Compile Options
 * - CONFIG_USB_GADGET_DEBUG_FILES: enable debug facilities
 * - STALL_IN:  non-empty bulk-in pipes cannot be halted
 *              if defined mass storage compliance succeeds but with warnings
 *              => case 4: Hi >  Dn
 *              => case 5: Hi >  Di
 *              => case 8: Hi <> Do
 *              if undefined usbtest 13 fails
 * - TRACE:     enable function tracing (depends on DEBUG)
 *
 * Main Features
 * - Chapter 9 & Mass Storage Compliance with Gadget File Storage
 * - Chapter 9 Compliance with Gadget Zero (STALL_IN undefined)
 * - Normal & LPM support
 *
 * USBTEST Report
 * - OK: 0-12, 13 (STALL_IN defined) & 14
 * - Not Supported: 15 & 16 (ISO)
 *
 * TODO List
 * - OTG
 * - Interrupt Traffic
 * - GET_STATUS(device) - always reports 0
 * - Gadget API (majority of optional features)
 * - Suspend & Remote Wakeup
 */
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/dma-mapping.h>
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/idr.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/pm_runtime.h>
#include <linux/usb/ch9.h>
#include <linux/usb/gadget.h>
#include <linux/usb/otg.h>
#include <linux/usb/chipidea.h>
#include <linux/usb/of.h>
#include <linux/phy.h>
#include <linux/regulator/consumer.h>

#include "ci.h"
#include "udc.h"
#include "bits.h"
#include "host.h"
#include "debug.h"
#include "otg.h"

/* Controller register map */
static const u8 ci_regs_nolpm[] = {
	[CAP_CAPLENGTH]		= 0x00U,
	[CAP_HCCPARAMS]		= 0x08U,
	[CAP_DCCPARAMS]		= 0x24U,
	[CAP_TESTMODE]		= 0x38U,
	[OP_USBCMD]		= 0x00U,
	[OP_USBSTS]		= 0x04U,
	[OP_USBINTR]		= 0x08U,
	[OP_DEVICEADDR]		= 0x14U,
	[OP_ENDPTLISTADDR]	= 0x18U,
	[OP_PORTSC]		= 0x44U,
	[OP_DEVLC]		= 0x84U,
	[OP_OTGSC]		= 0x64U,
	[OP_USBMODE]		= 0x68U,
	[OP_ENDPTSETUPSTAT]	= 0x6CU,
	[OP_ENDPTPRIME]		= 0x70U,
	[OP_ENDPTFLUSH]		= 0x74U,
	[OP_ENDPTSTAT]		= 0x78U,
	[OP_ENDPTCOMPLETE]	= 0x7CU,
	[OP_ENDPTCTRL]		= 0x80U,
};

static const u8 ci_regs_lpm[] = {
	[CAP_CAPLENGTH]		= 0x00U,
	[CAP_HCCPARAMS]		= 0x08U,
	[CAP_DCCPARAMS]		= 0x24U,
	[CAP_TESTMODE]		= 0xFCU,
	[OP_USBCMD]		= 0x00U,
	[OP_USBSTS]		= 0x04U,
	[OP_USBINTR]		= 0x08U,
	[OP_DEVICEADDR]		= 0x14U,
	[OP_ENDPTLISTADDR]	= 0x18U,
	[OP_PORTSC]		= 0x44U,
	[OP_DEVLC]		= 0x84U,
	[OP_OTGSC]		= 0xC4U,
	[OP_USBMODE]		= 0xC8U,
	[OP_ENDPTSETUPSTAT]	= 0xD8U,
	[OP_ENDPTPRIME]		= 0xDCU,
	[OP_ENDPTFLUSH]		= 0xE0U,
	[OP_ENDPTSTAT]		= 0xE4U,
	[OP_ENDPTCOMPLETE]	= 0xE8U,
	[OP_ENDPTCTRL]		= 0xECU,
};

static int hw_alloc_regmap(struct ci_hdrc *ci, bool is_lpm)
{
	int i;

	for (i = 0; i < OP_ENDPTCTRL; i++)
		ci->hw_bank.regmap[i] =
			(i <= CAP_LAST ? ci->hw_bank.cap : ci->hw_bank.op) +
			(is_lpm ? ci_regs_lpm[i] : ci_regs_nolpm[i]);

	for (; i <= OP_LAST; i++)
		ci->hw_bank.regmap[i] = ci->hw_bank.op +
			4 * (i - OP_ENDPTCTRL) +
			(is_lpm
			 ? ci_regs_lpm[OP_ENDPTCTRL]
			 : ci_regs_nolpm[OP_ENDPTCTRL]);

	return 0;
}

/**
 * hw_port_test_set: writes port test mode (execute without interruption)
 * @mode: new value
 *
 * This function returns an error code
 */
int hw_port_test_set(struct ci_hdrc *ci, u8 mode)
{
	const u8 TEST_MODE_MAX = 7;

	if (mode > TEST_MODE_MAX)
		return -EINVAL;

	hw_write(ci, OP_PORTSC, PORTSC_PTC, mode << __ffs(PORTSC_PTC));
	return 0;
}

/**
 * hw_port_test_get: reads port test mode value
 *
 * This function returns port test mode value
 */
u8 hw_port_test_get(struct ci_hdrc *ci)
{
	return hw_read(ci, OP_PORTSC, PORTSC_PTC) >> __ffs(PORTSC_PTC);
}

/* The PHY enters/leaves low power mode */
static void ci_hdrc_enter_lpm(struct ci_hdrc *ci, bool enable)
{
	enum ci_hw_regs reg = ci->hw_bank.lpm ? OP_DEVLC : OP_PORTSC;
	bool lpm = !!(hw_read(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm)));

	if (enable && !lpm) {
		hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm),
				PORTSC_PHCD(ci->hw_bank.lpm));
	} else  if (!enable && lpm) {
		hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm),
				0);
		/* 
		 * The controller needs at least 1ms to reflect
		 * PHY's status, the PHY also needs some time (less
		 * than 1ms) to leave low power mode.
		 */
		usleep_range(1500, 2000);
	}
}

static int hw_device_init(struct ci_hdrc *ci, void __iomem *base)
{
	u32 reg;

	/* bank is a module variable */
	ci->hw_bank.abs = base;

	ci->hw_bank.cap = ci->hw_bank.abs;
	ci->hw_bank.cap += ci->platdata->capoffset;
	ci->hw_bank.op = ci->hw_bank.cap + (ioread32(ci->hw_bank.cap) & 0xff);

	hw_alloc_regmap(ci, false);
	reg = hw_read(ci, CAP_HCCPARAMS, HCCPARAMS_LEN) >>
		__ffs(HCCPARAMS_LEN);
	ci->hw_bank.lpm  = reg;
	if (reg)
		hw_alloc_regmap(ci, !!reg);
	ci->hw_bank.size = ci->hw_bank.op - ci->hw_bank.abs;
	ci->hw_bank.size += OP_LAST;
	ci->hw_bank.size /= sizeof(u32);

	reg = hw_read(ci, CAP_DCCPARAMS, DCCPARAMS_DEN) >>
		__ffs(DCCPARAMS_DEN);
	ci->hw_ep_max = reg * 2;   /* cache hw ENDPT_MAX */

	if (ci->hw_ep_max > ENDPT_MAX)
		return -ENODEV;

	ci_hdrc_enter_lpm(ci, false);

	/* Disable all interrupts bits */
	hw_write(ci, OP_USBINTR, 0xffffffff, 0);

	/* Clear all interrupts status bits*/
	hw_write(ci, OP_USBSTS, 0xffffffff, 0xffffffff);

	dev_dbg(ci->dev, "ChipIdea HDRC found, lpm: %d; cap: %p op: %p\n",
		ci->hw_bank.lpm, ci->hw_bank.cap, ci->hw_bank.op);

	/* setup lock mode ? */

	/* ENDPTSETUPSTAT is '0' by default */

	/* HCSPARAMS.bf.ppc SHOULD BE zero for device */

	return 0;
}

static void hw_phymode_configure(struct ci_hdrc *ci)
{
	u32 portsc, lpm, sts = 0;

	switch (ci->platdata->phy_mode) {
	case USBPHY_INTERFACE_MODE_UTMI:
		portsc = PORTSC_PTS(PTS_UTMI);
		lpm = DEVLC_PTS(PTS_UTMI);
		break;
	case USBPHY_INTERFACE_MODE_UTMIW:
		portsc = PORTSC_PTS(PTS_UTMI) | PORTSC_PTW;
		lpm = DEVLC_PTS(PTS_UTMI) | DEVLC_PTW;
		break;
	case USBPHY_INTERFACE_MODE_ULPI:
		portsc = PORTSC_PTS(PTS_ULPI);
		lpm = DEVLC_PTS(PTS_ULPI);
		break;
	case USBPHY_INTERFACE_MODE_SERIAL:
		portsc = PORTSC_PTS(PTS_SERIAL);
		lpm = DEVLC_PTS(PTS_SERIAL);
		sts = 1;
		break;
	case USBPHY_INTERFACE_MODE_HSIC:
		portsc = PORTSC_PTS(PTS_HSIC);
		lpm = DEVLC_PTS(PTS_HSIC);
		break;
	default:
		return;
	}

	if (ci->hw_bank.lpm) {
		hw_write(ci, OP_DEVLC, DEVLC_PTS(7) | DEVLC_PTW, lpm);
		if (sts)
			hw_write(ci, OP_DEVLC, DEVLC_STS, DEVLC_STS);
	} else {
		hw_write(ci, OP_PORTSC, PORTSC_PTS(7) | PORTSC_PTW, portsc);
		if (sts)
			hw_write(ci, OP_PORTSC, PORTSC_STS, PORTSC_STS);
	}
}

/**
 * hw_device_reset: resets chip (execute without interruption)
 * @ci: the controller
  *
 * This function returns an error code
 */
int hw_device_reset(struct ci_hdrc *ci, u32 mode)
{
	/* should flush & stop before reset */
	hw_write(ci, OP_ENDPTFLUSH, ~0, ~0);
	hw_write(ci, OP_USBCMD, USBCMD_RS, 0);

	hw_write(ci, OP_USBCMD, USBCMD_RST, USBCMD_RST);
	while (hw_read(ci, OP_USBCMD, USBCMD_RST))
		udelay(10);		/* not RTOS friendly */

	if (ci->platdata->notify_event)
		ci->platdata->notify_event(ci,
			CI_HDRC_CONTROLLER_RESET_EVENT);

	if (ci->platdata->flags & CI_HDRC_DISABLE_STREAMING)
		hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS, USBMODE_CI_SDIS);

	/* USBMODE should be configured step by step */
	hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE);
	hw_write(ci, OP_USBMODE, USBMODE_CM, mode);
	/* HW >= 2.3 */
	hw_write(ci, OP_USBMODE, USBMODE_SLOM, USBMODE_SLOM);

	if (hw_read(ci, OP_USBMODE, USBMODE_CM) != mode) {
		pr_err("cannot enter in %s mode", ci_role(ci)->name);
		pr_err("lpm = %i", ci->hw_bank.lpm);
		return -ENODEV;
	}

	return 0;
}

/**
 * hw_wait_reg: wait the register value
 *
 * Sometimes, it needs to wait register value before going on.
 * Eg, when switch to device mode, the vbus value should be lower
 * than OTGSC_BSV before connects to host.
 *
 * @ci: the controller
 * @reg: register index
 * @mask: mast bit
 * @value: the bit value to wait
 * @timeout_ms: timeout in millisecond
 *
 * This function returns an error code if timeout
 */
int hw_wait_reg(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask,
				u32 value, unsigned int timeout_ms)
{
	unsigned long elapse = jiffies + msecs_to_jiffies(timeout_ms);

	while (hw_read(ci, reg, mask) != value) {
		if (time_after(jiffies, elapse)) {
			dev_err(ci->dev, "timeout waiting for %08x in %d\n",
					mask, reg);
			return -ETIMEDOUT;
		}
		msleep(20);
	}

	return 0;
}

static irqreturn_t ci_irq(int irq, void *data)
{
	struct ci_hdrc *ci = data;
	irqreturn_t ret = IRQ_NONE;
	u32 otgsc = 0;

	if (ci->is_otg)
		otgsc = hw_read(ci, OP_OTGSC, ~0);

	/*
	 * Handle id change interrupt, it indicates device/host function
	 * switch.
	 */
	if (ci->is_otg && (otgsc & OTGSC_IDIE) && (otgsc & OTGSC_IDIS)) {
		ci->id_event = true;
		ci_clear_otg_interrupt(ci, OTGSC_IDIS);
		disable_irq_nosync(ci->irq);
		queue_work(ci->wq, &ci->work);
		return IRQ_HANDLED;
	}

	/*
	 * Handle vbus change interrupt, it indicates device connection
	 * and disconnection events.
	 */
	if (ci->is_otg && (otgsc & OTGSC_BSVIE) && (otgsc & OTGSC_BSVIS)) {
		ci->b_sess_valid_event = true;
		ci_clear_otg_interrupt(ci, OTGSC_BSVIS);
		disable_irq_nosync(ci->irq);
		queue_work(ci->wq, &ci->work);
		return IRQ_HANDLED;
	}

	/* Handle device/host interrupt */
	if (ci->role != CI_ROLE_END)
		ret = ci_role(ci)->irq(ci);

	return ret;
}

static int ci_get_platdata(struct device *dev,
		struct ci_hdrc_platform_data *platdata)
{
	if (!platdata->phy_mode)
		platdata->phy_mode = of_usb_get_phy_mode(dev->of_node);

	if (!platdata->dr_mode)
		platdata->dr_mode = of_usb_get_dr_mode(dev->of_node);

	if (platdata->dr_mode == USB_DR_MODE_UNKNOWN)
		platdata->dr_mode = USB_DR_MODE_OTG;

	if (platdata->dr_mode != USB_DR_MODE_PERIPHERAL) {
		/* Get the vbus regulator */
		platdata->reg_vbus = devm_regulator_get(dev, "vbus");
		if (PTR_ERR(platdata->reg_vbus) == -EPROBE_DEFER) {
			return -EPROBE_DEFER;
		} else if (PTR_ERR(platdata->reg_vbus) == -ENODEV) {
			/* no vbus regualator is needed */
			platdata->reg_vbus = NULL;
		} else if (IS_ERR(platdata->reg_vbus)) {
			dev_err(dev, "Getting regulator error: %ld\n",
				PTR_ERR(platdata->reg_vbus));
			return PTR_ERR(platdata->reg_vbus);
		}
	}

	return 0;
}

static DEFINE_IDA(ci_ida);

struct platform_device *ci_hdrc_add_device(struct device *dev,
			struct resource *res, int nres,
			struct ci_hdrc_platform_data *platdata)
{
	struct platform_device *pdev;
	int id, ret;

	ret = ci_get_platdata(dev, platdata);
	if (ret)
		return ERR_PTR(ret);

	id = ida_simple_get(&ci_ida, 0, 0, GFP_KERNEL);
	if (id < 0)
		return ERR_PTR(id);

	pdev = platform_device_alloc("ci_hdrc", id);
	if (!pdev) {
		ret = -ENOMEM;
		goto put_id;
	}

	pdev->dev.parent = dev;
	pdev->dev.dma_mask = dev->dma_mask;
	pdev->dev.dma_parms = dev->dma_parms;
	dma_set_coherent_mask(&pdev->dev, dev->coherent_dma_mask);

	ret = platform_device_add_resources(pdev, res, nres);
	if (ret)
		goto err;

	ret = platform_device_add_data(pdev, platdata, sizeof(*platdata));
	if (ret)
		goto err;

	ret = platform_device_add(pdev);
	if (ret)
		goto err;

	return pdev;

err:
	platform_device_put(pdev);
put_id:
	ida_simple_remove(&ci_ida, id);
	return ERR_PTR(ret);
}
EXPORT_SYMBOL_GPL(ci_hdrc_add_device);

void ci_hdrc_remove_device(struct platform_device *pdev)
{
	int id = pdev->id;
	platform_device_unregister(pdev);
	ida_simple_remove(&ci_ida, id);
}
EXPORT_SYMBOL_GPL(ci_hdrc_remove_device);

static inline void ci_role_destroy(struct ci_hdrc *ci)
{
	ci_hdrc_gadget_destroy(ci);
	ci_hdrc_host_destroy(ci);
	if (ci->is_otg)
		ci_hdrc_otg_destroy(ci);
}

static void ci_get_otg_capable(struct ci_hdrc *ci)
{
	if (ci->platdata->flags & CI_HDRC_DUAL_ROLE_NOT_OTG)
		ci->is_otg = false;
	else
		ci->is_otg = (hw_read(ci, CAP_DCCPARAMS,
				DCCPARAMS_DC | DCCPARAMS_HC)
					== (DCCPARAMS_DC | DCCPARAMS_HC));
	if (ci->is_otg) {
		dev_dbg(ci->dev, "It is OTG capable controller\n");
		ci_disable_otg_interrupt(ci, OTGSC_INT_EN_BITS);
		ci_clear_otg_interrupt(ci, OTGSC_INT_STATUS_BITS);
	}
}

static int ci_hdrc_probe(struct platform_device *pdev)
{
	struct device	*dev = &pdev->dev;
	struct ci_hdrc	*ci;
	struct resource	*res;
	void __iomem	*base;
	int		ret;
	enum usb_dr_mode dr_mode;

	if (!dev_get_platdata(dev)) {
		dev_err(dev, "platform data missing\n");
		return -ENODEV;
	}

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	base = devm_ioremap_resource(dev, res);
	if (IS_ERR(base))
		return PTR_ERR(base);

	ci = devm_kzalloc(dev, sizeof(*ci), GFP_KERNEL);
	if (!ci) {
		dev_err(dev, "can't allocate device\n");
		return -ENOMEM;
	}

	ci->dev = dev;
	ci->platdata = dev_get_platdata(dev);
	ci->imx28_write_fix = !!(ci->platdata->flags &
		CI_HDRC_IMX28_WRITE_FIX);

	ret = hw_device_init(ci, base);
	if (ret < 0) {
		dev_err(dev, "can't initialize hardware\n");
		return -ENODEV;
	}

	hw_phymode_configure(ci);

	if (ci->platdata->phy)
		ci->transceiver = ci->platdata->phy;
	else
		ci->transceiver = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);

	if (IS_ERR(ci->transceiver)) {
		ret = PTR_ERR(ci->transceiver);
		/*
		 * if -ENXIO is returned, it means PHY layer wasn't
		 * enabled, so it makes no sense to return -EPROBE_DEFER
		 * in that case, since no PHY driver will ever probe.
		 */
		if (ret == -ENXIO)
			return ret;

		dev_err(dev, "no usb2 phy configured\n");
		return -EPROBE_DEFER;
	}

	ret = usb_phy_init(ci->transceiver);
	if (ret) {
		dev_err(dev, "unable to init phy: %d\n", ret);
		return ret;
	}

	ci->hw_bank.phys = res->start;

	ci->irq = platform_get_irq(pdev, 0);
	if (ci->irq < 0) {
		dev_err(dev, "missing IRQ\n");
		ret = -ENODEV;
		goto deinit_phy;
	}

	ci_get_otg_capable(ci);

	dr_mode = ci->platdata->dr_mode;
	/* initialize role(s) before the interrupt is requested */
	if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_HOST) {
		ret = ci_hdrc_host_init(ci);
		if (ret)
			dev_info(dev, "doesn't support host\n");
	}

	if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_PERIPHERAL) {
		ret = ci_hdrc_gadget_init(ci);
		if (ret)
			dev_info(dev, "doesn't support gadget\n");
	}

	if (!ci->roles[CI_ROLE_HOST] && !ci->roles[CI_ROLE_GADGET]) {
		dev_err(dev, "no supported roles\n");
		ret = -ENODEV;
		goto deinit_phy;
	}

	if (ci->is_otg) {
		ret = ci_hdrc_otg_init(ci);
		if (ret) {
			dev_err(dev, "init otg fails, ret = %d\n", ret);
			goto stop;
		}
	}

	if (ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET]) {
		if (ci->is_otg) {
			/*
			 * ID pin needs 1ms debouce time,
			 * we delay 2ms for safe.
			 */
			mdelay(2);
			ci->role = ci_otg_role(ci);
			ci_enable_otg_interrupt(ci, OTGSC_IDIE);
		} else {
			/*
			 * If the controller is not OTG capable, but support
			 * role switch, the defalt role is gadget, and the
			 * user can switch it through debugfs.
			 */
			ci->role = CI_ROLE_GADGET;
		}
	} else {
		ci->role = ci->roles[CI_ROLE_HOST]
			? CI_ROLE_HOST
			: CI_ROLE_GADGET;
	}

	/* only update vbus status for peripheral */
	if (ci->role == CI_ROLE_GADGET)
		ci_handle_vbus_change(ci);

	ret = ci_role_start(ci, ci->role);
	if (ret) {
		dev_err(dev, "can't start %s role\n", ci_role(ci)->name);
		goto stop;
	}

	platform_set_drvdata(pdev, ci);
	ret = request_irq(ci->irq, ci_irq, IRQF_SHARED, ci->platdata->name,
			  ci);
	if (ret)
		goto stop;

	ret = dbg_create_files(ci);
	if (!ret)
		return 0;

	free_irq(ci->irq, ci);
stop:
	ci_role_destroy(ci);
deinit_phy:
	usb_phy_shutdown(ci->transceiver);

	return ret;
}

static int ci_hdrc_remove(struct platform_device *pdev)
{
	struct ci_hdrc *ci = platform_get_drvdata(pdev);

	dbg_remove_files(ci);
	free_irq(ci->irq, ci);
	ci_role_destroy(ci);
	ci_hdrc_enter_lpm(ci, true);
	usb_phy_shutdown(ci->transceiver);
	kfree(ci->hw_bank.regmap);

	return 0;
}

static struct platform_driver ci_hdrc_driver = {
	.probe	= ci_hdrc_probe,
	.remove	= ci_hdrc_remove,
	.driver	= {
		.name	= "ci_hdrc",
	},
};

module_platform_driver(ci_hdrc_driver);

MODULE_ALIAS("platform:ci_hdrc");
MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("David Lopo <dlopo@chipidea.mips.com>");
MODULE_DESCRIPTION("ChipIdea HDRC Driver");
Commit	Line	Data
e443b333 AS	1	/*
	2	* core.c - ChipIdea USB IP core family device controller
	3	*
	4	* Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
	5	*
	6	* Author: David Lopo
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*/
	12
	13	/*
	14	* Description: ChipIdea USB IP core family device controller
	15	*
	16	* This driver is composed of several blocks:
	17	* - HW: hardware interface
	18	* - DBG: debug facilities (optional)
	19	* - UTIL: utilities
	20	* - ISR: interrupts handling
	21	* - ENDPT: endpoint operations (Gadget API)
	22	* - GADGET: gadget operations (Gadget API)
	23	* - BUS: bus glue code, bus abstraction layer
	24	*
	25	* Compile Options
	26	* - CONFIG_USB_GADGET_DEBUG_FILES: enable debug facilities
	27	* - STALL_IN: non-empty bulk-in pipes cannot be halted
	28	* if defined mass storage compliance succeeds but with warnings
	29	* => case 4: Hi > Dn
	30	* => case 5: Hi > Di
	31	* => case 8: Hi <> Do
	32	* if undefined usbtest 13 fails
	33	* - TRACE: enable function tracing (depends on DEBUG)
	34	*
	35	* Main Features
	36	* - Chapter 9 & Mass Storage Compliance with Gadget File Storage
	37	* - Chapter 9 Compliance with Gadget Zero (STALL_IN undefined)
	38	* - Normal & LPM support
	39	*
	40	* USBTEST Report
	41	* - OK: 0-12, 13 (STALL_IN defined) & 14
	42	* - Not Supported: 15 & 16 (ISO)
	43	*
	44	* TODO List
	45	* - OTG
e4ce4ecd	46	* - Interrupt Traffic
e443b333 AS	47	* - GET_STATUS(device) - always reports 0
	48	* - Gadget API (majority of optional features)
	49	* - Suspend & Remote Wakeup
	50	*/
	51	#include <linux/delay.h>
	52	#include <linux/device.h>
e443b333	53	#include <linux/dma-mapping.h>
e443b333 AS	54	#include <linux/platform_device.h>
e443b333 AS	55	#include <linux/module.h>
fe6e125e	56	#include <linux/idr.h>
e443b333 AS	57	#include <linux/interrupt.h>
e443b333 AS	58	#include <linux/io.h>
e443b333 AS	59	#include <linux/kernel.h>
	60	#include <linux/slab.h>
	61	#include <linux/pm_runtime.h>
	62	#include <linux/usb/ch9.h>
	63	#include <linux/usb/gadget.h>
	64	#include <linux/usb/otg.h>
	65	#include <linux/usb/chipidea.h>
40dcd0e8 MG	66	#include <linux/usb/of.h>
40dcd0e8 MG	67	#include <linux/phy.h>
1542d9c3	68	#include <linux/regulator/consumer.h>
e443b333 AS	69
	70	#include "ci.h"
	71	#include "udc.h"
	72	#include "bits.h"
eb70e5ab	73	#include "host.h"
e443b333	74	#include "debug.h"
c10b4f03	75	#include "otg.h"
e443b333	76
5f36e231	77	/* Controller register map */
987e7bc3 MKB	78	static const u8 ci_regs_nolpm[] = {
	79	[CAP_CAPLENGTH] = 0x00U,
	80	[CAP_HCCPARAMS] = 0x08U,
	81	[CAP_DCCPARAMS] = 0x24U,
	82	[CAP_TESTMODE] = 0x38U,
	83	[OP_USBCMD] = 0x00U,
	84	[OP_USBSTS] = 0x04U,
	85	[OP_USBINTR] = 0x08U,
	86	[OP_DEVICEADDR] = 0x14U,
	87	[OP_ENDPTLISTADDR] = 0x18U,
	88	[OP_PORTSC] = 0x44U,
	89	[OP_DEVLC] = 0x84U,
	90	[OP_OTGSC] = 0x64U,
	91	[OP_USBMODE] = 0x68U,
	92	[OP_ENDPTSETUPSTAT] = 0x6CU,
	93	[OP_ENDPTPRIME] = 0x70U,
	94	[OP_ENDPTFLUSH] = 0x74U,
	95	[OP_ENDPTSTAT] = 0x78U,
	96	[OP_ENDPTCOMPLETE] = 0x7CU,
	97	[OP_ENDPTCTRL] = 0x80U,
e443b333 AS	98	};
e443b333 AS	99
987e7bc3 MKB	100	static const u8 ci_regs_lpm[] = {
	101	[CAP_CAPLENGTH] = 0x00U,
	102	[CAP_HCCPARAMS] = 0x08U,
	103	[CAP_DCCPARAMS] = 0x24U,
	104	[CAP_TESTMODE] = 0xFCU,
	105	[OP_USBCMD] = 0x00U,
	106	[OP_USBSTS] = 0x04U,
	107	[OP_USBINTR] = 0x08U,
	108	[OP_DEVICEADDR] = 0x14U,
	109	[OP_ENDPTLISTADDR] = 0x18U,
	110	[OP_PORTSC] = 0x44U,
	111	[OP_DEVLC] = 0x84U,
	112	[OP_OTGSC] = 0xC4U,
	113	[OP_USBMODE] = 0xC8U,
	114	[OP_ENDPTSETUPSTAT] = 0xD8U,
	115	[OP_ENDPTPRIME] = 0xDCU,
	116	[OP_ENDPTFLUSH] = 0xE0U,
	117	[OP_ENDPTSTAT] = 0xE4U,
	118	[OP_ENDPTCOMPLETE] = 0xE8U,
	119	[OP_ENDPTCTRL] = 0xECU,
e443b333 AS	120	};
e443b333 AS	121
8e22978c	122	static int hw_alloc_regmap(struct ci_hdrc *ci, bool is_lpm)
e443b333 AS	123	{
	124	int i;
	125
e443b333	126	for (i = 0; i < OP_ENDPTCTRL; i++)
5f36e231 AS	127	ci->hw_bank.regmap[i] =
5f36e231 AS	128	(i <= CAP_LAST ? ci->hw_bank.cap : ci->hw_bank.op) +
e443b333 AS	129	(is_lpm ? ci_regs_lpm[i] : ci_regs_nolpm[i]);
	130
	131	for (; i <= OP_LAST; i++)
5f36e231	132	ci->hw_bank.regmap[i] = ci->hw_bank.op +
e443b333 AS	133	4 * (i - OP_ENDPTCTRL) +
	134	(is_lpm
	135	? ci_regs_lpm[OP_ENDPTCTRL]
	136	: ci_regs_nolpm[OP_ENDPTCTRL]);
	137
	138	return 0;
	139	}
	140
	141	/**
	142	* hw_port_test_set: writes port test mode (execute without interruption)
	143	* @mode: new value
	144	*
	145	* This function returns an error code
	146	*/
8e22978c	147	int hw_port_test_set(struct ci_hdrc *ci, u8 mode)
e443b333 AS	148	{
	149	const u8 TEST_MODE_MAX = 7;
	150
	151	if (mode > TEST_MODE_MAX)
	152	return -EINVAL;
	153
727b4ddb	154	hw_write(ci, OP_PORTSC, PORTSC_PTC, mode << __ffs(PORTSC_PTC));
e443b333 AS	155	return 0;
	156	}
	157
	158	/**
	159	* hw_port_test_get: reads port test mode value
	160	*
	161	* This function returns port test mode value
	162	*/
8e22978c	163	u8 hw_port_test_get(struct ci_hdrc *ci)
e443b333	164	{
727b4ddb	165	return hw_read(ci, OP_PORTSC, PORTSC_PTC) >> __ffs(PORTSC_PTC);
e443b333 AS	166	}
e443b333 AS	167
864cf949 PC	168	/* The PHY enters/leaves low power mode */
	169	static void ci_hdrc_enter_lpm(struct ci_hdrc *ci, bool enable)
	170	{
	171	enum ci_hw_regs reg = ci->hw_bank.lpm ? OP_DEVLC : OP_PORTSC;
	172	bool lpm = !!(hw_read(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm)));
	173
	174	if (enable && !lpm) {
	175	hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm),
	176	PORTSC_PHCD(ci->hw_bank.lpm));
	177	} else if (!enable && lpm) {
	178	hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm),
	179	0);
	180	/*
	181	* The controller needs at least 1ms to reflect
	182	* PHY's status, the PHY also needs some time (less
	183	* than 1ms) to leave low power mode.
	184	*/
	185	usleep_range(1500, 2000);
	186	}
	187	}
	188
8e22978c	189	static int hw_device_init(struct ci_hdrc ci, void __iomem base)
e443b333 AS	190	{
	191	u32 reg;
	192
	193	/* bank is a module variable */
5f36e231	194	ci->hw_bank.abs = base;
e443b333	195
5f36e231	196	ci->hw_bank.cap = ci->hw_bank.abs;
77c4400f	197	ci->hw_bank.cap += ci->platdata->capoffset;
938d323f	198	ci->hw_bank.op = ci->hw_bank.cap + (ioread32(ci->hw_bank.cap) & 0xff);
e443b333	199
5f36e231 AS	200	hw_alloc_regmap(ci, false);
5f36e231 AS	201	reg = hw_read(ci, CAP_HCCPARAMS, HCCPARAMS_LEN) >>
727b4ddb	202	__ffs(HCCPARAMS_LEN);
5f36e231	203	ci->hw_bank.lpm = reg;
aeb2c121 CR	204	if (reg)
aeb2c121 CR	205	hw_alloc_regmap(ci, !!reg);
5f36e231 AS	206	ci->hw_bank.size = ci->hw_bank.op - ci->hw_bank.abs;
	207	ci->hw_bank.size += OP_LAST;
	208	ci->hw_bank.size /= sizeof(u32);
e443b333	209
5f36e231	210	reg = hw_read(ci, CAP_DCCPARAMS, DCCPARAMS_DEN) >>
727b4ddb	211	__ffs(DCCPARAMS_DEN);
5f36e231	212	ci->hw_ep_max = reg * 2; /* cache hw ENDPT_MAX */
e443b333	213
09c94e62	214	if (ci->hw_ep_max > ENDPT_MAX)
e443b333 AS	215	return -ENODEV;
e443b333 AS	216
864cf949 PC	217	ci_hdrc_enter_lpm(ci, false);
864cf949 PC	218
c344b518 PC	219	/* Disable all interrupts bits */
	220	hw_write(ci, OP_USBINTR, 0xffffffff, 0);
	221
	222	/* Clear all interrupts status bits*/
	223	hw_write(ci, OP_USBSTS, 0xffffffff, 0xffffffff);
	224
5f36e231 AS	225	dev_dbg(ci->dev, "ChipIdea HDRC found, lpm: %d; cap: %p op: %p\n",
5f36e231 AS	226	ci->hw_bank.lpm, ci->hw_bank.cap, ci->hw_bank.op);
e443b333 AS	227
	228	/* setup lock mode ? */
	229
	230	/* ENDPTSETUPSTAT is '0' by default */
	231
	232	/* HCSPARAMS.bf.ppc SHOULD BE zero for device */
	233
	234	return 0;
	235	}
	236
8e22978c	237	static void hw_phymode_configure(struct ci_hdrc *ci)
40dcd0e8	238	{
3b5d3e68	239	u32 portsc, lpm, sts = 0;
40dcd0e8 MG	240
	241	switch (ci->platdata->phy_mode) {
	242	case USBPHY_INTERFACE_MODE_UTMI:
	243	portsc = PORTSC_PTS(PTS_UTMI);
	244	lpm = DEVLC_PTS(PTS_UTMI);
	245	break;
	246	case USBPHY_INTERFACE_MODE_UTMIW:
	247	portsc = PORTSC_PTS(PTS_UTMI) \| PORTSC_PTW;
	248	lpm = DEVLC_PTS(PTS_UTMI) \| DEVLC_PTW;
	249	break;
	250	case USBPHY_INTERFACE_MODE_ULPI:
	251	portsc = PORTSC_PTS(PTS_ULPI);
	252	lpm = DEVLC_PTS(PTS_ULPI);
	253	break;
	254	case USBPHY_INTERFACE_MODE_SERIAL:
	255	portsc = PORTSC_PTS(PTS_SERIAL);
	256	lpm = DEVLC_PTS(PTS_SERIAL);
	257	sts = 1;
	258	break;
	259	case USBPHY_INTERFACE_MODE_HSIC:
	260	portsc = PORTSC_PTS(PTS_HSIC);
	261	lpm = DEVLC_PTS(PTS_HSIC);
	262	break;
	263	default:
	264	return;
	265	}
	266
	267	if (ci->hw_bank.lpm) {
	268	hw_write(ci, OP_DEVLC, DEVLC_PTS(7) \| DEVLC_PTW, lpm);
3b5d3e68 CR	269	if (sts)
3b5d3e68 CR	270	hw_write(ci, OP_DEVLC, DEVLC_STS, DEVLC_STS);
40dcd0e8 MG	271	} else {
40dcd0e8 MG	272	hw_write(ci, OP_PORTSC, PORTSC_PTS(7) \| PORTSC_PTW, portsc);
3b5d3e68 CR	273	if (sts)
3b5d3e68 CR	274	hw_write(ci, OP_PORTSC, PORTSC_STS, PORTSC_STS);
40dcd0e8 MG	275	}
	276	}
	277
e443b333 AS	278	/**
	279	* hw_device_reset: resets chip (execute without interruption)
	280	* @ci: the controller
	281	*
	282	* This function returns an error code
	283	*/
8e22978c	284	int hw_device_reset(struct ci_hdrc *ci, u32 mode)
e443b333 AS	285	{
	286	/* should flush & stop before reset */
	287	hw_write(ci, OP_ENDPTFLUSH, ~0, ~0);
	288	hw_write(ci, OP_USBCMD, USBCMD_RS, 0);
	289
	290	hw_write(ci, OP_USBCMD, USBCMD_RST, USBCMD_RST);
	291	while (hw_read(ci, OP_USBCMD, USBCMD_RST))
	292	udelay(10); /* not RTOS friendly */
	293
77c4400f RZ	294	if (ci->platdata->notify_event)
77c4400f RZ	295	ci->platdata->notify_event(ci,
8e22978c	296	CI_HDRC_CONTROLLER_RESET_EVENT);
e443b333	297
8e22978c	298	if (ci->platdata->flags & CI_HDRC_DISABLE_STREAMING)
758fc986	299	hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS, USBMODE_CI_SDIS);
e443b333 AS	300
	301	/* USBMODE should be configured step by step */
	302	hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE);
eb70e5ab	303	hw_write(ci, OP_USBMODE, USBMODE_CM, mode);
e443b333 AS	304	/* HW >= 2.3 */
	305	hw_write(ci, OP_USBMODE, USBMODE_SLOM, USBMODE_SLOM);
	306
eb70e5ab AS	307	if (hw_read(ci, OP_USBMODE, USBMODE_CM) != mode) {
eb70e5ab AS	308	pr_err("cannot enter in %s mode", ci_role(ci)->name);
e443b333 AS	309	pr_err("lpm = %i", ci->hw_bank.lpm);
	310	return -ENODEV;
	311	}
	312
	313	return 0;
	314	}
	315
22fa8445 PC	316	/**
	317	* hw_wait_reg: wait the register value
	318	*
	319	* Sometimes, it needs to wait register value before going on.
	320	* Eg, when switch to device mode, the vbus value should be lower
	321	* than OTGSC_BSV before connects to host.
	322	*
	323	* @ci: the controller
	324	* @reg: register index
	325	* @mask: mast bit
	326	* @value: the bit value to wait
	327	* @timeout_ms: timeout in millisecond
	328	*
	329	* This function returns an error code if timeout
	330	*/
	331	int hw_wait_reg(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask,
	332	u32 value, unsigned int timeout_ms)
	333	{
	334	unsigned long elapse = jiffies + msecs_to_jiffies(timeout_ms);
	335
	336	while (hw_read(ci, reg, mask) != value) {
	337	if (time_after(jiffies, elapse)) {
	338	dev_err(ci->dev, "timeout waiting for %08x in %d\n",
	339	mask, reg);
	340	return -ETIMEDOUT;
	341	}
	342	msleep(20);
	343	}
	344
	345	return 0;
	346	}
	347
5f36e231 AS	348	static irqreturn_t ci_irq(int irq, void *data)
5f36e231 AS	349	{
8e22978c	350	struct ci_hdrc *ci = data;
5f36e231	351	irqreturn_t ret = IRQ_NONE;
b183c19f	352	u32 otgsc = 0;
5f36e231	353
b183c19f RZ	354	if (ci->is_otg)
b183c19f RZ	355	otgsc = hw_read(ci, OP_OTGSC, ~0);
5f36e231	356
a107f8c5 PC	357	/*
	358	* Handle id change interrupt, it indicates device/host function
	359	* switch.
	360	*/
	361	if (ci->is_otg && (otgsc & OTGSC_IDIE) && (otgsc & OTGSC_IDIS)) {
	362	ci->id_event = true;
	363	ci_clear_otg_interrupt(ci, OTGSC_IDIS);
	364	disable_irq_nosync(ci->irq);
	365	queue_work(ci->wq, &ci->work);
	366	return IRQ_HANDLED;
	367	}
b183c19f	368
a107f8c5 PC	369	/*
	370	* Handle vbus change interrupt, it indicates device connection
	371	* and disconnection events.
	372	*/
	373	if (ci->is_otg && (otgsc & OTGSC_BSVIE) && (otgsc & OTGSC_BSVIS)) {
	374	ci->b_sess_valid_event = true;
	375	ci_clear_otg_interrupt(ci, OTGSC_BSVIS);
b183c19f RZ	376	disable_irq_nosync(ci->irq);
b183c19f RZ	377	queue_work(ci->wq, &ci->work);
a107f8c5	378	return IRQ_HANDLED;
5f36e231 AS	379	}
5f36e231 AS	380
a107f8c5 PC	381	/* Handle device/host interrupt */
	382	if (ci->role != CI_ROLE_END)
	383	ret = ci_role(ci)->irq(ci);
	384
b183c19f	385	return ret;
5f36e231 AS	386	}
5f36e231 AS	387
1542d9c3 PC	388	static int ci_get_platdata(struct device *dev,
	389	struct ci_hdrc_platform_data *platdata)
	390	{
c22600c3 PC	391	if (!platdata->phy_mode)
	392	platdata->phy_mode = of_usb_get_phy_mode(dev->of_node);
	393
	394	if (!platdata->dr_mode)
	395	platdata->dr_mode = of_usb_get_dr_mode(dev->of_node);
	396
	397	if (platdata->dr_mode == USB_DR_MODE_UNKNOWN)
	398	platdata->dr_mode = USB_DR_MODE_OTG;
	399
c2ec3a73 PC	400	if (platdata->dr_mode != USB_DR_MODE_PERIPHERAL) {
	401	/* Get the vbus regulator */
	402	platdata->reg_vbus = devm_regulator_get(dev, "vbus");
	403	if (PTR_ERR(platdata->reg_vbus) == -EPROBE_DEFER) {
	404	return -EPROBE_DEFER;
	405	} else if (PTR_ERR(platdata->reg_vbus) == -ENODEV) {
	406	/* no vbus regualator is needed */
	407	platdata->reg_vbus = NULL;
	408	} else if (IS_ERR(platdata->reg_vbus)) {
	409	dev_err(dev, "Getting regulator error: %ld\n",
	410	PTR_ERR(platdata->reg_vbus));
	411	return PTR_ERR(platdata->reg_vbus);
	412	}
	413	}
	414
1542d9c3 PC	415	return 0;
	416	}
	417
fe6e125e RZ	418	static DEFINE_IDA(ci_ida);
fe6e125e RZ	419
8e22978c	420	struct platform_device ci_hdrc_add_device(struct device dev,
cbc6dc2a	421	struct resource *res, int nres,
8e22978c	422	struct ci_hdrc_platform_data *platdata)
cbc6dc2a RZ	423	{
cbc6dc2a RZ	424	struct platform_device *pdev;
fe6e125e	425	int id, ret;
cbc6dc2a	426
1542d9c3 PC	427	ret = ci_get_platdata(dev, platdata);
	428	if (ret)
	429	return ERR_PTR(ret);
	430
fe6e125e RZ	431	id = ida_simple_get(&ci_ida, 0, 0, GFP_KERNEL);
	432	if (id < 0)
	433	return ERR_PTR(id);
	434
	435	pdev = platform_device_alloc("ci_hdrc", id);
	436	if (!pdev) {
	437	ret = -ENOMEM;
	438	goto put_id;
	439	}
cbc6dc2a RZ	440
	441	pdev->dev.parent = dev;
	442	pdev->dev.dma_mask = dev->dma_mask;
	443	pdev->dev.dma_parms = dev->dma_parms;
	444	dma_set_coherent_mask(&pdev->dev, dev->coherent_dma_mask);
	445
	446	ret = platform_device_add_resources(pdev, res, nres);
	447	if (ret)
	448	goto err;
	449
	450	ret = platform_device_add_data(pdev, platdata, sizeof(*platdata));
	451	if (ret)
	452	goto err;
	453
	454	ret = platform_device_add(pdev);
	455	if (ret)
	456	goto err;
	457
	458	return pdev;
	459
	460	err:
	461	platform_device_put(pdev);
fe6e125e RZ	462	put_id:
fe6e125e RZ	463	ida_simple_remove(&ci_ida, id);
cbc6dc2a RZ	464	return ERR_PTR(ret);
cbc6dc2a RZ	465	}
8e22978c	466	EXPORT_SYMBOL_GPL(ci_hdrc_add_device);
cbc6dc2a	467
8e22978c	468	void ci_hdrc_remove_device(struct platform_device *pdev)
cbc6dc2a	469	{
98c35534	470	int id = pdev->id;
cbc6dc2a	471	platform_device_unregister(pdev);
98c35534	472	ida_simple_remove(&ci_ida, id);
cbc6dc2a	473	}
8e22978c	474	EXPORT_SYMBOL_GPL(ci_hdrc_remove_device);
cbc6dc2a	475
3f124d23 PC	476	static inline void ci_role_destroy(struct ci_hdrc *ci)
	477	{
	478	ci_hdrc_gadget_destroy(ci);
	479	ci_hdrc_host_destroy(ci);
cbec6bd5 PC	480	if (ci->is_otg)
cbec6bd5 PC	481	ci_hdrc_otg_destroy(ci);
3f124d23 PC	482	}
3f124d23 PC	483
577b232f PC	484	static void ci_get_otg_capable(struct ci_hdrc *ci)
	485	{
	486	if (ci->platdata->flags & CI_HDRC_DUAL_ROLE_NOT_OTG)
	487	ci->is_otg = false;
	488	else
	489	ci->is_otg = (hw_read(ci, CAP_DCCPARAMS,
	490	DCCPARAMS_DC \| DCCPARAMS_HC)
	491	== (DCCPARAMS_DC \| DCCPARAMS_HC));
c344b518	492	if (ci->is_otg) {
577b232f	493	dev_dbg(ci->dev, "It is OTG capable controller\n");
c344b518 PC	494	ci_disable_otg_interrupt(ci, OTGSC_INT_EN_BITS);
	495	ci_clear_otg_interrupt(ci, OTGSC_INT_STATUS_BITS);
	496	}
577b232f PC	497	}
577b232f PC	498
41ac7b3a	499	static int ci_hdrc_probe(struct platform_device *pdev)
e443b333 AS	500	{
e443b333 AS	501	struct device *dev = &pdev->dev;
8e22978c	502	struct ci_hdrc *ci;
e443b333 AS	503	struct resource *res;
	504	void __iomem *base;
	505	int ret;
691962d1	506	enum usb_dr_mode dr_mode;
e443b333	507
fad56745	508	if (!dev_get_platdata(dev)) {
e443b333 AS	509	dev_err(dev, "platform data missing\n");
	510	return -ENODEV;
	511	}
	512
	513	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
19290816 FB	514	base = devm_ioremap_resource(dev, res);
	515	if (IS_ERR(base))
	516	return PTR_ERR(base);
e443b333	517
5f36e231 AS	518	ci = devm_kzalloc(dev, sizeof(*ci), GFP_KERNEL);
	519	if (!ci) {
	520	dev_err(dev, "can't allocate device\n");
	521	return -ENOMEM;
	522	}
	523
	524	ci->dev = dev;
fad56745	525	ci->platdata = dev_get_platdata(dev);
ed8f8318 PC	526	ci->imx28_write_fix = !!(ci->platdata->flags &
ed8f8318 PC	527	CI_HDRC_IMX28_WRITE_FIX);
5f36e231 AS	528
	529	ret = hw_device_init(ci, base);
	530	if (ret < 0) {
	531	dev_err(dev, "can't initialize hardware\n");
	532	return -ENODEV;
	533	}
e443b333	534
cd0b42c2 CR	535	hw_phymode_configure(ci);
cd0b42c2 CR	536
c859aa65 PC	537	if (ci->platdata->phy)
	538	ci->transceiver = ci->platdata->phy;
	539	else
	540	ci->transceiver = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
	541
	542	if (IS_ERR(ci->transceiver)) {
	543	ret = PTR_ERR(ci->transceiver);
	544	/*
	545	* if -ENXIO is returned, it means PHY layer wasn't
	546	* enabled, so it makes no sense to return -EPROBE_DEFER
	547	* in that case, since no PHY driver will ever probe.
	548	*/
	549	if (ret == -ENXIO)
	550	return ret;
	551
	552	dev_err(dev, "no usb2 phy configured\n");
	553	return -EPROBE_DEFER;
	554	}
	555
	556	ret = usb_phy_init(ci->transceiver);
74475ede PC	557	if (ret) {
	558	dev_err(dev, "unable to init phy: %d\n", ret);
	559	return ret;
	560	}
	561
eb70e5ab AS	562	ci->hw_bank.phys = res->start;
eb70e5ab AS	563
5f36e231 AS	564	ci->irq = platform_get_irq(pdev, 0);
5f36e231 AS	565	if (ci->irq < 0) {
e443b333	566	dev_err(dev, "missing IRQ\n");
74475ede	567	ret = -ENODEV;
c859aa65	568	goto deinit_phy;
5f36e231 AS	569	}
5f36e231 AS	570
577b232f PC	571	ci_get_otg_capable(ci);
577b232f PC	572
691962d1	573	dr_mode = ci->platdata->dr_mode;
5f36e231	574	/* initialize role(s) before the interrupt is requested */
691962d1 SH	575	if (dr_mode == USB_DR_MODE_OTG \|\| dr_mode == USB_DR_MODE_HOST) {
	576	ret = ci_hdrc_host_init(ci);
	577	if (ret)
	578	dev_info(dev, "doesn't support host\n");
	579	}
eb70e5ab	580
691962d1 SH	581	if (dr_mode == USB_DR_MODE_OTG \|\| dr_mode == USB_DR_MODE_PERIPHERAL) {
	582	ret = ci_hdrc_gadget_init(ci);
	583	if (ret)
	584	dev_info(dev, "doesn't support gadget\n");
	585	}
5f36e231 AS	586
	587	if (!ci->roles[CI_ROLE_HOST] && !ci->roles[CI_ROLE_GADGET]) {
	588	dev_err(dev, "no supported roles\n");
74475ede	589	ret = -ENODEV;
c859aa65	590	goto deinit_phy;
cbec6bd5 PC	591	}
	592
	593	if (ci->is_otg) {
	594	ret = ci_hdrc_otg_init(ci);
	595	if (ret) {
	596	dev_err(dev, "init otg fails, ret = %d\n", ret);
	597	goto stop;
	598	}
5f36e231 AS	599	}
	600
	601	if (ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET]) {
577b232f PC	602	if (ci->is_otg) {
	603	/*
	604	* ID pin needs 1ms debouce time,
	605	* we delay 2ms for safe.
	606	*/
	607	mdelay(2);
	608	ci->role = ci_otg_role(ci);
cbec6bd5	609	ci_enable_otg_interrupt(ci, OTGSC_IDIE);
577b232f PC	610	} else {
	611	/*
	612	* If the controller is not OTG capable, but support
	613	* role switch, the defalt role is gadget, and the
	614	* user can switch it through debugfs.
	615	*/
	616	ci->role = CI_ROLE_GADGET;
	617	}
5f36e231 AS	618	} else {
	619	ci->role = ci->roles[CI_ROLE_HOST]
	620	? CI_ROLE_HOST
	621	: CI_ROLE_GADGET;
	622	}
	623
5a1e1456 PC	624	/* only update vbus status for peripheral */
	625	if (ci->role == CI_ROLE_GADGET)
	626	ci_handle_vbus_change(ci);
	627
5f36e231 AS	628	ret = ci_role_start(ci, ci->role);
	629	if (ret) {
	630	dev_err(dev, "can't start %s role\n", ci_role(ci)->name);
cbec6bd5	631	goto stop;
e443b333 AS	632	}
e443b333 AS	633
5f36e231	634	platform_set_drvdata(pdev, ci);
77c4400f	635	ret = request_irq(ci->irq, ci_irq, IRQF_SHARED, ci->platdata->name,
5f36e231 AS	636	ci);
	637	if (ret)
	638	goto stop;
e443b333	639
adf0f735 AS	640	ret = dbg_create_files(ci);
	641	if (!ret)
	642	return 0;
5f36e231	643
adf0f735	644	free_irq(ci->irq, ci);
5f36e231	645	stop:
3f124d23	646	ci_role_destroy(ci);
c859aa65 PC	647	deinit_phy:
c859aa65 PC	648	usb_phy_shutdown(ci->transceiver);
e443b333 AS	649
	650	return ret;
	651	}
	652
fb4e98ab	653	static int ci_hdrc_remove(struct platform_device *pdev)
e443b333	654	{
8e22978c	655	struct ci_hdrc *ci = platform_get_drvdata(pdev);
e443b333	656
adf0f735	657	dbg_remove_files(ci);
5f36e231	658	free_irq(ci->irq, ci);
3f124d23	659	ci_role_destroy(ci);
864cf949	660	ci_hdrc_enter_lpm(ci, true);
c859aa65 PC	661	usb_phy_shutdown(ci->transceiver);
c859aa65 PC	662	kfree(ci->hw_bank.regmap);
e443b333 AS	663
	664	return 0;
	665	}
	666
5f36e231 AS	667	static struct platform_driver ci_hdrc_driver = {
5f36e231 AS	668	.probe = ci_hdrc_probe,
7690417d	669	.remove = ci_hdrc_remove,
e443b333	670	.driver = {
5f36e231	671	.name = "ci_hdrc",
e443b333 AS	672	},
	673	};
	674
5f36e231	675	module_platform_driver(ci_hdrc_driver);
e443b333	676
5f36e231	677	MODULE_ALIAS("platform:ci_hdrc");
e443b333 AS	678	MODULE_LICENSE("GPL v2");
e443b333 AS	679	MODULE_AUTHOR("David Lopo <dlopo@chipidea.mips.com>");
5f36e231	680	MODULE_DESCRIPTION("ChipIdea HDRC Driver");