Commit | Line | Data |
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5fd54ace | 1 | // SPDX-License-Identifier: GPL-2.0 |
e443b333 AS |
2 | /* |
3 | * core.c - ChipIdea USB IP core family device controller | |
4 | * | |
5 | * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved. | |
6 | * | |
7 | * Author: David Lopo | |
e443b333 AS |
8 | */ |
9 | ||
10 | /* | |
11 | * Description: ChipIdea USB IP core family device controller | |
12 | * | |
13 | * This driver is composed of several blocks: | |
14 | * - HW: hardware interface | |
15 | * - DBG: debug facilities (optional) | |
16 | * - UTIL: utilities | |
17 | * - ISR: interrupts handling | |
18 | * - ENDPT: endpoint operations (Gadget API) | |
19 | * - GADGET: gadget operations (Gadget API) | |
20 | * - BUS: bus glue code, bus abstraction layer | |
21 | * | |
22 | * Compile Options | |
e443b333 AS |
23 | * - STALL_IN: non-empty bulk-in pipes cannot be halted |
24 | * if defined mass storage compliance succeeds but with warnings | |
25 | * => case 4: Hi > Dn | |
26 | * => case 5: Hi > Di | |
27 | * => case 8: Hi <> Do | |
28 | * if undefined usbtest 13 fails | |
29 | * - TRACE: enable function tracing (depends on DEBUG) | |
30 | * | |
31 | * Main Features | |
32 | * - Chapter 9 & Mass Storage Compliance with Gadget File Storage | |
33 | * - Chapter 9 Compliance with Gadget Zero (STALL_IN undefined) | |
34 | * - Normal & LPM support | |
35 | * | |
36 | * USBTEST Report | |
37 | * - OK: 0-12, 13 (STALL_IN defined) & 14 | |
38 | * - Not Supported: 15 & 16 (ISO) | |
39 | * | |
40 | * TODO List | |
e443b333 AS |
41 | * - Suspend & Remote Wakeup |
42 | */ | |
43 | #include <linux/delay.h> | |
44 | #include <linux/device.h> | |
e443b333 | 45 | #include <linux/dma-mapping.h> |
3ecb3e09 | 46 | #include <linux/extcon.h> |
1e5e2d3d | 47 | #include <linux/phy/phy.h> |
e443b333 AS |
48 | #include <linux/platform_device.h> |
49 | #include <linux/module.h> | |
fe6e125e | 50 | #include <linux/idr.h> |
e443b333 AS |
51 | #include <linux/interrupt.h> |
52 | #include <linux/io.h> | |
e443b333 AS |
53 | #include <linux/kernel.h> |
54 | #include <linux/slab.h> | |
55 | #include <linux/pm_runtime.h> | |
56 | #include <linux/usb/ch9.h> | |
57 | #include <linux/usb/gadget.h> | |
58 | #include <linux/usb/otg.h> | |
59 | #include <linux/usb/chipidea.h> | |
40dcd0e8 | 60 | #include <linux/usb/of.h> |
4f6743d5 | 61 | #include <linux/of.h> |
1542d9c3 | 62 | #include <linux/regulator/consumer.h> |
8022d3d5 | 63 | #include <linux/usb/ehci_def.h> |
e443b333 AS |
64 | |
65 | #include "ci.h" | |
66 | #include "udc.h" | |
67 | #include "bits.h" | |
eb70e5ab | 68 | #include "host.h" |
c10b4f03 | 69 | #include "otg.h" |
4dcf720c | 70 | #include "otg_fsm.h" |
e443b333 | 71 | |
5f36e231 | 72 | /* Controller register map */ |
987e7bc3 MKB |
73 | static const u8 ci_regs_nolpm[] = { |
74 | [CAP_CAPLENGTH] = 0x00U, | |
75 | [CAP_HCCPARAMS] = 0x08U, | |
76 | [CAP_DCCPARAMS] = 0x24U, | |
77 | [CAP_TESTMODE] = 0x38U, | |
78 | [OP_USBCMD] = 0x00U, | |
79 | [OP_USBSTS] = 0x04U, | |
80 | [OP_USBINTR] = 0x08U, | |
81 | [OP_DEVICEADDR] = 0x14U, | |
82 | [OP_ENDPTLISTADDR] = 0x18U, | |
28362673 | 83 | [OP_TTCTRL] = 0x1CU, |
96625ead | 84 | [OP_BURSTSIZE] = 0x20U, |
7bb7e9b1 | 85 | [OP_ULPI_VIEWPORT] = 0x30U, |
987e7bc3 MKB |
86 | [OP_PORTSC] = 0x44U, |
87 | [OP_DEVLC] = 0x84U, | |
88 | [OP_OTGSC] = 0x64U, | |
89 | [OP_USBMODE] = 0x68U, | |
90 | [OP_ENDPTSETUPSTAT] = 0x6CU, | |
91 | [OP_ENDPTPRIME] = 0x70U, | |
92 | [OP_ENDPTFLUSH] = 0x74U, | |
93 | [OP_ENDPTSTAT] = 0x78U, | |
94 | [OP_ENDPTCOMPLETE] = 0x7CU, | |
95 | [OP_ENDPTCTRL] = 0x80U, | |
e443b333 AS |
96 | }; |
97 | ||
987e7bc3 MKB |
98 | static const u8 ci_regs_lpm[] = { |
99 | [CAP_CAPLENGTH] = 0x00U, | |
100 | [CAP_HCCPARAMS] = 0x08U, | |
101 | [CAP_DCCPARAMS] = 0x24U, | |
102 | [CAP_TESTMODE] = 0xFCU, | |
103 | [OP_USBCMD] = 0x00U, | |
104 | [OP_USBSTS] = 0x04U, | |
105 | [OP_USBINTR] = 0x08U, | |
106 | [OP_DEVICEADDR] = 0x14U, | |
107 | [OP_ENDPTLISTADDR] = 0x18U, | |
28362673 | 108 | [OP_TTCTRL] = 0x1CU, |
96625ead | 109 | [OP_BURSTSIZE] = 0x20U, |
7bb7e9b1 | 110 | [OP_ULPI_VIEWPORT] = 0x30U, |
987e7bc3 MKB |
111 | [OP_PORTSC] = 0x44U, |
112 | [OP_DEVLC] = 0x84U, | |
113 | [OP_OTGSC] = 0xC4U, | |
114 | [OP_USBMODE] = 0xC8U, | |
115 | [OP_ENDPTSETUPSTAT] = 0xD8U, | |
116 | [OP_ENDPTPRIME] = 0xDCU, | |
117 | [OP_ENDPTFLUSH] = 0xE0U, | |
118 | [OP_ENDPTSTAT] = 0xE4U, | |
119 | [OP_ENDPTCOMPLETE] = 0xE8U, | |
120 | [OP_ENDPTCTRL] = 0xECU, | |
e443b333 AS |
121 | }; |
122 | ||
158ec071 | 123 | static void hw_alloc_regmap(struct ci_hdrc *ci, bool is_lpm) |
e443b333 AS |
124 | { |
125 | int i; | |
126 | ||
e443b333 | 127 | for (i = 0; i < OP_ENDPTCTRL; i++) |
5f36e231 AS |
128 | ci->hw_bank.regmap[i] = |
129 | (i <= CAP_LAST ? ci->hw_bank.cap : ci->hw_bank.op) + | |
e443b333 AS |
130 | (is_lpm ? ci_regs_lpm[i] : ci_regs_nolpm[i]); |
131 | ||
132 | for (; i <= OP_LAST; i++) | |
5f36e231 | 133 | ci->hw_bank.regmap[i] = ci->hw_bank.op + |
e443b333 AS |
134 | 4 * (i - OP_ENDPTCTRL) + |
135 | (is_lpm | |
136 | ? ci_regs_lpm[OP_ENDPTCTRL] | |
137 | : ci_regs_nolpm[OP_ENDPTCTRL]); | |
138 | ||
e443b333 AS |
139 | } |
140 | ||
cb271f3c PC |
141 | static enum ci_revision ci_get_revision(struct ci_hdrc *ci) |
142 | { | |
143 | int ver = hw_read_id_reg(ci, ID_ID, VERSION) >> __ffs(VERSION); | |
144 | enum ci_revision rev = CI_REVISION_UNKNOWN; | |
145 | ||
146 | if (ver == 0x2) { | |
147 | rev = hw_read_id_reg(ci, ID_ID, REVISION) | |
148 | >> __ffs(REVISION); | |
149 | rev += CI_REVISION_20; | |
150 | } else if (ver == 0x0) { | |
151 | rev = CI_REVISION_1X; | |
152 | } | |
153 | ||
154 | return rev; | |
155 | } | |
156 | ||
36304b06 LJ |
157 | /** |
158 | * hw_read_intr_enable: returns interrupt enable register | |
159 | * | |
19353881 PC |
160 | * @ci: the controller |
161 | * | |
36304b06 LJ |
162 | * This function returns register data |
163 | */ | |
164 | u32 hw_read_intr_enable(struct ci_hdrc *ci) | |
165 | { | |
166 | return hw_read(ci, OP_USBINTR, ~0); | |
167 | } | |
168 | ||
169 | /** | |
170 | * hw_read_intr_status: returns interrupt status register | |
171 | * | |
19353881 PC |
172 | * @ci: the controller |
173 | * | |
36304b06 LJ |
174 | * This function returns register data |
175 | */ | |
176 | u32 hw_read_intr_status(struct ci_hdrc *ci) | |
177 | { | |
178 | return hw_read(ci, OP_USBSTS, ~0); | |
179 | } | |
180 | ||
e443b333 AS |
181 | /** |
182 | * hw_port_test_set: writes port test mode (execute without interruption) | |
183 | * @mode: new value | |
184 | * | |
185 | * This function returns an error code | |
186 | */ | |
8e22978c | 187 | int hw_port_test_set(struct ci_hdrc *ci, u8 mode) |
e443b333 AS |
188 | { |
189 | const u8 TEST_MODE_MAX = 7; | |
190 | ||
191 | if (mode > TEST_MODE_MAX) | |
192 | return -EINVAL; | |
193 | ||
727b4ddb | 194 | hw_write(ci, OP_PORTSC, PORTSC_PTC, mode << __ffs(PORTSC_PTC)); |
e443b333 AS |
195 | return 0; |
196 | } | |
197 | ||
198 | /** | |
199 | * hw_port_test_get: reads port test mode value | |
200 | * | |
19353881 PC |
201 | * @ci: the controller |
202 | * | |
e443b333 AS |
203 | * This function returns port test mode value |
204 | */ | |
8e22978c | 205 | u8 hw_port_test_get(struct ci_hdrc *ci) |
e443b333 | 206 | { |
727b4ddb | 207 | return hw_read(ci, OP_PORTSC, PORTSC_PTC) >> __ffs(PORTSC_PTC); |
e443b333 AS |
208 | } |
209 | ||
b82613cf PC |
210 | static void hw_wait_phy_stable(void) |
211 | { | |
212 | /* | |
213 | * The phy needs some delay to output the stable status from low | |
214 | * power mode. And for OTGSC, the status inputs are debounced | |
215 | * using a 1 ms time constant, so, delay 2ms for controller to get | |
216 | * the stable status, like vbus and id when the phy leaves low power. | |
217 | */ | |
218 | usleep_range(2000, 2500); | |
219 | } | |
220 | ||
864cf949 PC |
221 | /* The PHY enters/leaves low power mode */ |
222 | static void ci_hdrc_enter_lpm(struct ci_hdrc *ci, bool enable) | |
223 | { | |
224 | enum ci_hw_regs reg = ci->hw_bank.lpm ? OP_DEVLC : OP_PORTSC; | |
225 | bool lpm = !!(hw_read(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm))); | |
226 | ||
6d037db6 | 227 | if (enable && !lpm) |
864cf949 PC |
228 | hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm), |
229 | PORTSC_PHCD(ci->hw_bank.lpm)); | |
6d037db6 | 230 | else if (!enable && lpm) |
864cf949 PC |
231 | hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm), |
232 | 0); | |
864cf949 PC |
233 | } |
234 | ||
8e22978c | 235 | static int hw_device_init(struct ci_hdrc *ci, void __iomem *base) |
e443b333 AS |
236 | { |
237 | u32 reg; | |
238 | ||
239 | /* bank is a module variable */ | |
5f36e231 | 240 | ci->hw_bank.abs = base; |
e443b333 | 241 | |
5f36e231 | 242 | ci->hw_bank.cap = ci->hw_bank.abs; |
77c4400f | 243 | ci->hw_bank.cap += ci->platdata->capoffset; |
938d323f | 244 | ci->hw_bank.op = ci->hw_bank.cap + (ioread32(ci->hw_bank.cap) & 0xff); |
e443b333 | 245 | |
5f36e231 AS |
246 | hw_alloc_regmap(ci, false); |
247 | reg = hw_read(ci, CAP_HCCPARAMS, HCCPARAMS_LEN) >> | |
727b4ddb | 248 | __ffs(HCCPARAMS_LEN); |
5f36e231 | 249 | ci->hw_bank.lpm = reg; |
aeb2c121 CR |
250 | if (reg) |
251 | hw_alloc_regmap(ci, !!reg); | |
5f36e231 AS |
252 | ci->hw_bank.size = ci->hw_bank.op - ci->hw_bank.abs; |
253 | ci->hw_bank.size += OP_LAST; | |
254 | ci->hw_bank.size /= sizeof(u32); | |
e443b333 | 255 | |
5f36e231 | 256 | reg = hw_read(ci, CAP_DCCPARAMS, DCCPARAMS_DEN) >> |
727b4ddb | 257 | __ffs(DCCPARAMS_DEN); |
5f36e231 | 258 | ci->hw_ep_max = reg * 2; /* cache hw ENDPT_MAX */ |
e443b333 | 259 | |
09c94e62 | 260 | if (ci->hw_ep_max > ENDPT_MAX) |
e443b333 AS |
261 | return -ENODEV; |
262 | ||
864cf949 PC |
263 | ci_hdrc_enter_lpm(ci, false); |
264 | ||
c344b518 PC |
265 | /* Disable all interrupts bits */ |
266 | hw_write(ci, OP_USBINTR, 0xffffffff, 0); | |
267 | ||
268 | /* Clear all interrupts status bits*/ | |
269 | hw_write(ci, OP_USBSTS, 0xffffffff, 0xffffffff); | |
270 | ||
cb271f3c PC |
271 | ci->rev = ci_get_revision(ci); |
272 | ||
273 | dev_dbg(ci->dev, | |
274 | "ChipIdea HDRC found, revision: %d, lpm: %d; cap: %p op: %p\n", | |
275 | ci->rev, ci->hw_bank.lpm, ci->hw_bank.cap, ci->hw_bank.op); | |
e443b333 AS |
276 | |
277 | /* setup lock mode ? */ | |
278 | ||
279 | /* ENDPTSETUPSTAT is '0' by default */ | |
280 | ||
281 | /* HCSPARAMS.bf.ppc SHOULD BE zero for device */ | |
282 | ||
283 | return 0; | |
284 | } | |
285 | ||
7bb7e9b1 | 286 | void hw_phymode_configure(struct ci_hdrc *ci) |
40dcd0e8 | 287 | { |
3b5d3e68 | 288 | u32 portsc, lpm, sts = 0; |
40dcd0e8 MG |
289 | |
290 | switch (ci->platdata->phy_mode) { | |
291 | case USBPHY_INTERFACE_MODE_UTMI: | |
292 | portsc = PORTSC_PTS(PTS_UTMI); | |
293 | lpm = DEVLC_PTS(PTS_UTMI); | |
294 | break; | |
295 | case USBPHY_INTERFACE_MODE_UTMIW: | |
296 | portsc = PORTSC_PTS(PTS_UTMI) | PORTSC_PTW; | |
297 | lpm = DEVLC_PTS(PTS_UTMI) | DEVLC_PTW; | |
298 | break; | |
299 | case USBPHY_INTERFACE_MODE_ULPI: | |
300 | portsc = PORTSC_PTS(PTS_ULPI); | |
301 | lpm = DEVLC_PTS(PTS_ULPI); | |
302 | break; | |
303 | case USBPHY_INTERFACE_MODE_SERIAL: | |
304 | portsc = PORTSC_PTS(PTS_SERIAL); | |
305 | lpm = DEVLC_PTS(PTS_SERIAL); | |
306 | sts = 1; | |
307 | break; | |
308 | case USBPHY_INTERFACE_MODE_HSIC: | |
309 | portsc = PORTSC_PTS(PTS_HSIC); | |
310 | lpm = DEVLC_PTS(PTS_HSIC); | |
311 | break; | |
312 | default: | |
313 | return; | |
314 | } | |
315 | ||
316 | if (ci->hw_bank.lpm) { | |
317 | hw_write(ci, OP_DEVLC, DEVLC_PTS(7) | DEVLC_PTW, lpm); | |
3b5d3e68 CR |
318 | if (sts) |
319 | hw_write(ci, OP_DEVLC, DEVLC_STS, DEVLC_STS); | |
40dcd0e8 MG |
320 | } else { |
321 | hw_write(ci, OP_PORTSC, PORTSC_PTS(7) | PORTSC_PTW, portsc); | |
3b5d3e68 CR |
322 | if (sts) |
323 | hw_write(ci, OP_PORTSC, PORTSC_STS, PORTSC_STS); | |
40dcd0e8 MG |
324 | } |
325 | } | |
11893dae | 326 | EXPORT_SYMBOL_GPL(hw_phymode_configure); |
40dcd0e8 | 327 | |
1e5e2d3d AT |
328 | /** |
329 | * _ci_usb_phy_init: initialize phy taking in account both phy and usb_phy | |
330 | * interfaces | |
331 | * @ci: the controller | |
332 | * | |
333 | * This function returns an error code if the phy failed to init | |
334 | */ | |
335 | static int _ci_usb_phy_init(struct ci_hdrc *ci) | |
336 | { | |
337 | int ret; | |
338 | ||
339 | if (ci->phy) { | |
340 | ret = phy_init(ci->phy); | |
341 | if (ret) | |
342 | return ret; | |
343 | ||
344 | ret = phy_power_on(ci->phy); | |
345 | if (ret) { | |
346 | phy_exit(ci->phy); | |
347 | return ret; | |
348 | } | |
349 | } else { | |
350 | ret = usb_phy_init(ci->usb_phy); | |
351 | } | |
352 | ||
353 | return ret; | |
354 | } | |
355 | ||
356 | /** | |
357 | * _ci_usb_phy_exit: deinitialize phy taking in account both phy and usb_phy | |
358 | * interfaces | |
359 | * @ci: the controller | |
360 | */ | |
361 | static void ci_usb_phy_exit(struct ci_hdrc *ci) | |
362 | { | |
8feb3680 SB |
363 | if (ci->platdata->flags & CI_HDRC_OVERRIDE_PHY_CONTROL) |
364 | return; | |
365 | ||
1e5e2d3d AT |
366 | if (ci->phy) { |
367 | phy_power_off(ci->phy); | |
368 | phy_exit(ci->phy); | |
369 | } else { | |
370 | usb_phy_shutdown(ci->usb_phy); | |
371 | } | |
372 | } | |
373 | ||
d03cccff PC |
374 | /** |
375 | * ci_usb_phy_init: initialize phy according to different phy type | |
376 | * @ci: the controller | |
19353881 | 377 | * |
d03cccff PC |
378 | * This function returns an error code if usb_phy_init has failed |
379 | */ | |
380 | static int ci_usb_phy_init(struct ci_hdrc *ci) | |
381 | { | |
382 | int ret; | |
383 | ||
8feb3680 SB |
384 | if (ci->platdata->flags & CI_HDRC_OVERRIDE_PHY_CONTROL) |
385 | return 0; | |
386 | ||
d03cccff PC |
387 | switch (ci->platdata->phy_mode) { |
388 | case USBPHY_INTERFACE_MODE_UTMI: | |
389 | case USBPHY_INTERFACE_MODE_UTMIW: | |
390 | case USBPHY_INTERFACE_MODE_HSIC: | |
1e5e2d3d | 391 | ret = _ci_usb_phy_init(ci); |
b82613cf PC |
392 | if (!ret) |
393 | hw_wait_phy_stable(); | |
394 | else | |
d03cccff PC |
395 | return ret; |
396 | hw_phymode_configure(ci); | |
397 | break; | |
398 | case USBPHY_INTERFACE_MODE_ULPI: | |
399 | case USBPHY_INTERFACE_MODE_SERIAL: | |
400 | hw_phymode_configure(ci); | |
1e5e2d3d | 401 | ret = _ci_usb_phy_init(ci); |
d03cccff PC |
402 | if (ret) |
403 | return ret; | |
404 | break; | |
405 | default: | |
1e5e2d3d | 406 | ret = _ci_usb_phy_init(ci); |
b82613cf PC |
407 | if (!ret) |
408 | hw_wait_phy_stable(); | |
d03cccff PC |
409 | } |
410 | ||
411 | return ret; | |
412 | } | |
413 | ||
bf9c85e7 PC |
414 | |
415 | /** | |
416 | * ci_platform_configure: do controller configure | |
417 | * @ci: the controller | |
418 | * | |
419 | */ | |
420 | void ci_platform_configure(struct ci_hdrc *ci) | |
421 | { | |
8022d3d5 PC |
422 | bool is_device_mode, is_host_mode; |
423 | ||
424 | is_device_mode = hw_read(ci, OP_USBMODE, USBMODE_CM) == USBMODE_CM_DC; | |
425 | is_host_mode = hw_read(ci, OP_USBMODE, USBMODE_CM) == USBMODE_CM_HC; | |
426 | ||
490b63e6 SB |
427 | if (is_device_mode) { |
428 | phy_set_mode(ci->phy, PHY_MODE_USB_DEVICE); | |
8022d3d5 | 429 | |
490b63e6 SB |
430 | if (ci->platdata->flags & CI_HDRC_DISABLE_DEVICE_STREAMING) |
431 | hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS, | |
432 | USBMODE_CI_SDIS); | |
433 | } | |
434 | ||
435 | if (is_host_mode) { | |
436 | phy_set_mode(ci->phy, PHY_MODE_USB_HOST); | |
437 | ||
438 | if (ci->platdata->flags & CI_HDRC_DISABLE_HOST_STREAMING) | |
439 | hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS, | |
440 | USBMODE_CI_SDIS); | |
441 | } | |
bf9c85e7 PC |
442 | |
443 | if (ci->platdata->flags & CI_HDRC_FORCE_FULLSPEED) { | |
444 | if (ci->hw_bank.lpm) | |
445 | hw_write(ci, OP_DEVLC, DEVLC_PFSC, DEVLC_PFSC); | |
446 | else | |
447 | hw_write(ci, OP_PORTSC, PORTSC_PFSC, PORTSC_PFSC); | |
448 | } | |
449 | ||
450 | if (ci->platdata->flags & CI_HDRC_SET_NON_ZERO_TTHA) | |
451 | hw_write(ci, OP_TTCTRL, TTCTRL_TTHA_MASK, TTCTRL_TTHA); | |
df96ed8d PC |
452 | |
453 | hw_write(ci, OP_USBCMD, 0xff0000, ci->platdata->itc_setting << 16); | |
454 | ||
65668718 PC |
455 | if (ci->platdata->flags & CI_HDRC_OVERRIDE_AHB_BURST) |
456 | hw_write_id_reg(ci, ID_SBUSCFG, AHBBRST_MASK, | |
457 | ci->platdata->ahb_burst_config); | |
96625ead PC |
458 | |
459 | /* override burst size, take effect only when ahb_burst_config is 0 */ | |
460 | if (!hw_read_id_reg(ci, ID_SBUSCFG, AHBBRST_MASK)) { | |
461 | if (ci->platdata->flags & CI_HDRC_OVERRIDE_TX_BURST) | |
462 | hw_write(ci, OP_BURSTSIZE, TX_BURST_MASK, | |
463 | ci->platdata->tx_burst_size << __ffs(TX_BURST_MASK)); | |
464 | ||
465 | if (ci->platdata->flags & CI_HDRC_OVERRIDE_RX_BURST) | |
466 | hw_write(ci, OP_BURSTSIZE, RX_BURST_MASK, | |
467 | ci->platdata->rx_burst_size); | |
468 | } | |
bf9c85e7 PC |
469 | } |
470 | ||
e443b333 | 471 | /** |
cdd278f2 | 472 | * hw_controller_reset: do controller reset |
e443b333 AS |
473 | * @ci: the controller |
474 | * | |
475 | * This function returns an error code | |
476 | */ | |
cdd278f2 PC |
477 | static int hw_controller_reset(struct ci_hdrc *ci) |
478 | { | |
479 | int count = 0; | |
480 | ||
481 | hw_write(ci, OP_USBCMD, USBCMD_RST, USBCMD_RST); | |
482 | while (hw_read(ci, OP_USBCMD, USBCMD_RST)) { | |
483 | udelay(10); | |
484 | if (count++ > 1000) | |
485 | return -ETIMEDOUT; | |
486 | } | |
487 | ||
488 | return 0; | |
489 | } | |
490 | ||
491 | /** | |
492 | * hw_device_reset: resets chip (execute without interruption) | |
493 | * @ci: the controller | |
494 | * | |
495 | * This function returns an error code | |
496 | */ | |
5b157300 | 497 | int hw_device_reset(struct ci_hdrc *ci) |
e443b333 | 498 | { |
cdd278f2 PC |
499 | int ret; |
500 | ||
e443b333 AS |
501 | /* should flush & stop before reset */ |
502 | hw_write(ci, OP_ENDPTFLUSH, ~0, ~0); | |
503 | hw_write(ci, OP_USBCMD, USBCMD_RS, 0); | |
504 | ||
cdd278f2 PC |
505 | ret = hw_controller_reset(ci); |
506 | if (ret) { | |
507 | dev_err(ci->dev, "error resetting controller, ret=%d\n", ret); | |
508 | return ret; | |
509 | } | |
e443b333 | 510 | |
11893dae SB |
511 | if (ci->platdata->notify_event) { |
512 | ret = ci->platdata->notify_event(ci, | |
8e22978c | 513 | CI_HDRC_CONTROLLER_RESET_EVENT); |
11893dae SB |
514 | if (ret) |
515 | return ret; | |
516 | } | |
e443b333 | 517 | |
e443b333 AS |
518 | /* USBMODE should be configured step by step */ |
519 | hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE); | |
5b157300 | 520 | hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_DC); |
e443b333 AS |
521 | /* HW >= 2.3 */ |
522 | hw_write(ci, OP_USBMODE, USBMODE_SLOM, USBMODE_SLOM); | |
523 | ||
5b157300 PC |
524 | if (hw_read(ci, OP_USBMODE, USBMODE_CM) != USBMODE_CM_DC) { |
525 | pr_err("cannot enter in %s device mode", ci_role(ci)->name); | |
e443b333 AS |
526 | pr_err("lpm = %i", ci->hw_bank.lpm); |
527 | return -ENODEV; | |
528 | } | |
529 | ||
bf9c85e7 PC |
530 | ci_platform_configure(ci); |
531 | ||
e443b333 AS |
532 | return 0; |
533 | } | |
534 | ||
5f36e231 AS |
535 | static irqreturn_t ci_irq(int irq, void *data) |
536 | { | |
8e22978c | 537 | struct ci_hdrc *ci = data; |
5f36e231 | 538 | irqreturn_t ret = IRQ_NONE; |
b183c19f | 539 | u32 otgsc = 0; |
5f36e231 | 540 | |
1f874edc PC |
541 | if (ci->in_lpm) { |
542 | disable_irq_nosync(irq); | |
543 | ci->wakeup_int = true; | |
544 | pm_runtime_get(ci->dev); | |
545 | return IRQ_HANDLED; | |
546 | } | |
547 | ||
4dcf720c | 548 | if (ci->is_otg) { |
0c33bf78 | 549 | otgsc = hw_read_otgsc(ci, ~0); |
4dcf720c LJ |
550 | if (ci_otg_is_fsm_mode(ci)) { |
551 | ret = ci_otg_fsm_irq(ci); | |
552 | if (ret == IRQ_HANDLED) | |
553 | return ret; | |
554 | } | |
555 | } | |
5f36e231 | 556 | |
a107f8c5 PC |
557 | /* |
558 | * Handle id change interrupt, it indicates device/host function | |
559 | * switch. | |
560 | */ | |
561 | if (ci->is_otg && (otgsc & OTGSC_IDIE) && (otgsc & OTGSC_IDIS)) { | |
562 | ci->id_event = true; | |
0c33bf78 LJ |
563 | /* Clear ID change irq status */ |
564 | hw_write_otgsc(ci, OTGSC_IDIS, OTGSC_IDIS); | |
be6b0c1b | 565 | ci_otg_queue_work(ci); |
a107f8c5 PC |
566 | return IRQ_HANDLED; |
567 | } | |
b183c19f | 568 | |
a107f8c5 PC |
569 | /* |
570 | * Handle vbus change interrupt, it indicates device connection | |
571 | * and disconnection events. | |
572 | */ | |
573 | if (ci->is_otg && (otgsc & OTGSC_BSVIE) && (otgsc & OTGSC_BSVIS)) { | |
574 | ci->b_sess_valid_event = true; | |
0c33bf78 LJ |
575 | /* Clear BSV irq */ |
576 | hw_write_otgsc(ci, OTGSC_BSVIS, OTGSC_BSVIS); | |
be6b0c1b | 577 | ci_otg_queue_work(ci); |
a107f8c5 | 578 | return IRQ_HANDLED; |
5f36e231 AS |
579 | } |
580 | ||
a107f8c5 PC |
581 | /* Handle device/host interrupt */ |
582 | if (ci->role != CI_ROLE_END) | |
583 | ret = ci_role(ci)->irq(ci); | |
584 | ||
b183c19f | 585 | return ret; |
5f36e231 AS |
586 | } |
587 | ||
5cc49268 SB |
588 | static int ci_cable_notifier(struct notifier_block *nb, unsigned long event, |
589 | void *ptr) | |
3ecb3e09 | 590 | { |
5cc49268 SB |
591 | struct ci_hdrc_cable *cbl = container_of(nb, struct ci_hdrc_cable, nb); |
592 | struct ci_hdrc *ci = cbl->ci; | |
3ecb3e09 | 593 | |
5cc49268 SB |
594 | cbl->connected = event; |
595 | cbl->changed = true; | |
3ecb3e09 II |
596 | |
597 | ci_irq(ci->irq, ci); | |
598 | return NOTIFY_DONE; | |
599 | } | |
600 | ||
1542d9c3 PC |
601 | static int ci_get_platdata(struct device *dev, |
602 | struct ci_hdrc_platform_data *platdata) | |
603 | { | |
3ecb3e09 II |
604 | struct extcon_dev *ext_vbus, *ext_id; |
605 | struct ci_hdrc_cable *cable; | |
79742351 LJ |
606 | int ret; |
607 | ||
c22600c3 PC |
608 | if (!platdata->phy_mode) |
609 | platdata->phy_mode = of_usb_get_phy_mode(dev->of_node); | |
610 | ||
611 | if (!platdata->dr_mode) | |
06e7114f | 612 | platdata->dr_mode = usb_get_dr_mode(dev); |
c22600c3 PC |
613 | |
614 | if (platdata->dr_mode == USB_DR_MODE_UNKNOWN) | |
615 | platdata->dr_mode = USB_DR_MODE_OTG; | |
616 | ||
c2ec3a73 PC |
617 | if (platdata->dr_mode != USB_DR_MODE_PERIPHERAL) { |
618 | /* Get the vbus regulator */ | |
619 | platdata->reg_vbus = devm_regulator_get(dev, "vbus"); | |
620 | if (PTR_ERR(platdata->reg_vbus) == -EPROBE_DEFER) { | |
621 | return -EPROBE_DEFER; | |
622 | } else if (PTR_ERR(platdata->reg_vbus) == -ENODEV) { | |
6629467b | 623 | /* no vbus regulator is needed */ |
c2ec3a73 PC |
624 | platdata->reg_vbus = NULL; |
625 | } else if (IS_ERR(platdata->reg_vbus)) { | |
626 | dev_err(dev, "Getting regulator error: %ld\n", | |
627 | PTR_ERR(platdata->reg_vbus)); | |
628 | return PTR_ERR(platdata->reg_vbus); | |
629 | } | |
f6a9ff07 PC |
630 | /* Get TPL support */ |
631 | if (!platdata->tpl_support) | |
632 | platdata->tpl_support = | |
633 | of_usb_host_tpl_support(dev->of_node); | |
c2ec3a73 PC |
634 | } |
635 | ||
79742351 LJ |
636 | if (platdata->dr_mode == USB_DR_MODE_OTG) { |
637 | /* We can support HNP and SRP of OTG 2.0 */ | |
638 | platdata->ci_otg_caps.otg_rev = 0x0200; | |
639 | platdata->ci_otg_caps.hnp_support = true; | |
640 | platdata->ci_otg_caps.srp_support = true; | |
641 | ||
642 | /* Update otg capabilities by DT properties */ | |
643 | ret = of_usb_update_otg_caps(dev->of_node, | |
644 | &platdata->ci_otg_caps); | |
645 | if (ret) | |
646 | return ret; | |
647 | } | |
648 | ||
63863b98 | 649 | if (usb_get_maximum_speed(dev) == USB_SPEED_FULL) |
4f6743d5 MG |
650 | platdata->flags |= CI_HDRC_FORCE_FULLSPEED; |
651 | ||
4b19b78a | 652 | of_property_read_u32(dev->of_node, "phy-clkgate-delay-us", |
1fbf4628 FE |
653 | &platdata->phy_clkgate_delay_us); |
654 | ||
df96ed8d | 655 | platdata->itc_setting = 1; |
df96ed8d | 656 | |
4b19b78a SS |
657 | of_property_read_u32(dev->of_node, "itc-setting", |
658 | &platdata->itc_setting); | |
659 | ||
660 | ret = of_property_read_u32(dev->of_node, "ahb-burst-config", | |
661 | &platdata->ahb_burst_config); | |
662 | if (!ret) { | |
65668718 | 663 | platdata->flags |= CI_HDRC_OVERRIDE_AHB_BURST; |
4b19b78a SS |
664 | } else if (ret != -EINVAL) { |
665 | dev_err(dev, "failed to get ahb-burst-config\n"); | |
666 | return ret; | |
65668718 PC |
667 | } |
668 | ||
4b19b78a SS |
669 | ret = of_property_read_u32(dev->of_node, "tx-burst-size-dword", |
670 | &platdata->tx_burst_size); | |
671 | if (!ret) { | |
96625ead | 672 | platdata->flags |= CI_HDRC_OVERRIDE_TX_BURST; |
4b19b78a SS |
673 | } else if (ret != -EINVAL) { |
674 | dev_err(dev, "failed to get tx-burst-size-dword\n"); | |
675 | return ret; | |
96625ead PC |
676 | } |
677 | ||
4b19b78a SS |
678 | ret = of_property_read_u32(dev->of_node, "rx-burst-size-dword", |
679 | &platdata->rx_burst_size); | |
680 | if (!ret) { | |
96625ead | 681 | platdata->flags |= CI_HDRC_OVERRIDE_RX_BURST; |
4b19b78a SS |
682 | } else if (ret != -EINVAL) { |
683 | dev_err(dev, "failed to get rx-burst-size-dword\n"); | |
684 | return ret; | |
96625ead PC |
685 | } |
686 | ||
aa738187 PC |
687 | if (of_find_property(dev->of_node, "non-zero-ttctrl-ttha", NULL)) |
688 | platdata->flags |= CI_HDRC_SET_NON_ZERO_TTHA; | |
689 | ||
3ecb3e09 II |
690 | ext_id = ERR_PTR(-ENODEV); |
691 | ext_vbus = ERR_PTR(-ENODEV); | |
692 | if (of_property_read_bool(dev->of_node, "extcon")) { | |
693 | /* Each one of them is not mandatory */ | |
694 | ext_vbus = extcon_get_edev_by_phandle(dev, 0); | |
695 | if (IS_ERR(ext_vbus) && PTR_ERR(ext_vbus) != -ENODEV) | |
696 | return PTR_ERR(ext_vbus); | |
697 | ||
698 | ext_id = extcon_get_edev_by_phandle(dev, 1); | |
699 | if (IS_ERR(ext_id) && PTR_ERR(ext_id) != -ENODEV) | |
700 | return PTR_ERR(ext_id); | |
701 | } | |
702 | ||
703 | cable = &platdata->vbus_extcon; | |
5cc49268 | 704 | cable->nb.notifier_call = ci_cable_notifier; |
3ecb3e09 II |
705 | cable->edev = ext_vbus; |
706 | ||
707 | if (!IS_ERR(ext_vbus)) { | |
3f991aa0 | 708 | ret = extcon_get_state(cable->edev, EXTCON_USB); |
3ecb3e09 | 709 | if (ret) |
5cc49268 | 710 | cable->connected = true; |
3ecb3e09 | 711 | else |
5cc49268 | 712 | cable->connected = false; |
3ecb3e09 II |
713 | } |
714 | ||
715 | cable = &platdata->id_extcon; | |
5cc49268 | 716 | cable->nb.notifier_call = ci_cable_notifier; |
3ecb3e09 II |
717 | cable->edev = ext_id; |
718 | ||
719 | if (!IS_ERR(ext_id)) { | |
3f991aa0 | 720 | ret = extcon_get_state(cable->edev, EXTCON_USB_HOST); |
3ecb3e09 | 721 | if (ret) |
5cc49268 | 722 | cable->connected = true; |
3ecb3e09 | 723 | else |
5cc49268 | 724 | cable->connected = false; |
3ecb3e09 | 725 | } |
1542d9c3 PC |
726 | return 0; |
727 | } | |
728 | ||
3ecb3e09 II |
729 | static int ci_extcon_register(struct ci_hdrc *ci) |
730 | { | |
731 | struct ci_hdrc_cable *id, *vbus; | |
732 | int ret; | |
733 | ||
734 | id = &ci->platdata->id_extcon; | |
735 | id->ci = ci; | |
7c3a8b81 | 736 | if (!IS_ERR_OR_NULL(id->edev)) { |
3f991aa0 CC |
737 | ret = devm_extcon_register_notifier(ci->dev, id->edev, |
738 | EXTCON_USB_HOST, &id->nb); | |
3ecb3e09 II |
739 | if (ret < 0) { |
740 | dev_err(ci->dev, "register ID failed\n"); | |
741 | return ret; | |
742 | } | |
743 | } | |
744 | ||
745 | vbus = &ci->platdata->vbus_extcon; | |
746 | vbus->ci = ci; | |
7c3a8b81 | 747 | if (!IS_ERR_OR_NULL(vbus->edev)) { |
3f991aa0 CC |
748 | ret = devm_extcon_register_notifier(ci->dev, vbus->edev, |
749 | EXTCON_USB, &vbus->nb); | |
3ecb3e09 | 750 | if (ret < 0) { |
3ecb3e09 II |
751 | dev_err(ci->dev, "register VBUS failed\n"); |
752 | return ret; | |
753 | } | |
754 | } | |
755 | ||
1542d9c3 PC |
756 | return 0; |
757 | } | |
758 | ||
fe6e125e RZ |
759 | static DEFINE_IDA(ci_ida); |
760 | ||
8e22978c | 761 | struct platform_device *ci_hdrc_add_device(struct device *dev, |
cbc6dc2a | 762 | struct resource *res, int nres, |
8e22978c | 763 | struct ci_hdrc_platform_data *platdata) |
cbc6dc2a RZ |
764 | { |
765 | struct platform_device *pdev; | |
fe6e125e | 766 | int id, ret; |
cbc6dc2a | 767 | |
1542d9c3 PC |
768 | ret = ci_get_platdata(dev, platdata); |
769 | if (ret) | |
770 | return ERR_PTR(ret); | |
771 | ||
fe6e125e RZ |
772 | id = ida_simple_get(&ci_ida, 0, 0, GFP_KERNEL); |
773 | if (id < 0) | |
774 | return ERR_PTR(id); | |
775 | ||
776 | pdev = platform_device_alloc("ci_hdrc", id); | |
777 | if (!pdev) { | |
778 | ret = -ENOMEM; | |
779 | goto put_id; | |
780 | } | |
cbc6dc2a RZ |
781 | |
782 | pdev->dev.parent = dev; | |
cbc6dc2a RZ |
783 | |
784 | ret = platform_device_add_resources(pdev, res, nres); | |
785 | if (ret) | |
786 | goto err; | |
787 | ||
788 | ret = platform_device_add_data(pdev, platdata, sizeof(*platdata)); | |
789 | if (ret) | |
790 | goto err; | |
791 | ||
792 | ret = platform_device_add(pdev); | |
793 | if (ret) | |
794 | goto err; | |
795 | ||
796 | return pdev; | |
797 | ||
798 | err: | |
799 | platform_device_put(pdev); | |
fe6e125e RZ |
800 | put_id: |
801 | ida_simple_remove(&ci_ida, id); | |
cbc6dc2a RZ |
802 | return ERR_PTR(ret); |
803 | } | |
8e22978c | 804 | EXPORT_SYMBOL_GPL(ci_hdrc_add_device); |
cbc6dc2a | 805 | |
8e22978c | 806 | void ci_hdrc_remove_device(struct platform_device *pdev) |
cbc6dc2a | 807 | { |
98c35534 | 808 | int id = pdev->id; |
cbc6dc2a | 809 | platform_device_unregister(pdev); |
98c35534 | 810 | ida_simple_remove(&ci_ida, id); |
cbc6dc2a | 811 | } |
8e22978c | 812 | EXPORT_SYMBOL_GPL(ci_hdrc_remove_device); |
cbc6dc2a | 813 | |
3f124d23 PC |
814 | static inline void ci_role_destroy(struct ci_hdrc *ci) |
815 | { | |
816 | ci_hdrc_gadget_destroy(ci); | |
817 | ci_hdrc_host_destroy(ci); | |
c4a0bbbd | 818 | if (ci->is_otg && ci->roles[CI_ROLE_GADGET]) |
cbec6bd5 | 819 | ci_hdrc_otg_destroy(ci); |
3f124d23 PC |
820 | } |
821 | ||
577b232f PC |
822 | static void ci_get_otg_capable(struct ci_hdrc *ci) |
823 | { | |
824 | if (ci->platdata->flags & CI_HDRC_DUAL_ROLE_NOT_OTG) | |
825 | ci->is_otg = false; | |
826 | else | |
827 | ci->is_otg = (hw_read(ci, CAP_DCCPARAMS, | |
828 | DCCPARAMS_DC | DCCPARAMS_HC) | |
829 | == (DCCPARAMS_DC | DCCPARAMS_HC)); | |
2e37cfd8 | 830 | if (ci->is_otg) { |
577b232f | 831 | dev_dbg(ci->dev, "It is OTG capable controller\n"); |
2e37cfd8 PC |
832 | /* Disable and clear all OTG irq */ |
833 | hw_write_otgsc(ci, OTGSC_INT_EN_BITS | OTGSC_INT_STATUS_BITS, | |
834 | OTGSC_INT_STATUS_BITS); | |
835 | } | |
577b232f PC |
836 | } |
837 | ||
ed5bd7a4 | 838 | static ssize_t role_show(struct device *dev, struct device_attribute *attr, |
a932a804 PC |
839 | char *buf) |
840 | { | |
841 | struct ci_hdrc *ci = dev_get_drvdata(dev); | |
842 | ||
cbb22ebc MT |
843 | if (ci->role != CI_ROLE_END) |
844 | return sprintf(buf, "%s\n", ci_role(ci)->name); | |
845 | ||
846 | return 0; | |
a932a804 PC |
847 | } |
848 | ||
ed5bd7a4 | 849 | static ssize_t role_store(struct device *dev, |
a932a804 PC |
850 | struct device_attribute *attr, const char *buf, size_t n) |
851 | { | |
852 | struct ci_hdrc *ci = dev_get_drvdata(dev); | |
853 | enum ci_role role; | |
854 | int ret; | |
855 | ||
856 | if (!(ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET])) { | |
857 | dev_warn(dev, "Current configuration is not dual-role, quit\n"); | |
858 | return -EPERM; | |
859 | } | |
860 | ||
861 | for (role = CI_ROLE_HOST; role < CI_ROLE_END; role++) | |
862 | if (!strncmp(buf, ci->roles[role]->name, | |
863 | strlen(ci->roles[role]->name))) | |
864 | break; | |
865 | ||
866 | if (role == CI_ROLE_END || role == ci->role) | |
867 | return -EINVAL; | |
868 | ||
869 | pm_runtime_get_sync(dev); | |
870 | disable_irq(ci->irq); | |
871 | ci_role_stop(ci); | |
872 | ret = ci_role_start(ci, role); | |
873 | if (!ret && ci->role == CI_ROLE_GADGET) | |
874 | ci_handle_vbus_change(ci); | |
875 | enable_irq(ci->irq); | |
876 | pm_runtime_put_sync(dev); | |
877 | ||
878 | return (ret == 0) ? n : ret; | |
879 | } | |
ed5bd7a4 | 880 | static DEVICE_ATTR_RW(role); |
a932a804 PC |
881 | |
882 | static struct attribute *ci_attrs[] = { | |
883 | &dev_attr_role.attr, | |
884 | NULL, | |
885 | }; | |
886 | ||
a351a2bf | 887 | static const struct attribute_group ci_attr_group = { |
a932a804 PC |
888 | .attrs = ci_attrs, |
889 | }; | |
890 | ||
41ac7b3a | 891 | static int ci_hdrc_probe(struct platform_device *pdev) |
e443b333 AS |
892 | { |
893 | struct device *dev = &pdev->dev; | |
8e22978c | 894 | struct ci_hdrc *ci; |
e443b333 AS |
895 | struct resource *res; |
896 | void __iomem *base; | |
897 | int ret; | |
691962d1 | 898 | enum usb_dr_mode dr_mode; |
e443b333 | 899 | |
fad56745 | 900 | if (!dev_get_platdata(dev)) { |
e443b333 AS |
901 | dev_err(dev, "platform data missing\n"); |
902 | return -ENODEV; | |
903 | } | |
904 | ||
905 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
19290816 FB |
906 | base = devm_ioremap_resource(dev, res); |
907 | if (IS_ERR(base)) | |
908 | return PTR_ERR(base); | |
e443b333 | 909 | |
5f36e231 | 910 | ci = devm_kzalloc(dev, sizeof(*ci), GFP_KERNEL); |
d0f99249 | 911 | if (!ci) |
5f36e231 | 912 | return -ENOMEM; |
5f36e231 | 913 | |
a5d906bb | 914 | spin_lock_init(&ci->lock); |
5f36e231 | 915 | ci->dev = dev; |
fad56745 | 916 | ci->platdata = dev_get_platdata(dev); |
ed8f8318 PC |
917 | ci->imx28_write_fix = !!(ci->platdata->flags & |
918 | CI_HDRC_IMX28_WRITE_FIX); | |
1f874edc PC |
919 | ci->supports_runtime_pm = !!(ci->platdata->flags & |
920 | CI_HDRC_SUPPORTS_RUNTIME_PM); | |
7bb7e9b1 | 921 | platform_set_drvdata(pdev, ci); |
5f36e231 AS |
922 | |
923 | ret = hw_device_init(ci, base); | |
924 | if (ret < 0) { | |
925 | dev_err(dev, "can't initialize hardware\n"); | |
926 | return -ENODEV; | |
927 | } | |
e443b333 | 928 | |
7bb7e9b1 SB |
929 | ret = ci_ulpi_init(ci); |
930 | if (ret) | |
931 | return ret; | |
932 | ||
1e5e2d3d AT |
933 | if (ci->platdata->phy) { |
934 | ci->phy = ci->platdata->phy; | |
935 | } else if (ci->platdata->usb_phy) { | |
ef44cb42 | 936 | ci->usb_phy = ci->platdata->usb_phy; |
1e5e2d3d | 937 | } else { |
21a5b579 AT |
938 | ci->phy = devm_phy_get(dev->parent, "usb-phy"); |
939 | ci->usb_phy = devm_usb_get_phy(dev->parent, USB_PHY_TYPE_USB2); | |
c859aa65 | 940 | |
1e5e2d3d AT |
941 | /* if both generic PHY and USB PHY layers aren't enabled */ |
942 | if (PTR_ERR(ci->phy) == -ENOSYS && | |
7bb7e9b1 SB |
943 | PTR_ERR(ci->usb_phy) == -ENXIO) { |
944 | ret = -ENXIO; | |
945 | goto ulpi_exit; | |
946 | } | |
1e5e2d3d | 947 | |
7bb7e9b1 SB |
948 | if (IS_ERR(ci->phy) && IS_ERR(ci->usb_phy)) { |
949 | ret = -EPROBE_DEFER; | |
950 | goto ulpi_exit; | |
951 | } | |
c859aa65 | 952 | |
1e5e2d3d AT |
953 | if (IS_ERR(ci->phy)) |
954 | ci->phy = NULL; | |
955 | else if (IS_ERR(ci->usb_phy)) | |
956 | ci->usb_phy = NULL; | |
c859aa65 PC |
957 | } |
958 | ||
d03cccff | 959 | ret = ci_usb_phy_init(ci); |
74475ede PC |
960 | if (ret) { |
961 | dev_err(dev, "unable to init phy: %d\n", ret); | |
962 | return ret; | |
963 | } | |
964 | ||
eb70e5ab AS |
965 | ci->hw_bank.phys = res->start; |
966 | ||
5f36e231 AS |
967 | ci->irq = platform_get_irq(pdev, 0); |
968 | if (ci->irq < 0) { | |
e443b333 | 969 | dev_err(dev, "missing IRQ\n"); |
42d18212 | 970 | ret = ci->irq; |
c859aa65 | 971 | goto deinit_phy; |
5f36e231 AS |
972 | } |
973 | ||
577b232f PC |
974 | ci_get_otg_capable(ci); |
975 | ||
691962d1 | 976 | dr_mode = ci->platdata->dr_mode; |
5f36e231 | 977 | /* initialize role(s) before the interrupt is requested */ |
691962d1 SH |
978 | if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_HOST) { |
979 | ret = ci_hdrc_host_init(ci); | |
c4a0bbbd JZ |
980 | if (ret) { |
981 | if (ret == -ENXIO) | |
982 | dev_info(dev, "doesn't support host\n"); | |
983 | else | |
984 | goto deinit_phy; | |
985 | } | |
691962d1 | 986 | } |
eb70e5ab | 987 | |
691962d1 SH |
988 | if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_PERIPHERAL) { |
989 | ret = ci_hdrc_gadget_init(ci); | |
c4a0bbbd JZ |
990 | if (ret) { |
991 | if (ret == -ENXIO) | |
992 | dev_info(dev, "doesn't support gadget\n"); | |
993 | else | |
994 | goto deinit_host; | |
995 | } | |
691962d1 | 996 | } |
5f36e231 AS |
997 | |
998 | if (!ci->roles[CI_ROLE_HOST] && !ci->roles[CI_ROLE_GADGET]) { | |
999 | dev_err(dev, "no supported roles\n"); | |
74475ede | 1000 | ret = -ENODEV; |
c4a0bbbd | 1001 | goto deinit_gadget; |
cbec6bd5 PC |
1002 | } |
1003 | ||
27c62c2d | 1004 | if (ci->is_otg && ci->roles[CI_ROLE_GADGET]) { |
cbec6bd5 PC |
1005 | ret = ci_hdrc_otg_init(ci); |
1006 | if (ret) { | |
1007 | dev_err(dev, "init otg fails, ret = %d\n", ret); | |
c4a0bbbd | 1008 | goto deinit_gadget; |
cbec6bd5 | 1009 | } |
5f36e231 AS |
1010 | } |
1011 | ||
1012 | if (ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET]) { | |
577b232f | 1013 | if (ci->is_otg) { |
577b232f | 1014 | ci->role = ci_otg_role(ci); |
0c33bf78 LJ |
1015 | /* Enable ID change irq */ |
1016 | hw_write_otgsc(ci, OTGSC_IDIE, OTGSC_IDIE); | |
577b232f PC |
1017 | } else { |
1018 | /* | |
1019 | * If the controller is not OTG capable, but support | |
1020 | * role switch, the defalt role is gadget, and the | |
1021 | * user can switch it through debugfs. | |
1022 | */ | |
1023 | ci->role = CI_ROLE_GADGET; | |
1024 | } | |
5f36e231 AS |
1025 | } else { |
1026 | ci->role = ci->roles[CI_ROLE_HOST] | |
1027 | ? CI_ROLE_HOST | |
1028 | : CI_ROLE_GADGET; | |
1029 | } | |
1030 | ||
4dcf720c | 1031 | if (!ci_otg_is_fsm_mode(ci)) { |
961ea496 LJ |
1032 | /* only update vbus status for peripheral */ |
1033 | if (ci->role == CI_ROLE_GADGET) | |
1034 | ci_handle_vbus_change(ci); | |
1035 | ||
4dcf720c LJ |
1036 | ret = ci_role_start(ci, ci->role); |
1037 | if (ret) { | |
1038 | dev_err(dev, "can't start %s role\n", | |
1039 | ci_role(ci)->name); | |
1040 | goto stop; | |
1041 | } | |
e443b333 AS |
1042 | } |
1043 | ||
4c503dd5 PC |
1044 | ret = devm_request_irq(dev, ci->irq, ci_irq, IRQF_SHARED, |
1045 | ci->platdata->name, ci); | |
5f36e231 AS |
1046 | if (ret) |
1047 | goto stop; | |
e443b333 | 1048 | |
3ecb3e09 II |
1049 | ret = ci_extcon_register(ci); |
1050 | if (ret) | |
1051 | goto stop; | |
1052 | ||
1f874edc PC |
1053 | if (ci->supports_runtime_pm) { |
1054 | pm_runtime_set_active(&pdev->dev); | |
1055 | pm_runtime_enable(&pdev->dev); | |
1056 | pm_runtime_set_autosuspend_delay(&pdev->dev, 2000); | |
1057 | pm_runtime_mark_last_busy(ci->dev); | |
1058 | pm_runtime_use_autosuspend(&pdev->dev); | |
1059 | } | |
1060 | ||
4dcf720c LJ |
1061 | if (ci_otg_is_fsm_mode(ci)) |
1062 | ci_hdrc_otg_fsm_start(ci); | |
1063 | ||
f8efa766 | 1064 | device_set_wakeup_capable(&pdev->dev, true); |
adf0f735 | 1065 | ret = dbg_create_files(ci); |
a932a804 PC |
1066 | if (ret) |
1067 | goto stop; | |
1068 | ||
1069 | ret = sysfs_create_group(&dev->kobj, &ci_attr_group); | |
1070 | if (ret) | |
1071 | goto remove_debug; | |
5f36e231 | 1072 | |
a932a804 PC |
1073 | return 0; |
1074 | ||
1075 | remove_debug: | |
1076 | dbg_remove_files(ci); | |
5f36e231 | 1077 | stop: |
c4a0bbbd JZ |
1078 | if (ci->is_otg && ci->roles[CI_ROLE_GADGET]) |
1079 | ci_hdrc_otg_destroy(ci); | |
1080 | deinit_gadget: | |
1081 | ci_hdrc_gadget_destroy(ci); | |
1082 | deinit_host: | |
1083 | ci_hdrc_host_destroy(ci); | |
c859aa65 | 1084 | deinit_phy: |
1e5e2d3d | 1085 | ci_usb_phy_exit(ci); |
7bb7e9b1 SB |
1086 | ulpi_exit: |
1087 | ci_ulpi_exit(ci); | |
e443b333 AS |
1088 | |
1089 | return ret; | |
1090 | } | |
1091 | ||
fb4e98ab | 1092 | static int ci_hdrc_remove(struct platform_device *pdev) |
e443b333 | 1093 | { |
8e22978c | 1094 | struct ci_hdrc *ci = platform_get_drvdata(pdev); |
e443b333 | 1095 | |
1f874edc PC |
1096 | if (ci->supports_runtime_pm) { |
1097 | pm_runtime_get_sync(&pdev->dev); | |
1098 | pm_runtime_disable(&pdev->dev); | |
1099 | pm_runtime_put_noidle(&pdev->dev); | |
1100 | } | |
1101 | ||
adf0f735 | 1102 | dbg_remove_files(ci); |
a932a804 | 1103 | sysfs_remove_group(&ci->dev->kobj, &ci_attr_group); |
3f124d23 | 1104 | ci_role_destroy(ci); |
864cf949 | 1105 | ci_hdrc_enter_lpm(ci, true); |
1e5e2d3d | 1106 | ci_usb_phy_exit(ci); |
7bb7e9b1 | 1107 | ci_ulpi_exit(ci); |
e443b333 AS |
1108 | |
1109 | return 0; | |
1110 | } | |
1111 | ||
1f874edc | 1112 | #ifdef CONFIG_PM |
961ea496 LJ |
1113 | /* Prepare wakeup by SRP before suspend */ |
1114 | static void ci_otg_fsm_suspend_for_srp(struct ci_hdrc *ci) | |
1115 | { | |
1116 | if ((ci->fsm.otg->state == OTG_STATE_A_IDLE) && | |
1117 | !hw_read_otgsc(ci, OTGSC_ID)) { | |
1118 | hw_write(ci, OP_PORTSC, PORTSC_W1C_BITS | PORTSC_PP, | |
1119 | PORTSC_PP); | |
1120 | hw_write(ci, OP_PORTSC, PORTSC_W1C_BITS | PORTSC_WKCN, | |
1121 | PORTSC_WKCN); | |
1122 | } | |
1123 | } | |
1124 | ||
1125 | /* Handle SRP when wakeup by data pulse */ | |
1126 | static void ci_otg_fsm_wakeup_by_srp(struct ci_hdrc *ci) | |
1127 | { | |
1128 | if ((ci->fsm.otg->state == OTG_STATE_A_IDLE) && | |
1129 | (ci->fsm.a_bus_drop == 1) && (ci->fsm.a_bus_req == 0)) { | |
1130 | if (!hw_read_otgsc(ci, OTGSC_ID)) { | |
1131 | ci->fsm.a_srp_det = 1; | |
1132 | ci->fsm.a_bus_drop = 0; | |
1133 | } else { | |
1134 | ci->fsm.id = 1; | |
1135 | } | |
1136 | ci_otg_queue_work(ci); | |
1137 | } | |
1138 | } | |
1139 | ||
8076932f PC |
1140 | static void ci_controller_suspend(struct ci_hdrc *ci) |
1141 | { | |
1f874edc | 1142 | disable_irq(ci->irq); |
8076932f | 1143 | ci_hdrc_enter_lpm(ci, true); |
1fbf4628 FE |
1144 | if (ci->platdata->phy_clkgate_delay_us) |
1145 | usleep_range(ci->platdata->phy_clkgate_delay_us, | |
1146 | ci->platdata->phy_clkgate_delay_us + 50); | |
1f874edc PC |
1147 | usb_phy_set_suspend(ci->usb_phy, 1); |
1148 | ci->in_lpm = true; | |
1149 | enable_irq(ci->irq); | |
8076932f PC |
1150 | } |
1151 | ||
1152 | static int ci_controller_resume(struct device *dev) | |
1153 | { | |
1154 | struct ci_hdrc *ci = dev_get_drvdata(dev); | |
7bb7e9b1 | 1155 | int ret; |
8076932f PC |
1156 | |
1157 | dev_dbg(dev, "at %s\n", __func__); | |
1158 | ||
1f874edc PC |
1159 | if (!ci->in_lpm) { |
1160 | WARN_ON(1); | |
1161 | return 0; | |
1162 | } | |
8076932f | 1163 | |
1f874edc | 1164 | ci_hdrc_enter_lpm(ci, false); |
7bb7e9b1 SB |
1165 | |
1166 | ret = ci_ulpi_resume(ci); | |
1167 | if (ret) | |
1168 | return ret; | |
1169 | ||
8076932f PC |
1170 | if (ci->usb_phy) { |
1171 | usb_phy_set_suspend(ci->usb_phy, 0); | |
1172 | usb_phy_set_wakeup(ci->usb_phy, false); | |
1173 | hw_wait_phy_stable(); | |
1174 | } | |
1175 | ||
1f874edc PC |
1176 | ci->in_lpm = false; |
1177 | if (ci->wakeup_int) { | |
1178 | ci->wakeup_int = false; | |
1179 | pm_runtime_mark_last_busy(ci->dev); | |
1180 | pm_runtime_put_autosuspend(ci->dev); | |
1181 | enable_irq(ci->irq); | |
961ea496 LJ |
1182 | if (ci_otg_is_fsm_mode(ci)) |
1183 | ci_otg_fsm_wakeup_by_srp(ci); | |
1f874edc PC |
1184 | } |
1185 | ||
8076932f PC |
1186 | return 0; |
1187 | } | |
1188 | ||
1f874edc | 1189 | #ifdef CONFIG_PM_SLEEP |
8076932f PC |
1190 | static int ci_suspend(struct device *dev) |
1191 | { | |
1192 | struct ci_hdrc *ci = dev_get_drvdata(dev); | |
1193 | ||
1194 | if (ci->wq) | |
1195 | flush_workqueue(ci->wq); | |
1f874edc PC |
1196 | /* |
1197 | * Controller needs to be active during suspend, otherwise the core | |
1198 | * may run resume when the parent is at suspend if other driver's | |
1199 | * suspend fails, it occurs before parent's suspend has not started, | |
1200 | * but the core suspend has finished. | |
1201 | */ | |
1202 | if (ci->in_lpm) | |
1203 | pm_runtime_resume(dev); | |
1204 | ||
1205 | if (ci->in_lpm) { | |
1206 | WARN_ON(1); | |
1207 | return 0; | |
1208 | } | |
8076932f | 1209 | |
f8efa766 | 1210 | if (device_may_wakeup(dev)) { |
961ea496 LJ |
1211 | if (ci_otg_is_fsm_mode(ci)) |
1212 | ci_otg_fsm_suspend_for_srp(ci); | |
1213 | ||
f8efa766 PC |
1214 | usb_phy_set_wakeup(ci->usb_phy, true); |
1215 | enable_irq_wake(ci->irq); | |
1216 | } | |
1217 | ||
8076932f PC |
1218 | ci_controller_suspend(ci); |
1219 | ||
1220 | return 0; | |
1221 | } | |
1222 | ||
1223 | static int ci_resume(struct device *dev) | |
1224 | { | |
1f874edc PC |
1225 | struct ci_hdrc *ci = dev_get_drvdata(dev); |
1226 | int ret; | |
1227 | ||
f8efa766 PC |
1228 | if (device_may_wakeup(dev)) |
1229 | disable_irq_wake(ci->irq); | |
1230 | ||
1f874edc PC |
1231 | ret = ci_controller_resume(dev); |
1232 | if (ret) | |
1233 | return ret; | |
1234 | ||
1235 | if (ci->supports_runtime_pm) { | |
1236 | pm_runtime_disable(dev); | |
1237 | pm_runtime_set_active(dev); | |
1238 | pm_runtime_enable(dev); | |
1239 | } | |
1240 | ||
1241 | return ret; | |
8076932f PC |
1242 | } |
1243 | #endif /* CONFIG_PM_SLEEP */ | |
1244 | ||
1f874edc PC |
1245 | static int ci_runtime_suspend(struct device *dev) |
1246 | { | |
1247 | struct ci_hdrc *ci = dev_get_drvdata(dev); | |
1248 | ||
1249 | dev_dbg(dev, "at %s\n", __func__); | |
1250 | ||
1251 | if (ci->in_lpm) { | |
1252 | WARN_ON(1); | |
1253 | return 0; | |
1254 | } | |
1255 | ||
961ea496 LJ |
1256 | if (ci_otg_is_fsm_mode(ci)) |
1257 | ci_otg_fsm_suspend_for_srp(ci); | |
1258 | ||
1f874edc PC |
1259 | usb_phy_set_wakeup(ci->usb_phy, true); |
1260 | ci_controller_suspend(ci); | |
1261 | ||
1262 | return 0; | |
1263 | } | |
1264 | ||
1265 | static int ci_runtime_resume(struct device *dev) | |
1266 | { | |
1267 | return ci_controller_resume(dev); | |
1268 | } | |
1269 | ||
1270 | #endif /* CONFIG_PM */ | |
8076932f PC |
1271 | static const struct dev_pm_ops ci_pm_ops = { |
1272 | SET_SYSTEM_SLEEP_PM_OPS(ci_suspend, ci_resume) | |
1f874edc | 1273 | SET_RUNTIME_PM_OPS(ci_runtime_suspend, ci_runtime_resume, NULL) |
8076932f | 1274 | }; |
1f874edc | 1275 | |
5f36e231 AS |
1276 | static struct platform_driver ci_hdrc_driver = { |
1277 | .probe = ci_hdrc_probe, | |
7690417d | 1278 | .remove = ci_hdrc_remove, |
e443b333 | 1279 | .driver = { |
5f36e231 | 1280 | .name = "ci_hdrc", |
8076932f | 1281 | .pm = &ci_pm_ops, |
e443b333 AS |
1282 | }, |
1283 | }; | |
1284 | ||
2f01a33b PC |
1285 | static int __init ci_hdrc_platform_register(void) |
1286 | { | |
1287 | ci_hdrc_host_driver_init(); | |
1288 | return platform_driver_register(&ci_hdrc_driver); | |
1289 | } | |
1290 | module_init(ci_hdrc_platform_register); | |
1291 | ||
1292 | static void __exit ci_hdrc_platform_unregister(void) | |
1293 | { | |
1294 | platform_driver_unregister(&ci_hdrc_driver); | |
1295 | } | |
1296 | module_exit(ci_hdrc_platform_unregister); | |
e443b333 | 1297 | |
5f36e231 | 1298 | MODULE_ALIAS("platform:ci_hdrc"); |
e443b333 AS |
1299 | MODULE_LICENSE("GPL v2"); |
1300 | MODULE_AUTHOR("David Lopo <dlopo@chipidea.mips.com>"); | |
5f36e231 | 1301 | MODULE_DESCRIPTION("ChipIdea HDRC Driver"); |