[linux-2.6-block.git] / drivers / usb / chipidea / core.c

/*
 * core.c - ChipIdea USB IP core family device controller
 *
 * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
 *
 * Author: David Lopo
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

/*
 * Description: ChipIdea USB IP core family device controller
 *
 * This driver is composed of several blocks:
 * - HW:     hardware interface
 * - DBG:    debug facilities (optional)
 * - UTIL:   utilities
 * - ISR:    interrupts handling
 * - ENDPT:  endpoint operations (Gadget API)
 * - GADGET: gadget operations (Gadget API)
 * - BUS:    bus glue code, bus abstraction layer
 *
 * Compile Options
 * - CONFIG_USB_GADGET_DEBUG_FILES: enable debug facilities
 * - STALL_IN:  non-empty bulk-in pipes cannot be halted
 *              if defined mass storage compliance succeeds but with warnings
 *              => case 4: Hi >  Dn
 *              => case 5: Hi >  Di
 *              => case 8: Hi <> Do
 *              if undefined usbtest 13 fails
 * - TRACE:     enable function tracing (depends on DEBUG)
 *
 * Main Features
 * - Chapter 9 & Mass Storage Compliance with Gadget File Storage
 * - Chapter 9 Compliance with Gadget Zero (STALL_IN undefined)
 * - Normal & LPM support
 *
 * USBTEST Report
 * - OK: 0-12, 13 (STALL_IN defined) & 14
 * - Not Supported: 15 & 16 (ISO)
 *
 * TODO List
 * - OTG
 * - Isochronous & Interrupt Traffic
 * - Handle requests which spawns into several TDs
 * - GET_STATUS(device) - always reports 0
 * - Gadget API (majority of optional features)
 * - Suspend & Remote Wakeup
 */
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/dmapool.h>
#include <linux/dma-mapping.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/pm_runtime.h>
#include <linux/usb/ch9.h>
#include <linux/usb/gadget.h>
#include <linux/usb/otg.h>
#include <linux/usb/chipidea.h>

#include "ci.h"
#include "udc.h"
#include "bits.h"
#include "host.h"
#include "debug.h"

/* Controller register map */
static uintptr_t ci_regs_nolpm[] = {
	[CAP_CAPLENGTH]		= 0x000UL,
	[CAP_HCCPARAMS]		= 0x008UL,
	[CAP_DCCPARAMS]		= 0x024UL,
	[CAP_TESTMODE]		= 0x038UL,
	[OP_USBCMD]		= 0x000UL,
	[OP_USBSTS]		= 0x004UL,
	[OP_USBINTR]		= 0x008UL,
	[OP_DEVICEADDR]		= 0x014UL,
	[OP_ENDPTLISTADDR]	= 0x018UL,
	[OP_PORTSC]		= 0x044UL,
	[OP_DEVLC]		= 0x084UL,
	[OP_OTGSC]		= 0x064UL,
	[OP_USBMODE]		= 0x068UL,
	[OP_ENDPTSETUPSTAT]	= 0x06CUL,
	[OP_ENDPTPRIME]		= 0x070UL,
	[OP_ENDPTFLUSH]		= 0x074UL,
	[OP_ENDPTSTAT]		= 0x078UL,
	[OP_ENDPTCOMPLETE]	= 0x07CUL,
	[OP_ENDPTCTRL]		= 0x080UL,
};

static uintptr_t ci_regs_lpm[] = {
	[CAP_CAPLENGTH]		= 0x000UL,
	[CAP_HCCPARAMS]		= 0x008UL,
	[CAP_DCCPARAMS]		= 0x024UL,
	[CAP_TESTMODE]		= 0x0FCUL,
	[OP_USBCMD]		= 0x000UL,
	[OP_USBSTS]		= 0x004UL,
	[OP_USBINTR]		= 0x008UL,
	[OP_DEVICEADDR]		= 0x014UL,
	[OP_ENDPTLISTADDR]	= 0x018UL,
	[OP_PORTSC]		= 0x044UL,
	[OP_DEVLC]		= 0x084UL,
	[OP_OTGSC]		= 0x0C4UL,
	[OP_USBMODE]		= 0x0C8UL,
	[OP_ENDPTSETUPSTAT]	= 0x0D8UL,
	[OP_ENDPTPRIME]		= 0x0DCUL,
	[OP_ENDPTFLUSH]		= 0x0E0UL,
	[OP_ENDPTSTAT]		= 0x0E4UL,
	[OP_ENDPTCOMPLETE]	= 0x0E8UL,
	[OP_ENDPTCTRL]		= 0x0ECUL,
};

static int hw_alloc_regmap(struct ci13xxx *ci, bool is_lpm)
{
	int i;

	kfree(ci->hw_bank.regmap);

	ci->hw_bank.regmap = kzalloc((OP_LAST + 1) * sizeof(void *),
				     GFP_KERNEL);
	if (!ci->hw_bank.regmap)
		return -ENOMEM;

	for (i = 0; i < OP_ENDPTCTRL; i++)
		ci->hw_bank.regmap[i] =
			(i <= CAP_LAST ? ci->hw_bank.cap : ci->hw_bank.op) +
			(is_lpm ? ci_regs_lpm[i] : ci_regs_nolpm[i]);

	for (; i <= OP_LAST; i++)
		ci->hw_bank.regmap[i] = ci->hw_bank.op +
			4 * (i - OP_ENDPTCTRL) +
			(is_lpm
			 ? ci_regs_lpm[OP_ENDPTCTRL]
			 : ci_regs_nolpm[OP_ENDPTCTRL]);

	return 0;
}

/**
 * hw_port_test_set: writes port test mode (execute without interruption)
 * @mode: new value
 *
 * This function returns an error code
 */
int hw_port_test_set(struct ci13xxx *ci, u8 mode)
{
	const u8 TEST_MODE_MAX = 7;

	if (mode > TEST_MODE_MAX)
		return -EINVAL;

	hw_write(ci, OP_PORTSC, PORTSC_PTC, mode << ffs_nr(PORTSC_PTC));
	return 0;
}

/**
 * hw_port_test_get: reads port test mode value
 *
 * This function returns port test mode value
 */
u8 hw_port_test_get(struct ci13xxx *ci)
{
	return hw_read(ci, OP_PORTSC, PORTSC_PTC) >> ffs_nr(PORTSC_PTC);
}

static int hw_device_init(struct ci13xxx *ci, void __iomem *base)
{
	u32 reg;

	/* bank is a module variable */
	ci->hw_bank.abs = base;

	ci->hw_bank.cap = ci->hw_bank.abs;
	ci->hw_bank.cap += ci->udc_driver->capoffset;
	ci->hw_bank.op = ci->hw_bank.cap + ioread8(ci->hw_bank.cap);

	hw_alloc_regmap(ci, false);
	reg = hw_read(ci, CAP_HCCPARAMS, HCCPARAMS_LEN) >>
		ffs_nr(HCCPARAMS_LEN);
	ci->hw_bank.lpm  = reg;
	hw_alloc_regmap(ci, !!reg);
	ci->hw_bank.size = ci->hw_bank.op - ci->hw_bank.abs;
	ci->hw_bank.size += OP_LAST;
	ci->hw_bank.size /= sizeof(u32);

	reg = hw_read(ci, CAP_DCCPARAMS, DCCPARAMS_DEN) >>
		ffs_nr(DCCPARAMS_DEN);
	ci->hw_ep_max = reg * 2;   /* cache hw ENDPT_MAX */

	if (ci->hw_ep_max > ENDPT_MAX)
		return -ENODEV;

	dev_dbg(ci->dev, "ChipIdea HDRC found, lpm: %d; cap: %p op: %p\n",
		ci->hw_bank.lpm, ci->hw_bank.cap, ci->hw_bank.op);

	/* setup lock mode ? */

	/* ENDPTSETUPSTAT is '0' by default */

	/* HCSPARAMS.bf.ppc SHOULD BE zero for device */

	return 0;
}

/**
 * hw_device_reset: resets chip (execute without interruption)
 * @ci: the controller
  *
 * This function returns an error code
 */
int hw_device_reset(struct ci13xxx *ci, u32 mode)
{
	/* should flush & stop before reset */
	hw_write(ci, OP_ENDPTFLUSH, ~0, ~0);
	hw_write(ci, OP_USBCMD, USBCMD_RS, 0);

	hw_write(ci, OP_USBCMD, USBCMD_RST, USBCMD_RST);
	while (hw_read(ci, OP_USBCMD, USBCMD_RST))
		udelay(10);		/* not RTOS friendly */


	if (ci->udc_driver->notify_event)
		ci->udc_driver->notify_event(ci,
			CI13XXX_CONTROLLER_RESET_EVENT);

	if (ci->udc_driver->flags & CI13XXX_DISABLE_STREAMING)
		hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS, USBMODE_CI_SDIS);

	/* USBMODE should be configured step by step */
	hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE);
	hw_write(ci, OP_USBMODE, USBMODE_CM, mode);
	/* HW >= 2.3 */
	hw_write(ci, OP_USBMODE, USBMODE_SLOM, USBMODE_SLOM);

	if (hw_read(ci, OP_USBMODE, USBMODE_CM) != mode) {
		pr_err("cannot enter in %s mode", ci_role(ci)->name);
		pr_err("lpm = %i", ci->hw_bank.lpm);
		return -ENODEV;
	}

	return 0;
}

/**
 * ci_otg_role - pick role based on ID pin state
 * @ci: the controller
 */
static enum ci_role ci_otg_role(struct ci13xxx *ci)
{
	u32 sts = hw_read(ci, OP_OTGSC, ~0);
	enum ci_role role = sts & OTGSC_ID
		? CI_ROLE_GADGET
		: CI_ROLE_HOST;

	return role;
}

/**
 * ci_role_work - perform role changing based on ID pin
 * @work: work struct
 */
static void ci_role_work(struct work_struct *work)
{
	struct ci13xxx *ci = container_of(work, struct ci13xxx, work);
	enum ci_role role = ci_otg_role(ci);

	hw_write(ci, OP_OTGSC, OTGSC_IDIS, OTGSC_IDIS);

	if (role != ci->role) {
		dev_dbg(ci->dev, "switching from %s to %s\n",
			ci_role(ci)->name, ci->roles[role]->name);

		ci_role_stop(ci);
		ci_role_start(ci, role);
	}
}

static ssize_t show_role(struct device *dev, struct device_attribute *attr,
			 char *buf)
{
	struct ci13xxx *ci = dev_get_drvdata(dev);

	return sprintf(buf, "%s\n", ci_role(ci)->name);
}

static ssize_t store_role(struct device *dev, struct device_attribute *attr,
			  const char *buf, size_t count)
{
	struct ci13xxx *ci = dev_get_drvdata(dev);
	enum ci_role role;
	int ret;

	for (role = CI_ROLE_HOST; role < CI_ROLE_END; role++)
		if (ci->roles[role] && !strcmp(buf, ci->roles[role]->name))
			break;

	if (role == CI_ROLE_END || role == ci->role)
		return -EINVAL;

	ci_role_stop(ci);
	ret = ci_role_start(ci, role);
	if (ret)
		return ret;

	return count;
}

static DEVICE_ATTR(role, S_IRUSR | S_IWUSR, show_role, store_role);

static irqreturn_t ci_irq(int irq, void *data)
{
	struct ci13xxx *ci = data;
	irqreturn_t ret = IRQ_NONE;

	if (ci->is_otg) {
		u32 sts = hw_read(ci, OP_OTGSC, ~0);

		if (sts & OTGSC_IDIS) {
			queue_work(ci->wq, &ci->work);
			ret = IRQ_HANDLED;
		}
	}

	return ci->role == CI_ROLE_END ? ret : ci_role(ci)->irq(ci);
}

static int __devinit ci_hdrc_probe(struct platform_device *pdev)
{
	struct device	*dev = &pdev->dev;
	struct ci13xxx	*ci;
	struct resource	*res;
	void __iomem	*base;
	int		ret;

	if (!dev->platform_data) {
		dev_err(dev, "platform data missing\n");
		return -ENODEV;
	}

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!res) {
		dev_err(dev, "missing resource\n");
		return -ENODEV;
	}

	base = devm_request_and_ioremap(dev, res);
	if (!res) {
		dev_err(dev, "can't request and ioremap resource\n");
		return -ENOMEM;
	}

	ci = devm_kzalloc(dev, sizeof(*ci), GFP_KERNEL);
	if (!ci) {
		dev_err(dev, "can't allocate device\n");
		return -ENOMEM;
	}

	ci->dev = dev;
	ci->udc_driver = dev->platform_data;

	ret = hw_device_init(ci, base);
	if (ret < 0) {
		dev_err(dev, "can't initialize hardware\n");
		return -ENODEV;
	}

	ci->hw_bank.phys = res->start;

	ci->irq = platform_get_irq(pdev, 0);
	if (ci->irq < 0) {
		dev_err(dev, "missing IRQ\n");
		return -ENODEV;
	}

	INIT_WORK(&ci->work, ci_role_work);
	ci->wq = create_singlethread_workqueue("ci_otg");
	if (!ci->wq) {
		dev_err(dev, "can't create workqueue\n");
		return -ENODEV;
	}

	/* initialize role(s) before the interrupt is requested */
	ret = ci_hdrc_host_init(ci);
	if (ret)
		dev_info(dev, "doesn't support host\n");

	ret = ci_hdrc_gadget_init(ci);
	if (ret)
		dev_info(dev, "doesn't support gadget\n");

	if (!ci->roles[CI_ROLE_HOST] && !ci->roles[CI_ROLE_GADGET]) {
		dev_err(dev, "no supported roles\n");
		ret = -ENODEV;
		goto rm_wq;
	}

	if (ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET]) {
		ci->is_otg = true;
		ci->role = ci_otg_role(ci);
	} else {
		ci->role = ci->roles[CI_ROLE_HOST]
			? CI_ROLE_HOST
			: CI_ROLE_GADGET;
	}

	ret = ci_role_start(ci, ci->role);
	if (ret) {
		dev_err(dev, "can't start %s role\n", ci_role(ci)->name);
		ret = -ENODEV;
		goto rm_wq;
	}

	platform_set_drvdata(pdev, ci);
	ret = request_irq(ci->irq, ci_irq, IRQF_SHARED, ci->udc_driver->name,
			  ci);
	if (ret)
		goto stop;

	ret = device_create_file(dev, &dev_attr_role);
	if (ret)
		goto rm_attr;

	if (ci->is_otg)
		hw_write(ci, OP_OTGSC, OTGSC_IDIE, OTGSC_IDIE);

	return ret;

rm_attr:
	device_remove_file(dev, &dev_attr_role);
stop:
	ci_role_stop(ci);
rm_wq:
	flush_workqueue(ci->wq);
	destroy_workqueue(ci->wq);

	return ret;
}

static int __devexit ci_hdrc_remove(struct platform_device *pdev)
{
	struct ci13xxx *ci = platform_get_drvdata(pdev);

	flush_workqueue(ci->wq);
	destroy_workqueue(ci->wq);
	device_remove_file(ci->dev, &dev_attr_role);
	free_irq(ci->irq, ci);
	ci_role_stop(ci);

	return 0;
}

static struct platform_driver ci_hdrc_driver = {
	.probe	= ci_hdrc_probe,
	.remove	= __devexit_p(ci_hdrc_remove),
	.driver	= {
		.name	= "ci_hdrc",
	},
};

module_platform_driver(ci_hdrc_driver);

MODULE_ALIAS("platform:ci_hdrc");
MODULE_ALIAS("platform:ci13xxx");
MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("David Lopo <dlopo@chipidea.mips.com>");
MODULE_DESCRIPTION("ChipIdea HDRC Driver");
Commit	Line	Data
e443b333 AS	1	/*
	2	* core.c - ChipIdea USB IP core family device controller
	3	*
	4	* Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
	5	*
	6	* Author: David Lopo
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*/
	12
	13	/*
	14	* Description: ChipIdea USB IP core family device controller
	15	*
	16	* This driver is composed of several blocks:
	17	* - HW: hardware interface
	18	* - DBG: debug facilities (optional)
	19	* - UTIL: utilities
	20	* - ISR: interrupts handling
	21	* - ENDPT: endpoint operations (Gadget API)
	22	* - GADGET: gadget operations (Gadget API)
	23	* - BUS: bus glue code, bus abstraction layer
	24	*
	25	* Compile Options
	26	* - CONFIG_USB_GADGET_DEBUG_FILES: enable debug facilities
	27	* - STALL_IN: non-empty bulk-in pipes cannot be halted
	28	* if defined mass storage compliance succeeds but with warnings
	29	* => case 4: Hi > Dn
	30	* => case 5: Hi > Di
	31	* => case 8: Hi <> Do
	32	* if undefined usbtest 13 fails
	33	* - TRACE: enable function tracing (depends on DEBUG)
	34	*
	35	* Main Features
	36	* - Chapter 9 & Mass Storage Compliance with Gadget File Storage
	37	* - Chapter 9 Compliance with Gadget Zero (STALL_IN undefined)
	38	* - Normal & LPM support
	39	*
	40	* USBTEST Report
	41	* - OK: 0-12, 13 (STALL_IN defined) & 14
	42	* - Not Supported: 15 & 16 (ISO)
	43	*
	44	* TODO List
	45	* - OTG
	46	* - Isochronous & Interrupt Traffic
	47	* - Handle requests which spawns into several TDs
	48	* - GET_STATUS(device) - always reports 0
	49	* - Gadget API (majority of optional features)
	50	* - Suspend & Remote Wakeup
	51	*/
	52	#include <linux/delay.h>
	53	#include <linux/device.h>
	54	#include <linux/dmapool.h>
	55	#include <linux/dma-mapping.h>
	56	#include <linux/init.h>
	57	#include <linux/platform_device.h>
	58	#include <linux/module.h>
	59	#include <linux/interrupt.h>
	60	#include <linux/io.h>
	61	#include <linux/irq.h>
	62	#include <linux/kernel.h>
	63	#include <linux/slab.h>
	64	#include <linux/pm_runtime.h>
65	#include <linux/usb/ch9.h>
66	#include <linux/usb/gadget.h>
67	#include <linux/usb/otg.h>
68	#include <linux/usb/chipidea.h>
69
70	#include "ci.h"
71	#include "udc.h"
72	#include "bits.h"
eb70e5ab	73	#include "host.h"
e443b333 AS	74	#include "debug.h"
e443b333 AS	75
5f36e231	76	/* Controller register map */
e443b333 AS	77	static uintptr_t ci_regs_nolpm[] = {
	78	[CAP_CAPLENGTH] = 0x000UL,
	79	[CAP_HCCPARAMS] = 0x008UL,
	80	[CAP_DCCPARAMS] = 0x024UL,
	81	[CAP_TESTMODE] = 0x038UL,
	82	[OP_USBCMD] = 0x000UL,
	83	[OP_USBSTS] = 0x004UL,
	84	[OP_USBINTR] = 0x008UL,
	85	[OP_DEVICEADDR] = 0x014UL,
	86	[OP_ENDPTLISTADDR] = 0x018UL,
	87	[OP_PORTSC] = 0x044UL,
	88	[OP_DEVLC] = 0x084UL,
5f36e231	89	[OP_OTGSC] = 0x064UL,
e443b333 AS	90	[OP_USBMODE] = 0x068UL,
	91	[OP_ENDPTSETUPSTAT] = 0x06CUL,
	92	[OP_ENDPTPRIME] = 0x070UL,
	93	[OP_ENDPTFLUSH] = 0x074UL,
	94	[OP_ENDPTSTAT] = 0x078UL,
	95	[OP_ENDPTCOMPLETE] = 0x07CUL,
	96	[OP_ENDPTCTRL] = 0x080UL,
	97	};
	98
	99	static uintptr_t ci_regs_lpm[] = {
	100	[CAP_CAPLENGTH] = 0x000UL,
	101	[CAP_HCCPARAMS] = 0x008UL,
	102	[CAP_DCCPARAMS] = 0x024UL,
	103	[CAP_TESTMODE] = 0x0FCUL,
	104	[OP_USBCMD] = 0x000UL,
	105	[OP_USBSTS] = 0x004UL,
	106	[OP_USBINTR] = 0x008UL,
	107	[OP_DEVICEADDR] = 0x014UL,
	108	[OP_ENDPTLISTADDR] = 0x018UL,
	109	[OP_PORTSC] = 0x044UL,
	110	[OP_DEVLC] = 0x084UL,
5f36e231	111	[OP_OTGSC] = 0x0C4UL,
e443b333 AS	112	[OP_USBMODE] = 0x0C8UL,
	113	[OP_ENDPTSETUPSTAT] = 0x0D8UL,
	114	[OP_ENDPTPRIME] = 0x0DCUL,
	115	[OP_ENDPTFLUSH] = 0x0E0UL,
	116	[OP_ENDPTSTAT] = 0x0E4UL,
	117	[OP_ENDPTCOMPLETE] = 0x0E8UL,
	118	[OP_ENDPTCTRL] = 0x0ECUL,
	119	};
	120
5f36e231	121	static int hw_alloc_regmap(struct ci13xxx *ci, bool is_lpm)
e443b333 AS	122	{
	123	int i;
	124
5f36e231	125	kfree(ci->hw_bank.regmap);
e443b333	126
5f36e231 AS	127	ci->hw_bank.regmap = kzalloc((OP_LAST + 1) * sizeof(void *),
	128	GFP_KERNEL);
	129	if (!ci->hw_bank.regmap)
e443b333 AS	130	return -ENOMEM;
	131
	132	for (i = 0; i < OP_ENDPTCTRL; i++)
5f36e231 AS	133	ci->hw_bank.regmap[i] =
5f36e231 AS	134	(i <= CAP_LAST ? ci->hw_bank.cap : ci->hw_bank.op) +
e443b333 AS	135	(is_lpm ? ci_regs_lpm[i] : ci_regs_nolpm[i]);
	136
	137	for (; i <= OP_LAST; i++)
5f36e231	138	ci->hw_bank.regmap[i] = ci->hw_bank.op +
e443b333 AS	139	4 * (i - OP_ENDPTCTRL) +
	140	(is_lpm
	141	? ci_regs_lpm[OP_ENDPTCTRL]
	142	: ci_regs_nolpm[OP_ENDPTCTRL]);
	143
	144	return 0;
	145	}
	146
	147	/**
	148	* hw_port_test_set: writes port test mode (execute without interruption)
	149	* @mode: new value
	150	*
	151	* This function returns an error code
	152	*/
	153	int hw_port_test_set(struct ci13xxx *ci, u8 mode)
	154	{
	155	const u8 TEST_MODE_MAX = 7;
	156
	157	if (mode > TEST_MODE_MAX)
	158	return -EINVAL;
	159
	160	hw_write(ci, OP_PORTSC, PORTSC_PTC, mode << ffs_nr(PORTSC_PTC));
	161	return 0;
	162	}
	163
	164	/**
	165	* hw_port_test_get: reads port test mode value
	166	*
	167	* This function returns port test mode value
	168	*/
	169	u8 hw_port_test_get(struct ci13xxx *ci)
	170	{
	171	return hw_read(ci, OP_PORTSC, PORTSC_PTC) >> ffs_nr(PORTSC_PTC);
	172	}
	173
5f36e231	174	static int hw_device_init(struct ci13xxx ci, void __iomem base)
e443b333 AS	175	{
	176	u32 reg;
	177
	178	/* bank is a module variable */
5f36e231	179	ci->hw_bank.abs = base;
e443b333	180
5f36e231 AS	181	ci->hw_bank.cap = ci->hw_bank.abs;
	182	ci->hw_bank.cap += ci->udc_driver->capoffset;
	183	ci->hw_bank.op = ci->hw_bank.cap + ioread8(ci->hw_bank.cap);
e443b333	184
5f36e231 AS	185	hw_alloc_regmap(ci, false);
5f36e231 AS	186	reg = hw_read(ci, CAP_HCCPARAMS, HCCPARAMS_LEN) >>
e443b333	187	ffs_nr(HCCPARAMS_LEN);
5f36e231 AS	188	ci->hw_bank.lpm = reg;
	189	hw_alloc_regmap(ci, !!reg);
	190	ci->hw_bank.size = ci->hw_bank.op - ci->hw_bank.abs;
	191	ci->hw_bank.size += OP_LAST;
	192	ci->hw_bank.size /= sizeof(u32);
e443b333	193
5f36e231	194	reg = hw_read(ci, CAP_DCCPARAMS, DCCPARAMS_DEN) >>
e443b333	195	ffs_nr(DCCPARAMS_DEN);
5f36e231	196	ci->hw_ep_max = reg * 2; /* cache hw ENDPT_MAX */
e443b333	197
09c94e62	198	if (ci->hw_ep_max > ENDPT_MAX)
e443b333 AS	199	return -ENODEV;
e443b333 AS	200
5f36e231 AS	201	dev_dbg(ci->dev, "ChipIdea HDRC found, lpm: %d; cap: %p op: %p\n",
5f36e231 AS	202	ci->hw_bank.lpm, ci->hw_bank.cap, ci->hw_bank.op);
e443b333 AS	203
	204	/* setup lock mode ? */
	205
	206	/* ENDPTSETUPSTAT is '0' by default */
	207
	208	/* HCSPARAMS.bf.ppc SHOULD BE zero for device */
	209
	210	return 0;
	211	}
	212
	213	/**
	214	* hw_device_reset: resets chip (execute without interruption)
	215	* @ci: the controller
	216	*
	217	* This function returns an error code
	218	*/
eb70e5ab	219	int hw_device_reset(struct ci13xxx *ci, u32 mode)
e443b333 AS	220	{
	221	/* should flush & stop before reset */
	222	hw_write(ci, OP_ENDPTFLUSH, ~0, ~0);
	223	hw_write(ci, OP_USBCMD, USBCMD_RS, 0);
	224
	225	hw_write(ci, OP_USBCMD, USBCMD_RST, USBCMD_RST);
	226	while (hw_read(ci, OP_USBCMD, USBCMD_RST))
	227	udelay(10); /* not RTOS friendly */
	228
	229
	230	if (ci->udc_driver->notify_event)
	231	ci->udc_driver->notify_event(ci,
	232	CI13XXX_CONTROLLER_RESET_EVENT);
	233
	234	if (ci->udc_driver->flags & CI13XXX_DISABLE_STREAMING)
758fc986	235	hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS, USBMODE_CI_SDIS);
e443b333 AS	236
	237	/* USBMODE should be configured step by step */
	238	hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE);
eb70e5ab	239	hw_write(ci, OP_USBMODE, USBMODE_CM, mode);
e443b333 AS	240	/* HW >= 2.3 */
	241	hw_write(ci, OP_USBMODE, USBMODE_SLOM, USBMODE_SLOM);
	242
eb70e5ab AS	243	if (hw_read(ci, OP_USBMODE, USBMODE_CM) != mode) {
eb70e5ab AS	244	pr_err("cannot enter in %s mode", ci_role(ci)->name);
e443b333 AS	245	pr_err("lpm = %i", ci->hw_bank.lpm);
	246	return -ENODEV;
	247	}
	248
	249	return 0;
	250	}
	251
5f36e231 AS	252	/**
	253	* ci_otg_role - pick role based on ID pin state
	254	* @ci: the controller
	255	*/
	256	static enum ci_role ci_otg_role(struct ci13xxx *ci)
	257	{
	258	u32 sts = hw_read(ci, OP_OTGSC, ~0);
	259	enum ci_role role = sts & OTGSC_ID
	260	? CI_ROLE_GADGET
	261	: CI_ROLE_HOST;
	262
	263	return role;
	264	}
	265
	266	/**
	267	* ci_role_work - perform role changing based on ID pin
	268	* @work: work struct
	269	*/
	270	static void ci_role_work(struct work_struct *work)
	271	{
	272	struct ci13xxx *ci = container_of(work, struct ci13xxx, work);
	273	enum ci_role role = ci_otg_role(ci);
	274
	275	hw_write(ci, OP_OTGSC, OTGSC_IDIS, OTGSC_IDIS);
	276
	277	if (role != ci->role) {
	278	dev_dbg(ci->dev, "switching from %s to %s\n",
	279	ci_role(ci)->name, ci->roles[role]->name);
	280
	281	ci_role_stop(ci);
	282	ci_role_start(ci, role);
	283	}
	284	}
	285
	286	static ssize_t show_role(struct device dev, struct device_attribute attr,
	287	char *buf)
	288	{
	289	struct ci13xxx *ci = dev_get_drvdata(dev);
	290
	291	return sprintf(buf, "%s\n", ci_role(ci)->name);
	292	}
	293
	294	static ssize_t store_role(struct device dev, struct device_attribute attr,
	295	const char *buf, size_t count)
	296	{
	297	struct ci13xxx *ci = dev_get_drvdata(dev);
	298	enum ci_role role;
	299	int ret;
	300
	301	for (role = CI_ROLE_HOST; role < CI_ROLE_END; role++)
	302	if (ci->roles[role] && !strcmp(buf, ci->roles[role]->name))
	303	break;
	304
	305	if (role == CI_ROLE_END \|\| role == ci->role)
	306	return -EINVAL;
	307
	308	ci_role_stop(ci);
	309	ret = ci_role_start(ci, role);
	310	if (ret)
	311	return ret;
	312
	313	return count;
	314	}
	315
316	static DEVICE_ATTR(role, S_IRUSR \| S_IWUSR, show_role, store_role);
317
318	static irqreturn_t ci_irq(int irq, void *data)
319	{
320	struct ci13xxx *ci = data;
321	irqreturn_t ret = IRQ_NONE;
322
323	if (ci->is_otg) {
324	u32 sts = hw_read(ci, OP_OTGSC, ~0);
325
326	if (sts & OTGSC_IDIS) {
327	queue_work(ci->wq, &ci->work);
328	ret = IRQ_HANDLED;
329	}
330	}
331
332	return ci->role == CI_ROLE_END ? ret : ci_role(ci)->irq(ci);
333	}
334
335	static int __devinit ci_hdrc_probe(struct platform_device *pdev)
e443b333 AS	336	{
e443b333 AS	337	struct device *dev = &pdev->dev;
5f36e231	338	struct ci13xxx *ci;
e443b333 AS	339	struct resource *res;
	340	void __iomem *base;
	341	int ret;
	342
5f36e231	343	if (!dev->platform_data) {
e443b333 AS	344	dev_err(dev, "platform data missing\n");
	345	return -ENODEV;
	346	}
	347
	348	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	349	if (!res) {
	350	dev_err(dev, "missing resource\n");
	351	return -ENODEV;
	352	}
	353
	354	base = devm_request_and_ioremap(dev, res);
	355	if (!res) {
	356	dev_err(dev, "can't request and ioremap resource\n");
	357	return -ENOMEM;
	358	}
	359
5f36e231 AS	360	ci = devm_kzalloc(dev, sizeof(*ci), GFP_KERNEL);
	361	if (!ci) {
	362	dev_err(dev, "can't allocate device\n");
	363	return -ENOMEM;
	364	}
	365
	366	ci->dev = dev;
	367	ci->udc_driver = dev->platform_data;
	368
	369	ret = hw_device_init(ci, base);
	370	if (ret < 0) {
	371	dev_err(dev, "can't initialize hardware\n");
	372	return -ENODEV;
	373	}
e443b333	374
eb70e5ab AS	375	ci->hw_bank.phys = res->start;
eb70e5ab AS	376
5f36e231 AS	377	ci->irq = platform_get_irq(pdev, 0);
5f36e231 AS	378	if (ci->irq < 0) {
e443b333	379	dev_err(dev, "missing IRQ\n");
5f36e231 AS	380	return -ENODEV;
	381	}
	382
	383	INIT_WORK(&ci->work, ci_role_work);
	384	ci->wq = create_singlethread_workqueue("ci_otg");
	385	if (!ci->wq) {
	386	dev_err(dev, "can't create workqueue\n");
	387	return -ENODEV;
	388	}
	389
	390	/* initialize role(s) before the interrupt is requested */
eb70e5ab AS	391	ret = ci_hdrc_host_init(ci);
	392	if (ret)
	393	dev_info(dev, "doesn't support host\n");
	394
5f36e231 AS	395	ret = ci_hdrc_gadget_init(ci);
	396	if (ret)
	397	dev_info(dev, "doesn't support gadget\n");
	398
	399	if (!ci->roles[CI_ROLE_HOST] && !ci->roles[CI_ROLE_GADGET]) {
	400	dev_err(dev, "no supported roles\n");
	401	ret = -ENODEV;
	402	goto rm_wq;
	403	}
	404
	405	if (ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET]) {
	406	ci->is_otg = true;
	407	ci->role = ci_otg_role(ci);
	408	} else {
	409	ci->role = ci->roles[CI_ROLE_HOST]
	410	? CI_ROLE_HOST
	411	: CI_ROLE_GADGET;
	412	}
	413
	414	ret = ci_role_start(ci, ci->role);
	415	if (ret) {
	416	dev_err(dev, "can't start %s role\n", ci_role(ci)->name);
e443b333	417	ret = -ENODEV;
5f36e231	418	goto rm_wq;
e443b333 AS	419	}
e443b333 AS	420
5f36e231 AS	421	platform_set_drvdata(pdev, ci);
	422	ret = request_irq(ci->irq, ci_irq, IRQF_SHARED, ci->udc_driver->name,
	423	ci);
	424	if (ret)
	425	goto stop;
e443b333	426
5f36e231	427	ret = device_create_file(dev, &dev_attr_role);
e443b333	428	if (ret)
5f36e231 AS	429	goto rm_attr;
	430
	431	if (ci->is_otg)
	432	hw_write(ci, OP_OTGSC, OTGSC_IDIE, OTGSC_IDIE);
	433
	434	return ret;
	435
	436	rm_attr:
	437	device_remove_file(dev, &dev_attr_role);
	438	stop:
	439	ci_role_stop(ci);
	440	rm_wq:
	441	flush_workqueue(ci->wq);
	442	destroy_workqueue(ci->wq);
e443b333 AS	443
	444	return ret;
	445	}
	446
5f36e231	447	static int __devexit ci_hdrc_remove(struct platform_device *pdev)
e443b333	448	{
5f36e231	449	struct ci13xxx *ci = platform_get_drvdata(pdev);
e443b333	450
5f36e231 AS	451	flush_workqueue(ci->wq);
	452	destroy_workqueue(ci->wq);
	453	device_remove_file(ci->dev, &dev_attr_role);
	454	free_irq(ci->irq, ci);
	455	ci_role_stop(ci);
e443b333 AS	456
	457	return 0;
	458	}
	459
5f36e231 AS	460	static struct platform_driver ci_hdrc_driver = {
	461	.probe = ci_hdrc_probe,
	462	.remove = __devexit_p(ci_hdrc_remove),
e443b333	463	.driver = {
5f36e231	464	.name = "ci_hdrc",
e443b333 AS	465	},
	466	};
	467
5f36e231	468	module_platform_driver(ci_hdrc_driver);
e443b333	469
5f36e231	470	MODULE_ALIAS("platform:ci_hdrc");
e443b333 AS	471	MODULE_ALIAS("platform:ci13xxx");
	472	MODULE_LICENSE("GPL v2");
	473	MODULE_AUTHOR("David Lopo <dlopo@chipidea.mips.com>");
5f36e231	474	MODULE_DESCRIPTION("ChipIdea HDRC Driver");