[linux-2.6-block.git] / drivers / usb / chipidea / core.c

/*
 * core.c - ChipIdea USB IP core family device controller
 *
 * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
 *
 * Author: David Lopo
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

/*
 * Description: ChipIdea USB IP core family device controller
 *
 * This driver is composed of several blocks:
 * - HW:     hardware interface
 * - DBG:    debug facilities (optional)
 * - UTIL:   utilities
 * - ISR:    interrupts handling
 * - ENDPT:  endpoint operations (Gadget API)
 * - GADGET: gadget operations (Gadget API)
 * - BUS:    bus glue code, bus abstraction layer
 *
 * Compile Options
 * - CONFIG_USB_GADGET_DEBUG_FILES: enable debug facilities
 * - STALL_IN:  non-empty bulk-in pipes cannot be halted
 *              if defined mass storage compliance succeeds but with warnings
 *              => case 4: Hi >  Dn
 *              => case 5: Hi >  Di
 *              => case 8: Hi <> Do
 *              if undefined usbtest 13 fails
 * - TRACE:     enable function tracing (depends on DEBUG)
 *
 * Main Features
 * - Chapter 9 & Mass Storage Compliance with Gadget File Storage
 * - Chapter 9 Compliance with Gadget Zero (STALL_IN undefined)
 * - Normal & LPM support
 *
 * USBTEST Report
 * - OK: 0-12, 13 (STALL_IN defined) & 14
 * - Not Supported: 15 & 16 (ISO)
 *
 * TODO List
 * - OTG
 * - Interrupt Traffic
 * - GET_STATUS(device) - always reports 0
 * - Gadget API (majority of optional features)
 * - Suspend & Remote Wakeup
 */
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/dma-mapping.h>
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/idr.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/pm_runtime.h>
#include <linux/usb/ch9.h>
#include <linux/usb/gadget.h>
#include <linux/usb/otg.h>
#include <linux/usb/chipidea.h>
#include <linux/usb/of.h>
#include <linux/phy.h>

#include "ci.h"
#include "udc.h"
#include "bits.h"
#include "host.h"
#include "debug.h"

/* Controller register map */
static uintptr_t ci_regs_nolpm[] = {
	[CAP_CAPLENGTH]		= 0x000UL,
	[CAP_HCCPARAMS]		= 0x008UL,
	[CAP_DCCPARAMS]		= 0x024UL,
	[CAP_TESTMODE]		= 0x038UL,
	[OP_USBCMD]		= 0x000UL,
	[OP_USBSTS]		= 0x004UL,
	[OP_USBINTR]		= 0x008UL,
	[OP_DEVICEADDR]		= 0x014UL,
	[OP_ENDPTLISTADDR]	= 0x018UL,
	[OP_PORTSC]		= 0x044UL,
	[OP_DEVLC]		= 0x084UL,
	[OP_OTGSC]		= 0x064UL,
	[OP_USBMODE]		= 0x068UL,
	[OP_ENDPTSETUPSTAT]	= 0x06CUL,
	[OP_ENDPTPRIME]		= 0x070UL,
	[OP_ENDPTFLUSH]		= 0x074UL,
	[OP_ENDPTSTAT]		= 0x078UL,
	[OP_ENDPTCOMPLETE]	= 0x07CUL,
	[OP_ENDPTCTRL]		= 0x080UL,
};

static uintptr_t ci_regs_lpm[] = {
	[CAP_CAPLENGTH]		= 0x000UL,
	[CAP_HCCPARAMS]		= 0x008UL,
	[CAP_DCCPARAMS]		= 0x024UL,
	[CAP_TESTMODE]		= 0x0FCUL,
	[OP_USBCMD]		= 0x000UL,
	[OP_USBSTS]		= 0x004UL,
	[OP_USBINTR]		= 0x008UL,
	[OP_DEVICEADDR]		= 0x014UL,
	[OP_ENDPTLISTADDR]	= 0x018UL,
	[OP_PORTSC]		= 0x044UL,
	[OP_DEVLC]		= 0x084UL,
	[OP_OTGSC]		= 0x0C4UL,
	[OP_USBMODE]		= 0x0C8UL,
	[OP_ENDPTSETUPSTAT]	= 0x0D8UL,
	[OP_ENDPTPRIME]		= 0x0DCUL,
	[OP_ENDPTFLUSH]		= 0x0E0UL,
	[OP_ENDPTSTAT]		= 0x0E4UL,
	[OP_ENDPTCOMPLETE]	= 0x0E8UL,
	[OP_ENDPTCTRL]		= 0x0ECUL,
};

static int hw_alloc_regmap(struct ci_hdrc *ci, bool is_lpm)
{
	int i;

	kfree(ci->hw_bank.regmap);

	ci->hw_bank.regmap = kzalloc((OP_LAST + 1) * sizeof(void *),
				     GFP_KERNEL);
	if (!ci->hw_bank.regmap)
		return -ENOMEM;

	for (i = 0; i < OP_ENDPTCTRL; i++)
		ci->hw_bank.regmap[i] =
			(i <= CAP_LAST ? ci->hw_bank.cap : ci->hw_bank.op) +
			(is_lpm ? ci_regs_lpm[i] : ci_regs_nolpm[i]);

	for (; i <= OP_LAST; i++)
		ci->hw_bank.regmap[i] = ci->hw_bank.op +
			4 * (i - OP_ENDPTCTRL) +
			(is_lpm
			 ? ci_regs_lpm[OP_ENDPTCTRL]
			 : ci_regs_nolpm[OP_ENDPTCTRL]);

	return 0;
}

/**
 * hw_port_test_set: writes port test mode (execute without interruption)
 * @mode: new value
 *
 * This function returns an error code
 */
int hw_port_test_set(struct ci_hdrc *ci, u8 mode)
{
	const u8 TEST_MODE_MAX = 7;

	if (mode > TEST_MODE_MAX)
		return -EINVAL;

	hw_write(ci, OP_PORTSC, PORTSC_PTC, mode << __ffs(PORTSC_PTC));
	return 0;
}

/**
 * hw_port_test_get: reads port test mode value
 *
 * This function returns port test mode value
 */
u8 hw_port_test_get(struct ci_hdrc *ci)
{
	return hw_read(ci, OP_PORTSC, PORTSC_PTC) >> __ffs(PORTSC_PTC);
}

static int hw_device_init(struct ci_hdrc *ci, void __iomem *base)
{
	u32 reg;

	/* bank is a module variable */
	ci->hw_bank.abs = base;

	ci->hw_bank.cap = ci->hw_bank.abs;
	ci->hw_bank.cap += ci->platdata->capoffset;
	ci->hw_bank.op = ci->hw_bank.cap + (ioread32(ci->hw_bank.cap) & 0xff);

	hw_alloc_regmap(ci, false);
	reg = hw_read(ci, CAP_HCCPARAMS, HCCPARAMS_LEN) >>
		__ffs(HCCPARAMS_LEN);
	ci->hw_bank.lpm  = reg;
	hw_alloc_regmap(ci, !!reg);
	ci->hw_bank.size = ci->hw_bank.op - ci->hw_bank.abs;
	ci->hw_bank.size += OP_LAST;
	ci->hw_bank.size /= sizeof(u32);

	reg = hw_read(ci, CAP_DCCPARAMS, DCCPARAMS_DEN) >>
		__ffs(DCCPARAMS_DEN);
	ci->hw_ep_max = reg * 2;   /* cache hw ENDPT_MAX */

	if (ci->hw_ep_max > ENDPT_MAX)
		return -ENODEV;

	dev_dbg(ci->dev, "ChipIdea HDRC found, lpm: %d; cap: %p op: %p\n",
		ci->hw_bank.lpm, ci->hw_bank.cap, ci->hw_bank.op);

	/* setup lock mode ? */

	/* ENDPTSETUPSTAT is '0' by default */

	/* HCSPARAMS.bf.ppc SHOULD BE zero for device */

	return 0;
}

static void hw_phymode_configure(struct ci_hdrc *ci)
{
	u32 portsc, lpm, sts;

	switch (ci->platdata->phy_mode) {
	case USBPHY_INTERFACE_MODE_UTMI:
		portsc = PORTSC_PTS(PTS_UTMI);
		lpm = DEVLC_PTS(PTS_UTMI);
		break;
	case USBPHY_INTERFACE_MODE_UTMIW:
		portsc = PORTSC_PTS(PTS_UTMI) | PORTSC_PTW;
		lpm = DEVLC_PTS(PTS_UTMI) | DEVLC_PTW;
		break;
	case USBPHY_INTERFACE_MODE_ULPI:
		portsc = PORTSC_PTS(PTS_ULPI);
		lpm = DEVLC_PTS(PTS_ULPI);
		break;
	case USBPHY_INTERFACE_MODE_SERIAL:
		portsc = PORTSC_PTS(PTS_SERIAL);
		lpm = DEVLC_PTS(PTS_SERIAL);
		sts = 1;
		break;
	case USBPHY_INTERFACE_MODE_HSIC:
		portsc = PORTSC_PTS(PTS_HSIC);
		lpm = DEVLC_PTS(PTS_HSIC);
		break;
	default:
		return;
	}

	if (ci->hw_bank.lpm) {
		hw_write(ci, OP_DEVLC, DEVLC_PTS(7) | DEVLC_PTW, lpm);
		hw_write(ci, OP_DEVLC, DEVLC_STS, sts);
	} else {
		hw_write(ci, OP_PORTSC, PORTSC_PTS(7) | PORTSC_PTW, portsc);
		hw_write(ci, OP_PORTSC, PORTSC_STS, sts);
	}
}

/**
 * hw_device_reset: resets chip (execute without interruption)
 * @ci: the controller
  *
 * This function returns an error code
 */
int hw_device_reset(struct ci_hdrc *ci, u32 mode)
{
	/* should flush & stop before reset */
	hw_write(ci, OP_ENDPTFLUSH, ~0, ~0);
	hw_write(ci, OP_USBCMD, USBCMD_RS, 0);

	hw_write(ci, OP_USBCMD, USBCMD_RST, USBCMD_RST);
	while (hw_read(ci, OP_USBCMD, USBCMD_RST))
		udelay(10);		/* not RTOS friendly */

	if (ci->platdata->notify_event)
		ci->platdata->notify_event(ci,
			CI_HDRC_CONTROLLER_RESET_EVENT);

	if (ci->platdata->flags & CI_HDRC_DISABLE_STREAMING)
		hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS, USBMODE_CI_SDIS);

	/* USBMODE should be configured step by step */
	hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE);
	hw_write(ci, OP_USBMODE, USBMODE_CM, mode);
	/* HW >= 2.3 */
	hw_write(ci, OP_USBMODE, USBMODE_SLOM, USBMODE_SLOM);

	if (hw_read(ci, OP_USBMODE, USBMODE_CM) != mode) {
		pr_err("cannot enter in %s mode", ci_role(ci)->name);
		pr_err("lpm = %i", ci->hw_bank.lpm);
		return -ENODEV;
	}

	return 0;
}

/**
 * ci_otg_role - pick role based on ID pin state
 * @ci: the controller
 */
static enum ci_role ci_otg_role(struct ci_hdrc *ci)
{
	u32 sts = hw_read(ci, OP_OTGSC, ~0);
	enum ci_role role = sts & OTGSC_ID
		? CI_ROLE_GADGET
		: CI_ROLE_HOST;

	return role;
}

/**
 * ci_role_work - perform role changing based on ID pin
 * @work: work struct
 */
static void ci_role_work(struct work_struct *work)
{
	struct ci_hdrc *ci = container_of(work, struct ci_hdrc, work);
	enum ci_role role = ci_otg_role(ci);

	if (role != ci->role) {
		dev_dbg(ci->dev, "switching from %s to %s\n",
			ci_role(ci)->name, ci->roles[role]->name);

		ci_role_stop(ci);
		ci_role_start(ci, role);
	}

	enable_irq(ci->irq);
}

static irqreturn_t ci_irq(int irq, void *data)
{
	struct ci_hdrc *ci = data;
	irqreturn_t ret = IRQ_NONE;
	u32 otgsc = 0;

	if (ci->is_otg)
		otgsc = hw_read(ci, OP_OTGSC, ~0);

	if (ci->role != CI_ROLE_END)
		ret = ci_role(ci)->irq(ci);

	if (ci->is_otg && (otgsc & OTGSC_IDIS)) {
		hw_write(ci, OP_OTGSC, OTGSC_IDIS, OTGSC_IDIS);
		disable_irq_nosync(ci->irq);
		queue_work(ci->wq, &ci->work);
		ret = IRQ_HANDLED;
	}

	return ret;
}

static DEFINE_IDA(ci_ida);

struct platform_device *ci_hdrc_add_device(struct device *dev,
			struct resource *res, int nres,
			struct ci_hdrc_platform_data *platdata)
{
	struct platform_device *pdev;
	int id, ret;

	id = ida_simple_get(&ci_ida, 0, 0, GFP_KERNEL);
	if (id < 0)
		return ERR_PTR(id);

	pdev = platform_device_alloc("ci_hdrc", id);
	if (!pdev) {
		ret = -ENOMEM;
		goto put_id;
	}

	pdev->dev.parent = dev;
	pdev->dev.dma_mask = dev->dma_mask;
	pdev->dev.dma_parms = dev->dma_parms;
	dma_set_coherent_mask(&pdev->dev, dev->coherent_dma_mask);

	ret = platform_device_add_resources(pdev, res, nres);
	if (ret)
		goto err;

	ret = platform_device_add_data(pdev, platdata, sizeof(*platdata));
	if (ret)
		goto err;

	ret = platform_device_add(pdev);
	if (ret)
		goto err;

	return pdev;

err:
	platform_device_put(pdev);
put_id:
	ida_simple_remove(&ci_ida, id);
	return ERR_PTR(ret);
}
EXPORT_SYMBOL_GPL(ci_hdrc_add_device);

void ci_hdrc_remove_device(struct platform_device *pdev)
{
	int id = pdev->id;
	platform_device_unregister(pdev);
	ida_simple_remove(&ci_ida, id);
}
EXPORT_SYMBOL_GPL(ci_hdrc_remove_device);

static int ci_hdrc_probe(struct platform_device *pdev)
{
	struct device	*dev = &pdev->dev;
	struct ci_hdrc	*ci;
	struct resource	*res;
	void __iomem	*base;
	int		ret;
	enum usb_dr_mode dr_mode;
	struct device_node *of_node = dev->of_node ?: dev->parent->of_node;

	if (!dev->platform_data) {
		dev_err(dev, "platform data missing\n");
		return -ENODEV;
	}

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	base = devm_ioremap_resource(dev, res);
	if (IS_ERR(base))
		return PTR_ERR(base);

	ci = devm_kzalloc(dev, sizeof(*ci), GFP_KERNEL);
	if (!ci) {
		dev_err(dev, "can't allocate device\n");
		return -ENOMEM;
	}

	ci->dev = dev;
	ci->platdata = dev->platform_data;
	if (ci->platdata->phy)
		ci->transceiver = ci->platdata->phy;
	else
		ci->global_phy = true;

	ret = hw_device_init(ci, base);
	if (ret < 0) {
		dev_err(dev, "can't initialize hardware\n");
		return -ENODEV;
	}

	ci->hw_bank.phys = res->start;

	ci->irq = platform_get_irq(pdev, 0);
	if (ci->irq < 0) {
		dev_err(dev, "missing IRQ\n");
		return -ENODEV;
	}

	INIT_WORK(&ci->work, ci_role_work);
	ci->wq = create_singlethread_workqueue("ci_otg");
	if (!ci->wq) {
		dev_err(dev, "can't create workqueue\n");
		return -ENODEV;
	}

	if (!ci->platdata->phy_mode)
		ci->platdata->phy_mode = of_usb_get_phy_mode(of_node);

	hw_phymode_configure(ci);

	if (!ci->platdata->dr_mode)
		ci->platdata->dr_mode = of_usb_get_dr_mode(of_node);

	if (ci->platdata->dr_mode == USB_DR_MODE_UNKNOWN)
		ci->platdata->dr_mode = USB_DR_MODE_OTG;

	dr_mode = ci->platdata->dr_mode;
	/* initialize role(s) before the interrupt is requested */
	if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_HOST) {
		ret = ci_hdrc_host_init(ci);
		if (ret)
			dev_info(dev, "doesn't support host\n");
	}

	if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_PERIPHERAL) {
		ret = ci_hdrc_gadget_init(ci);
		if (ret)
			dev_info(dev, "doesn't support gadget\n");
	}

	if (!ci->roles[CI_ROLE_HOST] && !ci->roles[CI_ROLE_GADGET]) {
		dev_err(dev, "no supported roles\n");
		ret = -ENODEV;
		goto rm_wq;
	}

	if (ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET]) {
		ci->is_otg = true;
		/* ID pin needs 1ms debouce time, we delay 2ms for safe */
		mdelay(2);
		ci->role = ci_otg_role(ci);
	} else {
		ci->role = ci->roles[CI_ROLE_HOST]
			? CI_ROLE_HOST
			: CI_ROLE_GADGET;
	}

	ret = ci_role_start(ci, ci->role);
	if (ret) {
		dev_err(dev, "can't start %s role\n", ci_role(ci)->name);
		goto rm_wq;
	}

	platform_set_drvdata(pdev, ci);
	ret = request_irq(ci->irq, ci_irq, IRQF_SHARED, ci->platdata->name,
			  ci);
	if (ret)
		goto stop;

	if (ci->is_otg)
		hw_write(ci, OP_OTGSC, OTGSC_IDIE, OTGSC_IDIE);

	ret = dbg_create_files(ci);
	if (!ret)
		return 0;

	free_irq(ci->irq, ci);
stop:
	ci_role_stop(ci);
rm_wq:
	flush_workqueue(ci->wq);
	destroy_workqueue(ci->wq);

	return ret;
}

static int ci_hdrc_remove(struct platform_device *pdev)
{
	struct ci_hdrc *ci = platform_get_drvdata(pdev);

	dbg_remove_files(ci);
	flush_workqueue(ci->wq);
	destroy_workqueue(ci->wq);
	free_irq(ci->irq, ci);
	ci_role_stop(ci);

	return 0;
}

static struct platform_driver ci_hdrc_driver = {
	.probe	= ci_hdrc_probe,
	.remove	= ci_hdrc_remove,
	.driver	= {
		.name	= "ci_hdrc",
	},
};

module_platform_driver(ci_hdrc_driver);

MODULE_ALIAS("platform:ci_hdrc");
MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("David Lopo <dlopo@chipidea.mips.com>");
MODULE_DESCRIPTION("ChipIdea HDRC Driver");
Commit	Line	Data
e443b333 AS	1	/*
	2	* core.c - ChipIdea USB IP core family device controller
	3	*
	4	* Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
	5	*
	6	* Author: David Lopo
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*/
	12
	13	/*
	14	* Description: ChipIdea USB IP core family device controller
	15	*
	16	* This driver is composed of several blocks:
	17	* - HW: hardware interface
	18	* - DBG: debug facilities (optional)
	19	* - UTIL: utilities
	20	* - ISR: interrupts handling
	21	* - ENDPT: endpoint operations (Gadget API)
	22	* - GADGET: gadget operations (Gadget API)
	23	* - BUS: bus glue code, bus abstraction layer
	24	*
	25	* Compile Options
	26	* - CONFIG_USB_GADGET_DEBUG_FILES: enable debug facilities
	27	* - STALL_IN: non-empty bulk-in pipes cannot be halted
	28	* if defined mass storage compliance succeeds but with warnings
	29	* => case 4: Hi > Dn
	30	* => case 5: Hi > Di
	31	* => case 8: Hi <> Do
	32	* if undefined usbtest 13 fails
	33	* - TRACE: enable function tracing (depends on DEBUG)
	34	*
	35	* Main Features
	36	* - Chapter 9 & Mass Storage Compliance with Gadget File Storage
	37	* - Chapter 9 Compliance with Gadget Zero (STALL_IN undefined)
	38	* - Normal & LPM support
	39	*
	40	* USBTEST Report
	41	* - OK: 0-12, 13 (STALL_IN defined) & 14
	42	* - Not Supported: 15 & 16 (ISO)
	43	*
	44	* TODO List
	45	* - OTG
e4ce4ecd	46	* - Interrupt Traffic
e443b333 AS	47	* - GET_STATUS(device) - always reports 0
	48	* - Gadget API (majority of optional features)
	49	* - Suspend & Remote Wakeup
	50	*/
	51	#include <linux/delay.h>
	52	#include <linux/device.h>
e443b333	53	#include <linux/dma-mapping.h>
e443b333 AS	54	#include <linux/platform_device.h>
e443b333 AS	55	#include <linux/module.h>
fe6e125e	56	#include <linux/idr.h>
e443b333 AS	57	#include <linux/interrupt.h>
e443b333 AS	58	#include <linux/io.h>
e443b333 AS	59	#include <linux/kernel.h>
	60	#include <linux/slab.h>
	61	#include <linux/pm_runtime.h>
	62	#include <linux/usb/ch9.h>
	63	#include <linux/usb/gadget.h>
	64	#include <linux/usb/otg.h>
	65	#include <linux/usb/chipidea.h>
40dcd0e8 MG	66	#include <linux/usb/of.h>
40dcd0e8 MG	67	#include <linux/phy.h>
e443b333 AS	68
	69	#include "ci.h"
	70	#include "udc.h"
	71	#include "bits.h"
eb70e5ab	72	#include "host.h"
e443b333 AS	73	#include "debug.h"
e443b333 AS	74
5f36e231	75	/* Controller register map */
e443b333 AS	76	static uintptr_t ci_regs_nolpm[] = {
	77	[CAP_CAPLENGTH] = 0x000UL,
	78	[CAP_HCCPARAMS] = 0x008UL,
	79	[CAP_DCCPARAMS] = 0x024UL,
	80	[CAP_TESTMODE] = 0x038UL,
	81	[OP_USBCMD] = 0x000UL,
	82	[OP_USBSTS] = 0x004UL,
	83	[OP_USBINTR] = 0x008UL,
	84	[OP_DEVICEADDR] = 0x014UL,
	85	[OP_ENDPTLISTADDR] = 0x018UL,
	86	[OP_PORTSC] = 0x044UL,
	87	[OP_DEVLC] = 0x084UL,
5f36e231	88	[OP_OTGSC] = 0x064UL,
e443b333 AS	89	[OP_USBMODE] = 0x068UL,
	90	[OP_ENDPTSETUPSTAT] = 0x06CUL,
	91	[OP_ENDPTPRIME] = 0x070UL,
	92	[OP_ENDPTFLUSH] = 0x074UL,
	93	[OP_ENDPTSTAT] = 0x078UL,
	94	[OP_ENDPTCOMPLETE] = 0x07CUL,
	95	[OP_ENDPTCTRL] = 0x080UL,
	96	};
	97
	98	static uintptr_t ci_regs_lpm[] = {
	99	[CAP_CAPLENGTH] = 0x000UL,
	100	[CAP_HCCPARAMS] = 0x008UL,
	101	[CAP_DCCPARAMS] = 0x024UL,
	102	[CAP_TESTMODE] = 0x0FCUL,
	103	[OP_USBCMD] = 0x000UL,
	104	[OP_USBSTS] = 0x004UL,
	105	[OP_USBINTR] = 0x008UL,
	106	[OP_DEVICEADDR] = 0x014UL,
	107	[OP_ENDPTLISTADDR] = 0x018UL,
	108	[OP_PORTSC] = 0x044UL,
	109	[OP_DEVLC] = 0x084UL,
5f36e231	110	[OP_OTGSC] = 0x0C4UL,
e443b333 AS	111	[OP_USBMODE] = 0x0C8UL,
	112	[OP_ENDPTSETUPSTAT] = 0x0D8UL,
	113	[OP_ENDPTPRIME] = 0x0DCUL,
	114	[OP_ENDPTFLUSH] = 0x0E0UL,
	115	[OP_ENDPTSTAT] = 0x0E4UL,
	116	[OP_ENDPTCOMPLETE] = 0x0E8UL,
	117	[OP_ENDPTCTRL] = 0x0ECUL,
	118	};
	119
8e22978c	120	static int hw_alloc_regmap(struct ci_hdrc *ci, bool is_lpm)
e443b333 AS	121	{
	122	int i;
	123
5f36e231	124	kfree(ci->hw_bank.regmap);
e443b333	125
5f36e231 AS	126	ci->hw_bank.regmap = kzalloc((OP_LAST + 1) * sizeof(void *),
	127	GFP_KERNEL);
	128	if (!ci->hw_bank.regmap)
e443b333 AS	129	return -ENOMEM;
	130
	131	for (i = 0; i < OP_ENDPTCTRL; i++)
5f36e231 AS	132	ci->hw_bank.regmap[i] =
5f36e231 AS	133	(i <= CAP_LAST ? ci->hw_bank.cap : ci->hw_bank.op) +
e443b333 AS	134	(is_lpm ? ci_regs_lpm[i] : ci_regs_nolpm[i]);
	135
	136	for (; i <= OP_LAST; i++)
5f36e231	137	ci->hw_bank.regmap[i] = ci->hw_bank.op +
e443b333 AS	138	4 * (i - OP_ENDPTCTRL) +
	139	(is_lpm
	140	? ci_regs_lpm[OP_ENDPTCTRL]
	141	: ci_regs_nolpm[OP_ENDPTCTRL]);
	142
	143	return 0;
	144	}
	145
	146	/**
	147	* hw_port_test_set: writes port test mode (execute without interruption)
	148	* @mode: new value
	149	*
	150	* This function returns an error code
	151	*/
8e22978c	152	int hw_port_test_set(struct ci_hdrc *ci, u8 mode)
e443b333 AS	153	{
	154	const u8 TEST_MODE_MAX = 7;
	155
	156	if (mode > TEST_MODE_MAX)
	157	return -EINVAL;
	158
727b4ddb	159	hw_write(ci, OP_PORTSC, PORTSC_PTC, mode << __ffs(PORTSC_PTC));
e443b333 AS	160	return 0;
	161	}
	162
	163	/**
	164	* hw_port_test_get: reads port test mode value
	165	*
	166	* This function returns port test mode value
	167	*/
8e22978c	168	u8 hw_port_test_get(struct ci_hdrc *ci)
e443b333	169	{
727b4ddb	170	return hw_read(ci, OP_PORTSC, PORTSC_PTC) >> __ffs(PORTSC_PTC);
e443b333 AS	171	}
e443b333 AS	172
8e22978c	173	static int hw_device_init(struct ci_hdrc ci, void __iomem base)
e443b333 AS	174	{
	175	u32 reg;
	176
	177	/* bank is a module variable */
5f36e231	178	ci->hw_bank.abs = base;
e443b333	179
5f36e231	180	ci->hw_bank.cap = ci->hw_bank.abs;
77c4400f	181	ci->hw_bank.cap += ci->platdata->capoffset;
938d323f	182	ci->hw_bank.op = ci->hw_bank.cap + (ioread32(ci->hw_bank.cap) & 0xff);
e443b333	183
5f36e231 AS	184	hw_alloc_regmap(ci, false);
5f36e231 AS	185	reg = hw_read(ci, CAP_HCCPARAMS, HCCPARAMS_LEN) >>
727b4ddb	186	__ffs(HCCPARAMS_LEN);
5f36e231 AS	187	ci->hw_bank.lpm = reg;
	188	hw_alloc_regmap(ci, !!reg);
	189	ci->hw_bank.size = ci->hw_bank.op - ci->hw_bank.abs;
	190	ci->hw_bank.size += OP_LAST;
	191	ci->hw_bank.size /= sizeof(u32);
e443b333	192
5f36e231	193	reg = hw_read(ci, CAP_DCCPARAMS, DCCPARAMS_DEN) >>
727b4ddb	194	__ffs(DCCPARAMS_DEN);
5f36e231	195	ci->hw_ep_max = reg * 2; /* cache hw ENDPT_MAX */
e443b333	196
09c94e62	197	if (ci->hw_ep_max > ENDPT_MAX)
e443b333 AS	198	return -ENODEV;
e443b333 AS	199
5f36e231 AS	200	dev_dbg(ci->dev, "ChipIdea HDRC found, lpm: %d; cap: %p op: %p\n",
5f36e231 AS	201	ci->hw_bank.lpm, ci->hw_bank.cap, ci->hw_bank.op);
e443b333 AS	202
	203	/* setup lock mode ? */
	204
	205	/* ENDPTSETUPSTAT is '0' by default */
	206
	207	/* HCSPARAMS.bf.ppc SHOULD BE zero for device */
	208
	209	return 0;
	210	}
	211
8e22978c	212	static void hw_phymode_configure(struct ci_hdrc *ci)
40dcd0e8 MG	213	{
	214	u32 portsc, lpm, sts;
	215
	216	switch (ci->platdata->phy_mode) {
	217	case USBPHY_INTERFACE_MODE_UTMI:
	218	portsc = PORTSC_PTS(PTS_UTMI);
	219	lpm = DEVLC_PTS(PTS_UTMI);
	220	break;
	221	case USBPHY_INTERFACE_MODE_UTMIW:
	222	portsc = PORTSC_PTS(PTS_UTMI) \| PORTSC_PTW;
	223	lpm = DEVLC_PTS(PTS_UTMI) \| DEVLC_PTW;
	224	break;
	225	case USBPHY_INTERFACE_MODE_ULPI:
	226	portsc = PORTSC_PTS(PTS_ULPI);
	227	lpm = DEVLC_PTS(PTS_ULPI);
	228	break;
	229	case USBPHY_INTERFACE_MODE_SERIAL:
	230	portsc = PORTSC_PTS(PTS_SERIAL);
	231	lpm = DEVLC_PTS(PTS_SERIAL);
	232	sts = 1;
	233	break;
	234	case USBPHY_INTERFACE_MODE_HSIC:
	235	portsc = PORTSC_PTS(PTS_HSIC);
	236	lpm = DEVLC_PTS(PTS_HSIC);
	237	break;
	238	default:
	239	return;
	240	}
	241
	242	if (ci->hw_bank.lpm) {
	243	hw_write(ci, OP_DEVLC, DEVLC_PTS(7) \| DEVLC_PTW, lpm);
	244	hw_write(ci, OP_DEVLC, DEVLC_STS, sts);
	245	} else {
	246	hw_write(ci, OP_PORTSC, PORTSC_PTS(7) \| PORTSC_PTW, portsc);
	247	hw_write(ci, OP_PORTSC, PORTSC_STS, sts);
	248	}
	249	}
	250
e443b333 AS	251	/**
	252	* hw_device_reset: resets chip (execute without interruption)
	253	* @ci: the controller
	254	*
	255	* This function returns an error code
	256	*/
8e22978c	257	int hw_device_reset(struct ci_hdrc *ci, u32 mode)
e443b333 AS	258	{
	259	/* should flush & stop before reset */
	260	hw_write(ci, OP_ENDPTFLUSH, ~0, ~0);
	261	hw_write(ci, OP_USBCMD, USBCMD_RS, 0);
	262
	263	hw_write(ci, OP_USBCMD, USBCMD_RST, USBCMD_RST);
	264	while (hw_read(ci, OP_USBCMD, USBCMD_RST))
	265	udelay(10); /* not RTOS friendly */
	266
77c4400f RZ	267	if (ci->platdata->notify_event)
77c4400f RZ	268	ci->platdata->notify_event(ci,
8e22978c	269	CI_HDRC_CONTROLLER_RESET_EVENT);
e443b333	270
8e22978c	271	if (ci->platdata->flags & CI_HDRC_DISABLE_STREAMING)
758fc986	272	hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS, USBMODE_CI_SDIS);
e443b333 AS	273
	274	/* USBMODE should be configured step by step */
	275	hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE);
eb70e5ab	276	hw_write(ci, OP_USBMODE, USBMODE_CM, mode);
e443b333 AS	277	/* HW >= 2.3 */
	278	hw_write(ci, OP_USBMODE, USBMODE_SLOM, USBMODE_SLOM);
	279
eb70e5ab AS	280	if (hw_read(ci, OP_USBMODE, USBMODE_CM) != mode) {
eb70e5ab AS	281	pr_err("cannot enter in %s mode", ci_role(ci)->name);
e443b333 AS	282	pr_err("lpm = %i", ci->hw_bank.lpm);
	283	return -ENODEV;
	284	}
	285
	286	return 0;
	287	}
	288
5f36e231 AS	289	/**
	290	* ci_otg_role - pick role based on ID pin state
	291	* @ci: the controller
	292	*/
8e22978c	293	static enum ci_role ci_otg_role(struct ci_hdrc *ci)
5f36e231 AS	294	{
	295	u32 sts = hw_read(ci, OP_OTGSC, ~0);
	296	enum ci_role role = sts & OTGSC_ID
	297	? CI_ROLE_GADGET
	298	: CI_ROLE_HOST;
	299
	300	return role;
	301	}
	302
	303	/**
	304	* ci_role_work - perform role changing based on ID pin
	305	* @work: work struct
	306	*/
	307	static void ci_role_work(struct work_struct *work)
	308	{
8e22978c	309	struct ci_hdrc *ci = container_of(work, struct ci_hdrc, work);
5f36e231 AS	310	enum ci_role role = ci_otg_role(ci);
5f36e231 AS	311
5f36e231 AS	312	if (role != ci->role) {
	313	dev_dbg(ci->dev, "switching from %s to %s\n",
	314	ci_role(ci)->name, ci->roles[role]->name);
	315
	316	ci_role_stop(ci);
	317	ci_role_start(ci, role);
	318	}
0c3f3dc6 AS	319
0c3f3dc6 AS	320	enable_irq(ci->irq);
5f36e231 AS	321	}
5f36e231 AS	322
5f36e231 AS	323	static irqreturn_t ci_irq(int irq, void *data)
5f36e231 AS	324	{
8e22978c	325	struct ci_hdrc *ci = data;
5f36e231	326	irqreturn_t ret = IRQ_NONE;
b183c19f	327	u32 otgsc = 0;
5f36e231	328
b183c19f RZ	329	if (ci->is_otg)
b183c19f RZ	330	otgsc = hw_read(ci, OP_OTGSC, ~0);
5f36e231	331
b183c19f RZ	332	if (ci->role != CI_ROLE_END)
	333	ret = ci_role(ci)->irq(ci);
	334
	335	if (ci->is_otg && (otgsc & OTGSC_IDIS)) {
	336	hw_write(ci, OP_OTGSC, OTGSC_IDIS, OTGSC_IDIS);
	337	disable_irq_nosync(ci->irq);
	338	queue_work(ci->wq, &ci->work);
	339	ret = IRQ_HANDLED;
5f36e231 AS	340	}
5f36e231 AS	341
b183c19f	342	return ret;
5f36e231 AS	343	}
5f36e231 AS	344
fe6e125e RZ	345	static DEFINE_IDA(ci_ida);
fe6e125e RZ	346
8e22978c	347	struct platform_device ci_hdrc_add_device(struct device dev,
cbc6dc2a	348	struct resource *res, int nres,
8e22978c	349	struct ci_hdrc_platform_data *platdata)
cbc6dc2a RZ	350	{
cbc6dc2a RZ	351	struct platform_device *pdev;
fe6e125e	352	int id, ret;
cbc6dc2a	353
fe6e125e RZ	354	id = ida_simple_get(&ci_ida, 0, 0, GFP_KERNEL);
	355	if (id < 0)
	356	return ERR_PTR(id);
	357
	358	pdev = platform_device_alloc("ci_hdrc", id);
	359	if (!pdev) {
	360	ret = -ENOMEM;
	361	goto put_id;
	362	}
cbc6dc2a RZ	363
	364	pdev->dev.parent = dev;
	365	pdev->dev.dma_mask = dev->dma_mask;
	366	pdev->dev.dma_parms = dev->dma_parms;
	367	dma_set_coherent_mask(&pdev->dev, dev->coherent_dma_mask);
	368
	369	ret = platform_device_add_resources(pdev, res, nres);
	370	if (ret)
	371	goto err;
	372
	373	ret = platform_device_add_data(pdev, platdata, sizeof(*platdata));
	374	if (ret)
	375	goto err;
	376
	377	ret = platform_device_add(pdev);
	378	if (ret)
	379	goto err;
	380
	381	return pdev;
	382
	383	err:
	384	platform_device_put(pdev);
fe6e125e RZ	385	put_id:
fe6e125e RZ	386	ida_simple_remove(&ci_ida, id);
cbc6dc2a RZ	387	return ERR_PTR(ret);
cbc6dc2a RZ	388	}
8e22978c	389	EXPORT_SYMBOL_GPL(ci_hdrc_add_device);
cbc6dc2a	390
8e22978c	391	void ci_hdrc_remove_device(struct platform_device *pdev)
cbc6dc2a	392	{
98c35534	393	int id = pdev->id;
cbc6dc2a	394	platform_device_unregister(pdev);
98c35534	395	ida_simple_remove(&ci_ida, id);
cbc6dc2a	396	}
8e22978c	397	EXPORT_SYMBOL_GPL(ci_hdrc_remove_device);
cbc6dc2a	398
41ac7b3a	399	static int ci_hdrc_probe(struct platform_device *pdev)
e443b333 AS	400	{
e443b333 AS	401	struct device *dev = &pdev->dev;
8e22978c	402	struct ci_hdrc *ci;
e443b333 AS	403	struct resource *res;
	404	void __iomem *base;
	405	int ret;
691962d1	406	enum usb_dr_mode dr_mode;
e98b44e9	407	struct device_node *of_node = dev->of_node ?: dev->parent->of_node;
e443b333	408
5f36e231	409	if (!dev->platform_data) {
e443b333 AS	410	dev_err(dev, "platform data missing\n");
	411	return -ENODEV;
	412	}
	413
	414	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
19290816 FB	415	base = devm_ioremap_resource(dev, res);
	416	if (IS_ERR(base))
	417	return PTR_ERR(base);
e443b333	418
5f36e231 AS	419	ci = devm_kzalloc(dev, sizeof(*ci), GFP_KERNEL);
	420	if (!ci) {
	421	dev_err(dev, "can't allocate device\n");
	422	return -ENOMEM;
	423	}
	424
	425	ci->dev = dev;
77c4400f	426	ci->platdata = dev->platform_data;
a2c3d690 RZ	427	if (ci->platdata->phy)
	428	ci->transceiver = ci->platdata->phy;
	429	else
	430	ci->global_phy = true;
5f36e231 AS	431
	432	ret = hw_device_init(ci, base);
	433	if (ret < 0) {
	434	dev_err(dev, "can't initialize hardware\n");
	435	return -ENODEV;
	436	}
e443b333	437
eb70e5ab AS	438	ci->hw_bank.phys = res->start;
eb70e5ab AS	439
5f36e231 AS	440	ci->irq = platform_get_irq(pdev, 0);
5f36e231 AS	441	if (ci->irq < 0) {
e443b333	442	dev_err(dev, "missing IRQ\n");
5f36e231 AS	443	return -ENODEV;
	444	}
	445
	446	INIT_WORK(&ci->work, ci_role_work);
	447	ci->wq = create_singlethread_workqueue("ci_otg");
	448	if (!ci->wq) {
	449	dev_err(dev, "can't create workqueue\n");
	450	return -ENODEV;
	451	}
	452
40dcd0e8	453	if (!ci->platdata->phy_mode)
e98b44e9	454	ci->platdata->phy_mode = of_usb_get_phy_mode(of_node);
40dcd0e8	455
03779f05 FE	456	hw_phymode_configure(ci);
03779f05 FE	457
691962d1	458	if (!ci->platdata->dr_mode)
e98b44e9	459	ci->platdata->dr_mode = of_usb_get_dr_mode(of_node);
691962d1 SH	460
	461	if (ci->platdata->dr_mode == USB_DR_MODE_UNKNOWN)
	462	ci->platdata->dr_mode = USB_DR_MODE_OTG;
	463
	464	dr_mode = ci->platdata->dr_mode;
5f36e231	465	/* initialize role(s) before the interrupt is requested */
691962d1 SH	466	if (dr_mode == USB_DR_MODE_OTG \|\| dr_mode == USB_DR_MODE_HOST) {
	467	ret = ci_hdrc_host_init(ci);
	468	if (ret)
	469	dev_info(dev, "doesn't support host\n");
	470	}
eb70e5ab	471
691962d1 SH	472	if (dr_mode == USB_DR_MODE_OTG \|\| dr_mode == USB_DR_MODE_PERIPHERAL) {
	473	ret = ci_hdrc_gadget_init(ci);
	474	if (ret)
	475	dev_info(dev, "doesn't support gadget\n");
	476	}
5f36e231 AS	477
	478	if (!ci->roles[CI_ROLE_HOST] && !ci->roles[CI_ROLE_GADGET]) {
	479	dev_err(dev, "no supported roles\n");
	480	ret = -ENODEV;
	481	goto rm_wq;
	482	}
	483
	484	if (ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET]) {
	485	ci->is_otg = true;
86ad01a9 RZ	486	/* ID pin needs 1ms debouce time, we delay 2ms for safe */
86ad01a9 RZ	487	mdelay(2);
5f36e231 AS	488	ci->role = ci_otg_role(ci);
	489	} else {
	490	ci->role = ci->roles[CI_ROLE_HOST]
	491	? CI_ROLE_HOST
	492	: CI_ROLE_GADGET;
	493	}
	494
	495	ret = ci_role_start(ci, ci->role);
	496	if (ret) {
	497	dev_err(dev, "can't start %s role\n", ci_role(ci)->name);
5f36e231	498	goto rm_wq;
e443b333 AS	499	}
e443b333 AS	500
5f36e231	501	platform_set_drvdata(pdev, ci);
77c4400f	502	ret = request_irq(ci->irq, ci_irq, IRQF_SHARED, ci->platdata->name,
5f36e231 AS	503	ci);
	504	if (ret)
	505	goto stop;
e443b333	506
5f36e231 AS	507	if (ci->is_otg)
	508	hw_write(ci, OP_OTGSC, OTGSC_IDIE, OTGSC_IDIE);
	509
adf0f735 AS	510	ret = dbg_create_files(ci);
	511	if (!ret)
	512	return 0;
5f36e231	513
adf0f735	514	free_irq(ci->irq, ci);
5f36e231 AS	515	stop:
	516	ci_role_stop(ci);
	517	rm_wq:
	518	flush_workqueue(ci->wq);
	519	destroy_workqueue(ci->wq);
e443b333 AS	520
	521	return ret;
	522	}
	523
fb4e98ab	524	static int ci_hdrc_remove(struct platform_device *pdev)
e443b333	525	{
8e22978c	526	struct ci_hdrc *ci = platform_get_drvdata(pdev);
e443b333	527
adf0f735	528	dbg_remove_files(ci);
5f36e231 AS	529	flush_workqueue(ci->wq);
5f36e231 AS	530	destroy_workqueue(ci->wq);
5f36e231 AS	531	free_irq(ci->irq, ci);
5f36e231 AS	532	ci_role_stop(ci);
e443b333 AS	533
	534	return 0;
	535	}
	536
5f36e231 AS	537	static struct platform_driver ci_hdrc_driver = {
5f36e231 AS	538	.probe = ci_hdrc_probe,
7690417d	539	.remove = ci_hdrc_remove,
e443b333	540	.driver = {
5f36e231	541	.name = "ci_hdrc",
e443b333 AS	542	},
	543	};
	544
5f36e231	545	module_platform_driver(ci_hdrc_driver);
e443b333	546
5f36e231	547	MODULE_ALIAS("platform:ci_hdrc");
e443b333 AS	548	MODULE_LICENSE("GPL v2");
e443b333 AS	549	MODULE_AUTHOR("David Lopo <dlopo@chipidea.mips.com>");
5f36e231	550	MODULE_DESCRIPTION("ChipIdea HDRC Driver");