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usb: chipidea: usbmisc_imx: Read MX53_USB_OTG_PHY_CTRL_1_OFFSET directly
[linux-2.6-block.git] / drivers / usb / chipidea / core.c
CommitLineData
e443b333
AS		 1/*
2 * core.c - ChipIdea USB IP core family device controller
3 *
4 * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
5 *
6 * Author: David Lopo
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13/*
14 * Description: ChipIdea USB IP core family device controller
15 *
16 * This driver is composed of several blocks:
17 * - HW: hardware interface
18 * - DBG: debug facilities (optional)
19 * - UTIL: utilities
20 * - ISR: interrupts handling
21 * - ENDPT: endpoint operations (Gadget API)
22 * - GADGET: gadget operations (Gadget API)
23 * - BUS: bus glue code, bus abstraction layer
24 *
25 * Compile Options
58ce8499 26 * - CONFIG_USB_CHIPIDEA_DEBUG: enable debug facilities
e443b333
AS		 27 * - STALL_IN: non-empty bulk-in pipes cannot be halted
28 * if defined mass storage compliance succeeds but with warnings
29 * => case 4: Hi > Dn
30 * => case 5: Hi > Di
31 * => case 8: Hi <> Do
32 * if undefined usbtest 13 fails
33 * - TRACE: enable function tracing (depends on DEBUG)
34 *
35 * Main Features
36 * - Chapter 9 & Mass Storage Compliance with Gadget File Storage
37 * - Chapter 9 Compliance with Gadget Zero (STALL_IN undefined)
38 * - Normal & LPM support
39 *
40 * USBTEST Report
41 * - OK: 0-12, 13 (STALL_IN defined) & 14
42 * - Not Supported: 15 & 16 (ISO)
43 *
44 * TODO List
e443b333
AS		 45 * - Suspend & Remote Wakeup
46 */
47#include <linux/delay.h>
48#include <linux/device.h>
e443b333 49#include <linux/dma-mapping.h>
1e5e2d3d 50#include <linux/phy/phy.h>
e443b333
AS		 51#include <linux/platform_device.h>
52#include <linux/module.h>
fe6e125e 53#include <linux/idr.h>
e443b333
AS		 54#include <linux/interrupt.h>
55#include <linux/io.h>
e443b333
AS		 56#include <linux/kernel.h>
57#include <linux/slab.h>
58#include <linux/pm_runtime.h>
59#include <linux/usb/ch9.h>
60#include <linux/usb/gadget.h>
61#include <linux/usb/otg.h>
62#include <linux/usb/chipidea.h>
40dcd0e8 63#include <linux/usb/of.h>
4f6743d5 64#include <linux/of.h>
40dcd0e8 65#include <linux/phy.h>
1542d9c3 66#include <linux/regulator/consumer.h>
e443b333
AS		 67
68#include "ci.h"
69#include "udc.h"
70#include "bits.h"
eb70e5ab 71#include "host.h"
e443b333 72#include "debug.h"
c10b4f03 73#include "otg.h"
4dcf720c 74#include "otg_fsm.h"
e443b333 75
5f36e231 76/* Controller register map */
987e7bc3
MKB		 77static const u8 ci_regs_nolpm[] = {
78 [CAP_CAPLENGTH] = 0x00U,
79 [CAP_HCCPARAMS] = 0x08U,
80 [CAP_DCCPARAMS] = 0x24U,
81 [CAP_TESTMODE] = 0x38U,
82 [OP_USBCMD] = 0x00U,
83 [OP_USBSTS] = 0x04U,
84 [OP_USBINTR] = 0x08U,
85 [OP_DEVICEADDR] = 0x14U,
86 [OP_ENDPTLISTADDR] = 0x18U,
87 [OP_PORTSC] = 0x44U,
88 [OP_DEVLC] = 0x84U,
89 [OP_OTGSC] = 0x64U,
90 [OP_USBMODE] = 0x68U,
91 [OP_ENDPTSETUPSTAT] = 0x6CU,
92 [OP_ENDPTPRIME] = 0x70U,
93 [OP_ENDPTFLUSH] = 0x74U,
94 [OP_ENDPTSTAT] = 0x78U,
95 [OP_ENDPTCOMPLETE] = 0x7CU,
96 [OP_ENDPTCTRL] = 0x80U,
e443b333
AS		 97};
98
987e7bc3
MKB		 99static const u8 ci_regs_lpm[] = {
100 [CAP_CAPLENGTH] = 0x00U,
101 [CAP_HCCPARAMS] = 0x08U,
102 [CAP_DCCPARAMS] = 0x24U,
103 [CAP_TESTMODE] = 0xFCU,
104 [OP_USBCMD] = 0x00U,
105 [OP_USBSTS] = 0x04U,
106 [OP_USBINTR] = 0x08U,
107 [OP_DEVICEADDR] = 0x14U,
108 [OP_ENDPTLISTADDR] = 0x18U,
109 [OP_PORTSC] = 0x44U,
110 [OP_DEVLC] = 0x84U,
111 [OP_OTGSC] = 0xC4U,
112 [OP_USBMODE] = 0xC8U,
113 [OP_ENDPTSETUPSTAT] = 0xD8U,
114 [OP_ENDPTPRIME] = 0xDCU,
115 [OP_ENDPTFLUSH] = 0xE0U,
116 [OP_ENDPTSTAT] = 0xE4U,
117 [OP_ENDPTCOMPLETE] = 0xE8U,
118 [OP_ENDPTCTRL] = 0xECU,
e443b333
AS		 119};
120
8e22978c 121static int hw_alloc_regmap(struct ci_hdrc *ci, bool is_lpm)
e443b333
AS		 122{
123 int i;
124
e443b333 125 for (i = 0; i < OP_ENDPTCTRL; i++)
5f36e231
AS		 126 ci->hw_bank.regmap[i] =
127 (i <= CAP_LAST ? ci->hw_bank.cap : ci->hw_bank.op) +
e443b333
AS		 128 (is_lpm ? ci_regs_lpm[i] : ci_regs_nolpm[i]);
129
130 for (; i <= OP_LAST; i++)
5f36e231 131 ci->hw_bank.regmap[i] = ci->hw_bank.op +
e443b333
AS		 132 4 * (i - OP_ENDPTCTRL) +
133 (is_lpm
134 ? ci_regs_lpm[OP_ENDPTCTRL]
135 : ci_regs_nolpm[OP_ENDPTCTRL]);
136
137 return 0;
138}
139
36304b06
LJ		 140/**
141 * hw_read_intr_enable: returns interrupt enable register
142 *
19353881
PC		 143 * @ci: the controller
144 *
36304b06
LJ		 145 * This function returns register data
146 */
147u32 hw_read_intr_enable(struct ci_hdrc *ci)
148{
149 return hw_read(ci, OP_USBINTR, ~0);
150}
151
152/**
153 * hw_read_intr_status: returns interrupt status register
154 *
19353881
PC		 155 * @ci: the controller
156 *
36304b06
LJ		 157 * This function returns register data
158 */
159u32 hw_read_intr_status(struct ci_hdrc *ci)
160{
161 return hw_read(ci, OP_USBSTS, ~0);
162}
163
e443b333
AS		 164/**
165 * hw_port_test_set: writes port test mode (execute without interruption)
166 * @mode: new value
167 *
168 * This function returns an error code
169 */
8e22978c 170int hw_port_test_set(struct ci_hdrc *ci, u8 mode)
e443b333
AS		 171{
172 const u8 TEST_MODE_MAX = 7;
173
174 if (mode > TEST_MODE_MAX)
175 return -EINVAL;
176
727b4ddb 177 hw_write(ci, OP_PORTSC, PORTSC_PTC, mode << __ffs(PORTSC_PTC));
e443b333
AS		 178 return 0;
179}
180
181/**
182 * hw_port_test_get: reads port test mode value
183 *
19353881
PC		 184 * @ci: the controller
185 *
e443b333
AS		 186 * This function returns port test mode value
187 */
8e22978c 188u8 hw_port_test_get(struct ci_hdrc *ci)
e443b333 189{
727b4ddb 190 return hw_read(ci, OP_PORTSC, PORTSC_PTC) >> __ffs(PORTSC_PTC);
e443b333
AS		 191}
192
864cf949
PC		 193/* The PHY enters/leaves low power mode */
194static void ci_hdrc_enter_lpm(struct ci_hdrc *ci, bool enable)
195{
196 enum ci_hw_regs reg = ci->hw_bank.lpm ? OP_DEVLC : OP_PORTSC;
197 bool lpm = !!(hw_read(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm)));
198
199 if (enable && !lpm) {
200 hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm),
201 PORTSC_PHCD(ci->hw_bank.lpm));
202 } else if (!enable && lpm) {
203 hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm),
204 0);
205 /*
90893b90 206 * the PHY needs some time (less
864cf949
PC		 207 * than 1ms) to leave low power mode.
208 */
90893b90 209 usleep_range(1000, 1100);
864cf949
PC		 210 }
211}
212
8e22978c 213static int hw_device_init(struct ci_hdrc *ci, void __iomem *base)
e443b333
AS		 214{
215 u32 reg;
216
217 /* bank is a module variable */
5f36e231 218 ci->hw_bank.abs = base;
e443b333 219
5f36e231 220 ci->hw_bank.cap = ci->hw_bank.abs;
77c4400f 221 ci->hw_bank.cap += ci->platdata->capoffset;
938d323f 222 ci->hw_bank.op = ci->hw_bank.cap + (ioread32(ci->hw_bank.cap) & 0xff);
e443b333 223
5f36e231
AS		 224 hw_alloc_regmap(ci, false);
225 reg = hw_read(ci, CAP_HCCPARAMS, HCCPARAMS_LEN) >>
727b4ddb 226 __ffs(HCCPARAMS_LEN);
5f36e231 227 ci->hw_bank.lpm = reg;
aeb2c121
CR		 228 if (reg)
229 hw_alloc_regmap(ci, !!reg);
5f36e231
AS		 230 ci->hw_bank.size = ci->hw_bank.op - ci->hw_bank.abs;
231 ci->hw_bank.size += OP_LAST;
232 ci->hw_bank.size /= sizeof(u32);
e443b333 233
5f36e231 234 reg = hw_read(ci, CAP_DCCPARAMS, DCCPARAMS_DEN) >>
727b4ddb 235 __ffs(DCCPARAMS_DEN);
5f36e231 236 ci->hw_ep_max = reg * 2; /* cache hw ENDPT_MAX */
e443b333 237
09c94e62 238 if (ci->hw_ep_max > ENDPT_MAX)
e443b333
AS		 239 return -ENODEV;
240
864cf949
PC		 241 ci_hdrc_enter_lpm(ci, false);
242
c344b518
PC		 243 /* Disable all interrupts bits */
244 hw_write(ci, OP_USBINTR, 0xffffffff, 0);
245
246 /* Clear all interrupts status bits*/
247 hw_write(ci, OP_USBSTS, 0xffffffff, 0xffffffff);
248
5f36e231
AS		 249 dev_dbg(ci->dev, "ChipIdea HDRC found, lpm: %d; cap: %p op: %p\n",
250 ci->hw_bank.lpm, ci->hw_bank.cap, ci->hw_bank.op);
e443b333
AS		 251
252 /* setup lock mode ? */
253
254 /* ENDPTSETUPSTAT is '0' by default */
255
256 /* HCSPARAMS.bf.ppc SHOULD BE zero for device */
257
258 return 0;
259}
260
8e22978c 261static void hw_phymode_configure(struct ci_hdrc *ci)
40dcd0e8 262{
3b5d3e68 263 u32 portsc, lpm, sts = 0;
40dcd0e8
MG		 264
265 switch (ci->platdata->phy_mode) {
266 case USBPHY_INTERFACE_MODE_UTMI:
267 portsc = PORTSC_PTS(PTS_UTMI);
268 lpm = DEVLC_PTS(PTS_UTMI);
269 break;
270 case USBPHY_INTERFACE_MODE_UTMIW:
271 portsc = PORTSC_PTS(PTS_UTMI) | PORTSC_PTW;
272 lpm = DEVLC_PTS(PTS_UTMI) | DEVLC_PTW;
273 break;
274 case USBPHY_INTERFACE_MODE_ULPI:
275 portsc = PORTSC_PTS(PTS_ULPI);
276 lpm = DEVLC_PTS(PTS_ULPI);
277 break;
278 case USBPHY_INTERFACE_MODE_SERIAL:
279 portsc = PORTSC_PTS(PTS_SERIAL);
280 lpm = DEVLC_PTS(PTS_SERIAL);
281 sts = 1;
282 break;
283 case USBPHY_INTERFACE_MODE_HSIC:
284 portsc = PORTSC_PTS(PTS_HSIC);
285 lpm = DEVLC_PTS(PTS_HSIC);
286 break;
287 default:
288 return;
289 }
290
291 if (ci->hw_bank.lpm) {
292 hw_write(ci, OP_DEVLC, DEVLC_PTS(7) | DEVLC_PTW, lpm);
3b5d3e68
CR		 293 if (sts)
294 hw_write(ci, OP_DEVLC, DEVLC_STS, DEVLC_STS);
40dcd0e8
MG		 295 } else {
296 hw_write(ci, OP_PORTSC, PORTSC_PTS(7) | PORTSC_PTW, portsc);
3b5d3e68
CR		 297 if (sts)
298 hw_write(ci, OP_PORTSC, PORTSC_STS, PORTSC_STS);
40dcd0e8
MG		 299 }
300}
301
1e5e2d3d
AT		 302/**
303 * _ci_usb_phy_init: initialize phy taking in account both phy and usb_phy
304 * interfaces
305 * @ci: the controller
306 *
307 * This function returns an error code if the phy failed to init
308 */
309static int _ci_usb_phy_init(struct ci_hdrc *ci)
310{
311 int ret;
312
313 if (ci->phy) {
314 ret = phy_init(ci->phy);
315 if (ret)
316 return ret;
317
318 ret = phy_power_on(ci->phy);
319 if (ret) {
320 phy_exit(ci->phy);
321 return ret;
322 }
323 } else {
324 ret = usb_phy_init(ci->usb_phy);
325 }
326
327 return ret;
328}
329
330/**
331 * _ci_usb_phy_exit: deinitialize phy taking in account both phy and usb_phy
332 * interfaces
333 * @ci: the controller
334 */
335static void ci_usb_phy_exit(struct ci_hdrc *ci)
336{
337 if (ci->phy) {
338 phy_power_off(ci->phy);
339 phy_exit(ci->phy);
340 } else {
341 usb_phy_shutdown(ci->usb_phy);
342 }
343}
344
d03cccff
PC		 345/**
346 * ci_usb_phy_init: initialize phy according to different phy type
347 * @ci: the controller
19353881 348 *
d03cccff
PC		 349 * This function returns an error code if usb_phy_init has failed
350 */
351static int ci_usb_phy_init(struct ci_hdrc *ci)
352{
353 int ret;
354
355 switch (ci->platdata->phy_mode) {
356 case USBPHY_INTERFACE_MODE_UTMI:
357 case USBPHY_INTERFACE_MODE_UTMIW:
358 case USBPHY_INTERFACE_MODE_HSIC:
1e5e2d3d 359 ret = _ci_usb_phy_init(ci);
d03cccff
PC		 360 if (ret)
361 return ret;
362 hw_phymode_configure(ci);
363 break;
364 case USBPHY_INTERFACE_MODE_ULPI:
365 case USBPHY_INTERFACE_MODE_SERIAL:
366 hw_phymode_configure(ci);
1e5e2d3d 367 ret = _ci_usb_phy_init(ci);
d03cccff
PC		 368 if (ret)
369 return ret;
370 break;
371 default:
1e5e2d3d 372 ret = _ci_usb_phy_init(ci);
d03cccff
PC		 373 }
374
375 return ret;
376}
377
e443b333
AS		 378/**
379 * hw_device_reset: resets chip (execute without interruption)
380 * @ci: the controller
381 *
382 * This function returns an error code
383 */
8e22978c 384int hw_device_reset(struct ci_hdrc *ci, u32 mode)
e443b333
AS		 385{
386 /* should flush & stop before reset */
387 hw_write(ci, OP_ENDPTFLUSH, ~0, ~0);
388 hw_write(ci, OP_USBCMD, USBCMD_RS, 0);
389
390 hw_write(ci, OP_USBCMD, USBCMD_RST, USBCMD_RST);
391 while (hw_read(ci, OP_USBCMD, USBCMD_RST))
392 udelay(10); /* not RTOS friendly */
393
77c4400f
RZ		 394 if (ci->platdata->notify_event)
395 ci->platdata->notify_event(ci,
8e22978c 396 CI_HDRC_CONTROLLER_RESET_EVENT);
e443b333 397
8e22978c 398 if (ci->platdata->flags & CI_HDRC_DISABLE_STREAMING)
758fc986 399 hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS, USBMODE_CI_SDIS);
e443b333 400
4f6743d5
MG		 401 if (ci->platdata->flags & CI_HDRC_FORCE_FULLSPEED) {
402 if (ci->hw_bank.lpm)
403 hw_write(ci, OP_DEVLC, DEVLC_PFSC, DEVLC_PFSC);
404 else
405 hw_write(ci, OP_PORTSC, PORTSC_PFSC, PORTSC_PFSC);
406 }
407
e443b333
AS		 408 /* USBMODE should be configured step by step */
409 hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE);
eb70e5ab 410 hw_write(ci, OP_USBMODE, USBMODE_CM, mode);
e443b333
AS		 411 /* HW >= 2.3 */
412 hw_write(ci, OP_USBMODE, USBMODE_SLOM, USBMODE_SLOM);
413
eb70e5ab
AS		 414 if (hw_read(ci, OP_USBMODE, USBMODE_CM) != mode) {
415 pr_err("cannot enter in %s mode", ci_role(ci)->name);
e443b333
AS		 416 pr_err("lpm = %i", ci->hw_bank.lpm);
417 return -ENODEV;
418 }
419
420 return 0;
421}
422
22fa8445
PC		 423/**
424 * hw_wait_reg: wait the register value
425 *
426 * Sometimes, it needs to wait register value before going on.
427 * Eg, when switch to device mode, the vbus value should be lower
428 * than OTGSC_BSV before connects to host.
429 *
430 * @ci: the controller
431 * @reg: register index
432 * @mask: mast bit
433 * @value: the bit value to wait
434 * @timeout_ms: timeout in millisecond
435 *
436 * This function returns an error code if timeout
437 */
438int hw_wait_reg(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask,
439 u32 value, unsigned int timeout_ms)
440{
441 unsigned long elapse = jiffies + msecs_to_jiffies(timeout_ms);
442
443 while (hw_read(ci, reg, mask) != value) {
444 if (time_after(jiffies, elapse)) {
445 dev_err(ci->dev, "timeout waiting for %08x in %d\n",
446 mask, reg);
447 return -ETIMEDOUT;
448 }
449 msleep(20);
450 }
451
452 return 0;
453}
454
5f36e231
AS		 455static irqreturn_t ci_irq(int irq, void *data)
456{
8e22978c 457 struct ci_hdrc *ci = data;
5f36e231 458 irqreturn_t ret = IRQ_NONE;
b183c19f 459 u32 otgsc = 0;
5f36e231 460
4dcf720c 461 if (ci->is_otg) {
0c33bf78 462 otgsc = hw_read_otgsc(ci, ~0);
4dcf720c
LJ		 463 if (ci_otg_is_fsm_mode(ci)) {
464 ret = ci_otg_fsm_irq(ci);
465 if (ret == IRQ_HANDLED)
466 return ret;
467 }
468 }
5f36e231 469
a107f8c5
PC		 470 /*
471 * Handle id change interrupt, it indicates device/host function
472 * switch.
473 */
474 if (ci->is_otg && (otgsc & OTGSC_IDIE) && (otgsc & OTGSC_IDIS)) {
475 ci->id_event = true;
0c33bf78
LJ		 476 /* Clear ID change irq status */
477 hw_write_otgsc(ci, OTGSC_IDIS, OTGSC_IDIS);
be6b0c1b 478 ci_otg_queue_work(ci);
a107f8c5
PC		 479 return IRQ_HANDLED;
480 }
b183c19f 481
a107f8c5
PC		 482 /*
483 * Handle vbus change interrupt, it indicates device connection
484 * and disconnection events.
485 */
486 if (ci->is_otg && (otgsc & OTGSC_BSVIE) && (otgsc & OTGSC_BSVIS)) {
487 ci->b_sess_valid_event = true;
0c33bf78
LJ		 488 /* Clear BSV irq */
489 hw_write_otgsc(ci, OTGSC_BSVIS, OTGSC_BSVIS);
be6b0c1b 490 ci_otg_queue_work(ci);
a107f8c5 491 return IRQ_HANDLED;
5f36e231
AS		 492 }
493
a107f8c5
PC		 494 /* Handle device/host interrupt */
495 if (ci->role != CI_ROLE_END)
496 ret = ci_role(ci)->irq(ci);
497
b183c19f 498 return ret;
5f36e231
AS		 499}
500
1542d9c3
PC		 501static int ci_get_platdata(struct device *dev,
502 struct ci_hdrc_platform_data *platdata)
503{
c22600c3
PC		 504 if (!platdata->phy_mode)
505 platdata->phy_mode = of_usb_get_phy_mode(dev->of_node);
506
507 if (!platdata->dr_mode)
508 platdata->dr_mode = of_usb_get_dr_mode(dev->of_node);
509
510 if (platdata->dr_mode == USB_DR_MODE_UNKNOWN)
511 platdata->dr_mode = USB_DR_MODE_OTG;
512
c2ec3a73
PC		 513 if (platdata->dr_mode != USB_DR_MODE_PERIPHERAL) {
514 /* Get the vbus regulator */
515 platdata->reg_vbus = devm_regulator_get(dev, "vbus");
516 if (PTR_ERR(platdata->reg_vbus) == -EPROBE_DEFER) {
517 return -EPROBE_DEFER;
518 } else if (PTR_ERR(platdata->reg_vbus) == -ENODEV) {
519 /* no vbus regualator is needed */
520 platdata->reg_vbus = NULL;
521 } else if (IS_ERR(platdata->reg_vbus)) {
522 dev_err(dev, "Getting regulator error: %ld\n",
523 PTR_ERR(platdata->reg_vbus));
524 return PTR_ERR(platdata->reg_vbus);
525 }
f6a9ff07
PC		 526 /* Get TPL support */
527 if (!platdata->tpl_support)
528 platdata->tpl_support =
529 of_usb_host_tpl_support(dev->of_node);
c2ec3a73
PC		 530 }
531
4f6743d5
MG		 532 if (of_usb_get_maximum_speed(dev->of_node) == USB_SPEED_FULL)
533 platdata->flags |= CI_HDRC_FORCE_FULLSPEED;
534
1542d9c3
PC		 535 return 0;
536}
537
fe6e125e
RZ		 538static DEFINE_IDA(ci_ida);
539
8e22978c 540struct platform_device *ci_hdrc_add_device(struct device *dev,
cbc6dc2a 541 struct resource *res, int nres,
8e22978c 542 struct ci_hdrc_platform_data *platdata)
cbc6dc2a
RZ		 543{
544 struct platform_device *pdev;
fe6e125e 545 int id, ret;
cbc6dc2a 546
1542d9c3
PC		 547 ret = ci_get_platdata(dev, platdata);
548 if (ret)
549 return ERR_PTR(ret);
550
fe6e125e
RZ		 551 id = ida_simple_get(&ci_ida, 0, 0, GFP_KERNEL);
552 if (id < 0)
553 return ERR_PTR(id);
554
555 pdev = platform_device_alloc("ci_hdrc", id);
556 if (!pdev) {
557 ret = -ENOMEM;
558 goto put_id;
559 }
cbc6dc2a
RZ		 560
561 pdev->dev.parent = dev;
562 pdev->dev.dma_mask = dev->dma_mask;
563 pdev->dev.dma_parms = dev->dma_parms;
564 dma_set_coherent_mask(&pdev->dev, dev->coherent_dma_mask);
565
566 ret = platform_device_add_resources(pdev, res, nres);
567 if (ret)
568 goto err;
569
570 ret = platform_device_add_data(pdev, platdata, sizeof(*platdata));
571 if (ret)
572 goto err;
573
574 ret = platform_device_add(pdev);
575 if (ret)
576 goto err;
577
578 return pdev;
579
580err:
581 platform_device_put(pdev);
fe6e125e
RZ		 582put_id:
583 ida_simple_remove(&ci_ida, id);
cbc6dc2a
RZ		 584 return ERR_PTR(ret);
585}
8e22978c 586EXPORT_SYMBOL_GPL(ci_hdrc_add_device);
cbc6dc2a 587
8e22978c 588void ci_hdrc_remove_device(struct platform_device *pdev)
cbc6dc2a 589{
98c35534 590 int id = pdev->id;
cbc6dc2a 591 platform_device_unregister(pdev);
98c35534 592 ida_simple_remove(&ci_ida, id);
cbc6dc2a 593}
8e22978c 594EXPORT_SYMBOL_GPL(ci_hdrc_remove_device);
cbc6dc2a 595
3f124d23
PC		 596static inline void ci_role_destroy(struct ci_hdrc *ci)
597{
598 ci_hdrc_gadget_destroy(ci);
599 ci_hdrc_host_destroy(ci);
cbec6bd5
PC		 600 if (ci->is_otg)
601 ci_hdrc_otg_destroy(ci);
3f124d23
PC		 602}
603
577b232f
PC		 604static void ci_get_otg_capable(struct ci_hdrc *ci)
605{
606 if (ci->platdata->flags & CI_HDRC_DUAL_ROLE_NOT_OTG)
607 ci->is_otg = false;
608 else
609 ci->is_otg = (hw_read(ci, CAP_DCCPARAMS,
610 DCCPARAMS_DC | DCCPARAMS_HC)
611 == (DCCPARAMS_DC | DCCPARAMS_HC));
90893b90 612 if (ci->is_otg)
577b232f
PC		 613 dev_dbg(ci->dev, "It is OTG capable controller\n");
614}
615
41ac7b3a 616static int ci_hdrc_probe(struct platform_device *pdev)
e443b333
AS		 617{
618 struct device *dev = &pdev->dev;
8e22978c 619 struct ci_hdrc *ci;
e443b333
AS		 620 struct resource *res;
621 void __iomem *base;
622 int ret;
691962d1 623 enum usb_dr_mode dr_mode;
e443b333 624
fad56745 625 if (!dev_get_platdata(dev)) {
e443b333
AS		 626 dev_err(dev, "platform data missing\n");
627 return -ENODEV;
628 }
629
630 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
19290816
FB		 631 base = devm_ioremap_resource(dev, res);
632 if (IS_ERR(base))
633 return PTR_ERR(base);
e443b333 634
5f36e231 635 ci = devm_kzalloc(dev, sizeof(*ci), GFP_KERNEL);
d0f99249 636 if (!ci)
5f36e231 637 return -ENOMEM;
5f36e231
AS		 638
639 ci->dev = dev;
fad56745 640 ci->platdata = dev_get_platdata(dev);
ed8f8318
PC		 641 ci->imx28_write_fix = !!(ci->platdata->flags &
642 CI_HDRC_IMX28_WRITE_FIX);
5f36e231
AS		 643
644 ret = hw_device_init(ci, base);
645 if (ret < 0) {
646 dev_err(dev, "can't initialize hardware\n");
647 return -ENODEV;
648 }
e443b333 649
1e5e2d3d
AT		 650 if (ci->platdata->phy) {
651 ci->phy = ci->platdata->phy;
652 } else if (ci->platdata->usb_phy) {
ef44cb42 653 ci->usb_phy = ci->platdata->usb_phy;
1e5e2d3d
AT		 654 } else {
655 ci->phy = devm_phy_get(dev, "usb-phy");
ef44cb42 656 ci->usb_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
c859aa65 657
1e5e2d3d
AT		 658 /* if both generic PHY and USB PHY layers aren't enabled */
659 if (PTR_ERR(ci->phy) == -ENOSYS &&
660 PTR_ERR(ci->usb_phy) == -ENXIO)
661 return -ENXIO;
662
663 if (IS_ERR(ci->phy) && IS_ERR(ci->usb_phy))
664 return -EPROBE_DEFER;
c859aa65 665
1e5e2d3d
AT		 666 if (IS_ERR(ci->phy))
667 ci->phy = NULL;
668 else if (IS_ERR(ci->usb_phy))
669 ci->usb_phy = NULL;
c859aa65
PC		 670 }
671
d03cccff 672 ret = ci_usb_phy_init(ci);
74475ede
PC		 673 if (ret) {
674 dev_err(dev, "unable to init phy: %d\n", ret);
675 return ret;
90893b90
PC		 676 } else {
677 /*
678 * The delay to sync PHY's status, the maximum delay is
679 * 2ms since the otgsc uses 1ms timer to debounce the
680 * PHY's input
681 */
682 usleep_range(2000, 2500);
74475ede
PC		 683 }
684
eb70e5ab
AS		 685 ci->hw_bank.phys = res->start;
686
5f36e231
AS		 687 ci->irq = platform_get_irq(pdev, 0);
688 if (ci->irq < 0) {
e443b333 689 dev_err(dev, "missing IRQ\n");
42d18212 690 ret = ci->irq;
c859aa65 691 goto deinit_phy;
5f36e231
AS		 692 }
693
577b232f
PC		 694 ci_get_otg_capable(ci);
695
691962d1 696 dr_mode = ci->platdata->dr_mode;
5f36e231 697 /* initialize role(s) before the interrupt is requested */
691962d1
SH		 698 if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_HOST) {
699 ret = ci_hdrc_host_init(ci);
700 if (ret)
701 dev_info(dev, "doesn't support host\n");
702 }
eb70e5ab 703
691962d1
SH		 704 if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_PERIPHERAL) {
705 ret = ci_hdrc_gadget_init(ci);
706 if (ret)
707 dev_info(dev, "doesn't support gadget\n");
708 }
5f36e231
AS		 709
710 if (!ci->roles[CI_ROLE_HOST] && !ci->roles[CI_ROLE_GADGET]) {
711 dev_err(dev, "no supported roles\n");
74475ede 712 ret = -ENODEV;
c859aa65 713 goto deinit_phy;
cbec6bd5
PC		 714 }
715
27c62c2d 716 if (ci->is_otg && ci->roles[CI_ROLE_GADGET]) {
90893b90
PC		 717 /* Disable and clear all OTG irq */
718 hw_write_otgsc(ci, OTGSC_INT_EN_BITS | OTGSC_INT_STATUS_BITS,
719 OTGSC_INT_STATUS_BITS);
cbec6bd5
PC		 720 ret = ci_hdrc_otg_init(ci);
721 if (ret) {
722 dev_err(dev, "init otg fails, ret = %d\n", ret);
723 goto stop;
724 }
5f36e231
AS		 725 }
726
727 if (ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET]) {
577b232f 728 if (ci->is_otg) {
577b232f 729 ci->role = ci_otg_role(ci);
0c33bf78
LJ		 730 /* Enable ID change irq */
731 hw_write_otgsc(ci, OTGSC_IDIE, OTGSC_IDIE);
577b232f
PC		 732 } else {
733 /*
734 * If the controller is not OTG capable, but support
735 * role switch, the defalt role is gadget, and the
736 * user can switch it through debugfs.
737 */
738 ci->role = CI_ROLE_GADGET;
739 }
5f36e231
AS		 740 } else {
741 ci->role = ci->roles[CI_ROLE_HOST]
742 ? CI_ROLE_HOST
743 : CI_ROLE_GADGET;
744 }
745
5a1e1456
PC		 746 /* only update vbus status for peripheral */
747 if (ci->role == CI_ROLE_GADGET)
748 ci_handle_vbus_change(ci);
749
4dcf720c
LJ		 750 if (!ci_otg_is_fsm_mode(ci)) {
751 ret = ci_role_start(ci, ci->role);
752 if (ret) {
753 dev_err(dev, "can't start %s role\n",
754 ci_role(ci)->name);
755 goto stop;
756 }
e443b333
AS		 757 }
758
5f36e231 759 platform_set_drvdata(pdev, ci);
4c503dd5
PC		 760 ret = devm_request_irq(dev, ci->irq, ci_irq, IRQF_SHARED,
761 ci->platdata->name, ci);
5f36e231
AS		 762 if (ret)
763 goto stop;
e443b333 764
4dcf720c
LJ		 765 if (ci_otg_is_fsm_mode(ci))
766 ci_hdrc_otg_fsm_start(ci);
767
adf0f735
AS		 768 ret = dbg_create_files(ci);
769 if (!ret)
770 return 0;
5f36e231 771
5f36e231 772stop:
3f124d23 773 ci_role_destroy(ci);
c859aa65 774deinit_phy:
1e5e2d3d 775 ci_usb_phy_exit(ci);
e443b333
AS		 776
777 return ret;
778}
779
fb4e98ab 780static int ci_hdrc_remove(struct platform_device *pdev)
e443b333 781{
8e22978c 782 struct ci_hdrc *ci = platform_get_drvdata(pdev);
e443b333 783
adf0f735 784 dbg_remove_files(ci);
3f124d23 785 ci_role_destroy(ci);
864cf949 786 ci_hdrc_enter_lpm(ci, true);
1e5e2d3d 787 ci_usb_phy_exit(ci);
e443b333
AS		 788
789 return 0;
790}
791
5f36e231
AS		 792static struct platform_driver ci_hdrc_driver = {
793 .probe = ci_hdrc_probe,
7690417d 794 .remove = ci_hdrc_remove,
e443b333 795 .driver = {
5f36e231 796 .name = "ci_hdrc",
7cf2f861 797 .owner = THIS_MODULE,
e443b333
AS		 798 },
799};
800
5f36e231 801module_platform_driver(ci_hdrc_driver);
e443b333 802
5f36e231 803MODULE_ALIAS("platform:ci_hdrc");
e443b333
AS		 804MODULE_LICENSE("GPL v2");
805MODULE_AUTHOR("David Lopo <dlopo@chipidea.mips.com>");
5f36e231 806MODULE_DESCRIPTION("ChipIdea HDRC Driver");
Linux 6.x block layer and io_uring tree(s)