Commit | Line | Data |
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e443b333 AS |
1 | /* |
2 | * core.c - ChipIdea USB IP core family device controller | |
3 | * | |
4 | * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved. | |
5 | * | |
6 | * Author: David Lopo | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | /* | |
14 | * Description: ChipIdea USB IP core family device controller | |
15 | * | |
16 | * This driver is composed of several blocks: | |
17 | * - HW: hardware interface | |
18 | * - DBG: debug facilities (optional) | |
19 | * - UTIL: utilities | |
20 | * - ISR: interrupts handling | |
21 | * - ENDPT: endpoint operations (Gadget API) | |
22 | * - GADGET: gadget operations (Gadget API) | |
23 | * - BUS: bus glue code, bus abstraction layer | |
24 | * | |
25 | * Compile Options | |
e443b333 AS |
26 | * - STALL_IN: non-empty bulk-in pipes cannot be halted |
27 | * if defined mass storage compliance succeeds but with warnings | |
28 | * => case 4: Hi > Dn | |
29 | * => case 5: Hi > Di | |
30 | * => case 8: Hi <> Do | |
31 | * if undefined usbtest 13 fails | |
32 | * - TRACE: enable function tracing (depends on DEBUG) | |
33 | * | |
34 | * Main Features | |
35 | * - Chapter 9 & Mass Storage Compliance with Gadget File Storage | |
36 | * - Chapter 9 Compliance with Gadget Zero (STALL_IN undefined) | |
37 | * - Normal & LPM support | |
38 | * | |
39 | * USBTEST Report | |
40 | * - OK: 0-12, 13 (STALL_IN defined) & 14 | |
41 | * - Not Supported: 15 & 16 (ISO) | |
42 | * | |
43 | * TODO List | |
e443b333 AS |
44 | * - Suspend & Remote Wakeup |
45 | */ | |
46 | #include <linux/delay.h> | |
47 | #include <linux/device.h> | |
e443b333 | 48 | #include <linux/dma-mapping.h> |
3ecb3e09 | 49 | #include <linux/extcon.h> |
1e5e2d3d | 50 | #include <linux/phy/phy.h> |
e443b333 AS |
51 | #include <linux/platform_device.h> |
52 | #include <linux/module.h> | |
fe6e125e | 53 | #include <linux/idr.h> |
e443b333 AS |
54 | #include <linux/interrupt.h> |
55 | #include <linux/io.h> | |
e443b333 AS |
56 | #include <linux/kernel.h> |
57 | #include <linux/slab.h> | |
58 | #include <linux/pm_runtime.h> | |
59 | #include <linux/usb/ch9.h> | |
60 | #include <linux/usb/gadget.h> | |
61 | #include <linux/usb/otg.h> | |
62 | #include <linux/usb/chipidea.h> | |
40dcd0e8 | 63 | #include <linux/usb/of.h> |
4f6743d5 | 64 | #include <linux/of.h> |
40dcd0e8 | 65 | #include <linux/phy.h> |
1542d9c3 | 66 | #include <linux/regulator/consumer.h> |
8022d3d5 | 67 | #include <linux/usb/ehci_def.h> |
e443b333 AS |
68 | |
69 | #include "ci.h" | |
70 | #include "udc.h" | |
71 | #include "bits.h" | |
eb70e5ab | 72 | #include "host.h" |
c10b4f03 | 73 | #include "otg.h" |
4dcf720c | 74 | #include "otg_fsm.h" |
e443b333 | 75 | |
5f36e231 | 76 | /* Controller register map */ |
987e7bc3 MKB |
77 | static const u8 ci_regs_nolpm[] = { |
78 | [CAP_CAPLENGTH] = 0x00U, | |
79 | [CAP_HCCPARAMS] = 0x08U, | |
80 | [CAP_DCCPARAMS] = 0x24U, | |
81 | [CAP_TESTMODE] = 0x38U, | |
82 | [OP_USBCMD] = 0x00U, | |
83 | [OP_USBSTS] = 0x04U, | |
84 | [OP_USBINTR] = 0x08U, | |
85 | [OP_DEVICEADDR] = 0x14U, | |
86 | [OP_ENDPTLISTADDR] = 0x18U, | |
28362673 | 87 | [OP_TTCTRL] = 0x1CU, |
96625ead | 88 | [OP_BURSTSIZE] = 0x20U, |
7bb7e9b1 | 89 | [OP_ULPI_VIEWPORT] = 0x30U, |
987e7bc3 MKB |
90 | [OP_PORTSC] = 0x44U, |
91 | [OP_DEVLC] = 0x84U, | |
92 | [OP_OTGSC] = 0x64U, | |
93 | [OP_USBMODE] = 0x68U, | |
94 | [OP_ENDPTSETUPSTAT] = 0x6CU, | |
95 | [OP_ENDPTPRIME] = 0x70U, | |
96 | [OP_ENDPTFLUSH] = 0x74U, | |
97 | [OP_ENDPTSTAT] = 0x78U, | |
98 | [OP_ENDPTCOMPLETE] = 0x7CU, | |
99 | [OP_ENDPTCTRL] = 0x80U, | |
e443b333 AS |
100 | }; |
101 | ||
987e7bc3 MKB |
102 | static const u8 ci_regs_lpm[] = { |
103 | [CAP_CAPLENGTH] = 0x00U, | |
104 | [CAP_HCCPARAMS] = 0x08U, | |
105 | [CAP_DCCPARAMS] = 0x24U, | |
106 | [CAP_TESTMODE] = 0xFCU, | |
107 | [OP_USBCMD] = 0x00U, | |
108 | [OP_USBSTS] = 0x04U, | |
109 | [OP_USBINTR] = 0x08U, | |
110 | [OP_DEVICEADDR] = 0x14U, | |
111 | [OP_ENDPTLISTADDR] = 0x18U, | |
28362673 | 112 | [OP_TTCTRL] = 0x1CU, |
96625ead | 113 | [OP_BURSTSIZE] = 0x20U, |
7bb7e9b1 | 114 | [OP_ULPI_VIEWPORT] = 0x30U, |
987e7bc3 MKB |
115 | [OP_PORTSC] = 0x44U, |
116 | [OP_DEVLC] = 0x84U, | |
117 | [OP_OTGSC] = 0xC4U, | |
118 | [OP_USBMODE] = 0xC8U, | |
119 | [OP_ENDPTSETUPSTAT] = 0xD8U, | |
120 | [OP_ENDPTPRIME] = 0xDCU, | |
121 | [OP_ENDPTFLUSH] = 0xE0U, | |
122 | [OP_ENDPTSTAT] = 0xE4U, | |
123 | [OP_ENDPTCOMPLETE] = 0xE8U, | |
124 | [OP_ENDPTCTRL] = 0xECU, | |
e443b333 AS |
125 | }; |
126 | ||
158ec071 | 127 | static void hw_alloc_regmap(struct ci_hdrc *ci, bool is_lpm) |
e443b333 AS |
128 | { |
129 | int i; | |
130 | ||
e443b333 | 131 | for (i = 0; i < OP_ENDPTCTRL; i++) |
5f36e231 AS |
132 | ci->hw_bank.regmap[i] = |
133 | (i <= CAP_LAST ? ci->hw_bank.cap : ci->hw_bank.op) + | |
e443b333 AS |
134 | (is_lpm ? ci_regs_lpm[i] : ci_regs_nolpm[i]); |
135 | ||
136 | for (; i <= OP_LAST; i++) | |
5f36e231 | 137 | ci->hw_bank.regmap[i] = ci->hw_bank.op + |
e443b333 AS |
138 | 4 * (i - OP_ENDPTCTRL) + |
139 | (is_lpm | |
140 | ? ci_regs_lpm[OP_ENDPTCTRL] | |
141 | : ci_regs_nolpm[OP_ENDPTCTRL]); | |
142 | ||
e443b333 AS |
143 | } |
144 | ||
cb271f3c PC |
145 | static enum ci_revision ci_get_revision(struct ci_hdrc *ci) |
146 | { | |
147 | int ver = hw_read_id_reg(ci, ID_ID, VERSION) >> __ffs(VERSION); | |
148 | enum ci_revision rev = CI_REVISION_UNKNOWN; | |
149 | ||
150 | if (ver == 0x2) { | |
151 | rev = hw_read_id_reg(ci, ID_ID, REVISION) | |
152 | >> __ffs(REVISION); | |
153 | rev += CI_REVISION_20; | |
154 | } else if (ver == 0x0) { | |
155 | rev = CI_REVISION_1X; | |
156 | } | |
157 | ||
158 | return rev; | |
159 | } | |
160 | ||
36304b06 LJ |
161 | /** |
162 | * hw_read_intr_enable: returns interrupt enable register | |
163 | * | |
19353881 PC |
164 | * @ci: the controller |
165 | * | |
36304b06 LJ |
166 | * This function returns register data |
167 | */ | |
168 | u32 hw_read_intr_enable(struct ci_hdrc *ci) | |
169 | { | |
170 | return hw_read(ci, OP_USBINTR, ~0); | |
171 | } | |
172 | ||
173 | /** | |
174 | * hw_read_intr_status: returns interrupt status register | |
175 | * | |
19353881 PC |
176 | * @ci: the controller |
177 | * | |
36304b06 LJ |
178 | * This function returns register data |
179 | */ | |
180 | u32 hw_read_intr_status(struct ci_hdrc *ci) | |
181 | { | |
182 | return hw_read(ci, OP_USBSTS, ~0); | |
183 | } | |
184 | ||
e443b333 AS |
185 | /** |
186 | * hw_port_test_set: writes port test mode (execute without interruption) | |
187 | * @mode: new value | |
188 | * | |
189 | * This function returns an error code | |
190 | */ | |
8e22978c | 191 | int hw_port_test_set(struct ci_hdrc *ci, u8 mode) |
e443b333 AS |
192 | { |
193 | const u8 TEST_MODE_MAX = 7; | |
194 | ||
195 | if (mode > TEST_MODE_MAX) | |
196 | return -EINVAL; | |
197 | ||
727b4ddb | 198 | hw_write(ci, OP_PORTSC, PORTSC_PTC, mode << __ffs(PORTSC_PTC)); |
e443b333 AS |
199 | return 0; |
200 | } | |
201 | ||
202 | /** | |
203 | * hw_port_test_get: reads port test mode value | |
204 | * | |
19353881 PC |
205 | * @ci: the controller |
206 | * | |
e443b333 AS |
207 | * This function returns port test mode value |
208 | */ | |
8e22978c | 209 | u8 hw_port_test_get(struct ci_hdrc *ci) |
e443b333 | 210 | { |
727b4ddb | 211 | return hw_read(ci, OP_PORTSC, PORTSC_PTC) >> __ffs(PORTSC_PTC); |
e443b333 AS |
212 | } |
213 | ||
b82613cf PC |
214 | static void hw_wait_phy_stable(void) |
215 | { | |
216 | /* | |
217 | * The phy needs some delay to output the stable status from low | |
218 | * power mode. And for OTGSC, the status inputs are debounced | |
219 | * using a 1 ms time constant, so, delay 2ms for controller to get | |
220 | * the stable status, like vbus and id when the phy leaves low power. | |
221 | */ | |
222 | usleep_range(2000, 2500); | |
223 | } | |
224 | ||
864cf949 PC |
225 | /* The PHY enters/leaves low power mode */ |
226 | static void ci_hdrc_enter_lpm(struct ci_hdrc *ci, bool enable) | |
227 | { | |
228 | enum ci_hw_regs reg = ci->hw_bank.lpm ? OP_DEVLC : OP_PORTSC; | |
229 | bool lpm = !!(hw_read(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm))); | |
230 | ||
6d037db6 | 231 | if (enable && !lpm) |
864cf949 PC |
232 | hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm), |
233 | PORTSC_PHCD(ci->hw_bank.lpm)); | |
6d037db6 | 234 | else if (!enable && lpm) |
864cf949 PC |
235 | hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm), |
236 | 0); | |
864cf949 PC |
237 | } |
238 | ||
8e22978c | 239 | static int hw_device_init(struct ci_hdrc *ci, void __iomem *base) |
e443b333 AS |
240 | { |
241 | u32 reg; | |
242 | ||
243 | /* bank is a module variable */ | |
5f36e231 | 244 | ci->hw_bank.abs = base; |
e443b333 | 245 | |
5f36e231 | 246 | ci->hw_bank.cap = ci->hw_bank.abs; |
77c4400f | 247 | ci->hw_bank.cap += ci->platdata->capoffset; |
938d323f | 248 | ci->hw_bank.op = ci->hw_bank.cap + (ioread32(ci->hw_bank.cap) & 0xff); |
e443b333 | 249 | |
5f36e231 AS |
250 | hw_alloc_regmap(ci, false); |
251 | reg = hw_read(ci, CAP_HCCPARAMS, HCCPARAMS_LEN) >> | |
727b4ddb | 252 | __ffs(HCCPARAMS_LEN); |
5f36e231 | 253 | ci->hw_bank.lpm = reg; |
aeb2c121 CR |
254 | if (reg) |
255 | hw_alloc_regmap(ci, !!reg); | |
5f36e231 AS |
256 | ci->hw_bank.size = ci->hw_bank.op - ci->hw_bank.abs; |
257 | ci->hw_bank.size += OP_LAST; | |
258 | ci->hw_bank.size /= sizeof(u32); | |
e443b333 | 259 | |
5f36e231 | 260 | reg = hw_read(ci, CAP_DCCPARAMS, DCCPARAMS_DEN) >> |
727b4ddb | 261 | __ffs(DCCPARAMS_DEN); |
5f36e231 | 262 | ci->hw_ep_max = reg * 2; /* cache hw ENDPT_MAX */ |
e443b333 | 263 | |
09c94e62 | 264 | if (ci->hw_ep_max > ENDPT_MAX) |
e443b333 AS |
265 | return -ENODEV; |
266 | ||
864cf949 PC |
267 | ci_hdrc_enter_lpm(ci, false); |
268 | ||
c344b518 PC |
269 | /* Disable all interrupts bits */ |
270 | hw_write(ci, OP_USBINTR, 0xffffffff, 0); | |
271 | ||
272 | /* Clear all interrupts status bits*/ | |
273 | hw_write(ci, OP_USBSTS, 0xffffffff, 0xffffffff); | |
274 | ||
cb271f3c PC |
275 | ci->rev = ci_get_revision(ci); |
276 | ||
277 | dev_dbg(ci->dev, | |
278 | "ChipIdea HDRC found, revision: %d, lpm: %d; cap: %p op: %p\n", | |
279 | ci->rev, ci->hw_bank.lpm, ci->hw_bank.cap, ci->hw_bank.op); | |
e443b333 AS |
280 | |
281 | /* setup lock mode ? */ | |
282 | ||
283 | /* ENDPTSETUPSTAT is '0' by default */ | |
284 | ||
285 | /* HCSPARAMS.bf.ppc SHOULD BE zero for device */ | |
286 | ||
287 | return 0; | |
288 | } | |
289 | ||
7bb7e9b1 | 290 | void hw_phymode_configure(struct ci_hdrc *ci) |
40dcd0e8 | 291 | { |
3b5d3e68 | 292 | u32 portsc, lpm, sts = 0; |
40dcd0e8 MG |
293 | |
294 | switch (ci->platdata->phy_mode) { | |
295 | case USBPHY_INTERFACE_MODE_UTMI: | |
296 | portsc = PORTSC_PTS(PTS_UTMI); | |
297 | lpm = DEVLC_PTS(PTS_UTMI); | |
298 | break; | |
299 | case USBPHY_INTERFACE_MODE_UTMIW: | |
300 | portsc = PORTSC_PTS(PTS_UTMI) | PORTSC_PTW; | |
301 | lpm = DEVLC_PTS(PTS_UTMI) | DEVLC_PTW; | |
302 | break; | |
303 | case USBPHY_INTERFACE_MODE_ULPI: | |
304 | portsc = PORTSC_PTS(PTS_ULPI); | |
305 | lpm = DEVLC_PTS(PTS_ULPI); | |
306 | break; | |
307 | case USBPHY_INTERFACE_MODE_SERIAL: | |
308 | portsc = PORTSC_PTS(PTS_SERIAL); | |
309 | lpm = DEVLC_PTS(PTS_SERIAL); | |
310 | sts = 1; | |
311 | break; | |
312 | case USBPHY_INTERFACE_MODE_HSIC: | |
313 | portsc = PORTSC_PTS(PTS_HSIC); | |
314 | lpm = DEVLC_PTS(PTS_HSIC); | |
315 | break; | |
316 | default: | |
317 | return; | |
318 | } | |
319 | ||
320 | if (ci->hw_bank.lpm) { | |
321 | hw_write(ci, OP_DEVLC, DEVLC_PTS(7) | DEVLC_PTW, lpm); | |
3b5d3e68 CR |
322 | if (sts) |
323 | hw_write(ci, OP_DEVLC, DEVLC_STS, DEVLC_STS); | |
40dcd0e8 MG |
324 | } else { |
325 | hw_write(ci, OP_PORTSC, PORTSC_PTS(7) | PORTSC_PTW, portsc); | |
3b5d3e68 CR |
326 | if (sts) |
327 | hw_write(ci, OP_PORTSC, PORTSC_STS, PORTSC_STS); | |
40dcd0e8 MG |
328 | } |
329 | } | |
330 | ||
1e5e2d3d AT |
331 | /** |
332 | * _ci_usb_phy_init: initialize phy taking in account both phy and usb_phy | |
333 | * interfaces | |
334 | * @ci: the controller | |
335 | * | |
336 | * This function returns an error code if the phy failed to init | |
337 | */ | |
338 | static int _ci_usb_phy_init(struct ci_hdrc *ci) | |
339 | { | |
340 | int ret; | |
341 | ||
342 | if (ci->phy) { | |
343 | ret = phy_init(ci->phy); | |
344 | if (ret) | |
345 | return ret; | |
346 | ||
347 | ret = phy_power_on(ci->phy); | |
348 | if (ret) { | |
349 | phy_exit(ci->phy); | |
350 | return ret; | |
351 | } | |
352 | } else { | |
353 | ret = usb_phy_init(ci->usb_phy); | |
354 | } | |
355 | ||
356 | return ret; | |
357 | } | |
358 | ||
359 | /** | |
360 | * _ci_usb_phy_exit: deinitialize phy taking in account both phy and usb_phy | |
361 | * interfaces | |
362 | * @ci: the controller | |
363 | */ | |
364 | static void ci_usb_phy_exit(struct ci_hdrc *ci) | |
365 | { | |
8feb3680 SB |
366 | if (ci->platdata->flags & CI_HDRC_OVERRIDE_PHY_CONTROL) |
367 | return; | |
368 | ||
1e5e2d3d AT |
369 | if (ci->phy) { |
370 | phy_power_off(ci->phy); | |
371 | phy_exit(ci->phy); | |
372 | } else { | |
373 | usb_phy_shutdown(ci->usb_phy); | |
374 | } | |
375 | } | |
376 | ||
d03cccff PC |
377 | /** |
378 | * ci_usb_phy_init: initialize phy according to different phy type | |
379 | * @ci: the controller | |
19353881 | 380 | * |
d03cccff PC |
381 | * This function returns an error code if usb_phy_init has failed |
382 | */ | |
383 | static int ci_usb_phy_init(struct ci_hdrc *ci) | |
384 | { | |
385 | int ret; | |
386 | ||
8feb3680 SB |
387 | if (ci->platdata->flags & CI_HDRC_OVERRIDE_PHY_CONTROL) |
388 | return 0; | |
389 | ||
d03cccff PC |
390 | switch (ci->platdata->phy_mode) { |
391 | case USBPHY_INTERFACE_MODE_UTMI: | |
392 | case USBPHY_INTERFACE_MODE_UTMIW: | |
393 | case USBPHY_INTERFACE_MODE_HSIC: | |
1e5e2d3d | 394 | ret = _ci_usb_phy_init(ci); |
b82613cf PC |
395 | if (!ret) |
396 | hw_wait_phy_stable(); | |
397 | else | |
d03cccff PC |
398 | return ret; |
399 | hw_phymode_configure(ci); | |
400 | break; | |
401 | case USBPHY_INTERFACE_MODE_ULPI: | |
402 | case USBPHY_INTERFACE_MODE_SERIAL: | |
403 | hw_phymode_configure(ci); | |
1e5e2d3d | 404 | ret = _ci_usb_phy_init(ci); |
d03cccff PC |
405 | if (ret) |
406 | return ret; | |
407 | break; | |
408 | default: | |
1e5e2d3d | 409 | ret = _ci_usb_phy_init(ci); |
b82613cf PC |
410 | if (!ret) |
411 | hw_wait_phy_stable(); | |
d03cccff PC |
412 | } |
413 | ||
414 | return ret; | |
415 | } | |
416 | ||
bf9c85e7 PC |
417 | |
418 | /** | |
419 | * ci_platform_configure: do controller configure | |
420 | * @ci: the controller | |
421 | * | |
422 | */ | |
423 | void ci_platform_configure(struct ci_hdrc *ci) | |
424 | { | |
8022d3d5 PC |
425 | bool is_device_mode, is_host_mode; |
426 | ||
427 | is_device_mode = hw_read(ci, OP_USBMODE, USBMODE_CM) == USBMODE_CM_DC; | |
428 | is_host_mode = hw_read(ci, OP_USBMODE, USBMODE_CM) == USBMODE_CM_HC; | |
429 | ||
430 | if (is_device_mode && | |
431 | (ci->platdata->flags & CI_HDRC_DISABLE_DEVICE_STREAMING)) | |
432 | hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS, USBMODE_CI_SDIS); | |
433 | ||
434 | if (is_host_mode && | |
435 | (ci->platdata->flags & CI_HDRC_DISABLE_HOST_STREAMING)) | |
bf9c85e7 PC |
436 | hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS, USBMODE_CI_SDIS); |
437 | ||
438 | if (ci->platdata->flags & CI_HDRC_FORCE_FULLSPEED) { | |
439 | if (ci->hw_bank.lpm) | |
440 | hw_write(ci, OP_DEVLC, DEVLC_PFSC, DEVLC_PFSC); | |
441 | else | |
442 | hw_write(ci, OP_PORTSC, PORTSC_PFSC, PORTSC_PFSC); | |
443 | } | |
444 | ||
445 | if (ci->platdata->flags & CI_HDRC_SET_NON_ZERO_TTHA) | |
446 | hw_write(ci, OP_TTCTRL, TTCTRL_TTHA_MASK, TTCTRL_TTHA); | |
df96ed8d PC |
447 | |
448 | hw_write(ci, OP_USBCMD, 0xff0000, ci->platdata->itc_setting << 16); | |
449 | ||
65668718 PC |
450 | if (ci->platdata->flags & CI_HDRC_OVERRIDE_AHB_BURST) |
451 | hw_write_id_reg(ci, ID_SBUSCFG, AHBBRST_MASK, | |
452 | ci->platdata->ahb_burst_config); | |
96625ead PC |
453 | |
454 | /* override burst size, take effect only when ahb_burst_config is 0 */ | |
455 | if (!hw_read_id_reg(ci, ID_SBUSCFG, AHBBRST_MASK)) { | |
456 | if (ci->platdata->flags & CI_HDRC_OVERRIDE_TX_BURST) | |
457 | hw_write(ci, OP_BURSTSIZE, TX_BURST_MASK, | |
458 | ci->platdata->tx_burst_size << __ffs(TX_BURST_MASK)); | |
459 | ||
460 | if (ci->platdata->flags & CI_HDRC_OVERRIDE_RX_BURST) | |
461 | hw_write(ci, OP_BURSTSIZE, RX_BURST_MASK, | |
462 | ci->platdata->rx_burst_size); | |
463 | } | |
bf9c85e7 PC |
464 | } |
465 | ||
e443b333 | 466 | /** |
cdd278f2 | 467 | * hw_controller_reset: do controller reset |
e443b333 AS |
468 | * @ci: the controller |
469 | * | |
470 | * This function returns an error code | |
471 | */ | |
cdd278f2 PC |
472 | static int hw_controller_reset(struct ci_hdrc *ci) |
473 | { | |
474 | int count = 0; | |
475 | ||
476 | hw_write(ci, OP_USBCMD, USBCMD_RST, USBCMD_RST); | |
477 | while (hw_read(ci, OP_USBCMD, USBCMD_RST)) { | |
478 | udelay(10); | |
479 | if (count++ > 1000) | |
480 | return -ETIMEDOUT; | |
481 | } | |
482 | ||
483 | return 0; | |
484 | } | |
485 | ||
486 | /** | |
487 | * hw_device_reset: resets chip (execute without interruption) | |
488 | * @ci: the controller | |
489 | * | |
490 | * This function returns an error code | |
491 | */ | |
5b157300 | 492 | int hw_device_reset(struct ci_hdrc *ci) |
e443b333 | 493 | { |
cdd278f2 PC |
494 | int ret; |
495 | ||
e443b333 AS |
496 | /* should flush & stop before reset */ |
497 | hw_write(ci, OP_ENDPTFLUSH, ~0, ~0); | |
498 | hw_write(ci, OP_USBCMD, USBCMD_RS, 0); | |
499 | ||
cdd278f2 PC |
500 | ret = hw_controller_reset(ci); |
501 | if (ret) { | |
502 | dev_err(ci->dev, "error resetting controller, ret=%d\n", ret); | |
503 | return ret; | |
504 | } | |
e443b333 | 505 | |
77c4400f RZ |
506 | if (ci->platdata->notify_event) |
507 | ci->platdata->notify_event(ci, | |
8e22978c | 508 | CI_HDRC_CONTROLLER_RESET_EVENT); |
e443b333 | 509 | |
e443b333 AS |
510 | /* USBMODE should be configured step by step */ |
511 | hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE); | |
5b157300 | 512 | hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_DC); |
e443b333 AS |
513 | /* HW >= 2.3 */ |
514 | hw_write(ci, OP_USBMODE, USBMODE_SLOM, USBMODE_SLOM); | |
515 | ||
5b157300 PC |
516 | if (hw_read(ci, OP_USBMODE, USBMODE_CM) != USBMODE_CM_DC) { |
517 | pr_err("cannot enter in %s device mode", ci_role(ci)->name); | |
e443b333 AS |
518 | pr_err("lpm = %i", ci->hw_bank.lpm); |
519 | return -ENODEV; | |
520 | } | |
521 | ||
bf9c85e7 PC |
522 | ci_platform_configure(ci); |
523 | ||
e443b333 AS |
524 | return 0; |
525 | } | |
526 | ||
5f36e231 AS |
527 | static irqreturn_t ci_irq(int irq, void *data) |
528 | { | |
8e22978c | 529 | struct ci_hdrc *ci = data; |
5f36e231 | 530 | irqreturn_t ret = IRQ_NONE; |
b183c19f | 531 | u32 otgsc = 0; |
5f36e231 | 532 | |
1f874edc PC |
533 | if (ci->in_lpm) { |
534 | disable_irq_nosync(irq); | |
535 | ci->wakeup_int = true; | |
536 | pm_runtime_get(ci->dev); | |
537 | return IRQ_HANDLED; | |
538 | } | |
539 | ||
4dcf720c | 540 | if (ci->is_otg) { |
0c33bf78 | 541 | otgsc = hw_read_otgsc(ci, ~0); |
4dcf720c LJ |
542 | if (ci_otg_is_fsm_mode(ci)) { |
543 | ret = ci_otg_fsm_irq(ci); | |
544 | if (ret == IRQ_HANDLED) | |
545 | return ret; | |
546 | } | |
547 | } | |
5f36e231 | 548 | |
a107f8c5 PC |
549 | /* |
550 | * Handle id change interrupt, it indicates device/host function | |
551 | * switch. | |
552 | */ | |
553 | if (ci->is_otg && (otgsc & OTGSC_IDIE) && (otgsc & OTGSC_IDIS)) { | |
554 | ci->id_event = true; | |
0c33bf78 LJ |
555 | /* Clear ID change irq status */ |
556 | hw_write_otgsc(ci, OTGSC_IDIS, OTGSC_IDIS); | |
be6b0c1b | 557 | ci_otg_queue_work(ci); |
a107f8c5 PC |
558 | return IRQ_HANDLED; |
559 | } | |
b183c19f | 560 | |
a107f8c5 PC |
561 | /* |
562 | * Handle vbus change interrupt, it indicates device connection | |
563 | * and disconnection events. | |
564 | */ | |
565 | if (ci->is_otg && (otgsc & OTGSC_BSVIE) && (otgsc & OTGSC_BSVIS)) { | |
566 | ci->b_sess_valid_event = true; | |
0c33bf78 LJ |
567 | /* Clear BSV irq */ |
568 | hw_write_otgsc(ci, OTGSC_BSVIS, OTGSC_BSVIS); | |
be6b0c1b | 569 | ci_otg_queue_work(ci); |
a107f8c5 | 570 | return IRQ_HANDLED; |
5f36e231 AS |
571 | } |
572 | ||
a107f8c5 PC |
573 | /* Handle device/host interrupt */ |
574 | if (ci->role != CI_ROLE_END) | |
575 | ret = ci_role(ci)->irq(ci); | |
576 | ||
b183c19f | 577 | return ret; |
5f36e231 AS |
578 | } |
579 | ||
5cc49268 SB |
580 | static int ci_cable_notifier(struct notifier_block *nb, unsigned long event, |
581 | void *ptr) | |
3ecb3e09 | 582 | { |
5cc49268 SB |
583 | struct ci_hdrc_cable *cbl = container_of(nb, struct ci_hdrc_cable, nb); |
584 | struct ci_hdrc *ci = cbl->ci; | |
3ecb3e09 | 585 | |
5cc49268 SB |
586 | cbl->connected = event; |
587 | cbl->changed = true; | |
3ecb3e09 II |
588 | |
589 | ci_irq(ci->irq, ci); | |
590 | return NOTIFY_DONE; | |
591 | } | |
592 | ||
1542d9c3 PC |
593 | static int ci_get_platdata(struct device *dev, |
594 | struct ci_hdrc_platform_data *platdata) | |
595 | { | |
3ecb3e09 II |
596 | struct extcon_dev *ext_vbus, *ext_id; |
597 | struct ci_hdrc_cable *cable; | |
79742351 LJ |
598 | int ret; |
599 | ||
c22600c3 PC |
600 | if (!platdata->phy_mode) |
601 | platdata->phy_mode = of_usb_get_phy_mode(dev->of_node); | |
602 | ||
603 | if (!platdata->dr_mode) | |
06e7114f | 604 | platdata->dr_mode = usb_get_dr_mode(dev); |
c22600c3 PC |
605 | |
606 | if (platdata->dr_mode == USB_DR_MODE_UNKNOWN) | |
607 | platdata->dr_mode = USB_DR_MODE_OTG; | |
608 | ||
c2ec3a73 PC |
609 | if (platdata->dr_mode != USB_DR_MODE_PERIPHERAL) { |
610 | /* Get the vbus regulator */ | |
611 | platdata->reg_vbus = devm_regulator_get(dev, "vbus"); | |
612 | if (PTR_ERR(platdata->reg_vbus) == -EPROBE_DEFER) { | |
613 | return -EPROBE_DEFER; | |
614 | } else if (PTR_ERR(platdata->reg_vbus) == -ENODEV) { | |
6629467b | 615 | /* no vbus regulator is needed */ |
c2ec3a73 PC |
616 | platdata->reg_vbus = NULL; |
617 | } else if (IS_ERR(platdata->reg_vbus)) { | |
618 | dev_err(dev, "Getting regulator error: %ld\n", | |
619 | PTR_ERR(platdata->reg_vbus)); | |
620 | return PTR_ERR(platdata->reg_vbus); | |
621 | } | |
f6a9ff07 PC |
622 | /* Get TPL support */ |
623 | if (!platdata->tpl_support) | |
624 | platdata->tpl_support = | |
625 | of_usb_host_tpl_support(dev->of_node); | |
c2ec3a73 PC |
626 | } |
627 | ||
79742351 LJ |
628 | if (platdata->dr_mode == USB_DR_MODE_OTG) { |
629 | /* We can support HNP and SRP of OTG 2.0 */ | |
630 | platdata->ci_otg_caps.otg_rev = 0x0200; | |
631 | platdata->ci_otg_caps.hnp_support = true; | |
632 | platdata->ci_otg_caps.srp_support = true; | |
633 | ||
634 | /* Update otg capabilities by DT properties */ | |
635 | ret = of_usb_update_otg_caps(dev->of_node, | |
636 | &platdata->ci_otg_caps); | |
637 | if (ret) | |
638 | return ret; | |
639 | } | |
640 | ||
63863b98 | 641 | if (usb_get_maximum_speed(dev) == USB_SPEED_FULL) |
4f6743d5 MG |
642 | platdata->flags |= CI_HDRC_FORCE_FULLSPEED; |
643 | ||
4b19b78a | 644 | of_property_read_u32(dev->of_node, "phy-clkgate-delay-us", |
1fbf4628 FE |
645 | &platdata->phy_clkgate_delay_us); |
646 | ||
df96ed8d | 647 | platdata->itc_setting = 1; |
df96ed8d | 648 | |
4b19b78a SS |
649 | of_property_read_u32(dev->of_node, "itc-setting", |
650 | &platdata->itc_setting); | |
651 | ||
652 | ret = of_property_read_u32(dev->of_node, "ahb-burst-config", | |
653 | &platdata->ahb_burst_config); | |
654 | if (!ret) { | |
65668718 | 655 | platdata->flags |= CI_HDRC_OVERRIDE_AHB_BURST; |
4b19b78a SS |
656 | } else if (ret != -EINVAL) { |
657 | dev_err(dev, "failed to get ahb-burst-config\n"); | |
658 | return ret; | |
65668718 PC |
659 | } |
660 | ||
4b19b78a SS |
661 | ret = of_property_read_u32(dev->of_node, "tx-burst-size-dword", |
662 | &platdata->tx_burst_size); | |
663 | if (!ret) { | |
96625ead | 664 | platdata->flags |= CI_HDRC_OVERRIDE_TX_BURST; |
4b19b78a SS |
665 | } else if (ret != -EINVAL) { |
666 | dev_err(dev, "failed to get tx-burst-size-dword\n"); | |
667 | return ret; | |
96625ead PC |
668 | } |
669 | ||
4b19b78a SS |
670 | ret = of_property_read_u32(dev->of_node, "rx-burst-size-dword", |
671 | &platdata->rx_burst_size); | |
672 | if (!ret) { | |
96625ead | 673 | platdata->flags |= CI_HDRC_OVERRIDE_RX_BURST; |
4b19b78a SS |
674 | } else if (ret != -EINVAL) { |
675 | dev_err(dev, "failed to get rx-burst-size-dword\n"); | |
676 | return ret; | |
96625ead PC |
677 | } |
678 | ||
aa738187 PC |
679 | if (of_find_property(dev->of_node, "non-zero-ttctrl-ttha", NULL)) |
680 | platdata->flags |= CI_HDRC_SET_NON_ZERO_TTHA; | |
681 | ||
3ecb3e09 II |
682 | ext_id = ERR_PTR(-ENODEV); |
683 | ext_vbus = ERR_PTR(-ENODEV); | |
684 | if (of_property_read_bool(dev->of_node, "extcon")) { | |
685 | /* Each one of them is not mandatory */ | |
686 | ext_vbus = extcon_get_edev_by_phandle(dev, 0); | |
687 | if (IS_ERR(ext_vbus) && PTR_ERR(ext_vbus) != -ENODEV) | |
688 | return PTR_ERR(ext_vbus); | |
689 | ||
690 | ext_id = extcon_get_edev_by_phandle(dev, 1); | |
691 | if (IS_ERR(ext_id) && PTR_ERR(ext_id) != -ENODEV) | |
692 | return PTR_ERR(ext_id); | |
693 | } | |
694 | ||
695 | cable = &platdata->vbus_extcon; | |
5cc49268 | 696 | cable->nb.notifier_call = ci_cable_notifier; |
3ecb3e09 II |
697 | cable->edev = ext_vbus; |
698 | ||
699 | if (!IS_ERR(ext_vbus)) { | |
3f991aa0 | 700 | ret = extcon_get_state(cable->edev, EXTCON_USB); |
3ecb3e09 | 701 | if (ret) |
5cc49268 | 702 | cable->connected = true; |
3ecb3e09 | 703 | else |
5cc49268 | 704 | cable->connected = false; |
3ecb3e09 II |
705 | } |
706 | ||
707 | cable = &platdata->id_extcon; | |
5cc49268 | 708 | cable->nb.notifier_call = ci_cable_notifier; |
3ecb3e09 II |
709 | cable->edev = ext_id; |
710 | ||
711 | if (!IS_ERR(ext_id)) { | |
3f991aa0 | 712 | ret = extcon_get_state(cable->edev, EXTCON_USB_HOST); |
3ecb3e09 | 713 | if (ret) |
5cc49268 | 714 | cable->connected = true; |
3ecb3e09 | 715 | else |
5cc49268 | 716 | cable->connected = false; |
3ecb3e09 | 717 | } |
1542d9c3 PC |
718 | return 0; |
719 | } | |
720 | ||
3ecb3e09 II |
721 | static int ci_extcon_register(struct ci_hdrc *ci) |
722 | { | |
723 | struct ci_hdrc_cable *id, *vbus; | |
724 | int ret; | |
725 | ||
726 | id = &ci->platdata->id_extcon; | |
727 | id->ci = ci; | |
728 | if (!IS_ERR(id->edev)) { | |
3f991aa0 CC |
729 | ret = devm_extcon_register_notifier(ci->dev, id->edev, |
730 | EXTCON_USB_HOST, &id->nb); | |
3ecb3e09 II |
731 | if (ret < 0) { |
732 | dev_err(ci->dev, "register ID failed\n"); | |
733 | return ret; | |
734 | } | |
735 | } | |
736 | ||
737 | vbus = &ci->platdata->vbus_extcon; | |
738 | vbus->ci = ci; | |
739 | if (!IS_ERR(vbus->edev)) { | |
3f991aa0 CC |
740 | ret = devm_extcon_register_notifier(ci->dev, vbus->edev, |
741 | EXTCON_USB, &vbus->nb); | |
3ecb3e09 | 742 | if (ret < 0) { |
3ecb3e09 II |
743 | dev_err(ci->dev, "register VBUS failed\n"); |
744 | return ret; | |
745 | } | |
746 | } | |
747 | ||
1542d9c3 PC |
748 | return 0; |
749 | } | |
750 | ||
fe6e125e RZ |
751 | static DEFINE_IDA(ci_ida); |
752 | ||
8e22978c | 753 | struct platform_device *ci_hdrc_add_device(struct device *dev, |
cbc6dc2a | 754 | struct resource *res, int nres, |
8e22978c | 755 | struct ci_hdrc_platform_data *platdata) |
cbc6dc2a RZ |
756 | { |
757 | struct platform_device *pdev; | |
fe6e125e | 758 | int id, ret; |
cbc6dc2a | 759 | |
1542d9c3 PC |
760 | ret = ci_get_platdata(dev, platdata); |
761 | if (ret) | |
762 | return ERR_PTR(ret); | |
763 | ||
fe6e125e RZ |
764 | id = ida_simple_get(&ci_ida, 0, 0, GFP_KERNEL); |
765 | if (id < 0) | |
766 | return ERR_PTR(id); | |
767 | ||
768 | pdev = platform_device_alloc("ci_hdrc", id); | |
769 | if (!pdev) { | |
770 | ret = -ENOMEM; | |
771 | goto put_id; | |
772 | } | |
cbc6dc2a RZ |
773 | |
774 | pdev->dev.parent = dev; | |
775 | pdev->dev.dma_mask = dev->dma_mask; | |
776 | pdev->dev.dma_parms = dev->dma_parms; | |
777 | dma_set_coherent_mask(&pdev->dev, dev->coherent_dma_mask); | |
778 | ||
779 | ret = platform_device_add_resources(pdev, res, nres); | |
780 | if (ret) | |
781 | goto err; | |
782 | ||
783 | ret = platform_device_add_data(pdev, platdata, sizeof(*platdata)); | |
784 | if (ret) | |
785 | goto err; | |
786 | ||
787 | ret = platform_device_add(pdev); | |
788 | if (ret) | |
789 | goto err; | |
790 | ||
791 | return pdev; | |
792 | ||
793 | err: | |
794 | platform_device_put(pdev); | |
fe6e125e RZ |
795 | put_id: |
796 | ida_simple_remove(&ci_ida, id); | |
cbc6dc2a RZ |
797 | return ERR_PTR(ret); |
798 | } | |
8e22978c | 799 | EXPORT_SYMBOL_GPL(ci_hdrc_add_device); |
cbc6dc2a | 800 | |
8e22978c | 801 | void ci_hdrc_remove_device(struct platform_device *pdev) |
cbc6dc2a | 802 | { |
98c35534 | 803 | int id = pdev->id; |
cbc6dc2a | 804 | platform_device_unregister(pdev); |
98c35534 | 805 | ida_simple_remove(&ci_ida, id); |
cbc6dc2a | 806 | } |
8e22978c | 807 | EXPORT_SYMBOL_GPL(ci_hdrc_remove_device); |
cbc6dc2a | 808 | |
3f124d23 PC |
809 | static inline void ci_role_destroy(struct ci_hdrc *ci) |
810 | { | |
811 | ci_hdrc_gadget_destroy(ci); | |
812 | ci_hdrc_host_destroy(ci); | |
cbec6bd5 PC |
813 | if (ci->is_otg) |
814 | ci_hdrc_otg_destroy(ci); | |
3f124d23 PC |
815 | } |
816 | ||
577b232f PC |
817 | static void ci_get_otg_capable(struct ci_hdrc *ci) |
818 | { | |
819 | if (ci->platdata->flags & CI_HDRC_DUAL_ROLE_NOT_OTG) | |
820 | ci->is_otg = false; | |
821 | else | |
822 | ci->is_otg = (hw_read(ci, CAP_DCCPARAMS, | |
823 | DCCPARAMS_DC | DCCPARAMS_HC) | |
824 | == (DCCPARAMS_DC | DCCPARAMS_HC)); | |
2e37cfd8 | 825 | if (ci->is_otg) { |
577b232f | 826 | dev_dbg(ci->dev, "It is OTG capable controller\n"); |
2e37cfd8 PC |
827 | /* Disable and clear all OTG irq */ |
828 | hw_write_otgsc(ci, OTGSC_INT_EN_BITS | OTGSC_INT_STATUS_BITS, | |
829 | OTGSC_INT_STATUS_BITS); | |
830 | } | |
577b232f PC |
831 | } |
832 | ||
41ac7b3a | 833 | static int ci_hdrc_probe(struct platform_device *pdev) |
e443b333 AS |
834 | { |
835 | struct device *dev = &pdev->dev; | |
8e22978c | 836 | struct ci_hdrc *ci; |
e443b333 AS |
837 | struct resource *res; |
838 | void __iomem *base; | |
839 | int ret; | |
691962d1 | 840 | enum usb_dr_mode dr_mode; |
e443b333 | 841 | |
fad56745 | 842 | if (!dev_get_platdata(dev)) { |
e443b333 AS |
843 | dev_err(dev, "platform data missing\n"); |
844 | return -ENODEV; | |
845 | } | |
846 | ||
847 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
19290816 FB |
848 | base = devm_ioremap_resource(dev, res); |
849 | if (IS_ERR(base)) | |
850 | return PTR_ERR(base); | |
e443b333 | 851 | |
5f36e231 | 852 | ci = devm_kzalloc(dev, sizeof(*ci), GFP_KERNEL); |
d0f99249 | 853 | if (!ci) |
5f36e231 | 854 | return -ENOMEM; |
5f36e231 | 855 | |
a5d906bb | 856 | spin_lock_init(&ci->lock); |
5f36e231 | 857 | ci->dev = dev; |
fad56745 | 858 | ci->platdata = dev_get_platdata(dev); |
ed8f8318 PC |
859 | ci->imx28_write_fix = !!(ci->platdata->flags & |
860 | CI_HDRC_IMX28_WRITE_FIX); | |
1f874edc PC |
861 | ci->supports_runtime_pm = !!(ci->platdata->flags & |
862 | CI_HDRC_SUPPORTS_RUNTIME_PM); | |
7bb7e9b1 | 863 | platform_set_drvdata(pdev, ci); |
5f36e231 AS |
864 | |
865 | ret = hw_device_init(ci, base); | |
866 | if (ret < 0) { | |
867 | dev_err(dev, "can't initialize hardware\n"); | |
868 | return -ENODEV; | |
869 | } | |
e443b333 | 870 | |
7bb7e9b1 SB |
871 | ret = ci_ulpi_init(ci); |
872 | if (ret) | |
873 | return ret; | |
874 | ||
1e5e2d3d AT |
875 | if (ci->platdata->phy) { |
876 | ci->phy = ci->platdata->phy; | |
877 | } else if (ci->platdata->usb_phy) { | |
ef44cb42 | 878 | ci->usb_phy = ci->platdata->usb_phy; |
1e5e2d3d | 879 | } else { |
21a5b579 AT |
880 | ci->phy = devm_phy_get(dev->parent, "usb-phy"); |
881 | ci->usb_phy = devm_usb_get_phy(dev->parent, USB_PHY_TYPE_USB2); | |
c859aa65 | 882 | |
1e5e2d3d AT |
883 | /* if both generic PHY and USB PHY layers aren't enabled */ |
884 | if (PTR_ERR(ci->phy) == -ENOSYS && | |
7bb7e9b1 SB |
885 | PTR_ERR(ci->usb_phy) == -ENXIO) { |
886 | ret = -ENXIO; | |
887 | goto ulpi_exit; | |
888 | } | |
1e5e2d3d | 889 | |
7bb7e9b1 SB |
890 | if (IS_ERR(ci->phy) && IS_ERR(ci->usb_phy)) { |
891 | ret = -EPROBE_DEFER; | |
892 | goto ulpi_exit; | |
893 | } | |
c859aa65 | 894 | |
1e5e2d3d AT |
895 | if (IS_ERR(ci->phy)) |
896 | ci->phy = NULL; | |
897 | else if (IS_ERR(ci->usb_phy)) | |
898 | ci->usb_phy = NULL; | |
c859aa65 PC |
899 | } |
900 | ||
d03cccff | 901 | ret = ci_usb_phy_init(ci); |
74475ede PC |
902 | if (ret) { |
903 | dev_err(dev, "unable to init phy: %d\n", ret); | |
904 | return ret; | |
905 | } | |
906 | ||
eb70e5ab AS |
907 | ci->hw_bank.phys = res->start; |
908 | ||
5f36e231 AS |
909 | ci->irq = platform_get_irq(pdev, 0); |
910 | if (ci->irq < 0) { | |
e443b333 | 911 | dev_err(dev, "missing IRQ\n"); |
42d18212 | 912 | ret = ci->irq; |
c859aa65 | 913 | goto deinit_phy; |
5f36e231 AS |
914 | } |
915 | ||
577b232f PC |
916 | ci_get_otg_capable(ci); |
917 | ||
691962d1 | 918 | dr_mode = ci->platdata->dr_mode; |
5f36e231 | 919 | /* initialize role(s) before the interrupt is requested */ |
691962d1 SH |
920 | if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_HOST) { |
921 | ret = ci_hdrc_host_init(ci); | |
922 | if (ret) | |
923 | dev_info(dev, "doesn't support host\n"); | |
924 | } | |
eb70e5ab | 925 | |
691962d1 SH |
926 | if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_PERIPHERAL) { |
927 | ret = ci_hdrc_gadget_init(ci); | |
928 | if (ret) | |
929 | dev_info(dev, "doesn't support gadget\n"); | |
930 | } | |
5f36e231 AS |
931 | |
932 | if (!ci->roles[CI_ROLE_HOST] && !ci->roles[CI_ROLE_GADGET]) { | |
933 | dev_err(dev, "no supported roles\n"); | |
74475ede | 934 | ret = -ENODEV; |
c859aa65 | 935 | goto deinit_phy; |
cbec6bd5 PC |
936 | } |
937 | ||
27c62c2d | 938 | if (ci->is_otg && ci->roles[CI_ROLE_GADGET]) { |
cbec6bd5 PC |
939 | ret = ci_hdrc_otg_init(ci); |
940 | if (ret) { | |
941 | dev_err(dev, "init otg fails, ret = %d\n", ret); | |
942 | goto stop; | |
943 | } | |
5f36e231 AS |
944 | } |
945 | ||
946 | if (ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET]) { | |
577b232f | 947 | if (ci->is_otg) { |
577b232f | 948 | ci->role = ci_otg_role(ci); |
0c33bf78 LJ |
949 | /* Enable ID change irq */ |
950 | hw_write_otgsc(ci, OTGSC_IDIE, OTGSC_IDIE); | |
577b232f PC |
951 | } else { |
952 | /* | |
953 | * If the controller is not OTG capable, but support | |
954 | * role switch, the defalt role is gadget, and the | |
955 | * user can switch it through debugfs. | |
956 | */ | |
957 | ci->role = CI_ROLE_GADGET; | |
958 | } | |
5f36e231 AS |
959 | } else { |
960 | ci->role = ci->roles[CI_ROLE_HOST] | |
961 | ? CI_ROLE_HOST | |
962 | : CI_ROLE_GADGET; | |
963 | } | |
964 | ||
4dcf720c | 965 | if (!ci_otg_is_fsm_mode(ci)) { |
961ea496 LJ |
966 | /* only update vbus status for peripheral */ |
967 | if (ci->role == CI_ROLE_GADGET) | |
968 | ci_handle_vbus_change(ci); | |
969 | ||
4dcf720c LJ |
970 | ret = ci_role_start(ci, ci->role); |
971 | if (ret) { | |
972 | dev_err(dev, "can't start %s role\n", | |
973 | ci_role(ci)->name); | |
974 | goto stop; | |
975 | } | |
e443b333 AS |
976 | } |
977 | ||
4c503dd5 PC |
978 | ret = devm_request_irq(dev, ci->irq, ci_irq, IRQF_SHARED, |
979 | ci->platdata->name, ci); | |
5f36e231 AS |
980 | if (ret) |
981 | goto stop; | |
e443b333 | 982 | |
3ecb3e09 II |
983 | ret = ci_extcon_register(ci); |
984 | if (ret) | |
985 | goto stop; | |
986 | ||
1f874edc PC |
987 | if (ci->supports_runtime_pm) { |
988 | pm_runtime_set_active(&pdev->dev); | |
989 | pm_runtime_enable(&pdev->dev); | |
990 | pm_runtime_set_autosuspend_delay(&pdev->dev, 2000); | |
991 | pm_runtime_mark_last_busy(ci->dev); | |
992 | pm_runtime_use_autosuspend(&pdev->dev); | |
993 | } | |
994 | ||
4dcf720c LJ |
995 | if (ci_otg_is_fsm_mode(ci)) |
996 | ci_hdrc_otg_fsm_start(ci); | |
997 | ||
f8efa766 PC |
998 | device_set_wakeup_capable(&pdev->dev, true); |
999 | ||
adf0f735 AS |
1000 | ret = dbg_create_files(ci); |
1001 | if (!ret) | |
1002 | return 0; | |
5f36e231 | 1003 | |
5f36e231 | 1004 | stop: |
3f124d23 | 1005 | ci_role_destroy(ci); |
c859aa65 | 1006 | deinit_phy: |
1e5e2d3d | 1007 | ci_usb_phy_exit(ci); |
7bb7e9b1 SB |
1008 | ulpi_exit: |
1009 | ci_ulpi_exit(ci); | |
e443b333 AS |
1010 | |
1011 | return ret; | |
1012 | } | |
1013 | ||
fb4e98ab | 1014 | static int ci_hdrc_remove(struct platform_device *pdev) |
e443b333 | 1015 | { |
8e22978c | 1016 | struct ci_hdrc *ci = platform_get_drvdata(pdev); |
e443b333 | 1017 | |
1f874edc PC |
1018 | if (ci->supports_runtime_pm) { |
1019 | pm_runtime_get_sync(&pdev->dev); | |
1020 | pm_runtime_disable(&pdev->dev); | |
1021 | pm_runtime_put_noidle(&pdev->dev); | |
1022 | } | |
1023 | ||
adf0f735 | 1024 | dbg_remove_files(ci); |
3f124d23 | 1025 | ci_role_destroy(ci); |
864cf949 | 1026 | ci_hdrc_enter_lpm(ci, true); |
1e5e2d3d | 1027 | ci_usb_phy_exit(ci); |
7bb7e9b1 | 1028 | ci_ulpi_exit(ci); |
e443b333 AS |
1029 | |
1030 | return 0; | |
1031 | } | |
1032 | ||
1f874edc | 1033 | #ifdef CONFIG_PM |
961ea496 LJ |
1034 | /* Prepare wakeup by SRP before suspend */ |
1035 | static void ci_otg_fsm_suspend_for_srp(struct ci_hdrc *ci) | |
1036 | { | |
1037 | if ((ci->fsm.otg->state == OTG_STATE_A_IDLE) && | |
1038 | !hw_read_otgsc(ci, OTGSC_ID)) { | |
1039 | hw_write(ci, OP_PORTSC, PORTSC_W1C_BITS | PORTSC_PP, | |
1040 | PORTSC_PP); | |
1041 | hw_write(ci, OP_PORTSC, PORTSC_W1C_BITS | PORTSC_WKCN, | |
1042 | PORTSC_WKCN); | |
1043 | } | |
1044 | } | |
1045 | ||
1046 | /* Handle SRP when wakeup by data pulse */ | |
1047 | static void ci_otg_fsm_wakeup_by_srp(struct ci_hdrc *ci) | |
1048 | { | |
1049 | if ((ci->fsm.otg->state == OTG_STATE_A_IDLE) && | |
1050 | (ci->fsm.a_bus_drop == 1) && (ci->fsm.a_bus_req == 0)) { | |
1051 | if (!hw_read_otgsc(ci, OTGSC_ID)) { | |
1052 | ci->fsm.a_srp_det = 1; | |
1053 | ci->fsm.a_bus_drop = 0; | |
1054 | } else { | |
1055 | ci->fsm.id = 1; | |
1056 | } | |
1057 | ci_otg_queue_work(ci); | |
1058 | } | |
1059 | } | |
1060 | ||
8076932f PC |
1061 | static void ci_controller_suspend(struct ci_hdrc *ci) |
1062 | { | |
1f874edc | 1063 | disable_irq(ci->irq); |
8076932f | 1064 | ci_hdrc_enter_lpm(ci, true); |
1fbf4628 FE |
1065 | if (ci->platdata->phy_clkgate_delay_us) |
1066 | usleep_range(ci->platdata->phy_clkgate_delay_us, | |
1067 | ci->platdata->phy_clkgate_delay_us + 50); | |
1f874edc PC |
1068 | usb_phy_set_suspend(ci->usb_phy, 1); |
1069 | ci->in_lpm = true; | |
1070 | enable_irq(ci->irq); | |
8076932f PC |
1071 | } |
1072 | ||
1073 | static int ci_controller_resume(struct device *dev) | |
1074 | { | |
1075 | struct ci_hdrc *ci = dev_get_drvdata(dev); | |
7bb7e9b1 | 1076 | int ret; |
8076932f PC |
1077 | |
1078 | dev_dbg(dev, "at %s\n", __func__); | |
1079 | ||
1f874edc PC |
1080 | if (!ci->in_lpm) { |
1081 | WARN_ON(1); | |
1082 | return 0; | |
1083 | } | |
8076932f | 1084 | |
1f874edc | 1085 | ci_hdrc_enter_lpm(ci, false); |
7bb7e9b1 SB |
1086 | |
1087 | ret = ci_ulpi_resume(ci); | |
1088 | if (ret) | |
1089 | return ret; | |
1090 | ||
8076932f PC |
1091 | if (ci->usb_phy) { |
1092 | usb_phy_set_suspend(ci->usb_phy, 0); | |
1093 | usb_phy_set_wakeup(ci->usb_phy, false); | |
1094 | hw_wait_phy_stable(); | |
1095 | } | |
1096 | ||
1f874edc PC |
1097 | ci->in_lpm = false; |
1098 | if (ci->wakeup_int) { | |
1099 | ci->wakeup_int = false; | |
1100 | pm_runtime_mark_last_busy(ci->dev); | |
1101 | pm_runtime_put_autosuspend(ci->dev); | |
1102 | enable_irq(ci->irq); | |
961ea496 LJ |
1103 | if (ci_otg_is_fsm_mode(ci)) |
1104 | ci_otg_fsm_wakeup_by_srp(ci); | |
1f874edc PC |
1105 | } |
1106 | ||
8076932f PC |
1107 | return 0; |
1108 | } | |
1109 | ||
1f874edc | 1110 | #ifdef CONFIG_PM_SLEEP |
8076932f PC |
1111 | static int ci_suspend(struct device *dev) |
1112 | { | |
1113 | struct ci_hdrc *ci = dev_get_drvdata(dev); | |
1114 | ||
1115 | if (ci->wq) | |
1116 | flush_workqueue(ci->wq); | |
1f874edc PC |
1117 | /* |
1118 | * Controller needs to be active during suspend, otherwise the core | |
1119 | * may run resume when the parent is at suspend if other driver's | |
1120 | * suspend fails, it occurs before parent's suspend has not started, | |
1121 | * but the core suspend has finished. | |
1122 | */ | |
1123 | if (ci->in_lpm) | |
1124 | pm_runtime_resume(dev); | |
1125 | ||
1126 | if (ci->in_lpm) { | |
1127 | WARN_ON(1); | |
1128 | return 0; | |
1129 | } | |
8076932f | 1130 | |
f8efa766 | 1131 | if (device_may_wakeup(dev)) { |
961ea496 LJ |
1132 | if (ci_otg_is_fsm_mode(ci)) |
1133 | ci_otg_fsm_suspend_for_srp(ci); | |
1134 | ||
f8efa766 PC |
1135 | usb_phy_set_wakeup(ci->usb_phy, true); |
1136 | enable_irq_wake(ci->irq); | |
1137 | } | |
1138 | ||
8076932f PC |
1139 | ci_controller_suspend(ci); |
1140 | ||
1141 | return 0; | |
1142 | } | |
1143 | ||
1144 | static int ci_resume(struct device *dev) | |
1145 | { | |
1f874edc PC |
1146 | struct ci_hdrc *ci = dev_get_drvdata(dev); |
1147 | int ret; | |
1148 | ||
f8efa766 PC |
1149 | if (device_may_wakeup(dev)) |
1150 | disable_irq_wake(ci->irq); | |
1151 | ||
1f874edc PC |
1152 | ret = ci_controller_resume(dev); |
1153 | if (ret) | |
1154 | return ret; | |
1155 | ||
1156 | if (ci->supports_runtime_pm) { | |
1157 | pm_runtime_disable(dev); | |
1158 | pm_runtime_set_active(dev); | |
1159 | pm_runtime_enable(dev); | |
1160 | } | |
1161 | ||
1162 | return ret; | |
8076932f PC |
1163 | } |
1164 | #endif /* CONFIG_PM_SLEEP */ | |
1165 | ||
1f874edc PC |
1166 | static int ci_runtime_suspend(struct device *dev) |
1167 | { | |
1168 | struct ci_hdrc *ci = dev_get_drvdata(dev); | |
1169 | ||
1170 | dev_dbg(dev, "at %s\n", __func__); | |
1171 | ||
1172 | if (ci->in_lpm) { | |
1173 | WARN_ON(1); | |
1174 | return 0; | |
1175 | } | |
1176 | ||
961ea496 LJ |
1177 | if (ci_otg_is_fsm_mode(ci)) |
1178 | ci_otg_fsm_suspend_for_srp(ci); | |
1179 | ||
1f874edc PC |
1180 | usb_phy_set_wakeup(ci->usb_phy, true); |
1181 | ci_controller_suspend(ci); | |
1182 | ||
1183 | return 0; | |
1184 | } | |
1185 | ||
1186 | static int ci_runtime_resume(struct device *dev) | |
1187 | { | |
1188 | return ci_controller_resume(dev); | |
1189 | } | |
1190 | ||
1191 | #endif /* CONFIG_PM */ | |
8076932f PC |
1192 | static const struct dev_pm_ops ci_pm_ops = { |
1193 | SET_SYSTEM_SLEEP_PM_OPS(ci_suspend, ci_resume) | |
1f874edc | 1194 | SET_RUNTIME_PM_OPS(ci_runtime_suspend, ci_runtime_resume, NULL) |
8076932f | 1195 | }; |
1f874edc | 1196 | |
5f36e231 AS |
1197 | static struct platform_driver ci_hdrc_driver = { |
1198 | .probe = ci_hdrc_probe, | |
7690417d | 1199 | .remove = ci_hdrc_remove, |
e443b333 | 1200 | .driver = { |
5f36e231 | 1201 | .name = "ci_hdrc", |
8076932f | 1202 | .pm = &ci_pm_ops, |
e443b333 AS |
1203 | }, |
1204 | }; | |
1205 | ||
2f01a33b PC |
1206 | static int __init ci_hdrc_platform_register(void) |
1207 | { | |
1208 | ci_hdrc_host_driver_init(); | |
1209 | return platform_driver_register(&ci_hdrc_driver); | |
1210 | } | |
1211 | module_init(ci_hdrc_platform_register); | |
1212 | ||
1213 | static void __exit ci_hdrc_platform_unregister(void) | |
1214 | { | |
1215 | platform_driver_unregister(&ci_hdrc_driver); | |
1216 | } | |
1217 | module_exit(ci_hdrc_platform_unregister); | |
e443b333 | 1218 | |
5f36e231 | 1219 | MODULE_ALIAS("platform:ci_hdrc"); |
e443b333 AS |
1220 | MODULE_LICENSE("GPL v2"); |
1221 | MODULE_AUTHOR("David Lopo <dlopo@chipidea.mips.com>"); | |
5f36e231 | 1222 | MODULE_DESCRIPTION("ChipIdea HDRC Driver"); |