[linux-2.6-block.git] / drivers / usb / chipidea / ci.h

/*
 * ci.h - common structures, functions, and macros of the ChipIdea driver
 *
 * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
 *
 * Author: David Lopo
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#ifndef __DRIVERS_USB_CHIPIDEA_CI_H
#define __DRIVERS_USB_CHIPIDEA_CI_H

#include <linux/list.h>
#include <linux/irqreturn.h>
#include <linux/usb.h>
#include <linux/usb/gadget.h>
#include <linux/usb/otg-fsm.h>

/******************************************************************************
 * DEFINE
 *****************************************************************************/
#define TD_PAGE_COUNT      5
#define CI_HDRC_PAGE_SIZE  4096ul /* page size for TD's */
#define ENDPT_MAX          32

/******************************************************************************
 * REGISTERS
 *****************************************************************************/
/* Identification Registers */
#define ID_ID				0x0
#define ID_HWGENERAL			0x4
#define ID_HWHOST			0x8
#define ID_HWDEVICE			0xc
#define ID_HWTXBUF			0x10
#define ID_HWRXBUF			0x14
#define ID_SBUSCFG			0x90

/* register indices */
enum ci_hw_regs {
	CAP_CAPLENGTH,
	CAP_HCCPARAMS,
	CAP_DCCPARAMS,
	CAP_TESTMODE,
	CAP_LAST = CAP_TESTMODE,
	OP_USBCMD,
	OP_USBSTS,
	OP_USBINTR,
	OP_DEVICEADDR,
	OP_ENDPTLISTADDR,
	OP_TTCTRL,
	OP_PORTSC,
	OP_DEVLC,
	OP_OTGSC,
	OP_USBMODE,
	OP_ENDPTSETUPSTAT,
	OP_ENDPTPRIME,
	OP_ENDPTFLUSH,
	OP_ENDPTSTAT,
	OP_ENDPTCOMPLETE,
	OP_ENDPTCTRL,
	/* endptctrl1..15 follow */
	OP_LAST = OP_ENDPTCTRL + ENDPT_MAX / 2,
};

/******************************************************************************
 * STRUCTURES
 *****************************************************************************/
/**
 * struct ci_hw_ep - endpoint representation
 * @ep: endpoint structure for gadget drivers
 * @dir: endpoint direction (TX/RX)
 * @num: endpoint number
 * @type: endpoint type
 * @name: string description of the endpoint
 * @qh: queue head for this endpoint
 * @wedge: is the endpoint wedged
 * @ci: pointer to the controller
 * @lock: pointer to controller's spinlock
 * @td_pool: pointer to controller's TD pool
 */
struct ci_hw_ep {
	struct usb_ep				ep;
	u8					dir;
	u8					num;
	u8					type;
	char					name[16];
	struct {
		struct list_head	queue;
		struct ci_hw_qh		*ptr;
		dma_addr_t		dma;
	}					qh;
	int					wedge;

	/* global resources */
	struct ci_hdrc				*ci;
	spinlock_t				*lock;
	struct dma_pool				*td_pool;
	struct td_node				*pending_td;
};

enum ci_role {
	CI_ROLE_HOST = 0,
	CI_ROLE_GADGET,
	CI_ROLE_END,
};

enum ci_revision {
	CI_REVISION_1X = 10,	/* Revision 1.x */
	CI_REVISION_20 = 20, /* Revision 2.0 */
	CI_REVISION_21, /* Revision 2.1 */
	CI_REVISION_22, /* Revision 2.2 */
	CI_REVISION_23, /* Revision 2.3 */
	CI_REVISION_24, /* Revision 2.4 */
	CI_REVISION_25, /* Revision 2.5 */
	CI_REVISION_25_PLUS, /* Revision above than 2.5 */
	CI_REVISION_UNKNOWN = 99, /* Unknown Revision */
};

/**
 * struct ci_role_driver - host/gadget role driver
 * @start: start this role
 * @stop: stop this role
 * @irq: irq handler for this role
 * @name: role name string (host/gadget)
 */
struct ci_role_driver {
	int		(*start)(struct ci_hdrc *);
	void		(*stop)(struct ci_hdrc *);
	irqreturn_t	(*irq)(struct ci_hdrc *);
	const char	*name;
};

/**
 * struct hw_bank - hardware register mapping representation
 * @lpm: set if the device is LPM capable
 * @phys: physical address of the controller's registers
 * @abs: absolute address of the beginning of register window
 * @cap: capability registers
 * @op: operational registers
 * @size: size of the register window
 * @regmap: register lookup table
 */
struct hw_bank {
	unsigned	lpm;
	resource_size_t	phys;
	void __iomem	*abs;
	void __iomem	*cap;
	void __iomem	*op;
	size_t		size;
	void __iomem	*regmap[OP_LAST + 1];
};

/**
 * struct ci_hdrc - chipidea device representation
 * @dev: pointer to parent device
 * @lock: access synchronization
 * @hw_bank: hardware register mapping
 * @irq: IRQ number
 * @roles: array of supported roles for this controller
 * @role: current role
 * @is_otg: if the device is otg-capable
 * @fsm: otg finite state machine
 * @otg_fsm_hrtimer: hrtimer for otg fsm timers
 * @hr_timeouts: time out list for active otg fsm timers
 * @enabled_otg_timer_bits: bits of enabled otg timers
 * @next_otg_timer: next nearest enabled timer to be expired
 * @work: work for role changing
 * @wq: workqueue thread
 * @qh_pool: allocation pool for queue heads
 * @td_pool: allocation pool for transfer descriptors
 * @gadget: device side representation for peripheral controller
 * @driver: gadget driver
 * @hw_ep_max: total number of endpoints supported by hardware
 * @ci_hw_ep: array of endpoints
 * @ep0_dir: ep0 direction
 * @ep0out: pointer to ep0 OUT endpoint
 * @ep0in: pointer to ep0 IN endpoint
 * @status: ep0 status request
 * @setaddr: if we should set the address on status completion
 * @address: usb address received from the host
 * @remote_wakeup: host-enabled remote wakeup
 * @suspended: suspended by host
 * @test_mode: the selected test mode
 * @platdata: platform specific information supplied by parent device
 * @vbus_active: is VBUS active
 * @phy: pointer to PHY, if any
 * @usb_phy: pointer to USB PHY, if any and if using the USB PHY framework
 * @hcd: pointer to usb_hcd for ehci host driver
 * @debugfs: root dentry for this controller in debugfs
 * @id_event: indicates there is an id event, and handled at ci_otg_work
 * @b_sess_valid_event: indicates there is a vbus event, and handled
 * at ci_otg_work
 * @imx28_write_fix: Freescale imx28 needs swp instruction for writing
 * @supports_runtime_pm: if runtime pm is supported
 * @in_lpm: if the core in low power mode
 * @wakeup_int: if wakeup interrupt occur
 * @rev: The revision number for controller
 */
struct ci_hdrc {
	struct device			*dev;
	spinlock_t			lock;
	struct hw_bank			hw_bank;
	int				irq;
	struct ci_role_driver		*roles[CI_ROLE_END];
	enum ci_role			role;
	bool				is_otg;
	struct usb_otg			otg;
	struct otg_fsm			fsm;
	struct hrtimer			otg_fsm_hrtimer;
	ktime_t				hr_timeouts[NUM_OTG_FSM_TIMERS];
	unsigned			enabled_otg_timer_bits;
	enum otg_fsm_timer		next_otg_timer;
	struct work_struct		work;
	struct workqueue_struct		*wq;

	struct dma_pool			*qh_pool;
	struct dma_pool			*td_pool;

	struct usb_gadget		gadget;
	struct usb_gadget_driver	*driver;
	unsigned			hw_ep_max;
	struct ci_hw_ep			ci_hw_ep[ENDPT_MAX];
	u32				ep0_dir;
	struct ci_hw_ep			*ep0out, *ep0in;

	struct usb_request		*status;
	bool				setaddr;
	u8				address;
	u8				remote_wakeup;
	u8				suspended;
	u8				test_mode;

	struct ci_hdrc_platform_data	*platdata;
	int				vbus_active;
	struct phy			*phy;
	/* old usb_phy interface */
	struct usb_phy			*usb_phy;
	struct usb_hcd			*hcd;
	struct dentry			*debugfs;
	bool				id_event;
	bool				b_sess_valid_event;
	bool				imx28_write_fix;
	bool				supports_runtime_pm;
	bool				in_lpm;
	bool				wakeup_int;
	enum ci_revision		rev;
};

static inline struct ci_role_driver *ci_role(struct ci_hdrc *ci)
{
	BUG_ON(ci->role >= CI_ROLE_END || !ci->roles[ci->role]);
	return ci->roles[ci->role];
}

static inline int ci_role_start(struct ci_hdrc *ci, enum ci_role role)
{
	int ret;

	if (role >= CI_ROLE_END)
		return -EINVAL;

	if (!ci->roles[role])
		return -ENXIO;

	ret = ci->roles[role]->start(ci);
	if (!ret)
		ci->role = role;
	return ret;
}

static inline void ci_role_stop(struct ci_hdrc *ci)
{
	enum ci_role role = ci->role;

	if (role == CI_ROLE_END)
		return;

	ci->role = CI_ROLE_END;

	ci->roles[role]->stop(ci);
}

/**
 * hw_read_id_reg: reads from a identification register
 * @ci: the controller
 * @offset: offset from the beginning of identification registers region
 * @mask: bitfield mask
 *
 * This function returns register contents
 */
static inline u32 hw_read_id_reg(struct ci_hdrc *ci, u32 offset, u32 mask)
{
	return ioread32(ci->hw_bank.abs + offset) & mask;
}

/**
 * hw_write_id_reg: writes to a identification register
 * @ci: the controller
 * @offset: offset from the beginning of identification registers region
 * @mask: bitfield mask
 * @data: new value
 */
static inline void hw_write_id_reg(struct ci_hdrc *ci, u32 offset,
			    u32 mask, u32 data)
{
	if (~mask)
		data = (ioread32(ci->hw_bank.abs + offset) & ~mask)
			| (data & mask);

	iowrite32(data, ci->hw_bank.abs + offset);
}

/**
 * hw_read: reads from a hw register
 * @ci: the controller
 * @reg:  register index
 * @mask: bitfield mask
 *
 * This function returns register contents
 */
static inline u32 hw_read(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask)
{
	return ioread32(ci->hw_bank.regmap[reg]) & mask;
}

#ifdef CONFIG_SOC_IMX28
static inline void imx28_ci_writel(u32 val, volatile void __iomem *addr)
{
	__asm__ ("swp %0, %0, [%1]" : : "r"(val), "r"(addr));
}
#else
static inline void imx28_ci_writel(u32 val, volatile void __iomem *addr)
{
}
#endif

static inline void __hw_write(struct ci_hdrc *ci, u32 val,
		void __iomem *addr)
{
	if (ci->imx28_write_fix)
		imx28_ci_writel(val, addr);
	else
		iowrite32(val, addr);
}

/**
 * hw_write: writes to a hw register
 * @ci: the controller
 * @reg:  register index
 * @mask: bitfield mask
 * @data: new value
 */
static inline void hw_write(struct ci_hdrc *ci, enum ci_hw_regs reg,
			    u32 mask, u32 data)
{
	if (~mask)
		data = (ioread32(ci->hw_bank.regmap[reg]) & ~mask)
			| (data & mask);

	__hw_write(ci, data, ci->hw_bank.regmap[reg]);
}

/**
 * hw_test_and_clear: tests & clears a hw register
 * @ci: the controller
 * @reg:  register index
 * @mask: bitfield mask
 *
 * This function returns register contents
 */
static inline u32 hw_test_and_clear(struct ci_hdrc *ci, enum ci_hw_regs reg,
				    u32 mask)
{
	u32 val = ioread32(ci->hw_bank.regmap[reg]) & mask;

	__hw_write(ci, val, ci->hw_bank.regmap[reg]);
	return val;
}

/**
 * hw_test_and_write: tests & writes a hw register
 * @ci: the controller
 * @reg:  register index
 * @mask: bitfield mask
 * @data: new value
 *
 * This function returns register contents
 */
static inline u32 hw_test_and_write(struct ci_hdrc *ci, enum ci_hw_regs reg,
				    u32 mask, u32 data)
{
	u32 val = hw_read(ci, reg, ~0);

	hw_write(ci, reg, mask, data);
	return (val & mask) >> __ffs(mask);
}

/**
 * ci_otg_is_fsm_mode: runtime check if otg controller
 * is in otg fsm mode.
 *
 * @ci: chipidea device
 */
static inline bool ci_otg_is_fsm_mode(struct ci_hdrc *ci)
{
#ifdef CONFIG_USB_OTG_FSM
	return ci->is_otg && ci->roles[CI_ROLE_HOST] &&
					ci->roles[CI_ROLE_GADGET];
#else
	return false;
#endif
}

u32 hw_read_intr_enable(struct ci_hdrc *ci);

u32 hw_read_intr_status(struct ci_hdrc *ci);

int hw_device_reset(struct ci_hdrc *ci);

int hw_port_test_set(struct ci_hdrc *ci, u8 mode);

u8 hw_port_test_get(struct ci_hdrc *ci);

int hw_wait_reg(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask,
				u32 value, unsigned int timeout_ms);

#endif	/* __DRIVERS_USB_CHIPIDEA_CI_H */
Commit	Line	Data
e443b333 AS	1	/*
	2	* ci.h - common structures, functions, and macros of the ChipIdea driver
	3	*
	4	* Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
	5	*
	6	* Author: David Lopo
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*/
	12
	13	#ifndef __DRIVERS_USB_CHIPIDEA_CI_H
	14	#define __DRIVERS_USB_CHIPIDEA_CI_H
	15
	16	#include <linux/list.h>
5f36e231	17	#include <linux/irqreturn.h>
eb70e5ab	18	#include <linux/usb.h>
e443b333	19	#include <linux/usb/gadget.h>
57677be5	20	#include <linux/usb/otg-fsm.h>
e443b333 AS	21
	22	/******************************************************************************
	23	* DEFINE
	24	*****************************************************************************/
b983e51a	25	#define TD_PAGE_COUNT 5
8e22978c	26	#define CI_HDRC_PAGE_SIZE 4096ul /* page size for TD's */
e443b333 AS	27	#define ENDPT_MAX 32
e443b333 AS	28
21395a1a MKB	29	/******************************************************************************
	30	* REGISTERS
	31	*****************************************************************************/
655d32e9 PC	32	/* Identification Registers */
	33	#define ID_ID 0x0
	34	#define ID_HWGENERAL 0x4
	35	#define ID_HWHOST 0x8
	36	#define ID_HWDEVICE 0xc
	37	#define ID_HWTXBUF 0x10
	38	#define ID_HWRXBUF 0x14
	39	#define ID_SBUSCFG 0x90
	40
21395a1a MKB	41	/* register indices */
	42	enum ci_hw_regs {
	43	CAP_CAPLENGTH,
	44	CAP_HCCPARAMS,
	45	CAP_DCCPARAMS,
	46	CAP_TESTMODE,
	47	CAP_LAST = CAP_TESTMODE,
	48	OP_USBCMD,
	49	OP_USBSTS,
	50	OP_USBINTR,
	51	OP_DEVICEADDR,
	52	OP_ENDPTLISTADDR,
28362673	53	OP_TTCTRL,
21395a1a MKB	54	OP_PORTSC,
	55	OP_DEVLC,
	56	OP_OTGSC,
	57	OP_USBMODE,
	58	OP_ENDPTSETUPSTAT,
	59	OP_ENDPTPRIME,
	60	OP_ENDPTFLUSH,
	61	OP_ENDPTSTAT,
	62	OP_ENDPTCOMPLETE,
	63	OP_ENDPTCTRL,
	64	/* endptctrl1..15 follow */
	65	OP_LAST = OP_ENDPTCTRL + ENDPT_MAX / 2,
	66	};
	67
e443b333 AS	68	/******************************************************************************
	69	* STRUCTURES
	70	*****************************************************************************/
551a8ac6	71	/**
8e22978c	72	* struct ci_hw_ep - endpoint representation
551a8ac6 AS	73	* @ep: endpoint structure for gadget drivers
	74	* @dir: endpoint direction (TX/RX)
	75	* @num: endpoint number
	76	* @type: endpoint type
	77	* @name: string description of the endpoint
	78	* @qh: queue head for this endpoint
	79	* @wedge: is the endpoint wedged
26c696c6	80	* @ci: pointer to the controller
551a8ac6	81	* @lock: pointer to controller's spinlock
551a8ac6 AS	82	* @td_pool: pointer to controller's TD pool
551a8ac6 AS	83	*/
8e22978c	84	struct ci_hw_ep {
551a8ac6 AS	85	struct usb_ep ep;
	86	u8 dir;
	87	u8 num;
	88	u8 type;
	89	char name[16];
e443b333	90	struct {
551a8ac6	91	struct list_head queue;
8e22978c	92	struct ci_hw_qh *ptr;
551a8ac6 AS	93	dma_addr_t dma;
	94	} qh;
	95	int wedge;
e443b333 AS	96
e443b333 AS	97	/* global resources */
8e22978c	98	struct ci_hdrc *ci;
551a8ac6	99	spinlock_t *lock;
551a8ac6	100	struct dma_pool *td_pool;
2e270412	101	struct td_node *pending_td;
e443b333 AS	102	};
e443b333 AS	103
5f36e231 AS	104	enum ci_role {
	105	CI_ROLE_HOST = 0,
	106	CI_ROLE_GADGET,
	107	CI_ROLE_END,
	108	};
	109
cb271f3c PC	110	enum ci_revision {
	111	CI_REVISION_1X = 10, /* Revision 1.x */
	112	CI_REVISION_20 = 20, /* Revision 2.0 */
	113	CI_REVISION_21, /* Revision 2.1 */
	114	CI_REVISION_22, /* Revision 2.2 */
	115	CI_REVISION_23, /* Revision 2.3 */
	116	CI_REVISION_24, /* Revision 2.4 */
	117	CI_REVISION_25, /* Revision 2.5 */
	118	CI_REVISION_25_PLUS, /* Revision above than 2.5 */
	119	CI_REVISION_UNKNOWN = 99, /* Unknown Revision */
	120	};
	121
5f36e231 AS	122	/**
5f36e231 AS	123	* struct ci_role_driver - host/gadget role driver
19353881 PC	124	* @start: start this role
	125	* @stop: stop this role
	126	* @irq: irq handler for this role
	127	* @name: role name string (host/gadget)
5f36e231 AS	128	*/
5f36e231 AS	129	struct ci_role_driver {
8e22978c AS	130	int (start)(struct ci_hdrc );
	131	void (stop)(struct ci_hdrc );
	132	irqreturn_t (irq)(struct ci_hdrc );
5f36e231 AS	133	const char *name;
	134	};
	135
551a8ac6 AS	136	/**
	137	* struct hw_bank - hardware register mapping representation
	138	* @lpm: set if the device is LPM capable
eb70e5ab	139	* @phys: physical address of the controller's registers
551a8ac6 AS	140	* @abs: absolute address of the beginning of register window
	141	* @cap: capability registers
	142	* @op: operational registers
	143	* @size: size of the register window
	144	* @regmap: register lookup table
	145	*/
e443b333	146	struct hw_bank {
551a8ac6	147	unsigned lpm;
eb70e5ab	148	resource_size_t phys;
551a8ac6 AS	149	void __iomem *abs;
	150	void __iomem *cap;
	151	void __iomem *op;
	152	size_t size;
21395a1a	153	void __iomem *regmap[OP_LAST + 1];
e443b333 AS	154	};
e443b333 AS	155
551a8ac6	156	/**
8e22978c	157	* struct ci_hdrc - chipidea device representation
551a8ac6 AS	158	* @dev: pointer to parent device
	159	* @lock: access synchronization
	160	* @hw_bank: hardware register mapping
	161	* @irq: IRQ number
	162	* @roles: array of supported roles for this controller
	163	* @role: current role
	164	* @is_otg: if the device is otg-capable
57677be5	165	* @fsm: otg finite state machine
3a316ec4 LJ	166	* @otg_fsm_hrtimer: hrtimer for otg fsm timers
	167	* @hr_timeouts: time out list for active otg fsm timers
	168	* @enabled_otg_timer_bits: bits of enabled otg timers
	169	* @next_otg_timer: next nearest enabled timer to be expired
551a8ac6 AS	170	* @work: work for role changing
	171	* @wq: workqueue thread
	172	* @qh_pool: allocation pool for queue heads
	173	* @td_pool: allocation pool for transfer descriptors
	174	* @gadget: device side representation for peripheral controller
	175	* @driver: gadget driver
	176	* @hw_ep_max: total number of endpoints supported by hardware
8e22978c	177	* @ci_hw_ep: array of endpoints
551a8ac6 AS	178	* @ep0_dir: ep0 direction
	179	* @ep0out: pointer to ep0 OUT endpoint
	180	* @ep0in: pointer to ep0 IN endpoint
	181	* @status: ep0 status request
	182	* @setaddr: if we should set the address on status completion
	183	* @address: usb address received from the host
	184	* @remote_wakeup: host-enabled remote wakeup
	185	* @suspended: suspended by host
	186	* @test_mode: the selected test mode
77c4400f	187	* @platdata: platform specific information supplied by parent device
551a8ac6	188	* @vbus_active: is VBUS active
1e5e2d3d AT	189	* @phy: pointer to PHY, if any
1e5e2d3d AT	190	* @usb_phy: pointer to USB PHY, if any and if using the USB PHY framework
eb70e5ab	191	* @hcd: pointer to usb_hcd for ehci host driver
2d651289	192	* @debugfs: root dentry for this controller in debugfs
a107f8c5 PC	193	* @id_event: indicates there is an id event, and handled at ci_otg_work
	194	* @b_sess_valid_event: indicates there is a vbus event, and handled
	195	* at ci_otg_work
ed8f8318	196	* @imx28_write_fix: Freescale imx28 needs swp instruction for writing
1f874edc PC	197	* @supports_runtime_pm: if runtime pm is supported
	198	* @in_lpm: if the core in low power mode
	199	* @wakeup_int: if wakeup interrupt occur
cb271f3c	200	* @rev: The revision number for controller
551a8ac6	201	*/
8e22978c	202	struct ci_hdrc {
551a8ac6 AS	203	struct device *dev;
	204	spinlock_t lock;
	205	struct hw_bank hw_bank;
	206	int irq;
	207	struct ci_role_driver *roles[CI_ROLE_END];
	208	enum ci_role role;
	209	bool is_otg;
ef44cb42	210	struct usb_otg otg;
57677be5	211	struct otg_fsm fsm;
3a316ec4 LJ	212	struct hrtimer otg_fsm_hrtimer;
	213	ktime_t hr_timeouts[NUM_OTG_FSM_TIMERS];
	214	unsigned enabled_otg_timer_bits;
	215	enum otg_fsm_timer next_otg_timer;
551a8ac6 AS	216	struct work_struct work;
	217	struct workqueue_struct *wq;
	218
	219	struct dma_pool *qh_pool;
	220	struct dma_pool *td_pool;
	221
	222	struct usb_gadget gadget;
	223	struct usb_gadget_driver *driver;
	224	unsigned hw_ep_max;
8e22978c	225	struct ci_hw_ep ci_hw_ep[ENDPT_MAX];
551a8ac6	226	u32 ep0_dir;
8e22978c	227	struct ci_hw_ep ep0out, ep0in;
551a8ac6 AS	228
	229	struct usb_request *status;
	230	bool setaddr;
	231	u8 address;
	232	u8 remote_wakeup;
	233	u8 suspended;
	234	u8 test_mode;
	235
8e22978c	236	struct ci_hdrc_platform_data *platdata;
551a8ac6	237	int vbus_active;
1e5e2d3d AT	238	struct phy *phy;
1e5e2d3d AT	239	/* old usb_phy interface */
ef44cb42	240	struct usb_phy *usb_phy;
eb70e5ab	241	struct usb_hcd *hcd;
2d651289	242	struct dentry *debugfs;
a107f8c5 PC	243	bool id_event;
a107f8c5 PC	244	bool b_sess_valid_event;
ed8f8318	245	bool imx28_write_fix;
1f874edc PC	246	bool supports_runtime_pm;
	247	bool in_lpm;
	248	bool wakeup_int;
cb271f3c	249	enum ci_revision rev;
e443b333 AS	250	};
e443b333 AS	251
8e22978c	252	static inline struct ci_role_driver ci_role(struct ci_hdrc ci)
5f36e231 AS	253	{
	254	BUG_ON(ci->role >= CI_ROLE_END \|\| !ci->roles[ci->role]);
	255	return ci->roles[ci->role];
	256	}
	257
8e22978c	258	static inline int ci_role_start(struct ci_hdrc *ci, enum ci_role role)
5f36e231 AS	259	{
	260	int ret;
	261
	262	if (role >= CI_ROLE_END)
	263	return -EINVAL;
	264
	265	if (!ci->roles[role])
	266	return -ENXIO;
	267
	268	ret = ci->roles[role]->start(ci);
	269	if (!ret)
	270	ci->role = role;
	271	return ret;
	272	}
	273
8e22978c	274	static inline void ci_role_stop(struct ci_hdrc *ci)
5f36e231 AS	275	{
	276	enum ci_role role = ci->role;
	277
	278	if (role == CI_ROLE_END)
	279	return;
	280
	281	ci->role = CI_ROLE_END;
	282
	283	ci->roles[role]->stop(ci);
	284	}
	285
655d32e9 PC	286	/**
	287	* hw_read_id_reg: reads from a identification register
	288	* @ci: the controller
	289	* @offset: offset from the beginning of identification registers region
	290	* @mask: bitfield mask
	291	*
	292	* This function returns register contents
	293	*/
	294	static inline u32 hw_read_id_reg(struct ci_hdrc *ci, u32 offset, u32 mask)
	295	{
	296	return ioread32(ci->hw_bank.abs + offset) & mask;
	297	}
	298
	299	/**
	300	* hw_write_id_reg: writes to a identification register
	301	* @ci: the controller
	302	* @offset: offset from the beginning of identification registers region
	303	* @mask: bitfield mask
	304	* @data: new value
	305	*/
	306	static inline void hw_write_id_reg(struct ci_hdrc *ci, u32 offset,
	307	u32 mask, u32 data)
	308	{
	309	if (~mask)
	310	data = (ioread32(ci->hw_bank.abs + offset) & ~mask)
	311	\| (data & mask);
	312
	313	iowrite32(data, ci->hw_bank.abs + offset);
	314	}
	315
e443b333 AS	316	/**
e443b333 AS	317	* hw_read: reads from a hw register
19353881	318	* @ci: the controller
e443b333 AS	319	* @reg: register index
	320	* @mask: bitfield mask
	321	*
	322	* This function returns register contents
	323	*/
8e22978c	324	static inline u32 hw_read(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask)
e443b333	325	{
26c696c6	326	return ioread32(ci->hw_bank.regmap[reg]) & mask;
e443b333 AS	327	}
e443b333 AS	328
ed8f8318 PC	329	#ifdef CONFIG_SOC_IMX28
	330	static inline void imx28_ci_writel(u32 val, volatile void __iomem *addr)
	331	{
	332	__asm__ ("swp %0, %0, [%1]" : : "r"(val), "r"(addr));
	333	}
	334	#else
	335	static inline void imx28_ci_writel(u32 val, volatile void __iomem *addr)
	336	{
	337	}
	338	#endif
	339
	340	static inline void __hw_write(struct ci_hdrc *ci, u32 val,
	341	void __iomem *addr)
	342	{
	343	if (ci->imx28_write_fix)
	344	imx28_ci_writel(val, addr);
	345	else
	346	iowrite32(val, addr);
	347	}
	348
e443b333 AS	349	/**
e443b333 AS	350	* hw_write: writes to a hw register
19353881	351	* @ci: the controller
e443b333 AS	352	* @reg: register index
	353	* @mask: bitfield mask
	354	* @data: new value
	355	*/
8e22978c	356	static inline void hw_write(struct ci_hdrc *ci, enum ci_hw_regs reg,
e443b333 AS	357	u32 mask, u32 data)
	358	{
	359	if (~mask)
26c696c6	360	data = (ioread32(ci->hw_bank.regmap[reg]) & ~mask)
e443b333 AS	361	\| (data & mask);
e443b333 AS	362
ed8f8318	363	__hw_write(ci, data, ci->hw_bank.regmap[reg]);
e443b333 AS	364	}
	365
	366	/**
	367	* hw_test_and_clear: tests & clears a hw register
19353881	368	* @ci: the controller
e443b333 AS	369	* @reg: register index
	370	* @mask: bitfield mask
	371	*
	372	* This function returns register contents
	373	*/
8e22978c	374	static inline u32 hw_test_and_clear(struct ci_hdrc *ci, enum ci_hw_regs reg,
e443b333 AS	375	u32 mask)
e443b333 AS	376	{
26c696c6	377	u32 val = ioread32(ci->hw_bank.regmap[reg]) & mask;
e443b333	378
ed8f8318	379	__hw_write(ci, val, ci->hw_bank.regmap[reg]);
e443b333 AS	380	return val;
	381	}
	382
	383	/**
	384	* hw_test_and_write: tests & writes a hw register
19353881	385	* @ci: the controller
e443b333 AS	386	* @reg: register index
	387	* @mask: bitfield mask
	388	* @data: new value
	389	*
	390	* This function returns register contents
	391	*/
8e22978c	392	static inline u32 hw_test_and_write(struct ci_hdrc *ci, enum ci_hw_regs reg,
e443b333 AS	393	u32 mask, u32 data)
e443b333 AS	394	{
26c696c6	395	u32 val = hw_read(ci, reg, ~0);
e443b333	396
26c696c6	397	hw_write(ci, reg, mask, data);
727b4ddb	398	return (val & mask) >> __ffs(mask);
e443b333 AS	399	}
e443b333 AS	400
57677be5 LJ	401	/**
	402	* ci_otg_is_fsm_mode: runtime check if otg controller
	403	* is in otg fsm mode.
19353881 PC	404	*
19353881 PC	405	* @ci: chipidea device
57677be5 LJ	406	*/
	407	static inline bool ci_otg_is_fsm_mode(struct ci_hdrc *ci)
	408	{
	409	#ifdef CONFIG_USB_OTG_FSM
	410	return ci->is_otg && ci->roles[CI_ROLE_HOST] &&
	411	ci->roles[CI_ROLE_GADGET];
	412	#else
	413	return false;
	414	#endif
	415	}
	416
36304b06 LJ	417	u32 hw_read_intr_enable(struct ci_hdrc *ci);
	418
	419	u32 hw_read_intr_status(struct ci_hdrc *ci);
	420
5b157300	421	int hw_device_reset(struct ci_hdrc *ci);
e443b333	422
8e22978c	423	int hw_port_test_set(struct ci_hdrc *ci, u8 mode);
e443b333	424
8e22978c	425	u8 hw_port_test_get(struct ci_hdrc *ci);
e443b333	426
22fa8445 PC	427	int hw_wait_reg(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask,
	428	u32 value, unsigned int timeout_ms);
	429
e443b333	430	#endif /* __DRIVERS_USB_CHIPIDEA_CI_H */