[linux-2.6-block.git] / drivers / usb / chipidea / ci.h

/*
 * ci.h - common structures, functions, and macros of the ChipIdea driver
 *
 * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
 *
 * Author: David Lopo
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#ifndef __DRIVERS_USB_CHIPIDEA_CI_H
#define __DRIVERS_USB_CHIPIDEA_CI_H

#include <linux/list.h>
#include <linux/irqreturn.h>
#include <linux/usb.h>
#include <linux/usb/gadget.h>
#include <linux/usb/otg-fsm.h>

/******************************************************************************
 * DEFINE
 *****************************************************************************/
#define TD_PAGE_COUNT      5
#define CI_HDRC_PAGE_SIZE  4096ul /* page size for TD's */
#define ENDPT_MAX          32

/******************************************************************************
 * REGISTERS
 *****************************************************************************/
/* register indices */
enum ci_hw_regs {
	CAP_CAPLENGTH,
	CAP_HCCPARAMS,
	CAP_DCCPARAMS,
	CAP_TESTMODE,
	CAP_LAST = CAP_TESTMODE,
	OP_USBCMD,
	OP_USBSTS,
	OP_USBINTR,
	OP_DEVICEADDR,
	OP_ENDPTLISTADDR,
	OP_PORTSC,
	OP_DEVLC,
	OP_OTGSC,
	OP_USBMODE,
	OP_ENDPTSETUPSTAT,
	OP_ENDPTPRIME,
	OP_ENDPTFLUSH,
	OP_ENDPTSTAT,
	OP_ENDPTCOMPLETE,
	OP_ENDPTCTRL,
	/* endptctrl1..15 follow */
	OP_LAST = OP_ENDPTCTRL + ENDPT_MAX / 2,
};

/******************************************************************************
 * STRUCTURES
 *****************************************************************************/
/**
 * struct ci_hw_ep - endpoint representation
 * @ep: endpoint structure for gadget drivers
 * @dir: endpoint direction (TX/RX)
 * @num: endpoint number
 * @type: endpoint type
 * @name: string description of the endpoint
 * @qh: queue head for this endpoint
 * @wedge: is the endpoint wedged
 * @ci: pointer to the controller
 * @lock: pointer to controller's spinlock
 * @td_pool: pointer to controller's TD pool
 */
struct ci_hw_ep {
	struct usb_ep				ep;
	u8					dir;
	u8					num;
	u8					type;
	char					name[16];
	struct {
		struct list_head	queue;
		struct ci_hw_qh		*ptr;
		dma_addr_t		dma;
	}					qh;
	int					wedge;

	/* global resources */
	struct ci_hdrc				*ci;
	spinlock_t				*lock;
	struct dma_pool				*td_pool;
	struct td_node				*pending_td;
};

enum ci_role {
	CI_ROLE_HOST = 0,
	CI_ROLE_GADGET,
	CI_ROLE_END,
};

/**
 * struct ci_role_driver - host/gadget role driver
 * @start: start this role
 * @stop: stop this role
 * @irq: irq handler for this role
 * @name: role name string (host/gadget)
 */
struct ci_role_driver {
	int		(*start)(struct ci_hdrc *);
	void		(*stop)(struct ci_hdrc *);
	irqreturn_t	(*irq)(struct ci_hdrc *);
	const char	*name;
};

/**
 * struct hw_bank - hardware register mapping representation
 * @lpm: set if the device is LPM capable
 * @phys: physical address of the controller's registers
 * @abs: absolute address of the beginning of register window
 * @cap: capability registers
 * @op: operational registers
 * @size: size of the register window
 * @regmap: register lookup table
 */
struct hw_bank {
	unsigned	lpm;
	resource_size_t	phys;
	void __iomem	*abs;
	void __iomem	*cap;
	void __iomem	*op;
	size_t		size;
	void __iomem	*regmap[OP_LAST + 1];
};

/**
 * struct ci_hdrc - chipidea device representation
 * @dev: pointer to parent device
 * @lock: access synchronization
 * @hw_bank: hardware register mapping
 * @irq: IRQ number
 * @roles: array of supported roles for this controller
 * @role: current role
 * @is_otg: if the device is otg-capable
 * @fsm: otg finite state machine
 * @fsm_timer: pointer to timer list of otg fsm
 * @work: work for role changing
 * @wq: workqueue thread
 * @qh_pool: allocation pool for queue heads
 * @td_pool: allocation pool for transfer descriptors
 * @gadget: device side representation for peripheral controller
 * @driver: gadget driver
 * @hw_ep_max: total number of endpoints supported by hardware
 * @ci_hw_ep: array of endpoints
 * @ep0_dir: ep0 direction
 * @ep0out: pointer to ep0 OUT endpoint
 * @ep0in: pointer to ep0 IN endpoint
 * @status: ep0 status request
 * @setaddr: if we should set the address on status completion
 * @address: usb address received from the host
 * @remote_wakeup: host-enabled remote wakeup
 * @suspended: suspended by host
 * @test_mode: the selected test mode
 * @platdata: platform specific information supplied by parent device
 * @vbus_active: is VBUS active
 * @phy: pointer to PHY, if any
 * @usb_phy: pointer to USB PHY, if any and if using the USB PHY framework
 * @hcd: pointer to usb_hcd for ehci host driver
 * @debugfs: root dentry for this controller in debugfs
 * @id_event: indicates there is an id event, and handled at ci_otg_work
 * @b_sess_valid_event: indicates there is a vbus event, and handled
 * at ci_otg_work
 * @imx28_write_fix: Freescale imx28 needs swp instruction for writing
 * @supports_runtime_pm: if runtime pm is supported
 * @in_lpm: if the core in low power mode
 * @wakeup_int: if wakeup interrupt occur
 */
struct ci_hdrc {
	struct device			*dev;
	spinlock_t			lock;
	struct hw_bank			hw_bank;
	int				irq;
	struct ci_role_driver		*roles[CI_ROLE_END];
	enum ci_role			role;
	bool				is_otg;
	struct usb_otg			otg;
	struct otg_fsm			fsm;
	struct ci_otg_fsm_timer_list	*fsm_timer;
	struct work_struct		work;
	struct workqueue_struct		*wq;

	struct dma_pool			*qh_pool;
	struct dma_pool			*td_pool;

	struct usb_gadget		gadget;
	struct usb_gadget_driver	*driver;
	unsigned			hw_ep_max;
	struct ci_hw_ep			ci_hw_ep[ENDPT_MAX];
	u32				ep0_dir;
	struct ci_hw_ep			*ep0out, *ep0in;

	struct usb_request		*status;
	bool				setaddr;
	u8				address;
	u8				remote_wakeup;
	u8				suspended;
	u8				test_mode;

	struct ci_hdrc_platform_data	*platdata;
	int				vbus_active;
	struct phy			*phy;
	/* old usb_phy interface */
	struct usb_phy			*usb_phy;
	struct usb_hcd			*hcd;
	struct dentry			*debugfs;
	bool				id_event;
	bool				b_sess_valid_event;
	bool				imx28_write_fix;
	bool				supports_runtime_pm;
	bool				in_lpm;
	bool				wakeup_int;
};

static inline struct ci_role_driver *ci_role(struct ci_hdrc *ci)
{
	BUG_ON(ci->role >= CI_ROLE_END || !ci->roles[ci->role]);
	return ci->roles[ci->role];
}

static inline int ci_role_start(struct ci_hdrc *ci, enum ci_role role)
{
	int ret;

	if (role >= CI_ROLE_END)
		return -EINVAL;

	if (!ci->roles[role])
		return -ENXIO;

	ret = ci->roles[role]->start(ci);
	if (!ret)
		ci->role = role;
	return ret;
}

static inline void ci_role_stop(struct ci_hdrc *ci)
{
	enum ci_role role = ci->role;

	if (role == CI_ROLE_END)
		return;

	ci->role = CI_ROLE_END;

	ci->roles[role]->stop(ci);
}

/**
 * hw_read: reads from a hw register
 * @ci: the controller
 * @reg:  register index
 * @mask: bitfield mask
 *
 * This function returns register contents
 */
static inline u32 hw_read(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask)
{
	return ioread32(ci->hw_bank.regmap[reg]) & mask;
}

#ifdef CONFIG_SOC_IMX28
static inline void imx28_ci_writel(u32 val, volatile void __iomem *addr)
{
	__asm__ ("swp %0, %0, [%1]" : : "r"(val), "r"(addr));
}
#else
static inline void imx28_ci_writel(u32 val, volatile void __iomem *addr)
{
}
#endif

static inline void __hw_write(struct ci_hdrc *ci, u32 val,
		void __iomem *addr)
{
	if (ci->imx28_write_fix)
		imx28_ci_writel(val, addr);
	else
		iowrite32(val, addr);
}

/**
 * hw_write: writes to a hw register
 * @ci: the controller
 * @reg:  register index
 * @mask: bitfield mask
 * @data: new value
 */
static inline void hw_write(struct ci_hdrc *ci, enum ci_hw_regs reg,
			    u32 mask, u32 data)
{
	if (~mask)
		data = (ioread32(ci->hw_bank.regmap[reg]) & ~mask)
			| (data & mask);

	__hw_write(ci, data, ci->hw_bank.regmap[reg]);
}

/**
 * hw_test_and_clear: tests & clears a hw register
 * @ci: the controller
 * @reg:  register index
 * @mask: bitfield mask
 *
 * This function returns register contents
 */
static inline u32 hw_test_and_clear(struct ci_hdrc *ci, enum ci_hw_regs reg,
				    u32 mask)
{
	u32 val = ioread32(ci->hw_bank.regmap[reg]) & mask;

	__hw_write(ci, val, ci->hw_bank.regmap[reg]);
	return val;
}

/**
 * hw_test_and_write: tests & writes a hw register
 * @ci: the controller
 * @reg:  register index
 * @mask: bitfield mask
 * @data: new value
 *
 * This function returns register contents
 */
static inline u32 hw_test_and_write(struct ci_hdrc *ci, enum ci_hw_regs reg,
				    u32 mask, u32 data)
{
	u32 val = hw_read(ci, reg, ~0);

	hw_write(ci, reg, mask, data);
	return (val & mask) >> __ffs(mask);
}

/**
 * ci_otg_is_fsm_mode: runtime check if otg controller
 * is in otg fsm mode.
 *
 * @ci: chipidea device
 */
static inline bool ci_otg_is_fsm_mode(struct ci_hdrc *ci)
{
#ifdef CONFIG_USB_OTG_FSM
	return ci->is_otg && ci->roles[CI_ROLE_HOST] &&
					ci->roles[CI_ROLE_GADGET];
#else
	return false;
#endif
}

u32 hw_read_intr_enable(struct ci_hdrc *ci);

u32 hw_read_intr_status(struct ci_hdrc *ci);

int hw_device_reset(struct ci_hdrc *ci);

int hw_port_test_set(struct ci_hdrc *ci, u8 mode);

u8 hw_port_test_get(struct ci_hdrc *ci);

int hw_wait_reg(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask,
				u32 value, unsigned int timeout_ms);

#endif	/* __DRIVERS_USB_CHIPIDEA_CI_H */
Commit	Line	Data
e443b333 AS	1	/*
	2	* ci.h - common structures, functions, and macros of the ChipIdea driver
	3	*
	4	* Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
	5	*
	6	* Author: David Lopo
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*/
	12
	13	#ifndef __DRIVERS_USB_CHIPIDEA_CI_H
	14	#define __DRIVERS_USB_CHIPIDEA_CI_H
	15
	16	#include <linux/list.h>
5f36e231	17	#include <linux/irqreturn.h>
eb70e5ab	18	#include <linux/usb.h>
e443b333	19	#include <linux/usb/gadget.h>
57677be5	20	#include <linux/usb/otg-fsm.h>
e443b333 AS	21
	22	/******************************************************************************
	23	* DEFINE
	24	*****************************************************************************/
b983e51a	25	#define TD_PAGE_COUNT 5
8e22978c	26	#define CI_HDRC_PAGE_SIZE 4096ul /* page size for TD's */
e443b333 AS	27	#define ENDPT_MAX 32
e443b333 AS	28
21395a1a MKB	29	/******************************************************************************
	30	* REGISTERS
	31	*****************************************************************************/
	32	/* register indices */
	33	enum ci_hw_regs {
	34	CAP_CAPLENGTH,
	35	CAP_HCCPARAMS,
	36	CAP_DCCPARAMS,
	37	CAP_TESTMODE,
	38	CAP_LAST = CAP_TESTMODE,
	39	OP_USBCMD,
	40	OP_USBSTS,
	41	OP_USBINTR,
	42	OP_DEVICEADDR,
	43	OP_ENDPTLISTADDR,
	44	OP_PORTSC,
	45	OP_DEVLC,
	46	OP_OTGSC,
	47	OP_USBMODE,
	48	OP_ENDPTSETUPSTAT,
	49	OP_ENDPTPRIME,
	50	OP_ENDPTFLUSH,
	51	OP_ENDPTSTAT,
	52	OP_ENDPTCOMPLETE,
	53	OP_ENDPTCTRL,
	54	/* endptctrl1..15 follow */
	55	OP_LAST = OP_ENDPTCTRL + ENDPT_MAX / 2,
	56	};
	57
e443b333 AS	58	/******************************************************************************
	59	* STRUCTURES
	60	*****************************************************************************/
551a8ac6	61	/**
8e22978c	62	* struct ci_hw_ep - endpoint representation
551a8ac6 AS	63	* @ep: endpoint structure for gadget drivers
	64	* @dir: endpoint direction (TX/RX)
	65	* @num: endpoint number
	66	* @type: endpoint type
	67	* @name: string description of the endpoint
	68	* @qh: queue head for this endpoint
	69	* @wedge: is the endpoint wedged
26c696c6	70	* @ci: pointer to the controller
551a8ac6	71	* @lock: pointer to controller's spinlock
551a8ac6 AS	72	* @td_pool: pointer to controller's TD pool
551a8ac6 AS	73	*/
8e22978c	74	struct ci_hw_ep {
551a8ac6 AS	75	struct usb_ep ep;
	76	u8 dir;
	77	u8 num;
	78	u8 type;
	79	char name[16];
e443b333	80	struct {
551a8ac6	81	struct list_head queue;
8e22978c	82	struct ci_hw_qh *ptr;
551a8ac6 AS	83	dma_addr_t dma;
	84	} qh;
	85	int wedge;
e443b333 AS	86
e443b333 AS	87	/* global resources */
8e22978c	88	struct ci_hdrc *ci;
551a8ac6	89	spinlock_t *lock;
551a8ac6	90	struct dma_pool *td_pool;
2e270412	91	struct td_node *pending_td;
e443b333 AS	92	};
e443b333 AS	93
5f36e231 AS	94	enum ci_role {
	95	CI_ROLE_HOST = 0,
	96	CI_ROLE_GADGET,
	97	CI_ROLE_END,
	98	};
	99
	100	/**
	101	* struct ci_role_driver - host/gadget role driver
19353881 PC	102	* @start: start this role
	103	* @stop: stop this role
	104	* @irq: irq handler for this role
	105	* @name: role name string (host/gadget)
5f36e231 AS	106	*/
5f36e231 AS	107	struct ci_role_driver {
8e22978c AS	108	int (start)(struct ci_hdrc );
	109	void (stop)(struct ci_hdrc );
	110	irqreturn_t (irq)(struct ci_hdrc );
5f36e231 AS	111	const char *name;
	112	};
	113
551a8ac6 AS	114	/**
	115	* struct hw_bank - hardware register mapping representation
	116	* @lpm: set if the device is LPM capable
eb70e5ab	117	* @phys: physical address of the controller's registers
551a8ac6 AS	118	* @abs: absolute address of the beginning of register window
	119	* @cap: capability registers
	120	* @op: operational registers
	121	* @size: size of the register window
	122	* @regmap: register lookup table
	123	*/
e443b333	124	struct hw_bank {
551a8ac6	125	unsigned lpm;
eb70e5ab	126	resource_size_t phys;
551a8ac6 AS	127	void __iomem *abs;
	128	void __iomem *cap;
	129	void __iomem *op;
	130	size_t size;
21395a1a	131	void __iomem *regmap[OP_LAST + 1];
e443b333 AS	132	};
e443b333 AS	133
551a8ac6	134	/**
8e22978c	135	* struct ci_hdrc - chipidea device representation
551a8ac6 AS	136	* @dev: pointer to parent device
	137	* @lock: access synchronization
	138	* @hw_bank: hardware register mapping
	139	* @irq: IRQ number
	140	* @roles: array of supported roles for this controller
	141	* @role: current role
	142	* @is_otg: if the device is otg-capable
57677be5	143	* @fsm: otg finite state machine
826cfe75	144	* @fsm_timer: pointer to timer list of otg fsm
551a8ac6 AS	145	* @work: work for role changing
	146	* @wq: workqueue thread
	147	* @qh_pool: allocation pool for queue heads
	148	* @td_pool: allocation pool for transfer descriptors
	149	* @gadget: device side representation for peripheral controller
	150	* @driver: gadget driver
	151	* @hw_ep_max: total number of endpoints supported by hardware
8e22978c	152	* @ci_hw_ep: array of endpoints
551a8ac6 AS	153	* @ep0_dir: ep0 direction
	154	* @ep0out: pointer to ep0 OUT endpoint
	155	* @ep0in: pointer to ep0 IN endpoint
	156	* @status: ep0 status request
	157	* @setaddr: if we should set the address on status completion
	158	* @address: usb address received from the host
	159	* @remote_wakeup: host-enabled remote wakeup
	160	* @suspended: suspended by host
	161	* @test_mode: the selected test mode
77c4400f	162	* @platdata: platform specific information supplied by parent device
551a8ac6	163	* @vbus_active: is VBUS active
1e5e2d3d AT	164	* @phy: pointer to PHY, if any
1e5e2d3d AT	165	* @usb_phy: pointer to USB PHY, if any and if using the USB PHY framework
eb70e5ab	166	* @hcd: pointer to usb_hcd for ehci host driver
2d651289	167	* @debugfs: root dentry for this controller in debugfs
a107f8c5 PC	168	* @id_event: indicates there is an id event, and handled at ci_otg_work
	169	* @b_sess_valid_event: indicates there is a vbus event, and handled
	170	* at ci_otg_work
ed8f8318	171	* @imx28_write_fix: Freescale imx28 needs swp instruction for writing
1f874edc PC	172	* @supports_runtime_pm: if runtime pm is supported
	173	* @in_lpm: if the core in low power mode
	174	* @wakeup_int: if wakeup interrupt occur
551a8ac6	175	*/
8e22978c	176	struct ci_hdrc {
551a8ac6 AS	177	struct device *dev;
	178	spinlock_t lock;
	179	struct hw_bank hw_bank;
	180	int irq;
	181	struct ci_role_driver *roles[CI_ROLE_END];
	182	enum ci_role role;
	183	bool is_otg;
ef44cb42	184	struct usb_otg otg;
57677be5	185	struct otg_fsm fsm;
826cfe75	186	struct ci_otg_fsm_timer_list *fsm_timer;
551a8ac6 AS	187	struct work_struct work;
	188	struct workqueue_struct *wq;
	189
	190	struct dma_pool *qh_pool;
	191	struct dma_pool *td_pool;
	192
	193	struct usb_gadget gadget;
	194	struct usb_gadget_driver *driver;
	195	unsigned hw_ep_max;
8e22978c	196	struct ci_hw_ep ci_hw_ep[ENDPT_MAX];
551a8ac6	197	u32 ep0_dir;
8e22978c	198	struct ci_hw_ep ep0out, ep0in;
551a8ac6 AS	199
	200	struct usb_request *status;
	201	bool setaddr;
	202	u8 address;
	203	u8 remote_wakeup;
	204	u8 suspended;
	205	u8 test_mode;
	206
8e22978c	207	struct ci_hdrc_platform_data *platdata;
551a8ac6	208	int vbus_active;
1e5e2d3d AT	209	struct phy *phy;
1e5e2d3d AT	210	/* old usb_phy interface */
ef44cb42	211	struct usb_phy *usb_phy;
eb70e5ab	212	struct usb_hcd *hcd;
2d651289	213	struct dentry *debugfs;
a107f8c5 PC	214	bool id_event;
a107f8c5 PC	215	bool b_sess_valid_event;
ed8f8318	216	bool imx28_write_fix;
1f874edc PC	217	bool supports_runtime_pm;
	218	bool in_lpm;
	219	bool wakeup_int;
e443b333 AS	220	};
e443b333 AS	221
8e22978c	222	static inline struct ci_role_driver ci_role(struct ci_hdrc ci)
5f36e231 AS	223	{
	224	BUG_ON(ci->role >= CI_ROLE_END \|\| !ci->roles[ci->role]);
	225	return ci->roles[ci->role];
	226	}
	227
8e22978c	228	static inline int ci_role_start(struct ci_hdrc *ci, enum ci_role role)
5f36e231 AS	229	{
	230	int ret;
	231
	232	if (role >= CI_ROLE_END)
	233	return -EINVAL;
	234
	235	if (!ci->roles[role])
	236	return -ENXIO;
	237
	238	ret = ci->roles[role]->start(ci);
	239	if (!ret)
	240	ci->role = role;
	241	return ret;
	242	}
	243
8e22978c	244	static inline void ci_role_stop(struct ci_hdrc *ci)
5f36e231 AS	245	{
	246	enum ci_role role = ci->role;
	247
	248	if (role == CI_ROLE_END)
	249	return;
	250
	251	ci->role = CI_ROLE_END;
	252
	253	ci->roles[role]->stop(ci);
	254	}
	255
e443b333 AS	256	/**
e443b333 AS	257	* hw_read: reads from a hw register
19353881	258	* @ci: the controller
e443b333 AS	259	* @reg: register index
	260	* @mask: bitfield mask
	261	*
	262	* This function returns register contents
	263	*/
8e22978c	264	static inline u32 hw_read(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask)
e443b333	265	{
26c696c6	266	return ioread32(ci->hw_bank.regmap[reg]) & mask;
e443b333 AS	267	}
e443b333 AS	268
ed8f8318 PC	269	#ifdef CONFIG_SOC_IMX28
	270	static inline void imx28_ci_writel(u32 val, volatile void __iomem *addr)
	271	{
	272	__asm__ ("swp %0, %0, [%1]" : : "r"(val), "r"(addr));
	273	}
	274	#else
	275	static inline void imx28_ci_writel(u32 val, volatile void __iomem *addr)
	276	{
	277	}
	278	#endif
	279
	280	static inline void __hw_write(struct ci_hdrc *ci, u32 val,
	281	void __iomem *addr)
	282	{
	283	if (ci->imx28_write_fix)
	284	imx28_ci_writel(val, addr);
	285	else
	286	iowrite32(val, addr);
	287	}
	288
e443b333 AS	289	/**
e443b333 AS	290	* hw_write: writes to a hw register
19353881	291	* @ci: the controller
e443b333 AS	292	* @reg: register index
	293	* @mask: bitfield mask
	294	* @data: new value
	295	*/
8e22978c	296	static inline void hw_write(struct ci_hdrc *ci, enum ci_hw_regs reg,
e443b333 AS	297	u32 mask, u32 data)
	298	{
	299	if (~mask)
26c696c6	300	data = (ioread32(ci->hw_bank.regmap[reg]) & ~mask)
e443b333 AS	301	\| (data & mask);
e443b333 AS	302
ed8f8318	303	__hw_write(ci, data, ci->hw_bank.regmap[reg]);
e443b333 AS	304	}
	305
	306	/**
	307	* hw_test_and_clear: tests & clears a hw register
19353881	308	* @ci: the controller
e443b333 AS	309	* @reg: register index
	310	* @mask: bitfield mask
	311	*
	312	* This function returns register contents
	313	*/
8e22978c	314	static inline u32 hw_test_and_clear(struct ci_hdrc *ci, enum ci_hw_regs reg,
e443b333 AS	315	u32 mask)
e443b333 AS	316	{
26c696c6	317	u32 val = ioread32(ci->hw_bank.regmap[reg]) & mask;
e443b333	318
ed8f8318	319	__hw_write(ci, val, ci->hw_bank.regmap[reg]);
e443b333 AS	320	return val;
	321	}
	322
	323	/**
	324	* hw_test_and_write: tests & writes a hw register
19353881	325	* @ci: the controller
e443b333 AS	326	* @reg: register index
	327	* @mask: bitfield mask
	328	* @data: new value
	329	*
	330	* This function returns register contents
	331	*/
8e22978c	332	static inline u32 hw_test_and_write(struct ci_hdrc *ci, enum ci_hw_regs reg,
e443b333 AS	333	u32 mask, u32 data)
e443b333 AS	334	{
26c696c6	335	u32 val = hw_read(ci, reg, ~0);
e443b333	336
26c696c6	337	hw_write(ci, reg, mask, data);
727b4ddb	338	return (val & mask) >> __ffs(mask);
e443b333 AS	339	}
e443b333 AS	340
57677be5 LJ	341	/**
	342	* ci_otg_is_fsm_mode: runtime check if otg controller
	343	* is in otg fsm mode.
19353881 PC	344	*
19353881 PC	345	* @ci: chipidea device
57677be5 LJ	346	*/
	347	static inline bool ci_otg_is_fsm_mode(struct ci_hdrc *ci)
	348	{
	349	#ifdef CONFIG_USB_OTG_FSM
	350	return ci->is_otg && ci->roles[CI_ROLE_HOST] &&
	351	ci->roles[CI_ROLE_GADGET];
	352	#else
	353	return false;
	354	#endif
	355	}
	356
36304b06 LJ	357	u32 hw_read_intr_enable(struct ci_hdrc *ci);
	358
	359	u32 hw_read_intr_status(struct ci_hdrc *ci);
	360
5b157300	361	int hw_device_reset(struct ci_hdrc *ci);
e443b333	362
8e22978c	363	int hw_port_test_set(struct ci_hdrc *ci, u8 mode);
e443b333	364
8e22978c	365	u8 hw_port_test_get(struct ci_hdrc *ci);
e443b333	366
22fa8445 PC	367	int hw_wait_reg(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask,
	368	u32 value, unsigned int timeout_ms);
	369
e443b333	370	#endif /* __DRIVERS_USB_CHIPIDEA_CI_H */