[linux-2.6-block.git] / drivers / usb / chipidea / ci.h

/*
 * ci.h - common structures, functions, and macros of the ChipIdea driver
 *
 * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
 *
 * Author: David Lopo
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#ifndef __DRIVERS_USB_CHIPIDEA_CI_H
#define __DRIVERS_USB_CHIPIDEA_CI_H

#include <linux/list.h>
#include <linux/irqreturn.h>
#include <linux/usb.h>
#include <linux/usb/gadget.h>

/******************************************************************************
 * DEFINE
 *****************************************************************************/
#define TD_PAGE_COUNT      5
#define CI_HDRC_PAGE_SIZE  4096ul /* page size for TD's */
#define ENDPT_MAX          32

/******************************************************************************
 * REGISTERS
 *****************************************************************************/
/* register indices */
enum ci_hw_regs {
	CAP_CAPLENGTH,
	CAP_HCCPARAMS,
	CAP_DCCPARAMS,
	CAP_TESTMODE,
	CAP_LAST = CAP_TESTMODE,
	OP_USBCMD,
	OP_USBSTS,
	OP_USBINTR,
	OP_DEVICEADDR,
	OP_ENDPTLISTADDR,
	OP_PORTSC,
	OP_DEVLC,
	OP_OTGSC,
	OP_USBMODE,
	OP_ENDPTSETUPSTAT,
	OP_ENDPTPRIME,
	OP_ENDPTFLUSH,
	OP_ENDPTSTAT,
	OP_ENDPTCOMPLETE,
	OP_ENDPTCTRL,
	/* endptctrl1..15 follow */
	OP_LAST = OP_ENDPTCTRL + ENDPT_MAX / 2,
};

/******************************************************************************
 * STRUCTURES
 *****************************************************************************/
/**
 * struct ci_hw_ep - endpoint representation
 * @ep: endpoint structure for gadget drivers
 * @dir: endpoint direction (TX/RX)
 * @num: endpoint number
 * @type: endpoint type
 * @name: string description of the endpoint
 * @qh: queue head for this endpoint
 * @wedge: is the endpoint wedged
 * @ci: pointer to the controller
 * @lock: pointer to controller's spinlock
 * @td_pool: pointer to controller's TD pool
 */
struct ci_hw_ep {
	struct usb_ep				ep;
	u8					dir;
	u8					num;
	u8					type;
	char					name[16];
	struct {
		struct list_head	queue;
		struct ci_hw_qh		*ptr;
		dma_addr_t		dma;
	}					qh;
	int					wedge;

	/* global resources */
	struct ci_hdrc				*ci;
	spinlock_t				*lock;
	struct dma_pool				*td_pool;
	struct td_node				*pending_td;
};

enum ci_role {
	CI_ROLE_HOST = 0,
	CI_ROLE_GADGET,
	CI_ROLE_END,
};

/**
 * struct ci_role_driver - host/gadget role driver
 * start: start this role
 * stop: stop this role
 * irq: irq handler for this role
 * name: role name string (host/gadget)
 */
struct ci_role_driver {
	int		(*start)(struct ci_hdrc *);
	void		(*stop)(struct ci_hdrc *);
	irqreturn_t	(*irq)(struct ci_hdrc *);
	const char	*name;
};

/**
 * struct hw_bank - hardware register mapping representation
 * @lpm: set if the device is LPM capable
 * @phys: physical address of the controller's registers
 * @abs: absolute address of the beginning of register window
 * @cap: capability registers
 * @op: operational registers
 * @size: size of the register window
 * @regmap: register lookup table
 */
struct hw_bank {
	unsigned	lpm;
	resource_size_t	phys;
	void __iomem	*abs;
	void __iomem	*cap;
	void __iomem	*op;
	size_t		size;
	void __iomem	*regmap[OP_LAST + 1];
};

/**
 * struct ci_hdrc - chipidea device representation
 * @dev: pointer to parent device
 * @lock: access synchronization
 * @hw_bank: hardware register mapping
 * @irq: IRQ number
 * @roles: array of supported roles for this controller
 * @role: current role
 * @is_otg: if the device is otg-capable
 * @work: work for role changing
 * @wq: workqueue thread
 * @qh_pool: allocation pool for queue heads
 * @td_pool: allocation pool for transfer descriptors
 * @gadget: device side representation for peripheral controller
 * @driver: gadget driver
 * @hw_ep_max: total number of endpoints supported by hardware
 * @ci_hw_ep: array of endpoints
 * @ep0_dir: ep0 direction
 * @ep0out: pointer to ep0 OUT endpoint
 * @ep0in: pointer to ep0 IN endpoint
 * @status: ep0 status request
 * @setaddr: if we should set the address on status completion
 * @address: usb address received from the host
 * @remote_wakeup: host-enabled remote wakeup
 * @suspended: suspended by host
 * @test_mode: the selected test mode
 * @platdata: platform specific information supplied by parent device
 * @vbus_active: is VBUS active
 * @transceiver: pointer to USB PHY, if any
 * @hcd: pointer to usb_hcd for ehci host driver
 * @debugfs: root dentry for this controller in debugfs
 * @id_event: indicates there is an id event, and handled at ci_otg_work
 * @b_sess_valid_event: indicates there is a vbus event, and handled
 * at ci_otg_work
 * @imx28_write_fix: Freescale imx28 needs swp instruction for writing
 */
struct ci_hdrc {
	struct device			*dev;
	spinlock_t			lock;
	struct hw_bank			hw_bank;
	int				irq;
	struct ci_role_driver		*roles[CI_ROLE_END];
	enum ci_role			role;
	bool				is_otg;
	struct work_struct		work;
	struct workqueue_struct		*wq;

	struct dma_pool			*qh_pool;
	struct dma_pool			*td_pool;

	struct usb_gadget		gadget;
	struct usb_gadget_driver	*driver;
	unsigned			hw_ep_max;
	struct ci_hw_ep			ci_hw_ep[ENDPT_MAX];
	u32				ep0_dir;
	struct ci_hw_ep			*ep0out, *ep0in;

	struct usb_request		*status;
	bool				setaddr;
	u8				address;
	u8				remote_wakeup;
	u8				suspended;
	u8				test_mode;

	struct ci_hdrc_platform_data	*platdata;
	int				vbus_active;
	/* FIXME: some day, we'll not use global phy */
	bool				global_phy;
	struct usb_phy			*transceiver;
	struct usb_hcd			*hcd;
	struct dentry			*debugfs;
	bool				id_event;
	bool				b_sess_valid_event;
	bool				imx28_write_fix;
};

static inline struct ci_role_driver *ci_role(struct ci_hdrc *ci)
{
	BUG_ON(ci->role >= CI_ROLE_END || !ci->roles[ci->role]);
	return ci->roles[ci->role];
}

static inline int ci_role_start(struct ci_hdrc *ci, enum ci_role role)
{
	int ret;

	if (role >= CI_ROLE_END)
		return -EINVAL;

	if (!ci->roles[role])
		return -ENXIO;

	ret = ci->roles[role]->start(ci);
	if (!ret)
		ci->role = role;
	return ret;
}

static inline void ci_role_stop(struct ci_hdrc *ci)
{
	enum ci_role role = ci->role;

	if (role == CI_ROLE_END)
		return;

	ci->role = CI_ROLE_END;

	ci->roles[role]->stop(ci);
}

/**
 * hw_read: reads from a hw register
 * @reg:  register index
 * @mask: bitfield mask
 *
 * This function returns register contents
 */
static inline u32 hw_read(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask)
{
	return ioread32(ci->hw_bank.regmap[reg]) & mask;
}

#ifdef CONFIG_SOC_IMX28
static inline void imx28_ci_writel(u32 val, volatile void __iomem *addr)
{
	__asm__ ("swp %0, %0, [%1]" : : "r"(val), "r"(addr));
}
#else
static inline void imx28_ci_writel(u32 val, volatile void __iomem *addr)
{
}
#endif

static inline void __hw_write(struct ci_hdrc *ci, u32 val,
		void __iomem *addr)
{
	if (ci->imx28_write_fix)
		imx28_ci_writel(val, addr);
	else
		iowrite32(val, addr);
}

/**
 * hw_write: writes to a hw register
 * @reg:  register index
 * @mask: bitfield mask
 * @data: new value
 */
static inline void hw_write(struct ci_hdrc *ci, enum ci_hw_regs reg,
			    u32 mask, u32 data)
{
	if (~mask)
		data = (ioread32(ci->hw_bank.regmap[reg]) & ~mask)
			| (data & mask);

	__hw_write(ci, data, ci->hw_bank.regmap[reg]);
}

/**
 * hw_test_and_clear: tests & clears a hw register
 * @reg:  register index
 * @mask: bitfield mask
 *
 * This function returns register contents
 */
static inline u32 hw_test_and_clear(struct ci_hdrc *ci, enum ci_hw_regs reg,
				    u32 mask)
{
	u32 val = ioread32(ci->hw_bank.regmap[reg]) & mask;

	__hw_write(ci, val, ci->hw_bank.regmap[reg]);
	return val;
}

/**
 * hw_test_and_write: tests & writes a hw register
 * @reg:  register index
 * @mask: bitfield mask
 * @data: new value
 *
 * This function returns register contents
 */
static inline u32 hw_test_and_write(struct ci_hdrc *ci, enum ci_hw_regs reg,
				    u32 mask, u32 data)
{
	u32 val = hw_read(ci, reg, ~0);

	hw_write(ci, reg, mask, data);
	return (val & mask) >> __ffs(mask);
}

int hw_device_reset(struct ci_hdrc *ci, u32 mode);

int hw_port_test_set(struct ci_hdrc *ci, u8 mode);

u8 hw_port_test_get(struct ci_hdrc *ci);

int hw_wait_reg(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask,
				u32 value, unsigned int timeout_ms);

#endif	/* __DRIVERS_USB_CHIPIDEA_CI_H */
Commit	Line	Data
e443b333 AS	1	/*
	2	* ci.h - common structures, functions, and macros of the ChipIdea driver
	3	*
	4	* Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
	5	*
	6	* Author: David Lopo
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*/
	12
	13	#ifndef __DRIVERS_USB_CHIPIDEA_CI_H
	14	#define __DRIVERS_USB_CHIPIDEA_CI_H
	15
	16	#include <linux/list.h>
5f36e231	17	#include <linux/irqreturn.h>
eb70e5ab	18	#include <linux/usb.h>
e443b333 AS	19	#include <linux/usb/gadget.h>
	20
	21	/******************************************************************************
	22	* DEFINE
	23	*****************************************************************************/
b983e51a	24	#define TD_PAGE_COUNT 5
8e22978c	25	#define CI_HDRC_PAGE_SIZE 4096ul /* page size for TD's */
e443b333 AS	26	#define ENDPT_MAX 32
e443b333 AS	27
21395a1a MKB	28	/******************************************************************************
	29	* REGISTERS
	30	*****************************************************************************/
	31	/* register indices */
	32	enum ci_hw_regs {
	33	CAP_CAPLENGTH,
	34	CAP_HCCPARAMS,
	35	CAP_DCCPARAMS,
	36	CAP_TESTMODE,
	37	CAP_LAST = CAP_TESTMODE,
	38	OP_USBCMD,
	39	OP_USBSTS,
	40	OP_USBINTR,
	41	OP_DEVICEADDR,
	42	OP_ENDPTLISTADDR,
	43	OP_PORTSC,
	44	OP_DEVLC,
	45	OP_OTGSC,
	46	OP_USBMODE,
	47	OP_ENDPTSETUPSTAT,
	48	OP_ENDPTPRIME,
	49	OP_ENDPTFLUSH,
	50	OP_ENDPTSTAT,
	51	OP_ENDPTCOMPLETE,
	52	OP_ENDPTCTRL,
	53	/* endptctrl1..15 follow */
	54	OP_LAST = OP_ENDPTCTRL + ENDPT_MAX / 2,
	55	};
	56
e443b333 AS	57	/******************************************************************************
	58	* STRUCTURES
	59	*****************************************************************************/
551a8ac6	60	/**
8e22978c	61	* struct ci_hw_ep - endpoint representation
551a8ac6 AS	62	* @ep: endpoint structure for gadget drivers
	63	* @dir: endpoint direction (TX/RX)
	64	* @num: endpoint number
	65	* @type: endpoint type
	66	* @name: string description of the endpoint
	67	* @qh: queue head for this endpoint
	68	* @wedge: is the endpoint wedged
26c696c6	69	* @ci: pointer to the controller
551a8ac6	70	* @lock: pointer to controller's spinlock
551a8ac6 AS	71	* @td_pool: pointer to controller's TD pool
551a8ac6 AS	72	*/
8e22978c	73	struct ci_hw_ep {
551a8ac6 AS	74	struct usb_ep ep;
	75	u8 dir;
	76	u8 num;
	77	u8 type;
	78	char name[16];
e443b333	79	struct {
551a8ac6	80	struct list_head queue;
8e22978c	81	struct ci_hw_qh *ptr;
551a8ac6 AS	82	dma_addr_t dma;
	83	} qh;
	84	int wedge;
e443b333 AS	85
e443b333 AS	86	/* global resources */
8e22978c	87	struct ci_hdrc *ci;
551a8ac6	88	spinlock_t *lock;
551a8ac6	89	struct dma_pool *td_pool;
2e270412	90	struct td_node *pending_td;
e443b333 AS	91	};
e443b333 AS	92
5f36e231 AS	93	enum ci_role {
	94	CI_ROLE_HOST = 0,
	95	CI_ROLE_GADGET,
	96	CI_ROLE_END,
	97	};
	98
	99	/**
	100	* struct ci_role_driver - host/gadget role driver
	101	* start: start this role
	102	* stop: stop this role
	103	* irq: irq handler for this role
	104	* name: role name string (host/gadget)
	105	*/
	106	struct ci_role_driver {
8e22978c AS	107	int (start)(struct ci_hdrc );
	108	void (stop)(struct ci_hdrc );
	109	irqreturn_t (irq)(struct ci_hdrc );
5f36e231 AS	110	const char *name;
	111	};
	112
551a8ac6 AS	113	/**
	114	* struct hw_bank - hardware register mapping representation
	115	* @lpm: set if the device is LPM capable
eb70e5ab	116	* @phys: physical address of the controller's registers
551a8ac6 AS	117	* @abs: absolute address of the beginning of register window
	118	* @cap: capability registers
	119	* @op: operational registers
	120	* @size: size of the register window
	121	* @regmap: register lookup table
	122	*/
e443b333	123	struct hw_bank {
551a8ac6	124	unsigned lpm;
eb70e5ab	125	resource_size_t phys;
551a8ac6 AS	126	void __iomem *abs;
	127	void __iomem *cap;
	128	void __iomem *op;
	129	size_t size;
21395a1a	130	void __iomem *regmap[OP_LAST + 1];
e443b333 AS	131	};
e443b333 AS	132
551a8ac6	133	/**
8e22978c	134	* struct ci_hdrc - chipidea device representation
551a8ac6 AS	135	* @dev: pointer to parent device
	136	* @lock: access synchronization
	137	* @hw_bank: hardware register mapping
	138	* @irq: IRQ number
	139	* @roles: array of supported roles for this controller
	140	* @role: current role
	141	* @is_otg: if the device is otg-capable
	142	* @work: work for role changing
	143	* @wq: workqueue thread
	144	* @qh_pool: allocation pool for queue heads
	145	* @td_pool: allocation pool for transfer descriptors
	146	* @gadget: device side representation for peripheral controller
	147	* @driver: gadget driver
	148	* @hw_ep_max: total number of endpoints supported by hardware
8e22978c	149	* @ci_hw_ep: array of endpoints
551a8ac6 AS	150	* @ep0_dir: ep0 direction
	151	* @ep0out: pointer to ep0 OUT endpoint
	152	* @ep0in: pointer to ep0 IN endpoint
	153	* @status: ep0 status request
	154	* @setaddr: if we should set the address on status completion
	155	* @address: usb address received from the host
	156	* @remote_wakeup: host-enabled remote wakeup
	157	* @suspended: suspended by host
	158	* @test_mode: the selected test mode
77c4400f	159	* @platdata: platform specific information supplied by parent device
551a8ac6 AS	160	* @vbus_active: is VBUS active
551a8ac6 AS	161	* @transceiver: pointer to USB PHY, if any
eb70e5ab	162	* @hcd: pointer to usb_hcd for ehci host driver
2d651289	163	* @debugfs: root dentry for this controller in debugfs
a107f8c5 PC	164	* @id_event: indicates there is an id event, and handled at ci_otg_work
	165	* @b_sess_valid_event: indicates there is a vbus event, and handled
	166	* at ci_otg_work
ed8f8318	167	* @imx28_write_fix: Freescale imx28 needs swp instruction for writing
551a8ac6	168	*/
8e22978c	169	struct ci_hdrc {
551a8ac6 AS	170	struct device *dev;
	171	spinlock_t lock;
	172	struct hw_bank hw_bank;
	173	int irq;
	174	struct ci_role_driver *roles[CI_ROLE_END];
	175	enum ci_role role;
	176	bool is_otg;
	177	struct work_struct work;
	178	struct workqueue_struct *wq;
	179
	180	struct dma_pool *qh_pool;
	181	struct dma_pool *td_pool;
	182
	183	struct usb_gadget gadget;
	184	struct usb_gadget_driver *driver;
	185	unsigned hw_ep_max;
8e22978c	186	struct ci_hw_ep ci_hw_ep[ENDPT_MAX];
551a8ac6	187	u32 ep0_dir;
8e22978c	188	struct ci_hw_ep ep0out, ep0in;
551a8ac6 AS	189
	190	struct usb_request *status;
	191	bool setaddr;
	192	u8 address;
	193	u8 remote_wakeup;
	194	u8 suspended;
	195	u8 test_mode;
	196
8e22978c	197	struct ci_hdrc_platform_data *platdata;
551a8ac6	198	int vbus_active;
a2c3d690 RZ	199	/* FIXME: some day, we'll not use global phy */
a2c3d690 RZ	200	bool global_phy;
551a8ac6	201	struct usb_phy *transceiver;
eb70e5ab	202	struct usb_hcd *hcd;
2d651289	203	struct dentry *debugfs;
a107f8c5 PC	204	bool id_event;
a107f8c5 PC	205	bool b_sess_valid_event;
ed8f8318	206	bool imx28_write_fix;
e443b333 AS	207	};
e443b333 AS	208
8e22978c	209	static inline struct ci_role_driver ci_role(struct ci_hdrc ci)
5f36e231 AS	210	{
	211	BUG_ON(ci->role >= CI_ROLE_END \|\| !ci->roles[ci->role]);
	212	return ci->roles[ci->role];
	213	}
	214
8e22978c	215	static inline int ci_role_start(struct ci_hdrc *ci, enum ci_role role)
5f36e231 AS	216	{
	217	int ret;
	218
	219	if (role >= CI_ROLE_END)
	220	return -EINVAL;
	221
	222	if (!ci->roles[role])
	223	return -ENXIO;
	224
	225	ret = ci->roles[role]->start(ci);
	226	if (!ret)
	227	ci->role = role;
	228	return ret;
	229	}
	230
8e22978c	231	static inline void ci_role_stop(struct ci_hdrc *ci)
5f36e231 AS	232	{
	233	enum ci_role role = ci->role;
	234
	235	if (role == CI_ROLE_END)
	236	return;
	237
	238	ci->role = CI_ROLE_END;
	239
	240	ci->roles[role]->stop(ci);
	241	}
	242
e443b333 AS	243	/**
	244	* hw_read: reads from a hw register
	245	* @reg: register index
	246	* @mask: bitfield mask
	247	*
	248	* This function returns register contents
	249	*/
8e22978c	250	static inline u32 hw_read(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask)
e443b333	251	{
26c696c6	252	return ioread32(ci->hw_bank.regmap[reg]) & mask;
e443b333 AS	253	}
e443b333 AS	254
ed8f8318 PC	255	#ifdef CONFIG_SOC_IMX28
	256	static inline void imx28_ci_writel(u32 val, volatile void __iomem *addr)
	257	{
	258	__asm__ ("swp %0, %0, [%1]" : : "r"(val), "r"(addr));
	259	}
	260	#else
	261	static inline void imx28_ci_writel(u32 val, volatile void __iomem *addr)
	262	{
	263	}
	264	#endif
	265
	266	static inline void __hw_write(struct ci_hdrc *ci, u32 val,
	267	void __iomem *addr)
	268	{
	269	if (ci->imx28_write_fix)
	270	imx28_ci_writel(val, addr);
	271	else
	272	iowrite32(val, addr);
	273	}
	274
e443b333 AS	275	/**
	276	* hw_write: writes to a hw register
	277	* @reg: register index
	278	* @mask: bitfield mask
	279	* @data: new value
	280	*/
8e22978c	281	static inline void hw_write(struct ci_hdrc *ci, enum ci_hw_regs reg,
e443b333 AS	282	u32 mask, u32 data)
	283	{
	284	if (~mask)
26c696c6	285	data = (ioread32(ci->hw_bank.regmap[reg]) & ~mask)
e443b333 AS	286	\| (data & mask);
e443b333 AS	287
ed8f8318	288	__hw_write(ci, data, ci->hw_bank.regmap[reg]);
e443b333 AS	289	}
	290
	291	/**
	292	* hw_test_and_clear: tests & clears a hw register
	293	* @reg: register index
	294	* @mask: bitfield mask
	295	*
	296	* This function returns register contents
	297	*/
8e22978c	298	static inline u32 hw_test_and_clear(struct ci_hdrc *ci, enum ci_hw_regs reg,
e443b333 AS	299	u32 mask)
e443b333 AS	300	{
26c696c6	301	u32 val = ioread32(ci->hw_bank.regmap[reg]) & mask;
e443b333	302
ed8f8318	303	__hw_write(ci, val, ci->hw_bank.regmap[reg]);
e443b333 AS	304	return val;
	305	}
	306
	307	/**
	308	* hw_test_and_write: tests & writes a hw register
	309	* @reg: register index
	310	* @mask: bitfield mask
	311	* @data: new value
	312	*
	313	* This function returns register contents
	314	*/
8e22978c	315	static inline u32 hw_test_and_write(struct ci_hdrc *ci, enum ci_hw_regs reg,
e443b333 AS	316	u32 mask, u32 data)
e443b333 AS	317	{
26c696c6	318	u32 val = hw_read(ci, reg, ~0);
e443b333	319
26c696c6	320	hw_write(ci, reg, mask, data);
727b4ddb	321	return (val & mask) >> __ffs(mask);
e443b333 AS	322	}
e443b333 AS	323
8e22978c	324	int hw_device_reset(struct ci_hdrc *ci, u32 mode);
e443b333	325
8e22978c	326	int hw_port_test_set(struct ci_hdrc *ci, u8 mode);
e443b333	327
8e22978c	328	u8 hw_port_test_get(struct ci_hdrc *ci);
e443b333	329
22fa8445 PC	330	int hw_wait_reg(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask,
	331	u32 value, unsigned int timeout_ms);
	332
e443b333	333	#endif /* __DRIVERS_USB_CHIPIDEA_CI_H */