[linux-block.git] / drivers / usb / chipidea / ci.h

/* SPDX-License-Identifier: GPL-2.0 */
/*
 * ci.h - common structures, functions, and macros of the ChipIdea driver
 *
 * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
 *
 * Author: David Lopo
 */

#ifndef __DRIVERS_USB_CHIPIDEA_CI_H
#define __DRIVERS_USB_CHIPIDEA_CI_H

#include <linux/list.h>
#include <linux/irqreturn.h>
#include <linux/usb.h>
#include <linux/usb/gadget.h>
#include <linux/usb/otg-fsm.h>
#include <linux/usb/otg.h>
#include <linux/usb/role.h>
#include <linux/ulpi/interface.h>

/******************************************************************************
 * DEFINE
 *****************************************************************************/
#define TD_PAGE_COUNT      5
#define CI_HDRC_PAGE_SIZE  4096ul /* page size for TD's */
#define ENDPT_MAX          32
#define CI_MAX_BUF_SIZE	(TD_PAGE_COUNT * CI_HDRC_PAGE_SIZE)

/******************************************************************************
 * REGISTERS
 *****************************************************************************/
/* Identification Registers */
#define ID_ID				0x0
#define ID_HWGENERAL			0x4
#define ID_HWHOST			0x8
#define ID_HWDEVICE			0xc
#define ID_HWTXBUF			0x10
#define ID_HWRXBUF			0x14
#define ID_SBUSCFG			0x90

/* register indices */
enum ci_hw_regs {
	CAP_CAPLENGTH,
	CAP_HCCPARAMS,
	CAP_DCCPARAMS,
	CAP_TESTMODE,
	CAP_LAST = CAP_TESTMODE,
	OP_USBCMD,
	OP_USBSTS,
	OP_USBINTR,
	OP_FRINDEX,
	OP_DEVICEADDR,
	OP_ENDPTLISTADDR,
	OP_TTCTRL,
	OP_BURSTSIZE,
	OP_ULPI_VIEWPORT,
	OP_PORTSC,
	OP_DEVLC,
	OP_OTGSC,
	OP_USBMODE,
	OP_ENDPTSETUPSTAT,
	OP_ENDPTPRIME,
	OP_ENDPTFLUSH,
	OP_ENDPTSTAT,
	OP_ENDPTCOMPLETE,
	OP_ENDPTCTRL,
	/* endptctrl1..15 follow */
	OP_LAST = OP_ENDPTCTRL + ENDPT_MAX / 2,
};

/******************************************************************************
 * STRUCTURES
 *****************************************************************************/
/**
 * struct ci_hw_ep - endpoint representation
 * @ep: endpoint structure for gadget drivers
 * @dir: endpoint direction (TX/RX)
 * @num: endpoint number
 * @type: endpoint type
 * @name: string description of the endpoint
 * @qh: queue head for this endpoint
 * @wedge: is the endpoint wedged
 * @ci: pointer to the controller
 * @lock: pointer to controller's spinlock
 * @td_pool: pointer to controller's TD pool
 */
struct ci_hw_ep {
	struct usb_ep				ep;
	u8					dir;
	u8					num;
	u8					type;
	char					name[16];
	struct {
		struct list_head	queue;
		struct ci_hw_qh		*ptr;
		dma_addr_t		dma;
	}					qh;
	int					wedge;

	/* global resources */
	struct ci_hdrc				*ci;
	spinlock_t				*lock;
	struct dma_pool				*td_pool;
	struct td_node				*pending_td;
};

enum ci_role {
	CI_ROLE_HOST = 0,
	CI_ROLE_GADGET,
	CI_ROLE_END,
};

enum ci_revision {
	CI_REVISION_1X = 10,	/* Revision 1.x */
	CI_REVISION_20 = 20, /* Revision 2.0 */
	CI_REVISION_21, /* Revision 2.1 */
	CI_REVISION_22, /* Revision 2.2 */
	CI_REVISION_23, /* Revision 2.3 */
	CI_REVISION_24, /* Revision 2.4 */
	CI_REVISION_25, /* Revision 2.5 */
	CI_REVISION_25_PLUS, /* Revision above than 2.5 */
	CI_REVISION_UNKNOWN = 99, /* Unknown Revision */
};

/**
 * struct ci_role_driver - host/gadget role driver
 * @start: start this role
 * @stop: stop this role
 * @suspend: system suspend handler for this role
 * @resume: system resume handler for this role
 * @irq: irq handler for this role
 * @name: role name string (host/gadget)
 */
struct ci_role_driver {
	int		(*start)(struct ci_hdrc *);
	void		(*stop)(struct ci_hdrc *);
	void		(*suspend)(struct ci_hdrc *ci);
	void		(*resume)(struct ci_hdrc *ci, bool power_lost);
	irqreturn_t	(*irq)(struct ci_hdrc *);
	const char	*name;
};

/**
 * struct hw_bank - hardware register mapping representation
 * @lpm: set if the device is LPM capable
 * @phys: physical address of the controller's registers
 * @abs: absolute address of the beginning of register window
 * @cap: capability registers
 * @op: operational registers
 * @size: size of the register window
 * @regmap: register lookup table
 */
struct hw_bank {
	unsigned	lpm;
	resource_size_t	phys;
	void __iomem	*abs;
	void __iomem	*cap;
	void __iomem	*op;
	size_t		size;
	void __iomem	*regmap[OP_LAST + 1];
};

/**
 * struct ci_hdrc - chipidea device representation
 * @dev: pointer to parent device
 * @lock: access synchronization
 * @hw_bank: hardware register mapping
 * @irq: IRQ number
 * @roles: array of supported roles for this controller
 * @role: current role
 * @is_otg: if the device is otg-capable
 * @fsm: otg finite state machine
 * @otg_fsm_hrtimer: hrtimer for otg fsm timers
 * @hr_timeouts: time out list for active otg fsm timers
 * @enabled_otg_timer_bits: bits of enabled otg timers
 * @next_otg_timer: next nearest enabled timer to be expired
 * @work: work for role changing
 * @wq: workqueue thread
 * @qh_pool: allocation pool for queue heads
 * @td_pool: allocation pool for transfer descriptors
 * @gadget: device side representation for peripheral controller
 * @driver: gadget driver
 * @resume_state: save the state of gadget suspend from
 * @hw_ep_max: total number of endpoints supported by hardware
 * @ci_hw_ep: array of endpoints
 * @ep0_dir: ep0 direction
 * @ep0out: pointer to ep0 OUT endpoint
 * @ep0in: pointer to ep0 IN endpoint
 * @status: ep0 status request
 * @setaddr: if we should set the address on status completion
 * @address: usb address received from the host
 * @remote_wakeup: host-enabled remote wakeup
 * @suspended: suspended by host
 * @test_mode: the selected test mode
 * @platdata: platform specific information supplied by parent device
 * @vbus_active: is VBUS active
 * @ulpi: pointer to ULPI device, if any
 * @ulpi_ops: ULPI read/write ops for this device
 * @phy: pointer to PHY, if any
 * @usb_phy: pointer to USB PHY, if any and if using the USB PHY framework
 * @hcd: pointer to usb_hcd for ehci host driver
 * @id_event: indicates there is an id event, and handled at ci_otg_work
 * @b_sess_valid_event: indicates there is a vbus event, and handled
 * at ci_otg_work
 * @imx28_write_fix: Freescale imx28 needs swp instruction for writing
 * @supports_runtime_pm: if runtime pm is supported
 * @in_lpm: if the core in low power mode
 * @wakeup_int: if wakeup interrupt occur
 * @rev: The revision number for controller
 * @mutex: protect code from concorrent running when doing role switch
 */
struct ci_hdrc {
	struct device			*dev;
	spinlock_t			lock;
	struct hw_bank			hw_bank;
	int				irq;
	struct ci_role_driver		*roles[CI_ROLE_END];
	enum ci_role			role;
	bool				is_otg;
	struct usb_otg			otg;
	struct otg_fsm			fsm;
	struct hrtimer			otg_fsm_hrtimer;
	ktime_t				hr_timeouts[NUM_OTG_FSM_TIMERS];
	unsigned			enabled_otg_timer_bits;
	enum otg_fsm_timer		next_otg_timer;
	struct usb_role_switch		*role_switch;
	struct work_struct		work;
	struct workqueue_struct		*wq;

	struct dma_pool			*qh_pool;
	struct dma_pool			*td_pool;

	struct usb_gadget		gadget;
	struct usb_gadget_driver	*driver;
	enum usb_device_state		resume_state;
	unsigned			hw_ep_max;
	struct ci_hw_ep			ci_hw_ep[ENDPT_MAX];
	u32				ep0_dir;
	struct ci_hw_ep			*ep0out, *ep0in;

	struct usb_request		*status;
	bool				setaddr;
	u8				address;
	u8				remote_wakeup;
	u8				suspended;
	u8				test_mode;

	struct ci_hdrc_platform_data	*platdata;
	int				vbus_active;
	struct ulpi			*ulpi;
	struct ulpi_ops 		ulpi_ops;
	struct phy			*phy;
	/* old usb_phy interface */
	struct usb_phy			*usb_phy;
	struct usb_hcd			*hcd;
	bool				id_event;
	bool				b_sess_valid_event;
	bool				imx28_write_fix;
	bool				supports_runtime_pm;
	bool				in_lpm;
	bool				wakeup_int;
	enum ci_revision		rev;
	struct mutex                    mutex;
};

static inline struct ci_role_driver *ci_role(struct ci_hdrc *ci)
{
	BUG_ON(ci->role >= CI_ROLE_END || !ci->roles[ci->role]);
	return ci->roles[ci->role];
}

static inline int ci_role_start(struct ci_hdrc *ci, enum ci_role role)
{
	int ret;

	if (role >= CI_ROLE_END)
		return -EINVAL;

	if (!ci->roles[role])
		return -ENXIO;

	ret = ci->roles[role]->start(ci);
	if (!ret)
		ci->role = role;
	return ret;
}

static inline void ci_role_stop(struct ci_hdrc *ci)
{
	enum ci_role role = ci->role;

	if (role == CI_ROLE_END)
		return;

	ci->role = CI_ROLE_END;

	ci->roles[role]->stop(ci);
}

static inline enum usb_role ci_role_to_usb_role(struct ci_hdrc *ci)
{
	if (ci->role == CI_ROLE_HOST)
		return USB_ROLE_HOST;
	else if (ci->role == CI_ROLE_GADGET && ci->vbus_active)
		return USB_ROLE_DEVICE;
	else
		return USB_ROLE_NONE;
}

static inline enum ci_role usb_role_to_ci_role(enum usb_role role)
{
	if (role == USB_ROLE_HOST)
		return CI_ROLE_HOST;
	else if (role == USB_ROLE_DEVICE)
		return CI_ROLE_GADGET;
	else
		return CI_ROLE_END;
}

/**
 * hw_read_id_reg: reads from a identification register
 * @ci: the controller
 * @offset: offset from the beginning of identification registers region
 * @mask: bitfield mask
 *
 * This function returns register contents
 */
static inline u32 hw_read_id_reg(struct ci_hdrc *ci, u32 offset, u32 mask)
{
	return ioread32(ci->hw_bank.abs + offset) & mask;
}

/**
 * hw_write_id_reg: writes to a identification register
 * @ci: the controller
 * @offset: offset from the beginning of identification registers region
 * @mask: bitfield mask
 * @data: new value
 */
static inline void hw_write_id_reg(struct ci_hdrc *ci, u32 offset,
			    u32 mask, u32 data)
{
	if (~mask)
		data = (ioread32(ci->hw_bank.abs + offset) & ~mask)
			| (data & mask);

	iowrite32(data, ci->hw_bank.abs + offset);
}

/**
 * hw_read: reads from a hw register
 * @ci: the controller
 * @reg:  register index
 * @mask: bitfield mask
 *
 * This function returns register contents
 */
static inline u32 hw_read(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask)
{
	return ioread32(ci->hw_bank.regmap[reg]) & mask;
}

#ifdef CONFIG_SOC_IMX28
static inline void imx28_ci_writel(u32 val, volatile void __iomem *addr)
{
	__asm__ ("swp %0, %0, [%1]" : : "r"(val), "r"(addr));
}
#else
static inline void imx28_ci_writel(u32 val, volatile void __iomem *addr)
{
}
#endif

static inline void __hw_write(struct ci_hdrc *ci, u32 val,
		void __iomem *addr)
{
	if (ci->imx28_write_fix)
		imx28_ci_writel(val, addr);
	else
		iowrite32(val, addr);
}

/**
 * hw_write: writes to a hw register
 * @ci: the controller
 * @reg:  register index
 * @mask: bitfield mask
 * @data: new value
 */
static inline void hw_write(struct ci_hdrc *ci, enum ci_hw_regs reg,
			    u32 mask, u32 data)
{
	if (~mask)
		data = (ioread32(ci->hw_bank.regmap[reg]) & ~mask)
			| (data & mask);

	__hw_write(ci, data, ci->hw_bank.regmap[reg]);
}

/**
 * hw_test_and_clear: tests & clears a hw register
 * @ci: the controller
 * @reg:  register index
 * @mask: bitfield mask
 *
 * This function returns register contents
 */
static inline u32 hw_test_and_clear(struct ci_hdrc *ci, enum ci_hw_regs reg,
				    u32 mask)
{
	u32 val = ioread32(ci->hw_bank.regmap[reg]) & mask;

	__hw_write(ci, val, ci->hw_bank.regmap[reg]);
	return val;
}

/**
 * hw_test_and_write: tests & writes a hw register
 * @ci: the controller
 * @reg:  register index
 * @mask: bitfield mask
 * @data: new value
 *
 * This function returns register contents
 */
static inline u32 hw_test_and_write(struct ci_hdrc *ci, enum ci_hw_regs reg,
				    u32 mask, u32 data)
{
	u32 val = hw_read(ci, reg, ~0);

	hw_write(ci, reg, mask, data);
	return (val & mask) >> __ffs(mask);
}

/**
 * ci_otg_is_fsm_mode: runtime check if otg controller
 * is in otg fsm mode.
 *
 * @ci: chipidea device
 */
static inline bool ci_otg_is_fsm_mode(struct ci_hdrc *ci)
{
#ifdef CONFIG_USB_OTG_FSM
	struct usb_otg_caps *otg_caps = &ci->platdata->ci_otg_caps;

	return ci->is_otg && ci->roles[CI_ROLE_HOST] &&
		ci->roles[CI_ROLE_GADGET] && (otg_caps->srp_support ||
		otg_caps->hnp_support || otg_caps->adp_support);
#else
	return false;
#endif
}

int ci_ulpi_init(struct ci_hdrc *ci);
void ci_ulpi_exit(struct ci_hdrc *ci);
int ci_ulpi_resume(struct ci_hdrc *ci);

u32 hw_read_intr_enable(struct ci_hdrc *ci);

u32 hw_read_intr_status(struct ci_hdrc *ci);

int hw_device_reset(struct ci_hdrc *ci);

int hw_port_test_set(struct ci_hdrc *ci, u8 mode);

u8 hw_port_test_get(struct ci_hdrc *ci);

void hw_phymode_configure(struct ci_hdrc *ci);

void ci_platform_configure(struct ci_hdrc *ci);

void dbg_create_files(struct ci_hdrc *ci);

void dbg_remove_files(struct ci_hdrc *ci);
#endif	/* __DRIVERS_USB_CHIPIDEA_CI_H */
Commit	Line	Data
d9958306	1	/* SPDX-License-Identifier: GPL-2.0 */
e443b333 AS	2	/*
	3	* ci.h - common structures, functions, and macros of the ChipIdea driver
	4	*
	5	* Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
	6	*
	7	* Author: David Lopo
e443b333 AS	8	*/
	9
	10	#ifndef __DRIVERS_USB_CHIPIDEA_CI_H
	11	#define __DRIVERS_USB_CHIPIDEA_CI_H
	12
	13	#include <linux/list.h>
5f36e231	14	#include <linux/irqreturn.h>
eb70e5ab	15	#include <linux/usb.h>
e443b333	16	#include <linux/usb/gadget.h>
57677be5	17	#include <linux/usb/otg-fsm.h>
7bb7e9b1	18	#include <linux/usb/otg.h>
05559f10	19	#include <linux/usb/role.h>
7bb7e9b1	20	#include <linux/ulpi/interface.h>
e443b333 AS	21
	22	/******************************************************************************
	23	* DEFINE
	24	*****************************************************************************/
b983e51a	25	#define TD_PAGE_COUNT 5
8e22978c	26	#define CI_HDRC_PAGE_SIZE 4096ul /* page size for TD's */
e443b333	27	#define ENDPT_MAX 32
e48aa1eb	28	#define CI_MAX_BUF_SIZE (TD_PAGE_COUNT * CI_HDRC_PAGE_SIZE)
e443b333	29
21395a1a MKB	30	/******************************************************************************
	31	* REGISTERS
	32	*****************************************************************************/
655d32e9 PC	33	/* Identification Registers */
	34	#define ID_ID 0x0
	35	#define ID_HWGENERAL 0x4
	36	#define ID_HWHOST 0x8
	37	#define ID_HWDEVICE 0xc
	38	#define ID_HWTXBUF 0x10
	39	#define ID_HWRXBUF 0x14
	40	#define ID_SBUSCFG 0x90
	41
21395a1a MKB	42	/* register indices */
	43	enum ci_hw_regs {
	44	CAP_CAPLENGTH,
	45	CAP_HCCPARAMS,
	46	CAP_DCCPARAMS,
	47	CAP_TESTMODE,
	48	CAP_LAST = CAP_TESTMODE,
	49	OP_USBCMD,
	50	OP_USBSTS,
	51	OP_USBINTR,
87091151	52	OP_FRINDEX,
21395a1a MKB	53	OP_DEVICEADDR,
21395a1a MKB	54	OP_ENDPTLISTADDR,
28362673	55	OP_TTCTRL,
96625ead	56	OP_BURSTSIZE,
7bb7e9b1	57	OP_ULPI_VIEWPORT,
21395a1a MKB	58	OP_PORTSC,
	59	OP_DEVLC,
	60	OP_OTGSC,
	61	OP_USBMODE,
	62	OP_ENDPTSETUPSTAT,
	63	OP_ENDPTPRIME,
	64	OP_ENDPTFLUSH,
	65	OP_ENDPTSTAT,
	66	OP_ENDPTCOMPLETE,
	67	OP_ENDPTCTRL,
	68	/* endptctrl1..15 follow */
	69	OP_LAST = OP_ENDPTCTRL + ENDPT_MAX / 2,
	70	};
	71
e443b333 AS	72	/******************************************************************************
	73	* STRUCTURES
	74	*****************************************************************************/
551a8ac6	75	/**
8e22978c	76	* struct ci_hw_ep - endpoint representation
551a8ac6 AS	77	* @ep: endpoint structure for gadget drivers
	78	* @dir: endpoint direction (TX/RX)
	79	* @num: endpoint number
	80	* @type: endpoint type
	81	* @name: string description of the endpoint
	82	* @qh: queue head for this endpoint
	83	* @wedge: is the endpoint wedged
26c696c6	84	* @ci: pointer to the controller
551a8ac6	85	* @lock: pointer to controller's spinlock
551a8ac6 AS	86	* @td_pool: pointer to controller's TD pool
551a8ac6 AS	87	*/
8e22978c	88	struct ci_hw_ep {
551a8ac6 AS	89	struct usb_ep ep;
	90	u8 dir;
	91	u8 num;
	92	u8 type;
	93	char name[16];
e443b333	94	struct {
551a8ac6	95	struct list_head queue;
8e22978c	96	struct ci_hw_qh *ptr;
551a8ac6 AS	97	dma_addr_t dma;
	98	} qh;
	99	int wedge;
e443b333 AS	100
e443b333 AS	101	/* global resources */
8e22978c	102	struct ci_hdrc *ci;
551a8ac6	103	spinlock_t *lock;
551a8ac6	104	struct dma_pool *td_pool;
2e270412	105	struct td_node *pending_td;
e443b333 AS	106	};
e443b333 AS	107
5f36e231 AS	108	enum ci_role {
	109	CI_ROLE_HOST = 0,
	110	CI_ROLE_GADGET,
	111	CI_ROLE_END,
	112	};
	113
cb271f3c PC	114	enum ci_revision {
	115	CI_REVISION_1X = 10, /* Revision 1.x */
	116	CI_REVISION_20 = 20, /* Revision 2.0 */
	117	CI_REVISION_21, /* Revision 2.1 */
	118	CI_REVISION_22, /* Revision 2.2 */
	119	CI_REVISION_23, /* Revision 2.3 */
	120	CI_REVISION_24, /* Revision 2.4 */
	121	CI_REVISION_25, /* Revision 2.5 */
	122	CI_REVISION_25_PLUS, /* Revision above than 2.5 */
	123	CI_REVISION_UNKNOWN = 99, /* Unknown Revision */
	124	};
	125
5f36e231 AS	126	/**
5f36e231 AS	127	* struct ci_role_driver - host/gadget role driver
19353881 PC	128	* @start: start this role
19353881 PC	129	* @stop: stop this role
450857c6 XY	130	* @suspend: system suspend handler for this role
450857c6 XY	131	* @resume: system resume handler for this role
19353881 PC	132	* @irq: irq handler for this role
19353881 PC	133	* @name: role name string (host/gadget)
5f36e231 AS	134	*/
5f36e231 AS	135	struct ci_role_driver {
8e22978c AS	136	int (start)(struct ci_hdrc );
8e22978c AS	137	void (stop)(struct ci_hdrc );
450857c6 XY	138	void (suspend)(struct ci_hdrc ci);
450857c6 XY	139	void (resume)(struct ci_hdrc ci, bool power_lost);
8e22978c	140	irqreturn_t (irq)(struct ci_hdrc );
5f36e231 AS	141	const char *name;
	142	};
	143
551a8ac6 AS	144	/**
	145	* struct hw_bank - hardware register mapping representation
	146	* @lpm: set if the device is LPM capable
eb70e5ab	147	* @phys: physical address of the controller's registers
551a8ac6 AS	148	* @abs: absolute address of the beginning of register window
	149	* @cap: capability registers
	150	* @op: operational registers
	151	* @size: size of the register window
	152	* @regmap: register lookup table
	153	*/
e443b333	154	struct hw_bank {
551a8ac6	155	unsigned lpm;
eb70e5ab	156	resource_size_t phys;
551a8ac6 AS	157	void __iomem *abs;
	158	void __iomem *cap;
	159	void __iomem *op;
	160	size_t size;
21395a1a	161	void __iomem *regmap[OP_LAST + 1];
e443b333 AS	162	};
e443b333 AS	163
551a8ac6	164	/**
8e22978c	165	* struct ci_hdrc - chipidea device representation
551a8ac6 AS	166	* @dev: pointer to parent device
	167	* @lock: access synchronization
	168	* @hw_bank: hardware register mapping
	169	* @irq: IRQ number
	170	* @roles: array of supported roles for this controller
	171	* @role: current role
	172	* @is_otg: if the device is otg-capable
57677be5	173	* @fsm: otg finite state machine
3a316ec4 LJ	174	* @otg_fsm_hrtimer: hrtimer for otg fsm timers
	175	* @hr_timeouts: time out list for active otg fsm timers
	176	* @enabled_otg_timer_bits: bits of enabled otg timers
	177	* @next_otg_timer: next nearest enabled timer to be expired
551a8ac6 AS	178	* @work: work for role changing
	179	* @wq: workqueue thread
	180	* @qh_pool: allocation pool for queue heads
	181	* @td_pool: allocation pool for transfer descriptors
	182	* @gadget: device side representation for peripheral controller
	183	* @driver: gadget driver
4f4555cf	184	* @resume_state: save the state of gadget suspend from
551a8ac6	185	* @hw_ep_max: total number of endpoints supported by hardware
8e22978c	186	* @ci_hw_ep: array of endpoints
551a8ac6 AS	187	* @ep0_dir: ep0 direction
	188	* @ep0out: pointer to ep0 OUT endpoint
	189	* @ep0in: pointer to ep0 IN endpoint
	190	* @status: ep0 status request
	191	* @setaddr: if we should set the address on status completion
	192	* @address: usb address received from the host
	193	* @remote_wakeup: host-enabled remote wakeup
	194	* @suspended: suspended by host
	195	* @test_mode: the selected test mode
77c4400f	196	* @platdata: platform specific information supplied by parent device
551a8ac6	197	* @vbus_active: is VBUS active
7bb7e9b1 SB	198	* @ulpi: pointer to ULPI device, if any
7bb7e9b1 SB	199	* @ulpi_ops: ULPI read/write ops for this device
1e5e2d3d AT	200	* @phy: pointer to PHY, if any
1e5e2d3d AT	201	* @usb_phy: pointer to USB PHY, if any and if using the USB PHY framework
eb70e5ab	202	* @hcd: pointer to usb_hcd for ehci host driver
a107f8c5 PC	203	* @id_event: indicates there is an id event, and handled at ci_otg_work
	204	* @b_sess_valid_event: indicates there is a vbus event, and handled
	205	* at ci_otg_work
ed8f8318	206	* @imx28_write_fix: Freescale imx28 needs swp instruction for writing
1f874edc PC	207	* @supports_runtime_pm: if runtime pm is supported
	208	* @in_lpm: if the core in low power mode
	209	* @wakeup_int: if wakeup interrupt occur
cb271f3c	210	* @rev: The revision number for controller
451b15ed	211	* @mutex: protect code from concorrent running when doing role switch
551a8ac6	212	*/
8e22978c	213	struct ci_hdrc {
551a8ac6 AS	214	struct device *dev;
	215	spinlock_t lock;
	216	struct hw_bank hw_bank;
	217	int irq;
	218	struct ci_role_driver *roles[CI_ROLE_END];
	219	enum ci_role role;
	220	bool is_otg;
ef44cb42	221	struct usb_otg otg;
57677be5	222	struct otg_fsm fsm;
3a316ec4 LJ	223	struct hrtimer otg_fsm_hrtimer;
	224	ktime_t hr_timeouts[NUM_OTG_FSM_TIMERS];
	225	unsigned enabled_otg_timer_bits;
	226	enum otg_fsm_timer next_otg_timer;
05559f10	227	struct usb_role_switch *role_switch;
551a8ac6 AS	228	struct work_struct work;
	229	struct workqueue_struct *wq;
	230
	231	struct dma_pool *qh_pool;
	232	struct dma_pool *td_pool;
	233
	234	struct usb_gadget gadget;
	235	struct usb_gadget_driver *driver;
4f4555cf	236	enum usb_device_state resume_state;
551a8ac6	237	unsigned hw_ep_max;
8e22978c	238	struct ci_hw_ep ci_hw_ep[ENDPT_MAX];
551a8ac6	239	u32 ep0_dir;
8e22978c	240	struct ci_hw_ep ep0out, ep0in;
551a8ac6 AS	241
	242	struct usb_request *status;
	243	bool setaddr;
	244	u8 address;
	245	u8 remote_wakeup;
	246	u8 suspended;
	247	u8 test_mode;
	248
8e22978c	249	struct ci_hdrc_platform_data *platdata;
551a8ac6	250	int vbus_active;
7bb7e9b1 SB	251	struct ulpi *ulpi;
7bb7e9b1 SB	252	struct ulpi_ops ulpi_ops;
1e5e2d3d AT	253	struct phy *phy;
1e5e2d3d AT	254	/* old usb_phy interface */
ef44cb42	255	struct usb_phy *usb_phy;
eb70e5ab	256	struct usb_hcd *hcd;
a107f8c5 PC	257	bool id_event;
a107f8c5 PC	258	bool b_sess_valid_event;
ed8f8318	259	bool imx28_write_fix;
1f874edc PC	260	bool supports_runtime_pm;
	261	bool in_lpm;
	262	bool wakeup_int;
cb271f3c	263	enum ci_revision rev;
451b15ed	264	struct mutex mutex;
e443b333 AS	265	};
e443b333 AS	266
8e22978c	267	static inline struct ci_role_driver ci_role(struct ci_hdrc ci)
5f36e231 AS	268	{
	269	BUG_ON(ci->role >= CI_ROLE_END \|\| !ci->roles[ci->role]);
	270	return ci->roles[ci->role];
	271	}
	272
8e22978c	273	static inline int ci_role_start(struct ci_hdrc *ci, enum ci_role role)
5f36e231 AS	274	{
	275	int ret;
	276
	277	if (role >= CI_ROLE_END)
	278	return -EINVAL;
	279
	280	if (!ci->roles[role])
	281	return -ENXIO;
	282
	283	ret = ci->roles[role]->start(ci);
	284	if (!ret)
	285	ci->role = role;
	286	return ret;
	287	}
	288
8e22978c	289	static inline void ci_role_stop(struct ci_hdrc *ci)
5f36e231 AS	290	{
	291	enum ci_role role = ci->role;
	292
	293	if (role == CI_ROLE_END)
	294	return;
	295
	296	ci->role = CI_ROLE_END;
	297
	298	ci->roles[role]->stop(ci);
	299	}
	300
05559f10 LJ	301	static inline enum usb_role ci_role_to_usb_role(struct ci_hdrc *ci)
	302	{
	303	if (ci->role == CI_ROLE_HOST)
	304	return USB_ROLE_HOST;
	305	else if (ci->role == CI_ROLE_GADGET && ci->vbus_active)
	306	return USB_ROLE_DEVICE;
	307	else
	308	return USB_ROLE_NONE;
	309	}
	310
27bf5be8 JL	311	static inline enum ci_role usb_role_to_ci_role(enum usb_role role)
	312	{
	313	if (role == USB_ROLE_HOST)
	314	return CI_ROLE_HOST;
	315	else if (role == USB_ROLE_DEVICE)
	316	return CI_ROLE_GADGET;
	317	else
	318	return CI_ROLE_END;
	319	}
	320
655d32e9 PC	321	/**
	322	* hw_read_id_reg: reads from a identification register
	323	* @ci: the controller
	324	* @offset: offset from the beginning of identification registers region
	325	* @mask: bitfield mask
	326	*
	327	* This function returns register contents
	328	*/
	329	static inline u32 hw_read_id_reg(struct ci_hdrc *ci, u32 offset, u32 mask)
	330	{
	331	return ioread32(ci->hw_bank.abs + offset) & mask;
	332	}
	333
	334	/**
	335	* hw_write_id_reg: writes to a identification register
	336	* @ci: the controller
	337	* @offset: offset from the beginning of identification registers region
	338	* @mask: bitfield mask
	339	* @data: new value
	340	*/
	341	static inline void hw_write_id_reg(struct ci_hdrc *ci, u32 offset,
	342	u32 mask, u32 data)
	343	{
	344	if (~mask)
	345	data = (ioread32(ci->hw_bank.abs + offset) & ~mask)
	346	\| (data & mask);
	347
	348	iowrite32(data, ci->hw_bank.abs + offset);
	349	}
	350
e443b333 AS	351	/**
e443b333 AS	352	* hw_read: reads from a hw register
19353881	353	* @ci: the controller
e443b333 AS	354	* @reg: register index
	355	* @mask: bitfield mask
	356	*
	357	* This function returns register contents
	358	*/
8e22978c	359	static inline u32 hw_read(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask)
e443b333	360	{
26c696c6	361	return ioread32(ci->hw_bank.regmap[reg]) & mask;
e443b333 AS	362	}
e443b333 AS	363
ed8f8318 PC	364	#ifdef CONFIG_SOC_IMX28
	365	static inline void imx28_ci_writel(u32 val, volatile void __iomem *addr)
	366	{
	367	__asm__ ("swp %0, %0, [%1]" : : "r"(val), "r"(addr));
	368	}
	369	#else
	370	static inline void imx28_ci_writel(u32 val, volatile void __iomem *addr)
	371	{
	372	}
	373	#endif
	374
	375	static inline void __hw_write(struct ci_hdrc *ci, u32 val,
	376	void __iomem *addr)
	377	{
	378	if (ci->imx28_write_fix)
	379	imx28_ci_writel(val, addr);
	380	else
	381	iowrite32(val, addr);
	382	}
	383
e443b333 AS	384	/**
e443b333 AS	385	* hw_write: writes to a hw register
19353881	386	* @ci: the controller
e443b333 AS	387	* @reg: register index
	388	* @mask: bitfield mask
	389	* @data: new value
	390	*/
8e22978c	391	static inline void hw_write(struct ci_hdrc *ci, enum ci_hw_regs reg,
e443b333 AS	392	u32 mask, u32 data)
	393	{
	394	if (~mask)
26c696c6	395	data = (ioread32(ci->hw_bank.regmap[reg]) & ~mask)
e443b333 AS	396	\| (data & mask);
e443b333 AS	397
ed8f8318	398	__hw_write(ci, data, ci->hw_bank.regmap[reg]);
e443b333 AS	399	}
	400
	401	/**
	402	* hw_test_and_clear: tests & clears a hw register
19353881	403	* @ci: the controller
e443b333 AS	404	* @reg: register index
	405	* @mask: bitfield mask
	406	*
	407	* This function returns register contents
	408	*/
8e22978c	409	static inline u32 hw_test_and_clear(struct ci_hdrc *ci, enum ci_hw_regs reg,
e443b333 AS	410	u32 mask)
e443b333 AS	411	{
26c696c6	412	u32 val = ioread32(ci->hw_bank.regmap[reg]) & mask;
e443b333	413
ed8f8318	414	__hw_write(ci, val, ci->hw_bank.regmap[reg]);
e443b333 AS	415	return val;
	416	}
	417
	418	/**
	419	* hw_test_and_write: tests & writes a hw register
19353881	420	* @ci: the controller
e443b333 AS	421	* @reg: register index
	422	* @mask: bitfield mask
	423	* @data: new value
	424	*
	425	* This function returns register contents
	426	*/
8e22978c	427	static inline u32 hw_test_and_write(struct ci_hdrc *ci, enum ci_hw_regs reg,
e443b333 AS	428	u32 mask, u32 data)
e443b333 AS	429	{
26c696c6	430	u32 val = hw_read(ci, reg, ~0);
e443b333	431
26c696c6	432	hw_write(ci, reg, mask, data);
727b4ddb	433	return (val & mask) >> __ffs(mask);
e443b333 AS	434	}
e443b333 AS	435
57677be5 LJ	436	/**
	437	* ci_otg_is_fsm_mode: runtime check if otg controller
	438	* is in otg fsm mode.
19353881 PC	439	*
19353881 PC	440	* @ci: chipidea device
57677be5 LJ	441	*/
	442	static inline bool ci_otg_is_fsm_mode(struct ci_hdrc *ci)
	443	{
	444	#ifdef CONFIG_USB_OTG_FSM
b0930d4c LJ	445	struct usb_otg_caps *otg_caps = &ci->platdata->ci_otg_caps;
b0930d4c LJ	446
57677be5	447	return ci->is_otg && ci->roles[CI_ROLE_HOST] &&
b0930d4c LJ	448	ci->roles[CI_ROLE_GADGET] && (otg_caps->srp_support \|\|
b0930d4c LJ	449	otg_caps->hnp_support \|\| otg_caps->adp_support);
57677be5 LJ	450	#else
	451	return false;
	452	#endif
	453	}
	454
7bb7e9b1 SB	455	int ci_ulpi_init(struct ci_hdrc *ci);
	456	void ci_ulpi_exit(struct ci_hdrc *ci);
	457	int ci_ulpi_resume(struct ci_hdrc *ci);
7bb7e9b1	458
36304b06 LJ	459	u32 hw_read_intr_enable(struct ci_hdrc *ci);
	460
	461	u32 hw_read_intr_status(struct ci_hdrc *ci);
	462
5b157300	463	int hw_device_reset(struct ci_hdrc *ci);
e443b333	464
8e22978c	465	int hw_port_test_set(struct ci_hdrc *ci, u8 mode);
e443b333	466
8e22978c	467	u8 hw_port_test_get(struct ci_hdrc *ci);
e443b333	468
7bb7e9b1 SB	469	void hw_phymode_configure(struct ci_hdrc *ci);
7bb7e9b1 SB	470
bf9c85e7 PC	471	void ci_platform_configure(struct ci_hdrc *ci);
bf9c85e7 PC	472
a61b75d1	473	void dbg_create_files(struct ci_hdrc *ci);
9d8c850d PC	474
9d8c850d PC	475	void dbg_remove_files(struct ci_hdrc *ci);
e443b333	476	#endif /* __DRIVERS_USB_CHIPIDEA_CI_H */