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3d829045 PL |
1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* | |
3 | * Cadence CDNSP DRD Driver. | |
4 | * | |
5 | * Copyright (C) 2020 Cadence. | |
6 | * | |
7 | * Author: Pawel Laszczak <pawell@cadence.com> | |
8 | * | |
9 | */ | |
10 | ||
11 | #include <linux/moduleparam.h> | |
12 | #include <linux/dma-mapping.h> | |
13 | #include <linux/module.h> | |
14 | #include <linux/iopoll.h> | |
15 | #include <linux/delay.h> | |
16 | #include <linux/log2.h> | |
17 | #include <linux/slab.h> | |
18 | #include <linux/pci.h> | |
19 | #include <linux/irq.h> | |
20 | #include <linux/dmi.h> | |
21 | ||
22 | #include "core.h" | |
23 | #include "gadget-export.h" | |
24 | #include "drd.h" | |
25 | #include "cdnsp-gadget.h" | |
118b2a32 | 26 | #include "cdnsp-trace.h" |
3d829045 PL |
27 | |
28 | unsigned int cdnsp_port_speed(unsigned int port_status) | |
29 | { | |
30 | /*Detect gadget speed based on PORTSC register*/ | |
31 | if (DEV_SUPERSPEEDPLUS(port_status)) | |
32 | return USB_SPEED_SUPER_PLUS; | |
33 | else if (DEV_SUPERSPEED(port_status)) | |
34 | return USB_SPEED_SUPER; | |
35 | else if (DEV_HIGHSPEED(port_status)) | |
36 | return USB_SPEED_HIGH; | |
37 | else if (DEV_FULLSPEED(port_status)) | |
38 | return USB_SPEED_FULL; | |
39 | ||
40 | /* If device is detached then speed will be USB_SPEED_UNKNOWN.*/ | |
41 | return USB_SPEED_UNKNOWN; | |
42 | } | |
43 | ||
44 | /* | |
45 | * Given a port state, this function returns a value that would result in the | |
46 | * port being in the same state, if the value was written to the port status | |
47 | * control register. | |
48 | * Save Read Only (RO) bits and save read/write bits where | |
49 | * writing a 0 clears the bit and writing a 1 sets the bit (RWS). | |
50 | * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect. | |
51 | */ | |
52 | u32 cdnsp_port_state_to_neutral(u32 state) | |
53 | { | |
54 | /* Save read-only status and port state. */ | |
55 | return (state & CDNSP_PORT_RO) | (state & CDNSP_PORT_RWS); | |
56 | } | |
57 | ||
58 | /** | |
59 | * Find the offset of the extended capabilities with capability ID id. | |
60 | * @base: PCI MMIO registers base address. | |
61 | * @start: Address at which to start looking, (0 or HCC_PARAMS to start at | |
62 | * beginning of list) | |
63 | * @id: Extended capability ID to search for. | |
64 | * | |
65 | * Returns the offset of the next matching extended capability structure. | |
66 | * Some capabilities can occur several times, | |
67 | * e.g., the EXT_CAPS_PROTOCOL, and this provides a way to find them all. | |
68 | */ | |
69 | int cdnsp_find_next_ext_cap(void __iomem *base, u32 start, int id) | |
70 | { | |
71 | u32 offset = start; | |
72 | u32 next; | |
73 | u32 val; | |
74 | ||
75 | if (!start || start == HCC_PARAMS_OFFSET) { | |
76 | val = readl(base + HCC_PARAMS_OFFSET); | |
77 | if (val == ~0) | |
78 | return 0; | |
79 | ||
80 | offset = HCC_EXT_CAPS(val) << 2; | |
81 | if (!offset) | |
82 | return 0; | |
83 | }; | |
84 | ||
85 | do { | |
86 | val = readl(base + offset); | |
87 | if (val == ~0) | |
88 | return 0; | |
89 | ||
90 | if (EXT_CAPS_ID(val) == id && offset != start) | |
91 | return offset; | |
92 | ||
93 | next = EXT_CAPS_NEXT(val); | |
94 | offset += next << 2; | |
95 | } while (next); | |
96 | ||
97 | return 0; | |
98 | } | |
99 | ||
100 | void cdnsp_set_link_state(struct cdnsp_device *pdev, | |
101 | __le32 __iomem *port_regs, | |
102 | u32 link_state) | |
103 | { | |
118b2a32 | 104 | int port_num = 0xFF; |
3d829045 PL |
105 | u32 temp; |
106 | ||
107 | temp = readl(port_regs); | |
108 | temp = cdnsp_port_state_to_neutral(temp); | |
109 | temp |= PORT_WKCONN_E | PORT_WKDISC_E; | |
110 | writel(temp, port_regs); | |
111 | ||
112 | temp &= ~PORT_PLS_MASK; | |
113 | temp |= PORT_LINK_STROBE | link_state; | |
114 | ||
118b2a32 PL |
115 | if (pdev->active_port) |
116 | port_num = pdev->active_port->port_num; | |
117 | ||
118 | trace_cdnsp_handle_port_status(port_num, readl(port_regs)); | |
3d829045 | 119 | writel(temp, port_regs); |
118b2a32 | 120 | trace_cdnsp_link_state_changed(port_num, readl(port_regs)); |
3d829045 PL |
121 | } |
122 | ||
123 | static void cdnsp_disable_port(struct cdnsp_device *pdev, | |
124 | __le32 __iomem *port_regs) | |
125 | { | |
126 | u32 temp = cdnsp_port_state_to_neutral(readl(port_regs)); | |
127 | ||
128 | writel(temp | PORT_PED, port_regs); | |
129 | } | |
130 | ||
131 | static void cdnsp_clear_port_change_bit(struct cdnsp_device *pdev, | |
132 | __le32 __iomem *port_regs) | |
133 | { | |
134 | u32 portsc = readl(port_regs); | |
135 | ||
136 | writel(cdnsp_port_state_to_neutral(portsc) | | |
137 | (portsc & PORT_CHANGE_BITS), port_regs); | |
138 | } | |
139 | ||
140 | static void cdnsp_set_chicken_bits_2(struct cdnsp_device *pdev, u32 bit) | |
141 | { | |
142 | __le32 __iomem *reg; | |
143 | void __iomem *base; | |
144 | u32 offset = 0; | |
145 | ||
146 | base = &pdev->cap_regs->hc_capbase; | |
147 | offset = cdnsp_find_next_ext_cap(base, offset, D_XEC_PRE_REGS_CAP); | |
148 | reg = base + offset + REG_CHICKEN_BITS_2_OFFSET; | |
149 | ||
150 | bit = readl(reg) | bit; | |
151 | writel(bit, reg); | |
152 | } | |
153 | ||
154 | static void cdnsp_clear_chicken_bits_2(struct cdnsp_device *pdev, u32 bit) | |
155 | { | |
156 | __le32 __iomem *reg; | |
157 | void __iomem *base; | |
158 | u32 offset = 0; | |
159 | ||
160 | base = &pdev->cap_regs->hc_capbase; | |
161 | offset = cdnsp_find_next_ext_cap(base, offset, D_XEC_PRE_REGS_CAP); | |
162 | reg = base + offset + REG_CHICKEN_BITS_2_OFFSET; | |
163 | ||
164 | bit = readl(reg) & ~bit; | |
165 | writel(bit, reg); | |
166 | } | |
167 | ||
168 | /* | |
169 | * Disable interrupts and begin the controller halting process. | |
170 | */ | |
171 | static void cdnsp_quiesce(struct cdnsp_device *pdev) | |
172 | { | |
173 | u32 halted; | |
174 | u32 mask; | |
175 | u32 cmd; | |
176 | ||
177 | mask = ~(u32)(CDNSP_IRQS); | |
178 | ||
179 | halted = readl(&pdev->op_regs->status) & STS_HALT; | |
180 | if (!halted) | |
181 | mask &= ~(CMD_R_S | CMD_DEVEN); | |
182 | ||
183 | cmd = readl(&pdev->op_regs->command); | |
184 | cmd &= mask; | |
185 | writel(cmd, &pdev->op_regs->command); | |
186 | } | |
187 | ||
188 | /* | |
189 | * Force controller into halt state. | |
190 | * | |
191 | * Disable any IRQs and clear the run/stop bit. | |
192 | * Controller will complete any current and actively pipelined transactions, and | |
193 | * should halt within 16 ms of the run/stop bit being cleared. | |
194 | * Read controller Halted bit in the status register to see when the | |
195 | * controller is finished. | |
196 | */ | |
197 | int cdnsp_halt(struct cdnsp_device *pdev) | |
198 | { | |
199 | int ret; | |
200 | u32 val; | |
201 | ||
202 | cdnsp_quiesce(pdev); | |
203 | ||
204 | ret = readl_poll_timeout_atomic(&pdev->op_regs->status, val, | |
205 | val & STS_HALT, 1, | |
206 | CDNSP_MAX_HALT_USEC); | |
207 | if (ret) { | |
208 | dev_err(pdev->dev, "ERROR: Device halt failed\n"); | |
209 | return ret; | |
210 | } | |
211 | ||
212 | pdev->cdnsp_state |= CDNSP_STATE_HALTED; | |
213 | ||
214 | return 0; | |
215 | } | |
216 | ||
217 | /* | |
218 | * device controller died, register read returns 0xffffffff, or command never | |
219 | * ends. | |
220 | */ | |
221 | void cdnsp_died(struct cdnsp_device *pdev) | |
222 | { | |
223 | dev_err(pdev->dev, "ERROR: CDNSP controller not responding\n"); | |
224 | pdev->cdnsp_state |= CDNSP_STATE_DYING; | |
225 | cdnsp_halt(pdev); | |
226 | } | |
227 | ||
228 | /* | |
229 | * Set the run bit and wait for the device to be running. | |
230 | */ | |
231 | static int cdnsp_start(struct cdnsp_device *pdev) | |
232 | { | |
233 | u32 temp; | |
234 | int ret; | |
235 | ||
236 | temp = readl(&pdev->op_regs->command); | |
237 | temp |= (CMD_R_S | CMD_DEVEN); | |
238 | writel(temp, &pdev->op_regs->command); | |
239 | ||
118b2a32 PL |
240 | trace_cdnsp_init("Turn on controller"); |
241 | ||
3d829045 PL |
242 | pdev->cdnsp_state = 0; |
243 | ||
244 | /* | |
245 | * Wait for the STS_HALT Status bit to be 0 to indicate the device is | |
246 | * running. | |
247 | */ | |
248 | ret = readl_poll_timeout_atomic(&pdev->op_regs->status, temp, | |
249 | !(temp & STS_HALT), 1, | |
250 | CDNSP_MAX_HALT_USEC); | |
251 | if (ret) { | |
252 | pdev->cdnsp_state = CDNSP_STATE_DYING; | |
253 | dev_err(pdev->dev, "ERROR: Controller run failed\n"); | |
254 | } | |
255 | ||
256 | return ret; | |
257 | } | |
258 | ||
259 | /* | |
260 | * Reset a halted controller. | |
261 | * | |
262 | * This resets pipelines, timers, counters, state machines, etc. | |
263 | * Transactions will be terminated immediately, and operational registers | |
264 | * will be set to their defaults. | |
265 | */ | |
266 | int cdnsp_reset(struct cdnsp_device *pdev) | |
267 | { | |
268 | u32 command; | |
269 | u32 temp; | |
270 | int ret; | |
271 | ||
272 | temp = readl(&pdev->op_regs->status); | |
273 | ||
274 | if (temp == ~(u32)0) { | |
275 | dev_err(pdev->dev, "Device not accessible, reset failed.\n"); | |
276 | return -ENODEV; | |
277 | } | |
278 | ||
279 | if ((temp & STS_HALT) == 0) { | |
280 | dev_err(pdev->dev, "Controller not halted, aborting reset.\n"); | |
281 | return -EINVAL; | |
282 | } | |
283 | ||
284 | command = readl(&pdev->op_regs->command); | |
285 | command |= CMD_RESET; | |
286 | writel(command, &pdev->op_regs->command); | |
287 | ||
288 | ret = readl_poll_timeout_atomic(&pdev->op_regs->command, temp, | |
289 | !(temp & CMD_RESET), 1, | |
290 | 10 * 1000); | |
291 | if (ret) { | |
292 | dev_err(pdev->dev, "ERROR: Controller reset failed\n"); | |
293 | return ret; | |
294 | } | |
295 | ||
296 | /* | |
297 | * CDNSP cannot write any doorbells or operational registers other | |
298 | * than status until the "Controller Not Ready" flag is cleared. | |
299 | */ | |
300 | ret = readl_poll_timeout_atomic(&pdev->op_regs->status, temp, | |
301 | !(temp & STS_CNR), 1, | |
302 | 10 * 1000); | |
303 | ||
304 | if (ret) { | |
305 | dev_err(pdev->dev, "ERROR: Controller not ready to work\n"); | |
306 | return ret; | |
307 | } | |
308 | ||
309 | dev_dbg(pdev->dev, "Controller ready to work"); | |
310 | ||
311 | return ret; | |
312 | } | |
313 | ||
314 | /* | |
315 | * cdnsp_get_endpoint_index - Find the index for an endpoint given its | |
316 | * descriptor.Use the return value to right shift 1 for the bitmask. | |
317 | * | |
318 | * Index = (epnum * 2) + direction - 1, | |
319 | * where direction = 0 for OUT, 1 for IN. | |
320 | * For control endpoints, the IN index is used (OUT index is unused), so | |
321 | * index = (epnum * 2) + direction - 1 = (epnum * 2) + 1 - 1 = (epnum * 2) | |
322 | */ | |
323 | static unsigned int | |
324 | cdnsp_get_endpoint_index(const struct usb_endpoint_descriptor *desc) | |
325 | { | |
326 | unsigned int index = (unsigned int)usb_endpoint_num(desc); | |
327 | ||
328 | if (usb_endpoint_xfer_control(desc)) | |
329 | return index * 2; | |
330 | ||
331 | return (index * 2) + (usb_endpoint_dir_in(desc) ? 1 : 0) - 1; | |
332 | } | |
333 | ||
334 | /* | |
335 | * Find the flag for this endpoint (for use in the control context). Use the | |
336 | * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is | |
337 | * bit 1, etc. | |
338 | */ | |
339 | static unsigned int | |
340 | cdnsp_get_endpoint_flag(const struct usb_endpoint_descriptor *desc) | |
341 | { | |
342 | return 1 << (cdnsp_get_endpoint_index(desc) + 1); | |
343 | } | |
344 | ||
345 | int cdnsp_ep_enqueue(struct cdnsp_ep *pep, struct cdnsp_request *preq) | |
346 | { | |
347 | struct cdnsp_device *pdev = pep->pdev; | |
348 | struct usb_request *request; | |
349 | int ret; | |
350 | ||
118b2a32 PL |
351 | if (preq->epnum == 0 && !list_empty(&pep->pending_list)) { |
352 | trace_cdnsp_request_enqueue_busy(preq); | |
3d829045 | 353 | return -EBUSY; |
118b2a32 | 354 | } |
3d829045 PL |
355 | |
356 | request = &preq->request; | |
357 | request->actual = 0; | |
358 | request->status = -EINPROGRESS; | |
359 | preq->direction = pep->direction; | |
360 | preq->epnum = pep->number; | |
361 | preq->td.drbl = 0; | |
362 | ||
363 | ret = usb_gadget_map_request_by_dev(pdev->dev, request, pep->direction); | |
118b2a32 PL |
364 | if (ret) { |
365 | trace_cdnsp_request_enqueue_error(preq); | |
3d829045 | 366 | return ret; |
118b2a32 | 367 | } |
3d829045 PL |
368 | |
369 | list_add_tail(&preq->list, &pep->pending_list); | |
370 | ||
118b2a32 PL |
371 | trace_cdnsp_request_enqueue(preq); |
372 | ||
3d829045 PL |
373 | switch (usb_endpoint_type(pep->endpoint.desc)) { |
374 | case USB_ENDPOINT_XFER_CONTROL: | |
375 | ret = cdnsp_queue_ctrl_tx(pdev, preq); | |
376 | break; | |
377 | case USB_ENDPOINT_XFER_BULK: | |
378 | case USB_ENDPOINT_XFER_INT: | |
379 | ret = cdnsp_queue_bulk_tx(pdev, preq); | |
380 | break; | |
381 | case USB_ENDPOINT_XFER_ISOC: | |
382 | ret = cdnsp_queue_isoc_tx_prepare(pdev, preq); | |
383 | } | |
384 | ||
385 | if (ret) | |
386 | goto unmap; | |
387 | ||
388 | return 0; | |
389 | ||
390 | unmap: | |
391 | usb_gadget_unmap_request_by_dev(pdev->dev, &preq->request, | |
392 | pep->direction); | |
393 | list_del(&preq->list); | |
118b2a32 | 394 | trace_cdnsp_request_enqueue_error(preq); |
3d829045 PL |
395 | |
396 | return ret; | |
397 | } | |
398 | ||
399 | /* | |
400 | * Remove the request's TD from the endpoint ring. This may cause the | |
401 | * controller to stop USB transfers, potentially stopping in the middle of a | |
402 | * TRB buffer. The controller should pick up where it left off in the TD, | |
403 | * unless a Set Transfer Ring Dequeue Pointer is issued. | |
404 | * | |
405 | * The TRBs that make up the buffers for the canceled request will be "removed" | |
406 | * from the ring. Since the ring is a contiguous structure, they can't be | |
407 | * physically removed. Instead, there are two options: | |
408 | * | |
409 | * 1) If the controller is in the middle of processing the request to be | |
410 | * canceled, we simply move the ring's dequeue pointer past those TRBs | |
411 | * using the Set Transfer Ring Dequeue Pointer command. This will be | |
412 | * the common case, when drivers timeout on the last submitted request | |
413 | * and attempt to cancel. | |
414 | * | |
415 | * 2) If the controller is in the middle of a different TD, we turn the TRBs | |
416 | * into a series of 1-TRB transfer no-op TDs. No-ops shouldn't be chained. | |
417 | * The controller will need to invalidate the any TRBs it has cached after | |
418 | * the stop endpoint command. | |
419 | * | |
420 | * 3) The TD may have completed by the time the Stop Endpoint Command | |
421 | * completes, so software needs to handle that case too. | |
422 | * | |
423 | */ | |
424 | int cdnsp_ep_dequeue(struct cdnsp_ep *pep, struct cdnsp_request *preq) | |
425 | { | |
426 | struct cdnsp_device *pdev = pep->pdev; | |
427 | int ret; | |
428 | ||
118b2a32 PL |
429 | trace_cdnsp_request_dequeue(preq); |
430 | ||
3d829045 PL |
431 | if (GET_EP_CTX_STATE(pep->out_ctx) == EP_STATE_RUNNING) { |
432 | ret = cdnsp_cmd_stop_ep(pdev, pep); | |
433 | if (ret) | |
434 | return ret; | |
435 | } | |
436 | ||
437 | return cdnsp_remove_request(pdev, preq, pep); | |
438 | } | |
439 | ||
440 | static void cdnsp_zero_in_ctx(struct cdnsp_device *pdev) | |
441 | { | |
442 | struct cdnsp_input_control_ctx *ctrl_ctx; | |
443 | struct cdnsp_slot_ctx *slot_ctx; | |
444 | struct cdnsp_ep_ctx *ep_ctx; | |
445 | int i; | |
446 | ||
447 | ctrl_ctx = cdnsp_get_input_control_ctx(&pdev->in_ctx); | |
448 | ||
449 | /* | |
450 | * When a device's add flag and drop flag are zero, any subsequent | |
451 | * configure endpoint command will leave that endpoint's state | |
452 | * untouched. Make sure we don't leave any old state in the input | |
453 | * endpoint contexts. | |
454 | */ | |
455 | ctrl_ctx->drop_flags = 0; | |
456 | ctrl_ctx->add_flags = 0; | |
457 | slot_ctx = cdnsp_get_slot_ctx(&pdev->in_ctx); | |
458 | slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK); | |
459 | ||
460 | /* Endpoint 0 is always valid */ | |
461 | slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1)); | |
462 | for (i = 1; i < CDNSP_ENDPOINTS_NUM; ++i) { | |
463 | ep_ctx = cdnsp_get_ep_ctx(&pdev->in_ctx, i); | |
464 | ep_ctx->ep_info = 0; | |
465 | ep_ctx->ep_info2 = 0; | |
466 | ep_ctx->deq = 0; | |
467 | ep_ctx->tx_info = 0; | |
468 | } | |
469 | } | |
470 | ||
471 | /* Issue a configure endpoint command and wait for it to finish. */ | |
472 | static int cdnsp_configure_endpoint(struct cdnsp_device *pdev) | |
473 | { | |
474 | int ret; | |
475 | ||
476 | cdnsp_queue_configure_endpoint(pdev, pdev->cmd.in_ctx->dma); | |
477 | cdnsp_ring_cmd_db(pdev); | |
478 | ret = cdnsp_wait_for_cmd_compl(pdev); | |
479 | if (ret) { | |
480 | dev_err(pdev->dev, | |
481 | "ERR: unexpected command completion code 0x%x.\n", ret); | |
482 | return -EINVAL; | |
483 | } | |
484 | ||
485 | return ret; | |
486 | } | |
487 | ||
488 | static void cdnsp_invalidate_ep_events(struct cdnsp_device *pdev, | |
489 | struct cdnsp_ep *pep) | |
490 | { | |
491 | struct cdnsp_segment *segment; | |
492 | union cdnsp_trb *event; | |
493 | u32 cycle_state; | |
494 | __le32 data; | |
495 | ||
496 | event = pdev->event_ring->dequeue; | |
497 | segment = pdev->event_ring->deq_seg; | |
498 | cycle_state = pdev->event_ring->cycle_state; | |
499 | ||
500 | while (1) { | |
501 | data = le32_to_cpu(event->trans_event.flags); | |
502 | ||
503 | /* Check the owner of the TRB. */ | |
504 | if ((data & TRB_CYCLE) != cycle_state) | |
505 | break; | |
506 | ||
507 | if (TRB_FIELD_TO_TYPE(data) == TRB_TRANSFER && | |
508 | TRB_TO_EP_ID(data) == (pep->idx + 1)) { | |
509 | data |= TRB_EVENT_INVALIDATE; | |
510 | event->trans_event.flags = cpu_to_le32(data); | |
511 | } | |
512 | ||
513 | if (cdnsp_last_trb_on_seg(segment, event)) { | |
514 | cycle_state ^= 1; | |
515 | segment = pdev->event_ring->deq_seg->next; | |
516 | event = segment->trbs; | |
517 | } else { | |
518 | event++; | |
519 | } | |
520 | } | |
521 | } | |
522 | ||
523 | int cdnsp_wait_for_cmd_compl(struct cdnsp_device *pdev) | |
524 | { | |
525 | struct cdnsp_segment *event_deq_seg; | |
526 | union cdnsp_trb *cmd_trb; | |
527 | dma_addr_t cmd_deq_dma; | |
528 | union cdnsp_trb *event; | |
529 | u32 cycle_state; | |
530 | __le32 flags; | |
531 | int ret, val; | |
532 | u64 cmd_dma; | |
533 | ||
534 | cmd_trb = pdev->cmd.command_trb; | |
535 | pdev->cmd.status = 0; | |
536 | ||
118b2a32 PL |
537 | trace_cdnsp_cmd_wait_for_compl(pdev->cmd_ring, &cmd_trb->generic); |
538 | ||
3d829045 PL |
539 | ret = readl_poll_timeout_atomic(&pdev->op_regs->cmd_ring, val, |
540 | !CMD_RING_BUSY(val), 1, | |
541 | CDNSP_CMD_TIMEOUT); | |
542 | if (ret) { | |
543 | dev_err(pdev->dev, "ERR: Timeout while waiting for command\n"); | |
118b2a32 | 544 | trace_cdnsp_cmd_timeout(pdev->cmd_ring, &cmd_trb->generic); |
3d829045 PL |
545 | pdev->cdnsp_state = CDNSP_STATE_DYING; |
546 | return -ETIMEDOUT; | |
547 | } | |
548 | ||
549 | event = pdev->event_ring->dequeue; | |
550 | event_deq_seg = pdev->event_ring->deq_seg; | |
551 | cycle_state = pdev->event_ring->cycle_state; | |
552 | ||
553 | cmd_deq_dma = cdnsp_trb_virt_to_dma(pdev->cmd_ring->deq_seg, cmd_trb); | |
554 | if (!cmd_deq_dma) | |
555 | return -EINVAL; | |
556 | ||
557 | while (1) { | |
558 | flags = le32_to_cpu(event->event_cmd.flags); | |
559 | ||
560 | /* Check the owner of the TRB. */ | |
561 | if ((flags & TRB_CYCLE) != cycle_state) | |
562 | return -EINVAL; | |
563 | ||
564 | cmd_dma = le64_to_cpu(event->event_cmd.cmd_trb); | |
565 | ||
566 | /* | |
567 | * Check whether the completion event is for last queued | |
568 | * command. | |
569 | */ | |
570 | if (TRB_FIELD_TO_TYPE(flags) != TRB_COMPLETION || | |
571 | cmd_dma != (u64)cmd_deq_dma) { | |
572 | if (!cdnsp_last_trb_on_seg(event_deq_seg, event)) { | |
573 | event++; | |
574 | continue; | |
575 | } | |
576 | ||
577 | if (cdnsp_last_trb_on_ring(pdev->event_ring, | |
578 | event_deq_seg, event)) | |
579 | cycle_state ^= 1; | |
580 | ||
581 | event_deq_seg = event_deq_seg->next; | |
582 | event = event_deq_seg->trbs; | |
583 | continue; | |
584 | } | |
585 | ||
118b2a32 PL |
586 | trace_cdnsp_handle_command(pdev->cmd_ring, &cmd_trb->generic); |
587 | ||
3d829045 PL |
588 | pdev->cmd.status = GET_COMP_CODE(le32_to_cpu(event->event_cmd.status)); |
589 | if (pdev->cmd.status == COMP_SUCCESS) | |
590 | return 0; | |
591 | ||
592 | return -pdev->cmd.status; | |
593 | } | |
594 | } | |
595 | ||
596 | int cdnsp_halt_endpoint(struct cdnsp_device *pdev, | |
597 | struct cdnsp_ep *pep, | |
598 | int value) | |
599 | { | |
600 | int ret; | |
601 | ||
118b2a32 PL |
602 | trace_cdnsp_ep_halt(value ? "Set" : "Clear"); |
603 | ||
3d829045 PL |
604 | if (value) { |
605 | ret = cdnsp_cmd_stop_ep(pdev, pep); | |
606 | if (ret) | |
607 | return ret; | |
608 | ||
609 | if (GET_EP_CTX_STATE(pep->out_ctx) == EP_STATE_STOPPED) { | |
610 | cdnsp_queue_halt_endpoint(pdev, pep->idx); | |
611 | cdnsp_ring_cmd_db(pdev); | |
612 | ret = cdnsp_wait_for_cmd_compl(pdev); | |
613 | } | |
614 | ||
615 | pep->ep_state |= EP_HALTED; | |
616 | } else { | |
617 | /* | |
618 | * In device mode driver can call reset endpoint command | |
619 | * from any endpoint state. | |
620 | */ | |
621 | cdnsp_queue_reset_ep(pdev, pep->idx); | |
622 | cdnsp_ring_cmd_db(pdev); | |
623 | ret = cdnsp_wait_for_cmd_compl(pdev); | |
118b2a32 PL |
624 | trace_cdnsp_handle_cmd_reset_ep(pep->out_ctx); |
625 | ||
3d829045 PL |
626 | if (ret) |
627 | return ret; | |
628 | ||
629 | pep->ep_state &= ~EP_HALTED; | |
630 | ||
631 | if (pep->idx != 0 && !(pep->ep_state & EP_WEDGE)) | |
632 | cdnsp_ring_doorbell_for_active_rings(pdev, pep); | |
633 | ||
634 | pep->ep_state &= ~EP_WEDGE; | |
635 | } | |
636 | ||
637 | return 0; | |
638 | } | |
639 | ||
640 | static int cdnsp_update_eps_configuration(struct cdnsp_device *pdev, | |
641 | struct cdnsp_ep *pep) | |
642 | { | |
643 | struct cdnsp_input_control_ctx *ctrl_ctx; | |
644 | struct cdnsp_slot_ctx *slot_ctx; | |
645 | int ret = 0; | |
646 | u32 ep_sts; | |
647 | int i; | |
648 | ||
649 | ctrl_ctx = cdnsp_get_input_control_ctx(&pdev->in_ctx); | |
650 | ||
651 | /* Don't issue the command if there's no endpoints to update. */ | |
652 | if (ctrl_ctx->add_flags == 0 && ctrl_ctx->drop_flags == 0) | |
653 | return 0; | |
654 | ||
655 | ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG); | |
656 | ctrl_ctx->add_flags &= cpu_to_le32(~EP0_FLAG); | |
657 | ctrl_ctx->drop_flags &= cpu_to_le32(~(SLOT_FLAG | EP0_FLAG)); | |
658 | ||
659 | /* Fix up Context Entries field. Minimum value is EP0 == BIT(1). */ | |
660 | slot_ctx = cdnsp_get_slot_ctx(&pdev->in_ctx); | |
661 | for (i = CDNSP_ENDPOINTS_NUM; i >= 1; i--) { | |
662 | __le32 le32 = cpu_to_le32(BIT(i)); | |
663 | ||
664 | if ((pdev->eps[i - 1].ring && !(ctrl_ctx->drop_flags & le32)) || | |
665 | (ctrl_ctx->add_flags & le32) || i == 1) { | |
666 | slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK); | |
667 | slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(i)); | |
668 | break; | |
669 | } | |
670 | } | |
671 | ||
672 | ep_sts = GET_EP_CTX_STATE(pep->out_ctx); | |
673 | ||
674 | if ((ctrl_ctx->add_flags != cpu_to_le32(SLOT_FLAG) && | |
675 | ep_sts == EP_STATE_DISABLED) || | |
676 | (ep_sts != EP_STATE_DISABLED && ctrl_ctx->drop_flags)) | |
677 | ret = cdnsp_configure_endpoint(pdev); | |
678 | ||
118b2a32 PL |
679 | trace_cdnsp_configure_endpoint(cdnsp_get_slot_ctx(&pdev->out_ctx)); |
680 | trace_cdnsp_handle_cmd_config_ep(pep->out_ctx); | |
681 | ||
3d829045 PL |
682 | cdnsp_zero_in_ctx(pdev); |
683 | ||
684 | return ret; | |
685 | } | |
686 | ||
687 | /* | |
688 | * This submits a Reset Device Command, which will set the device state to 0, | |
689 | * set the device address to 0, and disable all the endpoints except the default | |
690 | * control endpoint. The USB core should come back and call | |
691 | * cdnsp_setup_device(), and then re-set up the configuration. | |
692 | */ | |
693 | int cdnsp_reset_device(struct cdnsp_device *pdev) | |
694 | { | |
695 | struct cdnsp_slot_ctx *slot_ctx; | |
696 | int slot_state; | |
697 | int ret, i; | |
698 | ||
699 | slot_ctx = cdnsp_get_slot_ctx(&pdev->in_ctx); | |
700 | slot_ctx->dev_info = 0; | |
701 | pdev->device_address = 0; | |
702 | ||
703 | /* If device is not setup, there is no point in resetting it. */ | |
704 | slot_ctx = cdnsp_get_slot_ctx(&pdev->out_ctx); | |
705 | slot_state = GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)); | |
118b2a32 | 706 | trace_cdnsp_reset_device(slot_ctx); |
3d829045 PL |
707 | |
708 | if (slot_state <= SLOT_STATE_DEFAULT && | |
709 | pdev->eps[0].ep_state & EP_HALTED) { | |
710 | cdnsp_halt_endpoint(pdev, &pdev->eps[0], 0); | |
711 | } | |
712 | ||
713 | /* | |
714 | * During Reset Device command controller shall transition the | |
715 | * endpoint ep0 to the Running State. | |
716 | */ | |
717 | pdev->eps[0].ep_state &= ~(EP_STOPPED | EP_HALTED); | |
718 | pdev->eps[0].ep_state |= EP_ENABLED; | |
719 | ||
720 | if (slot_state <= SLOT_STATE_DEFAULT) | |
721 | return 0; | |
722 | ||
723 | cdnsp_queue_reset_device(pdev); | |
724 | cdnsp_ring_cmd_db(pdev); | |
725 | ret = cdnsp_wait_for_cmd_compl(pdev); | |
726 | ||
727 | /* | |
728 | * After Reset Device command all not default endpoints | |
729 | * are in Disabled state. | |
730 | */ | |
731 | for (i = 1; i < CDNSP_ENDPOINTS_NUM; ++i) | |
732 | pdev->eps[i].ep_state |= EP_STOPPED; | |
733 | ||
118b2a32 PL |
734 | trace_cdnsp_handle_cmd_reset_dev(slot_ctx); |
735 | ||
3d829045 PL |
736 | if (ret) |
737 | dev_err(pdev->dev, "Reset device failed with error code %d", | |
738 | ret); | |
739 | ||
740 | return ret; | |
741 | } | |
742 | ||
743 | /* | |
744 | * Sets the MaxPStreams field and the Linear Stream Array field. | |
745 | * Sets the dequeue pointer to the stream context array. | |
746 | */ | |
747 | static void cdnsp_setup_streams_ep_input_ctx(struct cdnsp_device *pdev, | |
748 | struct cdnsp_ep_ctx *ep_ctx, | |
749 | struct cdnsp_stream_info *stream_info) | |
750 | { | |
751 | u32 max_primary_streams; | |
752 | ||
753 | /* MaxPStreams is the number of stream context array entries, not the | |
754 | * number we're actually using. Must be in 2^(MaxPstreams + 1) format. | |
755 | * fls(0) = 0, fls(0x1) = 1, fls(0x10) = 2, fls(0x100) = 3, etc. | |
756 | */ | |
757 | max_primary_streams = fls(stream_info->num_stream_ctxs) - 2; | |
758 | ep_ctx->ep_info &= cpu_to_le32(~EP_MAXPSTREAMS_MASK); | |
759 | ep_ctx->ep_info |= cpu_to_le32(EP_MAXPSTREAMS(max_primary_streams) | |
760 | | EP_HAS_LSA); | |
761 | ep_ctx->deq = cpu_to_le64(stream_info->ctx_array_dma); | |
762 | } | |
763 | ||
764 | /* | |
765 | * The drivers use this function to prepare a bulk endpoints to use streams. | |
766 | * | |
767 | * Don't allow the call to succeed if endpoint only supports one stream | |
768 | * (which means it doesn't support streams at all). | |
769 | */ | |
770 | int cdnsp_alloc_streams(struct cdnsp_device *pdev, struct cdnsp_ep *pep) | |
771 | { | |
772 | unsigned int num_streams = usb_ss_max_streams(pep->endpoint.comp_desc); | |
773 | unsigned int num_stream_ctxs; | |
774 | int ret; | |
775 | ||
776 | if (num_streams == 0) | |
777 | return 0; | |
778 | ||
779 | if (num_streams > STREAM_NUM_STREAMS) | |
780 | return -EINVAL; | |
781 | ||
782 | /* | |
783 | * Add two to the number of streams requested to account for | |
784 | * stream 0 that is reserved for controller usage and one additional | |
785 | * for TASK SET FULL response. | |
786 | */ | |
787 | num_streams += 2; | |
788 | ||
789 | /* The stream context array size must be a power of two */ | |
790 | num_stream_ctxs = roundup_pow_of_two(num_streams); | |
791 | ||
118b2a32 PL |
792 | trace_cdnsp_stream_number(pep, num_stream_ctxs, num_streams); |
793 | ||
3d829045 PL |
794 | ret = cdnsp_alloc_stream_info(pdev, pep, num_stream_ctxs, num_streams); |
795 | if (ret) | |
796 | return ret; | |
797 | ||
798 | cdnsp_setup_streams_ep_input_ctx(pdev, pep->in_ctx, &pep->stream_info); | |
799 | ||
800 | pep->ep_state |= EP_HAS_STREAMS; | |
801 | pep->stream_info.td_count = 0; | |
802 | pep->stream_info.first_prime_det = 0; | |
803 | ||
804 | /* Subtract 1 for stream 0, which drivers can't use. */ | |
805 | return num_streams - 1; | |
806 | } | |
807 | ||
808 | int cdnsp_disable_slot(struct cdnsp_device *pdev) | |
809 | { | |
810 | int ret; | |
811 | ||
812 | cdnsp_queue_slot_control(pdev, TRB_DISABLE_SLOT); | |
813 | cdnsp_ring_cmd_db(pdev); | |
814 | ret = cdnsp_wait_for_cmd_compl(pdev); | |
815 | ||
816 | pdev->slot_id = 0; | |
817 | pdev->active_port = NULL; | |
818 | ||
118b2a32 PL |
819 | trace_cdnsp_handle_cmd_disable_slot(cdnsp_get_slot_ctx(&pdev->out_ctx)); |
820 | ||
3d829045 PL |
821 | memset(pdev->in_ctx.bytes, 0, CDNSP_CTX_SIZE); |
822 | memset(pdev->out_ctx.bytes, 0, CDNSP_CTX_SIZE); | |
823 | ||
824 | return ret; | |
825 | } | |
826 | ||
827 | int cdnsp_enable_slot(struct cdnsp_device *pdev) | |
828 | { | |
829 | struct cdnsp_slot_ctx *slot_ctx; | |
830 | int slot_state; | |
831 | int ret; | |
832 | ||
833 | /* If device is not setup, there is no point in resetting it */ | |
834 | slot_ctx = cdnsp_get_slot_ctx(&pdev->out_ctx); | |
835 | slot_state = GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)); | |
836 | ||
837 | if (slot_state != SLOT_STATE_DISABLED) | |
838 | return 0; | |
839 | ||
840 | cdnsp_queue_slot_control(pdev, TRB_ENABLE_SLOT); | |
841 | cdnsp_ring_cmd_db(pdev); | |
842 | ret = cdnsp_wait_for_cmd_compl(pdev); | |
843 | if (ret) | |
118b2a32 | 844 | goto show_trace; |
3d829045 PL |
845 | |
846 | pdev->slot_id = 1; | |
847 | ||
118b2a32 PL |
848 | show_trace: |
849 | trace_cdnsp_handle_cmd_enable_slot(cdnsp_get_slot_ctx(&pdev->out_ctx)); | |
850 | ||
851 | return ret; | |
3d829045 PL |
852 | } |
853 | ||
854 | /* | |
855 | * Issue an Address Device command with BSR=0 if setup is SETUP_CONTEXT_ONLY | |
856 | * or with BSR = 1 if set_address is SETUP_CONTEXT_ADDRESS. | |
857 | */ | |
858 | int cdnsp_setup_device(struct cdnsp_device *pdev, enum cdnsp_setup_dev setup) | |
859 | { | |
860 | struct cdnsp_input_control_ctx *ctrl_ctx; | |
861 | struct cdnsp_slot_ctx *slot_ctx; | |
862 | int dev_state = 0; | |
863 | int ret; | |
864 | ||
118b2a32 PL |
865 | if (!pdev->slot_id) { |
866 | trace_cdnsp_slot_id("incorrect"); | |
3d829045 | 867 | return -EINVAL; |
118b2a32 | 868 | } |
3d829045 PL |
869 | |
870 | if (!pdev->active_port->port_num) | |
871 | return -EINVAL; | |
872 | ||
873 | slot_ctx = cdnsp_get_slot_ctx(&pdev->out_ctx); | |
874 | dev_state = GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)); | |
875 | ||
118b2a32 PL |
876 | if (setup == SETUP_CONTEXT_ONLY && dev_state == SLOT_STATE_DEFAULT) { |
877 | trace_cdnsp_slot_already_in_default(slot_ctx); | |
3d829045 | 878 | return 0; |
118b2a32 | 879 | } |
3d829045 PL |
880 | |
881 | slot_ctx = cdnsp_get_slot_ctx(&pdev->in_ctx); | |
882 | ctrl_ctx = cdnsp_get_input_control_ctx(&pdev->in_ctx); | |
883 | ||
884 | if (!slot_ctx->dev_info || dev_state == SLOT_STATE_DEFAULT) { | |
885 | ret = cdnsp_setup_addressable_priv_dev(pdev); | |
886 | if (ret) | |
887 | return ret; | |
888 | } | |
889 | ||
890 | cdnsp_copy_ep0_dequeue_into_input_ctx(pdev); | |
891 | ||
892 | ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG | EP0_FLAG); | |
893 | ctrl_ctx->drop_flags = 0; | |
894 | ||
118b2a32 PL |
895 | trace_cdnsp_setup_device_slot(slot_ctx); |
896 | ||
3d829045 PL |
897 | cdnsp_queue_address_device(pdev, pdev->in_ctx.dma, setup); |
898 | cdnsp_ring_cmd_db(pdev); | |
899 | ret = cdnsp_wait_for_cmd_compl(pdev); | |
900 | ||
118b2a32 PL |
901 | trace_cdnsp_handle_cmd_addr_dev(cdnsp_get_slot_ctx(&pdev->out_ctx)); |
902 | ||
3d829045 PL |
903 | /* Zero the input context control for later use. */ |
904 | ctrl_ctx->add_flags = 0; | |
905 | ctrl_ctx->drop_flags = 0; | |
906 | ||
907 | return ret; | |
908 | } | |
909 | ||
910 | void cdnsp_set_usb2_hardware_lpm(struct cdnsp_device *pdev, | |
911 | struct usb_request *req, | |
912 | int enable) | |
913 | { | |
914 | if (pdev->active_port != &pdev->usb2_port || !pdev->gadget.lpm_capable) | |
915 | return; | |
916 | ||
118b2a32 PL |
917 | trace_cdnsp_lpm(enable); |
918 | ||
3d829045 PL |
919 | if (enable) |
920 | writel(PORT_BESL(CDNSP_DEFAULT_BESL) | PORT_L1S_NYET | PORT_HLE, | |
921 | &pdev->active_port->regs->portpmsc); | |
922 | else | |
923 | writel(PORT_L1S_NYET, &pdev->active_port->regs->portpmsc); | |
924 | } | |
925 | ||
926 | static int cdnsp_get_frame(struct cdnsp_device *pdev) | |
927 | { | |
928 | return readl(&pdev->run_regs->microframe_index) >> 3; | |
929 | } | |
930 | ||
931 | static int cdnsp_gadget_ep_enable(struct usb_ep *ep, | |
932 | const struct usb_endpoint_descriptor *desc) | |
933 | { | |
934 | struct cdnsp_input_control_ctx *ctrl_ctx; | |
935 | struct cdnsp_device *pdev; | |
936 | struct cdnsp_ep *pep; | |
937 | unsigned long flags; | |
938 | u32 added_ctxs; | |
939 | int ret; | |
940 | ||
941 | if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT || | |
942 | !desc->wMaxPacketSize) | |
943 | return -EINVAL; | |
944 | ||
945 | pep = to_cdnsp_ep(ep); | |
946 | pdev = pep->pdev; | |
947 | ||
948 | if (dev_WARN_ONCE(pdev->dev, pep->ep_state & EP_ENABLED, | |
949 | "%s is already enabled\n", pep->name)) | |
950 | return 0; | |
951 | ||
952 | spin_lock_irqsave(&pdev->lock, flags); | |
953 | ||
954 | added_ctxs = cdnsp_get_endpoint_flag(desc); | |
955 | if (added_ctxs == SLOT_FLAG || added_ctxs == EP0_FLAG) { | |
956 | dev_err(pdev->dev, "ERROR: Bad endpoint number\n"); | |
957 | ret = -EINVAL; | |
958 | goto unlock; | |
959 | } | |
960 | ||
961 | pep->interval = desc->bInterval ? BIT(desc->bInterval - 1) : 0; | |
962 | ||
963 | if (pdev->gadget.speed == USB_SPEED_FULL) { | |
964 | if (usb_endpoint_type(desc) == USB_ENDPOINT_XFER_INT) | |
965 | pep->interval = desc->bInterval << 3; | |
966 | if (usb_endpoint_type(desc) == USB_ENDPOINT_XFER_ISOC) | |
967 | pep->interval = BIT(desc->bInterval - 1) << 3; | |
968 | } | |
969 | ||
970 | if (usb_endpoint_type(desc) == USB_ENDPOINT_XFER_ISOC) { | |
971 | if (pep->interval > BIT(12)) { | |
972 | dev_err(pdev->dev, "bInterval %d not supported\n", | |
973 | desc->bInterval); | |
974 | ret = -EINVAL; | |
975 | goto unlock; | |
976 | } | |
977 | cdnsp_set_chicken_bits_2(pdev, CHICKEN_XDMA_2_TP_CACHE_DIS); | |
978 | } | |
979 | ||
980 | ret = cdnsp_endpoint_init(pdev, pep, GFP_ATOMIC); | |
981 | if (ret) | |
982 | goto unlock; | |
983 | ||
984 | ctrl_ctx = cdnsp_get_input_control_ctx(&pdev->in_ctx); | |
985 | ctrl_ctx->add_flags = cpu_to_le32(added_ctxs); | |
986 | ctrl_ctx->drop_flags = 0; | |
987 | ||
988 | ret = cdnsp_update_eps_configuration(pdev, pep); | |
989 | if (ret) { | |
990 | cdnsp_free_endpoint_rings(pdev, pep); | |
991 | goto unlock; | |
992 | } | |
993 | ||
994 | pep->ep_state |= EP_ENABLED; | |
995 | pep->ep_state &= ~EP_STOPPED; | |
996 | ||
997 | unlock: | |
118b2a32 | 998 | trace_cdnsp_ep_enable_end(pep, 0); |
3d829045 PL |
999 | spin_unlock_irqrestore(&pdev->lock, flags); |
1000 | ||
1001 | return ret; | |
1002 | } | |
1003 | ||
1004 | static int cdnsp_gadget_ep_disable(struct usb_ep *ep) | |
1005 | { | |
1006 | struct cdnsp_input_control_ctx *ctrl_ctx; | |
1007 | struct cdnsp_request *preq; | |
1008 | struct cdnsp_device *pdev; | |
1009 | struct cdnsp_ep *pep; | |
1010 | unsigned long flags; | |
1011 | u32 drop_flag; | |
1012 | int ret = 0; | |
1013 | ||
1014 | if (!ep) | |
1015 | return -EINVAL; | |
1016 | ||
1017 | pep = to_cdnsp_ep(ep); | |
1018 | pdev = pep->pdev; | |
1019 | ||
1020 | spin_lock_irqsave(&pdev->lock, flags); | |
1021 | ||
1022 | if (!(pep->ep_state & EP_ENABLED)) { | |
1023 | dev_err(pdev->dev, "%s is already disabled\n", pep->name); | |
1024 | ret = -EINVAL; | |
1025 | goto finish; | |
1026 | } | |
1027 | ||
1028 | cdnsp_cmd_stop_ep(pdev, pep); | |
1029 | pep->ep_state |= EP_DIS_IN_RROGRESS; | |
1030 | cdnsp_cmd_flush_ep(pdev, pep); | |
1031 | ||
1032 | /* Remove all queued USB requests. */ | |
1033 | while (!list_empty(&pep->pending_list)) { | |
1034 | preq = next_request(&pep->pending_list); | |
1035 | cdnsp_ep_dequeue(pep, preq); | |
1036 | } | |
1037 | ||
1038 | cdnsp_invalidate_ep_events(pdev, pep); | |
1039 | ||
1040 | pep->ep_state &= ~EP_DIS_IN_RROGRESS; | |
1041 | drop_flag = cdnsp_get_endpoint_flag(pep->endpoint.desc); | |
1042 | ctrl_ctx = cdnsp_get_input_control_ctx(&pdev->in_ctx); | |
1043 | ctrl_ctx->drop_flags = cpu_to_le32(drop_flag); | |
1044 | ctrl_ctx->add_flags = 0; | |
1045 | ||
1046 | cdnsp_endpoint_zero(pdev, pep); | |
1047 | ||
1048 | ret = cdnsp_update_eps_configuration(pdev, pep); | |
1049 | cdnsp_free_endpoint_rings(pdev, pep); | |
1050 | ||
1051 | pep->ep_state &= ~EP_ENABLED; | |
1052 | pep->ep_state |= EP_STOPPED; | |
1053 | ||
1054 | finish: | |
118b2a32 | 1055 | trace_cdnsp_ep_disable_end(pep, 0); |
3d829045 PL |
1056 | spin_unlock_irqrestore(&pdev->lock, flags); |
1057 | ||
1058 | return ret; | |
1059 | } | |
1060 | ||
1061 | static struct usb_request *cdnsp_gadget_ep_alloc_request(struct usb_ep *ep, | |
1062 | gfp_t gfp_flags) | |
1063 | { | |
1064 | struct cdnsp_ep *pep = to_cdnsp_ep(ep); | |
1065 | struct cdnsp_request *preq; | |
1066 | ||
1067 | preq = kzalloc(sizeof(*preq), gfp_flags); | |
1068 | if (!preq) | |
1069 | return NULL; | |
1070 | ||
1071 | preq->epnum = pep->number; | |
1072 | preq->pep = pep; | |
1073 | ||
118b2a32 PL |
1074 | trace_cdnsp_alloc_request(preq); |
1075 | ||
3d829045 PL |
1076 | return &preq->request; |
1077 | } | |
1078 | ||
1079 | static void cdnsp_gadget_ep_free_request(struct usb_ep *ep, | |
1080 | struct usb_request *request) | |
1081 | { | |
1082 | struct cdnsp_request *preq = to_cdnsp_request(request); | |
1083 | ||
118b2a32 | 1084 | trace_cdnsp_free_request(preq); |
3d829045 PL |
1085 | kfree(preq); |
1086 | } | |
1087 | ||
1088 | static int cdnsp_gadget_ep_queue(struct usb_ep *ep, | |
1089 | struct usb_request *request, | |
1090 | gfp_t gfp_flags) | |
1091 | { | |
1092 | struct cdnsp_request *preq; | |
1093 | struct cdnsp_device *pdev; | |
1094 | struct cdnsp_ep *pep; | |
1095 | unsigned long flags; | |
1096 | int ret; | |
1097 | ||
1098 | if (!request || !ep) | |
1099 | return -EINVAL; | |
1100 | ||
1101 | pep = to_cdnsp_ep(ep); | |
1102 | pdev = pep->pdev; | |
1103 | ||
1104 | if (!(pep->ep_state & EP_ENABLED)) { | |
1105 | dev_err(pdev->dev, "%s: can't queue to disabled endpoint\n", | |
1106 | pep->name); | |
1107 | return -EINVAL; | |
1108 | } | |
1109 | ||
1110 | preq = to_cdnsp_request(request); | |
1111 | spin_lock_irqsave(&pdev->lock, flags); | |
1112 | ret = cdnsp_ep_enqueue(pep, preq); | |
1113 | spin_unlock_irqrestore(&pdev->lock, flags); | |
1114 | ||
1115 | return ret; | |
1116 | } | |
1117 | ||
1118 | static int cdnsp_gadget_ep_dequeue(struct usb_ep *ep, | |
1119 | struct usb_request *request) | |
1120 | { | |
1121 | struct cdnsp_ep *pep = to_cdnsp_ep(ep); | |
1122 | struct cdnsp_device *pdev = pep->pdev; | |
1123 | unsigned long flags; | |
1124 | int ret; | |
1125 | ||
1126 | if (!pep->endpoint.desc) { | |
1127 | dev_err(pdev->dev, | |
1128 | "%s: can't dequeue to disabled endpoint\n", | |
1129 | pep->name); | |
1130 | return -ESHUTDOWN; | |
1131 | } | |
1132 | ||
1133 | spin_lock_irqsave(&pdev->lock, flags); | |
1134 | ret = cdnsp_ep_dequeue(pep, to_cdnsp_request(request)); | |
1135 | spin_unlock_irqrestore(&pdev->lock, flags); | |
1136 | ||
1137 | return ret; | |
1138 | } | |
1139 | ||
1140 | static int cdnsp_gadget_ep_set_halt(struct usb_ep *ep, int value) | |
1141 | { | |
1142 | struct cdnsp_ep *pep = to_cdnsp_ep(ep); | |
1143 | struct cdnsp_device *pdev = pep->pdev; | |
1144 | struct cdnsp_request *preq; | |
1145 | unsigned long flags = 0; | |
1146 | int ret; | |
1147 | ||
1148 | spin_lock_irqsave(&pdev->lock, flags); | |
1149 | ||
1150 | preq = next_request(&pep->pending_list); | |
1151 | if (value) { | |
1152 | if (preq) { | |
118b2a32 | 1153 | trace_cdnsp_ep_busy_try_halt_again(pep, 0); |
3d829045 PL |
1154 | ret = -EAGAIN; |
1155 | goto done; | |
1156 | } | |
1157 | } | |
1158 | ||
1159 | ret = cdnsp_halt_endpoint(pdev, pep, value); | |
1160 | ||
1161 | done: | |
1162 | spin_unlock_irqrestore(&pdev->lock, flags); | |
1163 | return ret; | |
1164 | } | |
1165 | ||
1166 | static int cdnsp_gadget_ep_set_wedge(struct usb_ep *ep) | |
1167 | { | |
1168 | struct cdnsp_ep *pep = to_cdnsp_ep(ep); | |
1169 | struct cdnsp_device *pdev = pep->pdev; | |
1170 | unsigned long flags = 0; | |
1171 | int ret; | |
1172 | ||
1173 | spin_lock_irqsave(&pdev->lock, flags); | |
1174 | pep->ep_state |= EP_WEDGE; | |
1175 | ret = cdnsp_halt_endpoint(pdev, pep, 1); | |
1176 | spin_unlock_irqrestore(&pdev->lock, flags); | |
1177 | ||
1178 | return ret; | |
1179 | } | |
1180 | ||
1181 | static const struct usb_ep_ops cdnsp_gadget_ep0_ops = { | |
1182 | .enable = cdnsp_gadget_ep_enable, | |
1183 | .disable = cdnsp_gadget_ep_disable, | |
1184 | .alloc_request = cdnsp_gadget_ep_alloc_request, | |
1185 | .free_request = cdnsp_gadget_ep_free_request, | |
1186 | .queue = cdnsp_gadget_ep_queue, | |
1187 | .dequeue = cdnsp_gadget_ep_dequeue, | |
1188 | .set_halt = cdnsp_gadget_ep_set_halt, | |
1189 | .set_wedge = cdnsp_gadget_ep_set_wedge, | |
1190 | }; | |
1191 | ||
1192 | static const struct usb_ep_ops cdnsp_gadget_ep_ops = { | |
1193 | .enable = cdnsp_gadget_ep_enable, | |
1194 | .disable = cdnsp_gadget_ep_disable, | |
1195 | .alloc_request = cdnsp_gadget_ep_alloc_request, | |
1196 | .free_request = cdnsp_gadget_ep_free_request, | |
1197 | .queue = cdnsp_gadget_ep_queue, | |
1198 | .dequeue = cdnsp_gadget_ep_dequeue, | |
1199 | .set_halt = cdnsp_gadget_ep_set_halt, | |
1200 | .set_wedge = cdnsp_gadget_ep_set_wedge, | |
1201 | }; | |
1202 | ||
1203 | void cdnsp_gadget_giveback(struct cdnsp_ep *pep, | |
1204 | struct cdnsp_request *preq, | |
1205 | int status) | |
1206 | { | |
1207 | struct cdnsp_device *pdev = pep->pdev; | |
1208 | ||
1209 | list_del(&preq->list); | |
1210 | ||
1211 | if (preq->request.status == -EINPROGRESS) | |
1212 | preq->request.status = status; | |
1213 | ||
1214 | usb_gadget_unmap_request_by_dev(pdev->dev, &preq->request, | |
1215 | preq->direction); | |
1216 | ||
118b2a32 PL |
1217 | trace_cdnsp_request_giveback(preq); |
1218 | ||
3d829045 PL |
1219 | if (preq != &pdev->ep0_preq) { |
1220 | spin_unlock(&pdev->lock); | |
1221 | usb_gadget_giveback_request(&pep->endpoint, &preq->request); | |
1222 | spin_lock(&pdev->lock); | |
1223 | } | |
1224 | } | |
1225 | ||
1226 | static struct usb_endpoint_descriptor cdnsp_gadget_ep0_desc = { | |
1227 | .bLength = USB_DT_ENDPOINT_SIZE, | |
1228 | .bDescriptorType = USB_DT_ENDPOINT, | |
1229 | .bmAttributes = USB_ENDPOINT_XFER_CONTROL, | |
1230 | }; | |
1231 | ||
1232 | static int cdnsp_run(struct cdnsp_device *pdev, | |
1233 | enum usb_device_speed speed) | |
1234 | { | |
1235 | u32 fs_speed = 0; | |
1236 | u64 temp_64; | |
1237 | u32 temp; | |
1238 | int ret; | |
1239 | ||
1240 | temp_64 = cdnsp_read_64(&pdev->ir_set->erst_dequeue); | |
1241 | temp_64 &= ~ERST_PTR_MASK; | |
1242 | temp = readl(&pdev->ir_set->irq_control); | |
1243 | temp &= ~IMOD_INTERVAL_MASK; | |
1244 | temp |= ((IMOD_DEFAULT_INTERVAL / 250) & IMOD_INTERVAL_MASK); | |
1245 | writel(temp, &pdev->ir_set->irq_control); | |
1246 | ||
1247 | temp = readl(&pdev->port3x_regs->mode_addr); | |
1248 | ||
1249 | switch (speed) { | |
1250 | case USB_SPEED_SUPER_PLUS: | |
1251 | temp |= CFG_3XPORT_SSP_SUPPORT; | |
1252 | break; | |
1253 | case USB_SPEED_SUPER: | |
1254 | temp &= ~CFG_3XPORT_SSP_SUPPORT; | |
1255 | break; | |
1256 | case USB_SPEED_HIGH: | |
1257 | break; | |
1258 | case USB_SPEED_FULL: | |
1259 | fs_speed = PORT_REG6_FORCE_FS; | |
1260 | break; | |
1261 | default: | |
1262 | dev_err(pdev->dev, "invalid maximum_speed parameter %d\n", | |
1263 | speed); | |
1264 | fallthrough; | |
1265 | case USB_SPEED_UNKNOWN: | |
1266 | /* Default to superspeed. */ | |
1267 | speed = USB_SPEED_SUPER; | |
1268 | break; | |
1269 | } | |
1270 | ||
1271 | if (speed >= USB_SPEED_SUPER) { | |
1272 | writel(temp, &pdev->port3x_regs->mode_addr); | |
1273 | cdnsp_set_link_state(pdev, &pdev->usb3_port.regs->portsc, | |
1274 | XDEV_RXDETECT); | |
1275 | } else { | |
1276 | cdnsp_disable_port(pdev, &pdev->usb3_port.regs->portsc); | |
1277 | } | |
1278 | ||
1279 | cdnsp_set_link_state(pdev, &pdev->usb2_port.regs->portsc, | |
1280 | XDEV_RXDETECT); | |
1281 | ||
1282 | cdnsp_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512); | |
1283 | ||
1284 | writel(PORT_REG6_L1_L0_HW_EN | fs_speed, &pdev->port20_regs->port_reg6); | |
1285 | ||
1286 | ret = cdnsp_start(pdev); | |
1287 | if (ret) { | |
1288 | ret = -ENODEV; | |
1289 | goto err; | |
1290 | } | |
1291 | ||
1292 | temp = readl(&pdev->op_regs->command); | |
1293 | temp |= (CMD_INTE); | |
1294 | writel(temp, &pdev->op_regs->command); | |
1295 | ||
1296 | temp = readl(&pdev->ir_set->irq_pending); | |
1297 | writel(IMAN_IE_SET(temp), &pdev->ir_set->irq_pending); | |
1298 | ||
118b2a32 | 1299 | trace_cdnsp_init("Controller ready to work"); |
3d829045 PL |
1300 | return 0; |
1301 | err: | |
1302 | cdnsp_halt(pdev); | |
1303 | return ret; | |
1304 | } | |
1305 | ||
1306 | static int cdnsp_gadget_udc_start(struct usb_gadget *g, | |
1307 | struct usb_gadget_driver *driver) | |
1308 | { | |
1309 | enum usb_device_speed max_speed = driver->max_speed; | |
1310 | struct cdnsp_device *pdev = gadget_to_cdnsp(g); | |
1311 | unsigned long flags; | |
1312 | int ret; | |
1313 | ||
1314 | spin_lock_irqsave(&pdev->lock, flags); | |
1315 | pdev->gadget_driver = driver; | |
1316 | ||
1317 | /* limit speed if necessary */ | |
1318 | max_speed = min(driver->max_speed, g->max_speed); | |
1319 | ret = cdnsp_run(pdev, max_speed); | |
1320 | ||
1321 | spin_unlock_irqrestore(&pdev->lock, flags); | |
1322 | ||
1323 | return ret; | |
1324 | } | |
1325 | ||
1326 | /* | |
1327 | * Update Event Ring Dequeue Pointer: | |
1328 | * - When all events have finished | |
1329 | * - To avoid "Event Ring Full Error" condition | |
1330 | */ | |
1331 | void cdnsp_update_erst_dequeue(struct cdnsp_device *pdev, | |
1332 | union cdnsp_trb *event_ring_deq, | |
1333 | u8 clear_ehb) | |
1334 | { | |
1335 | u64 temp_64; | |
1336 | dma_addr_t deq; | |
1337 | ||
1338 | temp_64 = cdnsp_read_64(&pdev->ir_set->erst_dequeue); | |
1339 | ||
1340 | /* If necessary, update the HW's version of the event ring deq ptr. */ | |
1341 | if (event_ring_deq != pdev->event_ring->dequeue) { | |
1342 | deq = cdnsp_trb_virt_to_dma(pdev->event_ring->deq_seg, | |
1343 | pdev->event_ring->dequeue); | |
1344 | temp_64 &= ERST_PTR_MASK; | |
1345 | temp_64 |= ((u64)deq & (u64)~ERST_PTR_MASK); | |
1346 | } | |
1347 | ||
1348 | /* Clear the event handler busy flag (RW1C). */ | |
1349 | if (clear_ehb) | |
1350 | temp_64 |= ERST_EHB; | |
1351 | else | |
1352 | temp_64 &= ~ERST_EHB; | |
1353 | ||
1354 | cdnsp_write_64(temp_64, &pdev->ir_set->erst_dequeue); | |
1355 | } | |
1356 | ||
1357 | static void cdnsp_clear_cmd_ring(struct cdnsp_device *pdev) | |
1358 | { | |
1359 | struct cdnsp_segment *seg; | |
1360 | u64 val_64; | |
1361 | int i; | |
1362 | ||
1363 | cdnsp_initialize_ring_info(pdev->cmd_ring); | |
1364 | ||
1365 | seg = pdev->cmd_ring->first_seg; | |
1366 | for (i = 0; i < pdev->cmd_ring->num_segs; i++) { | |
1367 | memset(seg->trbs, 0, | |
1368 | sizeof(union cdnsp_trb) * (TRBS_PER_SEGMENT - 1)); | |
1369 | seg = seg->next; | |
1370 | } | |
1371 | ||
1372 | /* Set the address in the Command Ring Control register. */ | |
1373 | val_64 = cdnsp_read_64(&pdev->op_regs->cmd_ring); | |
1374 | val_64 = (val_64 & (u64)CMD_RING_RSVD_BITS) | | |
1375 | (pdev->cmd_ring->first_seg->dma & (u64)~CMD_RING_RSVD_BITS) | | |
1376 | pdev->cmd_ring->cycle_state; | |
1377 | cdnsp_write_64(val_64, &pdev->op_regs->cmd_ring); | |
1378 | } | |
1379 | ||
1380 | static void cdnsp_consume_all_events(struct cdnsp_device *pdev) | |
1381 | { | |
1382 | struct cdnsp_segment *event_deq_seg; | |
1383 | union cdnsp_trb *event_ring_deq; | |
1384 | union cdnsp_trb *event; | |
1385 | u32 cycle_bit; | |
1386 | ||
1387 | event_ring_deq = pdev->event_ring->dequeue; | |
1388 | event_deq_seg = pdev->event_ring->deq_seg; | |
1389 | event = pdev->event_ring->dequeue; | |
1390 | ||
1391 | /* Update ring dequeue pointer. */ | |
1392 | while (1) { | |
1393 | cycle_bit = (le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE); | |
1394 | ||
1395 | /* Does the controller or driver own the TRB? */ | |
1396 | if (cycle_bit != pdev->event_ring->cycle_state) | |
1397 | break; | |
1398 | ||
1399 | cdnsp_inc_deq(pdev, pdev->event_ring); | |
1400 | ||
1401 | if (!cdnsp_last_trb_on_seg(event_deq_seg, event)) { | |
1402 | event++; | |
1403 | continue; | |
1404 | } | |
1405 | ||
1406 | if (cdnsp_last_trb_on_ring(pdev->event_ring, event_deq_seg, | |
1407 | event)) | |
1408 | cycle_bit ^= 1; | |
1409 | ||
1410 | event_deq_seg = event_deq_seg->next; | |
1411 | event = event_deq_seg->trbs; | |
1412 | } | |
1413 | ||
1414 | cdnsp_update_erst_dequeue(pdev, event_ring_deq, 1); | |
1415 | } | |
1416 | ||
1417 | static void cdnsp_stop(struct cdnsp_device *pdev) | |
1418 | { | |
1419 | u32 temp; | |
1420 | ||
1421 | cdnsp_cmd_flush_ep(pdev, &pdev->eps[0]); | |
1422 | ||
1423 | /* Remove internally queued request for ep0. */ | |
1424 | if (!list_empty(&pdev->eps[0].pending_list)) { | |
1425 | struct cdnsp_request *req; | |
1426 | ||
1427 | req = next_request(&pdev->eps[0].pending_list); | |
1428 | if (req == &pdev->ep0_preq) | |
1429 | cdnsp_ep_dequeue(&pdev->eps[0], req); | |
1430 | } | |
1431 | ||
1432 | cdnsp_disable_port(pdev, &pdev->usb2_port.regs->portsc); | |
1433 | cdnsp_disable_port(pdev, &pdev->usb3_port.regs->portsc); | |
1434 | cdnsp_disable_slot(pdev); | |
1435 | cdnsp_halt(pdev); | |
1436 | ||
1437 | temp = readl(&pdev->op_regs->status); | |
1438 | writel((temp & ~0x1fff) | STS_EINT, &pdev->op_regs->status); | |
1439 | temp = readl(&pdev->ir_set->irq_pending); | |
1440 | writel(IMAN_IE_CLEAR(temp), &pdev->ir_set->irq_pending); | |
1441 | ||
1442 | cdnsp_clear_port_change_bit(pdev, &pdev->usb2_port.regs->portsc); | |
1443 | cdnsp_clear_port_change_bit(pdev, &pdev->usb3_port.regs->portsc); | |
1444 | ||
1445 | /* Clear interrupt line */ | |
1446 | temp = readl(&pdev->ir_set->irq_pending); | |
1447 | temp |= IMAN_IP; | |
1448 | writel(temp, &pdev->ir_set->irq_pending); | |
1449 | ||
1450 | cdnsp_consume_all_events(pdev); | |
1451 | cdnsp_clear_cmd_ring(pdev); | |
118b2a32 PL |
1452 | |
1453 | trace_cdnsp_exit("Controller stopped."); | |
3d829045 PL |
1454 | } |
1455 | ||
1456 | /* | |
1457 | * Stop controller. | |
1458 | * This function is called by the gadget core when the driver is removed. | |
1459 | * Disable slot, disable IRQs, and quiesce the controller. | |
1460 | */ | |
1461 | static int cdnsp_gadget_udc_stop(struct usb_gadget *g) | |
1462 | { | |
1463 | struct cdnsp_device *pdev = gadget_to_cdnsp(g); | |
1464 | unsigned long flags; | |
1465 | ||
1466 | spin_lock_irqsave(&pdev->lock, flags); | |
1467 | cdnsp_stop(pdev); | |
1468 | pdev->gadget_driver = NULL; | |
1469 | spin_unlock_irqrestore(&pdev->lock, flags); | |
1470 | ||
1471 | return 0; | |
1472 | } | |
1473 | ||
1474 | static int cdnsp_gadget_get_frame(struct usb_gadget *g) | |
1475 | { | |
1476 | struct cdnsp_device *pdev = gadget_to_cdnsp(g); | |
1477 | ||
1478 | return cdnsp_get_frame(pdev); | |
1479 | } | |
1480 | ||
1481 | static void __cdnsp_gadget_wakeup(struct cdnsp_device *pdev) | |
1482 | { | |
1483 | struct cdnsp_port_regs __iomem *port_regs; | |
1484 | u32 portpm, portsc; | |
1485 | ||
1486 | port_regs = pdev->active_port->regs; | |
1487 | portsc = readl(&port_regs->portsc) & PORT_PLS_MASK; | |
1488 | ||
1489 | /* Remote wakeup feature is not enabled by host. */ | |
1490 | if (pdev->gadget.speed < USB_SPEED_SUPER && portsc == XDEV_U2) { | |
1491 | portpm = readl(&port_regs->portpmsc); | |
1492 | ||
1493 | if (!(portpm & PORT_RWE)) | |
1494 | return; | |
1495 | } | |
1496 | ||
1497 | if (portsc == XDEV_U3 && !pdev->may_wakeup) | |
1498 | return; | |
1499 | ||
1500 | cdnsp_set_link_state(pdev, &port_regs->portsc, XDEV_U0); | |
1501 | ||
1502 | pdev->cdnsp_state |= CDNSP_WAKEUP_PENDING; | |
1503 | } | |
1504 | ||
1505 | static int cdnsp_gadget_wakeup(struct usb_gadget *g) | |
1506 | { | |
1507 | struct cdnsp_device *pdev = gadget_to_cdnsp(g); | |
1508 | unsigned long flags; | |
1509 | ||
1510 | spin_lock_irqsave(&pdev->lock, flags); | |
1511 | __cdnsp_gadget_wakeup(pdev); | |
1512 | spin_unlock_irqrestore(&pdev->lock, flags); | |
1513 | ||
1514 | return 0; | |
1515 | } | |
1516 | ||
1517 | static int cdnsp_gadget_set_selfpowered(struct usb_gadget *g, | |
1518 | int is_selfpowered) | |
1519 | { | |
1520 | struct cdnsp_device *pdev = gadget_to_cdnsp(g); | |
1521 | unsigned long flags; | |
1522 | ||
1523 | spin_lock_irqsave(&pdev->lock, flags); | |
1524 | g->is_selfpowered = !!is_selfpowered; | |
1525 | spin_unlock_irqrestore(&pdev->lock, flags); | |
1526 | ||
1527 | return 0; | |
1528 | } | |
1529 | ||
1530 | static int cdnsp_gadget_pullup(struct usb_gadget *gadget, int is_on) | |
1531 | { | |
1532 | struct cdnsp_device *pdev = gadget_to_cdnsp(gadget); | |
1533 | struct cdns *cdns = dev_get_drvdata(pdev->dev); | |
1534 | ||
118b2a32 PL |
1535 | trace_cdnsp_pullup(is_on); |
1536 | ||
3d829045 PL |
1537 | if (!is_on) { |
1538 | cdnsp_reset_device(pdev); | |
1539 | cdns_clear_vbus(cdns); | |
1540 | } else { | |
1541 | cdns_set_vbus(cdns); | |
1542 | } | |
1543 | return 0; | |
1544 | } | |
1545 | ||
7650778e | 1546 | static const struct usb_gadget_ops cdnsp_gadget_ops = { |
3d829045 PL |
1547 | .get_frame = cdnsp_gadget_get_frame, |
1548 | .wakeup = cdnsp_gadget_wakeup, | |
1549 | .set_selfpowered = cdnsp_gadget_set_selfpowered, | |
1550 | .pullup = cdnsp_gadget_pullup, | |
1551 | .udc_start = cdnsp_gadget_udc_start, | |
1552 | .udc_stop = cdnsp_gadget_udc_stop, | |
1553 | }; | |
1554 | ||
1555 | static void cdnsp_get_ep_buffering(struct cdnsp_device *pdev, | |
1556 | struct cdnsp_ep *pep) | |
1557 | { | |
1558 | void __iomem *reg = &pdev->cap_regs->hc_capbase; | |
1559 | int endpoints; | |
1560 | ||
1561 | reg += cdnsp_find_next_ext_cap(reg, 0, XBUF_CAP_ID); | |
1562 | ||
1563 | if (!pep->direction) { | |
1564 | pep->buffering = readl(reg + XBUF_RX_TAG_MASK_0_OFFSET); | |
1565 | pep->buffering_period = readl(reg + XBUF_RX_TAG_MASK_1_OFFSET); | |
1566 | pep->buffering = (pep->buffering + 1) / 2; | |
1567 | pep->buffering_period = (pep->buffering_period + 1) / 2; | |
1568 | return; | |
1569 | } | |
1570 | ||
1571 | endpoints = HCS_ENDPOINTS(readl(&pdev->hcs_params1)) / 2; | |
1572 | ||
1573 | /* Set to XBUF_TX_TAG_MASK_0 register. */ | |
1574 | reg += XBUF_TX_CMD_OFFSET + (endpoints * 2 + 2) * sizeof(u32); | |
1575 | /* Set reg to XBUF_TX_TAG_MASK_N related with this endpoint. */ | |
1576 | reg += pep->number * sizeof(u32) * 2; | |
1577 | ||
1578 | pep->buffering = (readl(reg) + 1) / 2; | |
1579 | pep->buffering_period = pep->buffering; | |
1580 | } | |
1581 | ||
1582 | static int cdnsp_gadget_init_endpoints(struct cdnsp_device *pdev) | |
1583 | { | |
1584 | int max_streams = HCC_MAX_PSA(pdev->hcc_params); | |
1585 | struct cdnsp_ep *pep; | |
1586 | int i; | |
1587 | ||
1588 | INIT_LIST_HEAD(&pdev->gadget.ep_list); | |
1589 | ||
1590 | if (max_streams < STREAM_LOG_STREAMS) { | |
1591 | dev_err(pdev->dev, "Stream size %d not supported\n", | |
1592 | max_streams); | |
1593 | return -EINVAL; | |
1594 | } | |
1595 | ||
1596 | max_streams = STREAM_LOG_STREAMS; | |
1597 | ||
1598 | for (i = 0; i < CDNSP_ENDPOINTS_NUM; i++) { | |
1599 | bool direction = !(i & 1); /* Start from OUT endpoint. */ | |
1600 | u8 epnum = ((i + 1) >> 1); | |
1601 | ||
1602 | if (!CDNSP_IF_EP_EXIST(pdev, epnum, direction)) | |
1603 | continue; | |
1604 | ||
1605 | pep = &pdev->eps[i]; | |
1606 | pep->pdev = pdev; | |
1607 | pep->number = epnum; | |
1608 | pep->direction = direction; /* 0 for OUT, 1 for IN. */ | |
1609 | ||
1610 | /* | |
1611 | * Ep0 is bidirectional, so ep0in and ep0out are represented by | |
1612 | * pdev->eps[0] | |
1613 | */ | |
1614 | if (epnum == 0) { | |
1615 | snprintf(pep->name, sizeof(pep->name), "ep%d%s", | |
1616 | epnum, "BiDir"); | |
1617 | ||
1618 | pep->idx = 0; | |
1619 | usb_ep_set_maxpacket_limit(&pep->endpoint, 512); | |
1620 | pep->endpoint.maxburst = 1; | |
1621 | pep->endpoint.ops = &cdnsp_gadget_ep0_ops; | |
1622 | pep->endpoint.desc = &cdnsp_gadget_ep0_desc; | |
1623 | pep->endpoint.comp_desc = NULL; | |
1624 | pep->endpoint.caps.type_control = true; | |
1625 | pep->endpoint.caps.dir_in = true; | |
1626 | pep->endpoint.caps.dir_out = true; | |
1627 | ||
1628 | pdev->ep0_preq.epnum = pep->number; | |
1629 | pdev->ep0_preq.pep = pep; | |
1630 | pdev->gadget.ep0 = &pep->endpoint; | |
1631 | } else { | |
1632 | snprintf(pep->name, sizeof(pep->name), "ep%d%s", | |
1633 | epnum, (pep->direction) ? "in" : "out"); | |
1634 | ||
1635 | pep->idx = (epnum * 2 + (direction ? 1 : 0)) - 1; | |
1636 | usb_ep_set_maxpacket_limit(&pep->endpoint, 1024); | |
1637 | ||
1638 | pep->endpoint.max_streams = max_streams; | |
1639 | pep->endpoint.ops = &cdnsp_gadget_ep_ops; | |
1640 | list_add_tail(&pep->endpoint.ep_list, | |
1641 | &pdev->gadget.ep_list); | |
1642 | ||
1643 | pep->endpoint.caps.type_iso = true; | |
1644 | pep->endpoint.caps.type_bulk = true; | |
1645 | pep->endpoint.caps.type_int = true; | |
1646 | ||
1647 | pep->endpoint.caps.dir_in = direction; | |
1648 | pep->endpoint.caps.dir_out = !direction; | |
1649 | } | |
1650 | ||
1651 | pep->endpoint.name = pep->name; | |
1652 | pep->in_ctx = cdnsp_get_ep_ctx(&pdev->in_ctx, pep->idx); | |
1653 | pep->out_ctx = cdnsp_get_ep_ctx(&pdev->out_ctx, pep->idx); | |
1654 | cdnsp_get_ep_buffering(pdev, pep); | |
1655 | ||
1656 | dev_dbg(pdev->dev, "Init %s, MPS: %04x SupType: " | |
1657 | "CTRL: %s, INT: %s, BULK: %s, ISOC %s, " | |
1658 | "SupDir IN: %s, OUT: %s\n", | |
1659 | pep->name, 1024, | |
1660 | (pep->endpoint.caps.type_control) ? "yes" : "no", | |
1661 | (pep->endpoint.caps.type_int) ? "yes" : "no", | |
1662 | (pep->endpoint.caps.type_bulk) ? "yes" : "no", | |
1663 | (pep->endpoint.caps.type_iso) ? "yes" : "no", | |
1664 | (pep->endpoint.caps.dir_in) ? "yes" : "no", | |
1665 | (pep->endpoint.caps.dir_out) ? "yes" : "no"); | |
1666 | ||
1667 | INIT_LIST_HEAD(&pep->pending_list); | |
1668 | } | |
1669 | ||
1670 | return 0; | |
1671 | } | |
1672 | ||
1673 | static void cdnsp_gadget_free_endpoints(struct cdnsp_device *pdev) | |
1674 | { | |
1675 | struct cdnsp_ep *pep; | |
1676 | int i; | |
1677 | ||
1678 | for (i = 0; i < CDNSP_ENDPOINTS_NUM; i++) { | |
1679 | pep = &pdev->eps[i]; | |
1680 | if (pep->number != 0 && pep->out_ctx) | |
1681 | list_del(&pep->endpoint.ep_list); | |
1682 | } | |
1683 | } | |
1684 | ||
1685 | void cdnsp_disconnect_gadget(struct cdnsp_device *pdev) | |
1686 | { | |
1687 | pdev->cdnsp_state |= CDNSP_STATE_DISCONNECT_PENDING; | |
1688 | ||
1689 | if (pdev->gadget_driver && pdev->gadget_driver->disconnect) { | |
1690 | spin_unlock(&pdev->lock); | |
1691 | pdev->gadget_driver->disconnect(&pdev->gadget); | |
1692 | spin_lock(&pdev->lock); | |
1693 | } | |
1694 | ||
1695 | pdev->gadget.speed = USB_SPEED_UNKNOWN; | |
1696 | usb_gadget_set_state(&pdev->gadget, USB_STATE_NOTATTACHED); | |
1697 | ||
1698 | pdev->cdnsp_state &= ~CDNSP_STATE_DISCONNECT_PENDING; | |
1699 | } | |
1700 | ||
1701 | void cdnsp_suspend_gadget(struct cdnsp_device *pdev) | |
1702 | { | |
1703 | if (pdev->gadget_driver && pdev->gadget_driver->suspend) { | |
1704 | spin_unlock(&pdev->lock); | |
1705 | pdev->gadget_driver->suspend(&pdev->gadget); | |
1706 | spin_lock(&pdev->lock); | |
1707 | } | |
1708 | } | |
1709 | ||
1710 | void cdnsp_resume_gadget(struct cdnsp_device *pdev) | |
1711 | { | |
1712 | if (pdev->gadget_driver && pdev->gadget_driver->resume) { | |
1713 | spin_unlock(&pdev->lock); | |
1714 | pdev->gadget_driver->resume(&pdev->gadget); | |
1715 | spin_lock(&pdev->lock); | |
1716 | } | |
1717 | } | |
1718 | ||
1719 | void cdnsp_irq_reset(struct cdnsp_device *pdev) | |
1720 | { | |
1721 | struct cdnsp_port_regs __iomem *port_regs; | |
1722 | ||
1723 | cdnsp_reset_device(pdev); | |
1724 | ||
1725 | port_regs = pdev->active_port->regs; | |
1726 | pdev->gadget.speed = cdnsp_port_speed(readl(port_regs)); | |
1727 | ||
1728 | spin_unlock(&pdev->lock); | |
1729 | usb_gadget_udc_reset(&pdev->gadget, pdev->gadget_driver); | |
1730 | spin_lock(&pdev->lock); | |
1731 | ||
1732 | switch (pdev->gadget.speed) { | |
1733 | case USB_SPEED_SUPER_PLUS: | |
1734 | case USB_SPEED_SUPER: | |
1735 | cdnsp_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512); | |
1736 | pdev->gadget.ep0->maxpacket = 512; | |
1737 | break; | |
1738 | case USB_SPEED_HIGH: | |
1739 | case USB_SPEED_FULL: | |
1740 | cdnsp_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64); | |
1741 | pdev->gadget.ep0->maxpacket = 64; | |
1742 | break; | |
1743 | default: | |
1744 | /* Low speed is not supported. */ | |
1745 | dev_err(pdev->dev, "Unknown device speed\n"); | |
1746 | break; | |
1747 | } | |
1748 | ||
1749 | cdnsp_clear_chicken_bits_2(pdev, CHICKEN_XDMA_2_TP_CACHE_DIS); | |
1750 | cdnsp_setup_device(pdev, SETUP_CONTEXT_ONLY); | |
1751 | usb_gadget_set_state(&pdev->gadget, USB_STATE_DEFAULT); | |
1752 | } | |
1753 | ||
1754 | static void cdnsp_get_rev_cap(struct cdnsp_device *pdev) | |
1755 | { | |
1756 | void __iomem *reg = &pdev->cap_regs->hc_capbase; | |
1757 | struct cdnsp_rev_cap *rev_cap; | |
1758 | ||
1759 | reg += cdnsp_find_next_ext_cap(reg, 0, RTL_REV_CAP); | |
1760 | rev_cap = reg; | |
1761 | ||
1762 | pdev->rev_cap.ctrl_revision = readl(&rev_cap->ctrl_revision); | |
1763 | pdev->rev_cap.rtl_revision = readl(&rev_cap->rtl_revision); | |
1764 | pdev->rev_cap.ep_supported = readl(&rev_cap->ep_supported); | |
1765 | pdev->rev_cap.ext_cap = readl(&rev_cap->ext_cap); | |
1766 | pdev->rev_cap.rx_buff_size = readl(&rev_cap->rx_buff_size); | |
1767 | pdev->rev_cap.tx_buff_size = readl(&rev_cap->tx_buff_size); | |
1768 | ||
1769 | dev_info(pdev->dev, "Rev: %08x/%08x, eps: %08x, buff: %08x/%08x\n", | |
1770 | pdev->rev_cap.ctrl_revision, pdev->rev_cap.rtl_revision, | |
1771 | pdev->rev_cap.ep_supported, pdev->rev_cap.rx_buff_size, | |
1772 | pdev->rev_cap.tx_buff_size); | |
1773 | } | |
1774 | ||
1775 | static int cdnsp_gen_setup(struct cdnsp_device *pdev) | |
1776 | { | |
1777 | int ret; | |
1778 | u32 reg; | |
1779 | ||
1780 | pdev->cap_regs = pdev->regs; | |
1781 | pdev->op_regs = pdev->regs + | |
1782 | HC_LENGTH(readl(&pdev->cap_regs->hc_capbase)); | |
1783 | pdev->run_regs = pdev->regs + | |
1784 | (readl(&pdev->cap_regs->run_regs_off) & RTSOFF_MASK); | |
1785 | ||
1786 | /* Cache read-only capability registers */ | |
1787 | pdev->hcs_params1 = readl(&pdev->cap_regs->hcs_params1); | |
1788 | pdev->hcc_params = readl(&pdev->cap_regs->hc_capbase); | |
1789 | pdev->hci_version = HC_VERSION(pdev->hcc_params); | |
1790 | pdev->hcc_params = readl(&pdev->cap_regs->hcc_params); | |
1791 | ||
1792 | cdnsp_get_rev_cap(pdev); | |
1793 | ||
1794 | /* Make sure the Device Controller is halted. */ | |
1795 | ret = cdnsp_halt(pdev); | |
1796 | if (ret) | |
1797 | return ret; | |
1798 | ||
1799 | /* Reset the internal controller memory state and registers. */ | |
1800 | ret = cdnsp_reset(pdev); | |
1801 | if (ret) | |
1802 | return ret; | |
1803 | ||
1804 | /* | |
1805 | * Set dma_mask and coherent_dma_mask to 64-bits, | |
1806 | * if controller supports 64-bit addressing. | |
1807 | */ | |
1808 | if (HCC_64BIT_ADDR(pdev->hcc_params) && | |
1809 | !dma_set_mask(pdev->dev, DMA_BIT_MASK(64))) { | |
1810 | dev_dbg(pdev->dev, "Enabling 64-bit DMA addresses.\n"); | |
1811 | dma_set_coherent_mask(pdev->dev, DMA_BIT_MASK(64)); | |
1812 | } else { | |
1813 | /* | |
1814 | * This is to avoid error in cases where a 32-bit USB | |
1815 | * controller is used on a 64-bit capable system. | |
1816 | */ | |
1817 | ret = dma_set_mask(pdev->dev, DMA_BIT_MASK(32)); | |
1818 | if (ret) | |
1819 | return ret; | |
1820 | ||
1821 | dev_dbg(pdev->dev, "Enabling 32-bit DMA addresses.\n"); | |
1822 | dma_set_coherent_mask(pdev->dev, DMA_BIT_MASK(32)); | |
1823 | } | |
1824 | ||
1825 | spin_lock_init(&pdev->lock); | |
1826 | ||
dc68ba6c | 1827 | ret = cdnsp_mem_init(pdev); |
3d829045 PL |
1828 | if (ret) |
1829 | return ret; | |
1830 | ||
1831 | /* | |
1832 | * Software workaround for U1: after transition | |
1833 | * to U1 the controller starts gating clock, and in some cases, | |
1834 | * it causes that controller stack. | |
1835 | */ | |
1836 | reg = readl(&pdev->port3x_regs->mode_2); | |
1837 | reg &= ~CFG_3XPORT_U1_PIPE_CLK_GATE_EN; | |
1838 | writel(reg, &pdev->port3x_regs->mode_2); | |
1839 | ||
1840 | return 0; | |
1841 | } | |
1842 | ||
1843 | static int __cdnsp_gadget_init(struct cdns *cdns) | |
1844 | { | |
1845 | struct cdnsp_device *pdev; | |
1846 | u32 max_speed; | |
1847 | int ret = -ENOMEM; | |
1848 | ||
1849 | cdns_drd_gadget_on(cdns); | |
1850 | ||
1851 | pdev = kzalloc(sizeof(*pdev), GFP_KERNEL); | |
1852 | if (!pdev) | |
1853 | return -ENOMEM; | |
1854 | ||
1855 | pm_runtime_get_sync(cdns->dev); | |
1856 | ||
1857 | cdns->gadget_dev = pdev; | |
1858 | pdev->dev = cdns->dev; | |
1859 | pdev->regs = cdns->dev_regs; | |
1860 | max_speed = usb_get_maximum_speed(cdns->dev); | |
1861 | ||
1862 | switch (max_speed) { | |
1863 | case USB_SPEED_FULL: | |
1864 | case USB_SPEED_HIGH: | |
1865 | case USB_SPEED_SUPER: | |
1866 | case USB_SPEED_SUPER_PLUS: | |
1867 | break; | |
1868 | default: | |
1869 | dev_err(cdns->dev, "invalid speed parameter %d\n", max_speed); | |
1870 | fallthrough; | |
1871 | case USB_SPEED_UNKNOWN: | |
1872 | /* Default to SSP */ | |
1873 | max_speed = USB_SPEED_SUPER_PLUS; | |
1874 | break; | |
1875 | } | |
1876 | ||
1877 | pdev->gadget.ops = &cdnsp_gadget_ops; | |
1878 | pdev->gadget.name = "cdnsp-gadget"; | |
1879 | pdev->gadget.speed = USB_SPEED_UNKNOWN; | |
1880 | pdev->gadget.sg_supported = 1; | |
1881 | pdev->gadget.max_speed = USB_SPEED_SUPER_PLUS; | |
1882 | pdev->gadget.lpm_capable = 1; | |
1883 | ||
1884 | pdev->setup_buf = kzalloc(CDNSP_EP0_SETUP_SIZE, GFP_KERNEL); | |
1885 | if (!pdev->setup_buf) | |
1886 | goto free_pdev; | |
1887 | ||
1888 | /* | |
1889 | * Controller supports not aligned buffer but it should improve | |
1890 | * performance. | |
1891 | */ | |
1892 | pdev->gadget.quirk_ep_out_aligned_size = true; | |
1893 | ||
1894 | ret = cdnsp_gen_setup(pdev); | |
1895 | if (ret) { | |
1896 | dev_err(pdev->dev, "Generic initialization failed %d\n", ret); | |
1897 | goto free_setup; | |
1898 | } | |
1899 | ||
1900 | ret = cdnsp_gadget_init_endpoints(pdev); | |
1901 | if (ret) { | |
1902 | dev_err(pdev->dev, "failed to initialize endpoints\n"); | |
1903 | goto halt_pdev; | |
1904 | } | |
1905 | ||
1906 | ret = usb_add_gadget_udc(pdev->dev, &pdev->gadget); | |
1907 | if (ret) { | |
1908 | dev_err(pdev->dev, "failed to register udc\n"); | |
1909 | goto free_endpoints; | |
1910 | } | |
1911 | ||
1912 | ret = devm_request_threaded_irq(pdev->dev, cdns->dev_irq, | |
1913 | cdnsp_irq_handler, | |
1914 | cdnsp_thread_irq_handler, IRQF_SHARED, | |
1915 | dev_name(pdev->dev), pdev); | |
1916 | if (ret) | |
1917 | goto del_gadget; | |
1918 | ||
1919 | return 0; | |
1920 | ||
1921 | del_gadget: | |
1922 | usb_del_gadget_udc(&pdev->gadget); | |
1923 | free_endpoints: | |
1924 | cdnsp_gadget_free_endpoints(pdev); | |
1925 | halt_pdev: | |
1926 | cdnsp_halt(pdev); | |
1927 | cdnsp_reset(pdev); | |
1928 | cdnsp_mem_cleanup(pdev); | |
1929 | free_setup: | |
1930 | kfree(pdev->setup_buf); | |
1931 | free_pdev: | |
1932 | kfree(pdev); | |
1933 | ||
1934 | return ret; | |
1935 | } | |
1936 | ||
1937 | static void cdnsp_gadget_exit(struct cdns *cdns) | |
1938 | { | |
1939 | struct cdnsp_device *pdev = cdns->gadget_dev; | |
1940 | ||
1941 | devm_free_irq(pdev->dev, cdns->dev_irq, pdev); | |
1942 | pm_runtime_mark_last_busy(cdns->dev); | |
1943 | pm_runtime_put_autosuspend(cdns->dev); | |
1944 | usb_del_gadget_udc(&pdev->gadget); | |
1945 | cdnsp_gadget_free_endpoints(pdev); | |
1946 | cdnsp_mem_cleanup(pdev); | |
1947 | kfree(pdev); | |
1948 | cdns->gadget_dev = NULL; | |
1949 | cdns_drd_gadget_off(cdns); | |
1950 | } | |
1951 | ||
1952 | static int cdnsp_gadget_suspend(struct cdns *cdns, bool do_wakeup) | |
1953 | { | |
1954 | struct cdnsp_device *pdev = cdns->gadget_dev; | |
1955 | unsigned long flags; | |
1956 | ||
1957 | if (pdev->link_state == XDEV_U3) | |
1958 | return 0; | |
1959 | ||
1960 | spin_lock_irqsave(&pdev->lock, flags); | |
1961 | cdnsp_disconnect_gadget(pdev); | |
1962 | cdnsp_stop(pdev); | |
1963 | spin_unlock_irqrestore(&pdev->lock, flags); | |
1964 | ||
1965 | return 0; | |
1966 | } | |
1967 | ||
1968 | static int cdnsp_gadget_resume(struct cdns *cdns, bool hibernated) | |
1969 | { | |
1970 | struct cdnsp_device *pdev = cdns->gadget_dev; | |
1971 | enum usb_device_speed max_speed; | |
1972 | unsigned long flags; | |
1973 | int ret; | |
1974 | ||
1975 | if (!pdev->gadget_driver) | |
1976 | return 0; | |
1977 | ||
1978 | spin_lock_irqsave(&pdev->lock, flags); | |
1979 | max_speed = pdev->gadget_driver->max_speed; | |
1980 | ||
1981 | /* Limit speed if necessary. */ | |
1982 | max_speed = min(max_speed, pdev->gadget.max_speed); | |
1983 | ||
1984 | ret = cdnsp_run(pdev, max_speed); | |
1985 | ||
1986 | if (pdev->link_state == XDEV_U3) | |
1987 | __cdnsp_gadget_wakeup(pdev); | |
1988 | ||
1989 | spin_unlock_irqrestore(&pdev->lock, flags); | |
1990 | ||
1991 | return ret; | |
1992 | } | |
1993 | ||
1994 | /** | |
1995 | * cdnsp_gadget_init - initialize device structure | |
1996 | * @cdns: cdnsp instance | |
1997 | * | |
1998 | * This function initializes the gadget. | |
1999 | */ | |
2000 | int cdnsp_gadget_init(struct cdns *cdns) | |
2001 | { | |
2002 | struct cdns_role_driver *rdrv; | |
2003 | ||
2004 | rdrv = devm_kzalloc(cdns->dev, sizeof(*rdrv), GFP_KERNEL); | |
2005 | if (!rdrv) | |
2006 | return -ENOMEM; | |
2007 | ||
2008 | rdrv->start = __cdnsp_gadget_init; | |
2009 | rdrv->stop = cdnsp_gadget_exit; | |
2010 | rdrv->suspend = cdnsp_gadget_suspend; | |
2011 | rdrv->resume = cdnsp_gadget_resume; | |
2012 | rdrv->state = CDNS_ROLE_STATE_INACTIVE; | |
2013 | rdrv->name = "gadget"; | |
2014 | cdns->roles[USB_ROLE_DEVICE] = rdrv; | |
2015 | ||
2016 | return 0; | |
2017 | } |