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usb: cdnsp: cdns3 Add main part of Cadence USBSSP DRD Driver
[linux-block.git] / drivers / usb / cdns3 / cdnsp-gadget.c
CommitLineData
3d829045
PL		 1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Cadence CDNSP DRD Driver.
4 *
5 * Copyright (C) 2020 Cadence.
6 *
7 * Author: Pawel Laszczak <pawell@cadence.com>
8 *
9 */
10
11#include <linux/moduleparam.h>
12#include <linux/dma-mapping.h>
13#include <linux/module.h>
14#include <linux/iopoll.h>
15#include <linux/delay.h>
16#include <linux/log2.h>
17#include <linux/slab.h>
18#include <linux/pci.h>
19#include <linux/irq.h>
20#include <linux/dmi.h>
21
22#include "core.h"
23#include "gadget-export.h"
24#include "drd.h"
25#include "cdnsp-gadget.h"
26
27unsigned int cdnsp_port_speed(unsigned int port_status)
28{
29 /*Detect gadget speed based on PORTSC register*/
30 if (DEV_SUPERSPEEDPLUS(port_status))
31 return USB_SPEED_SUPER_PLUS;
32 else if (DEV_SUPERSPEED(port_status))
33 return USB_SPEED_SUPER;
34 else if (DEV_HIGHSPEED(port_status))
35 return USB_SPEED_HIGH;
36 else if (DEV_FULLSPEED(port_status))
37 return USB_SPEED_FULL;
38
39 /* If device is detached then speed will be USB_SPEED_UNKNOWN.*/
40 return USB_SPEED_UNKNOWN;
41}
42
43/*
44 * Given a port state, this function returns a value that would result in the
45 * port being in the same state, if the value was written to the port status
46 * control register.
47 * Save Read Only (RO) bits and save read/write bits where
48 * writing a 0 clears the bit and writing a 1 sets the bit (RWS).
49 * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect.
50 */
51u32 cdnsp_port_state_to_neutral(u32 state)
52{
53 /* Save read-only status and port state. */
54 return (state & CDNSP_PORT_RO) | (state & CDNSP_PORT_RWS);
55}
56
57/**
58 * Find the offset of the extended capabilities with capability ID id.
59 * @base: PCI MMIO registers base address.
60 * @start: Address at which to start looking, (0 or HCC_PARAMS to start at
61 * beginning of list)
62 * @id: Extended capability ID to search for.
63 *
64 * Returns the offset of the next matching extended capability structure.
65 * Some capabilities can occur several times,
66 * e.g., the EXT_CAPS_PROTOCOL, and this provides a way to find them all.
67 */
68int cdnsp_find_next_ext_cap(void __iomem *base, u32 start, int id)
69{
70 u32 offset = start;
71 u32 next;
72 u32 val;
73
74 if (!start || start == HCC_PARAMS_OFFSET) {
75 val = readl(base + HCC_PARAMS_OFFSET);
76 if (val == ~0)
77 return 0;
78
79 offset = HCC_EXT_CAPS(val) << 2;
80 if (!offset)
81 return 0;
82 };
83
84 do {
85 val = readl(base + offset);
86 if (val == ~0)
87 return 0;
88
89 if (EXT_CAPS_ID(val) == id && offset != start)
90 return offset;
91
92 next = EXT_CAPS_NEXT(val);
93 offset += next << 2;
94 } while (next);
95
96 return 0;
97}
98
99void cdnsp_set_link_state(struct cdnsp_device *pdev,
100 __le32 __iomem *port_regs,
101 u32 link_state)
102{
103 u32 temp;
104
105 temp = readl(port_regs);
106 temp = cdnsp_port_state_to_neutral(temp);
107 temp |= PORT_WKCONN_E | PORT_WKDISC_E;
108 writel(temp, port_regs);
109
110 temp &= ~PORT_PLS_MASK;
111 temp |= PORT_LINK_STROBE | link_state;
112
113 writel(temp, port_regs);
114}
115
116static void cdnsp_disable_port(struct cdnsp_device *pdev,
117 __le32 __iomem *port_regs)
118{
119 u32 temp = cdnsp_port_state_to_neutral(readl(port_regs));
120
121 writel(temp | PORT_PED, port_regs);
122}
123
124static void cdnsp_clear_port_change_bit(struct cdnsp_device *pdev,
125 __le32 __iomem *port_regs)
126{
127 u32 portsc = readl(port_regs);
128
129 writel(cdnsp_port_state_to_neutral(portsc) |
130 (portsc & PORT_CHANGE_BITS), port_regs);
131}
132
133static void cdnsp_set_chicken_bits_2(struct cdnsp_device *pdev, u32 bit)
134{
135 __le32 __iomem *reg;
136 void __iomem *base;
137 u32 offset = 0;
138
139 base = &pdev->cap_regs->hc_capbase;
140 offset = cdnsp_find_next_ext_cap(base, offset, D_XEC_PRE_REGS_CAP);
141 reg = base + offset + REG_CHICKEN_BITS_2_OFFSET;
142
143 bit = readl(reg) | bit;
144 writel(bit, reg);
145}
146
147static void cdnsp_clear_chicken_bits_2(struct cdnsp_device *pdev, u32 bit)
148{
149 __le32 __iomem *reg;
150 void __iomem *base;
151 u32 offset = 0;
152
153 base = &pdev->cap_regs->hc_capbase;
154 offset = cdnsp_find_next_ext_cap(base, offset, D_XEC_PRE_REGS_CAP);
155 reg = base + offset + REG_CHICKEN_BITS_2_OFFSET;
156
157 bit = readl(reg) & ~bit;
158 writel(bit, reg);
159}
160
161/*
162 * Disable interrupts and begin the controller halting process.
163 */
164static void cdnsp_quiesce(struct cdnsp_device *pdev)
165{
166 u32 halted;
167 u32 mask;
168 u32 cmd;
169
170 mask = ~(u32)(CDNSP_IRQS);
171
172 halted = readl(&pdev->op_regs->status) & STS_HALT;
173 if (!halted)
174 mask &= ~(CMD_R_S | CMD_DEVEN);
175
176 cmd = readl(&pdev->op_regs->command);
177 cmd &= mask;
178 writel(cmd, &pdev->op_regs->command);
179}
180
181/*
182 * Force controller into halt state.
183 *
184 * Disable any IRQs and clear the run/stop bit.
185 * Controller will complete any current and actively pipelined transactions, and
186 * should halt within 16 ms of the run/stop bit being cleared.
187 * Read controller Halted bit in the status register to see when the
188 * controller is finished.
189 */
190int cdnsp_halt(struct cdnsp_device *pdev)
191{
192 int ret;
193 u32 val;
194
195 cdnsp_quiesce(pdev);
196
197 ret = readl_poll_timeout_atomic(&pdev->op_regs->status, val,
198 val & STS_HALT, 1,
199 CDNSP_MAX_HALT_USEC);
200 if (ret) {
201 dev_err(pdev->dev, "ERROR: Device halt failed\n");
202 return ret;
203 }
204
205 pdev->cdnsp_state |= CDNSP_STATE_HALTED;
206
207 return 0;
208}
209
210/*
211 * device controller died, register read returns 0xffffffff, or command never
212 * ends.
213 */
214void cdnsp_died(struct cdnsp_device *pdev)
215{
216 dev_err(pdev->dev, "ERROR: CDNSP controller not responding\n");
217 pdev->cdnsp_state |= CDNSP_STATE_DYING;
218 cdnsp_halt(pdev);
219}
220
221/*
222 * Set the run bit and wait for the device to be running.
223 */
224static int cdnsp_start(struct cdnsp_device *pdev)
225{
226 u32 temp;
227 int ret;
228
229 temp = readl(&pdev->op_regs->command);
230 temp |= (CMD_R_S | CMD_DEVEN);
231 writel(temp, &pdev->op_regs->command);
232
233 pdev->cdnsp_state = 0;
234
235 /*
236 * Wait for the STS_HALT Status bit to be 0 to indicate the device is
237 * running.
238 */
239 ret = readl_poll_timeout_atomic(&pdev->op_regs->status, temp,
240 !(temp & STS_HALT), 1,
241 CDNSP_MAX_HALT_USEC);
242 if (ret) {
243 pdev->cdnsp_state = CDNSP_STATE_DYING;
244 dev_err(pdev->dev, "ERROR: Controller run failed\n");
245 }
246
247 return ret;
248}
249
250/*
251 * Reset a halted controller.
252 *
253 * This resets pipelines, timers, counters, state machines, etc.
254 * Transactions will be terminated immediately, and operational registers
255 * will be set to their defaults.
256 */
257int cdnsp_reset(struct cdnsp_device *pdev)
258{
259 u32 command;
260 u32 temp;
261 int ret;
262
263 temp = readl(&pdev->op_regs->status);
264
265 if (temp == ~(u32)0) {
266 dev_err(pdev->dev, "Device not accessible, reset failed.\n");
267 return -ENODEV;
268 }
269
270 if ((temp & STS_HALT) == 0) {
271 dev_err(pdev->dev, "Controller not halted, aborting reset.\n");
272 return -EINVAL;
273 }
274
275 command = readl(&pdev->op_regs->command);
276 command |= CMD_RESET;
277 writel(command, &pdev->op_regs->command);
278
279 ret = readl_poll_timeout_atomic(&pdev->op_regs->command, temp,
280 !(temp & CMD_RESET), 1,
281 10 * 1000);
282 if (ret) {
283 dev_err(pdev->dev, "ERROR: Controller reset failed\n");
284 return ret;
285 }
286
287 /*
288 * CDNSP cannot write any doorbells or operational registers other
289 * than status until the "Controller Not Ready" flag is cleared.
290 */
291 ret = readl_poll_timeout_atomic(&pdev->op_regs->status, temp,
292 !(temp & STS_CNR), 1,
293 10 * 1000);
294
295 if (ret) {
296 dev_err(pdev->dev, "ERROR: Controller not ready to work\n");
297 return ret;
298 }
299
300 dev_dbg(pdev->dev, "Controller ready to work");
301
302 return ret;
303}
304
305/*
306 * cdnsp_get_endpoint_index - Find the index for an endpoint given its
307 * descriptor.Use the return value to right shift 1 for the bitmask.
308 *
309 * Index = (epnum * 2) + direction - 1,
310 * where direction = 0 for OUT, 1 for IN.
311 * For control endpoints, the IN index is used (OUT index is unused), so
312 * index = (epnum * 2) + direction - 1 = (epnum * 2) + 1 - 1 = (epnum * 2)
313 */
314static unsigned int
315 cdnsp_get_endpoint_index(const struct usb_endpoint_descriptor *desc)
316{
317 unsigned int index = (unsigned int)usb_endpoint_num(desc);
318
319 if (usb_endpoint_xfer_control(desc))
320 return index * 2;
321
322 return (index * 2) + (usb_endpoint_dir_in(desc) ? 1 : 0) - 1;
323}
324
325/*
326 * Find the flag for this endpoint (for use in the control context). Use the
327 * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
328 * bit 1, etc.
329 */
330static unsigned int
331 cdnsp_get_endpoint_flag(const struct usb_endpoint_descriptor *desc)
332{
333 return 1 << (cdnsp_get_endpoint_index(desc) + 1);
334}
335
336int cdnsp_ep_enqueue(struct cdnsp_ep *pep, struct cdnsp_request *preq)
337{
338 struct cdnsp_device *pdev = pep->pdev;
339 struct usb_request *request;
340 int ret;
341
342 if (preq->epnum == 0 && !list_empty(&pep->pending_list))
343 return -EBUSY;
344
345 request = &preq->request;
346 request->actual = 0;
347 request->status = -EINPROGRESS;
348 preq->direction = pep->direction;
349 preq->epnum = pep->number;
350 preq->td.drbl = 0;
351
352 ret = usb_gadget_map_request_by_dev(pdev->dev, request, pep->direction);
353 if (ret)
354 return ret;
355
356 list_add_tail(&preq->list, &pep->pending_list);
357
358 switch (usb_endpoint_type(pep->endpoint.desc)) {
359 case USB_ENDPOINT_XFER_CONTROL:
360 ret = cdnsp_queue_ctrl_tx(pdev, preq);
361 break;
362 case USB_ENDPOINT_XFER_BULK:
363 case USB_ENDPOINT_XFER_INT:
364 ret = cdnsp_queue_bulk_tx(pdev, preq);
365 break;
366 case USB_ENDPOINT_XFER_ISOC:
367 ret = cdnsp_queue_isoc_tx_prepare(pdev, preq);
368 }
369
370 if (ret)
371 goto unmap;
372
373 return 0;
374
375unmap:
376 usb_gadget_unmap_request_by_dev(pdev->dev, &preq->request,
377 pep->direction);
378 list_del(&preq->list);
379
380 return ret;
381}
382
383/*
384 * Remove the request's TD from the endpoint ring. This may cause the
385 * controller to stop USB transfers, potentially stopping in the middle of a
386 * TRB buffer. The controller should pick up where it left off in the TD,
387 * unless a Set Transfer Ring Dequeue Pointer is issued.
388 *
389 * The TRBs that make up the buffers for the canceled request will be "removed"
390 * from the ring. Since the ring is a contiguous structure, they can't be
391 * physically removed. Instead, there are two options:
392 *
393 * 1) If the controller is in the middle of processing the request to be
394 * canceled, we simply move the ring's dequeue pointer past those TRBs
395 * using the Set Transfer Ring Dequeue Pointer command. This will be
396 * the common case, when drivers timeout on the last submitted request
397 * and attempt to cancel.
398 *
399 * 2) If the controller is in the middle of a different TD, we turn the TRBs
400 * into a series of 1-TRB transfer no-op TDs. No-ops shouldn't be chained.
401 * The controller will need to invalidate the any TRBs it has cached after
402 * the stop endpoint command.
403 *
404 * 3) The TD may have completed by the time the Stop Endpoint Command
405 * completes, so software needs to handle that case too.
406 *
407 */
408int cdnsp_ep_dequeue(struct cdnsp_ep *pep, struct cdnsp_request *preq)
409{
410 struct cdnsp_device *pdev = pep->pdev;
411 int ret;
412
413 if (GET_EP_CTX_STATE(pep->out_ctx) == EP_STATE_RUNNING) {
414 ret = cdnsp_cmd_stop_ep(pdev, pep);
415 if (ret)
416 return ret;
417 }
418
419 return cdnsp_remove_request(pdev, preq, pep);
420}
421
422static void cdnsp_zero_in_ctx(struct cdnsp_device *pdev)
423{
424 struct cdnsp_input_control_ctx *ctrl_ctx;
425 struct cdnsp_slot_ctx *slot_ctx;
426 struct cdnsp_ep_ctx *ep_ctx;
427 int i;
428
429 ctrl_ctx = cdnsp_get_input_control_ctx(&pdev->in_ctx);
430
431 /*
432 * When a device's add flag and drop flag are zero, any subsequent
433 * configure endpoint command will leave that endpoint's state
434 * untouched. Make sure we don't leave any old state in the input
435 * endpoint contexts.
436 */
437 ctrl_ctx->drop_flags = 0;
438 ctrl_ctx->add_flags = 0;
439 slot_ctx = cdnsp_get_slot_ctx(&pdev->in_ctx);
440 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
441
442 /* Endpoint 0 is always valid */
443 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1));
444 for (i = 1; i < CDNSP_ENDPOINTS_NUM; ++i) {
445 ep_ctx = cdnsp_get_ep_ctx(&pdev->in_ctx, i);
446 ep_ctx->ep_info = 0;
447 ep_ctx->ep_info2 = 0;
448 ep_ctx->deq = 0;
449 ep_ctx->tx_info = 0;
450 }
451}
452
453/* Issue a configure endpoint command and wait for it to finish. */
454static int cdnsp_configure_endpoint(struct cdnsp_device *pdev)
455{
456 int ret;
457
458 cdnsp_queue_configure_endpoint(pdev, pdev->cmd.in_ctx->dma);
459 cdnsp_ring_cmd_db(pdev);
460 ret = cdnsp_wait_for_cmd_compl(pdev);
461 if (ret) {
462 dev_err(pdev->dev,
463 "ERR: unexpected command completion code 0x%x.\n", ret);
464 return -EINVAL;
465 }
466
467 return ret;
468}
469
470static void cdnsp_invalidate_ep_events(struct cdnsp_device *pdev,
471 struct cdnsp_ep *pep)
472{
473 struct cdnsp_segment *segment;
474 union cdnsp_trb *event;
475 u32 cycle_state;
476 __le32 data;
477
478 event = pdev->event_ring->dequeue;
479 segment = pdev->event_ring->deq_seg;
480 cycle_state = pdev->event_ring->cycle_state;
481
482 while (1) {
483 data = le32_to_cpu(event->trans_event.flags);
484
485 /* Check the owner of the TRB. */
486 if ((data & TRB_CYCLE) != cycle_state)
487 break;
488
489 if (TRB_FIELD_TO_TYPE(data) == TRB_TRANSFER &&
490 TRB_TO_EP_ID(data) == (pep->idx + 1)) {
491 data |= TRB_EVENT_INVALIDATE;
492 event->trans_event.flags = cpu_to_le32(data);
493 }
494
495 if (cdnsp_last_trb_on_seg(segment, event)) {
496 cycle_state ^= 1;
497 segment = pdev->event_ring->deq_seg->next;
498 event = segment->trbs;
499 } else {
500 event++;
501 }
502 }
503}
504
505int cdnsp_wait_for_cmd_compl(struct cdnsp_device *pdev)
506{
507 struct cdnsp_segment *event_deq_seg;
508 union cdnsp_trb *cmd_trb;
509 dma_addr_t cmd_deq_dma;
510 union cdnsp_trb *event;
511 u32 cycle_state;
512 __le32 flags;
513 int ret, val;
514 u64 cmd_dma;
515
516 cmd_trb = pdev->cmd.command_trb;
517 pdev->cmd.status = 0;
518
519 ret = readl_poll_timeout_atomic(&pdev->op_regs->cmd_ring, val,
520 !CMD_RING_BUSY(val), 1,
521 CDNSP_CMD_TIMEOUT);
522 if (ret) {
523 dev_err(pdev->dev, "ERR: Timeout while waiting for command\n");
524 pdev->cdnsp_state = CDNSP_STATE_DYING;
525 return -ETIMEDOUT;
526 }
527
528 event = pdev->event_ring->dequeue;
529 event_deq_seg = pdev->event_ring->deq_seg;
530 cycle_state = pdev->event_ring->cycle_state;
531
532 cmd_deq_dma = cdnsp_trb_virt_to_dma(pdev->cmd_ring->deq_seg, cmd_trb);
533 if (!cmd_deq_dma)
534 return -EINVAL;
535
536 while (1) {
537 flags = le32_to_cpu(event->event_cmd.flags);
538
539 /* Check the owner of the TRB. */
540 if ((flags & TRB_CYCLE) != cycle_state)
541 return -EINVAL;
542
543 cmd_dma = le64_to_cpu(event->event_cmd.cmd_trb);
544
545 /*
546 * Check whether the completion event is for last queued
547 * command.
548 */
549 if (TRB_FIELD_TO_TYPE(flags) != TRB_COMPLETION ||
550 cmd_dma != (u64)cmd_deq_dma) {
551 if (!cdnsp_last_trb_on_seg(event_deq_seg, event)) {
552 event++;
553 continue;
554 }
555
556 if (cdnsp_last_trb_on_ring(pdev->event_ring,
557 event_deq_seg, event))
558 cycle_state ^= 1;
559
560 event_deq_seg = event_deq_seg->next;
561 event = event_deq_seg->trbs;
562 continue;
563 }
564
565 pdev->cmd.status = GET_COMP_CODE(le32_to_cpu(event->event_cmd.status));
566 if (pdev->cmd.status == COMP_SUCCESS)
567 return 0;
568
569 return -pdev->cmd.status;
570 }
571}
572
573int cdnsp_halt_endpoint(struct cdnsp_device *pdev,
574 struct cdnsp_ep *pep,
575 int value)
576{
577 int ret;
578
579 if (value) {
580 ret = cdnsp_cmd_stop_ep(pdev, pep);
581 if (ret)
582 return ret;
583
584 if (GET_EP_CTX_STATE(pep->out_ctx) == EP_STATE_STOPPED) {
585 cdnsp_queue_halt_endpoint(pdev, pep->idx);
586 cdnsp_ring_cmd_db(pdev);
587 ret = cdnsp_wait_for_cmd_compl(pdev);
588 }
589
590 pep->ep_state |= EP_HALTED;
591 } else {
592 /*
593 * In device mode driver can call reset endpoint command
594 * from any endpoint state.
595 */
596 cdnsp_queue_reset_ep(pdev, pep->idx);
597 cdnsp_ring_cmd_db(pdev);
598 ret = cdnsp_wait_for_cmd_compl(pdev);
599 if (ret)
600 return ret;
601
602 pep->ep_state &= ~EP_HALTED;
603
604 if (pep->idx != 0 && !(pep->ep_state & EP_WEDGE))
605 cdnsp_ring_doorbell_for_active_rings(pdev, pep);
606
607 pep->ep_state &= ~EP_WEDGE;
608 }
609
610 return 0;
611}
612
613static int cdnsp_update_eps_configuration(struct cdnsp_device *pdev,
614 struct cdnsp_ep *pep)
615{
616 struct cdnsp_input_control_ctx *ctrl_ctx;
617 struct cdnsp_slot_ctx *slot_ctx;
618 int ret = 0;
619 u32 ep_sts;
620 int i;
621
622 ctrl_ctx = cdnsp_get_input_control_ctx(&pdev->in_ctx);
623
624 /* Don't issue the command if there's no endpoints to update. */
625 if (ctrl_ctx->add_flags == 0 && ctrl_ctx->drop_flags == 0)
626 return 0;
627
628 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
629 ctrl_ctx->add_flags &= cpu_to_le32(~EP0_FLAG);
630 ctrl_ctx->drop_flags &= cpu_to_le32(~(SLOT_FLAG | EP0_FLAG));
631
632 /* Fix up Context Entries field. Minimum value is EP0 == BIT(1). */
633 slot_ctx = cdnsp_get_slot_ctx(&pdev->in_ctx);
634 for (i = CDNSP_ENDPOINTS_NUM; i >= 1; i--) {
635 __le32 le32 = cpu_to_le32(BIT(i));
636
637 if ((pdev->eps[i - 1].ring && !(ctrl_ctx->drop_flags & le32)) ||
638 (ctrl_ctx->add_flags & le32) || i == 1) {
639 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
640 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(i));
641 break;
642 }
643 }
644
645 ep_sts = GET_EP_CTX_STATE(pep->out_ctx);
646
647 if ((ctrl_ctx->add_flags != cpu_to_le32(SLOT_FLAG) &&
648 ep_sts == EP_STATE_DISABLED) ||
649 (ep_sts != EP_STATE_DISABLED && ctrl_ctx->drop_flags))
650 ret = cdnsp_configure_endpoint(pdev);
651
652 cdnsp_zero_in_ctx(pdev);
653
654 return ret;
655}
656
657/*
658 * This submits a Reset Device Command, which will set the device state to 0,
659 * set the device address to 0, and disable all the endpoints except the default
660 * control endpoint. The USB core should come back and call
661 * cdnsp_setup_device(), and then re-set up the configuration.
662 */
663int cdnsp_reset_device(struct cdnsp_device *pdev)
664{
665 struct cdnsp_slot_ctx *slot_ctx;
666 int slot_state;
667 int ret, i;
668
669 slot_ctx = cdnsp_get_slot_ctx(&pdev->in_ctx);
670 slot_ctx->dev_info = 0;
671 pdev->device_address = 0;
672
673 /* If device is not setup, there is no point in resetting it. */
674 slot_ctx = cdnsp_get_slot_ctx(&pdev->out_ctx);
675 slot_state = GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state));
676
677 if (slot_state <= SLOT_STATE_DEFAULT &&
678 pdev->eps[0].ep_state & EP_HALTED) {
679 cdnsp_halt_endpoint(pdev, &pdev->eps[0], 0);
680 }
681
682 /*
683 * During Reset Device command controller shall transition the
684 * endpoint ep0 to the Running State.
685 */
686 pdev->eps[0].ep_state &= ~(EP_STOPPED | EP_HALTED);
687 pdev->eps[0].ep_state |= EP_ENABLED;
688
689 if (slot_state <= SLOT_STATE_DEFAULT)
690 return 0;
691
692 cdnsp_queue_reset_device(pdev);
693 cdnsp_ring_cmd_db(pdev);
694 ret = cdnsp_wait_for_cmd_compl(pdev);
695
696 /*
697 * After Reset Device command all not default endpoints
698 * are in Disabled state.
699 */
700 for (i = 1; i < CDNSP_ENDPOINTS_NUM; ++i)
701 pdev->eps[i].ep_state |= EP_STOPPED;
702
703 if (ret)
704 dev_err(pdev->dev, "Reset device failed with error code %d",
705 ret);
706
707 return ret;
708}
709
710/*
711 * Sets the MaxPStreams field and the Linear Stream Array field.
712 * Sets the dequeue pointer to the stream context array.
713 */
714static void cdnsp_setup_streams_ep_input_ctx(struct cdnsp_device *pdev,
715 struct cdnsp_ep_ctx *ep_ctx,
716 struct cdnsp_stream_info *stream_info)
717{
718 u32 max_primary_streams;
719
720 /* MaxPStreams is the number of stream context array entries, not the
721 * number we're actually using. Must be in 2^(MaxPstreams + 1) format.
722 * fls(0) = 0, fls(0x1) = 1, fls(0x10) = 2, fls(0x100) = 3, etc.
723 */
724 max_primary_streams = fls(stream_info->num_stream_ctxs) - 2;
725 ep_ctx->ep_info &= cpu_to_le32(~EP_MAXPSTREAMS_MASK);
726 ep_ctx->ep_info |= cpu_to_le32(EP_MAXPSTREAMS(max_primary_streams)
727 | EP_HAS_LSA);
728 ep_ctx->deq = cpu_to_le64(stream_info->ctx_array_dma);
729}
730
731/*
732 * The drivers use this function to prepare a bulk endpoints to use streams.
733 *
734 * Don't allow the call to succeed if endpoint only supports one stream
735 * (which means it doesn't support streams at all).
736 */
737int cdnsp_alloc_streams(struct cdnsp_device *pdev, struct cdnsp_ep *pep)
738{
739 unsigned int num_streams = usb_ss_max_streams(pep->endpoint.comp_desc);
740 unsigned int num_stream_ctxs;
741 int ret;
742
743 if (num_streams == 0)
744 return 0;
745
746 if (num_streams > STREAM_NUM_STREAMS)
747 return -EINVAL;
748
749 /*
750 * Add two to the number of streams requested to account for
751 * stream 0 that is reserved for controller usage and one additional
752 * for TASK SET FULL response.
753 */
754 num_streams += 2;
755
756 /* The stream context array size must be a power of two */
757 num_stream_ctxs = roundup_pow_of_two(num_streams);
758
759 ret = cdnsp_alloc_stream_info(pdev, pep, num_stream_ctxs, num_streams);
760 if (ret)
761 return ret;
762
763 cdnsp_setup_streams_ep_input_ctx(pdev, pep->in_ctx, &pep->stream_info);
764
765 pep->ep_state |= EP_HAS_STREAMS;
766 pep->stream_info.td_count = 0;
767 pep->stream_info.first_prime_det = 0;
768
769 /* Subtract 1 for stream 0, which drivers can't use. */
770 return num_streams - 1;
771}
772
773int cdnsp_disable_slot(struct cdnsp_device *pdev)
774{
775 int ret;
776
777 cdnsp_queue_slot_control(pdev, TRB_DISABLE_SLOT);
778 cdnsp_ring_cmd_db(pdev);
779 ret = cdnsp_wait_for_cmd_compl(pdev);
780
781 pdev->slot_id = 0;
782 pdev->active_port = NULL;
783
784 memset(pdev->in_ctx.bytes, 0, CDNSP_CTX_SIZE);
785 memset(pdev->out_ctx.bytes, 0, CDNSP_CTX_SIZE);
786
787 return ret;
788}
789
790int cdnsp_enable_slot(struct cdnsp_device *pdev)
791{
792 struct cdnsp_slot_ctx *slot_ctx;
793 int slot_state;
794 int ret;
795
796 /* If device is not setup, there is no point in resetting it */
797 slot_ctx = cdnsp_get_slot_ctx(&pdev->out_ctx);
798 slot_state = GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state));
799
800 if (slot_state != SLOT_STATE_DISABLED)
801 return 0;
802
803 cdnsp_queue_slot_control(pdev, TRB_ENABLE_SLOT);
804 cdnsp_ring_cmd_db(pdev);
805 ret = cdnsp_wait_for_cmd_compl(pdev);
806 if (ret)
807 return ret;
808
809 pdev->slot_id = 1;
810
811 return 0;
812}
813
814/*
815 * Issue an Address Device command with BSR=0 if setup is SETUP_CONTEXT_ONLY
816 * or with BSR = 1 if set_address is SETUP_CONTEXT_ADDRESS.
817 */
818int cdnsp_setup_device(struct cdnsp_device *pdev, enum cdnsp_setup_dev setup)
819{
820 struct cdnsp_input_control_ctx *ctrl_ctx;
821 struct cdnsp_slot_ctx *slot_ctx;
822 int dev_state = 0;
823 int ret;
824
825 if (!pdev->slot_id)
826 return -EINVAL;
827
828 if (!pdev->active_port->port_num)
829 return -EINVAL;
830
831 slot_ctx = cdnsp_get_slot_ctx(&pdev->out_ctx);
832 dev_state = GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state));
833
834 if (setup == SETUP_CONTEXT_ONLY && dev_state == SLOT_STATE_DEFAULT)
835 return 0;
836
837 slot_ctx = cdnsp_get_slot_ctx(&pdev->in_ctx);
838 ctrl_ctx = cdnsp_get_input_control_ctx(&pdev->in_ctx);
839
840 if (!slot_ctx->dev_info || dev_state == SLOT_STATE_DEFAULT) {
841 ret = cdnsp_setup_addressable_priv_dev(pdev);
842 if (ret)
843 return ret;
844 }
845
846 cdnsp_copy_ep0_dequeue_into_input_ctx(pdev);
847
848 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG | EP0_FLAG);
849 ctrl_ctx->drop_flags = 0;
850
851 cdnsp_queue_address_device(pdev, pdev->in_ctx.dma, setup);
852 cdnsp_ring_cmd_db(pdev);
853 ret = cdnsp_wait_for_cmd_compl(pdev);
854
855 /* Zero the input context control for later use. */
856 ctrl_ctx->add_flags = 0;
857 ctrl_ctx->drop_flags = 0;
858
859 return ret;
860}
861
862void cdnsp_set_usb2_hardware_lpm(struct cdnsp_device *pdev,
863 struct usb_request *req,
864 int enable)
865{
866 if (pdev->active_port != &pdev->usb2_port || !pdev->gadget.lpm_capable)
867 return;
868
869 if (enable)
870 writel(PORT_BESL(CDNSP_DEFAULT_BESL) | PORT_L1S_NYET | PORT_HLE,
871 &pdev->active_port->regs->portpmsc);
872 else
873 writel(PORT_L1S_NYET, &pdev->active_port->regs->portpmsc);
874}
875
876static int cdnsp_get_frame(struct cdnsp_device *pdev)
877{
878 return readl(&pdev->run_regs->microframe_index) >> 3;
879}
880
881static int cdnsp_gadget_ep_enable(struct usb_ep *ep,
882 const struct usb_endpoint_descriptor *desc)
883{
884 struct cdnsp_input_control_ctx *ctrl_ctx;
885 struct cdnsp_device *pdev;
886 struct cdnsp_ep *pep;
887 unsigned long flags;
888 u32 added_ctxs;
889 int ret;
890
891 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT ||
892 !desc->wMaxPacketSize)
893 return -EINVAL;
894
895 pep = to_cdnsp_ep(ep);
896 pdev = pep->pdev;
897
898 if (dev_WARN_ONCE(pdev->dev, pep->ep_state & EP_ENABLED,
899 "%s is already enabled\n", pep->name))
900 return 0;
901
902 spin_lock_irqsave(&pdev->lock, flags);
903
904 added_ctxs = cdnsp_get_endpoint_flag(desc);
905 if (added_ctxs == SLOT_FLAG || added_ctxs == EP0_FLAG) {
906 dev_err(pdev->dev, "ERROR: Bad endpoint number\n");
907 ret = -EINVAL;
908 goto unlock;
909 }
910
911 pep->interval = desc->bInterval ? BIT(desc->bInterval - 1) : 0;
912
913 if (pdev->gadget.speed == USB_SPEED_FULL) {
914 if (usb_endpoint_type(desc) == USB_ENDPOINT_XFER_INT)
915 pep->interval = desc->bInterval << 3;
916 if (usb_endpoint_type(desc) == USB_ENDPOINT_XFER_ISOC)
917 pep->interval = BIT(desc->bInterval - 1) << 3;
918 }
919
920 if (usb_endpoint_type(desc) == USB_ENDPOINT_XFER_ISOC) {
921 if (pep->interval > BIT(12)) {
922 dev_err(pdev->dev, "bInterval %d not supported\n",
923 desc->bInterval);
924 ret = -EINVAL;
925 goto unlock;
926 }
927 cdnsp_set_chicken_bits_2(pdev, CHICKEN_XDMA_2_TP_CACHE_DIS);
928 }
929
930 ret = cdnsp_endpoint_init(pdev, pep, GFP_ATOMIC);
931 if (ret)
932 goto unlock;
933
934 ctrl_ctx = cdnsp_get_input_control_ctx(&pdev->in_ctx);
935 ctrl_ctx->add_flags = cpu_to_le32(added_ctxs);
936 ctrl_ctx->drop_flags = 0;
937
938 ret = cdnsp_update_eps_configuration(pdev, pep);
939 if (ret) {
940 cdnsp_free_endpoint_rings(pdev, pep);
941 goto unlock;
942 }
943
944 pep->ep_state |= EP_ENABLED;
945 pep->ep_state &= ~EP_STOPPED;
946
947unlock:
948 spin_unlock_irqrestore(&pdev->lock, flags);
949
950 return ret;
951}
952
953static int cdnsp_gadget_ep_disable(struct usb_ep *ep)
954{
955 struct cdnsp_input_control_ctx *ctrl_ctx;
956 struct cdnsp_request *preq;
957 struct cdnsp_device *pdev;
958 struct cdnsp_ep *pep;
959 unsigned long flags;
960 u32 drop_flag;
961 int ret = 0;
962
963 if (!ep)
964 return -EINVAL;
965
966 pep = to_cdnsp_ep(ep);
967 pdev = pep->pdev;
968
969 spin_lock_irqsave(&pdev->lock, flags);
970
971 if (!(pep->ep_state & EP_ENABLED)) {
972 dev_err(pdev->dev, "%s is already disabled\n", pep->name);
973 ret = -EINVAL;
974 goto finish;
975 }
976
977 cdnsp_cmd_stop_ep(pdev, pep);
978 pep->ep_state |= EP_DIS_IN_RROGRESS;
979 cdnsp_cmd_flush_ep(pdev, pep);
980
981 /* Remove all queued USB requests. */
982 while (!list_empty(&pep->pending_list)) {
983 preq = next_request(&pep->pending_list);
984 cdnsp_ep_dequeue(pep, preq);
985 }
986
987 cdnsp_invalidate_ep_events(pdev, pep);
988
989 pep->ep_state &= ~EP_DIS_IN_RROGRESS;
990 drop_flag = cdnsp_get_endpoint_flag(pep->endpoint.desc);
991 ctrl_ctx = cdnsp_get_input_control_ctx(&pdev->in_ctx);
992 ctrl_ctx->drop_flags = cpu_to_le32(drop_flag);
993 ctrl_ctx->add_flags = 0;
994
995 cdnsp_endpoint_zero(pdev, pep);
996
997 ret = cdnsp_update_eps_configuration(pdev, pep);
998 cdnsp_free_endpoint_rings(pdev, pep);
999
1000 pep->ep_state &= ~EP_ENABLED;
1001 pep->ep_state |= EP_STOPPED;
1002
1003finish:
1004 spin_unlock_irqrestore(&pdev->lock, flags);
1005
1006 return ret;
1007}
1008
1009static struct usb_request *cdnsp_gadget_ep_alloc_request(struct usb_ep *ep,
1010 gfp_t gfp_flags)
1011{
1012 struct cdnsp_ep *pep = to_cdnsp_ep(ep);
1013 struct cdnsp_request *preq;
1014
1015 preq = kzalloc(sizeof(*preq), gfp_flags);
1016 if (!preq)
1017 return NULL;
1018
1019 preq->epnum = pep->number;
1020 preq->pep = pep;
1021
1022 return &preq->request;
1023}
1024
1025static void cdnsp_gadget_ep_free_request(struct usb_ep *ep,
1026 struct usb_request *request)
1027{
1028 struct cdnsp_request *preq = to_cdnsp_request(request);
1029
1030 kfree(preq);
1031}
1032
1033static int cdnsp_gadget_ep_queue(struct usb_ep *ep,
1034 struct usb_request *request,
1035 gfp_t gfp_flags)
1036{
1037 struct cdnsp_request *preq;
1038 struct cdnsp_device *pdev;
1039 struct cdnsp_ep *pep;
1040 unsigned long flags;
1041 int ret;
1042
1043 if (!request || !ep)
1044 return -EINVAL;
1045
1046 pep = to_cdnsp_ep(ep);
1047 pdev = pep->pdev;
1048
1049 if (!(pep->ep_state & EP_ENABLED)) {
1050 dev_err(pdev->dev, "%s: can't queue to disabled endpoint\n",
1051 pep->name);
1052 return -EINVAL;
1053 }
1054
1055 preq = to_cdnsp_request(request);
1056 spin_lock_irqsave(&pdev->lock, flags);
1057 ret = cdnsp_ep_enqueue(pep, preq);
1058 spin_unlock_irqrestore(&pdev->lock, flags);
1059
1060 return ret;
1061}
1062
1063static int cdnsp_gadget_ep_dequeue(struct usb_ep *ep,
1064 struct usb_request *request)
1065{
1066 struct cdnsp_ep *pep = to_cdnsp_ep(ep);
1067 struct cdnsp_device *pdev = pep->pdev;
1068 unsigned long flags;
1069 int ret;
1070
1071 if (!pep->endpoint.desc) {
1072 dev_err(pdev->dev,
1073 "%s: can't dequeue to disabled endpoint\n",
1074 pep->name);
1075 return -ESHUTDOWN;
1076 }
1077
1078 spin_lock_irqsave(&pdev->lock, flags);
1079 ret = cdnsp_ep_dequeue(pep, to_cdnsp_request(request));
1080 spin_unlock_irqrestore(&pdev->lock, flags);
1081
1082 return ret;
1083}
1084
1085static int cdnsp_gadget_ep_set_halt(struct usb_ep *ep, int value)
1086{
1087 struct cdnsp_ep *pep = to_cdnsp_ep(ep);
1088 struct cdnsp_device *pdev = pep->pdev;
1089 struct cdnsp_request *preq;
1090 unsigned long flags = 0;
1091 int ret;
1092
1093 spin_lock_irqsave(&pdev->lock, flags);
1094
1095 preq = next_request(&pep->pending_list);
1096 if (value) {
1097 if (preq) {
1098 ret = -EAGAIN;
1099 goto done;
1100 }
1101 }
1102
1103 ret = cdnsp_halt_endpoint(pdev, pep, value);
1104
1105done:
1106 spin_unlock_irqrestore(&pdev->lock, flags);
1107 return ret;
1108}
1109
1110static int cdnsp_gadget_ep_set_wedge(struct usb_ep *ep)
1111{
1112 struct cdnsp_ep *pep = to_cdnsp_ep(ep);
1113 struct cdnsp_device *pdev = pep->pdev;
1114 unsigned long flags = 0;
1115 int ret;
1116
1117 spin_lock_irqsave(&pdev->lock, flags);
1118 pep->ep_state |= EP_WEDGE;
1119 ret = cdnsp_halt_endpoint(pdev, pep, 1);
1120 spin_unlock_irqrestore(&pdev->lock, flags);
1121
1122 return ret;
1123}
1124
1125static const struct usb_ep_ops cdnsp_gadget_ep0_ops = {
1126 .enable = cdnsp_gadget_ep_enable,
1127 .disable = cdnsp_gadget_ep_disable,
1128 .alloc_request = cdnsp_gadget_ep_alloc_request,
1129 .free_request = cdnsp_gadget_ep_free_request,
1130 .queue = cdnsp_gadget_ep_queue,
1131 .dequeue = cdnsp_gadget_ep_dequeue,
1132 .set_halt = cdnsp_gadget_ep_set_halt,
1133 .set_wedge = cdnsp_gadget_ep_set_wedge,
1134};
1135
1136static const struct usb_ep_ops cdnsp_gadget_ep_ops = {
1137 .enable = cdnsp_gadget_ep_enable,
1138 .disable = cdnsp_gadget_ep_disable,
1139 .alloc_request = cdnsp_gadget_ep_alloc_request,
1140 .free_request = cdnsp_gadget_ep_free_request,
1141 .queue = cdnsp_gadget_ep_queue,
1142 .dequeue = cdnsp_gadget_ep_dequeue,
1143 .set_halt = cdnsp_gadget_ep_set_halt,
1144 .set_wedge = cdnsp_gadget_ep_set_wedge,
1145};
1146
1147void cdnsp_gadget_giveback(struct cdnsp_ep *pep,
1148 struct cdnsp_request *preq,
1149 int status)
1150{
1151 struct cdnsp_device *pdev = pep->pdev;
1152
1153 list_del(&preq->list);
1154
1155 if (preq->request.status == -EINPROGRESS)
1156 preq->request.status = status;
1157
1158 usb_gadget_unmap_request_by_dev(pdev->dev, &preq->request,
1159 preq->direction);
1160
1161 if (preq != &pdev->ep0_preq) {
1162 spin_unlock(&pdev->lock);
1163 usb_gadget_giveback_request(&pep->endpoint, &preq->request);
1164 spin_lock(&pdev->lock);
1165 }
1166}
1167
1168static struct usb_endpoint_descriptor cdnsp_gadget_ep0_desc = {
1169 .bLength = USB_DT_ENDPOINT_SIZE,
1170 .bDescriptorType = USB_DT_ENDPOINT,
1171 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
1172};
1173
1174static int cdnsp_run(struct cdnsp_device *pdev,
1175 enum usb_device_speed speed)
1176{
1177 u32 fs_speed = 0;
1178 u64 temp_64;
1179 u32 temp;
1180 int ret;
1181
1182 temp_64 = cdnsp_read_64(&pdev->ir_set->erst_dequeue);
1183 temp_64 &= ~ERST_PTR_MASK;
1184 temp = readl(&pdev->ir_set->irq_control);
1185 temp &= ~IMOD_INTERVAL_MASK;
1186 temp |= ((IMOD_DEFAULT_INTERVAL / 250) & IMOD_INTERVAL_MASK);
1187 writel(temp, &pdev->ir_set->irq_control);
1188
1189 temp = readl(&pdev->port3x_regs->mode_addr);
1190
1191 switch (speed) {
1192 case USB_SPEED_SUPER_PLUS:
1193 temp |= CFG_3XPORT_SSP_SUPPORT;
1194 break;
1195 case USB_SPEED_SUPER:
1196 temp &= ~CFG_3XPORT_SSP_SUPPORT;
1197 break;
1198 case USB_SPEED_HIGH:
1199 break;
1200 case USB_SPEED_FULL:
1201 fs_speed = PORT_REG6_FORCE_FS;
1202 break;
1203 default:
1204 dev_err(pdev->dev, "invalid maximum_speed parameter %d\n",
1205 speed);
1206 fallthrough;
1207 case USB_SPEED_UNKNOWN:
1208 /* Default to superspeed. */
1209 speed = USB_SPEED_SUPER;
1210 break;
1211 }
1212
1213 if (speed >= USB_SPEED_SUPER) {
1214 writel(temp, &pdev->port3x_regs->mode_addr);
1215 cdnsp_set_link_state(pdev, &pdev->usb3_port.regs->portsc,
1216 XDEV_RXDETECT);
1217 } else {
1218 cdnsp_disable_port(pdev, &pdev->usb3_port.regs->portsc);
1219 }
1220
1221 cdnsp_set_link_state(pdev, &pdev->usb2_port.regs->portsc,
1222 XDEV_RXDETECT);
1223
1224 cdnsp_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1225
1226 writel(PORT_REG6_L1_L0_HW_EN | fs_speed, &pdev->port20_regs->port_reg6);
1227
1228 ret = cdnsp_start(pdev);
1229 if (ret) {
1230 ret = -ENODEV;
1231 goto err;
1232 }
1233
1234 temp = readl(&pdev->op_regs->command);
1235 temp |= (CMD_INTE);
1236 writel(temp, &pdev->op_regs->command);
1237
1238 temp = readl(&pdev->ir_set->irq_pending);
1239 writel(IMAN_IE_SET(temp), &pdev->ir_set->irq_pending);
1240
1241 return 0;
1242err:
1243 cdnsp_halt(pdev);
1244 return ret;
1245}
1246
1247static int cdnsp_gadget_udc_start(struct usb_gadget *g,
1248 struct usb_gadget_driver *driver)
1249{
1250 enum usb_device_speed max_speed = driver->max_speed;
1251 struct cdnsp_device *pdev = gadget_to_cdnsp(g);
1252 unsigned long flags;
1253 int ret;
1254
1255 spin_lock_irqsave(&pdev->lock, flags);
1256 pdev->gadget_driver = driver;
1257
1258 /* limit speed if necessary */
1259 max_speed = min(driver->max_speed, g->max_speed);
1260 ret = cdnsp_run(pdev, max_speed);
1261
1262 spin_unlock_irqrestore(&pdev->lock, flags);
1263
1264 return ret;
1265}
1266
1267/*
1268 * Update Event Ring Dequeue Pointer:
1269 * - When all events have finished
1270 * - To avoid "Event Ring Full Error" condition
1271 */
1272void cdnsp_update_erst_dequeue(struct cdnsp_device *pdev,
1273 union cdnsp_trb *event_ring_deq,
1274 u8 clear_ehb)
1275{
1276 u64 temp_64;
1277 dma_addr_t deq;
1278
1279 temp_64 = cdnsp_read_64(&pdev->ir_set->erst_dequeue);
1280
1281 /* If necessary, update the HW's version of the event ring deq ptr. */
1282 if (event_ring_deq != pdev->event_ring->dequeue) {
1283 deq = cdnsp_trb_virt_to_dma(pdev->event_ring->deq_seg,
1284 pdev->event_ring->dequeue);
1285 temp_64 &= ERST_PTR_MASK;
1286 temp_64 |= ((u64)deq & (u64)~ERST_PTR_MASK);
1287 }
1288
1289 /* Clear the event handler busy flag (RW1C). */
1290 if (clear_ehb)
1291 temp_64 |= ERST_EHB;
1292 else
1293 temp_64 &= ~ERST_EHB;
1294
1295 cdnsp_write_64(temp_64, &pdev->ir_set->erst_dequeue);
1296}
1297
1298static void cdnsp_clear_cmd_ring(struct cdnsp_device *pdev)
1299{
1300 struct cdnsp_segment *seg;
1301 u64 val_64;
1302 int i;
1303
1304 cdnsp_initialize_ring_info(pdev->cmd_ring);
1305
1306 seg = pdev->cmd_ring->first_seg;
1307 for (i = 0; i < pdev->cmd_ring->num_segs; i++) {
1308 memset(seg->trbs, 0,
1309 sizeof(union cdnsp_trb) * (TRBS_PER_SEGMENT - 1));
1310 seg = seg->next;
1311 }
1312
1313 /* Set the address in the Command Ring Control register. */
1314 val_64 = cdnsp_read_64(&pdev->op_regs->cmd_ring);
1315 val_64 = (val_64 & (u64)CMD_RING_RSVD_BITS) |
1316 (pdev->cmd_ring->first_seg->dma & (u64)~CMD_RING_RSVD_BITS) |
1317 pdev->cmd_ring->cycle_state;
1318 cdnsp_write_64(val_64, &pdev->op_regs->cmd_ring);
1319}
1320
1321static void cdnsp_consume_all_events(struct cdnsp_device *pdev)
1322{
1323 struct cdnsp_segment *event_deq_seg;
1324 union cdnsp_trb *event_ring_deq;
1325 union cdnsp_trb *event;
1326 u32 cycle_bit;
1327
1328 event_ring_deq = pdev->event_ring->dequeue;
1329 event_deq_seg = pdev->event_ring->deq_seg;
1330 event = pdev->event_ring->dequeue;
1331
1332 /* Update ring dequeue pointer. */
1333 while (1) {
1334 cycle_bit = (le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE);
1335
1336 /* Does the controller or driver own the TRB? */
1337 if (cycle_bit != pdev->event_ring->cycle_state)
1338 break;
1339
1340 cdnsp_inc_deq(pdev, pdev->event_ring);
1341
1342 if (!cdnsp_last_trb_on_seg(event_deq_seg, event)) {
1343 event++;
1344 continue;
1345 }
1346
1347 if (cdnsp_last_trb_on_ring(pdev->event_ring, event_deq_seg,
1348 event))
1349 cycle_bit ^= 1;
1350
1351 event_deq_seg = event_deq_seg->next;
1352 event = event_deq_seg->trbs;
1353 }
1354
1355 cdnsp_update_erst_dequeue(pdev, event_ring_deq, 1);
1356}
1357
1358static void cdnsp_stop(struct cdnsp_device *pdev)
1359{
1360 u32 temp;
1361
1362 cdnsp_cmd_flush_ep(pdev, &pdev->eps[0]);
1363
1364 /* Remove internally queued request for ep0. */
1365 if (!list_empty(&pdev->eps[0].pending_list)) {
1366 struct cdnsp_request *req;
1367
1368 req = next_request(&pdev->eps[0].pending_list);
1369 if (req == &pdev->ep0_preq)
1370 cdnsp_ep_dequeue(&pdev->eps[0], req);
1371 }
1372
1373 cdnsp_disable_port(pdev, &pdev->usb2_port.regs->portsc);
1374 cdnsp_disable_port(pdev, &pdev->usb3_port.regs->portsc);
1375 cdnsp_disable_slot(pdev);
1376 cdnsp_halt(pdev);
1377
1378 temp = readl(&pdev->op_regs->status);
1379 writel((temp & ~0x1fff) | STS_EINT, &pdev->op_regs->status);
1380 temp = readl(&pdev->ir_set->irq_pending);
1381 writel(IMAN_IE_CLEAR(temp), &pdev->ir_set->irq_pending);
1382
1383 cdnsp_clear_port_change_bit(pdev, &pdev->usb2_port.regs->portsc);
1384 cdnsp_clear_port_change_bit(pdev, &pdev->usb3_port.regs->portsc);
1385
1386 /* Clear interrupt line */
1387 temp = readl(&pdev->ir_set->irq_pending);
1388 temp |= IMAN_IP;
1389 writel(temp, &pdev->ir_set->irq_pending);
1390
1391 cdnsp_consume_all_events(pdev);
1392 cdnsp_clear_cmd_ring(pdev);
1393}
1394
1395/*
1396 * Stop controller.
1397 * This function is called by the gadget core when the driver is removed.
1398 * Disable slot, disable IRQs, and quiesce the controller.
1399 */
1400static int cdnsp_gadget_udc_stop(struct usb_gadget *g)
1401{
1402 struct cdnsp_device *pdev = gadget_to_cdnsp(g);
1403 unsigned long flags;
1404
1405 spin_lock_irqsave(&pdev->lock, flags);
1406 cdnsp_stop(pdev);
1407 pdev->gadget_driver = NULL;
1408 spin_unlock_irqrestore(&pdev->lock, flags);
1409
1410 return 0;
1411}
1412
1413static int cdnsp_gadget_get_frame(struct usb_gadget *g)
1414{
1415 struct cdnsp_device *pdev = gadget_to_cdnsp(g);
1416
1417 return cdnsp_get_frame(pdev);
1418}
1419
1420static void __cdnsp_gadget_wakeup(struct cdnsp_device *pdev)
1421{
1422 struct cdnsp_port_regs __iomem *port_regs;
1423 u32 portpm, portsc;
1424
1425 port_regs = pdev->active_port->regs;
1426 portsc = readl(&port_regs->portsc) & PORT_PLS_MASK;
1427
1428 /* Remote wakeup feature is not enabled by host. */
1429 if (pdev->gadget.speed < USB_SPEED_SUPER && portsc == XDEV_U2) {
1430 portpm = readl(&port_regs->portpmsc);
1431
1432 if (!(portpm & PORT_RWE))
1433 return;
1434 }
1435
1436 if (portsc == XDEV_U3 && !pdev->may_wakeup)
1437 return;
1438
1439 cdnsp_set_link_state(pdev, &port_regs->portsc, XDEV_U0);
1440
1441 pdev->cdnsp_state |= CDNSP_WAKEUP_PENDING;
1442}
1443
1444static int cdnsp_gadget_wakeup(struct usb_gadget *g)
1445{
1446 struct cdnsp_device *pdev = gadget_to_cdnsp(g);
1447 unsigned long flags;
1448
1449 spin_lock_irqsave(&pdev->lock, flags);
1450 __cdnsp_gadget_wakeup(pdev);
1451 spin_unlock_irqrestore(&pdev->lock, flags);
1452
1453 return 0;
1454}
1455
1456static int cdnsp_gadget_set_selfpowered(struct usb_gadget *g,
1457 int is_selfpowered)
1458{
1459 struct cdnsp_device *pdev = gadget_to_cdnsp(g);
1460 unsigned long flags;
1461
1462 spin_lock_irqsave(&pdev->lock, flags);
1463 g->is_selfpowered = !!is_selfpowered;
1464 spin_unlock_irqrestore(&pdev->lock, flags);
1465
1466 return 0;
1467}
1468
1469static int cdnsp_gadget_pullup(struct usb_gadget *gadget, int is_on)
1470{
1471 struct cdnsp_device *pdev = gadget_to_cdnsp(gadget);
1472 struct cdns *cdns = dev_get_drvdata(pdev->dev);
1473
1474 if (!is_on) {
1475 cdnsp_reset_device(pdev);
1476 cdns_clear_vbus(cdns);
1477 } else {
1478 cdns_set_vbus(cdns);
1479 }
1480 return 0;
1481}
1482
1483const struct usb_gadget_ops cdnsp_gadget_ops = {
1484 .get_frame = cdnsp_gadget_get_frame,
1485 .wakeup = cdnsp_gadget_wakeup,
1486 .set_selfpowered = cdnsp_gadget_set_selfpowered,
1487 .pullup = cdnsp_gadget_pullup,
1488 .udc_start = cdnsp_gadget_udc_start,
1489 .udc_stop = cdnsp_gadget_udc_stop,
1490};
1491
1492static void cdnsp_get_ep_buffering(struct cdnsp_device *pdev,
1493 struct cdnsp_ep *pep)
1494{
1495 void __iomem *reg = &pdev->cap_regs->hc_capbase;
1496 int endpoints;
1497
1498 reg += cdnsp_find_next_ext_cap(reg, 0, XBUF_CAP_ID);
1499
1500 if (!pep->direction) {
1501 pep->buffering = readl(reg + XBUF_RX_TAG_MASK_0_OFFSET);
1502 pep->buffering_period = readl(reg + XBUF_RX_TAG_MASK_1_OFFSET);
1503 pep->buffering = (pep->buffering + 1) / 2;
1504 pep->buffering_period = (pep->buffering_period + 1) / 2;
1505 return;
1506 }
1507
1508 endpoints = HCS_ENDPOINTS(readl(&pdev->hcs_params1)) / 2;
1509
1510 /* Set to XBUF_TX_TAG_MASK_0 register. */
1511 reg += XBUF_TX_CMD_OFFSET + (endpoints * 2 + 2) * sizeof(u32);
1512 /* Set reg to XBUF_TX_TAG_MASK_N related with this endpoint. */
1513 reg += pep->number * sizeof(u32) * 2;
1514
1515 pep->buffering = (readl(reg) + 1) / 2;
1516 pep->buffering_period = pep->buffering;
1517}
1518
1519static int cdnsp_gadget_init_endpoints(struct cdnsp_device *pdev)
1520{
1521 int max_streams = HCC_MAX_PSA(pdev->hcc_params);
1522 struct cdnsp_ep *pep;
1523 int i;
1524
1525 INIT_LIST_HEAD(&pdev->gadget.ep_list);
1526
1527 if (max_streams < STREAM_LOG_STREAMS) {
1528 dev_err(pdev->dev, "Stream size %d not supported\n",
1529 max_streams);
1530 return -EINVAL;
1531 }
1532
1533 max_streams = STREAM_LOG_STREAMS;
1534
1535 for (i = 0; i < CDNSP_ENDPOINTS_NUM; i++) {
1536 bool direction = !(i & 1); /* Start from OUT endpoint. */
1537 u8 epnum = ((i + 1) >> 1);
1538
1539 if (!CDNSP_IF_EP_EXIST(pdev, epnum, direction))
1540 continue;
1541
1542 pep = &pdev->eps[i];
1543 pep->pdev = pdev;
1544 pep->number = epnum;
1545 pep->direction = direction; /* 0 for OUT, 1 for IN. */
1546
1547 /*
1548 * Ep0 is bidirectional, so ep0in and ep0out are represented by
1549 * pdev->eps[0]
1550 */
1551 if (epnum == 0) {
1552 snprintf(pep->name, sizeof(pep->name), "ep%d%s",
1553 epnum, "BiDir");
1554
1555 pep->idx = 0;
1556 usb_ep_set_maxpacket_limit(&pep->endpoint, 512);
1557 pep->endpoint.maxburst = 1;
1558 pep->endpoint.ops = &cdnsp_gadget_ep0_ops;
1559 pep->endpoint.desc = &cdnsp_gadget_ep0_desc;
1560 pep->endpoint.comp_desc = NULL;
1561 pep->endpoint.caps.type_control = true;
1562 pep->endpoint.caps.dir_in = true;
1563 pep->endpoint.caps.dir_out = true;
1564
1565 pdev->ep0_preq.epnum = pep->number;
1566 pdev->ep0_preq.pep = pep;
1567 pdev->gadget.ep0 = &pep->endpoint;
1568 } else {
1569 snprintf(pep->name, sizeof(pep->name), "ep%d%s",
1570 epnum, (pep->direction) ? "in" : "out");
1571
1572 pep->idx = (epnum * 2 + (direction ? 1 : 0)) - 1;
1573 usb_ep_set_maxpacket_limit(&pep->endpoint, 1024);
1574
1575 pep->endpoint.max_streams = max_streams;
1576 pep->endpoint.ops = &cdnsp_gadget_ep_ops;
1577 list_add_tail(&pep->endpoint.ep_list,
1578 &pdev->gadget.ep_list);
1579
1580 pep->endpoint.caps.type_iso = true;
1581 pep->endpoint.caps.type_bulk = true;
1582 pep->endpoint.caps.type_int = true;
1583
1584 pep->endpoint.caps.dir_in = direction;
1585 pep->endpoint.caps.dir_out = !direction;
1586 }
1587
1588 pep->endpoint.name = pep->name;
1589 pep->in_ctx = cdnsp_get_ep_ctx(&pdev->in_ctx, pep->idx);
1590 pep->out_ctx = cdnsp_get_ep_ctx(&pdev->out_ctx, pep->idx);
1591 cdnsp_get_ep_buffering(pdev, pep);
1592
1593 dev_dbg(pdev->dev, "Init %s, MPS: %04x SupType: "
1594 "CTRL: %s, INT: %s, BULK: %s, ISOC %s, "
1595 "SupDir IN: %s, OUT: %s\n",
1596 pep->name, 1024,
1597 (pep->endpoint.caps.type_control) ? "yes" : "no",
1598 (pep->endpoint.caps.type_int) ? "yes" : "no",
1599 (pep->endpoint.caps.type_bulk) ? "yes" : "no",
1600 (pep->endpoint.caps.type_iso) ? "yes" : "no",
1601 (pep->endpoint.caps.dir_in) ? "yes" : "no",
1602 (pep->endpoint.caps.dir_out) ? "yes" : "no");
1603
1604 INIT_LIST_HEAD(&pep->pending_list);
1605 }
1606
1607 return 0;
1608}
1609
1610static void cdnsp_gadget_free_endpoints(struct cdnsp_device *pdev)
1611{
1612 struct cdnsp_ep *pep;
1613 int i;
1614
1615 for (i = 0; i < CDNSP_ENDPOINTS_NUM; i++) {
1616 pep = &pdev->eps[i];
1617 if (pep->number != 0 && pep->out_ctx)
1618 list_del(&pep->endpoint.ep_list);
1619 }
1620}
1621
1622void cdnsp_disconnect_gadget(struct cdnsp_device *pdev)
1623{
1624 pdev->cdnsp_state |= CDNSP_STATE_DISCONNECT_PENDING;
1625
1626 if (pdev->gadget_driver && pdev->gadget_driver->disconnect) {
1627 spin_unlock(&pdev->lock);
1628 pdev->gadget_driver->disconnect(&pdev->gadget);
1629 spin_lock(&pdev->lock);
1630 }
1631
1632 pdev->gadget.speed = USB_SPEED_UNKNOWN;
1633 usb_gadget_set_state(&pdev->gadget, USB_STATE_NOTATTACHED);
1634
1635 pdev->cdnsp_state &= ~CDNSP_STATE_DISCONNECT_PENDING;
1636}
1637
1638void cdnsp_suspend_gadget(struct cdnsp_device *pdev)
1639{
1640 if (pdev->gadget_driver && pdev->gadget_driver->suspend) {
1641 spin_unlock(&pdev->lock);
1642 pdev->gadget_driver->suspend(&pdev->gadget);
1643 spin_lock(&pdev->lock);
1644 }
1645}
1646
1647void cdnsp_resume_gadget(struct cdnsp_device *pdev)
1648{
1649 if (pdev->gadget_driver && pdev->gadget_driver->resume) {
1650 spin_unlock(&pdev->lock);
1651 pdev->gadget_driver->resume(&pdev->gadget);
1652 spin_lock(&pdev->lock);
1653 }
1654}
1655
1656void cdnsp_irq_reset(struct cdnsp_device *pdev)
1657{
1658 struct cdnsp_port_regs __iomem *port_regs;
1659
1660 cdnsp_reset_device(pdev);
1661
1662 port_regs = pdev->active_port->regs;
1663 pdev->gadget.speed = cdnsp_port_speed(readl(port_regs));
1664
1665 spin_unlock(&pdev->lock);
1666 usb_gadget_udc_reset(&pdev->gadget, pdev->gadget_driver);
1667 spin_lock(&pdev->lock);
1668
1669 switch (pdev->gadget.speed) {
1670 case USB_SPEED_SUPER_PLUS:
1671 case USB_SPEED_SUPER:
1672 cdnsp_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1673 pdev->gadget.ep0->maxpacket = 512;
1674 break;
1675 case USB_SPEED_HIGH:
1676 case USB_SPEED_FULL:
1677 cdnsp_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
1678 pdev->gadget.ep0->maxpacket = 64;
1679 break;
1680 default:
1681 /* Low speed is not supported. */
1682 dev_err(pdev->dev, "Unknown device speed\n");
1683 break;
1684 }
1685
1686 cdnsp_clear_chicken_bits_2(pdev, CHICKEN_XDMA_2_TP_CACHE_DIS);
1687 cdnsp_setup_device(pdev, SETUP_CONTEXT_ONLY);
1688 usb_gadget_set_state(&pdev->gadget, USB_STATE_DEFAULT);
1689}
1690
1691static void cdnsp_get_rev_cap(struct cdnsp_device *pdev)
1692{
1693 void __iomem *reg = &pdev->cap_regs->hc_capbase;
1694 struct cdnsp_rev_cap *rev_cap;
1695
1696 reg += cdnsp_find_next_ext_cap(reg, 0, RTL_REV_CAP);
1697 rev_cap = reg;
1698
1699 pdev->rev_cap.ctrl_revision = readl(&rev_cap->ctrl_revision);
1700 pdev->rev_cap.rtl_revision = readl(&rev_cap->rtl_revision);
1701 pdev->rev_cap.ep_supported = readl(&rev_cap->ep_supported);
1702 pdev->rev_cap.ext_cap = readl(&rev_cap->ext_cap);
1703 pdev->rev_cap.rx_buff_size = readl(&rev_cap->rx_buff_size);
1704 pdev->rev_cap.tx_buff_size = readl(&rev_cap->tx_buff_size);
1705
1706 dev_info(pdev->dev, "Rev: %08x/%08x, eps: %08x, buff: %08x/%08x\n",
1707 pdev->rev_cap.ctrl_revision, pdev->rev_cap.rtl_revision,
1708 pdev->rev_cap.ep_supported, pdev->rev_cap.rx_buff_size,
1709 pdev->rev_cap.tx_buff_size);
1710}
1711
1712static int cdnsp_gen_setup(struct cdnsp_device *pdev)
1713{
1714 int ret;
1715 u32 reg;
1716
1717 pdev->cap_regs = pdev->regs;
1718 pdev->op_regs = pdev->regs +
1719 HC_LENGTH(readl(&pdev->cap_regs->hc_capbase));
1720 pdev->run_regs = pdev->regs +
1721 (readl(&pdev->cap_regs->run_regs_off) & RTSOFF_MASK);
1722
1723 /* Cache read-only capability registers */
1724 pdev->hcs_params1 = readl(&pdev->cap_regs->hcs_params1);
1725 pdev->hcc_params = readl(&pdev->cap_regs->hc_capbase);
1726 pdev->hci_version = HC_VERSION(pdev->hcc_params);
1727 pdev->hcc_params = readl(&pdev->cap_regs->hcc_params);
1728
1729 cdnsp_get_rev_cap(pdev);
1730
1731 /* Make sure the Device Controller is halted. */
1732 ret = cdnsp_halt(pdev);
1733 if (ret)
1734 return ret;
1735
1736 /* Reset the internal controller memory state and registers. */
1737 ret = cdnsp_reset(pdev);
1738 if (ret)
1739 return ret;
1740
1741 /*
1742 * Set dma_mask and coherent_dma_mask to 64-bits,
1743 * if controller supports 64-bit addressing.
1744 */
1745 if (HCC_64BIT_ADDR(pdev->hcc_params) &&
1746 !dma_set_mask(pdev->dev, DMA_BIT_MASK(64))) {
1747 dev_dbg(pdev->dev, "Enabling 64-bit DMA addresses.\n");
1748 dma_set_coherent_mask(pdev->dev, DMA_BIT_MASK(64));
1749 } else {
1750 /*
1751 * This is to avoid error in cases where a 32-bit USB
1752 * controller is used on a 64-bit capable system.
1753 */
1754 ret = dma_set_mask(pdev->dev, DMA_BIT_MASK(32));
1755 if (ret)
1756 return ret;
1757
1758 dev_dbg(pdev->dev, "Enabling 32-bit DMA addresses.\n");
1759 dma_set_coherent_mask(pdev->dev, DMA_BIT_MASK(32));
1760 }
1761
1762 spin_lock_init(&pdev->lock);
1763
1764 ret = cdnsp_mem_init(pdev, GFP_KERNEL);
1765 if (ret)
1766 return ret;
1767
1768 /*
1769 * Software workaround for U1: after transition
1770 * to U1 the controller starts gating clock, and in some cases,
1771 * it causes that controller stack.
1772 */
1773 reg = readl(&pdev->port3x_regs->mode_2);
1774 reg &= ~CFG_3XPORT_U1_PIPE_CLK_GATE_EN;
1775 writel(reg, &pdev->port3x_regs->mode_2);
1776
1777 return 0;
1778}
1779
1780static int __cdnsp_gadget_init(struct cdns *cdns)
1781{
1782 struct cdnsp_device *pdev;
1783 u32 max_speed;
1784 int ret = -ENOMEM;
1785
1786 cdns_drd_gadget_on(cdns);
1787
1788 pdev = kzalloc(sizeof(*pdev), GFP_KERNEL);
1789 if (!pdev)
1790 return -ENOMEM;
1791
1792 pm_runtime_get_sync(cdns->dev);
1793
1794 cdns->gadget_dev = pdev;
1795 pdev->dev = cdns->dev;
1796 pdev->regs = cdns->dev_regs;
1797 max_speed = usb_get_maximum_speed(cdns->dev);
1798
1799 switch (max_speed) {
1800 case USB_SPEED_FULL:
1801 case USB_SPEED_HIGH:
1802 case USB_SPEED_SUPER:
1803 case USB_SPEED_SUPER_PLUS:
1804 break;
1805 default:
1806 dev_err(cdns->dev, "invalid speed parameter %d\n", max_speed);
1807 fallthrough;
1808 case USB_SPEED_UNKNOWN:
1809 /* Default to SSP */
1810 max_speed = USB_SPEED_SUPER_PLUS;
1811 break;
1812 }
1813
1814 pdev->gadget.ops = &cdnsp_gadget_ops;
1815 pdev->gadget.name = "cdnsp-gadget";
1816 pdev->gadget.speed = USB_SPEED_UNKNOWN;
1817 pdev->gadget.sg_supported = 1;
1818 pdev->gadget.max_speed = USB_SPEED_SUPER_PLUS;
1819 pdev->gadget.lpm_capable = 1;
1820
1821 pdev->setup_buf = kzalloc(CDNSP_EP0_SETUP_SIZE, GFP_KERNEL);
1822 if (!pdev->setup_buf)
1823 goto free_pdev;
1824
1825 /*
1826 * Controller supports not aligned buffer but it should improve
1827 * performance.
1828 */
1829 pdev->gadget.quirk_ep_out_aligned_size = true;
1830
1831 ret = cdnsp_gen_setup(pdev);
1832 if (ret) {
1833 dev_err(pdev->dev, "Generic initialization failed %d\n", ret);
1834 goto free_setup;
1835 }
1836
1837 ret = cdnsp_gadget_init_endpoints(pdev);
1838 if (ret) {
1839 dev_err(pdev->dev, "failed to initialize endpoints\n");
1840 goto halt_pdev;
1841 }
1842
1843 ret = usb_add_gadget_udc(pdev->dev, &pdev->gadget);
1844 if (ret) {
1845 dev_err(pdev->dev, "failed to register udc\n");
1846 goto free_endpoints;
1847 }
1848
1849 ret = devm_request_threaded_irq(pdev->dev, cdns->dev_irq,
1850 cdnsp_irq_handler,
1851 cdnsp_thread_irq_handler, IRQF_SHARED,
1852 dev_name(pdev->dev), pdev);
1853 if (ret)
1854 goto del_gadget;
1855
1856 return 0;
1857
1858del_gadget:
1859 usb_del_gadget_udc(&pdev->gadget);
1860free_endpoints:
1861 cdnsp_gadget_free_endpoints(pdev);
1862halt_pdev:
1863 cdnsp_halt(pdev);
1864 cdnsp_reset(pdev);
1865 cdnsp_mem_cleanup(pdev);
1866free_setup:
1867 kfree(pdev->setup_buf);
1868free_pdev:
1869 kfree(pdev);
1870
1871 return ret;
1872}
1873
1874static void cdnsp_gadget_exit(struct cdns *cdns)
1875{
1876 struct cdnsp_device *pdev = cdns->gadget_dev;
1877
1878 devm_free_irq(pdev->dev, cdns->dev_irq, pdev);
1879 pm_runtime_mark_last_busy(cdns->dev);
1880 pm_runtime_put_autosuspend(cdns->dev);
1881 usb_del_gadget_udc(&pdev->gadget);
1882 cdnsp_gadget_free_endpoints(pdev);
1883 cdnsp_mem_cleanup(pdev);
1884 kfree(pdev);
1885 cdns->gadget_dev = NULL;
1886 cdns_drd_gadget_off(cdns);
1887}
1888
1889static int cdnsp_gadget_suspend(struct cdns *cdns, bool do_wakeup)
1890{
1891 struct cdnsp_device *pdev = cdns->gadget_dev;
1892 unsigned long flags;
1893
1894 if (pdev->link_state == XDEV_U3)
1895 return 0;
1896
1897 spin_lock_irqsave(&pdev->lock, flags);
1898 cdnsp_disconnect_gadget(pdev);
1899 cdnsp_stop(pdev);
1900 spin_unlock_irqrestore(&pdev->lock, flags);
1901
1902 return 0;
1903}
1904
1905static int cdnsp_gadget_resume(struct cdns *cdns, bool hibernated)
1906{
1907 struct cdnsp_device *pdev = cdns->gadget_dev;
1908 enum usb_device_speed max_speed;
1909 unsigned long flags;
1910 int ret;
1911
1912 if (!pdev->gadget_driver)
1913 return 0;
1914
1915 spin_lock_irqsave(&pdev->lock, flags);
1916 max_speed = pdev->gadget_driver->max_speed;
1917
1918 /* Limit speed if necessary. */
1919 max_speed = min(max_speed, pdev->gadget.max_speed);
1920
1921 ret = cdnsp_run(pdev, max_speed);
1922
1923 if (pdev->link_state == XDEV_U3)
1924 __cdnsp_gadget_wakeup(pdev);
1925
1926 spin_unlock_irqrestore(&pdev->lock, flags);
1927
1928 return ret;
1929}
1930
1931/**
1932 * cdnsp_gadget_init - initialize device structure
1933 * @cdns: cdnsp instance
1934 *
1935 * This function initializes the gadget.
1936 */
1937int cdnsp_gadget_init(struct cdns *cdns)
1938{
1939 struct cdns_role_driver *rdrv;
1940
1941 rdrv = devm_kzalloc(cdns->dev, sizeof(*rdrv), GFP_KERNEL);
1942 if (!rdrv)
1943 return -ENOMEM;
1944
1945 rdrv->start = __cdnsp_gadget_init;
1946 rdrv->stop = cdnsp_gadget_exit;
1947 rdrv->suspend = cdnsp_gadget_suspend;
1948 rdrv->resume = cdnsp_gadget_resume;
1949 rdrv->state = CDNS_ROLE_STATE_INACTIVE;
1950 rdrv->name = "gadget";
1951 cdns->roles[USB_ROLE_DEVICE] = rdrv;
1952
1953 return 0;
1954}
Linux 6.x block layer and io_uring tree(s)