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scsi: ufs: core: Probe for EXT_IID support
[linux-2.6-block.git] / drivers / ufs / core / ufshcd.c
CommitLineData
67351119 1// SPDX-License-Identifier: GPL-2.0-or-later
7a3e97b0 2/*
e0eca63e 3 * Universal Flash Storage Host controller driver Core
3b1d0580 4 * Copyright (C) 2011-2013 Samsung India Software Operations
52ac95fe 5 * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
7a3e97b0 6 *
3b1d0580
VH		 7 * Authors:
8 * Santosh Yaraganavi <santosh.sy@samsung.com>
9 * Vinayak Holikatti <h.vinayak@samsung.com>
7a3e97b0
SY		 10 */
11
6ccf44fe 12#include <linux/async.h>
856b3483 13#include <linux/devfreq.h>
b573d484 14#include <linux/nls.h>
54b879b7 15#include <linux/of.h>
ad448378 16#include <linux/bitfield.h>
fb276f77 17#include <linux/blk-pm.h>
c72e79c0 18#include <linux/blkdev.h>
3f06f780
BVA		 19#include <linux/clk.h>
20#include <linux/delay.h>
21#include <linux/interrupt.h>
22#include <linux/module.h>
3f06f780 23#include <linux/regulator/consumer.h>
0f85e747 24#include <linux/sched/clock.h>
3f06f780
BVA		 25#include <scsi/scsi_cmnd.h>
26#include <scsi/scsi_dbg.h>
b294ff3e 27#include <scsi/scsi_driver.h>
3f06f780 28#include <scsi/scsi_eh.h>
4bc26113 29#include "ufshcd-priv.h"
dd11376b
BVA		 30#include <ufs/ufs_quirks.h>
31#include <ufs/unipro.h>
cbb6813e 32#include "ufs-sysfs.h"
b6cacaf2 33#include "ufs-debugfs.h"
c11a1ae9 34#include "ufs-fault-injection.h"
df032bf2 35#include "ufs_bsg.h"
df043c74 36#include "ufshcd-crypto.h"
f02bc975 37#include "ufshpb.h"
3d17b9b5 38#include <asm/unaligned.h>
7a3e97b0 39
7ff5ab47 40#define CREATE_TRACE_POINTS
41#include <trace/events/ufs.h>
42
2fbd009b
SJ		 43#define UFSHCD_ENABLE_INTRS (UTP_TRANSFER_REQ_COMPL |\
44 UTP_TASK_REQ_COMPL |\
45 UFSHCD_ERROR_MASK)
6ccf44fe
SJ		 46/* UIC command timeout, unit: ms */
47#define UIC_CMD_TIMEOUT 500
2fbd009b 48
5a0b0cb9
SRT		 49/* NOP OUT retries waiting for NOP IN response */
50#define NOP_OUT_RETRIES 10
782e2efb
DP		 51/* Timeout after 50 msecs if NOP OUT hangs without response */
52#define NOP_OUT_TIMEOUT 50 /* msecs */
5a0b0cb9 53
68078d5c 54/* Query request retries */
10fe5888 55#define QUERY_REQ_RETRIES 3
68078d5c 56/* Query request timeout */
10fe5888 57#define QUERY_REQ_TIMEOUT 1500 /* 1.5 seconds */
68078d5c 58
6ff265fc
BH		 59/* Advanced RPMB request timeout */
60#define ADVANCED_RPMB_REQ_TIMEOUT 3000 /* 3 seconds */
61
e2933132
SRT		 62/* Task management command timeout */
63#define TM_CMD_TIMEOUT 100 /* msecs */
64
64238fbd
YG		 65/* maximum number of retries for a general UIC command */
66#define UFS_UIC_COMMAND_RETRIES 3
67
1d337ec2
SRT		 68/* maximum number of link-startup retries */
69#define DME_LINKSTARTUP_RETRIES 3
70
71/* maximum number of reset retries before giving up */
72#define MAX_HOST_RESET_RETRIES 5
73
87bf6a6b
AH		 74/* Maximum number of error handler retries before giving up */
75#define MAX_ERR_HANDLER_RETRIES 5
76
68078d5c
DR		 77/* Expose the flag value from utp_upiu_query.value */
78#define MASK_QUERY_UPIU_FLAG_LOC 0xFF
79
7d568652
SJ		 80/* Interrupt aggregation default timeout, unit: 40us */
81#define INT_AGGR_DEF_TO 0x02
82
49615ba1
SC		 83/* default delay of autosuspend: 2000 ms */
84#define RPM_AUTOSUSPEND_DELAY_MS 2000
85
51dd905b
SC		 86/* Default delay of RPM device flush delayed work */
87#define RPM_DEV_FLUSH_RECHECK_WORK_DELAY_MS 5000
88
09f17791
CG		 89/* Default value of wait time before gating device ref clock */
90#define UFSHCD_REF_CLK_GATING_WAIT_US 0xFF /* microsecs */
91
29707fab
KK		 92/* Polling time to wait for fDeviceInit */
93#define FDEVICEINIT_COMPL_TIMEOUT 1500 /* millisecs */
94
aa497613
SRT		 95#define ufshcd_toggle_vreg(_dev, _vreg, _on) \
96 ({ \
97 int _ret; \
98 if (_on) \
99 _ret = ufshcd_enable_vreg(_dev, _vreg); \
100 else \
101 _ret = ufshcd_disable_vreg(_dev, _vreg); \
102 _ret; \
103 })
104
ba80917d
TW		 105#define ufshcd_hex_dump(prefix_str, buf, len) do { \
106 size_t __len = (len); \
107 print_hex_dump(KERN_ERR, prefix_str, \
108 __len > 4 ? DUMP_PREFIX_OFFSET : DUMP_PREFIX_NONE,\
109 16, 4, buf, __len, false); \
110} while (0)
111
112int ufshcd_dump_regs(struct ufs_hba *hba, size_t offset, size_t len,
113 const char *prefix)
114{
d6724756
MG		 115 u32 *regs;
116 size_t pos;
117
118 if (offset % 4 != 0 || len % 4 != 0) /* keep readl happy */
119 return -EINVAL;
ba80917d 120
cddaebaf 121 regs = kzalloc(len, GFP_ATOMIC);
ba80917d
TW		 122 if (!regs)
123 return -ENOMEM;
124
ef600310
KK		 125 for (pos = 0; pos < len; pos += 4) {
126 if (offset == 0 &&
127 pos >= REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER &&
128 pos <= REG_UIC_ERROR_CODE_DME)
129 continue;
d6724756 130 regs[pos / 4] = ufshcd_readl(hba, offset + pos);
ef600310 131 }
d6724756 132
ba80917d
TW		 133 ufshcd_hex_dump(prefix, regs, len);
134 kfree(regs);
135
136 return 0;
137}
138EXPORT_SYMBOL_GPL(ufshcd_dump_regs);
66cc820f 139
7a3e97b0
SY		 140enum {
141 UFSHCD_MAX_CHANNEL = 0,
142 UFSHCD_MAX_ID = 1,
945c3cca
BVA		 143 UFSHCD_NUM_RESERVED = 1,
144 UFSHCD_CMD_PER_LUN = 32 - UFSHCD_NUM_RESERVED,
145 UFSHCD_CAN_QUEUE = 32 - UFSHCD_NUM_RESERVED,
7a3e97b0
SY		 146};
147
4693fad7
BVA		 148static const char *const ufshcd_state_name[] = {
149 [UFSHCD_STATE_RESET] = "reset",
150 [UFSHCD_STATE_OPERATIONAL] = "operational",
151 [UFSHCD_STATE_ERROR] = "error",
152 [UFSHCD_STATE_EH_SCHEDULED_FATAL] = "eh_fatal",
153 [UFSHCD_STATE_EH_SCHEDULED_NON_FATAL] = "eh_non_fatal",
154};
155
3441da7d
SRT		 156/* UFSHCD error handling flags */
157enum {
158 UFSHCD_EH_IN_PROGRESS = (1 << 0),
7a3e97b0
SY		 159};
160
e8e7f271
SRT		 161/* UFSHCD UIC layer error flags */
162enum {
163 UFSHCD_UIC_DL_PA_INIT_ERROR = (1 << 0), /* Data link layer error */
9a47ec7c
YG		 164 UFSHCD_UIC_DL_NAC_RECEIVED_ERROR = (1 << 1), /* Data link layer error */
165 UFSHCD_UIC_DL_TCx_REPLAY_ERROR = (1 << 2), /* Data link layer error */
166 UFSHCD_UIC_NL_ERROR = (1 << 3), /* Network layer error */
167 UFSHCD_UIC_TL_ERROR = (1 << 4), /* Transport Layer error */
168 UFSHCD_UIC_DME_ERROR = (1 << 5), /* DME error */
2355b66e 169 UFSHCD_UIC_PA_GENERIC_ERROR = (1 << 6), /* Generic PA error */
e8e7f271
SRT		 170};
171
3441da7d 172#define ufshcd_set_eh_in_progress(h) \
9c490d2d 173 ((h)->eh_flags |= UFSHCD_EH_IN_PROGRESS)
3441da7d 174#define ufshcd_eh_in_progress(h) \
9c490d2d 175 ((h)->eh_flags & UFSHCD_EH_IN_PROGRESS)
3441da7d 176#define ufshcd_clear_eh_in_progress(h) \
9c490d2d 177 ((h)->eh_flags &= ~UFSHCD_EH_IN_PROGRESS)
3441da7d 178
35d11ec2 179const struct ufs_pm_lvl_states ufs_pm_lvl_states[] = {
e2ac7ab2
BVA		 180 [UFS_PM_LVL_0] = {UFS_ACTIVE_PWR_MODE, UIC_LINK_ACTIVE_STATE},
181 [UFS_PM_LVL_1] = {UFS_ACTIVE_PWR_MODE, UIC_LINK_HIBERN8_STATE},
182 [UFS_PM_LVL_2] = {UFS_SLEEP_PWR_MODE, UIC_LINK_ACTIVE_STATE},
183 [UFS_PM_LVL_3] = {UFS_SLEEP_PWR_MODE, UIC_LINK_HIBERN8_STATE},
184 [UFS_PM_LVL_4] = {UFS_POWERDOWN_PWR_MODE, UIC_LINK_HIBERN8_STATE},
185 [UFS_PM_LVL_5] = {UFS_POWERDOWN_PWR_MODE, UIC_LINK_OFF_STATE},
fe1d4c2e
AH		 186 /*
187 * For DeepSleep, the link is first put in hibern8 and then off.
188 * Leaving the link in hibern8 is not supported.
189 */
e2ac7ab2 190 [UFS_PM_LVL_6] = {UFS_DEEPSLEEP_PWR_MODE, UIC_LINK_OFF_STATE},
57d104c1
SJ		 191};
192
193static inline enum ufs_dev_pwr_mode
194ufs_get_pm_lvl_to_dev_pwr_mode(enum ufs_pm_level lvl)
195{
196 return ufs_pm_lvl_states[lvl].dev_state;
197}
198
199static inline enum uic_link_state
200ufs_get_pm_lvl_to_link_pwr_state(enum ufs_pm_level lvl)
201{
202 return ufs_pm_lvl_states[lvl].link_state;
203}
204
0c8f7586 205static inline enum ufs_pm_level
206ufs_get_desired_pm_lvl_for_dev_link_state(enum ufs_dev_pwr_mode dev_state,
207 enum uic_link_state link_state)
208{
209 enum ufs_pm_level lvl;
210
211 for (lvl = UFS_PM_LVL_0; lvl < UFS_PM_LVL_MAX; lvl++) {
212 if ((ufs_pm_lvl_states[lvl].dev_state == dev_state) &&
213 (ufs_pm_lvl_states[lvl].link_state == link_state))
214 return lvl;
215 }
216
217 /* if no match found, return the level 0 */
218 return UFS_PM_LVL_0;
219}
220
aead21f3 221static const struct ufs_dev_quirk ufs_fixups[] = {
56d4a186 222 /* UFS cards deviations table */
dd2cf44f
BVA		 223 { .wmanufacturerid = UFS_VENDOR_MICRON,
224 .model = UFS_ANY_MODEL,
225 .quirk = UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM |
226 UFS_DEVICE_QUIRK_SWAP_L2P_ENTRY_FOR_HPB_READ },
227 { .wmanufacturerid = UFS_VENDOR_SAMSUNG,
228 .model = UFS_ANY_MODEL,
229 .quirk = UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM |
230 UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE |
231 UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS },
232 { .wmanufacturerid = UFS_VENDOR_SKHYNIX,
233 .model = UFS_ANY_MODEL,
234 .quirk = UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME },
235 { .wmanufacturerid = UFS_VENDOR_SKHYNIX,
236 .model = "hB8aL1" /*H28U62301AMR*/,
237 .quirk = UFS_DEVICE_QUIRK_HOST_VS_DEBUGSAVECONFIGTIME },
238 { .wmanufacturerid = UFS_VENDOR_TOSHIBA,
239 .model = UFS_ANY_MODEL,
240 .quirk = UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM },
241 { .wmanufacturerid = UFS_VENDOR_TOSHIBA,
242 .model = "THGLF2G9C8KBADG",
243 .quirk = UFS_DEVICE_QUIRK_PA_TACTIVATE },
244 { .wmanufacturerid = UFS_VENDOR_TOSHIBA,
245 .model = "THGLF2G9D8KBADG",
246 .quirk = UFS_DEVICE_QUIRK_PA_TACTIVATE },
247 {}
56d4a186
SJ		 248};
249
9333d775 250static irqreturn_t ufshcd_tmc_handler(struct ufs_hba *hba);
3441da7d 251static void ufshcd_async_scan(void *data, async_cookie_t cookie);
e8e7f271 252static int ufshcd_reset_and_restore(struct ufs_hba *hba);
e7d38257 253static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd);
e8e7f271 254static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag);
1d337ec2 255static void ufshcd_hba_exit(struct ufs_hba *hba);
68444d73 256static int ufshcd_probe_hba(struct ufs_hba *hba, bool init_dev_params);
1ab27c9c 257static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on);
cad2e03d 258static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba);
57d104c1 259static int ufshcd_host_reset_and_restore(struct ufs_hba *hba);
fcb0c4b0
ST		 260static void ufshcd_resume_clkscaling(struct ufs_hba *hba);
261static void ufshcd_suspend_clkscaling(struct ufs_hba *hba);
401f1e44 262static void __ufshcd_suspend_clkscaling(struct ufs_hba *hba);
fcb0c4b0 263static int ufshcd_scale_clks(struct ufs_hba *hba, bool scale_up);
57d104c1 264static irqreturn_t ufshcd_intr(int irq, void *__hba);
874237f7
YG		 265static int ufshcd_change_power_mode(struct ufs_hba *hba,
266 struct ufs_pa_layer_attr *pwr_mode);
c72e79c0
CG		 267static int ufshcd_setup_hba_vreg(struct ufs_hba *hba, bool on);
268static int ufshcd_setup_vreg(struct ufs_hba *hba, bool on);
269static inline int ufshcd_config_vreg_hpm(struct ufs_hba *hba,
270 struct ufs_vreg *vreg);
307348f6 271static int ufshcd_try_to_abort_task(struct ufs_hba *hba, int tag);
4450a165
JC		 272static void ufshcd_wb_toggle_buf_flush_during_h8(struct ufs_hba *hba,
273 bool enable);
dd7143e2
CG		 274static void ufshcd_hba_vreg_set_lpm(struct ufs_hba *hba);
275static void ufshcd_hba_vreg_set_hpm(struct ufs_hba *hba);
3d17b9b5 276
5231d38c 277static inline void ufshcd_enable_irq(struct ufs_hba *hba)
57d104c1 278{
57d104c1 279 if (!hba->is_irq_enabled) {
5231d38c 280 enable_irq(hba->irq);
57d104c1
SJ		 281 hba->is_irq_enabled = true;
282 }
57d104c1
SJ		 283}
284
285static inline void ufshcd_disable_irq(struct ufs_hba *hba)
286{
287 if (hba->is_irq_enabled) {
5231d38c 288 disable_irq(hba->irq);
57d104c1
SJ		 289 hba->is_irq_enabled = false;
290 }
291}
3441da7d 292
4450a165 293static void ufshcd_configure_wb(struct ufs_hba *hba)
3d17b9b5 294{
79e3520f 295 if (!ufshcd_is_wb_allowed(hba))
3d17b9b5
AD		 296 return;
297
3b5f3c0d
YH		 298 ufshcd_wb_toggle(hba, true);
299
4450a165 300 ufshcd_wb_toggle_buf_flush_during_h8(hba, true);
42f8c5cd
JC		 301
302 if (ufshcd_is_wb_buf_flush_allowed(hba))
4450a165 303 ufshcd_wb_toggle_buf_flush(hba, true);
3d17b9b5
AD		 304}
305
38135535
SJ		 306static void ufshcd_scsi_unblock_requests(struct ufs_hba *hba)
307{
308 if (atomic_dec_and_test(&hba->scsi_block_reqs_cnt))
309 scsi_unblock_requests(hba->host);
310}
311
312static void ufshcd_scsi_block_requests(struct ufs_hba *hba)
313{
314 if (atomic_inc_return(&hba->scsi_block_reqs_cnt) == 1)
315 scsi_block_requests(hba->host);
316}
317
6667e6d9 318static void ufshcd_add_cmd_upiu_trace(struct ufs_hba *hba, unsigned int tag,
28fa68fc 319 enum ufs_trace_str_t str_t)
6667e6d9
OS		 320{
321 struct utp_upiu_req *rq = hba->lrb[tag].ucd_req_ptr;
89ac2c3b 322 struct utp_upiu_header *header;
6667e6d9 323
9d5095e7
BH		 324 if (!trace_ufshcd_upiu_enabled())
325 return;
326
89ac2c3b
BH		 327 if (str_t == UFS_CMD_SEND)
328 header = &rq->header;
329 else
330 header = &hba->lrb[tag].ucd_rsp_ptr->header;
331
332 trace_ufshcd_upiu(dev_name(hba->dev), str_t, header, &rq->sc.cdb,
867fdc2d 333 UFS_TSF_CDB);
6667e6d9
OS		 334}
335
fb475b74
AA		 336static void ufshcd_add_query_upiu_trace(struct ufs_hba *hba,
337 enum ufs_trace_str_t str_t,
338 struct utp_upiu_req *rq_rsp)
6667e6d9 339{
9d5095e7
BH		 340 if (!trace_ufshcd_upiu_enabled())
341 return;
6667e6d9 342
be20b51c 343 trace_ufshcd_upiu(dev_name(hba->dev), str_t, &rq_rsp->header,
867fdc2d 344 &rq_rsp->qr, UFS_TSF_OSF);
6667e6d9
OS		 345}
346
347static void ufshcd_add_tm_upiu_trace(struct ufs_hba *hba, unsigned int tag,
28fa68fc 348 enum ufs_trace_str_t str_t)
6667e6d9 349{
e8c2da7e 350 struct utp_task_req_desc *descp = &hba->utmrdl_base_addr[tag];
6667e6d9 351
9d5095e7
BH		 352 if (!trace_ufshcd_upiu_enabled())
353 return;
354
0ed083e9 355 if (str_t == UFS_TM_SEND)
1352eec8
GS		 356 trace_ufshcd_upiu(dev_name(hba->dev), str_t,
357 &descp->upiu_req.req_header,
358 &descp->upiu_req.input_param1,
359 UFS_TSF_TM_INPUT);
0ed083e9 360 else
1352eec8
GS		 361 trace_ufshcd_upiu(dev_name(hba->dev), str_t,
362 &descp->upiu_rsp.rsp_header,
363 &descp->upiu_rsp.output_param1,
364 UFS_TSF_TM_OUTPUT);
6667e6d9
OS		 365}
366
aa5c6979 367static void ufshcd_add_uic_command_trace(struct ufs_hba *hba,
35d11ec2 368 const struct uic_command *ucmd,
28fa68fc 369 enum ufs_trace_str_t str_t)
aa5c6979
SC		 370{
371 u32 cmd;
372
373 if (!trace_ufshcd_uic_command_enabled())
374 return;
375
28fa68fc 376 if (str_t == UFS_CMD_SEND)
aa5c6979
SC		 377 cmd = ucmd->command;
378 else
379 cmd = ufshcd_readl(hba, REG_UIC_COMMAND);
380
28fa68fc 381 trace_ufshcd_uic_command(dev_name(hba->dev), str_t, cmd,
aa5c6979
SC		 382 ufshcd_readl(hba, REG_UIC_COMMAND_ARG_1),
383 ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2),
384 ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3));
385}
386
28fa68fc
BH		 387static void ufshcd_add_command_trace(struct ufs_hba *hba, unsigned int tag,
388 enum ufs_trace_str_t str_t)
1a07f2d9 389{
2bd3b6b7 390 u64 lba = 0;
69a314d6 391 u8 opcode = 0, group_id = 0;
1a07f2d9 392 u32 intr, doorbell;
e7c3b379 393 struct ufshcd_lrb *lrbp = &hba->lrb[tag];
e4d2add7 394 struct scsi_cmnd *cmd = lrbp->cmd;
3f2c1002 395 struct request *rq = scsi_cmd_to_rq(cmd);
1a07f2d9
LS		 396 int transfer_len = -1;
397
44b5de36
BH		 398 if (!cmd)
399 return;
400
44b5de36
BH		 401 /* trace UPIU also */
402 ufshcd_add_cmd_upiu_trace(hba, tag, str_t);
f0101af4
BH		 403 if (!trace_ufshcd_command_enabled())
404 return;
405
44b5de36 406 opcode = cmd->cmnd[0];
44b5de36
BH		 407
408 if (opcode == READ_10 || opcode == WRITE_10) {
409 /*
410 * Currently we only fully trace read(10) and write(10) commands
411 */
412 transfer_len =
413 be32_to_cpu(lrbp->ucd_req_ptr->sc.exp_data_transfer_len);
2bd3b6b7 414 lba = scsi_get_lba(cmd);
44b5de36
BH		 415 if (opcode == WRITE_10)
416 group_id = lrbp->cmd->cmnd[6];
417 } else if (opcode == UNMAP) {
418 /*
419 * The number of Bytes to be unmapped beginning with the lba.
420 */
3f2c1002 421 transfer_len = blk_rq_bytes(rq);
2bd3b6b7 422 lba = scsi_get_lba(cmd);
1a07f2d9
LS		 423 }
424
425 intr = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
426 doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
28fa68fc 427 trace_ufshcd_command(dev_name(hba->dev), str_t, tag,
69a314d6 428 doorbell, transfer_len, intr, lba, opcode, group_id);
1a07f2d9
LS		 429}
430
ff8e20c6
DR		 431static void ufshcd_print_clk_freqs(struct ufs_hba *hba)
432{
433 struct ufs_clk_info *clki;
434 struct list_head *head = &hba->clk_list_head;
435
566ec9ad 436 if (list_empty(head))
ff8e20c6
DR		 437 return;
438
439 list_for_each_entry(clki, head, list) {
440 if (!IS_ERR_OR_NULL(clki->clk) && clki->min_freq &&
441 clki->max_freq)
442 dev_err(hba->dev, "clk: %s, rate: %u\n",
443 clki->name, clki->curr_freq);
444 }
445}
446
e965e5e0 447static void ufshcd_print_evt(struct ufs_hba *hba, u32 id,
35d11ec2 448 const char *err_name)
ff8e20c6
DR		 449{
450 int i;
27752647 451 bool found = false;
35d11ec2 452 const struct ufs_event_hist *e;
ff8e20c6 453
e965e5e0
SC		 454 if (id >= UFS_EVT_CNT)
455 return;
ff8e20c6 456
e965e5e0 457 e = &hba->ufs_stats.event[id];
ff8e20c6 458
e965e5e0
SC		 459 for (i = 0; i < UFS_EVENT_HIST_LENGTH; i++) {
460 int p = (i + e->pos) % UFS_EVENT_HIST_LENGTH;
461
462 if (e->tstamp[p] == 0)
ff8e20c6 463 continue;
c5397f13 464 dev_err(hba->dev, "%s[%d] = 0x%x at %lld us\n", err_name, p,
0f85e747 465 e->val[p], div_u64(e->tstamp[p], 1000));
27752647 466 found = true;
ff8e20c6 467 }
27752647
SC		 468
469 if (!found)
fd1fb4d5 470 dev_err(hba->dev, "No record of %s\n", err_name);
bafd09f8
DH		 471 else
472 dev_err(hba->dev, "%s: total cnt=%llu\n", err_name, e->cnt);
ff8e20c6
DR		 473}
474
e965e5e0 475static void ufshcd_print_evt_hist(struct ufs_hba *hba)
66cc820f 476{
ba80917d 477 ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE, "host_regs: ");
ff8e20c6 478
e965e5e0
SC		 479 ufshcd_print_evt(hba, UFS_EVT_PA_ERR, "pa_err");
480 ufshcd_print_evt(hba, UFS_EVT_DL_ERR, "dl_err");
481 ufshcd_print_evt(hba, UFS_EVT_NL_ERR, "nl_err");
482 ufshcd_print_evt(hba, UFS_EVT_TL_ERR, "tl_err");
483 ufshcd_print_evt(hba, UFS_EVT_DME_ERR, "dme_err");
484 ufshcd_print_evt(hba, UFS_EVT_AUTO_HIBERN8_ERR,
485 "auto_hibern8_err");
486 ufshcd_print_evt(hba, UFS_EVT_FATAL_ERR, "fatal_err");
487 ufshcd_print_evt(hba, UFS_EVT_LINK_STARTUP_FAIL,
488 "link_startup_fail");
489 ufshcd_print_evt(hba, UFS_EVT_RESUME_ERR, "resume_fail");
490 ufshcd_print_evt(hba, UFS_EVT_SUSPEND_ERR,
491 "suspend_fail");
a301d487
PW		 492 ufshcd_print_evt(hba, UFS_EVT_WL_RES_ERR, "wlun resume_fail");
493 ufshcd_print_evt(hba, UFS_EVT_WL_SUSP_ERR,
494 "wlun suspend_fail");
e965e5e0
SC		 495 ufshcd_print_evt(hba, UFS_EVT_DEV_RESET, "dev_reset");
496 ufshcd_print_evt(hba, UFS_EVT_HOST_RESET, "host_reset");
497 ufshcd_print_evt(hba, UFS_EVT_ABORT, "task_abort");
ff8e20c6 498
7c486d91 499 ufshcd_vops_dbg_register_dump(hba);
66cc820f
DR		 500}
501
502static
503void ufshcd_print_trs(struct ufs_hba *hba, unsigned long bitmap, bool pr_prdt)
504{
35d11ec2 505 const struct ufshcd_lrb *lrbp;
7fabb77b 506 int prdt_length;
66cc820f
DR		 507 int tag;
508
509 for_each_set_bit(tag, &bitmap, hba->nutrs) {
510 lrbp = &hba->lrb[tag];
511
ff8e20c6 512 dev_err(hba->dev, "UPIU[%d] - issue time %lld us\n",
0f85e747 513 tag, div_u64(lrbp->issue_time_stamp_local_clock, 1000));
09017188 514 dev_err(hba->dev, "UPIU[%d] - complete time %lld us\n",
0f85e747 515 tag, div_u64(lrbp->compl_time_stamp_local_clock, 1000));
ff8e20c6
DR		 516 dev_err(hba->dev,
517 "UPIU[%d] - Transfer Request Descriptor phys@0x%llx\n",
518 tag, (u64)lrbp->utrd_dma_addr);
519
66cc820f
DR		 520 ufshcd_hex_dump("UPIU TRD: ", lrbp->utr_descriptor_ptr,
521 sizeof(struct utp_transfer_req_desc));
ff8e20c6
DR		 522 dev_err(hba->dev, "UPIU[%d] - Request UPIU phys@0x%llx\n", tag,
523 (u64)lrbp->ucd_req_dma_addr);
66cc820f
DR		 524 ufshcd_hex_dump("UPIU REQ: ", lrbp->ucd_req_ptr,
525 sizeof(struct utp_upiu_req));
ff8e20c6
DR		 526 dev_err(hba->dev, "UPIU[%d] - Response UPIU phys@0x%llx\n", tag,
527 (u64)lrbp->ucd_rsp_dma_addr);
66cc820f
DR		 528 ufshcd_hex_dump("UPIU RSP: ", lrbp->ucd_rsp_ptr,
529 sizeof(struct utp_upiu_rsp));
66cc820f 530
7fabb77b
GB		 531 prdt_length = le16_to_cpu(
532 lrbp->utr_descriptor_ptr->prd_table_length);
cc770ce3 533 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN)
ada1e653 534 prdt_length /= ufshcd_sg_entry_size(hba);
cc770ce3 535
7fabb77b
GB		 536 dev_err(hba->dev,
537 "UPIU[%d] - PRDT - %d entries phys@0x%llx\n",
538 tag, prdt_length,
539 (u64)lrbp->ucd_prdt_dma_addr);
540
541 if (pr_prdt)
66cc820f 542 ufshcd_hex_dump("UPIU PRDT: ", lrbp->ucd_prdt_ptr,
ada1e653 543 ufshcd_sg_entry_size(hba) * prdt_length);
66cc820f
DR		 544 }
545}
546
547static void ufshcd_print_tmrs(struct ufs_hba *hba, unsigned long bitmap)
548{
66cc820f
DR		 549 int tag;
550
551 for_each_set_bit(tag, &bitmap, hba->nutmrs) {
391e388f
CH		 552 struct utp_task_req_desc *tmrdp = &hba->utmrdl_base_addr[tag];
553
66cc820f 554 dev_err(hba->dev, "TM[%d] - Task Management Header\n", tag);
391e388f 555 ufshcd_hex_dump("", tmrdp, sizeof(*tmrdp));
66cc820f
DR		 556 }
557}
558
6ba65588
GB		 559static void ufshcd_print_host_state(struct ufs_hba *hba)
560{
35d11ec2 561 const struct scsi_device *sdev_ufs = hba->ufs_device_wlun;
3f8af604 562
6ba65588 563 dev_err(hba->dev, "UFS Host state=%d\n", hba->ufshcd_state);
7252a360
BVA		 564 dev_err(hba->dev, "outstanding reqs=0x%lx tasks=0x%lx\n",
565 hba->outstanding_reqs, hba->outstanding_tasks);
6ba65588
GB		 566 dev_err(hba->dev, "saved_err=0x%x, saved_uic_err=0x%x\n",
567 hba->saved_err, hba->saved_uic_err);
568 dev_err(hba->dev, "Device power mode=%d, UIC link state=%d\n",
569 hba->curr_dev_pwr_mode, hba->uic_link_state);
570 dev_err(hba->dev, "PM in progress=%d, sys. suspended=%d\n",
571 hba->pm_op_in_progress, hba->is_sys_suspended);
572 dev_err(hba->dev, "Auto BKOPS=%d, Host self-block=%d\n",
573 hba->auto_bkops_enabled, hba->host->host_self_blocked);
574 dev_err(hba->dev, "Clk gate=%d\n", hba->clk_gating.state);
3f8af604
CG		 575 dev_err(hba->dev,
576 "last_hibern8_exit_tstamp at %lld us, hibern8_exit_cnt=%d\n",
0f85e747 577 div_u64(hba->ufs_stats.last_hibern8_exit_tstamp, 1000),
3f8af604
CG		 578 hba->ufs_stats.hibern8_exit_cnt);
579 dev_err(hba->dev, "last intr at %lld us, last intr status=0x%x\n",
0f85e747 580 div_u64(hba->ufs_stats.last_intr_ts, 1000),
3f8af604 581 hba->ufs_stats.last_intr_status);
6ba65588
GB		 582 dev_err(hba->dev, "error handling flags=0x%x, req. abort count=%d\n",
583 hba->eh_flags, hba->req_abort_count);
3f8af604
CG		 584 dev_err(hba->dev, "hba->ufs_version=0x%x, Host capabilities=0x%x, caps=0x%x\n",
585 hba->ufs_version, hba->capabilities, hba->caps);
6ba65588
GB		 586 dev_err(hba->dev, "quirks=0x%x, dev. quirks=0x%x\n", hba->quirks,
587 hba->dev_quirks);
3f8af604
CG		 588 if (sdev_ufs)
589 dev_err(hba->dev, "UFS dev info: %.8s %.16s rev %.4s\n",
590 sdev_ufs->vendor, sdev_ufs->model, sdev_ufs->rev);
591
592 ufshcd_print_clk_freqs(hba);
6ba65588
GB		 593}
594
ff8e20c6
DR		 595/**
596 * ufshcd_print_pwr_info - print power params as saved in hba
597 * power info
598 * @hba: per-adapter instance
599 */
600static void ufshcd_print_pwr_info(struct ufs_hba *hba)
601{
602 static const char * const names[] = {
603 "INVALID MODE",
604 "FAST MODE",
605 "SLOW_MODE",
606 "INVALID MODE",
607 "FASTAUTO_MODE",
608 "SLOWAUTO_MODE",
609 "INVALID MODE",
610 };
611
71bb9ab6
AH		 612 /*
613 * Using dev_dbg to avoid messages during runtime PM to avoid
614 * never-ending cycles of messages written back to storage by user space
615 * causing runtime resume, causing more messages and so on.
616 */
617 dev_dbg(hba->dev, "%s:[RX, TX]: gear=[%d, %d], lane[%d, %d], pwr[%s, %s], rate = %d\n",
ff8e20c6
DR		 618 __func__,
619 hba->pwr_info.gear_rx, hba->pwr_info.gear_tx,
620 hba->pwr_info.lane_rx, hba->pwr_info.lane_tx,
621 names[hba->pwr_info.pwr_rx],
622 names[hba->pwr_info.pwr_tx],
623 hba->pwr_info.hs_rate);
624}
625
31a5d9ca
SC		 626static void ufshcd_device_reset(struct ufs_hba *hba)
627{
628 int err;
629
630 err = ufshcd_vops_device_reset(hba);
631
632 if (!err) {
633 ufshcd_set_ufs_dev_active(hba);
634 if (ufshcd_is_wb_allowed(hba)) {
4cd48995
BH		 635 hba->dev_info.wb_enabled = false;
636 hba->dev_info.wb_buf_flush_enabled = false;
31a5d9ca
SC		 637 }
638 }
639 if (err != -EOPNOTSUPP)
640 ufshcd_update_evt_hist(hba, UFS_EVT_DEV_RESET, err);
641}
642
5c955c10
SC		 643void ufshcd_delay_us(unsigned long us, unsigned long tolerance)
644{
645 if (!us)
646 return;
647
648 if (us < 10)
649 udelay(us);
650 else
651 usleep_range(us, us + tolerance);
652}
653EXPORT_SYMBOL_GPL(ufshcd_delay_us);
654
5cac1095 655/**
5a0b0cb9 656 * ufshcd_wait_for_register - wait for register value to change
5cac1095
BVA		 657 * @hba: per-adapter interface
658 * @reg: mmio register offset
659 * @mask: mask to apply to the read register value
660 * @val: value to wait for
661 * @interval_us: polling interval in microseconds
662 * @timeout_ms: timeout in milliseconds
5a0b0cb9 663 *
5cac1095
BVA		 664 * Return:
665 * -ETIMEDOUT on error, zero on success.
5a0b0cb9 666 */
59a57bb7 667static int ufshcd_wait_for_register(struct ufs_hba *hba, u32 reg, u32 mask,
596585a2 668 u32 val, unsigned long interval_us,
5cac1095 669 unsigned long timeout_ms)
5a0b0cb9
SRT		 670{
671 int err = 0;
672 unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms);
673
674 /* ignore bits that we don't intend to wait on */
675 val = val & mask;
676
677 while ((ufshcd_readl(hba, reg) & mask) != val) {
5cac1095 678 usleep_range(interval_us, interval_us + 50);
5a0b0cb9
SRT		 679 if (time_after(jiffies, timeout)) {
680 if ((ufshcd_readl(hba, reg) & mask) != val)
681 err = -ETIMEDOUT;
682 break;
683 }
684 }
685
686 return err;
687}
688
2fbd009b
SJ		 689/**
690 * ufshcd_get_intr_mask - Get the interrupt bit mask
8aa29f19 691 * @hba: Pointer to adapter instance
2fbd009b
SJ		 692 *
693 * Returns interrupt bit mask per version
694 */
695static inline u32 ufshcd_get_intr_mask(struct ufs_hba *hba)
696{
51428818
CC		 697 if (hba->ufs_version == ufshci_version(1, 0))
698 return INTERRUPT_MASK_ALL_VER_10;
699 if (hba->ufs_version <= ufshci_version(2, 0))
700 return INTERRUPT_MASK_ALL_VER_11;
c01848c6 701
51428818 702 return INTERRUPT_MASK_ALL_VER_21;
2fbd009b
SJ		 703}
704
7a3e97b0
SY		 705/**
706 * ufshcd_get_ufs_version - Get the UFS version supported by the HBA
8aa29f19 707 * @hba: Pointer to adapter instance
7a3e97b0
SY		 708 *
709 * Returns UFSHCI version supported by the controller
710 */
711static inline u32 ufshcd_get_ufs_version(struct ufs_hba *hba)
712{
51428818
CC		 713 u32 ufshci_ver;
714
0263bcd0 715 if (hba->quirks & UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION)
51428818
CC		 716 ufshci_ver = ufshcd_vops_get_ufs_hci_version(hba);
717 else
718 ufshci_ver = ufshcd_readl(hba, REG_UFS_VERSION);
9949e702 719
51428818
CC		 720 /*
721 * UFSHCI v1.x uses a different version scheme, in order
722 * to allow the use of comparisons with the ufshci_version
723 * function, we convert it to the same scheme as ufs 2.0+.
724 */
725 if (ufshci_ver & 0x00010000)
726 return ufshci_version(1, ufshci_ver & 0x00000100);
727
728 return ufshci_ver;
7a3e97b0
SY		 729}
730
731/**
732 * ufshcd_is_device_present - Check if any device connected to
733 * the host controller
5c0c28a8 734 * @hba: pointer to adapter instance
7a3e97b0 735 *
c9e6010b 736 * Returns true if device present, false if no device detected
7a3e97b0 737 */
c9e6010b 738static inline bool ufshcd_is_device_present(struct ufs_hba *hba)
7a3e97b0 739{
51d1628f 740 return ufshcd_readl(hba, REG_CONTROLLER_STATUS) & DEVICE_PRESENT;
7a3e97b0
SY		 741}
742
743/**
744 * ufshcd_get_tr_ocs - Get the UTRD Overall Command Status
8aa29f19 745 * @lrbp: pointer to local command reference block
7a3e97b0
SY		 746 *
747 * This function is used to get the OCS field from UTRD
748 * Returns the OCS field in the UTRD
749 */
957d63e7 750static enum utp_ocs ufshcd_get_tr_ocs(struct ufshcd_lrb *lrbp)
7a3e97b0 751{
e8c8e82a 752 return le32_to_cpu(lrbp->utr_descriptor_ptr->header.dword_2) & MASK_OCS;
7a3e97b0
SY		 753}
754
7a3e97b0 755/**
d1a76446 756 * ufshcd_utrl_clear() - Clear requests from the controller request list.
7a3e97b0 757 * @hba: per adapter instance
d1a76446 758 * @mask: mask with one bit set for each request to be cleared
7a3e97b0 759 */
d1a76446 760static inline void ufshcd_utrl_clear(struct ufs_hba *hba, u32 mask)
7a3e97b0 761{
87183841 762 if (hba->quirks & UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR)
d1a76446
BVA		 763 mask = ~mask;
764 /*
765 * From the UFSHCI specification: "UTP Transfer Request List CLear
766 * Register (UTRLCLR): This field is bit significant. Each bit
767 * corresponds to a slot in the UTP Transfer Request List, where bit 0
768 * corresponds to request slot 0. A bit in this field is set to ‘0’
769 * by host software to indicate to the host controller that a transfer
770 * request slot is cleared. The host controller
771 * shall free up any resources associated to the request slot
772 * immediately, and shall set the associated bit in UTRLDBR to ‘0’. The
773 * host software indicates no change to request slots by setting the
774 * associated bits in this field to ‘1’. Bits in this field shall only
775 * be set ‘1’ or ‘0’ by host software when UTRLRSR is set to ‘1’."
776 */
777 ufshcd_writel(hba, ~mask, REG_UTP_TRANSFER_REQ_LIST_CLEAR);
1399c5b0
AA		 778}
779
780/**
4652b58f 781 * ufshcd_utmrl_clear - Clear a bit in UTMRLCLR register
1399c5b0
AA		 782 * @hba: per adapter instance
783 * @pos: position of the bit to be cleared
784 */
785static inline void ufshcd_utmrl_clear(struct ufs_hba *hba, u32 pos)
786{
87183841
AA		 787 if (hba->quirks & UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR)
788 ufshcd_writel(hba, (1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR);
789 else
790 ufshcd_writel(hba, ~(1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR);
7a3e97b0
SY		 791}
792
793/**
794 * ufshcd_get_lists_status - Check UCRDY, UTRLRDY and UTMRLRDY
795 * @reg: Register value of host controller status
796 *
797 * Returns integer, 0 on Success and positive value if failed
798 */
799static inline int ufshcd_get_lists_status(u32 reg)
800{
6cf16115 801 return !((reg & UFSHCD_STATUS_READY) == UFSHCD_STATUS_READY);
7a3e97b0
SY		 802}
803
804/**
805 * ufshcd_get_uic_cmd_result - Get the UIC command result
806 * @hba: Pointer to adapter instance
807 *
808 * This function gets the result of UIC command completion
809 * Returns 0 on success, non zero value on error
810 */
811static inline int ufshcd_get_uic_cmd_result(struct ufs_hba *hba)
812{
b873a275 813 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2) &
7a3e97b0
SY		 814 MASK_UIC_COMMAND_RESULT;
815}
816
12b4fdb4
SJ		 817/**
818 * ufshcd_get_dme_attr_val - Get the value of attribute returned by UIC command
819 * @hba: Pointer to adapter instance
820 *
821 * This function gets UIC command argument3
822 * Returns 0 on success, non zero value on error
823 */
824static inline u32 ufshcd_get_dme_attr_val(struct ufs_hba *hba)
825{
826 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3);
827}
828
7a3e97b0 829/**
5a0b0cb9 830 * ufshcd_get_req_rsp - returns the TR response transaction type
7a3e97b0 831 * @ucd_rsp_ptr: pointer to response UPIU
7a3e97b0
SY		 832 */
833static inline int
5a0b0cb9 834ufshcd_get_req_rsp(struct utp_upiu_rsp *ucd_rsp_ptr)
7a3e97b0 835{
5a0b0cb9 836 return be32_to_cpu(ucd_rsp_ptr->header.dword_0) >> 24;
7a3e97b0
SY		 837}
838
839/**
840 * ufshcd_get_rsp_upiu_result - Get the result from response UPIU
841 * @ucd_rsp_ptr: pointer to response UPIU
842 *
843 * This function gets the response status and scsi_status from response UPIU
844 * Returns the response result code.
845 */
846static inline int
847ufshcd_get_rsp_upiu_result(struct utp_upiu_rsp *ucd_rsp_ptr)
848{
849 return be32_to_cpu(ucd_rsp_ptr->header.dword_1) & MASK_RSP_UPIU_RESULT;
850}
851
1c2623c5
SJ		 852/*
853 * ufshcd_get_rsp_upiu_data_seg_len - Get the data segment length
854 * from response UPIU
855 * @ucd_rsp_ptr: pointer to response UPIU
856 *
857 * Return the data segment length.
858 */
859static inline unsigned int
860ufshcd_get_rsp_upiu_data_seg_len(struct utp_upiu_rsp *ucd_rsp_ptr)
861{
862 return be32_to_cpu(ucd_rsp_ptr->header.dword_2) &
863 MASK_RSP_UPIU_DATA_SEG_LEN;
864}
865
66ec6d59
SRT		 866/**
867 * ufshcd_is_exception_event - Check if the device raised an exception event
868 * @ucd_rsp_ptr: pointer to response UPIU
869 *
870 * The function checks if the device raised an exception event indicated in
871 * the Device Information field of response UPIU.
872 *
873 * Returns true if exception is raised, false otherwise.
874 */
875static inline bool ufshcd_is_exception_event(struct utp_upiu_rsp *ucd_rsp_ptr)
876{
877 return be32_to_cpu(ucd_rsp_ptr->header.dword_2) &
51d1628f 878 MASK_RSP_EXCEPTION_EVENT;
66ec6d59
SRT		 879}
880
7a3e97b0 881/**
7d568652 882 * ufshcd_reset_intr_aggr - Reset interrupt aggregation values.
7a3e97b0 883 * @hba: per adapter instance
7a3e97b0
SY		 884 */
885static inline void
7d568652 886ufshcd_reset_intr_aggr(struct ufs_hba *hba)
7a3e97b0 887{
7d568652
SJ		 888 ufshcd_writel(hba, INT_AGGR_ENABLE |
889 INT_AGGR_COUNTER_AND_TIMER_RESET,
890 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
891}
892
893/**
894 * ufshcd_config_intr_aggr - Configure interrupt aggregation values.
895 * @hba: per adapter instance
896 * @cnt: Interrupt aggregation counter threshold
897 * @tmout: Interrupt aggregation timeout value
898 */
899static inline void
900ufshcd_config_intr_aggr(struct ufs_hba *hba, u8 cnt, u8 tmout)
901{
902 ufshcd_writel(hba, INT_AGGR_ENABLE | INT_AGGR_PARAM_WRITE |
903 INT_AGGR_COUNTER_THLD_VAL(cnt) |
904 INT_AGGR_TIMEOUT_VAL(tmout),
905 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
7a3e97b0
SY		 906}
907
b852190e
YG		 908/**
909 * ufshcd_disable_intr_aggr - Disables interrupt aggregation.
910 * @hba: per adapter instance
911 */
912static inline void ufshcd_disable_intr_aggr(struct ufs_hba *hba)
913{
914 ufshcd_writel(hba, 0, REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
915}
916
7a3e97b0
SY		 917/**
918 * ufshcd_enable_run_stop_reg - Enable run-stop registers,
919 * When run-stop registers are set to 1, it indicates the
920 * host controller that it can process the requests
921 * @hba: per adapter instance
922 */
923static void ufshcd_enable_run_stop_reg(struct ufs_hba *hba)
924{
b873a275
SJ		 925 ufshcd_writel(hba, UTP_TASK_REQ_LIST_RUN_STOP_BIT,
926 REG_UTP_TASK_REQ_LIST_RUN_STOP);
927 ufshcd_writel(hba, UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT,
928 REG_UTP_TRANSFER_REQ_LIST_RUN_STOP);
7a3e97b0
SY		 929}
930
7a3e97b0
SY		 931/**
932 * ufshcd_hba_start - Start controller initialization sequence
933 * @hba: per adapter instance
934 */
935static inline void ufshcd_hba_start(struct ufs_hba *hba)
936{
df043c74
ST		 937 u32 val = CONTROLLER_ENABLE;
938
939 if (ufshcd_crypto_enable(hba))
940 val |= CRYPTO_GENERAL_ENABLE;
941
942 ufshcd_writel(hba, val, REG_CONTROLLER_ENABLE);
7a3e97b0
SY		 943}
944
945/**
946 * ufshcd_is_hba_active - Get controller state
947 * @hba: per adapter instance
948 *
acbbfe48 949 * Returns true if and only if the controller is active.
7a3e97b0 950 */
c9e6010b 951static inline bool ufshcd_is_hba_active(struct ufs_hba *hba)
7a3e97b0 952{
acbbfe48 953 return ufshcd_readl(hba, REG_CONTROLLER_ENABLE) & CONTROLLER_ENABLE;
7a3e97b0
SY		 954}
955
37113106
YG		 956u32 ufshcd_get_local_unipro_ver(struct ufs_hba *hba)
957{
958 /* HCI version 1.0 and 1.1 supports UniPro 1.41 */
51428818 959 if (hba->ufs_version <= ufshci_version(1, 1))
37113106
YG		 960 return UFS_UNIPRO_VER_1_41;
961 else
962 return UFS_UNIPRO_VER_1_6;
963}
964EXPORT_SYMBOL(ufshcd_get_local_unipro_ver);
965
966static bool ufshcd_is_unipro_pa_params_tuning_req(struct ufs_hba *hba)
967{
968 /*
969 * If both host and device support UniPro ver1.6 or later, PA layer
970 * parameters tuning happens during link startup itself.
971 *
972 * We can manually tune PA layer parameters if either host or device
973 * doesn't support UniPro ver 1.6 or later. But to keep manual tuning
974 * logic simple, we will only do manual tuning if local unipro version
975 * doesn't support ver1.6 or later.
976 */
a858af9a 977 return ufshcd_get_local_unipro_ver(hba) < UFS_UNIPRO_VER_1_6;
37113106
YG		 978}
979
394b949f
SJ		 980/**
981 * ufshcd_set_clk_freq - set UFS controller clock frequencies
982 * @hba: per adapter instance
983 * @scale_up: If True, set max possible frequency othewise set low frequency
984 *
985 * Returns 0 if successful
986 * Returns < 0 for any other errors
987 */
988static int ufshcd_set_clk_freq(struct ufs_hba *hba, bool scale_up)
a3cd5ec5 989{
990 int ret = 0;
991 struct ufs_clk_info *clki;
992 struct list_head *head = &hba->clk_list_head;
a3cd5ec5 993
566ec9ad 994 if (list_empty(head))
a3cd5ec5 995 goto out;
996
a3cd5ec5 997 list_for_each_entry(clki, head, list) {
998 if (!IS_ERR_OR_NULL(clki->clk)) {
999 if (scale_up && clki->max_freq) {
1000 if (clki->curr_freq == clki->max_freq)
1001 continue;
1002
a3cd5ec5 1003 ret = clk_set_rate(clki->clk, clki->max_freq);
1004 if (ret) {
1005 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
1006 __func__, clki->name,
1007 clki->max_freq, ret);
1008 break;
1009 }
1010 trace_ufshcd_clk_scaling(dev_name(hba->dev),
1011 "scaled up", clki->name,
1012 clki->curr_freq,
1013 clki->max_freq);
1014
1015 clki->curr_freq = clki->max_freq;
1016
1017 } else if (!scale_up && clki->min_freq) {
1018 if (clki->curr_freq == clki->min_freq)
1019 continue;
1020
a3cd5ec5 1021 ret = clk_set_rate(clki->clk, clki->min_freq);
1022 if (ret) {
1023 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
1024 __func__, clki->name,
1025 clki->min_freq, ret);
1026 break;
1027 }
1028 trace_ufshcd_clk_scaling(dev_name(hba->dev),
1029 "scaled down", clki->name,
1030 clki->curr_freq,
1031 clki->min_freq);
1032 clki->curr_freq = clki->min_freq;
1033 }
1034 }
1035 dev_dbg(hba->dev, "%s: clk: %s, rate: %lu\n", __func__,
1036 clki->name, clk_get_rate(clki->clk));
1037 }
1038
394b949f
SJ		 1039out:
1040 return ret;
1041}
1042
1043/**
1044 * ufshcd_scale_clks - scale up or scale down UFS controller clocks
1045 * @hba: per adapter instance
1046 * @scale_up: True if scaling up and false if scaling down
1047 *
1048 * Returns 0 if successful
1049 * Returns < 0 for any other errors
1050 */
1051static int ufshcd_scale_clks(struct ufs_hba *hba, bool scale_up)
1052{
1053 int ret = 0;
1054 ktime_t start = ktime_get();
1055
1056 ret = ufshcd_vops_clk_scale_notify(hba, scale_up, PRE_CHANGE);
1057 if (ret)
1058 goto out;
1059
1060 ret = ufshcd_set_clk_freq(hba, scale_up);
1061 if (ret)
1062 goto out;
1063
a3cd5ec5 1064 ret = ufshcd_vops_clk_scale_notify(hba, scale_up, POST_CHANGE);
394b949f
SJ		 1065 if (ret)
1066 ufshcd_set_clk_freq(hba, !scale_up);
a3cd5ec5 1067
1068out:
394b949f 1069 trace_ufshcd_profile_clk_scaling(dev_name(hba->dev),
a3cd5ec5 1070 (scale_up ? "up" : "down"),
1071 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
1072 return ret;
1073}
1074
1075/**
1076 * ufshcd_is_devfreq_scaling_required - check if scaling is required or not
1077 * @hba: per adapter instance
1078 * @scale_up: True if scaling up and false if scaling down
1079 *
1080 * Returns true if scaling is required, false otherwise.
1081 */
1082static bool ufshcd_is_devfreq_scaling_required(struct ufs_hba *hba,
1083 bool scale_up)
1084{
1085 struct ufs_clk_info *clki;
1086 struct list_head *head = &hba->clk_list_head;
1087
566ec9ad 1088 if (list_empty(head))
a3cd5ec5 1089 return false;
1090
1091 list_for_each_entry(clki, head, list) {
1092 if (!IS_ERR_OR_NULL(clki->clk)) {
1093 if (scale_up && clki->max_freq) {
1094 if (clki->curr_freq == clki->max_freq)
1095 continue;
1096 return true;
1097 } else if (!scale_up && clki->min_freq) {
1098 if (clki->curr_freq == clki->min_freq)
1099 continue;
1100 return true;
1101 }
1102 }
1103 }
1104
1105 return false;
1106}
1107
8d077ede
BVA		 1108/*
1109 * Determine the number of pending commands by counting the bits in the SCSI
1110 * device budget maps. This approach has been selected because a bit is set in
1111 * the budget map before scsi_host_queue_ready() checks the host_self_blocked
1112 * flag. The host_self_blocked flag can be modified by calling
1113 * scsi_block_requests() or scsi_unblock_requests().
1114 */
1115static u32 ufshcd_pending_cmds(struct ufs_hba *hba)
1116{
35d11ec2 1117 const struct scsi_device *sdev;
8d077ede
BVA		 1118 u32 pending = 0;
1119
99c66a88
BH		 1120 lockdep_assert_held(hba->host->host_lock);
1121 __shost_for_each_device(sdev, hba->host)
8d077ede
BVA		 1122 pending += sbitmap_weight(&sdev->budget_map);
1123
1124 return pending;
1125}
1126
b434ecfb
BVA		 1127/*
1128 * Wait until all pending SCSI commands and TMFs have finished or the timeout
1129 * has expired.
1130 *
1131 * Return: 0 upon success; -EBUSY upon timeout.
1132 */
a3cd5ec5 1133static int ufshcd_wait_for_doorbell_clr(struct ufs_hba *hba,
1134 u64 wait_timeout_us)
1135{
1136 unsigned long flags;
1137 int ret = 0;
1138 u32 tm_doorbell;
8d077ede 1139 u32 tr_pending;
a3cd5ec5 1140 bool timeout = false, do_last_check = false;
1141 ktime_t start;
1142
1143 ufshcd_hold(hba, false);
1144 spin_lock_irqsave(hba->host->host_lock, flags);
1145 /*
1146 * Wait for all the outstanding tasks/transfer requests.
1147 * Verify by checking the doorbell registers are clear.
1148 */
1149 start = ktime_get();
1150 do {
1151 if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL) {
1152 ret = -EBUSY;
1153 goto out;
1154 }
1155
1156 tm_doorbell = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL);
8d077ede
BVA		 1157 tr_pending = ufshcd_pending_cmds(hba);
1158 if (!tm_doorbell && !tr_pending) {
a3cd5ec5 1159 timeout = false;
1160 break;
1161 } else if (do_last_check) {
1162 break;
1163 }
1164
1165 spin_unlock_irqrestore(hba->host->host_lock, flags);
2000bc30 1166 io_schedule_timeout(msecs_to_jiffies(20));
a3cd5ec5 1167 if (ktime_to_us(ktime_sub(ktime_get(), start)) >
1168 wait_timeout_us) {
1169 timeout = true;
1170 /*
1171 * We might have scheduled out for long time so make
1172 * sure to check if doorbells are cleared by this time
1173 * or not.
1174 */
1175 do_last_check = true;
1176 }
1177 spin_lock_irqsave(hba->host->host_lock, flags);
8d077ede 1178 } while (tm_doorbell || tr_pending);
a3cd5ec5 1179
1180 if (timeout) {
1181 dev_err(hba->dev,
1182 "%s: timedout waiting for doorbell to clear (tm=0x%x, tr=0x%x)\n",
8d077ede 1183 __func__, tm_doorbell, tr_pending);
a3cd5ec5 1184 ret = -EBUSY;
1185 }
1186out:
1187 spin_unlock_irqrestore(hba->host->host_lock, flags);
1188 ufshcd_release(hba);
1189 return ret;
1190}
1191
1192/**
1193 * ufshcd_scale_gear - scale up/down UFS gear
1194 * @hba: per adapter instance
1195 * @scale_up: True for scaling up gear and false for scaling down
1196 *
1197 * Returns 0 for success,
1198 * Returns -EBUSY if scaling can't happen at this time
1199 * Returns non-zero for any other errors
1200 */
1201static int ufshcd_scale_gear(struct ufs_hba *hba, bool scale_up)
1202{
a3cd5ec5 1203 int ret = 0;
1204 struct ufs_pa_layer_attr new_pwr_info;
1205
1206 if (scale_up) {
1207 memcpy(&new_pwr_info, &hba->clk_scaling.saved_pwr_info.info,
1208 sizeof(struct ufs_pa_layer_attr));
1209 } else {
1210 memcpy(&new_pwr_info, &hba->pwr_info,
1211 sizeof(struct ufs_pa_layer_attr));
1212
29b87e92
CG		 1213 if (hba->pwr_info.gear_tx > hba->clk_scaling.min_gear ||
1214 hba->pwr_info.gear_rx > hba->clk_scaling.min_gear) {
a3cd5ec5 1215 /* save the current power mode */
1216 memcpy(&hba->clk_scaling.saved_pwr_info.info,
1217 &hba->pwr_info,
1218 sizeof(struct ufs_pa_layer_attr));
1219
1220 /* scale down gear */
29b87e92
CG		 1221 new_pwr_info.gear_tx = hba->clk_scaling.min_gear;
1222 new_pwr_info.gear_rx = hba->clk_scaling.min_gear;
a3cd5ec5 1223 }
1224 }
1225
1226 /* check if the power mode needs to be changed or not? */
6a9df818 1227 ret = ufshcd_config_pwr_mode(hba, &new_pwr_info);
a3cd5ec5 1228 if (ret)
1229 dev_err(hba->dev, "%s: failed err %d, old gear: (tx %d rx %d), new gear: (tx %d rx %d)",
1230 __func__, ret,
1231 hba->pwr_info.gear_tx, hba->pwr_info.gear_rx,
1232 new_pwr_info.gear_tx, new_pwr_info.gear_rx);
1233
1234 return ret;
1235}
1236
b434ecfb
BVA		 1237/*
1238 * Wait until all pending SCSI commands and TMFs have finished or the timeout
1239 * has expired.
1240 *
1241 * Return: 0 upon success; -EBUSY upon timeout.
1242 */
1243static int ufshcd_clock_scaling_prepare(struct ufs_hba *hba, u64 timeout_us)
a3cd5ec5 1244{
a3cd5ec5 1245 int ret = 0;
1246 /*
1247 * make sure that there are no outstanding requests when
1248 * clock scaling is in progress
1249 */
38135535 1250 ufshcd_scsi_block_requests(hba);
a3cd5ec5 1251 down_write(&hba->clk_scaling_lock);
0e9d4ca4
CG		 1252
1253 if (!hba->clk_scaling.is_allowed ||
b434ecfb 1254 ufshcd_wait_for_doorbell_clr(hba, timeout_us)) {
a3cd5ec5 1255 ret = -EBUSY;
1256 up_write(&hba->clk_scaling_lock);
38135535 1257 ufshcd_scsi_unblock_requests(hba);
0e9d4ca4 1258 goto out;
a3cd5ec5 1259 }
1260
0e9d4ca4
CG		 1261 /* let's not get into low power until clock scaling is completed */
1262 ufshcd_hold(hba, false);
1263
1264out:
a3cd5ec5 1265 return ret;
1266}
1267
0e9d4ca4 1268static void ufshcd_clock_scaling_unprepare(struct ufs_hba *hba, bool writelock)
a3cd5ec5 1269{
0e9d4ca4
CG		 1270 if (writelock)
1271 up_write(&hba->clk_scaling_lock);
1272 else
1273 up_read(&hba->clk_scaling_lock);
38135535 1274 ufshcd_scsi_unblock_requests(hba);
0e9d4ca4 1275 ufshcd_release(hba);
a3cd5ec5 1276}
1277
1278/**
1279 * ufshcd_devfreq_scale - scale up/down UFS clocks and gear
1280 * @hba: per adapter instance
1281 * @scale_up: True for scaling up and false for scalin down
1282 *
1283 * Returns 0 for success,
1284 * Returns -EBUSY if scaling can't happen at this time
1285 * Returns non-zero for any other errors
1286 */
1287static int ufshcd_devfreq_scale(struct ufs_hba *hba, bool scale_up)
1288{
1289 int ret = 0;
0e9d4ca4 1290 bool is_writelock = true;
401f1e44 1291
b434ecfb 1292 ret = ufshcd_clock_scaling_prepare(hba, 1 * USEC_PER_SEC);
a3cd5ec5 1293 if (ret)
0e9d4ca4 1294 return ret;
a3cd5ec5 1295
1296 /* scale down the gear before scaling down clocks */
1297 if (!scale_up) {
1298 ret = ufshcd_scale_gear(hba, false);
1299 if (ret)
394b949f 1300 goto out_unprepare;
a3cd5ec5 1301 }
1302
1303 ret = ufshcd_scale_clks(hba, scale_up);
1304 if (ret) {
1305 if (!scale_up)
1306 ufshcd_scale_gear(hba, true);
394b949f 1307 goto out_unprepare;
a3cd5ec5 1308 }
1309
1310 /* scale up the gear after scaling up clocks */
1311 if (scale_up) {
1312 ret = ufshcd_scale_gear(hba, true);
3d17b9b5 1313 if (ret) {
a3cd5ec5 1314 ufshcd_scale_clks(hba, false);
3d17b9b5
AD		 1315 goto out_unprepare;
1316 }
a3cd5ec5 1317 }
1318
3d17b9b5 1319 /* Enable Write Booster if we have scaled up else disable it */
87bd0501
PW		 1320 if (ufshcd_enable_wb_if_scaling_up(hba)) {
1321 downgrade_write(&hba->clk_scaling_lock);
1322 is_writelock = false;
1323 ufshcd_wb_toggle(hba, scale_up);
1324 }
3d17b9b5 1325
394b949f 1326out_unprepare:
0e9d4ca4 1327 ufshcd_clock_scaling_unprepare(hba, is_writelock);
a3cd5ec5 1328 return ret;
1329}
1330
401f1e44 1331static void ufshcd_clk_scaling_suspend_work(struct work_struct *work)
1332{
1333 struct ufs_hba *hba = container_of(work, struct ufs_hba,
1334 clk_scaling.suspend_work);
1335 unsigned long irq_flags;
1336
1337 spin_lock_irqsave(hba->host->host_lock, irq_flags);
1338 if (hba->clk_scaling.active_reqs || hba->clk_scaling.is_suspended) {
1339 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1340 return;
1341 }
1342 hba->clk_scaling.is_suspended = true;
1343 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1344
1345 __ufshcd_suspend_clkscaling(hba);
1346}
1347
1348static void ufshcd_clk_scaling_resume_work(struct work_struct *work)
1349{
1350 struct ufs_hba *hba = container_of(work, struct ufs_hba,
1351 clk_scaling.resume_work);
1352 unsigned long irq_flags;
1353
1354 spin_lock_irqsave(hba->host->host_lock, irq_flags);
1355 if (!hba->clk_scaling.is_suspended) {
1356 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1357 return;
1358 }
1359 hba->clk_scaling.is_suspended = false;
1360 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1361
1362 devfreq_resume_device(hba->devfreq);
1363}
1364
a3cd5ec5 1365static int ufshcd_devfreq_target(struct device *dev,
1366 unsigned long *freq, u32 flags)
1367{
1368 int ret = 0;
1369 struct ufs_hba *hba = dev_get_drvdata(dev);
1370 ktime_t start;
401f1e44 1371 bool scale_up, sched_clk_scaling_suspend_work = false;
092b4558
BA		 1372 struct list_head *clk_list = &hba->clk_list_head;
1373 struct ufs_clk_info *clki;
a3cd5ec5 1374 unsigned long irq_flags;
1375
1376 if (!ufshcd_is_clkscaling_supported(hba))
1377 return -EINVAL;
1378
91831d33
AD		 1379 clki = list_first_entry(&hba->clk_list_head, struct ufs_clk_info, list);
1380 /* Override with the closest supported frequency */
1381 *freq = (unsigned long) clk_round_rate(clki->clk, *freq);
a3cd5ec5 1382 spin_lock_irqsave(hba->host->host_lock, irq_flags);
1383 if (ufshcd_eh_in_progress(hba)) {
1384 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1385 return 0;
1386 }
1387
401f1e44 1388 if (!hba->clk_scaling.active_reqs)
1389 sched_clk_scaling_suspend_work = true;
1390
092b4558
BA		 1391 if (list_empty(clk_list)) {
1392 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1393 goto out;
1394 }
1395
91831d33 1396 /* Decide based on the rounded-off frequency and update */
51d1628f 1397 scale_up = *freq == clki->max_freq;
91831d33
AD		 1398 if (!scale_up)
1399 *freq = clki->min_freq;
1400 /* Update the frequency */
401f1e44 1401 if (!ufshcd_is_devfreq_scaling_required(hba, scale_up)) {
1402 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1403 ret = 0;
1404 goto out; /* no state change required */
a3cd5ec5 1405 }
1406 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1407
1408 start = ktime_get();
a3cd5ec5 1409 ret = ufshcd_devfreq_scale(hba, scale_up);
1410
a3cd5ec5 1411 trace_ufshcd_profile_clk_scaling(dev_name(hba->dev),
1412 (scale_up ? "up" : "down"),
1413 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
1414
401f1e44 1415out:
1416 if (sched_clk_scaling_suspend_work)
1417 queue_work(hba->clk_scaling.workq,
1418 &hba->clk_scaling.suspend_work);
1419
a3cd5ec5 1420 return ret;
1421}
1422
a3cd5ec5 1423static int ufshcd_devfreq_get_dev_status(struct device *dev,
1424 struct devfreq_dev_status *stat)
1425{
1426 struct ufs_hba *hba = dev_get_drvdata(dev);
1427 struct ufs_clk_scaling *scaling = &hba->clk_scaling;
1428 unsigned long flags;
91831d33
AD		 1429 struct list_head *clk_list = &hba->clk_list_head;
1430 struct ufs_clk_info *clki;
b1bf66d1 1431 ktime_t curr_t;
a3cd5ec5 1432
1433 if (!ufshcd_is_clkscaling_supported(hba))
1434 return -EINVAL;
1435
1436 memset(stat, 0, sizeof(*stat));
1437
1438 spin_lock_irqsave(hba->host->host_lock, flags);
b1bf66d1 1439 curr_t = ktime_get();
a3cd5ec5 1440 if (!scaling->window_start_t)
1441 goto start_window;
1442
91831d33
AD		 1443 clki = list_first_entry(clk_list, struct ufs_clk_info, list);
1444 /*
1445 * If current frequency is 0, then the ondemand governor considers
1446 * there's no initial frequency set. And it always requests to set
1447 * to max. frequency.
1448 */
1449 stat->current_frequency = clki->curr_freq;
a3cd5ec5 1450 if (scaling->is_busy_started)
b1bf66d1
SC		 1451 scaling->tot_busy_t += ktime_us_delta(curr_t,
1452 scaling->busy_start_t);
a3cd5ec5 1453
b1bf66d1 1454 stat->total_time = ktime_us_delta(curr_t, scaling->window_start_t);
a3cd5ec5 1455 stat->busy_time = scaling->tot_busy_t;
1456start_window:
b1bf66d1 1457 scaling->window_start_t = curr_t;
a3cd5ec5 1458 scaling->tot_busy_t = 0;
1459
1460 if (hba->outstanding_reqs) {
b1bf66d1 1461 scaling->busy_start_t = curr_t;
a3cd5ec5 1462 scaling->is_busy_started = true;
1463 } else {
1464 scaling->busy_start_t = 0;
1465 scaling->is_busy_started = false;
1466 }
1467 spin_unlock_irqrestore(hba->host->host_lock, flags);
1468 return 0;
1469}
1470
deac444f
BA		 1471static int ufshcd_devfreq_init(struct ufs_hba *hba)
1472{
092b4558
BA		 1473 struct list_head *clk_list = &hba->clk_list_head;
1474 struct ufs_clk_info *clki;
deac444f
BA		 1475 struct devfreq *devfreq;
1476 int ret;
1477
092b4558
BA		 1478 /* Skip devfreq if we don't have any clocks in the list */
1479 if (list_empty(clk_list))
1480 return 0;
1481
1482 clki = list_first_entry(clk_list, struct ufs_clk_info, list);
1483 dev_pm_opp_add(hba->dev, clki->min_freq, 0);
1484 dev_pm_opp_add(hba->dev, clki->max_freq, 0);
1485
90b8491c
SC		 1486 ufshcd_vops_config_scaling_param(hba, &hba->vps->devfreq_profile,
1487 &hba->vps->ondemand_data);
092b4558 1488 devfreq = devfreq_add_device(hba->dev,
90b8491c 1489 &hba->vps->devfreq_profile,
deac444f 1490 DEVFREQ_GOV_SIMPLE_ONDEMAND,
90b8491c 1491 &hba->vps->ondemand_data);
deac444f
BA		 1492 if (IS_ERR(devfreq)) {
1493 ret = PTR_ERR(devfreq);
1494 dev_err(hba->dev, "Unable to register with devfreq %d\n", ret);
092b4558
BA		 1495
1496 dev_pm_opp_remove(hba->dev, clki->min_freq);
1497 dev_pm_opp_remove(hba->dev, clki->max_freq);
deac444f
BA		 1498 return ret;
1499 }
1500
1501 hba->devfreq = devfreq;
1502
1503 return 0;
1504}
1505
092b4558
BA		 1506static void ufshcd_devfreq_remove(struct ufs_hba *hba)
1507{
1508 struct list_head *clk_list = &hba->clk_list_head;
1509 struct ufs_clk_info *clki;
1510
1511 if (!hba->devfreq)
1512 return;
1513
1514 devfreq_remove_device(hba->devfreq);
1515 hba->devfreq = NULL;
1516
1517 clki = list_first_entry(clk_list, struct ufs_clk_info, list);
1518 dev_pm_opp_remove(hba->dev, clki->min_freq);
1519 dev_pm_opp_remove(hba->dev, clki->max_freq);
1520}
1521
401f1e44 1522static void __ufshcd_suspend_clkscaling(struct ufs_hba *hba)
1523{
1524 unsigned long flags;
1525
1526 devfreq_suspend_device(hba->devfreq);
1527 spin_lock_irqsave(hba->host->host_lock, flags);
1528 hba->clk_scaling.window_start_t = 0;
1529 spin_unlock_irqrestore(hba->host->host_lock, flags);
1530}
a3cd5ec5 1531
a508253d
GB		 1532static void ufshcd_suspend_clkscaling(struct ufs_hba *hba)
1533{
401f1e44 1534 unsigned long flags;
1535 bool suspend = false;
1536
f9a7fa34
SC		 1537 cancel_work_sync(&hba->clk_scaling.suspend_work);
1538 cancel_work_sync(&hba->clk_scaling.resume_work);
fcb0c4b0 1539
401f1e44 1540 spin_lock_irqsave(hba->host->host_lock, flags);
1541 if (!hba->clk_scaling.is_suspended) {
1542 suspend = true;
1543 hba->clk_scaling.is_suspended = true;
1544 }
1545 spin_unlock_irqrestore(hba->host->host_lock, flags);
1546
1547 if (suspend)
1548 __ufshcd_suspend_clkscaling(hba);
a508253d
GB		 1549}
1550
1551static void ufshcd_resume_clkscaling(struct ufs_hba *hba)
1552{
401f1e44 1553 unsigned long flags;
1554 bool resume = false;
1555
401f1e44 1556 spin_lock_irqsave(hba->host->host_lock, flags);
1557 if (hba->clk_scaling.is_suspended) {
1558 resume = true;
1559 hba->clk_scaling.is_suspended = false;
1560 }
1561 spin_unlock_irqrestore(hba->host->host_lock, flags);
1562
1563 if (resume)
1564 devfreq_resume_device(hba->devfreq);
fcb0c4b0
ST		 1565}
1566
1567static ssize_t ufshcd_clkscale_enable_show(struct device *dev,
1568 struct device_attribute *attr, char *buf)
1569{
1570 struct ufs_hba *hba = dev_get_drvdata(dev);
1571
1481b7fe 1572 return sysfs_emit(buf, "%d\n", hba->clk_scaling.is_enabled);
fcb0c4b0
ST		 1573}
1574
1575static ssize_t ufshcd_clkscale_enable_store(struct device *dev,
1576 struct device_attribute *attr, const char *buf, size_t count)
1577{
1578 struct ufs_hba *hba = dev_get_drvdata(dev);
1579 u32 value;
9cd20d3f 1580 int err = 0;
fcb0c4b0
ST		 1581
1582 if (kstrtou32(buf, 0, &value))
1583 return -EINVAL;
1584
9cd20d3f
CG		 1585 down(&hba->host_sem);
1586 if (!ufshcd_is_user_access_allowed(hba)) {
1587 err = -EBUSY;
1588 goto out;
1589 }
1590
fcb0c4b0 1591 value = !!value;
0e9d4ca4 1592 if (value == hba->clk_scaling.is_enabled)
fcb0c4b0
ST		 1593 goto out;
1594
b294ff3e 1595 ufshcd_rpm_get_sync(hba);
fcb0c4b0
ST		 1596 ufshcd_hold(hba, false);
1597
0e9d4ca4 1598 hba->clk_scaling.is_enabled = value;
401f1e44 1599
fcb0c4b0
ST		 1600 if (value) {
1601 ufshcd_resume_clkscaling(hba);
1602 } else {
1603 ufshcd_suspend_clkscaling(hba);
a3cd5ec5 1604 err = ufshcd_devfreq_scale(hba, true);
fcb0c4b0
ST		 1605 if (err)
1606 dev_err(hba->dev, "%s: failed to scale clocks up %d\n",
1607 __func__, err);
1608 }
fcb0c4b0
ST		 1609
1610 ufshcd_release(hba);
b294ff3e 1611 ufshcd_rpm_put_sync(hba);
fcb0c4b0 1612out:
9cd20d3f
CG		 1613 up(&hba->host_sem);
1614 return err ? err : count;
a508253d
GB		 1615}
1616
4543d9d7 1617static void ufshcd_init_clk_scaling_sysfs(struct ufs_hba *hba)
a3cd5ec5 1618{
1619 hba->clk_scaling.enable_attr.show = ufshcd_clkscale_enable_show;
1620 hba->clk_scaling.enable_attr.store = ufshcd_clkscale_enable_store;
1621 sysfs_attr_init(&hba->clk_scaling.enable_attr.attr);
1622 hba->clk_scaling.enable_attr.attr.name = "clkscale_enable";
1623 hba->clk_scaling.enable_attr.attr.mode = 0644;
1624 if (device_create_file(hba->dev, &hba->clk_scaling.enable_attr))
1625 dev_err(hba->dev, "Failed to create sysfs for clkscale_enable\n");
1626}
1627
4543d9d7
CG		 1628static void ufshcd_remove_clk_scaling_sysfs(struct ufs_hba *hba)
1629{
1630 if (hba->clk_scaling.enable_attr.attr.name)
1631 device_remove_file(hba->dev, &hba->clk_scaling.enable_attr);
1632}
1633
1634static void ufshcd_init_clk_scaling(struct ufs_hba *hba)
1635{
1636 char wq_name[sizeof("ufs_clkscaling_00")];
1637
1638 if (!ufshcd_is_clkscaling_supported(hba))
1639 return;
1640
80d892f4
CG		 1641 if (!hba->clk_scaling.min_gear)
1642 hba->clk_scaling.min_gear = UFS_HS_G1;
1643
4543d9d7
CG		 1644 INIT_WORK(&hba->clk_scaling.suspend_work,
1645 ufshcd_clk_scaling_suspend_work);
1646 INIT_WORK(&hba->clk_scaling.resume_work,
1647 ufshcd_clk_scaling_resume_work);
1648
1649 snprintf(wq_name, sizeof(wq_name), "ufs_clkscaling_%d",
1650 hba->host->host_no);
1651 hba->clk_scaling.workq = create_singlethread_workqueue(wq_name);
1652
1653 hba->clk_scaling.is_initialized = true;
1654}
1655
1656static void ufshcd_exit_clk_scaling(struct ufs_hba *hba)
1657{
1658 if (!hba->clk_scaling.is_initialized)
1659 return;
1660
1661 ufshcd_remove_clk_scaling_sysfs(hba);
1662 destroy_workqueue(hba->clk_scaling.workq);
1663 ufshcd_devfreq_remove(hba);
1664 hba->clk_scaling.is_initialized = false;
1665}
1666
1ab27c9c
ST		 1667static void ufshcd_ungate_work(struct work_struct *work)
1668{
1669 int ret;
1670 unsigned long flags;
1671 struct ufs_hba *hba = container_of(work, struct ufs_hba,
1672 clk_gating.ungate_work);
1673
1674 cancel_delayed_work_sync(&hba->clk_gating.gate_work);
1675
1676 spin_lock_irqsave(hba->host->host_lock, flags);
1677 if (hba->clk_gating.state == CLKS_ON) {
1678 spin_unlock_irqrestore(hba->host->host_lock, flags);
1679 goto unblock_reqs;
1680 }
1681
1682 spin_unlock_irqrestore(hba->host->host_lock, flags);
dd7143e2 1683 ufshcd_hba_vreg_set_hpm(hba);
1ab27c9c
ST		 1684 ufshcd_setup_clocks(hba, true);
1685
8b0bbf00
SC		 1686 ufshcd_enable_irq(hba);
1687
1ab27c9c
ST		 1688 /* Exit from hibern8 */
1689 if (ufshcd_can_hibern8_during_gating(hba)) {
1690 /* Prevent gating in this path */
1691 hba->clk_gating.is_suspended = true;
1692 if (ufshcd_is_link_hibern8(hba)) {
1693 ret = ufshcd_uic_hibern8_exit(hba);
1694 if (ret)
1695 dev_err(hba->dev, "%s: hibern8 exit failed %d\n",
1696 __func__, ret);
1697 else
1698 ufshcd_set_link_active(hba);
1699 }
1700 hba->clk_gating.is_suspended = false;
1701 }
1702unblock_reqs:
38135535 1703 ufshcd_scsi_unblock_requests(hba);
1ab27c9c
ST		 1704}
1705
1706/**
1707 * ufshcd_hold - Enable clocks that were gated earlier due to ufshcd_release.
1708 * Also, exit from hibern8 mode and set the link as active.
1709 * @hba: per adapter instance
1710 * @async: This indicates whether caller should ungate clocks asynchronously.
1711 */
1712int ufshcd_hold(struct ufs_hba *hba, bool async)
1713{
1714 int rc = 0;
93b6c5db 1715 bool flush_result;
1ab27c9c
ST		 1716 unsigned long flags;
1717
3489c34b
BVA		 1718 if (!ufshcd_is_clkgating_allowed(hba) ||
1719 !hba->clk_gating.is_initialized)
1ab27c9c 1720 goto out;
1ab27c9c
ST		 1721 spin_lock_irqsave(hba->host->host_lock, flags);
1722 hba->clk_gating.active_reqs++;
1723
856b3483 1724start:
1ab27c9c
ST		 1725 switch (hba->clk_gating.state) {
1726 case CLKS_ON:
f2a785ac
VG		 1727 /*
1728 * Wait for the ungate work to complete if in progress.
1729 * Though the clocks may be in ON state, the link could
1730 * still be in hibner8 state if hibern8 is allowed
1731 * during clock gating.
1732 * Make sure we exit hibern8 state also in addition to
1733 * clocks being ON.
1734 */
1735 if (ufshcd_can_hibern8_during_gating(hba) &&
1736 ufshcd_is_link_hibern8(hba)) {
c63d6099
CG		 1737 if (async) {
1738 rc = -EAGAIN;
1739 hba->clk_gating.active_reqs--;
1740 break;
1741 }
f2a785ac 1742 spin_unlock_irqrestore(hba->host->host_lock, flags);
93b6c5db
SC		 1743 flush_result = flush_work(&hba->clk_gating.ungate_work);
1744 if (hba->clk_gating.is_suspended && !flush_result)
1745 goto out;
f2a785ac
VG		 1746 spin_lock_irqsave(hba->host->host_lock, flags);
1747 goto start;
1748 }
1ab27c9c
ST		 1749 break;
1750 case REQ_CLKS_OFF:
1751 if (cancel_delayed_work(&hba->clk_gating.gate_work)) {
1752 hba->clk_gating.state = CLKS_ON;
7ff5ab47 1753 trace_ufshcd_clk_gating(dev_name(hba->dev),
1754 hba->clk_gating.state);
1ab27c9c
ST		 1755 break;
1756 }
1757 /*
9c490d2d 1758 * If we are here, it means gating work is either done or
1ab27c9c
ST		 1759 * currently running. Hence, fall through to cancel gating
1760 * work and to enable clocks.
1761 */
df561f66 1762 fallthrough;
1ab27c9c 1763 case CLKS_OFF:
1ab27c9c 1764 hba->clk_gating.state = REQ_CLKS_ON;
7ff5ab47 1765 trace_ufshcd_clk_gating(dev_name(hba->dev),
1766 hba->clk_gating.state);
da3fecb0
CG		 1767 if (queue_work(hba->clk_gating.clk_gating_workq,
1768 &hba->clk_gating.ungate_work))
1769 ufshcd_scsi_block_requests(hba);
1ab27c9c
ST		 1770 /*
1771 * fall through to check if we should wait for this
1772 * work to be done or not.
1773 */
df561f66 1774 fallthrough;
1ab27c9c
ST		 1775 case REQ_CLKS_ON:
1776 if (async) {
1777 rc = -EAGAIN;
1778 hba->clk_gating.active_reqs--;
1779 break;
1780 }
1781
1782 spin_unlock_irqrestore(hba->host->host_lock, flags);
1783 flush_work(&hba->clk_gating.ungate_work);
1784 /* Make sure state is CLKS_ON before returning */
856b3483 1785 spin_lock_irqsave(hba->host->host_lock, flags);
1ab27c9c
ST		 1786 goto start;
1787 default:
1788 dev_err(hba->dev, "%s: clk gating is in invalid state %d\n",
1789 __func__, hba->clk_gating.state);
1790 break;
1791 }
1792 spin_unlock_irqrestore(hba->host->host_lock, flags);
1793out:
1794 return rc;
1795}
6e3fd44d 1796EXPORT_SYMBOL_GPL(ufshcd_hold);
1ab27c9c
ST		 1797
1798static void ufshcd_gate_work(struct work_struct *work)
1799{
1800 struct ufs_hba *hba = container_of(work, struct ufs_hba,
1801 clk_gating.gate_work.work);
1802 unsigned long flags;
4db7a236 1803 int ret;
1ab27c9c
ST		 1804
1805 spin_lock_irqsave(hba->host->host_lock, flags);
3f0c06de
VG		 1806 /*
1807 * In case you are here to cancel this work the gating state
1808 * would be marked as REQ_CLKS_ON. In this case save time by
1809 * skipping the gating work and exit after changing the clock
1810 * state to CLKS_ON.
1811 */
1812 if (hba->clk_gating.is_suspended ||
18f01374 1813 (hba->clk_gating.state != REQ_CLKS_OFF)) {
1ab27c9c 1814 hba->clk_gating.state = CLKS_ON;
7ff5ab47 1815 trace_ufshcd_clk_gating(dev_name(hba->dev),
1816 hba->clk_gating.state);
1ab27c9c
ST		 1817 goto rel_lock;
1818 }
1819
1820 if (hba->clk_gating.active_reqs
1821 || hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL
bd0b3538 1822 || hba->outstanding_reqs || hba->outstanding_tasks
1ab27c9c
ST		 1823 || hba->active_uic_cmd || hba->uic_async_done)
1824 goto rel_lock;
1825
1826 spin_unlock_irqrestore(hba->host->host_lock, flags);
1827
1828 /* put the link into hibern8 mode before turning off clocks */
1829 if (ufshcd_can_hibern8_during_gating(hba)) {
4db7a236
CG		 1830 ret = ufshcd_uic_hibern8_enter(hba);
1831 if (ret) {
1ab27c9c 1832 hba->clk_gating.state = CLKS_ON;
4db7a236
CG		 1833 dev_err(hba->dev, "%s: hibern8 enter failed %d\n",
1834 __func__, ret);
7ff5ab47 1835 trace_ufshcd_clk_gating(dev_name(hba->dev),
1836 hba->clk_gating.state);
1ab27c9c
ST		 1837 goto out;
1838 }
1839 ufshcd_set_link_hibern8(hba);
1840 }
1841
8b0bbf00
SC		 1842 ufshcd_disable_irq(hba);
1843
81309c24 1844 ufshcd_setup_clocks(hba, false);
1ab27c9c 1845
dd7143e2
CG		 1846 /* Put the host controller in low power mode if possible */
1847 ufshcd_hba_vreg_set_lpm(hba);
1ab27c9c
ST		 1848 /*
1849 * In case you are here to cancel this work the gating state
1850 * would be marked as REQ_CLKS_ON. In this case keep the state
1851 * as REQ_CLKS_ON which would anyway imply that clocks are off
1852 * and a request to turn them on is pending. By doing this way,
1853 * we keep the state machine in tact and this would ultimately
1854 * prevent from doing cancel work multiple times when there are
1855 * new requests arriving before the current cancel work is done.
1856 */
1857 spin_lock_irqsave(hba->host->host_lock, flags);
7ff5ab47 1858 if (hba->clk_gating.state == REQ_CLKS_OFF) {
1ab27c9c 1859 hba->clk_gating.state = CLKS_OFF;
7ff5ab47 1860 trace_ufshcd_clk_gating(dev_name(hba->dev),
1861 hba->clk_gating.state);
1862 }
1ab27c9c
ST		 1863rel_lock:
1864 spin_unlock_irqrestore(hba->host->host_lock, flags);
1865out:
1866 return;
1867}
1868
1869/* host lock must be held before calling this variant */
1870static void __ufshcd_release(struct ufs_hba *hba)
1871{
1872 if (!ufshcd_is_clkgating_allowed(hba))
1873 return;
1874
1875 hba->clk_gating.active_reqs--;
1876
4db7a236
CG		 1877 if (hba->clk_gating.active_reqs || hba->clk_gating.is_suspended ||
1878 hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL ||
3489c34b 1879 hba->outstanding_tasks || !hba->clk_gating.is_initialized ||
fd62de11
JK		 1880 hba->active_uic_cmd || hba->uic_async_done ||
1881 hba->clk_gating.state == CLKS_OFF)
1ab27c9c
ST		 1882 return;
1883
1884 hba->clk_gating.state = REQ_CLKS_OFF;
7ff5ab47 1885 trace_ufshcd_clk_gating(dev_name(hba->dev), hba->clk_gating.state);
f4bb7704
EG		 1886 queue_delayed_work(hba->clk_gating.clk_gating_workq,
1887 &hba->clk_gating.gate_work,
1888 msecs_to_jiffies(hba->clk_gating.delay_ms));
1ab27c9c
ST		 1889}
1890
1891void ufshcd_release(struct ufs_hba *hba)
1892{
1893 unsigned long flags;
1894
1895 spin_lock_irqsave(hba->host->host_lock, flags);
1896 __ufshcd_release(hba);
1897 spin_unlock_irqrestore(hba->host->host_lock, flags);
1898}
6e3fd44d 1899EXPORT_SYMBOL_GPL(ufshcd_release);
1ab27c9c
ST		 1900
1901static ssize_t ufshcd_clkgate_delay_show(struct device *dev,
1902 struct device_attribute *attr, char *buf)
1903{
1904 struct ufs_hba *hba = dev_get_drvdata(dev);
1905
bafd09f8 1906 return sysfs_emit(buf, "%lu\n", hba->clk_gating.delay_ms);
1ab27c9c
ST		 1907}
1908
ad8a647e
BVA		 1909void ufshcd_clkgate_delay_set(struct device *dev, unsigned long value)
1910{
1911 struct ufs_hba *hba = dev_get_drvdata(dev);
1912 unsigned long flags;
1913
1914 spin_lock_irqsave(hba->host->host_lock, flags);
1915 hba->clk_gating.delay_ms = value;
1916 spin_unlock_irqrestore(hba->host->host_lock, flags);
1917}
1918EXPORT_SYMBOL_GPL(ufshcd_clkgate_delay_set);
1919
1ab27c9c
ST		 1920static ssize_t ufshcd_clkgate_delay_store(struct device *dev,
1921 struct device_attribute *attr, const char *buf, size_t count)
1922{
ad8a647e 1923 unsigned long value;
1ab27c9c
ST		 1924
1925 if (kstrtoul(buf, 0, &value))
1926 return -EINVAL;
1927
ad8a647e 1928 ufshcd_clkgate_delay_set(dev, value);
1ab27c9c
ST		 1929 return count;
1930}
1931
b427411a
ST		 1932static ssize_t ufshcd_clkgate_enable_show(struct device *dev,
1933 struct device_attribute *attr, char *buf)
1934{
1935 struct ufs_hba *hba = dev_get_drvdata(dev);
1936
bafd09f8 1937 return sysfs_emit(buf, "%d\n", hba->clk_gating.is_enabled);
b427411a
ST		 1938}
1939
1940static ssize_t ufshcd_clkgate_enable_store(struct device *dev,
1941 struct device_attribute *attr, const char *buf, size_t count)
1942{
1943 struct ufs_hba *hba = dev_get_drvdata(dev);
1944 unsigned long flags;
1945 u32 value;
1946
1947 if (kstrtou32(buf, 0, &value))
1948 return -EINVAL;
1949
1950 value = !!value;
b6645112
JK		 1951
1952 spin_lock_irqsave(hba->host->host_lock, flags);
b427411a
ST		 1953 if (value == hba->clk_gating.is_enabled)
1954 goto out;
1955
b6645112
JK		 1956 if (value)
1957 __ufshcd_release(hba);
1958 else
b427411a 1959 hba->clk_gating.active_reqs++;
b427411a
ST		 1960
1961 hba->clk_gating.is_enabled = value;
1962out:
b6645112 1963 spin_unlock_irqrestore(hba->host->host_lock, flags);
b427411a
ST		 1964 return count;
1965}
1966
4543d9d7 1967static void ufshcd_init_clk_gating_sysfs(struct ufs_hba *hba)
eebcc196 1968{
4543d9d7
CG		 1969 hba->clk_gating.delay_attr.show = ufshcd_clkgate_delay_show;
1970 hba->clk_gating.delay_attr.store = ufshcd_clkgate_delay_store;
1971 sysfs_attr_init(&hba->clk_gating.delay_attr.attr);
1972 hba->clk_gating.delay_attr.attr.name = "clkgate_delay_ms";
1973 hba->clk_gating.delay_attr.attr.mode = 0644;
1974 if (device_create_file(hba->dev, &hba->clk_gating.delay_attr))
1975 dev_err(hba->dev, "Failed to create sysfs for clkgate_delay\n");
eebcc196 1976
4543d9d7
CG		 1977 hba->clk_gating.enable_attr.show = ufshcd_clkgate_enable_show;
1978 hba->clk_gating.enable_attr.store = ufshcd_clkgate_enable_store;
1979 sysfs_attr_init(&hba->clk_gating.enable_attr.attr);
1980 hba->clk_gating.enable_attr.attr.name = "clkgate_enable";
1981 hba->clk_gating.enable_attr.attr.mode = 0644;
1982 if (device_create_file(hba->dev, &hba->clk_gating.enable_attr))
1983 dev_err(hba->dev, "Failed to create sysfs for clkgate_enable\n");
eebcc196
VG		 1984}
1985
4543d9d7 1986static void ufshcd_remove_clk_gating_sysfs(struct ufs_hba *hba)
eebcc196 1987{
4543d9d7
CG		 1988 if (hba->clk_gating.delay_attr.attr.name)
1989 device_remove_file(hba->dev, &hba->clk_gating.delay_attr);
1990 if (hba->clk_gating.enable_attr.attr.name)
1991 device_remove_file(hba->dev, &hba->clk_gating.enable_attr);
eebcc196
VG		 1992}
1993
1ab27c9c
ST		 1994static void ufshcd_init_clk_gating(struct ufs_hba *hba)
1995{
10e5e375
VV		 1996 char wq_name[sizeof("ufs_clk_gating_00")];
1997
1ab27c9c
ST		 1998 if (!ufshcd_is_clkgating_allowed(hba))
1999 return;
2000
2dec9475
CG		 2001 hba->clk_gating.state = CLKS_ON;
2002
1ab27c9c
ST		 2003 hba->clk_gating.delay_ms = 150;
2004 INIT_DELAYED_WORK(&hba->clk_gating.gate_work, ufshcd_gate_work);
2005 INIT_WORK(&hba->clk_gating.ungate_work, ufshcd_ungate_work);
2006
10e5e375
VV		 2007 snprintf(wq_name, ARRAY_SIZE(wq_name), "ufs_clk_gating_%d",
2008 hba->host->host_no);
2009 hba->clk_gating.clk_gating_workq = alloc_ordered_workqueue(wq_name,
e93e6e49 2010 WQ_MEM_RECLAIM | WQ_HIGHPRI);
10e5e375 2011
4543d9d7 2012 ufshcd_init_clk_gating_sysfs(hba);
b427411a 2013
4543d9d7
CG		 2014 hba->clk_gating.is_enabled = true;
2015 hba->clk_gating.is_initialized = true;
1ab27c9c
ST		 2016}
2017
2018static void ufshcd_exit_clk_gating(struct ufs_hba *hba)
2019{
4543d9d7 2020 if (!hba->clk_gating.is_initialized)
1ab27c9c 2021 return;
3489c34b 2022
4543d9d7 2023 ufshcd_remove_clk_gating_sysfs(hba);
3489c34b
BVA		 2024
2025 /* Ungate the clock if necessary. */
2026 ufshcd_hold(hba, false);
4543d9d7 2027 hba->clk_gating.is_initialized = false;
3489c34b
BVA		 2028 ufshcd_release(hba);
2029
2030 destroy_workqueue(hba->clk_gating.clk_gating_workq);
1ab27c9c
ST		 2031}
2032
856b3483
ST		 2033static void ufshcd_clk_scaling_start_busy(struct ufs_hba *hba)
2034{
401f1e44 2035 bool queue_resume_work = false;
b1bf66d1 2036 ktime_t curr_t = ktime_get();
a45f9371 2037 unsigned long flags;
401f1e44 2038
fcb0c4b0 2039 if (!ufshcd_is_clkscaling_supported(hba))
856b3483
ST		 2040 return;
2041
a45f9371 2042 spin_lock_irqsave(hba->host->host_lock, flags);
401f1e44 2043 if (!hba->clk_scaling.active_reqs++)
2044 queue_resume_work = true;
2045
a45f9371
CG		 2046 if (!hba->clk_scaling.is_enabled || hba->pm_op_in_progress) {
2047 spin_unlock_irqrestore(hba->host->host_lock, flags);
401f1e44 2048 return;
a45f9371 2049 }
401f1e44 2050
2051 if (queue_resume_work)
2052 queue_work(hba->clk_scaling.workq,
2053 &hba->clk_scaling.resume_work);
2054
2055 if (!hba->clk_scaling.window_start_t) {
b1bf66d1 2056 hba->clk_scaling.window_start_t = curr_t;
401f1e44 2057 hba->clk_scaling.tot_busy_t = 0;
2058 hba->clk_scaling.is_busy_started = false;
2059 }
2060
856b3483 2061 if (!hba->clk_scaling.is_busy_started) {
b1bf66d1 2062 hba->clk_scaling.busy_start_t = curr_t;
856b3483
ST		 2063 hba->clk_scaling.is_busy_started = true;
2064 }
a45f9371 2065 spin_unlock_irqrestore(hba->host->host_lock, flags);
856b3483
ST		 2066}
2067
2068static void ufshcd_clk_scaling_update_busy(struct ufs_hba *hba)
2069{
2070 struct ufs_clk_scaling *scaling = &hba->clk_scaling;
a45f9371 2071 unsigned long flags;
856b3483 2072
fcb0c4b0 2073 if (!ufshcd_is_clkscaling_supported(hba))
856b3483
ST		 2074 return;
2075
a45f9371
CG		 2076 spin_lock_irqsave(hba->host->host_lock, flags);
2077 hba->clk_scaling.active_reqs--;
856b3483
ST		 2078 if (!hba->outstanding_reqs && scaling->is_busy_started) {
2079 scaling->tot_busy_t += ktime_to_us(ktime_sub(ktime_get(),
2080 scaling->busy_start_t));
8b0e1953 2081 scaling->busy_start_t = 0;
856b3483
ST		 2082 scaling->is_busy_started = false;
2083 }
a45f9371 2084 spin_unlock_irqrestore(hba->host->host_lock, flags);
856b3483 2085}
1d8613a2
CG		 2086
2087static inline int ufshcd_monitor_opcode2dir(u8 opcode)
2088{
2089 if (opcode == READ_6 || opcode == READ_10 || opcode == READ_16)
2090 return READ;
2091 else if (opcode == WRITE_6 || opcode == WRITE_10 || opcode == WRITE_16)
2092 return WRITE;
2093 else
2094 return -EINVAL;
2095}
2096
2097static inline bool ufshcd_should_inform_monitor(struct ufs_hba *hba,
2098 struct ufshcd_lrb *lrbp)
2099{
35d11ec2 2100 const struct ufs_hba_monitor *m = &hba->monitor;
1d8613a2
CG		 2101
2102 return (m->enabled && lrbp && lrbp->cmd &&
2103 (!m->chunk_size || m->chunk_size == lrbp->cmd->sdb.length) &&
2104 ktime_before(hba->monitor.enabled_ts, lrbp->issue_time_stamp));
2105}
2106
35d11ec2
KK		 2107static void ufshcd_start_monitor(struct ufs_hba *hba,
2108 const struct ufshcd_lrb *lrbp)
1d8613a2
CG		 2109{
2110 int dir = ufshcd_monitor_opcode2dir(*lrbp->cmd->cmnd);
a45f9371 2111 unsigned long flags;
1d8613a2 2112
a45f9371 2113 spin_lock_irqsave(hba->host->host_lock, flags);
1d8613a2
CG		 2114 if (dir >= 0 && hba->monitor.nr_queued[dir]++ == 0)
2115 hba->monitor.busy_start_ts[dir] = ktime_get();
a45f9371 2116 spin_unlock_irqrestore(hba->host->host_lock, flags);
1d8613a2
CG		 2117}
2118
35d11ec2 2119static void ufshcd_update_monitor(struct ufs_hba *hba, const struct ufshcd_lrb *lrbp)
1d8613a2
CG		 2120{
2121 int dir = ufshcd_monitor_opcode2dir(*lrbp->cmd->cmnd);
a45f9371 2122 unsigned long flags;
1d8613a2 2123
a45f9371 2124 spin_lock_irqsave(hba->host->host_lock, flags);
1d8613a2 2125 if (dir >= 0 && hba->monitor.nr_queued[dir] > 0) {
35d11ec2 2126 const struct request *req = scsi_cmd_to_rq(lrbp->cmd);
1d8613a2
CG		 2127 struct ufs_hba_monitor *m = &hba->monitor;
2128 ktime_t now, inc, lat;
2129
2130 now = lrbp->compl_time_stamp;
2131 inc = ktime_sub(now, m->busy_start_ts[dir]);
2132 m->total_busy[dir] = ktime_add(m->total_busy[dir], inc);
2133 m->nr_sec_rw[dir] += blk_rq_sectors(req);
2134
2135 /* Update latencies */
2136 m->nr_req[dir]++;
2137 lat = ktime_sub(now, lrbp->issue_time_stamp);
2138 m->lat_sum[dir] += lat;
2139 if (m->lat_max[dir] < lat || !m->lat_max[dir])
2140 m->lat_max[dir] = lat;
2141 if (m->lat_min[dir] > lat || !m->lat_min[dir])
2142 m->lat_min[dir] = lat;
2143
2144 m->nr_queued[dir]--;
2145 /* Push forward the busy start of monitor */
2146 m->busy_start_ts[dir] = now;
2147 }
a45f9371 2148 spin_unlock_irqrestore(hba->host->host_lock, flags);
856b3483 2149}
1d8613a2 2150
7a3e97b0
SY		 2151/**
2152 * ufshcd_send_command - Send SCSI or device management commands
2153 * @hba: per adapter instance
2154 * @task_tag: Task tag of the command
2155 */
2156static inline
2157void ufshcd_send_command(struct ufs_hba *hba, unsigned int task_tag)
2158{
6edfdcfe 2159 struct ufshcd_lrb *lrbp = &hba->lrb[task_tag];
1f522c50 2160 unsigned long flags;
6edfdcfe
SC		 2161
2162 lrbp->issue_time_stamp = ktime_get();
0f85e747 2163 lrbp->issue_time_stamp_local_clock = local_clock();
6edfdcfe 2164 lrbp->compl_time_stamp = ktime_set(0, 0);
0f85e747 2165 lrbp->compl_time_stamp_local_clock = 0;
28fa68fc 2166 ufshcd_add_command_trace(hba, task_tag, UFS_CMD_SEND);
856b3483 2167 ufshcd_clk_scaling_start_busy(hba);
1d8613a2
CG		 2168 if (unlikely(ufshcd_should_inform_monitor(hba, lrbp)))
2169 ufshcd_start_monitor(hba, lrbp);
169f5eb2
BVA		 2170
2171 spin_lock_irqsave(&hba->outstanding_lock, flags);
a024ad0d
BVA		 2172 if (hba->vops && hba->vops->setup_xfer_req)
2173 hba->vops->setup_xfer_req(hba, task_tag, !!lrbp->cmd);
169f5eb2 2174 __set_bit(task_tag, &hba->outstanding_reqs);
1f522c50 2175 ufshcd_writel(hba, 1 << task_tag, REG_UTP_TRANSFER_REQ_DOOR_BELL);
169f5eb2 2176 spin_unlock_irqrestore(&hba->outstanding_lock, flags);
7a3e97b0
SY		 2177}
2178
2179/**
2180 * ufshcd_copy_sense_data - Copy sense data in case of check condition
8aa29f19 2181 * @lrbp: pointer to local reference block
7a3e97b0
SY		 2182 */
2183static inline void ufshcd_copy_sense_data(struct ufshcd_lrb *lrbp)
2184{
1de4378f 2185 u8 *const sense_buffer = lrbp->cmd->sense_buffer;
7a3e97b0 2186 int len;
1de4378f
BVA		 2187
2188 if (sense_buffer &&
1c2623c5 2189 ufshcd_get_rsp_upiu_data_seg_len(lrbp->ucd_rsp_ptr)) {
e3ce73d6
YG		 2190 int len_to_copy;
2191
5a0b0cb9 2192 len = be16_to_cpu(lrbp->ucd_rsp_ptr->sr.sense_data_len);
09a5a24f 2193 len_to_copy = min_t(int, UFS_SENSE_SIZE, len);
e3ce73d6 2194
1de4378f 2195 memcpy(sense_buffer, lrbp->ucd_rsp_ptr->sr.sense_data,
09a5a24f 2196 len_to_copy);
7a3e97b0
SY		 2197 }
2198}
2199
68078d5c
DR		 2200/**
2201 * ufshcd_copy_query_response() - Copy the Query Response and the data
2202 * descriptor
2203 * @hba: per adapter instance
8aa29f19 2204 * @lrbp: pointer to local reference block
68078d5c
DR		 2205 */
2206static
c6d4a831 2207int ufshcd_copy_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
68078d5c
DR		 2208{
2209 struct ufs_query_res *query_res = &hba->dev_cmd.query.response;
2210
68078d5c 2211 memcpy(&query_res->upiu_res, &lrbp->ucd_rsp_ptr->qr, QUERY_OSF_SIZE);
68078d5c 2212
68078d5c 2213 /* Get the descriptor */
1c90836f
AA		 2214 if (hba->dev_cmd.query.descriptor &&
2215 lrbp->ucd_rsp_ptr->qr.opcode == UPIU_QUERY_OPCODE_READ_DESC) {
d44a5f98 2216 u8 *descp = (u8 *)lrbp->ucd_rsp_ptr +
68078d5c 2217 GENERAL_UPIU_REQUEST_SIZE;
c6d4a831
DR		 2218 u16 resp_len;
2219 u16 buf_len;
68078d5c
DR		 2220
2221 /* data segment length */
c6d4a831 2222 resp_len = be32_to_cpu(lrbp->ucd_rsp_ptr->header.dword_2) &
68078d5c 2223 MASK_QUERY_DATA_SEG_LEN;
ea2aab24
SRT		 2224 buf_len = be16_to_cpu(
2225 hba->dev_cmd.query.request.upiu_req.length);
c6d4a831
DR		 2226 if (likely(buf_len >= resp_len)) {
2227 memcpy(hba->dev_cmd.query.descriptor, descp, resp_len);
2228 } else {
2229 dev_warn(hba->dev,
3d4881d1
BH		 2230 "%s: rsp size %d is bigger than buffer size %d",
2231 __func__, resp_len, buf_len);
c6d4a831
DR		 2232 return -EINVAL;
2233 }
68078d5c 2234 }
c6d4a831
DR		 2235
2236 return 0;
68078d5c
DR		 2237}
2238
7a3e97b0
SY		 2239/**
2240 * ufshcd_hba_capabilities - Read controller capabilities
2241 * @hba: per adapter instance
df043c74
ST		 2242 *
2243 * Return: 0 on success, negative on error.
7a3e97b0 2244 */
df043c74 2245static inline int ufshcd_hba_capabilities(struct ufs_hba *hba)
7a3e97b0 2246{
df043c74
ST		 2247 int err;
2248
b873a275 2249 hba->capabilities = ufshcd_readl(hba, REG_CONTROLLER_CAPABILITIES);
6554400d
YS		 2250 if (hba->quirks & UFSHCD_QUIRK_BROKEN_64BIT_ADDRESS)
2251 hba->capabilities &= ~MASK_64_ADDRESSING_SUPPORT;
7a3e97b0
SY		 2252
2253 /* nutrs and nutmrs are 0 based values */
2254 hba->nutrs = (hba->capabilities & MASK_TRANSFER_REQUESTS_SLOTS) + 1;
2255 hba->nutmrs =
2256 ((hba->capabilities & MASK_TASK_MANAGEMENT_REQUEST_SLOTS) >> 16) + 1;
945c3cca 2257 hba->reserved_slot = hba->nutrs - 1;
df043c74
ST		 2258
2259 /* Read crypto capabilities */
2260 err = ufshcd_hba_init_crypto_capabilities(hba);
2261 if (err)
2262 dev_err(hba->dev, "crypto setup failed\n");
2263
6e1d850a
AD		 2264 hba->mcq_capabilities = ufshcd_readl(hba, REG_MCQCAP);
2265 hba->ext_iid_sup = FIELD_GET(MASK_EXT_IID_SUPPORT,
2266 hba->mcq_capabilities);
2267
df043c74 2268 return err;
7a3e97b0
SY		 2269}
2270
2271/**
6ccf44fe
SJ		 2272 * ufshcd_ready_for_uic_cmd - Check if controller is ready
2273 * to accept UIC commands
7a3e97b0 2274 * @hba: per adapter instance
6ccf44fe
SJ		 2275 * Return true on success, else false
2276 */
2277static inline bool ufshcd_ready_for_uic_cmd(struct ufs_hba *hba)
2278{
a858af9a 2279 return ufshcd_readl(hba, REG_CONTROLLER_STATUS) & UIC_COMMAND_READY;
6ccf44fe
SJ		 2280}
2281
53b3d9c3
SJ		 2282/**
2283 * ufshcd_get_upmcrs - Get the power mode change request status
2284 * @hba: Pointer to adapter instance
2285 *
2286 * This function gets the UPMCRS field of HCS register
2287 * Returns value of UPMCRS field
2288 */
2289static inline u8 ufshcd_get_upmcrs(struct ufs_hba *hba)
2290{
2291 return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) >> 8) & 0x7;
2292}
2293
6ccf44fe 2294/**
35c7d874 2295 * ufshcd_dispatch_uic_cmd - Dispatch an UIC command to the Unipro layer
6ccf44fe
SJ		 2296 * @hba: per adapter instance
2297 * @uic_cmd: UIC command
7a3e97b0
SY		 2298 */
2299static inline void
6ccf44fe 2300ufshcd_dispatch_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
7a3e97b0 2301{
35c7d874
BVA		 2302 lockdep_assert_held(&hba->uic_cmd_mutex);
2303
6ccf44fe
SJ		 2304 WARN_ON(hba->active_uic_cmd);
2305
2306 hba->active_uic_cmd = uic_cmd;
2307
7a3e97b0 2308 /* Write Args */
6ccf44fe
SJ		 2309 ufshcd_writel(hba, uic_cmd->argument1, REG_UIC_COMMAND_ARG_1);
2310 ufshcd_writel(hba, uic_cmd->argument2, REG_UIC_COMMAND_ARG_2);
2311 ufshcd_writel(hba, uic_cmd->argument3, REG_UIC_COMMAND_ARG_3);
7a3e97b0 2312
28fa68fc 2313 ufshcd_add_uic_command_trace(hba, uic_cmd, UFS_CMD_SEND);
aa5c6979 2314
7a3e97b0 2315 /* Write UIC Cmd */
6ccf44fe 2316 ufshcd_writel(hba, uic_cmd->command & COMMAND_OPCODE_MASK,
b873a275 2317 REG_UIC_COMMAND);
7a3e97b0
SY		 2318}
2319
6ccf44fe 2320/**
35c7d874 2321 * ufshcd_wait_for_uic_cmd - Wait for completion of an UIC command
6ccf44fe 2322 * @hba: per adapter instance
8aa29f19 2323 * @uic_cmd: UIC command
6ccf44fe 2324 *
6ccf44fe
SJ		 2325 * Returns 0 only if success.
2326 */
2327static int
2328ufshcd_wait_for_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
2329{
2330 int ret;
2331 unsigned long flags;
2332
35c7d874
BVA		 2333 lockdep_assert_held(&hba->uic_cmd_mutex);
2334
6ccf44fe 2335 if (wait_for_completion_timeout(&uic_cmd->done,
0f52fcb9 2336 msecs_to_jiffies(UIC_CMD_TIMEOUT))) {
6ccf44fe 2337 ret = uic_cmd->argument2 & MASK_UIC_COMMAND_RESULT;
0f52fcb9 2338 } else {
6ccf44fe 2339 ret = -ETIMEDOUT;
0f52fcb9
CG		 2340 dev_err(hba->dev,
2341 "uic cmd 0x%x with arg3 0x%x completion timeout\n",
2342 uic_cmd->command, uic_cmd->argument3);
2343
2344 if (!uic_cmd->cmd_active) {
2345 dev_err(hba->dev, "%s: UIC cmd has been completed, return the result\n",
2346 __func__);
2347 ret = uic_cmd->argument2 & MASK_UIC_COMMAND_RESULT;
2348 }
2349 }
6ccf44fe
SJ		 2350
2351 spin_lock_irqsave(hba->host->host_lock, flags);
2352 hba->active_uic_cmd = NULL;
2353 spin_unlock_irqrestore(hba->host->host_lock, flags);
2354
2355 return ret;
2356}
2357
2358/**
2359 * __ufshcd_send_uic_cmd - Send UIC commands and retrieve the result
2360 * @hba: per adapter instance
2361 * @uic_cmd: UIC command
d75f7fe4 2362 * @completion: initialize the completion only if this is set to true
6ccf44fe 2363 *
6ccf44fe
SJ		 2364 * Returns 0 only if success.
2365 */
2366static int
d75f7fe4
YG		 2367__ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd,
2368 bool completion)
6ccf44fe 2369{
35c7d874
BVA		 2370 lockdep_assert_held(&hba->uic_cmd_mutex);
2371 lockdep_assert_held(hba->host->host_lock);
2372
6ccf44fe
SJ		 2373 if (!ufshcd_ready_for_uic_cmd(hba)) {
2374 dev_err(hba->dev,
2375 "Controller not ready to accept UIC commands\n");
2376 return -EIO;
2377 }
2378
d75f7fe4
YG		 2379 if (completion)
2380 init_completion(&uic_cmd->done);
6ccf44fe 2381
0f52fcb9 2382 uic_cmd->cmd_active = 1;
6ccf44fe 2383 ufshcd_dispatch_uic_cmd(hba, uic_cmd);
6ccf44fe 2384
57d104c1 2385 return 0;
6ccf44fe
SJ		 2386}
2387
2388/**
2389 * ufshcd_send_uic_cmd - Send UIC commands and retrieve the result
2390 * @hba: per adapter instance
2391 * @uic_cmd: UIC command
2392 *
2393 * Returns 0 only if success.
2394 */
e77044c5 2395int ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
6ccf44fe
SJ		 2396{
2397 int ret;
57d104c1 2398 unsigned long flags;
6ccf44fe 2399
a22bcfdb 2400 if (hba->quirks & UFSHCD_QUIRK_BROKEN_UIC_CMD)
2401 return 0;
2402
1ab27c9c 2403 ufshcd_hold(hba, false);
6ccf44fe 2404 mutex_lock(&hba->uic_cmd_mutex);
cad2e03d
YG		 2405 ufshcd_add_delay_before_dme_cmd(hba);
2406
57d104c1 2407 spin_lock_irqsave(hba->host->host_lock, flags);
d75f7fe4 2408 ret = __ufshcd_send_uic_cmd(hba, uic_cmd, true);
57d104c1
SJ		 2409 spin_unlock_irqrestore(hba->host->host_lock, flags);
2410 if (!ret)
2411 ret = ufshcd_wait_for_uic_cmd(hba, uic_cmd);
2412
6ccf44fe
SJ		 2413 mutex_unlock(&hba->uic_cmd_mutex);
2414
1ab27c9c 2415 ufshcd_release(hba);
6ccf44fe
SJ		 2416 return ret;
2417}
2418
7a3e97b0 2419/**
7a4df79d
BH		 2420 * ufshcd_sgl_to_prdt - SG list to PRTD (Physical Region Description Table, 4DW format)
2421 * @hba: per-adapter instance
2422 * @lrbp: pointer to local reference block
2423 * @sg_entries: The number of sg lists actually used
2424 * @sg_list: Pointer to SG list
7a3e97b0 2425 */
7a4df79d
BH		 2426static void ufshcd_sgl_to_prdt(struct ufs_hba *hba, struct ufshcd_lrb *lrbp, int sg_entries,
2427 struct scatterlist *sg_list)
7a3e97b0 2428{
ada1e653 2429 struct ufshcd_sg_entry *prd;
7a3e97b0 2430 struct scatterlist *sg;
7a3e97b0
SY		 2431 int i;
2432
7a4df79d 2433 if (sg_entries) {
26f968d7
AA		 2434
2435 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN)
2436 lrbp->utr_descriptor_ptr->prd_table_length =
4a5bd1a9 2437 cpu_to_le16(sg_entries * ufshcd_sg_entry_size(hba));
26f968d7 2438 else
7a4df79d 2439 lrbp->utr_descriptor_ptr->prd_table_length = cpu_to_le16(sg_entries);
7a3e97b0 2440
ada1e653 2441 prd = lrbp->ucd_prdt_ptr;
7a3e97b0 2442
7a4df79d 2443 for_each_sg(sg_list, sg, sg_entries, i) {
1ea7d802
BVA		 2444 const unsigned int len = sg_dma_len(sg);
2445
2446 /*
2447 * From the UFSHCI spec: "Data Byte Count (DBC): A '0'
2448 * based value that indicates the length, in bytes, of
2449 * the data block. A maximum of length of 256KB may
2450 * exist for any entry. Bits 1:0 of this field shall be
2451 * 11b to indicate Dword granularity. A value of '3'
2452 * indicates 4 bytes, '7' indicates 8 bytes, etc."
2453 */
2454 WARN_ONCE(len > 256 * 1024, "len = %#x\n", len);
ada1e653
EB		 2455 prd->size = cpu_to_le32(len - 1);
2456 prd->addr = cpu_to_le64(sg->dma_address);
2457 prd->reserved = 0;
2458 prd = (void *)prd + ufshcd_sg_entry_size(hba);
7a3e97b0
SY		 2459 }
2460 } else {
2461 lrbp->utr_descriptor_ptr->prd_table_length = 0;
2462 }
7a4df79d
BH		 2463}
2464
2465/**
2466 * ufshcd_map_sg - Map scatter-gather list to prdt
2467 * @hba: per adapter instance
2468 * @lrbp: pointer to local reference block
2469 *
2470 * Returns 0 in case of success, non-zero value in case of failure
2471 */
2472static int ufshcd_map_sg(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2473{
2474 struct scsi_cmnd *cmd = lrbp->cmd;
2475 int sg_segments = scsi_dma_map(cmd);
2476
2477 if (sg_segments < 0)
2478 return sg_segments;
2479
2480 ufshcd_sgl_to_prdt(hba, lrbp, sg_segments, scsi_sglist(cmd));
7a3e97b0
SY		 2481
2482 return 0;
2483}
2484
2485/**
2fbd009b 2486 * ufshcd_enable_intr - enable interrupts
7a3e97b0 2487 * @hba: per adapter instance
2fbd009b 2488 * @intrs: interrupt bits
7a3e97b0 2489 */
2fbd009b 2490static void ufshcd_enable_intr(struct ufs_hba *hba, u32 intrs)
7a3e97b0 2491{
2fbd009b
SJ		 2492 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
2493
51428818 2494 if (hba->ufs_version == ufshci_version(1, 0)) {
2fbd009b
SJ		 2495 u32 rw;
2496 rw = set & INTERRUPT_MASK_RW_VER_10;
2497 set = rw | ((set ^ intrs) & intrs);
2498 } else {
2499 set |= intrs;
2500 }
2501
2502 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
2503}
2504
2505/**
2506 * ufshcd_disable_intr - disable interrupts
2507 * @hba: per adapter instance
2508 * @intrs: interrupt bits
2509 */
2510static void ufshcd_disable_intr(struct ufs_hba *hba, u32 intrs)
2511{
2512 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
2513
51428818 2514 if (hba->ufs_version == ufshci_version(1, 0)) {
2fbd009b
SJ		 2515 u32 rw;
2516 rw = (set & INTERRUPT_MASK_RW_VER_10) &
2517 ~(intrs & INTERRUPT_MASK_RW_VER_10);
2518 set = rw | ((set & intrs) & ~INTERRUPT_MASK_RW_VER_10);
2519
2520 } else {
2521 set &= ~intrs;
7a3e97b0 2522 }
2fbd009b
SJ		 2523
2524 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
7a3e97b0
SY		 2525}
2526
5a0b0cb9 2527/**
a4b1c9b9 2528 * ufshcd_prepare_req_desc_hdr - Fill UTP Transfer request descriptor header according to request
5a0b0cb9
SRT		 2529 * descriptor according to request
2530 * @lrbp: pointer to local reference block
2531 * @upiu_flags: flags required in the header
2532 * @cmd_dir: requests data direction
a4b1c9b9 2533 * @ehs_length: Total EHS Length (in 32‐bytes units of all Extra Header Segments)
5a0b0cb9 2534 */
a4b1c9b9
BH		 2535static void ufshcd_prepare_req_desc_hdr(struct ufshcd_lrb *lrbp, u8 *upiu_flags,
2536 enum dma_data_direction cmd_dir, int ehs_length)
5a0b0cb9
SRT		 2537{
2538 struct utp_transfer_req_desc *req_desc = lrbp->utr_descriptor_ptr;
2539 u32 data_direction;
2540 u32 dword_0;
df043c74
ST		 2541 u32 dword_1 = 0;
2542 u32 dword_3 = 0;
5a0b0cb9
SRT		 2543
2544 if (cmd_dir == DMA_FROM_DEVICE) {
2545 data_direction = UTP_DEVICE_TO_HOST;
2546 *upiu_flags = UPIU_CMD_FLAGS_READ;
2547 } else if (cmd_dir == DMA_TO_DEVICE) {
2548 data_direction = UTP_HOST_TO_DEVICE;
2549 *upiu_flags = UPIU_CMD_FLAGS_WRITE;
2550 } else {
2551 data_direction = UTP_NO_DATA_TRANSFER;
2552 *upiu_flags = UPIU_CMD_FLAGS_NONE;
2553 }
2554
a4b1c9b9
BH		 2555 dword_0 = data_direction | (lrbp->command_type << UPIU_COMMAND_TYPE_OFFSET) |
2556 ehs_length << 8;
5a0b0cb9
SRT		 2557 if (lrbp->intr_cmd)
2558 dword_0 |= UTP_REQ_DESC_INT_CMD;
2559
df043c74
ST		 2560 /* Prepare crypto related dwords */
2561 ufshcd_prepare_req_desc_hdr_crypto(lrbp, &dword_0, &dword_1, &dword_3);
2562
5a0b0cb9
SRT		 2563 /* Transfer request descriptor header fields */
2564 req_desc->header.dword_0 = cpu_to_le32(dword_0);
df043c74 2565 req_desc->header.dword_1 = cpu_to_le32(dword_1);
5a0b0cb9
SRT		 2566 /*
2567 * assigning invalid value for command status. Controller
2568 * updates OCS on command completion, with the command
2569 * status
2570 */
2571 req_desc->header.dword_2 =
2572 cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
df043c74 2573 req_desc->header.dword_3 = cpu_to_le32(dword_3);
51047266
YG		 2574
2575 req_desc->prd_table_length = 0;
5a0b0cb9
SRT		 2576}
2577
2578/**
2579 * ufshcd_prepare_utp_scsi_cmd_upiu() - fills the utp_transfer_req_desc,
2580 * for scsi commands
8aa29f19
BVA		 2581 * @lrbp: local reference block pointer
2582 * @upiu_flags: flags
5a0b0cb9
SRT		 2583 */
2584static
a23064c4 2585void ufshcd_prepare_utp_scsi_cmd_upiu(struct ufshcd_lrb *lrbp, u8 upiu_flags)
5a0b0cb9 2586{
1b21b8f0 2587 struct scsi_cmnd *cmd = lrbp->cmd;
5a0b0cb9 2588 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
52ac95fe 2589 unsigned short cdb_len;
5a0b0cb9
SRT		 2590
2591 /* command descriptor fields */
2592 ucd_req_ptr->header.dword_0 = UPIU_HEADER_DWORD(
2593 UPIU_TRANSACTION_COMMAND, upiu_flags,
2594 lrbp->lun, lrbp->task_tag);
2595 ucd_req_ptr->header.dword_1 = UPIU_HEADER_DWORD(
2596 UPIU_COMMAND_SET_TYPE_SCSI, 0, 0, 0);
2597
2598 /* Total EHS length and Data segment length will be zero */
2599 ucd_req_ptr->header.dword_2 = 0;
2600
1b21b8f0 2601 ucd_req_ptr->sc.exp_data_transfer_len = cpu_to_be32(cmd->sdb.length);
5a0b0cb9 2602
1b21b8f0 2603 cdb_len = min_t(unsigned short, cmd->cmd_len, UFS_CDB_SIZE);
a851b2bd 2604 memset(ucd_req_ptr->sc.cdb, 0, UFS_CDB_SIZE);
1b21b8f0 2605 memcpy(ucd_req_ptr->sc.cdb, cmd->cmnd, cdb_len);
52ac95fe
YG		 2606
2607 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
5a0b0cb9
SRT		 2608}
2609
68078d5c 2610/**
a4b1c9b9 2611 * ufshcd_prepare_utp_query_req_upiu() - fill the utp_transfer_req_desc for query request
68078d5c
DR		 2612 * @hba: UFS hba
2613 * @lrbp: local reference block pointer
2614 * @upiu_flags: flags
2615 */
2616static void ufshcd_prepare_utp_query_req_upiu(struct ufs_hba *hba,
a23064c4 2617 struct ufshcd_lrb *lrbp, u8 upiu_flags)
68078d5c
DR		 2618{
2619 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
2620 struct ufs_query *query = &hba->dev_cmd.query;
e8c8e82a 2621 u16 len = be16_to_cpu(query->request.upiu_req.length);
68078d5c
DR		 2622
2623 /* Query request header */
2624 ucd_req_ptr->header.dword_0 = UPIU_HEADER_DWORD(
2625 UPIU_TRANSACTION_QUERY_REQ, upiu_flags,
2626 lrbp->lun, lrbp->task_tag);
2627 ucd_req_ptr->header.dword_1 = UPIU_HEADER_DWORD(
2628 0, query->request.query_func, 0, 0);
2629
6861285c
ZL		 2630 /* Data segment length only need for WRITE_DESC */
2631 if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC)
2632 ucd_req_ptr->header.dword_2 =
2633 UPIU_HEADER_DWORD(0, 0, (len >> 8), (u8)len);
2634 else
2635 ucd_req_ptr->header.dword_2 = 0;
68078d5c
DR		 2636
2637 /* Copy the Query Request buffer as is */
2638 memcpy(&ucd_req_ptr->qr, &query->request.upiu_req,
2639 QUERY_OSF_SIZE);
68078d5c
DR		 2640
2641 /* Copy the Descriptor */
c6d4a831 2642 if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC)
220d17a6 2643 memcpy(ucd_req_ptr + 1, query->descriptor, len);
c6d4a831 2644
51047266 2645 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
68078d5c
DR		 2646}
2647
5a0b0cb9
SRT		 2648static inline void ufshcd_prepare_utp_nop_upiu(struct ufshcd_lrb *lrbp)
2649{
2650 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
2651
2652 memset(ucd_req_ptr, 0, sizeof(struct utp_upiu_req));
2653
2654 /* command descriptor fields */
2655 ucd_req_ptr->header.dword_0 =
2656 UPIU_HEADER_DWORD(
2657 UPIU_TRANSACTION_NOP_OUT, 0, 0, lrbp->task_tag);
51047266
YG		 2658 /* clear rest of the fields of basic header */
2659 ucd_req_ptr->header.dword_1 = 0;
2660 ucd_req_ptr->header.dword_2 = 0;
2661
2662 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
5a0b0cb9
SRT		 2663}
2664
7a3e97b0 2665/**
f273c54b 2666 * ufshcd_compose_devman_upiu - UFS Protocol Information Unit(UPIU)
300bb13f 2667 * for Device Management Purposes
8aa29f19
BVA		 2668 * @hba: per adapter instance
2669 * @lrbp: pointer to local reference block
7a3e97b0 2670 */
f273c54b
BH		 2671static int ufshcd_compose_devman_upiu(struct ufs_hba *hba,
2672 struct ufshcd_lrb *lrbp)
7a3e97b0 2673{
a23064c4 2674 u8 upiu_flags;
5a0b0cb9 2675 int ret = 0;
7a3e97b0 2676
51428818 2677 if (hba->ufs_version <= ufshci_version(1, 1))
300bb13f 2678 lrbp->command_type = UTP_CMD_TYPE_DEV_MANAGE;
83dc7e3d 2679 else
2680 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE;
300bb13f 2681
a4b1c9b9 2682 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, DMA_NONE, 0);
300bb13f
JP		 2683 if (hba->dev_cmd.type == DEV_CMD_TYPE_QUERY)
2684 ufshcd_prepare_utp_query_req_upiu(hba, lrbp, upiu_flags);
2685 else if (hba->dev_cmd.type == DEV_CMD_TYPE_NOP)
2686 ufshcd_prepare_utp_nop_upiu(lrbp);
2687 else
2688 ret = -EINVAL;
2689
2690 return ret;
2691}
2692
2693/**
2694 * ufshcd_comp_scsi_upiu - UFS Protocol Information Unit(UPIU)
2695 * for SCSI Purposes
8aa29f19
BVA		 2696 * @hba: per adapter instance
2697 * @lrbp: pointer to local reference block
300bb13f
JP		 2698 */
2699static int ufshcd_comp_scsi_upiu(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2700{
a23064c4 2701 u8 upiu_flags;
300bb13f
JP		 2702 int ret = 0;
2703
51428818 2704 if (hba->ufs_version <= ufshci_version(1, 1))
300bb13f 2705 lrbp->command_type = UTP_CMD_TYPE_SCSI;
83dc7e3d 2706 else
2707 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE;
300bb13f
JP		 2708
2709 if (likely(lrbp->cmd)) {
a4b1c9b9 2710 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, lrbp->cmd->sc_data_direction, 0);
300bb13f
JP		 2711 ufshcd_prepare_utp_scsi_cmd_upiu(lrbp, upiu_flags);
2712 } else {
2713 ret = -EINVAL;
2714 }
5a0b0cb9
SRT		 2715
2716 return ret;
7a3e97b0
SY		 2717}
2718
2a8fa600
SJ		 2719/**
2720 * ufshcd_upiu_wlun_to_scsi_wlun - maps UPIU W-LUN id to SCSI W-LUN ID
8aa29f19 2721 * @upiu_wlun_id: UPIU W-LUN id
2a8fa600
SJ		 2722 *
2723 * Returns SCSI W-LUN id
2724 */
2725static inline u16 ufshcd_upiu_wlun_to_scsi_wlun(u8 upiu_wlun_id)
2726{
2727 return (upiu_wlun_id & ~UFS_UPIU_WLUN_ID) | SCSI_W_LUN_BASE;
2728}
2729
b294ff3e
AD		 2730static inline bool is_device_wlun(struct scsi_device *sdev)
2731{
2732 return sdev->lun ==
2733 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_UFS_DEVICE_WLUN);
2734}
2735
eaab9b57
BVA		 2736/*
2737 * Associate the UFS controller queue with the default and poll HCTX types.
2738 * Initialize the mq_map[] arrays.
2739 */
a4e1d0b7 2740static void ufshcd_map_queues(struct Scsi_Host *shost)
eaab9b57 2741{
a4e1d0b7 2742 int i;
eaab9b57
BVA		 2743
2744 for (i = 0; i < shost->nr_maps; i++) {
2745 struct blk_mq_queue_map *map = &shost->tag_set.map[i];
2746
2747 switch (i) {
2748 case HCTX_TYPE_DEFAULT:
2749 case HCTX_TYPE_POLL:
2750 map->nr_queues = 1;
2751 break;
2752 case HCTX_TYPE_READ:
2753 map->nr_queues = 0;
10af1156 2754 continue;
eaab9b57
BVA		 2755 default:
2756 WARN_ON_ONCE(true);
2757 }
2758 map->queue_offset = 0;
a4e1d0b7 2759 blk_mq_map_queues(map);
eaab9b57 2760 }
eaab9b57
BVA		 2761}
2762
4d2b8d40
BVA		 2763static void ufshcd_init_lrb(struct ufs_hba *hba, struct ufshcd_lrb *lrb, int i)
2764{
ada1e653
EB		 2765 struct utp_transfer_cmd_desc *cmd_descp = (void *)hba->ucdl_base_addr +
2766 i * sizeof_utp_transfer_cmd_desc(hba);
4d2b8d40
BVA		 2767 struct utp_transfer_req_desc *utrdlp = hba->utrdl_base_addr;
2768 dma_addr_t cmd_desc_element_addr = hba->ucdl_dma_addr +
ada1e653 2769 i * sizeof_utp_transfer_cmd_desc(hba);
4d2b8d40
BVA		 2770 u16 response_offset = offsetof(struct utp_transfer_cmd_desc,
2771 response_upiu);
2772 u16 prdt_offset = offsetof(struct utp_transfer_cmd_desc, prd_table);
2773
2774 lrb->utr_descriptor_ptr = utrdlp + i;
2775 lrb->utrd_dma_addr = hba->utrdl_dma_addr +
2776 i * sizeof(struct utp_transfer_req_desc);
ada1e653 2777 lrb->ucd_req_ptr = (struct utp_upiu_req *)cmd_descp->command_upiu;
4d2b8d40 2778 lrb->ucd_req_dma_addr = cmd_desc_element_addr;
ada1e653 2779 lrb->ucd_rsp_ptr = (struct utp_upiu_rsp *)cmd_descp->response_upiu;
4d2b8d40 2780 lrb->ucd_rsp_dma_addr = cmd_desc_element_addr + response_offset;
ada1e653 2781 lrb->ucd_prdt_ptr = (struct ufshcd_sg_entry *)cmd_descp->prd_table;
4d2b8d40
BVA		 2782 lrb->ucd_prdt_dma_addr = cmd_desc_element_addr + prdt_offset;
2783}
2784
7a3e97b0
SY		 2785/**
2786 * ufshcd_queuecommand - main entry point for SCSI requests
8aa29f19 2787 * @host: SCSI host pointer
7a3e97b0 2788 * @cmd: command from SCSI Midlayer
7a3e97b0
SY		 2789 *
2790 * Returns 0 for success, non-zero in case of failure
2791 */
2792static int ufshcd_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
2793{
4728ab4a 2794 struct ufs_hba *hba = shost_priv(host);
3f2c1002 2795 int tag = scsi_cmd_to_rq(cmd)->tag;
7a3e97b0 2796 struct ufshcd_lrb *lrbp;
7a3e97b0
SY		 2797 int err = 0;
2798
eaab9b57 2799 WARN_ONCE(tag < 0 || tag >= hba->nutrs, "Invalid tag %d\n", tag);
7a3e97b0 2800
5675c381
BVA		 2801 /*
2802 * Allows the UFS error handler to wait for prior ufshcd_queuecommand()
2803 * calls.
2804 */
2805 rcu_read_lock();
2806
a45f9371
CG		 2807 switch (hba->ufshcd_state) {
2808 case UFSHCD_STATE_OPERATIONAL:
d489f18a 2809 break;
a45f9371 2810 case UFSHCD_STATE_EH_SCHEDULED_NON_FATAL:
d489f18a
AH		 2811 /*
2812 * SCSI error handler can call ->queuecommand() while UFS error
2813 * handler is in progress. Error interrupts could change the
2814 * state from UFSHCD_STATE_RESET to
2815 * UFSHCD_STATE_EH_SCHEDULED_NON_FATAL. Prevent requests
2816 * being issued in that case.
2817 */
2818 if (ufshcd_eh_in_progress(hba)) {
2819 err = SCSI_MLQUEUE_HOST_BUSY;
2820 goto out;
2821 }
a45f9371
CG		 2822 break;
2823 case UFSHCD_STATE_EH_SCHEDULED_FATAL:
2824 /*
2825 * pm_runtime_get_sync() is used at error handling preparation
2826 * stage. If a scsi cmd, e.g. the SSU cmd, is sent from hba's
2827 * PM ops, it can never be finished if we let SCSI layer keep
2828 * retrying it, which gets err handler stuck forever. Neither
2829 * can we let the scsi cmd pass through, because UFS is in bad
2830 * state, the scsi cmd may eventually time out, which will get
2831 * err handler blocked for too long. So, just fail the scsi cmd
2832 * sent from PM ops, err handler can recover PM error anyways.
2833 */
2834 if (hba->pm_op_in_progress) {
2835 hba->force_reset = true;
2836 set_host_byte(cmd, DID_BAD_TARGET);
35c3730a 2837 scsi_done(cmd);
a45f9371
CG		 2838 goto out;
2839 }
2840 fallthrough;
2841 case UFSHCD_STATE_RESET:
2842 err = SCSI_MLQUEUE_HOST_BUSY;
2843 goto out;
2844 case UFSHCD_STATE_ERROR:
2845 set_host_byte(cmd, DID_ERROR);
35c3730a 2846 scsi_done(cmd);
a45f9371 2847 goto out;
a45f9371
CG		 2848 }
2849
7fabb77b
GB		 2850 hba->req_abort_count = 0;
2851
1ab27c9c
ST		 2852 err = ufshcd_hold(hba, true);
2853 if (err) {
2854 err = SCSI_MLQUEUE_HOST_BUSY;
1ab27c9c
ST		 2855 goto out;
2856 }
2dec9475
CG		 2857 WARN_ON(ufshcd_is_clkgating_allowed(hba) &&
2858 (hba->clk_gating.state != CLKS_ON));
1ab27c9c 2859
a45f9371 2860 lrbp = &hba->lrb[tag];
5a0b0cb9 2861 WARN_ON(lrbp->cmd);
7a3e97b0 2862 lrbp->cmd = cmd;
7a3e97b0 2863 lrbp->task_tag = tag;
0ce147d4 2864 lrbp->lun = ufshcd_scsi_to_upiu_lun(cmd->device->lun);
51d1628f 2865 lrbp->intr_cmd = !ufshcd_is_intr_aggr_allowed(hba);
df043c74 2866
3f2c1002 2867 ufshcd_prepare_lrbp_crypto(scsi_cmd_to_rq(cmd), lrbp);
df043c74 2868
e0b299e3 2869 lrbp->req_abort_skip = false;
7a3e97b0 2870
09d9e4d0 2871 ufshpb_prep(hba, lrbp);
2fff76f8 2872
300bb13f
JP		 2873 ufshcd_comp_scsi_upiu(hba, lrbp);
2874
75b1cc4a 2875 err = ufshcd_map_sg(hba, lrbp);
5a0b0cb9
SRT		 2876 if (err) {
2877 lrbp->cmd = NULL;
17c7d35f 2878 ufshcd_release(hba);
7a3e97b0 2879 goto out;
5a0b0cb9 2880 }
7a3e97b0 2881
7a3e97b0 2882 ufshcd_send_command(hba, tag);
5675c381 2883
7a3e97b0 2884out:
5675c381
BVA		 2885 rcu_read_unlock();
2886
88b09900
AH		 2887 if (ufs_trigger_eh()) {
2888 unsigned long flags;
2889
2890 spin_lock_irqsave(hba->host->host_lock, flags);
2891 ufshcd_schedule_eh_work(hba);
2892 spin_unlock_irqrestore(hba->host->host_lock, flags);
2893 }
c11a1ae9 2894
7a3e97b0
SY		 2895 return err;
2896}
2897
5a0b0cb9
SRT		 2898static int ufshcd_compose_dev_cmd(struct ufs_hba *hba,
2899 struct ufshcd_lrb *lrbp, enum dev_cmd_type cmd_type, int tag)
2900{
2901 lrbp->cmd = NULL;
5a0b0cb9
SRT		 2902 lrbp->task_tag = tag;
2903 lrbp->lun = 0; /* device management cmd is not specific to any LUN */
5a0b0cb9 2904 lrbp->intr_cmd = true; /* No interrupt aggregation */
df043c74 2905 ufshcd_prepare_lrbp_crypto(NULL, lrbp);
5a0b0cb9
SRT		 2906 hba->dev_cmd.type = cmd_type;
2907
f273c54b 2908 return ufshcd_compose_devman_upiu(hba, lrbp);
5a0b0cb9
SRT		 2909}
2910
d1a76446
BVA		 2911/*
2912 * Clear all the requests from the controller for which a bit has been set in
2913 * @mask and wait until the controller confirms that these requests have been
2914 * cleared.
2915 */
2916static int ufshcd_clear_cmds(struct ufs_hba *hba, u32 mask)
5a0b0cb9 2917{
5a0b0cb9 2918 unsigned long flags;
5a0b0cb9
SRT		 2919
2920 /* clear outstanding transaction before retry */
2921 spin_lock_irqsave(hba->host->host_lock, flags);
d1a76446 2922 ufshcd_utrl_clear(hba, mask);
5a0b0cb9
SRT		 2923 spin_unlock_irqrestore(hba->host->host_lock, flags);
2924
2925 /*
32424902 2926 * wait for h/w to clear corresponding bit in door-bell.
5a0b0cb9
SRT		 2927 * max. wait is 1 sec.
2928 */
da8badd7
BVA		 2929 return ufshcd_wait_for_register(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL,
2930 mask, ~mask, 1000, 1000);
5a0b0cb9
SRT		 2931}
2932
c6d4a831
DR		 2933static int
2934ufshcd_check_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2935{
2936 struct ufs_query_res *query_res = &hba->dev_cmd.query.response;
2937
2938 /* Get the UPIU response */
2939 query_res->response = ufshcd_get_rsp_upiu_result(lrbp->ucd_rsp_ptr) >>
2940 UPIU_RSP_CODE_OFFSET;
2941 return query_res->response;
2942}
2943
5a0b0cb9
SRT		 2944/**
2945 * ufshcd_dev_cmd_completion() - handles device management command responses
2946 * @hba: per adapter instance
2947 * @lrbp: pointer to local reference block
2948 */
2949static int
2950ufshcd_dev_cmd_completion(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2951{
2952 int resp;
2953 int err = 0;
2954
ff8e20c6 2955 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0);
5a0b0cb9
SRT		 2956 resp = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr);
2957
2958 switch (resp) {
2959 case UPIU_TRANSACTION_NOP_IN:
2960 if (hba->dev_cmd.type != DEV_CMD_TYPE_NOP) {
2961 err = -EINVAL;
2962 dev_err(hba->dev, "%s: unexpected response %x\n",
2963 __func__, resp);
2964 }
2965 break;
68078d5c 2966 case UPIU_TRANSACTION_QUERY_RSP:
c6d4a831
DR		 2967 err = ufshcd_check_query_response(hba, lrbp);
2968 if (!err)
2969 err = ufshcd_copy_query_response(hba, lrbp);
68078d5c 2970 break;
5a0b0cb9
SRT		 2971 case UPIU_TRANSACTION_REJECT_UPIU:
2972 /* TODO: handle Reject UPIU Response */
2973 err = -EPERM;
2974 dev_err(hba->dev, "%s: Reject UPIU not fully implemented\n",
2975 __func__);
2976 break;
6ff265fc
BH		 2977 case UPIU_TRANSACTION_RESPONSE:
2978 if (hba->dev_cmd.type != DEV_CMD_TYPE_RPMB) {
2979 err = -EINVAL;
2980 dev_err(hba->dev, "%s: unexpected response %x\n", __func__, resp);
2981 }
2982 break;
5a0b0cb9
SRT		 2983 default:
2984 err = -EINVAL;
2985 dev_err(hba->dev, "%s: Invalid device management cmd response: %x\n",
2986 __func__, resp);
2987 break;
2988 }
2989
2990 return err;
2991}
2992
2993static int ufshcd_wait_for_dev_cmd(struct ufs_hba *hba,
2994 struct ufshcd_lrb *lrbp, int max_timeout)
2995{
f5c2976e 2996 unsigned long time_left = msecs_to_jiffies(max_timeout);
5a0b0cb9 2997 unsigned long flags;
f5c2976e
BVA		 2998 bool pending;
2999 int err;
5a0b0cb9 3000
f5c2976e 3001retry:
5a0b0cb9 3002 time_left = wait_for_completion_timeout(hba->dev_cmd.complete,
f5c2976e 3003 time_left);
5a0b0cb9 3004
5a0b0cb9 3005 if (likely(time_left)) {
f5c2976e
BVA		 3006 /*
3007 * The completion handler called complete() and the caller of
3008 * this function still owns the @lrbp tag so the code below does
3009 * not trigger any race conditions.
3010 */
3011 hba->dev_cmd.complete = NULL;
5a0b0cb9
SRT		 3012 err = ufshcd_get_tr_ocs(lrbp);
3013 if (!err)
3014 err = ufshcd_dev_cmd_completion(hba, lrbp);
f5c2976e 3015 } else {
5a0b0cb9 3016 err = -ETIMEDOUT;
a48353f6
YG		 3017 dev_dbg(hba->dev, "%s: dev_cmd request timedout, tag %d\n",
3018 __func__, lrbp->task_tag);
f5c2976e 3019 if (ufshcd_clear_cmds(hba, 1U << lrbp->task_tag) == 0) {
a48353f6 3020 /* successfully cleared the command, retry if needed */
5a0b0cb9 3021 err = -EAGAIN;
f5c2976e
BVA		 3022 /*
3023 * Since clearing the command succeeded we also need to
3024 * clear the task tag bit from the outstanding_reqs
3025 * variable.
3026 */
3027 spin_lock_irqsave(&hba->outstanding_lock, flags);
3028 pending = test_bit(lrbp->task_tag,
3029 &hba->outstanding_reqs);
3030 if (pending) {
3031 hba->dev_cmd.complete = NULL;
3032 __clear_bit(lrbp->task_tag,
3033 &hba->outstanding_reqs);
3034 }
3035 spin_unlock_irqrestore(&hba->outstanding_lock, flags);
3036
3037 if (!pending) {
3038 /*
3039 * The completion handler ran while we tried to
3040 * clear the command.
3041 */
3042 time_left = 1;
3043 goto retry;
3044 }
3045 } else {
3046 dev_err(hba->dev, "%s: failed to clear tag %d\n",
3047 __func__, lrbp->task_tag);
3048 }
5a0b0cb9
SRT		 3049 }
3050
3051 return err;
3052}
3053
5a0b0cb9
SRT		 3054/**
3055 * ufshcd_exec_dev_cmd - API for sending device management requests
8aa29f19
BVA		 3056 * @hba: UFS hba
3057 * @cmd_type: specifies the type (NOP, Query...)
d0b2b70e 3058 * @timeout: timeout in milliseconds
5a0b0cb9 3059 *
68078d5c
DR		 3060 * NOTE: Since there is only one available tag for device management commands,
3061 * it is expected you hold the hba->dev_cmd.lock mutex.
5a0b0cb9
SRT		 3062 */
3063static int ufshcd_exec_dev_cmd(struct ufs_hba *hba,
3064 enum dev_cmd_type cmd_type, int timeout)
3065{
8a686f26 3066 DECLARE_COMPLETION_ONSTACK(wait);
945c3cca 3067 const u32 tag = hba->reserved_slot;
5a0b0cb9
SRT		 3068 struct ufshcd_lrb *lrbp;
3069 int err;
5a0b0cb9 3070
945c3cca
BVA		 3071 /* Protects use of hba->reserved_slot. */
3072 lockdep_assert_held(&hba->dev_cmd.lock);
a3cd5ec5 3073
945c3cca 3074 down_read(&hba->clk_scaling_lock);
5a0b0cb9 3075
a45f9371 3076 lrbp = &hba->lrb[tag];
5a0b0cb9
SRT		 3077 WARN_ON(lrbp->cmd);
3078 err = ufshcd_compose_dev_cmd(hba, lrbp, cmd_type, tag);
3079 if (unlikely(err))
eb783bb8 3080 goto out;
5a0b0cb9
SRT		 3081
3082 hba->dev_cmd.complete = &wait;
3083
fb475b74 3084 ufshcd_add_query_upiu_trace(hba, UFS_QUERY_SEND, lrbp->ucd_req_ptr);
5a0b0cb9 3085
a45f9371 3086 ufshcd_send_command(hba, tag);
5a0b0cb9 3087 err = ufshcd_wait_for_dev_cmd(hba, lrbp, timeout);
fb475b74
AA		 3088 ufshcd_add_query_upiu_trace(hba, err ? UFS_QUERY_ERR : UFS_QUERY_COMP,
3089 (struct utp_upiu_req *)lrbp->ucd_rsp_ptr);
6667e6d9 3090
eb783bb8 3091out:
a3cd5ec5 3092 up_read(&hba->clk_scaling_lock);
5a0b0cb9
SRT		 3093 return err;
3094}
3095
d44a5f98
DR		 3096/**
3097 * ufshcd_init_query() - init the query response and request parameters
3098 * @hba: per-adapter instance
3099 * @request: address of the request pointer to be initialized
3100 * @response: address of the response pointer to be initialized
3101 * @opcode: operation to perform
3102 * @idn: flag idn to access
3103 * @index: LU number to access
3104 * @selector: query/flag/descriptor further identification
3105 */
3106static inline void ufshcd_init_query(struct ufs_hba *hba,
3107 struct ufs_query_req **request, struct ufs_query_res **response,
3108 enum query_opcode opcode, u8 idn, u8 index, u8 selector)
3109{
3110 *request = &hba->dev_cmd.query.request;
3111 *response = &hba->dev_cmd.query.response;
3112 memset(*request, 0, sizeof(struct ufs_query_req));
3113 memset(*response, 0, sizeof(struct ufs_query_res));
3114 (*request)->upiu_req.opcode = opcode;
3115 (*request)->upiu_req.idn = idn;
3116 (*request)->upiu_req.index = index;
3117 (*request)->upiu_req.selector = selector;
3118}
3119
dc3c8d3a 3120static int ufshcd_query_flag_retry(struct ufs_hba *hba,
1f34eedf 3121 enum query_opcode opcode, enum flag_idn idn, u8 index, bool *flag_res)
dc3c8d3a
YG		 3122{
3123 int ret;
3124 int retries;
3125
3126 for (retries = 0; retries < QUERY_REQ_RETRIES; retries++) {
1f34eedf 3127 ret = ufshcd_query_flag(hba, opcode, idn, index, flag_res);
dc3c8d3a
YG		 3128 if (ret)
3129 dev_dbg(hba->dev,
3130 "%s: failed with error %d, retries %d\n",
3131 __func__, ret, retries);
3132 else
3133 break;
3134 }
3135
3136 if (ret)
3137 dev_err(hba->dev,
48ee7952 3138 "%s: query flag, opcode %d, idn %d, failed with error %d after %d retries\n",
dc3c8d3a
YG		 3139 __func__, opcode, idn, ret, retries);
3140 return ret;
3141}
3142
68078d5c
DR		 3143/**
3144 * ufshcd_query_flag() - API function for sending flag query requests
8aa29f19
BVA		 3145 * @hba: per-adapter instance
3146 * @opcode: flag query to perform
3147 * @idn: flag idn to access
1f34eedf 3148 * @index: flag index to access
8aa29f19 3149 * @flag_res: the flag value after the query request completes
68078d5c
DR		 3150 *
3151 * Returns 0 for success, non-zero in case of failure
3152 */
dc3c8d3a 3153int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode,
1f34eedf 3154 enum flag_idn idn, u8 index, bool *flag_res)
68078d5c 3155{
d44a5f98
DR		 3156 struct ufs_query_req *request = NULL;
3157 struct ufs_query_res *response = NULL;
1f34eedf 3158 int err, selector = 0;
e5ad406c 3159 int timeout = QUERY_REQ_TIMEOUT;
68078d5c
DR		 3160
3161 BUG_ON(!hba);
3162
1ab27c9c 3163 ufshcd_hold(hba, false);
68078d5c 3164 mutex_lock(&hba->dev_cmd.lock);
d44a5f98
DR		 3165 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
3166 selector);
68078d5c
DR		 3167
3168 switch (opcode) {
3169 case UPIU_QUERY_OPCODE_SET_FLAG:
3170 case UPIU_QUERY_OPCODE_CLEAR_FLAG:
3171 case UPIU_QUERY_OPCODE_TOGGLE_FLAG:
3172 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
3173 break;
3174 case UPIU_QUERY_OPCODE_READ_FLAG:
3175 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
3176 if (!flag_res) {
3177 /* No dummy reads */
3178 dev_err(hba->dev, "%s: Invalid argument for read request\n",
3179 __func__);
3180 err = -EINVAL;
3181 goto out_unlock;
3182 }
3183 break;
3184 default:
3185 dev_err(hba->dev,
3186 "%s: Expected query flag opcode but got = %d\n",
3187 __func__, opcode);
3188 err = -EINVAL;
3189 goto out_unlock;
3190 }
68078d5c 3191
e5ad406c 3192 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, timeout);
68078d5c
DR		 3193
3194 if (err) {
3195 dev_err(hba->dev,
3196 "%s: Sending flag query for idn %d failed, err = %d\n",
3197 __func__, idn, err);
3198 goto out_unlock;
3199 }
3200
3201 if (flag_res)
e8c8e82a 3202 *flag_res = (be32_to_cpu(response->upiu_res.value) &
68078d5c
DR		 3203 MASK_QUERY_UPIU_FLAG_LOC) & 0x1;
3204
3205out_unlock:
3206 mutex_unlock(&hba->dev_cmd.lock);
1ab27c9c 3207 ufshcd_release(hba);
68078d5c
DR		 3208 return err;
3209}
3210
66ec6d59
SRT		 3211/**
3212 * ufshcd_query_attr - API function for sending attribute requests
8aa29f19
BVA		 3213 * @hba: per-adapter instance
3214 * @opcode: attribute opcode
3215 * @idn: attribute idn to access
3216 * @index: index field
3217 * @selector: selector field
3218 * @attr_val: the attribute value after the query request completes
66ec6d59
SRT		 3219 *
3220 * Returns 0 for success, non-zero in case of failure
3221*/
ec92b59c
SN		 3222int ufshcd_query_attr(struct ufs_hba *hba, enum query_opcode opcode,
3223 enum attr_idn idn, u8 index, u8 selector, u32 *attr_val)
66ec6d59 3224{
d44a5f98
DR		 3225 struct ufs_query_req *request = NULL;
3226 struct ufs_query_res *response = NULL;
66ec6d59
SRT		 3227 int err;
3228
3229 BUG_ON(!hba);
3230
3231 if (!attr_val) {
3232 dev_err(hba->dev, "%s: attribute value required for opcode 0x%x\n",
3233 __func__, opcode);
8ca1a40b 3234 return -EINVAL;
66ec6d59
SRT		 3235 }
3236
8ca1a40b 3237 ufshcd_hold(hba, false);
3238
66ec6d59 3239 mutex_lock(&hba->dev_cmd.lock);
d44a5f98
DR		 3240 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
3241 selector);
66ec6d59
SRT		 3242
3243 switch (opcode) {
3244 case UPIU_QUERY_OPCODE_WRITE_ATTR:
3245 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
e8c8e82a 3246 request->upiu_req.value = cpu_to_be32(*attr_val);
66ec6d59
SRT		 3247 break;
3248 case UPIU_QUERY_OPCODE_READ_ATTR:
3249 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
3250 break;
3251 default:
3252 dev_err(hba->dev, "%s: Expected query attr opcode but got = 0x%.2x\n",
3253 __func__, opcode);
3254 err = -EINVAL;
3255 goto out_unlock;
3256 }
3257
d44a5f98 3258 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
66ec6d59
SRT		 3259
3260 if (err) {
4b761b58
YG		 3261 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n",
3262 __func__, opcode, idn, index, err);
66ec6d59
SRT		 3263 goto out_unlock;
3264 }
3265
e8c8e82a 3266 *attr_val = be32_to_cpu(response->upiu_res.value);
66ec6d59
SRT		 3267
3268out_unlock:
3269 mutex_unlock(&hba->dev_cmd.lock);
1ab27c9c 3270 ufshcd_release(hba);
66ec6d59
SRT		 3271 return err;
3272}
3273
5e86ae44
YG		 3274/**
3275 * ufshcd_query_attr_retry() - API function for sending query
3276 * attribute with retries
3277 * @hba: per-adapter instance
3278 * @opcode: attribute opcode
3279 * @idn: attribute idn to access
3280 * @index: index field
3281 * @selector: selector field
3282 * @attr_val: the attribute value after the query request
3283 * completes
3284 *
3285 * Returns 0 for success, non-zero in case of failure
3286*/
41d8a933 3287int ufshcd_query_attr_retry(struct ufs_hba *hba,
5e86ae44
YG		 3288 enum query_opcode opcode, enum attr_idn idn, u8 index, u8 selector,
3289 u32 *attr_val)
3290{
3291 int ret = 0;
3292 u32 retries;
3293
68c9fcfd 3294 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
5e86ae44
YG		 3295 ret = ufshcd_query_attr(hba, opcode, idn, index,
3296 selector, attr_val);
3297 if (ret)
3298 dev_dbg(hba->dev, "%s: failed with error %d, retries %d\n",
3299 __func__, ret, retries);
3300 else
3301 break;
3302 }
3303
3304 if (ret)
3305 dev_err(hba->dev,
82ede9c1 3306 "%s: query attribute, idn %d, failed with error %d after %d retries\n",
5e86ae44
YG		 3307 __func__, idn, ret, QUERY_REQ_RETRIES);
3308 return ret;
3309}
3310
a70e91b8 3311static int __ufshcd_query_descriptor(struct ufs_hba *hba,
d44a5f98
DR		 3312 enum query_opcode opcode, enum desc_idn idn, u8 index,
3313 u8 selector, u8 *desc_buf, int *buf_len)
3314{
3315 struct ufs_query_req *request = NULL;
3316 struct ufs_query_res *response = NULL;
3317 int err;
3318
3319 BUG_ON(!hba);
3320
3321 if (!desc_buf) {
3322 dev_err(hba->dev, "%s: descriptor buffer required for opcode 0x%x\n",
3323 __func__, opcode);
8ca1a40b 3324 return -EINVAL;
d44a5f98
DR		 3325 }
3326
a4b0e8a4 3327 if (*buf_len < QUERY_DESC_MIN_SIZE || *buf_len > QUERY_DESC_MAX_SIZE) {
d44a5f98
DR		 3328 dev_err(hba->dev, "%s: descriptor buffer size (%d) is out of range\n",
3329 __func__, *buf_len);
8ca1a40b 3330 return -EINVAL;
d44a5f98
DR		 3331 }
3332
8ca1a40b 3333 ufshcd_hold(hba, false);
3334
d44a5f98
DR		 3335 mutex_lock(&hba->dev_cmd.lock);
3336 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
3337 selector);
3338 hba->dev_cmd.query.descriptor = desc_buf;
ea2aab24 3339 request->upiu_req.length = cpu_to_be16(*buf_len);
d44a5f98
DR		 3340
3341 switch (opcode) {
3342 case UPIU_QUERY_OPCODE_WRITE_DESC:
3343 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
3344 break;
3345 case UPIU_QUERY_OPCODE_READ_DESC:
3346 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
3347 break;
3348 default:
3349 dev_err(hba->dev,
3350 "%s: Expected query descriptor opcode but got = 0x%.2x\n",
3351 __func__, opcode);
3352 err = -EINVAL;
3353 goto out_unlock;
3354 }
3355
3356 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
3357
3358 if (err) {
4b761b58
YG		 3359 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n",
3360 __func__, opcode, idn, index, err);
d44a5f98
DR		 3361 goto out_unlock;
3362 }
3363
ea2aab24 3364 *buf_len = be16_to_cpu(response->upiu_res.length);
d44a5f98
DR		 3365
3366out_unlock:
cfcbae38 3367 hba->dev_cmd.query.descriptor = NULL;
d44a5f98 3368 mutex_unlock(&hba->dev_cmd.lock);
1ab27c9c 3369 ufshcd_release(hba);
d44a5f98
DR		 3370 return err;
3371}
3372
a70e91b8 3373/**
8aa29f19
BVA		 3374 * ufshcd_query_descriptor_retry - API function for sending descriptor requests
3375 * @hba: per-adapter instance
3376 * @opcode: attribute opcode
3377 * @idn: attribute idn to access
3378 * @index: index field
3379 * @selector: selector field
3380 * @desc_buf: the buffer that contains the descriptor
3381 * @buf_len: length parameter passed to the device
a70e91b8
YG		 3382 *
3383 * Returns 0 for success, non-zero in case of failure.
3384 * The buf_len parameter will contain, on return, the length parameter
3385 * received on the response.
3386 */
2238d31c
SN		 3387int ufshcd_query_descriptor_retry(struct ufs_hba *hba,
3388 enum query_opcode opcode,
3389 enum desc_idn idn, u8 index,
3390 u8 selector,
3391 u8 *desc_buf, int *buf_len)
a70e91b8
YG		 3392{
3393 int err;
3394 int retries;
3395
3396 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
3397 err = __ufshcd_query_descriptor(hba, opcode, idn, index,
3398 selector, desc_buf, buf_len);
3399 if (!err || err == -EINVAL)
3400 break;
3401 }
3402
3403 return err;
3404}
a70e91b8 3405
da461cec
SJ		 3406/**
3407 * ufshcd_read_desc_param - read the specified descriptor parameter
3408 * @hba: Pointer to adapter instance
3409 * @desc_id: descriptor idn value
3410 * @desc_index: descriptor index
3411 * @param_offset: offset of the parameter to read
3412 * @param_read_buf: pointer to buffer where parameter would be read
3413 * @param_size: sizeof(param_read_buf)
3414 *
3415 * Return 0 in case of success, non-zero otherwise
3416 */
45bced87
SN		 3417int ufshcd_read_desc_param(struct ufs_hba *hba,
3418 enum desc_idn desc_id,
3419 int desc_index,
3420 u8 param_offset,
3421 u8 *param_read_buf,
3422 u8 param_size)
da461cec
SJ		 3423{
3424 int ret;
3425 u8 *desc_buf;
f2a89b07 3426 int buff_len = QUERY_DESC_MAX_SIZE;
da461cec
SJ		 3427 bool is_kmalloc = true;
3428
a4b0e8a4
PM		 3429 /* Safety check */
3430 if (desc_id >= QUERY_DESC_IDN_MAX || !param_size)
da461cec
SJ		 3431 return -EINVAL;
3432
a4b0e8a4
PM		 3433 /* Check whether we need temp memory */
3434 if (param_offset != 0 || param_size < buff_len) {
1699f980 3435 desc_buf = kzalloc(buff_len, GFP_KERNEL);
da461cec
SJ		 3436 if (!desc_buf)
3437 return -ENOMEM;
a4b0e8a4
PM		 3438 } else {
3439 desc_buf = param_read_buf;
3440 is_kmalloc = false;
da461cec
SJ		 3441 }
3442
a4b0e8a4 3443 /* Request for full descriptor */
a70e91b8 3444 ret = ufshcd_query_descriptor_retry(hba, UPIU_QUERY_OPCODE_READ_DESC,
16ed9d31
AS		 3445 desc_id, desc_index, 0,
3446 desc_buf, &buff_len);
bde44bb6 3447 if (ret) {
1699f980 3448 dev_err(hba->dev, "%s: Failed reading descriptor. desc_id %d, desc_index %d, param_offset %d, ret %d\n",
bde44bb6 3449 __func__, desc_id, desc_index, param_offset, ret);
da461cec
SJ		 3450 goto out;
3451 }
3452
16ed9d31
AS		 3453 /* Update descriptor length */
3454 buff_len = desc_buf[QUERY_DESC_LENGTH_OFFSET];
3455
3456 if (param_offset >= buff_len) {
3457 dev_err(hba->dev, "%s: Invalid offset 0x%x in descriptor IDN 0x%x, length 0x%x\n",
3458 __func__, param_offset, desc_id, buff_len);
3459 return -EINVAL;
3460 }
3461
bde44bb6 3462 /* Sanity check */
3463 if (desc_buf[QUERY_DESC_DESC_TYPE_OFFSET] != desc_id) {
1699f980 3464 dev_err(hba->dev, "%s: invalid desc_id %d in descriptor header\n",
bde44bb6 3465 __func__, desc_buf[QUERY_DESC_DESC_TYPE_OFFSET]);
3466 ret = -EINVAL;
3467 goto out;
3468 }
3469
1699f980
CG		 3470 if (is_kmalloc) {
3471 /* Make sure we don't copy more data than available */
d3d9c457
BVA		 3472 if (param_offset >= buff_len)
3473 ret = -EINVAL;
3474 else
3475 memcpy(param_read_buf, &desc_buf[param_offset],
3476 min_t(u32, param_size, buff_len - param_offset));
1699f980 3477 }
da461cec
SJ		 3478out:
3479 if (is_kmalloc)
3480 kfree(desc_buf);
3481 return ret;
3482}
3483
4b828fe1
TW		 3484/**
3485 * struct uc_string_id - unicode string
3486 *
3487 * @len: size of this descriptor inclusive
3488 * @type: descriptor type
3489 * @uc: unicode string character
3490 */
3491struct uc_string_id {
3492 u8 len;
3493 u8 type;
ec38c0ad 3494 wchar_t uc[];
4b828fe1
TW		 3495} __packed;
3496
3497/* replace non-printable or non-ASCII characters with spaces */
3498static inline char ufshcd_remove_non_printable(u8 ch)
3499{
3500 return (ch >= 0x20 && ch <= 0x7e) ? ch : ' ';
3501}
3502
b573d484
YG		 3503/**
3504 * ufshcd_read_string_desc - read string descriptor
3505 * @hba: pointer to adapter instance
3506 * @desc_index: descriptor index
4b828fe1
TW		 3507 * @buf: pointer to buffer where descriptor would be read,
3508 * the caller should free the memory.
b573d484 3509 * @ascii: if true convert from unicode to ascii characters
4b828fe1 3510 * null terminated string.
b573d484 3511 *
4b828fe1
TW		 3512 * Return:
3513 * * string size on success.
3514 * * -ENOMEM: on allocation failure
3515 * * -EINVAL: on a wrong parameter
b573d484 3516 */
4b828fe1
TW		 3517int ufshcd_read_string_desc(struct ufs_hba *hba, u8 desc_index,
3518 u8 **buf, bool ascii)
b573d484 3519{
4b828fe1
TW		 3520 struct uc_string_id *uc_str;
3521 u8 *str;
3522 int ret;
b573d484 3523
4b828fe1
TW		 3524 if (!buf)
3525 return -EINVAL;
b573d484 3526
4b828fe1
TW		 3527 uc_str = kzalloc(QUERY_DESC_MAX_SIZE, GFP_KERNEL);
3528 if (!uc_str)
3529 return -ENOMEM;
b573d484 3530
c4607a09
BH		 3531 ret = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_STRING, desc_index, 0,
3532 (u8 *)uc_str, QUERY_DESC_MAX_SIZE);
4b828fe1
TW		 3533 if (ret < 0) {
3534 dev_err(hba->dev, "Reading String Desc failed after %d retries. err = %d\n",
3535 QUERY_REQ_RETRIES, ret);
3536 str = NULL;
3537 goto out;
3538 }
3539
3540 if (uc_str->len <= QUERY_DESC_HDR_SIZE) {
3541 dev_dbg(hba->dev, "String Desc is of zero length\n");
3542 str = NULL;
3543 ret = 0;
b573d484
YG		 3544 goto out;
3545 }
3546
3547 if (ascii) {
4b828fe1 3548 ssize_t ascii_len;
b573d484 3549 int i;
b573d484 3550 /* remove header and divide by 2 to move from UTF16 to UTF8 */
4b828fe1
TW		 3551 ascii_len = (uc_str->len - QUERY_DESC_HDR_SIZE) / 2 + 1;
3552 str = kzalloc(ascii_len, GFP_KERNEL);
3553 if (!str) {
3554 ret = -ENOMEM;
fcbefc3b 3555 goto out;
b573d484
YG		 3556 }
3557
3558 /*
3559 * the descriptor contains string in UTF16 format
3560 * we need to convert to utf-8 so it can be displayed
3561 */
4b828fe1
TW		 3562 ret = utf16s_to_utf8s(uc_str->uc,
3563 uc_str->len - QUERY_DESC_HDR_SIZE,
3564 UTF16_BIG_ENDIAN, str, ascii_len);
b573d484
YG		 3565
3566 /* replace non-printable or non-ASCII characters with spaces */
4b828fe1
TW		 3567 for (i = 0; i < ret; i++)
3568 str[i] = ufshcd_remove_non_printable(str[i]);
b573d484 3569
4b828fe1
TW		 3570 str[ret++] = '\0';
3571
3572 } else {
5f57704d 3573 str = kmemdup(uc_str, uc_str->len, GFP_KERNEL);
4b828fe1
TW		 3574 if (!str) {
3575 ret = -ENOMEM;
3576 goto out;
3577 }
4b828fe1 3578 ret = uc_str->len;
b573d484
YG		 3579 }
3580out:
4b828fe1
TW		 3581 *buf = str;
3582 kfree(uc_str);
3583 return ret;
b573d484 3584}
b573d484 3585
da461cec
SJ		 3586/**
3587 * ufshcd_read_unit_desc_param - read the specified unit descriptor parameter
3588 * @hba: Pointer to adapter instance
3589 * @lun: lun id
3590 * @param_offset: offset of the parameter to read
3591 * @param_read_buf: pointer to buffer where parameter would be read
3592 * @param_size: sizeof(param_read_buf)
3593 *
3594 * Return 0 in case of success, non-zero otherwise
3595 */
3596static inline int ufshcd_read_unit_desc_param(struct ufs_hba *hba,
3597 int lun,
3598 enum unit_desc_param param_offset,
3599 u8 *param_read_buf,
3600 u32 param_size)
3601{
3602 /*
3603 * Unit descriptors are only available for general purpose LUs (LUN id
3604 * from 0 to 7) and RPMB Well known LU.
3605 */
b43678ea 3606 if (!ufs_is_valid_unit_desc_lun(&hba->dev_info, lun))
da461cec
SJ		 3607 return -EOPNOTSUPP;
3608
3609 return ufshcd_read_desc_param(hba, QUERY_DESC_IDN_UNIT, lun,
3610 param_offset, param_read_buf, param_size);
3611}
3612
09f17791
CG		 3613static int ufshcd_get_ref_clk_gating_wait(struct ufs_hba *hba)
3614{
3615 int err = 0;
3616 u32 gating_wait = UFSHCD_REF_CLK_GATING_WAIT_US;
3617
3618 if (hba->dev_info.wspecversion >= 0x300) {
3619 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
3620 QUERY_ATTR_IDN_REF_CLK_GATING_WAIT_TIME, 0, 0,
3621 &gating_wait);
3622 if (err)
3623 dev_err(hba->dev, "Failed reading bRefClkGatingWait. err = %d, use default %uus\n",
3624 err, gating_wait);
3625
3626 if (gating_wait == 0) {
3627 gating_wait = UFSHCD_REF_CLK_GATING_WAIT_US;
3628 dev_err(hba->dev, "Undefined ref clk gating wait time, use default %uus\n",
3629 gating_wait);
3630 }
3631
3632 hba->dev_info.clk_gating_wait_us = gating_wait;
3633 }
3634
3635 return err;
3636}
3637
7a3e97b0
SY		 3638/**
3639 * ufshcd_memory_alloc - allocate memory for host memory space data structures
3640 * @hba: per adapter instance
3641 *
3642 * 1. Allocate DMA memory for Command Descriptor array
3643 * Each command descriptor consist of Command UPIU, Response UPIU and PRDT
3644 * 2. Allocate DMA memory for UTP Transfer Request Descriptor List (UTRDL).
3645 * 3. Allocate DMA memory for UTP Task Management Request Descriptor List
3646 * (UTMRDL)
3647 * 4. Allocate memory for local reference block(lrb).
3648 *
3649 * Returns 0 for success, non-zero in case of failure
3650 */
3651static int ufshcd_memory_alloc(struct ufs_hba *hba)
3652{
3653 size_t utmrdl_size, utrdl_size, ucdl_size;
3654
3655 /* Allocate memory for UTP command descriptors */
ada1e653 3656 ucdl_size = sizeof_utp_transfer_cmd_desc(hba) * hba->nutrs;
2953f850
SJ		 3657 hba->ucdl_base_addr = dmam_alloc_coherent(hba->dev,
3658 ucdl_size,
3659 &hba->ucdl_dma_addr,
3660 GFP_KERNEL);
7a3e97b0
SY		 3661
3662 /*
3663 * UFSHCI requires UTP command descriptor to be 128 byte aligned.
3664 * make sure hba->ucdl_dma_addr is aligned to PAGE_SIZE
3665 * if hba->ucdl_dma_addr is aligned to PAGE_SIZE, then it will
3666 * be aligned to 128 bytes as well
3667 */
3668 if (!hba->ucdl_base_addr ||
3669 WARN_ON(hba->ucdl_dma_addr & (PAGE_SIZE - 1))) {
3b1d0580 3670 dev_err(hba->dev,
7a3e97b0
SY		 3671 "Command Descriptor Memory allocation failed\n");
3672 goto out;
3673 }
3674
3675 /*
3676 * Allocate memory for UTP Transfer descriptors
3677 * UFSHCI requires 1024 byte alignment of UTRD
3678 */
3679 utrdl_size = (sizeof(struct utp_transfer_req_desc) * hba->nutrs);
2953f850
SJ		 3680 hba->utrdl_base_addr = dmam_alloc_coherent(hba->dev,
3681 utrdl_size,
3682 &hba->utrdl_dma_addr,
3683 GFP_KERNEL);
7a3e97b0
SY		 3684 if (!hba->utrdl_base_addr ||
3685 WARN_ON(hba->utrdl_dma_addr & (PAGE_SIZE - 1))) {
3b1d0580 3686 dev_err(hba->dev,
7a3e97b0
SY		 3687 "Transfer Descriptor Memory allocation failed\n");
3688 goto out;
3689 }
3690
3691 /*
3692 * Allocate memory for UTP Task Management descriptors
3693 * UFSHCI requires 1024 byte alignment of UTMRD
3694 */
3695 utmrdl_size = sizeof(struct utp_task_req_desc) * hba->nutmrs;
2953f850
SJ		 3696 hba->utmrdl_base_addr = dmam_alloc_coherent(hba->dev,
3697 utmrdl_size,
3698 &hba->utmrdl_dma_addr,
3699 GFP_KERNEL);
7a3e97b0
SY		 3700 if (!hba->utmrdl_base_addr ||
3701 WARN_ON(hba->utmrdl_dma_addr & (PAGE_SIZE - 1))) {
3b1d0580 3702 dev_err(hba->dev,
7a3e97b0
SY		 3703 "Task Management Descriptor Memory allocation failed\n");
3704 goto out;
3705 }
3706
3707 /* Allocate memory for local reference block */
a86854d0
KC		 3708 hba->lrb = devm_kcalloc(hba->dev,
3709 hba->nutrs, sizeof(struct ufshcd_lrb),
2953f850 3710 GFP_KERNEL);
7a3e97b0 3711 if (!hba->lrb) {
3b1d0580 3712 dev_err(hba->dev, "LRB Memory allocation failed\n");
7a3e97b0
SY		 3713 goto out;
3714 }
3715 return 0;
3716out:
7a3e97b0
SY		 3717 return -ENOMEM;
3718}
3719
3720/**
3721 * ufshcd_host_memory_configure - configure local reference block with
3722 * memory offsets
3723 * @hba: per adapter instance
3724 *
3725 * Configure Host memory space
3726 * 1. Update Corresponding UTRD.UCDBA and UTRD.UCDBAU with UCD DMA
3727 * address.
3728 * 2. Update each UTRD with Response UPIU offset, Response UPIU length
3729 * and PRDT offset.
3730 * 3. Save the corresponding addresses of UTRD, UCD.CMD, UCD.RSP and UCD.PRDT
3731 * into local reference block.
3732 */
3733static void ufshcd_host_memory_configure(struct ufs_hba *hba)
3734{
7a3e97b0
SY		 3735 struct utp_transfer_req_desc *utrdlp;
3736 dma_addr_t cmd_desc_dma_addr;
3737 dma_addr_t cmd_desc_element_addr;
3738 u16 response_offset;
3739 u16 prdt_offset;
3740 int cmd_desc_size;
3741 int i;
3742
3743 utrdlp = hba->utrdl_base_addr;
7a3e97b0
SY		 3744
3745 response_offset =
3746 offsetof(struct utp_transfer_cmd_desc, response_upiu);
3747 prdt_offset =
3748 offsetof(struct utp_transfer_cmd_desc, prd_table);
3749
ada1e653 3750 cmd_desc_size = sizeof_utp_transfer_cmd_desc(hba);
7a3e97b0
SY		 3751 cmd_desc_dma_addr = hba->ucdl_dma_addr;
3752
3753 for (i = 0; i < hba->nutrs; i++) {
3754 /* Configure UTRD with command descriptor base address */
3755 cmd_desc_element_addr =
3756 (cmd_desc_dma_addr + (cmd_desc_size * i));
3757 utrdlp[i].command_desc_base_addr_lo =
3758 cpu_to_le32(lower_32_bits(cmd_desc_element_addr));
3759 utrdlp[i].command_desc_base_addr_hi =
3760 cpu_to_le32(upper_32_bits(cmd_desc_element_addr));
3761
3762 /* Response upiu and prdt offset should be in double words */
26f968d7
AA		 3763 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN) {
3764 utrdlp[i].response_upiu_offset =
3765 cpu_to_le16(response_offset);
3766 utrdlp[i].prd_table_offset =
3767 cpu_to_le16(prdt_offset);
3768 utrdlp[i].response_upiu_length =
3769 cpu_to_le16(ALIGNED_UPIU_SIZE);
3770 } else {
3771 utrdlp[i].response_upiu_offset =
3772 cpu_to_le16(response_offset >> 2);
3773 utrdlp[i].prd_table_offset =
3774 cpu_to_le16(prdt_offset >> 2);
3775 utrdlp[i].response_upiu_length =
3776 cpu_to_le16(ALIGNED_UPIU_SIZE >> 2);
3777 }
7a3e97b0 3778
4d2b8d40 3779 ufshcd_init_lrb(hba, &hba->lrb[i], i);
7a3e97b0
SY		 3780 }
3781}
3782
3783/**
3784 * ufshcd_dme_link_startup - Notify Unipro to perform link startup
3785 * @hba: per adapter instance
3786 *
3787 * UIC_CMD_DME_LINK_STARTUP command must be issued to Unipro layer,
3788 * in order to initialize the Unipro link startup procedure.
3789 * Once the Unipro links are up, the device connected to the controller
3790 * is detected.
3791 *
3792 * Returns 0 on success, non-zero value on failure
3793 */
3794static int ufshcd_dme_link_startup(struct ufs_hba *hba)
3795{
6ccf44fe
SJ		 3796 struct uic_command uic_cmd = {0};
3797 int ret;
7a3e97b0 3798
6ccf44fe 3799 uic_cmd.command = UIC_CMD_DME_LINK_STARTUP;
7a3e97b0 3800
6ccf44fe
SJ		 3801 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3802 if (ret)
ff8e20c6 3803 dev_dbg(hba->dev,
6ccf44fe
SJ		 3804 "dme-link-startup: error code %d\n", ret);
3805 return ret;
7a3e97b0 3806}
39bf2d83
AA		 3807/**
3808 * ufshcd_dme_reset - UIC command for DME_RESET
3809 * @hba: per adapter instance
3810 *
3811 * DME_RESET command is issued in order to reset UniPro stack.
3812 * This function now deals with cold reset.
3813 *
3814 * Returns 0 on success, non-zero value on failure
3815 */
3816static int ufshcd_dme_reset(struct ufs_hba *hba)
3817{
3818 struct uic_command uic_cmd = {0};
3819 int ret;
3820
3821 uic_cmd.command = UIC_CMD_DME_RESET;
3822
3823 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3824 if (ret)
3825 dev_err(hba->dev,
3826 "dme-reset: error code %d\n", ret);
3827
3828 return ret;
3829}
3830
fc85a74e
SC		 3831int ufshcd_dme_configure_adapt(struct ufs_hba *hba,
3832 int agreed_gear,
3833 int adapt_val)
3834{
3835 int ret;
3836
d81c4c6f 3837 if (agreed_gear < UFS_HS_G4)
66df79cc 3838 adapt_val = PA_NO_ADAPT;
fc85a74e
SC		 3839
3840 ret = ufshcd_dme_set(hba,
3841 UIC_ARG_MIB(PA_TXHSADAPTTYPE),
3842 adapt_val);
3843 return ret;
3844}
3845EXPORT_SYMBOL_GPL(ufshcd_dme_configure_adapt);
3846
39bf2d83
AA		 3847/**
3848 * ufshcd_dme_enable - UIC command for DME_ENABLE
3849 * @hba: per adapter instance
3850 *
3851 * DME_ENABLE command is issued in order to enable UniPro stack.
3852 *
3853 * Returns 0 on success, non-zero value on failure
3854 */
3855static int ufshcd_dme_enable(struct ufs_hba *hba)
3856{
3857 struct uic_command uic_cmd = {0};
3858 int ret;
3859
3860 uic_cmd.command = UIC_CMD_DME_ENABLE;
3861
3862 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3863 if (ret)
3864 dev_err(hba->dev,
1fa05700 3865 "dme-enable: error code %d\n", ret);
39bf2d83
AA		 3866
3867 return ret;
3868}
7a3e97b0 3869
cad2e03d
YG		 3870static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba)
3871{
3872 #define MIN_DELAY_BEFORE_DME_CMDS_US 1000
3873 unsigned long min_sleep_time_us;
3874
3875 if (!(hba->quirks & UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS))
3876 return;
3877
3878 /*
3879 * last_dme_cmd_tstamp will be 0 only for 1st call to
3880 * this function
3881 */
3882 if (unlikely(!ktime_to_us(hba->last_dme_cmd_tstamp))) {
3883 min_sleep_time_us = MIN_DELAY_BEFORE_DME_CMDS_US;
3884 } else {
3885 unsigned long delta =
3886 (unsigned long) ktime_to_us(
3887 ktime_sub(ktime_get(),
3888 hba->last_dme_cmd_tstamp));
3889
3890 if (delta < MIN_DELAY_BEFORE_DME_CMDS_US)
3891 min_sleep_time_us =
3892 MIN_DELAY_BEFORE_DME_CMDS_US - delta;
3893 else
3894 return; /* no more delay required */
3895 }
3896
3897 /* allow sleep for extra 50us if needed */
3898 usleep_range(min_sleep_time_us, min_sleep_time_us + 50);
3899}
3900
12b4fdb4
SJ		 3901/**
3902 * ufshcd_dme_set_attr - UIC command for DME_SET, DME_PEER_SET
3903 * @hba: per adapter instance
3904 * @attr_sel: uic command argument1
3905 * @attr_set: attribute set type as uic command argument2
3906 * @mib_val: setting value as uic command argument3
3907 * @peer: indicate whether peer or local
3908 *
3909 * Returns 0 on success, non-zero value on failure
3910 */
3911int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel,
3912 u8 attr_set, u32 mib_val, u8 peer)
3913{
3914 struct uic_command uic_cmd = {0};
3915 static const char *const action[] = {
3916 "dme-set",
3917 "dme-peer-set"
3918 };
3919 const char *set = action[!!peer];
3920 int ret;
64238fbd 3921 int retries = UFS_UIC_COMMAND_RETRIES;
12b4fdb4
SJ		 3922
3923 uic_cmd.command = peer ?
3924 UIC_CMD_DME_PEER_SET : UIC_CMD_DME_SET;
3925 uic_cmd.argument1 = attr_sel;
3926 uic_cmd.argument2 = UIC_ARG_ATTR_TYPE(attr_set);
3927 uic_cmd.argument3 = mib_val;
3928
64238fbd
YG		 3929 do {
3930 /* for peer attributes we retry upon failure */
3931 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3932 if (ret)
3933 dev_dbg(hba->dev, "%s: attr-id 0x%x val 0x%x error code %d\n",
3934 set, UIC_GET_ATTR_ID(attr_sel), mib_val, ret);
3935 } while (ret && peer && --retries);
3936
f37e9f8c 3937 if (ret)
64238fbd 3938 dev_err(hba->dev, "%s: attr-id 0x%x val 0x%x failed %d retries\n",
f37e9f8c
YG		 3939 set, UIC_GET_ATTR_ID(attr_sel), mib_val,
3940 UFS_UIC_COMMAND_RETRIES - retries);
12b4fdb4
SJ		 3941
3942 return ret;
3943}
3944EXPORT_SYMBOL_GPL(ufshcd_dme_set_attr);
3945
3946/**
3947 * ufshcd_dme_get_attr - UIC command for DME_GET, DME_PEER_GET
3948 * @hba: per adapter instance
3949 * @attr_sel: uic command argument1
3950 * @mib_val: the value of the attribute as returned by the UIC command
3951 * @peer: indicate whether peer or local
3952 *
3953 * Returns 0 on success, non-zero value on failure
3954 */
3955int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel,
3956 u32 *mib_val, u8 peer)
3957{
3958 struct uic_command uic_cmd = {0};
3959 static const char *const action[] = {
3960 "dme-get",
3961 "dme-peer-get"
3962 };
3963 const char *get = action[!!peer];
3964 int ret;
64238fbd 3965 int retries = UFS_UIC_COMMAND_RETRIES;
874237f7
YG		 3966 struct ufs_pa_layer_attr orig_pwr_info;
3967 struct ufs_pa_layer_attr temp_pwr_info;
3968 bool pwr_mode_change = false;
3969
3970 if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE)) {
3971 orig_pwr_info = hba->pwr_info;
3972 temp_pwr_info = orig_pwr_info;
3973
3974 if (orig_pwr_info.pwr_tx == FAST_MODE ||
3975 orig_pwr_info.pwr_rx == FAST_MODE) {
3976 temp_pwr_info.pwr_tx = FASTAUTO_MODE;
3977 temp_pwr_info.pwr_rx = FASTAUTO_MODE;
3978 pwr_mode_change = true;
3979 } else if (orig_pwr_info.pwr_tx == SLOW_MODE ||
3980 orig_pwr_info.pwr_rx == SLOW_MODE) {
3981 temp_pwr_info.pwr_tx = SLOWAUTO_MODE;
3982 temp_pwr_info.pwr_rx = SLOWAUTO_MODE;
3983 pwr_mode_change = true;
3984 }
3985 if (pwr_mode_change) {
3986 ret = ufshcd_change_power_mode(hba, &temp_pwr_info);
3987 if (ret)
3988 goto out;
3989 }
3990 }
12b4fdb4
SJ		 3991
3992 uic_cmd.command = peer ?
3993 UIC_CMD_DME_PEER_GET : UIC_CMD_DME_GET;
3994 uic_cmd.argument1 = attr_sel;
3995
64238fbd
YG		 3996 do {
3997 /* for peer attributes we retry upon failure */
3998 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3999 if (ret)
4000 dev_dbg(hba->dev, "%s: attr-id 0x%x error code %d\n",
4001 get, UIC_GET_ATTR_ID(attr_sel), ret);
4002 } while (ret && peer && --retries);
4003
f37e9f8c 4004 if (ret)
64238fbd 4005 dev_err(hba->dev, "%s: attr-id 0x%x failed %d retries\n",
f37e9f8c
YG		 4006 get, UIC_GET_ATTR_ID(attr_sel),
4007 UFS_UIC_COMMAND_RETRIES - retries);
12b4fdb4 4008
64238fbd 4009 if (mib_val && !ret)
12b4fdb4 4010 *mib_val = uic_cmd.argument3;
874237f7
YG		 4011
4012 if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE)
4013 && pwr_mode_change)
4014 ufshcd_change_power_mode(hba, &orig_pwr_info);
12b4fdb4
SJ		 4015out:
4016 return ret;
4017}
4018EXPORT_SYMBOL_GPL(ufshcd_dme_get_attr);
4019
53b3d9c3 4020/**
57d104c1
SJ		 4021 * ufshcd_uic_pwr_ctrl - executes UIC commands (which affects the link power
4022 * state) and waits for it to take effect.
4023 *
53b3d9c3 4024 * @hba: per adapter instance
57d104c1
SJ		 4025 * @cmd: UIC command to execute
4026 *
4027 * DME operations like DME_SET(PA_PWRMODE), DME_HIBERNATE_ENTER &
4028 * DME_HIBERNATE_EXIT commands take some time to take its effect on both host
4029 * and device UniPro link and hence it's final completion would be indicated by
4030 * dedicated status bits in Interrupt Status register (UPMS, UHES, UHXS) in
4031 * addition to normal UIC command completion Status (UCCS). This function only
4032 * returns after the relevant status bits indicate the completion.
53b3d9c3
SJ		 4033 *
4034 * Returns 0 on success, non-zero value on failure
4035 */
57d104c1 4036static int ufshcd_uic_pwr_ctrl(struct ufs_hba *hba, struct uic_command *cmd)
53b3d9c3 4037{
8a686f26 4038 DECLARE_COMPLETION_ONSTACK(uic_async_done);
53b3d9c3
SJ		 4039 unsigned long flags;
4040 u8 status;
4041 int ret;
d75f7fe4 4042 bool reenable_intr = false;
53b3d9c3 4043
53b3d9c3 4044 mutex_lock(&hba->uic_cmd_mutex);
cad2e03d 4045 ufshcd_add_delay_before_dme_cmd(hba);
53b3d9c3
SJ		 4046
4047 spin_lock_irqsave(hba->host->host_lock, flags);
4db7a236
CG		 4048 if (ufshcd_is_link_broken(hba)) {
4049 ret = -ENOLINK;
4050 goto out_unlock;
4051 }
57d104c1 4052 hba->uic_async_done = &uic_async_done;
d75f7fe4
YG		 4053 if (ufshcd_readl(hba, REG_INTERRUPT_ENABLE) & UIC_COMMAND_COMPL) {
4054 ufshcd_disable_intr(hba, UIC_COMMAND_COMPL);
4055 /*
4056 * Make sure UIC command completion interrupt is disabled before
4057 * issuing UIC command.
4058 */
4059 wmb();
4060 reenable_intr = true;
57d104c1 4061 }
d75f7fe4
YG		 4062 ret = __ufshcd_send_uic_cmd(hba, cmd, false);
4063 spin_unlock_irqrestore(hba->host->host_lock, flags);
57d104c1
SJ		 4064 if (ret) {
4065 dev_err(hba->dev,
4066 "pwr ctrl cmd 0x%x with mode 0x%x uic error %d\n",
4067 cmd->command, cmd->argument3, ret);
53b3d9c3
SJ		 4068 goto out;
4069 }
4070
57d104c1 4071 if (!wait_for_completion_timeout(hba->uic_async_done,
53b3d9c3
SJ		 4072 msecs_to_jiffies(UIC_CMD_TIMEOUT))) {
4073 dev_err(hba->dev,
57d104c1
SJ		 4074 "pwr ctrl cmd 0x%x with mode 0x%x completion timeout\n",
4075 cmd->command, cmd->argument3);
0f52fcb9
CG		 4076
4077 if (!cmd->cmd_active) {
4078 dev_err(hba->dev, "%s: Power Mode Change operation has been completed, go check UPMCRS\n",
4079 __func__);
4080 goto check_upmcrs;
4081 }
4082
53b3d9c3
SJ		 4083 ret = -ETIMEDOUT;
4084 goto out;
4085 }
4086
0f52fcb9 4087check_upmcrs:
53b3d9c3
SJ		 4088 status = ufshcd_get_upmcrs(hba);
4089 if (status != PWR_LOCAL) {
4090 dev_err(hba->dev,
479da360 4091 "pwr ctrl cmd 0x%x failed, host upmcrs:0x%x\n",
57d104c1 4092 cmd->command, status);
53b3d9c3
SJ		 4093 ret = (status != PWR_OK) ? status : -1;
4094 }
4095out:
7942f7b5
VG		 4096 if (ret) {
4097 ufshcd_print_host_state(hba);
4098 ufshcd_print_pwr_info(hba);
e965e5e0 4099 ufshcd_print_evt_hist(hba);
7942f7b5
VG		 4100 }
4101
53b3d9c3 4102 spin_lock_irqsave(hba->host->host_lock, flags);
d75f7fe4 4103 hba->active_uic_cmd = NULL;
57d104c1 4104 hba->uic_async_done = NULL;
d75f7fe4
YG		 4105 if (reenable_intr)
4106 ufshcd_enable_intr(hba, UIC_COMMAND_COMPL);
4db7a236
CG		 4107 if (ret) {
4108 ufshcd_set_link_broken(hba);
88b09900 4109 ufshcd_schedule_eh_work(hba);
4db7a236
CG		 4110 }
4111out_unlock:
53b3d9c3
SJ		 4112 spin_unlock_irqrestore(hba->host->host_lock, flags);
4113 mutex_unlock(&hba->uic_cmd_mutex);
1ab27c9c 4114
53b3d9c3
SJ		 4115 return ret;
4116}
4117
57d104c1
SJ		 4118/**
4119 * ufshcd_uic_change_pwr_mode - Perform the UIC power mode chage
4120 * using DME_SET primitives.
4121 * @hba: per adapter instance
4122 * @mode: powr mode value
4123 *
4124 * Returns 0 on success, non-zero value on failure
4125 */
fc53683b 4126int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode)
57d104c1
SJ		 4127{
4128 struct uic_command uic_cmd = {0};
1ab27c9c 4129 int ret;
57d104c1 4130
c3a2f9ee
YG		 4131 if (hba->quirks & UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP) {
4132 ret = ufshcd_dme_set(hba,
4133 UIC_ARG_MIB_SEL(PA_RXHSUNTERMCAP, 0), 1);
4134 if (ret) {
4135 dev_err(hba->dev, "%s: failed to enable PA_RXHSUNTERMCAP ret %d\n",
4136 __func__, ret);
4137 goto out;
4138 }
4139 }
4140
57d104c1
SJ		 4141 uic_cmd.command = UIC_CMD_DME_SET;
4142 uic_cmd.argument1 = UIC_ARG_MIB(PA_PWRMODE);
4143 uic_cmd.argument3 = mode;
1ab27c9c
ST		 4144 ufshcd_hold(hba, false);
4145 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
4146 ufshcd_release(hba);
57d104c1 4147
c3a2f9ee 4148out:
1ab27c9c 4149 return ret;
57d104c1 4150}
fc53683b 4151EXPORT_SYMBOL_GPL(ufshcd_uic_change_pwr_mode);
57d104c1 4152
087c5efa 4153int ufshcd_link_recovery(struct ufs_hba *hba)
53c12d0e
YG		 4154{
4155 int ret;
4156 unsigned long flags;
4157
4158 spin_lock_irqsave(hba->host->host_lock, flags);
4159 hba->ufshcd_state = UFSHCD_STATE_RESET;
4160 ufshcd_set_eh_in_progress(hba);
4161 spin_unlock_irqrestore(hba->host->host_lock, flags);
4162
ebdd1dfd 4163 /* Reset the attached device */
31a5d9ca 4164 ufshcd_device_reset(hba);
ebdd1dfd 4165
53c12d0e
YG		 4166 ret = ufshcd_host_reset_and_restore(hba);
4167
4168 spin_lock_irqsave(hba->host->host_lock, flags);
4169 if (ret)
4170 hba->ufshcd_state = UFSHCD_STATE_ERROR;
4171 ufshcd_clear_eh_in_progress(hba);
4172 spin_unlock_irqrestore(hba->host->host_lock, flags);
4173
4174 if (ret)
4175 dev_err(hba->dev, "%s: link recovery failed, err %d",
4176 __func__, ret);
4177
4178 return ret;
4179}
087c5efa 4180EXPORT_SYMBOL_GPL(ufshcd_link_recovery);
53c12d0e 4181
525943a5 4182int ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
57d104c1 4183{
87d0b4a6 4184 int ret;
57d104c1 4185 struct uic_command uic_cmd = {0};
911a0771 4186 ktime_t start = ktime_get();
57d104c1 4187
ee32c909
KK		 4188 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_ENTER, PRE_CHANGE);
4189
57d104c1 4190 uic_cmd.command = UIC_CMD_DME_HIBER_ENTER;
87d0b4a6 4191 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
911a0771 4192 trace_ufshcd_profile_hibern8(dev_name(hba->dev), "enter",
4193 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
87d0b4a6 4194
4db7a236 4195 if (ret)
87d0b4a6
YG		 4196 dev_err(hba->dev, "%s: hibern8 enter failed. ret = %d\n",
4197 __func__, ret);
4db7a236 4198 else
ee32c909
KK		 4199 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_ENTER,
4200 POST_CHANGE);
53c12d0e 4201
87d0b4a6
YG		 4202 return ret;
4203}
525943a5 4204EXPORT_SYMBOL_GPL(ufshcd_uic_hibern8_enter);
87d0b4a6 4205
9d19bf7a 4206int ufshcd_uic_hibern8_exit(struct ufs_hba *hba)
57d104c1
SJ		 4207{
4208 struct uic_command uic_cmd = {0};
4209 int ret;
911a0771 4210 ktime_t start = ktime_get();
57d104c1 4211
ee32c909
KK		 4212 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_EXIT, PRE_CHANGE);
4213
57d104c1
SJ		 4214 uic_cmd.command = UIC_CMD_DME_HIBER_EXIT;
4215 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
911a0771 4216 trace_ufshcd_profile_hibern8(dev_name(hba->dev), "exit",
4217 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
4218
57d104c1 4219 if (ret) {
53c12d0e
YG		 4220 dev_err(hba->dev, "%s: hibern8 exit failed. ret = %d\n",
4221 __func__, ret);
ff8e20c6 4222 } else {
ee32c909
KK		 4223 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_EXIT,
4224 POST_CHANGE);
0f85e747 4225 hba->ufs_stats.last_hibern8_exit_tstamp = local_clock();
ff8e20c6
DR		 4226 hba->ufs_stats.hibern8_exit_cnt++;
4227 }
57d104c1
SJ		 4228
4229 return ret;
4230}
9d19bf7a 4231EXPORT_SYMBOL_GPL(ufshcd_uic_hibern8_exit);
57d104c1 4232
ba7af5ec
SC		 4233void ufshcd_auto_hibern8_update(struct ufs_hba *hba, u32 ahit)
4234{
4235 unsigned long flags;
be7594a4 4236 bool update = false;
ba7af5ec 4237
be7594a4 4238 if (!ufshcd_is_auto_hibern8_supported(hba))
ba7af5ec
SC		 4239 return;
4240
4241 spin_lock_irqsave(hba->host->host_lock, flags);
be7594a4
CG		 4242 if (hba->ahit != ahit) {
4243 hba->ahit = ahit;
4244 update = true;
4245 }
ba7af5ec 4246 spin_unlock_irqrestore(hba->host->host_lock, flags);
be7594a4 4247
b294ff3e 4248 if (update &&
e2106584 4249 !pm_runtime_suspended(&hba->ufs_device_wlun->sdev_gendev)) {
b294ff3e 4250 ufshcd_rpm_get_sync(hba);
be7594a4
CG		 4251 ufshcd_hold(hba, false);
4252 ufshcd_auto_hibern8_enable(hba);
4253 ufshcd_release(hba);
b294ff3e 4254 ufshcd_rpm_put_sync(hba);
be7594a4 4255 }
ba7af5ec
SC		 4256}
4257EXPORT_SYMBOL_GPL(ufshcd_auto_hibern8_update);
4258
71d848b8 4259void ufshcd_auto_hibern8_enable(struct ufs_hba *hba)
ad448378 4260{
499f7a96 4261 if (!ufshcd_is_auto_hibern8_supported(hba))
ad448378
AH		 4262 return;
4263
ad448378 4264 ufshcd_writel(hba, hba->ahit, REG_AUTO_HIBERNATE_IDLE_TIMER);
ad448378
AH		 4265}
4266
5064636c
YG		 4267 /**
4268 * ufshcd_init_pwr_info - setting the POR (power on reset)
4269 * values in hba power info
4270 * @hba: per-adapter instance
4271 */
4272static void ufshcd_init_pwr_info(struct ufs_hba *hba)
4273{
4274 hba->pwr_info.gear_rx = UFS_PWM_G1;
4275 hba->pwr_info.gear_tx = UFS_PWM_G1;
4276 hba->pwr_info.lane_rx = 1;
4277 hba->pwr_info.lane_tx = 1;
4278 hba->pwr_info.pwr_rx = SLOWAUTO_MODE;
4279 hba->pwr_info.pwr_tx = SLOWAUTO_MODE;
4280 hba->pwr_info.hs_rate = 0;
4281}
4282
d3e89bac 4283/**
7eb584db
DR		 4284 * ufshcd_get_max_pwr_mode - reads the max power mode negotiated with device
4285 * @hba: per-adapter instance
d3e89bac 4286 */
7eb584db 4287static int ufshcd_get_max_pwr_mode(struct ufs_hba *hba)
d3e89bac 4288{
7eb584db
DR		 4289 struct ufs_pa_layer_attr *pwr_info = &hba->max_pwr_info.info;
4290
4291 if (hba->max_pwr_info.is_valid)
4292 return 0;
4293
2f11bbc2
YS		 4294 if (hba->quirks & UFSHCD_QUIRK_HIBERN_FASTAUTO) {
4295 pwr_info->pwr_tx = FASTAUTO_MODE;
4296 pwr_info->pwr_rx = FASTAUTO_MODE;
4297 } else {
4298 pwr_info->pwr_tx = FAST_MODE;
4299 pwr_info->pwr_rx = FAST_MODE;
4300 }
7eb584db 4301 pwr_info->hs_rate = PA_HS_MODE_B;
d3e89bac
SJ		 4302
4303 /* Get the connected lane count */
7eb584db
DR		 4304 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDRXDATALANES),
4305 &pwr_info->lane_rx);
4306 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
4307 &pwr_info->lane_tx);
4308
4309 if (!pwr_info->lane_rx || !pwr_info->lane_tx) {
4310 dev_err(hba->dev, "%s: invalid connected lanes value. rx=%d, tx=%d\n",
4311 __func__,
4312 pwr_info->lane_rx,
4313 pwr_info->lane_tx);
4314 return -EINVAL;
4315 }
d3e89bac
SJ		 4316
4317 /*
4318 * First, get the maximum gears of HS speed.
4319 * If a zero value, it means there is no HSGEAR capability.
4320 * Then, get the maximum gears of PWM speed.
4321 */
7eb584db
DR		 4322 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR), &pwr_info->gear_rx);
4323 if (!pwr_info->gear_rx) {
4324 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
4325 &pwr_info->gear_rx);
4326 if (!pwr_info->gear_rx) {
4327 dev_err(hba->dev, "%s: invalid max pwm rx gear read = %d\n",
4328 __func__, pwr_info->gear_rx);
4329 return -EINVAL;
4330 }
2349b533 4331 pwr_info->pwr_rx = SLOW_MODE;
d3e89bac
SJ		 4332 }
4333
7eb584db
DR		 4334 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR),
4335 &pwr_info->gear_tx);
4336 if (!pwr_info->gear_tx) {
d3e89bac 4337 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
7eb584db
DR		 4338 &pwr_info->gear_tx);
4339 if (!pwr_info->gear_tx) {
4340 dev_err(hba->dev, "%s: invalid max pwm tx gear read = %d\n",
4341 __func__, pwr_info->gear_tx);
4342 return -EINVAL;
4343 }
2349b533 4344 pwr_info->pwr_tx = SLOW_MODE;
7eb584db
DR		 4345 }
4346
4347 hba->max_pwr_info.is_valid = true;
4348 return 0;
4349}
4350
4351static int ufshcd_change_power_mode(struct ufs_hba *hba,
4352 struct ufs_pa_layer_attr *pwr_mode)
4353{
4354 int ret;
4355
4356 /* if already configured to the requested pwr_mode */
2355b66e
CG		 4357 if (!hba->force_pmc &&
4358 pwr_mode->gear_rx == hba->pwr_info.gear_rx &&
7eb584db
DR		 4359 pwr_mode->gear_tx == hba->pwr_info.gear_tx &&
4360 pwr_mode->lane_rx == hba->pwr_info.lane_rx &&
4361 pwr_mode->lane_tx == hba->pwr_info.lane_tx &&
4362 pwr_mode->pwr_rx == hba->pwr_info.pwr_rx &&
4363 pwr_mode->pwr_tx == hba->pwr_info.pwr_tx &&
4364 pwr_mode->hs_rate == hba->pwr_info.hs_rate) {
4365 dev_dbg(hba->dev, "%s: power already configured\n", __func__);
4366 return 0;
d3e89bac
SJ		 4367 }
4368
4369 /*
4370 * Configure attributes for power mode change with below.
4371 * - PA_RXGEAR, PA_ACTIVERXDATALANES, PA_RXTERMINATION,
4372 * - PA_TXGEAR, PA_ACTIVETXDATALANES, PA_TXTERMINATION,
4373 * - PA_HSSERIES
4374 */
7eb584db
DR		 4375 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXGEAR), pwr_mode->gear_rx);
4376 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVERXDATALANES),
4377 pwr_mode->lane_rx);
4378 if (pwr_mode->pwr_rx == FASTAUTO_MODE ||
4379 pwr_mode->pwr_rx == FAST_MODE)
21c2e341 4380 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), true);
7eb584db 4381 else
21c2e341 4382 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), false);
d3e89bac 4383
7eb584db
DR		 4384 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXGEAR), pwr_mode->gear_tx);
4385 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVETXDATALANES),
4386 pwr_mode->lane_tx);
4387 if (pwr_mode->pwr_tx == FASTAUTO_MODE ||
4388 pwr_mode->pwr_tx == FAST_MODE)
21c2e341 4389 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), true);
7eb584db 4390 else
21c2e341 4391 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), false);
d3e89bac 4392
7eb584db
DR		 4393 if (pwr_mode->pwr_rx == FASTAUTO_MODE ||
4394 pwr_mode->pwr_tx == FASTAUTO_MODE ||
4395 pwr_mode->pwr_rx == FAST_MODE ||
4396 pwr_mode->pwr_tx == FAST_MODE)
4397 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HSSERIES),
4398 pwr_mode->hs_rate);
d3e89bac 4399
b1d0d2eb
KK		 4400 if (!(hba->quirks & UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING)) {
4401 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA0),
4402 DL_FC0ProtectionTimeOutVal_Default);
4403 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA1),
4404 DL_TC0ReplayTimeOutVal_Default);
4405 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA2),
4406 DL_AFC0ReqTimeOutVal_Default);
4407 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA3),
4408 DL_FC1ProtectionTimeOutVal_Default);
4409 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA4),
4410 DL_TC1ReplayTimeOutVal_Default);
4411 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA5),
4412 DL_AFC1ReqTimeOutVal_Default);
4413
4414 ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalFC0ProtectionTimeOutVal),
4415 DL_FC0ProtectionTimeOutVal_Default);
4416 ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalTC0ReplayTimeOutVal),
4417 DL_TC0ReplayTimeOutVal_Default);
4418 ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalAFC0ReqTimeOutVal),
4419 DL_AFC0ReqTimeOutVal_Default);
4420 }
08342537 4421
7eb584db
DR		 4422 ret = ufshcd_uic_change_pwr_mode(hba, pwr_mode->pwr_rx << 4
4423 | pwr_mode->pwr_tx);
4424
4425 if (ret) {
d3e89bac 4426 dev_err(hba->dev,
7eb584db
DR		 4427 "%s: power mode change failed %d\n", __func__, ret);
4428 } else {
0263bcd0
YG		 4429 ufshcd_vops_pwr_change_notify(hba, POST_CHANGE, NULL,
4430 pwr_mode);
7eb584db
DR		 4431
4432 memcpy(&hba->pwr_info, pwr_mode,
4433 sizeof(struct ufs_pa_layer_attr));
4434 }
4435
4436 return ret;
4437}
4438
4439/**
4440 * ufshcd_config_pwr_mode - configure a new power mode
4441 * @hba: per-adapter instance
4442 * @desired_pwr_mode: desired power configuration
4443 */
0d846e70 4444int ufshcd_config_pwr_mode(struct ufs_hba *hba,
7eb584db
DR		 4445 struct ufs_pa_layer_attr *desired_pwr_mode)
4446{
4447 struct ufs_pa_layer_attr final_params = { 0 };
4448 int ret;
4449
0263bcd0
YG		 4450 ret = ufshcd_vops_pwr_change_notify(hba, PRE_CHANGE,
4451 desired_pwr_mode, &final_params);
4452
4453 if (ret)
7eb584db
DR		 4454 memcpy(&final_params, desired_pwr_mode, sizeof(final_params));
4455
4456 ret = ufshcd_change_power_mode(hba, &final_params);
d3e89bac
SJ		 4457
4458 return ret;
4459}
0d846e70 4460EXPORT_SYMBOL_GPL(ufshcd_config_pwr_mode);
d3e89bac 4461
68078d5c
DR		 4462/**
4463 * ufshcd_complete_dev_init() - checks device readiness
8aa29f19 4464 * @hba: per-adapter instance
68078d5c
DR		 4465 *
4466 * Set fDeviceInit flag and poll until device toggles it.
4467 */
4468static int ufshcd_complete_dev_init(struct ufs_hba *hba)
4469{
dc3c8d3a 4470 int err;
7dfdcc39 4471 bool flag_res = true;
29707fab 4472 ktime_t timeout;
68078d5c 4473
dc3c8d3a 4474 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG,
1f34eedf 4475 QUERY_FLAG_IDN_FDEVICEINIT, 0, NULL);
68078d5c
DR		 4476 if (err) {
4477 dev_err(hba->dev,
859ed37c 4478 "%s: setting fDeviceInit flag failed with error %d\n",
68078d5c
DR		 4479 __func__, err);
4480 goto out;
4481 }
4482
29707fab
KK		 4483 /* Poll fDeviceInit flag to be cleared */
4484 timeout = ktime_add_ms(ktime_get(), FDEVICEINIT_COMPL_TIMEOUT);
4485 do {
4486 err = ufshcd_query_flag(hba, UPIU_QUERY_OPCODE_READ_FLAG,
4487 QUERY_FLAG_IDN_FDEVICEINIT, 0, &flag_res);
4488 if (!flag_res)
4489 break;
a4e6496f 4490 usleep_range(500, 1000);
29707fab 4491 } while (ktime_before(ktime_get(), timeout));
dc3c8d3a 4492
29707fab 4493 if (err) {
68078d5c 4494 dev_err(hba->dev,
859ed37c 4495 "%s: reading fDeviceInit flag failed with error %d\n",
29707fab
KK		 4496 __func__, err);
4497 } else if (flag_res) {
68078d5c 4498 dev_err(hba->dev,
859ed37c 4499 "%s: fDeviceInit was not cleared by the device\n",
29707fab
KK		 4500 __func__);
4501 err = -EBUSY;
4502 }
68078d5c
DR		 4503out:
4504 return err;
4505}
4506
7a3e97b0
SY		 4507/**
4508 * ufshcd_make_hba_operational - Make UFS controller operational
4509 * @hba: per adapter instance
4510 *
4511 * To bring UFS host controller to operational state,
5c0c28a8
SRT		 4512 * 1. Enable required interrupts
4513 * 2. Configure interrupt aggregation
897efe62 4514 * 3. Program UTRL and UTMRL base address
5c0c28a8 4515 * 4. Configure run-stop-registers
7a3e97b0
SY		 4516 *
4517 * Returns 0 on success, non-zero value on failure
4518 */
9d19bf7a 4519int ufshcd_make_hba_operational(struct ufs_hba *hba)
7a3e97b0
SY		 4520{
4521 int err = 0;
4522 u32 reg;
4523
6ccf44fe
SJ		 4524 /* Enable required interrupts */
4525 ufshcd_enable_intr(hba, UFSHCD_ENABLE_INTRS);
4526
4527 /* Configure interrupt aggregation */
b852190e
YG		 4528 if (ufshcd_is_intr_aggr_allowed(hba))
4529 ufshcd_config_intr_aggr(hba, hba->nutrs - 1, INT_AGGR_DEF_TO);
4530 else
4531 ufshcd_disable_intr_aggr(hba);
6ccf44fe
SJ		 4532
4533 /* Configure UTRL and UTMRL base address registers */
4534 ufshcd_writel(hba, lower_32_bits(hba->utrdl_dma_addr),
4535 REG_UTP_TRANSFER_REQ_LIST_BASE_L);
4536 ufshcd_writel(hba, upper_32_bits(hba->utrdl_dma_addr),
4537 REG_UTP_TRANSFER_REQ_LIST_BASE_H);
4538 ufshcd_writel(hba, lower_32_bits(hba->utmrdl_dma_addr),
4539 REG_UTP_TASK_REQ_LIST_BASE_L);
4540 ufshcd_writel(hba, upper_32_bits(hba->utmrdl_dma_addr),
4541 REG_UTP_TASK_REQ_LIST_BASE_H);
4542
897efe62
YG		 4543 /*
4544 * Make sure base address and interrupt setup are updated before
4545 * enabling the run/stop registers below.
4546 */
4547 wmb();
4548
7a3e97b0
SY		 4549 /*
4550 * UCRDY, UTMRLDY and UTRLRDY bits must be 1
7a3e97b0 4551 */
5c0c28a8 4552 reg = ufshcd_readl(hba, REG_CONTROLLER_STATUS);
7a3e97b0
SY		 4553 if (!(ufshcd_get_lists_status(reg))) {
4554 ufshcd_enable_run_stop_reg(hba);
4555 } else {
3b1d0580 4556 dev_err(hba->dev,
7a3e97b0
SY		 4557 "Host controller not ready to process requests");
4558 err = -EIO;
7a3e97b0
SY		 4559 }
4560
7a3e97b0
SY		 4561 return err;
4562}
9d19bf7a 4563EXPORT_SYMBOL_GPL(ufshcd_make_hba_operational);
7a3e97b0 4564
596585a2
YG		 4565/**
4566 * ufshcd_hba_stop - Send controller to reset state
4567 * @hba: per adapter instance
596585a2 4568 */
3a95f5b3 4569void ufshcd_hba_stop(struct ufs_hba *hba)
596585a2 4570{
5cac1095 4571 unsigned long flags;
596585a2
YG		 4572 int err;
4573
5cac1095
BVA		 4574 /*
4575 * Obtain the host lock to prevent that the controller is disabled
4576 * while the UFS interrupt handler is active on another CPU.
4577 */
4578 spin_lock_irqsave(hba->host->host_lock, flags);
596585a2 4579 ufshcd_writel(hba, CONTROLLER_DISABLE, REG_CONTROLLER_ENABLE);
5cac1095
BVA		 4580 spin_unlock_irqrestore(hba->host->host_lock, flags);
4581
596585a2
YG		 4582 err = ufshcd_wait_for_register(hba, REG_CONTROLLER_ENABLE,
4583 CONTROLLER_ENABLE, CONTROLLER_DISABLE,
5cac1095 4584 10, 1);
596585a2
YG		 4585 if (err)
4586 dev_err(hba->dev, "%s: Controller disable failed\n", __func__);
4587}
3a95f5b3 4588EXPORT_SYMBOL_GPL(ufshcd_hba_stop);
596585a2 4589
7a3e97b0 4590/**
39bf2d83 4591 * ufshcd_hba_execute_hce - initialize the controller
7a3e97b0
SY		 4592 * @hba: per adapter instance
4593 *
4594 * The controller resets itself and controller firmware initialization
4595 * sequence kicks off. When controller is ready it will set
4596 * the Host Controller Enable bit to 1.
4597 *
4598 * Returns 0 on success, non-zero value on failure
4599 */
39bf2d83 4600static int ufshcd_hba_execute_hce(struct ufs_hba *hba)
7a3e97b0 4601{
6081b12c
SC		 4602 int retry_outer = 3;
4603 int retry_inner;
7a3e97b0 4604
6081b12c 4605start:
acbbfe48 4606 if (ufshcd_is_hba_active(hba))
7a3e97b0 4607 /* change controller state to "reset state" */
5cac1095 4608 ufshcd_hba_stop(hba);
7a3e97b0 4609
57d104c1
SJ		 4610 /* UniPro link is disabled at this point */
4611 ufshcd_set_link_off(hba);
4612
0263bcd0 4613 ufshcd_vops_hce_enable_notify(hba, PRE_CHANGE);
5c0c28a8 4614
7a3e97b0
SY		 4615 /* start controller initialization sequence */
4616 ufshcd_hba_start(hba);
4617
4618 /*
4619 * To initialize a UFS host controller HCE bit must be set to 1.
4620 * During initialization the HCE bit value changes from 1->0->1.
4621 * When the host controller completes initialization sequence
4622 * it sets the value of HCE bit to 1. The same HCE bit is read back
4623 * to check if the controller has completed initialization sequence.
4624 * So without this delay the value HCE = 1, set in the previous
4625 * instruction might be read back.
4626 * This delay can be changed based on the controller.
4627 */
90b8491c 4628 ufshcd_delay_us(hba->vps->hba_enable_delay_us, 100);
7a3e97b0
SY		 4629
4630 /* wait for the host controller to complete initialization */
6081b12c 4631 retry_inner = 50;
acbbfe48 4632 while (!ufshcd_is_hba_active(hba)) {
6081b12c
SC		 4633 if (retry_inner) {
4634 retry_inner--;
7a3e97b0 4635 } else {
3b1d0580 4636 dev_err(hba->dev,
7a3e97b0 4637 "Controller enable failed\n");
6081b12c
SC		 4638 if (retry_outer) {
4639 retry_outer--;
4640 goto start;
4641 }
7a3e97b0
SY		 4642 return -EIO;
4643 }
9fc305ef 4644 usleep_range(1000, 1100);
7a3e97b0 4645 }
5c0c28a8 4646
1d337ec2 4647 /* enable UIC related interrupts */
57d104c1 4648 ufshcd_enable_intr(hba, UFSHCD_UIC_MASK);
1d337ec2 4649
0263bcd0 4650 ufshcd_vops_hce_enable_notify(hba, POST_CHANGE);
5c0c28a8 4651
7a3e97b0
SY		 4652 return 0;
4653}
39bf2d83
AA		 4654
4655int ufshcd_hba_enable(struct ufs_hba *hba)
4656{
4657 int ret;
4658
4659 if (hba->quirks & UFSHCI_QUIRK_BROKEN_HCE) {
4660 ufshcd_set_link_off(hba);
4661 ufshcd_vops_hce_enable_notify(hba, PRE_CHANGE);
4662
4663 /* enable UIC related interrupts */
4664 ufshcd_enable_intr(hba, UFSHCD_UIC_MASK);
4665 ret = ufshcd_dme_reset(hba);
bc77fb9c
KP		 4666 if (ret) {
4667 dev_err(hba->dev, "DME_RESET failed\n");
4668 return ret;
4669 }
4670
4671 ret = ufshcd_dme_enable(hba);
4672 if (ret) {
4673 dev_err(hba->dev, "Enabling DME failed\n");
4674 return ret;
39bf2d83 4675 }
bc77fb9c
KP		 4676
4677 ufshcd_vops_hce_enable_notify(hba, POST_CHANGE);
39bf2d83
AA		 4678 } else {
4679 ret = ufshcd_hba_execute_hce(hba);
4680 }
4681
4682 return ret;
4683}
9d19bf7a
SC		 4684EXPORT_SYMBOL_GPL(ufshcd_hba_enable);
4685
7ca38cf3
YG		 4686static int ufshcd_disable_tx_lcc(struct ufs_hba *hba, bool peer)
4687{
ba0320fb 4688 int tx_lanes = 0, i, err = 0;
7ca38cf3
YG		 4689
4690 if (!peer)
4691 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
4692 &tx_lanes);
4693 else
4694 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
4695 &tx_lanes);
4696 for (i = 0; i < tx_lanes; i++) {
4697 if (!peer)
4698 err = ufshcd_dme_set(hba,
4699 UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
4700 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
4701 0);
4702 else
4703 err = ufshcd_dme_peer_set(hba,
4704 UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
4705 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
4706 0);
4707 if (err) {
4708 dev_err(hba->dev, "%s: TX LCC Disable failed, peer = %d, lane = %d, err = %d",
4709 __func__, peer, i, err);
4710 break;
4711 }
4712 }
4713
4714 return err;
4715}
4716
4717static inline int ufshcd_disable_device_tx_lcc(struct ufs_hba *hba)
4718{
4719 return ufshcd_disable_tx_lcc(hba, true);
4720}
4721
e965e5e0 4722void ufshcd_update_evt_hist(struct ufs_hba *hba, u32 id, u32 val)
8808b4e9 4723{
e965e5e0
SC		 4724 struct ufs_event_hist *e;
4725
4726 if (id >= UFS_EVT_CNT)
4727 return;
4728
4729 e = &hba->ufs_stats.event[id];
4730 e->val[e->pos] = val;
0f85e747 4731 e->tstamp[e->pos] = local_clock();
b6cacaf2 4732 e->cnt += 1;
e965e5e0 4733 e->pos = (e->pos + 1) % UFS_EVENT_HIST_LENGTH;
172614a9
SC		 4734
4735 ufshcd_vops_event_notify(hba, id, &val);
8808b4e9 4736}
e965e5e0 4737EXPORT_SYMBOL_GPL(ufshcd_update_evt_hist);
8808b4e9 4738
7a3e97b0 4739/**
6ccf44fe 4740 * ufshcd_link_startup - Initialize unipro link startup
7a3e97b0
SY		 4741 * @hba: per adapter instance
4742 *
6ccf44fe 4743 * Returns 0 for success, non-zero in case of failure
7a3e97b0 4744 */
6ccf44fe 4745static int ufshcd_link_startup(struct ufs_hba *hba)
7a3e97b0 4746{
6ccf44fe 4747 int ret;
1d337ec2 4748 int retries = DME_LINKSTARTUP_RETRIES;
7caf489b 4749 bool link_startup_again = false;
7a3e97b0 4750
7caf489b 4751 /*
4752 * If UFS device isn't active then we will have to issue link startup
4753 * 2 times to make sure the device state move to active.
4754 */
4755 if (!ufshcd_is_ufs_dev_active(hba))
4756 link_startup_again = true;
7a3e97b0 4757
7caf489b 4758link_startup:
1d337ec2 4759 do {
0263bcd0 4760 ufshcd_vops_link_startup_notify(hba, PRE_CHANGE);
6ccf44fe 4761
1d337ec2 4762 ret = ufshcd_dme_link_startup(hba);
5c0c28a8 4763
1d337ec2
SRT		 4764 /* check if device is detected by inter-connect layer */
4765 if (!ret && !ufshcd_is_device_present(hba)) {
e965e5e0
SC		 4766 ufshcd_update_evt_hist(hba,
4767 UFS_EVT_LINK_STARTUP_FAIL,
8808b4e9 4768 0);
1d337ec2
SRT		 4769 dev_err(hba->dev, "%s: Device not present\n", __func__);
4770 ret = -ENXIO;
4771 goto out;
4772 }
6ccf44fe 4773
1d337ec2
SRT		 4774 /*
4775 * DME link lost indication is only received when link is up,
4776 * but we can't be sure if the link is up until link startup
4777 * succeeds. So reset the local Uni-Pro and try again.
4778 */
174e909b 4779 if (ret && retries && ufshcd_hba_enable(hba)) {
e965e5e0
SC		 4780 ufshcd_update_evt_hist(hba,
4781 UFS_EVT_LINK_STARTUP_FAIL,
8808b4e9 4782 (u32)ret);
1d337ec2 4783 goto out;
8808b4e9 4784 }
1d337ec2
SRT		 4785 } while (ret && retries--);
4786
8808b4e9 4787 if (ret) {
1d337ec2 4788 /* failed to get the link up... retire */
e965e5e0
SC		 4789 ufshcd_update_evt_hist(hba,
4790 UFS_EVT_LINK_STARTUP_FAIL,
8808b4e9 4791 (u32)ret);
5c0c28a8 4792 goto out;
8808b4e9 4793 }
5c0c28a8 4794
7caf489b 4795 if (link_startup_again) {
4796 link_startup_again = false;
4797 retries = DME_LINKSTARTUP_RETRIES;
4798 goto link_startup;
4799 }
4800
d2aebb9b 4801 /* Mark that link is up in PWM-G1, 1-lane, SLOW-AUTO mode */
4802 ufshcd_init_pwr_info(hba);
4803 ufshcd_print_pwr_info(hba);
4804
7ca38cf3
YG		 4805 if (hba->quirks & UFSHCD_QUIRK_BROKEN_LCC) {
4806 ret = ufshcd_disable_device_tx_lcc(hba);
4807 if (ret)
4808 goto out;
4809 }
4810
5c0c28a8 4811 /* Include any host controller configuration via UIC commands */
0263bcd0
YG		 4812 ret = ufshcd_vops_link_startup_notify(hba, POST_CHANGE);
4813 if (ret)
4814 goto out;
7a3e97b0 4815
2355b66e
CG		 4816 /* Clear UECPA once due to LINERESET has happened during LINK_STARTUP */
4817 ufshcd_readl(hba, REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER);
5c0c28a8 4818 ret = ufshcd_make_hba_operational(hba);
6ccf44fe 4819out:
7942f7b5 4820 if (ret) {
6ccf44fe 4821 dev_err(hba->dev, "link startup failed %d\n", ret);
7942f7b5
VG		 4822 ufshcd_print_host_state(hba);
4823 ufshcd_print_pwr_info(hba);
e965e5e0 4824 ufshcd_print_evt_hist(hba);
7942f7b5 4825 }
6ccf44fe 4826 return ret;
7a3e97b0
SY		 4827}
4828
5a0b0cb9
SRT		 4829/**
4830 * ufshcd_verify_dev_init() - Verify device initialization
4831 * @hba: per-adapter instance
4832 *
4833 * Send NOP OUT UPIU and wait for NOP IN response to check whether the
4834 * device Transport Protocol (UTP) layer is ready after a reset.
4835 * If the UTP layer at the device side is not initialized, it may
4836 * not respond with NOP IN UPIU within timeout of %NOP_OUT_TIMEOUT
4837 * and we retry sending NOP OUT for %NOP_OUT_RETRIES iterations.
4838 */
4839static int ufshcd_verify_dev_init(struct ufs_hba *hba)
4840{
4841 int err = 0;
4842 int retries;
4843
1ab27c9c 4844 ufshcd_hold(hba, false);
5a0b0cb9
SRT		 4845 mutex_lock(&hba->dev_cmd.lock);
4846 for (retries = NOP_OUT_RETRIES; retries > 0; retries--) {
4847 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_NOP,
1cbc9ad3 4848 hba->nop_out_timeout);
5a0b0cb9
SRT		 4849
4850 if (!err || err == -ETIMEDOUT)
4851 break;
4852
4853 dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, err);
4854 }
4855 mutex_unlock(&hba->dev_cmd.lock);
1ab27c9c 4856 ufshcd_release(hba);
5a0b0cb9
SRT		 4857
4858 if (err)
4859 dev_err(hba->dev, "%s: NOP OUT failed %d\n", __func__, err);
4860 return err;
4861}
4862
b294ff3e
AD		 4863/**
4864 * ufshcd_setup_links - associate link b/w device wlun and other luns
4865 * @sdev: pointer to SCSI device
4866 * @hba: pointer to ufs hba
4867 */
4868static void ufshcd_setup_links(struct ufs_hba *hba, struct scsi_device *sdev)
4869{
4870 struct device_link *link;
4871
4872 /*
4873 * Device wlun is the supplier & rest of the luns are consumers.
4874 * This ensures that device wlun suspends after all other luns.
4875 */
e2106584 4876 if (hba->ufs_device_wlun) {
b294ff3e 4877 link = device_link_add(&sdev->sdev_gendev,
e2106584 4878 &hba->ufs_device_wlun->sdev_gendev,
b294ff3e
AD		 4879 DL_FLAG_PM_RUNTIME | DL_FLAG_RPM_ACTIVE);
4880 if (!link) {
4881 dev_err(&sdev->sdev_gendev, "Failed establishing link - %s\n",
e2106584 4882 dev_name(&hba->ufs_device_wlun->sdev_gendev));
b294ff3e
AD		 4883 return;
4884 }
4885 hba->luns_avail--;
4886 /* Ignore REPORT_LUN wlun probing */
4887 if (hba->luns_avail == 1) {
4888 ufshcd_rpm_put(hba);
4889 return;
4890 }
4891 } else {
4892 /*
4893 * Device wlun is probed. The assumption is that WLUNs are
4894 * scanned before other LUNs.
4895 */
4896 hba->luns_avail--;
4897 }
4898}
4899
dca899bc
BH		 4900/**
4901 * ufshcd_lu_init - Initialize the relevant parameters of the LU
4902 * @hba: per-adapter instance
4903 * @sdev: pointer to SCSI device
4904 */
4905static void ufshcd_lu_init(struct ufs_hba *hba, struct scsi_device *sdev)
4906{
f2a89b07 4907 int len = QUERY_DESC_MAX_SIZE;
dca899bc
BH		 4908 u8 lun = ufshcd_scsi_to_upiu_lun(sdev->lun);
4909 u8 lun_qdepth = hba->nutrs;
4910 u8 *desc_buf;
4911 int ret;
4912
4913 desc_buf = kzalloc(len, GFP_KERNEL);
4914 if (!desc_buf)
4915 goto set_qdepth;
4916
4917 ret = ufshcd_read_unit_desc_param(hba, lun, 0, desc_buf, len);
4918 if (ret < 0) {
4919 if (ret == -EOPNOTSUPP)
4920 /* If LU doesn't support unit descriptor, its queue depth is set to 1 */
4921 lun_qdepth = 1;
4922 kfree(desc_buf);
4923 goto set_qdepth;
4924 }
4925
4926 if (desc_buf[UNIT_DESC_PARAM_LU_Q_DEPTH]) {
4927 /*
4928 * In per-LU queueing architecture, bLUQueueDepth will not be 0, then we will
4929 * use the smaller between UFSHCI CAP.NUTRS and UFS LU bLUQueueDepth
4930 */
4931 lun_qdepth = min_t(int, desc_buf[UNIT_DESC_PARAM_LU_Q_DEPTH], hba->nutrs);
4932 }
4933 /*
4934 * According to UFS device specification, the write protection mode is only supported by
4935 * normal LU, not supported by WLUN.
4936 */
4937 if (hba->dev_info.f_power_on_wp_en && lun < hba->dev_info.max_lu_supported &&
4938 !hba->dev_info.is_lu_power_on_wp &&
4939 desc_buf[UNIT_DESC_PARAM_LU_WR_PROTECT] == UFS_LU_POWER_ON_WP)
4940 hba->dev_info.is_lu_power_on_wp = true;
4941
f6b9d0fe
BH		 4942 /* In case of RPMB LU, check if advanced RPMB mode is enabled */
4943 if (desc_buf[UNIT_DESC_PARAM_UNIT_INDEX] == UFS_UPIU_RPMB_WLUN &&
4944 desc_buf[RPMB_UNIT_DESC_PARAM_REGION_EN] & BIT(4))
4945 hba->dev_info.b_advanced_rpmb_en = true;
4946
4947
dca899bc
BH		 4948 kfree(desc_buf);
4949set_qdepth:
4950 /*
4951 * For WLUNs that don't support unit descriptor, queue depth is set to 1. For LUs whose
4952 * bLUQueueDepth == 0, the queue depth is set to a maximum value that host can queue.
4953 */
4954 dev_dbg(hba->dev, "Set LU %x queue depth %d\n", lun, lun_qdepth);
4955 scsi_change_queue_depth(sdev, lun_qdepth);
4956}
4957
7a3e97b0
SY		 4958/**
4959 * ufshcd_slave_alloc - handle initial SCSI device configurations
4960 * @sdev: pointer to SCSI device
4961 *
4962 * Returns success
4963 */
4964static int ufshcd_slave_alloc(struct scsi_device *sdev)
4965{
4966 struct ufs_hba *hba;
4967
4968 hba = shost_priv(sdev->host);
7a3e97b0
SY		 4969
4970 /* Mode sense(6) is not supported by UFS, so use Mode sense(10) */
4971 sdev->use_10_for_ms = 1;
a3a76391
CG		 4972
4973 /* DBD field should be set to 1 in mode sense(10) */
4974 sdev->set_dbd_for_ms = 1;
7a3e97b0 4975
e8e7f271
SRT		 4976 /* allow SCSI layer to restart the device in case of errors */
4977 sdev->allow_restart = 1;
4264fd61 4978
b2a6c522
SRT		 4979 /* REPORT SUPPORTED OPERATION CODES is not supported */
4980 sdev->no_report_opcodes = 1;
4981
84af7e8b
SRT		 4982 /* WRITE_SAME command is not supported */
4983 sdev->no_write_same = 1;
e8e7f271 4984
dca899bc 4985 ufshcd_lu_init(hba, sdev);
57d104c1 4986
b294ff3e
AD		 4987 ufshcd_setup_links(hba, sdev);
4988
7a3e97b0
SY		 4989 return 0;
4990}
4991
4264fd61
SRT		 4992/**
4993 * ufshcd_change_queue_depth - change queue depth
4994 * @sdev: pointer to SCSI device
4995 * @depth: required depth to set
4264fd61 4996 *
db5ed4df 4997 * Change queue depth and make sure the max. limits are not crossed.
4264fd61 4998 */
db5ed4df 4999static int ufshcd_change_queue_depth(struct scsi_device *sdev, int depth)
4264fd61 5000{
fc21da8a 5001 return scsi_change_queue_depth(sdev, min(depth, sdev->host->can_queue));
4264fd61
SRT		 5002}
5003
f02bc975
DP		 5004static void ufshcd_hpb_destroy(struct ufs_hba *hba, struct scsi_device *sdev)
5005{
5006 /* skip well-known LU */
41d8a933
DP		 5007 if ((sdev->lun >= UFS_UPIU_MAX_UNIT_NUM_ID) ||
5008 !(hba->dev_info.hpb_enabled) || !ufshpb_is_allowed(hba))
f02bc975
DP		 5009 return;
5010
5011 ufshpb_destroy_lu(hba, sdev);
5012}
5013
5014static void ufshcd_hpb_configure(struct ufs_hba *hba, struct scsi_device *sdev)
5015{
5016 /* skip well-known LU */
5017 if ((sdev->lun >= UFS_UPIU_MAX_UNIT_NUM_ID) ||
5018 !(hba->dev_info.hpb_enabled) || !ufshpb_is_allowed(hba))
5019 return;
5020
5021 ufshpb_init_hpb_lu(hba, sdev);
5022}
5023
eeda4749
AM		 5024/**
5025 * ufshcd_slave_configure - adjust SCSI device configurations
5026 * @sdev: pointer to SCSI device
5027 */
5028static int ufshcd_slave_configure(struct scsi_device *sdev)
5029{
49615ba1 5030 struct ufs_hba *hba = shost_priv(sdev->host);
eeda4749
AM		 5031 struct request_queue *q = sdev->request_queue;
5032
f02bc975
DP		 5033 ufshcd_hpb_configure(hba, sdev);
5034
eeda4749 5035 blk_queue_update_dma_pad(q, PRDT_DATA_BYTE_COUNT_PAD - 1);
2b2bfc8a
KK		 5036 if (hba->quirks & UFSHCD_QUIRK_ALIGN_SG_WITH_PAGE_SIZE)
5037 blk_queue_update_dma_alignment(q, PAGE_SIZE - 1);
b294ff3e
AD		 5038 /*
5039 * Block runtime-pm until all consumers are added.
5040 * Refer ufshcd_setup_links().
5041 */
5042 if (is_device_wlun(sdev))
5043 pm_runtime_get_noresume(&sdev->sdev_gendev);
5044 else if (ufshcd_is_rpm_autosuspend_allowed(hba))
49615ba1 5045 sdev->rpm_autosuspend = 1;
71bb9ab6
AH		 5046 /*
5047 * Do not print messages during runtime PM to avoid never-ending cycles
5048 * of messages written back to storage by user space causing runtime
5049 * resume, causing more messages and so on.
5050 */
5051 sdev->silence_suspend = 1;
49615ba1 5052
cb77cb5a 5053 ufshcd_crypto_register(hba, q);
df043c74 5054
eeda4749
AM		 5055 return 0;
5056}
5057
7a3e97b0
SY		 5058/**
5059 * ufshcd_slave_destroy - remove SCSI device configurations
5060 * @sdev: pointer to SCSI device
5061 */
5062static void ufshcd_slave_destroy(struct scsi_device *sdev)
5063{
5064 struct ufs_hba *hba;
bf25967a 5065 unsigned long flags;
7a3e97b0
SY		 5066
5067 hba = shost_priv(sdev->host);
f02bc975
DP		 5068
5069 ufshcd_hpb_destroy(hba, sdev);
5070
0ce147d4 5071 /* Drop the reference as it won't be needed anymore */
7c48bfd0 5072 if (ufshcd_scsi_to_upiu_lun(sdev->lun) == UFS_UPIU_UFS_DEVICE_WLUN) {
7c48bfd0 5073 spin_lock_irqsave(hba->host->host_lock, flags);
e2106584 5074 hba->ufs_device_wlun = NULL;
7c48bfd0 5075 spin_unlock_irqrestore(hba->host->host_lock, flags);
e2106584 5076 } else if (hba->ufs_device_wlun) {
bf25967a
AH		 5077 struct device *supplier = NULL;
5078
5079 /* Ensure UFS Device WLUN exists and does not disappear */
5080 spin_lock_irqsave(hba->host->host_lock, flags);
e2106584
BVA		 5081 if (hba->ufs_device_wlun) {
5082 supplier = &hba->ufs_device_wlun->sdev_gendev;
bf25967a
AH		 5083 get_device(supplier);
5084 }
5085 spin_unlock_irqrestore(hba->host->host_lock, flags);
5086
5087 if (supplier) {
5088 /*
5089 * If a LUN fails to probe (e.g. absent BOOT WLUN), the
5090 * device will not have been registered but can still
5091 * have a device link holding a reference to the device.
5092 */
5093 device_link_remove(&sdev->sdev_gendev, supplier);
5094 put_device(supplier);
5095 }
7c48bfd0 5096 }
7a3e97b0
SY		 5097}
5098
7a3e97b0
SY		 5099/**
5100 * ufshcd_scsi_cmd_status - Update SCSI command result based on SCSI status
8aa29f19 5101 * @lrbp: pointer to local reference block of completed command
7a3e97b0
SY		 5102 * @scsi_status: SCSI command status
5103 *
5104 * Returns value base on SCSI command status
5105 */
5106static inline int
5107ufshcd_scsi_cmd_status(struct ufshcd_lrb *lrbp, int scsi_status)
5108{
5109 int result = 0;
5110
5111 switch (scsi_status) {
7a3e97b0 5112 case SAM_STAT_CHECK_CONDITION:
1c2623c5 5113 ufshcd_copy_sense_data(lrbp);
df561f66 5114 fallthrough;
1c2623c5 5115 case SAM_STAT_GOOD:
db83d8a5 5116 result |= DID_OK << 16 | scsi_status;
7a3e97b0
SY		 5117 break;
5118 case SAM_STAT_TASK_SET_FULL:
1c2623c5 5119 case SAM_STAT_BUSY:
7a3e97b0 5120 case SAM_STAT_TASK_ABORTED:
1c2623c5
SJ		 5121 ufshcd_copy_sense_data(lrbp);
5122 result |= scsi_status;
7a3e97b0
SY		 5123 break;
5124 default:
5125 result |= DID_ERROR << 16;
5126 break;
5127 } /* end of switch */
5128
5129 return result;
5130}
5131
5132/**
5133 * ufshcd_transfer_rsp_status - Get overall status of the response
5134 * @hba: per adapter instance
8aa29f19 5135 * @lrbp: pointer to local reference block of completed command
7a3e97b0
SY		 5136 *
5137 * Returns result of the command to notify SCSI midlayer
5138 */
5139static inline int
5140ufshcd_transfer_rsp_status(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
5141{
5142 int result = 0;
5143 int scsi_status;
957d63e7 5144 enum utp_ocs ocs;
7a3e97b0
SY		 5145
5146 /* overall command status of utrd */
5147 ocs = ufshcd_get_tr_ocs(lrbp);
5148
d779a6e9
KK		 5149 if (hba->quirks & UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR) {
5150 if (be32_to_cpu(lrbp->ucd_rsp_ptr->header.dword_1) &
5151 MASK_RSP_UPIU_RESULT)
5152 ocs = OCS_SUCCESS;
5153 }
5154
7a3e97b0
SY		 5155 switch (ocs) {
5156 case OCS_SUCCESS:
5a0b0cb9 5157 result = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr);
ff8e20c6 5158 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0);
5a0b0cb9
SRT		 5159 switch (result) {
5160 case UPIU_TRANSACTION_RESPONSE:
5161 /*
5162 * get the response UPIU result to extract
5163 * the SCSI command status
5164 */
5165 result = ufshcd_get_rsp_upiu_result(lrbp->ucd_rsp_ptr);
5166
5167 /*
5168 * get the result based on SCSI status response
5169 * to notify the SCSI midlayer of the command status
5170 */
5171 scsi_status = result & MASK_SCSI_STATUS;
5172 result = ufshcd_scsi_cmd_status(lrbp, scsi_status);
66ec6d59 5173
f05ac2e5
YG		 5174 /*
5175 * Currently we are only supporting BKOPs exception
5176 * events hence we can ignore BKOPs exception event
5177 * during power management callbacks. BKOPs exception
5178 * event is not expected to be raised in runtime suspend
5179 * callback as it allows the urgent bkops.
5180 * During system suspend, we are anyway forcefully
5181 * disabling the bkops and if urgent bkops is needed
5182 * it will be enabled on system resume. Long term
5183 * solution could be to abort the system suspend if
5184 * UFS device needs urgent BKOPs.
5185 */
5186 if (!hba->pm_op_in_progress &&
aa53f580 5187 !ufshcd_eh_in_progress(hba) &&
b294ff3e
AD		 5188 ufshcd_is_exception_event(lrbp->ucd_rsp_ptr))
5189 /* Flushed in suspend */
5190 schedule_work(&hba->eeh_work);
4b5f4907
DP		 5191
5192 if (scsi_status == SAM_STAT_GOOD)
5193 ufshpb_rsp_upiu(hba, lrbp);
5a0b0cb9
SRT		 5194 break;
5195 case UPIU_TRANSACTION_REJECT_UPIU:
5196 /* TODO: handle Reject UPIU Response */
5197 result = DID_ERROR << 16;
3b1d0580 5198 dev_err(hba->dev,
5a0b0cb9
SRT		 5199 "Reject UPIU not fully implemented\n");
5200 break;
5201 default:
5a0b0cb9
SRT		 5202 dev_err(hba->dev,
5203 "Unexpected request response code = %x\n",
5204 result);
e0347d89 5205 result = DID_ERROR << 16;
7a3e97b0
SY		 5206 break;
5207 }
7a3e97b0
SY		 5208 break;
5209 case OCS_ABORTED:
5210 result |= DID_ABORT << 16;
5211 break;
e8e7f271
SRT		 5212 case OCS_INVALID_COMMAND_STATUS:
5213 result |= DID_REQUEUE << 16;
5214 break;
7a3e97b0
SY		 5215 case OCS_INVALID_CMD_TABLE_ATTR:
5216 case OCS_INVALID_PRDT_ATTR:
5217 case OCS_MISMATCH_DATA_BUF_SIZE:
5218 case OCS_MISMATCH_RESP_UPIU_SIZE:
5219 case OCS_PEER_COMM_FAILURE:
5220 case OCS_FATAL_ERROR:
5e7341e1
ST		 5221 case OCS_DEVICE_FATAL_ERROR:
5222 case OCS_INVALID_CRYPTO_CONFIG:
5223 case OCS_GENERAL_CRYPTO_ERROR:
7a3e97b0
SY		 5224 default:
5225 result |= DID_ERROR << 16;
3b1d0580 5226 dev_err(hba->dev,
ff8e20c6
DR		 5227 "OCS error from controller = %x for tag %d\n",
5228 ocs, lrbp->task_tag);
e965e5e0 5229 ufshcd_print_evt_hist(hba);
6ba65588 5230 ufshcd_print_host_state(hba);
7a3e97b0
SY		 5231 break;
5232 } /* end of switch */
5233
eeb1b55b
JK		 5234 if ((host_byte(result) != DID_OK) &&
5235 (host_byte(result) != DID_REQUEUE) && !hba->silence_err_logs)
66cc820f 5236 ufshcd_print_trs(hba, 1 << lrbp->task_tag, true);
7a3e97b0
SY		 5237 return result;
5238}
5239
a45f9371
CG		 5240static bool ufshcd_is_auto_hibern8_error(struct ufs_hba *hba,
5241 u32 intr_mask)
5242{
5243 if (!ufshcd_is_auto_hibern8_supported(hba) ||
5244 !ufshcd_is_auto_hibern8_enabled(hba))
5245 return false;
5246
5247 if (!(intr_mask & UFSHCD_UIC_HIBERN8_MASK))
5248 return false;
5249
5250 if (hba->active_uic_cmd &&
5251 (hba->active_uic_cmd->command == UIC_CMD_DME_HIBER_ENTER ||
5252 hba->active_uic_cmd->command == UIC_CMD_DME_HIBER_EXIT))
5253 return false;
5254
5255 return true;
5256}
5257
6ccf44fe
SJ		 5258/**
5259 * ufshcd_uic_cmd_compl - handle completion of uic command
5260 * @hba: per adapter instance
53b3d9c3 5261 * @intr_status: interrupt status generated by the controller
9333d775
VG		 5262 *
5263 * Returns
5264 * IRQ_HANDLED - If interrupt is valid
5265 * IRQ_NONE - If invalid interrupt
6ccf44fe 5266 */
9333d775 5267static irqreturn_t ufshcd_uic_cmd_compl(struct ufs_hba *hba, u32 intr_status)
6ccf44fe 5268{
9333d775
VG		 5269 irqreturn_t retval = IRQ_NONE;
5270
a45f9371
CG		 5271 spin_lock(hba->host->host_lock);
5272 if (ufshcd_is_auto_hibern8_error(hba, intr_status))
5273 hba->errors |= (UFSHCD_UIC_HIBERN8_MASK & intr_status);
5274
53b3d9c3 5275 if ((intr_status & UIC_COMMAND_COMPL) && hba->active_uic_cmd) {
6ccf44fe
SJ		 5276 hba->active_uic_cmd->argument2 |=
5277 ufshcd_get_uic_cmd_result(hba);
12b4fdb4
SJ		 5278 hba->active_uic_cmd->argument3 =
5279 ufshcd_get_dme_attr_val(hba);
0f52fcb9
CG		 5280 if (!hba->uic_async_done)
5281 hba->active_uic_cmd->cmd_active = 0;
6ccf44fe 5282 complete(&hba->active_uic_cmd->done);
9333d775 5283 retval = IRQ_HANDLED;
6ccf44fe 5284 }
53b3d9c3 5285
9333d775 5286 if ((intr_status & UFSHCD_UIC_PWR_MASK) && hba->uic_async_done) {
0f52fcb9 5287 hba->active_uic_cmd->cmd_active = 0;
57d104c1 5288 complete(hba->uic_async_done);
9333d775
VG		 5289 retval = IRQ_HANDLED;
5290 }
aa5c6979
SC		 5291
5292 if (retval == IRQ_HANDLED)
5293 ufshcd_add_uic_command_trace(hba, hba->active_uic_cmd,
28fa68fc 5294 UFS_CMD_COMP);
a45f9371 5295 spin_unlock(hba->host->host_lock);
9333d775 5296 return retval;
6ccf44fe
SJ		 5297}
5298
6f8dafde
BVA		 5299/* Release the resources allocated for processing a SCSI command. */
5300static void ufshcd_release_scsi_cmd(struct ufs_hba *hba,
5301 struct ufshcd_lrb *lrbp)
5302{
5303 struct scsi_cmnd *cmd = lrbp->cmd;
5304
5305 scsi_dma_unmap(cmd);
5306 lrbp->cmd = NULL; /* Mark the command as completed. */
5307 ufshcd_release(hba);
5308 ufshcd_clk_scaling_update_busy(hba);
5309}
5310
7a3e97b0 5311/**
9a47ec7c 5312 * __ufshcd_transfer_req_compl - handle SCSI and query command completion
7a3e97b0 5313 * @hba: per adapter instance
73dc3c4a 5314 * @completed_reqs: bitmask that indicates which requests to complete
7a3e97b0 5315 */
9a47ec7c 5316static void __ufshcd_transfer_req_compl(struct ufs_hba *hba,
11682523 5317 unsigned long completed_reqs)
7a3e97b0 5318{
5a0b0cb9
SRT		 5319 struct ufshcd_lrb *lrbp;
5320 struct scsi_cmnd *cmd;
7a3e97b0 5321 int index;
e9d501b1 5322
e9d501b1
DR		 5323 for_each_set_bit(index, &completed_reqs, hba->nutrs) {
5324 lrbp = &hba->lrb[index];
a3170376 5325 lrbp->compl_time_stamp = ktime_get();
0f85e747 5326 lrbp->compl_time_stamp_local_clock = local_clock();
e9d501b1
DR		 5327 cmd = lrbp->cmd;
5328 if (cmd) {
1d8613a2
CG		 5329 if (unlikely(ufshcd_should_inform_monitor(hba, lrbp)))
5330 ufshcd_update_monitor(hba, lrbp);
28fa68fc 5331 ufshcd_add_command_trace(hba, index, UFS_CMD_COMP);
6f8dafde
BVA		 5332 cmd->result = ufshcd_transfer_rsp_status(hba, lrbp);
5333 ufshcd_release_scsi_cmd(hba, lrbp);
e9d501b1 5334 /* Do not touch lrbp after scsi done */
35c3730a 5335 scsi_done(cmd);
300bb13f
JP		 5336 } else if (lrbp->command_type == UTP_CMD_TYPE_DEV_MANAGE ||
5337 lrbp->command_type == UTP_CMD_TYPE_UFS_STORAGE) {
1a07f2d9
LS		 5338 if (hba->dev_cmd.complete) {
5339 ufshcd_add_command_trace(hba, index,
28fa68fc 5340 UFS_DEV_COMP);
e9d501b1 5341 complete(hba->dev_cmd.complete);
3eb9dcc0 5342 ufshcd_clk_scaling_update_busy(hba);
1a07f2d9 5343 }
e9d501b1
DR		 5344 }
5345 }
7a3e97b0
SY		 5346}
5347
ee8c88ca
BVA		 5348/* Any value that is not an existing queue number is fine for this constant. */
5349enum {
5350 UFSHCD_POLL_FROM_INTERRUPT_CONTEXT = -1
5351};
5352
5353static void ufshcd_clear_polled(struct ufs_hba *hba,
5354 unsigned long *completed_reqs)
5355{
5356 int tag;
5357
5358 for_each_set_bit(tag, completed_reqs, hba->nutrs) {
5359 struct scsi_cmnd *cmd = hba->lrb[tag].cmd;
5360
5361 if (!cmd)
5362 continue;
5363 if (scsi_cmd_to_rq(cmd)->cmd_flags & REQ_POLLED)
5364 __clear_bit(tag, completed_reqs);
5365 }
5366}
5367
eaab9b57
BVA		 5368/*
5369 * Returns > 0 if one or more commands have been completed or 0 if no
5370 * requests have been completed.
5371 */
5372static int ufshcd_poll(struct Scsi_Host *shost, unsigned int queue_num)
5373{
5374 struct ufs_hba *hba = shost_priv(shost);
5375 unsigned long completed_reqs, flags;
5376 u32 tr_doorbell;
5377
5378 spin_lock_irqsave(&hba->outstanding_lock, flags);
5379 tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
5380 completed_reqs = ~tr_doorbell & hba->outstanding_reqs;
5381 WARN_ONCE(completed_reqs & ~hba->outstanding_reqs,
5382 "completed: %#lx; outstanding: %#lx\n", completed_reqs,
5383 hba->outstanding_reqs);
ee8c88ca
BVA		 5384 if (queue_num == UFSHCD_POLL_FROM_INTERRUPT_CONTEXT) {
5385 /* Do not complete polled requests from interrupt context. */
5386 ufshcd_clear_polled(hba, &completed_reqs);
5387 }
eaab9b57
BVA		 5388 hba->outstanding_reqs &= ~completed_reqs;
5389 spin_unlock_irqrestore(&hba->outstanding_lock, flags);
5390
5391 if (completed_reqs)
5392 __ufshcd_transfer_req_compl(hba, completed_reqs);
5393
ee8c88ca 5394 return completed_reqs != 0;
eaab9b57
BVA		 5395}
5396
9a47ec7c 5397/**
1f522c50 5398 * ufshcd_transfer_req_compl - handle SCSI and query command completion
9a47ec7c 5399 * @hba: per adapter instance
9333d775
VG		 5400 *
5401 * Returns
5402 * IRQ_HANDLED - If interrupt is valid
5403 * IRQ_NONE - If invalid interrupt
9a47ec7c 5404 */
11682523 5405static irqreturn_t ufshcd_transfer_req_compl(struct ufs_hba *hba)
9a47ec7c 5406{
9a47ec7c
YG		 5407 /* Resetting interrupt aggregation counters first and reading the
5408 * DOOR_BELL afterward allows us to handle all the completed requests.
5409 * In order to prevent other interrupts starvation the DB is read once
5410 * after reset. The down side of this solution is the possibility of
5411 * false interrupt if device completes another request after resetting
5412 * aggregation and before reading the DB.
5413 */
b638b5eb
AA		 5414 if (ufshcd_is_intr_aggr_allowed(hba) &&
5415 !(hba->quirks & UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR))
9a47ec7c
YG		 5416 ufshcd_reset_intr_aggr(hba);
5417
c11a1ae9
BVA		 5418 if (ufs_fail_completion())
5419 return IRQ_HANDLED;
5420
eaab9b57
BVA		 5421 /*
5422 * Ignore the ufshcd_poll() return value and return IRQ_HANDLED since we
5423 * do not want polling to trigger spurious interrupt complaints.
5424 */
ee8c88ca 5425 ufshcd_poll(hba->host, UFSHCD_POLL_FROM_INTERRUPT_CONTEXT);
9a47ec7c 5426
eaab9b57 5427 return IRQ_HANDLED;
9a47ec7c
YG		 5428}
5429
7deedfda 5430int __ufshcd_write_ee_control(struct ufs_hba *hba, u32 ee_ctrl_mask)
cd469475
AH		 5431{
5432 return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
5433 QUERY_ATTR_IDN_EE_CONTROL, 0, 0,
5434 &ee_ctrl_mask);
5435}
5436
7deedfda 5437int ufshcd_write_ee_control(struct ufs_hba *hba)
cd469475
AH		 5438{
5439 int err;
5440
5441 mutex_lock(&hba->ee_ctrl_mutex);
5442 err = __ufshcd_write_ee_control(hba, hba->ee_ctrl_mask);
5443 mutex_unlock(&hba->ee_ctrl_mutex);
5444 if (err)
5445 dev_err(hba->dev, "%s: failed to write ee control %d\n",
5446 __func__, err);
5447 return err;
5448}
5449
35d11ec2
KK		 5450int ufshcd_update_ee_control(struct ufs_hba *hba, u16 *mask,
5451 const u16 *other_mask, u16 set, u16 clr)
cd469475
AH		 5452{
5453 u16 new_mask, ee_ctrl_mask;
5454 int err = 0;
5455
5456 mutex_lock(&hba->ee_ctrl_mutex);
5457 new_mask = (*mask & ~clr) | set;
5458 ee_ctrl_mask = new_mask | *other_mask;
5459 if (ee_ctrl_mask != hba->ee_ctrl_mask)
5460 err = __ufshcd_write_ee_control(hba, ee_ctrl_mask);
5461 /* Still need to update 'mask' even if 'ee_ctrl_mask' was unchanged */
5462 if (!err) {
5463 hba->ee_ctrl_mask = ee_ctrl_mask;
5464 *mask = new_mask;
5465 }
5466 mutex_unlock(&hba->ee_ctrl_mutex);
5467 return err;
5468}
5469
66ec6d59
SRT		 5470/**
5471 * ufshcd_disable_ee - disable exception event
5472 * @hba: per-adapter instance
5473 * @mask: exception event to disable
5474 *
5475 * Disables exception event in the device so that the EVENT_ALERT
5476 * bit is not set.
5477 *
5478 * Returns zero on success, non-zero error value on failure.
5479 */
cd469475 5480static inline int ufshcd_disable_ee(struct ufs_hba *hba, u16 mask)
66ec6d59 5481{
cd469475 5482 return ufshcd_update_ee_drv_mask(hba, 0, mask);
66ec6d59
SRT		 5483}
5484
5485/**
5486 * ufshcd_enable_ee - enable exception event
5487 * @hba: per-adapter instance
5488 * @mask: exception event to enable
5489 *
5490 * Enable corresponding exception event in the device to allow
5491 * device to alert host in critical scenarios.
5492 *
5493 * Returns zero on success, non-zero error value on failure.
5494 */
cd469475 5495static inline int ufshcd_enable_ee(struct ufs_hba *hba, u16 mask)
66ec6d59 5496{
cd469475 5497 return ufshcd_update_ee_drv_mask(hba, mask, 0);
66ec6d59
SRT		 5498}
5499
5500/**
5501 * ufshcd_enable_auto_bkops - Allow device managed BKOPS
5502 * @hba: per-adapter instance
5503 *
5504 * Allow device to manage background operations on its own. Enabling
5505 * this might lead to inconsistent latencies during normal data transfers
5506 * as the device is allowed to manage its own way of handling background
5507 * operations.
5508 *
5509 * Returns zero on success, non-zero on failure.
5510 */
5511static int ufshcd_enable_auto_bkops(struct ufs_hba *hba)
5512{
5513 int err = 0;
5514
5515 if (hba->auto_bkops_enabled)
5516 goto out;
5517
dc3c8d3a 5518 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG,
1f34eedf 5519 QUERY_FLAG_IDN_BKOPS_EN, 0, NULL);
66ec6d59
SRT		 5520 if (err) {
5521 dev_err(hba->dev, "%s: failed to enable bkops %d\n",
5522 __func__, err);
5523 goto out;
5524 }
5525
5526 hba->auto_bkops_enabled = true;
7ff5ab47 5527 trace_ufshcd_auto_bkops_state(dev_name(hba->dev), "Enabled");
66ec6d59
SRT		 5528
5529 /* No need of URGENT_BKOPS exception from the device */
5530 err = ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS);
5531 if (err)
5532 dev_err(hba->dev, "%s: failed to disable exception event %d\n",
5533 __func__, err);
5534out:
5535 return err;
5536}
5537
5538/**
5539 * ufshcd_disable_auto_bkops - block device in doing background operations
5540 * @hba: per-adapter instance
5541 *
5542 * Disabling background operations improves command response latency but
5543 * has drawback of device moving into critical state where the device is
5544 * not-operable. Make sure to call ufshcd_enable_auto_bkops() whenever the
5545 * host is idle so that BKOPS are managed effectively without any negative
5546 * impacts.
5547 *
5548 * Returns zero on success, non-zero on failure.
5549 */
5550static int ufshcd_disable_auto_bkops(struct ufs_hba *hba)
5551{
5552 int err = 0;
5553
5554 if (!hba->auto_bkops_enabled)
5555 goto out;
5556
5557 /*
5558 * If host assisted BKOPs is to be enabled, make sure
5559 * urgent bkops exception is allowed.
5560 */
5561 err = ufshcd_enable_ee(hba, MASK_EE_URGENT_BKOPS);
5562 if (err) {
5563 dev_err(hba->dev, "%s: failed to enable exception event %d\n",
5564 __func__, err);
5565 goto out;
5566 }
5567
dc3c8d3a 5568 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_CLEAR_FLAG,
1f34eedf 5569 QUERY_FLAG_IDN_BKOPS_EN, 0, NULL);
66ec6d59
SRT		 5570 if (err) {
5571 dev_err(hba->dev, "%s: failed to disable bkops %d\n",
5572 __func__, err);
5573 ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS);
5574 goto out;
5575 }
5576
5577 hba->auto_bkops_enabled = false;
7ff5ab47 5578 trace_ufshcd_auto_bkops_state(dev_name(hba->dev), "Disabled");
24366c2a 5579 hba->is_urgent_bkops_lvl_checked = false;
66ec6d59
SRT		 5580out:
5581 return err;
5582}
5583
5584/**
4e768e76 5585 * ufshcd_force_reset_auto_bkops - force reset auto bkops state
66ec6d59
SRT		 5586 * @hba: per adapter instance
5587 *
5588 * After a device reset the device may toggle the BKOPS_EN flag
5589 * to default value. The s/w tracking variables should be updated
4e768e76 5590 * as well. This function would change the auto-bkops state based on
5591 * UFSHCD_CAP_KEEP_AUTO_BKOPS_ENABLED_EXCEPT_SUSPEND.
66ec6d59 5592 */
4e768e76 5593static void ufshcd_force_reset_auto_bkops(struct ufs_hba *hba)
66ec6d59 5594{
4e768e76 5595 if (ufshcd_keep_autobkops_enabled_except_suspend(hba)) {
5596 hba->auto_bkops_enabled = false;
5597 hba->ee_ctrl_mask |= MASK_EE_URGENT_BKOPS;
5598 ufshcd_enable_auto_bkops(hba);
5599 } else {
5600 hba->auto_bkops_enabled = true;
5601 hba->ee_ctrl_mask &= ~MASK_EE_URGENT_BKOPS;
5602 ufshcd_disable_auto_bkops(hba);
5603 }
7b6668d8 5604 hba->urgent_bkops_lvl = BKOPS_STATUS_PERF_IMPACT;
24366c2a 5605 hba->is_urgent_bkops_lvl_checked = false;
66ec6d59
SRT		 5606}
5607
5608static inline int ufshcd_get_bkops_status(struct ufs_hba *hba, u32 *status)
5609{
5e86ae44 5610 return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
66ec6d59
SRT		 5611 QUERY_ATTR_IDN_BKOPS_STATUS, 0, 0, status);
5612}
5613
5614/**
57d104c1 5615 * ufshcd_bkops_ctrl - control the auto bkops based on current bkops status
66ec6d59 5616 * @hba: per-adapter instance
57d104c1 5617 * @status: bkops_status value
66ec6d59 5618 *
57d104c1
SJ		 5619 * Read the bkops_status from the UFS device and Enable fBackgroundOpsEn
5620 * flag in the device to permit background operations if the device
5621 * bkops_status is greater than or equal to "status" argument passed to
5622 * this function, disable otherwise.
5623 *
5624 * Returns 0 for success, non-zero in case of failure.
5625 *
5626 * NOTE: Caller of this function can check the "hba->auto_bkops_enabled" flag
5627 * to know whether auto bkops is enabled or disabled after this function
5628 * returns control to it.
66ec6d59 5629 */
57d104c1
SJ		 5630static int ufshcd_bkops_ctrl(struct ufs_hba *hba,
5631 enum bkops_status status)
66ec6d59
SRT		 5632{
5633 int err;
57d104c1 5634 u32 curr_status = 0;
66ec6d59 5635
57d104c1 5636 err = ufshcd_get_bkops_status(hba, &curr_status);
66ec6d59
SRT		 5637 if (err) {
5638 dev_err(hba->dev, "%s: failed to get BKOPS status %d\n",
5639 __func__, err);
5640 goto out;
57d104c1
SJ		 5641 } else if (curr_status > BKOPS_STATUS_MAX) {
5642 dev_err(hba->dev, "%s: invalid BKOPS status %d\n",
5643 __func__, curr_status);
5644 err = -EINVAL;
5645 goto out;
66ec6d59
SRT		 5646 }
5647
57d104c1 5648 if (curr_status >= status)
66ec6d59 5649 err = ufshcd_enable_auto_bkops(hba);
57d104c1
SJ		 5650 else
5651 err = ufshcd_disable_auto_bkops(hba);
66ec6d59
SRT		 5652out:
5653 return err;
5654}
5655
57d104c1
SJ		 5656/**
5657 * ufshcd_urgent_bkops - handle urgent bkops exception event
5658 * @hba: per-adapter instance
5659 *
5660 * Enable fBackgroundOpsEn flag in the device to permit background
5661 * operations.
5662 *
5663 * If BKOPs is enabled, this function returns 0, 1 if the bkops in not enabled
5664 * and negative error value for any other failure.
5665 */
5666static int ufshcd_urgent_bkops(struct ufs_hba *hba)
5667{
afdfff59 5668 return ufshcd_bkops_ctrl(hba, hba->urgent_bkops_lvl);
57d104c1
SJ		 5669}
5670
66ec6d59
SRT		 5671static inline int ufshcd_get_ee_status(struct ufs_hba *hba, u32 *status)
5672{
5e86ae44 5673 return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
66ec6d59
SRT		 5674 QUERY_ATTR_IDN_EE_STATUS, 0, 0, status);
5675}
5676
afdfff59
YG		 5677static void ufshcd_bkops_exception_event_handler(struct ufs_hba *hba)
5678{
5679 int err;
5680 u32 curr_status = 0;
5681
5682 if (hba->is_urgent_bkops_lvl_checked)
5683 goto enable_auto_bkops;
5684
5685 err = ufshcd_get_bkops_status(hba, &curr_status);
5686 if (err) {
5687 dev_err(hba->dev, "%s: failed to get BKOPS status %d\n",
5688 __func__, err);
5689 goto out;
5690 }
5691
5692 /*
5693 * We are seeing that some devices are raising the urgent bkops
5694 * exception events even when BKOPS status doesn't indicate performace
5695 * impacted or critical. Handle these device by determining their urgent
5696 * bkops status at runtime.
5697 */
5698 if (curr_status < BKOPS_STATUS_PERF_IMPACT) {
5699 dev_err(hba->dev, "%s: device raised urgent BKOPS exception for bkops status %d\n",
5700 __func__, curr_status);
5701 /* update the current status as the urgent bkops level */
5702 hba->urgent_bkops_lvl = curr_status;
5703 hba->is_urgent_bkops_lvl_checked = true;
5704 }
5705
5706enable_auto_bkops:
5707 err = ufshcd_enable_auto_bkops(hba);
5708out:
5709 if (err < 0)
5710 dev_err(hba->dev, "%s: failed to handle urgent bkops %d\n",
5711 __func__, err);
5712}
5713
322c4b29
AA		 5714static void ufshcd_temp_exception_event_handler(struct ufs_hba *hba, u16 status)
5715{
5716 u32 value;
5717
5718 if (ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
5719 QUERY_ATTR_IDN_CASE_ROUGH_TEMP, 0, 0, &value))
5720 return;
5721
5722 dev_info(hba->dev, "exception Tcase %d\n", value - 80);
5723
5724 ufs_hwmon_notify_event(hba, status & MASK_EE_URGENT_TEMP);
5725
5726 /*
5727 * A placeholder for the platform vendors to add whatever additional
5728 * steps required
5729 */
5730}
5731
3b5f3c0d 5732static int __ufshcd_wb_toggle(struct ufs_hba *hba, bool set, enum flag_idn idn)
3d17b9b5 5733{
6f8d5a6a 5734 u8 index;
3b5f3c0d
YH		 5735 enum query_opcode opcode = set ? UPIU_QUERY_OPCODE_SET_FLAG :
5736 UPIU_QUERY_OPCODE_CLEAR_FLAG;
5737
5738 index = ufshcd_wb_get_query_index(hba);
5739 return ufshcd_query_flag_retry(hba, opcode, idn, index, NULL);
5740}
5741
5742int ufshcd_wb_toggle(struct ufs_hba *hba, bool enable)
5743{
5744 int ret;
3d17b9b5 5745
f8dc7a31
JC		 5746 if (!ufshcd_is_wb_allowed(hba) ||
5747 hba->dev_info.wb_enabled == enable)
3d17b9b5 5748 return 0;
3d17b9b5 5749
3b5f3c0d 5750 ret = __ufshcd_wb_toggle(hba, enable, QUERY_FLAG_IDN_WB_EN);
3d17b9b5 5751 if (ret) {
4f6b69f3
JC		 5752 dev_err(hba->dev, "%s: Write Booster %s failed %d\n",
5753 __func__, enable ? "enabling" : "disabling", ret);
3d17b9b5
AD		 5754 return ret;
5755 }
5756
4cd48995 5757 hba->dev_info.wb_enabled = enable;
4f6b69f3 5758 dev_dbg(hba->dev, "%s: Write Booster %s\n",
3b5f3c0d 5759 __func__, enable ? "enabled" : "disabled");
3d17b9b5
AD		 5760
5761 return ret;
5762}
5763
4450a165
JC		 5764static void ufshcd_wb_toggle_buf_flush_during_h8(struct ufs_hba *hba,
5765 bool enable)
3d17b9b5 5766{
3b5f3c0d 5767 int ret;
3d17b9b5 5768
4450a165 5769 ret = __ufshcd_wb_toggle(hba, enable,
3b5f3c0d
YH		 5770 QUERY_FLAG_IDN_WB_BUFF_FLUSH_DURING_HIBERN8);
5771 if (ret) {
4f6b69f3
JC		 5772 dev_err(hba->dev, "%s: WB-Buf Flush during H8 %s failed %d\n",
5773 __func__, enable ? "enabling" : "disabling", ret);
3b5f3c0d
YH		 5774 return;
5775 }
4f6b69f3 5776 dev_dbg(hba->dev, "%s: WB-Buf Flush during H8 %s\n",
4450a165 5777 __func__, enable ? "enabled" : "disabled");
3d17b9b5
AD		 5778}
5779
6c4148ce 5780int ufshcd_wb_toggle_buf_flush(struct ufs_hba *hba, bool enable)
3d17b9b5
AD		 5781{
5782 int ret;
5783
d3ba622d
BH		 5784 if (!ufshcd_is_wb_allowed(hba) ||
5785 hba->dev_info.wb_buf_flush_enabled == enable)
6c4148ce 5786 return 0;
3d17b9b5 5787
3b5f3c0d 5788 ret = __ufshcd_wb_toggle(hba, enable, QUERY_FLAG_IDN_WB_BUFF_FLUSH_EN);
3d17b9b5 5789 if (ret) {
4f6b69f3
JC		 5790 dev_err(hba->dev, "%s: WB-Buf Flush %s failed %d\n",
5791 __func__, enable ? "enabling" : "disabling", ret);
6c4148ce 5792 return ret;
3d17b9b5
AD		 5793 }
5794
d3ba622d 5795 hba->dev_info.wb_buf_flush_enabled = enable;
4f6b69f3 5796 dev_dbg(hba->dev, "%s: WB-Buf Flush %s\n",
3b5f3c0d 5797 __func__, enable ? "enabled" : "disabled");
6c4148ce
JC		 5798
5799 return ret;
3d17b9b5
AD		 5800}
5801
5802static bool ufshcd_wb_presrv_usrspc_keep_vcc_on(struct ufs_hba *hba,
5803 u32 avail_buf)
5804{
5805 u32 cur_buf;
5806 int ret;
e31011ab 5807 u8 index;
3d17b9b5 5808
e31011ab 5809 index = ufshcd_wb_get_query_index(hba);
3d17b9b5
AD		 5810 ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
5811 QUERY_ATTR_IDN_CURR_WB_BUFF_SIZE,
e31011ab 5812 index, 0, &cur_buf);
3d17b9b5 5813 if (ret) {
4f6b69f3 5814 dev_err(hba->dev, "%s: dCurWriteBoosterBufferSize read failed %d\n",
3d17b9b5
AD		 5815 __func__, ret);
5816 return false;
5817 }
5818
5819 if (!cur_buf) {
5820 dev_info(hba->dev, "dCurWBBuf: %d WB disabled until free-space is available\n",
5821 cur_buf);
5822 return false;
5823 }
d14734ae 5824 /* Let it continue to flush when available buffer exceeds threshold */
a858af9a 5825 return avail_buf < hba->vps->wb_flush_threshold;
3d17b9b5
AD		 5826}
5827
f681d107
JC		 5828static void ufshcd_wb_force_disable(struct ufs_hba *hba)
5829{
42f8c5cd 5830 if (ufshcd_is_wb_buf_flush_allowed(hba))
4450a165 5831 ufshcd_wb_toggle_buf_flush(hba, false);
f681d107 5832
4450a165 5833 ufshcd_wb_toggle_buf_flush_during_h8(hba, false);
f681d107
JC		 5834 ufshcd_wb_toggle(hba, false);
5835 hba->caps &= ~UFSHCD_CAP_WB_EN;
5836
5837 dev_info(hba->dev, "%s: WB force disabled\n", __func__);
5838}
5839
5840static bool ufshcd_is_wb_buf_lifetime_available(struct ufs_hba *hba)
5841{
5842 u32 lifetime;
5843 int ret;
5844 u8 index;
5845
5846 index = ufshcd_wb_get_query_index(hba);
5847 ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
5848 QUERY_ATTR_IDN_WB_BUFF_LIFE_TIME_EST,
5849 index, 0, &lifetime);
5850 if (ret) {
5851 dev_err(hba->dev,
5852 "%s: bWriteBoosterBufferLifeTimeEst read failed %d\n",
5853 __func__, ret);
5854 return false;
5855 }
5856
5857 if (lifetime == UFS_WB_EXCEED_LIFETIME) {
5858 dev_err(hba->dev, "%s: WB buf lifetime is exhausted 0x%02X\n",
5859 __func__, lifetime);
5860 return false;
5861 }
5862
5863 dev_dbg(hba->dev, "%s: WB buf lifetime is 0x%02X\n",
5864 __func__, lifetime);
5865
5866 return true;
5867}
5868
51dd905b 5869static bool ufshcd_wb_need_flush(struct ufs_hba *hba)
3d17b9b5
AD		 5870{
5871 int ret;
5872 u32 avail_buf;
e31011ab 5873 u8 index;
3d17b9b5 5874
79e3520f 5875 if (!ufshcd_is_wb_allowed(hba))
3d17b9b5 5876 return false;
f681d107
JC		 5877
5878 if (!ufshcd_is_wb_buf_lifetime_available(hba)) {
5879 ufshcd_wb_force_disable(hba);
5880 return false;
5881 }
5882
3d17b9b5
AD		 5883 /*
5884 * The ufs device needs the vcc to be ON to flush.
5885 * With user-space reduction enabled, it's enough to enable flush
5886 * by checking only the available buffer. The threshold
5887 * defined here is > 90% full.
5888 * With user-space preserved enabled, the current-buffer
5889 * should be checked too because the wb buffer size can reduce
5890 * when disk tends to be full. This info is provided by current
5891 * buffer (dCurrentWriteBoosterBufferSize). There's no point in
5892 * keeping vcc on when current buffer is empty.
5893 */
e31011ab 5894 index = ufshcd_wb_get_query_index(hba);
3d17b9b5
AD		 5895 ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
5896 QUERY_ATTR_IDN_AVAIL_WB_BUFF_SIZE,
e31011ab 5897 index, 0, &avail_buf);
3d17b9b5 5898 if (ret) {
4f6b69f3 5899 dev_warn(hba->dev, "%s: dAvailableWriteBoosterBufferSize read failed %d\n",
3d17b9b5
AD		 5900 __func__, ret);
5901 return false;
5902 }
5903
a858af9a
BVA		 5904 if (!hba->dev_info.b_presrv_uspc_en)
5905 return avail_buf <= UFS_WB_BUF_REMAIN_PERCENT(10);
3d17b9b5
AD		 5906
5907 return ufshcd_wb_presrv_usrspc_keep_vcc_on(hba, avail_buf);
5908}
5909
51dd905b
SC		 5910static void ufshcd_rpm_dev_flush_recheck_work(struct work_struct *work)
5911{
5912 struct ufs_hba *hba = container_of(to_delayed_work(work),
5913 struct ufs_hba,
5914 rpm_dev_flush_recheck_work);
5915 /*
5916 * To prevent unnecessary VCC power drain after device finishes
5917 * WriteBooster buffer flush or Auto BKOPs, force runtime resume
5918 * after a certain delay to recheck the threshold by next runtime
5919 * suspend.
5920 */
b294ff3e
AD		 5921 ufshcd_rpm_get_sync(hba);
5922 ufshcd_rpm_put_sync(hba);
51dd905b
SC		 5923}
5924
66ec6d59
SRT		 5925/**
5926 * ufshcd_exception_event_handler - handle exceptions raised by device
5927 * @work: pointer to work data
5928 *
5929 * Read bExceptionEventStatus attribute from the device and handle the
5930 * exception event accordingly.
5931 */
5932static void ufshcd_exception_event_handler(struct work_struct *work)
5933{
5934 struct ufs_hba *hba;
5935 int err;
5936 u32 status = 0;
5937 hba = container_of(work, struct ufs_hba, eeh_work);
5938
03e1d28e 5939 ufshcd_scsi_block_requests(hba);
66ec6d59
SRT		 5940 err = ufshcd_get_ee_status(hba, &status);
5941 if (err) {
5942 dev_err(hba->dev, "%s: failed to get exception status %d\n",
5943 __func__, err);
5944 goto out;
5945 }
5946
f7733625
AH		 5947 trace_ufshcd_exception_event(dev_name(hba->dev), status);
5948
cd469475 5949 if (status & hba->ee_drv_mask & MASK_EE_URGENT_BKOPS)
afdfff59
YG		 5950 ufshcd_bkops_exception_event_handler(hba);
5951
322c4b29
AA		 5952 if (status & hba->ee_drv_mask & MASK_EE_URGENT_TEMP)
5953 ufshcd_temp_exception_event_handler(hba, status);
5954
7deedfda 5955 ufs_debugfs_exception_event(hba, status);
66ec6d59 5956out:
03e1d28e 5957 ufshcd_scsi_unblock_requests(hba);
66ec6d59
SRT		 5958}
5959
9a47ec7c
YG		 5960/* Complete requests that have door-bell cleared */
5961static void ufshcd_complete_requests(struct ufs_hba *hba)
5962{
11682523 5963 ufshcd_transfer_req_compl(hba);
9a47ec7c
YG		 5964 ufshcd_tmc_handler(hba);
5965}
5966
583fa62d
YG		 5967/**
5968 * ufshcd_quirk_dl_nac_errors - This function checks if error handling is
5969 * to recover from the DL NAC errors or not.
5970 * @hba: per-adapter instance
5971 *
5972 * Returns true if error handling is required, false otherwise
5973 */
5974static bool ufshcd_quirk_dl_nac_errors(struct ufs_hba *hba)
5975{
5976 unsigned long flags;
5977 bool err_handling = true;
5978
5979 spin_lock_irqsave(hba->host->host_lock, flags);
5980 /*
5981 * UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS only workaround the
5982 * device fatal error and/or DL NAC & REPLAY timeout errors.
5983 */
5984 if (hba->saved_err & (CONTROLLER_FATAL_ERROR | SYSTEM_BUS_FATAL_ERROR))
5985 goto out;
5986
5987 if ((hba->saved_err & DEVICE_FATAL_ERROR) ||
5988 ((hba->saved_err & UIC_ERROR) &&
5989 (hba->saved_uic_err & UFSHCD_UIC_DL_TCx_REPLAY_ERROR)))
5990 goto out;
5991
5992 if ((hba->saved_err & UIC_ERROR) &&
5993 (hba->saved_uic_err & UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)) {
5994 int err;
5995 /*
5996 * wait for 50ms to see if we can get any other errors or not.
5997 */
5998 spin_unlock_irqrestore(hba->host->host_lock, flags);
5999 msleep(50);
6000 spin_lock_irqsave(hba->host->host_lock, flags);
6001
6002 /*
6003 * now check if we have got any other severe errors other than
6004 * DL NAC error?
6005 */
6006 if ((hba->saved_err & INT_FATAL_ERRORS) ||
6007 ((hba->saved_err & UIC_ERROR) &&
6008 (hba->saved_uic_err & ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)))
6009 goto out;
6010
6011 /*
6012 * As DL NAC is the only error received so far, send out NOP
6013 * command to confirm if link is still active or not.
6014 * - If we don't get any response then do error recovery.
6015 * - If we get response then clear the DL NAC error bit.
6016 */
6017
6018 spin_unlock_irqrestore(hba->host->host_lock, flags);
6019 err = ufshcd_verify_dev_init(hba);
6020 spin_lock_irqsave(hba->host->host_lock, flags);
6021
6022 if (err)
6023 goto out;
6024
6025 /* Link seems to be alive hence ignore the DL NAC errors */
6026 if (hba->saved_uic_err == UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)
6027 hba->saved_err &= ~UIC_ERROR;
6028 /* clear NAC error */
6029 hba->saved_uic_err &= ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR;
b0008625 6030 if (!hba->saved_uic_err)
583fa62d 6031 err_handling = false;
583fa62d
YG		 6032 }
6033out:
6034 spin_unlock_irqrestore(hba->host->host_lock, flags);
6035 return err_handling;
6036}
6037
88b09900
AH		 6038/* host lock must be held before calling this func */
6039static inline bool ufshcd_is_saved_err_fatal(struct ufs_hba *hba)
6040{
6041 return (hba->saved_uic_err & UFSHCD_UIC_DL_PA_INIT_ERROR) ||
6042 (hba->saved_err & (INT_FATAL_ERRORS | UFSHCD_UIC_HIBERN8_MASK));
6043}
6044
267a59f6 6045void ufshcd_schedule_eh_work(struct ufs_hba *hba)
88b09900 6046{
267a59f6
BVA		 6047 lockdep_assert_held(hba->host->host_lock);
6048
88b09900
AH		 6049 /* handle fatal errors only when link is not in error state */
6050 if (hba->ufshcd_state != UFSHCD_STATE_ERROR) {
6051 if (hba->force_reset || ufshcd_is_link_broken(hba) ||
6052 ufshcd_is_saved_err_fatal(hba))
6053 hba->ufshcd_state = UFSHCD_STATE_EH_SCHEDULED_FATAL;
6054 else
6055 hba->ufshcd_state = UFSHCD_STATE_EH_SCHEDULED_NON_FATAL;
6056 queue_work(hba->eh_wq, &hba->eh_work);
6057 }
6058}
6059
348e1bc5
SC		 6060static void ufshcd_clk_scaling_allow(struct ufs_hba *hba, bool allow)
6061{
6062 down_write(&hba->clk_scaling_lock);
6063 hba->clk_scaling.is_allowed = allow;
6064 up_write(&hba->clk_scaling_lock);
6065}
6066
6067static void ufshcd_clk_scaling_suspend(struct ufs_hba *hba, bool suspend)
6068{
6069 if (suspend) {
6070 if (hba->clk_scaling.is_enabled)
6071 ufshcd_suspend_clkscaling(hba);
6072 ufshcd_clk_scaling_allow(hba, false);
6073 } else {
6074 ufshcd_clk_scaling_allow(hba, true);
6075 if (hba->clk_scaling.is_enabled)
6076 ufshcd_resume_clkscaling(hba);
6077 }
6078}
6079
c72e79c0
CG		 6080static void ufshcd_err_handling_prepare(struct ufs_hba *hba)
6081{
b294ff3e 6082 ufshcd_rpm_get_sync(hba);
e2106584 6083 if (pm_runtime_status_suspended(&hba->ufs_device_wlun->sdev_gendev) ||
b294ff3e 6084 hba->is_sys_suspended) {
88a92d6a
CG		 6085 enum ufs_pm_op pm_op;
6086
c72e79c0 6087 /*
b294ff3e 6088 * Don't assume anything of resume, if
c72e79c0
CG		 6089 * resume fails, irq and clocks can be OFF, and powers
6090 * can be OFF or in LPM.
6091 */
6092 ufshcd_setup_hba_vreg(hba, true);
6093 ufshcd_enable_irq(hba);
6094 ufshcd_setup_vreg(hba, true);
6095 ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq);
6096 ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq2);
6097 ufshcd_hold(hba, false);
6098 if (!ufshcd_is_clkgating_allowed(hba))
6099 ufshcd_setup_clocks(hba, true);
6100 ufshcd_release(hba);
88a92d6a
CG		 6101 pm_op = hba->is_sys_suspended ? UFS_SYSTEM_PM : UFS_RUNTIME_PM;
6102 ufshcd_vops_resume(hba, pm_op);
c72e79c0
CG		 6103 } else {
6104 ufshcd_hold(hba, false);
348e1bc5
SC		 6105 if (ufshcd_is_clkscaling_supported(hba) &&
6106 hba->clk_scaling.is_enabled)
c72e79c0 6107 ufshcd_suspend_clkscaling(hba);
348e1bc5 6108 ufshcd_clk_scaling_allow(hba, false);
c72e79c0 6109 }
aa53f580
CG		 6110 ufshcd_scsi_block_requests(hba);
6111 /* Drain ufshcd_queuecommand() */
5675c381 6112 synchronize_rcu();
aa53f580 6113 cancel_work_sync(&hba->eeh_work);
c72e79c0
CG		 6114}
6115
6116static void ufshcd_err_handling_unprepare(struct ufs_hba *hba)
6117{
aa53f580 6118 ufshcd_scsi_unblock_requests(hba);
c72e79c0 6119 ufshcd_release(hba);
348e1bc5
SC		 6120 if (ufshcd_is_clkscaling_supported(hba))
6121 ufshcd_clk_scaling_suspend(hba, false);
b294ff3e 6122 ufshcd_rpm_put(hba);
c72e79c0
CG		 6123}
6124
6125static inline bool ufshcd_err_handling_should_stop(struct ufs_hba *hba)
6126{
9cd20d3f 6127 return (!hba->is_powered || hba->shutting_down ||
e2106584 6128 !hba->ufs_device_wlun ||
9cd20d3f 6129 hba->ufshcd_state == UFSHCD_STATE_ERROR ||
c72e79c0 6130 (!(hba->saved_err || hba->saved_uic_err || hba->force_reset ||
9cd20d3f 6131 ufshcd_is_link_broken(hba))));
c72e79c0
CG		 6132}
6133
6134#ifdef CONFIG_PM
6135static void ufshcd_recover_pm_error(struct ufs_hba *hba)
6136{
6137 struct Scsi_Host *shost = hba->host;
6138 struct scsi_device *sdev;
6139 struct request_queue *q;
6140 int ret;
6141
88a92d6a 6142 hba->is_sys_suspended = false;
c72e79c0 6143 /*
b294ff3e 6144 * Set RPM status of wlun device to RPM_ACTIVE,
c72e79c0
CG		 6145 * this also clears its runtime error.
6146 */
e2106584 6147 ret = pm_runtime_set_active(&hba->ufs_device_wlun->sdev_gendev);
b294ff3e
AD		 6148
6149 /* hba device might have a runtime error otherwise */
6150 if (ret)
6151 ret = pm_runtime_set_active(hba->dev);
c72e79c0 6152 /*
b294ff3e
AD		 6153 * If wlun device had runtime error, we also need to resume those
6154 * consumer scsi devices in case any of them has failed to be
6155 * resumed due to supplier runtime resume failure. This is to unblock
c72e79c0
CG		 6156 * blk_queue_enter in case there are bios waiting inside it.
6157 */
6158 if (!ret) {
6159 shost_for_each_device(sdev, shost) {
6160 q = sdev->request_queue;
6161 if (q->dev && (q->rpm_status == RPM_SUSPENDED ||
6162 q->rpm_status == RPM_SUSPENDING))
6163 pm_request_resume(q->dev);
6164 }
6165 }
6166}
6167#else
6168static inline void ufshcd_recover_pm_error(struct ufs_hba *hba)
6169{
6170}
6171#endif
6172
2355b66e
CG		 6173static bool ufshcd_is_pwr_mode_restore_needed(struct ufs_hba *hba)
6174{
6175 struct ufs_pa_layer_attr *pwr_info = &hba->pwr_info;
6176 u32 mode;
6177
6178 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_PWRMODE), &mode);
6179
6180 if (pwr_info->pwr_rx != ((mode >> PWRMODE_RX_OFFSET) & PWRMODE_MASK))
6181 return true;
6182
6183 if (pwr_info->pwr_tx != (mode & PWRMODE_MASK))
6184 return true;
6185
6186 return false;
6187}
6188
b817e6ff
BVA		 6189static bool ufshcd_abort_all(struct ufs_hba *hba)
6190{
6191 bool needs_reset = false;
6192 int tag, ret;
6193
6194 /* Clear pending transfer requests */
6195 for_each_set_bit(tag, &hba->outstanding_reqs, hba->nutrs) {
6196 ret = ufshcd_try_to_abort_task(hba, tag);
6197 dev_err(hba->dev, "Aborting tag %d / CDB %#02x %s\n", tag,
6198 hba->lrb[tag].cmd ? hba->lrb[tag].cmd->cmnd[0] : -1,
6199 ret ? "failed" : "succeeded");
6200 if (ret) {
6201 needs_reset = true;
6202 goto out;
6203 }
6204 }
6205
6206 /* Clear pending task management requests */
6207 for_each_set_bit(tag, &hba->outstanding_tasks, hba->nutmrs) {
6208 if (ufshcd_clear_tm_cmd(hba, tag)) {
6209 needs_reset = true;
6210 goto out;
6211 }
6212 }
6213
6214out:
6215 /* Complete the requests that are cleared by s/w */
6216 ufshcd_complete_requests(hba);
6217
6218 return needs_reset;
6219}
6220
7a3e97b0 6221/**
e8e7f271 6222 * ufshcd_err_handler - handle UFS errors that require s/w attention
88b09900 6223 * @work: pointer to work structure
7a3e97b0 6224 */
88b09900 6225static void ufshcd_err_handler(struct work_struct *work)
7a3e97b0 6226{
87bf6a6b 6227 int retries = MAX_ERR_HANDLER_RETRIES;
88b09900 6228 struct ufs_hba *hba;
e8e7f271 6229 unsigned long flags;
87bf6a6b
AH		 6230 bool needs_restore;
6231 bool needs_reset;
87bf6a6b 6232 int pmc_err;
e8e7f271 6233
88b09900
AH		 6234 hba = container_of(work, struct ufs_hba, eh_work);
6235
4693fad7
BVA		 6236 dev_info(hba->dev,
6237 "%s started; HBA state %s; powered %d; shutting down %d; saved_err = %d; saved_uic_err = %d; force_reset = %d%s\n",
6238 __func__, ufshcd_state_name[hba->ufshcd_state],
6239 hba->is_powered, hba->shutting_down, hba->saved_err,
6240 hba->saved_uic_err, hba->force_reset,
6241 ufshcd_is_link_broken(hba) ? "; link is broken" : "");
6242
9cd20d3f 6243 down(&hba->host_sem);
e8e7f271 6244 spin_lock_irqsave(hba->host->host_lock, flags);
c72e79c0 6245 if (ufshcd_err_handling_should_stop(hba)) {
4db7a236
CG		 6246 if (hba->ufshcd_state != UFSHCD_STATE_ERROR)
6247 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
6248 spin_unlock_irqrestore(hba->host->host_lock, flags);
9cd20d3f 6249 up(&hba->host_sem);
4db7a236
CG		 6250 return;
6251 }
6252 ufshcd_set_eh_in_progress(hba);
6253 spin_unlock_irqrestore(hba->host->host_lock, flags);
c72e79c0 6254 ufshcd_err_handling_prepare(hba);
a45f9371
CG		 6255 /* Complete requests that have door-bell cleared by h/w */
6256 ufshcd_complete_requests(hba);
e8e7f271 6257 spin_lock_irqsave(hba->host->host_lock, flags);
87bf6a6b
AH		 6258again:
6259 needs_restore = false;
6260 needs_reset = false;
87bf6a6b 6261
aa53f580
CG		 6262 if (hba->ufshcd_state != UFSHCD_STATE_ERROR)
6263 hba->ufshcd_state = UFSHCD_STATE_RESET;
88a92d6a
CG		 6264 /*
6265 * A full reset and restore might have happened after preparation
6266 * is finished, double check whether we should stop.
6267 */
6268 if (ufshcd_err_handling_should_stop(hba))
6269 goto skip_err_handling;
6270
583fa62d
YG		 6271 if (hba->dev_quirks & UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) {
6272 bool ret;
6273
6274 spin_unlock_irqrestore(hba->host->host_lock, flags);
6275 /* release the lock as ufshcd_quirk_dl_nac_errors() may sleep */
6276 ret = ufshcd_quirk_dl_nac_errors(hba);
6277 spin_lock_irqsave(hba->host->host_lock, flags);
88a92d6a 6278 if (!ret && ufshcd_err_handling_should_stop(hba))
583fa62d
YG		 6279 goto skip_err_handling;
6280 }
4db7a236 6281
2355b66e
CG		 6282 if ((hba->saved_err & (INT_FATAL_ERRORS | UFSHCD_UIC_HIBERN8_MASK)) ||
6283 (hba->saved_uic_err &&
6284 (hba->saved_uic_err != UFSHCD_UIC_PA_GENERIC_ERROR))) {
c3be8d1e
CG		 6285 bool pr_prdt = !!(hba->saved_err & SYSTEM_BUS_FATAL_ERROR);
6286
6287 spin_unlock_irqrestore(hba->host->host_lock, flags);
6288 ufshcd_print_host_state(hba);
6289 ufshcd_print_pwr_info(hba);
e965e5e0 6290 ufshcd_print_evt_hist(hba);
c3be8d1e
CG		 6291 ufshcd_print_tmrs(hba, hba->outstanding_tasks);
6292 ufshcd_print_trs(hba, hba->outstanding_reqs, pr_prdt);
6293 spin_lock_irqsave(hba->host->host_lock, flags);
6294 }
6295
9a47ec7c
YG		 6296 /*
6297 * if host reset is required then skip clearing the pending
2df74b69
CG		 6298 * transfers forcefully because they will get cleared during
6299 * host reset and restore
9a47ec7c 6300 */
88a92d6a
CG		 6301 if (hba->force_reset || ufshcd_is_link_broken(hba) ||
6302 ufshcd_is_saved_err_fatal(hba) ||
6303 ((hba->saved_err & UIC_ERROR) &&
6304 (hba->saved_uic_err & (UFSHCD_UIC_DL_NAC_RECEIVED_ERROR |
6305 UFSHCD_UIC_DL_TCx_REPLAY_ERROR)))) {
6306 needs_reset = true;
2355b66e 6307 goto do_reset;
88a92d6a 6308 }
9a47ec7c 6309
2355b66e
CG		 6310 /*
6311 * If LINERESET was caught, UFS might have been put to PWM mode,
6312 * check if power mode restore is needed.
6313 */
6314 if (hba->saved_uic_err & UFSHCD_UIC_PA_GENERIC_ERROR) {
6315 hba->saved_uic_err &= ~UFSHCD_UIC_PA_GENERIC_ERROR;
6316 if (!hba->saved_uic_err)
6317 hba->saved_err &= ~UIC_ERROR;
6318 spin_unlock_irqrestore(hba->host->host_lock, flags);
6319 if (ufshcd_is_pwr_mode_restore_needed(hba))
6320 needs_restore = true;
6321 spin_lock_irqsave(hba->host->host_lock, flags);
6322 if (!hba->saved_err && !needs_restore)
6323 goto skip_err_handling;
6324 }
9a47ec7c 6325
2355b66e 6326 hba->silence_err_logs = true;
9a47ec7c
YG		 6327 /* release lock as clear command might sleep */
6328 spin_unlock_irqrestore(hba->host->host_lock, flags);
e8e7f271 6329
b817e6ff 6330 needs_reset = ufshcd_abort_all(hba);
9a47ec7c 6331
a45f9371
CG		 6332 spin_lock_irqsave(hba->host->host_lock, flags);
6333 hba->silence_err_logs = false;
b817e6ff 6334 if (needs_reset)
2355b66e 6335 goto do_reset;
9a47ec7c 6336
2355b66e
CG		 6337 /*
6338 * After all reqs and tasks are cleared from doorbell,
6339 * now it is safe to retore power mode.
6340 */
6341 if (needs_restore) {
6342 spin_unlock_irqrestore(hba->host->host_lock, flags);
6343 /*
6344 * Hold the scaling lock just in case dev cmds
6345 * are sent via bsg and/or sysfs.
6346 */
6347 down_write(&hba->clk_scaling_lock);
6348 hba->force_pmc = true;
6349 pmc_err = ufshcd_config_pwr_mode(hba, &(hba->pwr_info));
6350 if (pmc_err) {
6351 needs_reset = true;
6352 dev_err(hba->dev, "%s: Failed to restore power mode, err = %d\n",
6353 __func__, pmc_err);
6354 }
6355 hba->force_pmc = false;
6356 ufshcd_print_pwr_info(hba);
6357 up_write(&hba->clk_scaling_lock);
6358 spin_lock_irqsave(hba->host->host_lock, flags);
6359 }
9a47ec7c 6360
2355b66e 6361do_reset:
e8e7f271 6362 /* Fatal errors need reset */
9a47ec7c 6363 if (needs_reset) {
87bf6a6b
AH		 6364 int err;
6365
4db7a236 6366 hba->force_reset = false;
9a47ec7c 6367 spin_unlock_irqrestore(hba->host->host_lock, flags);
e8e7f271 6368 err = ufshcd_reset_and_restore(hba);
4db7a236
CG		 6369 if (err)
6370 dev_err(hba->dev, "%s: reset and restore failed with err %d\n",
6371 __func__, err);
c72e79c0
CG		 6372 else
6373 ufshcd_recover_pm_error(hba);
9a47ec7c 6374 spin_lock_irqsave(hba->host->host_lock, flags);
e8e7f271 6375 }
9a47ec7c 6376
583fa62d 6377skip_err_handling:
9a47ec7c 6378 if (!needs_reset) {
4db7a236
CG		 6379 if (hba->ufshcd_state == UFSHCD_STATE_RESET)
6380 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
9a47ec7c
YG		 6381 if (hba->saved_err || hba->saved_uic_err)
6382 dev_err_ratelimited(hba->dev, "%s: exit: saved_err 0x%x saved_uic_err 0x%x",
6383 __func__, hba->saved_err, hba->saved_uic_err);
6384 }
87bf6a6b
AH		 6385 /* Exit in an operational state or dead */
6386 if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL &&
6387 hba->ufshcd_state != UFSHCD_STATE_ERROR) {
6388 if (--retries)
6389 goto again;
6390 hba->ufshcd_state = UFSHCD_STATE_ERROR;
6391 }
e8e7f271 6392 ufshcd_clear_eh_in_progress(hba);
9a47ec7c 6393 spin_unlock_irqrestore(hba->host->host_lock, flags);
c72e79c0 6394 ufshcd_err_handling_unprepare(hba);
9cd20d3f 6395 up(&hba->host_sem);
4693fad7
BVA		 6396
6397 dev_info(hba->dev, "%s finished; HBA state %s\n", __func__,
6398 ufshcd_state_name[hba->ufshcd_state]);
7a3e97b0
SY		 6399}
6400
6401/**
e8e7f271
SRT		 6402 * ufshcd_update_uic_error - check and set fatal UIC error flags.
6403 * @hba: per-adapter instance
9333d775
VG		 6404 *
6405 * Returns
6406 * IRQ_HANDLED - If interrupt is valid
6407 * IRQ_NONE - If invalid interrupt
7a3e97b0 6408 */
9333d775 6409static irqreturn_t ufshcd_update_uic_error(struct ufs_hba *hba)
7a3e97b0
SY		 6410{
6411 u32 reg;
9333d775 6412 irqreturn_t retval = IRQ_NONE;
7a3e97b0 6413
2355b66e 6414 /* PHY layer error */
fb7b45f0 6415 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER);
fb7b45f0 6416 if ((reg & UIC_PHY_ADAPTER_LAYER_ERROR) &&
2355b66e 6417 (reg & UIC_PHY_ADAPTER_LAYER_ERROR_CODE_MASK)) {
e965e5e0 6418 ufshcd_update_evt_hist(hba, UFS_EVT_PA_ERR, reg);
fb7b45f0
DR		 6419 /*
6420 * To know whether this error is fatal or not, DB timeout
6421 * must be checked but this error is handled separately.
6422 */
2355b66e
CG		 6423 if (reg & UIC_PHY_ADAPTER_LAYER_LANE_ERR_MASK)
6424 dev_dbg(hba->dev, "%s: UIC Lane error reported\n",
6425 __func__);
6426
6427 /* Got a LINERESET indication. */
6428 if (reg & UIC_PHY_ADAPTER_LAYER_GENERIC_ERROR) {
6429 struct uic_command *cmd = NULL;
6430
6431 hba->uic_error |= UFSHCD_UIC_PA_GENERIC_ERROR;
6432 if (hba->uic_async_done && hba->active_uic_cmd)
6433 cmd = hba->active_uic_cmd;
6434 /*
6435 * Ignore the LINERESET during power mode change
6436 * operation via DME_SET command.
6437 */
6438 if (cmd && (cmd->command == UIC_CMD_DME_SET))
6439 hba->uic_error &= ~UFSHCD_UIC_PA_GENERIC_ERROR;
6440 }
9333d775 6441 retval |= IRQ_HANDLED;
ff8e20c6 6442 }
fb7b45f0 6443
e8e7f271
SRT		 6444 /* PA_INIT_ERROR is fatal and needs UIC reset */
6445 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DATA_LINK_LAYER);
9333d775
VG		 6446 if ((reg & UIC_DATA_LINK_LAYER_ERROR) &&
6447 (reg & UIC_DATA_LINK_LAYER_ERROR_CODE_MASK)) {
e965e5e0 6448 ufshcd_update_evt_hist(hba, UFS_EVT_DL_ERR, reg);
ff8e20c6 6449
9333d775
VG		 6450 if (reg & UIC_DATA_LINK_LAYER_ERROR_PA_INIT)
6451 hba->uic_error |= UFSHCD_UIC_DL_PA_INIT_ERROR;
6452 else if (hba->dev_quirks &
6453 UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) {
6454 if (reg & UIC_DATA_LINK_LAYER_ERROR_NAC_RECEIVED)
6455 hba->uic_error |=
6456 UFSHCD_UIC_DL_NAC_RECEIVED_ERROR;
6457 else if (reg & UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_TIMEOUT)
6458 hba->uic_error |= UFSHCD_UIC_DL_TCx_REPLAY_ERROR;
6459 }
6460 retval |= IRQ_HANDLED;
583fa62d 6461 }
e8e7f271
SRT		 6462
6463 /* UIC NL/TL/DME errors needs software retry */
6464 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_NETWORK_LAYER);
9333d775
VG		 6465 if ((reg & UIC_NETWORK_LAYER_ERROR) &&
6466 (reg & UIC_NETWORK_LAYER_ERROR_CODE_MASK)) {
e965e5e0 6467 ufshcd_update_evt_hist(hba, UFS_EVT_NL_ERR, reg);
e8e7f271 6468 hba->uic_error |= UFSHCD_UIC_NL_ERROR;
9333d775 6469 retval |= IRQ_HANDLED;
ff8e20c6 6470 }
e8e7f271
SRT		 6471
6472 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_TRANSPORT_LAYER);
9333d775
VG		 6473 if ((reg & UIC_TRANSPORT_LAYER_ERROR) &&
6474 (reg & UIC_TRANSPORT_LAYER_ERROR_CODE_MASK)) {
e965e5e0 6475 ufshcd_update_evt_hist(hba, UFS_EVT_TL_ERR, reg);
e8e7f271 6476 hba->uic_error |= UFSHCD_UIC_TL_ERROR;
9333d775 6477 retval |= IRQ_HANDLED;
ff8e20c6 6478 }
e8e7f271
SRT		 6479
6480 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DME);
9333d775
VG		 6481 if ((reg & UIC_DME_ERROR) &&
6482 (reg & UIC_DME_ERROR_CODE_MASK)) {
e965e5e0 6483 ufshcd_update_evt_hist(hba, UFS_EVT_DME_ERR, reg);
e8e7f271 6484 hba->uic_error |= UFSHCD_UIC_DME_ERROR;
9333d775 6485 retval |= IRQ_HANDLED;
ff8e20c6 6486 }
e8e7f271
SRT		 6487
6488 dev_dbg(hba->dev, "%s: UIC error flags = 0x%08x\n",
6489 __func__, hba->uic_error);
9333d775 6490 return retval;
e8e7f271
SRT		 6491}
6492
6493/**
6494 * ufshcd_check_errors - Check for errors that need s/w attention
6495 * @hba: per-adapter instance
a45f9371 6496 * @intr_status: interrupt status generated by the controller
9333d775
VG		 6497 *
6498 * Returns
6499 * IRQ_HANDLED - If interrupt is valid
6500 * IRQ_NONE - If invalid interrupt
e8e7f271 6501 */
a45f9371 6502static irqreturn_t ufshcd_check_errors(struct ufs_hba *hba, u32 intr_status)
e8e7f271
SRT		 6503{
6504 bool queue_eh_work = false;
9333d775 6505 irqreturn_t retval = IRQ_NONE;
e8e7f271 6506
a45f9371
CG		 6507 spin_lock(hba->host->host_lock);
6508 hba->errors |= UFSHCD_ERROR_MASK & intr_status;
6509
d3c615bf 6510 if (hba->errors & INT_FATAL_ERRORS) {
e965e5e0
SC		 6511 ufshcd_update_evt_hist(hba, UFS_EVT_FATAL_ERR,
6512 hba->errors);
e8e7f271 6513 queue_eh_work = true;
d3c615bf 6514 }
7a3e97b0
SY		 6515
6516 if (hba->errors & UIC_ERROR) {
e8e7f271 6517 hba->uic_error = 0;
9333d775 6518 retval = ufshcd_update_uic_error(hba);
e8e7f271
SRT		 6519 if (hba->uic_error)
6520 queue_eh_work = true;
7a3e97b0 6521 }
e8e7f271 6522
82174440
SC		 6523 if (hba->errors & UFSHCD_UIC_HIBERN8_MASK) {
6524 dev_err(hba->dev,
6525 "%s: Auto Hibern8 %s failed - status: 0x%08x, upmcrs: 0x%08x\n",
6526 __func__, (hba->errors & UIC_HIBERNATE_ENTER) ?
6527 "Enter" : "Exit",
6528 hba->errors, ufshcd_get_upmcrs(hba));
e965e5e0 6529 ufshcd_update_evt_hist(hba, UFS_EVT_AUTO_HIBERN8_ERR,
d3c615bf 6530 hba->errors);
4db7a236 6531 ufshcd_set_link_broken(hba);
82174440
SC		 6532 queue_eh_work = true;
6533 }
6534
e8e7f271 6535 if (queue_eh_work) {
9a47ec7c
YG		 6536 /*
6537 * update the transfer error masks to sticky bits, let's do this
6538 * irrespective of current ufshcd_state.
6539 */
6540 hba->saved_err |= hba->errors;
6541 hba->saved_uic_err |= hba->uic_error;
6542
4db7a236 6543 /* dump controller state before resetting */
ace3804b
CG		 6544 if ((hba->saved_err &
6545 (INT_FATAL_ERRORS | UFSHCD_UIC_HIBERN8_MASK)) ||
2355b66e
CG		 6546 (hba->saved_uic_err &&
6547 (hba->saved_uic_err != UFSHCD_UIC_PA_GENERIC_ERROR))) {
4db7a236 6548 dev_err(hba->dev, "%s: saved_err 0x%x saved_uic_err 0x%x\n",
66cc820f
DR		 6549 __func__, hba->saved_err,
6550 hba->saved_uic_err);
c3be8d1e
CG		 6551 ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE,
6552 "host_regs: ");
4db7a236 6553 ufshcd_print_pwr_info(hba);
e8e7f271 6554 }
88b09900 6555 ufshcd_schedule_eh_work(hba);
9333d775 6556 retval |= IRQ_HANDLED;
3441da7d 6557 }
e8e7f271
SRT		 6558 /*
6559 * if (!queue_eh_work) -
6560 * Other errors are either non-fatal where host recovers
6561 * itself without s/w intervention or errors that will be
6562 * handled by the SCSI core layer.
6563 */
a45f9371
CG		 6564 hba->errors = 0;
6565 hba->uic_error = 0;
6566 spin_unlock(hba->host->host_lock);
9333d775 6567 return retval;
7a3e97b0
SY		 6568}
6569
6570/**
6571 * ufshcd_tmc_handler - handle task management function completion
6572 * @hba: per adapter instance
9333d775
VG		 6573 *
6574 * Returns
6575 * IRQ_HANDLED - If interrupt is valid
6576 * IRQ_NONE - If invalid interrupt
7a3e97b0 6577 */
9333d775 6578static irqreturn_t ufshcd_tmc_handler(struct ufs_hba *hba)
7a3e97b0 6579{
f5ef336f
AH		 6580 unsigned long flags, pending, issued;
6581 irqreturn_t ret = IRQ_NONE;
6582 int tag;
6583
a45f9371 6584 spin_lock_irqsave(hba->host->host_lock, flags);
5cb37a26 6585 pending = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL);
f5ef336f
AH		 6586 issued = hba->outstanding_tasks & ~pending;
6587 for_each_set_bit(tag, &issued, hba->nutmrs) {
6588 struct request *req = hba->tmf_rqs[tag];
6589 struct completion *c = req->end_io_data;
6590
6591 complete(c);
6592 ret = IRQ_HANDLED;
6593 }
a45f9371
CG		 6594 spin_unlock_irqrestore(hba->host->host_lock, flags);
6595
f5ef336f 6596 return ret;
7a3e97b0
SY		 6597}
6598
6599/**
6600 * ufshcd_sl_intr - Interrupt service routine
6601 * @hba: per adapter instance
6602 * @intr_status: contains interrupts generated by the controller
9333d775
VG		 6603 *
6604 * Returns
6605 * IRQ_HANDLED - If interrupt is valid
6606 * IRQ_NONE - If invalid interrupt
7a3e97b0 6607 */
9333d775 6608static irqreturn_t ufshcd_sl_intr(struct ufs_hba *hba, u32 intr_status)
7a3e97b0 6609{
9333d775
VG		 6610 irqreturn_t retval = IRQ_NONE;
6611
53b3d9c3 6612 if (intr_status & UFSHCD_UIC_MASK)
9333d775 6613 retval |= ufshcd_uic_cmd_compl(hba, intr_status);
7a3e97b0 6614
a45f9371
CG		 6615 if (intr_status & UFSHCD_ERROR_MASK || hba->errors)
6616 retval |= ufshcd_check_errors(hba, intr_status);
6617
7a3e97b0 6618 if (intr_status & UTP_TASK_REQ_COMPL)
9333d775 6619 retval |= ufshcd_tmc_handler(hba);
7a3e97b0
SY		 6620
6621 if (intr_status & UTP_TRANSFER_REQ_COMPL)
11682523 6622 retval |= ufshcd_transfer_req_compl(hba);
9333d775
VG		 6623
6624 return retval;
7a3e97b0
SY		 6625}
6626
6627/**
6628 * ufshcd_intr - Main interrupt service routine
6629 * @irq: irq number
6630 * @__hba: pointer to adapter instance
6631 *
9333d775
VG		 6632 * Returns
6633 * IRQ_HANDLED - If interrupt is valid
6634 * IRQ_NONE - If invalid interrupt
7a3e97b0
SY		 6635 */
6636static irqreturn_t ufshcd_intr(int irq, void *__hba)
6637{
127d5f7c 6638 u32 intr_status, enabled_intr_status = 0;
7a3e97b0
SY		 6639 irqreturn_t retval = IRQ_NONE;
6640 struct ufs_hba *hba = __hba;
7f6ba4f1 6641 int retries = hba->nutrs;
7a3e97b0 6642
b873a275 6643 intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
3f8af604 6644 hba->ufs_stats.last_intr_status = intr_status;
0f85e747 6645 hba->ufs_stats.last_intr_ts = local_clock();
7a3e97b0 6646
7f6ba4f1
VG		 6647 /*
6648 * There could be max of hba->nutrs reqs in flight and in worst case
6649 * if the reqs get finished 1 by 1 after the interrupt status is
6650 * read, make sure we handle them by checking the interrupt status
6651 * again in a loop until we process all of the reqs before returning.
6652 */
127d5f7c 6653 while (intr_status && retries--) {
7f6ba4f1
VG		 6654 enabled_intr_status =
6655 intr_status & ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
60ec3755 6656 ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS);
9333d775
VG		 6657 if (enabled_intr_status)
6658 retval |= ufshcd_sl_intr(hba, enabled_intr_status);
7f6ba4f1
VG		 6659
6660 intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
127d5f7c 6661 }
d75f7fe4 6662
eeb1b55b 6663 if (enabled_intr_status && retval == IRQ_NONE &&
40d2fd05
BVA		 6664 (!(enabled_intr_status & UTP_TRANSFER_REQ_COMPL) ||
6665 hba->outstanding_reqs) && !ufshcd_eh_in_progress(hba)) {
eeb1b55b
JK		 6666 dev_err(hba->dev, "%s: Unhandled interrupt 0x%08x (0x%08x, 0x%08x)\n",
6667 __func__,
6668 intr_status,
6669 hba->ufs_stats.last_intr_status,
6670 enabled_intr_status);
9333d775
VG		 6671 ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE, "host_regs: ");
6672 }
6673
7a3e97b0
SY		 6674 return retval;
6675}
6676
e2933132
SRT		 6677static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag)
6678{
6679 int err = 0;
6680 u32 mask = 1 << tag;
6681 unsigned long flags;
6682
6683 if (!test_bit(tag, &hba->outstanding_tasks))
6684 goto out;
6685
6686 spin_lock_irqsave(hba->host->host_lock, flags);
1399c5b0 6687 ufshcd_utmrl_clear(hba, tag);
e2933132
SRT		 6688 spin_unlock_irqrestore(hba->host->host_lock, flags);
6689
6690 /* poll for max. 1 sec to clear door bell register by h/w */
6691 err = ufshcd_wait_for_register(hba,
6692 REG_UTP_TASK_REQ_DOOR_BELL,
5cac1095 6693 mask, 0, 1000, 1000);
4693fad7
BVA		 6694
6695 dev_err(hba->dev, "Clearing task management function with tag %d %s\n",
6696 tag, err ? "succeeded" : "failed");
6697
e2933132
SRT		 6698out:
6699 return err;
6700}
6701
c6049cd9
CH		 6702static int __ufshcd_issue_tm_cmd(struct ufs_hba *hba,
6703 struct utp_task_req_desc *treq, u8 tm_function)
7a3e97b0 6704{
69a6c269 6705 struct request_queue *q = hba->tmf_queue;
c6049cd9 6706 struct Scsi_Host *host = hba->host;
69a6c269
BVA		 6707 DECLARE_COMPLETION_ONSTACK(wait);
6708 struct request *req;
7a3e97b0 6709 unsigned long flags;
4b42d557 6710 int task_tag, err;
7a3e97b0 6711
e2933132 6712 /*
0bf6d96c 6713 * blk_mq_alloc_request() is used here only to get a free tag.
e2933132 6714 */
0bf6d96c 6715 req = blk_mq_alloc_request(q, REQ_OP_DRV_OUT, 0);
eeb1b55b
JK		 6716 if (IS_ERR(req))
6717 return PTR_ERR(req);
6718
69a6c269 6719 req->end_io_data = &wait;
1ab27c9c 6720 ufshcd_hold(hba, false);
7a3e97b0 6721
e2933132 6722 spin_lock_irqsave(host->host_lock, flags);
7a3e97b0 6723
4b42d557 6724 task_tag = req->tag;
eaab9b57
BVA		 6725 WARN_ONCE(task_tag < 0 || task_tag >= hba->nutmrs, "Invalid tag %d\n",
6726 task_tag);
f5ef336f 6727 hba->tmf_rqs[req->tag] = req;
1352eec8 6728 treq->upiu_req.req_header.dword_0 |= cpu_to_be32(task_tag);
c6049cd9 6729
4b42d557
CG		 6730 memcpy(hba->utmrdl_base_addr + task_tag, treq, sizeof(*treq));
6731 ufshcd_vops_setup_task_mgmt(hba, task_tag, tm_function);
d2877be4 6732
7a3e97b0 6733 /* send command to the controller */
4b42d557 6734 __set_bit(task_tag, &hba->outstanding_tasks);
897efe62 6735
4b42d557 6736 ufshcd_writel(hba, 1 << task_tag, REG_UTP_TASK_REQ_DOOR_BELL);
ad1a1b9c
GB		 6737 /* Make sure that doorbell is committed immediately */
6738 wmb();
7a3e97b0
SY		 6739
6740 spin_unlock_irqrestore(host->host_lock, flags);
6741
28fa68fc 6742 ufshcd_add_tm_upiu_trace(hba, task_tag, UFS_TM_SEND);
6667e6d9 6743
7a3e97b0 6744 /* wait until the task management command is completed */
69a6c269 6745 err = wait_for_completion_io_timeout(&wait,
e2933132 6746 msecs_to_jiffies(TM_CMD_TIMEOUT));
7a3e97b0 6747 if (!err) {
28fa68fc 6748 ufshcd_add_tm_upiu_trace(hba, task_tag, UFS_TM_ERR);
e2933132
SRT		 6749 dev_err(hba->dev, "%s: task management cmd 0x%.2x timed-out\n",
6750 __func__, tm_function);
4b42d557
CG		 6751 if (ufshcd_clear_tm_cmd(hba, task_tag))
6752 dev_WARN(hba->dev, "%s: unable to clear tm cmd (slot %d) after timeout\n",
6753 __func__, task_tag);
e2933132
SRT		 6754 err = -ETIMEDOUT;
6755 } else {
c6049cd9 6756 err = 0;
4b42d557 6757 memcpy(treq, hba->utmrdl_base_addr + task_tag, sizeof(*treq));
c6049cd9 6758
28fa68fc 6759 ufshcd_add_tm_upiu_trace(hba, task_tag, UFS_TM_COMP);
7a3e97b0 6760 }
e2933132 6761
b557217c 6762 spin_lock_irqsave(hba->host->host_lock, flags);
f5ef336f 6763 hba->tmf_rqs[req->tag] = NULL;
4b42d557 6764 __clear_bit(task_tag, &hba->outstanding_tasks);
b557217c
SC		 6765 spin_unlock_irqrestore(hba->host->host_lock, flags);
6766
4b42d557 6767 ufshcd_release(hba);
0bf6d96c 6768 blk_mq_free_request(req);
e2933132 6769
7a3e97b0
SY		 6770 return err;
6771}
6772
c6049cd9
CH		 6773/**
6774 * ufshcd_issue_tm_cmd - issues task management commands to controller
6775 * @hba: per adapter instance
6776 * @lun_id: LUN ID to which TM command is sent
6777 * @task_id: task ID to which the TM command is applicable
6778 * @tm_function: task management function opcode
6779 * @tm_response: task management service response return value
6780 *
6781 * Returns non-zero value on error, zero on success.
6782 */
6783static int ufshcd_issue_tm_cmd(struct ufs_hba *hba, int lun_id, int task_id,
6784 u8 tm_function, u8 *tm_response)
6785{
6786 struct utp_task_req_desc treq = { { 0 }, };
957d63e7
BVA		 6787 enum utp_ocs ocs_value;
6788 int err;
c6049cd9
CH		 6789
6790 /* Configure task request descriptor */
6791 treq.header.dword_0 = cpu_to_le32(UTP_REQ_DESC_INT_CMD);
6792 treq.header.dword_2 = cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
6793
6794 /* Configure task request UPIU */
1352eec8 6795 treq.upiu_req.req_header.dword_0 = cpu_to_be32(lun_id << 8) |
c6049cd9 6796 cpu_to_be32(UPIU_TRANSACTION_TASK_REQ << 24);
1352eec8 6797 treq.upiu_req.req_header.dword_1 = cpu_to_be32(tm_function << 16);
c6049cd9
CH		 6798
6799 /*
6800 * The host shall provide the same value for LUN field in the basic
6801 * header and for Input Parameter.
6802 */
1352eec8
GS		 6803 treq.upiu_req.input_param1 = cpu_to_be32(lun_id);
6804 treq.upiu_req.input_param2 = cpu_to_be32(task_id);
c6049cd9
CH		 6805
6806 err = __ufshcd_issue_tm_cmd(hba, &treq, tm_function);
6807 if (err == -ETIMEDOUT)
6808 return err;
6809
6810 ocs_value = le32_to_cpu(treq.header.dword_2) & MASK_OCS;
6811 if (ocs_value != OCS_SUCCESS)
6812 dev_err(hba->dev, "%s: failed, ocs = 0x%x\n",
6813 __func__, ocs_value);
6814 else if (tm_response)
1352eec8 6815 *tm_response = be32_to_cpu(treq.upiu_rsp.output_param1) &
c6049cd9
CH		 6816 MASK_TM_SERVICE_RESP;
6817 return err;
6818}
6819
5e0a86ee
AA		 6820/**
6821 * ufshcd_issue_devman_upiu_cmd - API for sending "utrd" type requests
6822 * @hba: per-adapter instance
6823 * @req_upiu: upiu request
6824 * @rsp_upiu: upiu reply
5e0a86ee
AA		 6825 * @desc_buff: pointer to descriptor buffer, NULL if NA
6826 * @buff_len: descriptor size, 0 if NA
d0e9760d 6827 * @cmd_type: specifies the type (NOP, Query...)
5e0a86ee
AA		 6828 * @desc_op: descriptor operation
6829 *
6830 * Those type of requests uses UTP Transfer Request Descriptor - utrd.
6831 * Therefore, it "rides" the device management infrastructure: uses its tag and
6832 * tasks work queues.
6833 *
6834 * Since there is only one available tag for device management commands,
6835 * the caller is expected to hold the hba->dev_cmd.lock mutex.
6836 */
6837static int ufshcd_issue_devman_upiu_cmd(struct ufs_hba *hba,
6838 struct utp_upiu_req *req_upiu,
6839 struct utp_upiu_req *rsp_upiu,
6840 u8 *desc_buff, int *buff_len,
7f674c38 6841 enum dev_cmd_type cmd_type,
5e0a86ee
AA		 6842 enum query_opcode desc_op)
6843{
8a686f26 6844 DECLARE_COMPLETION_ONSTACK(wait);
945c3cca 6845 const u32 tag = hba->reserved_slot;
5e0a86ee
AA		 6846 struct ufshcd_lrb *lrbp;
6847 int err = 0;
a23064c4 6848 u8 upiu_flags;
5e0a86ee 6849
945c3cca
BVA		 6850 /* Protects use of hba->reserved_slot. */
6851 lockdep_assert_held(&hba->dev_cmd.lock);
5e0a86ee 6852
945c3cca 6853 down_read(&hba->clk_scaling_lock);
5e0a86ee 6854
a45f9371 6855 lrbp = &hba->lrb[tag];
7a7e66c6 6856 WARN_ON(lrbp->cmd);
5e0a86ee 6857 lrbp->cmd = NULL;
5e0a86ee
AA		 6858 lrbp->task_tag = tag;
6859 lrbp->lun = 0;
6860 lrbp->intr_cmd = true;
df043c74 6861 ufshcd_prepare_lrbp_crypto(NULL, lrbp);
5e0a86ee
AA		 6862 hba->dev_cmd.type = cmd_type;
6863
51428818 6864 if (hba->ufs_version <= ufshci_version(1, 1))
5e0a86ee 6865 lrbp->command_type = UTP_CMD_TYPE_DEV_MANAGE;
51428818 6866 else
5e0a86ee 6867 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE;
5e0a86ee
AA		 6868
6869 /* update the task tag in the request upiu */
6870 req_upiu->header.dword_0 |= cpu_to_be32(tag);
6871
a4b1c9b9 6872 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, DMA_NONE, 0);
5e0a86ee
AA		 6873
6874 /* just copy the upiu request as it is */
6875 memcpy(lrbp->ucd_req_ptr, req_upiu, sizeof(*lrbp->ucd_req_ptr));
6876 if (desc_buff && desc_op == UPIU_QUERY_OPCODE_WRITE_DESC) {
6877 /* The Data Segment Area is optional depending upon the query
6878 * function value. for WRITE DESCRIPTOR, the data segment
6879 * follows right after the tsf.
6880 */
6881 memcpy(lrbp->ucd_req_ptr + 1, desc_buff, *buff_len);
6882 *buff_len = 0;
6883 }
6884
6885 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
6886
6887 hba->dev_cmd.complete = &wait;
6888
10542489 6889 ufshcd_add_query_upiu_trace(hba, UFS_QUERY_SEND, lrbp->ucd_req_ptr);
5e0a86ee 6890
a45f9371 6891 ufshcd_send_command(hba, tag);
5e0a86ee
AA		 6892 /*
6893 * ignore the returning value here - ufshcd_check_query_response is
6894 * bound to fail since dev_cmd.query and dev_cmd.type were left empty.
6895 * read the response directly ignoring all errors.
6896 */
6897 ufshcd_wait_for_dev_cmd(hba, lrbp, QUERY_REQ_TIMEOUT);
6898
6899 /* just copy the upiu response as it is */
6900 memcpy(rsp_upiu, lrbp->ucd_rsp_ptr, sizeof(*rsp_upiu));
4bbbe242
AA		 6901 if (desc_buff && desc_op == UPIU_QUERY_OPCODE_READ_DESC) {
6902 u8 *descp = (u8 *)lrbp->ucd_rsp_ptr + sizeof(*rsp_upiu);
6903 u16 resp_len = be32_to_cpu(lrbp->ucd_rsp_ptr->header.dword_2) &
6904 MASK_QUERY_DATA_SEG_LEN;
6905
6906 if (*buff_len >= resp_len) {
6907 memcpy(desc_buff, descp, resp_len);
6908 *buff_len = resp_len;
6909 } else {
3d4881d1
BH		 6910 dev_warn(hba->dev,
6911 "%s: rsp size %d is bigger than buffer size %d",
6912 __func__, resp_len, *buff_len);
4bbbe242
AA		 6913 *buff_len = 0;
6914 err = -EINVAL;
6915 }
6916 }
10542489
BH		 6917 ufshcd_add_query_upiu_trace(hba, err ? UFS_QUERY_ERR : UFS_QUERY_COMP,
6918 (struct utp_upiu_req *)lrbp->ucd_rsp_ptr);
5e0a86ee 6919
5e0a86ee
AA		 6920 up_read(&hba->clk_scaling_lock);
6921 return err;
6922}
6923
6924/**
6925 * ufshcd_exec_raw_upiu_cmd - API function for sending raw upiu commands
6926 * @hba: per-adapter instance
6927 * @req_upiu: upiu request
6928 * @rsp_upiu: upiu reply - only 8 DW as we do not support scsi commands
6929 * @msgcode: message code, one of UPIU Transaction Codes Initiator to Target
6930 * @desc_buff: pointer to descriptor buffer, NULL if NA
6931 * @buff_len: descriptor size, 0 if NA
6932 * @desc_op: descriptor operation
6933 *
6934 * Supports UTP Transfer requests (nop and query), and UTP Task
6935 * Management requests.
6936 * It is up to the caller to fill the upiu conent properly, as it will
6937 * be copied without any further input validations.
6938 */
6939int ufshcd_exec_raw_upiu_cmd(struct ufs_hba *hba,
6940 struct utp_upiu_req *req_upiu,
6941 struct utp_upiu_req *rsp_upiu,
6942 int msgcode,
6943 u8 *desc_buff, int *buff_len,
6944 enum query_opcode desc_op)
6945{
6946 int err;
7f674c38 6947 enum dev_cmd_type cmd_type = DEV_CMD_TYPE_QUERY;
5e0a86ee 6948 struct utp_task_req_desc treq = { { 0 }, };
957d63e7 6949 enum utp_ocs ocs_value;
5e0a86ee
AA		 6950 u8 tm_f = be32_to_cpu(req_upiu->header.dword_1) >> 16 & MASK_TM_FUNC;
6951
5e0a86ee
AA		 6952 switch (msgcode) {
6953 case UPIU_TRANSACTION_NOP_OUT:
6954 cmd_type = DEV_CMD_TYPE_NOP;
df561f66 6955 fallthrough;
5e0a86ee
AA		 6956 case UPIU_TRANSACTION_QUERY_REQ:
6957 ufshcd_hold(hba, false);
6958 mutex_lock(&hba->dev_cmd.lock);
6959 err = ufshcd_issue_devman_upiu_cmd(hba, req_upiu, rsp_upiu,
6960 desc_buff, buff_len,
6961 cmd_type, desc_op);
6962 mutex_unlock(&hba->dev_cmd.lock);
6963 ufshcd_release(hba);
6964
6965 break;
6966 case UPIU_TRANSACTION_TASK_REQ:
6967 treq.header.dword_0 = cpu_to_le32(UTP_REQ_DESC_INT_CMD);
6968 treq.header.dword_2 = cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
6969
1352eec8 6970 memcpy(&treq.upiu_req, req_upiu, sizeof(*req_upiu));
5e0a86ee
AA		 6971
6972 err = __ufshcd_issue_tm_cmd(hba, &treq, tm_f);
6973 if (err == -ETIMEDOUT)
6974 break;
6975
6976 ocs_value = le32_to_cpu(treq.header.dword_2) & MASK_OCS;
6977 if (ocs_value != OCS_SUCCESS) {
6978 dev_err(hba->dev, "%s: failed, ocs = 0x%x\n", __func__,
6979 ocs_value);
6980 break;
6981 }
6982
1352eec8 6983 memcpy(rsp_upiu, &treq.upiu_rsp, sizeof(*rsp_upiu));
5e0a86ee
AA		 6984
6985 break;
6986 default:
6987 err = -EINVAL;
6988
6989 break;
6990 }
6991
5e0a86ee
AA		 6992 return err;
6993}
6994
6ff265fc
BH		 6995/**
6996 * ufshcd_advanced_rpmb_req_handler - handle advanced RPMB request
6997 * @hba: per adapter instance
6998 * @req_upiu: upiu request
6999 * @rsp_upiu: upiu reply
7000 * @req_ehs: EHS field which contains Advanced RPMB Request Message
7001 * @rsp_ehs: EHS field which returns Advanced RPMB Response Message
7002 * @sg_cnt: The number of sg lists actually used
7003 * @sg_list: Pointer to SG list when DATA IN/OUT UPIU is required in ARPMB operation
7004 * @dir: DMA direction
7005 *
7006 * Returns zero on success, non-zero on failure
7007 */
7008int ufshcd_advanced_rpmb_req_handler(struct ufs_hba *hba, struct utp_upiu_req *req_upiu,
7009 struct utp_upiu_req *rsp_upiu, struct ufs_ehs *req_ehs,
7010 struct ufs_ehs *rsp_ehs, int sg_cnt, struct scatterlist *sg_list,
7011 enum dma_data_direction dir)
7012{
7013 DECLARE_COMPLETION_ONSTACK(wait);
7014 const u32 tag = hba->reserved_slot;
7015 struct ufshcd_lrb *lrbp;
7016 int err = 0;
7017 int result;
7018 u8 upiu_flags;
7019 u8 *ehs_data;
7020 u16 ehs_len;
7021
7022 /* Protects use of hba->reserved_slot. */
7023 ufshcd_hold(hba, false);
7024 mutex_lock(&hba->dev_cmd.lock);
7025 down_read(&hba->clk_scaling_lock);
7026
7027 lrbp = &hba->lrb[tag];
7028 WARN_ON(lrbp->cmd);
7029 lrbp->cmd = NULL;
7030 lrbp->task_tag = tag;
7031 lrbp->lun = UFS_UPIU_RPMB_WLUN;
7032
7033 lrbp->intr_cmd = true;
7034 ufshcd_prepare_lrbp_crypto(NULL, lrbp);
7035 hba->dev_cmd.type = DEV_CMD_TYPE_RPMB;
7036
7037 /* Advanced RPMB starts from UFS 4.0, so its command type is UTP_CMD_TYPE_UFS_STORAGE */
7038 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE;
7039
7040 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, dir, 2);
7041
7042 /* update the task tag and LUN in the request upiu */
7043 req_upiu->header.dword_0 |= cpu_to_be32(upiu_flags << 16 | UFS_UPIU_RPMB_WLUN << 8 | tag);
7044
7045 /* copy the UPIU(contains CDB) request as it is */
7046 memcpy(lrbp->ucd_req_ptr, req_upiu, sizeof(*lrbp->ucd_req_ptr));
7047 /* Copy EHS, starting with byte32, immediately after the CDB package */
7048 memcpy(lrbp->ucd_req_ptr + 1, req_ehs, sizeof(*req_ehs));
7049
7050 if (dir != DMA_NONE && sg_list)
7051 ufshcd_sgl_to_prdt(hba, lrbp, sg_cnt, sg_list);
7052
7053 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
7054
7055 hba->dev_cmd.complete = &wait;
7056
7057 ufshcd_send_command(hba, tag);
7058
7059 err = ufshcd_wait_for_dev_cmd(hba, lrbp, ADVANCED_RPMB_REQ_TIMEOUT);
7060
7061 if (!err) {
7062 /* Just copy the upiu response as it is */
7063 memcpy(rsp_upiu, lrbp->ucd_rsp_ptr, sizeof(*rsp_upiu));
7064 /* Get the response UPIU result */
7065 result = ufshcd_get_rsp_upiu_result(lrbp->ucd_rsp_ptr);
7066
7067 ehs_len = be32_to_cpu(lrbp->ucd_rsp_ptr->header.dword_2) >> 24;
7068 /*
7069 * Since the bLength in EHS indicates the total size of the EHS Header and EHS Data
7070 * in 32 Byte units, the value of the bLength Request/Response for Advanced RPMB
7071 * Message is 02h
7072 */
7073 if (ehs_len == 2 && rsp_ehs) {
7074 /*
7075 * ucd_rsp_ptr points to a buffer with a length of 512 bytes
7076 * (ALIGNED_UPIU_SIZE = 512), and the EHS data just starts from byte32
7077 */
7078 ehs_data = (u8 *)lrbp->ucd_rsp_ptr + EHS_OFFSET_IN_RESPONSE;
7079 memcpy(rsp_ehs, ehs_data, ehs_len * 32);
7080 }
7081 }
7082
7083 up_read(&hba->clk_scaling_lock);
7084 mutex_unlock(&hba->dev_cmd.lock);
7085 ufshcd_release(hba);
7086 return err ? : result;
7087}
7088
7a3e97b0 7089/**
2acd76e7 7090 * ufshcd_eh_device_reset_handler() - Reset a single logical unit.
7a3e97b0
SY		 7091 * @cmd: SCSI command pointer
7092 *
7093 * Returns SUCCESS/FAILED
7094 */
3441da7d 7095static int ufshcd_eh_device_reset_handler(struct scsi_cmnd *cmd)
7a3e97b0 7096{
2acd76e7 7097 unsigned long flags, pending_reqs = 0, not_cleared = 0;
7a3e97b0
SY		 7098 struct Scsi_Host *host;
7099 struct ufs_hba *hba;
7a3e97b0
SY		 7100 u32 pos;
7101 int err;
35fc4cd3 7102 u8 resp = 0xF, lun;
7a3e97b0
SY		 7103
7104 host = cmd->device->host;
7105 hba = shost_priv(host);
7a3e97b0 7106
35fc4cd3
CG		 7107 lun = ufshcd_scsi_to_upiu_lun(cmd->device->lun);
7108 err = ufshcd_issue_tm_cmd(hba, lun, 0, UFS_LOGICAL_RESET, &resp);
e2933132 7109 if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
3441da7d
SRT		 7110 if (!err)
7111 err = resp;
7a3e97b0 7112 goto out;
e2933132 7113 }
7a3e97b0 7114
3441da7d 7115 /* clear the commands that were pending for corresponding LUN */
2acd76e7
BVA		 7116 spin_lock_irqsave(&hba->outstanding_lock, flags);
7117 for_each_set_bit(pos, &hba->outstanding_reqs, hba->nutrs)
7118 if (hba->lrb[pos].lun == lun)
7119 __set_bit(pos, &pending_reqs);
7120 hba->outstanding_reqs &= ~pending_reqs;
7121 spin_unlock_irqrestore(&hba->outstanding_lock, flags);
7122
7123 if (ufshcd_clear_cmds(hba, pending_reqs) < 0) {
7124 spin_lock_irqsave(&hba->outstanding_lock, flags);
7125 not_cleared = pending_reqs &
7126 ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
7127 hba->outstanding_reqs |= not_cleared;
7128 spin_unlock_irqrestore(&hba->outstanding_lock, flags);
7129
7130 dev_err(hba->dev, "%s: failed to clear requests %#lx\n",
7131 __func__, not_cleared);
3441da7d 7132 }
2acd76e7 7133 __ufshcd_transfer_req_compl(hba, pending_reqs & ~not_cleared);
7fabb77b 7134
7a3e97b0 7135out:
7fabb77b 7136 hba->req_abort_count = 0;
e965e5e0 7137 ufshcd_update_evt_hist(hba, UFS_EVT_DEV_RESET, (u32)err);
3441da7d
SRT		 7138 if (!err) {
7139 err = SUCCESS;
7140 } else {
7141 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err);
7142 err = FAILED;
7143 }
7a3e97b0
SY		 7144 return err;
7145}
7146
e0b299e3
GB		 7147static void ufshcd_set_req_abort_skip(struct ufs_hba *hba, unsigned long bitmap)
7148{
7149 struct ufshcd_lrb *lrbp;
7150 int tag;
7151
7152 for_each_set_bit(tag, &bitmap, hba->nutrs) {
7153 lrbp = &hba->lrb[tag];
7154 lrbp->req_abort_skip = true;
7155 }
7156}
7157
7a3e97b0 7158/**
307348f6 7159 * ufshcd_try_to_abort_task - abort a specific task
d23ec0b6
LJ		 7160 * @hba: Pointer to adapter instance
7161 * @tag: Task tag/index to be aborted
7a3e97b0 7162 *
f20810d8
SRT		 7163 * Abort the pending command in device by sending UFS_ABORT_TASK task management
7164 * command, and in host controller by clearing the door-bell register. There can
7165 * be race between controller sending the command to the device while abort is
7166 * issued. To avoid that, first issue UFS_QUERY_TASK to check if the command is
7167 * really issued and then try to abort it.
7168 *
307348f6
CG		 7169 * Returns zero on success, non-zero on failure
7170 */
7171static int ufshcd_try_to_abort_task(struct ufs_hba *hba, int tag)
7172{
7173 struct ufshcd_lrb *lrbp = &hba->lrb[tag];
7174 int err = 0;
7175 int poll_cnt;
7176 u8 resp = 0xF;
7177 u32 reg;
7178
7179 for (poll_cnt = 100; poll_cnt; poll_cnt--) {
7180 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag,
7181 UFS_QUERY_TASK, &resp);
7182 if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_SUCCEEDED) {
7183 /* cmd pending in the device */
7184 dev_err(hba->dev, "%s: cmd pending in the device. tag = %d\n",
7185 __func__, tag);
7186 break;
7187 } else if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
7188 /*
7189 * cmd not pending in the device, check if it is
7190 * in transition.
7191 */
7192 dev_err(hba->dev, "%s: cmd at tag %d not pending in the device.\n",
7193 __func__, tag);
7194 reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
7195 if (reg & (1 << tag)) {
7196 /* sleep for max. 200us to stabilize */
7197 usleep_range(100, 200);
7198 continue;
7199 }
7200 /* command completed already */
7201 dev_err(hba->dev, "%s: cmd at tag %d successfully cleared from DB.\n",
7202 __func__, tag);
7203 goto out;
7204 } else {
7205 dev_err(hba->dev,
7206 "%s: no response from device. tag = %d, err %d\n",
7207 __func__, tag, err);
7208 if (!err)
7209 err = resp; /* service response error */
7210 goto out;
7211 }
7212 }
7213
7214 if (!poll_cnt) {
7215 err = -EBUSY;
7216 goto out;
7217 }
7218
7219 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag,
7220 UFS_ABORT_TASK, &resp);
7221 if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
7222 if (!err) {
7223 err = resp; /* service response error */
7224 dev_err(hba->dev, "%s: issued. tag = %d, err %d\n",
7225 __func__, tag, err);
7226 }
7227 goto out;
7228 }
7229
d1a76446 7230 err = ufshcd_clear_cmds(hba, 1U << tag);
307348f6
CG		 7231 if (err)
7232 dev_err(hba->dev, "%s: Failed clearing cmd at tag %d, err %d\n",
7233 __func__, tag, err);
7234
7235out:
7236 return err;
7237}
7238
7239/**
7240 * ufshcd_abort - scsi host template eh_abort_handler callback
7241 * @cmd: SCSI command pointer
7242 *
7a3e97b0
SY		 7243 * Returns SUCCESS/FAILED
7244 */
7245static int ufshcd_abort(struct scsi_cmnd *cmd)
7246{
4728ab4a
BVA		 7247 struct Scsi_Host *host = cmd->device->host;
7248 struct ufs_hba *hba = shost_priv(host);
3f2c1002 7249 int tag = scsi_cmd_to_rq(cmd)->tag;
4728ab4a 7250 struct ufshcd_lrb *lrbp = &hba->lrb[tag];
7a3e97b0 7251 unsigned long flags;
64180742 7252 int err = FAILED;
1fbaa02d 7253 bool outstanding;
e9d501b1 7254 u32 reg;
7a3e97b0 7255
4728ab4a 7256 WARN_ONCE(tag < 0, "Invalid tag %d\n", tag);
7a3e97b0 7257
1ab27c9c 7258 ufshcd_hold(hba, false);
14497328 7259 reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
64180742 7260 /* If command is already aborted/completed, return FAILED. */
14497328
YG		 7261 if (!(test_bit(tag, &hba->outstanding_reqs))) {
7262 dev_err(hba->dev,
7263 "%s: cmd at tag %d already completed, outstanding=0x%lx, doorbell=0x%x\n",
7264 __func__, tag, hba->outstanding_reqs, reg);
64180742 7265 goto release;
14497328 7266 }
7a3e97b0 7267
66cc820f 7268 /* Print Transfer Request of aborted task */
d87a1f6d 7269 dev_info(hba->dev, "%s: Device abort task at tag %d\n", __func__, tag);
66cc820f 7270
7fabb77b
GB		 7271 /*
7272 * Print detailed info about aborted request.
7273 * As more than one request might get aborted at the same time,
7274 * print full information only for the first aborted request in order
7275 * to reduce repeated printouts. For other aborted requests only print
7276 * basic details.
7277 */
7a7e66c6 7278 scsi_print_command(cmd);
7fabb77b 7279 if (!hba->req_abort_count) {
e965e5e0
SC		 7280 ufshcd_update_evt_hist(hba, UFS_EVT_ABORT, tag);
7281 ufshcd_print_evt_hist(hba);
6ba65588 7282 ufshcd_print_host_state(hba);
7fabb77b
GB		 7283 ufshcd_print_pwr_info(hba);
7284 ufshcd_print_trs(hba, 1 << tag, true);
7285 } else {
7286 ufshcd_print_trs(hba, 1 << tag, false);
7287 }
7288 hba->req_abort_count++;
e0b299e3 7289
d87a1f6d
BH		 7290 if (!(reg & (1 << tag))) {
7291 dev_err(hba->dev,
7292 "%s: cmd was completed, but without a notifying intr, tag = %d",
7293 __func__, tag);
11682523 7294 __ufshcd_transfer_req_compl(hba, 1UL << tag);
64180742 7295 goto release;
d87a1f6d
BH		 7296 }
7297
7a7e66c6
CG		 7298 /*
7299 * Task abort to the device W-LUN is illegal. When this command
7300 * will fail, due to spec violation, scsi err handling next step
7301 * will be to send LU reset which, again, is a spec violation.
7302 * To avoid these unnecessary/illegal steps, first we clean up
a45f9371 7303 * the lrb taken by this cmd and re-set it in outstanding_reqs,
88b09900 7304 * then queue the eh_work and bail.
7a7e66c6
CG		 7305 */
7306 if (lrbp->lun == UFS_UPIU_UFS_DEVICE_WLUN) {
7307 ufshcd_update_evt_hist(hba, UFS_EVT_ABORT, lrbp->lun);
64180742 7308
7a7e66c6 7309 spin_lock_irqsave(host->host_lock, flags);
a45f9371 7310 hba->force_reset = true;
88b09900 7311 ufshcd_schedule_eh_work(hba);
7a7e66c6 7312 spin_unlock_irqrestore(host->host_lock, flags);
64180742 7313 goto release;
7a7e66c6
CG		 7314 }
7315
e0b299e3 7316 /* Skip task abort in case previous aborts failed and report failure */
64180742
BVA		 7317 if (lrbp->req_abort_skip) {
7318 dev_err(hba->dev, "%s: skipping abort\n", __func__);
7319 ufshcd_set_req_abort_skip(hba, hba->outstanding_reqs);
7320 goto release;
7321 }
f20810d8 7322
64180742
BVA		 7323 err = ufshcd_try_to_abort_task(hba, tag);
7324 if (err) {
f20810d8 7325 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err);
e0b299e3 7326 ufshcd_set_req_abort_skip(hba, hba->outstanding_reqs);
f20810d8 7327 err = FAILED;
64180742 7328 goto release;
f20810d8
SRT		 7329 }
7330
1fbaa02d
BVA		 7331 /*
7332 * Clear the corresponding bit from outstanding_reqs since the command
7333 * has been aborted successfully.
7334 */
7335 spin_lock_irqsave(&hba->outstanding_lock, flags);
7336 outstanding = __test_and_clear_bit(tag, &hba->outstanding_reqs);
7337 spin_unlock_irqrestore(&hba->outstanding_lock, flags);
7338
7339 if (outstanding)
7340 ufshcd_release_scsi_cmd(hba, lrbp);
7341
64180742
BVA		 7342 err = SUCCESS;
7343
7344release:
7345 /* Matches the ufshcd_hold() call at the start of this function. */
1ab27c9c 7346 ufshcd_release(hba);
7a3e97b0
SY		 7347 return err;
7348}
7349
3441da7d
SRT		 7350/**
7351 * ufshcd_host_reset_and_restore - reset and restore host controller
7352 * @hba: per-adapter instance
7353 *
7354 * Note that host controller reset may issue DME_RESET to
7355 * local and remote (device) Uni-Pro stack and the attributes
7356 * are reset to default state.
7357 *
7358 * Returns zero on success, non-zero on failure
7359 */
7360static int ufshcd_host_reset_and_restore(struct ufs_hba *hba)
7361{
7362 int err;
3441da7d 7363
2df74b69
CG		 7364 /*
7365 * Stop the host controller and complete the requests
7366 * cleared by h/w
7367 */
facc239c 7368 ufshpb_toggle_state(hba, HPB_PRESENT, HPB_RESET);
5cac1095 7369 ufshcd_hba_stop(hba);
2df74b69 7370 hba->silence_err_logs = true;
11682523 7371 ufshcd_complete_requests(hba);
2df74b69 7372 hba->silence_err_logs = false;
3441da7d 7373
a3cd5ec5 7374 /* scale up clocks to max frequency before full reinitialization */
52a51801 7375 ufshcd_scale_clks(hba, true);
a3cd5ec5 7376
3441da7d 7377 err = ufshcd_hba_enable(hba);
3441da7d
SRT		 7378
7379 /* Establish the link again and restore the device */
1918651f 7380 if (!err)
4ee7ee53
JK		 7381 err = ufshcd_probe_hba(hba, false);
7382
3441da7d
SRT		 7383 if (err)
7384 dev_err(hba->dev, "%s: Host init failed %d\n", __func__, err);
e965e5e0 7385 ufshcd_update_evt_hist(hba, UFS_EVT_HOST_RESET, (u32)err);
3441da7d
SRT		 7386 return err;
7387}
7388
7389/**
7390 * ufshcd_reset_and_restore - reset and re-initialize host/device
7391 * @hba: per-adapter instance
7392 *
7393 * Reset and recover device, host and re-establish link. This
7394 * is helpful to recover the communication in fatal error conditions.
7395 *
7396 * Returns zero on success, non-zero on failure
7397 */
7398static int ufshcd_reset_and_restore(struct ufs_hba *hba)
7399{
54a40453
AH		 7400 u32 saved_err = 0;
7401 u32 saved_uic_err = 0;
3441da7d 7402 int err = 0;
4db7a236 7403 unsigned long flags;
1d337ec2 7404 int retries = MAX_HOST_RESET_RETRIES;
3441da7d 7405
4db7a236 7406 spin_lock_irqsave(hba->host->host_lock, flags);
1d337ec2 7407 do {
54a40453
AH		 7408 /*
7409 * This is a fresh start, cache and clear saved error first,
7410 * in case new error generated during reset and restore.
7411 */
7412 saved_err |= hba->saved_err;
7413 saved_uic_err |= hba->saved_uic_err;
7414 hba->saved_err = 0;
7415 hba->saved_uic_err = 0;
7416 hba->force_reset = false;
7417 hba->ufshcd_state = UFSHCD_STATE_RESET;
7418 spin_unlock_irqrestore(hba->host->host_lock, flags);
7419
d8d9f793 7420 /* Reset the attached device */
31a5d9ca 7421 ufshcd_device_reset(hba);
d8d9f793 7422
1d337ec2 7423 err = ufshcd_host_reset_and_restore(hba);
54a40453
AH		 7424
7425 spin_lock_irqsave(hba->host->host_lock, flags);
7426 if (err)
7427 continue;
7428 /* Do not exit unless operational or dead */
7429 if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL &&
7430 hba->ufshcd_state != UFSHCD_STATE_ERROR &&
7431 hba->ufshcd_state != UFSHCD_STATE_EH_SCHEDULED_NON_FATAL)
7432 err = -EAGAIN;
1d337ec2 7433 } while (err && --retries);
3441da7d 7434
4db7a236
CG		 7435 /*
7436 * Inform scsi mid-layer that we did reset and allow to handle
7437 * Unit Attention properly.
7438 */
7439 scsi_report_bus_reset(hba->host, 0);
7440 if (err) {
88a92d6a 7441 hba->ufshcd_state = UFSHCD_STATE_ERROR;
4db7a236
CG		 7442 hba->saved_err |= saved_err;
7443 hba->saved_uic_err |= saved_uic_err;
7444 }
7445 spin_unlock_irqrestore(hba->host->host_lock, flags);
7446
3441da7d
SRT		 7447 return err;
7448}
7449
7450/**
7451 * ufshcd_eh_host_reset_handler - host reset handler registered to scsi layer
8aa29f19 7452 * @cmd: SCSI command pointer
3441da7d
SRT		 7453 *
7454 * Returns SUCCESS/FAILED
7455 */
7456static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd)
7457{
4db7a236 7458 int err = SUCCESS;
3441da7d
SRT		 7459 unsigned long flags;
7460 struct ufs_hba *hba;
7461
7462 hba = shost_priv(cmd->device->host);
7463
4db7a236
CG		 7464 spin_lock_irqsave(hba->host->host_lock, flags);
7465 hba->force_reset = true;
88b09900 7466 ufshcd_schedule_eh_work(hba);
4db7a236 7467 dev_err(hba->dev, "%s: reset in progress - 1\n", __func__);
3441da7d
SRT		 7468 spin_unlock_irqrestore(hba->host->host_lock, flags);
7469
88b09900 7470 flush_work(&hba->eh_work);
3441da7d
SRT		 7471
7472 spin_lock_irqsave(hba->host->host_lock, flags);
4db7a236 7473 if (hba->ufshcd_state == UFSHCD_STATE_ERROR)
3441da7d 7474 err = FAILED;
3441da7d
SRT		 7475 spin_unlock_irqrestore(hba->host->host_lock, flags);
7476
7477 return err;
7478}
7479
3a4bf06d
YG		 7480/**
7481 * ufshcd_get_max_icc_level - calculate the ICC level
7482 * @sup_curr_uA: max. current supported by the regulator
7483 * @start_scan: row at the desc table to start scan from
7484 * @buff: power descriptor buffer
7485 *
7486 * Returns calculated max ICC level for specific regulator
7487 */
35d11ec2
KK		 7488static u32 ufshcd_get_max_icc_level(int sup_curr_uA, u32 start_scan,
7489 const char *buff)
3a4bf06d
YG		 7490{
7491 int i;
7492 int curr_uA;
7493 u16 data;
7494 u16 unit;
7495
7496 for (i = start_scan; i >= 0; i--) {
9d3ab17e 7497 data = get_unaligned_be16(&buff[2 * i]);
3a4bf06d
YG		 7498 unit = (data & ATTR_ICC_LVL_UNIT_MASK) >>
7499 ATTR_ICC_LVL_UNIT_OFFSET;
7500 curr_uA = data & ATTR_ICC_LVL_VALUE_MASK;
7501 switch (unit) {
7502 case UFSHCD_NANO_AMP:
7503 curr_uA = curr_uA / 1000;
7504 break;
7505 case UFSHCD_MILI_AMP:
7506 curr_uA = curr_uA * 1000;
7507 break;
7508 case UFSHCD_AMP:
7509 curr_uA = curr_uA * 1000 * 1000;
7510 break;
7511 case UFSHCD_MICRO_AMP:
7512 default:
7513 break;
7514 }
7515 if (sup_curr_uA >= curr_uA)
7516 break;
7517 }
7518 if (i < 0) {
7519 i = 0;
7520 pr_err("%s: Couldn't find valid icc_level = %d", __func__, i);
7521 }
7522
7523 return (u32)i;
7524}
7525
7526/**
11eea9b3 7527 * ufshcd_find_max_sup_active_icc_level - calculate the max ICC level
3a4bf06d
YG		 7528 * In case regulators are not initialized we'll return 0
7529 * @hba: per-adapter instance
7530 * @desc_buf: power descriptor buffer to extract ICC levels from.
3a4bf06d
YG		 7531 *
7532 * Returns calculated ICC level
7533 */
7534static u32 ufshcd_find_max_sup_active_icc_level(struct ufs_hba *hba,
01a0d515 7535 const u8 *desc_buf)
3a4bf06d
YG		 7536{
7537 u32 icc_level = 0;
7538
7539 if (!hba->vreg_info.vcc || !hba->vreg_info.vccq ||
7540 !hba->vreg_info.vccq2) {
71bb9ab6
AH		 7541 /*
7542 * Using dev_dbg to avoid messages during runtime PM to avoid
7543 * never-ending cycles of messages written back to storage by
7544 * user space causing runtime resume, causing more messages and
7545 * so on.
7546 */
7547 dev_dbg(hba->dev,
3a4bf06d
YG		 7548 "%s: Regulator capability was not set, actvIccLevel=%d",
7549 __func__, icc_level);
7550 goto out;
7551 }
7552
0873045f 7553 if (hba->vreg_info.vcc->max_uA)
3a4bf06d
YG		 7554 icc_level = ufshcd_get_max_icc_level(
7555 hba->vreg_info.vcc->max_uA,
7556 POWER_DESC_MAX_ACTV_ICC_LVLS - 1,
7557 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCC_0]);
7558
0873045f 7559 if (hba->vreg_info.vccq->max_uA)
3a4bf06d
YG		 7560 icc_level = ufshcd_get_max_icc_level(
7561 hba->vreg_info.vccq->max_uA,
7562 icc_level,
7563 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ_0]);
7564
0873045f 7565 if (hba->vreg_info.vccq2->max_uA)
3a4bf06d
YG		 7566 icc_level = ufshcd_get_max_icc_level(
7567 hba->vreg_info.vccq2->max_uA,
7568 icc_level,
7569 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ2_0]);
7570out:
7571 return icc_level;
7572}
7573
e89860f1 7574static void ufshcd_set_active_icc_lvl(struct ufs_hba *hba)
3a4bf06d
YG		 7575{
7576 int ret;
bbe21d7a 7577 u8 *desc_buf;
e89860f1 7578 u32 icc_level;
bbe21d7a 7579
f2a89b07 7580 desc_buf = kzalloc(QUERY_DESC_MAX_SIZE, GFP_KERNEL);
bbe21d7a
KC		 7581 if (!desc_buf)
7582 return;
3a4bf06d 7583
c4607a09 7584 ret = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_POWER, 0, 0,
f2a89b07 7585 desc_buf, QUERY_DESC_MAX_SIZE);
3a4bf06d
YG		 7586 if (ret) {
7587 dev_err(hba->dev,
f2a89b07
AS		 7588 "%s: Failed reading power descriptor ret = %d",
7589 __func__, ret);
bbe21d7a 7590 goto out;
3a4bf06d
YG		 7591 }
7592
01a0d515 7593 icc_level = ufshcd_find_max_sup_active_icc_level(hba, desc_buf);
e89860f1 7594 dev_dbg(hba->dev, "%s: setting icc_level 0x%x", __func__, icc_level);
3a4bf06d 7595
dbd34a61 7596 ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
e89860f1 7597 QUERY_ATTR_IDN_ACTIVE_ICC_LVL, 0, 0, &icc_level);
3a4bf06d
YG		 7598
7599 if (ret)
7600 dev_err(hba->dev,
7601 "%s: Failed configuring bActiveICCLevel = %d ret = %d",
e89860f1 7602 __func__, icc_level, ret);
3a4bf06d 7603
bbe21d7a
KC		 7604out:
7605 kfree(desc_buf);
3a4bf06d
YG		 7606}
7607
fb276f77
CG		 7608static inline void ufshcd_blk_pm_runtime_init(struct scsi_device *sdev)
7609{
7610 scsi_autopm_get_device(sdev);
7611 blk_pm_runtime_init(sdev->request_queue, &sdev->sdev_gendev);
7612 if (sdev->rpm_autosuspend)
7613 pm_runtime_set_autosuspend_delay(&sdev->sdev_gendev,
7614 RPM_AUTOSUSPEND_DELAY_MS);
7615 scsi_autopm_put_device(sdev);
7616}
7617
2a8fa600
SJ		 7618/**
7619 * ufshcd_scsi_add_wlus - Adds required W-LUs
7620 * @hba: per-adapter instance
7621 *
7622 * UFS device specification requires the UFS devices to support 4 well known
7623 * logical units:
7624 * "REPORT_LUNS" (address: 01h)
7625 * "UFS Device" (address: 50h)
7626 * "RPMB" (address: 44h)
7627 * "BOOT" (address: 30h)
7628 * UFS device's power management needs to be controlled by "POWER CONDITION"
7629 * field of SSU (START STOP UNIT) command. But this "power condition" field
7630 * will take effect only when its sent to "UFS device" well known logical unit
7631 * hence we require the scsi_device instance to represent this logical unit in
7632 * order for the UFS host driver to send the SSU command for power management.
8aa29f19 7633 *
2a8fa600
SJ		 7634 * We also require the scsi_device instance for "RPMB" (Replay Protected Memory
7635 * Block) LU so user space process can control this LU. User space may also
7636 * want to have access to BOOT LU.
8aa29f19 7637 *
2a8fa600
SJ		 7638 * This function adds scsi device instances for each of all well known LUs
7639 * (except "REPORT LUNS" LU).
7640 *
7641 * Returns zero on success (all required W-LUs are added successfully),
7642 * non-zero error value on failure (if failed to add any of the required W-LU).
7643 */
7644static int ufshcd_scsi_add_wlus(struct ufs_hba *hba)
7645{
7646 int ret = 0;
59830c09 7647 struct scsi_device *sdev_boot, *sdev_rpmb;
2a8fa600 7648
e2106584 7649 hba->ufs_device_wlun = __scsi_add_device(hba->host, 0, 0,
2a8fa600 7650 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_UFS_DEVICE_WLUN), NULL);
e2106584
BVA		 7651 if (IS_ERR(hba->ufs_device_wlun)) {
7652 ret = PTR_ERR(hba->ufs_device_wlun);
7653 hba->ufs_device_wlun = NULL;
2a8fa600
SJ		 7654 goto out;
7655 }
e2106584 7656 scsi_device_put(hba->ufs_device_wlun);
2a8fa600 7657
59830c09 7658 sdev_rpmb = __scsi_add_device(hba->host, 0, 0,
2a8fa600 7659 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_RPMB_WLUN), NULL);
59830c09
BVA		 7660 if (IS_ERR(sdev_rpmb)) {
7661 ret = PTR_ERR(sdev_rpmb);
e2106584 7662 goto remove_ufs_device_wlun;
2a8fa600 7663 }
59830c09
BVA		 7664 ufshcd_blk_pm_runtime_init(sdev_rpmb);
7665 scsi_device_put(sdev_rpmb);
3d21fbde
HK		 7666
7667 sdev_boot = __scsi_add_device(hba->host, 0, 0,
7668 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_BOOT_WLUN), NULL);
fb276f77 7669 if (IS_ERR(sdev_boot)) {
3d21fbde 7670 dev_err(hba->dev, "%s: BOOT WLUN not found\n", __func__);
fb276f77
CG		 7671 } else {
7672 ufshcd_blk_pm_runtime_init(sdev_boot);
3d21fbde 7673 scsi_device_put(sdev_boot);
fb276f77 7674 }
2a8fa600
SJ		 7675 goto out;
7676
e2106584
BVA		 7677remove_ufs_device_wlun:
7678 scsi_remove_device(hba->ufs_device_wlun);
2a8fa600
SJ		 7679out:
7680 return ret;
7681}
7682
35d11ec2 7683static void ufshcd_wb_probe(struct ufs_hba *hba, const u8 *desc_buf)
3d17b9b5 7684{
a7f1e69d 7685 struct ufs_dev_info *dev_info = &hba->dev_info;
6f8d5a6a
SC		 7686 u8 lun;
7687 u32 d_lu_wb_buf_alloc;
e8d03813 7688 u32 ext_ufs_feature;
6f8d5a6a 7689
817d7e14
SC		 7690 if (!ufshcd_is_wb_allowed(hba))
7691 return;
f681d107 7692
a7f1e69d
SC		 7693 /*
7694 * Probe WB only for UFS-2.2 and UFS-3.1 (and later) devices or
7695 * UFS devices with quirk UFS_DEVICE_QUIRK_SUPPORT_EXTENDED_FEATURES
7696 * enabled
7697 */
7698 if (!(dev_info->wspecversion >= 0x310 ||
7699 dev_info->wspecversion == 0x220 ||
7700 (hba->dev_quirks & UFS_DEVICE_QUIRK_SUPPORT_EXTENDED_FEATURES)))
7701 goto wb_disabled;
817d7e14 7702
e8d03813
BH		 7703 ext_ufs_feature = get_unaligned_be32(desc_buf +
7704 DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP);
817d7e14 7705
e8d03813 7706 if (!(ext_ufs_feature & UFS_DEV_WRITE_BOOSTER_SUP))
817d7e14
SC		 7707 goto wb_disabled;
7708
3d17b9b5 7709 /*
ae1ce1fc
BH		 7710 * WB may be supported but not configured while provisioning. The spec
7711 * says, in dedicated wb buffer mode, a max of 1 lun would have wb
7712 * buffer configured.
3d17b9b5 7713 */
4cd48995 7714 dev_info->wb_buffer_type = desc_buf[DEVICE_DESC_PARAM_WB_TYPE];
3d17b9b5 7715
a7f1e69d 7716 dev_info->b_presrv_uspc_en =
3d17b9b5
AD		 7717 desc_buf[DEVICE_DESC_PARAM_WB_PRESRV_USRSPC_EN];
7718
4cd48995 7719 if (dev_info->wb_buffer_type == WB_BUF_MODE_SHARED) {
e8d03813
BH		 7720 if (!get_unaligned_be32(desc_buf +
7721 DEVICE_DESC_PARAM_WB_SHARED_ALLOC_UNITS))
6f8d5a6a
SC		 7722 goto wb_disabled;
7723 } else {
7724 for (lun = 0; lun < UFS_UPIU_MAX_WB_LUN_ID; lun++) {
7725 d_lu_wb_buf_alloc = 0;
7726 ufshcd_read_unit_desc_param(hba,
7727 lun,
7728 UNIT_DESC_PARAM_WB_BUF_ALLOC_UNITS,
7729 (u8 *)&d_lu_wb_buf_alloc,
7730 sizeof(d_lu_wb_buf_alloc));
7731 if (d_lu_wb_buf_alloc) {
a7f1e69d 7732 dev_info->wb_dedicated_lu = lun;
6f8d5a6a
SC		 7733 break;
7734 }
7735 }
817d7e14 7736
6f8d5a6a
SC		 7737 if (!d_lu_wb_buf_alloc)
7738 goto wb_disabled;
7739 }
f681d107
JC		 7740
7741 if (!ufshcd_is_wb_buf_lifetime_available(hba))
7742 goto wb_disabled;
7743
817d7e14
SC		 7744 return;
7745
7746wb_disabled:
7747 hba->caps &= ~UFSHCD_CAP_WB_EN;
7748}
7749
35d11ec2 7750static void ufshcd_temp_notif_probe(struct ufs_hba *hba, const u8 *desc_buf)
e88e2d32
AA		 7751{
7752 struct ufs_dev_info *dev_info = &hba->dev_info;
7753 u32 ext_ufs_feature;
7754 u8 mask = 0;
7755
7756 if (!(hba->caps & UFSHCD_CAP_TEMP_NOTIF) || dev_info->wspecversion < 0x300)
7757 return;
7758
7759 ext_ufs_feature = get_unaligned_be32(desc_buf + DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP);
7760
7761 if (ext_ufs_feature & UFS_DEV_LOW_TEMP_NOTIF)
7762 mask |= MASK_EE_TOO_LOW_TEMP;
7763
7764 if (ext_ufs_feature & UFS_DEV_HIGH_TEMP_NOTIF)
7765 mask |= MASK_EE_TOO_HIGH_TEMP;
7766
7767 if (mask) {
7768 ufshcd_enable_ee(hba, mask);
7769 ufs_hwmon_probe(hba, mask);
7770 }
7771}
7772
6e1d850a
AD		 7773static void ufshcd_ext_iid_probe(struct ufs_hba *hba, u8 *desc_buf)
7774{
7775 struct ufs_dev_info *dev_info = &hba->dev_info;
7776 u32 ext_ufs_feature;
7777 u32 ext_iid_en = 0;
7778 int err;
7779
7780 /* Only UFS-4.0 and above may support EXT_IID */
7781 if (dev_info->wspecversion < 0x400)
7782 goto out;
7783
7784 ext_ufs_feature = get_unaligned_be32(desc_buf +
7785 DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP);
7786 if (!(ext_ufs_feature & UFS_DEV_EXT_IID_SUP))
7787 goto out;
7788
7789 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
7790 QUERY_ATTR_IDN_EXT_IID_EN, 0, 0, &ext_iid_en);
7791 if (err)
7792 dev_err(hba->dev, "failed reading bEXTIIDEn. err = %d\n", err);
7793
7794out:
7795 dev_info->b_ext_iid_en = ext_iid_en;
7796}
7797
aead21f3
BVA		 7798void ufshcd_fixup_dev_quirks(struct ufs_hba *hba,
7799 const struct ufs_dev_quirk *fixups)
817d7e14 7800{
aead21f3 7801 const struct ufs_dev_quirk *f;
817d7e14
SC		 7802 struct ufs_dev_info *dev_info = &hba->dev_info;
7803
8db269a5
SC		 7804 if (!fixups)
7805 return;
7806
7807 for (f = fixups; f->quirk; f++) {
817d7e14
SC		 7808 if ((f->wmanufacturerid == dev_info->wmanufacturerid ||
7809 f->wmanufacturerid == UFS_ANY_VENDOR) &&
7810 ((dev_info->model &&
7811 STR_PRFX_EQUAL(f->model, dev_info->model)) ||
7812 !strcmp(f->model, UFS_ANY_MODEL)))
7813 hba->dev_quirks |= f->quirk;
7814 }
3d17b9b5 7815}
8db269a5 7816EXPORT_SYMBOL_GPL(ufshcd_fixup_dev_quirks);
3d17b9b5 7817
c28c00ba
SC		 7818static void ufs_fixup_device_setup(struct ufs_hba *hba)
7819{
7820 /* fix by general quirk table */
8db269a5 7821 ufshcd_fixup_dev_quirks(hba, ufs_fixups);
c28c00ba
SC		 7822
7823 /* allow vendors to fix quirks */
7824 ufshcd_vops_fixup_dev_quirks(hba);
7825}
7826
09750066 7827static int ufs_get_device_desc(struct ufs_hba *hba)
c58ab7aa
YG		 7828{
7829 int err;
7830 u8 model_index;
f02bc975 7831 u8 b_ufs_feature_sup;
bbe21d7a 7832 u8 *desc_buf;
09750066 7833 struct ufs_dev_info *dev_info = &hba->dev_info;
4b828fe1 7834
f2a89b07 7835 desc_buf = kzalloc(QUERY_DESC_MAX_SIZE, GFP_KERNEL);
bbe21d7a
KC		 7836 if (!desc_buf) {
7837 err = -ENOMEM;
7838 goto out;
7839 }
c58ab7aa 7840
c4607a09 7841 err = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_DEVICE, 0, 0, desc_buf,
f2a89b07 7842 QUERY_DESC_MAX_SIZE);
c58ab7aa
YG		 7843 if (err) {
7844 dev_err(hba->dev, "%s: Failed reading Device Desc. err = %d\n",
7845 __func__, err);
7846 goto out;
7847 }
7848
7849 /*
7850 * getting vendor (manufacturerID) and Bank Index in big endian
7851 * format
7852 */
09750066 7853 dev_info->wmanufacturerid = desc_buf[DEVICE_DESC_PARAM_MANF_ID] << 8 |
c58ab7aa
YG		 7854 desc_buf[DEVICE_DESC_PARAM_MANF_ID + 1];
7855
09f17791
CG		 7856 /* getting Specification Version in big endian format */
7857 dev_info->wspecversion = desc_buf[DEVICE_DESC_PARAM_SPEC_VER] << 8 |
7858 desc_buf[DEVICE_DESC_PARAM_SPEC_VER + 1];
f02bc975 7859 b_ufs_feature_sup = desc_buf[DEVICE_DESC_PARAM_UFS_FEAT];
09f17791 7860
c58ab7aa 7861 model_index = desc_buf[DEVICE_DESC_PARAM_PRDCT_NAME];
3d17b9b5 7862
f02bc975
DP		 7863 if (dev_info->wspecversion >= UFS_DEV_HPB_SUPPORT_VERSION &&
7864 (b_ufs_feature_sup & UFS_DEV_HPB_SUPPORT)) {
41d8a933
DP		 7865 bool hpb_en = false;
7866
f02bc975 7867 ufshpb_get_dev_info(hba, desc_buf);
41d8a933
DP		 7868
7869 if (!ufshpb_is_legacy(hba))
7870 err = ufshcd_query_flag_retry(hba,
7871 UPIU_QUERY_OPCODE_READ_FLAG,
7872 QUERY_FLAG_IDN_HPB_EN, 0,
7873 &hpb_en);
7874
7875 if (ufshpb_is_legacy(hba) || (!err && hpb_en))
7876 dev_info->hpb_enabled = true;
f02bc975
DP		 7877 }
7878
4b828fe1 7879 err = ufshcd_read_string_desc(hba, model_index,
09750066 7880 &dev_info->model, SD_ASCII_STD);
4b828fe1 7881 if (err < 0) {
c58ab7aa
YG		 7882 dev_err(hba->dev, "%s: Failed reading Product Name. err = %d\n",
7883 __func__, err);
7884 goto out;
7885 }
7886
b294ff3e
AD		 7887 hba->luns_avail = desc_buf[DEVICE_DESC_PARAM_NUM_LU] +
7888 desc_buf[DEVICE_DESC_PARAM_NUM_WLU];
7889
817d7e14
SC		 7890 ufs_fixup_device_setup(hba);
7891
a7f1e69d 7892 ufshcd_wb_probe(hba, desc_buf);
817d7e14 7893
e88e2d32
AA		 7894 ufshcd_temp_notif_probe(hba, desc_buf);
7895
6e1d850a
AD		 7896 if (hba->ext_iid_sup)
7897 ufshcd_ext_iid_probe(hba, desc_buf);
7898
4b828fe1
TW		 7899 /*
7900 * ufshcd_read_string_desc returns size of the string
7901 * reset the error value
7902 */
7903 err = 0;
c58ab7aa
YG		 7904
7905out:
bbe21d7a 7906 kfree(desc_buf);
c58ab7aa
YG		 7907 return err;
7908}
7909
09750066 7910static void ufs_put_device_desc(struct ufs_hba *hba)
4b828fe1 7911{
09750066
BH		 7912 struct ufs_dev_info *dev_info = &hba->dev_info;
7913
7914 kfree(dev_info->model);
7915 dev_info->model = NULL;
4b828fe1
TW		 7916}
7917
37113106
YG		 7918/**
7919 * ufshcd_tune_pa_tactivate - Tunes PA_TActivate of local UniPro
7920 * @hba: per-adapter instance
7921 *
7922 * PA_TActivate parameter can be tuned manually if UniPro version is less than
7923 * 1.61. PA_TActivate needs to be greater than or equal to peerM-PHY's
7924 * RX_MIN_ACTIVATETIME_CAPABILITY attribute. This optimal value can help reduce
7925 * the hibern8 exit latency.
7926 *
7927 * Returns zero on success, non-zero error value on failure.
7928 */
7929static int ufshcd_tune_pa_tactivate(struct ufs_hba *hba)
7930{
7931 int ret = 0;
7932 u32 peer_rx_min_activatetime = 0, tuned_pa_tactivate;
7933
7934 ret = ufshcd_dme_peer_get(hba,
7935 UIC_ARG_MIB_SEL(
7936 RX_MIN_ACTIVATETIME_CAPABILITY,
7937 UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)),
7938 &peer_rx_min_activatetime);
7939 if (ret)
7940 goto out;
7941
7942 /* make sure proper unit conversion is applied */
7943 tuned_pa_tactivate =
7944 ((peer_rx_min_activatetime * RX_MIN_ACTIVATETIME_UNIT_US)
7945 / PA_TACTIVATE_TIME_UNIT_US);
7946 ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE),
7947 tuned_pa_tactivate);
7948
7949out:
7950 return ret;
7951}
7952
7953/**
7954 * ufshcd_tune_pa_hibern8time - Tunes PA_Hibern8Time of local UniPro
7955 * @hba: per-adapter instance
7956 *
7957 * PA_Hibern8Time parameter can be tuned manually if UniPro version is less than
7958 * 1.61. PA_Hibern8Time needs to be maximum of local M-PHY's
7959 * TX_HIBERN8TIME_CAPABILITY & peer M-PHY's RX_HIBERN8TIME_CAPABILITY.
7960 * This optimal value can help reduce the hibern8 exit latency.
7961 *
7962 * Returns zero on success, non-zero error value on failure.
7963 */
7964static int ufshcd_tune_pa_hibern8time(struct ufs_hba *hba)
7965{
7966 int ret = 0;
7967 u32 local_tx_hibern8_time_cap = 0, peer_rx_hibern8_time_cap = 0;
7968 u32 max_hibern8_time, tuned_pa_hibern8time;
7969
7970 ret = ufshcd_dme_get(hba,
7971 UIC_ARG_MIB_SEL(TX_HIBERN8TIME_CAPABILITY,
7972 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
7973 &local_tx_hibern8_time_cap);
7974 if (ret)
7975 goto out;
7976
7977 ret = ufshcd_dme_peer_get(hba,
7978 UIC_ARG_MIB_SEL(RX_HIBERN8TIME_CAPABILITY,
7979 UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)),
7980 &peer_rx_hibern8_time_cap);
7981 if (ret)
7982 goto out;
7983
7984 max_hibern8_time = max(local_tx_hibern8_time_cap,
7985 peer_rx_hibern8_time_cap);
7986 /* make sure proper unit conversion is applied */
7987 tuned_pa_hibern8time = ((max_hibern8_time * HIBERN8TIME_UNIT_US)
7988 / PA_HIBERN8_TIME_UNIT_US);
7989 ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HIBERN8TIME),
7990 tuned_pa_hibern8time);
7991out:
7992 return ret;
7993}
7994
c6a6db43 7995/**
7996 * ufshcd_quirk_tune_host_pa_tactivate - Ensures that host PA_TACTIVATE is
7997 * less than device PA_TACTIVATE time.
7998 * @hba: per-adapter instance
7999 *
8000 * Some UFS devices require host PA_TACTIVATE to be lower than device
8001 * PA_TACTIVATE, we need to enable UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE quirk
8002 * for such devices.
8003 *
8004 * Returns zero on success, non-zero error value on failure.
8005 */
8006static int ufshcd_quirk_tune_host_pa_tactivate(struct ufs_hba *hba)
8007{
8008 int ret = 0;
8009 u32 granularity, peer_granularity;
8010 u32 pa_tactivate, peer_pa_tactivate;
8011 u32 pa_tactivate_us, peer_pa_tactivate_us;
35d11ec2 8012 static const u8 gran_to_us_table[] = {1, 4, 8, 16, 32, 100};
c6a6db43 8013
8014 ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_GRANULARITY),
8015 &granularity);
8016 if (ret)
8017 goto out;
8018
8019 ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_GRANULARITY),
8020 &peer_granularity);
8021 if (ret)
8022 goto out;
8023
8024 if ((granularity < PA_GRANULARITY_MIN_VAL) ||
8025 (granularity > PA_GRANULARITY_MAX_VAL)) {
8026 dev_err(hba->dev, "%s: invalid host PA_GRANULARITY %d",
8027 __func__, granularity);
8028 return -EINVAL;
8029 }
8030
8031 if ((peer_granularity < PA_GRANULARITY_MIN_VAL) ||
8032 (peer_granularity > PA_GRANULARITY_MAX_VAL)) {
8033 dev_err(hba->dev, "%s: invalid device PA_GRANULARITY %d",
8034 __func__, peer_granularity);
8035 return -EINVAL;
8036 }
8037
8038 ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_TACTIVATE), &pa_tactivate);
8039 if (ret)
8040 goto out;
8041
8042 ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_TACTIVATE),
8043 &peer_pa_tactivate);
8044 if (ret)
8045 goto out;
8046
8047 pa_tactivate_us = pa_tactivate * gran_to_us_table[granularity - 1];
8048 peer_pa_tactivate_us = peer_pa_tactivate *
8049 gran_to_us_table[peer_granularity - 1];
8050
9008661e 8051 if (pa_tactivate_us >= peer_pa_tactivate_us) {
c6a6db43 8052 u32 new_peer_pa_tactivate;
8053
8054 new_peer_pa_tactivate = pa_tactivate_us /
8055 gran_to_us_table[peer_granularity - 1];
8056 new_peer_pa_tactivate++;
8057 ret = ufshcd_dme_peer_set(hba, UIC_ARG_MIB(PA_TACTIVATE),
8058 new_peer_pa_tactivate);
8059 }
8060
8061out:
8062 return ret;
8063}
8064
09750066 8065static void ufshcd_tune_unipro_params(struct ufs_hba *hba)
37113106
YG		 8066{
8067 if (ufshcd_is_unipro_pa_params_tuning_req(hba)) {
8068 ufshcd_tune_pa_tactivate(hba);
8069 ufshcd_tune_pa_hibern8time(hba);
8070 }
8071
e91ed9e0
CG		 8072 ufshcd_vops_apply_dev_quirks(hba);
8073
37113106
YG		 8074 if (hba->dev_quirks & UFS_DEVICE_QUIRK_PA_TACTIVATE)
8075 /* set 1ms timeout for PA_TACTIVATE */
8076 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE), 10);
c6a6db43 8077
8078 if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE)
8079 ufshcd_quirk_tune_host_pa_tactivate(hba);
37113106
YG		 8080}
8081
ff8e20c6
DR		 8082static void ufshcd_clear_dbg_ufs_stats(struct ufs_hba *hba)
8083{
ff8e20c6
DR		 8084 hba->ufs_stats.hibern8_exit_cnt = 0;
8085 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0);
7fabb77b 8086 hba->req_abort_count = 0;
ff8e20c6
DR		 8087}
8088
731f0621
BH		 8089static int ufshcd_device_geo_params_init(struct ufs_hba *hba)
8090{
8091 int err;
731f0621
BH		 8092 u8 *desc_buf;
8093
f2a89b07 8094 desc_buf = kzalloc(QUERY_DESC_MAX_SIZE, GFP_KERNEL);
731f0621
BH		 8095 if (!desc_buf) {
8096 err = -ENOMEM;
8097 goto out;
8098 }
8099
c4607a09 8100 err = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_GEOMETRY, 0, 0,
f2a89b07 8101 desc_buf, QUERY_DESC_MAX_SIZE);
731f0621
BH		 8102 if (err) {
8103 dev_err(hba->dev, "%s: Failed reading Geometry Desc. err = %d\n",
8104 __func__, err);
8105 goto out;
8106 }
8107
8108 if (desc_buf[GEOMETRY_DESC_PARAM_MAX_NUM_LUN] == 1)
8109 hba->dev_info.max_lu_supported = 32;
8110 else if (desc_buf[GEOMETRY_DESC_PARAM_MAX_NUM_LUN] == 0)
8111 hba->dev_info.max_lu_supported = 8;
8112
f2a89b07 8113 if (desc_buf[QUERY_DESC_LENGTH_OFFSET] >=
f02bc975
DP		 8114 GEOMETRY_DESC_PARAM_HPB_MAX_ACTIVE_REGS)
8115 ufshpb_get_geo_info(hba, desc_buf);
8116
731f0621
BH		 8117out:
8118 kfree(desc_buf);
8119 return err;
8120}
8121
743b09d8
BVA		 8122struct ufs_ref_clk {
8123 unsigned long freq_hz;
8124 enum ufs_ref_clk_freq val;
8125};
8126
35d11ec2 8127static const struct ufs_ref_clk ufs_ref_clk_freqs[] = {
9e1e8a75
SJ		 8128 {19200000, REF_CLK_FREQ_19_2_MHZ},
8129 {26000000, REF_CLK_FREQ_26_MHZ},
8130 {38400000, REF_CLK_FREQ_38_4_MHZ},
8131 {52000000, REF_CLK_FREQ_52_MHZ},
8132 {0, REF_CLK_FREQ_INVAL},
8133};
8134
8135static enum ufs_ref_clk_freq
8136ufs_get_bref_clk_from_hz(unsigned long freq)
8137{
8138 int i;
8139
8140 for (i = 0; ufs_ref_clk_freqs[i].freq_hz; i++)
8141 if (ufs_ref_clk_freqs[i].freq_hz == freq)
8142 return ufs_ref_clk_freqs[i].val;
8143
8144 return REF_CLK_FREQ_INVAL;
8145}
8146
8147void ufshcd_parse_dev_ref_clk_freq(struct ufs_hba *hba, struct clk *refclk)
8148{
8149 unsigned long freq;
8150
8151 freq = clk_get_rate(refclk);
8152
8153 hba->dev_ref_clk_freq =
8154 ufs_get_bref_clk_from_hz(freq);
8155
8156 if (hba->dev_ref_clk_freq == REF_CLK_FREQ_INVAL)
8157 dev_err(hba->dev,
8158 "invalid ref_clk setting = %ld\n", freq);
8159}
8160
8161static int ufshcd_set_dev_ref_clk(struct ufs_hba *hba)
8162{
8163 int err;
8164 u32 ref_clk;
8165 u32 freq = hba->dev_ref_clk_freq;
8166
8167 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
8168 QUERY_ATTR_IDN_REF_CLK_FREQ, 0, 0, &ref_clk);
8169
8170 if (err) {
8171 dev_err(hba->dev, "failed reading bRefClkFreq. err = %d\n",
8172 err);
8173 goto out;
8174 }
8175
8176 if (ref_clk == freq)
8177 goto out; /* nothing to update */
8178
8179 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
8180 QUERY_ATTR_IDN_REF_CLK_FREQ, 0, 0, &freq);
8181
8182 if (err) {
8183 dev_err(hba->dev, "bRefClkFreq setting to %lu Hz failed\n",
8184 ufs_ref_clk_freqs[freq].freq_hz);
8185 goto out;
8186 }
8187
8188 dev_dbg(hba->dev, "bRefClkFreq setting to %lu Hz succeeded\n",
8189 ufs_ref_clk_freqs[freq].freq_hz);
8190
8191out:
8192 return err;
8193}
8194
1b9e2141
BH		 8195static int ufshcd_device_params_init(struct ufs_hba *hba)
8196{
8197 bool flag;
f2a89b07 8198 int ret;
1b9e2141 8199
731f0621
BH		 8200 /* Init UFS geometry descriptor related parameters */
8201 ret = ufshcd_device_geo_params_init(hba);
8202 if (ret)
8203 goto out;
8204
1b9e2141
BH		 8205 /* Check and apply UFS device quirks */
8206 ret = ufs_get_device_desc(hba);
8207 if (ret) {
8208 dev_err(hba->dev, "%s: Failed getting device info. err = %d\n",
8209 __func__, ret);
8210 goto out;
8211 }
8212
09f17791
CG		 8213 ufshcd_get_ref_clk_gating_wait(hba);
8214
1b9e2141 8215 if (!ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_READ_FLAG,
1f34eedf 8216 QUERY_FLAG_IDN_PWR_ON_WPE, 0, &flag))
1b9e2141
BH		 8217 hba->dev_info.f_power_on_wp_en = flag;
8218
2b35b2ad
BH		 8219 /* Probe maximum power mode co-supported by both UFS host and device */
8220 if (ufshcd_get_max_pwr_mode(hba))
8221 dev_err(hba->dev,
8222 "%s: Failed getting max supported power mode\n",
8223 __func__);
1b9e2141
BH		 8224out:
8225 return ret;
8226}
8227
8228/**
8229 * ufshcd_add_lus - probe and add UFS logical units
8230 * @hba: per-adapter instance
8231 */
8232static int ufshcd_add_lus(struct ufs_hba *hba)
8233{
8234 int ret;
8235
1b9e2141
BH		 8236 /* Add required well known logical units to scsi mid layer */
8237 ret = ufshcd_scsi_add_wlus(hba);
8238 if (ret)
8239 goto out;
8240
8241 /* Initialize devfreq after UFS device is detected */
8242 if (ufshcd_is_clkscaling_supported(hba)) {
8243 memcpy(&hba->clk_scaling.saved_pwr_info.info,
8244 &hba->pwr_info,
8245 sizeof(struct ufs_pa_layer_attr));
8246 hba->clk_scaling.saved_pwr_info.is_valid = true;
1b9e2141 8247 hba->clk_scaling.is_allowed = true;
1b9e2141 8248
b058fa86
SC		 8249 ret = ufshcd_devfreq_init(hba);
8250 if (ret)
8251 goto out;
8252
8253 hba->clk_scaling.is_enabled = true;
8254 ufshcd_init_clk_scaling_sysfs(hba);
1b9e2141
BH		 8255 }
8256
8257 ufs_bsg_probe(hba);
f02bc975 8258 ufshpb_init(hba);
1b9e2141
BH		 8259 scsi_scan_host(hba->host);
8260 pm_runtime_put_sync(hba->dev);
8261
1b9e2141
BH		 8262out:
8263 return ret;
8264}
8265
96a7141d 8266static int ufshcd_device_init(struct ufs_hba *hba, bool init_dev_params)
6ccf44fe 8267{
6ccf44fe
SJ		 8268 int ret;
8269
aa53f580
CG		 8270 hba->ufshcd_state = UFSHCD_STATE_RESET;
8271
6ccf44fe 8272 ret = ufshcd_link_startup(hba);
5a0b0cb9 8273 if (ret)
96a7141d 8274 return ret;
5a0b0cb9 8275
10fb4f87 8276 if (hba->quirks & UFSHCD_QUIRK_SKIP_PH_CONFIGURATION)
96a7141d 8277 return ret;
10fb4f87 8278
ff8e20c6
DR		 8279 /* Debug counters initialization */
8280 ufshcd_clear_dbg_ufs_stats(hba);
8281
57d104c1
SJ		 8282 /* UniPro link is active now */
8283 ufshcd_set_link_active(hba);
d3e89bac 8284
1b9e2141 8285 /* Verify device initialization by sending NOP OUT UPIU */
5a0b0cb9
SRT		 8286 ret = ufshcd_verify_dev_init(hba);
8287 if (ret)
96a7141d 8288 return ret;
68078d5c 8289
1b9e2141 8290 /* Initiate UFS initialization, and waiting until completion */
68078d5c
DR		 8291 ret = ufshcd_complete_dev_init(hba);
8292 if (ret)
96a7141d 8293 return ret;
5a0b0cb9 8294
1b9e2141
BH		 8295 /*
8296 * Initialize UFS device parameters used by driver, these
8297 * parameters are associated with UFS descriptors.
8298 */
568dd995 8299 if (init_dev_params) {
1b9e2141
BH		 8300 ret = ufshcd_device_params_init(hba);
8301 if (ret)
96a7141d 8302 return ret;
93fdd5ac
TW		 8303 }
8304
09750066 8305 ufshcd_tune_unipro_params(hba);
4b828fe1 8306
57d104c1
SJ		 8307 /* UFS device is also active now */
8308 ufshcd_set_ufs_dev_active(hba);
66ec6d59 8309 ufshcd_force_reset_auto_bkops(hba);
57d104c1 8310
2b35b2ad
BH		 8311 /* Gear up to HS gear if supported */
8312 if (hba->max_pwr_info.is_valid) {
9e1e8a75
SJ		 8313 /*
8314 * Set the right value to bRefClkFreq before attempting to
8315 * switch to HS gears.
8316 */
8317 if (hba->dev_ref_clk_freq != REF_CLK_FREQ_INVAL)
8318 ufshcd_set_dev_ref_clk(hba);
7eb584db 8319 ret = ufshcd_config_pwr_mode(hba, &hba->max_pwr_info.info);
8643ae66 8320 if (ret) {
7eb584db
DR		 8321 dev_err(hba->dev, "%s: Failed setting power mode, err = %d\n",
8322 __func__, ret);
96a7141d
MS		 8323 return ret;
8324 }
8325 }
8326
8327 return 0;
8328}
8329
8330/**
8331 * ufshcd_probe_hba - probe hba to detect device and initialize it
8332 * @hba: per-adapter instance
8333 * @init_dev_params: whether or not to call ufshcd_device_params_init().
8334 *
8335 * Execute link-startup and verify device initialization
8336 */
8337static int ufshcd_probe_hba(struct ufs_hba *hba, bool init_dev_params)
8338{
8339 ktime_t start = ktime_get();
8340 unsigned long flags;
8341 int ret;
8342
8343 ret = ufshcd_device_init(hba, init_dev_params);
8344 if (ret)
8345 goto out;
8346
8347 if (hba->quirks & UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH) {
8348 /* Reset the device and controller before doing reinit */
8349 ufshcd_device_reset(hba);
8350 ufshcd_hba_stop(hba);
8351 ufshcd_vops_reinit_notify(hba);
8352 ret = ufshcd_hba_enable(hba);
8353 if (ret) {
8354 dev_err(hba->dev, "Host controller enable failed\n");
8355 ufshcd_print_evt_hist(hba);
8356 ufshcd_print_host_state(hba);
8643ae66
DL		 8357 goto out;
8358 }
96a7141d
MS		 8359
8360 /* Reinit the device */
8361 ret = ufshcd_device_init(hba, init_dev_params);
8362 if (ret)
8363 goto out;
7eb584db 8364 }
57d104c1 8365
96a7141d
MS		 8366 ufshcd_print_pwr_info(hba);
8367
e89860f1
CG		 8368 /*
8369 * bActiveICCLevel is volatile for UFS device (as per latest v2.1 spec)
8370 * and for removable UFS card as well, hence always set the parameter.
8371 * Note: Error handler may issue the device reset hence resetting
8372 * bActiveICCLevel as well so it is always safe to set this here.
8373 */
8374 ufshcd_set_active_icc_lvl(hba);
8375
4450a165
JC		 8376 /* Enable UFS Write Booster if supported */
8377 ufshcd_configure_wb(hba);
8378
cd469475
AH		 8379 if (hba->ee_usr_mask)
8380 ufshcd_write_ee_control(hba);
71d848b8
CG		 8381 /* Enable Auto-Hibernate if configured */
8382 ufshcd_auto_hibern8_enable(hba);
8383
facc239c 8384 ufshpb_toggle_state(hba, HPB_RESET, HPB_PRESENT);
5a0b0cb9 8385out:
4db7a236
CG		 8386 spin_lock_irqsave(hba->host->host_lock, flags);
8387 if (ret)
8388 hba->ufshcd_state = UFSHCD_STATE_ERROR;
8389 else if (hba->ufshcd_state == UFSHCD_STATE_RESET)
8390 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
8391 spin_unlock_irqrestore(hba->host->host_lock, flags);
1d337ec2 8392
7ff5ab47 8393 trace_ufshcd_init(dev_name(hba->dev), ret,
8394 ktime_to_us(ktime_sub(ktime_get(), start)),
73eba2be 8395 hba->curr_dev_pwr_mode, hba->uic_link_state);
1d337ec2
SRT		 8396 return ret;
8397}
8398
8399/**
8400 * ufshcd_async_scan - asynchronous execution for probing hba
8401 * @data: data pointer to pass to this function
8402 * @cookie: cookie data
8403 */
8404static void ufshcd_async_scan(void *data, async_cookie_t cookie)
8405{
8406 struct ufs_hba *hba = (struct ufs_hba *)data;
1b9e2141 8407 int ret;
1d337ec2 8408
9cd20d3f 8409 down(&hba->host_sem);
1b9e2141
BH		 8410 /* Initialize hba, detect and initialize UFS device */
8411 ret = ufshcd_probe_hba(hba, true);
9cd20d3f 8412 up(&hba->host_sem);
1b9e2141
BH		 8413 if (ret)
8414 goto out;
8415
8416 /* Probe and add UFS logical units */
8417 ret = ufshcd_add_lus(hba);
8418out:
8419 /*
8420 * If we failed to initialize the device or the device is not
8421 * present, turn off the power/clocks etc.
8422 */
8423 if (ret) {
8424 pm_runtime_put_sync(hba->dev);
1b9e2141
BH		 8425 ufshcd_hba_exit(hba);
8426 }
6ccf44fe
SJ		 8427}
8428
7029e215
BVA		 8429static enum scsi_timeout_action ufshcd_eh_timed_out(struct scsi_cmnd *scmd)
8430{
8431 struct ufs_hba *hba = shost_priv(scmd->device->host);
8432
8433 if (!hba->system_suspending) {
8434 /* Activate the error handler in the SCSI core. */
8435 return SCSI_EH_NOT_HANDLED;
8436 }
8437
8438 /*
8439 * If we get here we know that no TMFs are outstanding and also that
8440 * the only pending command is a START STOP UNIT command. Handle the
8441 * timeout of that command directly to prevent a deadlock between
8442 * ufshcd_set_dev_pwr_mode() and ufshcd_err_handler().
8443 */
8444 ufshcd_link_recovery(hba);
8445 dev_info(hba->dev, "%s() finished; outstanding_tasks = %#lx.\n",
8446 __func__, hba->outstanding_tasks);
8447
8448 return hba->outstanding_reqs ? SCSI_EH_RESET_TIMER : SCSI_EH_DONE;
8449}
8450
d829fc8a
SN		 8451static const struct attribute_group *ufshcd_driver_groups[] = {
8452 &ufs_sysfs_unit_descriptor_group,
ec92b59c 8453 &ufs_sysfs_lun_attributes_group,
f02bc975
DP		 8454#ifdef CONFIG_SCSI_UFS_HPB
8455 &ufs_sysfs_hpb_stat_group,
41d8a933 8456 &ufs_sysfs_hpb_param_group,
f02bc975 8457#endif
d829fc8a
SN		 8458 NULL,
8459};
8460
90b8491c
SC		 8461static struct ufs_hba_variant_params ufs_hba_vps = {
8462 .hba_enable_delay_us = 1000,
d14734ae 8463 .wb_flush_threshold = UFS_WB_BUF_REMAIN_PERCENT(40),
90b8491c
SC		 8464 .devfreq_profile.polling_ms = 100,
8465 .devfreq_profile.target = ufshcd_devfreq_target,
8466 .devfreq_profile.get_dev_status = ufshcd_devfreq_get_dev_status,
8467 .ondemand_data.upthreshold = 70,
8468 .ondemand_data.downdifferential = 5,
8469};
8470
7a3e97b0
SY		 8471static struct scsi_host_template ufshcd_driver_template = {
8472 .module = THIS_MODULE,
8473 .name = UFSHCD,
8474 .proc_name = UFSHCD,
eaab9b57 8475 .map_queues = ufshcd_map_queues,
7a3e97b0 8476 .queuecommand = ufshcd_queuecommand,
eaab9b57 8477 .mq_poll = ufshcd_poll,
7a3e97b0 8478 .slave_alloc = ufshcd_slave_alloc,
eeda4749 8479 .slave_configure = ufshcd_slave_configure,
7a3e97b0 8480 .slave_destroy = ufshcd_slave_destroy,
4264fd61 8481 .change_queue_depth = ufshcd_change_queue_depth,
7a3e97b0 8482 .eh_abort_handler = ufshcd_abort,
3441da7d
SRT		 8483 .eh_device_reset_handler = ufshcd_eh_device_reset_handler,
8484 .eh_host_reset_handler = ufshcd_eh_host_reset_handler,
7029e215 8485 .eh_timed_out = ufshcd_eh_timed_out,
7a3e97b0
SY		 8486 .this_id = -1,
8487 .sg_tablesize = SG_ALL,
8488 .cmd_per_lun = UFSHCD_CMD_PER_LUN,
8489 .can_queue = UFSHCD_CAN_QUEUE,
552a990c 8490 .max_segment_size = PRDT_DATA_BYTE_COUNT_MAX,
86a44f04 8491 .max_sectors = (1 << 20) / SECTOR_SIZE, /* 1 MiB */
1ab27c9c 8492 .max_host_blocked = 1,
c40ecc12 8493 .track_queue_depth = 1,
d829fc8a 8494 .sdev_groups = ufshcd_driver_groups,
4af14d11 8495 .dma_boundary = PAGE_SIZE - 1,
49615ba1 8496 .rpm_autosuspend_delay = RPM_AUTOSUSPEND_DELAY_MS,
7a3e97b0
SY		 8497};
8498
57d104c1
SJ		 8499static int ufshcd_config_vreg_load(struct device *dev, struct ufs_vreg *vreg,
8500 int ua)
8501{
7b16a07c 8502 int ret;
57d104c1 8503
7b16a07c
BA		 8504 if (!vreg)
8505 return 0;
57d104c1 8506
0487fff7
SC		 8507 /*
8508 * "set_load" operation shall be required on those regulators
8509 * which specifically configured current limitation. Otherwise
8510 * zero max_uA may cause unexpected behavior when regulator is
8511 * enabled or set as high power mode.
8512 */
8513 if (!vreg->max_uA)
8514 return 0;
8515
7b16a07c
BA		 8516 ret = regulator_set_load(vreg->reg, ua);
8517 if (ret < 0) {
8518 dev_err(dev, "%s: %s set load (ua=%d) failed, err=%d\n",
8519 __func__, vreg->name, ua, ret);
57d104c1
SJ		 8520 }
8521
8522 return ret;
8523}
8524
8525static inline int ufshcd_config_vreg_lpm(struct ufs_hba *hba,
8526 struct ufs_vreg *vreg)
8527{
73067981 8528 return ufshcd_config_vreg_load(hba->dev, vreg, UFS_VREG_LPM_LOAD_UA);
57d104c1
SJ		 8529}
8530
8531static inline int ufshcd_config_vreg_hpm(struct ufs_hba *hba,
8532 struct ufs_vreg *vreg)
8533{
7c7cfdcf
AH		 8534 if (!vreg)
8535 return 0;
8536
73067981 8537 return ufshcd_config_vreg_load(hba->dev, vreg, vreg->max_uA);
57d104c1
SJ		 8538}
8539
aa497613
SRT		 8540static int ufshcd_config_vreg(struct device *dev,
8541 struct ufs_vreg *vreg, bool on)
8542{
9474c64e
BVA		 8543 if (regulator_count_voltages(vreg->reg) <= 0)
8544 return 0;
90d88f47 8545
9474c64e 8546 return ufshcd_config_vreg_load(dev, vreg, on ? vreg->max_uA : 0);
aa497613
SRT		 8547}
8548
8549static int ufshcd_enable_vreg(struct device *dev, struct ufs_vreg *vreg)
8550{
8551 int ret = 0;
8552
73067981 8553 if (!vreg || vreg->enabled)
aa497613
SRT		 8554 goto out;
8555
8556 ret = ufshcd_config_vreg(dev, vreg, true);
8557 if (!ret)
8558 ret = regulator_enable(vreg->reg);
8559
8560 if (!ret)
8561 vreg->enabled = true;
8562 else
8563 dev_err(dev, "%s: %s enable failed, err=%d\n",
8564 __func__, vreg->name, ret);
8565out:
8566 return ret;
8567}
8568
8569static int ufshcd_disable_vreg(struct device *dev, struct ufs_vreg *vreg)
8570{
8571 int ret = 0;
8572
f8162ac7 8573 if (!vreg || !vreg->enabled || vreg->always_on)
aa497613
SRT		 8574 goto out;
8575
8576 ret = regulator_disable(vreg->reg);
8577
8578 if (!ret) {
8579 /* ignore errors on applying disable config */
8580 ufshcd_config_vreg(dev, vreg, false);
8581 vreg->enabled = false;
8582 } else {
8583 dev_err(dev, "%s: %s disable failed, err=%d\n",
8584 __func__, vreg->name, ret);
8585 }
8586out:
8587 return ret;
8588}
8589
8590static int ufshcd_setup_vreg(struct ufs_hba *hba, bool on)
8591{
8592 int ret = 0;
8593 struct device *dev = hba->dev;
8594 struct ufs_vreg_info *info = &hba->vreg_info;
8595
aa497613
SRT		 8596 ret = ufshcd_toggle_vreg(dev, info->vcc, on);
8597 if (ret)
8598 goto out;
8599
8600 ret = ufshcd_toggle_vreg(dev, info->vccq, on);
8601 if (ret)
8602 goto out;
8603
8604 ret = ufshcd_toggle_vreg(dev, info->vccq2, on);
aa497613
SRT		 8605
8606out:
8607 if (ret) {
8608 ufshcd_toggle_vreg(dev, info->vccq2, false);
8609 ufshcd_toggle_vreg(dev, info->vccq, false);
8610 ufshcd_toggle_vreg(dev, info->vcc, false);
8611 }
8612 return ret;
8613}
8614
6a771a65
RS		 8615static int ufshcd_setup_hba_vreg(struct ufs_hba *hba, bool on)
8616{
8617 struct ufs_vreg_info *info = &hba->vreg_info;
8618
60b7b823 8619 return ufshcd_toggle_vreg(hba->dev, info->vdd_hba, on);
6a771a65
RS		 8620}
8621
1d6f9dec 8622int ufshcd_get_vreg(struct device *dev, struct ufs_vreg *vreg)
aa497613
SRT		 8623{
8624 int ret = 0;
8625
8626 if (!vreg)
8627 goto out;
8628
8629 vreg->reg = devm_regulator_get(dev, vreg->name);
8630 if (IS_ERR(vreg->reg)) {
8631 ret = PTR_ERR(vreg->reg);
8632 dev_err(dev, "%s: %s get failed, err=%d\n",
8633 __func__, vreg->name, ret);
8634 }
8635out:
8636 return ret;
8637}
1d6f9dec 8638EXPORT_SYMBOL_GPL(ufshcd_get_vreg);
aa497613
SRT		 8639
8640static int ufshcd_init_vreg(struct ufs_hba *hba)
8641{
8642 int ret = 0;
8643 struct device *dev = hba->dev;
8644 struct ufs_vreg_info *info = &hba->vreg_info;
8645
aa497613
SRT		 8646 ret = ufshcd_get_vreg(dev, info->vcc);
8647 if (ret)
8648 goto out;
8649
8650 ret = ufshcd_get_vreg(dev, info->vccq);
b0008625
BH		 8651 if (!ret)
8652 ret = ufshcd_get_vreg(dev, info->vccq2);
aa497613
SRT		 8653out:
8654 return ret;
8655}
8656
6a771a65
RS		 8657static int ufshcd_init_hba_vreg(struct ufs_hba *hba)
8658{
8659 struct ufs_vreg_info *info = &hba->vreg_info;
8660
476e4592 8661 return ufshcd_get_vreg(hba->dev, info->vdd_hba);
6a771a65
RS		 8662}
8663
81309c24 8664static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on)
c6e79dac
SRT		 8665{
8666 int ret = 0;
8667 struct ufs_clk_info *clki;
8668 struct list_head *head = &hba->clk_list_head;
1ab27c9c 8669 unsigned long flags;
911a0771 8670 ktime_t start = ktime_get();
8671 bool clk_state_changed = false;
c6e79dac 8672
566ec9ad 8673 if (list_empty(head))
c6e79dac
SRT		 8674 goto out;
8675
38f3242e
CG		 8676 ret = ufshcd_vops_setup_clocks(hba, on, PRE_CHANGE);
8677 if (ret)
8678 return ret;
1e879e8f 8679
c6e79dac
SRT		 8680 list_for_each_entry(clki, head, list) {
8681 if (!IS_ERR_OR_NULL(clki->clk)) {
81309c24
CG		 8682 /*
8683 * Don't disable clocks which are needed
8684 * to keep the link active.
8685 */
8686 if (ufshcd_is_link_active(hba) &&
8687 clki->keep_link_active)
57d104c1
SJ		 8688 continue;
8689
911a0771 8690 clk_state_changed = on ^ clki->enabled;
c6e79dac
SRT		 8691 if (on && !clki->enabled) {
8692 ret = clk_prepare_enable(clki->clk);
8693 if (ret) {
8694 dev_err(hba->dev, "%s: %s prepare enable failed, %d\n",
8695 __func__, clki->name, ret);
8696 goto out;
8697 }
8698 } else if (!on && clki->enabled) {
8699 clk_disable_unprepare(clki->clk);
8700 }
8701 clki->enabled = on;
8702 dev_dbg(hba->dev, "%s: clk: %s %sabled\n", __func__,
8703 clki->name, on ? "en" : "dis");
8704 }
8705 }
1ab27c9c 8706
38f3242e
CG		 8707 ret = ufshcd_vops_setup_clocks(hba, on, POST_CHANGE);
8708 if (ret)
8709 return ret;
1e879e8f 8710
c6e79dac
SRT		 8711out:
8712 if (ret) {
8713 list_for_each_entry(clki, head, list) {
8714 if (!IS_ERR_OR_NULL(clki->clk) && clki->enabled)
8715 clk_disable_unprepare(clki->clk);
8716 }
7ff5ab47 8717 } else if (!ret && on) {
1ab27c9c
ST		 8718 spin_lock_irqsave(hba->host->host_lock, flags);
8719 hba->clk_gating.state = CLKS_ON;
7ff5ab47 8720 trace_ufshcd_clk_gating(dev_name(hba->dev),
8721 hba->clk_gating.state);
1ab27c9c 8722 spin_unlock_irqrestore(hba->host->host_lock, flags);
c6e79dac 8723 }
7ff5ab47 8724
911a0771 8725 if (clk_state_changed)
8726 trace_ufshcd_profile_clk_gating(dev_name(hba->dev),
8727 (on ? "on" : "off"),
8728 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
c6e79dac
SRT		 8729 return ret;
8730}
8731
ca452621
DL		 8732static enum ufs_ref_clk_freq ufshcd_parse_ref_clk_property(struct ufs_hba *hba)
8733{
8734 u32 freq;
8735 int ret = device_property_read_u32(hba->dev, "ref-clk-freq", &freq);
8736
8737 if (ret) {
aaa26e38 8738 dev_dbg(hba->dev, "Cannot query 'ref-clk-freq' property = %d", ret);
ca452621
DL		 8739 return REF_CLK_FREQ_INVAL;
8740 }
8741
8742 return ufs_get_bref_clk_from_hz(freq);
8743}
8744
c6e79dac
SRT		 8745static int ufshcd_init_clocks(struct ufs_hba *hba)
8746{
8747 int ret = 0;
8748 struct ufs_clk_info *clki;
8749 struct device *dev = hba->dev;
8750 struct list_head *head = &hba->clk_list_head;
8751
566ec9ad 8752 if (list_empty(head))
c6e79dac
SRT		 8753 goto out;
8754
8755 list_for_each_entry(clki, head, list) {
8756 if (!clki->name)
8757 continue;
8758
8759 clki->clk = devm_clk_get(dev, clki->name);
8760 if (IS_ERR(clki->clk)) {
8761 ret = PTR_ERR(clki->clk);
8762 dev_err(dev, "%s: %s clk get failed, %d\n",
8763 __func__, clki->name, ret);
8764 goto out;
8765 }
8766
9e1e8a75
SJ		 8767 /*
8768 * Parse device ref clk freq as per device tree "ref_clk".
8769 * Default dev_ref_clk_freq is set to REF_CLK_FREQ_INVAL
8770 * in ufshcd_alloc_host().
8771 */
8772 if (!strcmp(clki->name, "ref_clk"))
8773 ufshcd_parse_dev_ref_clk_freq(hba, clki->clk);
8774
c6e79dac
SRT		 8775 if (clki->max_freq) {
8776 ret = clk_set_rate(clki->clk, clki->max_freq);
8777 if (ret) {
8778 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
8779 __func__, clki->name,
8780 clki->max_freq, ret);
8781 goto out;
8782 }
856b3483 8783 clki->curr_freq = clki->max_freq;
c6e79dac
SRT		 8784 }
8785 dev_dbg(dev, "%s: clk: %s, rate: %lu\n", __func__,
8786 clki->name, clk_get_rate(clki->clk));
8787 }
8788out:
8789 return ret;
8790}
8791
5c0c28a8
SRT		 8792static int ufshcd_variant_hba_init(struct ufs_hba *hba)
8793{
8794 int err = 0;
8795
8796 if (!hba->vops)
8797 goto out;
8798
0263bcd0 8799 err = ufshcd_vops_init(hba);
5c0c28a8
SRT		 8800 if (err)
8801 dev_err(hba->dev, "%s: variant %s init failed err %d\n",
0263bcd0 8802 __func__, ufshcd_get_var_name(hba), err);
ade921a8 8803out:
5c0c28a8
SRT		 8804 return err;
8805}
8806
8807static void ufshcd_variant_hba_exit(struct ufs_hba *hba)
8808{
8809 if (!hba->vops)
8810 return;
8811
0263bcd0 8812 ufshcd_vops_exit(hba);
5c0c28a8
SRT		 8813}
8814
aa497613
SRT		 8815static int ufshcd_hba_init(struct ufs_hba *hba)
8816{
8817 int err;
8818
6a771a65
RS		 8819 /*
8820 * Handle host controller power separately from the UFS device power
8821 * rails as it will help controlling the UFS host controller power
8822 * collapse easily which is different than UFS device power collapse.
8823 * Also, enable the host controller power before we go ahead with rest
8824 * of the initialization here.
8825 */
8826 err = ufshcd_init_hba_vreg(hba);
aa497613
SRT		 8827 if (err)
8828 goto out;
8829
6a771a65 8830 err = ufshcd_setup_hba_vreg(hba, true);
aa497613
SRT		 8831 if (err)
8832 goto out;
8833
6a771a65
RS		 8834 err = ufshcd_init_clocks(hba);
8835 if (err)
8836 goto out_disable_hba_vreg;
8837
ca452621
DL		 8838 if (hba->dev_ref_clk_freq == REF_CLK_FREQ_INVAL)
8839 hba->dev_ref_clk_freq = ufshcd_parse_ref_clk_property(hba);
8840
6a771a65
RS		 8841 err = ufshcd_setup_clocks(hba, true);
8842 if (err)
8843 goto out_disable_hba_vreg;
8844
c6e79dac
SRT		 8845 err = ufshcd_init_vreg(hba);
8846 if (err)
8847 goto out_disable_clks;
8848
8849 err = ufshcd_setup_vreg(hba, true);
8850 if (err)
8851 goto out_disable_clks;
8852
aa497613
SRT		 8853 err = ufshcd_variant_hba_init(hba);
8854 if (err)
8855 goto out_disable_vreg;
8856
b6cacaf2
AH		 8857 ufs_debugfs_hba_init(hba);
8858
1d337ec2 8859 hba->is_powered = true;
aa497613
SRT		 8860 goto out;
8861
8862out_disable_vreg:
8863 ufshcd_setup_vreg(hba, false);
c6e79dac
SRT		 8864out_disable_clks:
8865 ufshcd_setup_clocks(hba, false);
6a771a65
RS		 8866out_disable_hba_vreg:
8867 ufshcd_setup_hba_vreg(hba, false);
aa497613
SRT		 8868out:
8869 return err;
8870}
8871
8872static void ufshcd_hba_exit(struct ufs_hba *hba)
8873{
1d337ec2 8874 if (hba->is_powered) {
4543d9d7
CG		 8875 ufshcd_exit_clk_scaling(hba);
8876 ufshcd_exit_clk_gating(hba);
88b09900
AH		 8877 if (hba->eh_wq)
8878 destroy_workqueue(hba->eh_wq);
b6cacaf2 8879 ufs_debugfs_hba_exit(hba);
1d337ec2
SRT		 8880 ufshcd_variant_hba_exit(hba);
8881 ufshcd_setup_vreg(hba, false);
8882 ufshcd_setup_clocks(hba, false);
8883 ufshcd_setup_hba_vreg(hba, false);
8884 hba->is_powered = false;
09750066 8885 ufs_put_device_desc(hba);
1d337ec2 8886 }
aa497613
SRT		 8887}
8888
6a354a7e
BVA		 8889static int ufshcd_execute_start_stop(struct scsi_device *sdev,
8890 enum ufs_dev_pwr_mode pwr_mode,
8891 struct scsi_sense_hdr *sshdr)
8892{
8893 unsigned char cdb[6] = { START_STOP, 0, 0, 0, pwr_mode << 4, 0 };
8894 struct request *req;
8895 struct scsi_cmnd *scmd;
8896 int ret;
8897
8898 req = scsi_alloc_request(sdev->request_queue, REQ_OP_DRV_IN,
8899 BLK_MQ_REQ_PM);
8900 if (IS_ERR(req))
8901 return PTR_ERR(req);
8902
8903 scmd = blk_mq_rq_to_pdu(req);
8904 scmd->cmd_len = COMMAND_SIZE(cdb[0]);
8905 memcpy(scmd->cmnd, cdb, scmd->cmd_len);
8906 scmd->allowed = 0/*retries*/;
7029e215 8907 scmd->flags |= SCMD_FAIL_IF_RECOVERING;
6a354a7e
BVA		 8908 req->timeout = 1 * HZ;
8909 req->rq_flags |= RQF_PM | RQF_QUIET;
8910
8911 blk_execute_rq(req, /*at_head=*/true);
8912
8913 if (sshdr)
8914 scsi_normalize_sense(scmd->sense_buffer, scmd->sense_len,
8915 sshdr);
8916 ret = scmd->result;
8917
8918 blk_mq_free_request(req);
8919
8920 return ret;
8921}
8922
57d104c1
SJ		 8923/**
8924 * ufshcd_set_dev_pwr_mode - sends START STOP UNIT command to set device
8925 * power mode
8926 * @hba: per adapter instance
8927 * @pwr_mode: device power mode to set
8928 *
8929 * Returns 0 if requested power mode is set successfully
ad6c8a42 8930 * Returns < 0 if failed to set the requested power mode
57d104c1
SJ		 8931 */
8932static int ufshcd_set_dev_pwr_mode(struct ufs_hba *hba,
8933 enum ufs_dev_pwr_mode pwr_mode)
8934{
57d104c1 8935 struct scsi_sense_hdr sshdr;
7c48bfd0
AM		 8936 struct scsi_device *sdp;
8937 unsigned long flags;
af21c3fd 8938 int ret, retries;
57d104c1 8939
7c48bfd0 8940 spin_lock_irqsave(hba->host->host_lock, flags);
e2106584 8941 sdp = hba->ufs_device_wlun;
6d1aa3b0 8942 if (sdp && scsi_device_online(sdp))
7c48bfd0 8943 ret = scsi_device_get(sdp);
6d1aa3b0 8944 else
7c48bfd0 8945 ret = -ENODEV;
7c48bfd0
AM		 8946 spin_unlock_irqrestore(hba->host->host_lock, flags);
8947
8948 if (ret)
8949 return ret;
57d104c1
SJ		 8950
8951 /*
8952 * If scsi commands fail, the scsi mid-layer schedules scsi error-
8953 * handling, which would wait for host to be resumed. Since we know
8954 * we are functional while we are here, skip host resume in error
8955 * handling context.
8956 */
8957 hba->host->eh_noresume = 1;
57d104c1 8958
57d104c1
SJ		 8959 /*
8960 * Current function would be generally called from the power management
e8064021 8961 * callbacks hence set the RQF_PM flag so that it doesn't resume the
57d104c1
SJ		 8962 * already suspended childs.
8963 */
af21c3fd 8964 for (retries = 3; retries > 0; --retries) {
6a354a7e 8965 ret = ufshcd_execute_start_stop(sdp, pwr_mode, &sshdr);
579a4e9d
BVA		 8966 /*
8967 * scsi_execute() only returns a negative value if the request
8968 * queue is dying.
8969 */
8970 if (ret <= 0)
af21c3fd
JK		 8971 break;
8972 }
57d104c1
SJ		 8973 if (ret) {
8974 sdev_printk(KERN_WARNING, sdp,
ef61329d
HR		 8975 "START_STOP failed for power mode: %d, result %x\n",
8976 pwr_mode, ret);
ad6c8a42
KK		 8977 if (ret > 0) {
8978 if (scsi_sense_valid(&sshdr))
8979 scsi_print_sense_hdr(sdp, NULL, &sshdr);
8980 ret = -EIO;
8981 }
836d322d 8982 } else {
57d104c1 8983 hba->curr_dev_pwr_mode = pwr_mode;
836d322d 8984 }
1918651f 8985
7c48bfd0 8986 scsi_device_put(sdp);
57d104c1
SJ		 8987 hba->host->eh_noresume = 0;
8988 return ret;
8989}
8990
8991static int ufshcd_link_state_transition(struct ufs_hba *hba,
8992 enum uic_link_state req_link_state,
5277326d 8993 bool check_for_bkops)
57d104c1
SJ		 8994{
8995 int ret = 0;
8996
8997 if (req_link_state == hba->uic_link_state)
8998 return 0;
8999
9000 if (req_link_state == UIC_LINK_HIBERN8_STATE) {
9001 ret = ufshcd_uic_hibern8_enter(hba);
4db7a236 9002 if (!ret) {
57d104c1 9003 ufshcd_set_link_hibern8(hba);
4db7a236
CG		 9004 } else {
9005 dev_err(hba->dev, "%s: hibern8 enter failed %d\n",
9006 __func__, ret);
57d104c1 9007 goto out;
4db7a236 9008 }
57d104c1
SJ		 9009 }
9010 /*
9011 * If autobkops is enabled, link can't be turned off because
fe1d4c2e
AH		 9012 * turning off the link would also turn off the device, except in the
9013 * case of DeepSleep where the device is expected to remain powered.
57d104c1
SJ		 9014 */
9015 else if ((req_link_state == UIC_LINK_OFF_STATE) &&
dc30c9e6 9016 (!check_for_bkops || !hba->auto_bkops_enabled)) {
f3099fbd
YG		 9017 /*
9018 * Let's make sure that link is in low power mode, we are doing
9019 * this currently by putting the link in Hibern8. Otherway to
9020 * put the link in low power mode is to send the DME end point
9021 * to device and then send the DME reset command to local
9022 * unipro. But putting the link in hibern8 is much faster.
fe1d4c2e
AH		 9023 *
9024 * Note also that putting the link in Hibern8 is a requirement
9025 * for entering DeepSleep.
f3099fbd
YG		 9026 */
9027 ret = ufshcd_uic_hibern8_enter(hba);
4db7a236
CG		 9028 if (ret) {
9029 dev_err(hba->dev, "%s: hibern8 enter failed %d\n",
9030 __func__, ret);
f3099fbd 9031 goto out;
4db7a236 9032 }
57d104c1
SJ		 9033 /*
9034 * Change controller state to "reset state" which
9035 * should also put the link in off/reset state
9036 */
5cac1095 9037 ufshcd_hba_stop(hba);
57d104c1
SJ		 9038 /*
9039 * TODO: Check if we need any delay to make sure that
9040 * controller is reset
9041 */
9042 ufshcd_set_link_off(hba);
9043 }
9044
9045out:
9046 return ret;
9047}
9048
9049static void ufshcd_vreg_set_lpm(struct ufs_hba *hba)
9050{
c4df6eed
SC		 9051 bool vcc_off = false;
9052
b799fdf7
YG		 9053 /*
9054 * It seems some UFS devices may keep drawing more than sleep current
9055 * (atleast for 500us) from UFS rails (especially from VCCQ rail).
9056 * To avoid this situation, add 2ms delay before putting these UFS
9057 * rails in LPM mode.
9058 */
9059 if (!ufshcd_is_link_active(hba) &&
9060 hba->dev_quirks & UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM)
9061 usleep_range(2000, 2100);
9062
57d104c1
SJ		 9063 /*
9064 * If UFS device is either in UFS_Sleep turn off VCC rail to save some
9065 * power.
9066 *
9067 * If UFS device and link is in OFF state, all power supplies (VCC,
9068 * VCCQ, VCCQ2) can be turned off if power on write protect is not
9069 * required. If UFS link is inactive (Hibern8 or OFF state) and device
9070 * is in sleep state, put VCCQ & VCCQ2 rails in LPM mode.
9071 *
9072 * Ignore the error returned by ufshcd_toggle_vreg() as device is anyway
9073 * in low power state which would save some power.
3d17b9b5
AD		 9074 *
9075 * If Write Booster is enabled and the device needs to flush the WB
9076 * buffer OR if bkops status is urgent for WB, keep Vcc on.
57d104c1
SJ		 9077 */
9078 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) &&
9079 !hba->dev_info.is_lu_power_on_wp) {
9080 ufshcd_setup_vreg(hba, false);
c4df6eed 9081 vcc_off = true;
57d104c1 9082 } else if (!ufshcd_is_ufs_dev_active(hba)) {
51dd905b 9083 ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false);
c4df6eed 9084 vcc_off = true;
23043dd8 9085 if (ufshcd_is_link_hibern8(hba) || ufshcd_is_link_off(hba)) {
57d104c1
SJ		 9086 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq);
9087 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq2);
9088 }
9089 }
c4df6eed
SC		 9090
9091 /*
9092 * Some UFS devices require delay after VCC power rail is turned-off.
9093 */
9094 if (vcc_off && hba->vreg_info.vcc &&
9095 hba->dev_quirks & UFS_DEVICE_QUIRK_DELAY_AFTER_LPM)
9096 usleep_range(5000, 5100);
57d104c1
SJ		 9097}
9098
9bb25e5d 9099#ifdef CONFIG_PM
57d104c1
SJ		 9100static int ufshcd_vreg_set_hpm(struct ufs_hba *hba)
9101{
9102 int ret = 0;
9103
9104 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) &&
9105 !hba->dev_info.is_lu_power_on_wp) {
9106 ret = ufshcd_setup_vreg(hba, true);
9107 } else if (!ufshcd_is_ufs_dev_active(hba)) {
23043dd8 9108 if (!ufshcd_is_link_active(hba)) {
57d104c1
SJ		 9109 ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq);
9110 if (ret)
9111 goto vcc_disable;
9112 ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq2);
9113 if (ret)
9114 goto vccq_lpm;
9115 }
69d72ac8 9116 ret = ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, true);
57d104c1
SJ		 9117 }
9118 goto out;
9119
9120vccq_lpm:
9121 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq);
9122vcc_disable:
9123 ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false);
9124out:
9125 return ret;
9126}
9bb25e5d 9127#endif /* CONFIG_PM */
57d104c1
SJ		 9128
9129static void ufshcd_hba_vreg_set_lpm(struct ufs_hba *hba)
9130{
dd7143e2 9131 if (ufshcd_is_link_off(hba) || ufshcd_can_aggressive_pc(hba))
57d104c1
SJ		 9132 ufshcd_setup_hba_vreg(hba, false);
9133}
9134
9135static void ufshcd_hba_vreg_set_hpm(struct ufs_hba *hba)
9136{
dd7143e2 9137 if (ufshcd_is_link_off(hba) || ufshcd_can_aggressive_pc(hba))
57d104c1
SJ		 9138 ufshcd_setup_hba_vreg(hba, true);
9139}
9140
b294ff3e 9141static int __ufshcd_wl_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op)
7a3e97b0 9142{
57d104c1 9143 int ret = 0;
5277326d 9144 bool check_for_bkops;
57d104c1
SJ		 9145 enum ufs_pm_level pm_lvl;
9146 enum ufs_dev_pwr_mode req_dev_pwr_mode;
9147 enum uic_link_state req_link_state;
9148
b294ff3e 9149 hba->pm_op_in_progress = true;
4c6cb9ed
BVA		 9150 if (pm_op != UFS_SHUTDOWN_PM) {
9151 pm_lvl = pm_op == UFS_RUNTIME_PM ?
57d104c1
SJ		 9152 hba->rpm_lvl : hba->spm_lvl;
9153 req_dev_pwr_mode = ufs_get_pm_lvl_to_dev_pwr_mode(pm_lvl);
9154 req_link_state = ufs_get_pm_lvl_to_link_pwr_state(pm_lvl);
9155 } else {
9156 req_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE;
9157 req_link_state = UIC_LINK_OFF_STATE;
9158 }
9159
f02bc975
DP		 9160 ufshpb_suspend(hba);
9161
7a3e97b0 9162 /*
57d104c1
SJ		 9163 * If we can't transition into any of the low power modes
9164 * just gate the clocks.
7a3e97b0 9165 */
1ab27c9c
ST		 9166 ufshcd_hold(hba, false);
9167 hba->clk_gating.is_suspended = true;
9168
348e1bc5
SC		 9169 if (ufshcd_is_clkscaling_supported(hba))
9170 ufshcd_clk_scaling_suspend(hba, true);
d6fcf81a 9171
57d104c1
SJ		 9172 if (req_dev_pwr_mode == UFS_ACTIVE_PWR_MODE &&
9173 req_link_state == UIC_LINK_ACTIVE_STATE) {
b294ff3e 9174 goto vops_suspend;
57d104c1 9175 }
7a3e97b0 9176
57d104c1
SJ		 9177 if ((req_dev_pwr_mode == hba->curr_dev_pwr_mode) &&
9178 (req_link_state == hba->uic_link_state))
b294ff3e 9179 goto enable_scaling;
57d104c1
SJ		 9180
9181 /* UFS device & link must be active before we enter in this function */
9182 if (!ufshcd_is_ufs_dev_active(hba) || !ufshcd_is_link_active(hba)) {
9183 ret = -EINVAL;
b294ff3e 9184 goto enable_scaling;
57d104c1
SJ		 9185 }
9186
4c6cb9ed 9187 if (pm_op == UFS_RUNTIME_PM) {
374a246e
SJ		 9188 if (ufshcd_can_autobkops_during_suspend(hba)) {
9189 /*
9190 * The device is idle with no requests in the queue,
9191 * allow background operations if bkops status shows
9192 * that performance might be impacted.
9193 */
9194 ret = ufshcd_urgent_bkops(hba);
9195 if (ret)
b294ff3e 9196 goto enable_scaling;
374a246e
SJ		 9197 } else {
9198 /* make sure that auto bkops is disabled */
9199 ufshcd_disable_auto_bkops(hba);
9200 }
3d17b9b5 9201 /*
51dd905b
SC		 9202 * If device needs to do BKOP or WB buffer flush during
9203 * Hibern8, keep device power mode as "active power mode"
9204 * and VCC supply.
3d17b9b5 9205 */
51dd905b
SC		 9206 hba->dev_info.b_rpm_dev_flush_capable =
9207 hba->auto_bkops_enabled ||
9208 (((req_link_state == UIC_LINK_HIBERN8_STATE) ||
9209 ((req_link_state == UIC_LINK_ACTIVE_STATE) &&
9210 ufshcd_is_auto_hibern8_enabled(hba))) &&
9211 ufshcd_wb_need_flush(hba));
9212 }
9213
6948a96a
KK		 9214 flush_work(&hba->eeh_work);
9215
9561f584
PW		 9216 ret = ufshcd_vops_suspend(hba, pm_op, PRE_CHANGE);
9217 if (ret)
9218 goto enable_scaling;
9219
51dd905b 9220 if (req_dev_pwr_mode != hba->curr_dev_pwr_mode) {
4c6cb9ed 9221 if (pm_op != UFS_RUNTIME_PM)
51dd905b
SC		 9222 /* ensure that bkops is disabled */
9223 ufshcd_disable_auto_bkops(hba);
57d104c1 9224
51dd905b
SC		 9225 if (!hba->dev_info.b_rpm_dev_flush_capable) {
9226 ret = ufshcd_set_dev_pwr_mode(hba, req_dev_pwr_mode);
9227 if (ret)
b294ff3e 9228 goto enable_scaling;
51dd905b 9229 }
57d104c1
SJ		 9230 }
9231
fe1d4c2e
AH		 9232 /*
9233 * In the case of DeepSleep, the device is expected to remain powered
9234 * with the link off, so do not check for bkops.
9235 */
9236 check_for_bkops = !ufshcd_is_ufs_dev_deepsleep(hba);
9237 ret = ufshcd_link_state_transition(hba, req_link_state, check_for_bkops);
57d104c1
SJ		 9238 if (ret)
9239 goto set_dev_active;
9240
b294ff3e 9241vops_suspend:
57d104c1
SJ		 9242 /*
9243 * Call vendor specific suspend callback. As these callbacks may access
9244 * vendor specific host controller register space call them before the
9245 * host clocks are ON.
9246 */
9561f584 9247 ret = ufshcd_vops_suspend(hba, pm_op, POST_CHANGE);
0263bcd0
YG		 9248 if (ret)
9249 goto set_link_active;
57d104c1
SJ		 9250 goto out;
9251
57d104c1 9252set_link_active:
fe1d4c2e
AH		 9253 /*
9254 * Device hardware reset is required to exit DeepSleep. Also, for
9255 * DeepSleep, the link is off so host reset and restore will be done
9256 * further below.
9257 */
9258 if (ufshcd_is_ufs_dev_deepsleep(hba)) {
31a5d9ca 9259 ufshcd_device_reset(hba);
fe1d4c2e
AH		 9260 WARN_ON(!ufshcd_is_link_off(hba));
9261 }
57d104c1
SJ		 9262 if (ufshcd_is_link_hibern8(hba) && !ufshcd_uic_hibern8_exit(hba))
9263 ufshcd_set_link_active(hba);
9264 else if (ufshcd_is_link_off(hba))
9265 ufshcd_host_reset_and_restore(hba);
9266set_dev_active:
fe1d4c2e
AH		 9267 /* Can also get here needing to exit DeepSleep */
9268 if (ufshcd_is_ufs_dev_deepsleep(hba)) {
31a5d9ca 9269 ufshcd_device_reset(hba);
fe1d4c2e
AH		 9270 ufshcd_host_reset_and_restore(hba);
9271 }
57d104c1
SJ		 9272 if (!ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE))
9273 ufshcd_disable_auto_bkops(hba);
b294ff3e 9274enable_scaling:
348e1bc5
SC		 9275 if (ufshcd_is_clkscaling_supported(hba))
9276 ufshcd_clk_scaling_suspend(hba, false);
9277
51dd905b 9278 hba->dev_info.b_rpm_dev_flush_capable = false;
57d104c1 9279out:
51dd905b
SC		 9280 if (hba->dev_info.b_rpm_dev_flush_capable) {
9281 schedule_delayed_work(&hba->rpm_dev_flush_recheck_work,
9282 msecs_to_jiffies(RPM_DEV_FLUSH_RECHECK_WORK_DELAY_MS));
9283 }
9284
b294ff3e
AD		 9285 if (ret) {
9286 ufshcd_update_evt_hist(hba, UFS_EVT_WL_SUSP_ERR, (u32)ret);
9287 hba->clk_gating.is_suspended = false;
9288 ufshcd_release(hba);
f02bc975 9289 ufshpb_resume(hba);
b294ff3e
AD		 9290 }
9291 hba->pm_op_in_progress = false;
57d104c1 9292 return ret;
7a3e97b0
SY		 9293}
9294
75d645a6 9295#ifdef CONFIG_PM
b294ff3e 9296static int __ufshcd_wl_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
7a3e97b0 9297{
57d104c1 9298 int ret;
b294ff3e 9299 enum uic_link_state old_link_state = hba->uic_link_state;
57d104c1 9300
b294ff3e 9301 hba->pm_op_in_progress = true;
57d104c1 9302
7a3e97b0 9303 /*
57d104c1
SJ		 9304 * Call vendor specific resume callback. As these callbacks may access
9305 * vendor specific host controller register space call them when the
9306 * host clocks are ON.
7a3e97b0 9307 */
0263bcd0
YG		 9308 ret = ufshcd_vops_resume(hba, pm_op);
9309 if (ret)
b294ff3e 9310 goto out;
57d104c1 9311
fe1d4c2e
AH		 9312 /* For DeepSleep, the only supported option is to have the link off */
9313 WARN_ON(ufshcd_is_ufs_dev_deepsleep(hba) && !ufshcd_is_link_off(hba));
9314
57d104c1
SJ		 9315 if (ufshcd_is_link_hibern8(hba)) {
9316 ret = ufshcd_uic_hibern8_exit(hba);
4db7a236 9317 if (!ret) {
57d104c1 9318 ufshcd_set_link_active(hba);
4db7a236
CG		 9319 } else {
9320 dev_err(hba->dev, "%s: hibern8 exit failed %d\n",
9321 __func__, ret);
57d104c1 9322 goto vendor_suspend;
4db7a236 9323 }
57d104c1 9324 } else if (ufshcd_is_link_off(hba)) {
57d104c1 9325 /*
089f5b64
AD		 9326 * A full initialization of the host and the device is
9327 * required since the link was put to off during suspend.
fe1d4c2e
AH		 9328 * Note, in the case of DeepSleep, the device will exit
9329 * DeepSleep due to device reset.
089f5b64
AD		 9330 */
9331 ret = ufshcd_reset_and_restore(hba);
9332 /*
9333 * ufshcd_reset_and_restore() should have already
57d104c1
SJ		 9334 * set the link state as active
9335 */
9336 if (ret || !ufshcd_is_link_active(hba))
9337 goto vendor_suspend;
9338 }
9339
9340 if (!ufshcd_is_ufs_dev_active(hba)) {
9341 ret = ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE);
9342 if (ret)
9343 goto set_old_link_state;
9344 }
9345
4e768e76 9346 if (ufshcd_keep_autobkops_enabled_except_suspend(hba))
9347 ufshcd_enable_auto_bkops(hba);
9348 else
9349 /*
9350 * If BKOPs operations are urgently needed at this moment then
9351 * keep auto-bkops enabled or else disable it.
9352 */
9353 ufshcd_urgent_bkops(hba);
9354
cd469475
AH		 9355 if (hba->ee_usr_mask)
9356 ufshcd_write_ee_control(hba);
9357
348e1bc5
SC		 9358 if (ufshcd_is_clkscaling_supported(hba))
9359 ufshcd_clk_scaling_suspend(hba, false);
856b3483 9360
51dd905b
SC		 9361 if (hba->dev_info.b_rpm_dev_flush_capable) {
9362 hba->dev_info.b_rpm_dev_flush_capable = false;
9363 cancel_delayed_work(&hba->rpm_dev_flush_recheck_work);
9364 }
9365
b294ff3e
AD		 9366 /* Enable Auto-Hibernate if configured */
9367 ufshcd_auto_hibern8_enable(hba);
f02bc975
DP		 9368
9369 ufshpb_resume(hba);
57d104c1
SJ		 9370 goto out;
9371
9372set_old_link_state:
9373 ufshcd_link_state_transition(hba, old_link_state, 0);
9374vendor_suspend:
9561f584
PW		 9375 ufshcd_vops_suspend(hba, pm_op, PRE_CHANGE);
9376 ufshcd_vops_suspend(hba, pm_op, POST_CHANGE);
b294ff3e
AD		 9377out:
9378 if (ret)
9379 ufshcd_update_evt_hist(hba, UFS_EVT_WL_RES_ERR, (u32)ret);
9380 hba->clk_gating.is_suspended = false;
9381 ufshcd_release(hba);
9382 hba->pm_op_in_progress = false;
9383 return ret;
9384}
9385
9386static int ufshcd_wl_runtime_suspend(struct device *dev)
9387{
9388 struct scsi_device *sdev = to_scsi_device(dev);
9389 struct ufs_hba *hba;
9390 int ret;
9391 ktime_t start = ktime_get();
9392
9393 hba = shost_priv(sdev->host);
9394
9395 ret = __ufshcd_wl_suspend(hba, UFS_RUNTIME_PM);
9396 if (ret)
9397 dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__, ret);
9398
9399 trace_ufshcd_wl_runtime_suspend(dev_name(dev), ret,
9400 ktime_to_us(ktime_sub(ktime_get(), start)),
9401 hba->curr_dev_pwr_mode, hba->uic_link_state);
9402
9403 return ret;
9404}
9405
9406static int ufshcd_wl_runtime_resume(struct device *dev)
9407{
9408 struct scsi_device *sdev = to_scsi_device(dev);
9409 struct ufs_hba *hba;
9410 int ret = 0;
9411 ktime_t start = ktime_get();
9412
9413 hba = shost_priv(sdev->host);
9414
9415 ret = __ufshcd_wl_resume(hba, UFS_RUNTIME_PM);
9416 if (ret)
9417 dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__, ret);
9418
9419 trace_ufshcd_wl_runtime_resume(dev_name(dev), ret,
9420 ktime_to_us(ktime_sub(ktime_get(), start)),
9421 hba->curr_dev_pwr_mode, hba->uic_link_state);
9422
9423 return ret;
9424}
75d645a6 9425#endif
b294ff3e
AD		 9426
9427#ifdef CONFIG_PM_SLEEP
9428static int ufshcd_wl_suspend(struct device *dev)
9429{
9430 struct scsi_device *sdev = to_scsi_device(dev);
9431 struct ufs_hba *hba;
9432 int ret = 0;
9433 ktime_t start = ktime_get();
9434
9435 hba = shost_priv(sdev->host);
9436 down(&hba->host_sem);
1a547cbc 9437 hba->system_suspending = true;
b294ff3e
AD		 9438
9439 if (pm_runtime_suspended(dev))
9440 goto out;
9441
9442 ret = __ufshcd_wl_suspend(hba, UFS_SYSTEM_PM);
9443 if (ret) {
9444 dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__, ret);
9445 up(&hba->host_sem);
9446 }
9447
9448out:
9449 if (!ret)
9450 hba->is_sys_suspended = true;
9451 trace_ufshcd_wl_suspend(dev_name(dev), ret,
9452 ktime_to_us(ktime_sub(ktime_get(), start)),
9453 hba->curr_dev_pwr_mode, hba->uic_link_state);
9454
9455 return ret;
9456}
9457
9458static int ufshcd_wl_resume(struct device *dev)
9459{
9460 struct scsi_device *sdev = to_scsi_device(dev);
9461 struct ufs_hba *hba;
9462 int ret = 0;
9463 ktime_t start = ktime_get();
9464
9465 hba = shost_priv(sdev->host);
9466
9467 if (pm_runtime_suspended(dev))
9468 goto out;
9469
9470 ret = __ufshcd_wl_resume(hba, UFS_SYSTEM_PM);
9471 if (ret)
9472 dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__, ret);
9473out:
9474 trace_ufshcd_wl_resume(dev_name(dev), ret,
9475 ktime_to_us(ktime_sub(ktime_get(), start)),
9476 hba->curr_dev_pwr_mode, hba->uic_link_state);
9477 if (!ret)
9478 hba->is_sys_suspended = false;
1a547cbc 9479 hba->system_suspending = false;
b294ff3e
AD		 9480 up(&hba->host_sem);
9481 return ret;
9482}
9483#endif
9484
9485static void ufshcd_wl_shutdown(struct device *dev)
9486{
9487 struct scsi_device *sdev = to_scsi_device(dev);
9488 struct ufs_hba *hba;
9489
9490 hba = shost_priv(sdev->host);
9491
9492 down(&hba->host_sem);
9493 hba->shutting_down = true;
9494 up(&hba->host_sem);
9495
9496 /* Turn on everything while shutting down */
9497 ufshcd_rpm_get_sync(hba);
9498 scsi_device_quiesce(sdev);
9499 shost_for_each_device(sdev, hba->host) {
e2106584 9500 if (sdev == hba->ufs_device_wlun)
b294ff3e
AD		 9501 continue;
9502 scsi_device_quiesce(sdev);
9503 }
9504 __ufshcd_wl_suspend(hba, UFS_SHUTDOWN_PM);
9505}
9506
9507/**
9508 * ufshcd_suspend - helper function for suspend operations
9509 * @hba: per adapter instance
9510 *
9511 * This function will put disable irqs, turn off clocks
9512 * and set vreg and hba-vreg in lpm mode.
b294ff3e
AD		 9513 */
9514static int ufshcd_suspend(struct ufs_hba *hba)
9515{
9516 int ret;
9517
9518 if (!hba->is_powered)
9519 return 0;
9520 /*
9521 * Disable the host irq as host controller as there won't be any
9522 * host controller transaction expected till resume.
9523 */
57d104c1 9524 ufshcd_disable_irq(hba);
b294ff3e
AD		 9525 ret = ufshcd_setup_clocks(hba, false);
9526 if (ret) {
9527 ufshcd_enable_irq(hba);
9528 return ret;
9529 }
2dec9475
CG		 9530 if (ufshcd_is_clkgating_allowed(hba)) {
9531 hba->clk_gating.state = CLKS_OFF;
9532 trace_ufshcd_clk_gating(dev_name(hba->dev),
9533 hba->clk_gating.state);
9534 }
b294ff3e
AD		 9535
9536 ufshcd_vreg_set_lpm(hba);
9537 /* Put the host controller in low power mode if possible */
9538 ufshcd_hba_vreg_set_lpm(hba);
9539 return ret;
9540}
9541
9bb25e5d 9542#ifdef CONFIG_PM
b294ff3e
AD		 9543/**
9544 * ufshcd_resume - helper function for resume operations
9545 * @hba: per adapter instance
9546 *
9547 * This function basically turns on the regulators, clocks and
9548 * irqs of the hba.
b294ff3e
AD		 9549 *
9550 * Returns 0 for success and non-zero for failure
9551 */
9552static int ufshcd_resume(struct ufs_hba *hba)
9553{
9554 int ret;
9555
9556 if (!hba->is_powered)
9557 return 0;
9558
9559 ufshcd_hba_vreg_set_hpm(hba);
9560 ret = ufshcd_vreg_set_hpm(hba);
9561 if (ret)
9562 goto out;
9563
9564 /* Make sure clocks are enabled before accessing controller */
9565 ret = ufshcd_setup_clocks(hba, true);
9566 if (ret)
9567 goto disable_vreg;
9568
9569 /* enable the host irq as host controller would be active soon */
9570 ufshcd_enable_irq(hba);
9571 goto out;
9572
528db9e5
ZC		 9573disable_vreg:
9574 ufshcd_vreg_set_lpm(hba);
57d104c1 9575out:
8808b4e9 9576 if (ret)
e965e5e0 9577 ufshcd_update_evt_hist(hba, UFS_EVT_RESUME_ERR, (u32)ret);
57d104c1
SJ		 9578 return ret;
9579}
9bb25e5d 9580#endif /* CONFIG_PM */
57d104c1 9581
9bb25e5d 9582#ifdef CONFIG_PM_SLEEP
57d104c1 9583/**
f1ecbe1e
BVA		 9584 * ufshcd_system_suspend - system suspend callback
9585 * @dev: Device associated with the UFS controller.
57d104c1 9586 *
f1ecbe1e
BVA		 9587 * Executed before putting the system into a sleep state in which the contents
9588 * of main memory are preserved.
57d104c1
SJ		 9589 *
9590 * Returns 0 for success and non-zero for failure
9591 */
f1ecbe1e 9592int ufshcd_system_suspend(struct device *dev)
57d104c1 9593{
f1ecbe1e 9594 struct ufs_hba *hba = dev_get_drvdata(dev);
57d104c1 9595 int ret = 0;
7ff5ab47 9596 ktime_t start = ktime_get();
57d104c1 9597
b294ff3e 9598 if (pm_runtime_suspended(hba->dev))
0b257734 9599 goto out;
57d104c1 9600
b294ff3e 9601 ret = ufshcd_suspend(hba);
57d104c1 9602out:
7ff5ab47 9603 trace_ufshcd_system_suspend(dev_name(hba->dev), ret,
9604 ktime_to_us(ktime_sub(ktime_get(), start)),
73eba2be 9605 hba->curr_dev_pwr_mode, hba->uic_link_state);
57d104c1
SJ		 9606 return ret;
9607}
9608EXPORT_SYMBOL(ufshcd_system_suspend);
9609
9610/**
f1ecbe1e
BVA		 9611 * ufshcd_system_resume - system resume callback
9612 * @dev: Device associated with the UFS controller.
9613 *
9614 * Executed after waking the system up from a sleep state in which the contents
9615 * of main memory were preserved.
57d104c1
SJ		 9616 *
9617 * Returns 0 for success and non-zero for failure
9618 */
f1ecbe1e 9619int ufshcd_system_resume(struct device *dev)
57d104c1 9620{
f1ecbe1e 9621 struct ufs_hba *hba = dev_get_drvdata(dev);
7ff5ab47 9622 ktime_t start = ktime_get();
f1ecbe1e 9623 int ret = 0;
7ff5ab47 9624
b294ff3e 9625 if (pm_runtime_suspended(hba->dev))
7ff5ab47 9626 goto out;
b294ff3e
AD		 9627
9628 ret = ufshcd_resume(hba);
9629
7ff5ab47 9630out:
9631 trace_ufshcd_system_resume(dev_name(hba->dev), ret,
9632 ktime_to_us(ktime_sub(ktime_get(), start)),
73eba2be 9633 hba->curr_dev_pwr_mode, hba->uic_link_state);
b294ff3e 9634
7ff5ab47 9635 return ret;
7a3e97b0 9636}
57d104c1 9637EXPORT_SYMBOL(ufshcd_system_resume);
9bb25e5d 9638#endif /* CONFIG_PM_SLEEP */
3b1d0580 9639
9bb25e5d 9640#ifdef CONFIG_PM
57d104c1 9641/**
f1ecbe1e
BVA		 9642 * ufshcd_runtime_suspend - runtime suspend callback
9643 * @dev: Device associated with the UFS controller.
57d104c1
SJ		 9644 *
9645 * Check the description of ufshcd_suspend() function for more details.
9646 *
9647 * Returns 0 for success and non-zero for failure
9648 */
f1ecbe1e 9649int ufshcd_runtime_suspend(struct device *dev)
66ec6d59 9650{
f1ecbe1e 9651 struct ufs_hba *hba = dev_get_drvdata(dev);
b294ff3e 9652 int ret;
7ff5ab47 9653 ktime_t start = ktime_get();
9654
b294ff3e
AD		 9655 ret = ufshcd_suspend(hba);
9656
7ff5ab47 9657 trace_ufshcd_runtime_suspend(dev_name(hba->dev), ret,
9658 ktime_to_us(ktime_sub(ktime_get(), start)),
73eba2be 9659 hba->curr_dev_pwr_mode, hba->uic_link_state);
7ff5ab47 9660 return ret;
66ec6d59
SRT		 9661}
9662EXPORT_SYMBOL(ufshcd_runtime_suspend);
9663
57d104c1
SJ		 9664/**
9665 * ufshcd_runtime_resume - runtime resume routine
f1ecbe1e 9666 * @dev: Device associated with the UFS controller.
57d104c1 9667 *
b294ff3e 9668 * This function basically brings controller
57d104c1
SJ		 9669 * to active state. Following operations are done in this function:
9670 *
9671 * 1. Turn on all the controller related clocks
b294ff3e 9672 * 2. Turn ON VCC rail
57d104c1 9673 */
f1ecbe1e 9674int ufshcd_runtime_resume(struct device *dev)
66ec6d59 9675{
f1ecbe1e 9676 struct ufs_hba *hba = dev_get_drvdata(dev);
b294ff3e 9677 int ret;
7ff5ab47 9678 ktime_t start = ktime_get();
9679
b294ff3e
AD		 9680 ret = ufshcd_resume(hba);
9681
7ff5ab47 9682 trace_ufshcd_runtime_resume(dev_name(hba->dev), ret,
9683 ktime_to_us(ktime_sub(ktime_get(), start)),
73eba2be 9684 hba->curr_dev_pwr_mode, hba->uic_link_state);
7ff5ab47 9685 return ret;
66ec6d59
SRT		 9686}
9687EXPORT_SYMBOL(ufshcd_runtime_resume);
9bb25e5d 9688#endif /* CONFIG_PM */
66ec6d59 9689
57d104c1
SJ		 9690/**
9691 * ufshcd_shutdown - shutdown routine
9692 * @hba: per adapter instance
9693 *
b294ff3e
AD		 9694 * This function would turn off both UFS device and UFS hba
9695 * regulators. It would also disable clocks.
57d104c1
SJ		 9696 *
9697 * Returns 0 always to allow force shutdown even in case of errors.
9698 */
9699int ufshcd_shutdown(struct ufs_hba *hba)
9700{
57d104c1 9701 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba))
00511d2a 9702 ufshcd_suspend(hba);
57d104c1 9703
88a92d6a 9704 hba->is_powered = false;
57d104c1
SJ		 9705 /* allow force shutdown even in case of errors */
9706 return 0;
9707}
9708EXPORT_SYMBOL(ufshcd_shutdown);
9709
7a3e97b0 9710/**
3b1d0580 9711 * ufshcd_remove - de-allocate SCSI host and host memory space
7a3e97b0 9712 * data structure memory
8aa29f19 9713 * @hba: per adapter instance
7a3e97b0 9714 */
3b1d0580 9715void ufshcd_remove(struct ufs_hba *hba)
7a3e97b0 9716{
e2106584 9717 if (hba->ufs_device_wlun)
b294ff3e 9718 ufshcd_rpm_get_sync(hba);
e88e2d32 9719 ufs_hwmon_remove(hba);
df032bf2 9720 ufs_bsg_remove(hba);
4b5f4907 9721 ufshpb_remove(hba);
cbb6813e 9722 ufs_sysfs_remove_nodes(hba->dev);
6f8191fd 9723 blk_mq_destroy_queue(hba->tmf_queue);
2b3f056f 9724 blk_put_queue(hba->tmf_queue);
69a6c269 9725 blk_mq_free_tag_set(&hba->tmf_tag_set);
cfdf9c91 9726 scsi_remove_host(hba->host);
7a3e97b0 9727 /* disable interrupts */
2fbd009b 9728 ufshcd_disable_intr(hba, hba->intr_mask);
5cac1095 9729 ufshcd_hba_stop(hba);
aa497613 9730 ufshcd_hba_exit(hba);
3b1d0580
VH		 9731}
9732EXPORT_SYMBOL_GPL(ufshcd_remove);
9733
47555a5c
YG		 9734/**
9735 * ufshcd_dealloc_host - deallocate Host Bus Adapter (HBA)
9736 * @hba: pointer to Host Bus Adapter (HBA)
9737 */
9738void ufshcd_dealloc_host(struct ufs_hba *hba)
9739{
9740 scsi_host_put(hba->host);
9741}
9742EXPORT_SYMBOL_GPL(ufshcd_dealloc_host);
9743
ca3d7bf9
AM		 9744/**
9745 * ufshcd_set_dma_mask - Set dma mask based on the controller
9746 * addressing capability
9747 * @hba: per adapter instance
9748 *
9749 * Returns 0 for success, non-zero for failure
9750 */
9751static int ufshcd_set_dma_mask(struct ufs_hba *hba)
9752{
9753 if (hba->capabilities & MASK_64_ADDRESSING_SUPPORT) {
9754 if (!dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(64)))
9755 return 0;
9756 }
9757 return dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(32));
9758}
9759
7a3e97b0 9760/**
5c0c28a8 9761 * ufshcd_alloc_host - allocate Host Bus Adapter (HBA)
3b1d0580
VH		 9762 * @dev: pointer to device handle
9763 * @hba_handle: driver private handle
7a3e97b0
SY		 9764 * Returns 0 on success, non-zero value on failure
9765 */
5c0c28a8 9766int ufshcd_alloc_host(struct device *dev, struct ufs_hba **hba_handle)
7a3e97b0
SY		 9767{
9768 struct Scsi_Host *host;
9769 struct ufs_hba *hba;
5c0c28a8 9770 int err = 0;
7a3e97b0 9771
3b1d0580
VH		 9772 if (!dev) {
9773 dev_err(dev,
9774 "Invalid memory reference for dev is NULL\n");
9775 err = -ENODEV;
7a3e97b0
SY		 9776 goto out_error;
9777 }
9778
7a3e97b0
SY		 9779 host = scsi_host_alloc(&ufshcd_driver_template,
9780 sizeof(struct ufs_hba));
9781 if (!host) {
3b1d0580 9782 dev_err(dev, "scsi_host_alloc failed\n");
7a3e97b0 9783 err = -ENOMEM;
3b1d0580 9784 goto out_error;
7a3e97b0 9785 }
eaab9b57 9786 host->nr_maps = HCTX_TYPE_POLL + 1;
7a3e97b0 9787 hba = shost_priv(host);
7a3e97b0 9788 hba->host = host;
3b1d0580 9789 hba->dev = dev;
9e1e8a75 9790 hba->dev_ref_clk_freq = REF_CLK_FREQ_INVAL;
1cbc9ad3 9791 hba->nop_out_timeout = NOP_OUT_TIMEOUT;
ada1e653 9792 ufshcd_set_sg_entry_size(hba, sizeof(struct ufshcd_sg_entry));
566ec9ad 9793 INIT_LIST_HEAD(&hba->clk_list_head);
169f5eb2
BVA		 9794 spin_lock_init(&hba->outstanding_lock);
9795
9796 *hba_handle = hba;
566ec9ad 9797
5c0c28a8
SRT		 9798out_error:
9799 return err;
9800}
9801EXPORT_SYMBOL(ufshcd_alloc_host);
9802
69a6c269
BVA		 9803/* This function exists because blk_mq_alloc_tag_set() requires this. */
9804static blk_status_t ufshcd_queue_tmf(struct blk_mq_hw_ctx *hctx,
9805 const struct blk_mq_queue_data *qd)
9806{
9807 WARN_ON_ONCE(true);
9808 return BLK_STS_NOTSUPP;
9809}
9810
9811static const struct blk_mq_ops ufshcd_tmf_ops = {
9812 .queue_rq = ufshcd_queue_tmf,
9813};
9814
5c0c28a8
SRT		 9815/**
9816 * ufshcd_init - Driver initialization routine
9817 * @hba: per-adapter instance
9818 * @mmio_base: base register address
9819 * @irq: Interrupt line of device
9820 * Returns 0 on success, non-zero value on failure
9821 */
9822int ufshcd_init(struct ufs_hba *hba, void __iomem *mmio_base, unsigned int irq)
9823{
9824 int err;
9825 struct Scsi_Host *host = hba->host;
9826 struct device *dev = hba->dev;
88b09900 9827 char eh_wq_name[sizeof("ufs_eh_wq_00")];
5c0c28a8 9828
21ad0e49
BVA		 9829 /*
9830 * dev_set_drvdata() must be called before any callbacks are registered
9831 * that use dev_get_drvdata() (frequency scaling, clock scaling, hwmon,
9832 * sysfs).
9833 */
9834 dev_set_drvdata(dev, hba);
9835
5c0c28a8
SRT		 9836 if (!mmio_base) {
9837 dev_err(hba->dev,
9838 "Invalid memory reference for mmio_base is NULL\n");
9839 err = -ENODEV;
9840 goto out_error;
9841 }
9842
3b1d0580
VH		 9843 hba->mmio_base = mmio_base;
9844 hba->irq = irq;
90b8491c 9845 hba->vps = &ufs_hba_vps;
7a3e97b0 9846
aa497613 9847 err = ufshcd_hba_init(hba);
5c0c28a8
SRT		 9848 if (err)
9849 goto out_error;
9850
7a3e97b0 9851 /* Read capabilities registers */
df043c74
ST		 9852 err = ufshcd_hba_capabilities(hba);
9853 if (err)
9854 goto out_disable;
7a3e97b0
SY		 9855
9856 /* Get UFS version supported by the controller */
9857 hba->ufs_version = ufshcd_get_ufs_version(hba);
9858
2fbd009b
SJ		 9859 /* Get Interrupt bit mask per version */
9860 hba->intr_mask = ufshcd_get_intr_mask(hba);
9861
ca3d7bf9
AM		 9862 err = ufshcd_set_dma_mask(hba);
9863 if (err) {
9864 dev_err(hba->dev, "set dma mask failed\n");
9865 goto out_disable;
9866 }
9867
7a3e97b0
SY		 9868 /* Allocate memory for host memory space */
9869 err = ufshcd_memory_alloc(hba);
9870 if (err) {
3b1d0580
VH		 9871 dev_err(hba->dev, "Memory allocation failed\n");
9872 goto out_disable;
7a3e97b0
SY		 9873 }
9874
9875 /* Configure LRB */
9876 ufshcd_host_memory_configure(hba);
9877
945c3cca
BVA		 9878 host->can_queue = hba->nutrs - UFSHCD_NUM_RESERVED;
9879 host->cmd_per_lun = hba->nutrs - UFSHCD_NUM_RESERVED;
7a3e97b0 9880 host->max_id = UFSHCD_MAX_ID;
0ce147d4 9881 host->max_lun = UFS_MAX_LUNS;
7a3e97b0
SY		 9882 host->max_channel = UFSHCD_MAX_CHANNEL;
9883 host->unique_id = host->host_no;
a851b2bd 9884 host->max_cmd_len = UFS_CDB_SIZE;
7a3e97b0 9885
7eb584db
DR		 9886 hba->max_pwr_info.is_valid = false;
9887
88b09900
AH		 9888 /* Initialize work queues */
9889 snprintf(eh_wq_name, sizeof(eh_wq_name), "ufs_eh_wq_%d",
9890 hba->host->host_no);
9891 hba->eh_wq = create_singlethread_workqueue(eh_wq_name);
9892 if (!hba->eh_wq) {
9893 dev_err(hba->dev, "%s: failed to create eh workqueue\n",
9894 __func__);
9895 err = -ENOMEM;
9896 goto out_disable;
9897 }
9898 INIT_WORK(&hba->eh_work, ufshcd_err_handler);
66ec6d59 9899 INIT_WORK(&hba->eeh_work, ufshcd_exception_event_handler);
7a3e97b0 9900
9cd20d3f 9901 sema_init(&hba->host_sem, 1);
88a92d6a 9902
6ccf44fe
SJ		 9903 /* Initialize UIC command mutex */
9904 mutex_init(&hba->uic_cmd_mutex);
9905
5a0b0cb9
SRT		 9906 /* Initialize mutex for device management commands */
9907 mutex_init(&hba->dev_cmd.lock);
9908
cd469475
AH		 9909 /* Initialize mutex for exception event control */
9910 mutex_init(&hba->ee_ctrl_mutex);
9911
a3cd5ec5 9912 init_rwsem(&hba->clk_scaling_lock);
9913
1ab27c9c 9914 ufshcd_init_clk_gating(hba);
199ef13c 9915
eebcc196
VG		 9916 ufshcd_init_clk_scaling(hba);
9917
199ef13c
YG		 9918 /*
9919 * In order to avoid any spurious interrupt immediately after
9920 * registering UFS controller interrupt handler, clear any pending UFS
9921 * interrupt status and disable all the UFS interrupts.
9922 */
9923 ufshcd_writel(hba, ufshcd_readl(hba, REG_INTERRUPT_STATUS),
9924 REG_INTERRUPT_STATUS);
9925 ufshcd_writel(hba, 0, REG_INTERRUPT_ENABLE);
9926 /*
9927 * Make sure that UFS interrupts are disabled and any pending interrupt
9928 * status is cleared before registering UFS interrupt handler.
9929 */
9930 mb();
9931
7a3e97b0 9932 /* IRQ registration */
2953f850 9933 err = devm_request_irq(dev, irq, ufshcd_intr, IRQF_SHARED, UFSHCD, hba);
7a3e97b0 9934 if (err) {
3b1d0580 9935 dev_err(hba->dev, "request irq failed\n");
4543d9d7 9936 goto out_disable;
57d104c1
SJ		 9937 } else {
9938 hba->is_irq_enabled = true;
7a3e97b0
SY		 9939 }
9940
3b1d0580 9941 err = scsi_add_host(host, hba->dev);
7a3e97b0 9942 if (err) {
3b1d0580 9943 dev_err(hba->dev, "scsi_add_host failed\n");
4543d9d7 9944 goto out_disable;
7a3e97b0
SY		 9945 }
9946
69a6c269
BVA		 9947 hba->tmf_tag_set = (struct blk_mq_tag_set) {
9948 .nr_hw_queues = 1,
9949 .queue_depth = hba->nutmrs,
9950 .ops = &ufshcd_tmf_ops,
9951 .flags = BLK_MQ_F_NO_SCHED,
9952 };
9953 err = blk_mq_alloc_tag_set(&hba->tmf_tag_set);
9954 if (err < 0)
511a083b 9955 goto out_remove_scsi_host;
69a6c269
BVA		 9956 hba->tmf_queue = blk_mq_init_queue(&hba->tmf_tag_set);
9957 if (IS_ERR(hba->tmf_queue)) {
9958 err = PTR_ERR(hba->tmf_queue);
9959 goto free_tmf_tag_set;
9960 }
f5ef336f
AH		 9961 hba->tmf_rqs = devm_kcalloc(hba->dev, hba->nutmrs,
9962 sizeof(*hba->tmf_rqs), GFP_KERNEL);
9963 if (!hba->tmf_rqs) {
9964 err = -ENOMEM;
9965 goto free_tmf_queue;
9966 }
69a6c269 9967
d8d9f793 9968 /* Reset the attached device */
31a5d9ca 9969 ufshcd_device_reset(hba);
d8d9f793 9970
df043c74
ST		 9971 ufshcd_init_crypto(hba);
9972
6ccf44fe
SJ		 9973 /* Host controller enable */
9974 err = ufshcd_hba_enable(hba);
7a3e97b0 9975 if (err) {
6ccf44fe 9976 dev_err(hba->dev, "Host controller enable failed\n");
e965e5e0 9977 ufshcd_print_evt_hist(hba);
6ba65588 9978 ufshcd_print_host_state(hba);
69a6c269 9979 goto free_tmf_queue;
7a3e97b0 9980 }
6ccf44fe 9981
0c8f7586 9982 /*
9983 * Set the default power management level for runtime and system PM.
9984 * Default power saving mode is to keep UFS link in Hibern8 state
9985 * and UFS device in sleep state.
9986 */
9987 hba->rpm_lvl = ufs_get_desired_pm_lvl_for_dev_link_state(
9988 UFS_SLEEP_PWR_MODE,
9989 UIC_LINK_HIBERN8_STATE);
9990 hba->spm_lvl = ufs_get_desired_pm_lvl_for_dev_link_state(
9991 UFS_SLEEP_PWR_MODE,
9992 UIC_LINK_HIBERN8_STATE);
9993
51dd905b
SC		 9994 INIT_DELAYED_WORK(&hba->rpm_dev_flush_recheck_work,
9995 ufshcd_rpm_dev_flush_recheck_work);
9996
ad448378 9997 /* Set the default auto-hiberate idle timer value to 150 ms */
f571b377 9998 if (ufshcd_is_auto_hibern8_supported(hba) && !hba->ahit) {
ad448378
AH		 9999 hba->ahit = FIELD_PREP(UFSHCI_AHIBERN8_TIMER_MASK, 150) |
10000 FIELD_PREP(UFSHCI_AHIBERN8_SCALE_MASK, 3);
10001 }
10002
62694735
SRT		 10003 /* Hold auto suspend until async scan completes */
10004 pm_runtime_get_sync(dev);
38135535 10005 atomic_set(&hba->scsi_block_reqs_cnt, 0);
57d104c1 10006 /*
7caf489b 10007 * We are assuming that device wasn't put in sleep/power-down
10008 * state exclusively during the boot stage before kernel.
10009 * This assumption helps avoid doing link startup twice during
10010 * ufshcd_probe_hba().
57d104c1 10011 */
7caf489b 10012 ufshcd_set_ufs_dev_active(hba);
57d104c1 10013
6ccf44fe 10014 async_schedule(ufshcd_async_scan, hba);
cbb6813e 10015 ufs_sysfs_add_nodes(hba->dev);
6ccf44fe 10016
1084514c 10017 device_enable_async_suspend(dev);
7a3e97b0
SY		 10018 return 0;
10019
69a6c269 10020free_tmf_queue:
6f8191fd 10021 blk_mq_destroy_queue(hba->tmf_queue);
2b3f056f 10022 blk_put_queue(hba->tmf_queue);
69a6c269
BVA		 10023free_tmf_tag_set:
10024 blk_mq_free_tag_set(&hba->tmf_tag_set);
3b1d0580
VH		 10025out_remove_scsi_host:
10026 scsi_remove_host(hba->host);
3b1d0580 10027out_disable:
57d104c1 10028 hba->is_irq_enabled = false;
aa497613 10029 ufshcd_hba_exit(hba);
3b1d0580
VH		 10030out_error:
10031 return err;
10032}
10033EXPORT_SYMBOL_GPL(ufshcd_init);
10034
b294ff3e
AD		 10035void ufshcd_resume_complete(struct device *dev)
10036{
10037 struct ufs_hba *hba = dev_get_drvdata(dev);
10038
10039 if (hba->complete_put) {
10040 ufshcd_rpm_put(hba);
10041 hba->complete_put = false;
10042 }
b294ff3e
AD		 10043}
10044EXPORT_SYMBOL_GPL(ufshcd_resume_complete);
10045
ddba1cf7
AH		 10046static bool ufshcd_rpm_ok_for_spm(struct ufs_hba *hba)
10047{
e2106584 10048 struct device *dev = &hba->ufs_device_wlun->sdev_gendev;
ddba1cf7
AH		 10049 enum ufs_dev_pwr_mode dev_pwr_mode;
10050 enum uic_link_state link_state;
10051 unsigned long flags;
10052 bool res;
10053
10054 spin_lock_irqsave(&dev->power.lock, flags);
10055 dev_pwr_mode = ufs_get_pm_lvl_to_dev_pwr_mode(hba->spm_lvl);
10056 link_state = ufs_get_pm_lvl_to_link_pwr_state(hba->spm_lvl);
10057 res = pm_runtime_suspended(dev) &&
10058 hba->curr_dev_pwr_mode == dev_pwr_mode &&
10059 hba->uic_link_state == link_state &&
10060 !hba->dev_info.b_rpm_dev_flush_capable;
10061 spin_unlock_irqrestore(&dev->power.lock, flags);
10062
10063 return res;
10064}
10065
10066int __ufshcd_suspend_prepare(struct device *dev, bool rpm_ok_for_spm)
b294ff3e
AD		 10067{
10068 struct ufs_hba *hba = dev_get_drvdata(dev);
10069 int ret;
10070
10071 /*
10072 * SCSI assumes that runtime-pm and system-pm for scsi drivers
10073 * are same. And it doesn't wake up the device for system-suspend
10074 * if it's runtime suspended. But ufs doesn't follow that.
10075 * Refer ufshcd_resume_complete()
10076 */
e2106584 10077 if (hba->ufs_device_wlun) {
ddba1cf7
AH		 10078 /* Prevent runtime suspend */
10079 ufshcd_rpm_get_noresume(hba);
10080 /*
10081 * Check if already runtime suspended in same state as system
10082 * suspend would be.
10083 */
10084 if (!rpm_ok_for_spm || !ufshcd_rpm_ok_for_spm(hba)) {
10085 /* RPM state is not ok for SPM, so runtime resume */
10086 ret = ufshcd_rpm_resume(hba);
10087 if (ret < 0 && ret != -EACCES) {
10088 ufshcd_rpm_put(hba);
10089 return ret;
10090 }
b294ff3e
AD		 10091 }
10092 hba->complete_put = true;
10093 }
b294ff3e
AD		 10094 return 0;
10095}
ddba1cf7
AH		 10096EXPORT_SYMBOL_GPL(__ufshcd_suspend_prepare);
10097
10098int ufshcd_suspend_prepare(struct device *dev)
10099{
10100 return __ufshcd_suspend_prepare(dev, true);
10101}
b294ff3e
AD		 10102EXPORT_SYMBOL_GPL(ufshcd_suspend_prepare);
10103
10104#ifdef CONFIG_PM_SLEEP
10105static int ufshcd_wl_poweroff(struct device *dev)
10106{
10107 struct scsi_device *sdev = to_scsi_device(dev);
10108 struct ufs_hba *hba = shost_priv(sdev->host);
10109
10110 __ufshcd_wl_suspend(hba, UFS_SHUTDOWN_PM);
10111 return 0;
10112}
10113#endif
10114
10115static int ufshcd_wl_probe(struct device *dev)
10116{
10117 struct scsi_device *sdev = to_scsi_device(dev);
10118
10119 if (!is_device_wlun(sdev))
10120 return -ENODEV;
10121
10122 blk_pm_runtime_init(sdev->request_queue, dev);
10123 pm_runtime_set_autosuspend_delay(dev, 0);
10124 pm_runtime_allow(dev);
10125
10126 return 0;
10127}
10128
10129static int ufshcd_wl_remove(struct device *dev)
10130{
10131 pm_runtime_forbid(dev);
10132 return 0;
10133}
10134
10135static const struct dev_pm_ops ufshcd_wl_pm_ops = {
10136#ifdef CONFIG_PM_SLEEP
10137 .suspend = ufshcd_wl_suspend,
10138 .resume = ufshcd_wl_resume,
10139 .freeze = ufshcd_wl_suspend,
10140 .thaw = ufshcd_wl_resume,
10141 .poweroff = ufshcd_wl_poweroff,
10142 .restore = ufshcd_wl_resume,
10143#endif
10144 SET_RUNTIME_PM_OPS(ufshcd_wl_runtime_suspend, ufshcd_wl_runtime_resume, NULL)
10145};
10146
10147/*
10148 * ufs_dev_wlun_template - describes ufs device wlun
10149 * ufs-device wlun - used to send pm commands
10150 * All luns are consumers of ufs-device wlun.
10151 *
10152 * Currently, no sd driver is present for wluns.
10153 * Hence the no specific pm operations are performed.
10154 * With ufs design, SSU should be sent to ufs-device wlun.
10155 * Hence register a scsi driver for ufs wluns only.
10156 */
10157static struct scsi_driver ufs_dev_wlun_template = {
10158 .gendrv = {
10159 .name = "ufs_device_wlun",
10160 .owner = THIS_MODULE,
10161 .probe = ufshcd_wl_probe,
10162 .remove = ufshcd_wl_remove,
10163 .pm = &ufshcd_wl_pm_ops,
10164 .shutdown = ufshcd_wl_shutdown,
10165 },
10166};
10167
b6cacaf2
AH		 10168static int __init ufshcd_core_init(void)
10169{
b294ff3e
AD		 10170 int ret;
10171
b6cacaf2 10172 ufs_debugfs_init();
b294ff3e
AD		 10173
10174 ret = scsi_register_driver(&ufs_dev_wlun_template.gendrv);
10175 if (ret)
edc0596c 10176 ufs_debugfs_exit();
b294ff3e 10177 return ret;
b6cacaf2
AH		 10178}
10179
10180static void __exit ufshcd_core_exit(void)
10181{
10182 ufs_debugfs_exit();
b294ff3e 10183 scsi_unregister_driver(&ufs_dev_wlun_template.gendrv);
b6cacaf2
AH		 10184}
10185
10186module_init(ufshcd_core_init);
10187module_exit(ufshcd_core_exit);
10188
3b1d0580
VH		 10189MODULE_AUTHOR("Santosh Yaragnavi <santosh.sy@samsung.com>");
10190MODULE_AUTHOR("Vinayak Holikatti <h.vinayak@samsung.com>");
e0eca63e 10191MODULE_DESCRIPTION("Generic UFS host controller driver Core");
7a3e97b0 10192MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)