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tty: localise ptychar and make it const
[linux-2.6-block.git] / drivers / tty / synclink_gt.c
CommitLineData
e3b3d0f5 1// SPDX-License-Identifier: GPL-1.0+
705b6c7b 2/*
705b6c7b
PF		 3 * Device driver for Microgate SyncLink GT serial adapters.
4 *
5 * written by Paul Fulghum for Microgate Corporation
6 * paulkf@microgate.com
7 *
8 * Microgate and SyncLink are trademarks of Microgate Corporation
9 *
705b6c7b
PF		 10 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
11 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
12 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
13 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
14 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
15 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
16 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
17 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
18 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
19 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
20 * OF THE POSSIBILITY OF SUCH DAMAGE.
21 */
22
23/*
24 * DEBUG OUTPUT DEFINITIONS
25 *
26 * uncomment lines below to enable specific types of debug output
27 *
28 * DBGINFO information - most verbose output
29 * DBGERR serious errors
30 * DBGBH bottom half service routine debugging
31 * DBGISR interrupt service routine debugging
32 * DBGDATA output receive and transmit data
33 * DBGTBUF output transmit DMA buffers and registers
34 * DBGRBUF output receive DMA buffers and registers
35 */
36
37#define DBGINFO(fmt) if (debug_level >= DEBUG_LEVEL_INFO) printk fmt
38#define DBGERR(fmt) if (debug_level >= DEBUG_LEVEL_ERROR) printk fmt
39#define DBGBH(fmt) if (debug_level >= DEBUG_LEVEL_BH) printk fmt
40#define DBGISR(fmt) if (debug_level >= DEBUG_LEVEL_ISR) printk fmt
41#define DBGDATA(info, buf, size, label) if (debug_level >= DEBUG_LEVEL_DATA) trace_block((info), (buf), (size), (label))
f602501d
AC		 42/*#define DBGTBUF(info) dump_tbufs(info)*/
43/*#define DBGRBUF(info) dump_rbufs(info)*/
705b6c7b
PF		 44
45
705b6c7b 46#include <linux/module.h>
705b6c7b
PF		 47#include <linux/errno.h>
48#include <linux/signal.h>
49#include <linux/sched.h>
50#include <linux/timer.h>
51#include <linux/interrupt.h>
52#include <linux/pci.h>
53#include <linux/tty.h>
54#include <linux/tty_flip.h>
55#include <linux/serial.h>
56#include <linux/major.h>
57#include <linux/string.h>
58#include <linux/fcntl.h>
59#include <linux/ptrace.h>
60#include <linux/ioport.h>
61#include <linux/mm.h>
a18c56e5 62#include <linux/seq_file.h>
705b6c7b
PF		 63#include <linux/slab.h>
64#include <linux/netdevice.h>
65#include <linux/vmalloc.h>
66#include <linux/init.h>
67#include <linux/delay.h>
68#include <linux/ioctl.h>
69#include <linux/termios.h>
70#include <linux/bitops.h>
71#include <linux/workqueue.h>
72#include <linux/hdlc.h>
3dd1247f 73#include <linux/synclink.h>
705b6c7b 74
705b6c7b
PF		 75#include <asm/io.h>
76#include <asm/irq.h>
77#include <asm/dma.h>
78#include <asm/types.h>
7c0f6ba6 79#include <linux/uaccess.h>
705b6c7b 80
af69c7f9
PF		 81#if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_GT_MODULE))
82#define SYNCLINK_GENERIC_HDLC 1
83#else
84#define SYNCLINK_GENERIC_HDLC 0
705b6c7b
PF		 85#endif
86
87/*
88 * module identification
89 */
90static char *driver_name = "SyncLink GT";
076fe303 91static char *slgt_driver_name = "synclink_gt";
705b6c7b
PF		 92static char *tty_dev_prefix = "ttySLG";
93MODULE_LICENSE("GPL");
94#define MGSL_MAGIC 0x5401
a077c1a0 95#define MAX_DEVICES 32
705b6c7b 96
0846b762 97static const struct pci_device_id pci_table[] = {
705b6c7b 98 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
6f84be84 99 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT2_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
705b6c7b
PF		 100 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT4_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
101 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_AC_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
102 {0,}, /* terminate list */
103};
104MODULE_DEVICE_TABLE(pci, pci_table);
105
106static int init_one(struct pci_dev *dev,const struct pci_device_id *ent);
107static void remove_one(struct pci_dev *dev);
108static struct pci_driver pci_driver = {
109 .name = "synclink_gt",
110 .id_table = pci_table,
111 .probe = init_one,
91116cba 112 .remove = remove_one,
705b6c7b
PF		 113};
114
0fab6de0 115static bool pci_registered;
705b6c7b
PF		 116
117/*
118 * module configuration and status
119 */
120static struct slgt_info *slgt_device_list;
121static int slgt_device_count;
122
123static int ttymajor;
124static int debug_level;
125static int maxframe[MAX_DEVICES];
705b6c7b
PF		 126
127module_param(ttymajor, int, 0);
128module_param(debug_level, int, 0);
129module_param_array(maxframe, int, NULL, 0);
705b6c7b
PF		 130
131MODULE_PARM_DESC(ttymajor, "TTY major device number override: 0=auto assigned");
132MODULE_PARM_DESC(debug_level, "Debug syslog output: 0=disabled, 1 to 5=increasing detail");
133MODULE_PARM_DESC(maxframe, "Maximum frame size used by device (4096 to 65535)");
705b6c7b
PF		 134
135/*
136 * tty support and callbacks
137 */
705b6c7b
PF		 138static struct tty_driver *serial_driver;
139
140static int open(struct tty_struct *tty, struct file * filp);
141static void close(struct tty_struct *tty, struct file * filp);
142static void hangup(struct tty_struct *tty);
606d099c 143static void set_termios(struct tty_struct *tty, struct ktermios *old_termios);
705b6c7b
PF		 144
145static int write(struct tty_struct *tty, const unsigned char *buf, int count);
55da7789 146static int put_char(struct tty_struct *tty, unsigned char ch);
705b6c7b
PF		 147static void send_xchar(struct tty_struct *tty, char ch);
148static void wait_until_sent(struct tty_struct *tty, int timeout);
149static int write_room(struct tty_struct *tty);
150static void flush_chars(struct tty_struct *tty);
151static void flush_buffer(struct tty_struct *tty);
152static void tx_hold(struct tty_struct *tty);
153static void tx_release(struct tty_struct *tty);
154
6caa76b7 155static int ioctl(struct tty_struct *tty, unsigned int cmd, unsigned long arg);
705b6c7b
PF		 156static int chars_in_buffer(struct tty_struct *tty);
157static void throttle(struct tty_struct * tty);
158static void unthrottle(struct tty_struct * tty);
9e98966c 159static int set_break(struct tty_struct *tty, int break_state);
705b6c7b
PF		 160
161/*
162 * generic HDLC support and callbacks
163 */
af69c7f9 164#if SYNCLINK_GENERIC_HDLC
705b6c7b
PF		 165#define dev_to_port(D) (dev_to_hdlc(D)->priv)
166static void hdlcdev_tx_done(struct slgt_info *info);
167static void hdlcdev_rx(struct slgt_info *info, char *buf, int size);
168static int hdlcdev_init(struct slgt_info *info);
169static void hdlcdev_exit(struct slgt_info *info);
170#endif
171
172
173/*
174 * device specific structures, macros and functions
175 */
176
177#define SLGT_MAX_PORTS 4
178#define SLGT_REG_SIZE 256
179
0080b7aa
PF		 180/*
181 * conditional wait facility
182 */
183struct cond_wait {
184 struct cond_wait *next;
185 wait_queue_head_t q;
ac6424b9 186 wait_queue_entry_t wait;
0080b7aa
PF		 187 unsigned int data;
188};
189static void init_cond_wait(struct cond_wait *w, unsigned int data);
190static void add_cond_wait(struct cond_wait **head, struct cond_wait *w);
191static void remove_cond_wait(struct cond_wait **head, struct cond_wait *w);
192static void flush_cond_wait(struct cond_wait **head);
193
705b6c7b
PF		 194/*
195 * DMA buffer descriptor and access macros
196 */
197struct slgt_desc
198{
51ef9c57
AV		 199 __le16 count;
200 __le16 status;
201 __le32 pbuf; /* physical address of data buffer */
202 __le32 next; /* physical address of next descriptor */
705b6c7b
PF		 203
204 /* driver book keeping */
205 char *buf; /* virtual address of data buffer */
206 unsigned int pdesc; /* physical address of this descriptor */
207 dma_addr_t buf_dma_addr;
403214d0 208 unsigned short buf_count;
705b6c7b
PF		 209};
210
211#define set_desc_buffer(a,b) (a).pbuf = cpu_to_le32((unsigned int)(b))
212#define set_desc_next(a,b) (a).next = cpu_to_le32((unsigned int)(b))
213#define set_desc_count(a,b)(a).count = cpu_to_le16((unsigned short)(b))
214#define set_desc_eof(a,b) (a).status = cpu_to_le16((b) ? (le16_to_cpu((a).status) | BIT0) : (le16_to_cpu((a).status) & ~BIT0))
5ba5a5d2 215#define set_desc_status(a, b) (a).status = cpu_to_le16((unsigned short)(b))
705b6c7b
PF		 216#define desc_count(a) (le16_to_cpu((a).count))
217#define desc_status(a) (le16_to_cpu((a).status))
218#define desc_complete(a) (le16_to_cpu((a).status) & BIT15)
219#define desc_eof(a) (le16_to_cpu((a).status) & BIT2)
220#define desc_crc_error(a) (le16_to_cpu((a).status) & BIT1)
221#define desc_abort(a) (le16_to_cpu((a).status) & BIT0)
222#define desc_residue(a) ((le16_to_cpu((a).status) & 0x38) >> 3)
223
224struct _input_signal_events {
225 int ri_up;
226 int ri_down;
227 int dsr_up;
228 int dsr_down;
229 int dcd_up;
230 int dcd_down;
231 int cts_up;
232 int cts_down;
233};
234
235/*
236 * device instance data structure
237 */
238struct slgt_info {
239 void *if_ptr; /* General purpose pointer (used by SPPP) */
8fb06c77 240 struct tty_port port;
705b6c7b
PF		 241
242 struct slgt_info *next_device; /* device list link */
243
244 int magic;
705b6c7b
PF		 245
246 char device_name[25];
247 struct pci_dev *pdev;
248
249 int port_count; /* count of ports on adapter */
250 int adapter_num; /* adapter instance number */
251 int port_num; /* port instance number */
252
253 /* array of pointers to port contexts on this adapter */
254 struct slgt_info *port_array[SLGT_MAX_PORTS];
255
705b6c7b 256 int line; /* tty line instance number */
705b6c7b
PF		 257
258 struct mgsl_icount icount;
259
705b6c7b
PF		 260 int timeout;
261 int x_char; /* xon/xoff character */
705b6c7b
PF		 262 unsigned int read_status_mask;
263 unsigned int ignore_status_mask;
264
705b6c7b
PF		 265 wait_queue_head_t status_event_wait_q;
266 wait_queue_head_t event_wait_q;
267 struct timer_list tx_timer;
268 struct timer_list rx_timer;
269
0080b7aa
PF		 270 unsigned int gpio_present;
271 struct cond_wait *gpio_wait_q;
272
705b6c7b
PF		 273 spinlock_t lock; /* spinlock for synchronizing with ISR */
274
275 struct work_struct task;
276 u32 pending_bh;
0fab6de0
JP		 277 bool bh_requested;
278 bool bh_running;
705b6c7b
PF		 279
280 int isr_overflow;
0fab6de0
JP		 281 bool irq_requested; /* true if IRQ requested */
282 bool irq_occurred; /* for diagnostics use */
705b6c7b
PF		 283
284 /* device configuration */
285
286 unsigned int bus_type;
287 unsigned int irq_level;
288 unsigned long irq_flags;
289
290 unsigned char __iomem * reg_addr; /* memory mapped registers address */
291 u32 phys_reg_addr;
0fab6de0 292 bool reg_addr_requested;
705b6c7b
PF		 293
294 MGSL_PARAMS params; /* communications parameters */
295 u32 idle_mode;
296 u32 max_frame_size; /* as set by device config */
297
814dae03 298 unsigned int rbuf_fill_level;
5ba5a5d2 299 unsigned int rx_pio;
705b6c7b 300 unsigned int if_mode;
1f80769f 301 unsigned int base_clock;
9807224f
PF		 302 unsigned int xsync;
303 unsigned int xctrl;
705b6c7b
PF		 304
305 /* device status */
306
0fab6de0
JP		 307 bool rx_enabled;
308 bool rx_restart;
705b6c7b 309
0fab6de0
JP		 310 bool tx_enabled;
311 bool tx_active;
705b6c7b
PF		 312
313 unsigned char signals; /* serial signal states */
2641dfd9 314 int init_error; /* initialization error */
705b6c7b
PF		 315
316 unsigned char *tx_buf;
317 int tx_count;
318
a6b68a69 319 char *flag_buf;
0fab6de0 320 bool drop_rts_on_tx_done;
705b6c7b
PF		 321 struct _input_signal_events input_signal_events;
322
323 int dcd_chkcount; /* check counts to prevent */
324 int cts_chkcount; /* too many IRQs if a signal */
325 int dsr_chkcount; /* is floating */
326 int ri_chkcount;
327
328 char *bufs; /* virtual address of DMA buffer lists */
329 dma_addr_t bufs_dma_addr; /* physical address of buffer descriptors */
330
331 unsigned int rbuf_count;
332 struct slgt_desc *rbufs;
333 unsigned int rbuf_current;
334 unsigned int rbuf_index;
5ba5a5d2
PF		 335 unsigned int rbuf_fill_index;
336 unsigned short rbuf_fill_count;
705b6c7b
PF		 337
338 unsigned int tbuf_count;
339 struct slgt_desc *tbufs;
340 unsigned int tbuf_current;
341 unsigned int tbuf_start;
342
343 unsigned char *tmp_rbuf;
344 unsigned int tmp_rbuf_count;
345
346 /* SPPP/Cisco HDLC device parts */
347
348 int netcount;
705b6c7b 349 spinlock_t netlock;
af69c7f9 350#if SYNCLINK_GENERIC_HDLC
705b6c7b
PF		 351 struct net_device *netdev;
352#endif
353
354};
355
356static MGSL_PARAMS default_params = {
357 .mode = MGSL_MODE_HDLC,
358 .loopback = 0,
359 .flags = HDLC_FLAG_UNDERRUN_ABORT15,
360 .encoding = HDLC_ENCODING_NRZI_SPACE,
361 .clock_speed = 0,
362 .addr_filter = 0xff,
363 .crc_type = HDLC_CRC_16_CCITT,
364 .preamble_length = HDLC_PREAMBLE_LENGTH_8BITS,
365 .preamble = HDLC_PREAMBLE_PATTERN_NONE,
366 .data_rate = 9600,
367 .data_bits = 8,
368 .stop_bits = 1,
369 .parity = ASYNC_PARITY_NONE
370};
371
372
373#define BH_RECEIVE 1
374#define BH_TRANSMIT 2
375#define BH_STATUS 4
376#define IO_PIN_SHUTDOWN_LIMIT 100
377
378#define DMABUFSIZE 256
379#define DESC_LIST_SIZE 4096
380
381#define MASK_PARITY BIT1
202af6d5
PF		 382#define MASK_FRAMING BIT0
383#define MASK_BREAK BIT14
705b6c7b
PF		 384#define MASK_OVERRUN BIT4
385
386#define GSR 0x00 /* global status */
0080b7aa
PF		 387#define JCR 0x04 /* JTAG control */
388#define IODR 0x08 /* GPIO direction */
389#define IOER 0x0c /* GPIO interrupt enable */
390#define IOVR 0x10 /* GPIO value */
391#define IOSR 0x14 /* GPIO interrupt status */
705b6c7b
PF		 392#define TDR 0x80 /* tx data */
393#define RDR 0x80 /* rx data */
394#define TCR 0x82 /* tx control */
395#define TIR 0x84 /* tx idle */
396#define TPR 0x85 /* tx preamble */
397#define RCR 0x86 /* rx control */
398#define VCR 0x88 /* V.24 control */
399#define CCR 0x89 /* clock control */
400#define BDR 0x8a /* baud divisor */
401#define SCR 0x8c /* serial control */
402#define SSR 0x8e /* serial status */
403#define RDCSR 0x90 /* rx DMA control/status */
404#define TDCSR 0x94 /* tx DMA control/status */
405#define RDDAR 0x98 /* rx DMA descriptor address */
406#define TDDAR 0x9c /* tx DMA descriptor address */
9807224f
PF		 407#define XSR 0x40 /* extended sync pattern */
408#define XCR 0x44 /* extended control */
705b6c7b
PF		 409
410#define RXIDLE BIT14
411#define RXBREAK BIT14
412#define IRQ_TXDATA BIT13
413#define IRQ_TXIDLE BIT12
414#define IRQ_TXUNDER BIT11 /* HDLC */
415#define IRQ_RXDATA BIT10
416#define IRQ_RXIDLE BIT9 /* HDLC */
417#define IRQ_RXBREAK BIT9 /* async */
418#define IRQ_RXOVER BIT8
419#define IRQ_DSR BIT7
420#define IRQ_CTS BIT6
421#define IRQ_DCD BIT5
422#define IRQ_RI BIT4
423#define IRQ_ALL 0x3ff0
424#define IRQ_MASTER BIT0
425
426#define slgt_irq_on(info, mask) \
427 wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) | (mask)))
428#define slgt_irq_off(info, mask) \
429 wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) & ~(mask)))
430
431static __u8 rd_reg8(struct slgt_info *info, unsigned int addr);
432static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value);
433static __u16 rd_reg16(struct slgt_info *info, unsigned int addr);
434static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value);
435static __u32 rd_reg32(struct slgt_info *info, unsigned int addr);
436static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value);
437
438static void msc_set_vcr(struct slgt_info *info);
439
440static int startup(struct slgt_info *info);
441static int block_til_ready(struct tty_struct *tty, struct file * filp,struct slgt_info *info);
442static void shutdown(struct slgt_info *info);
443static void program_hw(struct slgt_info *info);
444static void change_params(struct slgt_info *info);
445
446static int register_test(struct slgt_info *info);
447static int irq_test(struct slgt_info *info);
448static int loopback_test(struct slgt_info *info);
449static int adapter_test(struct slgt_info *info);
450
451static void reset_adapter(struct slgt_info *info);
452static void reset_port(struct slgt_info *info);
453static void async_mode(struct slgt_info *info);
cb10dc9a 454static void sync_mode(struct slgt_info *info);
705b6c7b
PF		 455
456static void rx_stop(struct slgt_info *info);
457static void rx_start(struct slgt_info *info);
458static void reset_rbufs(struct slgt_info *info);
459static void free_rbufs(struct slgt_info *info, unsigned int first, unsigned int last);
460static void rdma_reset(struct slgt_info *info);
0fab6de0
JP		 461static bool rx_get_frame(struct slgt_info *info);
462static bool rx_get_buf(struct slgt_info *info);
705b6c7b
PF		 463
464static void tx_start(struct slgt_info *info);
465static void tx_stop(struct slgt_info *info);
466static void tx_set_idle(struct slgt_info *info);
467static unsigned int free_tbuf_count(struct slgt_info *info);
403214d0 468static unsigned int tbuf_bytes(struct slgt_info *info);
705b6c7b
PF		 469static void reset_tbufs(struct slgt_info *info);
470static void tdma_reset(struct slgt_info *info);
de538eb3 471static bool tx_load(struct slgt_info *info, const char *buf, unsigned int count);
705b6c7b
PF		 472
473static void get_signals(struct slgt_info *info);
474static void set_signals(struct slgt_info *info);
475static void enable_loopback(struct slgt_info *info);
476static void set_rate(struct slgt_info *info, u32 data_rate);
477
478static int bh_action(struct slgt_info *info);
c4028958 479static void bh_handler(struct work_struct *work);
705b6c7b
PF		 480static void bh_transmit(struct slgt_info *info);
481static void isr_serial(struct slgt_info *info);
482static void isr_rdma(struct slgt_info *info);
483static void isr_txeom(struct slgt_info *info, unsigned short status);
484static void isr_tdma(struct slgt_info *info);
705b6c7b
PF		 485
486static int alloc_dma_bufs(struct slgt_info *info);
487static void free_dma_bufs(struct slgt_info *info);
488static int alloc_desc(struct slgt_info *info);
489static void free_desc(struct slgt_info *info);
490static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
491static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
492
493static int alloc_tmp_rbuf(struct slgt_info *info);
494static void free_tmp_rbuf(struct slgt_info *info);
495
e99e88a9
KC		 496static void tx_timeout(struct timer_list *t);
497static void rx_timeout(struct timer_list *t);
705b6c7b
PF		 498
499/*
500 * ioctl handlers
501 */
502static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount);
503static int get_params(struct slgt_info *info, MGSL_PARAMS __user *params);
504static int set_params(struct slgt_info *info, MGSL_PARAMS __user *params);
505static int get_txidle(struct slgt_info *info, int __user *idle_mode);
506static int set_txidle(struct slgt_info *info, int idle_mode);
507static int tx_enable(struct slgt_info *info, int enable);
508static int tx_abort(struct slgt_info *info);
509static int rx_enable(struct slgt_info *info, int enable);
510static int modem_input_wait(struct slgt_info *info,int arg);
511static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr);
60b33c13 512static int tiocmget(struct tty_struct *tty);
20b9d177
AC		 513static int tiocmset(struct tty_struct *tty,
514 unsigned int set, unsigned int clear);
9e98966c 515static int set_break(struct tty_struct *tty, int break_state);
705b6c7b
PF		 516static int get_interface(struct slgt_info *info, int __user *if_mode);
517static int set_interface(struct slgt_info *info, int if_mode);
0080b7aa
PF		 518static int set_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
519static int get_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
520static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
9807224f
PF		 521static int get_xsync(struct slgt_info *info, int __user *if_mode);
522static int set_xsync(struct slgt_info *info, int if_mode);
523static int get_xctrl(struct slgt_info *info, int __user *if_mode);
524static int set_xctrl(struct slgt_info *info, int if_mode);
705b6c7b
PF		 525
526/*
527 * driver functions
528 */
529static void add_device(struct slgt_info *info);
530static void device_init(int adapter_num, struct pci_dev *pdev);
531static int claim_resources(struct slgt_info *info);
532static void release_resources(struct slgt_info *info);
533
534/*
535 * DEBUG OUTPUT CODE
536 */
537#ifndef DBGINFO
538#define DBGINFO(fmt)
539#endif
540#ifndef DBGERR
541#define DBGERR(fmt)
542#endif
543#ifndef DBGBH
544#define DBGBH(fmt)
545#endif
546#ifndef DBGISR
547#define DBGISR(fmt)
548#endif
549
550#ifdef DBGDATA
551static void trace_block(struct slgt_info *info, const char *data, int count, const char *label)
552{
553 int i;
554 int linecount;
555 printk("%s %s data:\n",info->device_name, label);
556 while(count) {
557 linecount = (count > 16) ? 16 : count;
558 for(i=0; i < linecount; i++)
559 printk("%02X ",(unsigned char)data[i]);
560 for(;i<17;i++)
561 printk(" ");
562 for(i=0;i<linecount;i++) {
563 if (data[i]>=040 && data[i]<=0176)
564 printk("%c",data[i]);
565 else
566 printk(".");
567 }
568 printk("\n");
569 data += linecount;
570 count -= linecount;
571 }
572}
573#else
574#define DBGDATA(info, buf, size, label)
575#endif
576
577#ifdef DBGTBUF
578static void dump_tbufs(struct slgt_info *info)
579{
580 int i;
581 printk("tbuf_current=%d\n", info->tbuf_current);
582 for (i=0 ; i < info->tbuf_count ; i++) {
583 printk("%d: count=%04X status=%04X\n",
584 i, le16_to_cpu(info->tbufs[i].count), le16_to_cpu(info->tbufs[i].status));
585 }
586}
587#else
588#define DBGTBUF(info)
589#endif
590
591#ifdef DBGRBUF
592static void dump_rbufs(struct slgt_info *info)
593{
594 int i;
595 printk("rbuf_current=%d\n", info->rbuf_current);
596 for (i=0 ; i < info->rbuf_count ; i++) {
597 printk("%d: count=%04X status=%04X\n",
598 i, le16_to_cpu(info->rbufs[i].count), le16_to_cpu(info->rbufs[i].status));
599 }
600}
601#else
602#define DBGRBUF(info)
603#endif
604
605static inline int sanity_check(struct slgt_info *info, char *devname, const char *name)
606{
607#ifdef SANITY_CHECK
608 if (!info) {
609 printk("null struct slgt_info for (%s) in %s\n", devname, name);
610 return 1;
611 }
612 if (info->magic != MGSL_MAGIC) {
613 printk("bad magic number struct slgt_info (%s) in %s\n", devname, name);
614 return 1;
615 }
616#else
617 if (!info)
618 return 1;
619#endif
620 return 0;
621}
622
71b061e2 623/*
705b6c7b
PF		 624 * line discipline callback wrappers
625 *
626 * The wrappers maintain line discipline references
627 * while calling into the line discipline.
628 *
629 * ldisc_receive_buf - pass receive data to line discipline
630 */
631static void ldisc_receive_buf(struct tty_struct *tty,
632 const __u8 *data, char *flags, int count)
633{
634 struct tty_ldisc *ld;
635 if (!tty)
636 return;
637 ld = tty_ldisc_ref(tty);
638 if (ld) {
a352def2
AC		 639 if (ld->ops->receive_buf)
640 ld->ops->receive_buf(tty, data, flags, count);
705b6c7b
PF		 641 tty_ldisc_deref(ld);
642 }
643}
644
645/* tty callbacks */
646
647static int open(struct tty_struct *tty, struct file *filp)
648{
649 struct slgt_info *info;
650 int retval, line;
651 unsigned long flags;
652
653 line = tty->index;
410235fd 654 if (line >= slgt_device_count) {
705b6c7b
PF		 655 DBGERR(("%s: open with invalid line #%d.\n", driver_name, line));
656 return -ENODEV;
657 }
658
659 info = slgt_device_list;
660 while(info && info->line != line)
661 info = info->next_device;
662 if (sanity_check(info, tty->name, "open"))
663 return -ENODEV;
664 if (info->init_error) {
665 DBGERR(("%s init error=%d\n", info->device_name, info->init_error));
666 return -ENODEV;
667 }
668
669 tty->driver_data = info;
8fb06c77 670 info->port.tty = tty;
705b6c7b 671
8fb06c77 672 DBGINFO(("%s open, old ref count = %d\n", info->device_name, info->port.count));
705b6c7b 673
a360fae6 674 mutex_lock(&info->port.mutex);
705b6c7b
PF		 675
676 spin_lock_irqsave(&info->netlock, flags);
677 if (info->netcount) {
678 retval = -EBUSY;
679 spin_unlock_irqrestore(&info->netlock, flags);
a360fae6 680 mutex_unlock(&info->port.mutex);
705b6c7b
PF		 681 goto cleanup;
682 }
8fb06c77 683 info->port.count++;
705b6c7b
PF		 684 spin_unlock_irqrestore(&info->netlock, flags);
685
8fb06c77 686 if (info->port.count == 1) {
705b6c7b
PF		 687 /* 1st open on this device, init hardware */
688 retval = startup(info);
80d04f22
DC		 689 if (retval < 0) {
690 mutex_unlock(&info->port.mutex);
705b6c7b 691 goto cleanup;
80d04f22 692 }
705b6c7b 693 }
a360fae6 694 mutex_unlock(&info->port.mutex);
705b6c7b
PF		 695 retval = block_til_ready(tty, filp, info);
696 if (retval) {
697 DBGINFO(("%s block_til_ready rc=%d\n", info->device_name, retval));
698 goto cleanup;
699 }
700
701 retval = 0;
702
703cleanup:
704 if (retval) {
705 if (tty->count == 1)
8fb06c77
AC		 706 info->port.tty = NULL; /* tty layer will release tty struct */
707 if(info->port.count)
708 info->port.count--;
705b6c7b
PF		 709 }
710
711 DBGINFO(("%s open rc=%d\n", info->device_name, retval));
712 return retval;
713}
714
715static void close(struct tty_struct *tty, struct file *filp)
716{
717 struct slgt_info *info = tty->driver_data;
718
719 if (sanity_check(info, tty->name, "close"))
720 return;
8fb06c77 721 DBGINFO(("%s close entry, count=%d\n", info->device_name, info->port.count));
705b6c7b 722
a6614999 723 if (tty_port_close_start(&info->port, tty, filp) == 0)
705b6c7b
PF		 724 goto cleanup;
725
a360fae6 726 mutex_lock(&info->port.mutex);
d41861ca 727 if (tty_port_initialized(&info->port))
705b6c7b 728 wait_until_sent(tty, info->timeout);
978e595f 729 flush_buffer(tty);
705b6c7b
PF		 730 tty_ldisc_flush(tty);
731
732 shutdown(info);
a360fae6 733 mutex_unlock(&info->port.mutex);
705b6c7b 734
a6614999 735 tty_port_close_end(&info->port, tty);
8fb06c77 736 info->port.tty = NULL;
705b6c7b 737cleanup:
8fb06c77 738 DBGINFO(("%s close exit, count=%d\n", tty->driver->name, info->port.count));
705b6c7b
PF		 739}
740
741static void hangup(struct tty_struct *tty)
742{
743 struct slgt_info *info = tty->driver_data;
a360fae6 744 unsigned long flags;
705b6c7b
PF		 745
746 if (sanity_check(info, tty->name, "hangup"))
747 return;
748 DBGINFO(("%s hangup\n", info->device_name));
749
750 flush_buffer(tty);
a360fae6
AC		 751
752 mutex_lock(&info->port.mutex);
705b6c7b
PF		 753 shutdown(info);
754
a360fae6 755 spin_lock_irqsave(&info->port.lock, flags);
8fb06c77 756 info->port.count = 0;
8fb06c77 757 info->port.tty = NULL;
a360fae6 758 spin_unlock_irqrestore(&info->port.lock, flags);
807c8d81 759 tty_port_set_active(&info->port, 0);
a360fae6 760 mutex_unlock(&info->port.mutex);
705b6c7b 761
8fb06c77 762 wake_up_interruptible(&info->port.open_wait);
705b6c7b
PF		 763}
764
606d099c 765static void set_termios(struct tty_struct *tty, struct ktermios *old_termios)
705b6c7b
PF		 766{
767 struct slgt_info *info = tty->driver_data;
768 unsigned long flags;
769
770 DBGINFO(("%s set_termios\n", tty->driver->name));
771
705b6c7b
PF		 772 change_params(info);
773
774 /* Handle transition to B0 status */
9db276f8 775 if ((old_termios->c_cflag & CBAUD) && !C_BAUD(tty)) {
9fe8074b 776 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
705b6c7b
PF		 777 spin_lock_irqsave(&info->lock,flags);
778 set_signals(info);
779 spin_unlock_irqrestore(&info->lock,flags);
780 }
781
782 /* Handle transition away from B0 status */
9db276f8 783 if (!(old_termios->c_cflag & CBAUD) && C_BAUD(tty)) {
705b6c7b 784 info->signals |= SerialSignal_DTR;
97ef38b8 785 if (!C_CRTSCTS(tty) || !tty_throttled(tty))
705b6c7b 786 info->signals |= SerialSignal_RTS;
705b6c7b
PF		 787 spin_lock_irqsave(&info->lock,flags);
788 set_signals(info);
789 spin_unlock_irqrestore(&info->lock,flags);
790 }
791
792 /* Handle turning off CRTSCTS */
9db276f8 793 if ((old_termios->c_cflag & CRTSCTS) && !C_CRTSCTS(tty)) {
705b6c7b
PF		 794 tty->hw_stopped = 0;
795 tx_release(tty);
796 }
797}
798
ce89294c
PF		 799static void update_tx_timer(struct slgt_info *info)
800{
801 /*
802 * use worst case speed of 1200bps to calculate transmit timeout
803 * based on data in buffers (tbuf_bytes) and FIFO (128 bytes)
804 */
805 if (info->params.mode == MGSL_MODE_HDLC) {
806 int timeout = (tbuf_bytes(info) * 7) + 1000;
807 mod_timer(&info->tx_timer, jiffies + msecs_to_jiffies(timeout));
808 }
809}
810
705b6c7b
PF		 811static int write(struct tty_struct *tty,
812 const unsigned char *buf, int count)
813{
814 int ret = 0;
815 struct slgt_info *info = tty->driver_data;
816 unsigned long flags;
817
818 if (sanity_check(info, tty->name, "write"))
de538eb3
PF		 819 return -EIO;
820
705b6c7b
PF		 821 DBGINFO(("%s write count=%d\n", info->device_name, count));
822
de538eb3
PF		 823 if (!info->tx_buf || (count > info->max_frame_size))
824 return -EIO;
705b6c7b 825
de538eb3
PF		 826 if (!count || tty->stopped || tty->hw_stopped)
827 return 0;
705b6c7b 828
de538eb3 829 spin_lock_irqsave(&info->lock, flags);
705b6c7b 830
de538eb3 831 if (info->tx_count) {
8a38c285 832 /* send accumulated data from send_char() */
de538eb3
PF		 833 if (!tx_load(info, info->tx_buf, info->tx_count))
834 goto cleanup;
835 info->tx_count = 0;
705b6c7b
PF		 836 }
837
de538eb3
PF		 838 if (tx_load(info, buf, count))
839 ret = count;
705b6c7b
PF		 840
841cleanup:
de538eb3 842 spin_unlock_irqrestore(&info->lock, flags);
705b6c7b
PF		 843 DBGINFO(("%s write rc=%d\n", info->device_name, ret));
844 return ret;
845}
846
55da7789 847static int put_char(struct tty_struct *tty, unsigned char ch)
705b6c7b
PF		 848{
849 struct slgt_info *info = tty->driver_data;
850 unsigned long flags;
6c82c415 851 int ret = 0;
705b6c7b
PF		 852
853 if (sanity_check(info, tty->name, "put_char"))
55da7789 854 return 0;
705b6c7b 855 DBGINFO(("%s put_char(%d)\n", info->device_name, ch));
326f28e9 856 if (!info->tx_buf)
55da7789 857 return 0;
705b6c7b 858 spin_lock_irqsave(&info->lock,flags);
de538eb3 859 if (info->tx_count < info->max_frame_size) {
705b6c7b 860 info->tx_buf[info->tx_count++] = ch;
55da7789
AC		 861 ret = 1;
862 }
705b6c7b 863 spin_unlock_irqrestore(&info->lock,flags);
55da7789 864 return ret;
705b6c7b
PF		 865}
866
867static void send_xchar(struct tty_struct *tty, char ch)
868{
869 struct slgt_info *info = tty->driver_data;
870 unsigned long flags;
871
872 if (sanity_check(info, tty->name, "send_xchar"))
873 return;
874 DBGINFO(("%s send_xchar(%d)\n", info->device_name, ch));
875 info->x_char = ch;
876 if (ch) {
877 spin_lock_irqsave(&info->lock,flags);
878 if (!info->tx_enabled)
879 tx_start(info);
880 spin_unlock_irqrestore(&info->lock,flags);
881 }
882}
883
884static void wait_until_sent(struct tty_struct *tty, int timeout)
885{
886 struct slgt_info *info = tty->driver_data;
887 unsigned long orig_jiffies, char_time;
888
889 if (!info )
890 return;
891 if (sanity_check(info, tty->name, "wait_until_sent"))
892 return;
893 DBGINFO(("%s wait_until_sent entry\n", info->device_name));
d41861ca 894 if (!tty_port_initialized(&info->port))
705b6c7b
PF		 895 goto exit;
896
897 orig_jiffies = jiffies;
898
899 /* Set check interval to 1/5 of estimated time to
900 * send a character, and make it at least 1. The check
901 * interval should also be less than the timeout.
902 * Note: use tight timings here to satisfy the NIST-PCTS.
903 */
904
905 if (info->params.data_rate) {
906 char_time = info->timeout/(32 * 5);
907 if (!char_time)
908 char_time++;
909 } else
910 char_time = 1;
911
912 if (timeout)
913 char_time = min_t(unsigned long, char_time, timeout);
914
915 while (info->tx_active) {
916 msleep_interruptible(jiffies_to_msecs(char_time));
917 if (signal_pending(current))
918 break;
919 if (timeout && time_after(jiffies, orig_jiffies + timeout))
920 break;
921 }
705b6c7b
PF		 922exit:
923 DBGINFO(("%s wait_until_sent exit\n", info->device_name));
924}
925
926static int write_room(struct tty_struct *tty)
927{
928 struct slgt_info *info = tty->driver_data;
929 int ret;
930
931 if (sanity_check(info, tty->name, "write_room"))
932 return 0;
933 ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
934 DBGINFO(("%s write_room=%d\n", info->device_name, ret));
935 return ret;
936}
937
938static void flush_chars(struct tty_struct *tty)
939{
940 struct slgt_info *info = tty->driver_data;
941 unsigned long flags;
942
943 if (sanity_check(info, tty->name, "flush_chars"))
944 return;
945 DBGINFO(("%s flush_chars entry tx_count=%d\n", info->device_name, info->tx_count));
946
947 if (info->tx_count <= 0 || tty->stopped ||
948 tty->hw_stopped || !info->tx_buf)
949 return;
950
951 DBGINFO(("%s flush_chars start transmit\n", info->device_name));
952
953 spin_lock_irqsave(&info->lock,flags);
de538eb3
PF		 954 if (info->tx_count && tx_load(info, info->tx_buf, info->tx_count))
955 info->tx_count = 0;
705b6c7b
PF		 956 spin_unlock_irqrestore(&info->lock,flags);
957}
958
959static void flush_buffer(struct tty_struct *tty)
960{
961 struct slgt_info *info = tty->driver_data;
962 unsigned long flags;
963
964 if (sanity_check(info, tty->name, "flush_buffer"))
965 return;
966 DBGINFO(("%s flush_buffer\n", info->device_name));
967
de538eb3
PF		 968 spin_lock_irqsave(&info->lock, flags);
969 info->tx_count = 0;
970 spin_unlock_irqrestore(&info->lock, flags);
705b6c7b 971
705b6c7b
PF		 972 tty_wakeup(tty);
973}
974
975/*
976 * throttle (stop) transmitter
977 */
978static void tx_hold(struct tty_struct *tty)
979{
980 struct slgt_info *info = tty->driver_data;
981 unsigned long flags;
982
983 if (sanity_check(info, tty->name, "tx_hold"))
984 return;
985 DBGINFO(("%s tx_hold\n", info->device_name));
986 spin_lock_irqsave(&info->lock,flags);
987 if (info->tx_enabled && info->params.mode == MGSL_MODE_ASYNC)
988 tx_stop(info);
989 spin_unlock_irqrestore(&info->lock,flags);
990}
991
992/*
993 * release (start) transmitter
994 */
995static void tx_release(struct tty_struct *tty)
996{
997 struct slgt_info *info = tty->driver_data;
998 unsigned long flags;
999
1000 if (sanity_check(info, tty->name, "tx_release"))
1001 return;
1002 DBGINFO(("%s tx_release\n", info->device_name));
de538eb3
PF		 1003 spin_lock_irqsave(&info->lock, flags);
1004 if (info->tx_count && tx_load(info, info->tx_buf, info->tx_count))
1005 info->tx_count = 0;
1006 spin_unlock_irqrestore(&info->lock, flags);
705b6c7b
PF		 1007}
1008
1009/*
1010 * Service an IOCTL request
1011 *
1012 * Arguments
1013 *
1014 * tty pointer to tty instance data
705b6c7b
PF		 1015 * cmd IOCTL command code
1016 * arg command argument/context
1017 *
1018 * Return 0 if success, otherwise error code
1019 */
6caa76b7 1020static int ioctl(struct tty_struct *tty,
705b6c7b
PF		 1021 unsigned int cmd, unsigned long arg)
1022{
1023 struct slgt_info *info = tty->driver_data;
705b6c7b 1024 void __user *argp = (void __user *)arg;
1f8cabb7 1025 int ret;
705b6c7b
PF		 1026
1027 if (sanity_check(info, tty->name, "ioctl"))
1028 return -ENODEV;
1029 DBGINFO(("%s ioctl() cmd=%08X\n", info->device_name, cmd));
1030
f82fc0fe 1031 if (cmd != TIOCMIWAIT) {
18900ca6 1032 if (tty_io_error(tty))
705b6c7b
PF		 1033 return -EIO;
1034 }
1035
f602501d
AC		 1036 switch (cmd) {
1037 case MGSL_IOCWAITEVENT:
1038 return wait_mgsl_event(info, argp);
1039 case TIOCMIWAIT:
1040 return modem_input_wait(info,(int)arg);
f602501d
AC		 1041 case MGSL_IOCSGPIO:
1042 return set_gpio(info, argp);
1043 case MGSL_IOCGGPIO:
1044 return get_gpio(info, argp);
1045 case MGSL_IOCWAITGPIO:
1046 return wait_gpio(info, argp);
9807224f
PF		 1047 case MGSL_IOCGXSYNC:
1048 return get_xsync(info, argp);
1049 case MGSL_IOCSXSYNC:
1050 return set_xsync(info, (int)arg);
1051 case MGSL_IOCGXCTRL:
1052 return get_xctrl(info, argp);
1053 case MGSL_IOCSXCTRL:
1054 return set_xctrl(info, (int)arg);
f602501d
AC		 1055 }
1056 mutex_lock(&info->port.mutex);
705b6c7b
PF		 1057 switch (cmd) {
1058 case MGSL_IOCGPARAMS:
1f8cabb7
AC		 1059 ret = get_params(info, argp);
1060 break;
705b6c7b 1061 case MGSL_IOCSPARAMS:
1f8cabb7
AC		 1062 ret = set_params(info, argp);
1063 break;
705b6c7b 1064 case MGSL_IOCGTXIDLE:
1f8cabb7
AC		 1065 ret = get_txidle(info, argp);
1066 break;
705b6c7b 1067 case MGSL_IOCSTXIDLE:
1f8cabb7
AC		 1068 ret = set_txidle(info, (int)arg);
1069 break;
705b6c7b 1070 case MGSL_IOCTXENABLE:
1f8cabb7
AC		 1071 ret = tx_enable(info, (int)arg);
1072 break;
705b6c7b 1073 case MGSL_IOCRXENABLE:
1f8cabb7
AC		 1074 ret = rx_enable(info, (int)arg);
1075 break;
705b6c7b 1076 case MGSL_IOCTXABORT:
1f8cabb7
AC		 1077 ret = tx_abort(info);
1078 break;
705b6c7b 1079 case MGSL_IOCGSTATS:
1f8cabb7
AC		 1080 ret = get_stats(info, argp);
1081 break;
705b6c7b 1082 case MGSL_IOCGIF:
1f8cabb7
AC		 1083 ret = get_interface(info, argp);
1084 break;
705b6c7b 1085 case MGSL_IOCSIF:
1f8cabb7
AC		 1086 ret = set_interface(info,(int)arg);
1087 break;
705b6c7b 1088 default:
1f8cabb7 1089 ret = -ENOIOCTLCMD;
705b6c7b 1090 }
f602501d 1091 mutex_unlock(&info->port.mutex);
1f8cabb7 1092 return ret;
705b6c7b
PF		 1093}
1094
0587102c
AC		 1095static int get_icount(struct tty_struct *tty,
1096 struct serial_icounter_struct *icount)
1097
1098{
1099 struct slgt_info *info = tty->driver_data;
1100 struct mgsl_icount cnow; /* kernel counter temps */
1101 unsigned long flags;
1102
1103 spin_lock_irqsave(&info->lock,flags);
1104 cnow = info->icount;
1105 spin_unlock_irqrestore(&info->lock,flags);
1106
1107 icount->cts = cnow.cts;
1108 icount->dsr = cnow.dsr;
1109 icount->rng = cnow.rng;
1110 icount->dcd = cnow.dcd;
1111 icount->rx = cnow.rx;
1112 icount->tx = cnow.tx;
1113 icount->frame = cnow.frame;
1114 icount->overrun = cnow.overrun;
1115 icount->parity = cnow.parity;
1116 icount->brk = cnow.brk;
1117 icount->buf_overrun = cnow.buf_overrun;
1118
1119 return 0;
1120}
1121
2acdb169
PF		 1122/*
1123 * support for 32 bit ioctl calls on 64 bit systems
1124 */
1125#ifdef CONFIG_COMPAT
1126static long get_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *user_params)
1127{
1128 struct MGSL_PARAMS32 tmp_params;
1129
1130 DBGINFO(("%s get_params32\n", info->device_name));
ed77ed61 1131 memset(&tmp_params, 0, sizeof(tmp_params));
2acdb169
PF		 1132 tmp_params.mode = (compat_ulong_t)info->params.mode;
1133 tmp_params.loopback = info->params.loopback;
1134 tmp_params.flags = info->params.flags;
1135 tmp_params.encoding = info->params.encoding;
1136 tmp_params.clock_speed = (compat_ulong_t)info->params.clock_speed;
1137 tmp_params.addr_filter = info->params.addr_filter;
1138 tmp_params.crc_type = info->params.crc_type;
1139 tmp_params.preamble_length = info->params.preamble_length;
1140 tmp_params.preamble = info->params.preamble;
1141 tmp_params.data_rate = (compat_ulong_t)info->params.data_rate;
1142 tmp_params.data_bits = info->params.data_bits;
1143 tmp_params.stop_bits = info->params.stop_bits;
1144 tmp_params.parity = info->params.parity;
1145 if (copy_to_user(user_params, &tmp_params, sizeof(struct MGSL_PARAMS32)))
1146 return -EFAULT;
1147 return 0;
1148}
1149
1150static long set_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *new_params)
1151{
1152 struct MGSL_PARAMS32 tmp_params;
1153
1154 DBGINFO(("%s set_params32\n", info->device_name));
1155 if (copy_from_user(&tmp_params, new_params, sizeof(struct MGSL_PARAMS32)))
1156 return -EFAULT;
1157
1158 spin_lock(&info->lock);
1f80769f
PF		 1159 if (tmp_params.mode == MGSL_MODE_BASE_CLOCK) {
1160 info->base_clock = tmp_params.clock_speed;
1161 } else {
1162 info->params.mode = tmp_params.mode;
1163 info->params.loopback = tmp_params.loopback;
1164 info->params.flags = tmp_params.flags;
1165 info->params.encoding = tmp_params.encoding;
1166 info->params.clock_speed = tmp_params.clock_speed;
1167 info->params.addr_filter = tmp_params.addr_filter;
1168 info->params.crc_type = tmp_params.crc_type;
1169 info->params.preamble_length = tmp_params.preamble_length;
1170 info->params.preamble = tmp_params.preamble;
1171 info->params.data_rate = tmp_params.data_rate;
1172 info->params.data_bits = tmp_params.data_bits;
1173 info->params.stop_bits = tmp_params.stop_bits;
1174 info->params.parity = tmp_params.parity;
1175 }
2acdb169
PF		 1176 spin_unlock(&info->lock);
1177
1f80769f 1178 program_hw(info);
2acdb169
PF		 1179
1180 return 0;
1181}
1182
6caa76b7 1183static long slgt_compat_ioctl(struct tty_struct *tty,
2acdb169
PF		 1184 unsigned int cmd, unsigned long arg)
1185{
1186 struct slgt_info *info = tty->driver_data;
27230e51 1187 int rc;
2acdb169
PF		 1188
1189 if (sanity_check(info, tty->name, "compat_ioctl"))
1190 return -ENODEV;
1191 DBGINFO(("%s compat_ioctl() cmd=%08X\n", info->device_name, cmd));
1192
1193 switch (cmd) {
2acdb169
PF		 1194 case MGSL_IOCSPARAMS32:
1195 rc = set_params32(info, compat_ptr(arg));
1196 break;
1197
1198 case MGSL_IOCGPARAMS32:
1199 rc = get_params32(info, compat_ptr(arg));
1200 break;
1201
1202 case MGSL_IOCGPARAMS:
1203 case MGSL_IOCSPARAMS:
1204 case MGSL_IOCGTXIDLE:
1205 case MGSL_IOCGSTATS:
1206 case MGSL_IOCWAITEVENT:
1207 case MGSL_IOCGIF:
1208 case MGSL_IOCSGPIO:
1209 case MGSL_IOCGGPIO:
1210 case MGSL_IOCWAITGPIO:
9807224f
PF		 1211 case MGSL_IOCGXSYNC:
1212 case MGSL_IOCGXCTRL:
27230e51 1213 rc = ioctl(tty, cmd, (unsigned long)compat_ptr(arg));
2acdb169 1214 break;
27230e51
AV		 1215 default:
1216 rc = ioctl(tty, cmd, arg);
2acdb169 1217 }
2acdb169
PF		 1218 DBGINFO(("%s compat_ioctl() cmd=%08X rc=%d\n", info->device_name, cmd, rc));
1219 return rc;
1220}
1221#else
1222#define slgt_compat_ioctl NULL
1223#endif /* ifdef CONFIG_COMPAT */
1224
705b6c7b
PF		 1225/*
1226 * proc fs support
1227 */
a18c56e5 1228static inline void line_info(struct seq_file *m, struct slgt_info *info)
705b6c7b
PF		 1229{
1230 char stat_buf[30];
705b6c7b
PF		 1231 unsigned long flags;
1232
a18c56e5 1233 seq_printf(m, "%s: IO=%08X IRQ=%d MaxFrameSize=%u\n",
705b6c7b
PF		 1234 info->device_name, info->phys_reg_addr,
1235 info->irq_level, info->max_frame_size);
1236
1237 /* output current serial signal states */
1238 spin_lock_irqsave(&info->lock,flags);
1239 get_signals(info);
1240 spin_unlock_irqrestore(&info->lock,flags);
1241
1242 stat_buf[0] = 0;
1243 stat_buf[1] = 0;
1244 if (info->signals & SerialSignal_RTS)
1245 strcat(stat_buf, "|RTS");
1246 if (info->signals & SerialSignal_CTS)
1247 strcat(stat_buf, "|CTS");
1248 if (info->signals & SerialSignal_DTR)
1249 strcat(stat_buf, "|DTR");
1250 if (info->signals & SerialSignal_DSR)
1251 strcat(stat_buf, "|DSR");
1252 if (info->signals & SerialSignal_DCD)
1253 strcat(stat_buf, "|CD");
1254 if (info->signals & SerialSignal_RI)
1255 strcat(stat_buf, "|RI");
1256
1257 if (info->params.mode != MGSL_MODE_ASYNC) {
a18c56e5 1258 seq_printf(m, "\tHDLC txok:%d rxok:%d",
705b6c7b
PF		 1259 info->icount.txok, info->icount.rxok);
1260 if (info->icount.txunder)
a18c56e5 1261 seq_printf(m, " txunder:%d", info->icount.txunder);
705b6c7b 1262 if (info->icount.txabort)
a18c56e5 1263 seq_printf(m, " txabort:%d", info->icount.txabort);
705b6c7b 1264 if (info->icount.rxshort)
a18c56e5 1265 seq_printf(m, " rxshort:%d", info->icount.rxshort);
705b6c7b 1266 if (info->icount.rxlong)
a18c56e5 1267 seq_printf(m, " rxlong:%d", info->icount.rxlong);
705b6c7b 1268 if (info->icount.rxover)
a18c56e5 1269 seq_printf(m, " rxover:%d", info->icount.rxover);
705b6c7b 1270 if (info->icount.rxcrc)
a18c56e5 1271 seq_printf(m, " rxcrc:%d", info->icount.rxcrc);
705b6c7b 1272 } else {
a18c56e5 1273 seq_printf(m, "\tASYNC tx:%d rx:%d",
705b6c7b
PF		 1274 info->icount.tx, info->icount.rx);
1275 if (info->icount.frame)
a18c56e5 1276 seq_printf(m, " fe:%d", info->icount.frame);
705b6c7b 1277 if (info->icount.parity)
a18c56e5 1278 seq_printf(m, " pe:%d", info->icount.parity);
705b6c7b 1279 if (info->icount.brk)
a18c56e5 1280 seq_printf(m, " brk:%d", info->icount.brk);
705b6c7b 1281 if (info->icount.overrun)
a18c56e5 1282 seq_printf(m, " oe:%d", info->icount.overrun);
705b6c7b
PF		 1283 }
1284
1285 /* Append serial signal status to end */
a18c56e5 1286 seq_printf(m, " %s\n", stat_buf+1);
705b6c7b 1287
a18c56e5 1288 seq_printf(m, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
705b6c7b
PF		 1289 info->tx_active,info->bh_requested,info->bh_running,
1290 info->pending_bh);
705b6c7b
PF		 1291}
1292
1293/* Called to print information about devices
1294 */
a18c56e5 1295static int synclink_gt_proc_show(struct seq_file *m, void *v)
705b6c7b 1296{
705b6c7b
PF		 1297 struct slgt_info *info;
1298
a18c56e5 1299 seq_puts(m, "synclink_gt driver\n");
705b6c7b
PF		 1300
1301 info = slgt_device_list;
1302 while( info ) {
a18c56e5 1303 line_info(m, info);
705b6c7b
PF		 1304 info = info->next_device;
1305 }
a18c56e5
AD		 1306 return 0;
1307}
705b6c7b 1308
705b6c7b
PF		 1309/*
1310 * return count of bytes in transmit buffer
1311 */
1312static int chars_in_buffer(struct tty_struct *tty)
1313{
1314 struct slgt_info *info = tty->driver_data;
403214d0 1315 int count;
705b6c7b
PF		 1316 if (sanity_check(info, tty->name, "chars_in_buffer"))
1317 return 0;
403214d0
PF		 1318 count = tbuf_bytes(info);
1319 DBGINFO(("%s chars_in_buffer()=%d\n", info->device_name, count));
1320 return count;
705b6c7b
PF		 1321}
1322
1323/*
1324 * signal remote device to throttle send data (our receive data)
1325 */
1326static void throttle(struct tty_struct * tty)
1327{
1328 struct slgt_info *info = tty->driver_data;
1329 unsigned long flags;
1330
1331 if (sanity_check(info, tty->name, "throttle"))
1332 return;
1333 DBGINFO(("%s throttle\n", info->device_name));
1334 if (I_IXOFF(tty))
1335 send_xchar(tty, STOP_CHAR(tty));
446e7687 1336 if (C_CRTSCTS(tty)) {
705b6c7b
PF		 1337 spin_lock_irqsave(&info->lock,flags);
1338 info->signals &= ~SerialSignal_RTS;
446e7687 1339 set_signals(info);
705b6c7b
PF		 1340 spin_unlock_irqrestore(&info->lock,flags);
1341 }
1342}
1343
1344/*
1345 * signal remote device to stop throttling send data (our receive data)
1346 */
1347static void unthrottle(struct tty_struct * tty)
1348{
1349 struct slgt_info *info = tty->driver_data;
1350 unsigned long flags;
1351
1352 if (sanity_check(info, tty->name, "unthrottle"))
1353 return;
1354 DBGINFO(("%s unthrottle\n", info->device_name));
1355 if (I_IXOFF(tty)) {
1356 if (info->x_char)
1357 info->x_char = 0;
1358 else
1359 send_xchar(tty, START_CHAR(tty));
1360 }
446e7687 1361 if (C_CRTSCTS(tty)) {
705b6c7b
PF		 1362 spin_lock_irqsave(&info->lock,flags);
1363 info->signals |= SerialSignal_RTS;
446e7687 1364 set_signals(info);
705b6c7b
PF		 1365 spin_unlock_irqrestore(&info->lock,flags);
1366 }
1367}
1368
1369/*
1370 * set or clear transmit break condition
1371 * break_state -1=set break condition, 0=clear
1372 */
9e98966c 1373static int set_break(struct tty_struct *tty, int break_state)
705b6c7b
PF		 1374{
1375 struct slgt_info *info = tty->driver_data;
1376 unsigned short value;
1377 unsigned long flags;
1378
1379 if (sanity_check(info, tty->name, "set_break"))
9e98966c 1380 return -EINVAL;
705b6c7b
PF		 1381 DBGINFO(("%s set_break(%d)\n", info->device_name, break_state));
1382
1383 spin_lock_irqsave(&info->lock,flags);
1384 value = rd_reg16(info, TCR);
1385 if (break_state == -1)
1386 value |= BIT6;
1387 else
1388 value &= ~BIT6;
1389 wr_reg16(info, TCR, value);
1390 spin_unlock_irqrestore(&info->lock,flags);
9e98966c 1391 return 0;
705b6c7b
PF		 1392}
1393
af69c7f9 1394#if SYNCLINK_GENERIC_HDLC
705b6c7b
PF		 1395
1396/**
87d03a94
JS		 1397 * hdlcdev_attach - called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1398 * @dev: pointer to network device structure
1399 * @encoding: serial encoding setting
1400 * @parity: FCS setting
705b6c7b 1401 *
87d03a94 1402 * Set encoding and frame check sequence (FCS) options.
705b6c7b 1403 *
87d03a94 1404 * Return: 0 if success, otherwise error code
705b6c7b
PF		 1405 */
1406static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1407 unsigned short parity)
1408{
1409 struct slgt_info *info = dev_to_port(dev);
1410 unsigned char new_encoding;
1411 unsigned short new_crctype;
1412
1413 /* return error if TTY interface open */
8fb06c77 1414 if (info->port.count)
705b6c7b
PF		 1415 return -EBUSY;
1416
1417 DBGINFO(("%s hdlcdev_attach\n", info->device_name));
1418
1419 switch (encoding)
1420 {
1421 case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
1422 case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1423 case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1424 case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1425 case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1426 default: return -EINVAL;
1427 }
1428
1429 switch (parity)
1430 {
1431 case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
1432 case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1433 case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1434 default: return -EINVAL;
1435 }
1436
1437 info->params.encoding = new_encoding;
53b3531b 1438 info->params.crc_type = new_crctype;
705b6c7b
PF		 1439
1440 /* if network interface up, reprogram hardware */
1441 if (info->netcount)
1442 program_hw(info);
1443
1444 return 0;
1445}
1446
1447/**
87d03a94
JS		 1448 * hdlcdev_xmit - called by generic HDLC layer to send a frame
1449 * @skb: socket buffer containing HDLC frame
1450 * @dev: pointer to network device structure
705b6c7b 1451 */
4c5d502d
SH		 1452static netdev_tx_t hdlcdev_xmit(struct sk_buff *skb,
1453 struct net_device *dev)
705b6c7b
PF		 1454{
1455 struct slgt_info *info = dev_to_port(dev);
705b6c7b
PF		 1456 unsigned long flags;
1457
1458 DBGINFO(("%s hdlc_xmit\n", dev->name));
1459
de538eb3
PF		 1460 if (!skb->len)
1461 return NETDEV_TX_OK;
1462
705b6c7b
PF		 1463 /* stop sending until this frame completes */
1464 netif_stop_queue(dev);
1465
705b6c7b 1466 /* update network statistics */
198191c4
KH		 1467 dev->stats.tx_packets++;
1468 dev->stats.tx_bytes += skb->len;
705b6c7b 1469
705b6c7b 1470 /* save start time for transmit timeout detection */
860e9538 1471 netif_trans_update(dev);
705b6c7b 1472
de538eb3
PF		 1473 spin_lock_irqsave(&info->lock, flags);
1474 tx_load(info, skb->data, skb->len);
1475 spin_unlock_irqrestore(&info->lock, flags);
1476
1477 /* done with socket buffer, so free it */
1478 dev_kfree_skb(skb);
705b6c7b 1479
4c5d502d 1480 return NETDEV_TX_OK;
705b6c7b
PF		 1481}
1482
1483/**
87d03a94
JS		 1484 * hdlcdev_open - called by network layer when interface enabled
1485 * @dev: pointer to network device structure
705b6c7b 1486 *
87d03a94 1487 * Claim resources and initialize hardware.
705b6c7b 1488 *
87d03a94 1489 * Return: 0 if success, otherwise error code
705b6c7b
PF		 1490 */
1491static int hdlcdev_open(struct net_device *dev)
1492{
1493 struct slgt_info *info = dev_to_port(dev);
1494 int rc;
1495 unsigned long flags;
1496
d4c63b7c
PF		 1497 if (!try_module_get(THIS_MODULE))
1498 return -EBUSY;
1499
705b6c7b
PF		 1500 DBGINFO(("%s hdlcdev_open\n", dev->name));
1501
1502 /* generic HDLC layer open processing */
3236133e
GKH		 1503 rc = hdlc_open(dev);
1504 if (rc)
705b6c7b
PF		 1505 return rc;
1506
1507 /* arbitrate between network and tty opens */
1508 spin_lock_irqsave(&info->netlock, flags);
8fb06c77 1509 if (info->port.count != 0 || info->netcount != 0) {
705b6c7b
PF		 1510 DBGINFO(("%s hdlc_open busy\n", dev->name));
1511 spin_unlock_irqrestore(&info->netlock, flags);
1512 return -EBUSY;
1513 }
1514 info->netcount=1;
1515 spin_unlock_irqrestore(&info->netlock, flags);
1516
1517 /* claim resources and init adapter */
1518 if ((rc = startup(info)) != 0) {
1519 spin_lock_irqsave(&info->netlock, flags);
1520 info->netcount=0;
1521 spin_unlock_irqrestore(&info->netlock, flags);
1522 return rc;
1523 }
1524
9fe8074b
JP		 1525 /* assert RTS and DTR, apply hardware settings */
1526 info->signals |= SerialSignal_RTS | SerialSignal_DTR;
705b6c7b
PF		 1527 program_hw(info);
1528
1529 /* enable network layer transmit */
860e9538 1530 netif_trans_update(dev);
705b6c7b
PF		 1531 netif_start_queue(dev);
1532
1533 /* inform generic HDLC layer of current DCD status */
1534 spin_lock_irqsave(&info->lock, flags);
1535 get_signals(info);
1536 spin_unlock_irqrestore(&info->lock, flags);
fbeff3c1
KH		 1537 if (info->signals & SerialSignal_DCD)
1538 netif_carrier_on(dev);
1539 else
1540 netif_carrier_off(dev);
705b6c7b
PF		 1541 return 0;
1542}
1543
1544/**
87d03a94
JS		 1545 * hdlcdev_close - called by network layer when interface is disabled
1546 * @dev: pointer to network device structure
705b6c7b 1547 *
87d03a94 1548 * Shutdown hardware and release resources.
705b6c7b 1549 *
87d03a94 1550 * Return: 0 if success, otherwise error code
705b6c7b
PF		 1551 */
1552static int hdlcdev_close(struct net_device *dev)
1553{
1554 struct slgt_info *info = dev_to_port(dev);
1555 unsigned long flags;
1556
1557 DBGINFO(("%s hdlcdev_close\n", dev->name));
1558
1559 netif_stop_queue(dev);
1560
1561 /* shutdown adapter and release resources */
1562 shutdown(info);
1563
1564 hdlc_close(dev);
1565
1566 spin_lock_irqsave(&info->netlock, flags);
1567 info->netcount=0;
1568 spin_unlock_irqrestore(&info->netlock, flags);
1569
d4c63b7c 1570 module_put(THIS_MODULE);
705b6c7b
PF		 1571 return 0;
1572}
1573
1574/**
87d03a94
JS		 1575 * hdlcdev_ioctl - called by network layer to process IOCTL call to network device
1576 * @dev: pointer to network device structure
1577 * @ifr: pointer to network interface request structure
1578 * @cmd: IOCTL command code
705b6c7b 1579 *
87d03a94 1580 * Return: 0 if success, otherwise error code
705b6c7b
PF		 1581 */
1582static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1583{
1584 const size_t size = sizeof(sync_serial_settings);
1585 sync_serial_settings new_line;
1586 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1587 struct slgt_info *info = dev_to_port(dev);
1588 unsigned int flags;
1589
1590 DBGINFO(("%s hdlcdev_ioctl\n", dev->name));
1591
1592 /* return error if TTY interface open */
8fb06c77 1593 if (info->port.count)
705b6c7b
PF		 1594 return -EBUSY;
1595
1596 if (cmd != SIOCWANDEV)
1597 return hdlc_ioctl(dev, ifr, cmd);
1598
ed77ed61
VK		 1599 memset(&new_line, 0, sizeof(new_line));
1600
705b6c7b
PF		 1601 switch(ifr->ifr_settings.type) {
1602 case IF_GET_IFACE: /* return current sync_serial_settings */
1603
1604 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1605 if (ifr->ifr_settings.size < size) {
1606 ifr->ifr_settings.size = size; /* data size wanted */
1607 return -ENOBUFS;
1608 }
1609
1610 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1611 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1612 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1613 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1614
1615 switch (flags){
1616 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1617 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
1618 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
1619 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1620 default: new_line.clock_type = CLOCK_DEFAULT;
1621 }
1622
1623 new_line.clock_rate = info->params.clock_speed;
1624 new_line.loopback = info->params.loopback ? 1:0;
1625
1626 if (copy_to_user(line, &new_line, size))
1627 return -EFAULT;
1628 return 0;
1629
1630 case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1631
1632 if(!capable(CAP_NET_ADMIN))
1633 return -EPERM;
1634 if (copy_from_user(&new_line, line, size))
1635 return -EFAULT;
1636
1637 switch (new_line.clock_type)
1638 {
1639 case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1640 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1641 case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
1642 case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
1643 case CLOCK_DEFAULT: flags = info->params.flags &
1644 (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1645 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1646 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1647 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
1648 default: return -EINVAL;
1649 }
1650
1651 if (new_line.loopback != 0 && new_line.loopback != 1)
1652 return -EINVAL;
1653
1654 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1655 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1656 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1657 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1658 info->params.flags |= flags;
1659
1660 info->params.loopback = new_line.loopback;
1661
1662 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1663 info->params.clock_speed = new_line.clock_rate;
1664 else
1665 info->params.clock_speed = 0;
1666
1667 /* if network interface up, reprogram hardware */
1668 if (info->netcount)
1669 program_hw(info);
1670 return 0;
1671
1672 default:
1673 return hdlc_ioctl(dev, ifr, cmd);
1674 }
1675}
1676
1677/**
87d03a94
JS		 1678 * hdlcdev_tx_timeout - called by network layer when transmit timeout is detected
1679 * @dev: pointer to network device structure
71b061e2 1680 * @txqueue: unused
705b6c7b 1681 */
0290bd29 1682static void hdlcdev_tx_timeout(struct net_device *dev, unsigned int txqueue)
705b6c7b
PF		 1683{
1684 struct slgt_info *info = dev_to_port(dev);
705b6c7b
PF		 1685 unsigned long flags;
1686
1687 DBGINFO(("%s hdlcdev_tx_timeout\n", dev->name));
1688
198191c4
KH		 1689 dev->stats.tx_errors++;
1690 dev->stats.tx_aborted_errors++;
705b6c7b
PF		 1691
1692 spin_lock_irqsave(&info->lock,flags);
1693 tx_stop(info);
1694 spin_unlock_irqrestore(&info->lock,flags);
1695
1696 netif_wake_queue(dev);
1697}
1698
1699/**
87d03a94
JS		 1700 * hdlcdev_tx_done - called by device driver when transmit completes
1701 * @info: pointer to device instance information
705b6c7b 1702 *
87d03a94 1703 * Reenable network layer transmit if stopped.
705b6c7b
PF		 1704 */
1705static void hdlcdev_tx_done(struct slgt_info *info)
1706{
1707 if (netif_queue_stopped(info->netdev))
1708 netif_wake_queue(info->netdev);
1709}
1710
1711/**
87d03a94
JS		 1712 * hdlcdev_rx - called by device driver when frame received
1713 * @info: pointer to device instance information
1714 * @buf: pointer to buffer contianing frame data
1715 * @size: count of data bytes in buf
705b6c7b 1716 *
87d03a94 1717 * Pass frame to network layer.
705b6c7b
PF		 1718 */
1719static void hdlcdev_rx(struct slgt_info *info, char *buf, int size)
1720{
1721 struct sk_buff *skb = dev_alloc_skb(size);
1722 struct net_device *dev = info->netdev;
705b6c7b
PF		 1723
1724 DBGINFO(("%s hdlcdev_rx\n", dev->name));
1725
1726 if (skb == NULL) {
1727 DBGERR(("%s: can't alloc skb, drop packet\n", dev->name));
198191c4 1728 dev->stats.rx_dropped++;
705b6c7b
PF		 1729 return;
1730 }
1731
59ae1d12 1732 skb_put_data(skb, buf, size);
705b6c7b 1733
198191c4 1734 skb->protocol = hdlc_type_trans(skb, dev);
705b6c7b 1735
198191c4
KH		 1736 dev->stats.rx_packets++;
1737 dev->stats.rx_bytes += size;
705b6c7b
PF		 1738
1739 netif_rx(skb);
705b6c7b
PF		 1740}
1741
991990a1
KH		 1742static const struct net_device_ops hdlcdev_ops = {
1743 .ndo_open = hdlcdev_open,
1744 .ndo_stop = hdlcdev_close,
991990a1
KH		 1745 .ndo_start_xmit = hdlc_start_xmit,
1746 .ndo_do_ioctl = hdlcdev_ioctl,
1747 .ndo_tx_timeout = hdlcdev_tx_timeout,
1748};
1749
705b6c7b 1750/**
87d03a94
JS		 1751 * hdlcdev_init - called by device driver when adding device instance
1752 * @info: pointer to device instance information
705b6c7b 1753 *
87d03a94 1754 * Do generic HDLC initialization.
705b6c7b 1755 *
87d03a94 1756 * Return: 0 if success, otherwise error code
705b6c7b
PF		 1757 */
1758static int hdlcdev_init(struct slgt_info *info)
1759{
1760 int rc;
1761 struct net_device *dev;
1762 hdlc_device *hdlc;
1763
1764 /* allocate and initialize network and HDLC layer objects */
1765
3236133e
GKH		 1766 dev = alloc_hdlcdev(info);
1767 if (!dev) {
705b6c7b
PF		 1768 printk(KERN_ERR "%s hdlc device alloc failure\n", info->device_name);
1769 return -ENOMEM;
1770 }
1771
1772 /* for network layer reporting purposes only */
1773 dev->mem_start = info->phys_reg_addr;
1774 dev->mem_end = info->phys_reg_addr + SLGT_REG_SIZE - 1;
1775 dev->irq = info->irq_level;
1776
1777 /* network layer callbacks and settings */
991990a1
KH		 1778 dev->netdev_ops = &hdlcdev_ops;
1779 dev->watchdog_timeo = 10 * HZ;
705b6c7b
PF		 1780 dev->tx_queue_len = 50;
1781
1782 /* generic HDLC layer callbacks and settings */
1783 hdlc = dev_to_hdlc(dev);
1784 hdlc->attach = hdlcdev_attach;
1785 hdlc->xmit = hdlcdev_xmit;
1786
1787 /* register objects with HDLC layer */
3236133e
GKH		 1788 rc = register_hdlc_device(dev);
1789 if (rc) {
705b6c7b
PF		 1790 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
1791 free_netdev(dev);
1792 return rc;
1793 }
1794
1795 info->netdev = dev;
1796 return 0;
1797}
1798
1799/**
87d03a94
JS		 1800 * hdlcdev_exit - called by device driver when removing device instance
1801 * @info: pointer to device instance information
705b6c7b 1802 *
87d03a94 1803 * Do generic HDLC cleanup.
705b6c7b
PF		 1804 */
1805static void hdlcdev_exit(struct slgt_info *info)
1806{
1807 unregister_hdlc_device(info->netdev);
1808 free_netdev(info->netdev);
1809 info->netdev = NULL;
1810}
1811
1812#endif /* ifdef CONFIG_HDLC */
1813
1814/*
1815 * get async data from rx DMA buffers
1816 */
1817static void rx_async(struct slgt_info *info)
1818{
705b6c7b
PF		 1819 struct mgsl_icount *icount = &info->icount;
1820 unsigned int start, end;
1821 unsigned char *p;
1822 unsigned char status;
1823 struct slgt_desc *bufs = info->rbufs;
1824 int i, count;
33f0f88f
AC		 1825 int chars = 0;
1826 int stat;
1827 unsigned char ch;
705b6c7b
PF		 1828
1829 start = end = info->rbuf_current;
1830
1831 while(desc_complete(bufs[end])) {
1832 count = desc_count(bufs[end]) - info->rbuf_index;
1833 p = bufs[end].buf + info->rbuf_index;
1834
1835 DBGISR(("%s rx_async count=%d\n", info->device_name, count));
1836 DBGDATA(info, p, count, "rx");
1837
1838 for(i=0 ; i < count; i+=2, p+=2) {
33f0f88f 1839 ch = *p;
705b6c7b
PF		 1840 icount->rx++;
1841
33f0f88f
AC		 1842 stat = 0;
1843
3236133e
GKH		 1844 status = *(p + 1) & (BIT1 + BIT0);
1845 if (status) {
202af6d5 1846 if (status & BIT1)
705b6c7b 1847 icount->parity++;
202af6d5 1848 else if (status & BIT0)
705b6c7b
PF		 1849 icount->frame++;
1850 /* discard char if tty control flags say so */
1851 if (status & info->ignore_status_mask)
1852 continue;
202af6d5 1853 if (status & BIT1)
33f0f88f 1854 stat = TTY_PARITY;
202af6d5 1855 else if (status & BIT0)
33f0f88f 1856 stat = TTY_FRAME;
705b6c7b 1857 }
92a19f9c
JS		 1858 tty_insert_flip_char(&info->port, ch, stat);
1859 chars++;
705b6c7b
PF		 1860 }
1861
1862 if (i < count) {
1863 /* receive buffer not completed */
1864 info->rbuf_index += i;
40565f19 1865 mod_timer(&info->rx_timer, jiffies + 1);
705b6c7b
PF		 1866 break;
1867 }
1868
1869 info->rbuf_index = 0;
1870 free_rbufs(info, end, end);
1871
1872 if (++end == info->rbuf_count)
1873 end = 0;
1874
1875 /* if entire list searched then no frame available */
1876 if (end == start)
1877 break;
1878 }
1879
2e124b4a
JS		 1880 if (chars)
1881 tty_flip_buffer_push(&info->port);
705b6c7b
PF		 1882}
1883
1884/*
1885 * return next bottom half action to perform
1886 */
1887static int bh_action(struct slgt_info *info)
1888{
1889 unsigned long flags;
1890 int rc;
1891
1892 spin_lock_irqsave(&info->lock,flags);
1893
1894 if (info->pending_bh & BH_RECEIVE) {
1895 info->pending_bh &= ~BH_RECEIVE;
1896 rc = BH_RECEIVE;
1897 } else if (info->pending_bh & BH_TRANSMIT) {
1898 info->pending_bh &= ~BH_TRANSMIT;
1899 rc = BH_TRANSMIT;
1900 } else if (info->pending_bh & BH_STATUS) {
1901 info->pending_bh &= ~BH_STATUS;
1902 rc = BH_STATUS;
1903 } else {
1904 /* Mark BH routine as complete */
0fab6de0
JP		 1905 info->bh_running = false;
1906 info->bh_requested = false;
705b6c7b
PF		 1907 rc = 0;
1908 }
1909
1910 spin_unlock_irqrestore(&info->lock,flags);
1911
1912 return rc;
1913}
1914
1915/*
1916 * perform bottom half processing
1917 */
c4028958 1918static void bh_handler(struct work_struct *work)
705b6c7b 1919{
c4028958 1920 struct slgt_info *info = container_of(work, struct slgt_info, task);
705b6c7b
PF		 1921 int action;
1922
0fab6de0 1923 info->bh_running = true;
705b6c7b
PF		 1924
1925 while((action = bh_action(info))) {
1926 switch (action) {
1927 case BH_RECEIVE:
1928 DBGBH(("%s bh receive\n", info->device_name));
1929 switch(info->params.mode) {
1930 case MGSL_MODE_ASYNC:
1931 rx_async(info);
1932 break;
1933 case MGSL_MODE_HDLC:
1934 while(rx_get_frame(info));
1935 break;
1936 case MGSL_MODE_RAW:
cb10dc9a
PF		 1937 case MGSL_MODE_MONOSYNC:
1938 case MGSL_MODE_BISYNC:
9807224f 1939 case MGSL_MODE_XSYNC:
705b6c7b
PF		 1940 while(rx_get_buf(info));
1941 break;
1942 }
1943 /* restart receiver if rx DMA buffers exhausted */
1944 if (info->rx_restart)
1945 rx_start(info);
1946 break;
1947 case BH_TRANSMIT:
1948 bh_transmit(info);
1949 break;
1950 case BH_STATUS:
1951 DBGBH(("%s bh status\n", info->device_name));
1952 info->ri_chkcount = 0;
1953 info->dsr_chkcount = 0;
1954 info->dcd_chkcount = 0;
1955 info->cts_chkcount = 0;
1956 break;
1957 default:
1958 DBGBH(("%s unknown action\n", info->device_name));
1959 break;
1960 }
1961 }
1962 DBGBH(("%s bh_handler exit\n", info->device_name));
1963}
1964
1965static void bh_transmit(struct slgt_info *info)
1966{
8fb06c77 1967 struct tty_struct *tty = info->port.tty;
705b6c7b
PF		 1968
1969 DBGBH(("%s bh_transmit\n", info->device_name));
b963a844 1970 if (tty)
705b6c7b 1971 tty_wakeup(tty);
705b6c7b
PF		 1972}
1973
ed8485fb 1974static void dsr_change(struct slgt_info *info, unsigned short status)
705b6c7b 1975{
ed8485fb
PF		 1976 if (status & BIT3) {
1977 info->signals |= SerialSignal_DSR;
1978 info->input_signal_events.dsr_up++;
1979 } else {
1980 info->signals &= ~SerialSignal_DSR;
1981 info->input_signal_events.dsr_down++;
1982 }
705b6c7b
PF		 1983 DBGISR(("dsr_change %s signals=%04X\n", info->device_name, info->signals));
1984 if ((info->dsr_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
1985 slgt_irq_off(info, IRQ_DSR);
1986 return;
1987 }
1988 info->icount.dsr++;
705b6c7b
PF		 1989 wake_up_interruptible(&info->status_event_wait_q);
1990 wake_up_interruptible(&info->event_wait_q);
1991 info->pending_bh |= BH_STATUS;
1992}
1993
ed8485fb 1994static void cts_change(struct slgt_info *info, unsigned short status)
705b6c7b 1995{
ed8485fb
PF		 1996 if (status & BIT2) {
1997 info->signals |= SerialSignal_CTS;
1998 info->input_signal_events.cts_up++;
1999 } else {
2000 info->signals &= ~SerialSignal_CTS;
2001 info->input_signal_events.cts_down++;
2002 }
705b6c7b
PF		 2003 DBGISR(("cts_change %s signals=%04X\n", info->device_name, info->signals));
2004 if ((info->cts_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2005 slgt_irq_off(info, IRQ_CTS);
2006 return;
2007 }
2008 info->icount.cts++;
705b6c7b
PF		 2009 wake_up_interruptible(&info->status_event_wait_q);
2010 wake_up_interruptible(&info->event_wait_q);
2011 info->pending_bh |= BH_STATUS;
2012
f21ec3d2 2013 if (tty_port_cts_enabled(&info->port)) {
8fb06c77
AC		 2014 if (info->port.tty) {
2015 if (info->port.tty->hw_stopped) {
705b6c7b 2016 if (info->signals & SerialSignal_CTS) {
8fb06c77 2017 info->port.tty->hw_stopped = 0;
705b6c7b
PF		 2018 info->pending_bh |= BH_TRANSMIT;
2019 return;
2020 }
2021 } else {
2022 if (!(info->signals & SerialSignal_CTS))
8fb06c77 2023 info->port.tty->hw_stopped = 1;
705b6c7b
PF		 2024 }
2025 }
2026 }
2027}
2028
ed8485fb 2029static void dcd_change(struct slgt_info *info, unsigned short status)
705b6c7b 2030{
ed8485fb
PF		 2031 if (status & BIT1) {
2032 info->signals |= SerialSignal_DCD;
2033 info->input_signal_events.dcd_up++;
2034 } else {
2035 info->signals &= ~SerialSignal_DCD;
2036 info->input_signal_events.dcd_down++;
2037 }
705b6c7b
PF		 2038 DBGISR(("dcd_change %s signals=%04X\n", info->device_name, info->signals));
2039 if ((info->dcd_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2040 slgt_irq_off(info, IRQ_DCD);
2041 return;
2042 }
2043 info->icount.dcd++;
af69c7f9 2044#if SYNCLINK_GENERIC_HDLC
fbeff3c1
KH		 2045 if (info->netcount) {
2046 if (info->signals & SerialSignal_DCD)
2047 netif_carrier_on(info->netdev);
2048 else
2049 netif_carrier_off(info->netdev);
2050 }
705b6c7b
PF		 2051#endif
2052 wake_up_interruptible(&info->status_event_wait_q);
2053 wake_up_interruptible(&info->event_wait_q);
2054 info->pending_bh |= BH_STATUS;
2055
2d68655d 2056 if (tty_port_check_carrier(&info->port)) {
705b6c7b 2057 if (info->signals & SerialSignal_DCD)
8fb06c77 2058 wake_up_interruptible(&info->port.open_wait);
705b6c7b 2059 else {
8fb06c77
AC		 2060 if (info->port.tty)
2061 tty_hangup(info->port.tty);
705b6c7b
PF		 2062 }
2063 }
2064}
2065
ed8485fb 2066static void ri_change(struct slgt_info *info, unsigned short status)
705b6c7b 2067{
ed8485fb
PF		 2068 if (status & BIT0) {
2069 info->signals |= SerialSignal_RI;
2070 info->input_signal_events.ri_up++;
2071 } else {
2072 info->signals &= ~SerialSignal_RI;
2073 info->input_signal_events.ri_down++;
2074 }
705b6c7b
PF		 2075 DBGISR(("ri_change %s signals=%04X\n", info->device_name, info->signals));
2076 if ((info->ri_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2077 slgt_irq_off(info, IRQ_RI);
2078 return;
2079 }
ed8485fb 2080 info->icount.rng++;
705b6c7b
PF		 2081 wake_up_interruptible(&info->status_event_wait_q);
2082 wake_up_interruptible(&info->event_wait_q);
2083 info->pending_bh |= BH_STATUS;
2084}
2085
5ba5a5d2
PF		 2086static void isr_rxdata(struct slgt_info *info)
2087{
2088 unsigned int count = info->rbuf_fill_count;
2089 unsigned int i = info->rbuf_fill_index;
2090 unsigned short reg;
2091
2092 while (rd_reg16(info, SSR) & IRQ_RXDATA) {
2093 reg = rd_reg16(info, RDR);
2094 DBGISR(("isr_rxdata %s RDR=%04X\n", info->device_name, reg));
2095 if (desc_complete(info->rbufs[i])) {
2096 /* all buffers full */
2097 rx_stop(info);
bf22182c 2098 info->rx_restart = true;
5ba5a5d2
PF		 2099 continue;
2100 }
2101 info->rbufs[i].buf[count++] = (unsigned char)reg;
2102 /* async mode saves status byte to buffer for each data byte */
2103 if (info->params.mode == MGSL_MODE_ASYNC)
2104 info->rbufs[i].buf[count++] = (unsigned char)(reg >> 8);
2105 if (count == info->rbuf_fill_level || (reg & BIT10)) {
2106 /* buffer full or end of frame */
2107 set_desc_count(info->rbufs[i], count);
2108 set_desc_status(info->rbufs[i], BIT15 | (reg >> 8));
2109 info->rbuf_fill_count = count = 0;
2110 if (++i == info->rbuf_count)
2111 i = 0;
2112 info->pending_bh |= BH_RECEIVE;
2113 }
2114 }
2115
2116 info->rbuf_fill_index = i;
2117 info->rbuf_fill_count = count;
2118}
2119
705b6c7b
PF		 2120static void isr_serial(struct slgt_info *info)
2121{
2122 unsigned short status = rd_reg16(info, SSR);
2123
2124 DBGISR(("%s isr_serial status=%04X\n", info->device_name, status));
2125
2126 wr_reg16(info, SSR, status); /* clear pending */
2127
0fab6de0 2128 info->irq_occurred = true;
705b6c7b
PF		 2129
2130 if (info->params.mode == MGSL_MODE_ASYNC) {
2131 if (status & IRQ_TXIDLE) {
de538eb3 2132 if (info->tx_active)
705b6c7b
PF		 2133 isr_txeom(info, status);
2134 }
5ba5a5d2
PF		 2135 if (info->rx_pio && (status & IRQ_RXDATA))
2136 isr_rxdata(info);
705b6c7b
PF		 2137 if ((status & IRQ_RXBREAK) && (status & RXBREAK)) {
2138 info->icount.brk++;
2139 /* process break detection if tty control allows */
8fb06c77 2140 if (info->port.tty) {
705b6c7b
PF		 2141 if (!(status & info->ignore_status_mask)) {
2142 if (info->read_status_mask & MASK_BREAK) {
92a19f9c 2143 tty_insert_flip_char(&info->port, 0, TTY_BREAK);
8fb06c77
AC		 2144 if (info->port.flags & ASYNC_SAK)
2145 do_SAK(info->port.tty);
705b6c7b
PF		 2146 }
2147 }
2148 }
2149 }
2150 } else {
2151 if (status & (IRQ_TXIDLE + IRQ_TXUNDER))
2152 isr_txeom(info, status);
5ba5a5d2
PF		 2153 if (info->rx_pio && (status & IRQ_RXDATA))
2154 isr_rxdata(info);
705b6c7b
PF		 2155 if (status & IRQ_RXIDLE) {
2156 if (status & RXIDLE)
2157 info->icount.rxidle++;
2158 else
2159 info->icount.exithunt++;
2160 wake_up_interruptible(&info->event_wait_q);
2161 }
2162
2163 if (status & IRQ_RXOVER)
2164 rx_start(info);
2165 }
2166
2167 if (status & IRQ_DSR)
ed8485fb 2168 dsr_change(info, status);
705b6c7b 2169 if (status & IRQ_CTS)
ed8485fb 2170 cts_change(info, status);
705b6c7b 2171 if (status & IRQ_DCD)
ed8485fb 2172 dcd_change(info, status);
705b6c7b 2173 if (status & IRQ_RI)
ed8485fb 2174 ri_change(info, status);
705b6c7b
PF		 2175}
2176
2177static void isr_rdma(struct slgt_info *info)
2178{
2179 unsigned int status = rd_reg32(info, RDCSR);
2180
2181 DBGISR(("%s isr_rdma status=%08x\n", info->device_name, status));
2182
2183 /* RDCSR (rx DMA control/status)
2184 *
2185 * 31..07 reserved
2186 * 06 save status byte to DMA buffer
2187 * 05 error
2188 * 04 eol (end of list)
2189 * 03 eob (end of buffer)
2190 * 02 IRQ enable
2191 * 01 reset
2192 * 00 enable
2193 */
2194 wr_reg32(info, RDCSR, status); /* clear pending */
2195
2196 if (status & (BIT5 + BIT4)) {
2197 DBGISR(("%s isr_rdma rx_restart=1\n", info->device_name));
0fab6de0 2198 info->rx_restart = true;
705b6c7b
PF		 2199 }
2200 info->pending_bh |= BH_RECEIVE;
2201}
2202
2203static void isr_tdma(struct slgt_info *info)
2204{
2205 unsigned int status = rd_reg32(info, TDCSR);
2206
2207 DBGISR(("%s isr_tdma status=%08x\n", info->device_name, status));
2208
2209 /* TDCSR (tx DMA control/status)
2210 *
2211 * 31..06 reserved
2212 * 05 error
2213 * 04 eol (end of list)
2214 * 03 eob (end of buffer)
2215 * 02 IRQ enable
2216 * 01 reset
2217 * 00 enable
2218 */
2219 wr_reg32(info, TDCSR, status); /* clear pending */
2220
2221 if (status & (BIT5 + BIT4 + BIT3)) {
2222 // another transmit buffer has completed
2223 // run bottom half to get more send data from user
2224 info->pending_bh |= BH_TRANSMIT;
2225 }
2226}
2227
de538eb3
PF		 2228/*
2229 * return true if there are unsent tx DMA buffers, otherwise false
2230 *
2231 * if there are unsent buffers then info->tbuf_start
2232 * is set to index of first unsent buffer
2233 */
2234static bool unsent_tbufs(struct slgt_info *info)
2235{
2236 unsigned int i = info->tbuf_current;
2237 bool rc = false;
2238
2239 /*
2240 * search backwards from last loaded buffer (precedes tbuf_current)
2241 * for first unsent buffer (desc_count > 0)
2242 */
2243
2244 do {
2245 if (i)
2246 i--;
2247 else
2248 i = info->tbuf_count - 1;
2249 if (!desc_count(info->tbufs[i]))
2250 break;
2251 info->tbuf_start = i;
2252 rc = true;
2253 } while (i != info->tbuf_current);
2254
2255 return rc;
2256}
2257
705b6c7b
PF		 2258static void isr_txeom(struct slgt_info *info, unsigned short status)
2259{
2260 DBGISR(("%s txeom status=%04x\n", info->device_name, status));
2261
2262 slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
2263 tdma_reset(info);
705b6c7b
PF		 2264 if (status & IRQ_TXUNDER) {
2265 unsigned short val = rd_reg16(info, TCR);
2266 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
2267 wr_reg16(info, TCR, val); /* clear reset bit */
2268 }
2269
2270 if (info->tx_active) {
2271 if (info->params.mode != MGSL_MODE_ASYNC) {
2272 if (status & IRQ_TXUNDER)
2273 info->icount.txunder++;
2274 else if (status & IRQ_TXIDLE)
2275 info->icount.txok++;
2276 }
2277
de538eb3
PF		 2278 if (unsent_tbufs(info)) {
2279 tx_start(info);
2280 update_tx_timer(info);
2281 return;
2282 }
0fab6de0 2283 info->tx_active = false;
705b6c7b
PF		 2284
2285 del_timer(&info->tx_timer);
2286
2287 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done) {
2288 info->signals &= ~SerialSignal_RTS;
0fab6de0 2289 info->drop_rts_on_tx_done = false;
705b6c7b
PF		 2290 set_signals(info);
2291 }
2292
af69c7f9 2293#if SYNCLINK_GENERIC_HDLC
705b6c7b
PF		 2294 if (info->netcount)
2295 hdlcdev_tx_done(info);
2296 else
2297#endif
2298 {
8fb06c77 2299 if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
705b6c7b
PF		 2300 tx_stop(info);
2301 return;
2302 }
2303 info->pending_bh |= BH_TRANSMIT;
2304 }
2305 }
2306}
2307
0080b7aa
PF		 2308static void isr_gpio(struct slgt_info *info, unsigned int changed, unsigned int state)
2309{
2310 struct cond_wait *w, *prev;
2311
2312 /* wake processes waiting for specific transitions */
2313 for (w = info->gpio_wait_q, prev = NULL ; w != NULL ; w = w->next) {
2314 if (w->data & changed) {
2315 w->data = state;
2316 wake_up_interruptible(&w->q);
2317 if (prev != NULL)
2318 prev->next = w->next;
2319 else
2320 info->gpio_wait_q = w->next;
2321 } else
2322 prev = w;
2323 }
2324}
2325
705b6c7b
PF		 2326/* interrupt service routine
2327 *
2328 * irq interrupt number
2329 * dev_id device ID supplied during interrupt registration
705b6c7b 2330 */
a6f97b29 2331static irqreturn_t slgt_interrupt(int dummy, void *dev_id)
705b6c7b 2332{
a6f97b29 2333 struct slgt_info *info = dev_id;
705b6c7b
PF		 2334 unsigned int gsr;
2335 unsigned int i;
2336
a6f97b29 2337 DBGISR(("slgt_interrupt irq=%d entry\n", info->irq_level));
705b6c7b 2338
705b6c7b
PF		 2339 while((gsr = rd_reg32(info, GSR) & 0xffffff00)) {
2340 DBGISR(("%s gsr=%08x\n", info->device_name, gsr));
0fab6de0 2341 info->irq_occurred = true;
705b6c7b
PF		 2342 for(i=0; i < info->port_count ; i++) {
2343 if (info->port_array[i] == NULL)
2344 continue;
ffd7d6ba 2345 spin_lock(&info->port_array[i]->lock);
705b6c7b
PF		 2346 if (gsr & (BIT8 << i))
2347 isr_serial(info->port_array[i]);
2348 if (gsr & (BIT16 << (i*2)))
2349 isr_rdma(info->port_array[i]);
2350 if (gsr & (BIT17 << (i*2)))
2351 isr_tdma(info->port_array[i]);
ffd7d6ba 2352 spin_unlock(&info->port_array[i]->lock);
705b6c7b
PF		 2353 }
2354 }
2355
0080b7aa
PF		 2356 if (info->gpio_present) {
2357 unsigned int state;
2358 unsigned int changed;
ffd7d6ba 2359 spin_lock(&info->lock);
0080b7aa
PF		 2360 while ((changed = rd_reg32(info, IOSR)) != 0) {
2361 DBGISR(("%s iosr=%08x\n", info->device_name, changed));
2362 /* read latched state of GPIO signals */
2363 state = rd_reg32(info, IOVR);
2364 /* clear pending GPIO interrupt bits */
2365 wr_reg32(info, IOSR, changed);
2366 for (i=0 ; i < info->port_count ; i++) {
2367 if (info->port_array[i] != NULL)
2368 isr_gpio(info->port_array[i], changed, state);
2369 }
2370 }
ffd7d6ba 2371 spin_unlock(&info->lock);
0080b7aa
PF		 2372 }
2373
705b6c7b
PF		 2374 for(i=0; i < info->port_count ; i++) {
2375 struct slgt_info *port = info->port_array[i];
ffd7d6ba
PF		 2376 if (port == NULL)
2377 continue;
2378 spin_lock(&port->lock);
2379 if ((port->port.count || port->netcount) &&
705b6c7b
PF		 2380 port->pending_bh && !port->bh_running &&
2381 !port->bh_requested) {
2382 DBGISR(("%s bh queued\n", port->device_name));
2383 schedule_work(&port->task);
0fab6de0 2384 port->bh_requested = true;
705b6c7b 2385 }
ffd7d6ba 2386 spin_unlock(&port->lock);
705b6c7b
PF		 2387 }
2388
a6f97b29 2389 DBGISR(("slgt_interrupt irq=%d exit\n", info->irq_level));
705b6c7b
PF		 2390 return IRQ_HANDLED;
2391}
2392
2393static int startup(struct slgt_info *info)
2394{
2395 DBGINFO(("%s startup\n", info->device_name));
2396
d41861ca 2397 if (tty_port_initialized(&info->port))
705b6c7b
PF		 2398 return 0;
2399
2400 if (!info->tx_buf) {
2401 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
2402 if (!info->tx_buf) {
2403 DBGERR(("%s can't allocate tx buffer\n", info->device_name));
2404 return -ENOMEM;
2405 }
2406 }
2407
2408 info->pending_bh = 0;
2409
2410 memset(&info->icount, 0, sizeof(info->icount));
2411
2412 /* program hardware for current parameters */
2413 change_params(info);
2414
8fb06c77
AC		 2415 if (info->port.tty)
2416 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
705b6c7b 2417
d41861ca 2418 tty_port_set_initialized(&info->port, 1);
705b6c7b
PF		 2419
2420 return 0;
2421}
2422
2423/*
2424 * called by close() and hangup() to shutdown hardware
2425 */
2426static void shutdown(struct slgt_info *info)
2427{
2428 unsigned long flags;
2429
d41861ca 2430 if (!tty_port_initialized(&info->port))
705b6c7b
PF		 2431 return;
2432
2433 DBGINFO(("%s shutdown\n", info->device_name));
2434
2435 /* clear status wait queue because status changes */
2436 /* can't happen after shutting down the hardware */
2437 wake_up_interruptible(&info->status_event_wait_q);
2438 wake_up_interruptible(&info->event_wait_q);
2439
2440 del_timer_sync(&info->tx_timer);
2441 del_timer_sync(&info->rx_timer);
2442
2443 kfree(info->tx_buf);
2444 info->tx_buf = NULL;
2445
2446 spin_lock_irqsave(&info->lock,flags);
2447
2448 tx_stop(info);
2449 rx_stop(info);
2450
2451 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
2452
adc8d746 2453 if (!info->port.tty || info->port.tty->termios.c_cflag & HUPCL) {
9fe8074b 2454 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
705b6c7b
PF		 2455 set_signals(info);
2456 }
2457
0080b7aa
PF		 2458 flush_cond_wait(&info->gpio_wait_q);
2459
705b6c7b
PF		 2460 spin_unlock_irqrestore(&info->lock,flags);
2461
8fb06c77
AC		 2462 if (info->port.tty)
2463 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
705b6c7b 2464
d41861ca 2465 tty_port_set_initialized(&info->port, 0);
705b6c7b
PF		 2466}
2467
2468static void program_hw(struct slgt_info *info)
2469{
2470 unsigned long flags;
2471
2472 spin_lock_irqsave(&info->lock,flags);
2473
2474 rx_stop(info);
2475 tx_stop(info);
2476
cb10dc9a 2477 if (info->params.mode != MGSL_MODE_ASYNC ||
705b6c7b 2478 info->netcount)
cb10dc9a 2479 sync_mode(info);
705b6c7b
PF		 2480 else
2481 async_mode(info);
2482
2483 set_signals(info);
2484
2485 info->dcd_chkcount = 0;
2486 info->cts_chkcount = 0;
2487 info->ri_chkcount = 0;
2488 info->dsr_chkcount = 0;
2489
a6b2f87b 2490 slgt_irq_on(info, IRQ_DCD | IRQ_CTS | IRQ_DSR | IRQ_RI);
705b6c7b
PF		 2491 get_signals(info);
2492
2493 if (info->netcount ||
adc8d746 2494 (info->port.tty && info->port.tty->termios.c_cflag & CREAD))
705b6c7b
PF		 2495 rx_start(info);
2496
2497 spin_unlock_irqrestore(&info->lock,flags);
2498}
2499
2500/*
2501 * reconfigure adapter based on new parameters
2502 */
2503static void change_params(struct slgt_info *info)
2504{
2505 unsigned cflag;
2506 int bits_per_char;
2507
adc8d746 2508 if (!info->port.tty)
705b6c7b
PF		 2509 return;
2510 DBGINFO(("%s change_params\n", info->device_name));
2511
adc8d746 2512 cflag = info->port.tty->termios.c_cflag;
705b6c7b 2513
9fe8074b
JP		 2514 /* if B0 rate (hangup) specified then negate RTS and DTR */
2515 /* otherwise assert RTS and DTR */
705b6c7b 2516 if (cflag & CBAUD)
9fe8074b 2517 info->signals |= SerialSignal_RTS | SerialSignal_DTR;
705b6c7b 2518 else
9fe8074b 2519 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
705b6c7b
PF		 2520
2521 /* byte size and parity */
2522
2523 switch (cflag & CSIZE) {
2524 case CS5: info->params.data_bits = 5; break;
2525 case CS6: info->params.data_bits = 6; break;
2526 case CS7: info->params.data_bits = 7; break;
2527 case CS8: info->params.data_bits = 8; break;
2528 default: info->params.data_bits = 7; break;
2529 }
2530
2531 info->params.stop_bits = (cflag & CSTOPB) ? 2 : 1;
2532
2533 if (cflag & PARENB)
2534 info->params.parity = (cflag & PARODD) ? ASYNC_PARITY_ODD : ASYNC_PARITY_EVEN;
2535 else
2536 info->params.parity = ASYNC_PARITY_NONE;
2537
2538 /* calculate number of jiffies to transmit a full
2539 * FIFO (32 bytes) at specified data rate
2540 */
2541 bits_per_char = info->params.data_bits +
2542 info->params.stop_bits + 1;
2543
8fb06c77 2544 info->params.data_rate = tty_get_baud_rate(info->port.tty);
705b6c7b
PF		 2545
2546 if (info->params.data_rate) {
2547 info->timeout = (32*HZ*bits_per_char) /
2548 info->params.data_rate;
2549 }
2550 info->timeout += HZ/50; /* Add .02 seconds of slop */
2551
5604a98e 2552 tty_port_set_cts_flow(&info->port, cflag & CRTSCTS);
2d68655d 2553 tty_port_set_check_carrier(&info->port, ~cflag & CLOCAL);
705b6c7b
PF		 2554
2555 /* process tty input control flags */
2556
2557 info->read_status_mask = IRQ_RXOVER;
8fb06c77 2558 if (I_INPCK(info->port.tty))
705b6c7b 2559 info->read_status_mask |= MASK_PARITY | MASK_FRAMING;
446e7687
NC		 2560 if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
2561 info->read_status_mask |= MASK_BREAK;
8fb06c77 2562 if (I_IGNPAR(info->port.tty))
705b6c7b 2563 info->ignore_status_mask |= MASK_PARITY | MASK_FRAMING;
8fb06c77 2564 if (I_IGNBRK(info->port.tty)) {
705b6c7b
PF		 2565 info->ignore_status_mask |= MASK_BREAK;
2566 /* If ignoring parity and break indicators, ignore
2567 * overruns too. (For real raw support).
2568 */
8fb06c77 2569 if (I_IGNPAR(info->port.tty))
705b6c7b
PF		 2570 info->ignore_status_mask |= MASK_OVERRUN;
2571 }
2572
2573 program_hw(info);
2574}
2575
2576static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount)
2577{
2578 DBGINFO(("%s get_stats\n", info->device_name));
2579 if (!user_icount) {
2580 memset(&info->icount, 0, sizeof(info->icount));
2581 } else {
2582 if (copy_to_user(user_icount, &info->icount, sizeof(struct mgsl_icount)))
2583 return -EFAULT;
2584 }
2585 return 0;
2586}
2587
2588static int get_params(struct slgt_info *info, MGSL_PARAMS __user *user_params)
2589{
2590 DBGINFO(("%s get_params\n", info->device_name));
2591 if (copy_to_user(user_params, &info->params, sizeof(MGSL_PARAMS)))
2592 return -EFAULT;
2593 return 0;
2594}
2595
2596static int set_params(struct slgt_info *info, MGSL_PARAMS __user *new_params)
2597{
2598 unsigned long flags;
2599 MGSL_PARAMS tmp_params;
2600
2601 DBGINFO(("%s set_params\n", info->device_name));
2602 if (copy_from_user(&tmp_params, new_params, sizeof(MGSL_PARAMS)))
2603 return -EFAULT;
2604
2605 spin_lock_irqsave(&info->lock, flags);
1f80769f
PF		 2606 if (tmp_params.mode == MGSL_MODE_BASE_CLOCK)
2607 info->base_clock = tmp_params.clock_speed;
2608 else
2609 memcpy(&info->params, &tmp_params, sizeof(MGSL_PARAMS));
705b6c7b
PF		 2610 spin_unlock_irqrestore(&info->lock, flags);
2611
1f80769f 2612 program_hw(info);
705b6c7b
PF		 2613
2614 return 0;
2615}
2616
2617static int get_txidle(struct slgt_info *info, int __user *idle_mode)
2618{
2619 DBGINFO(("%s get_txidle=%d\n", info->device_name, info->idle_mode));
2620 if (put_user(info->idle_mode, idle_mode))
2621 return -EFAULT;
2622 return 0;
2623}
2624
2625static int set_txidle(struct slgt_info *info, int idle_mode)
2626{
2627 unsigned long flags;
2628 DBGINFO(("%s set_txidle(%d)\n", info->device_name, idle_mode));
2629 spin_lock_irqsave(&info->lock,flags);
2630 info->idle_mode = idle_mode;
643f3319
PF		 2631 if (info->params.mode != MGSL_MODE_ASYNC)
2632 tx_set_idle(info);
705b6c7b
PF		 2633 spin_unlock_irqrestore(&info->lock,flags);
2634 return 0;
2635}
2636
2637static int tx_enable(struct slgt_info *info, int enable)
2638{
2639 unsigned long flags;
2640 DBGINFO(("%s tx_enable(%d)\n", info->device_name, enable));
2641 spin_lock_irqsave(&info->lock,flags);
2642 if (enable) {
2643 if (!info->tx_enabled)
2644 tx_start(info);
2645 } else {
2646 if (info->tx_enabled)
2647 tx_stop(info);
2648 }
2649 spin_unlock_irqrestore(&info->lock,flags);
2650 return 0;
2651}
2652
2653/*
2654 * abort transmit HDLC frame
2655 */
2656static int tx_abort(struct slgt_info *info)
2657{
2658 unsigned long flags;
2659 DBGINFO(("%s tx_abort\n", info->device_name));
2660 spin_lock_irqsave(&info->lock,flags);
2661 tdma_reset(info);
2662 spin_unlock_irqrestore(&info->lock,flags);
2663 return 0;
2664}
2665
2666static int rx_enable(struct slgt_info *info, int enable)
2667{
2668 unsigned long flags;
814dae03
PF		 2669 unsigned int rbuf_fill_level;
2670 DBGINFO(("%s rx_enable(%08x)\n", info->device_name, enable));
705b6c7b 2671 spin_lock_irqsave(&info->lock,flags);
814dae03
PF		 2672 /*
2673 * enable[31..16] = receive DMA buffer fill level
2674 * 0 = noop (leave fill level unchanged)
2675 * fill level must be multiple of 4 and <= buffer size
2676 */
2677 rbuf_fill_level = ((unsigned int)enable) >> 16;
2678 if (rbuf_fill_level) {
c68a99cd
PF		 2679 if ((rbuf_fill_level > DMABUFSIZE) || (rbuf_fill_level % 4)) {
2680 spin_unlock_irqrestore(&info->lock, flags);
814dae03 2681 return -EINVAL;
c68a99cd 2682 }
814dae03 2683 info->rbuf_fill_level = rbuf_fill_level;
5ba5a5d2
PF		 2684 if (rbuf_fill_level < 128)
2685 info->rx_pio = 1; /* PIO mode */
2686 else
2687 info->rx_pio = 0; /* DMA mode */
814dae03
PF		 2688 rx_stop(info); /* restart receiver to use new fill level */
2689 }
2690
2691 /*
2692 * enable[1..0] = receiver enable command
2693 * 0 = disable
2694 * 1 = enable
2695 * 2 = enable or force hunt mode if already enabled
2696 */
2697 enable &= 3;
705b6c7b
PF		 2698 if (enable) {
2699 if (!info->rx_enabled)
2700 rx_start(info);
cb10dc9a
PF		 2701 else if (enable == 2) {
2702 /* force hunt mode (write 1 to RCR[3]) */
2703 wr_reg16(info, RCR, rd_reg16(info, RCR) | BIT3);
2704 }
705b6c7b
PF		 2705 } else {
2706 if (info->rx_enabled)
2707 rx_stop(info);
2708 }
2709 spin_unlock_irqrestore(&info->lock,flags);
2710 return 0;
2711}
2712
2713/*
2714 * wait for specified event to occur
2715 */
2716static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr)
2717{
2718 unsigned long flags;
2719 int s;
2720 int rc=0;
2721 struct mgsl_icount cprev, cnow;
2722 int events;
2723 int mask;
2724 struct _input_signal_events oldsigs, newsigs;
2725 DECLARE_WAITQUEUE(wait, current);
2726
2727 if (get_user(mask, mask_ptr))
2728 return -EFAULT;
2729
2730 DBGINFO(("%s wait_mgsl_event(%d)\n", info->device_name, mask));
2731
2732 spin_lock_irqsave(&info->lock,flags);
2733
2734 /* return immediately if state matches requested events */
2735 get_signals(info);
2736 s = info->signals;
2737
2738 events = mask &
2739 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
2740 ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
2741 ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
2742 ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
2743 if (events) {
2744 spin_unlock_irqrestore(&info->lock,flags);
2745 goto exit;
2746 }
2747
2748 /* save current irq counts */
2749 cprev = info->icount;
2750 oldsigs = info->input_signal_events;
2751
2752 /* enable hunt and idle irqs if needed */
2753 if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
2754 unsigned short val = rd_reg16(info, SCR);
2755 if (!(val & IRQ_RXIDLE))
2756 wr_reg16(info, SCR, (unsigned short)(val | IRQ_RXIDLE));
2757 }
2758
2759 set_current_state(TASK_INTERRUPTIBLE);
2760 add_wait_queue(&info->event_wait_q, &wait);
2761
2762 spin_unlock_irqrestore(&info->lock,flags);
2763
2764 for(;;) {
2765 schedule();
2766 if (signal_pending(current)) {
2767 rc = -ERESTARTSYS;
2768 break;
2769 }
2770
2771 /* get current irq counts */
2772 spin_lock_irqsave(&info->lock,flags);
2773 cnow = info->icount;
2774 newsigs = info->input_signal_events;
2775 set_current_state(TASK_INTERRUPTIBLE);
2776 spin_unlock_irqrestore(&info->lock,flags);
2777
2778 /* if no change, wait aborted for some reason */
2779 if (newsigs.dsr_up == oldsigs.dsr_up &&
2780 newsigs.dsr_down == oldsigs.dsr_down &&
2781 newsigs.dcd_up == oldsigs.dcd_up &&
2782 newsigs.dcd_down == oldsigs.dcd_down &&
2783 newsigs.cts_up == oldsigs.cts_up &&
2784 newsigs.cts_down == oldsigs.cts_down &&
2785 newsigs.ri_up == oldsigs.ri_up &&
2786 newsigs.ri_down == oldsigs.ri_down &&
2787 cnow.exithunt == cprev.exithunt &&
2788 cnow.rxidle == cprev.rxidle) {
2789 rc = -EIO;
2790 break;
2791 }
2792
2793 events = mask &
2794 ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
2795 (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
2796 (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
2797 (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
2798 (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
2799 (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
2800 (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
2801 (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
2802 (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
2803 (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
2804 if (events)
2805 break;
2806
2807 cprev = cnow;
2808 oldsigs = newsigs;
2809 }
2810
2811 remove_wait_queue(&info->event_wait_q, &wait);
2812 set_current_state(TASK_RUNNING);
2813
2814
2815 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2816 spin_lock_irqsave(&info->lock,flags);
2817 if (!waitqueue_active(&info->event_wait_q)) {
2818 /* disable enable exit hunt mode/idle rcvd IRQs */
2819 wr_reg16(info, SCR,
2820 (unsigned short)(rd_reg16(info, SCR) & ~IRQ_RXIDLE));
2821 }
2822 spin_unlock_irqrestore(&info->lock,flags);
2823 }
2824exit:
2825 if (rc == 0)
2826 rc = put_user(events, mask_ptr);
2827 return rc;
2828}
2829
2830static int get_interface(struct slgt_info *info, int __user *if_mode)
2831{
2832 DBGINFO(("%s get_interface=%x\n", info->device_name, info->if_mode));
2833 if (put_user(info->if_mode, if_mode))
2834 return -EFAULT;
2835 return 0;
2836}
2837
2838static int set_interface(struct slgt_info *info, int if_mode)
2839{
2840 unsigned long flags;
35fbd397 2841 unsigned short val;
705b6c7b
PF		 2842
2843 DBGINFO(("%s set_interface=%x)\n", info->device_name, if_mode));
2844 spin_lock_irqsave(&info->lock,flags);
2845 info->if_mode = if_mode;
2846
2847 msc_set_vcr(info);
2848
2849 /* TCR (tx control) 07 1=RTS driver control */
2850 val = rd_reg16(info, TCR);
2851 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
2852 val |= BIT7;
2853 else
2854 val &= ~BIT7;
2855 wr_reg16(info, TCR, val);
2856
2857 spin_unlock_irqrestore(&info->lock,flags);
2858 return 0;
2859}
2860
9807224f
PF		 2861static int get_xsync(struct slgt_info *info, int __user *xsync)
2862{
2863 DBGINFO(("%s get_xsync=%x\n", info->device_name, info->xsync));
2864 if (put_user(info->xsync, xsync))
2865 return -EFAULT;
2866 return 0;
2867}
2868
2869/*
2870 * set extended sync pattern (1 to 4 bytes) for extended sync mode
2871 *
2872 * sync pattern is contained in least significant bytes of value
2873 * most significant byte of sync pattern is oldest (1st sent/detected)
2874 */
2875static int set_xsync(struct slgt_info *info, int xsync)
2876{
2877 unsigned long flags;
2878
2879 DBGINFO(("%s set_xsync=%x)\n", info->device_name, xsync));
2880 spin_lock_irqsave(&info->lock, flags);
2881 info->xsync = xsync;
2882 wr_reg32(info, XSR, xsync);
2883 spin_unlock_irqrestore(&info->lock, flags);
2884 return 0;
2885}
2886
2887static int get_xctrl(struct slgt_info *info, int __user *xctrl)
2888{
2889 DBGINFO(("%s get_xctrl=%x\n", info->device_name, info->xctrl));
2890 if (put_user(info->xctrl, xctrl))
2891 return -EFAULT;
2892 return 0;
2893}
2894
2895/*
2896 * set extended control options
2897 *
2898 * xctrl[31:19] reserved, must be zero
2899 * xctrl[18:17] extended sync pattern length in bytes
2900 * 00 = 1 byte in xsr[7:0]
2901 * 01 = 2 bytes in xsr[15:0]
2902 * 10 = 3 bytes in xsr[23:0]
2903 * 11 = 4 bytes in xsr[31:0]
2904 * xctrl[16] 1 = enable terminal count, 0=disabled
2905 * xctrl[15:0] receive terminal count for fixed length packets
2906 * value is count minus one (0 = 1 byte packet)
2907 * when terminal count is reached, receiver
2908 * automatically returns to hunt mode and receive
2909 * FIFO contents are flushed to DMA buffers with
2910 * end of frame (EOF) status
2911 */
2912static int set_xctrl(struct slgt_info *info, int xctrl)
2913{
2914 unsigned long flags;
2915
2916 DBGINFO(("%s set_xctrl=%x)\n", info->device_name, xctrl));
2917 spin_lock_irqsave(&info->lock, flags);
2918 info->xctrl = xctrl;
2919 wr_reg32(info, XCR, xctrl);
2920 spin_unlock_irqrestore(&info->lock, flags);
2921 return 0;
2922}
2923
0080b7aa
PF		 2924/*
2925 * set general purpose IO pin state and direction
2926 *
2927 * user_gpio fields:
2928 * state each bit indicates a pin state
2929 * smask set bit indicates pin state to set
2930 * dir each bit indicates a pin direction (0=input, 1=output)
2931 * dmask set bit indicates pin direction to set
2932 */
2933static int set_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2934{
2935 unsigned long flags;
2936 struct gpio_desc gpio;
2937 __u32 data;
2938
2939 if (!info->gpio_present)
2940 return -EINVAL;
2941 if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2942 return -EFAULT;
2943 DBGINFO(("%s set_gpio state=%08x smask=%08x dir=%08x dmask=%08x\n",
2944 info->device_name, gpio.state, gpio.smask,
2945 gpio.dir, gpio.dmask));
2946
ffd7d6ba 2947 spin_lock_irqsave(&info->port_array[0]->lock, flags);
0080b7aa
PF		 2948 if (gpio.dmask) {
2949 data = rd_reg32(info, IODR);
2950 data |= gpio.dmask & gpio.dir;
2951 data &= ~(gpio.dmask & ~gpio.dir);
2952 wr_reg32(info, IODR, data);
2953 }
2954 if (gpio.smask) {
2955 data = rd_reg32(info, IOVR);
2956 data |= gpio.smask & gpio.state;
2957 data &= ~(gpio.smask & ~gpio.state);
2958 wr_reg32(info, IOVR, data);
2959 }
ffd7d6ba 2960 spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
0080b7aa
PF		 2961
2962 return 0;
2963}
2964
2965/*
2966 * get general purpose IO pin state and direction
2967 */
2968static int get_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2969{
2970 struct gpio_desc gpio;
2971 if (!info->gpio_present)
2972 return -EINVAL;
2973 gpio.state = rd_reg32(info, IOVR);
2974 gpio.smask = 0xffffffff;
2975 gpio.dir = rd_reg32(info, IODR);
2976 gpio.dmask = 0xffffffff;
2977 if (copy_to_user(user_gpio, &gpio, sizeof(gpio)))
2978 return -EFAULT;
2979 DBGINFO(("%s get_gpio state=%08x dir=%08x\n",
2980 info->device_name, gpio.state, gpio.dir));
2981 return 0;
2982}
2983
2984/*
2985 * conditional wait facility
2986 */
2987static void init_cond_wait(struct cond_wait *w, unsigned int data)
2988{
2989 init_waitqueue_head(&w->q);
2990 init_waitqueue_entry(&w->wait, current);
2991 w->data = data;
2992}
2993
2994static void add_cond_wait(struct cond_wait **head, struct cond_wait *w)
2995{
2996 set_current_state(TASK_INTERRUPTIBLE);
2997 add_wait_queue(&w->q, &w->wait);
2998 w->next = *head;
2999 *head = w;
3000}
3001
3002static void remove_cond_wait(struct cond_wait **head, struct cond_wait *cw)
3003{
3004 struct cond_wait *w, *prev;
3005 remove_wait_queue(&cw->q, &cw->wait);
3006 set_current_state(TASK_RUNNING);
3007 for (w = *head, prev = NULL ; w != NULL ; prev = w, w = w->next) {
3008 if (w == cw) {
3009 if (prev != NULL)
3010 prev->next = w->next;
3011 else
3012 *head = w->next;
3013 break;
3014 }
3015 }
3016}
3017
3018static void flush_cond_wait(struct cond_wait **head)
3019{
3020 while (*head != NULL) {
3021 wake_up_interruptible(&(*head)->q);
3022 *head = (*head)->next;
3023 }
3024}
3025
3026/*
3027 * wait for general purpose I/O pin(s) to enter specified state
3028 *
3029 * user_gpio fields:
3030 * state - bit indicates target pin state
3031 * smask - set bit indicates watched pin
3032 *
3033 * The wait ends when at least one watched pin enters the specified
3034 * state. When 0 (no error) is returned, user_gpio->state is set to the
3035 * state of all GPIO pins when the wait ends.
3036 *
3037 * Note: Each pin may be a dedicated input, dedicated output, or
3038 * configurable input/output. The number and configuration of pins
3039 * varies with the specific adapter model. Only input pins (dedicated
3040 * or configured) can be monitored with this function.
3041 */
3042static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
3043{
3044 unsigned long flags;
3045 int rc = 0;
3046 struct gpio_desc gpio;
3047 struct cond_wait wait;
3048 u32 state;
3049
3050 if (!info->gpio_present)
3051 return -EINVAL;
3052 if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
3053 return -EFAULT;
3054 DBGINFO(("%s wait_gpio() state=%08x smask=%08x\n",
3055 info->device_name, gpio.state, gpio.smask));
3056 /* ignore output pins identified by set IODR bit */
3057 if ((gpio.smask &= ~rd_reg32(info, IODR)) == 0)
3058 return -EINVAL;
3059 init_cond_wait(&wait, gpio.smask);
3060
ffd7d6ba 3061 spin_lock_irqsave(&info->port_array[0]->lock, flags);
0080b7aa
PF		 3062 /* enable interrupts for watched pins */
3063 wr_reg32(info, IOER, rd_reg32(info, IOER) | gpio.smask);
3064 /* get current pin states */
3065 state = rd_reg32(info, IOVR);
3066
3067 if (gpio.smask & ~(state ^ gpio.state)) {
3068 /* already in target state */
3069 gpio.state = state;
3070 } else {
3071 /* wait for target state */
3072 add_cond_wait(&info->gpio_wait_q, &wait);
ffd7d6ba 3073 spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
0080b7aa
PF		 3074 schedule();
3075 if (signal_pending(current))
3076 rc = -ERESTARTSYS;
3077 else
3078 gpio.state = wait.data;
ffd7d6ba 3079 spin_lock_irqsave(&info->port_array[0]->lock, flags);
0080b7aa
PF		 3080 remove_cond_wait(&info->gpio_wait_q, &wait);
3081 }
3082
3083 /* disable all GPIO interrupts if no waiting processes */
3084 if (info->gpio_wait_q == NULL)
3085 wr_reg32(info, IOER, 0);
ffd7d6ba 3086 spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
0080b7aa
PF		 3087
3088 if ((rc == 0) && copy_to_user(user_gpio, &gpio, sizeof(gpio)))
3089 rc = -EFAULT;
3090 return rc;
3091}
3092
705b6c7b
PF		 3093static int modem_input_wait(struct slgt_info *info,int arg)
3094{
3095 unsigned long flags;
3096 int rc;
3097 struct mgsl_icount cprev, cnow;
3098 DECLARE_WAITQUEUE(wait, current);
3099
3100 /* save current irq counts */
3101 spin_lock_irqsave(&info->lock,flags);
3102 cprev = info->icount;
3103 add_wait_queue(&info->status_event_wait_q, &wait);
3104 set_current_state(TASK_INTERRUPTIBLE);
3105 spin_unlock_irqrestore(&info->lock,flags);
3106
3107 for(;;) {
3108 schedule();
3109 if (signal_pending(current)) {
3110 rc = -ERESTARTSYS;
3111 break;
3112 }
3113
3114 /* get new irq counts */
3115 spin_lock_irqsave(&info->lock,flags);
3116 cnow = info->icount;
3117 set_current_state(TASK_INTERRUPTIBLE);
3118 spin_unlock_irqrestore(&info->lock,flags);
3119
3120 /* if no change, wait aborted for some reason */
3121 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3122 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3123 rc = -EIO;
3124 break;
3125 }
3126
3127 /* check for change in caller specified modem input */
3128 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3129 (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3130 (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
3131 (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3132 rc = 0;
3133 break;
3134 }
3135
3136 cprev = cnow;
3137 }
3138 remove_wait_queue(&info->status_event_wait_q, &wait);
3139 set_current_state(TASK_RUNNING);
3140 return rc;
3141}
3142
3143/*
3144 * return state of serial control and status signals
3145 */
60b33c13 3146static int tiocmget(struct tty_struct *tty)
705b6c7b
PF		 3147{
3148 struct slgt_info *info = tty->driver_data;
3149 unsigned int result;
3150 unsigned long flags;
3151
3152 spin_lock_irqsave(&info->lock,flags);
3153 get_signals(info);
3154 spin_unlock_irqrestore(&info->lock,flags);
3155
3156 result = ((info->signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
3157 ((info->signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
3158 ((info->signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
3159 ((info->signals & SerialSignal_RI) ? TIOCM_RNG:0) +
3160 ((info->signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
3161 ((info->signals & SerialSignal_CTS) ? TIOCM_CTS:0);
3162
3163 DBGINFO(("%s tiocmget value=%08X\n", info->device_name, result));
3164 return result;
3165}
3166
3167/*
3168 * set modem control signals (DTR/RTS)
3169 *
3170 * cmd signal command: TIOCMBIS = set bit TIOCMBIC = clear bit
3171 * TIOCMSET = set/clear signal values
3172 * value bit mask for command
3173 */
20b9d177 3174static int tiocmset(struct tty_struct *tty,
705b6c7b
PF		 3175 unsigned int set, unsigned int clear)
3176{
3177 struct slgt_info *info = tty->driver_data;
3178 unsigned long flags;
3179
3180 DBGINFO(("%s tiocmset(%x,%x)\n", info->device_name, set, clear));
3181
3182 if (set & TIOCM_RTS)
3183 info->signals |= SerialSignal_RTS;
3184 if (set & TIOCM_DTR)
3185 info->signals |= SerialSignal_DTR;
3186 if (clear & TIOCM_RTS)
3187 info->signals &= ~SerialSignal_RTS;
3188 if (clear & TIOCM_DTR)
3189 info->signals &= ~SerialSignal_DTR;
3190
3191 spin_lock_irqsave(&info->lock,flags);
446e7687 3192 set_signals(info);
705b6c7b
PF		 3193 spin_unlock_irqrestore(&info->lock,flags);
3194 return 0;
3195}
3196
31f35939
AC		 3197static int carrier_raised(struct tty_port *port)
3198{
3199 unsigned long flags;
3200 struct slgt_info *info = container_of(port, struct slgt_info, port);
3201
3202 spin_lock_irqsave(&info->lock,flags);
446e7687 3203 get_signals(info);
31f35939
AC		 3204 spin_unlock_irqrestore(&info->lock,flags);
3205 return (info->signals & SerialSignal_DCD) ? 1 : 0;
3206}
3207
fcc8ac18 3208static void dtr_rts(struct tty_port *port, int on)
5d951fb4
AC		 3209{
3210 unsigned long flags;
3211 struct slgt_info *info = container_of(port, struct slgt_info, port);
3212
3213 spin_lock_irqsave(&info->lock,flags);
fcc8ac18 3214 if (on)
9fe8074b 3215 info->signals |= SerialSignal_RTS | SerialSignal_DTR;
fcc8ac18 3216 else
9fe8074b 3217 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
446e7687 3218 set_signals(info);
5d951fb4
AC		 3219 spin_unlock_irqrestore(&info->lock,flags);
3220}
3221
3222
705b6c7b
PF		 3223/*
3224 * block current process until the device is ready to open
3225 */
3226static int block_til_ready(struct tty_struct *tty, struct file *filp,
3227 struct slgt_info *info)
3228{
3229 DECLARE_WAITQUEUE(wait, current);
3230 int retval;
0fab6de0 3231 bool do_clocal = false;
705b6c7b 3232 unsigned long flags;
31f35939
AC		 3233 int cd;
3234 struct tty_port *port = &info->port;
705b6c7b
PF		 3235
3236 DBGINFO(("%s block_til_ready\n", tty->driver->name));
3237
18900ca6 3238 if (filp->f_flags & O_NONBLOCK || tty_io_error(tty)) {
705b6c7b 3239 /* nonblock mode is set or port is not enabled */
807c8d81 3240 tty_port_set_active(port, 1);
705b6c7b
PF		 3241 return 0;
3242 }
3243
9db276f8 3244 if (C_CLOCAL(tty))
0fab6de0 3245 do_clocal = true;
705b6c7b
PF		 3246
3247 /* Wait for carrier detect and the line to become
3248 * free (i.e., not in use by the callout). While we are in
31f35939 3249 * this loop, port->count is dropped by one, so that
705b6c7b
PF		 3250 * close() knows when to free things. We restore it upon
3251 * exit, either normal or abnormal.
3252 */
3253
3254 retval = 0;
31f35939 3255 add_wait_queue(&port->open_wait, &wait);
705b6c7b
PF		 3256
3257 spin_lock_irqsave(&info->lock, flags);
e359a4e3 3258 port->count--;
705b6c7b 3259 spin_unlock_irqrestore(&info->lock, flags);
31f35939 3260 port->blocked_open++;
705b6c7b
PF		 3261
3262 while (1) {
d41861ca 3263 if (C_BAUD(tty) && tty_port_initialized(port))
5d951fb4 3264 tty_port_raise_dtr_rts(port);
705b6c7b
PF		 3265
3266 set_current_state(TASK_INTERRUPTIBLE);
3267
d41861ca 3268 if (tty_hung_up_p(filp) || !tty_port_initialized(port)) {
31f35939 3269 retval = (port->flags & ASYNC_HUP_NOTIFY) ?
705b6c7b
PF		 3270 -EAGAIN : -ERESTARTSYS;
3271 break;
3272 }
3273
31f35939 3274 cd = tty_port_carrier_raised(port);
fef062cb
PH		 3275 if (do_clocal || cd)
3276 break;
705b6c7b
PF		 3277
3278 if (signal_pending(current)) {
3279 retval = -ERESTARTSYS;
3280 break;
3281 }
3282
3283 DBGINFO(("%s block_til_ready wait\n", tty->driver->name));
89c8d91e 3284 tty_unlock(tty);
705b6c7b 3285 schedule();
89c8d91e 3286 tty_lock(tty);
705b6c7b
PF		 3287 }
3288
3289 set_current_state(TASK_RUNNING);
31f35939 3290 remove_wait_queue(&port->open_wait, &wait);
705b6c7b 3291
e359a4e3 3292 if (!tty_hung_up_p(filp))
31f35939
AC		 3293 port->count++;
3294 port->blocked_open--;
705b6c7b
PF		 3295
3296 if (!retval)
807c8d81 3297 tty_port_set_active(port, 1);
705b6c7b
PF		 3298
3299 DBGINFO(("%s block_til_ready ready, rc=%d\n", tty->driver->name, retval));
3300 return retval;
3301}
3302
a6b68a69
PF		 3303/*
3304 * allocate buffers used for calling line discipline receive_buf
3305 * directly in synchronous mode
3306 * note: add 5 bytes to max frame size to allow appending
3307 * 32-bit CRC and status byte when configured to do so
3308 */
705b6c7b
PF		 3309static int alloc_tmp_rbuf(struct slgt_info *info)
3310{
04b374d0 3311 info->tmp_rbuf = kmalloc(info->max_frame_size + 5, GFP_KERNEL);
705b6c7b
PF		 3312 if (info->tmp_rbuf == NULL)
3313 return -ENOMEM;
a6b68a69
PF		 3314 /* unused flag buffer to satisfy receive_buf calling interface */
3315 info->flag_buf = kzalloc(info->max_frame_size + 5, GFP_KERNEL);
3316 if (!info->flag_buf) {
3317 kfree(info->tmp_rbuf);
3318 info->tmp_rbuf = NULL;
3319 return -ENOMEM;
3320 }
705b6c7b
PF		 3321 return 0;
3322}
3323
3324static void free_tmp_rbuf(struct slgt_info *info)
3325{
3326 kfree(info->tmp_rbuf);
3327 info->tmp_rbuf = NULL;
a6b68a69
PF		 3328 kfree(info->flag_buf);
3329 info->flag_buf = NULL;
705b6c7b
PF		 3330}
3331
3332/*
3333 * allocate DMA descriptor lists.
3334 */
3335static int alloc_desc(struct slgt_info *info)
3336{
3337 unsigned int i;
3338 unsigned int pbufs;
3339
3340 /* allocate memory to hold descriptor lists */
68778cab
CJ		 3341 info->bufs = dma_alloc_coherent(&info->pdev->dev, DESC_LIST_SIZE,
3342 &info->bufs_dma_addr, GFP_KERNEL);
705b6c7b
PF		 3343 if (info->bufs == NULL)
3344 return -ENOMEM;
3345
705b6c7b
PF		 3346 info->rbufs = (struct slgt_desc*)info->bufs;
3347 info->tbufs = ((struct slgt_desc*)info->bufs) + info->rbuf_count;
3348
3349 pbufs = (unsigned int)info->bufs_dma_addr;
3350
3351 /*
3352 * Build circular lists of descriptors
3353 */
3354
3355 for (i=0; i < info->rbuf_count; i++) {
3356 /* physical address of this descriptor */
3357 info->rbufs[i].pdesc = pbufs + (i * sizeof(struct slgt_desc));
3358
3359 /* physical address of next descriptor */
3360 if (i == info->rbuf_count - 1)
3361 info->rbufs[i].next = cpu_to_le32(pbufs);
3362 else
3363 info->rbufs[i].next = cpu_to_le32(pbufs + ((i+1) * sizeof(struct slgt_desc)));
3364 set_desc_count(info->rbufs[i], DMABUFSIZE);
3365 }
3366
3367 for (i=0; i < info->tbuf_count; i++) {
3368 /* physical address of this descriptor */
3369 info->tbufs[i].pdesc = pbufs + ((info->rbuf_count + i) * sizeof(struct slgt_desc));
3370
3371 /* physical address of next descriptor */
3372 if (i == info->tbuf_count - 1)
3373 info->tbufs[i].next = cpu_to_le32(pbufs + info->rbuf_count * sizeof(struct slgt_desc));
3374 else
3375 info->tbufs[i].next = cpu_to_le32(pbufs + ((info->rbuf_count + i + 1) * sizeof(struct slgt_desc)));
3376 }
3377
3378 return 0;
3379}
3380
3381static void free_desc(struct slgt_info *info)
3382{
3383 if (info->bufs != NULL) {
68778cab
CJ		 3384 dma_free_coherent(&info->pdev->dev, DESC_LIST_SIZE,
3385 info->bufs, info->bufs_dma_addr);
705b6c7b
PF		 3386 info->bufs = NULL;
3387 info->rbufs = NULL;
3388 info->tbufs = NULL;
3389 }
3390}
3391
3392static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3393{
3394 int i;
3395 for (i=0; i < count; i++) {
68778cab
CJ		 3396 bufs[i].buf = dma_alloc_coherent(&info->pdev->dev, DMABUFSIZE,
3397 &bufs[i].buf_dma_addr, GFP_KERNEL);
3398 if (!bufs[i].buf)
705b6c7b
PF		 3399 return -ENOMEM;
3400 bufs[i].pbuf = cpu_to_le32((unsigned int)bufs[i].buf_dma_addr);
3401 }
3402 return 0;
3403}
3404
3405static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3406{
3407 int i;
3408 for (i=0; i < count; i++) {
3409 if (bufs[i].buf == NULL)
3410 continue;
68778cab
CJ		 3411 dma_free_coherent(&info->pdev->dev, DMABUFSIZE, bufs[i].buf,
3412 bufs[i].buf_dma_addr);
705b6c7b
PF		 3413 bufs[i].buf = NULL;
3414 }
3415}
3416
3417static int alloc_dma_bufs(struct slgt_info *info)
3418{
3419 info->rbuf_count = 32;
3420 info->tbuf_count = 32;
3421
3422 if (alloc_desc(info) < 0 ||
3423 alloc_bufs(info, info->rbufs, info->rbuf_count) < 0 ||
3424 alloc_bufs(info, info->tbufs, info->tbuf_count) < 0 ||
3425 alloc_tmp_rbuf(info) < 0) {
3426 DBGERR(("%s DMA buffer alloc fail\n", info->device_name));
3427 return -ENOMEM;
3428 }
3429 reset_rbufs(info);
3430 return 0;
3431}
3432
3433static void free_dma_bufs(struct slgt_info *info)
3434{
3435 if (info->bufs) {
3436 free_bufs(info, info->rbufs, info->rbuf_count);
3437 free_bufs(info, info->tbufs, info->tbuf_count);
3438 free_desc(info);
3439 }
3440 free_tmp_rbuf(info);
3441}
3442
3443static int claim_resources(struct slgt_info *info)
3444{
3445 if (request_mem_region(info->phys_reg_addr, SLGT_REG_SIZE, "synclink_gt") == NULL) {
3446 DBGERR(("%s reg addr conflict, addr=%08X\n",
3447 info->device_name, info->phys_reg_addr));
3448 info->init_error = DiagStatus_AddressConflict;
3449 goto errout;
3450 }
3451 else
0fab6de0 3452 info->reg_addr_requested = true;
705b6c7b 3453
4bdc0d67 3454 info->reg_addr = ioremap(info->phys_reg_addr, SLGT_REG_SIZE);
705b6c7b 3455 if (!info->reg_addr) {
25985edc 3456 DBGERR(("%s can't map device registers, addr=%08X\n",
705b6c7b
PF		 3457 info->device_name, info->phys_reg_addr));
3458 info->init_error = DiagStatus_CantAssignPciResources;
3459 goto errout;
3460 }
705b6c7b
PF		 3461 return 0;
3462
3463errout:
3464 release_resources(info);
3465 return -ENODEV;
3466}
3467
3468static void release_resources(struct slgt_info *info)
3469{
3470 if (info->irq_requested) {
3471 free_irq(info->irq_level, info);
0fab6de0 3472 info->irq_requested = false;
705b6c7b
PF		 3473 }
3474
3475 if (info->reg_addr_requested) {
3476 release_mem_region(info->phys_reg_addr, SLGT_REG_SIZE);
0fab6de0 3477 info->reg_addr_requested = false;
705b6c7b
PF		 3478 }
3479
3480 if (info->reg_addr) {
0c8365ec 3481 iounmap(info->reg_addr);
705b6c7b
PF		 3482 info->reg_addr = NULL;
3483 }
3484}
3485
3486/* Add the specified device instance data structure to the
3487 * global linked list of devices and increment the device count.
3488 */
3489static void add_device(struct slgt_info *info)
3490{
3491 char *devstr;
3492
3493 info->next_device = NULL;
3494 info->line = slgt_device_count;
3495 sprintf(info->device_name, "%s%d", tty_dev_prefix, info->line);
3496
3497 if (info->line < MAX_DEVICES) {
3498 if (maxframe[info->line])
3499 info->max_frame_size = maxframe[info->line];
705b6c7b
PF		 3500 }
3501
3502 slgt_device_count++;
3503
3504 if (!slgt_device_list)
3505 slgt_device_list = info;
3506 else {
3507 struct slgt_info *current_dev = slgt_device_list;
3508 while(current_dev->next_device)
3509 current_dev = current_dev->next_device;
3510 current_dev->next_device = info;
3511 }
3512
3513 if (info->max_frame_size < 4096)
3514 info->max_frame_size = 4096;
3515 else if (info->max_frame_size > 65535)
3516 info->max_frame_size = 65535;
3517
3518 switch(info->pdev->device) {
3519 case SYNCLINK_GT_DEVICE_ID:
3520 devstr = "GT";
3521 break;
6f84be84
PF		 3522 case SYNCLINK_GT2_DEVICE_ID:
3523 devstr = "GT2";
3524 break;
705b6c7b
PF		 3525 case SYNCLINK_GT4_DEVICE_ID:
3526 devstr = "GT4";
3527 break;
3528 case SYNCLINK_AC_DEVICE_ID:
3529 devstr = "AC";
3530 info->params.mode = MGSL_MODE_ASYNC;
3531 break;
3532 default:
3533 devstr = "(unknown model)";
3534 }
3535 printk("SyncLink %s %s IO=%08x IRQ=%d MaxFrameSize=%u\n",
3536 devstr, info->device_name, info->phys_reg_addr,
3537 info->irq_level, info->max_frame_size);
3538
af69c7f9 3539#if SYNCLINK_GENERIC_HDLC
705b6c7b
PF		 3540 hdlcdev_init(info);
3541#endif
3542}
3543
31f35939
AC		 3544static const struct tty_port_operations slgt_port_ops = {
3545 .carrier_raised = carrier_raised,
fcc8ac18 3546 .dtr_rts = dtr_rts,
31f35939
AC		 3547};
3548
705b6c7b
PF		 3549/*
3550 * allocate device instance structure, return NULL on failure
3551 */
3552static struct slgt_info *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3553{
3554 struct slgt_info *info;
3555
dd00cc48 3556 info = kzalloc(sizeof(struct slgt_info), GFP_KERNEL);
705b6c7b
PF		 3557
3558 if (!info) {
3559 DBGERR(("%s device alloc failed adapter=%d port=%d\n",
3560 driver_name, adapter_num, port_num));
3561 } else {
44b7d1b3 3562 tty_port_init(&info->port);
31f35939 3563 info->port.ops = &slgt_port_ops;
705b6c7b 3564 info->magic = MGSL_MAGIC;
c4028958 3565 INIT_WORK(&info->task, bh_handler);
705b6c7b 3566 info->max_frame_size = 4096;
1f80769f 3567 info->base_clock = 14745600;
814dae03 3568 info->rbuf_fill_level = DMABUFSIZE;
44b7d1b3
AC		 3569 info->port.close_delay = 5*HZ/10;
3570 info->port.closing_wait = 30*HZ;
705b6c7b
PF		 3571 init_waitqueue_head(&info->status_event_wait_q);
3572 init_waitqueue_head(&info->event_wait_q);
3573 spin_lock_init(&info->netlock);
3574 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3575 info->idle_mode = HDLC_TXIDLE_FLAGS;
3576 info->adapter_num = adapter_num;
3577 info->port_num = port_num;
3578
e99e88a9
KC		 3579 timer_setup(&info->tx_timer, tx_timeout, 0);
3580 timer_setup(&info->rx_timer, rx_timeout, 0);
705b6c7b
PF		 3581
3582 /* Copy configuration info to device instance data */
3583 info->pdev = pdev;
3584 info->irq_level = pdev->irq;
3585 info->phys_reg_addr = pci_resource_start(pdev,0);
3586
705b6c7b 3587 info->bus_type = MGSL_BUS_TYPE_PCI;
0f2ed4c6 3588 info->irq_flags = IRQF_SHARED;
705b6c7b
PF		 3589
3590 info->init_error = -1; /* assume error, set to 0 on successful init */
3591 }
3592
3593 return info;
3594}
3595
3596static void device_init(int adapter_num, struct pci_dev *pdev)
3597{
3598 struct slgt_info *port_array[SLGT_MAX_PORTS];
3599 int i;
3600 int port_count = 1;
3601
6f84be84
PF		 3602 if (pdev->device == SYNCLINK_GT2_DEVICE_ID)
3603 port_count = 2;
3604 else if (pdev->device == SYNCLINK_GT4_DEVICE_ID)
705b6c7b
PF		 3605 port_count = 4;
3606
3607 /* allocate device instances for all ports */
3608 for (i=0; i < port_count; ++i) {
3609 port_array[i] = alloc_dev(adapter_num, i, pdev);
3610 if (port_array[i] == NULL) {
191c5f10
JS		 3611 for (--i; i >= 0; --i) {
3612 tty_port_destroy(&port_array[i]->port);
705b6c7b 3613 kfree(port_array[i]);
191c5f10 3614 }
705b6c7b
PF		 3615 return;
3616 }
3617 }
3618
3619 /* give copy of port_array to all ports and add to device list */
3620 for (i=0; i < port_count; ++i) {
3621 memcpy(port_array[i]->port_array, port_array, sizeof(port_array));
3622 add_device(port_array[i]);
3623 port_array[i]->port_count = port_count;
3624 spin_lock_init(&port_array[i]->lock);
3625 }
3626
3627 /* Allocate and claim adapter resources */
3628 if (!claim_resources(port_array[0])) {
3629
3630 alloc_dma_bufs(port_array[0]);
3631
3632 /* copy resource information from first port to others */
3633 for (i = 1; i < port_count; ++i) {
705b6c7b
PF		 3634 port_array[i]->irq_level = port_array[0]->irq_level;
3635 port_array[i]->reg_addr = port_array[0]->reg_addr;
3636 alloc_dma_bufs(port_array[i]);
3637 }
3638
3639 if (request_irq(port_array[0]->irq_level,
3640 slgt_interrupt,
3641 port_array[0]->irq_flags,
3642 port_array[0]->device_name,
3643 port_array[0]) < 0) {
3644 DBGERR(("%s request_irq failed IRQ=%d\n",
3645 port_array[0]->device_name,
3646 port_array[0]->irq_level));
3647 } else {
0fab6de0 3648 port_array[0]->irq_requested = true;
705b6c7b 3649 adapter_test(port_array[0]);
0080b7aa 3650 for (i=1 ; i < port_count ; i++) {
705b6c7b 3651 port_array[i]->init_error = port_array[0]->init_error;
0080b7aa
PF		 3652 port_array[i]->gpio_present = port_array[0]->gpio_present;
3653 }
705b6c7b
PF		 3654 }
3655 }
62eb5b1f 3656
734cc178
JS		 3657 for (i = 0; i < port_count; ++i) {
3658 struct slgt_info *info = port_array[i];
3659 tty_port_register_device(&info->port, serial_driver, info->line,
3660 &info->pdev->dev);
3661 }
705b6c7b
PF		 3662}
3663
9671f099 3664static int init_one(struct pci_dev *dev,
705b6c7b
PF		 3665 const struct pci_device_id *ent)
3666{
3667 if (pci_enable_device(dev)) {
3668 printk("error enabling pci device %p\n", dev);
3669 return -EIO;
3670 }
3671 pci_set_master(dev);
3672 device_init(slgt_device_count, dev);
3673 return 0;
3674}
3675
ae8d8a14 3676static void remove_one(struct pci_dev *dev)
705b6c7b
PF		 3677{
3678}
3679
b68e31d0 3680static const struct tty_operations ops = {
705b6c7b
PF		 3681 .open = open,
3682 .close = close,
3683 .write = write,
3684 .put_char = put_char,
3685 .flush_chars = flush_chars,
3686 .write_room = write_room,
3687 .chars_in_buffer = chars_in_buffer,
3688 .flush_buffer = flush_buffer,
3689 .ioctl = ioctl,
2acdb169 3690 .compat_ioctl = slgt_compat_ioctl,
705b6c7b
PF		 3691 .throttle = throttle,
3692 .unthrottle = unthrottle,
3693 .send_xchar = send_xchar,
3694 .break_ctl = set_break,
3695 .wait_until_sent = wait_until_sent,
705b6c7b
PF		 3696 .set_termios = set_termios,
3697 .stop = tx_hold,
3698 .start = tx_release,
3699 .hangup = hangup,
3700 .tiocmget = tiocmget,
3701 .tiocmset = tiocmset,
0587102c 3702 .get_icount = get_icount,
8a8dcabf 3703 .proc_show = synclink_gt_proc_show,
705b6c7b
PF		 3704};
3705
3706static void slgt_cleanup(void)
3707{
705b6c7b
PF		 3708 struct slgt_info *info;
3709 struct slgt_info *tmp;
3710
a6b2f87b 3711 printk(KERN_INFO "unload %s\n", driver_name);
705b6c7b
PF		 3712
3713 if (serial_driver) {
62eb5b1f
PF		 3714 for (info=slgt_device_list ; info != NULL ; info=info->next_device)
3715 tty_unregister_device(serial_driver, info->line);
6c2e6317 3716 tty_unregister_driver(serial_driver);
705b6c7b
PF		 3717 put_tty_driver(serial_driver);
3718 }
3719
3720 /* reset devices */
3721 info = slgt_device_list;
3722 while(info) {
3723 reset_port(info);
3724 info = info->next_device;
3725 }
3726
3727 /* release devices */
3728 info = slgt_device_list;
3729 while(info) {
af69c7f9 3730#if SYNCLINK_GENERIC_HDLC
705b6c7b
PF		 3731 hdlcdev_exit(info);
3732#endif
3733 free_dma_bufs(info);
3734 free_tmp_rbuf(info);
3735 if (info->port_num == 0)
3736 release_resources(info);
3737 tmp = info;
3738 info = info->next_device;
191c5f10 3739 tty_port_destroy(&tmp->port);
705b6c7b
PF		 3740 kfree(tmp);
3741 }
3742
3743 if (pci_registered)
3744 pci_unregister_driver(&pci_driver);
3745}
3746
3747/*
3748 * Driver initialization entry point.
3749 */
3750static int __init slgt_init(void)
3751{
3752 int rc;
3753
a6b2f87b 3754 printk(KERN_INFO "%s\n", driver_name);
705b6c7b 3755
705b6c7b
PF		 3756 serial_driver = alloc_tty_driver(MAX_DEVICES);
3757 if (!serial_driver) {
62eb5b1f
PF		 3758 printk("%s can't allocate tty driver\n", driver_name);
3759 return -ENOMEM;
705b6c7b
PF		 3760 }
3761
3762 /* Initialize the tty_driver structure */
3763
076fe303 3764 serial_driver->driver_name = slgt_driver_name;
705b6c7b
PF		 3765 serial_driver->name = tty_dev_prefix;
3766 serial_driver->major = ttymajor;
3767 serial_driver->minor_start = 64;
3768 serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
3769 serial_driver->subtype = SERIAL_TYPE_NORMAL;
3770 serial_driver->init_termios = tty_std_termios;
3771 serial_driver->init_termios.c_cflag =
3772 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
606d099c
AC		 3773 serial_driver->init_termios.c_ispeed = 9600;
3774 serial_driver->init_termios.c_ospeed = 9600;
62eb5b1f 3775 serial_driver->flags = TTY_DRIVER_REAL_RAW | TTY_DRIVER_DYNAMIC_DEV;
705b6c7b
PF		 3776 tty_set_operations(serial_driver, &ops);
3777 if ((rc = tty_register_driver(serial_driver)) < 0) {
3778 DBGERR(("%s can't register serial driver\n", driver_name));
3779 put_tty_driver(serial_driver);
3780 serial_driver = NULL;
3781 goto error;
3782 }
3783
a6b2f87b
PF		 3784 printk(KERN_INFO "%s, tty major#%d\n",
3785 driver_name, serial_driver->major);
705b6c7b 3786
62eb5b1f
PF		 3787 slgt_device_count = 0;
3788 if ((rc = pci_register_driver(&pci_driver)) < 0) {
3789 printk("%s pci_register_driver error=%d\n", driver_name, rc);
3790 goto error;
3791 }
0fab6de0 3792 pci_registered = true;
62eb5b1f
PF		 3793
3794 if (!slgt_device_list)
3795 printk("%s no devices found\n",driver_name);
3796
705b6c7b
PF		 3797 return 0;
3798
3799error:
3800 slgt_cleanup();
3801 return rc;
3802}
3803
3804static void __exit slgt_exit(void)
3805{
3806 slgt_cleanup();
3807}
3808
3809module_init(slgt_init);
3810module_exit(slgt_exit);
3811
3812/*
3813 * register access routines
3814 */
3815
3816#define CALC_REGADDR() \
3817 unsigned long reg_addr = ((unsigned long)info->reg_addr) + addr; \
3818 if (addr >= 0x80) \
9807224f
PF		 3819 reg_addr += (info->port_num) * 32; \
3820 else if (addr >= 0x40) \
3821 reg_addr += (info->port_num) * 16;
705b6c7b
PF		 3822
3823static __u8 rd_reg8(struct slgt_info *info, unsigned int addr)
3824{
3825 CALC_REGADDR();
3826 return readb((void __iomem *)reg_addr);
3827}
3828
3829static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value)
3830{
3831 CALC_REGADDR();
3832 writeb(value, (void __iomem *)reg_addr);
3833}
3834
3835static __u16 rd_reg16(struct slgt_info *info, unsigned int addr)
3836{
3837 CALC_REGADDR();
3838 return readw((void __iomem *)reg_addr);
3839}
3840
3841static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value)
3842{
3843 CALC_REGADDR();
3844 writew(value, (void __iomem *)reg_addr);
3845}
3846
3847static __u32 rd_reg32(struct slgt_info *info, unsigned int addr)
3848{
3849 CALC_REGADDR();
3850 return readl((void __iomem *)reg_addr);
3851}
3852
3853static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value)
3854{
3855 CALC_REGADDR();
3856 writel(value, (void __iomem *)reg_addr);
3857}
3858
3859static void rdma_reset(struct slgt_info *info)
3860{
3861 unsigned int i;
3862
3863 /* set reset bit */
3864 wr_reg32(info, RDCSR, BIT1);
3865
3866 /* wait for enable bit cleared */
3867 for(i=0 ; i < 1000 ; i++)
3868 if (!(rd_reg32(info, RDCSR) & BIT0))
3869 break;
3870}
3871
3872static void tdma_reset(struct slgt_info *info)
3873{
3874 unsigned int i;
3875
3876 /* set reset bit */
3877 wr_reg32(info, TDCSR, BIT1);
3878
3879 /* wait for enable bit cleared */
3880 for(i=0 ; i < 1000 ; i++)
3881 if (!(rd_reg32(info, TDCSR) & BIT0))
3882 break;
3883}
3884
3885/*
3886 * enable internal loopback
3887 * TxCLK and RxCLK are generated from BRG
3888 * and TxD is looped back to RxD internally.
3889 */
3890static void enable_loopback(struct slgt_info *info)
3891{
5980c001 3892 /* SCR (serial control) BIT2=loopback enable */
705b6c7b
PF		 3893 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT2));
3894
3895 if (info->params.mode != MGSL_MODE_ASYNC) {
3896 /* CCR (clock control)
3897 * 07..05 tx clock source (010 = BRG)
3898 * 04..02 rx clock source (010 = BRG)
3899 * 01 auxclk enable (0 = disable)
3900 * 00 BRG enable (1 = enable)
3901 *
3902 * 0100 1001
3903 */
3904 wr_reg8(info, CCR, 0x49);
3905
3906 /* set speed if available, otherwise use default */
3907 if (info->params.clock_speed)
3908 set_rate(info, info->params.clock_speed);
3909 else
3910 set_rate(info, 3686400);
3911 }
3912}
3913
3914/*
3915 * set baud rate generator to specified rate
3916 */
3917static void set_rate(struct slgt_info *info, u32 rate)
3918{
3919 unsigned int div;
1f80769f 3920 unsigned int osc = info->base_clock;
705b6c7b
PF		 3921
3922 /* div = osc/rate - 1
3923 *
3924 * Round div up if osc/rate is not integer to
3925 * force to next slowest rate.
3926 */
3927
3928 if (rate) {
3929 div = osc/rate;
3930 if (!(osc % rate) && div)
3931 div--;
3932 wr_reg16(info, BDR, (unsigned short)div);
3933 }
3934}
3935
3936static void rx_stop(struct slgt_info *info)
3937{
3938 unsigned short val;
3939
3940 /* disable and reset receiver */
3941 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3942 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3943 wr_reg16(info, RCR, val); /* clear reset bit */
3944
3945 slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA + IRQ_RXIDLE);
3946
3947 /* clear pending rx interrupts */
3948 wr_reg16(info, SSR, IRQ_RXIDLE + IRQ_RXOVER);
3949
3950 rdma_reset(info);
3951
0fab6de0
JP		 3952 info->rx_enabled = false;
3953 info->rx_restart = false;
705b6c7b
PF		 3954}
3955
3956static void rx_start(struct slgt_info *info)
3957{
3958 unsigned short val;
3959
3960 slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA);
3961
3962 /* clear pending rx overrun IRQ */
3963 wr_reg16(info, SSR, IRQ_RXOVER);
3964
3965 /* reset and disable receiver */
3966 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3967 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3968 wr_reg16(info, RCR, val); /* clear reset bit */
3969
3970 rdma_reset(info);
3971 reset_rbufs(info);
3972
5ba5a5d2
PF		 3973 if (info->rx_pio) {
3974 /* rx request when rx FIFO not empty */
3975 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) & ~BIT14));
3976 slgt_irq_on(info, IRQ_RXDATA);
3977 if (info->params.mode == MGSL_MODE_ASYNC) {
3978 /* enable saving of rx status */
3979 wr_reg32(info, RDCSR, BIT6);
3980 }
705b6c7b 3981 } else {
5ba5a5d2
PF		 3982 /* rx request when rx FIFO half full */
3983 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT14));
3984 /* set 1st descriptor address */
3985 wr_reg32(info, RDDAR, info->rbufs[0].pdesc);
3986
3987 if (info->params.mode != MGSL_MODE_ASYNC) {
3988 /* enable rx DMA and DMA interrupt */
3989 wr_reg32(info, RDCSR, (BIT2 + BIT0));
3990 } else {
3991 /* enable saving of rx status, rx DMA and DMA interrupt */
3992 wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0));
3993 }
705b6c7b
PF		 3994 }
3995
3996 slgt_irq_on(info, IRQ_RXOVER);
3997
3998 /* enable receiver */
3999 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | BIT1));
4000
0fab6de0
JP		 4001 info->rx_restart = false;
4002 info->rx_enabled = true;
705b6c7b
PF		 4003}
4004
4005static void tx_start(struct slgt_info *info)
4006{
4007 if (!info->tx_enabled) {
4008 wr_reg16(info, TCR,
cb10dc9a 4009 (unsigned short)((rd_reg16(info, TCR) | BIT1) & ~BIT2));
0fab6de0 4010 info->tx_enabled = true;
705b6c7b
PF		 4011 }
4012
de538eb3 4013 if (desc_count(info->tbufs[info->tbuf_start])) {
0fab6de0 4014 info->drop_rts_on_tx_done = false;
705b6c7b
PF		 4015
4016 if (info->params.mode != MGSL_MODE_ASYNC) {
4017 if (info->params.flags & HDLC_FLAG_AUTO_RTS) {
4018 get_signals(info);
4019 if (!(info->signals & SerialSignal_RTS)) {
4020 info->signals |= SerialSignal_RTS;
4021 set_signals(info);
0fab6de0 4022 info->drop_rts_on_tx_done = true;
705b6c7b
PF		 4023 }
4024 }
4025
4026 slgt_irq_off(info, IRQ_TXDATA);
4027 slgt_irq_on(info, IRQ_TXUNDER + IRQ_TXIDLE);
4028 /* clear tx idle and underrun status bits */
4029 wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
705b6c7b 4030 } else {
705b6c7b
PF		 4031 slgt_irq_off(info, IRQ_TXDATA);
4032 slgt_irq_on(info, IRQ_TXIDLE);
4033 /* clear tx idle status bit */
4034 wr_reg16(info, SSR, IRQ_TXIDLE);
705b6c7b 4035 }
ce89294c
PF		 4036 /* set 1st descriptor address and start DMA */
4037 wr_reg32(info, TDDAR, info->tbufs[info->tbuf_start].pdesc);
4038 wr_reg32(info, TDCSR, BIT2 + BIT0);
0fab6de0 4039 info->tx_active = true;
705b6c7b
PF		 4040 }
4041}
4042
4043static void tx_stop(struct slgt_info *info)
4044{
4045 unsigned short val;
4046
4047 del_timer(&info->tx_timer);
4048
4049 tdma_reset(info);
4050
4051 /* reset and disable transmitter */
4052 val = rd_reg16(info, TCR) & ~BIT1; /* clear enable bit */
4053 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
705b6c7b
PF		 4054
4055 slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
4056
4057 /* clear tx idle and underrun status bit */
4058 wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
4059
4060 reset_tbufs(info);
4061
0fab6de0
JP		 4062 info->tx_enabled = false;
4063 info->tx_active = false;
705b6c7b
PF		 4064}
4065
4066static void reset_port(struct slgt_info *info)
4067{
4068 if (!info->reg_addr)
4069 return;
4070
4071 tx_stop(info);
4072 rx_stop(info);
4073
9fe8074b 4074 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
705b6c7b
PF		 4075 set_signals(info);
4076
4077 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4078}
4079
4080static void reset_adapter(struct slgt_info *info)
4081{
4082 int i;
4083 for (i=0; i < info->port_count; ++i) {
4084 if (info->port_array[i])
4085 reset_port(info->port_array[i]);
4086 }
4087}
4088
4089static void async_mode(struct slgt_info *info)
4090{
4091 unsigned short val;
4092
4093 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4094 tx_stop(info);
4095 rx_stop(info);
4096
4097 /* TCR (tx control)
4098 *
4099 * 15..13 mode, 010=async
4100 * 12..10 encoding, 000=NRZ
4101 * 09 parity enable
4102 * 08 1=odd parity, 0=even parity
4103 * 07 1=RTS driver control
4104 * 06 1=break enable
4105 * 05..04 character length
4106 * 00=5 bits
4107 * 01=6 bits
4108 * 10=7 bits
4109 * 11=8 bits
4110 * 03 0=1 stop bit, 1=2 stop bits
4111 * 02 reset
4112 * 01 enable
4113 * 00 auto-CTS enable
4114 */
4115 val = 0x4000;
4116
4117 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4118 val |= BIT7;
4119
4120 if (info->params.parity != ASYNC_PARITY_NONE) {
4121 val |= BIT9;
4122 if (info->params.parity == ASYNC_PARITY_ODD)
4123 val |= BIT8;
4124 }
4125
4126 switch (info->params.data_bits)
4127 {
4128 case 6: val |= BIT4; break;
4129 case 7: val |= BIT5; break;
4130 case 8: val |= BIT5 + BIT4; break;
4131 }
4132
4133 if (info->params.stop_bits != 1)
4134 val |= BIT3;
4135
4136 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4137 val |= BIT0;
4138
4139 wr_reg16(info, TCR, val);
4140
4141 /* RCR (rx control)
4142 *
4143 * 15..13 mode, 010=async
4144 * 12..10 encoding, 000=NRZ
4145 * 09 parity enable
4146 * 08 1=odd parity, 0=even parity
4147 * 07..06 reserved, must be 0
4148 * 05..04 character length
4149 * 00=5 bits
4150 * 01=6 bits
4151 * 10=7 bits
4152 * 11=8 bits
4153 * 03 reserved, must be zero
4154 * 02 reset
4155 * 01 enable
4156 * 00 auto-DCD enable
4157 */
4158 val = 0x4000;
4159
4160 if (info->params.parity != ASYNC_PARITY_NONE) {
4161 val |= BIT9;
4162 if (info->params.parity == ASYNC_PARITY_ODD)
4163 val |= BIT8;
4164 }
4165
4166 switch (info->params.data_bits)
4167 {
4168 case 6: val |= BIT4; break;
4169 case 7: val |= BIT5; break;
4170 case 8: val |= BIT5 + BIT4; break;
4171 }
4172
4173 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4174 val |= BIT0;
4175
4176 wr_reg16(info, RCR, val);
4177
4178 /* CCR (clock control)
4179 *
4180 * 07..05 011 = tx clock source is BRG/16
4181 * 04..02 010 = rx clock source is BRG
4182 * 01 0 = auxclk disabled
4183 * 00 1 = BRG enabled
4184 *
4185 * 0110 1001
4186 */
4187 wr_reg8(info, CCR, 0x69);
4188
4189 msc_set_vcr(info);
4190
705b6c7b
PF		 4191 /* SCR (serial control)
4192 *
4193 * 15 1=tx req on FIFO half empty
4194 * 14 1=rx req on FIFO half full
4195 * 13 tx data IRQ enable
4196 * 12 tx idle IRQ enable
4197 * 11 rx break on IRQ enable
4198 * 10 rx data IRQ enable
4199 * 09 rx break off IRQ enable
4200 * 08 overrun IRQ enable
4201 * 07 DSR IRQ enable
4202 * 06 CTS IRQ enable
4203 * 05 DCD IRQ enable
4204 * 04 RI IRQ enable
1f80769f 4205 * 03 0=16x sampling, 1=8x sampling
705b6c7b
PF		 4206 * 02 1=txd->rxd internal loopback enable
4207 * 01 reserved, must be zero
4208 * 00 1=master IRQ enable
4209 */
4210 val = BIT15 + BIT14 + BIT0;
1f80769f
PF		 4211 /* JCR[8] : 1 = x8 async mode feature available */
4212 if ((rd_reg32(info, JCR) & BIT8) && info->params.data_rate &&
4213 ((info->base_clock < (info->params.data_rate * 16)) ||
4214 (info->base_clock % (info->params.data_rate * 16)))) {
4215 /* use 8x sampling */
4216 val |= BIT3;
4217 set_rate(info, info->params.data_rate * 8);
4218 } else {
4219 /* use 16x sampling */
4220 set_rate(info, info->params.data_rate * 16);
4221 }
705b6c7b
PF		 4222 wr_reg16(info, SCR, val);
4223
4224 slgt_irq_on(info, IRQ_RXBREAK | IRQ_RXOVER);
4225
705b6c7b
PF		 4226 if (info->params.loopback)
4227 enable_loopback(info);
4228}
4229
cb10dc9a 4230static void sync_mode(struct slgt_info *info)
705b6c7b
PF		 4231{
4232 unsigned short val;
4233
4234 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4235 tx_stop(info);
4236 rx_stop(info);
4237
4238 /* TCR (tx control)
4239 *
9807224f
PF		 4240 * 15..13 mode
4241 * 000=HDLC/SDLC
4242 * 001=raw bit synchronous
4243 * 010=asynchronous/isochronous
4244 * 011=monosync byte synchronous
4245 * 100=bisync byte synchronous
4246 * 101=xsync byte synchronous
705b6c7b
PF		 4247 * 12..10 encoding
4248 * 09 CRC enable
4249 * 08 CRC32
4250 * 07 1=RTS driver control
4251 * 06 preamble enable
4252 * 05..04 preamble length
4253 * 03 share open/close flag
4254 * 02 reset
4255 * 01 enable
4256 * 00 auto-CTS enable
4257 */
993456cd 4258 val = BIT2;
705b6c7b 4259
cb10dc9a 4260 switch(info->params.mode) {
9807224f
PF		 4261 case MGSL_MODE_XSYNC:
4262 val |= BIT15 + BIT13;
4263 break;
cb10dc9a
PF		 4264 case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4265 case MGSL_MODE_BISYNC: val |= BIT15; break;
4266 case MGSL_MODE_RAW: val |= BIT13; break;
4267 }
705b6c7b
PF		 4268 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4269 val |= BIT7;
4270
4271 switch(info->params.encoding)
4272 {
4273 case HDLC_ENCODING_NRZB: val |= BIT10; break;
4274 case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break;
4275 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break;
4276 case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break;
4277 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4278 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4279 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4280 }
4281
04b374d0 4282 switch (info->params.crc_type & HDLC_CRC_MASK)
705b6c7b
PF		 4283 {
4284 case HDLC_CRC_16_CCITT: val |= BIT9; break;
4285 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4286 }
4287
4288 if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE)
4289 val |= BIT6;
4290
4291 switch (info->params.preamble_length)
4292 {
4293 case HDLC_PREAMBLE_LENGTH_16BITS: val |= BIT5; break;
4294 case HDLC_PREAMBLE_LENGTH_32BITS: val |= BIT4; break;
4295 case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; break;
4296 }
4297
4298 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4299 val |= BIT0;
4300
4301 wr_reg16(info, TCR, val);
4302
4303 /* TPR (transmit preamble) */
4304
4305 switch (info->params.preamble)
4306 {
4307 case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break;
4308 case HDLC_PREAMBLE_PATTERN_ONES: val = 0xff; break;
4309 case HDLC_PREAMBLE_PATTERN_ZEROS: val = 0x00; break;
4310 case HDLC_PREAMBLE_PATTERN_10: val = 0x55; break;
4311 case HDLC_PREAMBLE_PATTERN_01: val = 0xaa; break;
4312 default: val = 0x7e; break;
4313 }
4314 wr_reg8(info, TPR, (unsigned char)val);
4315
4316 /* RCR (rx control)
4317 *
9807224f
PF		 4318 * 15..13 mode
4319 * 000=HDLC/SDLC
4320 * 001=raw bit synchronous
4321 * 010=asynchronous/isochronous
4322 * 011=monosync byte synchronous
4323 * 100=bisync byte synchronous
4324 * 101=xsync byte synchronous
705b6c7b
PF		 4325 * 12..10 encoding
4326 * 09 CRC enable
4327 * 08 CRC32
4328 * 07..03 reserved, must be 0
4329 * 02 reset
4330 * 01 enable
4331 * 00 auto-DCD enable
4332 */
4333 val = 0;
4334
cb10dc9a 4335 switch(info->params.mode) {
9807224f
PF		 4336 case MGSL_MODE_XSYNC:
4337 val |= BIT15 + BIT13;
4338 break;
cb10dc9a
PF		 4339 case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4340 case MGSL_MODE_BISYNC: val |= BIT15; break;
4341 case MGSL_MODE_RAW: val |= BIT13; break;
4342 }
705b6c7b
PF		 4343
4344 switch(info->params.encoding)
4345 {
4346 case HDLC_ENCODING_NRZB: val |= BIT10; break;
4347 case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break;
4348 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break;
4349 case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break;
4350 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4351 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4352 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4353 }
4354
04b374d0 4355 switch (info->params.crc_type & HDLC_CRC_MASK)
705b6c7b
PF		 4356 {
4357 case HDLC_CRC_16_CCITT: val |= BIT9; break;
4358 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4359 }
4360
4361 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4362 val |= BIT0;
4363
4364 wr_reg16(info, RCR, val);
4365
4366 /* CCR (clock control)
4367 *
4368 * 07..05 tx clock source
4369 * 04..02 rx clock source
4370 * 01 auxclk enable
4371 * 00 BRG enable
4372 */
4373 val = 0;
4374
4375 if (info->params.flags & HDLC_FLAG_TXC_BRG)
4376 {
4377 // when RxC source is DPLL, BRG generates 16X DPLL
4378 // reference clock, so take TxC from BRG/16 to get
4379 // transmit clock at actual data rate
4380 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4381 val |= BIT6 + BIT5; /* 011, txclk = BRG/16 */
4382 else
4383 val |= BIT6; /* 010, txclk = BRG */
4384 }
4385 else if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4386 val |= BIT7; /* 100, txclk = DPLL Input */
4387 else if (info->params.flags & HDLC_FLAG_TXC_RXCPIN)
4388 val |= BIT5; /* 001, txclk = RXC Input */
4389
4390 if (info->params.flags & HDLC_FLAG_RXC_BRG)
4391 val |= BIT3; /* 010, rxclk = BRG */
4392 else if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4393 val |= BIT4; /* 100, rxclk = DPLL */
4394 else if (info->params.flags & HDLC_FLAG_RXC_TXCPIN)
4395 val |= BIT2; /* 001, rxclk = TXC Input */
4396
4397 if (info->params.clock_speed)
4398 val |= BIT1 + BIT0;
4399
4400 wr_reg8(info, CCR, (unsigned char)val);
4401
4402 if (info->params.flags & (HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL))
4403 {
4404 // program DPLL mode
4405 switch(info->params.encoding)
4406 {
4407 case HDLC_ENCODING_BIPHASE_MARK:
4408 case HDLC_ENCODING_BIPHASE_SPACE:
4409 val = BIT7; break;
4410 case HDLC_ENCODING_BIPHASE_LEVEL:
4411 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL:
4412 val = BIT7 + BIT6; break;
4413 default: val = BIT6; // NRZ encodings
4414 }
4415 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | val));
4416
4417 // DPLL requires a 16X reference clock from BRG
4418 set_rate(info, info->params.clock_speed * 16);
4419 }
4420 else
4421 set_rate(info, info->params.clock_speed);
4422
4423 tx_set_idle(info);
4424
4425 msc_set_vcr(info);
4426
4427 /* SCR (serial control)
4428 *
4429 * 15 1=tx req on FIFO half empty
4430 * 14 1=rx req on FIFO half full
4431 * 13 tx data IRQ enable
4432 * 12 tx idle IRQ enable
4433 * 11 underrun IRQ enable
4434 * 10 rx data IRQ enable
4435 * 09 rx idle IRQ enable
4436 * 08 overrun IRQ enable
4437 * 07 DSR IRQ enable
4438 * 06 CTS IRQ enable
4439 * 05 DCD IRQ enable
4440 * 04 RI IRQ enable
4441 * 03 reserved, must be zero
4442 * 02 1=txd->rxd internal loopback enable
4443 * 01 reserved, must be zero
4444 * 00 1=master IRQ enable
4445 */
4446 wr_reg16(info, SCR, BIT15 + BIT14 + BIT0);
4447
4448 if (info->params.loopback)
4449 enable_loopback(info);
4450}
4451
4452/*
4453 * set transmit idle mode
4454 */
4455static void tx_set_idle(struct slgt_info *info)
4456{
643f3319
PF		 4457 unsigned char val;
4458 unsigned short tcr;
705b6c7b 4459
643f3319
PF		 4460 /* if preamble enabled (tcr[6] == 1) then tx idle size = 8 bits
4461 * else tcr[5:4] = tx idle size: 00 = 8 bits, 01 = 16 bits
4462 */
4463 tcr = rd_reg16(info, TCR);
4464 if (info->idle_mode & HDLC_TXIDLE_CUSTOM_16) {
4465 /* disable preamble, set idle size to 16 bits */
4466 tcr = (tcr & ~(BIT6 + BIT5)) | BIT4;
4467 /* MSB of 16 bit idle specified in tx preamble register (TPR) */
4468 wr_reg8(info, TPR, (unsigned char)((info->idle_mode >> 8) & 0xff));
4469 } else if (!(tcr & BIT6)) {
4470 /* preamble is disabled, set idle size to 8 bits */
4471 tcr &= ~(BIT5 + BIT4);
4472 }
4473 wr_reg16(info, TCR, tcr);
4474
4475 if (info->idle_mode & (HDLC_TXIDLE_CUSTOM_8 | HDLC_TXIDLE_CUSTOM_16)) {
4476 /* LSB of custom tx idle specified in tx idle register */
4477 val = (unsigned char)(info->idle_mode & 0xff);
4478 } else {
4479 /* standard 8 bit idle patterns */
4480 switch(info->idle_mode)
4481 {
4482 case HDLC_TXIDLE_FLAGS: val = 0x7e; break;
4483 case HDLC_TXIDLE_ALT_ZEROS_ONES:
4484 case HDLC_TXIDLE_ALT_MARK_SPACE: val = 0xaa; break;
4485 case HDLC_TXIDLE_ZEROS:
4486 case HDLC_TXIDLE_SPACE: val = 0x00; break;
4487 default: val = 0xff;
4488 }
705b6c7b
PF		 4489 }
4490
4491 wr_reg8(info, TIR, val);
4492}
4493
4494/*
4495 * get state of V24 status (input) signals
4496 */
4497static void get_signals(struct slgt_info *info)
4498{
4499 unsigned short status = rd_reg16(info, SSR);
4500
9fe8074b
JP		 4501 /* clear all serial signals except RTS and DTR */
4502 info->signals &= SerialSignal_RTS | SerialSignal_DTR;
705b6c7b
PF		 4503
4504 if (status & BIT3)
4505 info->signals |= SerialSignal_DSR;
4506 if (status & BIT2)
4507 info->signals |= SerialSignal_CTS;
4508 if (status & BIT1)
4509 info->signals |= SerialSignal_DCD;
4510 if (status & BIT0)
4511 info->signals |= SerialSignal_RI;
4512}
4513
4514/*
4515 * set V.24 Control Register based on current configuration
4516 */
4517static void msc_set_vcr(struct slgt_info *info)
4518{
4519 unsigned char val = 0;
4520
4521 /* VCR (V.24 control)
4522 *
4523 * 07..04 serial IF select
4524 * 03 DTR
4525 * 02 RTS
4526 * 01 LL
4527 * 00 RL
4528 */
4529
4530 switch(info->if_mode & MGSL_INTERFACE_MASK)
4531 {
4532 case MGSL_INTERFACE_RS232:
4533 val |= BIT5; /* 0010 */
4534 break;
4535 case MGSL_INTERFACE_V35:
4536 val |= BIT7 + BIT6 + BIT5; /* 1110 */
4537 break;
4538 case MGSL_INTERFACE_RS422:
4539 val |= BIT6; /* 0100 */
4540 break;
4541 }
4542
e5590717
PF		 4543 if (info->if_mode & MGSL_INTERFACE_MSB_FIRST)
4544 val |= BIT4;
705b6c7b
PF		 4545 if (info->signals & SerialSignal_DTR)
4546 val |= BIT3;
4547 if (info->signals & SerialSignal_RTS)
4548 val |= BIT2;
4549 if (info->if_mode & MGSL_INTERFACE_LL)
4550 val |= BIT1;
4551 if (info->if_mode & MGSL_INTERFACE_RL)
4552 val |= BIT0;
4553 wr_reg8(info, VCR, val);
4554}
4555
4556/*
4557 * set state of V24 control (output) signals
4558 */
4559static void set_signals(struct slgt_info *info)
4560{
4561 unsigned char val = rd_reg8(info, VCR);
4562 if (info->signals & SerialSignal_DTR)
4563 val |= BIT3;
4564 else
4565 val &= ~BIT3;
4566 if (info->signals & SerialSignal_RTS)
4567 val |= BIT2;
4568 else
4569 val &= ~BIT2;
4570 wr_reg8(info, VCR, val);
4571}
4572
4573/*
4574 * free range of receive DMA buffers (i to last)
4575 */
4576static void free_rbufs(struct slgt_info *info, unsigned int i, unsigned int last)
4577{
4578 int done = 0;
4579
4580 while(!done) {
4581 /* reset current buffer for reuse */
4582 info->rbufs[i].status = 0;
814dae03 4583 set_desc_count(info->rbufs[i], info->rbuf_fill_level);
705b6c7b
PF		 4584 if (i == last)
4585 done = 1;
4586 if (++i == info->rbuf_count)
4587 i = 0;
4588 }
4589 info->rbuf_current = i;
4590}
4591
4592/*
4593 * mark all receive DMA buffers as free
4594 */
4595static void reset_rbufs(struct slgt_info *info)
4596{
4597 free_rbufs(info, 0, info->rbuf_count - 1);
5ba5a5d2
PF		 4598 info->rbuf_fill_index = 0;
4599 info->rbuf_fill_count = 0;
705b6c7b
PF		 4600}
4601
4602/*
4603 * pass receive HDLC frame to upper layer
4604 *
0fab6de0 4605 * return true if frame available, otherwise false
705b6c7b 4606 */
0fab6de0 4607static bool rx_get_frame(struct slgt_info *info)
705b6c7b
PF		 4608{
4609 unsigned int start, end;
4610 unsigned short status;
4611 unsigned int framesize = 0;
705b6c7b 4612 unsigned long flags;
8fb06c77 4613 struct tty_struct *tty = info->port.tty;
705b6c7b 4614 unsigned char addr_field = 0xff;
04b374d0
PF		 4615 unsigned int crc_size = 0;
4616
4617 switch (info->params.crc_type & HDLC_CRC_MASK) {
4618 case HDLC_CRC_16_CCITT: crc_size = 2; break;
4619 case HDLC_CRC_32_CCITT: crc_size = 4; break;
4620 }
705b6c7b
PF		 4621
4622check_again:
4623
4624 framesize = 0;
4625 addr_field = 0xff;
4626 start = end = info->rbuf_current;
4627
4628 for (;;) {
4629 if (!desc_complete(info->rbufs[end]))
4630 goto cleanup;
4631
4632 if (framesize == 0 && info->params.addr_filter != 0xff)
4633 addr_field = info->rbufs[end].buf[0];
4634
4635 framesize += desc_count(info->rbufs[end]);
4636
4637 if (desc_eof(info->rbufs[end]))
4638 break;
4639
4640 if (++end == info->rbuf_count)
4641 end = 0;
4642
4643 if (end == info->rbuf_current) {
4644 if (info->rx_enabled){
4645 spin_lock_irqsave(&info->lock,flags);
4646 rx_start(info);
4647 spin_unlock_irqrestore(&info->lock,flags);
4648 }
4649 goto cleanup;
4650 }
4651 }
4652
4653 /* status
4654 *
4655 * 15 buffer complete
4656 * 14..06 reserved
4657 * 05..04 residue
4658 * 02 eof (end of frame)
4659 * 01 CRC error
4660 * 00 abort
4661 */
4662 status = desc_status(info->rbufs[end]);
4663
4664 /* ignore CRC bit if not using CRC (bit is undefined) */
04b374d0 4665 if ((info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_NONE)
705b6c7b
PF		 4666 status &= ~BIT1;
4667
4668 if (framesize == 0 ||
4669 (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4670 free_rbufs(info, start, end);
4671 goto check_again;
4672 }
4673
04b374d0
PF		 4674 if (framesize < (2 + crc_size) || status & BIT0) {
4675 info->icount.rxshort++;
705b6c7b 4676 framesize = 0;
04b374d0
PF		 4677 } else if (status & BIT1) {
4678 info->icount.rxcrc++;
4679 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX))
4680 framesize = 0;
4681 }
705b6c7b 4682
af69c7f9 4683#if SYNCLINK_GENERIC_HDLC
04b374d0 4684 if (framesize == 0) {
198191c4
KH		 4685 info->netdev->stats.rx_errors++;
4686 info->netdev->stats.rx_frame_errors++;
705b6c7b 4687 }
04b374d0 4688#endif
705b6c7b
PF		 4689
4690 DBGBH(("%s rx frame status=%04X size=%d\n",
4691 info->device_name, status, framesize));
814dae03 4692 DBGDATA(info, info->rbufs[start].buf, min_t(int, framesize, info->rbuf_fill_level), "rx");
705b6c7b
PF		 4693
4694 if (framesize) {
04b374d0
PF		 4695 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX)) {
4696 framesize -= crc_size;
4697 crc_size = 0;
4698 }
4699
4700 if (framesize > info->max_frame_size + crc_size)
705b6c7b
PF		 4701 info->icount.rxlong++;
4702 else {
4703 /* copy dma buffer(s) to contiguous temp buffer */
4704 int copy_count = framesize;
4705 int i = start;
4706 unsigned char *p = info->tmp_rbuf;
4707 info->tmp_rbuf_count = framesize;
4708
4709 info->icount.rxok++;
4710
4711 while(copy_count) {
814dae03 4712 int partial_count = min_t(int, copy_count, info->rbuf_fill_level);
705b6c7b
PF		 4713 memcpy(p, info->rbufs[i].buf, partial_count);
4714 p += partial_count;
4715 copy_count -= partial_count;
4716 if (++i == info->rbuf_count)
4717 i = 0;
4718 }
4719
04b374d0
PF		 4720 if (info->params.crc_type & HDLC_CRC_RETURN_EX) {
4721 *p = (status & BIT1) ? RX_CRC_ERROR : RX_OK;
4722 framesize++;
4723 }
4724
af69c7f9 4725#if SYNCLINK_GENERIC_HDLC
705b6c7b
PF		 4726 if (info->netcount)
4727 hdlcdev_rx(info,info->tmp_rbuf, framesize);
4728 else
4729#endif
4730 ldisc_receive_buf(tty, info->tmp_rbuf, info->flag_buf, framesize);
4731 }
4732 }
4733 free_rbufs(info, start, end);
0fab6de0 4734 return true;
705b6c7b
PF		 4735
4736cleanup:
0fab6de0 4737 return false;
705b6c7b
PF		 4738}
4739
4740/*
4741 * pass receive buffer (RAW synchronous mode) to tty layer
0fab6de0 4742 * return true if buffer available, otherwise false
705b6c7b 4743 */
0fab6de0 4744static bool rx_get_buf(struct slgt_info *info)
705b6c7b
PF		 4745{
4746 unsigned int i = info->rbuf_current;
cb10dc9a 4747 unsigned int count;
705b6c7b
PF		 4748
4749 if (!desc_complete(info->rbufs[i]))
0fab6de0 4750 return false;
cb10dc9a
PF		 4751 count = desc_count(info->rbufs[i]);
4752 switch(info->params.mode) {
4753 case MGSL_MODE_MONOSYNC:
4754 case MGSL_MODE_BISYNC:
9807224f 4755 case MGSL_MODE_XSYNC:
cb10dc9a
PF		 4756 /* ignore residue in byte synchronous modes */
4757 if (desc_residue(info->rbufs[i]))
4758 count--;
4759 break;
4760 }
4761 DBGDATA(info, info->rbufs[i].buf, count, "rx");
4762 DBGINFO(("rx_get_buf size=%d\n", count));
4763 if (count)
8fb06c77 4764 ldisc_receive_buf(info->port.tty, info->rbufs[i].buf,
cb10dc9a 4765 info->flag_buf, count);
705b6c7b 4766 free_rbufs(info, i, i);
0fab6de0 4767 return true;
705b6c7b
PF		 4768}
4769
4770static void reset_tbufs(struct slgt_info *info)
4771{
4772 unsigned int i;
4773 info->tbuf_current = 0;
4774 for (i=0 ; i < info->tbuf_count ; i++) {
4775 info->tbufs[i].status = 0;
4776 info->tbufs[i].count = 0;
4777 }
4778}
4779
4780/*
4781 * return number of free transmit DMA buffers
4782 */
4783static unsigned int free_tbuf_count(struct slgt_info *info)
4784{
4785 unsigned int count = 0;
4786 unsigned int i = info->tbuf_current;
4787
4788 do
4789 {
4790 if (desc_count(info->tbufs[i]))
4791 break; /* buffer in use */
4792 ++count;
4793 if (++i == info->tbuf_count)
4794 i=0;
4795 } while (i != info->tbuf_current);
4796
bb029c67
PF		 4797 /* if tx DMA active, last zero count buffer is in use */
4798 if (count && (rd_reg32(info, TDCSR) & BIT0))
705b6c7b
PF		 4799 --count;
4800
4801 return count;
4802}
4803
403214d0
PF		 4804/*
4805 * return number of bytes in unsent transmit DMA buffers
4806 * and the serial controller tx FIFO
4807 */
4808static unsigned int tbuf_bytes(struct slgt_info *info)
4809{
4810 unsigned int total_count = 0;
4811 unsigned int i = info->tbuf_current;
4812 unsigned int reg_value;
4813 unsigned int count;
4814 unsigned int active_buf_count = 0;
4815
4816 /*
4817 * Add descriptor counts for all tx DMA buffers.
4818 * If count is zero (cleared by DMA controller after read),
4819 * the buffer is complete or is actively being read from.
4820 *
4821 * Record buf_count of last buffer with zero count starting
4822 * from current ring position. buf_count is mirror
4823 * copy of count and is not cleared by serial controller.
4824 * If DMA controller is active, that buffer is actively
4825 * being read so add to total.
4826 */
4827 do {
4828 count = desc_count(info->tbufs[i]);
4829 if (count)
4830 total_count += count;
4831 else if (!total_count)
4832 active_buf_count = info->tbufs[i].buf_count;
4833 if (++i == info->tbuf_count)
4834 i = 0;
4835 } while (i != info->tbuf_current);
4836
4837 /* read tx DMA status register */
4838 reg_value = rd_reg32(info, TDCSR);
4839
4840 /* if tx DMA active, last zero count buffer is in use */
4841 if (reg_value & BIT0)
4842 total_count += active_buf_count;
4843
4844 /* add tx FIFO count = reg_value[15..8] */
4845 total_count += (reg_value >> 8) & 0xff;
4846
4847 /* if transmitter active add one byte for shift register */
4848 if (info->tx_active)
4849 total_count++;
4850
4851 return total_count;
4852}
4853
705b6c7b 4854/*
de538eb3
PF		 4855 * load data into transmit DMA buffer ring and start transmitter if needed
4856 * return true if data accepted, otherwise false (buffers full)
705b6c7b 4857 */
de538eb3 4858static bool tx_load(struct slgt_info *info, const char *buf, unsigned int size)
705b6c7b
PF		 4859{
4860 unsigned short count;
4861 unsigned int i;
4862 struct slgt_desc *d;
4863
de538eb3
PF		 4864 /* check required buffer space */
4865 if (DIV_ROUND_UP(size, DMABUFSIZE) > free_tbuf_count(info))
4866 return false;
705b6c7b
PF		 4867
4868 DBGDATA(info, buf, size, "tx");
4869
de538eb3
PF		 4870 /*
4871 * copy data to one or more DMA buffers in circular ring
4872 * tbuf_start = first buffer for this data
4873 * tbuf_current = next free buffer
4874 *
4875 * Copy all data before making data visible to DMA controller by
4876 * setting descriptor count of the first buffer.
4877 * This prevents an active DMA controller from reading the first DMA
4878 * buffers of a frame and stopping before the final buffers are filled.
4879 */
4880
705b6c7b
PF		 4881 info->tbuf_start = i = info->tbuf_current;
4882
4883 while (size) {
4884 d = &info->tbufs[i];
705b6c7b
PF		 4885
4886 count = (unsigned short)((size > DMABUFSIZE) ? DMABUFSIZE : size);
4887 memcpy(d->buf, buf, count);
4888
4889 size -= count;
4890 buf += count;
4891
cb10dc9a
PF		 4892 /*
4893 * set EOF bit for last buffer of HDLC frame or
4894 * for every buffer in raw mode
4895 */
4896 if ((!size && info->params.mode == MGSL_MODE_HDLC) ||
4897 info->params.mode == MGSL_MODE_RAW)
4898 set_desc_eof(*d, 1);
705b6c7b
PF		 4899 else
4900 set_desc_eof(*d, 0);
4901
de538eb3
PF		 4902 /* set descriptor count for all but first buffer */
4903 if (i != info->tbuf_start)
4904 set_desc_count(*d, count);
403214d0 4905 d->buf_count = count;
de538eb3
PF		 4906
4907 if (++i == info->tbuf_count)
4908 i = 0;
705b6c7b
PF		 4909 }
4910
4911 info->tbuf_current = i;
de538eb3
PF		 4912
4913 /* set first buffer count to make new data visible to DMA controller */
4914 d = &info->tbufs[info->tbuf_start];
4915 set_desc_count(*d, d->buf_count);
4916
4917 /* start transmitter if needed and update transmit timeout */
4918 if (!info->tx_active)
4919 tx_start(info);
4920 update_tx_timer(info);
4921
4922 return true;
705b6c7b
PF		 4923}
4924
4925static int register_test(struct slgt_info *info)
4926{
4927 static unsigned short patterns[] =
4928 {0x0000, 0xffff, 0xaaaa, 0x5555, 0x6969, 0x9696};
7ea7c6d5 4929 static unsigned int count = ARRAY_SIZE(patterns);
705b6c7b
PF		 4930 unsigned int i;
4931 int rc = 0;
4932
4933 for (i=0 ; i < count ; i++) {
4934 wr_reg16(info, TIR, patterns[i]);
4935 wr_reg16(info, BDR, patterns[(i+1)%count]);
4936 if ((rd_reg16(info, TIR) != patterns[i]) ||
4937 (rd_reg16(info, BDR) != patterns[(i+1)%count])) {
4938 rc = -ENODEV;
4939 break;
4940 }
4941 }
0080b7aa 4942 info->gpio_present = (rd_reg32(info, JCR) & BIT5) ? 1 : 0;
705b6c7b
PF		 4943 info->init_error = rc ? 0 : DiagStatus_AddressFailure;
4944 return rc;
4945}
4946
4947static int irq_test(struct slgt_info *info)
4948{
4949 unsigned long timeout;
4950 unsigned long flags;
8fb06c77 4951 struct tty_struct *oldtty = info->port.tty;
705b6c7b
PF		 4952 u32 speed = info->params.data_rate;
4953
4954 info->params.data_rate = 921600;
8fb06c77 4955 info->port.tty = NULL;
705b6c7b
PF		 4956
4957 spin_lock_irqsave(&info->lock, flags);
4958 async_mode(info);
4959 slgt_irq_on(info, IRQ_TXIDLE);
4960
4961 /* enable transmitter */
4962 wr_reg16(info, TCR,
4963 (unsigned short)(rd_reg16(info, TCR) | BIT1));
4964
4965 /* write one byte and wait for tx idle */
4966 wr_reg16(info, TDR, 0);
4967
4968 /* assume failure */
4969 info->init_error = DiagStatus_IrqFailure;
0fab6de0 4970 info->irq_occurred = false;
705b6c7b
PF		 4971
4972 spin_unlock_irqrestore(&info->lock, flags);
4973
4974 timeout=100;
4975 while(timeout-- && !info->irq_occurred)
4976 msleep_interruptible(10);
4977
4978 spin_lock_irqsave(&info->lock,flags);
4979 reset_port(info);
4980 spin_unlock_irqrestore(&info->lock,flags);
4981
4982 info->params.data_rate = speed;
8fb06c77 4983 info->port.tty = oldtty;
705b6c7b
PF		 4984
4985 info->init_error = info->irq_occurred ? 0 : DiagStatus_IrqFailure;
4986 return info->irq_occurred ? 0 : -ENODEV;
4987}
4988
4989static int loopback_test_rx(struct slgt_info *info)
4990{
4991 unsigned char *src, *dest;
4992 int count;
4993
4994 if (desc_complete(info->rbufs[0])) {
4995 count = desc_count(info->rbufs[0]);
4996 src = info->rbufs[0].buf;
4997 dest = info->tmp_rbuf;
4998
4999 for( ; count ; count-=2, src+=2) {
5000 /* src=data byte (src+1)=status byte */
5001 if (!(*(src+1) & (BIT9 + BIT8))) {
5002 *dest = *src;
5003 dest++;
5004 info->tmp_rbuf_count++;
5005 }
5006 }
5007 DBGDATA(info, info->tmp_rbuf, info->tmp_rbuf_count, "rx");
5008 return 1;
5009 }
5010 return 0;
5011}
5012
5013static int loopback_test(struct slgt_info *info)
5014{
5015#define TESTFRAMESIZE 20
5016
5017 unsigned long timeout;
5018 u16 count = TESTFRAMESIZE;
5019 unsigned char buf[TESTFRAMESIZE];
5020 int rc = -ENODEV;
5021 unsigned long flags;
5022
8fb06c77 5023 struct tty_struct *oldtty = info->port.tty;
705b6c7b
PF		 5024 MGSL_PARAMS params;
5025
5026 memcpy(&params, &info->params, sizeof(params));
5027
5028 info->params.mode = MGSL_MODE_ASYNC;
5029 info->params.data_rate = 921600;
5030 info->params.loopback = 1;
8fb06c77 5031 info->port.tty = NULL;
705b6c7b
PF		 5032
5033 /* build and send transmit frame */
5034 for (count = 0; count < TESTFRAMESIZE; ++count)
5035 buf[count] = (unsigned char)count;
5036
5037 info->tmp_rbuf_count = 0;
5038 memset(info->tmp_rbuf, 0, TESTFRAMESIZE);
5039
5040 /* program hardware for HDLC and enabled receiver */
5041 spin_lock_irqsave(&info->lock,flags);
5042 async_mode(info);
5043 rx_start(info);
705b6c7b 5044 tx_load(info, buf, count);
705b6c7b
PF		 5045 spin_unlock_irqrestore(&info->lock, flags);
5046
5047 /* wait for receive complete */
5048 for (timeout = 100; timeout; --timeout) {
5049 msleep_interruptible(10);
5050 if (loopback_test_rx(info)) {
5051 rc = 0;
5052 break;
5053 }
5054 }
5055
5056 /* verify received frame length and contents */
5057 if (!rc && (info->tmp_rbuf_count != count ||
5058 memcmp(buf, info->tmp_rbuf, count))) {
5059 rc = -ENODEV;
5060 }
5061
5062 spin_lock_irqsave(&info->lock,flags);
5063 reset_adapter(info);
5064 spin_unlock_irqrestore(&info->lock,flags);
5065
5066 memcpy(&info->params, &params, sizeof(info->params));
8fb06c77 5067 info->port.tty = oldtty;
705b6c7b
PF		 5068
5069 info->init_error = rc ? DiagStatus_DmaFailure : 0;
5070 return rc;
5071}
5072
5073static int adapter_test(struct slgt_info *info)
5074{
5075 DBGINFO(("testing %s\n", info->device_name));
294dad05 5076 if (register_test(info) < 0) {
705b6c7b
PF		 5077 printk("register test failure %s addr=%08X\n",
5078 info->device_name, info->phys_reg_addr);
294dad05 5079 } else if (irq_test(info) < 0) {
705b6c7b
PF		 5080 printk("IRQ test failure %s IRQ=%d\n",
5081 info->device_name, info->irq_level);
294dad05 5082 } else if (loopback_test(info) < 0) {
705b6c7b
PF		 5083 printk("loopback test failure %s\n", info->device_name);
5084 }
5085 return info->init_error;
5086}
5087
5088/*
5089 * transmit timeout handler
5090 */
e99e88a9 5091static void tx_timeout(struct timer_list *t)
705b6c7b 5092{
e99e88a9 5093 struct slgt_info *info = from_timer(info, t, tx_timer);
705b6c7b
PF		 5094 unsigned long flags;
5095
5096 DBGINFO(("%s tx_timeout\n", info->device_name));
5097 if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
5098 info->icount.txtimeout++;
5099 }
5100 spin_lock_irqsave(&info->lock,flags);
ce89294c 5101 tx_stop(info);
705b6c7b
PF		 5102 spin_unlock_irqrestore(&info->lock,flags);
5103
af69c7f9 5104#if SYNCLINK_GENERIC_HDLC
705b6c7b
PF		 5105 if (info->netcount)
5106 hdlcdev_tx_done(info);
5107 else
5108#endif
5109 bh_transmit(info);
5110}
5111
5112/*
5113 * receive buffer polling timer
5114 */
e99e88a9 5115static void rx_timeout(struct timer_list *t)
705b6c7b 5116{
e99e88a9 5117 struct slgt_info *info = from_timer(info, t, rx_timer);
705b6c7b
PF		 5118 unsigned long flags;
5119
5120 DBGINFO(("%s rx_timeout\n", info->device_name));
5121 spin_lock_irqsave(&info->lock, flags);
5122 info->pending_bh |= BH_RECEIVE;
5123 spin_unlock_irqrestore(&info->lock, flags);
c4028958 5124 bh_handler(&info->task);
705b6c7b
PF		 5125}
5126
Linux 6.x block layer and io_uring tree(s)