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tty: add SPDX identifiers to all remaining files in drivers/tty/
[linux-block.git] / drivers / tty / synclink.c
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e3b3d0f5 1// SPDX-License-Identifier: GPL-1.0+
1da177e4 2/*
0ff1b2c8 3 * $Id: synclink.c,v 4.38 2005/11/07 16:30:34 paulkf Exp $
1da177e4
LT		 4 *
5 * Device driver for Microgate SyncLink ISA and PCI
6 * high speed multiprotocol serial adapters.
7 *
8 * written by Paul Fulghum for Microgate Corporation
9 * paulkf@microgate.com
10 *
11 * Microgate and SyncLink are trademarks of Microgate Corporation
12 *
13 * Derived from serial.c written by Theodore Ts'o and Linus Torvalds
14 *
15 * Original release 01/11/99
16 *
17 * This code is released under the GNU General Public License (GPL)
18 *
19 * This driver is primarily intended for use in synchronous
20 * HDLC mode. Asynchronous mode is also provided.
21 *
22 * When operating in synchronous mode, each call to mgsl_write()
23 * contains exactly one complete HDLC frame. Calling mgsl_put_char
24 * will start assembling an HDLC frame that will not be sent until
25 * mgsl_flush_chars or mgsl_write is called.
26 *
27 * Synchronous receive data is reported as complete frames. To accomplish
28 * this, the TTY flip buffer is bypassed (too small to hold largest
29 * frame and may fragment frames) and the line discipline
30 * receive entry point is called directly.
31 *
32 * This driver has been tested with a slightly modified ppp.c driver
33 * for synchronous PPP.
34 *
35 * 2000/02/16
36 * Added interface for syncppp.c driver (an alternate synchronous PPP
37 * implementation that also supports Cisco HDLC). Each device instance
38 * registers as a tty device AND a network device (if dosyncppp option
39 * is set for the device). The functionality is determined by which
40 * device interface is opened.
41 *
42 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
43 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
44 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
45 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
46 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
47 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
48 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
49 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
50 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
51 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
52 * OF THE POSSIBILITY OF SUCH DAMAGE.
53 */
54
55#if defined(__i386__)
56# define BREAKPOINT() asm(" int $3");
57#else
58# define BREAKPOINT() { }
59#endif
60
61#define MAX_ISA_DEVICES 10
62#define MAX_PCI_DEVICES 10
63#define MAX_TOTAL_DEVICES 20
64
1da177e4
LT		 65#include <linux/module.h>
66#include <linux/errno.h>
67#include <linux/signal.h>
68#include <linux/sched.h>
69#include <linux/timer.h>
70#include <linux/interrupt.h>
71#include <linux/pci.h>
72#include <linux/tty.h>
73#include <linux/tty_flip.h>
74#include <linux/serial.h>
75#include <linux/major.h>
76#include <linux/string.h>
77#include <linux/fcntl.h>
78#include <linux/ptrace.h>
79#include <linux/ioport.h>
80#include <linux/mm.h>
d337829b 81#include <linux/seq_file.h>
1da177e4
LT		 82#include <linux/slab.h>
83#include <linux/delay.h>
1da177e4 84#include <linux/netdevice.h>
1da177e4
LT		 85#include <linux/vmalloc.h>
86#include <linux/init.h>
1da177e4 87#include <linux/ioctl.h>
3dd1247f 88#include <linux/synclink.h>
1da177e4 89
1da177e4
LT		 90#include <asm/io.h>
91#include <asm/irq.h>
92#include <asm/dma.h>
93#include <linux/bitops.h>
94#include <asm/types.h>
95#include <linux/termios.h>
96#include <linux/workqueue.h>
97#include <linux/hdlc.h>
0ff1b2c8 98#include <linux/dma-mapping.h>
1da177e4 99
af69c7f9
PF		 100#if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_MODULE))
101#define SYNCLINK_GENERIC_HDLC 1
102#else
103#define SYNCLINK_GENERIC_HDLC 0
1da177e4
LT		 104#endif
105
106#define GET_USER(error,value,addr) error = get_user(value,addr)
107#define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
108#define PUT_USER(error,value,addr) error = put_user(value,addr)
109#define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
110
7c0f6ba6 111#include <linux/uaccess.h>
1da177e4 112
1da177e4
LT		 113#define RCLRVALUE 0xffff
114
115static MGSL_PARAMS default_params = {
116 MGSL_MODE_HDLC, /* unsigned long mode */
117 0, /* unsigned char loopback; */
118 HDLC_FLAG_UNDERRUN_ABORT15, /* unsigned short flags; */
119 HDLC_ENCODING_NRZI_SPACE, /* unsigned char encoding; */
120 0, /* unsigned long clock_speed; */
121 0xff, /* unsigned char addr_filter; */
122 HDLC_CRC_16_CCITT, /* unsigned short crc_type; */
123 HDLC_PREAMBLE_LENGTH_8BITS, /* unsigned char preamble_length; */
124 HDLC_PREAMBLE_PATTERN_NONE, /* unsigned char preamble; */
125 9600, /* unsigned long data_rate; */
126 8, /* unsigned char data_bits; */
127 1, /* unsigned char stop_bits; */
128 ASYNC_PARITY_NONE /* unsigned char parity; */
129};
130
131#define SHARED_MEM_ADDRESS_SIZE 0x40000
623a4395
PF		 132#define BUFFERLISTSIZE 4096
133#define DMABUFFERSIZE 4096
1da177e4
LT		 134#define MAXRXFRAMES 7
135
136typedef struct _DMABUFFERENTRY
137{
138 u32 phys_addr; /* 32-bit flat physical address of data buffer */
4a918bc2
PF		 139 volatile u16 count; /* buffer size/data count */
140 volatile u16 status; /* Control/status field */
141 volatile u16 rcc; /* character count field */
1da177e4
LT		 142 u16 reserved; /* padding required by 16C32 */
143 u32 link; /* 32-bit flat link to next buffer entry */
144 char *virt_addr; /* virtual address of data buffer */
145 u32 phys_entry; /* physical address of this buffer entry */
0ff1b2c8 146 dma_addr_t dma_addr;
1da177e4
LT		 147} DMABUFFERENTRY, *DMAPBUFFERENTRY;
148
149/* The queue of BH actions to be performed */
150
151#define BH_RECEIVE 1
152#define BH_TRANSMIT 2
153#define BH_STATUS 4
154
155#define IO_PIN_SHUTDOWN_LIMIT 100
156
1da177e4
LT		 157struct _input_signal_events {
158 int ri_up;
159 int ri_down;
160 int dsr_up;
161 int dsr_down;
162 int dcd_up;
163 int dcd_down;
164 int cts_up;
165 int cts_down;
166};
167
168/* transmit holding buffer definitions*/
169#define MAX_TX_HOLDING_BUFFERS 5
170struct tx_holding_buffer {
171 int buffer_size;
172 unsigned char * buffer;
173};
174
175
176/*
177 * Device instance data structure
178 */
179
180struct mgsl_struct {
181 int magic;
8fb06c77 182 struct tty_port port;
1da177e4
LT		 183 int line;
184 int hw_version;
1da177e4
LT		 185
186 struct mgsl_icount icount;
187
1da177e4
LT		 188 int timeout;
189 int x_char; /* xon/xoff character */
1da177e4
LT		 190 u16 read_status_mask;
191 u16 ignore_status_mask;
192 unsigned char *xmit_buf;
193 int xmit_head;
194 int xmit_tail;
195 int xmit_cnt;
196
1da177e4
LT		 197 wait_queue_head_t status_event_wait_q;
198 wait_queue_head_t event_wait_q;
199 struct timer_list tx_timer; /* HDLC transmit timeout timer */
200 struct mgsl_struct *next_device; /* device list link */
201
202 spinlock_t irq_spinlock; /* spinlock for synchronizing with ISR */
203 struct work_struct task; /* task structure for scheduling bh */
204
205 u32 EventMask; /* event trigger mask */
206 u32 RecordedEvents; /* pending events */
207
208 u32 max_frame_size; /* as set by device config */
209
210 u32 pending_bh;
211
0fab6de0 212 bool bh_running; /* Protection from multiple */
1da177e4 213 int isr_overflow;
0fab6de0 214 bool bh_requested;
1da177e4
LT		 215
216 int dcd_chkcount; /* check counts to prevent */
217 int cts_chkcount; /* too many IRQs if a signal */
218 int dsr_chkcount; /* is floating */
219 int ri_chkcount;
220
221 char *buffer_list; /* virtual address of Rx & Tx buffer lists */
0ff1b2c8
PF		 222 u32 buffer_list_phys;
223 dma_addr_t buffer_list_dma_addr;
1da177e4
LT		 224
225 unsigned int rx_buffer_count; /* count of total allocated Rx buffers */
226 DMABUFFERENTRY *rx_buffer_list; /* list of receive buffer entries */
227 unsigned int current_rx_buffer;
228
229 int num_tx_dma_buffers; /* number of tx dma frames required */
230 int tx_dma_buffers_used;
231 unsigned int tx_buffer_count; /* count of total allocated Tx buffers */
232 DMABUFFERENTRY *tx_buffer_list; /* list of transmit buffer entries */
233 int start_tx_dma_buffer; /* tx dma buffer to start tx dma operation */
234 int current_tx_buffer; /* next tx dma buffer to be loaded */
235
236 unsigned char *intermediate_rxbuffer;
237
238 int num_tx_holding_buffers; /* number of tx holding buffer allocated */
239 int get_tx_holding_index; /* next tx holding buffer for adapter to load */
240 int put_tx_holding_index; /* next tx holding buffer to store user request */
241 int tx_holding_count; /* number of tx holding buffers waiting */
242 struct tx_holding_buffer tx_holding_buffers[MAX_TX_HOLDING_BUFFERS];
243
0fab6de0
JP		 244 bool rx_enabled;
245 bool rx_overflow;
246 bool rx_rcc_underrun;
1da177e4 247
0fab6de0
JP		 248 bool tx_enabled;
249 bool tx_active;
1da177e4
LT		 250 u32 idle_mode;
251
252 u16 cmr_value;
253 u16 tcsr_value;
254
255 char device_name[25]; /* device instance name */
256
257 unsigned int bus_type; /* expansion bus type (ISA,EISA,PCI) */
258 unsigned char bus; /* expansion bus number (zero based) */
259 unsigned char function; /* PCI device number */
260
261 unsigned int io_base; /* base I/O address of adapter */
262 unsigned int io_addr_size; /* size of the I/O address range */
0fab6de0 263 bool io_addr_requested; /* true if I/O address requested */
1da177e4
LT		 264
265 unsigned int irq_level; /* interrupt level */
266 unsigned long irq_flags;
0fab6de0 267 bool irq_requested; /* true if IRQ requested */
1da177e4
LT		 268
269 unsigned int dma_level; /* DMA channel */
0fab6de0 270 bool dma_requested; /* true if dma channel requested */
1da177e4
LT		 271
272 u16 mbre_bit;
273 u16 loopback_bits;
274 u16 usc_idle_mode;
275
276 MGSL_PARAMS params; /* communications parameters */
277
278 unsigned char serial_signals; /* current serial signal states */
279
0fab6de0 280 bool irq_occurred; /* for diagnostics use */
1da177e4
LT		 281 unsigned int init_error; /* Initialization startup error (DIAGS) */
282 int fDiagnosticsmode; /* Driver in Diagnostic mode? (DIAGS) */
283
284 u32 last_mem_alloc;
285 unsigned char* memory_base; /* shared memory address (PCI only) */
286 u32 phys_memory_base;
0fab6de0 287 bool shared_mem_requested;
1da177e4
LT		 288
289 unsigned char* lcr_base; /* local config registers (PCI only) */
290 u32 phys_lcr_base;
291 u32 lcr_offset;
0fab6de0 292 bool lcr_mem_requested;
1da177e4
LT		 293
294 u32 misc_ctrl_value;
a6b68a69 295 char *flag_buf;
0fab6de0 296 bool drop_rts_on_tx_done;
1da177e4 297
0fab6de0
JP		 298 bool loopmode_insert_requested;
299 bool loopmode_send_done_requested;
1da177e4
LT		 300
301 struct _input_signal_events input_signal_events;
302
303 /* generic HDLC device parts */
304 int netcount;
1da177e4
LT		 305 spinlock_t netlock;
306
af69c7f9 307#if SYNCLINK_GENERIC_HDLC
1da177e4
LT		 308 struct net_device *netdev;
309#endif
310};
311
312#define MGSL_MAGIC 0x5401
313
314/*
315 * The size of the serial xmit buffer is 1 page, or 4096 bytes
316 */
317#ifndef SERIAL_XMIT_SIZE
318#define SERIAL_XMIT_SIZE 4096
319#endif
320
321/*
322 * These macros define the offsets used in calculating the
323 * I/O address of the specified USC registers.
324 */
325
326
327#define DCPIN 2 /* Bit 1 of I/O address */
328#define SDPIN 4 /* Bit 2 of I/O address */
329
330#define DCAR 0 /* DMA command/address register */
331#define CCAR SDPIN /* channel command/address register */
332#define DATAREG DCPIN + SDPIN /* serial data register */
333#define MSBONLY 0x41
334#define LSBONLY 0x40
335
336/*
337 * These macros define the register address (ordinal number)
338 * used for writing address/value pairs to the USC.
339 */
340
341#define CMR 0x02 /* Channel mode Register */
342#define CCSR 0x04 /* Channel Command/status Register */
343#define CCR 0x06 /* Channel Control Register */
344#define PSR 0x08 /* Port status Register */
345#define PCR 0x0a /* Port Control Register */
346#define TMDR 0x0c /* Test mode Data Register */
347#define TMCR 0x0e /* Test mode Control Register */
348#define CMCR 0x10 /* Clock mode Control Register */
349#define HCR 0x12 /* Hardware Configuration Register */
350#define IVR 0x14 /* Interrupt Vector Register */
351#define IOCR 0x16 /* Input/Output Control Register */
352#define ICR 0x18 /* Interrupt Control Register */
353#define DCCR 0x1a /* Daisy Chain Control Register */
354#define MISR 0x1c /* Misc Interrupt status Register */
355#define SICR 0x1e /* status Interrupt Control Register */
356#define RDR 0x20 /* Receive Data Register */
357#define RMR 0x22 /* Receive mode Register */
358#define RCSR 0x24 /* Receive Command/status Register */
359#define RICR 0x26 /* Receive Interrupt Control Register */
360#define RSR 0x28 /* Receive Sync Register */
361#define RCLR 0x2a /* Receive count Limit Register */
362#define RCCR 0x2c /* Receive Character count Register */
363#define TC0R 0x2e /* Time Constant 0 Register */
364#define TDR 0x30 /* Transmit Data Register */
365#define TMR 0x32 /* Transmit mode Register */
366#define TCSR 0x34 /* Transmit Command/status Register */
367#define TICR 0x36 /* Transmit Interrupt Control Register */
368#define TSR 0x38 /* Transmit Sync Register */
369#define TCLR 0x3a /* Transmit count Limit Register */
370#define TCCR 0x3c /* Transmit Character count Register */
371#define TC1R 0x3e /* Time Constant 1 Register */
372
373
374/*
375 * MACRO DEFINITIONS FOR DMA REGISTERS
376 */
377
378#define DCR 0x06 /* DMA Control Register (shared) */
379#define DACR 0x08 /* DMA Array count Register (shared) */
380#define BDCR 0x12 /* Burst/Dwell Control Register (shared) */
381#define DIVR 0x14 /* DMA Interrupt Vector Register (shared) */
382#define DICR 0x18 /* DMA Interrupt Control Register (shared) */
383#define CDIR 0x1a /* Clear DMA Interrupt Register (shared) */
384#define SDIR 0x1c /* Set DMA Interrupt Register (shared) */
385
386#define TDMR 0x02 /* Transmit DMA mode Register */
387#define TDIAR 0x1e /* Transmit DMA Interrupt Arm Register */
388#define TBCR 0x2a /* Transmit Byte count Register */
389#define TARL 0x2c /* Transmit Address Register (low) */
390#define TARU 0x2e /* Transmit Address Register (high) */
391#define NTBCR 0x3a /* Next Transmit Byte count Register */
392#define NTARL 0x3c /* Next Transmit Address Register (low) */
393#define NTARU 0x3e /* Next Transmit Address Register (high) */
394
395#define RDMR 0x82 /* Receive DMA mode Register (non-shared) */
396#define RDIAR 0x9e /* Receive DMA Interrupt Arm Register */
397#define RBCR 0xaa /* Receive Byte count Register */
398#define RARL 0xac /* Receive Address Register (low) */
399#define RARU 0xae /* Receive Address Register (high) */
400#define NRBCR 0xba /* Next Receive Byte count Register */
401#define NRARL 0xbc /* Next Receive Address Register (low) */
402#define NRARU 0xbe /* Next Receive Address Register (high) */
403
404
405/*
406 * MACRO DEFINITIONS FOR MODEM STATUS BITS
407 */
408
409#define MODEMSTATUS_DTR 0x80
410#define MODEMSTATUS_DSR 0x40
411#define MODEMSTATUS_RTS 0x20
412#define MODEMSTATUS_CTS 0x10
413#define MODEMSTATUS_RI 0x04
414#define MODEMSTATUS_DCD 0x01
415
416
417/*
418 * Channel Command/Address Register (CCAR) Command Codes
419 */
420
421#define RTCmd_Null 0x0000
422#define RTCmd_ResetHighestIus 0x1000
423#define RTCmd_TriggerChannelLoadDma 0x2000
424#define RTCmd_TriggerRxDma 0x2800
425#define RTCmd_TriggerTxDma 0x3000
426#define RTCmd_TriggerRxAndTxDma 0x3800
427#define RTCmd_PurgeRxFifo 0x4800
428#define RTCmd_PurgeTxFifo 0x5000
429#define RTCmd_PurgeRxAndTxFifo 0x5800
430#define RTCmd_LoadRcc 0x6800
431#define RTCmd_LoadTcc 0x7000
432#define RTCmd_LoadRccAndTcc 0x7800
433#define RTCmd_LoadTC0 0x8800
434#define RTCmd_LoadTC1 0x9000
435#define RTCmd_LoadTC0AndTC1 0x9800
436#define RTCmd_SerialDataLSBFirst 0xa000
437#define RTCmd_SerialDataMSBFirst 0xa800
438#define RTCmd_SelectBigEndian 0xb000
439#define RTCmd_SelectLittleEndian 0xb800
440
441
442/*
443 * DMA Command/Address Register (DCAR) Command Codes
444 */
445
446#define DmaCmd_Null 0x0000
447#define DmaCmd_ResetTxChannel 0x1000
448#define DmaCmd_ResetRxChannel 0x1200
449#define DmaCmd_StartTxChannel 0x2000
450#define DmaCmd_StartRxChannel 0x2200
451#define DmaCmd_ContinueTxChannel 0x3000
452#define DmaCmd_ContinueRxChannel 0x3200
453#define DmaCmd_PauseTxChannel 0x4000
454#define DmaCmd_PauseRxChannel 0x4200
455#define DmaCmd_AbortTxChannel 0x5000
456#define DmaCmd_AbortRxChannel 0x5200
457#define DmaCmd_InitTxChannel 0x7000
458#define DmaCmd_InitRxChannel 0x7200
459#define DmaCmd_ResetHighestDmaIus 0x8000
460#define DmaCmd_ResetAllChannels 0x9000
461#define DmaCmd_StartAllChannels 0xa000
462#define DmaCmd_ContinueAllChannels 0xb000
463#define DmaCmd_PauseAllChannels 0xc000
464#define DmaCmd_AbortAllChannels 0xd000
465#define DmaCmd_InitAllChannels 0xf000
466
467#define TCmd_Null 0x0000
468#define TCmd_ClearTxCRC 0x2000
469#define TCmd_SelectTicrTtsaData 0x4000
470#define TCmd_SelectTicrTxFifostatus 0x5000
471#define TCmd_SelectTicrIntLevel 0x6000
472#define TCmd_SelectTicrdma_level 0x7000
473#define TCmd_SendFrame 0x8000
474#define TCmd_SendAbort 0x9000
475#define TCmd_EnableDleInsertion 0xc000
476#define TCmd_DisableDleInsertion 0xd000
477#define TCmd_ClearEofEom 0xe000
478#define TCmd_SetEofEom 0xf000
479
480#define RCmd_Null 0x0000
481#define RCmd_ClearRxCRC 0x2000
482#define RCmd_EnterHuntmode 0x3000
483#define RCmd_SelectRicrRtsaData 0x4000
484#define RCmd_SelectRicrRxFifostatus 0x5000
485#define RCmd_SelectRicrIntLevel 0x6000
486#define RCmd_SelectRicrdma_level 0x7000
487
488/*
489 * Bits for enabling and disabling IRQs in Interrupt Control Register (ICR)
490 */
491
492#define RECEIVE_STATUS BIT5
493#define RECEIVE_DATA BIT4
494#define TRANSMIT_STATUS BIT3
495#define TRANSMIT_DATA BIT2
496#define IO_PIN BIT1
497#define MISC BIT0
498
499
500/*
501 * Receive status Bits in Receive Command/status Register RCSR
502 */
503
504#define RXSTATUS_SHORT_FRAME BIT8
505#define RXSTATUS_CODE_VIOLATION BIT8
506#define RXSTATUS_EXITED_HUNT BIT7
507#define RXSTATUS_IDLE_RECEIVED BIT6
508#define RXSTATUS_BREAK_RECEIVED BIT5
509#define RXSTATUS_ABORT_RECEIVED BIT5
510#define RXSTATUS_RXBOUND BIT4
511#define RXSTATUS_CRC_ERROR BIT3
512#define RXSTATUS_FRAMING_ERROR BIT3
513#define RXSTATUS_ABORT BIT2
514#define RXSTATUS_PARITY_ERROR BIT2
515#define RXSTATUS_OVERRUN BIT1
516#define RXSTATUS_DATA_AVAILABLE BIT0
517#define RXSTATUS_ALL 0x01f6
518#define usc_UnlatchRxstatusBits(a,b) usc_OutReg( (a), RCSR, (u16)((b) & RXSTATUS_ALL) )
519
520/*
521 * Values for setting transmit idle mode in
522 * Transmit Control/status Register (TCSR)
523 */
524#define IDLEMODE_FLAGS 0x0000
525#define IDLEMODE_ALT_ONE_ZERO 0x0100
526#define IDLEMODE_ZERO 0x0200
527#define IDLEMODE_ONE 0x0300
528#define IDLEMODE_ALT_MARK_SPACE 0x0500
529#define IDLEMODE_SPACE 0x0600
530#define IDLEMODE_MARK 0x0700
531#define IDLEMODE_MASK 0x0700
532
533/*
534 * IUSC revision identifiers
535 */
536#define IUSC_SL1660 0x4d44
537#define IUSC_PRE_SL1660 0x4553
538
539/*
540 * Transmit status Bits in Transmit Command/status Register (TCSR)
541 */
542
543#define TCSR_PRESERVE 0x0F00
544
545#define TCSR_UNDERWAIT BIT11
546#define TXSTATUS_PREAMBLE_SENT BIT7
547#define TXSTATUS_IDLE_SENT BIT6
548#define TXSTATUS_ABORT_SENT BIT5
549#define TXSTATUS_EOF_SENT BIT4
550#define TXSTATUS_EOM_SENT BIT4
551#define TXSTATUS_CRC_SENT BIT3
552#define TXSTATUS_ALL_SENT BIT2
553#define TXSTATUS_UNDERRUN BIT1
554#define TXSTATUS_FIFO_EMPTY BIT0
555#define TXSTATUS_ALL 0x00fa
556#define usc_UnlatchTxstatusBits(a,b) usc_OutReg( (a), TCSR, (u16)((a)->tcsr_value + ((b) & 0x00FF)) )
557
558
559#define MISCSTATUS_RXC_LATCHED BIT15
560#define MISCSTATUS_RXC BIT14
561#define MISCSTATUS_TXC_LATCHED BIT13
562#define MISCSTATUS_TXC BIT12
563#define MISCSTATUS_RI_LATCHED BIT11
564#define MISCSTATUS_RI BIT10
565#define MISCSTATUS_DSR_LATCHED BIT9
566#define MISCSTATUS_DSR BIT8
567#define MISCSTATUS_DCD_LATCHED BIT7
568#define MISCSTATUS_DCD BIT6
569#define MISCSTATUS_CTS_LATCHED BIT5
570#define MISCSTATUS_CTS BIT4
571#define MISCSTATUS_RCC_UNDERRUN BIT3
572#define MISCSTATUS_DPLL_NO_SYNC BIT2
573#define MISCSTATUS_BRG1_ZERO BIT1
574#define MISCSTATUS_BRG0_ZERO BIT0
575
576#define usc_UnlatchIostatusBits(a,b) usc_OutReg((a),MISR,(u16)((b) & 0xaaa0))
577#define usc_UnlatchMiscstatusBits(a,b) usc_OutReg((a),MISR,(u16)((b) & 0x000f))
578
579#define SICR_RXC_ACTIVE BIT15
580#define SICR_RXC_INACTIVE BIT14
e06922aa 581#define SICR_RXC (BIT15|BIT14)
1da177e4
LT		 582#define SICR_TXC_ACTIVE BIT13
583#define SICR_TXC_INACTIVE BIT12
e06922aa 584#define SICR_TXC (BIT13|BIT12)
1da177e4
LT		 585#define SICR_RI_ACTIVE BIT11
586#define SICR_RI_INACTIVE BIT10
e06922aa 587#define SICR_RI (BIT11|BIT10)
1da177e4
LT		 588#define SICR_DSR_ACTIVE BIT9
589#define SICR_DSR_INACTIVE BIT8
e06922aa 590#define SICR_DSR (BIT9|BIT8)
1da177e4
LT		 591#define SICR_DCD_ACTIVE BIT7
592#define SICR_DCD_INACTIVE BIT6
e06922aa 593#define SICR_DCD (BIT7|BIT6)
1da177e4
LT		 594#define SICR_CTS_ACTIVE BIT5
595#define SICR_CTS_INACTIVE BIT4
e06922aa 596#define SICR_CTS (BIT5|BIT4)
1da177e4
LT		 597#define SICR_RCC_UNDERFLOW BIT3
598#define SICR_DPLL_NO_SYNC BIT2
599#define SICR_BRG1_ZERO BIT1
600#define SICR_BRG0_ZERO BIT0
601
602void usc_DisableMasterIrqBit( struct mgsl_struct *info );
603void usc_EnableMasterIrqBit( struct mgsl_struct *info );
604void usc_EnableInterrupts( struct mgsl_struct *info, u16 IrqMask );
605void usc_DisableInterrupts( struct mgsl_struct *info, u16 IrqMask );
606void usc_ClearIrqPendingBits( struct mgsl_struct *info, u16 IrqMask );
607
608#define usc_EnableInterrupts( a, b ) \
609 usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0xff00) + 0xc0 + (b)) )
610
611#define usc_DisableInterrupts( a, b ) \
612 usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0xff00) + 0x80 + (b)) )
613
614#define usc_EnableMasterIrqBit(a) \
615 usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0x0f00) + 0xb000) )
616
617#define usc_DisableMasterIrqBit(a) \
618 usc_OutReg( (a), ICR, (u16)(usc_InReg((a),ICR) & 0x7f00) )
619
620#define usc_ClearIrqPendingBits( a, b ) usc_OutReg( (a), DCCR, 0x40 + (b) )
621
622/*
623 * Transmit status Bits in Transmit Control status Register (TCSR)
624 * and Transmit Interrupt Control Register (TICR) (except BIT2, BIT0)
625 */
626
627#define TXSTATUS_PREAMBLE_SENT BIT7
628#define TXSTATUS_IDLE_SENT BIT6
629#define TXSTATUS_ABORT_SENT BIT5
630#define TXSTATUS_EOF BIT4
631#define TXSTATUS_CRC_SENT BIT3
632#define TXSTATUS_ALL_SENT BIT2
633#define TXSTATUS_UNDERRUN BIT1
634#define TXSTATUS_FIFO_EMPTY BIT0
635
636#define DICR_MASTER BIT15
637#define DICR_TRANSMIT BIT0
638#define DICR_RECEIVE BIT1
639
640#define usc_EnableDmaInterrupts(a,b) \
641 usc_OutDmaReg( (a), DICR, (u16)(usc_InDmaReg((a),DICR) | (b)) )
642
643#define usc_DisableDmaInterrupts(a,b) \
644 usc_OutDmaReg( (a), DICR, (u16)(usc_InDmaReg((a),DICR) & ~(b)) )
645
646#define usc_EnableStatusIrqs(a,b) \
647 usc_OutReg( (a), SICR, (u16)(usc_InReg((a),SICR) | (b)) )
648
649#define usc_DisablestatusIrqs(a,b) \
650 usc_OutReg( (a), SICR, (u16)(usc_InReg((a),SICR) & ~(b)) )
651
652/* Transmit status Bits in Transmit Control status Register (TCSR) */
653/* and Transmit Interrupt Control Register (TICR) (except BIT2, BIT0) */
654
655
656#define DISABLE_UNCONDITIONAL 0
657#define DISABLE_END_OF_FRAME 1
658#define ENABLE_UNCONDITIONAL 2
659#define ENABLE_AUTO_CTS 3
660#define ENABLE_AUTO_DCD 3
661#define usc_EnableTransmitter(a,b) \
662 usc_OutReg( (a), TMR, (u16)((usc_InReg((a),TMR) & 0xfffc) | (b)) )
663#define usc_EnableReceiver(a,b) \
664 usc_OutReg( (a), RMR, (u16)((usc_InReg((a),RMR) & 0xfffc) | (b)) )
665
666static u16 usc_InDmaReg( struct mgsl_struct *info, u16 Port );
667static void usc_OutDmaReg( struct mgsl_struct *info, u16 Port, u16 Value );
668static void usc_DmaCmd( struct mgsl_struct *info, u16 Cmd );
669
670static u16 usc_InReg( struct mgsl_struct *info, u16 Port );
671static void usc_OutReg( struct mgsl_struct *info, u16 Port, u16 Value );
672static void usc_RTCmd( struct mgsl_struct *info, u16 Cmd );
673void usc_RCmd( struct mgsl_struct *info, u16 Cmd );
674void usc_TCmd( struct mgsl_struct *info, u16 Cmd );
675
676#define usc_TCmd(a,b) usc_OutReg((a), TCSR, (u16)((a)->tcsr_value + (b)))
677#define usc_RCmd(a,b) usc_OutReg((a), RCSR, (b))
678
679#define usc_SetTransmitSyncChars(a,s0,s1) usc_OutReg((a), TSR, (u16)(((u16)s0<<8)|(u16)s1))
680
681static void usc_process_rxoverrun_sync( struct mgsl_struct *info );
682static void usc_start_receiver( struct mgsl_struct *info );
683static void usc_stop_receiver( struct mgsl_struct *info );
684
685static void usc_start_transmitter( struct mgsl_struct *info );
686static void usc_stop_transmitter( struct mgsl_struct *info );
687static void usc_set_txidle( struct mgsl_struct *info );
688static void usc_load_txfifo( struct mgsl_struct *info );
689
690static void usc_enable_aux_clock( struct mgsl_struct *info, u32 DataRate );
691static void usc_enable_loopback( struct mgsl_struct *info, int enable );
692
693static void usc_get_serial_signals( struct mgsl_struct *info );
694static void usc_set_serial_signals( struct mgsl_struct *info );
695
696static void usc_reset( struct mgsl_struct *info );
697
698static void usc_set_sync_mode( struct mgsl_struct *info );
699static void usc_set_sdlc_mode( struct mgsl_struct *info );
700static void usc_set_async_mode( struct mgsl_struct *info );
701static void usc_enable_async_clock( struct mgsl_struct *info, u32 DataRate );
702
703static void usc_loopback_frame( struct mgsl_struct *info );
704
705static void mgsl_tx_timeout(unsigned long context);
706
707
708static void usc_loopmode_cancel_transmit( struct mgsl_struct * info );
709static void usc_loopmode_insert_request( struct mgsl_struct * info );
710static int usc_loopmode_active( struct mgsl_struct * info);
711static void usc_loopmode_send_done( struct mgsl_struct * info );
712
713static int mgsl_ioctl_common(struct mgsl_struct *info, unsigned int cmd, unsigned long arg);
714
af69c7f9 715#if SYNCLINK_GENERIC_HDLC
1da177e4
LT		 716#define dev_to_port(D) (dev_to_hdlc(D)->priv)
717static void hdlcdev_tx_done(struct mgsl_struct *info);
718static void hdlcdev_rx(struct mgsl_struct *info, char *buf, int size);
719static int hdlcdev_init(struct mgsl_struct *info);
720static void hdlcdev_exit(struct mgsl_struct *info);
721#endif
722
723/*
724 * Defines a BUS descriptor value for the PCI adapter
725 * local bus address ranges.
726 */
727
728#define BUS_DESCRIPTOR( WrHold, WrDly, RdDly, Nwdd, Nwad, Nxda, Nrdd, Nrad ) \
729(0x00400020 + \
730((WrHold) << 30) + \
731((WrDly) << 28) + \
732((RdDly) << 26) + \
733((Nwdd) << 20) + \
734((Nwad) << 15) + \
735((Nxda) << 13) + \
736((Nrdd) << 11) + \
737((Nrad) << 6) )
738
739static void mgsl_trace_block(struct mgsl_struct *info,const char* data, int count, int xmit);
740
741/*
742 * Adapter diagnostic routines
743 */
0fab6de0
JP		 744static bool mgsl_register_test( struct mgsl_struct *info );
745static bool mgsl_irq_test( struct mgsl_struct *info );
746static bool mgsl_dma_test( struct mgsl_struct *info );
747static bool mgsl_memory_test( struct mgsl_struct *info );
1da177e4
LT		 748static int mgsl_adapter_test( struct mgsl_struct *info );
749
750/*
751 * device and resource management routines
752 */
753static int mgsl_claim_resources(struct mgsl_struct *info);
754static void mgsl_release_resources(struct mgsl_struct *info);
755static void mgsl_add_device(struct mgsl_struct *info);
756static struct mgsl_struct* mgsl_allocate_device(void);
757
758/*
759 * DMA buffer manupulation functions.
760 */
761static void mgsl_free_rx_frame_buffers( struct mgsl_struct *info, unsigned int StartIndex, unsigned int EndIndex );
0fab6de0
JP		 762static bool mgsl_get_rx_frame( struct mgsl_struct *info );
763static bool mgsl_get_raw_rx_frame( struct mgsl_struct *info );
1da177e4
LT		 764static void mgsl_reset_rx_dma_buffers( struct mgsl_struct *info );
765static void mgsl_reset_tx_dma_buffers( struct mgsl_struct *info );
766static int num_free_tx_dma_buffers(struct mgsl_struct *info);
767static void mgsl_load_tx_dma_buffer( struct mgsl_struct *info, const char *Buffer, unsigned int BufferSize);
768static void mgsl_load_pci_memory(char* TargetPtr, const char* SourcePtr, unsigned short count);
769
770/*
771 * DMA and Shared Memory buffer allocation and formatting
772 */
773static int mgsl_allocate_dma_buffers(struct mgsl_struct *info);
774static void mgsl_free_dma_buffers(struct mgsl_struct *info);
775static int mgsl_alloc_frame_memory(struct mgsl_struct *info, DMABUFFERENTRY *BufferList,int Buffercount);
776static void mgsl_free_frame_memory(struct mgsl_struct *info, DMABUFFERENTRY *BufferList,int Buffercount);
777static int mgsl_alloc_buffer_list_memory(struct mgsl_struct *info);
778static void mgsl_free_buffer_list_memory(struct mgsl_struct *info);
779static int mgsl_alloc_intermediate_rxbuffer_memory(struct mgsl_struct *info);
780static void mgsl_free_intermediate_rxbuffer_memory(struct mgsl_struct *info);
781static int mgsl_alloc_intermediate_txbuffer_memory(struct mgsl_struct *info);
782static void mgsl_free_intermediate_txbuffer_memory(struct mgsl_struct *info);
0fab6de0 783static bool load_next_tx_holding_buffer(struct mgsl_struct *info);
1da177e4
LT		 784static int save_tx_buffer_request(struct mgsl_struct *info,const char *Buffer, unsigned int BufferSize);
785
786/*
787 * Bottom half interrupt handlers
788 */
c4028958 789static void mgsl_bh_handler(struct work_struct *work);
1da177e4
LT		 790static void mgsl_bh_receive(struct mgsl_struct *info);
791static void mgsl_bh_transmit(struct mgsl_struct *info);
792static void mgsl_bh_status(struct mgsl_struct *info);
793
794/*
795 * Interrupt handler routines and dispatch table.
796 */
797static void mgsl_isr_null( struct mgsl_struct *info );
798static void mgsl_isr_transmit_data( struct mgsl_struct *info );
799static void mgsl_isr_receive_data( struct mgsl_struct *info );
800static void mgsl_isr_receive_status( struct mgsl_struct *info );
801static void mgsl_isr_transmit_status( struct mgsl_struct *info );
802static void mgsl_isr_io_pin( struct mgsl_struct *info );
803static void mgsl_isr_misc( struct mgsl_struct *info );
804static void mgsl_isr_receive_dma( struct mgsl_struct *info );
805static void mgsl_isr_transmit_dma( struct mgsl_struct *info );
806
807typedef void (*isr_dispatch_func)(struct mgsl_struct *);
808
809static isr_dispatch_func UscIsrTable[7] =
810{
811 mgsl_isr_null,
812 mgsl_isr_misc,
813 mgsl_isr_io_pin,
814 mgsl_isr_transmit_data,
815 mgsl_isr_transmit_status,
816 mgsl_isr_receive_data,
817 mgsl_isr_receive_status
818};
819
820/*
821 * ioctl call handlers
822 */
60b33c13 823static int tiocmget(struct tty_struct *tty);
20b9d177 824static int tiocmset(struct tty_struct *tty,
1da177e4
LT		 825 unsigned int set, unsigned int clear);
826static int mgsl_get_stats(struct mgsl_struct * info, struct mgsl_icount
827 __user *user_icount);
828static int mgsl_get_params(struct mgsl_struct * info, MGSL_PARAMS __user *user_params);
829static int mgsl_set_params(struct mgsl_struct * info, MGSL_PARAMS __user *new_params);
830static int mgsl_get_txidle(struct mgsl_struct * info, int __user *idle_mode);
831static int mgsl_set_txidle(struct mgsl_struct * info, int idle_mode);
832static int mgsl_txenable(struct mgsl_struct * info, int enable);
833static int mgsl_txabort(struct mgsl_struct * info);
834static int mgsl_rxenable(struct mgsl_struct * info, int enable);
835static int mgsl_wait_event(struct mgsl_struct * info, int __user *mask);
836static int mgsl_loopmode_send_done( struct mgsl_struct * info );
837
838/* set non-zero on successful registration with PCI subsystem */
0fab6de0 839static bool pci_registered;
1da177e4
LT		 840
841/*
842 * Global linked list of SyncLink devices
843 */
844static struct mgsl_struct *mgsl_device_list;
845static int mgsl_device_count;
846
847/*
848 * Set this param to non-zero to load eax with the
849 * .text section address and breakpoint on module load.
850 * This is useful for use with gdb and add-symbol-file command.
851 */
90ab5ee9 852static bool break_on_load;
1da177e4
LT		 853
854/*
855 * Driver major number, defaults to zero to get auto
856 * assigned major number. May be forced as module parameter.
857 */
858static int ttymajor;
859
860/*
861 * Array of user specified options for ISA adapters.
862 */
863static int io[MAX_ISA_DEVICES];
864static int irq[MAX_ISA_DEVICES];
865static int dma[MAX_ISA_DEVICES];
866static int debug_level;
867static int maxframe[MAX_TOTAL_DEVICES];
1da177e4
LT		 868static int txdmabufs[MAX_TOTAL_DEVICES];
869static int txholdbufs[MAX_TOTAL_DEVICES];
870
871module_param(break_on_load, bool, 0);
872module_param(ttymajor, int, 0);
3b60daf8
DH		 873module_param_hw_array(io, int, ioport, NULL, 0);
874module_param_hw_array(irq, int, irq, NULL, 0);
875module_param_hw_array(dma, int, dma, NULL, 0);
1da177e4
LT		 876module_param(debug_level, int, 0);
877module_param_array(maxframe, int, NULL, 0);
1da177e4
LT		 878module_param_array(txdmabufs, int, NULL, 0);
879module_param_array(txholdbufs, int, NULL, 0);
880
881static char *driver_name = "SyncLink serial driver";
0ff1b2c8 882static char *driver_version = "$Revision: 4.38 $";
1da177e4
LT		 883
884static int synclink_init_one (struct pci_dev *dev,
885 const struct pci_device_id *ent);
886static void synclink_remove_one (struct pci_dev *dev);
887
ba38aac1 888static const struct pci_device_id synclink_pci_tbl[] = {
1da177e4
LT		 889 { PCI_VENDOR_ID_MICROGATE, PCI_DEVICE_ID_MICROGATE_USC, PCI_ANY_ID, PCI_ANY_ID, },
890 { PCI_VENDOR_ID_MICROGATE, 0x0210, PCI_ANY_ID, PCI_ANY_ID, },
891 { 0, }, /* terminate list */
892};
893MODULE_DEVICE_TABLE(pci, synclink_pci_tbl);
894
895MODULE_LICENSE("GPL");
896
897static struct pci_driver synclink_pci_driver = {
898 .name = "synclink",
899 .id_table = synclink_pci_tbl,
900 .probe = synclink_init_one,
91116cba 901 .remove = synclink_remove_one,
1da177e4
LT		 902};
903
904static struct tty_driver *serial_driver;
905
906/* number of characters left in xmit buffer before we ask for more */
907#define WAKEUP_CHARS 256
908
909
910static void mgsl_change_params(struct mgsl_struct *info);
911static void mgsl_wait_until_sent(struct tty_struct *tty, int timeout);
912
913/*
914 * 1st function defined in .text section. Calling this function in
915 * init_module() followed by a breakpoint allows a remote debugger
916 * (gdb) to get the .text address for the add-symbol-file command.
917 * This allows remote debugging of dynamically loadable modules.
918 */
919static void* mgsl_get_text_ptr(void)
920{
921 return mgsl_get_text_ptr;
922}
923
1da177e4
LT		 924static inline int mgsl_paranoia_check(struct mgsl_struct *info,
925 char *name, const char *routine)
926{
927#ifdef MGSL_PARANOIA_CHECK
928 static const char *badmagic =
929 "Warning: bad magic number for mgsl struct (%s) in %s\n";
930 static const char *badinfo =
931 "Warning: null mgsl_struct for (%s) in %s\n";
932
933 if (!info) {
934 printk(badinfo, name, routine);
935 return 1;
936 }
937 if (info->magic != MGSL_MAGIC) {
938 printk(badmagic, name, routine);
939 return 1;
940 }
941#else
942 if (!info)
943 return 1;
944#endif
945 return 0;
946}
947
948/**
949 * line discipline callback wrappers
950 *
951 * The wrappers maintain line discipline references
952 * while calling into the line discipline.
953 *
954 * ldisc_receive_buf - pass receive data to line discipline
955 */
956
957static void ldisc_receive_buf(struct tty_struct *tty,
958 const __u8 *data, char *flags, int count)
959{
960 struct tty_ldisc *ld;
961 if (!tty)
962 return;
963 ld = tty_ldisc_ref(tty);
964 if (ld) {
a352def2
AC		 965 if (ld->ops->receive_buf)
966 ld->ops->receive_buf(tty, data, flags, count);
1da177e4
LT		 967 tty_ldisc_deref(ld);
968 }
969}
970
971/* mgsl_stop() throttle (stop) transmitter
972 *
973 * Arguments: tty pointer to tty info structure
974 * Return Value: None
975 */
976static void mgsl_stop(struct tty_struct *tty)
977{
c9f19e96 978 struct mgsl_struct *info = tty->driver_data;
1da177e4
LT		 979 unsigned long flags;
980
981 if (mgsl_paranoia_check(info, tty->name, "mgsl_stop"))
982 return;
983
984 if ( debug_level >= DEBUG_LEVEL_INFO )
985 printk("mgsl_stop(%s)\n",info->device_name);
986
987 spin_lock_irqsave(&info->irq_spinlock,flags);
988 if (info->tx_enabled)
989 usc_stop_transmitter(info);
990 spin_unlock_irqrestore(&info->irq_spinlock,flags);
991
992} /* end of mgsl_stop() */
993
994/* mgsl_start() release (start) transmitter
995 *
996 * Arguments: tty pointer to tty info structure
997 * Return Value: None
998 */
999static void mgsl_start(struct tty_struct *tty)
1000{
c9f19e96 1001 struct mgsl_struct *info = tty->driver_data;
1da177e4
LT		 1002 unsigned long flags;
1003
1004 if (mgsl_paranoia_check(info, tty->name, "mgsl_start"))
1005 return;
1006
1007 if ( debug_level >= DEBUG_LEVEL_INFO )
1008 printk("mgsl_start(%s)\n",info->device_name);
1009
1010 spin_lock_irqsave(&info->irq_spinlock,flags);
1011 if (!info->tx_enabled)
1012 usc_start_transmitter(info);
1013 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1014
1015} /* end of mgsl_start() */
1016
1017/*
1018 * Bottom half work queue access functions
1019 */
1020
1021/* mgsl_bh_action() Return next bottom half action to perform.
1022 * Return Value: BH action code or 0 if nothing to do.
1023 */
1024static int mgsl_bh_action(struct mgsl_struct *info)
1025{
1026 unsigned long flags;
1027 int rc = 0;
1028
1029 spin_lock_irqsave(&info->irq_spinlock,flags);
1030
1031 if (info->pending_bh & BH_RECEIVE) {
1032 info->pending_bh &= ~BH_RECEIVE;
1033 rc = BH_RECEIVE;
1034 } else if (info->pending_bh & BH_TRANSMIT) {
1035 info->pending_bh &= ~BH_TRANSMIT;
1036 rc = BH_TRANSMIT;
1037 } else if (info->pending_bh & BH_STATUS) {
1038 info->pending_bh &= ~BH_STATUS;
1039 rc = BH_STATUS;
1040 }
1041
1042 if (!rc) {
1043 /* Mark BH routine as complete */
0fab6de0
JP		 1044 info->bh_running = false;
1045 info->bh_requested = false;
1da177e4
LT		 1046 }
1047
1048 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1049
1050 return rc;
1051}
1052
1053/*
1054 * Perform bottom half processing of work items queued by ISR.
1055 */
c4028958 1056static void mgsl_bh_handler(struct work_struct *work)
1da177e4 1057{
c4028958
DH		 1058 struct mgsl_struct *info =
1059 container_of(work, struct mgsl_struct, task);
1da177e4
LT		 1060 int action;
1061
1da177e4
LT		 1062 if ( debug_level >= DEBUG_LEVEL_BH )
1063 printk( "%s(%d):mgsl_bh_handler(%s) entry\n",
1064 __FILE__,__LINE__,info->device_name);
1065
0fab6de0 1066 info->bh_running = true;
1da177e4
LT		 1067
1068 while((action = mgsl_bh_action(info)) != 0) {
1069
1070 /* Process work item */
1071 if ( debug_level >= DEBUG_LEVEL_BH )
1072 printk( "%s(%d):mgsl_bh_handler() work item action=%d\n",
1073 __FILE__,__LINE__,action);
1074
1075 switch (action) {
1076
1077 case BH_RECEIVE:
1078 mgsl_bh_receive(info);
1079 break;
1080 case BH_TRANSMIT:
1081 mgsl_bh_transmit(info);
1082 break;
1083 case BH_STATUS:
1084 mgsl_bh_status(info);
1085 break;
1086 default:
1087 /* unknown work item ID */
1088 printk("Unknown work item ID=%08X!\n", action);
1089 break;
1090 }
1091 }
1092
1093 if ( debug_level >= DEBUG_LEVEL_BH )
1094 printk( "%s(%d):mgsl_bh_handler(%s) exit\n",
1095 __FILE__,__LINE__,info->device_name);
1096}
1097
1098static void mgsl_bh_receive(struct mgsl_struct *info)
1099{
0fab6de0 1100 bool (*get_rx_frame)(struct mgsl_struct *info) =
1da177e4
LT		 1101 (info->params.mode == MGSL_MODE_HDLC ? mgsl_get_rx_frame : mgsl_get_raw_rx_frame);
1102
1103 if ( debug_level >= DEBUG_LEVEL_BH )
1104 printk( "%s(%d):mgsl_bh_receive(%s)\n",
1105 __FILE__,__LINE__,info->device_name);
1106
1107 do
1108 {
1109 if (info->rx_rcc_underrun) {
1110 unsigned long flags;
1111 spin_lock_irqsave(&info->irq_spinlock,flags);
1112 usc_start_receiver(info);
1113 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1114 return;
1115 }
1116 } while(get_rx_frame(info));
1117}
1118
1119static void mgsl_bh_transmit(struct mgsl_struct *info)
1120{
8fb06c77 1121 struct tty_struct *tty = info->port.tty;
1da177e4
LT		 1122 unsigned long flags;
1123
1124 if ( debug_level >= DEBUG_LEVEL_BH )
1125 printk( "%s(%d):mgsl_bh_transmit() entry on %s\n",
1126 __FILE__,__LINE__,info->device_name);
1127
b963a844 1128 if (tty)
1da177e4 1129 tty_wakeup(tty);
1da177e4
LT		 1130
1131 /* if transmitter idle and loopmode_send_done_requested
1132 * then start echoing RxD to TxD
1133 */
1134 spin_lock_irqsave(&info->irq_spinlock,flags);
1135 if ( !info->tx_active && info->loopmode_send_done_requested )
1136 usc_loopmode_send_done( info );
1137 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1138}
1139
1140static void mgsl_bh_status(struct mgsl_struct *info)
1141{
1142 if ( debug_level >= DEBUG_LEVEL_BH )
1143 printk( "%s(%d):mgsl_bh_status() entry on %s\n",
1144 __FILE__,__LINE__,info->device_name);
1145
1146 info->ri_chkcount = 0;
1147 info->dsr_chkcount = 0;
1148 info->dcd_chkcount = 0;
1149 info->cts_chkcount = 0;
1150}
1151
1152/* mgsl_isr_receive_status()
1153 *
1154 * Service a receive status interrupt. The type of status
1155 * interrupt is indicated by the state of the RCSR.
1156 * This is only used for HDLC mode.
1157 *
1158 * Arguments: info pointer to device instance data
1159 * Return Value: None
1160 */
1161static void mgsl_isr_receive_status( struct mgsl_struct *info )
1162{
1163 u16 status = usc_InReg( info, RCSR );
1164
e06922aa 1165 if ( debug_level >= DEBUG_LEVEL_ISR )
1da177e4
LT		 1166 printk("%s(%d):mgsl_isr_receive_status status=%04X\n",
1167 __FILE__,__LINE__,status);
1168
1169 if ( (status & RXSTATUS_ABORT_RECEIVED) &&
1170 info->loopmode_insert_requested &&
1171 usc_loopmode_active(info) )
1172 {
1173 ++info->icount.rxabort;
0fab6de0 1174 info->loopmode_insert_requested = false;
1da177e4
LT		 1175
1176 /* clear CMR:13 to start echoing RxD to TxD */
1177 info->cmr_value &= ~BIT13;
1178 usc_OutReg(info, CMR, info->cmr_value);
1179
1180 /* disable received abort irq (no longer required) */
1181 usc_OutReg(info, RICR,
1182 (usc_InReg(info, RICR) & ~RXSTATUS_ABORT_RECEIVED));
1183 }
1184
e06922aa 1185 if (status & (RXSTATUS_EXITED_HUNT | RXSTATUS_IDLE_RECEIVED)) {
1da177e4
LT		 1186 if (status & RXSTATUS_EXITED_HUNT)
1187 info->icount.exithunt++;
1188 if (status & RXSTATUS_IDLE_RECEIVED)
1189 info->icount.rxidle++;
1190 wake_up_interruptible(&info->event_wait_q);
1191 }
1192
1193 if (status & RXSTATUS_OVERRUN){
1194 info->icount.rxover++;
1195 usc_process_rxoverrun_sync( info );
1196 }
1197
1198 usc_ClearIrqPendingBits( info, RECEIVE_STATUS );
1199 usc_UnlatchRxstatusBits( info, status );
1200
1201} /* end of mgsl_isr_receive_status() */
1202
1203/* mgsl_isr_transmit_status()
1204 *
1205 * Service a transmit status interrupt
1206 * HDLC mode :end of transmit frame
1207 * Async mode:all data is sent
1208 * transmit status is indicated by bits in the TCSR.
1209 *
1210 * Arguments: info pointer to device instance data
1211 * Return Value: None
1212 */
1213static void mgsl_isr_transmit_status( struct mgsl_struct *info )
1214{
1215 u16 status = usc_InReg( info, TCSR );
1216
1217 if ( debug_level >= DEBUG_LEVEL_ISR )
1218 printk("%s(%d):mgsl_isr_transmit_status status=%04X\n",
1219 __FILE__,__LINE__,status);
1220
1221 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
1222 usc_UnlatchTxstatusBits( info, status );
1223
1224 if ( status & (TXSTATUS_UNDERRUN | TXSTATUS_ABORT_SENT) )
1225 {
1226 /* finished sending HDLC abort. This may leave */
1227 /* the TxFifo with data from the aborted frame */
1228 /* so purge the TxFifo. Also shutdown the DMA */
1229 /* channel in case there is data remaining in */
1230 /* the DMA buffer */
1231 usc_DmaCmd( info, DmaCmd_ResetTxChannel );
1232 usc_RTCmd( info, RTCmd_PurgeTxFifo );
1233 }
1234
1235 if ( status & TXSTATUS_EOF_SENT )
1236 info->icount.txok++;
1237 else if ( status & TXSTATUS_UNDERRUN )
1238 info->icount.txunder++;
1239 else if ( status & TXSTATUS_ABORT_SENT )
1240 info->icount.txabort++;
1241 else
1242 info->icount.txunder++;
1243
0fab6de0 1244 info->tx_active = false;
1da177e4
LT		 1245 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
1246 del_timer(&info->tx_timer);
1247
1248 if ( info->drop_rts_on_tx_done ) {
1249 usc_get_serial_signals( info );
1250 if ( info->serial_signals & SerialSignal_RTS ) {
1251 info->serial_signals &= ~SerialSignal_RTS;
1252 usc_set_serial_signals( info );
1253 }
0fab6de0 1254 info->drop_rts_on_tx_done = false;
1da177e4
LT		 1255 }
1256
af69c7f9 1257#if SYNCLINK_GENERIC_HDLC
1da177e4
LT		 1258 if (info->netcount)
1259 hdlcdev_tx_done(info);
1260 else
1261#endif
1262 {
8fb06c77 1263 if (info->port.tty->stopped || info->port.tty->hw_stopped) {
1da177e4
LT		 1264 usc_stop_transmitter(info);
1265 return;
1266 }
1267 info->pending_bh |= BH_TRANSMIT;
1268 }
1269
1270} /* end of mgsl_isr_transmit_status() */
1271
1272/* mgsl_isr_io_pin()
1273 *
1274 * Service an Input/Output pin interrupt. The type of
1275 * interrupt is indicated by bits in the MISR
1276 *
1277 * Arguments: info pointer to device instance data
1278 * Return Value: None
1279 */
1280static void mgsl_isr_io_pin( struct mgsl_struct *info )
1281{
1282 struct mgsl_icount *icount;
1283 u16 status = usc_InReg( info, MISR );
1284
1285 if ( debug_level >= DEBUG_LEVEL_ISR )
1286 printk("%s(%d):mgsl_isr_io_pin status=%04X\n",
1287 __FILE__,__LINE__,status);
1288
1289 usc_ClearIrqPendingBits( info, IO_PIN );
1290 usc_UnlatchIostatusBits( info, status );
1291
1292 if (status & (MISCSTATUS_CTS_LATCHED | MISCSTATUS_DCD_LATCHED |
1293 MISCSTATUS_DSR_LATCHED | MISCSTATUS_RI_LATCHED) ) {
1294 icount = &info->icount;
1295 /* update input line counters */
1296 if (status & MISCSTATUS_RI_LATCHED) {
1297 if ((info->ri_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1298 usc_DisablestatusIrqs(info,SICR_RI);
1299 icount->rng++;
1300 if ( status & MISCSTATUS_RI )
1301 info->input_signal_events.ri_up++;
1302 else
1303 info->input_signal_events.ri_down++;
1304 }
1305 if (status & MISCSTATUS_DSR_LATCHED) {
1306 if ((info->dsr_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1307 usc_DisablestatusIrqs(info,SICR_DSR);
1308 icount->dsr++;
1309 if ( status & MISCSTATUS_DSR )
1310 info->input_signal_events.dsr_up++;
1311 else
1312 info->input_signal_events.dsr_down++;
1313 }
1314 if (status & MISCSTATUS_DCD_LATCHED) {
1315 if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1316 usc_DisablestatusIrqs(info,SICR_DCD);
1317 icount->dcd++;
1318 if (status & MISCSTATUS_DCD) {
1319 info->input_signal_events.dcd_up++;
1320 } else
1321 info->input_signal_events.dcd_down++;
af69c7f9 1322#if SYNCLINK_GENERIC_HDLC
fbeff3c1
KH		 1323 if (info->netcount) {
1324 if (status & MISCSTATUS_DCD)
1325 netif_carrier_on(info->netdev);
1326 else
1327 netif_carrier_off(info->netdev);
1328 }
1da177e4
LT		 1329#endif
1330 }
1331 if (status & MISCSTATUS_CTS_LATCHED)
1332 {
1333 if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1334 usc_DisablestatusIrqs(info,SICR_CTS);
1335 icount->cts++;
1336 if ( status & MISCSTATUS_CTS )
1337 info->input_signal_events.cts_up++;
1338 else
1339 info->input_signal_events.cts_down++;
1340 }
1341 wake_up_interruptible(&info->status_event_wait_q);
1342 wake_up_interruptible(&info->event_wait_q);
1343
2d68655d 1344 if (tty_port_check_carrier(&info->port) &&
1da177e4
LT		 1345 (status & MISCSTATUS_DCD_LATCHED) ) {
1346 if ( debug_level >= DEBUG_LEVEL_ISR )
1347 printk("%s CD now %s...", info->device_name,
1348 (status & MISCSTATUS_DCD) ? "on" : "off");
1349 if (status & MISCSTATUS_DCD)
8fb06c77 1350 wake_up_interruptible(&info->port.open_wait);
1da177e4
LT		 1351 else {
1352 if ( debug_level >= DEBUG_LEVEL_ISR )
1353 printk("doing serial hangup...");
8fb06c77
AC		 1354 if (info->port.tty)
1355 tty_hangup(info->port.tty);
1da177e4
LT		 1356 }
1357 }
1358
f21ec3d2 1359 if (tty_port_cts_enabled(&info->port) &&
1da177e4 1360 (status & MISCSTATUS_CTS_LATCHED) ) {
8fb06c77 1361 if (info->port.tty->hw_stopped) {
1da177e4
LT		 1362 if (status & MISCSTATUS_CTS) {
1363 if ( debug_level >= DEBUG_LEVEL_ISR )
1364 printk("CTS tx start...");
42331433 1365 info->port.tty->hw_stopped = 0;
1da177e4
LT		 1366 usc_start_transmitter(info);
1367 info->pending_bh |= BH_TRANSMIT;
1368 return;
1369 }
1370 } else {
1371 if (!(status & MISCSTATUS_CTS)) {
1372 if ( debug_level >= DEBUG_LEVEL_ISR )
1373 printk("CTS tx stop...");
8fb06c77
AC		 1374 if (info->port.tty)
1375 info->port.tty->hw_stopped = 1;
1da177e4
LT		 1376 usc_stop_transmitter(info);
1377 }
1378 }
1379 }
1380 }
1381
1382 info->pending_bh |= BH_STATUS;
1383
1384 /* for diagnostics set IRQ flag */
1385 if ( status & MISCSTATUS_TXC_LATCHED ){
1386 usc_OutReg( info, SICR,
1387 (unsigned short)(usc_InReg(info,SICR) & ~(SICR_TXC_ACTIVE+SICR_TXC_INACTIVE)) );
1388 usc_UnlatchIostatusBits( info, MISCSTATUS_TXC_LATCHED );
0fab6de0 1389 info->irq_occurred = true;
1da177e4
LT		 1390 }
1391
1392} /* end of mgsl_isr_io_pin() */
1393
1394/* mgsl_isr_transmit_data()
1395 *
1396 * Service a transmit data interrupt (async mode only).
1397 *
1398 * Arguments: info pointer to device instance data
1399 * Return Value: None
1400 */
1401static void mgsl_isr_transmit_data( struct mgsl_struct *info )
1402{
1403 if ( debug_level >= DEBUG_LEVEL_ISR )
1404 printk("%s(%d):mgsl_isr_transmit_data xmit_cnt=%d\n",
1405 __FILE__,__LINE__,info->xmit_cnt);
1406
1407 usc_ClearIrqPendingBits( info, TRANSMIT_DATA );
1408
8fb06c77 1409 if (info->port.tty->stopped || info->port.tty->hw_stopped) {
1da177e4
LT		 1410 usc_stop_transmitter(info);
1411 return;
1412 }
1413
1414 if ( info->xmit_cnt )
1415 usc_load_txfifo( info );
1416 else
0fab6de0 1417 info->tx_active = false;
1da177e4
LT		 1418
1419 if (info->xmit_cnt < WAKEUP_CHARS)
1420 info->pending_bh |= BH_TRANSMIT;
1421
1422} /* end of mgsl_isr_transmit_data() */
1423
1424/* mgsl_isr_receive_data()
1425 *
1426 * Service a receive data interrupt. This occurs
1427 * when operating in asynchronous interrupt transfer mode.
1428 * The receive data FIFO is flushed to the receive data buffers.
1429 *
1430 * Arguments: info pointer to device instance data
1431 * Return Value: None
1432 */
1433static void mgsl_isr_receive_data( struct mgsl_struct *info )
1434{
1435 int Fifocount;
1436 u16 status;
33f0f88f 1437 int work = 0;
1da177e4 1438 unsigned char DataByte;
1da177e4
LT		 1439 struct mgsl_icount *icount = &info->icount;
1440
1441 if ( debug_level >= DEBUG_LEVEL_ISR )
1442 printk("%s(%d):mgsl_isr_receive_data\n",
1443 __FILE__,__LINE__);
1444
1445 usc_ClearIrqPendingBits( info, RECEIVE_DATA );
1446
1447 /* select FIFO status for RICR readback */
1448 usc_RCmd( info, RCmd_SelectRicrRxFifostatus );
1449
1450 /* clear the Wordstatus bit so that status readback */
1451 /* only reflects the status of this byte */
1452 usc_OutReg( info, RICR+LSBONLY, (u16)(usc_InReg(info, RICR+LSBONLY) & ~BIT3 ));
1453
1454 /* flush the receive FIFO */
1455
1456 while( (Fifocount = (usc_InReg(info,RICR) >> 8)) ) {
33f0f88f
AC		 1457 int flag;
1458
1da177e4
LT		 1459 /* read one byte from RxFIFO */
1460 outw( (inw(info->io_base + CCAR) & 0x0780) | (RDR+LSBONLY),
1461 info->io_base + CCAR );
1462 DataByte = inb( info->io_base + CCAR );
1463
1464 /* get the status of the received byte */
1465 status = usc_InReg(info, RCSR);
e06922aa
AJ		 1466 if ( status & (RXSTATUS_FRAMING_ERROR | RXSTATUS_PARITY_ERROR |
1467 RXSTATUS_OVERRUN | RXSTATUS_BREAK_RECEIVED) )
1da177e4
LT		 1468 usc_UnlatchRxstatusBits(info,RXSTATUS_ALL);
1469
1da177e4
LT		 1470 icount->rx++;
1471
33f0f88f 1472 flag = 0;
e06922aa
AJ		 1473 if ( status & (RXSTATUS_FRAMING_ERROR | RXSTATUS_PARITY_ERROR |
1474 RXSTATUS_OVERRUN | RXSTATUS_BREAK_RECEIVED) ) {
1475 printk("rxerr=%04X\n",status);
1da177e4
LT		 1476 /* update error statistics */
1477 if ( status & RXSTATUS_BREAK_RECEIVED ) {
e06922aa 1478 status &= ~(RXSTATUS_FRAMING_ERROR | RXSTATUS_PARITY_ERROR);
1da177e4 1479 icount->brk++;
e06922aa 1480 } else if (status & RXSTATUS_PARITY_ERROR)
1da177e4
LT		 1481 icount->parity++;
1482 else if (status & RXSTATUS_FRAMING_ERROR)
1483 icount->frame++;
1484 else if (status & RXSTATUS_OVERRUN) {
1485 /* must issue purge fifo cmd before */
1486 /* 16C32 accepts more receive chars */
1487 usc_RTCmd(info,RTCmd_PurgeRxFifo);
1488 icount->overrun++;
1489 }
1490
e06922aa 1491 /* discard char if tty control flags say so */
1da177e4
LT		 1492 if (status & info->ignore_status_mask)
1493 continue;
1494
1495 status &= info->read_status_mask;
1496
1497 if (status & RXSTATUS_BREAK_RECEIVED) {
33f0f88f 1498 flag = TTY_BREAK;
8fb06c77 1499 if (info->port.flags & ASYNC_SAK)
2e124b4a 1500 do_SAK(info->port.tty);
1da177e4 1501 } else if (status & RXSTATUS_PARITY_ERROR)
33f0f88f 1502 flag = TTY_PARITY;
1da177e4 1503 else if (status & RXSTATUS_FRAMING_ERROR)
33f0f88f 1504 flag = TTY_FRAME;
1da177e4 1505 } /* end of if (error) */
92a19f9c 1506 tty_insert_flip_char(&info->port, DataByte, flag);
33f0f88f
AC		 1507 if (status & RXSTATUS_OVERRUN) {
1508 /* Overrun is special, since it's
1509 * reported immediately, and doesn't
1510 * affect the current character
1511 */
92a19f9c 1512 work += tty_insert_flip_char(&info->port, 0, TTY_OVERRUN);
33f0f88f 1513 }
1da177e4
LT		 1514 }
1515
1516 if ( debug_level >= DEBUG_LEVEL_ISR ) {
1da177e4
LT		 1517 printk("%s(%d):rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
1518 __FILE__,__LINE__,icount->rx,icount->brk,
1519 icount->parity,icount->frame,icount->overrun);
1520 }
1521
33f0f88f 1522 if(work)
2e124b4a 1523 tty_flip_buffer_push(&info->port);
1da177e4
LT		 1524}
1525
1526/* mgsl_isr_misc()
1527 *
8dfba4d7 1528 * Service a miscellaneous interrupt source.
1da177e4
LT		 1529 *
1530 * Arguments: info pointer to device extension (instance data)
1531 * Return Value: None
1532 */
1533static void mgsl_isr_misc( struct mgsl_struct *info )
1534{
1535 u16 status = usc_InReg( info, MISR );
1536
1537 if ( debug_level >= DEBUG_LEVEL_ISR )
1538 printk("%s(%d):mgsl_isr_misc status=%04X\n",
1539 __FILE__,__LINE__,status);
1540
1541 if ((status & MISCSTATUS_RCC_UNDERRUN) &&
1542 (info->params.mode == MGSL_MODE_HDLC)) {
1543
1544 /* turn off receiver and rx DMA */
1545 usc_EnableReceiver(info,DISABLE_UNCONDITIONAL);
1546 usc_DmaCmd(info, DmaCmd_ResetRxChannel);
1547 usc_UnlatchRxstatusBits(info, RXSTATUS_ALL);
e06922aa
AJ		 1548 usc_ClearIrqPendingBits(info, RECEIVE_DATA | RECEIVE_STATUS);
1549 usc_DisableInterrupts(info, RECEIVE_DATA | RECEIVE_STATUS);
1da177e4
LT		 1550
1551 /* schedule BH handler to restart receiver */
1552 info->pending_bh |= BH_RECEIVE;
0fab6de0 1553 info->rx_rcc_underrun = true;
1da177e4
LT		 1554 }
1555
1556 usc_ClearIrqPendingBits( info, MISC );
1557 usc_UnlatchMiscstatusBits( info, status );
1558
1559} /* end of mgsl_isr_misc() */
1560
1561/* mgsl_isr_null()
1562 *
1563 * Services undefined interrupt vectors from the
1564 * USC. (hence this function SHOULD never be called)
1565 *
1566 * Arguments: info pointer to device extension (instance data)
1567 * Return Value: None
1568 */
1569static void mgsl_isr_null( struct mgsl_struct *info )
1570{
1571
1572} /* end of mgsl_isr_null() */
1573
1574/* mgsl_isr_receive_dma()
1575 *
1576 * Service a receive DMA channel interrupt.
1577 * For this driver there are two sources of receive DMA interrupts
1578 * as identified in the Receive DMA mode Register (RDMR):
1579 *
1580 * BIT3 EOA/EOL End of List, all receive buffers in receive
1581 * buffer list have been filled (no more free buffers
1582 * available). The DMA controller has shut down.
1583 *
1584 * BIT2 EOB End of Buffer. This interrupt occurs when a receive
1585 * DMA buffer is terminated in response to completion
1586 * of a good frame or a frame with errors. The status
1587 * of the frame is stored in the buffer entry in the
1588 * list of receive buffer entries.
1589 *
1590 * Arguments: info pointer to device instance data
1591 * Return Value: None
1592 */
1593static void mgsl_isr_receive_dma( struct mgsl_struct *info )
1594{
1595 u16 status;
1596
1597 /* clear interrupt pending and IUS bit for Rx DMA IRQ */
e06922aa 1598 usc_OutDmaReg( info, CDIR, BIT9 | BIT1 );
1da177e4
LT		 1599
1600 /* Read the receive DMA status to identify interrupt type. */
1601 /* This also clears the status bits. */
1602 status = usc_InDmaReg( info, RDMR );
1603
1604 if ( debug_level >= DEBUG_LEVEL_ISR )
1605 printk("%s(%d):mgsl_isr_receive_dma(%s) status=%04X\n",
1606 __FILE__,__LINE__,info->device_name,status);
1607
1608 info->pending_bh |= BH_RECEIVE;
1609
1610 if ( status & BIT3 ) {
0fab6de0 1611 info->rx_overflow = true;
1da177e4
LT		 1612 info->icount.buf_overrun++;
1613 }
1614
1615} /* end of mgsl_isr_receive_dma() */
1616
1617/* mgsl_isr_transmit_dma()
1618 *
1619 * This function services a transmit DMA channel interrupt.
1620 *
1621 * For this driver there is one source of transmit DMA interrupts
1622 * as identified in the Transmit DMA Mode Register (TDMR):
1623 *
1624 * BIT2 EOB End of Buffer. This interrupt occurs when a
1625 * transmit DMA buffer has been emptied.
1626 *
1627 * The driver maintains enough transmit DMA buffers to hold at least
1628 * one max frame size transmit frame. When operating in a buffered
1629 * transmit mode, there may be enough transmit DMA buffers to hold at
1630 * least two or more max frame size frames. On an EOB condition,
1631 * determine if there are any queued transmit buffers and copy into
1632 * transmit DMA buffers if we have room.
1633 *
1634 * Arguments: info pointer to device instance data
1635 * Return Value: None
1636 */
1637static void mgsl_isr_transmit_dma( struct mgsl_struct *info )
1638{
1639 u16 status;
1640
1641 /* clear interrupt pending and IUS bit for Tx DMA IRQ */
e06922aa 1642 usc_OutDmaReg(info, CDIR, BIT8 | BIT0 );
1da177e4
LT		 1643
1644 /* Read the transmit DMA status to identify interrupt type. */
1645 /* This also clears the status bits. */
1646
1647 status = usc_InDmaReg( info, TDMR );
1648
1649 if ( debug_level >= DEBUG_LEVEL_ISR )
1650 printk("%s(%d):mgsl_isr_transmit_dma(%s) status=%04X\n",
1651 __FILE__,__LINE__,info->device_name,status);
1652
1653 if ( status & BIT2 ) {
1654 --info->tx_dma_buffers_used;
1655
1656 /* if there are transmit frames queued,
1657 * try to load the next one
1658 */
1659 if ( load_next_tx_holding_buffer(info) ) {
1660 /* if call returns non-zero value, we have
1661 * at least one free tx holding buffer
1662 */
1663 info->pending_bh |= BH_TRANSMIT;
1664 }
1665 }
1666
1667} /* end of mgsl_isr_transmit_dma() */
1668
1669/* mgsl_interrupt()
1670 *
1671 * Interrupt service routine entry point.
1672 *
1673 * Arguments:
1674 *
1675 * irq interrupt number that caused interrupt
1676 * dev_id device ID supplied during interrupt registration
1da177e4
LT		 1677 *
1678 * Return Value: None
1679 */
a6f97b29 1680static irqreturn_t mgsl_interrupt(int dummy, void *dev_id)
1da177e4 1681{
a6f97b29 1682 struct mgsl_struct *info = dev_id;
1da177e4
LT		 1683 u16 UscVector;
1684 u16 DmaVector;
1685
1686 if ( debug_level >= DEBUG_LEVEL_ISR )
a6f97b29
JG		 1687 printk(KERN_DEBUG "%s(%d):mgsl_interrupt(%d)entry.\n",
1688 __FILE__, __LINE__, info->irq_level);
1da177e4 1689
1da177e4
LT		 1690 spin_lock(&info->irq_spinlock);
1691
1692 for(;;) {
1693 /* Read the interrupt vectors from hardware. */
1694 UscVector = usc_InReg(info, IVR) >> 9;
1695 DmaVector = usc_InDmaReg(info, DIVR);
1696
1697 if ( debug_level >= DEBUG_LEVEL_ISR )
1698 printk("%s(%d):%s UscVector=%08X DmaVector=%08X\n",
1699 __FILE__,__LINE__,info->device_name,UscVector,DmaVector);
1700
1701 if ( !UscVector && !DmaVector )
1702 break;
1703
1704 /* Dispatch interrupt vector */
1705 if ( UscVector )
1706 (*UscIsrTable[UscVector])(info);
1707 else if ( (DmaVector&(BIT10|BIT9)) == BIT10)
1708 mgsl_isr_transmit_dma(info);
1709 else
1710 mgsl_isr_receive_dma(info);
1711
1712 if ( info->isr_overflow ) {
a6f97b29
JG		 1713 printk(KERN_ERR "%s(%d):%s isr overflow irq=%d\n",
1714 __FILE__, __LINE__, info->device_name, info->irq_level);
1da177e4
LT		 1715 usc_DisableMasterIrqBit(info);
1716 usc_DisableDmaInterrupts(info,DICR_MASTER);
1717 break;
1718 }
1719 }
1720
1721 /* Request bottom half processing if there's something
1722 * for it to do and the bh is not already running
1723 */
1724
1725 if ( info->pending_bh && !info->bh_running && !info->bh_requested ) {
1726 if ( debug_level >= DEBUG_LEVEL_ISR )
1727 printk("%s(%d):%s queueing bh task.\n",
1728 __FILE__,__LINE__,info->device_name);
1729 schedule_work(&info->task);
0fab6de0 1730 info->bh_requested = true;
1da177e4
LT		 1731 }
1732
1733 spin_unlock(&info->irq_spinlock);
1734
1735 if ( debug_level >= DEBUG_LEVEL_ISR )
a6f97b29
JG		 1736 printk(KERN_DEBUG "%s(%d):mgsl_interrupt(%d)exit.\n",
1737 __FILE__, __LINE__, info->irq_level);
1738
1da177e4
LT		 1739 return IRQ_HANDLED;
1740} /* end of mgsl_interrupt() */
1741
1742/* startup()
1743 *
1744 * Initialize and start device.
1745 *
1746 * Arguments: info pointer to device instance data
1747 * Return Value: 0 if success, otherwise error code
1748 */
1749static int startup(struct mgsl_struct * info)
1750{
1751 int retval = 0;
d41861ca 1752
1da177e4
LT		 1753 if ( debug_level >= DEBUG_LEVEL_INFO )
1754 printk("%s(%d):mgsl_startup(%s)\n",__FILE__,__LINE__,info->device_name);
d41861ca
PH		 1755
1756 if (tty_port_initialized(&info->port))
1da177e4 1757 return 0;
d41861ca 1758
1da177e4
LT		 1759 if (!info->xmit_buf) {
1760 /* allocate a page of memory for a transmit buffer */
1761 info->xmit_buf = (unsigned char *)get_zeroed_page(GFP_KERNEL);
1762 if (!info->xmit_buf) {
1763 printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n",
1764 __FILE__,__LINE__,info->device_name);
1765 return -ENOMEM;
1766 }
1767 }
1768
1769 info->pending_bh = 0;
1770
9661239f
PF		 1771 memset(&info->icount, 0, sizeof(info->icount));
1772
40565f19 1773 setup_timer(&info->tx_timer, mgsl_tx_timeout, (unsigned long)info);
1da177e4
LT		 1774
1775 /* Allocate and claim adapter resources */
1776 retval = mgsl_claim_resources(info);
1777
1778 /* perform existence check and diagnostics */
1779 if ( !retval )
1780 retval = mgsl_adapter_test(info);
1781
1782 if ( retval ) {
8fb06c77
AC		 1783 if (capable(CAP_SYS_ADMIN) && info->port.tty)
1784 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
1da177e4
LT		 1785 mgsl_release_resources(info);
1786 return retval;
1787 }
1788
1789 /* program hardware for current parameters */
1790 mgsl_change_params(info);
d41861ca 1791
8fb06c77
AC		 1792 if (info->port.tty)
1793 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
1da177e4 1794
d41861ca
PH		 1795 tty_port_set_initialized(&info->port, 1);
1796
1da177e4 1797 return 0;
1da177e4
LT		 1798} /* end of startup() */
1799
1800/* shutdown()
1801 *
1802 * Called by mgsl_close() and mgsl_hangup() to shutdown hardware
1803 *
1804 * Arguments: info pointer to device instance data
1805 * Return Value: None
1806 */
1807static void shutdown(struct mgsl_struct * info)
1808{
1809 unsigned long flags;
d41861ca
PH		 1810
1811 if (!tty_port_initialized(&info->port))
1da177e4
LT		 1812 return;
1813
1814 if (debug_level >= DEBUG_LEVEL_INFO)
1815 printk("%s(%d):mgsl_shutdown(%s)\n",
1816 __FILE__,__LINE__, info->device_name );
1817
1818 /* clear status wait queue because status changes */
1819 /* can't happen after shutting down the hardware */
1820 wake_up_interruptible(&info->status_event_wait_q);
1821 wake_up_interruptible(&info->event_wait_q);
1822
40565f19 1823 del_timer_sync(&info->tx_timer);
1da177e4
LT		 1824
1825 if (info->xmit_buf) {
1826 free_page((unsigned long) info->xmit_buf);
1827 info->xmit_buf = NULL;
1828 }
1829
1830 spin_lock_irqsave(&info->irq_spinlock,flags);
1831 usc_DisableMasterIrqBit(info);
1832 usc_stop_receiver(info);
1833 usc_stop_transmitter(info);
e06922aa
AJ		 1834 usc_DisableInterrupts(info,RECEIVE_DATA | RECEIVE_STATUS |
1835 TRANSMIT_DATA | TRANSMIT_STATUS | IO_PIN | MISC );
1da177e4 1836 usc_DisableDmaInterrupts(info,DICR_MASTER + DICR_TRANSMIT + DICR_RECEIVE);
adc8d746 1837
1da177e4
LT		 1838 /* Disable DMAEN (Port 7, Bit 14) */
1839 /* This disconnects the DMA request signal from the ISA bus */
1840 /* on the ISA adapter. This has no effect for the PCI adapter */
1841 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT15) | BIT14));
adc8d746 1842
1da177e4
LT		 1843 /* Disable INTEN (Port 6, Bit12) */
1844 /* This disconnects the IRQ request signal to the ISA bus */
1845 /* on the ISA adapter. This has no effect for the PCI adapter */
1846 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) | BIT12));
adc8d746
AC		 1847
1848 if (!info->port.tty || info->port.tty->termios.c_cflag & HUPCL) {
9fe8074b 1849 info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
1da177e4
LT		 1850 usc_set_serial_signals(info);
1851 }
adc8d746 1852
1da177e4
LT		 1853 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1854
d41861ca
PH		 1855 mgsl_release_resources(info);
1856
8fb06c77
AC		 1857 if (info->port.tty)
1858 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
1da177e4 1859
d41861ca 1860 tty_port_set_initialized(&info->port, 0);
1da177e4
LT		 1861} /* end of shutdown() */
1862
1863static void mgsl_program_hw(struct mgsl_struct *info)
1864{
1865 unsigned long flags;
1866
1867 spin_lock_irqsave(&info->irq_spinlock,flags);
1868
1869 usc_stop_receiver(info);
1870 usc_stop_transmitter(info);
1871 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
1872
1873 if (info->params.mode == MGSL_MODE_HDLC ||
1874 info->params.mode == MGSL_MODE_RAW ||
1875 info->netcount)
1876 usc_set_sync_mode(info);
1877 else
1878 usc_set_async_mode(info);
1879
1880 usc_set_serial_signals(info);
1881
1882 info->dcd_chkcount = 0;
1883 info->cts_chkcount = 0;
1884 info->ri_chkcount = 0;
1885 info->dsr_chkcount = 0;
1886
e06922aa 1887 usc_EnableStatusIrqs(info,SICR_CTS+SICR_DSR+SICR_DCD+SICR_RI);
1da177e4
LT		 1888 usc_EnableInterrupts(info, IO_PIN);
1889 usc_get_serial_signals(info);
1890
adc8d746 1891 if (info->netcount || info->port.tty->termios.c_cflag & CREAD)
1da177e4
LT		 1892 usc_start_receiver(info);
1893
1894 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1895}
1896
1897/* Reconfigure adapter based on new parameters
1898 */
1899static void mgsl_change_params(struct mgsl_struct *info)
1900{
1901 unsigned cflag;
1902 int bits_per_char;
1903
adc8d746 1904 if (!info->port.tty)
1da177e4
LT		 1905 return;
1906
1907 if (debug_level >= DEBUG_LEVEL_INFO)
1908 printk("%s(%d):mgsl_change_params(%s)\n",
1909 __FILE__,__LINE__, info->device_name );
1910
adc8d746 1911 cflag = info->port.tty->termios.c_cflag;
1da177e4 1912
9fe8074b
JP		 1913 /* if B0 rate (hangup) specified then negate RTS and DTR */
1914 /* otherwise assert RTS and DTR */
1da177e4 1915 if (cflag & CBAUD)
9fe8074b 1916 info->serial_signals |= SerialSignal_RTS | SerialSignal_DTR;
1da177e4 1917 else
9fe8074b 1918 info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
1da177e4
LT		 1919
1920 /* byte size and parity */
1921
1922 switch (cflag & CSIZE) {
1923 case CS5: info->params.data_bits = 5; break;
1924 case CS6: info->params.data_bits = 6; break;
1925 case CS7: info->params.data_bits = 7; break;
1926 case CS8: info->params.data_bits = 8; break;
1927 /* Never happens, but GCC is too dumb to figure it out */
1928 default: info->params.data_bits = 7; break;
1929 }
1930
1931 if (cflag & CSTOPB)
1932 info->params.stop_bits = 2;
1933 else
1934 info->params.stop_bits = 1;
1935
1936 info->params.parity = ASYNC_PARITY_NONE;
1937 if (cflag & PARENB) {
1938 if (cflag & PARODD)
1939 info->params.parity = ASYNC_PARITY_ODD;
1940 else
1941 info->params.parity = ASYNC_PARITY_EVEN;
1942#ifdef CMSPAR
1943 if (cflag & CMSPAR)
1944 info->params.parity = ASYNC_PARITY_SPACE;
1945#endif
1946 }
1947
1948 /* calculate number of jiffies to transmit a full
1949 * FIFO (32 bytes) at specified data rate
1950 */
1951 bits_per_char = info->params.data_bits +
1952 info->params.stop_bits + 1;
1953
1954 /* if port data rate is set to 460800 or less then
1955 * allow tty settings to override, otherwise keep the
1956 * current data rate.
1957 */
1958 if (info->params.data_rate <= 460800)
8fb06c77 1959 info->params.data_rate = tty_get_baud_rate(info->port.tty);
1da177e4
LT		 1960
1961 if ( info->params.data_rate ) {
1962 info->timeout = (32*HZ*bits_per_char) /
1963 info->params.data_rate;
1964 }
1965 info->timeout += HZ/50; /* Add .02 seconds of slop */
1966
5604a98e 1967 tty_port_set_cts_flow(&info->port, cflag & CRTSCTS);
2d68655d 1968 tty_port_set_check_carrier(&info->port, ~cflag & CLOCAL);
1da177e4
LT		 1969
1970 /* process tty input control flags */
1971
1972 info->read_status_mask = RXSTATUS_OVERRUN;
8fb06c77 1973 if (I_INPCK(info->port.tty))
1da177e4 1974 info->read_status_mask |= RXSTATUS_PARITY_ERROR | RXSTATUS_FRAMING_ERROR;
8fb06c77 1975 if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
1da177e4
LT		 1976 info->read_status_mask |= RXSTATUS_BREAK_RECEIVED;
1977
8fb06c77 1978 if (I_IGNPAR(info->port.tty))
1da177e4 1979 info->ignore_status_mask |= RXSTATUS_PARITY_ERROR | RXSTATUS_FRAMING_ERROR;
8fb06c77 1980 if (I_IGNBRK(info->port.tty)) {
1da177e4
LT		 1981 info->ignore_status_mask |= RXSTATUS_BREAK_RECEIVED;
1982 /* If ignoring parity and break indicators, ignore
1983 * overruns too. (For real raw support).
1984 */
8fb06c77 1985 if (I_IGNPAR(info->port.tty))
1da177e4
LT		 1986 info->ignore_status_mask |= RXSTATUS_OVERRUN;
1987 }
1988
1989 mgsl_program_hw(info);
1990
1991} /* end of mgsl_change_params() */
1992
1993/* mgsl_put_char()
1994 *
1995 * Add a character to the transmit buffer.
1996 *
1997 * Arguments: tty pointer to tty information structure
1998 * ch character to add to transmit buffer
1999 *
2000 * Return Value: None
2001 */
55da7789 2002static int mgsl_put_char(struct tty_struct *tty, unsigned char ch)
1da177e4 2003{
07648230 2004 struct mgsl_struct *info = tty->driver_data;
1da177e4 2005 unsigned long flags;
07648230 2006 int ret = 0;
1da177e4 2007
07648230 2008 if (debug_level >= DEBUG_LEVEL_INFO) {
5098021e 2009 printk(KERN_DEBUG "%s(%d):mgsl_put_char(%d) on %s\n",
07648230 2010 __FILE__, __LINE__, ch, info->device_name);
1da177e4
LT		 2011 }
2012
2013 if (mgsl_paranoia_check(info, tty->name, "mgsl_put_char"))
55da7789 2014 return 0;
1da177e4 2015
ca1cce49 2016 if (!info->xmit_buf)
55da7789 2017 return 0;
1da177e4 2018
07648230 2019 spin_lock_irqsave(&info->irq_spinlock, flags);
1da177e4 2020
07648230 2021 if ((info->params.mode == MGSL_MODE_ASYNC ) || !info->tx_active) {
1da177e4
LT		 2022 if (info->xmit_cnt < SERIAL_XMIT_SIZE - 1) {
2023 info->xmit_buf[info->xmit_head++] = ch;
2024 info->xmit_head &= SERIAL_XMIT_SIZE-1;
2025 info->xmit_cnt++;
55da7789 2026 ret = 1;
1da177e4
LT		 2027 }
2028 }
07648230 2029 spin_unlock_irqrestore(&info->irq_spinlock, flags);
55da7789 2030 return ret;
1da177e4
LT		 2031
2032} /* end of mgsl_put_char() */
2033
2034/* mgsl_flush_chars()
2035 *
2036 * Enable transmitter so remaining characters in the
2037 * transmit buffer are sent.
2038 *
2039 * Arguments: tty pointer to tty information structure
2040 * Return Value: None
2041 */
2042static void mgsl_flush_chars(struct tty_struct *tty)
2043{
c9f19e96 2044 struct mgsl_struct *info = tty->driver_data;
1da177e4
LT		 2045 unsigned long flags;
2046
2047 if ( debug_level >= DEBUG_LEVEL_INFO )
2048 printk( "%s(%d):mgsl_flush_chars() entry on %s xmit_cnt=%d\n",
2049 __FILE__,__LINE__,info->device_name,info->xmit_cnt);
2050
2051 if (mgsl_paranoia_check(info, tty->name, "mgsl_flush_chars"))
2052 return;
2053
2054 if (info->xmit_cnt <= 0 || tty->stopped || tty->hw_stopped ||
2055 !info->xmit_buf)
2056 return;
2057
2058 if ( debug_level >= DEBUG_LEVEL_INFO )
2059 printk( "%s(%d):mgsl_flush_chars() entry on %s starting transmitter\n",
2060 __FILE__,__LINE__,info->device_name );
2061
2062 spin_lock_irqsave(&info->irq_spinlock,flags);
2063
2064 if (!info->tx_active) {
2065 if ( (info->params.mode == MGSL_MODE_HDLC ||
2066 info->params.mode == MGSL_MODE_RAW) && info->xmit_cnt ) {
2067 /* operating in synchronous (frame oriented) mode */
2068 /* copy data from circular xmit_buf to */
2069 /* transmit DMA buffer. */
2070 mgsl_load_tx_dma_buffer(info,
2071 info->xmit_buf,info->xmit_cnt);
2072 }
2073 usc_start_transmitter(info);
2074 }
2075
2076 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2077
2078} /* end of mgsl_flush_chars() */
2079
2080/* mgsl_write()
2081 *
2082 * Send a block of data
2083 *
2084 * Arguments:
2085 *
2086 * tty pointer to tty information structure
2087 * buf pointer to buffer containing send data
2088 * count size of send data in bytes
2089 *
2090 * Return Value: number of characters written
2091 */
2092static int mgsl_write(struct tty_struct * tty,
2093 const unsigned char *buf, int count)
2094{
2095 int c, ret = 0;
c9f19e96 2096 struct mgsl_struct *info = tty->driver_data;
1da177e4
LT		 2097 unsigned long flags;
2098
2099 if ( debug_level >= DEBUG_LEVEL_INFO )
2100 printk( "%s(%d):mgsl_write(%s) count=%d\n",
2101 __FILE__,__LINE__,info->device_name,count);
2102
2103 if (mgsl_paranoia_check(info, tty->name, "mgsl_write"))
2104 goto cleanup;
2105
ca1cce49 2106 if (!info->xmit_buf)
1da177e4
LT		 2107 goto cleanup;
2108
2109 if ( info->params.mode == MGSL_MODE_HDLC ||
2110 info->params.mode == MGSL_MODE_RAW ) {
2111 /* operating in synchronous (frame oriented) mode */
1da177e4
LT		 2112 if (info->tx_active) {
2113
2114 if ( info->params.mode == MGSL_MODE_HDLC ) {
2115 ret = 0;
2116 goto cleanup;
2117 }
2118 /* transmitter is actively sending data -
2119 * if we have multiple transmit dma and
2120 * holding buffers, attempt to queue this
2121 * frame for transmission at a later time.
2122 */
2123 if (info->tx_holding_count >= info->num_tx_holding_buffers ) {
2124 /* no tx holding buffers available */
2125 ret = 0;
2126 goto cleanup;
2127 }
2128
2129 /* queue transmit frame request */
2130 ret = count;
2131 save_tx_buffer_request(info,buf,count);
2132
2133 /* if we have sufficient tx dma buffers,
2134 * load the next buffered tx request
2135 */
2136 spin_lock_irqsave(&info->irq_spinlock,flags);
2137 load_next_tx_holding_buffer(info);
2138 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2139 goto cleanup;
2140 }
2141
2142 /* if operating in HDLC LoopMode and the adapter */
2143 /* has yet to be inserted into the loop, we can't */
2144 /* transmit */
2145
2146 if ( (info->params.flags & HDLC_FLAG_HDLC_LOOPMODE) &&
2147 !usc_loopmode_active(info) )
2148 {
2149 ret = 0;
2150 goto cleanup;
2151 }
2152
2153 if ( info->xmit_cnt ) {
2154 /* Send accumulated from send_char() calls */
2155 /* as frame and wait before accepting more data. */
2156 ret = 0;
2157
2158 /* copy data from circular xmit_buf to */
2159 /* transmit DMA buffer. */
2160 mgsl_load_tx_dma_buffer(info,
2161 info->xmit_buf,info->xmit_cnt);
2162 if ( debug_level >= DEBUG_LEVEL_INFO )
2163 printk( "%s(%d):mgsl_write(%s) sync xmit_cnt flushing\n",
2164 __FILE__,__LINE__,info->device_name);
2165 } else {
2166 if ( debug_level >= DEBUG_LEVEL_INFO )
2167 printk( "%s(%d):mgsl_write(%s) sync transmit accepted\n",
2168 __FILE__,__LINE__,info->device_name);
2169 ret = count;
2170 info->xmit_cnt = count;
2171 mgsl_load_tx_dma_buffer(info,buf,count);
2172 }
2173 } else {
2174 while (1) {
2175 spin_lock_irqsave(&info->irq_spinlock,flags);
2176 c = min_t(int, count,
2177 min(SERIAL_XMIT_SIZE - info->xmit_cnt - 1,
2178 SERIAL_XMIT_SIZE - info->xmit_head));
2179 if (c <= 0) {
2180 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2181 break;
2182 }
2183 memcpy(info->xmit_buf + info->xmit_head, buf, c);
2184 info->xmit_head = ((info->xmit_head + c) &
2185 (SERIAL_XMIT_SIZE-1));
2186 info->xmit_cnt += c;
2187 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2188 buf += c;
2189 count -= c;
2190 ret += c;
2191 }
2192 }
2193
2194 if (info->xmit_cnt && !tty->stopped && !tty->hw_stopped) {
2195 spin_lock_irqsave(&info->irq_spinlock,flags);
2196 if (!info->tx_active)
2197 usc_start_transmitter(info);
2198 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2199 }
2200cleanup:
2201 if ( debug_level >= DEBUG_LEVEL_INFO )
2202 printk( "%s(%d):mgsl_write(%s) returning=%d\n",
2203 __FILE__,__LINE__,info->device_name,ret);
2204
2205 return ret;
2206
2207} /* end of mgsl_write() */
2208
2209/* mgsl_write_room()
2210 *
2211 * Return the count of free bytes in transmit buffer
2212 *
2213 * Arguments: tty pointer to tty info structure
2214 * Return Value: None
2215 */
2216static int mgsl_write_room(struct tty_struct *tty)
2217{
c9f19e96 2218 struct mgsl_struct *info = tty->driver_data;
1da177e4
LT		 2219 int ret;
2220
2221 if (mgsl_paranoia_check(info, tty->name, "mgsl_write_room"))
2222 return 0;
2223 ret = SERIAL_XMIT_SIZE - info->xmit_cnt - 1;
2224 if (ret < 0)
2225 ret = 0;
2226
2227 if (debug_level >= DEBUG_LEVEL_INFO)
2228 printk("%s(%d):mgsl_write_room(%s)=%d\n",
2229 __FILE__,__LINE__, info->device_name,ret );
2230
2231 if ( info->params.mode == MGSL_MODE_HDLC ||
2232 info->params.mode == MGSL_MODE_RAW ) {
2233 /* operating in synchronous (frame oriented) mode */
2234 if ( info->tx_active )
2235 return 0;
2236 else
2237 return HDLC_MAX_FRAME_SIZE;
2238 }
2239
2240 return ret;
2241
2242} /* end of mgsl_write_room() */
2243
2244/* mgsl_chars_in_buffer()
2245 *
2246 * Return the count of bytes in transmit buffer
2247 *
2248 * Arguments: tty pointer to tty info structure
2249 * Return Value: None
2250 */
2251static int mgsl_chars_in_buffer(struct tty_struct *tty)
2252{
c9f19e96 2253 struct mgsl_struct *info = tty->driver_data;
1da177e4
LT		 2254
2255 if (debug_level >= DEBUG_LEVEL_INFO)
2256 printk("%s(%d):mgsl_chars_in_buffer(%s)\n",
2257 __FILE__,__LINE__, info->device_name );
2258
2259 if (mgsl_paranoia_check(info, tty->name, "mgsl_chars_in_buffer"))
2260 return 0;
2261
2262 if (debug_level >= DEBUG_LEVEL_INFO)
2263 printk("%s(%d):mgsl_chars_in_buffer(%s)=%d\n",
2264 __FILE__,__LINE__, info->device_name,info->xmit_cnt );
2265
2266 if ( info->params.mode == MGSL_MODE_HDLC ||
2267 info->params.mode == MGSL_MODE_RAW ) {
2268 /* operating in synchronous (frame oriented) mode */
2269 if ( info->tx_active )
2270 return info->max_frame_size;
2271 else
2272 return 0;
2273 }
2274
2275 return info->xmit_cnt;
2276} /* end of mgsl_chars_in_buffer() */
2277
2278/* mgsl_flush_buffer()
2279 *
2280 * Discard all data in the send buffer
2281 *
2282 * Arguments: tty pointer to tty info structure
2283 * Return Value: None
2284 */
2285static void mgsl_flush_buffer(struct tty_struct *tty)
2286{
c9f19e96 2287 struct mgsl_struct *info = tty->driver_data;
1da177e4
LT		 2288 unsigned long flags;
2289
2290 if (debug_level >= DEBUG_LEVEL_INFO)
2291 printk("%s(%d):mgsl_flush_buffer(%s) entry\n",
2292 __FILE__,__LINE__, info->device_name );
2293
2294 if (mgsl_paranoia_check(info, tty->name, "mgsl_flush_buffer"))
2295 return;
2296
2297 spin_lock_irqsave(&info->irq_spinlock,flags);
2298 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
2299 del_timer(&info->tx_timer);
2300 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2301
1da177e4
LT		 2302 tty_wakeup(tty);
2303}
2304
2305/* mgsl_send_xchar()
2306 *
2307 * Send a high-priority XON/XOFF character
2308 *
2309 * Arguments: tty pointer to tty info structure
2310 * ch character to send
2311 * Return Value: None
2312 */
2313static void mgsl_send_xchar(struct tty_struct *tty, char ch)
2314{
c9f19e96 2315 struct mgsl_struct *info = tty->driver_data;
1da177e4
LT		 2316 unsigned long flags;
2317
2318 if (debug_level >= DEBUG_LEVEL_INFO)
2319 printk("%s(%d):mgsl_send_xchar(%s,%d)\n",
2320 __FILE__,__LINE__, info->device_name, ch );
2321
2322 if (mgsl_paranoia_check(info, tty->name, "mgsl_send_xchar"))
2323 return;
2324
2325 info->x_char = ch;
2326 if (ch) {
2327 /* Make sure transmit interrupts are on */
2328 spin_lock_irqsave(&info->irq_spinlock,flags);
2329 if (!info->tx_enabled)
2330 usc_start_transmitter(info);
2331 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2332 }
2333} /* end of mgsl_send_xchar() */
2334
2335/* mgsl_throttle()
2336 *
2337 * Signal remote device to throttle send data (our receive data)
2338 *
2339 * Arguments: tty pointer to tty info structure
2340 * Return Value: None
2341 */
2342static void mgsl_throttle(struct tty_struct * tty)
2343{
c9f19e96 2344 struct mgsl_struct *info = tty->driver_data;
1da177e4
LT		 2345 unsigned long flags;
2346
2347 if (debug_level >= DEBUG_LEVEL_INFO)
2348 printk("%s(%d):mgsl_throttle(%s) entry\n",
2349 __FILE__,__LINE__, info->device_name );
2350
2351 if (mgsl_paranoia_check(info, tty->name, "mgsl_throttle"))
2352 return;
2353
2354 if (I_IXOFF(tty))
2355 mgsl_send_xchar(tty, STOP_CHAR(tty));
adc8d746 2356
9db276f8 2357 if (C_CRTSCTS(tty)) {
1da177e4
LT		 2358 spin_lock_irqsave(&info->irq_spinlock,flags);
2359 info->serial_signals &= ~SerialSignal_RTS;
2360 usc_set_serial_signals(info);
2361 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2362 }
2363} /* end of mgsl_throttle() */
2364
2365/* mgsl_unthrottle()
2366 *
2367 * Signal remote device to stop throttling send data (our receive data)
2368 *
2369 * Arguments: tty pointer to tty info structure
2370 * Return Value: None
2371 */
2372static void mgsl_unthrottle(struct tty_struct * tty)
2373{
c9f19e96 2374 struct mgsl_struct *info = tty->driver_data;
1da177e4
LT		 2375 unsigned long flags;
2376
2377 if (debug_level >= DEBUG_LEVEL_INFO)
2378 printk("%s(%d):mgsl_unthrottle(%s) entry\n",
2379 __FILE__,__LINE__, info->device_name );
2380
2381 if (mgsl_paranoia_check(info, tty->name, "mgsl_unthrottle"))
2382 return;
2383
2384 if (I_IXOFF(tty)) {
2385 if (info->x_char)
2386 info->x_char = 0;
2387 else
2388 mgsl_send_xchar(tty, START_CHAR(tty));
2389 }
adc8d746 2390
9db276f8 2391 if (C_CRTSCTS(tty)) {
1da177e4
LT		 2392 spin_lock_irqsave(&info->irq_spinlock,flags);
2393 info->serial_signals |= SerialSignal_RTS;
2394 usc_set_serial_signals(info);
2395 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2396 }
2397
2398} /* end of mgsl_unthrottle() */
2399
2400/* mgsl_get_stats()
2401 *
2402 * get the current serial parameters information
2403 *
2404 * Arguments: info pointer to device instance data
2405 * user_icount pointer to buffer to hold returned stats
2406 *
2407 * Return Value: 0 if success, otherwise error code
2408 */
2409static int mgsl_get_stats(struct mgsl_struct * info, struct mgsl_icount __user *user_icount)
2410{
2411 int err;
2412
2413 if (debug_level >= DEBUG_LEVEL_INFO)
2414 printk("%s(%d):mgsl_get_params(%s)\n",
2415 __FILE__,__LINE__, info->device_name);
2416
9661239f
PF		 2417 if (!user_icount) {
2418 memset(&info->icount, 0, sizeof(info->icount));
2419 } else {
f602501d 2420 mutex_lock(&info->port.mutex);
9661239f 2421 COPY_TO_USER(err, user_icount, &info->icount, sizeof(struct mgsl_icount));
f602501d 2422 mutex_unlock(&info->port.mutex);
9661239f
PF		 2423 if (err)
2424 return -EFAULT;
1da177e4
LT		 2425 }
2426
2427 return 0;
2428
2429} /* end of mgsl_get_stats() */
2430
2431/* mgsl_get_params()
2432 *
2433 * get the current serial parameters information
2434 *
2435 * Arguments: info pointer to device instance data
2436 * user_params pointer to buffer to hold returned params
2437 *
2438 * Return Value: 0 if success, otherwise error code
2439 */
2440static int mgsl_get_params(struct mgsl_struct * info, MGSL_PARAMS __user *user_params)
2441{
2442 int err;
2443 if (debug_level >= DEBUG_LEVEL_INFO)
2444 printk("%s(%d):mgsl_get_params(%s)\n",
2445 __FILE__,__LINE__, info->device_name);
2446
f602501d 2447 mutex_lock(&info->port.mutex);
1da177e4 2448 COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS));
f602501d 2449 mutex_unlock(&info->port.mutex);
1da177e4
LT		 2450 if (err) {
2451 if ( debug_level >= DEBUG_LEVEL_INFO )
2452 printk( "%s(%d):mgsl_get_params(%s) user buffer copy failed\n",
2453 __FILE__,__LINE__,info->device_name);
2454 return -EFAULT;
2455 }
2456
2457 return 0;
2458
2459} /* end of mgsl_get_params() */
2460
2461/* mgsl_set_params()
2462 *
2463 * set the serial parameters
2464 *
2465 * Arguments:
2466 *
2467 * info pointer to device instance data
2468 * new_params user buffer containing new serial params
2469 *
2470 * Return Value: 0 if success, otherwise error code
2471 */
2472static int mgsl_set_params(struct mgsl_struct * info, MGSL_PARAMS __user *new_params)
2473{
2474 unsigned long flags;
2475 MGSL_PARAMS tmp_params;
2476 int err;
2477
2478 if (debug_level >= DEBUG_LEVEL_INFO)
2479 printk("%s(%d):mgsl_set_params %s\n", __FILE__,__LINE__,
2480 info->device_name );
2481 COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS));
2482 if (err) {
2483 if ( debug_level >= DEBUG_LEVEL_INFO )
2484 printk( "%s(%d):mgsl_set_params(%s) user buffer copy failed\n",
2485 __FILE__,__LINE__,info->device_name);
2486 return -EFAULT;
2487 }
2488
f602501d 2489 mutex_lock(&info->port.mutex);
1da177e4
LT		 2490 spin_lock_irqsave(&info->irq_spinlock,flags);
2491 memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
2492 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2493
2494 mgsl_change_params(info);
f602501d 2495 mutex_unlock(&info->port.mutex);
1da177e4
LT		 2496
2497 return 0;
2498
2499} /* end of mgsl_set_params() */
2500
2501/* mgsl_get_txidle()
2502 *
2503 * get the current transmit idle mode
2504 *
2505 * Arguments: info pointer to device instance data
2506 * idle_mode pointer to buffer to hold returned idle mode
2507 *
2508 * Return Value: 0 if success, otherwise error code
2509 */
2510static int mgsl_get_txidle(struct mgsl_struct * info, int __user *idle_mode)
2511{
2512 int err;
2513
2514 if (debug_level >= DEBUG_LEVEL_INFO)
2515 printk("%s(%d):mgsl_get_txidle(%s)=%d\n",
2516 __FILE__,__LINE__, info->device_name, info->idle_mode);
2517
2518 COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int));
2519 if (err) {
2520 if ( debug_level >= DEBUG_LEVEL_INFO )
2521 printk( "%s(%d):mgsl_get_txidle(%s) user buffer copy failed\n",
2522 __FILE__,__LINE__,info->device_name);
2523 return -EFAULT;
2524 }
2525
2526 return 0;
2527
2528} /* end of mgsl_get_txidle() */
2529
2530/* mgsl_set_txidle() service ioctl to set transmit idle mode
2531 *
2532 * Arguments: info pointer to device instance data
2533 * idle_mode new idle mode
2534 *
2535 * Return Value: 0 if success, otherwise error code
2536 */
2537static int mgsl_set_txidle(struct mgsl_struct * info, int idle_mode)
2538{
2539 unsigned long flags;
2540
2541 if (debug_level >= DEBUG_LEVEL_INFO)
2542 printk("%s(%d):mgsl_set_txidle(%s,%d)\n", __FILE__,__LINE__,
2543 info->device_name, idle_mode );
2544
2545 spin_lock_irqsave(&info->irq_spinlock,flags);
2546 info->idle_mode = idle_mode;
2547 usc_set_txidle( info );
2548 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2549 return 0;
2550
2551} /* end of mgsl_set_txidle() */
2552
2553/* mgsl_txenable()
2554 *
2555 * enable or disable the transmitter
2556 *
2557 * Arguments:
2558 *
2559 * info pointer to device instance data
2560 * enable 1 = enable, 0 = disable
2561 *
2562 * Return Value: 0 if success, otherwise error code
2563 */
2564static int mgsl_txenable(struct mgsl_struct * info, int enable)
2565{
2566 unsigned long flags;
2567
2568 if (debug_level >= DEBUG_LEVEL_INFO)
2569 printk("%s(%d):mgsl_txenable(%s,%d)\n", __FILE__,__LINE__,
2570 info->device_name, enable);
2571
2572 spin_lock_irqsave(&info->irq_spinlock,flags);
2573 if ( enable ) {
2574 if ( !info->tx_enabled ) {
2575
2576 usc_start_transmitter(info);
2577 /*--------------------------------------------------
2578 * if HDLC/SDLC Loop mode, attempt to insert the
2579 * station in the 'loop' by setting CMR:13. Upon
2580 * receipt of the next GoAhead (RxAbort) sequence,
2581 * the OnLoop indicator (CCSR:7) should go active
2582 * to indicate that we are on the loop
2583 *--------------------------------------------------*/
2584 if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
2585 usc_loopmode_insert_request( info );
2586 }
2587 } else {
2588 if ( info->tx_enabled )
2589 usc_stop_transmitter(info);
2590 }
2591 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2592 return 0;
2593
2594} /* end of mgsl_txenable() */
2595
2596/* mgsl_txabort() abort send HDLC frame
2597 *
2598 * Arguments: info pointer to device instance data
2599 * Return Value: 0 if success, otherwise error code
2600 */
2601static int mgsl_txabort(struct mgsl_struct * info)
2602{
2603 unsigned long flags;
2604
2605 if (debug_level >= DEBUG_LEVEL_INFO)
2606 printk("%s(%d):mgsl_txabort(%s)\n", __FILE__,__LINE__,
2607 info->device_name);
2608
2609 spin_lock_irqsave(&info->irq_spinlock,flags);
2610 if ( info->tx_active && info->params.mode == MGSL_MODE_HDLC )
2611 {
2612 if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
2613 usc_loopmode_cancel_transmit( info );
2614 else
2615 usc_TCmd(info,TCmd_SendAbort);
2616 }
2617 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2618 return 0;
2619
2620} /* end of mgsl_txabort() */
2621
2622/* mgsl_rxenable() enable or disable the receiver
2623 *
2624 * Arguments: info pointer to device instance data
2625 * enable 1 = enable, 0 = disable
2626 * Return Value: 0 if success, otherwise error code
2627 */
2628static int mgsl_rxenable(struct mgsl_struct * info, int enable)
2629{
2630 unsigned long flags;
2631
2632 if (debug_level >= DEBUG_LEVEL_INFO)
2633 printk("%s(%d):mgsl_rxenable(%s,%d)\n", __FILE__,__LINE__,
2634 info->device_name, enable);
2635
2636 spin_lock_irqsave(&info->irq_spinlock,flags);
2637 if ( enable ) {
2638 if ( !info->rx_enabled )
2639 usc_start_receiver(info);
2640 } else {
2641 if ( info->rx_enabled )
2642 usc_stop_receiver(info);
2643 }
2644 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2645 return 0;
2646
2647} /* end of mgsl_rxenable() */
2648
2649/* mgsl_wait_event() wait for specified event to occur
2650 *
2651 * Arguments: info pointer to device instance data
2652 * mask pointer to bitmask of events to wait for
2653 * Return Value: 0 if successful and bit mask updated with
2654 * of events triggerred,
2655 * otherwise error code
2656 */
2657static int mgsl_wait_event(struct mgsl_struct * info, int __user * mask_ptr)
2658{
2659 unsigned long flags;
2660 int s;
2661 int rc=0;
2662 struct mgsl_icount cprev, cnow;
2663 int events;
2664 int mask;
2665 struct _input_signal_events oldsigs, newsigs;
2666 DECLARE_WAITQUEUE(wait, current);
2667
2668 COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int));
2669 if (rc) {
2670 return -EFAULT;
2671 }
2672
2673 if (debug_level >= DEBUG_LEVEL_INFO)
2674 printk("%s(%d):mgsl_wait_event(%s,%d)\n", __FILE__,__LINE__,
2675 info->device_name, mask);
2676
2677 spin_lock_irqsave(&info->irq_spinlock,flags);
2678
2679 /* return immediately if state matches requested events */
2680 usc_get_serial_signals(info);
2681 s = info->serial_signals;
2682 events = mask &
2683 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
2684 ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
2685 ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
2686 ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
2687 if (events) {
2688 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2689 goto exit;
2690 }
2691
2692 /* save current irq counts */
2693 cprev = info->icount;
2694 oldsigs = info->input_signal_events;
2695
2696 /* enable hunt and idle irqs if needed */
2697 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2698 u16 oldreg = usc_InReg(info,RICR);
2699 u16 newreg = oldreg +
2700 (mask & MgslEvent_ExitHuntMode ? RXSTATUS_EXITED_HUNT:0) +
2701 (mask & MgslEvent_IdleReceived ? RXSTATUS_IDLE_RECEIVED:0);
2702 if (oldreg != newreg)
2703 usc_OutReg(info, RICR, newreg);
2704 }
2705
2706 set_current_state(TASK_INTERRUPTIBLE);
2707 add_wait_queue(&info->event_wait_q, &wait);
2708
2709 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2710
2711
2712 for(;;) {
2713 schedule();
2714 if (signal_pending(current)) {
2715 rc = -ERESTARTSYS;
2716 break;
2717 }
2718
2719 /* get current irq counts */
2720 spin_lock_irqsave(&info->irq_spinlock,flags);
2721 cnow = info->icount;
2722 newsigs = info->input_signal_events;
2723 set_current_state(TASK_INTERRUPTIBLE);
2724 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2725
2726 /* if no change, wait aborted for some reason */
2727 if (newsigs.dsr_up == oldsigs.dsr_up &&
2728 newsigs.dsr_down == oldsigs.dsr_down &&
2729 newsigs.dcd_up == oldsigs.dcd_up &&
2730 newsigs.dcd_down == oldsigs.dcd_down &&
2731 newsigs.cts_up == oldsigs.cts_up &&
2732 newsigs.cts_down == oldsigs.cts_down &&
2733 newsigs.ri_up == oldsigs.ri_up &&
2734 newsigs.ri_down == oldsigs.ri_down &&
2735 cnow.exithunt == cprev.exithunt &&
2736 cnow.rxidle == cprev.rxidle) {
2737 rc = -EIO;
2738 break;
2739 }
2740
2741 events = mask &
2742 ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
2743 (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
2744 (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
2745 (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
2746 (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
2747 (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
2748 (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
2749 (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
2750 (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
2751 (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
2752 if (events)
2753 break;
2754
2755 cprev = cnow;
2756 oldsigs = newsigs;
2757 }
2758
2759 remove_wait_queue(&info->event_wait_q, &wait);
2760 set_current_state(TASK_RUNNING);
2761
2762 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2763 spin_lock_irqsave(&info->irq_spinlock,flags);
2764 if (!waitqueue_active(&info->event_wait_q)) {
2765 /* disable enable exit hunt mode/idle rcvd IRQs */
2766 usc_OutReg(info, RICR, usc_InReg(info,RICR) &
e06922aa 2767 ~(RXSTATUS_EXITED_HUNT | RXSTATUS_IDLE_RECEIVED));
1da177e4
LT		 2768 }
2769 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2770 }
2771exit:
2772 if ( rc == 0 )
2773 PUT_USER(rc, events, mask_ptr);
2774
2775 return rc;
2776
2777} /* end of mgsl_wait_event() */
2778
2779static int modem_input_wait(struct mgsl_struct *info,int arg)
2780{
2781 unsigned long flags;
2782 int rc;
2783 struct mgsl_icount cprev, cnow;
2784 DECLARE_WAITQUEUE(wait, current);
2785
2786 /* save current irq counts */
2787 spin_lock_irqsave(&info->irq_spinlock,flags);
2788 cprev = info->icount;
2789 add_wait_queue(&info->status_event_wait_q, &wait);
2790 set_current_state(TASK_INTERRUPTIBLE);
2791 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2792
2793 for(;;) {
2794 schedule();
2795 if (signal_pending(current)) {
2796 rc = -ERESTARTSYS;
2797 break;
2798 }
2799
2800 /* get new irq counts */
2801 spin_lock_irqsave(&info->irq_spinlock,flags);
2802 cnow = info->icount;
2803 set_current_state(TASK_INTERRUPTIBLE);
2804 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2805
2806 /* if no change, wait aborted for some reason */
2807 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
2808 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
2809 rc = -EIO;
2810 break;
2811 }
2812
2813 /* check for change in caller specified modem input */
2814 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
2815 (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
2816 (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
2817 (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
2818 rc = 0;
2819 break;
2820 }
2821
2822 cprev = cnow;
2823 }
2824 remove_wait_queue(&info->status_event_wait_q, &wait);
2825 set_current_state(TASK_RUNNING);
2826 return rc;
2827}
2828
2829/* return the state of the serial control and status signals
2830 */
60b33c13 2831static int tiocmget(struct tty_struct *tty)
1da177e4 2832{
c9f19e96 2833 struct mgsl_struct *info = tty->driver_data;
1da177e4
LT		 2834 unsigned int result;
2835 unsigned long flags;
2836
2837 spin_lock_irqsave(&info->irq_spinlock,flags);
2838 usc_get_serial_signals(info);
2839 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2840
2841 result = ((info->serial_signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
2842 ((info->serial_signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
2843 ((info->serial_signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
2844 ((info->serial_signals & SerialSignal_RI) ? TIOCM_RNG:0) +
2845 ((info->serial_signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
2846 ((info->serial_signals & SerialSignal_CTS) ? TIOCM_CTS:0);
2847
2848 if (debug_level >= DEBUG_LEVEL_INFO)
2849 printk("%s(%d):%s tiocmget() value=%08X\n",
2850 __FILE__,__LINE__, info->device_name, result );
2851 return result;
2852}
2853
2854/* set modem control signals (DTR/RTS)
2855 */
20b9d177
AC		 2856static int tiocmset(struct tty_struct *tty,
2857 unsigned int set, unsigned int clear)
1da177e4 2858{
c9f19e96 2859 struct mgsl_struct *info = tty->driver_data;
1da177e4
LT		 2860 unsigned long flags;
2861
2862 if (debug_level >= DEBUG_LEVEL_INFO)
2863 printk("%s(%d):%s tiocmset(%x,%x)\n",
2864 __FILE__,__LINE__,info->device_name, set, clear);
2865
2866 if (set & TIOCM_RTS)
2867 info->serial_signals |= SerialSignal_RTS;
2868 if (set & TIOCM_DTR)
2869 info->serial_signals |= SerialSignal_DTR;
2870 if (clear & TIOCM_RTS)
2871 info->serial_signals &= ~SerialSignal_RTS;
2872 if (clear & TIOCM_DTR)
2873 info->serial_signals &= ~SerialSignal_DTR;
2874
2875 spin_lock_irqsave(&info->irq_spinlock,flags);
2876 usc_set_serial_signals(info);
2877 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2878
2879 return 0;
2880}
2881
2882/* mgsl_break() Set or clear transmit break condition
2883 *
2884 * Arguments: tty pointer to tty instance data
2885 * break_state -1=set break condition, 0=clear
9e98966c 2886 * Return Value: error code
1da177e4 2887 */
9e98966c 2888static int mgsl_break(struct tty_struct *tty, int break_state)
1da177e4 2889{
c9f19e96 2890 struct mgsl_struct * info = tty->driver_data;
1da177e4
LT		 2891 unsigned long flags;
2892
2893 if (debug_level >= DEBUG_LEVEL_INFO)
2894 printk("%s(%d):mgsl_break(%s,%d)\n",
2895 __FILE__,__LINE__, info->device_name, break_state);
2896
2897 if (mgsl_paranoia_check(info, tty->name, "mgsl_break"))
9e98966c 2898 return -EINVAL;
1da177e4
LT		 2899
2900 spin_lock_irqsave(&info->irq_spinlock,flags);
2901 if (break_state == -1)
2902 usc_OutReg(info,IOCR,(u16)(usc_InReg(info,IOCR) | BIT7));
2903 else
2904 usc_OutReg(info,IOCR,(u16)(usc_InReg(info,IOCR) & ~BIT7));
2905 spin_unlock_irqrestore(&info->irq_spinlock,flags);
9e98966c 2906 return 0;
1da177e4
LT		 2907
2908} /* end of mgsl_break() */
2909
0587102c
AC		 2910/*
2911 * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
2912 * Return: write counters to the user passed counter struct
2913 * NB: both 1->0 and 0->1 transitions are counted except for
2914 * RI where only 0->1 is counted.
2915 */
2916static int msgl_get_icount(struct tty_struct *tty,
2917 struct serial_icounter_struct *icount)
2918
2919{
2920 struct mgsl_struct * info = tty->driver_data;
2921 struct mgsl_icount cnow; /* kernel counter temps */
2922 unsigned long flags;
2923
2924 spin_lock_irqsave(&info->irq_spinlock,flags);
2925 cnow = info->icount;
2926 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2927
2928 icount->cts = cnow.cts;
2929 icount->dsr = cnow.dsr;
2930 icount->rng = cnow.rng;
2931 icount->dcd = cnow.dcd;
2932 icount->rx = cnow.rx;
2933 icount->tx = cnow.tx;
2934 icount->frame = cnow.frame;
2935 icount->overrun = cnow.overrun;
2936 icount->parity = cnow.parity;
2937 icount->brk = cnow.brk;
2938 icount->buf_overrun = cnow.buf_overrun;
2939 return 0;
2940}
2941
1da177e4
LT		 2942/* mgsl_ioctl() Service an IOCTL request
2943 *
2944 * Arguments:
2945 *
2946 * tty pointer to tty instance data
1da177e4
LT		 2947 * cmd IOCTL command code
2948 * arg command argument/context
2949 *
2950 * Return Value: 0 if success, otherwise error code
2951 */
6caa76b7 2952static int mgsl_ioctl(struct tty_struct *tty,
1da177e4
LT		 2953 unsigned int cmd, unsigned long arg)
2954{
c9f19e96 2955 struct mgsl_struct * info = tty->driver_data;
1da177e4
LT		 2956
2957 if (debug_level >= DEBUG_LEVEL_INFO)
2958 printk("%s(%d):mgsl_ioctl %s cmd=%08X\n", __FILE__,__LINE__,
2959 info->device_name, cmd );
2960
2961 if (mgsl_paranoia_check(info, tty->name, "mgsl_ioctl"))
2962 return -ENODEV;
2963
2964 if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
0587102c 2965 (cmd != TIOCMIWAIT)) {
18900ca6 2966 if (tty_io_error(tty))
1da177e4
LT		 2967 return -EIO;
2968 }
2969
f602501d 2970 return mgsl_ioctl_common(info, cmd, arg);
1da177e4
LT		 2971}
2972
2973static int mgsl_ioctl_common(struct mgsl_struct *info, unsigned int cmd, unsigned long arg)
2974{
1da177e4 2975 void __user *argp = (void __user *)arg;
1da177e4
LT		 2976
2977 switch (cmd) {
2978 case MGSL_IOCGPARAMS:
2979 return mgsl_get_params(info, argp);
2980 case MGSL_IOCSPARAMS:
2981 return mgsl_set_params(info, argp);
2982 case MGSL_IOCGTXIDLE:
2983 return mgsl_get_txidle(info, argp);
2984 case MGSL_IOCSTXIDLE:
2985 return mgsl_set_txidle(info,(int)arg);
2986 case MGSL_IOCTXENABLE:
2987 return mgsl_txenable(info,(int)arg);
2988 case MGSL_IOCRXENABLE:
2989 return mgsl_rxenable(info,(int)arg);
2990 case MGSL_IOCTXABORT:
2991 return mgsl_txabort(info);
2992 case MGSL_IOCGSTATS:
2993 return mgsl_get_stats(info, argp);
2994 case MGSL_IOCWAITEVENT:
2995 return mgsl_wait_event(info, argp);
2996 case MGSL_IOCLOOPTXDONE:
2997 return mgsl_loopmode_send_done(info);
2998 /* Wait for modem input (DCD,RI,DSR,CTS) change
2999 * as specified by mask in arg (TIOCM_RNG/DSR/CD/CTS)
3000 */
3001 case TIOCMIWAIT:
3002 return modem_input_wait(info,(int)arg);
3003
1da177e4
LT		 3004 default:
3005 return -ENOIOCTLCMD;
3006 }
3007 return 0;
3008}
3009
3010/* mgsl_set_termios()
3011 *
3012 * Set new termios settings
3013 *
3014 * Arguments:
3015 *
3016 * tty pointer to tty structure
3017 * termios pointer to buffer to hold returned old termios
3018 *
3019 * Return Value: None
3020 */
606d099c 3021static void mgsl_set_termios(struct tty_struct *tty, struct ktermios *old_termios)
1da177e4 3022{
c9f19e96 3023 struct mgsl_struct *info = tty->driver_data;
1da177e4
LT		 3024 unsigned long flags;
3025
3026 if (debug_level >= DEBUG_LEVEL_INFO)
3027 printk("%s(%d):mgsl_set_termios %s\n", __FILE__,__LINE__,
3028 tty->driver->name );
3029
1da177e4
LT		 3030 mgsl_change_params(info);
3031
3032 /* Handle transition to B0 status */
9db276f8 3033 if ((old_termios->c_cflag & CBAUD) && !C_BAUD(tty)) {
9fe8074b 3034 info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
1da177e4
LT		 3035 spin_lock_irqsave(&info->irq_spinlock,flags);
3036 usc_set_serial_signals(info);
3037 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3038 }
9db276f8 3039
1da177e4 3040 /* Handle transition away from B0 status */
9db276f8 3041 if (!(old_termios->c_cflag & CBAUD) && C_BAUD(tty)) {
1da177e4 3042 info->serial_signals |= SerialSignal_DTR;
97ef38b8 3043 if (!C_CRTSCTS(tty) || !tty_throttled(tty))
1da177e4 3044 info->serial_signals |= SerialSignal_RTS;
1da177e4
LT		 3045 spin_lock_irqsave(&info->irq_spinlock,flags);
3046 usc_set_serial_signals(info);
3047 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3048 }
9db276f8 3049
1da177e4 3050 /* Handle turning off CRTSCTS */
9db276f8 3051 if (old_termios->c_cflag & CRTSCTS && !C_CRTSCTS(tty)) {
1da177e4
LT		 3052 tty->hw_stopped = 0;
3053 mgsl_start(tty);
3054 }
3055
3056} /* end of mgsl_set_termios() */
3057
3058/* mgsl_close()
3059 *
3060 * Called when port is closed. Wait for remaining data to be
3061 * sent. Disable port and free resources.
3062 *
3063 * Arguments:
3064 *
3065 * tty pointer to open tty structure
3066 * filp pointer to open file object
3067 *
3068 * Return Value: None
3069 */
3070static void mgsl_close(struct tty_struct *tty, struct file * filp)
3071{
c9f19e96 3072 struct mgsl_struct * info = tty->driver_data;
1da177e4
LT		 3073
3074 if (mgsl_paranoia_check(info, tty->name, "mgsl_close"))
3075 return;
3076
3077 if (debug_level >= DEBUG_LEVEL_INFO)
3078 printk("%s(%d):mgsl_close(%s) entry, count=%d\n",
8fb06c77 3079 __FILE__,__LINE__, info->device_name, info->port.count);
1da177e4 3080
e06922aa 3081 if (tty_port_close_start(&info->port, tty, filp) == 0)
1da177e4 3082 goto cleanup;
f602501d
AC		 3083
3084 mutex_lock(&info->port.mutex);
d41861ca 3085 if (tty_port_initialized(&info->port))
1da177e4 3086 mgsl_wait_until_sent(tty, info->timeout);
978e595f 3087 mgsl_flush_buffer(tty);
1da177e4 3088 tty_ldisc_flush(tty);
1da177e4 3089 shutdown(info);
f602501d 3090 mutex_unlock(&info->port.mutex);
a6614999
AC		 3091
3092 tty_port_close_end(&info->port, tty);
8fb06c77 3093 info->port.tty = NULL;
1da177e4
LT		 3094cleanup:
3095 if (debug_level >= DEBUG_LEVEL_INFO)
3096 printk("%s(%d):mgsl_close(%s) exit, count=%d\n", __FILE__,__LINE__,
8fb06c77 3097 tty->driver->name, info->port.count);
1da177e4
LT		 3098
3099} /* end of mgsl_close() */
3100
3101/* mgsl_wait_until_sent()
3102 *
3103 * Wait until the transmitter is empty.
3104 *
3105 * Arguments:
3106 *
3107 * tty pointer to tty info structure
3108 * timeout time to wait for send completion
3109 *
3110 * Return Value: None
3111 */
3112static void mgsl_wait_until_sent(struct tty_struct *tty, int timeout)
3113{
c9f19e96 3114 struct mgsl_struct * info = tty->driver_data;
1da177e4
LT		 3115 unsigned long orig_jiffies, char_time;
3116
3117 if (!info )
3118 return;
3119
3120 if (debug_level >= DEBUG_LEVEL_INFO)
3121 printk("%s(%d):mgsl_wait_until_sent(%s) entry\n",
3122 __FILE__,__LINE__, info->device_name );
d41861ca 3123
1da177e4
LT		 3124 if (mgsl_paranoia_check(info, tty->name, "mgsl_wait_until_sent"))
3125 return;
3126
d41861ca 3127 if (!tty_port_initialized(&info->port))
1da177e4 3128 goto exit;
d41861ca 3129
1da177e4 3130 orig_jiffies = jiffies;
d41861ca 3131
1da177e4
LT		 3132 /* Set check interval to 1/5 of estimated time to
3133 * send a character, and make it at least 1. The check
3134 * interval should also be less than the timeout.
3135 * Note: use tight timings here to satisfy the NIST-PCTS.
3136 */
978e595f 3137
1da177e4
LT		 3138 if ( info->params.data_rate ) {
3139 char_time = info->timeout/(32 * 5);
3140 if (!char_time)
3141 char_time++;
3142 } else
3143 char_time = 1;
3144
3145 if (timeout)
3146 char_time = min_t(unsigned long, char_time, timeout);
3147
3148 if ( info->params.mode == MGSL_MODE_HDLC ||
3149 info->params.mode == MGSL_MODE_RAW ) {
3150 while (info->tx_active) {
3151 msleep_interruptible(jiffies_to_msecs(char_time));
3152 if (signal_pending(current))
3153 break;
3154 if (timeout && time_after(jiffies, orig_jiffies + timeout))
3155 break;
3156 }
3157 } else {
3158 while (!(usc_InReg(info,TCSR) & TXSTATUS_ALL_SENT) &&
3159 info->tx_enabled) {
3160 msleep_interruptible(jiffies_to_msecs(char_time));
3161 if (signal_pending(current))
3162 break;
3163 if (timeout && time_after(jiffies, orig_jiffies + timeout))
3164 break;
3165 }
3166 }
3167
3168exit:
3169 if (debug_level >= DEBUG_LEVEL_INFO)
3170 printk("%s(%d):mgsl_wait_until_sent(%s) exit\n",
3171 __FILE__,__LINE__, info->device_name );
3172
3173} /* end of mgsl_wait_until_sent() */
3174
3175/* mgsl_hangup()
3176 *
3177 * Called by tty_hangup() when a hangup is signaled.
3178 * This is the same as to closing all open files for the port.
3179 *
3180 * Arguments: tty pointer to associated tty object
3181 * Return Value: None
3182 */
3183static void mgsl_hangup(struct tty_struct *tty)
3184{
c9f19e96 3185 struct mgsl_struct * info = tty->driver_data;
1da177e4
LT		 3186
3187 if (debug_level >= DEBUG_LEVEL_INFO)
3188 printk("%s(%d):mgsl_hangup(%s)\n",
3189 __FILE__,__LINE__, info->device_name );
3190
3191 if (mgsl_paranoia_check(info, tty->name, "mgsl_hangup"))
3192 return;
3193
3194 mgsl_flush_buffer(tty);
3195 shutdown(info);
3196
8fb06c77 3197 info->port.count = 0;
807c8d81 3198 tty_port_set_active(&info->port, 0);
8fb06c77 3199 info->port.tty = NULL;
1da177e4 3200
8fb06c77 3201 wake_up_interruptible(&info->port.open_wait);
1da177e4
LT		 3202
3203} /* end of mgsl_hangup() */
3204
31f35939
AC		 3205/*
3206 * carrier_raised()
3207 *
3208 * Return true if carrier is raised
3209 */
3210
3211static int carrier_raised(struct tty_port *port)
3212{
3213 unsigned long flags;
3214 struct mgsl_struct *info = container_of(port, struct mgsl_struct, port);
3215
3216 spin_lock_irqsave(&info->irq_spinlock, flags);
3217 usc_get_serial_signals(info);
3218 spin_unlock_irqrestore(&info->irq_spinlock, flags);
3219 return (info->serial_signals & SerialSignal_DCD) ? 1 : 0;
3220}
3221
fcc8ac18 3222static void dtr_rts(struct tty_port *port, int on)
5d951fb4
AC		 3223{
3224 struct mgsl_struct *info = container_of(port, struct mgsl_struct, port);
3225 unsigned long flags;
3226
3227 spin_lock_irqsave(&info->irq_spinlock,flags);
fcc8ac18 3228 if (on)
9fe8074b 3229 info->serial_signals |= SerialSignal_RTS | SerialSignal_DTR;
fcc8ac18 3230 else
9fe8074b 3231 info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
5d951fb4
AC		 3232 usc_set_serial_signals(info);
3233 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3234}
3235
3236
1da177e4
LT		 3237/* block_til_ready()
3238 *
3239 * Block the current process until the specified port
3240 * is ready to be opened.
3241 *
3242 * Arguments:
3243 *
3244 * tty pointer to tty info structure
3245 * filp pointer to open file object
3246 * info pointer to device instance data
3247 *
3248 * Return Value: 0 if success, otherwise error code
3249 */
3250static int block_til_ready(struct tty_struct *tty, struct file * filp,
3251 struct mgsl_struct *info)
3252{
3253 DECLARE_WAITQUEUE(wait, current);
3254 int retval;
0fab6de0 3255 bool do_clocal = false;
1da177e4 3256 unsigned long flags;
31f35939
AC		 3257 int dcd;
3258 struct tty_port *port = &info->port;
1da177e4
LT		 3259
3260 if (debug_level >= DEBUG_LEVEL_INFO)
3261 printk("%s(%d):block_til_ready on %s\n",
3262 __FILE__,__LINE__, tty->driver->name );
3263
18900ca6 3264 if (filp->f_flags & O_NONBLOCK || tty_io_error(tty)) {
1da177e4 3265 /* nonblock mode is set or port is not enabled */
807c8d81 3266 tty_port_set_active(port, 1);
1da177e4
LT		 3267 return 0;
3268 }
3269
9db276f8 3270 if (C_CLOCAL(tty))
0fab6de0 3271 do_clocal = true;
1da177e4
LT		 3272
3273 /* Wait for carrier detect and the line to become
3274 * free (i.e., not in use by the callout). While we are in
31f35939 3275 * this loop, port->count is dropped by one, so that
1da177e4
LT		 3276 * mgsl_close() knows when to free things. We restore it upon
3277 * exit, either normal or abnormal.
3278 */
3279
3280 retval = 0;
31f35939 3281 add_wait_queue(&port->open_wait, &wait);
1da177e4
LT		 3282
3283 if (debug_level >= DEBUG_LEVEL_INFO)
3284 printk("%s(%d):block_til_ready before block on %s count=%d\n",
31f35939 3285 __FILE__,__LINE__, tty->driver->name, port->count );
1da177e4
LT		 3286
3287 spin_lock_irqsave(&info->irq_spinlock, flags);
e359a4e3 3288 port->count--;
1da177e4 3289 spin_unlock_irqrestore(&info->irq_spinlock, flags);
31f35939 3290 port->blocked_open++;
d41861ca 3291
1da177e4 3292 while (1) {
d41861ca 3293 if (C_BAUD(tty) && tty_port_initialized(port))
5d951fb4 3294 tty_port_raise_dtr_rts(port);
d41861ca 3295
1da177e4 3296 set_current_state(TASK_INTERRUPTIBLE);
d41861ca
PH		 3297
3298 if (tty_hung_up_p(filp) || !tty_port_initialized(port)) {
31f35939 3299 retval = (port->flags & ASYNC_HUP_NOTIFY) ?
1da177e4
LT		 3300 -EAGAIN : -ERESTARTSYS;
3301 break;
3302 }
fef062cb 3303
31f35939 3304 dcd = tty_port_carrier_raised(&info->port);
fef062cb
PH		 3305 if (do_clocal || dcd)
3306 break;
3307
1da177e4
LT		 3308 if (signal_pending(current)) {
3309 retval = -ERESTARTSYS;
3310 break;
3311 }
3312
3313 if (debug_level >= DEBUG_LEVEL_INFO)
3314 printk("%s(%d):block_til_ready blocking on %s count=%d\n",
31f35939 3315 __FILE__,__LINE__, tty->driver->name, port->count );
1da177e4 3316
89c8d91e 3317 tty_unlock(tty);
1da177e4 3318 schedule();
89c8d91e 3319 tty_lock(tty);
1da177e4
LT		 3320 }
3321
3322 set_current_state(TASK_RUNNING);
31f35939 3323 remove_wait_queue(&port->open_wait, &wait);
1da177e4 3324
36c621d8 3325 /* FIXME: Racy on hangup during close wait */
e359a4e3 3326 if (!tty_hung_up_p(filp))
31f35939
AC		 3327 port->count++;
3328 port->blocked_open--;
1da177e4
LT		 3329
3330 if (debug_level >= DEBUG_LEVEL_INFO)
3331 printk("%s(%d):block_til_ready after blocking on %s count=%d\n",
31f35939 3332 __FILE__,__LINE__, tty->driver->name, port->count );
1da177e4
LT		 3333
3334 if (!retval)
807c8d81 3335 tty_port_set_active(port, 1);
1da177e4
LT		 3336
3337 return retval;
3338
3339} /* end of block_til_ready() */
3340
8a3ad104
JS		 3341static int mgsl_install(struct tty_driver *driver, struct tty_struct *tty)
3342{
3343 struct mgsl_struct *info;
3344 int line = tty->index;
3345
3346 /* verify range of specified line number */
3347 if (line >= mgsl_device_count) {
3348 printk("%s(%d):mgsl_open with invalid line #%d.\n",
3349 __FILE__, __LINE__, line);
3350 return -ENODEV;
3351 }
3352
3353 /* find the info structure for the specified line */
3354 info = mgsl_device_list;
3355 while (info && info->line != line)
3356 info = info->next_device;
3357 if (mgsl_paranoia_check(info, tty->name, "mgsl_open"))
3358 return -ENODEV;
3359 tty->driver_data = info;
3360
3361 return tty_port_install(&info->port, driver, tty);
3362}
3363
1da177e4
LT		 3364/* mgsl_open()
3365 *
3366 * Called when a port is opened. Init and enable port.
3367 * Perform serial-specific initialization for the tty structure.
3368 *
3369 * Arguments: tty pointer to tty info structure
3370 * filp associated file pointer
3371 *
3372 * Return Value: 0 if success, otherwise error code
3373 */
3374static int mgsl_open(struct tty_struct *tty, struct file * filp)
3375{
8a3ad104 3376 struct mgsl_struct *info = tty->driver_data;
1da177e4 3377 unsigned long flags;
8a3ad104 3378 int retval;
1da177e4 3379
8fb06c77 3380 info->port.tty = tty;
1da177e4
LT		 3381
3382 if (debug_level >= DEBUG_LEVEL_INFO)
3383 printk("%s(%d):mgsl_open(%s), old ref count = %d\n",
8fb06c77 3384 __FILE__,__LINE__,tty->driver->name, info->port.count);
1da177e4 3385
d6c53c0e 3386 info->port.low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0;
1da177e4
LT		 3387
3388 spin_lock_irqsave(&info->netlock, flags);
3389 if (info->netcount) {
3390 retval = -EBUSY;
3391 spin_unlock_irqrestore(&info->netlock, flags);
3392 goto cleanup;
3393 }
8fb06c77 3394 info->port.count++;
1da177e4
LT		 3395 spin_unlock_irqrestore(&info->netlock, flags);
3396
8fb06c77 3397 if (info->port.count == 1) {
1da177e4
LT		 3398 /* 1st open on this device, init hardware */
3399 retval = startup(info);
3400 if (retval < 0)
3401 goto cleanup;
3402 }
3403
3404 retval = block_til_ready(tty, filp, info);
3405 if (retval) {
3406 if (debug_level >= DEBUG_LEVEL_INFO)
3407 printk("%s(%d):block_til_ready(%s) returned %d\n",
3408 __FILE__,__LINE__, info->device_name, retval);
3409 goto cleanup;
3410 }
3411
3412 if (debug_level >= DEBUG_LEVEL_INFO)
3413 printk("%s(%d):mgsl_open(%s) success\n",
3414 __FILE__,__LINE__, info->device_name);
3415 retval = 0;
3416
3417cleanup:
3418 if (retval) {
3419 if (tty->count == 1)
8fb06c77
AC		 3420 info->port.tty = NULL; /* tty layer will release tty struct */
3421 if(info->port.count)
3422 info->port.count--;
1da177e4
LT		 3423 }
3424
3425 return retval;
3426
3427} /* end of mgsl_open() */
3428
3429/*
3430 * /proc fs routines....
3431 */
3432
d337829b 3433static inline void line_info(struct seq_file *m, struct mgsl_struct *info)
1da177e4
LT		 3434{
3435 char stat_buf[30];
1da177e4
LT		 3436 unsigned long flags;
3437
3438 if (info->bus_type == MGSL_BUS_TYPE_PCI) {
d337829b 3439 seq_printf(m, "%s:PCI io:%04X irq:%d mem:%08X lcr:%08X",
1da177e4
LT		 3440 info->device_name, info->io_base, info->irq_level,
3441 info->phys_memory_base, info->phys_lcr_base);
3442 } else {
d337829b 3443 seq_printf(m, "%s:(E)ISA io:%04X irq:%d dma:%d",
1da177e4
LT		 3444 info->device_name, info->io_base,
3445 info->irq_level, info->dma_level);
3446 }
3447
3448 /* output current serial signal states */
3449 spin_lock_irqsave(&info->irq_spinlock,flags);
3450 usc_get_serial_signals(info);
3451 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3452
3453 stat_buf[0] = 0;
3454 stat_buf[1] = 0;
3455 if (info->serial_signals & SerialSignal_RTS)
3456 strcat(stat_buf, "|RTS");
3457 if (info->serial_signals & SerialSignal_CTS)
3458 strcat(stat_buf, "|CTS");
3459 if (info->serial_signals & SerialSignal_DTR)
3460 strcat(stat_buf, "|DTR");
3461 if (info->serial_signals & SerialSignal_DSR)
3462 strcat(stat_buf, "|DSR");
3463 if (info->serial_signals & SerialSignal_DCD)
3464 strcat(stat_buf, "|CD");
3465 if (info->serial_signals & SerialSignal_RI)
3466 strcat(stat_buf, "|RI");
3467
3468 if (info->params.mode == MGSL_MODE_HDLC ||
3469 info->params.mode == MGSL_MODE_RAW ) {
d337829b 3470 seq_printf(m, " HDLC txok:%d rxok:%d",
1da177e4
LT		 3471 info->icount.txok, info->icount.rxok);
3472 if (info->icount.txunder)
d337829b 3473 seq_printf(m, " txunder:%d", info->icount.txunder);
1da177e4 3474 if (info->icount.txabort)
d337829b 3475 seq_printf(m, " txabort:%d", info->icount.txabort);
1da177e4 3476 if (info->icount.rxshort)
d337829b 3477 seq_printf(m, " rxshort:%d", info->icount.rxshort);
1da177e4 3478 if (info->icount.rxlong)
d337829b 3479 seq_printf(m, " rxlong:%d", info->icount.rxlong);
1da177e4 3480 if (info->icount.rxover)
d337829b 3481 seq_printf(m, " rxover:%d", info->icount.rxover);
1da177e4 3482 if (info->icount.rxcrc)
d337829b 3483 seq_printf(m, " rxcrc:%d", info->icount.rxcrc);
1da177e4 3484 } else {
d337829b 3485 seq_printf(m, " ASYNC tx:%d rx:%d",
1da177e4
LT		 3486 info->icount.tx, info->icount.rx);
3487 if (info->icount.frame)
d337829b 3488 seq_printf(m, " fe:%d", info->icount.frame);
1da177e4 3489 if (info->icount.parity)
d337829b 3490 seq_printf(m, " pe:%d", info->icount.parity);
1da177e4 3491 if (info->icount.brk)
d337829b 3492 seq_printf(m, " brk:%d", info->icount.brk);
1da177e4 3493 if (info->icount.overrun)
d337829b 3494 seq_printf(m, " oe:%d", info->icount.overrun);
1da177e4
LT		 3495 }
3496
3497 /* Append serial signal status to end */
d337829b 3498 seq_printf(m, " %s\n", stat_buf+1);
1da177e4 3499
d337829b 3500 seq_printf(m, "txactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1da177e4
LT		 3501 info->tx_active,info->bh_requested,info->bh_running,
3502 info->pending_bh);
3503
3504 spin_lock_irqsave(&info->irq_spinlock,flags);
3505 {
3506 u16 Tcsr = usc_InReg( info, TCSR );
3507 u16 Tdmr = usc_InDmaReg( info, TDMR );
3508 u16 Ticr = usc_InReg( info, TICR );
3509 u16 Rscr = usc_InReg( info, RCSR );
3510 u16 Rdmr = usc_InDmaReg( info, RDMR );
3511 u16 Ricr = usc_InReg( info, RICR );
3512 u16 Icr = usc_InReg( info, ICR );
3513 u16 Dccr = usc_InReg( info, DCCR );
3514 u16 Tmr = usc_InReg( info, TMR );
3515 u16 Tccr = usc_InReg( info, TCCR );
3516 u16 Ccar = inw( info->io_base + CCAR );
d337829b 3517 seq_printf(m, "tcsr=%04X tdmr=%04X ticr=%04X rcsr=%04X rdmr=%04X\n"
1da177e4
LT		 3518 "ricr=%04X icr =%04X dccr=%04X tmr=%04X tccr=%04X ccar=%04X\n",
3519 Tcsr,Tdmr,Ticr,Rscr,Rdmr,Ricr,Icr,Dccr,Tmr,Tccr,Ccar );
3520 }
3521 spin_unlock_irqrestore(&info->irq_spinlock,flags);
d337829b 3522}
1da177e4 3523
d337829b
AD		 3524/* Called to print information about devices */
3525static int mgsl_proc_show(struct seq_file *m, void *v)
1da177e4 3526{
1da177e4
LT		 3527 struct mgsl_struct *info;
3528
d337829b 3529 seq_printf(m, "synclink driver:%s\n", driver_version);
1da177e4
LT		 3530
3531 info = mgsl_device_list;
3532 while( info ) {
d337829b 3533 line_info(m, info);
1da177e4
LT		 3534 info = info->next_device;
3535 }
d337829b
AD		 3536 return 0;
3537}
1da177e4 3538
d337829b
AD		 3539static int mgsl_proc_open(struct inode *inode, struct file *file)
3540{
3541 return single_open(file, mgsl_proc_show, NULL);
3542}
3543
3544static const struct file_operations mgsl_proc_fops = {
3545 .owner = THIS_MODULE,
3546 .open = mgsl_proc_open,
3547 .read = seq_read,
3548 .llseek = seq_lseek,
3549 .release = single_release,
3550};
1da177e4
LT		 3551
3552/* mgsl_allocate_dma_buffers()
3553 *
3554 * Allocate and format DMA buffers (ISA adapter)
3555 * or format shared memory buffers (PCI adapter).
3556 *
3557 * Arguments: info pointer to device instance data
3558 * Return Value: 0 if success, otherwise error
3559 */
3560static int mgsl_allocate_dma_buffers(struct mgsl_struct *info)
3561{
3562 unsigned short BuffersPerFrame;
3563
3564 info->last_mem_alloc = 0;
3565
3566 /* Calculate the number of DMA buffers necessary to hold the */
3567 /* largest allowable frame size. Note: If the max frame size is */
3568 /* not an even multiple of the DMA buffer size then we need to */
3569 /* round the buffer count per frame up one. */
3570
3571 BuffersPerFrame = (unsigned short)(info->max_frame_size/DMABUFFERSIZE);
3572 if ( info->max_frame_size % DMABUFFERSIZE )
3573 BuffersPerFrame++;
3574
3575 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
3576 /*
3577 * The PCI adapter has 256KBytes of shared memory to use.
3578 * This is 64 PAGE_SIZE buffers.
3579 *
3580 * The first page is used for padding at this time so the
3581 * buffer list does not begin at offset 0 of the PCI
3582 * adapter's shared memory.
3583 *
3584 * The 2nd page is used for the buffer list. A 4K buffer
3585 * list can hold 128 DMA_BUFFER structures at 32 bytes
3586 * each.
3587 *
3588 * This leaves 62 4K pages.
3589 *
3590 * The next N pages are used for transmit frame(s). We
3591 * reserve enough 4K page blocks to hold the required
3592 * number of transmit dma buffers (num_tx_dma_buffers),
3593 * each of MaxFrameSize size.
3594 *
3595 * Of the remaining pages (62-N), determine how many can
3596 * be used to receive full MaxFrameSize inbound frames
3597 */
3598 info->tx_buffer_count = info->num_tx_dma_buffers * BuffersPerFrame;
3599 info->rx_buffer_count = 62 - info->tx_buffer_count;
3600 } else {
3601 /* Calculate the number of PAGE_SIZE buffers needed for */
3602 /* receive and transmit DMA buffers. */
3603
3604
3605 /* Calculate the number of DMA buffers necessary to */
3606 /* hold 7 max size receive frames and one max size transmit frame. */
3607 /* The receive buffer count is bumped by one so we avoid an */
3608 /* End of List condition if all receive buffers are used when */
3609 /* using linked list DMA buffers. */
3610
3611 info->tx_buffer_count = info->num_tx_dma_buffers * BuffersPerFrame;
3612 info->rx_buffer_count = (BuffersPerFrame * MAXRXFRAMES) + 6;
3613
3614 /*
3615 * limit total TxBuffers & RxBuffers to 62 4K total
3616 * (ala PCI Allocation)
3617 */
3618
3619 if ( (info->tx_buffer_count + info->rx_buffer_count) > 62 )
3620 info->rx_buffer_count = 62 - info->tx_buffer_count;
3621
3622 }
3623
3624 if ( debug_level >= DEBUG_LEVEL_INFO )
3625 printk("%s(%d):Allocating %d TX and %d RX DMA buffers.\n",
3626 __FILE__,__LINE__, info->tx_buffer_count,info->rx_buffer_count);
3627
3628 if ( mgsl_alloc_buffer_list_memory( info ) < 0 ||
3629 mgsl_alloc_frame_memory(info, info->rx_buffer_list, info->rx_buffer_count) < 0 ||
3630 mgsl_alloc_frame_memory(info, info->tx_buffer_list, info->tx_buffer_count) < 0 ||
3631 mgsl_alloc_intermediate_rxbuffer_memory(info) < 0 ||
3632 mgsl_alloc_intermediate_txbuffer_memory(info) < 0 ) {
3633 printk("%s(%d):Can't allocate DMA buffer memory\n",__FILE__,__LINE__);
3634 return -ENOMEM;
3635 }
3636
3637 mgsl_reset_rx_dma_buffers( info );
3638 mgsl_reset_tx_dma_buffers( info );
3639
3640 return 0;
3641
3642} /* end of mgsl_allocate_dma_buffers() */
3643
3644/*
3645 * mgsl_alloc_buffer_list_memory()
3646 *
3647 * Allocate a common DMA buffer for use as the
3648 * receive and transmit buffer lists.
3649 *
3650 * A buffer list is a set of buffer entries where each entry contains
3651 * a pointer to an actual buffer and a pointer to the next buffer entry
3652 * (plus some other info about the buffer).
3653 *
3654 * The buffer entries for a list are built to form a circular list so
3655 * that when the entire list has been traversed you start back at the
3656 * beginning.
3657 *
3658 * This function allocates memory for just the buffer entries.
3659 * The links (pointer to next entry) are filled in with the physical
3660 * address of the next entry so the adapter can navigate the list
3661 * using bus master DMA. The pointers to the actual buffers are filled
3662 * out later when the actual buffers are allocated.
3663 *
3664 * Arguments: info pointer to device instance data
3665 * Return Value: 0 if success, otherwise error
3666 */
3667static int mgsl_alloc_buffer_list_memory( struct mgsl_struct *info )
3668{
3669 unsigned int i;
3670
3671 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
3672 /* PCI adapter uses shared memory. */
3673 info->buffer_list = info->memory_base + info->last_mem_alloc;
3674 info->buffer_list_phys = info->last_mem_alloc;
3675 info->last_mem_alloc += BUFFERLISTSIZE;
3676 } else {
3677 /* ISA adapter uses system memory. */
3678 /* The buffer lists are allocated as a common buffer that both */
3679 /* the processor and adapter can access. This allows the driver to */
3680 /* inspect portions of the buffer while other portions are being */
3681 /* updated by the adapter using Bus Master DMA. */
3682
0ff1b2c8
PF		 3683 info->buffer_list = dma_alloc_coherent(NULL, BUFFERLISTSIZE, &info->buffer_list_dma_addr, GFP_KERNEL);
3684 if (info->buffer_list == NULL)
1da177e4 3685 return -ENOMEM;
0ff1b2c8 3686 info->buffer_list_phys = (u32)(info->buffer_list_dma_addr);
1da177e4
LT		 3687 }
3688
3689 /* We got the memory for the buffer entry lists. */
3690 /* Initialize the memory block to all zeros. */
3691 memset( info->buffer_list, 0, BUFFERLISTSIZE );
3692
3693 /* Save virtual address pointers to the receive and */
3694 /* transmit buffer lists. (Receive 1st). These pointers will */
3695 /* be used by the processor to access the lists. */
3696 info->rx_buffer_list = (DMABUFFERENTRY *)info->buffer_list;
3697 info->tx_buffer_list = (DMABUFFERENTRY *)info->buffer_list;
3698 info->tx_buffer_list += info->rx_buffer_count;
3699
3700 /*
3701 * Build the links for the buffer entry lists such that
3702 * two circular lists are built. (Transmit and Receive).
3703 *
3704 * Note: the links are physical addresses
3705 * which are read by the adapter to determine the next
3706 * buffer entry to use.
3707 */
3708
3709 for ( i = 0; i < info->rx_buffer_count; i++ ) {
3710 /* calculate and store physical address of this buffer entry */
3711 info->rx_buffer_list[i].phys_entry =
3712 info->buffer_list_phys + (i * sizeof(DMABUFFERENTRY));
3713
3714 /* calculate and store physical address of */
3715 /* next entry in cirular list of entries */
3716
3717 info->rx_buffer_list[i].link = info->buffer_list_phys;
3718
3719 if ( i < info->rx_buffer_count - 1 )
3720 info->rx_buffer_list[i].link += (i + 1) * sizeof(DMABUFFERENTRY);
3721 }
3722
3723 for ( i = 0; i < info->tx_buffer_count; i++ ) {
3724 /* calculate and store physical address of this buffer entry */
3725 info->tx_buffer_list[i].phys_entry = info->buffer_list_phys +
3726 ((info->rx_buffer_count + i) * sizeof(DMABUFFERENTRY));
3727
3728 /* calculate and store physical address of */
3729 /* next entry in cirular list of entries */
3730
3731 info->tx_buffer_list[i].link = info->buffer_list_phys +
3732 info->rx_buffer_count * sizeof(DMABUFFERENTRY);
3733
3734 if ( i < info->tx_buffer_count - 1 )
3735 info->tx_buffer_list[i].link += (i + 1) * sizeof(DMABUFFERENTRY);
3736 }
3737
3738 return 0;
3739
3740} /* end of mgsl_alloc_buffer_list_memory() */
3741
3742/* Free DMA buffers allocated for use as the
3743 * receive and transmit buffer lists.
3744 * Warning:
3745 *
3746 * The data transfer buffers associated with the buffer list
3747 * MUST be freed before freeing the buffer list itself because
3748 * the buffer list contains the information necessary to free
3749 * the individual buffers!
3750 */
3751static void mgsl_free_buffer_list_memory( struct mgsl_struct *info )
3752{
0ff1b2c8
PF		 3753 if (info->buffer_list && info->bus_type != MGSL_BUS_TYPE_PCI)
3754 dma_free_coherent(NULL, BUFFERLISTSIZE, info->buffer_list, info->buffer_list_dma_addr);
1da177e4
LT		 3755
3756 info->buffer_list = NULL;
3757 info->rx_buffer_list = NULL;
3758 info->tx_buffer_list = NULL;
3759
3760} /* end of mgsl_free_buffer_list_memory() */
3761
3762/*
3763 * mgsl_alloc_frame_memory()
3764 *
3765 * Allocate the frame DMA buffers used by the specified buffer list.
3766 * Each DMA buffer will be one memory page in size. This is necessary
3767 * because memory can fragment enough that it may be impossible
3768 * contiguous pages.
3769 *
3770 * Arguments:
3771 *
3772 * info pointer to device instance data
3773 * BufferList pointer to list of buffer entries
3774 * Buffercount count of buffer entries in buffer list
3775 *
3776 * Return Value: 0 if success, otherwise -ENOMEM
3777 */
3778static int mgsl_alloc_frame_memory(struct mgsl_struct *info,DMABUFFERENTRY *BufferList,int Buffercount)
3779{
3780 int i;
0ff1b2c8 3781 u32 phys_addr;
1da177e4
LT		 3782
3783 /* Allocate page sized buffers for the receive buffer list */
3784
3785 for ( i = 0; i < Buffercount; i++ ) {
3786 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
3787 /* PCI adapter uses shared memory buffers. */
3788 BufferList[i].virt_addr = info->memory_base + info->last_mem_alloc;
3789 phys_addr = info->last_mem_alloc;
3790 info->last_mem_alloc += DMABUFFERSIZE;
3791 } else {
3792 /* ISA adapter uses system memory. */
0ff1b2c8
PF		 3793 BufferList[i].virt_addr = dma_alloc_coherent(NULL, DMABUFFERSIZE, &BufferList[i].dma_addr, GFP_KERNEL);
3794 if (BufferList[i].virt_addr == NULL)
1da177e4 3795 return -ENOMEM;
0ff1b2c8 3796 phys_addr = (u32)(BufferList[i].dma_addr);
1da177e4
LT		 3797 }
3798 BufferList[i].phys_addr = phys_addr;
3799 }
3800
3801 return 0;
3802
3803} /* end of mgsl_alloc_frame_memory() */
3804
3805/*
3806 * mgsl_free_frame_memory()
3807 *
3808 * Free the buffers associated with
3809 * each buffer entry of a buffer list.
3810 *
3811 * Arguments:
3812 *
3813 * info pointer to device instance data
3814 * BufferList pointer to list of buffer entries
3815 * Buffercount count of buffer entries in buffer list
3816 *
3817 * Return Value: None
3818 */
3819static void mgsl_free_frame_memory(struct mgsl_struct *info, DMABUFFERENTRY *BufferList, int Buffercount)
3820{
3821 int i;
3822
3823 if ( BufferList ) {
3824 for ( i = 0 ; i < Buffercount ; i++ ) {
3825 if ( BufferList[i].virt_addr ) {
3826 if ( info->bus_type != MGSL_BUS_TYPE_PCI )
0ff1b2c8 3827 dma_free_coherent(NULL, DMABUFFERSIZE, BufferList[i].virt_addr, BufferList[i].dma_addr);
1da177e4
LT		 3828 BufferList[i].virt_addr = NULL;
3829 }
3830 }
3831 }
3832
3833} /* end of mgsl_free_frame_memory() */
3834
3835/* mgsl_free_dma_buffers()
3836 *
3837 * Free DMA buffers
3838 *
3839 * Arguments: info pointer to device instance data
3840 * Return Value: None
3841 */
3842static void mgsl_free_dma_buffers( struct mgsl_struct *info )
3843{
3844 mgsl_free_frame_memory( info, info->rx_buffer_list, info->rx_buffer_count );
3845 mgsl_free_frame_memory( info, info->tx_buffer_list, info->tx_buffer_count );
3846 mgsl_free_buffer_list_memory( info );
3847
3848} /* end of mgsl_free_dma_buffers() */
3849
3850
3851/*
3852 * mgsl_alloc_intermediate_rxbuffer_memory()
3853 *
3854 * Allocate a buffer large enough to hold max_frame_size. This buffer
3855 * is used to pass an assembled frame to the line discipline.
3856 *
3857 * Arguments:
3858 *
3859 * info pointer to device instance data
3860 *
3861 * Return Value: 0 if success, otherwise -ENOMEM
3862 */
3863static int mgsl_alloc_intermediate_rxbuffer_memory(struct mgsl_struct *info)
3864{
3865 info->intermediate_rxbuffer = kmalloc(info->max_frame_size, GFP_KERNEL | GFP_DMA);
3866 if ( info->intermediate_rxbuffer == NULL )
3867 return -ENOMEM;
a6b68a69
PF		 3868 /* unused flag buffer to satisfy receive_buf calling interface */
3869 info->flag_buf = kzalloc(info->max_frame_size, GFP_KERNEL);
3870 if (!info->flag_buf) {
3871 kfree(info->intermediate_rxbuffer);
3872 info->intermediate_rxbuffer = NULL;
3873 return -ENOMEM;
3874 }
1da177e4
LT		 3875 return 0;
3876
3877} /* end of mgsl_alloc_intermediate_rxbuffer_memory() */
3878
3879/*
3880 * mgsl_free_intermediate_rxbuffer_memory()
3881 *
3882 *
3883 * Arguments:
3884 *
3885 * info pointer to device instance data
3886 *
3887 * Return Value: None
3888 */
3889static void mgsl_free_intermediate_rxbuffer_memory(struct mgsl_struct *info)
3890{
735d5661 3891 kfree(info->intermediate_rxbuffer);
1da177e4 3892 info->intermediate_rxbuffer = NULL;
a6b68a69
PF		 3893 kfree(info->flag_buf);
3894 info->flag_buf = NULL;
1da177e4
LT		 3895
3896} /* end of mgsl_free_intermediate_rxbuffer_memory() */
3897
3898/*
3899 * mgsl_alloc_intermediate_txbuffer_memory()
3900 *
3901 * Allocate intermdiate transmit buffer(s) large enough to hold max_frame_size.
3902 * This buffer is used to load transmit frames into the adapter's dma transfer
3903 * buffers when there is sufficient space.
3904 *
3905 * Arguments:
3906 *
3907 * info pointer to device instance data
3908 *
3909 * Return Value: 0 if success, otherwise -ENOMEM
3910 */
3911static int mgsl_alloc_intermediate_txbuffer_memory(struct mgsl_struct *info)
3912{
3913 int i;
3914
3915 if ( debug_level >= DEBUG_LEVEL_INFO )
3916 printk("%s %s(%d) allocating %d tx holding buffers\n",
3917 info->device_name, __FILE__,__LINE__,info->num_tx_holding_buffers);
3918
3919 memset(info->tx_holding_buffers,0,sizeof(info->tx_holding_buffers));
3920
3921 for ( i=0; i<info->num_tx_holding_buffers; ++i) {
3922 info->tx_holding_buffers[i].buffer =
3923 kmalloc(info->max_frame_size, GFP_KERNEL);
d9a2f4a4
AC		 3924 if (info->tx_holding_buffers[i].buffer == NULL) {
3925 for (--i; i >= 0; i--) {
3926 kfree(info->tx_holding_buffers[i].buffer);
3927 info->tx_holding_buffers[i].buffer = NULL;
3928 }
1da177e4 3929 return -ENOMEM;
d9a2f4a4 3930 }
1da177e4
LT		 3931 }
3932
3933 return 0;
3934
3935} /* end of mgsl_alloc_intermediate_txbuffer_memory() */
3936
3937/*
3938 * mgsl_free_intermediate_txbuffer_memory()
3939 *
3940 *
3941 * Arguments:
3942 *
3943 * info pointer to device instance data
3944 *
3945 * Return Value: None
3946 */
3947static void mgsl_free_intermediate_txbuffer_memory(struct mgsl_struct *info)
3948{
3949 int i;
3950
3951 for ( i=0; i<info->num_tx_holding_buffers; ++i ) {
735d5661
JJ		 3952 kfree(info->tx_holding_buffers[i].buffer);
3953 info->tx_holding_buffers[i].buffer = NULL;
1da177e4
LT		 3954 }
3955
3956 info->get_tx_holding_index = 0;
3957 info->put_tx_holding_index = 0;
3958 info->tx_holding_count = 0;
3959
3960} /* end of mgsl_free_intermediate_txbuffer_memory() */
3961
3962
3963/*
3964 * load_next_tx_holding_buffer()
3965 *
3966 * attempts to load the next buffered tx request into the
3967 * tx dma buffers
3968 *
3969 * Arguments:
3970 *
3971 * info pointer to device instance data
3972 *
0fab6de0 3973 * Return Value: true if next buffered tx request loaded
1da177e4 3974 * into adapter's tx dma buffer,
0fab6de0 3975 * false otherwise
1da177e4 3976 */
0fab6de0 3977static bool load_next_tx_holding_buffer(struct mgsl_struct *info)
1da177e4 3978{
0fab6de0 3979 bool ret = false;
1da177e4
LT		 3980
3981 if ( info->tx_holding_count ) {
3982 /* determine if we have enough tx dma buffers
3983 * to accommodate the next tx frame
3984 */
3985 struct tx_holding_buffer *ptx =
3986 &info->tx_holding_buffers[info->get_tx_holding_index];
3987 int num_free = num_free_tx_dma_buffers(info);
3988 int num_needed = ptx->buffer_size / DMABUFFERSIZE;
3989 if ( ptx->buffer_size % DMABUFFERSIZE )
3990 ++num_needed;
3991
3992 if (num_needed <= num_free) {
3993 info->xmit_cnt = ptx->buffer_size;
3994 mgsl_load_tx_dma_buffer(info,ptx->buffer,ptx->buffer_size);
3995
3996 --info->tx_holding_count;
3997 if ( ++info->get_tx_holding_index >= info->num_tx_holding_buffers)
3998 info->get_tx_holding_index=0;
3999
4000 /* restart transmit timer */
4001 mod_timer(&info->tx_timer, jiffies + msecs_to_jiffies(5000));
4002
0fab6de0 4003 ret = true;
1da177e4
LT		 4004 }
4005 }
4006
4007 return ret;
4008}
4009
4010/*
4011 * save_tx_buffer_request()
4012 *
4013 * attempt to store transmit frame request for later transmission
4014 *
4015 * Arguments:
4016 *
4017 * info pointer to device instance data
4018 * Buffer pointer to buffer containing frame to load
4019 * BufferSize size in bytes of frame in Buffer
4020 *
4021 * Return Value: 1 if able to store, 0 otherwise
4022 */
4023static int save_tx_buffer_request(struct mgsl_struct *info,const char *Buffer, unsigned int BufferSize)
4024{
4025 struct tx_holding_buffer *ptx;
4026
4027 if ( info->tx_holding_count >= info->num_tx_holding_buffers ) {
4028 return 0; /* all buffers in use */
4029 }
4030
4031 ptx = &info->tx_holding_buffers[info->put_tx_holding_index];
4032 ptx->buffer_size = BufferSize;
4033 memcpy( ptx->buffer, Buffer, BufferSize);
4034
4035 ++info->tx_holding_count;
4036 if ( ++info->put_tx_holding_index >= info->num_tx_holding_buffers)
4037 info->put_tx_holding_index=0;
4038
4039 return 1;
4040}
4041
4042static int mgsl_claim_resources(struct mgsl_struct *info)
4043{
4044 if (request_region(info->io_base,info->io_addr_size,"synclink") == NULL) {
4045 printk( "%s(%d):I/O address conflict on device %s Addr=%08X\n",
4046 __FILE__,__LINE__,info->device_name, info->io_base);
4047 return -ENODEV;
4048 }
0fab6de0 4049 info->io_addr_requested = true;
1da177e4
LT		 4050
4051 if ( request_irq(info->irq_level,mgsl_interrupt,info->irq_flags,
4052 info->device_name, info ) < 0 ) {
25985edc 4053 printk( "%s(%d):Can't request interrupt on device %s IRQ=%d\n",
1da177e4
LT		 4054 __FILE__,__LINE__,info->device_name, info->irq_level );
4055 goto errout;
4056 }
0fab6de0 4057 info->irq_requested = true;
1da177e4
LT		 4058
4059 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
4060 if (request_mem_region(info->phys_memory_base,0x40000,"synclink") == NULL) {
4061 printk( "%s(%d):mem addr conflict device %s Addr=%08X\n",
4062 __FILE__,__LINE__,info->device_name, info->phys_memory_base);
4063 goto errout;
4064 }
0fab6de0 4065 info->shared_mem_requested = true;
1da177e4
LT		 4066 if (request_mem_region(info->phys_lcr_base + info->lcr_offset,128,"synclink") == NULL) {
4067 printk( "%s(%d):lcr mem addr conflict device %s Addr=%08X\n",
4068 __FILE__,__LINE__,info->device_name, info->phys_lcr_base + info->lcr_offset);
4069 goto errout;
4070 }
0fab6de0 4071 info->lcr_mem_requested = true;
1da177e4 4072
24cb2335
AC		 4073 info->memory_base = ioremap_nocache(info->phys_memory_base,
4074 0x40000);
1da177e4 4075 if (!info->memory_base) {
25985edc 4076 printk( "%s(%d):Can't map shared memory on device %s MemAddr=%08X\n",
1da177e4
LT		 4077 __FILE__,__LINE__,info->device_name, info->phys_memory_base );
4078 goto errout;
4079 }
4080
4081 if ( !mgsl_memory_test(info) ) {
4082 printk( "%s(%d):Failed shared memory test %s MemAddr=%08X\n",
4083 __FILE__,__LINE__,info->device_name, info->phys_memory_base );
4084 goto errout;
4085 }
4086
24cb2335
AC		 4087 info->lcr_base = ioremap_nocache(info->phys_lcr_base,
4088 PAGE_SIZE);
1da177e4 4089 if (!info->lcr_base) {
25985edc 4090 printk( "%s(%d):Can't map LCR memory on device %s MemAddr=%08X\n",
1da177e4
LT		 4091 __FILE__,__LINE__,info->device_name, info->phys_lcr_base );
4092 goto errout;
4093 }
24cb2335 4094 info->lcr_base += info->lcr_offset;
1da177e4
LT		 4095
4096 } else {
4097 /* claim DMA channel */
4098
4099 if (request_dma(info->dma_level,info->device_name) < 0){
25985edc 4100 printk( "%s(%d):Can't request DMA channel on device %s DMA=%d\n",
1da177e4 4101 __FILE__,__LINE__,info->device_name, info->dma_level );
556c2780 4102 goto errout;
1da177e4 4103 }
0fab6de0 4104 info->dma_requested = true;
1da177e4
LT		 4105
4106 /* ISA adapter uses bus master DMA */
4107 set_dma_mode(info->dma_level,DMA_MODE_CASCADE);
4108 enable_dma(info->dma_level);
4109 }
4110
4111 if ( mgsl_allocate_dma_buffers(info) < 0 ) {
25985edc 4112 printk( "%s(%d):Can't allocate DMA buffers on device %s DMA=%d\n",
1da177e4
LT		 4113 __FILE__,__LINE__,info->device_name, info->dma_level );
4114 goto errout;
4115 }
4116
4117 return 0;
4118errout:
4119 mgsl_release_resources(info);
4120 return -ENODEV;
4121
4122} /* end of mgsl_claim_resources() */
4123
4124static void mgsl_release_resources(struct mgsl_struct *info)
4125{
4126 if ( debug_level >= DEBUG_LEVEL_INFO )
4127 printk( "%s(%d):mgsl_release_resources(%s) entry\n",
4128 __FILE__,__LINE__,info->device_name );
4129
4130 if ( info->irq_requested ) {
4131 free_irq(info->irq_level, info);
0fab6de0 4132 info->irq_requested = false;
1da177e4
LT		 4133 }
4134 if ( info->dma_requested ) {
4135 disable_dma(info->dma_level);
4136 free_dma(info->dma_level);
0fab6de0 4137 info->dma_requested = false;
1da177e4
LT		 4138 }
4139 mgsl_free_dma_buffers(info);
4140 mgsl_free_intermediate_rxbuffer_memory(info);
4141 mgsl_free_intermediate_txbuffer_memory(info);
4142
4143 if ( info->io_addr_requested ) {
4144 release_region(info->io_base,info->io_addr_size);
0fab6de0 4145 info->io_addr_requested = false;
1da177e4
LT		 4146 }
4147 if ( info->shared_mem_requested ) {
4148 release_mem_region(info->phys_memory_base,0x40000);
0fab6de0 4149 info->shared_mem_requested = false;
1da177e4
LT		 4150 }
4151 if ( info->lcr_mem_requested ) {
4152 release_mem_region(info->phys_lcr_base + info->lcr_offset,128);
0fab6de0 4153 info->lcr_mem_requested = false;
1da177e4
LT		 4154 }
4155 if (info->memory_base){
4156 iounmap(info->memory_base);
4157 info->memory_base = NULL;
4158 }
4159 if (info->lcr_base){
4160 iounmap(info->lcr_base - info->lcr_offset);
4161 info->lcr_base = NULL;
4162 }
4163
4164 if ( debug_level >= DEBUG_LEVEL_INFO )
4165 printk( "%s(%d):mgsl_release_resources(%s) exit\n",
4166 __FILE__,__LINE__,info->device_name );
4167
4168} /* end of mgsl_release_resources() */
4169
4170/* mgsl_add_device()
4171 *
4172 * Add the specified device instance data structure to the
4173 * global linked list of devices and increment the device count.
4174 *
4175 * Arguments: info pointer to device instance data
4176 * Return Value: None
4177 */
4178static void mgsl_add_device( struct mgsl_struct *info )
4179{
4180 info->next_device = NULL;
4181 info->line = mgsl_device_count;
4182 sprintf(info->device_name,"ttySL%d",info->line);
4183
4184 if (info->line < MAX_TOTAL_DEVICES) {
4185 if (maxframe[info->line])
4186 info->max_frame_size = maxframe[info->line];
1da177e4
LT		 4187
4188 if (txdmabufs[info->line]) {
4189 info->num_tx_dma_buffers = txdmabufs[info->line];
4190 if (info->num_tx_dma_buffers < 1)
4191 info->num_tx_dma_buffers = 1;
4192 }
4193
4194 if (txholdbufs[info->line]) {
4195 info->num_tx_holding_buffers = txholdbufs[info->line];
4196 if (info->num_tx_holding_buffers < 1)
4197 info->num_tx_holding_buffers = 1;
4198 else if (info->num_tx_holding_buffers > MAX_TX_HOLDING_BUFFERS)
4199 info->num_tx_holding_buffers = MAX_TX_HOLDING_BUFFERS;
4200 }
4201 }
4202
4203 mgsl_device_count++;
4204
4205 if ( !mgsl_device_list )
4206 mgsl_device_list = info;
4207 else {
4208 struct mgsl_struct *current_dev = mgsl_device_list;
4209 while( current_dev->next_device )
4210 current_dev = current_dev->next_device;
4211 current_dev->next_device = info;
4212 }
4213
4214 if ( info->max_frame_size < 4096 )
4215 info->max_frame_size = 4096;
4216 else if ( info->max_frame_size > 65535 )
4217 info->max_frame_size = 65535;
4218
4219 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
4220 printk( "SyncLink PCI v%d %s: IO=%04X IRQ=%d Mem=%08X,%08X MaxFrameSize=%u\n",
4221 info->hw_version + 1, info->device_name, info->io_base, info->irq_level,
4222 info->phys_memory_base, info->phys_lcr_base,
4223 info->max_frame_size );
4224 } else {
4225 printk( "SyncLink ISA %s: IO=%04X IRQ=%d DMA=%d MaxFrameSize=%u\n",
4226 info->device_name, info->io_base, info->irq_level, info->dma_level,
4227 info->max_frame_size );
4228 }
4229
af69c7f9 4230#if SYNCLINK_GENERIC_HDLC
1da177e4
LT		 4231 hdlcdev_init(info);
4232#endif
4233
4234} /* end of mgsl_add_device() */
4235
31f35939
AC		 4236static const struct tty_port_operations mgsl_port_ops = {
4237 .carrier_raised = carrier_raised,
fcc8ac18 4238 .dtr_rts = dtr_rts,
31f35939
AC		 4239};
4240
4241
1da177e4
LT		 4242/* mgsl_allocate_device()
4243 *
4244 * Allocate and initialize a device instance structure
4245 *
4246 * Arguments: none
4247 * Return Value: pointer to mgsl_struct if success, otherwise NULL
4248 */
4249static struct mgsl_struct* mgsl_allocate_device(void)
4250{
4251 struct mgsl_struct *info;
4252
dd00cc48 4253 info = kzalloc(sizeof(struct mgsl_struct),
1da177e4
LT		 4254 GFP_KERNEL);
4255
4256 if (!info) {
4257 printk("Error can't allocate device instance data\n");
4258 } else {
44b7d1b3 4259 tty_port_init(&info->port);
31f35939 4260 info->port.ops = &mgsl_port_ops;
1da177e4 4261 info->magic = MGSL_MAGIC;
c4028958 4262 INIT_WORK(&info->task, mgsl_bh_handler);
1da177e4 4263 info->max_frame_size = 4096;
44b7d1b3
AC		 4264 info->port.close_delay = 5*HZ/10;
4265 info->port.closing_wait = 30*HZ;
1da177e4
LT		 4266 init_waitqueue_head(&info->status_event_wait_q);
4267 init_waitqueue_head(&info->event_wait_q);
4268 spin_lock_init(&info->irq_spinlock);
4269 spin_lock_init(&info->netlock);
4270 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
e06922aa 4271 info->idle_mode = HDLC_TXIDLE_FLAGS;
1da177e4
LT		 4272 info->num_tx_dma_buffers = 1;
4273 info->num_tx_holding_buffers = 0;
4274 }
4275
4276 return info;
4277
4278} /* end of mgsl_allocate_device()*/
4279
b68e31d0 4280static const struct tty_operations mgsl_ops = {
8a3ad104 4281 .install = mgsl_install,
1da177e4
LT		 4282 .open = mgsl_open,
4283 .close = mgsl_close,
4284 .write = mgsl_write,
4285 .put_char = mgsl_put_char,
4286 .flush_chars = mgsl_flush_chars,
4287 .write_room = mgsl_write_room,
4288 .chars_in_buffer = mgsl_chars_in_buffer,
4289 .flush_buffer = mgsl_flush_buffer,
4290 .ioctl = mgsl_ioctl,
4291 .throttle = mgsl_throttle,
4292 .unthrottle = mgsl_unthrottle,
4293 .send_xchar = mgsl_send_xchar,
4294 .break_ctl = mgsl_break,
4295 .wait_until_sent = mgsl_wait_until_sent,
1da177e4
LT		 4296 .set_termios = mgsl_set_termios,
4297 .stop = mgsl_stop,
4298 .start = mgsl_start,
4299 .hangup = mgsl_hangup,
4300 .tiocmget = tiocmget,
4301 .tiocmset = tiocmset,
0587102c 4302 .get_icount = msgl_get_icount,
d337829b 4303 .proc_fops = &mgsl_proc_fops,
1da177e4
LT		 4304};
4305
4306/*
4307 * perform tty device initialization
4308 */
4309static int mgsl_init_tty(void)
4310{
4311 int rc;
4312
4313 serial_driver = alloc_tty_driver(128);
4314 if (!serial_driver)
4315 return -ENOMEM;
4316
1da177e4
LT		 4317 serial_driver->driver_name = "synclink";
4318 serial_driver->name = "ttySL";
4319 serial_driver->major = ttymajor;
4320 serial_driver->minor_start = 64;
4321 serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
4322 serial_driver->subtype = SERIAL_TYPE_NORMAL;
4323 serial_driver->init_termios = tty_std_termios;
4324 serial_driver->init_termios.c_cflag =
4325 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
606d099c
AC		 4326 serial_driver->init_termios.c_ispeed = 9600;
4327 serial_driver->init_termios.c_ospeed = 9600;
1da177e4
LT		 4328 serial_driver->flags = TTY_DRIVER_REAL_RAW;
4329 tty_set_operations(serial_driver, &mgsl_ops);
4330 if ((rc = tty_register_driver(serial_driver)) < 0) {
4331 printk("%s(%d):Couldn't register serial driver\n",
4332 __FILE__,__LINE__);
4333 put_tty_driver(serial_driver);
4334 serial_driver = NULL;
4335 return rc;
4336 }
4337
4338 printk("%s %s, tty major#%d\n",
4339 driver_name, driver_version,
4340 serial_driver->major);
4341 return 0;
4342}
4343
4344/* enumerate user specified ISA adapters
4345 */
4346static void mgsl_enum_isa_devices(void)
4347{
4348 struct mgsl_struct *info;
4349 int i;
4350
4351 /* Check for user specified ISA devices */
4352
4353 for (i=0 ;(i < MAX_ISA_DEVICES) && io[i] && irq[i]; i++){
4354 if ( debug_level >= DEBUG_LEVEL_INFO )
4355 printk("ISA device specified io=%04X,irq=%d,dma=%d\n",
4356 io[i], irq[i], dma[i] );
4357
4358 info = mgsl_allocate_device();
4359 if ( !info ) {
4360 /* error allocating device instance data */
4361 if ( debug_level >= DEBUG_LEVEL_ERROR )
4362 printk( "can't allocate device instance data.\n");
4363 continue;
4364 }
4365
4366 /* Copy user configuration info to device instance data */
4367 info->io_base = (unsigned int)io[i];
4368 info->irq_level = (unsigned int)irq[i];
4369 info->irq_level = irq_canonicalize(info->irq_level);
4370 info->dma_level = (unsigned int)dma[i];
4371 info->bus_type = MGSL_BUS_TYPE_ISA;
4372 info->io_addr_size = 16;
4373 info->irq_flags = 0;
4374
4375 mgsl_add_device( info );
4376 }
4377}
4378
4379static void synclink_cleanup(void)
4380{
4381 int rc;
4382 struct mgsl_struct *info;
4383 struct mgsl_struct *tmp;
4384
4385 printk("Unloading %s: %s\n", driver_name, driver_version);
4386
4387 if (serial_driver) {
a271ca37
GKH		 4388 rc = tty_unregister_driver(serial_driver);
4389 if (rc)
1da177e4
LT		 4390 printk("%s(%d) failed to unregister tty driver err=%d\n",
4391 __FILE__,__LINE__,rc);
4392 put_tty_driver(serial_driver);
4393 }
4394
4395 info = mgsl_device_list;
4396 while(info) {
af69c7f9 4397#if SYNCLINK_GENERIC_HDLC
1da177e4
LT		 4398 hdlcdev_exit(info);
4399#endif
4400 mgsl_release_resources(info);
4401 tmp = info;
4402 info = info->next_device;
191c5f10 4403 tty_port_destroy(&tmp->port);
1da177e4
LT		 4404 kfree(tmp);
4405 }
4406
1da177e4
LT		 4407 if (pci_registered)
4408 pci_unregister_driver(&synclink_pci_driver);
4409}
4410
4411static int __init synclink_init(void)
4412{
4413 int rc;
4414
4415 if (break_on_load) {
4416 mgsl_get_text_ptr();
4417 BREAKPOINT();
4418 }
4419
4420 printk("%s %s\n", driver_name, driver_version);
4421
4422 mgsl_enum_isa_devices();
4423 if ((rc = pci_register_driver(&synclink_pci_driver)) < 0)
4424 printk("%s:failed to register PCI driver, error=%d\n",__FILE__,rc);
4425 else
0fab6de0 4426 pci_registered = true;
1da177e4
LT		 4427
4428 if ((rc = mgsl_init_tty()) < 0)
4429 goto error;
4430
4431 return 0;
4432
4433error:
4434 synclink_cleanup();
4435 return rc;
4436}
4437
4438static void __exit synclink_exit(void)
4439{
4440 synclink_cleanup();
4441}
4442
4443module_init(synclink_init);
4444module_exit(synclink_exit);
4445
4446/*
4447 * usc_RTCmd()
4448 *
4449 * Issue a USC Receive/Transmit command to the
4450 * Channel Command/Address Register (CCAR).
4451 *
4452 * Notes:
4453 *
4454 * The command is encoded in the most significant 5 bits <15..11>
4455 * of the CCAR value. Bits <10..7> of the CCAR must be preserved
4456 * and Bits <6..0> must be written as zeros.
4457 *
4458 * Arguments:
4459 *
4460 * info pointer to device information structure
4461 * Cmd command mask (use symbolic macros)
4462 *
4463 * Return Value:
4464 *
4465 * None
4466 */
4467static void usc_RTCmd( struct mgsl_struct *info, u16 Cmd )
4468{
4469 /* output command to CCAR in bits <15..11> */
4470 /* preserve bits <10..7>, bits <6..0> must be zero */
4471
4472 outw( Cmd + info->loopback_bits, info->io_base + CCAR );
4473
4474 /* Read to flush write to CCAR */
4475 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4476 inw( info->io_base + CCAR );
4477
4478} /* end of usc_RTCmd() */
4479
4480/*
4481 * usc_DmaCmd()
4482 *
4483 * Issue a DMA command to the DMA Command/Address Register (DCAR).
4484 *
4485 * Arguments:
4486 *
4487 * info pointer to device information structure
4488 * Cmd DMA command mask (usc_DmaCmd_XX Macros)
4489 *
4490 * Return Value:
4491 *
4492 * None
4493 */
4494static void usc_DmaCmd( struct mgsl_struct *info, u16 Cmd )
4495{
4496 /* write command mask to DCAR */
4497 outw( Cmd + info->mbre_bit, info->io_base );
4498
4499 /* Read to flush write to DCAR */
4500 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4501 inw( info->io_base );
4502
4503} /* end of usc_DmaCmd() */
4504
4505/*
4506 * usc_OutDmaReg()
4507 *
4508 * Write a 16-bit value to a USC DMA register
4509 *
4510 * Arguments:
4511 *
4512 * info pointer to device info structure
4513 * RegAddr register address (number) for write
4514 * RegValue 16-bit value to write to register
4515 *
4516 * Return Value:
4517 *
4518 * None
4519 *
4520 */
4521static void usc_OutDmaReg( struct mgsl_struct *info, u16 RegAddr, u16 RegValue )
4522{
4523 /* Note: The DCAR is located at the adapter base address */
4524 /* Note: must preserve state of BIT8 in DCAR */
4525
4526 outw( RegAddr + info->mbre_bit, info->io_base );
4527 outw( RegValue, info->io_base );
4528
4529 /* Read to flush write to DCAR */
4530 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4531 inw( info->io_base );
4532
4533} /* end of usc_OutDmaReg() */
4534
4535/*
4536 * usc_InDmaReg()
4537 *
4538 * Read a 16-bit value from a DMA register
4539 *
4540 * Arguments:
4541 *
4542 * info pointer to device info structure
4543 * RegAddr register address (number) to read from
4544 *
4545 * Return Value:
4546 *
4547 * The 16-bit value read from register
4548 *
4549 */
4550static u16 usc_InDmaReg( struct mgsl_struct *info, u16 RegAddr )
4551{
4552 /* Note: The DCAR is located at the adapter base address */
4553 /* Note: must preserve state of BIT8 in DCAR */
4554
4555 outw( RegAddr + info->mbre_bit, info->io_base );
4556 return inw( info->io_base );
4557
4558} /* end of usc_InDmaReg() */
4559
4560/*
4561 *
4562 * usc_OutReg()
4563 *
4564 * Write a 16-bit value to a USC serial channel register
4565 *
4566 * Arguments:
4567 *
4568 * info pointer to device info structure
4569 * RegAddr register address (number) to write to
4570 * RegValue 16-bit value to write to register
4571 *
4572 * Return Value:
4573 *
4574 * None
4575 *
4576 */
4577static void usc_OutReg( struct mgsl_struct *info, u16 RegAddr, u16 RegValue )
4578{
4579 outw( RegAddr + info->loopback_bits, info->io_base + CCAR );
4580 outw( RegValue, info->io_base + CCAR );
4581
4582 /* Read to flush write to CCAR */
4583 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4584 inw( info->io_base + CCAR );
4585
4586} /* end of usc_OutReg() */
4587
4588/*
4589 * usc_InReg()
4590 *
4591 * Reads a 16-bit value from a USC serial channel register
4592 *
4593 * Arguments:
4594 *
4595 * info pointer to device extension
4596 * RegAddr register address (number) to read from
4597 *
4598 * Return Value:
4599 *
4600 * 16-bit value read from register
4601 */
4602static u16 usc_InReg( struct mgsl_struct *info, u16 RegAddr )
4603{
4604 outw( RegAddr + info->loopback_bits, info->io_base + CCAR );
4605 return inw( info->io_base + CCAR );
4606
4607} /* end of usc_InReg() */
4608
4609/* usc_set_sdlc_mode()
4610 *
4611 * Set up the adapter for SDLC DMA communications.
4612 *
4613 * Arguments: info pointer to device instance data
4614 * Return Value: NONE
4615 */
4616static void usc_set_sdlc_mode( struct mgsl_struct *info )
4617{
4618 u16 RegValue;
0fab6de0 4619 bool PreSL1660;
1da177e4
LT		 4620
4621 /*
4622 * determine if the IUSC on the adapter is pre-SL1660. If
4623 * not, take advantage of the UnderWait feature of more
4624 * modern chips. If an underrun occurs and this bit is set,
4625 * the transmitter will idle the programmed idle pattern
4626 * until the driver has time to service the underrun. Otherwise,
4627 * the dma controller may get the cycles previously requested
4628 * and begin transmitting queued tx data.
4629 */
4630 usc_OutReg(info,TMCR,0x1f);
4631 RegValue=usc_InReg(info,TMDR);
0fab6de0 4632 PreSL1660 = (RegValue == IUSC_PRE_SL1660);
1da177e4
LT		 4633
4634 if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
4635 {
4636 /*
4637 ** Channel Mode Register (CMR)
4638 **
4639 ** <15..14> 10 Tx Sub Modes, Send Flag on Underrun
4640 ** <13> 0 0 = Transmit Disabled (initially)
4641 ** <12> 0 1 = Consecutive Idles share common 0
4642 ** <11..8> 1110 Transmitter Mode = HDLC/SDLC Loop
4643 ** <7..4> 0000 Rx Sub Modes, addr/ctrl field handling
4644 ** <3..0> 0110 Receiver Mode = HDLC/SDLC
4645 **
4646 ** 1000 1110 0000 0110 = 0x8e06
4647 */
4648 RegValue = 0x8e06;
4649
4650 /*--------------------------------------------------
4651 * ignore user options for UnderRun Actions and
4652 * preambles
4653 *--------------------------------------------------*/
4654 }
4655 else
4656 {
4657 /* Channel mode Register (CMR)
4658 *
4659 * <15..14> 00 Tx Sub modes, Underrun Action
4660 * <13> 0 1 = Send Preamble before opening flag
4661 * <12> 0 1 = Consecutive Idles share common 0
4662 * <11..8> 0110 Transmitter mode = HDLC/SDLC
4663 * <7..4> 0000 Rx Sub modes, addr/ctrl field handling
4664 * <3..0> 0110 Receiver mode = HDLC/SDLC
4665 *
4666 * 0000 0110 0000 0110 = 0x0606
4667 */
4668 if (info->params.mode == MGSL_MODE_RAW) {
4669 RegValue = 0x0001; /* Set Receive mode = external sync */
4670
4671 usc_OutReg( info, IOCR, /* Set IOCR DCD is RxSync Detect Input */
4672 (unsigned short)((usc_InReg(info, IOCR) & ~(BIT13|BIT12)) | BIT12));
4673
4674 /*
4675 * TxSubMode:
4676 * CMR <15> 0 Don't send CRC on Tx Underrun
4677 * CMR <14> x undefined
4678 * CMR <13> 0 Send preamble before openning sync
4679 * CMR <12> 0 Send 8-bit syncs, 1=send Syncs per TxLength
4680 *
4681 * TxMode:
4682 * CMR <11-8) 0100 MonoSync
4683 *
4684 * 0x00 0100 xxxx xxxx 04xx
4685 */
4686 RegValue |= 0x0400;
4687 }
4688 else {
4689
4690 RegValue = 0x0606;
4691
4692 if ( info->params.flags & HDLC_FLAG_UNDERRUN_ABORT15 )
4693 RegValue |= BIT14;
4694 else if ( info->params.flags & HDLC_FLAG_UNDERRUN_FLAG )
4695 RegValue |= BIT15;
4696 else if ( info->params.flags & HDLC_FLAG_UNDERRUN_CRC )
e06922aa 4697 RegValue |= BIT15 | BIT14;
1da177e4
LT		 4698 }
4699
4700 if ( info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE )
4701 RegValue |= BIT13;
4702 }
4703
4704 if ( info->params.mode == MGSL_MODE_HDLC &&
4705 (info->params.flags & HDLC_FLAG_SHARE_ZERO) )
4706 RegValue |= BIT12;
4707
4708 if ( info->params.addr_filter != 0xff )
4709 {
4710 /* set up receive address filtering */
4711 usc_OutReg( info, RSR, info->params.addr_filter );
4712 RegValue |= BIT4;
4713 }
4714
4715 usc_OutReg( info, CMR, RegValue );
4716 info->cmr_value = RegValue;
4717
4718 /* Receiver mode Register (RMR)
4719 *
4720 * <15..13> 000 encoding
4721 * <12..11> 00 FCS = 16bit CRC CCITT (x15 + x12 + x5 + 1)
4722 * <10> 1 1 = Set CRC to all 1s (use for SDLC/HDLC)
4723 * <9> 0 1 = Include Receive chars in CRC
4724 * <8> 1 1 = Use Abort/PE bit as abort indicator
4725 * <7..6> 00 Even parity
4726 * <5> 0 parity disabled
4727 * <4..2> 000 Receive Char Length = 8 bits
4728 * <1..0> 00 Disable Receiver
4729 *
4730 * 0000 0101 0000 0000 = 0x0500
4731 */
4732
4733 RegValue = 0x0500;
4734
4735 switch ( info->params.encoding ) {
4736 case HDLC_ENCODING_NRZB: RegValue |= BIT13; break;
4737 case HDLC_ENCODING_NRZI_MARK: RegValue |= BIT14; break;
e06922aa 4738 case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT14 | BIT13; break;
1da177e4 4739 case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT15; break;
e06922aa
AJ		 4740 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT15 | BIT13; break;
4741 case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT15 | BIT14; break;
4742 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT15 | BIT14 | BIT13; break;
1da177e4
LT		 4743 }
4744
4745 if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_16_CCITT )
4746 RegValue |= BIT9;
4747 else if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_32_CCITT )
4748 RegValue |= ( BIT12 | BIT10 | BIT9 );
4749
4750 usc_OutReg( info, RMR, RegValue );
4751
4752 /* Set the Receive count Limit Register (RCLR) to 0xffff. */
4753 /* When an opening flag of an SDLC frame is recognized the */
4754 /* Receive Character count (RCC) is loaded with the value in */
4755 /* RCLR. The RCC is decremented for each received byte. The */
4756 /* value of RCC is stored after the closing flag of the frame */
4757 /* allowing the frame size to be computed. */
4758
4759 usc_OutReg( info, RCLR, RCLRVALUE );
4760
4761 usc_RCmd( info, RCmd_SelectRicrdma_level );
4762
4763 /* Receive Interrupt Control Register (RICR)
4764 *
4765 * <15..8> ? RxFIFO DMA Request Level
4766 * <7> 0 Exited Hunt IA (Interrupt Arm)
4767 * <6> 0 Idle Received IA
4768 * <5> 0 Break/Abort IA
4769 * <4> 0 Rx Bound IA
4770 * <3> 1 Queued status reflects oldest 2 bytes in FIFO
4771 * <2> 0 Abort/PE IA
4772 * <1> 1 Rx Overrun IA
4773 * <0> 0 Select TC0 value for readback
4774 *
4775 * 0000 0000 0000 1000 = 0x000a
4776 */
4777
4778 /* Carry over the Exit Hunt and Idle Received bits */
4779 /* in case they have been armed by usc_ArmEvents. */
4780
4781 RegValue = usc_InReg( info, RICR ) & 0xc0;
4782
4783 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4784 usc_OutReg( info, RICR, (u16)(0x030a | RegValue) );
4785 else
4786 usc_OutReg( info, RICR, (u16)(0x140a | RegValue) );
4787
4788 /* Unlatch all Rx status bits and clear Rx status IRQ Pending */
4789
4790 usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
4791 usc_ClearIrqPendingBits( info, RECEIVE_STATUS );
4792
4793 /* Transmit mode Register (TMR)
4794 *
4795 * <15..13> 000 encoding
4796 * <12..11> 00 FCS = 16bit CRC CCITT (x15 + x12 + x5 + 1)
4797 * <10> 1 1 = Start CRC as all 1s (use for SDLC/HDLC)
4798 * <9> 0 1 = Tx CRC Enabled
4799 * <8> 0 1 = Append CRC to end of transmit frame
4800 * <7..6> 00 Transmit parity Even
4801 * <5> 0 Transmit parity Disabled
4802 * <4..2> 000 Tx Char Length = 8 bits
4803 * <1..0> 00 Disable Transmitter
4804 *
4805 * 0000 0100 0000 0000 = 0x0400
4806 */
4807
4808 RegValue = 0x0400;
4809
4810 switch ( info->params.encoding ) {
4811 case HDLC_ENCODING_NRZB: RegValue |= BIT13; break;
4812 case HDLC_ENCODING_NRZI_MARK: RegValue |= BIT14; break;
e06922aa 4813 case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT14 | BIT13; break;
1da177e4 4814 case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT15; break;
e06922aa
AJ		 4815 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT15 | BIT13; break;
4816 case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT15 | BIT14; break;
4817 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT15 | BIT14 | BIT13; break;
1da177e4
LT		 4818 }
4819
4820 if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_16_CCITT )
e06922aa 4821 RegValue |= BIT9 | BIT8;
1da177e4
LT		 4822 else if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_32_CCITT )
4823 RegValue |= ( BIT12 | BIT10 | BIT9 | BIT8);
4824
4825 usc_OutReg( info, TMR, RegValue );
4826
4827 usc_set_txidle( info );
4828
4829
4830 usc_TCmd( info, TCmd_SelectTicrdma_level );
4831
4832 /* Transmit Interrupt Control Register (TICR)
4833 *
4834 * <15..8> ? Transmit FIFO DMA Level
4835 * <7> 0 Present IA (Interrupt Arm)
4836 * <6> 0 Idle Sent IA
4837 * <5> 1 Abort Sent IA
4838 * <4> 1 EOF/EOM Sent IA
4839 * <3> 0 CRC Sent IA
4840 * <2> 1 1 = Wait for SW Trigger to Start Frame
4841 * <1> 1 Tx Underrun IA
4842 * <0> 0 TC0 constant on read back
4843 *
4844 * 0000 0000 0011 0110 = 0x0036
4845 */
4846
4847 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4848 usc_OutReg( info, TICR, 0x0736 );
4849 else
4850 usc_OutReg( info, TICR, 0x1436 );
4851
4852 usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
4853 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
4854
4855 /*
4856 ** Transmit Command/Status Register (TCSR)
4857 **
4858 ** <15..12> 0000 TCmd
4859 ** <11> 0/1 UnderWait
4860 ** <10..08> 000 TxIdle
4861 ** <7> x PreSent
4862 ** <6> x IdleSent
4863 ** <5> x AbortSent
4864 ** <4> x EOF/EOM Sent
4865 ** <3> x CRC Sent
4866 ** <2> x All Sent
4867 ** <1> x TxUnder
4868 ** <0> x TxEmpty
4869 **
4870 ** 0000 0000 0000 0000 = 0x0000
4871 */
4872 info->tcsr_value = 0;
4873
4874 if ( !PreSL1660 )
4875 info->tcsr_value |= TCSR_UNDERWAIT;
4876
4877 usc_OutReg( info, TCSR, info->tcsr_value );
4878
4879 /* Clock mode Control Register (CMCR)
4880 *
4881 * <15..14> 00 counter 1 Source = Disabled
4882 * <13..12> 00 counter 0 Source = Disabled
4883 * <11..10> 11 BRG1 Input is TxC Pin
4884 * <9..8> 11 BRG0 Input is TxC Pin
4885 * <7..6> 01 DPLL Input is BRG1 Output
4886 * <5..3> XXX TxCLK comes from Port 0
4887 * <2..0> XXX RxCLK comes from Port 1
4888 *
4889 * 0000 1111 0111 0111 = 0x0f77
4890 */
4891
4892 RegValue = 0x0f40;
4893
4894 if ( info->params.flags & HDLC_FLAG_RXC_DPLL )
4895 RegValue |= 0x0003; /* RxCLK from DPLL */
4896 else if ( info->params.flags & HDLC_FLAG_RXC_BRG )
4897 RegValue |= 0x0004; /* RxCLK from BRG0 */
4898 else if ( info->params.flags & HDLC_FLAG_RXC_TXCPIN)
4899 RegValue |= 0x0006; /* RxCLK from TXC Input */
4900 else
4901 RegValue |= 0x0007; /* RxCLK from Port1 */
4902
4903 if ( info->params.flags & HDLC_FLAG_TXC_DPLL )
4904 RegValue |= 0x0018; /* TxCLK from DPLL */
4905 else if ( info->params.flags & HDLC_FLAG_TXC_BRG )
4906 RegValue |= 0x0020; /* TxCLK from BRG0 */
4907 else if ( info->params.flags & HDLC_FLAG_TXC_RXCPIN)
4908 RegValue |= 0x0038; /* RxCLK from TXC Input */
4909 else
4910 RegValue |= 0x0030; /* TxCLK from Port0 */
4911
4912 usc_OutReg( info, CMCR, RegValue );
4913
4914
4915 /* Hardware Configuration Register (HCR)
4916 *
4917 * <15..14> 00 CTR0 Divisor:00=32,01=16,10=8,11=4
4918 * <13> 0 CTR1DSel:0=CTR0Div determines CTR0Div
4919 * <12> 0 CVOK:0=report code violation in biphase
4920 * <11..10> 00 DPLL Divisor:00=32,01=16,10=8,11=4
4921 * <9..8> XX DPLL mode:00=disable,01=NRZ,10=Biphase,11=Biphase Level
4922 * <7..6> 00 reserved
4923 * <5> 0 BRG1 mode:0=continuous,1=single cycle
4924 * <4> X BRG1 Enable
4925 * <3..2> 00 reserved
4926 * <1> 0 BRG0 mode:0=continuous,1=single cycle
4927 * <0> 0 BRG0 Enable
4928 */
4929
4930 RegValue = 0x0000;
4931
e06922aa 4932 if ( info->params.flags & (HDLC_FLAG_RXC_DPLL | HDLC_FLAG_TXC_DPLL) ) {
1da177e4
LT		 4933 u32 XtalSpeed;
4934 u32 DpllDivisor;
4935 u16 Tc;
4936
4937 /* DPLL is enabled. Use BRG1 to provide continuous reference clock */
4938 /* for DPLL. DPLL mode in HCR is dependent on the encoding used. */
4939
4940 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4941 XtalSpeed = 11059200;
4942 else
4943 XtalSpeed = 14745600;
4944
4945 if ( info->params.flags & HDLC_FLAG_DPLL_DIV16 ) {
4946 DpllDivisor = 16;
4947 RegValue |= BIT10;
4948 }
4949 else if ( info->params.flags & HDLC_FLAG_DPLL_DIV8 ) {
4950 DpllDivisor = 8;
4951 RegValue |= BIT11;
4952 }
4953 else
4954 DpllDivisor = 32;
4955
4956 /* Tc = (Xtal/Speed) - 1 */
4957 /* If twice the remainder of (Xtal/Speed) is greater than Speed */
4958 /* then rounding up gives a more precise time constant. Instead */
4959 /* of rounding up and then subtracting 1 we just don't subtract */
4960 /* the one in this case. */
4961
4962 /*--------------------------------------------------
4963 * ejz: for DPLL mode, application should use the
4964 * same clock speed as the partner system, even
4965 * though clocking is derived from the input RxData.
4966 * In case the user uses a 0 for the clock speed,
4967 * default to 0xffffffff and don't try to divide by
4968 * zero
4969 *--------------------------------------------------*/
4970 if ( info->params.clock_speed )
4971 {
4972 Tc = (u16)((XtalSpeed/DpllDivisor)/info->params.clock_speed);
4973 if ( !((((XtalSpeed/DpllDivisor) % info->params.clock_speed) * 2)
4974 / info->params.clock_speed) )
4975 Tc--;
4976 }
4977 else
4978 Tc = -1;
4979
4980
4981 /* Write 16-bit Time Constant for BRG1 */
4982 usc_OutReg( info, TC1R, Tc );
4983
4984 RegValue |= BIT4; /* enable BRG1 */
4985
4986 switch ( info->params.encoding ) {
4987 case HDLC_ENCODING_NRZ:
4988 case HDLC_ENCODING_NRZB:
4989 case HDLC_ENCODING_NRZI_MARK:
4990 case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT8; break;
4991 case HDLC_ENCODING_BIPHASE_MARK:
4992 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT9; break;
4993 case HDLC_ENCODING_BIPHASE_LEVEL:
e06922aa 4994 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT9 | BIT8; break;
1da177e4
LT		 4995 }
4996 }
4997
4998 usc_OutReg( info, HCR, RegValue );
4999
5000
5001 /* Channel Control/status Register (CCSR)
5002 *
5003 * <15> X RCC FIFO Overflow status (RO)
5004 * <14> X RCC FIFO Not Empty status (RO)
5005 * <13> 0 1 = Clear RCC FIFO (WO)
5006 * <12> X DPLL Sync (RW)
5007 * <11> X DPLL 2 Missed Clocks status (RO)
5008 * <10> X DPLL 1 Missed Clock status (RO)
5009 * <9..8> 00 DPLL Resync on rising and falling edges (RW)
5010 * <7> X SDLC Loop On status (RO)
5011 * <6> X SDLC Loop Send status (RO)
5012 * <5> 1 Bypass counters for TxClk and RxClk (RW)
5013 * <4..2> 000 Last Char of SDLC frame has 8 bits (RW)
5014 * <1..0> 00 reserved
5015 *
5016 * 0000 0000 0010 0000 = 0x0020
5017 */
5018
5019 usc_OutReg( info, CCSR, 0x1020 );
5020
5021
5022 if ( info->params.flags & HDLC_FLAG_AUTO_CTS ) {
5023 usc_OutReg( info, SICR,
5024 (u16)(usc_InReg(info,SICR) | SICR_CTS_INACTIVE) );
5025 }
5026
5027
5028 /* enable Master Interrupt Enable bit (MIE) */
5029 usc_EnableMasterIrqBit( info );
5030
e06922aa
AJ		 5031 usc_ClearIrqPendingBits( info, RECEIVE_STATUS | RECEIVE_DATA |
5032 TRANSMIT_STATUS | TRANSMIT_DATA | MISC);
1da177e4
LT		 5033
5034 /* arm RCC underflow interrupt */
5035 usc_OutReg(info, SICR, (u16)(usc_InReg(info,SICR) | BIT3));
5036 usc_EnableInterrupts(info, MISC);
5037
5038 info->mbre_bit = 0;
5039 outw( 0, info->io_base ); /* clear Master Bus Enable (DCAR) */
5040 usc_DmaCmd( info, DmaCmd_ResetAllChannels ); /* disable both DMA channels */
5041 info->mbre_bit = BIT8;
5042 outw( BIT8, info->io_base ); /* set Master Bus Enable (DCAR) */
5043
5044 if (info->bus_type == MGSL_BUS_TYPE_ISA) {
5045 /* Enable DMAEN (Port 7, Bit 14) */
5046 /* This connects the DMA request signal to the ISA bus */
5047 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT15) & ~BIT14));
5048 }
5049
5050 /* DMA Control Register (DCR)
5051 *
5052 * <15..14> 10 Priority mode = Alternating Tx/Rx
5053 * 01 Rx has priority
5054 * 00 Tx has priority
5055 *
5056 * <13> 1 Enable Priority Preempt per DCR<15..14>
5057 * (WARNING DCR<11..10> must be 00 when this is 1)
5058 * 0 Choose activate channel per DCR<11..10>
5059 *
5060 * <12> 0 Little Endian for Array/List
5061 * <11..10> 00 Both Channels can use each bus grant
5062 * <9..6> 0000 reserved
5063 * <5> 0 7 CLK - Minimum Bus Re-request Interval
5064 * <4> 0 1 = drive D/C and S/D pins
5065 * <3> 1 1 = Add one wait state to all DMA cycles.
5066 * <2> 0 1 = Strobe /UAS on every transfer.
5067 * <1..0> 11 Addr incrementing only affects LS24 bits
5068 *
5069 * 0110 0000 0000 1011 = 0x600b
5070 */
5071
5072 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
5073 /* PCI adapter does not need DMA wait state */
5074 usc_OutDmaReg( info, DCR, 0xa00b );
5075 }
5076 else
5077 usc_OutDmaReg( info, DCR, 0x800b );
5078
5079
5080 /* Receive DMA mode Register (RDMR)
5081 *
5082 * <15..14> 11 DMA mode = Linked List Buffer mode
5083 * <13> 1 RSBinA/L = store Rx status Block in Arrary/List entry
5084 * <12> 1 Clear count of List Entry after fetching
5085 * <11..10> 00 Address mode = Increment
5086 * <9> 1 Terminate Buffer on RxBound
5087 * <8> 0 Bus Width = 16bits
5088 * <7..0> ? status Bits (write as 0s)
5089 *
5090 * 1111 0010 0000 0000 = 0xf200
5091 */
5092
5093 usc_OutDmaReg( info, RDMR, 0xf200 );
5094
5095
5096 /* Transmit DMA mode Register (TDMR)
5097 *
5098 * <15..14> 11 DMA mode = Linked List Buffer mode
5099 * <13> 1 TCBinA/L = fetch Tx Control Block from List entry
5100 * <12> 1 Clear count of List Entry after fetching
5101 * <11..10> 00 Address mode = Increment
5102 * <9> 1 Terminate Buffer on end of frame
5103 * <8> 0 Bus Width = 16bits
5104 * <7..0> ? status Bits (Read Only so write as 0)
5105 *
5106 * 1111 0010 0000 0000 = 0xf200
5107 */
5108
5109 usc_OutDmaReg( info, TDMR, 0xf200 );
5110
5111
5112 /* DMA Interrupt Control Register (DICR)
5113 *
5114 * <15> 1 DMA Interrupt Enable
5115 * <14> 0 1 = Disable IEO from USC
5116 * <13> 0 1 = Don't provide vector during IntAck
5117 * <12> 1 1 = Include status in Vector
5118 * <10..2> 0 reserved, Must be 0s
5119 * <1> 0 1 = Rx DMA Interrupt Enabled
5120 * <0> 0 1 = Tx DMA Interrupt Enabled
5121 *
5122 * 1001 0000 0000 0000 = 0x9000
5123 */
5124
5125 usc_OutDmaReg( info, DICR, 0x9000 );
5126
5127 usc_InDmaReg( info, RDMR ); /* clear pending receive DMA IRQ bits */
5128 usc_InDmaReg( info, TDMR ); /* clear pending transmit DMA IRQ bits */
5129 usc_OutDmaReg( info, CDIR, 0x0303 ); /* clear IUS and Pending for Tx and Rx */
5130
5131 /* Channel Control Register (CCR)
5132 *
5133 * <15..14> 10 Use 32-bit Tx Control Blocks (TCBs)
5134 * <13> 0 Trigger Tx on SW Command Disabled
5135 * <12> 0 Flag Preamble Disabled
5136 * <11..10> 00 Preamble Length
5137 * <9..8> 00 Preamble Pattern
5138 * <7..6> 10 Use 32-bit Rx status Blocks (RSBs)
5139 * <5> 0 Trigger Rx on SW Command Disabled
5140 * <4..0> 0 reserved
5141 *
5142 * 1000 0000 1000 0000 = 0x8080
5143 */
5144
5145 RegValue = 0x8080;
5146
5147 switch ( info->params.preamble_length ) {
5148 case HDLC_PREAMBLE_LENGTH_16BITS: RegValue |= BIT10; break;
5149 case HDLC_PREAMBLE_LENGTH_32BITS: RegValue |= BIT11; break;
e06922aa 5150 case HDLC_PREAMBLE_LENGTH_64BITS: RegValue |= BIT11 | BIT10; break;
1da177e4
LT		 5151 }
5152
5153 switch ( info->params.preamble ) {
e06922aa 5154 case HDLC_PREAMBLE_PATTERN_FLAGS: RegValue |= BIT8 | BIT12; break;
1da177e4
LT		 5155 case HDLC_PREAMBLE_PATTERN_ONES: RegValue |= BIT8; break;
5156 case HDLC_PREAMBLE_PATTERN_10: RegValue |= BIT9; break;
e06922aa 5157 case HDLC_PREAMBLE_PATTERN_01: RegValue |= BIT9 | BIT8; break;
1da177e4
LT		 5158 }
5159
5160 usc_OutReg( info, CCR, RegValue );
5161
5162
5163 /*
5164 * Burst/Dwell Control Register
5165 *
5166 * <15..8> 0x20 Maximum number of transfers per bus grant
5167 * <7..0> 0x00 Maximum number of clock cycles per bus grant
5168 */
5169
5170 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
5171 /* don't limit bus occupancy on PCI adapter */
5172 usc_OutDmaReg( info, BDCR, 0x0000 );
5173 }
5174 else
5175 usc_OutDmaReg( info, BDCR, 0x2000 );
5176
5177 usc_stop_transmitter(info);
5178 usc_stop_receiver(info);
5179
5180} /* end of usc_set_sdlc_mode() */
5181
5182/* usc_enable_loopback()
5183 *
5184 * Set the 16C32 for internal loopback mode.
5185 * The TxCLK and RxCLK signals are generated from the BRG0 and
5186 * the TxD is looped back to the RxD internally.
5187 *
5188 * Arguments: info pointer to device instance data
5189 * enable 1 = enable loopback, 0 = disable
5190 * Return Value: None
5191 */
5192static void usc_enable_loopback(struct mgsl_struct *info, int enable)
5193{
5194 if (enable) {
5195 /* blank external TXD output */
e06922aa 5196 usc_OutReg(info,IOCR,usc_InReg(info,IOCR) | (BIT7 | BIT6));
1da177e4
LT		 5197
5198 /* Clock mode Control Register (CMCR)
5199 *
5200 * <15..14> 00 counter 1 Disabled
5201 * <13..12> 00 counter 0 Disabled
5202 * <11..10> 11 BRG1 Input is TxC Pin
5203 * <9..8> 11 BRG0 Input is TxC Pin
5204 * <7..6> 01 DPLL Input is BRG1 Output
5205 * <5..3> 100 TxCLK comes from BRG0
5206 * <2..0> 100 RxCLK comes from BRG0
5207 *
5208 * 0000 1111 0110 0100 = 0x0f64
5209 */
5210
5211 usc_OutReg( info, CMCR, 0x0f64 );
5212
5213 /* Write 16-bit Time Constant for BRG0 */
5214 /* use clock speed if available, otherwise use 8 for diagnostics */
5215 if (info->params.clock_speed) {
5216 if (info->bus_type == MGSL_BUS_TYPE_PCI)
5217 usc_OutReg(info, TC0R, (u16)((11059200/info->params.clock_speed)-1));
5218 else
5219 usc_OutReg(info, TC0R, (u16)((14745600/info->params.clock_speed)-1));
5220 } else
5221 usc_OutReg(info, TC0R, (u16)8);
5222
5223 /* Hardware Configuration Register (HCR) Clear Bit 1, BRG0
5224 mode = Continuous Set Bit 0 to enable BRG0. */
5225 usc_OutReg( info, HCR, (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) );
5226
5227 /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
5228 usc_OutReg(info, IOCR, (u16)((usc_InReg(info, IOCR) & 0xfff8) | 0x0004));
5229
5230 /* set Internal Data loopback mode */
5231 info->loopback_bits = 0x300;
5232 outw( 0x0300, info->io_base + CCAR );
5233 } else {
5234 /* enable external TXD output */
e06922aa 5235 usc_OutReg(info,IOCR,usc_InReg(info,IOCR) & ~(BIT7 | BIT6));
1da177e4
LT		 5236
5237 /* clear Internal Data loopback mode */
5238 info->loopback_bits = 0;
5239 outw( 0,info->io_base + CCAR );
5240 }
5241
5242} /* end of usc_enable_loopback() */
5243
5244/* usc_enable_aux_clock()
5245 *
5246 * Enabled the AUX clock output at the specified frequency.
5247 *
5248 * Arguments:
5249 *
5250 * info pointer to device extension
5251 * data_rate data rate of clock in bits per second
5252 * A data rate of 0 disables the AUX clock.
5253 *
5254 * Return Value: None
5255 */
5256static void usc_enable_aux_clock( struct mgsl_struct *info, u32 data_rate )
5257{
5258 u32 XtalSpeed;
5259 u16 Tc;
5260
5261 if ( data_rate ) {
5262 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
5263 XtalSpeed = 11059200;
5264 else
5265 XtalSpeed = 14745600;
5266
5267
5268 /* Tc = (Xtal/Speed) - 1 */
5269 /* If twice the remainder of (Xtal/Speed) is greater than Speed */
5270 /* then rounding up gives a more precise time constant. Instead */
5271 /* of rounding up and then subtracting 1 we just don't subtract */
5272 /* the one in this case. */
5273
5274
5275 Tc = (u16)(XtalSpeed/data_rate);
5276 if ( !(((XtalSpeed % data_rate) * 2) / data_rate) )
5277 Tc--;
5278
5279 /* Write 16-bit Time Constant for BRG0 */
5280 usc_OutReg( info, TC0R, Tc );
5281
5282 /*
5283 * Hardware Configuration Register (HCR)
5284 * Clear Bit 1, BRG0 mode = Continuous
5285 * Set Bit 0 to enable BRG0.
5286 */
5287
5288 usc_OutReg( info, HCR, (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) );
5289
5290 /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
5291 usc_OutReg( info, IOCR, (u16)((usc_InReg(info, IOCR) & 0xfff8) | 0x0004) );
5292 } else {
5293 /* data rate == 0 so turn off BRG0 */
5294 usc_OutReg( info, HCR, (u16)(usc_InReg( info, HCR ) & ~BIT0) );
5295 }
5296
5297} /* end of usc_enable_aux_clock() */
5298
5299/*
5300 *
5301 * usc_process_rxoverrun_sync()
5302 *
5303 * This function processes a receive overrun by resetting the
5304 * receive DMA buffers and issuing a Purge Rx FIFO command
5305 * to allow the receiver to continue receiving.
5306 *
5307 * Arguments:
5308 *
5309 * info pointer to device extension
5310 *
5311 * Return Value: None
5312 */
5313static void usc_process_rxoverrun_sync( struct mgsl_struct *info )
5314{
5315 int start_index;
5316 int end_index;
5317 int frame_start_index;
0fab6de0
JP		 5318 bool start_of_frame_found = false;
5319 bool end_of_frame_found = false;
5320 bool reprogram_dma = false;
1da177e4
LT		 5321
5322 DMABUFFERENTRY *buffer_list = info->rx_buffer_list;
5323 u32 phys_addr;
5324
5325 usc_DmaCmd( info, DmaCmd_PauseRxChannel );
5326 usc_RCmd( info, RCmd_EnterHuntmode );
5327 usc_RTCmd( info, RTCmd_PurgeRxFifo );
5328
5329 /* CurrentRxBuffer points to the 1st buffer of the next */
5330 /* possibly available receive frame. */
5331
5332 frame_start_index = start_index = end_index = info->current_rx_buffer;
5333
5334 /* Search for an unfinished string of buffers. This means */
5335 /* that a receive frame started (at least one buffer with */
5336 /* count set to zero) but there is no terminiting buffer */
5337 /* (status set to non-zero). */
5338
5339 while( !buffer_list[end_index].count )
5340 {
5341 /* Count field has been reset to zero by 16C32. */
5342 /* This buffer is currently in use. */
5343
5344 if ( !start_of_frame_found )
5345 {
0fab6de0 5346 start_of_frame_found = true;
1da177e4 5347 frame_start_index = end_index;
0fab6de0 5348 end_of_frame_found = false;
1da177e4
LT		 5349 }
5350
5351 if ( buffer_list[end_index].status )
5352 {
5353 /* Status field has been set by 16C32. */
5354 /* This is the last buffer of a received frame. */
5355
5356 /* We want to leave the buffers for this frame intact. */
5357 /* Move on to next possible frame. */
5358
0fab6de0
JP		 5359 start_of_frame_found = false;
5360 end_of_frame_found = true;
1da177e4
LT		 5361 }
5362
5363 /* advance to next buffer entry in linked list */
5364 end_index++;
5365 if ( end_index == info->rx_buffer_count )
5366 end_index = 0;
5367
5368 if ( start_index == end_index )
5369 {
5370 /* The entire list has been searched with all Counts == 0 and */
5371 /* all Status == 0. The receive buffers are */
5372 /* completely screwed, reset all receive buffers! */
5373 mgsl_reset_rx_dma_buffers( info );
5374 frame_start_index = 0;
0fab6de0
JP		 5375 start_of_frame_found = false;
5376 reprogram_dma = true;
1da177e4
LT		 5377 break;
5378 }
5379 }
5380
5381 if ( start_of_frame_found && !end_of_frame_found )
5382 {
5383 /* There is an unfinished string of receive DMA buffers */
5384 /* as a result of the receiver overrun. */
5385
5386 /* Reset the buffers for the unfinished frame */
5387 /* and reprogram the receive DMA controller to start */
5388 /* at the 1st buffer of unfinished frame. */
5389
5390 start_index = frame_start_index;
5391
5392 do
5393 {
5394 *((unsigned long *)&(info->rx_buffer_list[start_index++].count)) = DMABUFFERSIZE;
5395
5396 /* Adjust index for wrap around. */
5397 if ( start_index == info->rx_buffer_count )
5398 start_index = 0;
5399
5400 } while( start_index != end_index );
5401
0fab6de0 5402 reprogram_dma = true;
1da177e4
LT		 5403 }
5404
5405 if ( reprogram_dma )
5406 {
5407 usc_UnlatchRxstatusBits(info,RXSTATUS_ALL);
5408 usc_ClearIrqPendingBits(info, RECEIVE_DATA|RECEIVE_STATUS);
5409 usc_UnlatchRxstatusBits(info, RECEIVE_DATA|RECEIVE_STATUS);
5410
5411 usc_EnableReceiver(info,DISABLE_UNCONDITIONAL);
5412
5413 /* This empties the receive FIFO and loads the RCC with RCLR */
5414 usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
5415
5416 /* program 16C32 with physical address of 1st DMA buffer entry */
5417 phys_addr = info->rx_buffer_list[frame_start_index].phys_entry;
5418 usc_OutDmaReg( info, NRARL, (u16)phys_addr );
5419 usc_OutDmaReg( info, NRARU, (u16)(phys_addr >> 16) );
5420
5421 usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
e06922aa 5422 usc_ClearIrqPendingBits( info, RECEIVE_DATA | RECEIVE_STATUS );
1da177e4
LT		 5423 usc_EnableInterrupts( info, RECEIVE_STATUS );
5424
5425 /* 1. Arm End of Buffer (EOB) Receive DMA Interrupt (BIT2 of RDIAR) */
5426 /* 2. Enable Receive DMA Interrupts (BIT1 of DICR) */
5427
e06922aa 5428 usc_OutDmaReg( info, RDIAR, BIT3 | BIT2 );
1da177e4
LT		 5429 usc_OutDmaReg( info, DICR, (u16)(usc_InDmaReg(info,DICR) | BIT1) );
5430 usc_DmaCmd( info, DmaCmd_InitRxChannel );
5431 if ( info->params.flags & HDLC_FLAG_AUTO_DCD )
5432 usc_EnableReceiver(info,ENABLE_AUTO_DCD);
5433 else
5434 usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
5435 }
5436 else
5437 {
5438 /* This empties the receive FIFO and loads the RCC with RCLR */
5439 usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
5440 usc_RTCmd( info, RTCmd_PurgeRxFifo );
5441 }
5442
5443} /* end of usc_process_rxoverrun_sync() */
5444
5445/* usc_stop_receiver()
5446 *
5447 * Disable USC receiver
5448 *
5449 * Arguments: info pointer to device instance data
5450 * Return Value: None
5451 */
5452static void usc_stop_receiver( struct mgsl_struct *info )
5453{
5454 if (debug_level >= DEBUG_LEVEL_ISR)
5455 printk("%s(%d):usc_stop_receiver(%s)\n",
5456 __FILE__,__LINE__, info->device_name );
5457
5458 /* Disable receive DMA channel. */
5459 /* This also disables receive DMA channel interrupts */
5460 usc_DmaCmd( info, DmaCmd_ResetRxChannel );
5461
5462 usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
e06922aa
AJ		 5463 usc_ClearIrqPendingBits( info, RECEIVE_DATA | RECEIVE_STATUS );
5464 usc_DisableInterrupts( info, RECEIVE_DATA | RECEIVE_STATUS );
1da177e4
LT		 5465
5466 usc_EnableReceiver(info,DISABLE_UNCONDITIONAL);
5467
5468 /* This empties the receive FIFO and loads the RCC with RCLR */
5469 usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
5470 usc_RTCmd( info, RTCmd_PurgeRxFifo );
5471
0fab6de0
JP		 5472 info->rx_enabled = false;
5473 info->rx_overflow = false;
5474 info->rx_rcc_underrun = false;
1da177e4
LT		 5475
5476} /* end of stop_receiver() */
5477
5478/* usc_start_receiver()
5479 *
5480 * Enable the USC receiver
5481 *
5482 * Arguments: info pointer to device instance data
5483 * Return Value: None
5484 */
5485static void usc_start_receiver( struct mgsl_struct *info )
5486{
5487 u32 phys_addr;
5488
5489 if (debug_level >= DEBUG_LEVEL_ISR)
5490 printk("%s(%d):usc_start_receiver(%s)\n",
5491 __FILE__,__LINE__, info->device_name );
5492
5493 mgsl_reset_rx_dma_buffers( info );
5494 usc_stop_receiver( info );
5495
5496 usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
5497 usc_RTCmd( info, RTCmd_PurgeRxFifo );
5498
5499 if ( info->params.mode == MGSL_MODE_HDLC ||
5500 info->params.mode == MGSL_MODE_RAW ) {
5501 /* DMA mode Transfers */
5502 /* Program the DMA controller. */
5503 /* Enable the DMA controller end of buffer interrupt. */
5504
5505 /* program 16C32 with physical address of 1st DMA buffer entry */
5506 phys_addr = info->rx_buffer_list[0].phys_entry;
5507 usc_OutDmaReg( info, NRARL, (u16)phys_addr );
5508 usc_OutDmaReg( info, NRARU, (u16)(phys_addr >> 16) );
5509
5510 usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
e06922aa 5511 usc_ClearIrqPendingBits( info, RECEIVE_DATA | RECEIVE_STATUS );
1da177e4
LT		 5512 usc_EnableInterrupts( info, RECEIVE_STATUS );
5513
5514 /* 1. Arm End of Buffer (EOB) Receive DMA Interrupt (BIT2 of RDIAR) */
5515 /* 2. Enable Receive DMA Interrupts (BIT1 of DICR) */
5516
e06922aa 5517 usc_OutDmaReg( info, RDIAR, BIT3 | BIT2 );
1da177e4
LT		 5518 usc_OutDmaReg( info, DICR, (u16)(usc_InDmaReg(info,DICR) | BIT1) );
5519 usc_DmaCmd( info, DmaCmd_InitRxChannel );
5520 if ( info->params.flags & HDLC_FLAG_AUTO_DCD )
5521 usc_EnableReceiver(info,ENABLE_AUTO_DCD);
5522 else
5523 usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
5524 } else {
5525 usc_UnlatchRxstatusBits(info, RXSTATUS_ALL);
e06922aa 5526 usc_ClearIrqPendingBits(info, RECEIVE_DATA | RECEIVE_STATUS);
1da177e4
LT		 5527 usc_EnableInterrupts(info, RECEIVE_DATA);
5528
5529 usc_RTCmd( info, RTCmd_PurgeRxFifo );
5530 usc_RCmd( info, RCmd_EnterHuntmode );
5531
5532 usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
5533 }
5534
5535 usc_OutReg( info, CCSR, 0x1020 );
5536
0fab6de0 5537 info->rx_enabled = true;
1da177e4
LT		 5538
5539} /* end of usc_start_receiver() */
5540
5541/* usc_start_transmitter()
5542 *
5543 * Enable the USC transmitter and send a transmit frame if
5544 * one is loaded in the DMA buffers.
5545 *
5546 * Arguments: info pointer to device instance data
5547 * Return Value: None
5548 */
5549static void usc_start_transmitter( struct mgsl_struct *info )
5550{
5551 u32 phys_addr;
5552 unsigned int FrameSize;
5553
5554 if (debug_level >= DEBUG_LEVEL_ISR)
5555 printk("%s(%d):usc_start_transmitter(%s)\n",
5556 __FILE__,__LINE__, info->device_name );
5557
5558 if ( info->xmit_cnt ) {
5559
5560 /* If auto RTS enabled and RTS is inactive, then assert */
5561 /* RTS and set a flag indicating that the driver should */
5562 /* negate RTS when the transmission completes. */
5563
0fab6de0 5564 info->drop_rts_on_tx_done = false;
1da177e4
LT		 5565
5566 if ( info->params.flags & HDLC_FLAG_AUTO_RTS ) {
5567 usc_get_serial_signals( info );
5568 if ( !(info->serial_signals & SerialSignal_RTS) ) {
5569 info->serial_signals |= SerialSignal_RTS;
5570 usc_set_serial_signals( info );
0fab6de0 5571 info->drop_rts_on_tx_done = true;
1da177e4
LT		 5572 }
5573 }
5574
5575
5576 if ( info->params.mode == MGSL_MODE_ASYNC ) {
5577 if ( !info->tx_active ) {
5578 usc_UnlatchTxstatusBits(info, TXSTATUS_ALL);
5579 usc_ClearIrqPendingBits(info, TRANSMIT_STATUS + TRANSMIT_DATA);
5580 usc_EnableInterrupts(info, TRANSMIT_DATA);
5581 usc_load_txfifo(info);
5582 }
5583 } else {
5584 /* Disable transmit DMA controller while programming. */
5585 usc_DmaCmd( info, DmaCmd_ResetTxChannel );
5586
5587 /* Transmit DMA buffer is loaded, so program USC */
5588 /* to send the frame contained in the buffers. */
5589
5590 FrameSize = info->tx_buffer_list[info->start_tx_dma_buffer].rcc;
5591
5592 /* if operating in Raw sync mode, reset the rcc component
5593 * of the tx dma buffer entry, otherwise, the serial controller
5594 * will send a closing sync char after this count.
5595 */
5596 if ( info->params.mode == MGSL_MODE_RAW )
5597 info->tx_buffer_list[info->start_tx_dma_buffer].rcc = 0;
5598
5599 /* Program the Transmit Character Length Register (TCLR) */
5600 /* and clear FIFO (TCC is loaded with TCLR on FIFO clear) */
5601 usc_OutReg( info, TCLR, (u16)FrameSize );
5602
5603 usc_RTCmd( info, RTCmd_PurgeTxFifo );
5604
5605 /* Program the address of the 1st DMA Buffer Entry in linked list */
5606 phys_addr = info->tx_buffer_list[info->start_tx_dma_buffer].phys_entry;
5607 usc_OutDmaReg( info, NTARL, (u16)phys_addr );
5608 usc_OutDmaReg( info, NTARU, (u16)(phys_addr >> 16) );
5609
5610 usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
5611 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
5612 usc_EnableInterrupts( info, TRANSMIT_STATUS );
5613
5614 if ( info->params.mode == MGSL_MODE_RAW &&
5615 info->num_tx_dma_buffers > 1 ) {
5616 /* When running external sync mode, attempt to 'stream' transmit */
5617 /* by filling tx dma buffers as they become available. To do this */
5618 /* we need to enable Tx DMA EOB Status interrupts : */
5619 /* */
5620 /* 1. Arm End of Buffer (EOB) Transmit DMA Interrupt (BIT2 of TDIAR) */
5621 /* 2. Enable Transmit DMA Interrupts (BIT0 of DICR) */
5622
5623 usc_OutDmaReg( info, TDIAR, BIT2|BIT3 );
5624 usc_OutDmaReg( info, DICR, (u16)(usc_InDmaReg(info,DICR) | BIT0) );
5625 }
5626
5627 /* Initialize Transmit DMA Channel */
5628 usc_DmaCmd( info, DmaCmd_InitTxChannel );
5629
5630 usc_TCmd( info, TCmd_SendFrame );
5631
40565f19
JS		 5632 mod_timer(&info->tx_timer, jiffies +
5633 msecs_to_jiffies(5000));
1da177e4 5634 }
0fab6de0 5635 info->tx_active = true;
1da177e4
LT		 5636 }
5637
5638 if ( !info->tx_enabled ) {
0fab6de0 5639 info->tx_enabled = true;
1da177e4
LT		 5640 if ( info->params.flags & HDLC_FLAG_AUTO_CTS )
5641 usc_EnableTransmitter(info,ENABLE_AUTO_CTS);
5642 else
5643 usc_EnableTransmitter(info,ENABLE_UNCONDITIONAL);
5644 }
5645
5646} /* end of usc_start_transmitter() */
5647
5648/* usc_stop_transmitter()
5649 *
5650 * Stops the transmitter and DMA
5651 *
5652 * Arguments: info pointer to device isntance data
5653 * Return Value: None
5654 */
5655static void usc_stop_transmitter( struct mgsl_struct *info )
5656{
5657 if (debug_level >= DEBUG_LEVEL_ISR)
5658 printk("%s(%d):usc_stop_transmitter(%s)\n",
5659 __FILE__,__LINE__, info->device_name );
5660
5661 del_timer(&info->tx_timer);
5662
5663 usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
5664 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS + TRANSMIT_DATA );
5665 usc_DisableInterrupts( info, TRANSMIT_STATUS + TRANSMIT_DATA );
5666
5667 usc_EnableTransmitter(info,DISABLE_UNCONDITIONAL);
5668 usc_DmaCmd( info, DmaCmd_ResetTxChannel );
5669 usc_RTCmd( info, RTCmd_PurgeTxFifo );
5670
0fab6de0
JP		 5671 info->tx_enabled = false;
5672 info->tx_active = false;
1da177e4
LT		 5673
5674} /* end of usc_stop_transmitter() */
5675
5676/* usc_load_txfifo()
5677 *
5678 * Fill the transmit FIFO until the FIFO is full or
5679 * there is no more data to load.
5680 *
5681 * Arguments: info pointer to device extension (instance data)
5682 * Return Value: None
5683 */
5684static void usc_load_txfifo( struct mgsl_struct *info )
5685{
5686 int Fifocount;
5687 u8 TwoBytes[2];
5688
5689 if ( !info->xmit_cnt && !info->x_char )
5690 return;
5691
5692 /* Select transmit FIFO status readback in TICR */
5693 usc_TCmd( info, TCmd_SelectTicrTxFifostatus );
5694
5695 /* load the Transmit FIFO until FIFOs full or all data sent */
5696
5697 while( (Fifocount = usc_InReg(info, TICR) >> 8) && info->xmit_cnt ) {
5698 /* there is more space in the transmit FIFO and */
5699 /* there is more data in transmit buffer */
5700
5701 if ( (info->xmit_cnt > 1) && (Fifocount > 1) && !info->x_char ) {
5702 /* write a 16-bit word from transmit buffer to 16C32 */
5703
5704 TwoBytes[0] = info->xmit_buf[info->xmit_tail++];
5705 info->xmit_tail = info->xmit_tail & (SERIAL_XMIT_SIZE-1);
5706 TwoBytes[1] = info->xmit_buf[info->xmit_tail++];
5707 info->xmit_tail = info->xmit_tail & (SERIAL_XMIT_SIZE-1);
5708
5709 outw( *((u16 *)TwoBytes), info->io_base + DATAREG);
5710
5711 info->xmit_cnt -= 2;
5712 info->icount.tx += 2;
5713 } else {
5714 /* only 1 byte left to transmit or 1 FIFO slot left */
5715
5716 outw( (inw( info->io_base + CCAR) & 0x0780) | (TDR+LSBONLY),
5717 info->io_base + CCAR );
5718
5719 if (info->x_char) {
5720 /* transmit pending high priority char */
5721 outw( info->x_char,info->io_base + CCAR );
5722 info->x_char = 0;
5723 } else {
5724 outw( info->xmit_buf[info->xmit_tail++],info->io_base + CCAR );
5725 info->xmit_tail = info->xmit_tail & (SERIAL_XMIT_SIZE-1);
5726 info->xmit_cnt--;
5727 }
5728 info->icount.tx++;
5729 }
5730 }
5731
5732} /* end of usc_load_txfifo() */
5733
5734/* usc_reset()
5735 *
5736 * Reset the adapter to a known state and prepare it for further use.
5737 *
5738 * Arguments: info pointer to device instance data
5739 * Return Value: None
5740 */
5741static void usc_reset( struct mgsl_struct *info )
5742{
5743 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
5744 int i;
5745 u32 readval;
5746
5747 /* Set BIT30 of Misc Control Register */
5748 /* (Local Control Register 0x50) to force reset of USC. */
5749
5750 volatile u32 *MiscCtrl = (u32 *)(info->lcr_base + 0x50);
5751 u32 *LCR0BRDR = (u32 *)(info->lcr_base + 0x28);
5752
5753 info->misc_ctrl_value |= BIT30;
5754 *MiscCtrl = info->misc_ctrl_value;
5755
5756 /*
5757 * Force at least 170ns delay before clearing
5758 * reset bit. Each read from LCR takes at least
5759 * 30ns so 10 times for 300ns to be safe.
5760 */
5761 for(i=0;i<10;i++)
5762 readval = *MiscCtrl;
5763
5764 info->misc_ctrl_value &= ~BIT30;
5765 *MiscCtrl = info->misc_ctrl_value;
5766
5767 *LCR0BRDR = BUS_DESCRIPTOR(
5768 1, // Write Strobe Hold (0-3)
5769 2, // Write Strobe Delay (0-3)
5770 2, // Read Strobe Delay (0-3)
5771 0, // NWDD (Write data-data) (0-3)
5772 4, // NWAD (Write Addr-data) (0-31)
5773 0, // NXDA (Read/Write Data-Addr) (0-3)
5774 0, // NRDD (Read Data-Data) (0-3)
5775 5 // NRAD (Read Addr-Data) (0-31)
5776 );
5777 } else {
5778 /* do HW reset */
5779 outb( 0,info->io_base + 8 );
5780 }
5781
5782 info->mbre_bit = 0;
5783 info->loopback_bits = 0;
5784 info->usc_idle_mode = 0;
5785
5786 /*
5787 * Program the Bus Configuration Register (BCR)
5788 *
5789 * <15> 0 Don't use separate address
5790 * <14..6> 0 reserved
5791 * <5..4> 00 IAckmode = Default, don't care
5792 * <3> 1 Bus Request Totem Pole output
5793 * <2> 1 Use 16 Bit data bus
5794 * <1> 0 IRQ Totem Pole output
5795 * <0> 0 Don't Shift Right Addr
5796 *
5797 * 0000 0000 0000 1100 = 0x000c
5798 *
5799 * By writing to io_base + SDPIN the Wait/Ack pin is
5800 * programmed to work as a Wait pin.
5801 */
5802
5803 outw( 0x000c,info->io_base + SDPIN );
5804
5805
5806 outw( 0,info->io_base );
5807 outw( 0,info->io_base + CCAR );
5808
5809 /* select little endian byte ordering */
5810 usc_RTCmd( info, RTCmd_SelectLittleEndian );
5811
5812
5813 /* Port Control Register (PCR)
5814 *
5815 * <15..14> 11 Port 7 is Output (~DMAEN, Bit 14 : 0 = Enabled)
5816 * <13..12> 11 Port 6 is Output (~INTEN, Bit 12 : 0 = Enabled)
5817 * <11..10> 00 Port 5 is Input (No Connect, Don't Care)
5818 * <9..8> 00 Port 4 is Input (No Connect, Don't Care)
5819 * <7..6> 11 Port 3 is Output (~RTS, Bit 6 : 0 = Enabled )
5820 * <5..4> 11 Port 2 is Output (~DTR, Bit 4 : 0 = Enabled )
5821 * <3..2> 01 Port 1 is Input (Dedicated RxC)
5822 * <1..0> 01 Port 0 is Input (Dedicated TxC)
5823 *
5824 * 1111 0000 1111 0101 = 0xf0f5
5825 */
5826
5827 usc_OutReg( info, PCR, 0xf0f5 );
5828
5829
5830 /*
5831 * Input/Output Control Register
5832 *
5833 * <15..14> 00 CTS is active low input
5834 * <13..12> 00 DCD is active low input
5835 * <11..10> 00 TxREQ pin is input (DSR)
5836 * <9..8> 00 RxREQ pin is input (RI)
5837 * <7..6> 00 TxD is output (Transmit Data)
5838 * <5..3> 000 TxC Pin in Input (14.7456MHz Clock)
5839 * <2..0> 100 RxC is Output (drive with BRG0)
5840 *
5841 * 0000 0000 0000 0100 = 0x0004
5842 */
5843
5844 usc_OutReg( info, IOCR, 0x0004 );
5845
5846} /* end of usc_reset() */
5847
5848/* usc_set_async_mode()
5849 *
5850 * Program adapter for asynchronous communications.
5851 *
5852 * Arguments: info pointer to device instance data
5853 * Return Value: None
5854 */
5855static void usc_set_async_mode( struct mgsl_struct *info )
5856{
5857 u16 RegValue;
5858
5859 /* disable interrupts while programming USC */
5860 usc_DisableMasterIrqBit( info );
5861
5862 outw( 0, info->io_base ); /* clear Master Bus Enable (DCAR) */
5863 usc_DmaCmd( info, DmaCmd_ResetAllChannels ); /* disable both DMA channels */
5864
5865 usc_loopback_frame( info );
5866
5867 /* Channel mode Register (CMR)
5868 *
5869 * <15..14> 00 Tx Sub modes, 00 = 1 Stop Bit
5870 * <13..12> 00 00 = 16X Clock
5871 * <11..8> 0000 Transmitter mode = Asynchronous
5872 * <7..6> 00 reserved?
5873 * <5..4> 00 Rx Sub modes, 00 = 16X Clock
5874 * <3..0> 0000 Receiver mode = Asynchronous
5875 *
5876 * 0000 0000 0000 0000 = 0x0
5877 */
5878
5879 RegValue = 0;
5880 if ( info->params.stop_bits != 1 )
5881 RegValue |= BIT14;
5882 usc_OutReg( info, CMR, RegValue );
5883
5884
5885 /* Receiver mode Register (RMR)
5886 *
5887 * <15..13> 000 encoding = None
5888 * <12..08> 00000 reserved (Sync Only)
5889 * <7..6> 00 Even parity
5890 * <5> 0 parity disabled
5891 * <4..2> 000 Receive Char Length = 8 bits
5892 * <1..0> 00 Disable Receiver
5893 *
5894 * 0000 0000 0000 0000 = 0x0
5895 */
5896
5897 RegValue = 0;
5898
5899 if ( info->params.data_bits != 8 )
e06922aa 5900 RegValue |= BIT4 | BIT3 | BIT2;
1da177e4
LT		 5901
5902 if ( info->params.parity != ASYNC_PARITY_NONE ) {
5903 RegValue |= BIT5;
5904 if ( info->params.parity != ASYNC_PARITY_ODD )
5905 RegValue |= BIT6;
5906 }
5907
5908 usc_OutReg( info, RMR, RegValue );
5909
5910
5911 /* Set IRQ trigger level */
5912
5913 usc_RCmd( info, RCmd_SelectRicrIntLevel );
5914
5915
5916 /* Receive Interrupt Control Register (RICR)
5917 *
5918 * <15..8> ? RxFIFO IRQ Request Level
5919 *
5920 * Note: For async mode the receive FIFO level must be set
7f927fcc 5921 * to 0 to avoid the situation where the FIFO contains fewer bytes
1da177e4
LT		 5922 * than the trigger level and no more data is expected.
5923 *
5924 * <7> 0 Exited Hunt IA (Interrupt Arm)
5925 * <6> 0 Idle Received IA
5926 * <5> 0 Break/Abort IA
5927 * <4> 0 Rx Bound IA
5928 * <3> 0 Queued status reflects oldest byte in FIFO
5929 * <2> 0 Abort/PE IA
5930 * <1> 0 Rx Overrun IA
5931 * <0> 0 Select TC0 value for readback
5932 *
5933 * 0000 0000 0100 0000 = 0x0000 + (FIFOLEVEL in MSB)
5934 */
5935
5936 usc_OutReg( info, RICR, 0x0000 );
5937
5938 usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
5939 usc_ClearIrqPendingBits( info, RECEIVE_STATUS );
5940
5941
5942 /* Transmit mode Register (TMR)
5943 *
5944 * <15..13> 000 encoding = None
5945 * <12..08> 00000 reserved (Sync Only)
5946 * <7..6> 00 Transmit parity Even
5947 * <5> 0 Transmit parity Disabled
5948 * <4..2> 000 Tx Char Length = 8 bits
5949 * <1..0> 00 Disable Transmitter
5950 *
5951 * 0000 0000 0000 0000 = 0x0
5952 */
5953
5954 RegValue = 0;
5955
5956 if ( info->params.data_bits != 8 )
e06922aa 5957 RegValue |= BIT4 | BIT3 | BIT2;
1da177e4
LT		 5958
5959 if ( info->params.parity != ASYNC_PARITY_NONE ) {
5960 RegValue |= BIT5;
5961 if ( info->params.parity != ASYNC_PARITY_ODD )
5962 RegValue |= BIT6;
5963 }
5964
5965 usc_OutReg( info, TMR, RegValue );
5966
5967 usc_set_txidle( info );
5968
5969
5970 /* Set IRQ trigger level */
5971
5972 usc_TCmd( info, TCmd_SelectTicrIntLevel );
5973
5974
5975 /* Transmit Interrupt Control Register (TICR)
5976 *
5977 * <15..8> ? Transmit FIFO IRQ Level
5978 * <7> 0 Present IA (Interrupt Arm)
5979 * <6> 1 Idle Sent IA
5980 * <5> 0 Abort Sent IA
5981 * <4> 0 EOF/EOM Sent IA
5982 * <3> 0 CRC Sent IA
5983 * <2> 0 1 = Wait for SW Trigger to Start Frame
5984 * <1> 0 Tx Underrun IA
5985 * <0> 0 TC0 constant on read back
5986 *
5987 * 0000 0000 0100 0000 = 0x0040
5988 */
5989
5990 usc_OutReg( info, TICR, 0x1f40 );
5991
5992 usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
5993 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
5994
5995 usc_enable_async_clock( info, info->params.data_rate );
5996
5997
5998 /* Channel Control/status Register (CCSR)
5999 *
6000 * <15> X RCC FIFO Overflow status (RO)
6001 * <14> X RCC FIFO Not Empty status (RO)
6002 * <13> 0 1 = Clear RCC FIFO (WO)
6003 * <12> X DPLL in Sync status (RO)
6004 * <11> X DPLL 2 Missed Clocks status (RO)
6005 * <10> X DPLL 1 Missed Clock status (RO)
6006 * <9..8> 00 DPLL Resync on rising and falling edges (RW)
6007 * <7> X SDLC Loop On status (RO)
6008 * <6> X SDLC Loop Send status (RO)
6009 * <5> 1 Bypass counters for TxClk and RxClk (RW)
6010 * <4..2> 000 Last Char of SDLC frame has 8 bits (RW)
6011 * <1..0> 00 reserved
6012 *
6013 * 0000 0000 0010 0000 = 0x0020
6014 */
6015
6016 usc_OutReg( info, CCSR, 0x0020 );
6017
6018 usc_DisableInterrupts( info, TRANSMIT_STATUS + TRANSMIT_DATA +
6019 RECEIVE_DATA + RECEIVE_STATUS );
6020
6021 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS + TRANSMIT_DATA +
6022 RECEIVE_DATA + RECEIVE_STATUS );
6023
6024 usc_EnableMasterIrqBit( info );
6025
6026 if (info->bus_type == MGSL_BUS_TYPE_ISA) {
6027 /* Enable INTEN (Port 6, Bit12) */
6028 /* This connects the IRQ request signal to the ISA bus */
6029 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) & ~BIT12));
6030 }
6031
7c1fff58
PF		 6032 if (info->params.loopback) {
6033 info->loopback_bits = 0x300;
6034 outw(0x0300, info->io_base + CCAR);
6035 }
6036
1da177e4
LT		 6037} /* end of usc_set_async_mode() */
6038
6039/* usc_loopback_frame()
6040 *
6041 * Loop back a small (2 byte) dummy SDLC frame.
6042 * Interrupts and DMA are NOT used. The purpose of this is to
6043 * clear any 'stale' status info left over from running in async mode.
6044 *
6045 * The 16C32 shows the strange behaviour of marking the 1st
6046 * received SDLC frame with a CRC error even when there is no
6047 * CRC error. To get around this a small dummy from of 2 bytes
6048 * is looped back when switching from async to sync mode.
6049 *
6050 * Arguments: info pointer to device instance data
6051 * Return Value: None
6052 */
6053static void usc_loopback_frame( struct mgsl_struct *info )
6054{
6055 int i;
6056 unsigned long oldmode = info->params.mode;
6057
6058 info->params.mode = MGSL_MODE_HDLC;
6059
6060 usc_DisableMasterIrqBit( info );
6061
6062 usc_set_sdlc_mode( info );
6063 usc_enable_loopback( info, 1 );
6064
6065 /* Write 16-bit Time Constant for BRG0 */
6066 usc_OutReg( info, TC0R, 0 );
6067
6068 /* Channel Control Register (CCR)
6069 *
6070 * <15..14> 00 Don't use 32-bit Tx Control Blocks (TCBs)
6071 * <13> 0 Trigger Tx on SW Command Disabled
6072 * <12> 0 Flag Preamble Disabled
6073 * <11..10> 00 Preamble Length = 8-Bits
6074 * <9..8> 01 Preamble Pattern = flags
6075 * <7..6> 10 Don't use 32-bit Rx status Blocks (RSBs)
6076 * <5> 0 Trigger Rx on SW Command Disabled
6077 * <4..0> 0 reserved
6078 *
6079 * 0000 0001 0000 0000 = 0x0100
6080 */
6081
6082 usc_OutReg( info, CCR, 0x0100 );
6083
6084 /* SETUP RECEIVER */
6085 usc_RTCmd( info, RTCmd_PurgeRxFifo );
6086 usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
6087
6088 /* SETUP TRANSMITTER */
6089 /* Program the Transmit Character Length Register (TCLR) */
6090 /* and clear FIFO (TCC is loaded with TCLR on FIFO clear) */
6091 usc_OutReg( info, TCLR, 2 );
6092 usc_RTCmd( info, RTCmd_PurgeTxFifo );
6093
6094 /* unlatch Tx status bits, and start transmit channel. */
6095 usc_UnlatchTxstatusBits(info,TXSTATUS_ALL);
6096 outw(0,info->io_base + DATAREG);
6097
6098 /* ENABLE TRANSMITTER */
6099 usc_TCmd( info, TCmd_SendFrame );
6100 usc_EnableTransmitter(info,ENABLE_UNCONDITIONAL);
6101
6102 /* WAIT FOR RECEIVE COMPLETE */
6103 for (i=0 ; i<1000 ; i++)
e06922aa 6104 if (usc_InReg( info, RCSR ) & (BIT8 | BIT4 | BIT3 | BIT1))
1da177e4
LT		 6105 break;
6106
6107 /* clear Internal Data loopback mode */
6108 usc_enable_loopback(info, 0);
6109
6110 usc_EnableMasterIrqBit(info);
6111
6112 info->params.mode = oldmode;
6113
6114} /* end of usc_loopback_frame() */
6115
6116/* usc_set_sync_mode() Programs the USC for SDLC communications.
6117 *
6118 * Arguments: info pointer to adapter info structure
6119 * Return Value: None
6120 */
6121static void usc_set_sync_mode( struct mgsl_struct *info )
6122{
6123 usc_loopback_frame( info );
6124 usc_set_sdlc_mode( info );
6125
6126 if (info->bus_type == MGSL_BUS_TYPE_ISA) {
6127 /* Enable INTEN (Port 6, Bit12) */
6128 /* This connects the IRQ request signal to the ISA bus */
6129 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) & ~BIT12));
6130 }
6131
6132 usc_enable_aux_clock(info, info->params.clock_speed);
6133
6134 if (info->params.loopback)
6135 usc_enable_loopback(info,1);
6136
6137} /* end of mgsl_set_sync_mode() */
6138
6139/* usc_set_txidle() Set the HDLC idle mode for the transmitter.
6140 *
6141 * Arguments: info pointer to device instance data
6142 * Return Value: None
6143 */
6144static void usc_set_txidle( struct mgsl_struct *info )
6145{
6146 u16 usc_idle_mode = IDLEMODE_FLAGS;
6147
6148 /* Map API idle mode to USC register bits */
6149
6150 switch( info->idle_mode ){
6151 case HDLC_TXIDLE_FLAGS: usc_idle_mode = IDLEMODE_FLAGS; break;
6152 case HDLC_TXIDLE_ALT_ZEROS_ONES: usc_idle_mode = IDLEMODE_ALT_ONE_ZERO; break;
6153 case HDLC_TXIDLE_ZEROS: usc_idle_mode = IDLEMODE_ZERO; break;
6154 case HDLC_TXIDLE_ONES: usc_idle_mode = IDLEMODE_ONE; break;
6155 case HDLC_TXIDLE_ALT_MARK_SPACE: usc_idle_mode = IDLEMODE_ALT_MARK_SPACE; break;
6156 case HDLC_TXIDLE_SPACE: usc_idle_mode = IDLEMODE_SPACE; break;
6157 case HDLC_TXIDLE_MARK: usc_idle_mode = IDLEMODE_MARK; break;
6158 }
6159
6160 info->usc_idle_mode = usc_idle_mode;
6161 //usc_OutReg(info, TCSR, usc_idle_mode);
6162 info->tcsr_value &= ~IDLEMODE_MASK; /* clear idle mode bits */
6163 info->tcsr_value += usc_idle_mode;
6164 usc_OutReg(info, TCSR, info->tcsr_value);
6165
6166 /*
6167 * if SyncLink WAN adapter is running in external sync mode, the
6168 * transmitter has been set to Monosync in order to try to mimic
6169 * a true raw outbound bit stream. Monosync still sends an open/close
6170 * sync char at the start/end of a frame. Try to match those sync
6171 * patterns to the idle mode set here
6172 */
6173 if ( info->params.mode == MGSL_MODE_RAW ) {
6174 unsigned char syncpat = 0;
6175 switch( info->idle_mode ) {
6176 case HDLC_TXIDLE_FLAGS:
6177 syncpat = 0x7e;
6178 break;
6179 case HDLC_TXIDLE_ALT_ZEROS_ONES:
6180 syncpat = 0x55;
6181 break;
6182 case HDLC_TXIDLE_ZEROS:
6183 case HDLC_TXIDLE_SPACE:
6184 syncpat = 0x00;
6185 break;
6186 case HDLC_TXIDLE_ONES:
6187 case HDLC_TXIDLE_MARK:
6188 syncpat = 0xff;
6189 break;
6190 case HDLC_TXIDLE_ALT_MARK_SPACE:
6191 syncpat = 0xaa;
6192 break;
6193 }
6194
6195 usc_SetTransmitSyncChars(info,syncpat,syncpat);
6196 }
6197
6198} /* end of usc_set_txidle() */
6199
6200/* usc_get_serial_signals()
6201 *
6202 * Query the adapter for the state of the V24 status (input) signals.
6203 *
6204 * Arguments: info pointer to device instance data
6205 * Return Value: None
6206 */
6207static void usc_get_serial_signals( struct mgsl_struct *info )
6208{
6209 u16 status;
6210
9fe8074b
JP		 6211 /* clear all serial signals except RTS and DTR */
6212 info->serial_signals &= SerialSignal_RTS | SerialSignal_DTR;
1da177e4
LT		 6213
6214 /* Read the Misc Interrupt status Register (MISR) to get */
6215 /* the V24 status signals. */
6216
6217 status = usc_InReg( info, MISR );
6218
6219 /* set serial signal bits to reflect MISR */
6220
6221 if ( status & MISCSTATUS_CTS )
6222 info->serial_signals |= SerialSignal_CTS;
6223
6224 if ( status & MISCSTATUS_DCD )
6225 info->serial_signals |= SerialSignal_DCD;
6226
6227 if ( status & MISCSTATUS_RI )
6228 info->serial_signals |= SerialSignal_RI;
6229
6230 if ( status & MISCSTATUS_DSR )
6231 info->serial_signals |= SerialSignal_DSR;
6232
6233} /* end of usc_get_serial_signals() */
6234
6235/* usc_set_serial_signals()
6236 *
9fe8074b 6237 * Set the state of RTS and DTR based on contents of
1da177e4
LT		 6238 * serial_signals member of device extension.
6239 *
6240 * Arguments: info pointer to device instance data
6241 * Return Value: None
6242 */
6243static void usc_set_serial_signals( struct mgsl_struct *info )
6244{
6245 u16 Control;
6246 unsigned char V24Out = info->serial_signals;
6247
6248 /* get the current value of the Port Control Register (PCR) */
6249
6250 Control = usc_InReg( info, PCR );
6251
6252 if ( V24Out & SerialSignal_RTS )
6253 Control &= ~(BIT6);
6254 else
6255 Control |= BIT6;
6256
6257 if ( V24Out & SerialSignal_DTR )
6258 Control &= ~(BIT4);
6259 else
6260 Control |= BIT4;
6261
6262 usc_OutReg( info, PCR, Control );
6263
6264} /* end of usc_set_serial_signals() */
6265
6266/* usc_enable_async_clock()
6267 *
6268 * Enable the async clock at the specified frequency.
6269 *
6270 * Arguments: info pointer to device instance data
6271 * data_rate data rate of clock in bps
6272 * 0 disables the AUX clock.
6273 * Return Value: None
6274 */
6275static void usc_enable_async_clock( struct mgsl_struct *info, u32 data_rate )
6276{
6277 if ( data_rate ) {
6278 /*
6279 * Clock mode Control Register (CMCR)
6280 *
6281 * <15..14> 00 counter 1 Disabled
6282 * <13..12> 00 counter 0 Disabled
6283 * <11..10> 11 BRG1 Input is TxC Pin
6284 * <9..8> 11 BRG0 Input is TxC Pin
6285 * <7..6> 01 DPLL Input is BRG1 Output
6286 * <5..3> 100 TxCLK comes from BRG0
6287 * <2..0> 100 RxCLK comes from BRG0
6288 *
6289 * 0000 1111 0110 0100 = 0x0f64
6290 */
6291
6292 usc_OutReg( info, CMCR, 0x0f64 );
6293
6294
6295 /*
6296 * Write 16-bit Time Constant for BRG0
6297 * Time Constant = (ClkSpeed / data_rate) - 1
6298 * ClkSpeed = 921600 (ISA), 691200 (PCI)
6299 */
6300
6301 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
6302 usc_OutReg( info, TC0R, (u16)((691200/data_rate) - 1) );
6303 else
6304 usc_OutReg( info, TC0R, (u16)((921600/data_rate) - 1) );
6305
6306
6307 /*
6308 * Hardware Configuration Register (HCR)
6309 * Clear Bit 1, BRG0 mode = Continuous
6310 * Set Bit 0 to enable BRG0.
6311 */
6312
6313 usc_OutReg( info, HCR,
6314 (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) );
6315
6316
6317 /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
6318
6319 usc_OutReg( info, IOCR,
6320 (u16)((usc_InReg(info, IOCR) & 0xfff8) | 0x0004) );
6321 } else {
6322 /* data rate == 0 so turn off BRG0 */
6323 usc_OutReg( info, HCR, (u16)(usc_InReg( info, HCR ) & ~BIT0) );
6324 }
6325
6326} /* end of usc_enable_async_clock() */
6327
6328/*
6329 * Buffer Structures:
6330 *
6331 * Normal memory access uses virtual addresses that can make discontiguous
6332 * physical memory pages appear to be contiguous in the virtual address
6333 * space (the processors memory mapping handles the conversions).
6334 *
6335 * DMA transfers require physically contiguous memory. This is because
6336 * the DMA system controller and DMA bus masters deal with memory using
6337 * only physical addresses.
6338 *
6339 * This causes a problem under Windows NT when large DMA buffers are
6340 * needed. Fragmentation of the nonpaged pool prevents allocations of
6341 * physically contiguous buffers larger than the PAGE_SIZE.
6342 *
6343 * However the 16C32 supports Bus Master Scatter/Gather DMA which
6344 * allows DMA transfers to physically discontiguous buffers. Information
6345 * about each data transfer buffer is contained in a memory structure
6346 * called a 'buffer entry'. A list of buffer entries is maintained
6347 * to track and control the use of the data transfer buffers.
6348 *
6349 * To support this strategy we will allocate sufficient PAGE_SIZE
6350 * contiguous memory buffers to allow for the total required buffer
6351 * space.
6352 *
6353 * The 16C32 accesses the list of buffer entries using Bus Master
6354 * DMA. Control information is read from the buffer entries by the
6355 * 16C32 to control data transfers. status information is written to
6356 * the buffer entries by the 16C32 to indicate the status of completed
6357 * transfers.
6358 *
6359 * The CPU writes control information to the buffer entries to control
6360 * the 16C32 and reads status information from the buffer entries to
6361 * determine information about received and transmitted frames.
6362 *
6363 * Because the CPU and 16C32 (adapter) both need simultaneous access
6364 * to the buffer entries, the buffer entry memory is allocated with
6365 * HalAllocateCommonBuffer(). This restricts the size of the buffer
6366 * entry list to PAGE_SIZE.
6367 *
6368 * The actual data buffers on the other hand will only be accessed
6369 * by the CPU or the adapter but not by both simultaneously. This allows
6370 * Scatter/Gather packet based DMA procedures for using physically
6371 * discontiguous pages.
6372 */
6373
6374/*
6375 * mgsl_reset_tx_dma_buffers()
6376 *
6377 * Set the count for all transmit buffers to 0 to indicate the
6378 * buffer is available for use and set the current buffer to the
6379 * first buffer. This effectively makes all buffers free and
6380 * discards any data in buffers.
6381 *
6382 * Arguments: info pointer to device instance data
6383 * Return Value: None
6384 */
6385static void mgsl_reset_tx_dma_buffers( struct mgsl_struct *info )
6386{
6387 unsigned int i;
6388
6389 for ( i = 0; i < info->tx_buffer_count; i++ ) {
6390 *((unsigned long *)&(info->tx_buffer_list[i].count)) = 0;
6391 }
6392
6393 info->current_tx_buffer = 0;
6394 info->start_tx_dma_buffer = 0;
6395 info->tx_dma_buffers_used = 0;
6396
6397 info->get_tx_holding_index = 0;
6398 info->put_tx_holding_index = 0;
6399 info->tx_holding_count = 0;
6400
6401} /* end of mgsl_reset_tx_dma_buffers() */
6402
6403/*
6404 * num_free_tx_dma_buffers()
6405 *
6406 * returns the number of free tx dma buffers available
6407 *
6408 * Arguments: info pointer to device instance data
6409 * Return Value: number of free tx dma buffers
6410 */
6411static int num_free_tx_dma_buffers(struct mgsl_struct *info)
6412{
6413 return info->tx_buffer_count - info->tx_dma_buffers_used;
6414}
6415
6416/*
6417 * mgsl_reset_rx_dma_buffers()
6418 *
6419 * Set the count for all receive buffers to DMABUFFERSIZE
6420 * and set the current buffer to the first buffer. This effectively
6421 * makes all buffers free and discards any data in buffers.
6422 *
6423 * Arguments: info pointer to device instance data
6424 * Return Value: None
6425 */
6426static void mgsl_reset_rx_dma_buffers( struct mgsl_struct *info )
6427{
6428 unsigned int i;
6429
6430 for ( i = 0; i < info->rx_buffer_count; i++ ) {
6431 *((unsigned long *)&(info->rx_buffer_list[i].count)) = DMABUFFERSIZE;
6432// info->rx_buffer_list[i].count = DMABUFFERSIZE;
6433// info->rx_buffer_list[i].status = 0;
6434 }
6435
6436 info->current_rx_buffer = 0;
6437
6438} /* end of mgsl_reset_rx_dma_buffers() */
6439
6440/*
6441 * mgsl_free_rx_frame_buffers()
6442 *
6443 * Free the receive buffers used by a received SDLC
6444 * frame such that the buffers can be reused.
6445 *
6446 * Arguments:
6447 *
6448 * info pointer to device instance data
6449 * StartIndex index of 1st receive buffer of frame
6450 * EndIndex index of last receive buffer of frame
6451 *
6452 * Return Value: None
6453 */
6454static void mgsl_free_rx_frame_buffers( struct mgsl_struct *info, unsigned int StartIndex, unsigned int EndIndex )
6455{
0fab6de0 6456 bool Done = false;
1da177e4
LT		 6457 DMABUFFERENTRY *pBufEntry;
6458 unsigned int Index;
6459
6460 /* Starting with 1st buffer entry of the frame clear the status */
6461 /* field and set the count field to DMA Buffer Size. */
6462
6463 Index = StartIndex;
6464
6465 while( !Done ) {
6466 pBufEntry = &(info->rx_buffer_list[Index]);
6467
6468 if ( Index == EndIndex ) {
6469 /* This is the last buffer of the frame! */
0fab6de0 6470 Done = true;
1da177e4
LT		 6471 }
6472
6473 /* reset current buffer for reuse */
6474// pBufEntry->status = 0;
6475// pBufEntry->count = DMABUFFERSIZE;
6476 *((unsigned long *)&(pBufEntry->count)) = DMABUFFERSIZE;
6477
6478 /* advance to next buffer entry in linked list */
6479 Index++;
6480 if ( Index == info->rx_buffer_count )
6481 Index = 0;
6482 }
6483
6484 /* set current buffer to next buffer after last buffer of frame */
6485 info->current_rx_buffer = Index;
6486
6487} /* end of free_rx_frame_buffers() */
6488
6489/* mgsl_get_rx_frame()
6490 *
6491 * This function attempts to return a received SDLC frame from the
6492 * receive DMA buffers. Only frames received without errors are returned.
6493 *
6494 * Arguments: info pointer to device extension
0fab6de0 6495 * Return Value: true if frame returned, otherwise false
1da177e4 6496 */
0fab6de0 6497static bool mgsl_get_rx_frame(struct mgsl_struct *info)
1da177e4
LT		 6498{
6499 unsigned int StartIndex, EndIndex; /* index of 1st and last buffers of Rx frame */
6500 unsigned short status;
6501 DMABUFFERENTRY *pBufEntry;
6502 unsigned int framesize = 0;
0fab6de0 6503 bool ReturnCode = false;
1da177e4 6504 unsigned long flags;
8fb06c77 6505 struct tty_struct *tty = info->port.tty;
0fab6de0 6506 bool return_frame = false;
1da177e4
LT		 6507
6508 /*
6509 * current_rx_buffer points to the 1st buffer of the next available
6510 * receive frame. To find the last buffer of the frame look for
6511 * a non-zero status field in the buffer entries. (The status
6512 * field is set by the 16C32 after completing a receive frame.
6513 */
6514
6515 StartIndex = EndIndex = info->current_rx_buffer;
6516
6517 while( !info->rx_buffer_list[EndIndex].status ) {
6518 /*
6519 * If the count field of the buffer entry is non-zero then
6520 * this buffer has not been used. (The 16C32 clears the count
6521 * field when it starts using the buffer.) If an unused buffer
6522 * is encountered then there are no frames available.
6523 */
6524
6525 if ( info->rx_buffer_list[EndIndex].count )
6526 goto Cleanup;
6527
6528 /* advance to next buffer entry in linked list */
6529 EndIndex++;
6530 if ( EndIndex == info->rx_buffer_count )
6531 EndIndex = 0;
6532
6533 /* if entire list searched then no frame available */
6534 if ( EndIndex == StartIndex ) {
6535 /* If this occurs then something bad happened,
6536 * all buffers have been 'used' but none mark
6537 * the end of a frame. Reset buffers and receiver.
6538 */
6539
6540 if ( info->rx_enabled ){
6541 spin_lock_irqsave(&info->irq_spinlock,flags);
6542 usc_start_receiver(info);
6543 spin_unlock_irqrestore(&info->irq_spinlock,flags);
6544 }
6545 goto Cleanup;
6546 }
6547 }
6548
6549
6550 /* check status of receive frame */
6551
6552 status = info->rx_buffer_list[EndIndex].status;
6553
e06922aa
AJ		 6554 if ( status & (RXSTATUS_SHORT_FRAME | RXSTATUS_OVERRUN |
6555 RXSTATUS_CRC_ERROR | RXSTATUS_ABORT) ) {
1da177e4
LT		 6556 if ( status & RXSTATUS_SHORT_FRAME )
6557 info->icount.rxshort++;
6558 else if ( status & RXSTATUS_ABORT )
6559 info->icount.rxabort++;
6560 else if ( status & RXSTATUS_OVERRUN )
6561 info->icount.rxover++;
6562 else {
6563 info->icount.rxcrc++;
6564 if ( info->params.crc_type & HDLC_CRC_RETURN_EX )
0fab6de0 6565 return_frame = true;
1da177e4
LT		 6566 }
6567 framesize = 0;
af69c7f9 6568#if SYNCLINK_GENERIC_HDLC
1da177e4 6569 {
198191c4
KH		 6570 info->netdev->stats.rx_errors++;
6571 info->netdev->stats.rx_frame_errors++;
1da177e4
LT		 6572 }
6573#endif
6574 } else
0fab6de0 6575 return_frame = true;
1da177e4
LT		 6576
6577 if ( return_frame ) {
6578 /* receive frame has no errors, get frame size.
6579 * The frame size is the starting value of the RCC (which was
6580 * set to 0xffff) minus the ending value of the RCC (decremented
6581 * once for each receive character) minus 2 for the 16-bit CRC.
6582 */
6583
6584 framesize = RCLRVALUE - info->rx_buffer_list[EndIndex].rcc;
6585
6586 /* adjust frame size for CRC if any */
6587 if ( info->params.crc_type == HDLC_CRC_16_CCITT )
6588 framesize -= 2;
6589 else if ( info->params.crc_type == HDLC_CRC_32_CCITT )
6590 framesize -= 4;
6591 }
6592
6593 if ( debug_level >= DEBUG_LEVEL_BH )
6594 printk("%s(%d):mgsl_get_rx_frame(%s) status=%04X size=%d\n",
6595 __FILE__,__LINE__,info->device_name,status,framesize);
6596
6597 if ( debug_level >= DEBUG_LEVEL_DATA )
6598 mgsl_trace_block(info,info->rx_buffer_list[StartIndex].virt_addr,
6599 min_t(int, framesize, DMABUFFERSIZE),0);
6600
6601 if (framesize) {
6602 if ( ( (info->params.crc_type & HDLC_CRC_RETURN_EX) &&
6603 ((framesize+1) > info->max_frame_size) ) ||
6604 (framesize > info->max_frame_size) )
6605 info->icount.rxlong++;
6606 else {
6607 /* copy dma buffer(s) to contiguous intermediate buffer */
6608 int copy_count = framesize;
6609 int index = StartIndex;
6610 unsigned char *ptmp = info->intermediate_rxbuffer;
6611
6612 if ( !(status & RXSTATUS_CRC_ERROR))
4bd01622 6613 info->icount.rxok++;
1da177e4
LT		 6614
6615 while(copy_count) {
6616 int partial_count;
6617 if ( copy_count > DMABUFFERSIZE )
6618 partial_count = DMABUFFERSIZE;
6619 else
6620 partial_count = copy_count;
6621
6622 pBufEntry = &(info->rx_buffer_list[index]);
6623 memcpy( ptmp, pBufEntry->virt_addr, partial_count );
6624 ptmp += partial_count;
6625 copy_count -= partial_count;
6626
6627 if ( ++index == info->rx_buffer_count )
6628 index = 0;
6629 }
6630
6631 if ( info->params.crc_type & HDLC_CRC_RETURN_EX ) {
6632 ++framesize;
6633 *ptmp = (status & RXSTATUS_CRC_ERROR ?
6634 RX_CRC_ERROR :
6635 RX_OK);
6636
6637 if ( debug_level >= DEBUG_LEVEL_DATA )
6638 printk("%s(%d):mgsl_get_rx_frame(%s) rx frame status=%d\n",
6639 __FILE__,__LINE__,info->device_name,
6640 *ptmp);
6641 }
6642
af69c7f9 6643#if SYNCLINK_GENERIC_HDLC
1da177e4
LT		 6644 if (info->netcount)
6645 hdlcdev_rx(info,info->intermediate_rxbuffer,framesize);
6646 else
6647#endif
6648 ldisc_receive_buf(tty, info->intermediate_rxbuffer, info->flag_buf, framesize);
6649 }
6650 }
6651 /* Free the buffers used by this frame. */
6652 mgsl_free_rx_frame_buffers( info, StartIndex, EndIndex );
6653
0fab6de0 6654 ReturnCode = true;
1da177e4
LT		 6655
6656Cleanup:
6657
6658 if ( info->rx_enabled && info->rx_overflow ) {
6659 /* The receiver needs to restarted because of
6660 * a receive overflow (buffer or FIFO). If the
6661 * receive buffers are now empty, then restart receiver.
6662 */
6663
6664 if ( !info->rx_buffer_list[EndIndex].status &&
6665 info->rx_buffer_list[EndIndex].count ) {
6666 spin_lock_irqsave(&info->irq_spinlock,flags);
6667 usc_start_receiver(info);
6668 spin_unlock_irqrestore(&info->irq_spinlock,flags);
6669 }
6670 }
6671
6672 return ReturnCode;
6673
6674} /* end of mgsl_get_rx_frame() */
6675
6676/* mgsl_get_raw_rx_frame()
6677 *
6678 * This function attempts to return a received frame from the
6679 * receive DMA buffers when running in external loop mode. In this mode,
6680 * we will return at most one DMABUFFERSIZE frame to the application.
6681 * The USC receiver is triggering off of DCD going active to start a new
6682 * frame, and DCD going inactive to terminate the frame (similar to
6683 * processing a closing flag character).
6684 *
6685 * In this routine, we will return DMABUFFERSIZE "chunks" at a time.
6686 * If DCD goes inactive, the last Rx DMA Buffer will have a non-zero
6687 * status field and the RCC field will indicate the length of the
6688 * entire received frame. We take this RCC field and get the modulus
6689 * of RCC and DMABUFFERSIZE to determine if number of bytes in the
6690 * last Rx DMA buffer and return that last portion of the frame.
6691 *
6692 * Arguments: info pointer to device extension
0fab6de0 6693 * Return Value: true if frame returned, otherwise false
1da177e4 6694 */
0fab6de0 6695static bool mgsl_get_raw_rx_frame(struct mgsl_struct *info)
1da177e4
LT		 6696{
6697 unsigned int CurrentIndex, NextIndex;
6698 unsigned short status;
6699 DMABUFFERENTRY *pBufEntry;
6700 unsigned int framesize = 0;
0fab6de0 6701 bool ReturnCode = false;
1da177e4 6702 unsigned long flags;
8fb06c77 6703 struct tty_struct *tty = info->port.tty;
1da177e4
LT		 6704
6705 /*
6706 * current_rx_buffer points to the 1st buffer of the next available
6707 * receive frame. The status field is set by the 16C32 after
6708 * completing a receive frame. If the status field of this buffer
6709 * is zero, either the USC is still filling this buffer or this
6710 * is one of a series of buffers making up a received frame.
6711 *
6712 * If the count field of this buffer is zero, the USC is either
6713 * using this buffer or has used this buffer. Look at the count
6714 * field of the next buffer. If that next buffer's count is
6715 * non-zero, the USC is still actively using the current buffer.
6716 * Otherwise, if the next buffer's count field is zero, the
6717 * current buffer is complete and the USC is using the next
6718 * buffer.
6719 */
6720 CurrentIndex = NextIndex = info->current_rx_buffer;
6721 ++NextIndex;
6722 if ( NextIndex == info->rx_buffer_count )
6723 NextIndex = 0;
6724
6725 if ( info->rx_buffer_list[CurrentIndex].status != 0 ||
6726 (info->rx_buffer_list[CurrentIndex].count == 0 &&
6727 info->rx_buffer_list[NextIndex].count == 0)) {
6728 /*
6729 * Either the status field of this dma buffer is non-zero
6730 * (indicating the last buffer of a receive frame) or the next
6731 * buffer is marked as in use -- implying this buffer is complete
6732 * and an intermediate buffer for this received frame.
6733 */
6734
6735 status = info->rx_buffer_list[CurrentIndex].status;
6736
e06922aa
AJ		 6737 if ( status & (RXSTATUS_SHORT_FRAME | RXSTATUS_OVERRUN |
6738 RXSTATUS_CRC_ERROR | RXSTATUS_ABORT) ) {
1da177e4
LT		 6739 if ( status & RXSTATUS_SHORT_FRAME )
6740 info->icount.rxshort++;
6741 else if ( status & RXSTATUS_ABORT )
6742 info->icount.rxabort++;
6743 else if ( status & RXSTATUS_OVERRUN )
6744 info->icount.rxover++;
6745 else
6746 info->icount.rxcrc++;
6747 framesize = 0;
6748 } else {
6749 /*
6750 * A receive frame is available, get frame size and status.
6751 *
6752 * The frame size is the starting value of the RCC (which was
6753 * set to 0xffff) minus the ending value of the RCC (decremented
6754 * once for each receive character) minus 2 or 4 for the 16-bit
6755 * or 32-bit CRC.
6756 *
6757 * If the status field is zero, this is an intermediate buffer.
6758 * It's size is 4K.
6759 *
6760 * If the DMA Buffer Entry's Status field is non-zero, the
6761 * receive operation completed normally (ie: DCD dropped). The
6762 * RCC field is valid and holds the received frame size.
6763 * It is possible that the RCC field will be zero on a DMA buffer
6764 * entry with a non-zero status. This can occur if the total
6765 * frame size (number of bytes between the time DCD goes active
6766 * to the time DCD goes inactive) exceeds 65535 bytes. In this
6767 * case the 16C32 has underrun on the RCC count and appears to
6768 * stop updating this counter to let us know the actual received
6769 * frame size. If this happens (non-zero status and zero RCC),
6770 * simply return the entire RxDMA Buffer
6771 */
6772 if ( status ) {
6773 /*
6774 * In the event that the final RxDMA Buffer is
6775 * terminated with a non-zero status and the RCC
6776 * field is zero, we interpret this as the RCC
6777 * having underflowed (received frame > 65535 bytes).
6778 *
6779 * Signal the event to the user by passing back
6780 * a status of RxStatus_CrcError returning the full
6781 * buffer and let the app figure out what data is
6782 * actually valid
6783 */
6784 if ( info->rx_buffer_list[CurrentIndex].rcc )
6785 framesize = RCLRVALUE - info->rx_buffer_list[CurrentIndex].rcc;
6786 else
6787 framesize = DMABUFFERSIZE;
6788 }
6789 else
6790 framesize = DMABUFFERSIZE;
6791 }
6792
6793 if ( framesize > DMABUFFERSIZE ) {
6794 /*
6795 * if running in raw sync mode, ISR handler for
6796 * End Of Buffer events terminates all buffers at 4K.
6797 * If this frame size is said to be >4K, get the
6798 * actual number of bytes of the frame in this buffer.
6799 */
6800 framesize = framesize % DMABUFFERSIZE;
6801 }
6802
6803
6804 if ( debug_level >= DEBUG_LEVEL_BH )
6805 printk("%s(%d):mgsl_get_raw_rx_frame(%s) status=%04X size=%d\n",
6806 __FILE__,__LINE__,info->device_name,status,framesize);
6807
6808 if ( debug_level >= DEBUG_LEVEL_DATA )
6809 mgsl_trace_block(info,info->rx_buffer_list[CurrentIndex].virt_addr,
6810 min_t(int, framesize, DMABUFFERSIZE),0);
6811
6812 if (framesize) {
6813 /* copy dma buffer(s) to contiguous intermediate buffer */
6814 /* NOTE: we never copy more than DMABUFFERSIZE bytes */
6815
6816 pBufEntry = &(info->rx_buffer_list[CurrentIndex]);
6817 memcpy( info->intermediate_rxbuffer, pBufEntry->virt_addr, framesize);
6818 info->icount.rxok++;
6819
6820 ldisc_receive_buf(tty, info->intermediate_rxbuffer, info->flag_buf, framesize);
6821 }
6822
6823 /* Free the buffers used by this frame. */
6824 mgsl_free_rx_frame_buffers( info, CurrentIndex, CurrentIndex );
6825
0fab6de0 6826 ReturnCode = true;
1da177e4
LT		 6827 }
6828
6829
6830 if ( info->rx_enabled && info->rx_overflow ) {
6831 /* The receiver needs to restarted because of
6832 * a receive overflow (buffer or FIFO). If the
6833 * receive buffers are now empty, then restart receiver.
6834 */
6835
6836 if ( !info->rx_buffer_list[CurrentIndex].status &&
6837 info->rx_buffer_list[CurrentIndex].count ) {
6838 spin_lock_irqsave(&info->irq_spinlock,flags);
6839 usc_start_receiver(info);
6840 spin_unlock_irqrestore(&info->irq_spinlock,flags);
6841 }
6842 }
6843
6844 return ReturnCode;
6845
6846} /* end of mgsl_get_raw_rx_frame() */
6847
6848/* mgsl_load_tx_dma_buffer()
6849 *
6850 * Load the transmit DMA buffer with the specified data.
6851 *
6852 * Arguments:
6853 *
6854 * info pointer to device extension
6855 * Buffer pointer to buffer containing frame to load
6856 * BufferSize size in bytes of frame in Buffer
6857 *
6858 * Return Value: None
6859 */
6860static void mgsl_load_tx_dma_buffer(struct mgsl_struct *info,
6861 const char *Buffer, unsigned int BufferSize)
6862{
6863 unsigned short Copycount;
6864 unsigned int i = 0;
6865 DMABUFFERENTRY *pBufEntry;
6866
6867 if ( debug_level >= DEBUG_LEVEL_DATA )
6868 mgsl_trace_block(info,Buffer, min_t(int, BufferSize, DMABUFFERSIZE), 1);
6869
6870 if (info->params.flags & HDLC_FLAG_HDLC_LOOPMODE) {
6871 /* set CMR:13 to start transmit when
6872 * next GoAhead (abort) is received
6873 */
e06922aa 6874 info->cmr_value |= BIT13;
1da177e4
LT		 6875 }
6876
6877 /* begin loading the frame in the next available tx dma
6878 * buffer, remember it's starting location for setting
6879 * up tx dma operation
6880 */
6881 i = info->current_tx_buffer;
6882 info->start_tx_dma_buffer = i;
6883
6884 /* Setup the status and RCC (Frame Size) fields of the 1st */
6885 /* buffer entry in the transmit DMA buffer list. */
6886
6887 info->tx_buffer_list[i].status = info->cmr_value & 0xf000;
6888 info->tx_buffer_list[i].rcc = BufferSize;
6889 info->tx_buffer_list[i].count = BufferSize;
6890
6891 /* Copy frame data from 1st source buffer to the DMA buffers. */
6892 /* The frame data may span multiple DMA buffers. */
6893
6894 while( BufferSize ){
6895 /* Get a pointer to next DMA buffer entry. */
6896 pBufEntry = &info->tx_buffer_list[i++];
6897
6898 if ( i == info->tx_buffer_count )
6899 i=0;
6900
6901 /* Calculate the number of bytes that can be copied from */
6902 /* the source buffer to this DMA buffer. */
6903 if ( BufferSize > DMABUFFERSIZE )
6904 Copycount = DMABUFFERSIZE;
6905 else
6906 Copycount = BufferSize;
6907
6908 /* Actually copy data from source buffer to DMA buffer. */
6909 /* Also set the data count for this individual DMA buffer. */
6910 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
6911 mgsl_load_pci_memory(pBufEntry->virt_addr, Buffer,Copycount);
6912 else
6913 memcpy(pBufEntry->virt_addr, Buffer, Copycount);
6914
6915 pBufEntry->count = Copycount;
6916
6917 /* Advance source pointer and reduce remaining data count. */
6918 Buffer += Copycount;
6919 BufferSize -= Copycount;
6920
6921 ++info->tx_dma_buffers_used;
6922 }
6923
6924 /* remember next available tx dma buffer */
6925 info->current_tx_buffer = i;
6926
6927} /* end of mgsl_load_tx_dma_buffer() */
6928
6929/*
6930 * mgsl_register_test()
6931 *
6932 * Performs a register test of the 16C32.
6933 *
6934 * Arguments: info pointer to device instance data
0fab6de0 6935 * Return Value: true if test passed, otherwise false
1da177e4 6936 */
0fab6de0 6937static bool mgsl_register_test( struct mgsl_struct *info )
1da177e4
LT		 6938{
6939 static unsigned short BitPatterns[] =
6940 { 0x0000, 0xffff, 0xaaaa, 0x5555, 0x1234, 0x6969, 0x9696, 0x0f0f };
fe971071 6941 static unsigned int Patterncount = ARRAY_SIZE(BitPatterns);
1da177e4 6942 unsigned int i;
0fab6de0 6943 bool rc = true;
1da177e4
LT		 6944 unsigned long flags;
6945
6946 spin_lock_irqsave(&info->irq_spinlock,flags);
6947 usc_reset(info);
6948
6949 /* Verify the reset state of some registers. */
6950
6951 if ( (usc_InReg( info, SICR ) != 0) ||
6952 (usc_InReg( info, IVR ) != 0) ||
6953 (usc_InDmaReg( info, DIVR ) != 0) ){
0fab6de0 6954 rc = false;
1da177e4
LT		 6955 }
6956
0fab6de0 6957 if ( rc ){
1da177e4
LT		 6958 /* Write bit patterns to various registers but do it out of */
6959 /* sync, then read back and verify values. */
6960
6961 for ( i = 0 ; i < Patterncount ; i++ ) {
6962 usc_OutReg( info, TC0R, BitPatterns[i] );
6963 usc_OutReg( info, TC1R, BitPatterns[(i+1)%Patterncount] );
6964 usc_OutReg( info, TCLR, BitPatterns[(i+2)%Patterncount] );
6965 usc_OutReg( info, RCLR, BitPatterns[(i+3)%Patterncount] );
6966 usc_OutReg( info, RSR, BitPatterns[(i+4)%Patterncount] );
6967 usc_OutDmaReg( info, TBCR, BitPatterns[(i+5)%Patterncount] );
6968
6969 if ( (usc_InReg( info, TC0R ) != BitPatterns[i]) ||
6970 (usc_InReg( info, TC1R ) != BitPatterns[(i+1)%Patterncount]) ||
6971 (usc_InReg( info, TCLR ) != BitPatterns[(i+2)%Patterncount]) ||
6972 (usc_InReg( info, RCLR ) != BitPatterns[(i+3)%Patterncount]) ||
6973 (usc_InReg( info, RSR ) != BitPatterns[(i+4)%Patterncount]) ||
6974 (usc_InDmaReg( info, TBCR ) != BitPatterns[(i+5)%Patterncount]) ){
0fab6de0 6975 rc = false;
1da177e4
LT		 6976 break;
6977 }
6978 }
6979 }
6980
6981 usc_reset(info);
6982 spin_unlock_irqrestore(&info->irq_spinlock,flags);
6983
6984 return rc;
6985
6986} /* end of mgsl_register_test() */
6987
6988/* mgsl_irq_test() Perform interrupt test of the 16C32.
6989 *
6990 * Arguments: info pointer to device instance data
0fab6de0 6991 * Return Value: true if test passed, otherwise false
1da177e4 6992 */
0fab6de0 6993static bool mgsl_irq_test( struct mgsl_struct *info )
1da177e4
LT		 6994{
6995 unsigned long EndTime;
6996 unsigned long flags;
6997
6998 spin_lock_irqsave(&info->irq_spinlock,flags);
6999 usc_reset(info);
7000
7001 /*
7002 * Setup 16C32 to interrupt on TxC pin (14MHz clock) transition.
0fab6de0 7003 * The ISR sets irq_occurred to true.
1da177e4
LT		 7004 */
7005
0fab6de0 7006 info->irq_occurred = false;
1da177e4
LT		 7007
7008 /* Enable INTEN gate for ISA adapter (Port 6, Bit12) */
7009 /* Enable INTEN (Port 6, Bit12) */
7010 /* This connects the IRQ request signal to the ISA bus */
7011 /* on the ISA adapter. This has no effect for the PCI adapter */
7012 usc_OutReg( info, PCR, (unsigned short)((usc_InReg(info, PCR) | BIT13) & ~BIT12) );
7013
7014 usc_EnableMasterIrqBit(info);
7015 usc_EnableInterrupts(info, IO_PIN);
7016 usc_ClearIrqPendingBits(info, IO_PIN);
7017
7018 usc_UnlatchIostatusBits(info, MISCSTATUS_TXC_LATCHED);
7019 usc_EnableStatusIrqs(info, SICR_TXC_ACTIVE + SICR_TXC_INACTIVE);
7020
7021 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7022
7023 EndTime=100;
7024 while( EndTime-- && !info->irq_occurred ) {
7025 msleep_interruptible(10);
7026 }
7027
7028 spin_lock_irqsave(&info->irq_spinlock,flags);
7029 usc_reset(info);
7030 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7031
0fab6de0 7032 return info->irq_occurred;
1da177e4
LT		 7033
7034} /* end of mgsl_irq_test() */
7035
7036/* mgsl_dma_test()
7037 *
7038 * Perform a DMA test of the 16C32. A small frame is
7039 * transmitted via DMA from a transmit buffer to a receive buffer
7040 * using single buffer DMA mode.
7041 *
7042 * Arguments: info pointer to device instance data
0fab6de0 7043 * Return Value: true if test passed, otherwise false
1da177e4 7044 */
0fab6de0 7045static bool mgsl_dma_test( struct mgsl_struct *info )
1da177e4
LT		 7046{
7047 unsigned short FifoLevel;
7048 unsigned long phys_addr;
7049 unsigned int FrameSize;
7050 unsigned int i;
7051 char *TmpPtr;
0fab6de0 7052 bool rc = true;
1da177e4
LT		 7053 unsigned short status=0;
7054 unsigned long EndTime;
7055 unsigned long flags;
7056 MGSL_PARAMS tmp_params;
7057
7058 /* save current port options */
7059 memcpy(&tmp_params,&info->params,sizeof(MGSL_PARAMS));
7060 /* load default port options */
7061 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
7062
7063#define TESTFRAMESIZE 40
7064
7065 spin_lock_irqsave(&info->irq_spinlock,flags);
7066
7067 /* setup 16C32 for SDLC DMA transfer mode */
7068
7069 usc_reset(info);
7070 usc_set_sdlc_mode(info);
7071 usc_enable_loopback(info,1);
7072
7073 /* Reprogram the RDMR so that the 16C32 does NOT clear the count
7074 * field of the buffer entry after fetching buffer address. This
7075 * way we can detect a DMA failure for a DMA read (which should be
7076 * non-destructive to system memory) before we try and write to
7077 * memory (where a failure could corrupt system memory).
7078 */
7079
7080 /* Receive DMA mode Register (RDMR)
7081 *
7082 * <15..14> 11 DMA mode = Linked List Buffer mode
7083 * <13> 1 RSBinA/L = store Rx status Block in List entry
7084 * <12> 0 1 = Clear count of List Entry after fetching
7085 * <11..10> 00 Address mode = Increment
7086 * <9> 1 Terminate Buffer on RxBound
7087 * <8> 0 Bus Width = 16bits
7088 * <7..0> ? status Bits (write as 0s)
7089 *
7090 * 1110 0010 0000 0000 = 0xe200
7091 */
7092
7093 usc_OutDmaReg( info, RDMR, 0xe200 );
7094
7095 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7096
7097
7098 /* SETUP TRANSMIT AND RECEIVE DMA BUFFERS */
7099
7100 FrameSize = TESTFRAMESIZE;
7101
7102 /* setup 1st transmit buffer entry: */
7103 /* with frame size and transmit control word */
7104
7105 info->tx_buffer_list[0].count = FrameSize;
7106 info->tx_buffer_list[0].rcc = FrameSize;
7107 info->tx_buffer_list[0].status = 0x4000;
7108
7109 /* build a transmit frame in 1st transmit DMA buffer */
7110
7111 TmpPtr = info->tx_buffer_list[0].virt_addr;
7112 for (i = 0; i < FrameSize; i++ )
7113 *TmpPtr++ = i;
7114
7115 /* setup 1st receive buffer entry: */
7116 /* clear status, set max receive buffer size */
7117
7118 info->rx_buffer_list[0].status = 0;
7119 info->rx_buffer_list[0].count = FrameSize + 4;
7120
7121 /* zero out the 1st receive buffer */
7122
7123 memset( info->rx_buffer_list[0].virt_addr, 0, FrameSize + 4 );
7124
7125 /* Set count field of next buffer entries to prevent */
7126 /* 16C32 from using buffers after the 1st one. */
7127
7128 info->tx_buffer_list[1].count = 0;
7129 info->rx_buffer_list[1].count = 0;
7130
7131
7132 /***************************/
7133 /* Program 16C32 receiver. */
7134 /***************************/
7135
7136 spin_lock_irqsave(&info->irq_spinlock,flags);
7137
7138 /* setup DMA transfers */
7139 usc_RTCmd( info, RTCmd_PurgeRxFifo );
7140
7141 /* program 16C32 receiver with physical address of 1st DMA buffer entry */
7142 phys_addr = info->rx_buffer_list[0].phys_entry;
7143 usc_OutDmaReg( info, NRARL, (unsigned short)phys_addr );
7144 usc_OutDmaReg( info, NRARU, (unsigned short)(phys_addr >> 16) );
7145
7146 /* Clear the Rx DMA status bits (read RDMR) and start channel */
7147 usc_InDmaReg( info, RDMR );
7148 usc_DmaCmd( info, DmaCmd_InitRxChannel );
7149
7150 /* Enable Receiver (RMR <1..0> = 10) */
7151 usc_OutReg( info, RMR, (unsigned short)((usc_InReg(info, RMR) & 0xfffc) | 0x0002) );
7152
7153 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7154
7155
7156 /*************************************************************/
7157 /* WAIT FOR RECEIVER TO DMA ALL PARAMETERS FROM BUFFER ENTRY */
7158 /*************************************************************/
7159
7160 /* Wait 100ms for interrupt. */
7161 EndTime = jiffies + msecs_to_jiffies(100);
7162
7163 for(;;) {
7164 if (time_after(jiffies, EndTime)) {
0fab6de0 7165 rc = false;
1da177e4
LT		 7166 break;
7167 }
7168
7169 spin_lock_irqsave(&info->irq_spinlock,flags);
7170 status = usc_InDmaReg( info, RDMR );
7171 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7172
7173 if ( !(status & BIT4) && (status & BIT5) ) {
7174 /* INITG (BIT 4) is inactive (no entry read in progress) AND */
7175 /* BUSY (BIT 5) is active (channel still active). */
7176 /* This means the buffer entry read has completed. */
7177 break;
7178 }
7179 }
7180
7181
7182 /******************************/
7183 /* Program 16C32 transmitter. */
7184 /******************************/
7185
7186 spin_lock_irqsave(&info->irq_spinlock,flags);
7187
7188 /* Program the Transmit Character Length Register (TCLR) */
7189 /* and clear FIFO (TCC is loaded with TCLR on FIFO clear) */
7190
7191 usc_OutReg( info, TCLR, (unsigned short)info->tx_buffer_list[0].count );
7192 usc_RTCmd( info, RTCmd_PurgeTxFifo );
7193
7194 /* Program the address of the 1st DMA Buffer Entry in linked list */
7195
7196 phys_addr = info->tx_buffer_list[0].phys_entry;
7197 usc_OutDmaReg( info, NTARL, (unsigned short)phys_addr );
7198 usc_OutDmaReg( info, NTARU, (unsigned short)(phys_addr >> 16) );
7199
7200 /* unlatch Tx status bits, and start transmit channel. */
7201
7202 usc_OutReg( info, TCSR, (unsigned short)(( usc_InReg(info, TCSR) & 0x0f00) | 0xfa) );
7203 usc_DmaCmd( info, DmaCmd_InitTxChannel );
7204
7205 /* wait for DMA controller to fill transmit FIFO */
7206
7207 usc_TCmd( info, TCmd_SelectTicrTxFifostatus );
7208
7209 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7210
7211
7212 /**********************************/
7213 /* WAIT FOR TRANSMIT FIFO TO FILL */
7214 /**********************************/
7215
7216 /* Wait 100ms */
7217 EndTime = jiffies + msecs_to_jiffies(100);
7218
7219 for(;;) {
7220 if (time_after(jiffies, EndTime)) {
0fab6de0 7221 rc = false;
1da177e4
LT		 7222 break;
7223 }
7224
7225 spin_lock_irqsave(&info->irq_spinlock,flags);
7226 FifoLevel = usc_InReg(info, TICR) >> 8;
7227 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7228
7229 if ( FifoLevel < 16 )
7230 break;
7231 else
7232 if ( FrameSize < 32 ) {
7233 /* This frame is smaller than the entire transmit FIFO */
7234 /* so wait for the entire frame to be loaded. */
7235 if ( FifoLevel <= (32 - FrameSize) )
7236 break;
7237 }
7238 }
7239
7240
0fab6de0 7241 if ( rc )
1da177e4
LT		 7242 {
7243 /* Enable 16C32 transmitter. */
7244
7245 spin_lock_irqsave(&info->irq_spinlock,flags);
7246
7247 /* Transmit mode Register (TMR), <1..0> = 10, Enable Transmitter */
7248 usc_TCmd( info, TCmd_SendFrame );
7249 usc_OutReg( info, TMR, (unsigned short)((usc_InReg(info, TMR) & 0xfffc) | 0x0002) );
7250
7251 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7252
e06922aa 7253
1da177e4
LT		 7254 /******************************/
7255 /* WAIT FOR TRANSMIT COMPLETE */
7256 /******************************/
7257
7258 /* Wait 100ms */
7259 EndTime = jiffies + msecs_to_jiffies(100);
7260
7261 /* While timer not expired wait for transmit complete */
7262
7263 spin_lock_irqsave(&info->irq_spinlock,flags);
7264 status = usc_InReg( info, TCSR );
7265 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7266
e06922aa 7267 while ( !(status & (BIT6 | BIT5 | BIT4 | BIT2 | BIT1)) ) {
1da177e4 7268 if (time_after(jiffies, EndTime)) {
0fab6de0 7269 rc = false;
1da177e4
LT		 7270 break;
7271 }
7272
7273 spin_lock_irqsave(&info->irq_spinlock,flags);
7274 status = usc_InReg( info, TCSR );
7275 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7276 }
7277 }
7278
7279
0fab6de0 7280 if ( rc ){
1da177e4 7281 /* CHECK FOR TRANSMIT ERRORS */
e06922aa 7282 if ( status & (BIT5 | BIT1) )
0fab6de0 7283 rc = false;
1da177e4
LT		 7284 }
7285
0fab6de0 7286 if ( rc ) {
1da177e4
LT		 7287 /* WAIT FOR RECEIVE COMPLETE */
7288
7289 /* Wait 100ms */
7290 EndTime = jiffies + msecs_to_jiffies(100);
7291
7292 /* Wait for 16C32 to write receive status to buffer entry. */
7293 status=info->rx_buffer_list[0].status;
7294 while ( status == 0 ) {
7295 if (time_after(jiffies, EndTime)) {
0fab6de0 7296 rc = false;
1da177e4
LT		 7297 break;
7298 }
7299 status=info->rx_buffer_list[0].status;
7300 }
7301 }
7302
7303
0fab6de0 7304 if ( rc ) {
1da177e4
LT		 7305 /* CHECK FOR RECEIVE ERRORS */
7306 status = info->rx_buffer_list[0].status;
7307
e06922aa 7308 if ( status & (BIT8 | BIT3 | BIT1) ) {
1da177e4 7309 /* receive error has occurred */
0fab6de0 7310 rc = false;
1da177e4
LT		 7311 } else {
7312 if ( memcmp( info->tx_buffer_list[0].virt_addr ,
7313 info->rx_buffer_list[0].virt_addr, FrameSize ) ){
0fab6de0 7314 rc = false;
1da177e4
LT		 7315 }
7316 }
7317 }
7318
7319 spin_lock_irqsave(&info->irq_spinlock,flags);
7320 usc_reset( info );
7321 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7322
7323 /* restore current port options */
7324 memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
7325
7326 return rc;
7327
7328} /* end of mgsl_dma_test() */
7329
7330/* mgsl_adapter_test()
7331 *
7332 * Perform the register, IRQ, and DMA tests for the 16C32.
7333 *
7334 * Arguments: info pointer to device instance data
7335 * Return Value: 0 if success, otherwise -ENODEV
7336 */
7337static int mgsl_adapter_test( struct mgsl_struct *info )
7338{
7339 if ( debug_level >= DEBUG_LEVEL_INFO )
7340 printk( "%s(%d):Testing device %s\n",
7341 __FILE__,__LINE__,info->device_name );
7342
7343 if ( !mgsl_register_test( info ) ) {
7344 info->init_error = DiagStatus_AddressFailure;
7345 printk( "%s(%d):Register test failure for device %s Addr=%04X\n",
7346 __FILE__,__LINE__,info->device_name, (unsigned short)(info->io_base) );
7347 return -ENODEV;
7348 }
7349
7350 if ( !mgsl_irq_test( info ) ) {
7351 info->init_error = DiagStatus_IrqFailure;
7352 printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
7353 __FILE__,__LINE__,info->device_name, (unsigned short)(info->irq_level) );
7354 return -ENODEV;
7355 }
7356
7357 if ( !mgsl_dma_test( info ) ) {
7358 info->init_error = DiagStatus_DmaFailure;
7359 printk( "%s(%d):DMA test failure for device %s DMA=%d\n",
7360 __FILE__,__LINE__,info->device_name, (unsigned short)(info->dma_level) );
7361 return -ENODEV;
7362 }
7363
7364 if ( debug_level >= DEBUG_LEVEL_INFO )
7365 printk( "%s(%d):device %s passed diagnostics\n",
7366 __FILE__,__LINE__,info->device_name );
7367
7368 return 0;
7369
7370} /* end of mgsl_adapter_test() */
7371
7372/* mgsl_memory_test()
7373 *
7374 * Test the shared memory on a PCI adapter.
7375 *
7376 * Arguments: info pointer to device instance data
0fab6de0 7377 * Return Value: true if test passed, otherwise false
1da177e4 7378 */
0fab6de0 7379static bool mgsl_memory_test( struct mgsl_struct *info )
1da177e4 7380{
fe971071
TK		 7381 static unsigned long BitPatterns[] =
7382 { 0x0, 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999, 0xffffffff, 0x12345678 };
7383 unsigned long Patterncount = ARRAY_SIZE(BitPatterns);
1da177e4
LT		 7384 unsigned long i;
7385 unsigned long TestLimit = SHARED_MEM_ADDRESS_SIZE/sizeof(unsigned long);
7386 unsigned long * TestAddr;
7387
7388 if ( info->bus_type != MGSL_BUS_TYPE_PCI )
0fab6de0 7389 return true;
1da177e4
LT		 7390
7391 TestAddr = (unsigned long *)info->memory_base;
7392
7393 /* Test data lines with test pattern at one location. */
7394
7395 for ( i = 0 ; i < Patterncount ; i++ ) {
7396 *TestAddr = BitPatterns[i];
7397 if ( *TestAddr != BitPatterns[i] )
0fab6de0 7398 return false;
1da177e4
LT		 7399 }
7400
7401 /* Test address lines with incrementing pattern over */
7402 /* entire address range. */
7403
7404 for ( i = 0 ; i < TestLimit ; i++ ) {
7405 *TestAddr = i * 4;
7406 TestAddr++;
7407 }
7408
7409 TestAddr = (unsigned long *)info->memory_base;
7410
7411 for ( i = 0 ; i < TestLimit ; i++ ) {
7412 if ( *TestAddr != i * 4 )
0fab6de0 7413 return false;
1da177e4
LT		 7414 TestAddr++;
7415 }
7416
7417 memset( info->memory_base, 0, SHARED_MEM_ADDRESS_SIZE );
7418
0fab6de0 7419 return true;
1da177e4
LT		 7420
7421} /* End Of mgsl_memory_test() */
7422
7423
7424/* mgsl_load_pci_memory()
7425 *
7426 * Load a large block of data into the PCI shared memory.
7427 * Use this instead of memcpy() or memmove() to move data
7428 * into the PCI shared memory.
7429 *
7430 * Notes:
7431 *
7432 * This function prevents the PCI9050 interface chip from hogging
7433 * the adapter local bus, which can starve the 16C32 by preventing
7434 * 16C32 bus master cycles.
7435 *
7436 * The PCI9050 documentation says that the 9050 will always release
7437 * control of the local bus after completing the current read
7438 * or write operation.
7439 *
7440 * It appears that as long as the PCI9050 write FIFO is full, the
7441 * PCI9050 treats all of the writes as a single burst transaction
7442 * and will not release the bus. This causes DMA latency problems
7443 * at high speeds when copying large data blocks to the shared
7444 * memory.
7445 *
7446 * This function in effect, breaks the a large shared memory write
7447 * into multiple transations by interleaving a shared memory read
7448 * which will flush the write FIFO and 'complete' the write
7449 * transation. This allows any pending DMA request to gain control
7450 * of the local bus in a timely fasion.
7451 *
7452 * Arguments:
7453 *
7454 * TargetPtr pointer to target address in PCI shared memory
7455 * SourcePtr pointer to source buffer for data
7456 * count count in bytes of data to copy
7457 *
7458 * Return Value: None
7459 */
7460static void mgsl_load_pci_memory( char* TargetPtr, const char* SourcePtr,
7461 unsigned short count )
7462{
7463 /* 16 32-bit writes @ 60ns each = 960ns max latency on local bus */
7464#define PCI_LOAD_INTERVAL 64
7465
7466 unsigned short Intervalcount = count / PCI_LOAD_INTERVAL;
7467 unsigned short Index;
7468 unsigned long Dummy;
7469
7470 for ( Index = 0 ; Index < Intervalcount ; Index++ )
7471 {
7472 memcpy(TargetPtr, SourcePtr, PCI_LOAD_INTERVAL);
7473 Dummy = *((volatile unsigned long *)TargetPtr);
7474 TargetPtr += PCI_LOAD_INTERVAL;
7475 SourcePtr += PCI_LOAD_INTERVAL;
7476 }
7477
7478 memcpy( TargetPtr, SourcePtr, count % PCI_LOAD_INTERVAL );
7479
7480} /* End Of mgsl_load_pci_memory() */
7481
7482static void mgsl_trace_block(struct mgsl_struct *info,const char* data, int count, int xmit)
7483{
7484 int i;
7485 int linecount;
7486 if (xmit)
7487 printk("%s tx data:\n",info->device_name);
7488 else
7489 printk("%s rx data:\n",info->device_name);
7490
7491 while(count) {
7492 if (count > 16)
7493 linecount = 16;
7494 else
7495 linecount = count;
7496
7497 for(i=0;i<linecount;i++)
7498 printk("%02X ",(unsigned char)data[i]);
7499 for(;i<17;i++)
7500 printk(" ");
7501 for(i=0;i<linecount;i++) {
7502 if (data[i]>=040 && data[i]<=0176)
7503 printk("%c",data[i]);
7504 else
7505 printk(".");
7506 }
7507 printk("\n");
7508
7509 data += linecount;
7510 count -= linecount;
7511 }
7512} /* end of mgsl_trace_block() */
7513
7514/* mgsl_tx_timeout()
7515 *
7516 * called when HDLC frame times out
7517 * update stats and do tx completion processing
7518 *
7519 * Arguments: context pointer to device instance data
7520 * Return Value: None
7521 */
7522static void mgsl_tx_timeout(unsigned long context)
7523{
7524 struct mgsl_struct *info = (struct mgsl_struct*)context;
7525 unsigned long flags;
7526
7527 if ( debug_level >= DEBUG_LEVEL_INFO )
7528 printk( "%s(%d):mgsl_tx_timeout(%s)\n",
7529 __FILE__,__LINE__,info->device_name);
7530 if(info->tx_active &&
7531 (info->params.mode == MGSL_MODE_HDLC ||
7532 info->params.mode == MGSL_MODE_RAW) ) {
7533 info->icount.txtimeout++;
7534 }
7535 spin_lock_irqsave(&info->irq_spinlock,flags);
0fab6de0 7536 info->tx_active = false;
1da177e4
LT		 7537 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
7538
7539 if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
7540 usc_loopmode_cancel_transmit( info );
7541
7542 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7543
af69c7f9 7544#if SYNCLINK_GENERIC_HDLC
1da177e4
LT		 7545 if (info->netcount)
7546 hdlcdev_tx_done(info);
7547 else
7548#endif
7549 mgsl_bh_transmit(info);
7550
7551} /* end of mgsl_tx_timeout() */
7552
7553/* signal that there are no more frames to send, so that
7554 * line is 'released' by echoing RxD to TxD when current
7555 * transmission is complete (or immediately if no tx in progress).
7556 */
7557static int mgsl_loopmode_send_done( struct mgsl_struct * info )
7558{
7559 unsigned long flags;
7560
7561 spin_lock_irqsave(&info->irq_spinlock,flags);
7562 if (info->params.flags & HDLC_FLAG_HDLC_LOOPMODE) {
7563 if (info->tx_active)
0fab6de0 7564 info->loopmode_send_done_requested = true;
1da177e4
LT		 7565 else
7566 usc_loopmode_send_done(info);
7567 }
7568 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7569
7570 return 0;
7571}
7572
7573/* release the line by echoing RxD to TxD
7574 * upon completion of a transmit frame
7575 */
7576static void usc_loopmode_send_done( struct mgsl_struct * info )
7577{
0fab6de0 7578 info->loopmode_send_done_requested = false;
1da177e4 7579 /* clear CMR:13 to 0 to start echoing RxData to TxData */
e06922aa 7580 info->cmr_value &= ~BIT13;
1da177e4
LT		 7581 usc_OutReg(info, CMR, info->cmr_value);
7582}
7583
7584/* abort a transmit in progress while in HDLC LoopMode
7585 */
7586static void usc_loopmode_cancel_transmit( struct mgsl_struct * info )
7587{
7588 /* reset tx dma channel and purge TxFifo */
7589 usc_RTCmd( info, RTCmd_PurgeTxFifo );
7590 usc_DmaCmd( info, DmaCmd_ResetTxChannel );
7591 usc_loopmode_send_done( info );
7592}
7593
7594/* for HDLC/SDLC LoopMode, setting CMR:13 after the transmitter is enabled
7595 * is an Insert Into Loop action. Upon receipt of a GoAhead sequence (RxAbort)
7596 * we must clear CMR:13 to begin repeating TxData to RxData
7597 */
7598static void usc_loopmode_insert_request( struct mgsl_struct * info )
7599{
0fab6de0 7600 info->loopmode_insert_requested = true;
1da177e4
LT		 7601
7602 /* enable RxAbort irq. On next RxAbort, clear CMR:13 to
7603 * begin repeating TxData on RxData (complete insertion)
7604 */
7605 usc_OutReg( info, RICR,
7606 (usc_InReg( info, RICR ) | RXSTATUS_ABORT_RECEIVED ) );
7607
7608 /* set CMR:13 to insert into loop on next GoAhead (RxAbort) */
7609 info->cmr_value |= BIT13;
7610 usc_OutReg(info, CMR, info->cmr_value);
7611}
7612
7613/* return 1 if station is inserted into the loop, otherwise 0
7614 */
7615static int usc_loopmode_active( struct mgsl_struct * info)
7616{
7617 return usc_InReg( info, CCSR ) & BIT7 ? 1 : 0 ;
7618}
7619
af69c7f9 7620#if SYNCLINK_GENERIC_HDLC
1da177e4
LT		 7621
7622/**
7623 * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
7624 * set encoding and frame check sequence (FCS) options
7625 *
7626 * dev pointer to network device structure
7627 * encoding serial encoding setting
7628 * parity FCS setting
7629 *
7630 * returns 0 if success, otherwise error code
7631 */
7632static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
7633 unsigned short parity)
7634{
7635 struct mgsl_struct *info = dev_to_port(dev);
7636 unsigned char new_encoding;
7637 unsigned short new_crctype;
7638
7639 /* return error if TTY interface open */
8fb06c77 7640 if (info->port.count)
1da177e4
LT		 7641 return -EBUSY;
7642
7643 switch (encoding)
7644 {
7645 case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
7646 case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
7647 case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
7648 case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
7649 case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
7650 default: return -EINVAL;
7651 }
7652
7653 switch (parity)
7654 {
7655 case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
7656 case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
7657 case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
7658 default: return -EINVAL;
7659 }
7660
7661 info->params.encoding = new_encoding;
53b3531b 7662 info->params.crc_type = new_crctype;
1da177e4
LT		 7663
7664 /* if network interface up, reprogram hardware */
7665 if (info->netcount)
7666 mgsl_program_hw(info);
7667
7668 return 0;
7669}
7670
7671/**
7672 * called by generic HDLC layer to send frame
7673 *
7674 * skb socket buffer containing HDLC frame
7675 * dev pointer to network device structure
1da177e4 7676 */
4c5d502d
SH		 7677static netdev_tx_t hdlcdev_xmit(struct sk_buff *skb,
7678 struct net_device *dev)
1da177e4
LT		 7679{
7680 struct mgsl_struct *info = dev_to_port(dev);
1da177e4
LT		 7681 unsigned long flags;
7682
7683 if (debug_level >= DEBUG_LEVEL_INFO)
7684 printk(KERN_INFO "%s:hdlc_xmit(%s)\n",__FILE__,dev->name);
7685
7686 /* stop sending until this frame completes */
7687 netif_stop_queue(dev);
7688
7689 /* copy data to device buffers */
7690 info->xmit_cnt = skb->len;
7691 mgsl_load_tx_dma_buffer(info, skb->data, skb->len);
7692
7693 /* update network statistics */
198191c4
KH		 7694 dev->stats.tx_packets++;
7695 dev->stats.tx_bytes += skb->len;
1da177e4
LT		 7696
7697 /* done with socket buffer, so free it */
7698 dev_kfree_skb(skb);
7699
7700 /* save start time for transmit timeout detection */
860e9538 7701 netif_trans_update(dev);
1da177e4
LT		 7702
7703 /* start hardware transmitter if necessary */
7704 spin_lock_irqsave(&info->irq_spinlock,flags);
7705 if (!info->tx_active)
7706 usc_start_transmitter(info);
7707 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7708
4c5d502d 7709 return NETDEV_TX_OK;
1da177e4
LT		 7710}
7711
7712/**
7713 * called by network layer when interface enabled
7714 * claim resources and initialize hardware
7715 *
7716 * dev pointer to network device structure
7717 *
7718 * returns 0 if success, otherwise error code
7719 */
7720static int hdlcdev_open(struct net_device *dev)
7721{
7722 struct mgsl_struct *info = dev_to_port(dev);
7723 int rc;
7724 unsigned long flags;
7725
7726 if (debug_level >= DEBUG_LEVEL_INFO)
7727 printk("%s:hdlcdev_open(%s)\n",__FILE__,dev->name);
7728
7729 /* generic HDLC layer open processing */
a271ca37
GKH		 7730 rc = hdlc_open(dev);
7731 if (rc)
1da177e4
LT		 7732 return rc;
7733
7734 /* arbitrate between network and tty opens */
7735 spin_lock_irqsave(&info->netlock, flags);
8fb06c77 7736 if (info->port.count != 0 || info->netcount != 0) {
1da177e4
LT		 7737 printk(KERN_WARNING "%s: hdlc_open returning busy\n", dev->name);
7738 spin_unlock_irqrestore(&info->netlock, flags);
7739 return -EBUSY;
7740 }
7741 info->netcount=1;
7742 spin_unlock_irqrestore(&info->netlock, flags);
7743
7744 /* claim resources and init adapter */
7745 if ((rc = startup(info)) != 0) {
7746 spin_lock_irqsave(&info->netlock, flags);
7747 info->netcount=0;
7748 spin_unlock_irqrestore(&info->netlock, flags);
7749 return rc;
7750 }
7751
9fe8074b
JP		 7752 /* assert RTS and DTR, apply hardware settings */
7753 info->serial_signals |= SerialSignal_RTS | SerialSignal_DTR;
1da177e4
LT		 7754 mgsl_program_hw(info);
7755
7756 /* enable network layer transmit */
860e9538 7757 netif_trans_update(dev);
1da177e4
LT		 7758 netif_start_queue(dev);
7759
7760 /* inform generic HDLC layer of current DCD status */
7761 spin_lock_irqsave(&info->irq_spinlock, flags);
7762 usc_get_serial_signals(info);
7763 spin_unlock_irqrestore(&info->irq_spinlock, flags);
fbeff3c1
KH		 7764 if (info->serial_signals & SerialSignal_DCD)
7765 netif_carrier_on(dev);
7766 else
7767 netif_carrier_off(dev);
1da177e4
LT		 7768 return 0;
7769}
7770
7771/**
7772 * called by network layer when interface is disabled
7773 * shutdown hardware and release resources
7774 *
7775 * dev pointer to network device structure
7776 *
7777 * returns 0 if success, otherwise error code
7778 */
7779static int hdlcdev_close(struct net_device *dev)
7780{
7781 struct mgsl_struct *info = dev_to_port(dev);
7782 unsigned long flags;
7783
7784 if (debug_level >= DEBUG_LEVEL_INFO)
7785 printk("%s:hdlcdev_close(%s)\n",__FILE__,dev->name);
7786
7787 netif_stop_queue(dev);
7788
7789 /* shutdown adapter and release resources */
7790 shutdown(info);
7791
7792 hdlc_close(dev);
7793
7794 spin_lock_irqsave(&info->netlock, flags);
7795 info->netcount=0;
7796 spin_unlock_irqrestore(&info->netlock, flags);
7797
7798 return 0;
7799}
7800
7801/**
7802 * called by network layer to process IOCTL call to network device
7803 *
7804 * dev pointer to network device structure
7805 * ifr pointer to network interface request structure
7806 * cmd IOCTL command code
7807 *
7808 * returns 0 if success, otherwise error code
7809 */
7810static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
7811{
7812 const size_t size = sizeof(sync_serial_settings);
7813 sync_serial_settings new_line;
7814 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
7815 struct mgsl_struct *info = dev_to_port(dev);
7816 unsigned int flags;
7817
7818 if (debug_level >= DEBUG_LEVEL_INFO)
7819 printk("%s:hdlcdev_ioctl(%s)\n",__FILE__,dev->name);
7820
7821 /* return error if TTY interface open */
8fb06c77 7822 if (info->port.count)
1da177e4
LT		 7823 return -EBUSY;
7824
7825 if (cmd != SIOCWANDEV)
7826 return hdlc_ioctl(dev, ifr, cmd);
7827
7828 switch(ifr->ifr_settings.type) {
7829 case IF_GET_IFACE: /* return current sync_serial_settings */
7830
7831 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
7832 if (ifr->ifr_settings.size < size) {
7833 ifr->ifr_settings.size = size; /* data size wanted */
7834 return -ENOBUFS;
7835 }
7836
7837 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
7838 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
7839 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
7840 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
7841
b19a47e0 7842 memset(&new_line, 0, sizeof(new_line));
1da177e4
LT		 7843 switch (flags){
7844 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
7845 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
7846 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
7847 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
7848 default: new_line.clock_type = CLOCK_DEFAULT;
7849 }
7850
7851 new_line.clock_rate = info->params.clock_speed;
7852 new_line.loopback = info->params.loopback ? 1:0;
7853
7854 if (copy_to_user(line, &new_line, size))
7855 return -EFAULT;
7856 return 0;
7857
7858 case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
7859
7860 if(!capable(CAP_NET_ADMIN))
7861 return -EPERM;
7862 if (copy_from_user(&new_line, line, size))
7863 return -EFAULT;
7864
7865 switch (new_line.clock_type)
7866 {
7867 case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
7868 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
7869 case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
7870 case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
7871 case CLOCK_DEFAULT: flags = info->params.flags &
7872 (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
7873 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
7874 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
7875 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
7876 default: return -EINVAL;
7877 }
7878
7879 if (new_line.loopback != 0 && new_line.loopback != 1)
7880 return -EINVAL;
7881
7882 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
7883 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
7884 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
7885 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
7886 info->params.flags |= flags;
7887
7888 info->params.loopback = new_line.loopback;
7889
7890 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
7891 info->params.clock_speed = new_line.clock_rate;
7892 else
7893 info->params.clock_speed = 0;
7894
7895 /* if network interface up, reprogram hardware */
7896 if (info->netcount)
7897 mgsl_program_hw(info);
7898 return 0;
7899
7900 default:
7901 return hdlc_ioctl(dev, ifr, cmd);
7902 }
7903}
7904
7905/**
7906 * called by network layer when transmit timeout is detected
7907 *
7908 * dev pointer to network device structure
7909 */
7910static void hdlcdev_tx_timeout(struct net_device *dev)
7911{
7912 struct mgsl_struct *info = dev_to_port(dev);
1da177e4
LT		 7913 unsigned long flags;
7914
7915 if (debug_level >= DEBUG_LEVEL_INFO)
7916 printk("hdlcdev_tx_timeout(%s)\n",dev->name);
7917
198191c4
KH		 7918 dev->stats.tx_errors++;
7919 dev->stats.tx_aborted_errors++;
1da177e4
LT		 7920
7921 spin_lock_irqsave(&info->irq_spinlock,flags);
7922 usc_stop_transmitter(info);
7923 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7924
7925 netif_wake_queue(dev);
7926}
7927
7928/**
7929 * called by device driver when transmit completes
7930 * reenable network layer transmit if stopped
7931 *
7932 * info pointer to device instance information
7933 */
7934static void hdlcdev_tx_done(struct mgsl_struct *info)
7935{
7936 if (netif_queue_stopped(info->netdev))
7937 netif_wake_queue(info->netdev);
7938}
7939
7940/**
7941 * called by device driver when frame received
7942 * pass frame to network layer
7943 *
7944 * info pointer to device instance information
7945 * buf pointer to buffer contianing frame data
7946 * size count of data bytes in buf
7947 */
7948static void hdlcdev_rx(struct mgsl_struct *info, char *buf, int size)
7949{
7950 struct sk_buff *skb = dev_alloc_skb(size);
7951 struct net_device *dev = info->netdev;
1da177e4
LT		 7952
7953 if (debug_level >= DEBUG_LEVEL_INFO)
198191c4 7954 printk("hdlcdev_rx(%s)\n", dev->name);
1da177e4
LT		 7955
7956 if (skb == NULL) {
198191c4
KH		 7957 printk(KERN_NOTICE "%s: can't alloc skb, dropping packet\n",
7958 dev->name);
7959 dev->stats.rx_dropped++;
1da177e4
LT		 7960 return;
7961 }
7962
59ae1d12 7963 skb_put_data(skb, buf, size);
1da177e4 7964
198191c4 7965 skb->protocol = hdlc_type_trans(skb, dev);
1da177e4 7966
198191c4
KH		 7967 dev->stats.rx_packets++;
7968 dev->stats.rx_bytes += size;
1da177e4
LT		 7969
7970 netif_rx(skb);
1da177e4
LT		 7971}
7972
991990a1
KH		 7973static const struct net_device_ops hdlcdev_ops = {
7974 .ndo_open = hdlcdev_open,
7975 .ndo_stop = hdlcdev_close,
991990a1
KH		 7976 .ndo_start_xmit = hdlc_start_xmit,
7977 .ndo_do_ioctl = hdlcdev_ioctl,
7978 .ndo_tx_timeout = hdlcdev_tx_timeout,
7979};
7980
1da177e4
LT		 7981/**
7982 * called by device driver when adding device instance
7983 * do generic HDLC initialization
7984 *
7985 * info pointer to device instance information
7986 *
7987 * returns 0 if success, otherwise error code
7988 */
7989static int hdlcdev_init(struct mgsl_struct *info)
7990{
7991 int rc;
7992 struct net_device *dev;
7993 hdlc_device *hdlc;
7994
7995 /* allocate and initialize network and HDLC layer objects */
7996
a271ca37
GKH		 7997 dev = alloc_hdlcdev(info);
7998 if (!dev) {
1da177e4
LT		 7999 printk(KERN_ERR "%s:hdlc device allocation failure\n",__FILE__);
8000 return -ENOMEM;
8001 }
8002
8003 /* for network layer reporting purposes only */
8004 dev->base_addr = info->io_base;
8005 dev->irq = info->irq_level;
8006 dev->dma = info->dma_level;
8007
8008 /* network layer callbacks and settings */
991990a1
KH		 8009 dev->netdev_ops = &hdlcdev_ops;
8010 dev->watchdog_timeo = 10 * HZ;
1da177e4
LT		 8011 dev->tx_queue_len = 50;
8012
8013 /* generic HDLC layer callbacks and settings */
8014 hdlc = dev_to_hdlc(dev);
8015 hdlc->attach = hdlcdev_attach;
8016 hdlc->xmit = hdlcdev_xmit;
8017
8018 /* register objects with HDLC layer */
a271ca37
GKH		 8019 rc = register_hdlc_device(dev);
8020 if (rc) {
1da177e4
LT		 8021 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
8022 free_netdev(dev);
8023 return rc;
8024 }
8025
8026 info->netdev = dev;
8027 return 0;
8028}
8029
8030/**
8031 * called by device driver when removing device instance
8032 * do generic HDLC cleanup
8033 *
8034 * info pointer to device instance information
8035 */
8036static void hdlcdev_exit(struct mgsl_struct *info)
8037{
8038 unregister_hdlc_device(info->netdev);
8039 free_netdev(info->netdev);
8040 info->netdev = NULL;
8041}
8042
8043#endif /* CONFIG_HDLC */
8044
8045
9671f099 8046static int synclink_init_one (struct pci_dev *dev,
1da177e4
LT		 8047 const struct pci_device_id *ent)
8048{
8049 struct mgsl_struct *info;
8050
8051 if (pci_enable_device(dev)) {
8052 printk("error enabling pci device %p\n", dev);
8053 return -EIO;
8054 }
8055
a271ca37
GKH		 8056 info = mgsl_allocate_device();
8057 if (!info) {
1da177e4
LT		 8058 printk("can't allocate device instance data.\n");
8059 return -EIO;
8060 }
8061
8062 /* Copy user configuration info to device instance data */
8063
8064 info->io_base = pci_resource_start(dev, 2);
8065 info->irq_level = dev->irq;
8066 info->phys_memory_base = pci_resource_start(dev, 3);
8067
8068 /* Because veremap only works on page boundaries we must map
8069 * a larger area than is actually implemented for the LCR
8070 * memory range. We map a full page starting at the page boundary.
8071 */
8072 info->phys_lcr_base = pci_resource_start(dev, 0);
8073 info->lcr_offset = info->phys_lcr_base & (PAGE_SIZE-1);
8074 info->phys_lcr_base &= ~(PAGE_SIZE-1);
8075
8076 info->bus_type = MGSL_BUS_TYPE_PCI;
8077 info->io_addr_size = 8;
0f2ed4c6 8078 info->irq_flags = IRQF_SHARED;
1da177e4
LT		 8079
8080 if (dev->device == 0x0210) {
8081 /* Version 1 PCI9030 based universal PCI adapter */
8082 info->misc_ctrl_value = 0x007c4080;
8083 info->hw_version = 1;
8084 } else {
8085 /* Version 0 PCI9050 based 5V PCI adapter
8086 * A PCI9050 bug prevents reading LCR registers if
8087 * LCR base address bit 7 is set. Maintain shadow
8088 * value so we can write to LCR misc control reg.
8089 */
8090 info->misc_ctrl_value = 0x087e4546;
8091 info->hw_version = 0;
8092 }
8093
8094 mgsl_add_device(info);
8095
8096 return 0;
8097}
8098
ae8d8a14 8099static void synclink_remove_one (struct pci_dev *dev)
1da177e4
LT		 8100{
8101}
8102
Linux 6.x block layer and io_uring tree(s)