Commit | Line | Data |
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61ec9016 JL |
1 | /* |
2 | * Xilinx PS UART driver | |
3 | * | |
e555a211 | 4 | * 2011 - 2014 (C) Xilinx Inc. |
61ec9016 JL |
5 | * |
6 | * This program is free software; you can redistribute it | |
7 | * and/or modify it under the terms of the GNU General Public | |
8 | * License as published by the Free Software Foundation; | |
9 | * either version 2 of the License, or (at your option) any | |
10 | * later version. | |
61ec9016 JL |
11 | */ |
12 | ||
0c0c47bc VL |
13 | #if defined(CONFIG_SERIAL_XILINX_PS_UART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) |
14 | #define SUPPORT_SYSRQ | |
15 | #endif | |
16 | ||
61ec9016 | 17 | #include <linux/platform_device.h> |
ee160a38 | 18 | #include <linux/serial.h> |
0c0c47bc | 19 | #include <linux/console.h> |
61ec9016 | 20 | #include <linux/serial_core.h> |
30e1e285 | 21 | #include <linux/slab.h> |
ee160a38 JS |
22 | #include <linux/tty.h> |
23 | #include <linux/tty_flip.h> | |
2326669c | 24 | #include <linux/clk.h> |
61ec9016 JL |
25 | #include <linux/irq.h> |
26 | #include <linux/io.h> | |
27 | #include <linux/of.h> | |
578b9ce0 | 28 | #include <linux/module.h> |
61ec9016 JL |
29 | |
30 | #define XUARTPS_TTY_NAME "ttyPS" | |
31 | #define XUARTPS_NAME "xuartps" | |
32 | #define XUARTPS_MAJOR 0 /* use dynamic node allocation */ | |
33 | #define XUARTPS_MINOR 0 /* works best with devtmpfs */ | |
34 | #define XUARTPS_NR_PORTS 2 | |
85baf542 | 35 | #define XUARTPS_FIFO_SIZE 64 /* FIFO size */ |
61ec9016 JL |
36 | #define XUARTPS_REGISTER_SPACE 0xFFF |
37 | ||
38 | #define xuartps_readl(offset) ioread32(port->membase + offset) | |
39 | #define xuartps_writel(val, offset) iowrite32(val, port->membase + offset) | |
40 | ||
85baf542 S |
41 | /* Rx Trigger level */ |
42 | static int rx_trigger_level = 56; | |
43 | module_param(rx_trigger_level, uint, S_IRUGO); | |
44 | MODULE_PARM_DESC(rx_trigger_level, "Rx trigger level, 1-63 bytes"); | |
45 | ||
46 | /* Rx Timeout */ | |
47 | static int rx_timeout = 10; | |
48 | module_param(rx_timeout, uint, S_IRUGO); | |
49 | MODULE_PARM_DESC(rx_timeout, "Rx timeout, 1-255"); | |
50 | ||
e555a211 SB |
51 | /* Register offsets for the UART. */ |
52 | #define XUARTPS_CR_OFFSET 0x00 /* Control Register */ | |
53 | #define XUARTPS_MR_OFFSET 0x04 /* Mode Register */ | |
54 | #define XUARTPS_IER_OFFSET 0x08 /* Interrupt Enable */ | |
55 | #define XUARTPS_IDR_OFFSET 0x0C /* Interrupt Disable */ | |
56 | #define XUARTPS_IMR_OFFSET 0x10 /* Interrupt Mask */ | |
57 | #define XUARTPS_ISR_OFFSET 0x14 /* Interrupt Status */ | |
58 | #define XUARTPS_BAUDGEN_OFFSET 0x18 /* Baud Rate Generator */ | |
59 | #define XUARTPS_RXTOUT_OFFSET 0x1C /* RX Timeout */ | |
60 | #define XUARTPS_RXWM_OFFSET 0x20 /* RX FIFO Trigger Level */ | |
61 | #define XUARTPS_MODEMCR_OFFSET 0x24 /* Modem Control */ | |
62 | #define XUARTPS_MODEMSR_OFFSET 0x28 /* Modem Status */ | |
63 | #define XUARTPS_SR_OFFSET 0x2C /* Channel Status */ | |
64 | #define XUARTPS_FIFO_OFFSET 0x30 /* FIFO */ | |
65 | #define XUARTPS_BAUDDIV_OFFSET 0x34 /* Baud Rate Divider */ | |
66 | #define XUARTPS_FLOWDEL_OFFSET 0x38 /* Flow Delay */ | |
67 | #define XUARTPS_IRRX_PWIDTH_OFFSET 0x3C /* IR Minimum Received Pulse Width */ | |
68 | #define XUARTPS_IRTX_PWIDTH_OFFSET 0x40 /* IR Transmitted pulse Width */ | |
69 | #define XUARTPS_TXWM_OFFSET 0x44 /* TX FIFO Trigger Level */ | |
70 | ||
71 | /* Control Register Bit Definitions */ | |
61ec9016 JL |
72 | #define XUARTPS_CR_STOPBRK 0x00000100 /* Stop TX break */ |
73 | #define XUARTPS_CR_STARTBRK 0x00000080 /* Set TX break */ | |
74 | #define XUARTPS_CR_TX_DIS 0x00000020 /* TX disabled. */ | |
75 | #define XUARTPS_CR_TX_EN 0x00000010 /* TX enabled */ | |
76 | #define XUARTPS_CR_RX_DIS 0x00000008 /* RX disabled. */ | |
77 | #define XUARTPS_CR_RX_EN 0x00000004 /* RX enabled */ | |
78 | #define XUARTPS_CR_TXRST 0x00000002 /* TX logic reset */ | |
79 | #define XUARTPS_CR_RXRST 0x00000001 /* RX logic reset */ | |
80 | #define XUARTPS_CR_RST_TO 0x00000040 /* Restart Timeout Counter */ | |
81 | ||
e555a211 SB |
82 | /* |
83 | * Mode Register: | |
61ec9016 JL |
84 | * The mode register (MR) defines the mode of transfer as well as the data |
85 | * format. If this register is modified during transmission or reception, | |
86 | * data validity cannot be guaranteed. | |
61ec9016 JL |
87 | */ |
88 | #define XUARTPS_MR_CLKSEL 0x00000001 /* Pre-scalar selection */ | |
89 | #define XUARTPS_MR_CHMODE_L_LOOP 0x00000200 /* Local loop back mode */ | |
90 | #define XUARTPS_MR_CHMODE_NORM 0x00000000 /* Normal mode */ | |
91 | ||
92 | #define XUARTPS_MR_STOPMODE_2_BIT 0x00000080 /* 2 stop bits */ | |
93 | #define XUARTPS_MR_STOPMODE_1_BIT 0x00000000 /* 1 stop bit */ | |
94 | ||
95 | #define XUARTPS_MR_PARITY_NONE 0x00000020 /* No parity mode */ | |
96 | #define XUARTPS_MR_PARITY_MARK 0x00000018 /* Mark parity mode */ | |
97 | #define XUARTPS_MR_PARITY_SPACE 0x00000010 /* Space parity mode */ | |
98 | #define XUARTPS_MR_PARITY_ODD 0x00000008 /* Odd parity mode */ | |
99 | #define XUARTPS_MR_PARITY_EVEN 0x00000000 /* Even parity mode */ | |
100 | ||
101 | #define XUARTPS_MR_CHARLEN_6_BIT 0x00000006 /* 6 bits data */ | |
102 | #define XUARTPS_MR_CHARLEN_7_BIT 0x00000004 /* 7 bits data */ | |
103 | #define XUARTPS_MR_CHARLEN_8_BIT 0x00000000 /* 8 bits data */ | |
104 | ||
e555a211 SB |
105 | /* |
106 | * Interrupt Registers: | |
61ec9016 JL |
107 | * Interrupt control logic uses the interrupt enable register (IER) and the |
108 | * interrupt disable register (IDR) to set the value of the bits in the | |
109 | * interrupt mask register (IMR). The IMR determines whether to pass an | |
110 | * interrupt to the interrupt status register (ISR). | |
111 | * Writing a 1 to IER Enables an interrupt, writing a 1 to IDR disables an | |
112 | * interrupt. IMR and ISR are read only, and IER and IDR are write only. | |
113 | * Reading either IER or IDR returns 0x00. | |
61ec9016 JL |
114 | * All four registers have the same bit definitions. |
115 | */ | |
116 | #define XUARTPS_IXR_TOUT 0x00000100 /* RX Timeout error interrupt */ | |
117 | #define XUARTPS_IXR_PARITY 0x00000080 /* Parity error interrupt */ | |
118 | #define XUARTPS_IXR_FRAMING 0x00000040 /* Framing error interrupt */ | |
119 | #define XUARTPS_IXR_OVERRUN 0x00000020 /* Overrun error interrupt */ | |
120 | #define XUARTPS_IXR_TXFULL 0x00000010 /* TX FIFO Full interrupt */ | |
121 | #define XUARTPS_IXR_TXEMPTY 0x00000008 /* TX FIFO empty interrupt */ | |
122 | #define XUARTPS_ISR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt */ | |
123 | #define XUARTPS_IXR_RXTRIG 0x00000001 /* RX FIFO trigger interrupt */ | |
124 | #define XUARTPS_IXR_RXFULL 0x00000004 /* RX FIFO full interrupt. */ | |
125 | #define XUARTPS_IXR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt. */ | |
126 | #define XUARTPS_IXR_MASK 0x00001FFF /* Valid bit mask */ | |
127 | ||
0c0c47bc VL |
128 | /* Goes in read_status_mask for break detection as the HW doesn't do it*/ |
129 | #define XUARTPS_IXR_BRK 0x80000000 | |
130 | ||
e555a211 SB |
131 | /* |
132 | * Channel Status Register: | |
61ec9016 JL |
133 | * The channel status register (CSR) is provided to enable the control logic |
134 | * to monitor the status of bits in the channel interrupt status register, | |
135 | * even if these are masked out by the interrupt mask register. | |
136 | */ | |
137 | #define XUARTPS_SR_RXEMPTY 0x00000002 /* RX FIFO empty */ | |
138 | #define XUARTPS_SR_TXEMPTY 0x00000008 /* TX FIFO empty */ | |
139 | #define XUARTPS_SR_TXFULL 0x00000010 /* TX FIFO full */ | |
140 | #define XUARTPS_SR_RXTRIG 0x00000001 /* Rx Trigger */ | |
141 | ||
e6b39bfd SB |
142 | /* baud dividers min/max values */ |
143 | #define XUARTPS_BDIV_MIN 4 | |
144 | #define XUARTPS_BDIV_MAX 255 | |
145 | #define XUARTPS_CD_MAX 65535 | |
146 | ||
30e1e285 SB |
147 | /** |
148 | * struct xuartps - device data | |
489810a1 MS |
149 | * @port: Pointer to the UART port |
150 | * @refclk: Reference clock | |
151 | * @aperclk: APB clock | |
152 | * @baud: Current baud rate | |
153 | * @clk_rate_change_nb: Notifier block for clock changes | |
30e1e285 SB |
154 | */ |
155 | struct xuartps { | |
c4b0510c | 156 | struct uart_port *port; |
30e1e285 SB |
157 | struct clk *refclk; |
158 | struct clk *aperclk; | |
c4b0510c SB |
159 | unsigned int baud; |
160 | struct notifier_block clk_rate_change_nb; | |
30e1e285 | 161 | }; |
c4b0510c | 162 | #define to_xuartps(_nb) container_of(_nb, struct xuartps, clk_rate_change_nb); |
30e1e285 | 163 | |
61ec9016 JL |
164 | /** |
165 | * xuartps_isr - Interrupt handler | |
166 | * @irq: Irq number | |
167 | * @dev_id: Id of the port | |
168 | * | |
489810a1 MS |
169 | * Return: IRQHANDLED |
170 | */ | |
61ec9016 JL |
171 | static irqreturn_t xuartps_isr(int irq, void *dev_id) |
172 | { | |
173 | struct uart_port *port = (struct uart_port *)dev_id; | |
61ec9016 JL |
174 | unsigned long flags; |
175 | unsigned int isrstatus, numbytes; | |
176 | unsigned int data; | |
177 | char status = TTY_NORMAL; | |
178 | ||
61ec9016 JL |
179 | spin_lock_irqsave(&port->lock, flags); |
180 | ||
181 | /* Read the interrupt status register to determine which | |
182 | * interrupt(s) is/are active. | |
183 | */ | |
184 | isrstatus = xuartps_readl(XUARTPS_ISR_OFFSET); | |
185 | ||
0c0c47bc VL |
186 | /* |
187 | * There is no hardware break detection, so we interpret framing | |
188 | * error with all-zeros data as a break sequence. Most of the time, | |
189 | * there's another non-zero byte at the end of the sequence. | |
190 | */ | |
0c0c47bc VL |
191 | if (isrstatus & XUARTPS_IXR_FRAMING) { |
192 | while (!(xuartps_readl(XUARTPS_SR_OFFSET) & | |
193 | XUARTPS_SR_RXEMPTY)) { | |
194 | if (!xuartps_readl(XUARTPS_FIFO_OFFSET)) { | |
195 | port->read_status_mask |= XUARTPS_IXR_BRK; | |
196 | isrstatus &= ~XUARTPS_IXR_FRAMING; | |
197 | } | |
198 | } | |
199 | xuartps_writel(XUARTPS_IXR_FRAMING, XUARTPS_ISR_OFFSET); | |
200 | } | |
201 | ||
61ec9016 JL |
202 | /* drop byte with parity error if IGNPAR specified */ |
203 | if (isrstatus & port->ignore_status_mask & XUARTPS_IXR_PARITY) | |
204 | isrstatus &= ~(XUARTPS_IXR_RXTRIG | XUARTPS_IXR_TOUT); | |
205 | ||
206 | isrstatus &= port->read_status_mask; | |
207 | isrstatus &= ~port->ignore_status_mask; | |
208 | ||
209 | if ((isrstatus & XUARTPS_IXR_TOUT) || | |
210 | (isrstatus & XUARTPS_IXR_RXTRIG)) { | |
211 | /* Receive Timeout Interrupt */ | |
212 | while ((xuartps_readl(XUARTPS_SR_OFFSET) & | |
213 | XUARTPS_SR_RXEMPTY) != XUARTPS_SR_RXEMPTY) { | |
214 | data = xuartps_readl(XUARTPS_FIFO_OFFSET); | |
0c0c47bc VL |
215 | |
216 | /* Non-NULL byte after BREAK is garbage (99%) */ | |
217 | if (data && (port->read_status_mask & | |
218 | XUARTPS_IXR_BRK)) { | |
219 | port->read_status_mask &= ~XUARTPS_IXR_BRK; | |
220 | port->icount.brk++; | |
221 | if (uart_handle_break(port)) | |
222 | continue; | |
223 | } | |
224 | ||
c2db11ec | 225 | #ifdef SUPPORT_SYSRQ |
0c0c47bc VL |
226 | /* |
227 | * uart_handle_sysrq_char() doesn't work if | |
228 | * spinlocked, for some reason | |
229 | */ | |
230 | if (port->sysrq) { | |
231 | spin_unlock(&port->lock); | |
232 | if (uart_handle_sysrq_char(port, | |
233 | (unsigned char)data)) { | |
234 | spin_lock(&port->lock); | |
235 | continue; | |
236 | } | |
237 | spin_lock(&port->lock); | |
238 | } | |
c2db11ec | 239 | #endif |
0c0c47bc | 240 | |
61ec9016 JL |
241 | port->icount.rx++; |
242 | ||
243 | if (isrstatus & XUARTPS_IXR_PARITY) { | |
244 | port->icount.parity++; | |
245 | status = TTY_PARITY; | |
246 | } else if (isrstatus & XUARTPS_IXR_FRAMING) { | |
247 | port->icount.frame++; | |
248 | status = TTY_FRAME; | |
e555a211 | 249 | } else if (isrstatus & XUARTPS_IXR_OVERRUN) { |
61ec9016 | 250 | port->icount.overrun++; |
e555a211 | 251 | } |
61ec9016 | 252 | |
2e124b4a JS |
253 | uart_insert_char(port, isrstatus, XUARTPS_IXR_OVERRUN, |
254 | data, status); | |
61ec9016 JL |
255 | } |
256 | spin_unlock(&port->lock); | |
2e124b4a | 257 | tty_flip_buffer_push(&port->state->port); |
61ec9016 JL |
258 | spin_lock(&port->lock); |
259 | } | |
260 | ||
261 | /* Dispatch an appropriate handler */ | |
262 | if ((isrstatus & XUARTPS_IXR_TXEMPTY) == XUARTPS_IXR_TXEMPTY) { | |
263 | if (uart_circ_empty(&port->state->xmit)) { | |
264 | xuartps_writel(XUARTPS_IXR_TXEMPTY, | |
265 | XUARTPS_IDR_OFFSET); | |
266 | } else { | |
267 | numbytes = port->fifosize; | |
268 | /* Break if no more data available in the UART buffer */ | |
269 | while (numbytes--) { | |
270 | if (uart_circ_empty(&port->state->xmit)) | |
271 | break; | |
272 | /* Get the data from the UART circular buffer | |
273 | * and write it to the xuartps's TX_FIFO | |
274 | * register. | |
275 | */ | |
276 | xuartps_writel( | |
277 | port->state->xmit.buf[port->state->xmit. | |
278 | tail], XUARTPS_FIFO_OFFSET); | |
279 | ||
280 | port->icount.tx++; | |
281 | ||
282 | /* Adjust the tail of the UART buffer and wrap | |
283 | * the buffer if it reaches limit. | |
284 | */ | |
285 | port->state->xmit.tail = | |
e555a211 | 286 | (port->state->xmit.tail + 1) & |
61ec9016 JL |
287 | (UART_XMIT_SIZE - 1); |
288 | } | |
289 | ||
290 | if (uart_circ_chars_pending( | |
291 | &port->state->xmit) < WAKEUP_CHARS) | |
292 | uart_write_wakeup(port); | |
293 | } | |
294 | } | |
295 | ||
296 | xuartps_writel(isrstatus, XUARTPS_ISR_OFFSET); | |
297 | ||
298 | /* be sure to release the lock and tty before leaving */ | |
299 | spin_unlock_irqrestore(&port->lock, flags); | |
61ec9016 JL |
300 | |
301 | return IRQ_HANDLED; | |
302 | } | |
303 | ||
304 | /** | |
e6b39bfd SB |
305 | * xuartps_calc_baud_divs - Calculate baud rate divisors |
306 | * @clk: UART module input clock | |
307 | * @baud: Desired baud rate | |
308 | * @rbdiv: BDIV value (return value) | |
309 | * @rcd: CD value (return value) | |
310 | * @div8: Value for clk_sel bit in mod (return value) | |
489810a1 | 311 | * Return: baud rate, requested baud when possible, or actual baud when there |
e6b39bfd SB |
312 | * was too much error, zero if no valid divisors are found. |
313 | * | |
314 | * Formula to obtain baud rate is | |
315 | * baud_tx/rx rate = clk/CD * (BDIV + 1) | |
316 | * input_clk = (Uart User Defined Clock or Apb Clock) | |
317 | * depends on UCLKEN in MR Reg | |
318 | * clk = input_clk or input_clk/8; | |
319 | * depends on CLKS in MR reg | |
320 | * CD and BDIV depends on values in | |
321 | * baud rate generate register | |
322 | * baud rate clock divisor register | |
323 | */ | |
324 | static unsigned int xuartps_calc_baud_divs(unsigned int clk, unsigned int baud, | |
325 | u32 *rbdiv, u32 *rcd, int *div8) | |
61ec9016 | 326 | { |
e6b39bfd SB |
327 | u32 cd, bdiv; |
328 | unsigned int calc_baud; | |
329 | unsigned int bestbaud = 0; | |
61ec9016 | 330 | unsigned int bauderror; |
e6b39bfd | 331 | unsigned int besterror = ~0; |
61ec9016 | 332 | |
e6b39bfd SB |
333 | if (baud < clk / ((XUARTPS_BDIV_MAX + 1) * XUARTPS_CD_MAX)) { |
334 | *div8 = 1; | |
335 | clk /= 8; | |
336 | } else { | |
337 | *div8 = 0; | |
338 | } | |
61ec9016 | 339 | |
e6b39bfd SB |
340 | for (bdiv = XUARTPS_BDIV_MIN; bdiv <= XUARTPS_BDIV_MAX; bdiv++) { |
341 | cd = DIV_ROUND_CLOSEST(clk, baud * (bdiv + 1)); | |
342 | if (cd < 1 || cd > XUARTPS_CD_MAX) | |
61ec9016 JL |
343 | continue; |
344 | ||
e6b39bfd | 345 | calc_baud = clk / (cd * (bdiv + 1)); |
61ec9016 JL |
346 | |
347 | if (baud > calc_baud) | |
348 | bauderror = baud - calc_baud; | |
349 | else | |
350 | bauderror = calc_baud - baud; | |
351 | ||
e6b39bfd SB |
352 | if (besterror > bauderror) { |
353 | *rbdiv = bdiv; | |
354 | *rcd = cd; | |
355 | bestbaud = calc_baud; | |
356 | besterror = bauderror; | |
61ec9016 JL |
357 | } |
358 | } | |
e6b39bfd SB |
359 | /* use the values when percent error is acceptable */ |
360 | if (((besterror * 100) / baud) < 3) | |
361 | bestbaud = baud; | |
362 | ||
363 | return bestbaud; | |
364 | } | |
61ec9016 | 365 | |
e6b39bfd SB |
366 | /** |
367 | * xuartps_set_baud_rate - Calculate and set the baud rate | |
368 | * @port: Handle to the uart port structure | |
369 | * @baud: Baud rate to set | |
489810a1 | 370 | * Return: baud rate, requested baud when possible, or actual baud when there |
e6b39bfd SB |
371 | * was too much error, zero if no valid divisors are found. |
372 | */ | |
373 | static unsigned int xuartps_set_baud_rate(struct uart_port *port, | |
374 | unsigned int baud) | |
375 | { | |
376 | unsigned int calc_baud; | |
d54b181e | 377 | u32 cd = 0, bdiv = 0; |
e6b39bfd SB |
378 | u32 mreg; |
379 | int div8; | |
c4b0510c | 380 | struct xuartps *xuartps = port->private_data; |
e6b39bfd SB |
381 | |
382 | calc_baud = xuartps_calc_baud_divs(port->uartclk, baud, &bdiv, &cd, | |
383 | &div8); | |
384 | ||
385 | /* Write new divisors to hardware */ | |
386 | mreg = xuartps_readl(XUARTPS_MR_OFFSET); | |
387 | if (div8) | |
388 | mreg |= XUARTPS_MR_CLKSEL; | |
389 | else | |
390 | mreg &= ~XUARTPS_MR_CLKSEL; | |
391 | xuartps_writel(mreg, XUARTPS_MR_OFFSET); | |
392 | xuartps_writel(cd, XUARTPS_BAUDGEN_OFFSET); | |
393 | xuartps_writel(bdiv, XUARTPS_BAUDDIV_OFFSET); | |
c4b0510c | 394 | xuartps->baud = baud; |
61ec9016 JL |
395 | |
396 | return calc_baud; | |
397 | } | |
398 | ||
7ac57347 | 399 | #ifdef CONFIG_COMMON_CLK |
c4b0510c SB |
400 | /** |
401 | * xuartps_clk_notitifer_cb - Clock notifier callback | |
402 | * @nb: Notifier block | |
403 | * @event: Notify event | |
404 | * @data: Notifier data | |
e555a211 | 405 | * Return: NOTIFY_OK or NOTIFY_DONE on success, NOTIFY_BAD on error. |
c4b0510c SB |
406 | */ |
407 | static int xuartps_clk_notifier_cb(struct notifier_block *nb, | |
408 | unsigned long event, void *data) | |
409 | { | |
410 | u32 ctrl_reg; | |
411 | struct uart_port *port; | |
412 | int locked = 0; | |
413 | struct clk_notifier_data *ndata = data; | |
414 | unsigned long flags = 0; | |
415 | struct xuartps *xuartps = to_xuartps(nb); | |
416 | ||
417 | port = xuartps->port; | |
418 | if (port->suspended) | |
419 | return NOTIFY_OK; | |
420 | ||
421 | switch (event) { | |
422 | case PRE_RATE_CHANGE: | |
423 | { | |
e555a211 | 424 | u32 bdiv, cd; |
c4b0510c SB |
425 | int div8; |
426 | ||
427 | /* | |
428 | * Find out if current baud-rate can be achieved with new clock | |
429 | * frequency. | |
430 | */ | |
431 | if (!xuartps_calc_baud_divs(ndata->new_rate, xuartps->baud, | |
432 | &bdiv, &cd, &div8)) | |
433 | return NOTIFY_BAD; | |
434 | ||
435 | spin_lock_irqsave(&xuartps->port->lock, flags); | |
436 | ||
437 | /* Disable the TX and RX to set baud rate */ | |
438 | xuartps_writel(xuartps_readl(XUARTPS_CR_OFFSET) | | |
439 | (XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS), | |
440 | XUARTPS_CR_OFFSET); | |
441 | ||
442 | spin_unlock_irqrestore(&xuartps->port->lock, flags); | |
443 | ||
444 | return NOTIFY_OK; | |
445 | } | |
446 | case POST_RATE_CHANGE: | |
447 | /* | |
448 | * Set clk dividers to generate correct baud with new clock | |
449 | * frequency. | |
450 | */ | |
451 | ||
452 | spin_lock_irqsave(&xuartps->port->lock, flags); | |
453 | ||
454 | locked = 1; | |
455 | port->uartclk = ndata->new_rate; | |
456 | ||
457 | xuartps->baud = xuartps_set_baud_rate(xuartps->port, | |
458 | xuartps->baud); | |
459 | /* fall through */ | |
460 | case ABORT_RATE_CHANGE: | |
461 | if (!locked) | |
462 | spin_lock_irqsave(&xuartps->port->lock, flags); | |
463 | ||
464 | /* Set TX/RX Reset */ | |
465 | xuartps_writel(xuartps_readl(XUARTPS_CR_OFFSET) | | |
466 | (XUARTPS_CR_TXRST | XUARTPS_CR_RXRST), | |
467 | XUARTPS_CR_OFFSET); | |
468 | ||
469 | while (xuartps_readl(XUARTPS_CR_OFFSET) & | |
470 | (XUARTPS_CR_TXRST | XUARTPS_CR_RXRST)) | |
471 | cpu_relax(); | |
472 | ||
473 | /* | |
474 | * Clear the RX disable and TX disable bits and then set the TX | |
475 | * enable bit and RX enable bit to enable the transmitter and | |
476 | * receiver. | |
477 | */ | |
478 | xuartps_writel(rx_timeout, XUARTPS_RXTOUT_OFFSET); | |
479 | ctrl_reg = xuartps_readl(XUARTPS_CR_OFFSET); | |
480 | xuartps_writel( | |
481 | (ctrl_reg & ~(XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS)) | | |
482 | (XUARTPS_CR_TX_EN | XUARTPS_CR_RX_EN), | |
483 | XUARTPS_CR_OFFSET); | |
484 | ||
485 | spin_unlock_irqrestore(&xuartps->port->lock, flags); | |
486 | ||
487 | return NOTIFY_OK; | |
488 | default: | |
489 | return NOTIFY_DONE; | |
490 | } | |
491 | } | |
7ac57347 | 492 | #endif |
c4b0510c | 493 | |
61ec9016 JL |
494 | /** |
495 | * xuartps_start_tx - Start transmitting bytes | |
496 | * @port: Handle to the uart port structure | |
489810a1 | 497 | */ |
61ec9016 JL |
498 | static void xuartps_start_tx(struct uart_port *port) |
499 | { | |
500 | unsigned int status, numbytes = port->fifosize; | |
501 | ||
502 | if (uart_circ_empty(&port->state->xmit) || uart_tx_stopped(port)) | |
503 | return; | |
504 | ||
505 | status = xuartps_readl(XUARTPS_CR_OFFSET); | |
506 | /* Set the TX enable bit and clear the TX disable bit to enable the | |
507 | * transmitter. | |
508 | */ | |
509 | xuartps_writel((status & ~XUARTPS_CR_TX_DIS) | XUARTPS_CR_TX_EN, | |
510 | XUARTPS_CR_OFFSET); | |
511 | ||
e555a211 SB |
512 | while (numbytes-- && ((xuartps_readl(XUARTPS_SR_OFFSET) & |
513 | XUARTPS_SR_TXFULL)) != XUARTPS_SR_TXFULL) { | |
61ec9016 JL |
514 | /* Break if no more data available in the UART buffer */ |
515 | if (uart_circ_empty(&port->state->xmit)) | |
516 | break; | |
517 | ||
518 | /* Get the data from the UART circular buffer and | |
519 | * write it to the xuartps's TX_FIFO register. | |
520 | */ | |
521 | xuartps_writel( | |
522 | port->state->xmit.buf[port->state->xmit.tail], | |
523 | XUARTPS_FIFO_OFFSET); | |
524 | port->icount.tx++; | |
525 | ||
526 | /* Adjust the tail of the UART buffer and wrap | |
527 | * the buffer if it reaches limit. | |
528 | */ | |
529 | port->state->xmit.tail = (port->state->xmit.tail + 1) & | |
530 | (UART_XMIT_SIZE - 1); | |
531 | } | |
85baf542 | 532 | xuartps_writel(XUARTPS_IXR_TXEMPTY, XUARTPS_ISR_OFFSET); |
61ec9016 JL |
533 | /* Enable the TX Empty interrupt */ |
534 | xuartps_writel(XUARTPS_IXR_TXEMPTY, XUARTPS_IER_OFFSET); | |
535 | ||
536 | if (uart_circ_chars_pending(&port->state->xmit) < WAKEUP_CHARS) | |
537 | uart_write_wakeup(port); | |
538 | } | |
539 | ||
540 | /** | |
541 | * xuartps_stop_tx - Stop TX | |
542 | * @port: Handle to the uart port structure | |
489810a1 | 543 | */ |
61ec9016 JL |
544 | static void xuartps_stop_tx(struct uart_port *port) |
545 | { | |
546 | unsigned int regval; | |
547 | ||
548 | regval = xuartps_readl(XUARTPS_CR_OFFSET); | |
549 | regval |= XUARTPS_CR_TX_DIS; | |
550 | /* Disable the transmitter */ | |
551 | xuartps_writel(regval, XUARTPS_CR_OFFSET); | |
552 | } | |
553 | ||
554 | /** | |
555 | * xuartps_stop_rx - Stop RX | |
556 | * @port: Handle to the uart port structure | |
489810a1 | 557 | */ |
61ec9016 JL |
558 | static void xuartps_stop_rx(struct uart_port *port) |
559 | { | |
560 | unsigned int regval; | |
561 | ||
562 | regval = xuartps_readl(XUARTPS_CR_OFFSET); | |
563 | regval |= XUARTPS_CR_RX_DIS; | |
564 | /* Disable the receiver */ | |
565 | xuartps_writel(regval, XUARTPS_CR_OFFSET); | |
566 | } | |
567 | ||
568 | /** | |
569 | * xuartps_tx_empty - Check whether TX is empty | |
570 | * @port: Handle to the uart port structure | |
571 | * | |
489810a1 MS |
572 | * Return: TIOCSER_TEMT on success, 0 otherwise |
573 | */ | |
61ec9016 JL |
574 | static unsigned int xuartps_tx_empty(struct uart_port *port) |
575 | { | |
576 | unsigned int status; | |
577 | ||
578 | status = xuartps_readl(XUARTPS_ISR_OFFSET) & XUARTPS_IXR_TXEMPTY; | |
579 | return status ? TIOCSER_TEMT : 0; | |
580 | } | |
581 | ||
582 | /** | |
583 | * xuartps_break_ctl - Based on the input ctl we have to start or stop | |
584 | * transmitting char breaks | |
585 | * @port: Handle to the uart port structure | |
586 | * @ctl: Value based on which start or stop decision is taken | |
489810a1 | 587 | */ |
61ec9016 JL |
588 | static void xuartps_break_ctl(struct uart_port *port, int ctl) |
589 | { | |
590 | unsigned int status; | |
591 | unsigned long flags; | |
592 | ||
593 | spin_lock_irqsave(&port->lock, flags); | |
594 | ||
595 | status = xuartps_readl(XUARTPS_CR_OFFSET); | |
596 | ||
597 | if (ctl == -1) | |
598 | xuartps_writel(XUARTPS_CR_STARTBRK | status, | |
599 | XUARTPS_CR_OFFSET); | |
600 | else { | |
601 | if ((status & XUARTPS_CR_STOPBRK) == 0) | |
602 | xuartps_writel(XUARTPS_CR_STOPBRK | status, | |
603 | XUARTPS_CR_OFFSET); | |
604 | } | |
605 | spin_unlock_irqrestore(&port->lock, flags); | |
606 | } | |
607 | ||
608 | /** | |
609 | * xuartps_set_termios - termios operations, handling data length, parity, | |
610 | * stop bits, flow control, baud rate | |
611 | * @port: Handle to the uart port structure | |
612 | * @termios: Handle to the input termios structure | |
613 | * @old: Values of the previously saved termios structure | |
489810a1 | 614 | */ |
61ec9016 JL |
615 | static void xuartps_set_termios(struct uart_port *port, |
616 | struct ktermios *termios, struct ktermios *old) | |
617 | { | |
618 | unsigned int cval = 0; | |
e6b39bfd | 619 | unsigned int baud, minbaud, maxbaud; |
61ec9016 JL |
620 | unsigned long flags; |
621 | unsigned int ctrl_reg, mode_reg; | |
622 | ||
623 | spin_lock_irqsave(&port->lock, flags); | |
624 | ||
625 | /* Empty the receive FIFO 1st before making changes */ | |
626 | while ((xuartps_readl(XUARTPS_SR_OFFSET) & | |
627 | XUARTPS_SR_RXEMPTY) != XUARTPS_SR_RXEMPTY) { | |
628 | xuartps_readl(XUARTPS_FIFO_OFFSET); | |
629 | } | |
630 | ||
631 | /* Disable the TX and RX to set baud rate */ | |
632 | xuartps_writel(xuartps_readl(XUARTPS_CR_OFFSET) | | |
633 | (XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS), | |
634 | XUARTPS_CR_OFFSET); | |
635 | ||
e6b39bfd SB |
636 | /* |
637 | * Min baud rate = 6bps and Max Baud Rate is 10Mbps for 100Mhz clk | |
638 | * min and max baud should be calculated here based on port->uartclk. | |
639 | * this way we get a valid baud and can safely call set_baud() | |
640 | */ | |
641 | minbaud = port->uartclk / ((XUARTPS_BDIV_MAX + 1) * XUARTPS_CD_MAX * 8); | |
642 | maxbaud = port->uartclk / (XUARTPS_BDIV_MIN + 1); | |
643 | baud = uart_get_baud_rate(port, termios, old, minbaud, maxbaud); | |
61ec9016 JL |
644 | baud = xuartps_set_baud_rate(port, baud); |
645 | if (tty_termios_baud_rate(termios)) | |
646 | tty_termios_encode_baud_rate(termios, baud, baud); | |
647 | ||
e555a211 | 648 | /* Update the per-port timeout. */ |
61ec9016 JL |
649 | uart_update_timeout(port, termios->c_cflag, baud); |
650 | ||
651 | /* Set TX/RX Reset */ | |
652 | xuartps_writel(xuartps_readl(XUARTPS_CR_OFFSET) | | |
653 | (XUARTPS_CR_TXRST | XUARTPS_CR_RXRST), | |
654 | XUARTPS_CR_OFFSET); | |
655 | ||
656 | ctrl_reg = xuartps_readl(XUARTPS_CR_OFFSET); | |
657 | ||
e555a211 SB |
658 | /* |
659 | * Clear the RX disable and TX disable bits and then set the TX enable | |
61ec9016 JL |
660 | * bit and RX enable bit to enable the transmitter and receiver. |
661 | */ | |
662 | xuartps_writel( | |
663 | (ctrl_reg & ~(XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS)) | |
664 | | (XUARTPS_CR_TX_EN | XUARTPS_CR_RX_EN), | |
665 | XUARTPS_CR_OFFSET); | |
666 | ||
85baf542 | 667 | xuartps_writel(rx_timeout, XUARTPS_RXTOUT_OFFSET); |
61ec9016 JL |
668 | |
669 | port->read_status_mask = XUARTPS_IXR_TXEMPTY | XUARTPS_IXR_RXTRIG | | |
670 | XUARTPS_IXR_OVERRUN | XUARTPS_IXR_TOUT; | |
671 | port->ignore_status_mask = 0; | |
672 | ||
673 | if (termios->c_iflag & INPCK) | |
674 | port->read_status_mask |= XUARTPS_IXR_PARITY | | |
675 | XUARTPS_IXR_FRAMING; | |
676 | ||
677 | if (termios->c_iflag & IGNPAR) | |
678 | port->ignore_status_mask |= XUARTPS_IXR_PARITY | | |
679 | XUARTPS_IXR_FRAMING | XUARTPS_IXR_OVERRUN; | |
680 | ||
681 | /* ignore all characters if CREAD is not set */ | |
682 | if ((termios->c_cflag & CREAD) == 0) | |
683 | port->ignore_status_mask |= XUARTPS_IXR_RXTRIG | | |
684 | XUARTPS_IXR_TOUT | XUARTPS_IXR_PARITY | | |
685 | XUARTPS_IXR_FRAMING | XUARTPS_IXR_OVERRUN; | |
686 | ||
687 | mode_reg = xuartps_readl(XUARTPS_MR_OFFSET); | |
688 | ||
689 | /* Handling Data Size */ | |
690 | switch (termios->c_cflag & CSIZE) { | |
691 | case CS6: | |
692 | cval |= XUARTPS_MR_CHARLEN_6_BIT; | |
693 | break; | |
694 | case CS7: | |
695 | cval |= XUARTPS_MR_CHARLEN_7_BIT; | |
696 | break; | |
697 | default: | |
698 | case CS8: | |
699 | cval |= XUARTPS_MR_CHARLEN_8_BIT; | |
700 | termios->c_cflag &= ~CSIZE; | |
701 | termios->c_cflag |= CS8; | |
702 | break; | |
703 | } | |
704 | ||
705 | /* Handling Parity and Stop Bits length */ | |
706 | if (termios->c_cflag & CSTOPB) | |
707 | cval |= XUARTPS_MR_STOPMODE_2_BIT; /* 2 STOP bits */ | |
708 | else | |
709 | cval |= XUARTPS_MR_STOPMODE_1_BIT; /* 1 STOP bit */ | |
710 | ||
711 | if (termios->c_cflag & PARENB) { | |
712 | /* Mark or Space parity */ | |
713 | if (termios->c_cflag & CMSPAR) { | |
714 | if (termios->c_cflag & PARODD) | |
715 | cval |= XUARTPS_MR_PARITY_MARK; | |
716 | else | |
717 | cval |= XUARTPS_MR_PARITY_SPACE; | |
e6b39bfd SB |
718 | } else { |
719 | if (termios->c_cflag & PARODD) | |
61ec9016 JL |
720 | cval |= XUARTPS_MR_PARITY_ODD; |
721 | else | |
722 | cval |= XUARTPS_MR_PARITY_EVEN; | |
e6b39bfd SB |
723 | } |
724 | } else { | |
61ec9016 | 725 | cval |= XUARTPS_MR_PARITY_NONE; |
e6b39bfd SB |
726 | } |
727 | cval |= mode_reg & 1; | |
728 | xuartps_writel(cval, XUARTPS_MR_OFFSET); | |
61ec9016 JL |
729 | |
730 | spin_unlock_irqrestore(&port->lock, flags); | |
731 | } | |
732 | ||
733 | /** | |
734 | * xuartps_startup - Called when an application opens a xuartps port | |
735 | * @port: Handle to the uart port structure | |
736 | * | |
e555a211 | 737 | * Return: 0 on success, negative errno otherwise |
489810a1 | 738 | */ |
61ec9016 JL |
739 | static int xuartps_startup(struct uart_port *port) |
740 | { | |
741 | unsigned int retval = 0, status = 0; | |
742 | ||
743 | retval = request_irq(port->irq, xuartps_isr, 0, XUARTPS_NAME, | |
744 | (void *)port); | |
745 | if (retval) | |
746 | return retval; | |
747 | ||
748 | /* Disable the TX and RX */ | |
749 | xuartps_writel(XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS, | |
750 | XUARTPS_CR_OFFSET); | |
751 | ||
752 | /* Set the Control Register with TX/RX Enable, TX/RX Reset, | |
753 | * no break chars. | |
754 | */ | |
755 | xuartps_writel(XUARTPS_CR_TXRST | XUARTPS_CR_RXRST, | |
756 | XUARTPS_CR_OFFSET); | |
757 | ||
758 | status = xuartps_readl(XUARTPS_CR_OFFSET); | |
759 | ||
760 | /* Clear the RX disable and TX disable bits and then set the TX enable | |
761 | * bit and RX enable bit to enable the transmitter and receiver. | |
762 | */ | |
763 | xuartps_writel((status & ~(XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS)) | |
764 | | (XUARTPS_CR_TX_EN | XUARTPS_CR_RX_EN | | |
765 | XUARTPS_CR_STOPBRK), XUARTPS_CR_OFFSET); | |
766 | ||
767 | /* Set the Mode Register with normal mode,8 data bits,1 stop bit, | |
768 | * no parity. | |
769 | */ | |
770 | xuartps_writel(XUARTPS_MR_CHMODE_NORM | XUARTPS_MR_STOPMODE_1_BIT | |
771 | | XUARTPS_MR_PARITY_NONE | XUARTPS_MR_CHARLEN_8_BIT, | |
772 | XUARTPS_MR_OFFSET); | |
773 | ||
85baf542 S |
774 | /* |
775 | * Set the RX FIFO Trigger level to use most of the FIFO, but it | |
776 | * can be tuned with a module parameter | |
777 | */ | |
778 | xuartps_writel(rx_trigger_level, XUARTPS_RXWM_OFFSET); | |
61ec9016 | 779 | |
85baf542 S |
780 | /* |
781 | * Receive Timeout register is enabled but it | |
782 | * can be tuned with a module parameter | |
783 | */ | |
784 | xuartps_writel(rx_timeout, XUARTPS_RXTOUT_OFFSET); | |
61ec9016 | 785 | |
855f6fd9 JL |
786 | /* Clear out any pending interrupts before enabling them */ |
787 | xuartps_writel(xuartps_readl(XUARTPS_ISR_OFFSET), XUARTPS_ISR_OFFSET); | |
61ec9016 JL |
788 | |
789 | /* Set the Interrupt Registers with desired interrupts */ | |
790 | xuartps_writel(XUARTPS_IXR_TXEMPTY | XUARTPS_IXR_PARITY | | |
791 | XUARTPS_IXR_FRAMING | XUARTPS_IXR_OVERRUN | | |
792 | XUARTPS_IXR_RXTRIG | XUARTPS_IXR_TOUT, XUARTPS_IER_OFFSET); | |
61ec9016 JL |
793 | |
794 | return retval; | |
795 | } | |
796 | ||
797 | /** | |
798 | * xuartps_shutdown - Called when an application closes a xuartps port | |
799 | * @port: Handle to the uart port structure | |
489810a1 | 800 | */ |
61ec9016 JL |
801 | static void xuartps_shutdown(struct uart_port *port) |
802 | { | |
803 | int status; | |
804 | ||
805 | /* Disable interrupts */ | |
806 | status = xuartps_readl(XUARTPS_IMR_OFFSET); | |
807 | xuartps_writel(status, XUARTPS_IDR_OFFSET); | |
808 | ||
809 | /* Disable the TX and RX */ | |
810 | xuartps_writel(XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS, | |
811 | XUARTPS_CR_OFFSET); | |
812 | free_irq(port->irq, port); | |
813 | } | |
814 | ||
815 | /** | |
816 | * xuartps_type - Set UART type to xuartps port | |
817 | * @port: Handle to the uart port structure | |
818 | * | |
489810a1 MS |
819 | * Return: string on success, NULL otherwise |
820 | */ | |
61ec9016 JL |
821 | static const char *xuartps_type(struct uart_port *port) |
822 | { | |
823 | return port->type == PORT_XUARTPS ? XUARTPS_NAME : NULL; | |
824 | } | |
825 | ||
826 | /** | |
827 | * xuartps_verify_port - Verify the port params | |
828 | * @port: Handle to the uart port structure | |
829 | * @ser: Handle to the structure whose members are compared | |
830 | * | |
e555a211 | 831 | * Return: 0 on success, negative errno otherwise. |
489810a1 | 832 | */ |
61ec9016 JL |
833 | static int xuartps_verify_port(struct uart_port *port, |
834 | struct serial_struct *ser) | |
835 | { | |
836 | if (ser->type != PORT_UNKNOWN && ser->type != PORT_XUARTPS) | |
837 | return -EINVAL; | |
838 | if (port->irq != ser->irq) | |
839 | return -EINVAL; | |
840 | if (ser->io_type != UPIO_MEM) | |
841 | return -EINVAL; | |
842 | if (port->iobase != ser->port) | |
843 | return -EINVAL; | |
844 | if (ser->hub6 != 0) | |
845 | return -EINVAL; | |
846 | return 0; | |
847 | } | |
848 | ||
849 | /** | |
850 | * xuartps_request_port - Claim the memory region attached to xuartps port, | |
851 | * called when the driver adds a xuartps port via | |
852 | * uart_add_one_port() | |
853 | * @port: Handle to the uart port structure | |
854 | * | |
e555a211 | 855 | * Return: 0 on success, negative errno otherwise. |
489810a1 | 856 | */ |
61ec9016 JL |
857 | static int xuartps_request_port(struct uart_port *port) |
858 | { | |
859 | if (!request_mem_region(port->mapbase, XUARTPS_REGISTER_SPACE, | |
860 | XUARTPS_NAME)) { | |
861 | return -ENOMEM; | |
862 | } | |
863 | ||
864 | port->membase = ioremap(port->mapbase, XUARTPS_REGISTER_SPACE); | |
865 | if (!port->membase) { | |
866 | dev_err(port->dev, "Unable to map registers\n"); | |
867 | release_mem_region(port->mapbase, XUARTPS_REGISTER_SPACE); | |
868 | return -ENOMEM; | |
869 | } | |
870 | return 0; | |
871 | } | |
872 | ||
873 | /** | |
e555a211 | 874 | * xuartps_release_port - Release UART port |
61ec9016 | 875 | * @port: Handle to the uart port structure |
e555a211 SB |
876 | * |
877 | * Release the memory region attached to a xuartps port. Called when the | |
878 | * driver removes a xuartps port via uart_remove_one_port(). | |
489810a1 | 879 | */ |
61ec9016 JL |
880 | static void xuartps_release_port(struct uart_port *port) |
881 | { | |
882 | release_mem_region(port->mapbase, XUARTPS_REGISTER_SPACE); | |
883 | iounmap(port->membase); | |
884 | port->membase = NULL; | |
885 | } | |
886 | ||
887 | /** | |
e555a211 | 888 | * xuartps_config_port - Configure UART port |
61ec9016 JL |
889 | * @port: Handle to the uart port structure |
890 | * @flags: If any | |
489810a1 | 891 | */ |
61ec9016 JL |
892 | static void xuartps_config_port(struct uart_port *port, int flags) |
893 | { | |
894 | if (flags & UART_CONFIG_TYPE && xuartps_request_port(port) == 0) | |
895 | port->type = PORT_XUARTPS; | |
896 | } | |
897 | ||
898 | /** | |
899 | * xuartps_get_mctrl - Get the modem control state | |
61ec9016 JL |
900 | * @port: Handle to the uart port structure |
901 | * | |
489810a1 MS |
902 | * Return: the modem control state |
903 | */ | |
61ec9016 JL |
904 | static unsigned int xuartps_get_mctrl(struct uart_port *port) |
905 | { | |
906 | return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR; | |
907 | } | |
908 | ||
909 | static void xuartps_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
910 | { | |
911 | /* N/A */ | |
912 | } | |
913 | ||
914 | static void xuartps_enable_ms(struct uart_port *port) | |
915 | { | |
916 | /* N/A */ | |
917 | } | |
918 | ||
6ee04c6c VL |
919 | #ifdef CONFIG_CONSOLE_POLL |
920 | static int xuartps_poll_get_char(struct uart_port *port) | |
921 | { | |
922 | u32 imr; | |
923 | int c; | |
924 | ||
925 | /* Disable all interrupts */ | |
926 | imr = xuartps_readl(XUARTPS_IMR_OFFSET); | |
927 | xuartps_writel(imr, XUARTPS_IDR_OFFSET); | |
928 | ||
929 | /* Check if FIFO is empty */ | |
930 | if (xuartps_readl(XUARTPS_SR_OFFSET) & XUARTPS_SR_RXEMPTY) | |
931 | c = NO_POLL_CHAR; | |
932 | else /* Read a character */ | |
933 | c = (unsigned char) xuartps_readl(XUARTPS_FIFO_OFFSET); | |
934 | ||
935 | /* Enable interrupts */ | |
936 | xuartps_writel(imr, XUARTPS_IER_OFFSET); | |
937 | ||
938 | return c; | |
939 | } | |
940 | ||
941 | static void xuartps_poll_put_char(struct uart_port *port, unsigned char c) | |
942 | { | |
943 | u32 imr; | |
944 | ||
945 | /* Disable all interrupts */ | |
946 | imr = xuartps_readl(XUARTPS_IMR_OFFSET); | |
947 | xuartps_writel(imr, XUARTPS_IDR_OFFSET); | |
948 | ||
949 | /* Wait until FIFO is empty */ | |
950 | while (!(xuartps_readl(XUARTPS_SR_OFFSET) & XUARTPS_SR_TXEMPTY)) | |
951 | cpu_relax(); | |
952 | ||
953 | /* Write a character */ | |
954 | xuartps_writel(c, XUARTPS_FIFO_OFFSET); | |
955 | ||
956 | /* Wait until FIFO is empty */ | |
957 | while (!(xuartps_readl(XUARTPS_SR_OFFSET) & XUARTPS_SR_TXEMPTY)) | |
958 | cpu_relax(); | |
959 | ||
960 | /* Enable interrupts */ | |
961 | xuartps_writel(imr, XUARTPS_IER_OFFSET); | |
962 | ||
963 | return; | |
964 | } | |
965 | #endif | |
966 | ||
61ec9016 JL |
967 | static struct uart_ops xuartps_ops = { |
968 | .set_mctrl = xuartps_set_mctrl, | |
969 | .get_mctrl = xuartps_get_mctrl, | |
970 | .enable_ms = xuartps_enable_ms, | |
e555a211 SB |
971 | .start_tx = xuartps_start_tx, |
972 | .stop_tx = xuartps_stop_tx, | |
973 | .stop_rx = xuartps_stop_rx, | |
974 | .tx_empty = xuartps_tx_empty, | |
975 | .break_ctl = xuartps_break_ctl, | |
976 | .set_termios = xuartps_set_termios, | |
977 | .startup = xuartps_startup, | |
978 | .shutdown = xuartps_shutdown, | |
979 | .type = xuartps_type, | |
980 | .verify_port = xuartps_verify_port, | |
981 | .request_port = xuartps_request_port, | |
982 | .release_port = xuartps_release_port, | |
983 | .config_port = xuartps_config_port, | |
6ee04c6c VL |
984 | #ifdef CONFIG_CONSOLE_POLL |
985 | .poll_get_char = xuartps_poll_get_char, | |
986 | .poll_put_char = xuartps_poll_put_char, | |
987 | #endif | |
61ec9016 JL |
988 | }; |
989 | ||
990 | static struct uart_port xuartps_port[2]; | |
991 | ||
992 | /** | |
e555a211 | 993 | * xuartps_get_port - Configure the port from the platform device resource info |
928e9263 MS |
994 | * @id: Port id |
995 | * | |
489810a1 MS |
996 | * Return: a pointer to a uart_port or NULL for failure |
997 | */ | |
928e9263 | 998 | static struct uart_port *xuartps_get_port(int id) |
61ec9016 JL |
999 | { |
1000 | struct uart_port *port; | |
61ec9016 | 1001 | |
928e9263 MS |
1002 | /* Try the given port id if failed use default method */ |
1003 | if (xuartps_port[id].mapbase != 0) { | |
1004 | /* Find the next unused port */ | |
1005 | for (id = 0; id < XUARTPS_NR_PORTS; id++) | |
1006 | if (xuartps_port[id].mapbase == 0) | |
1007 | break; | |
1008 | } | |
61ec9016 JL |
1009 | |
1010 | if (id >= XUARTPS_NR_PORTS) | |
1011 | return NULL; | |
1012 | ||
1013 | port = &xuartps_port[id]; | |
1014 | ||
1015 | /* At this point, we've got an empty uart_port struct, initialize it */ | |
1016 | spin_lock_init(&port->lock); | |
1017 | port->membase = NULL; | |
1018 | port->iobase = 1; /* mark port in use */ | |
1019 | port->irq = 0; | |
1020 | port->type = PORT_UNKNOWN; | |
1021 | port->iotype = UPIO_MEM32; | |
1022 | port->flags = UPF_BOOT_AUTOCONF; | |
1023 | port->ops = &xuartps_ops; | |
1024 | port->fifosize = XUARTPS_FIFO_SIZE; | |
1025 | port->line = id; | |
1026 | port->dev = NULL; | |
1027 | return port; | |
1028 | } | |
1029 | ||
61ec9016 JL |
1030 | #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE |
1031 | /** | |
1032 | * xuartps_console_wait_tx - Wait for the TX to be full | |
1033 | * @port: Handle to the uart port structure | |
489810a1 | 1034 | */ |
61ec9016 JL |
1035 | static void xuartps_console_wait_tx(struct uart_port *port) |
1036 | { | |
1037 | while ((xuartps_readl(XUARTPS_SR_OFFSET) & XUARTPS_SR_TXEMPTY) | |
1038 | != XUARTPS_SR_TXEMPTY) | |
1039 | barrier(); | |
1040 | } | |
1041 | ||
1042 | /** | |
1043 | * xuartps_console_putchar - write the character to the FIFO buffer | |
1044 | * @port: Handle to the uart port structure | |
1045 | * @ch: Character to be written | |
489810a1 | 1046 | */ |
61ec9016 JL |
1047 | static void xuartps_console_putchar(struct uart_port *port, int ch) |
1048 | { | |
1049 | xuartps_console_wait_tx(port); | |
1050 | xuartps_writel(ch, XUARTPS_FIFO_OFFSET); | |
1051 | } | |
1052 | ||
1053 | /** | |
1054 | * xuartps_console_write - perform write operation | |
489810a1 | 1055 | * @co: Console handle |
61ec9016 JL |
1056 | * @s: Pointer to character array |
1057 | * @count: No of characters | |
489810a1 | 1058 | */ |
61ec9016 JL |
1059 | static void xuartps_console_write(struct console *co, const char *s, |
1060 | unsigned int count) | |
1061 | { | |
1062 | struct uart_port *port = &xuartps_port[co->index]; | |
1063 | unsigned long flags; | |
d3755f5e | 1064 | unsigned int imr, ctrl; |
61ec9016 JL |
1065 | int locked = 1; |
1066 | ||
1067 | if (oops_in_progress) | |
1068 | locked = spin_trylock_irqsave(&port->lock, flags); | |
1069 | else | |
1070 | spin_lock_irqsave(&port->lock, flags); | |
1071 | ||
1072 | /* save and disable interrupt */ | |
1073 | imr = xuartps_readl(XUARTPS_IMR_OFFSET); | |
1074 | xuartps_writel(imr, XUARTPS_IDR_OFFSET); | |
1075 | ||
d3755f5e LPC |
1076 | /* |
1077 | * Make sure that the tx part is enabled. Set the TX enable bit and | |
1078 | * clear the TX disable bit to enable the transmitter. | |
1079 | */ | |
1080 | ctrl = xuartps_readl(XUARTPS_CR_OFFSET); | |
1081 | xuartps_writel((ctrl & ~XUARTPS_CR_TX_DIS) | XUARTPS_CR_TX_EN, | |
1082 | XUARTPS_CR_OFFSET); | |
1083 | ||
61ec9016 JL |
1084 | uart_console_write(port, s, count, xuartps_console_putchar); |
1085 | xuartps_console_wait_tx(port); | |
1086 | ||
d3755f5e LPC |
1087 | xuartps_writel(ctrl, XUARTPS_CR_OFFSET); |
1088 | ||
61ec9016 JL |
1089 | /* restore interrupt state, it seems like there may be a h/w bug |
1090 | * in that the interrupt enable register should not need to be | |
1091 | * written based on the data sheet | |
1092 | */ | |
1093 | xuartps_writel(~imr, XUARTPS_IDR_OFFSET); | |
1094 | xuartps_writel(imr, XUARTPS_IER_OFFSET); | |
1095 | ||
1096 | if (locked) | |
1097 | spin_unlock_irqrestore(&port->lock, flags); | |
1098 | } | |
1099 | ||
1100 | /** | |
1101 | * xuartps_console_setup - Initialize the uart to default config | |
1102 | * @co: Console handle | |
1103 | * @options: Initial settings of uart | |
1104 | * | |
e555a211 | 1105 | * Return: 0 on success, negative errno otherwise. |
489810a1 | 1106 | */ |
61ec9016 JL |
1107 | static int __init xuartps_console_setup(struct console *co, char *options) |
1108 | { | |
1109 | struct uart_port *port = &xuartps_port[co->index]; | |
1110 | int baud = 9600; | |
1111 | int bits = 8; | |
1112 | int parity = 'n'; | |
1113 | int flow = 'n'; | |
1114 | ||
1115 | if (co->index < 0 || co->index >= XUARTPS_NR_PORTS) | |
1116 | return -EINVAL; | |
1117 | ||
1118 | if (!port->mapbase) { | |
1119 | pr_debug("console on ttyPS%i not present\n", co->index); | |
1120 | return -ENODEV; | |
1121 | } | |
1122 | ||
1123 | if (options) | |
1124 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
1125 | ||
1126 | return uart_set_options(port, co, baud, parity, bits, flow); | |
1127 | } | |
1128 | ||
1129 | static struct uart_driver xuartps_uart_driver; | |
1130 | ||
1131 | static struct console xuartps_console = { | |
1132 | .name = XUARTPS_TTY_NAME, | |
1133 | .write = xuartps_console_write, | |
1134 | .device = uart_console_device, | |
1135 | .setup = xuartps_console_setup, | |
1136 | .flags = CON_PRINTBUFFER, | |
1137 | .index = -1, /* Specified on the cmdline (e.g. console=ttyPS ) */ | |
1138 | .data = &xuartps_uart_driver, | |
1139 | }; | |
1140 | ||
1141 | /** | |
1142 | * xuartps_console_init - Initialization call | |
1143 | * | |
e555a211 | 1144 | * Return: 0 on success, negative errno otherwise |
489810a1 | 1145 | */ |
61ec9016 JL |
1146 | static int __init xuartps_console_init(void) |
1147 | { | |
1148 | register_console(&xuartps_console); | |
1149 | return 0; | |
1150 | } | |
1151 | ||
1152 | console_initcall(xuartps_console_init); | |
1153 | ||
1154 | #endif /* CONFIG_SERIAL_XILINX_PS_UART_CONSOLE */ | |
1155 | ||
d3641f64 | 1156 | static struct uart_driver xuartps_uart_driver = { |
e555a211 SB |
1157 | .owner = THIS_MODULE, |
1158 | .driver_name = XUARTPS_NAME, | |
1159 | .dev_name = XUARTPS_TTY_NAME, | |
1160 | .major = XUARTPS_MAJOR, | |
1161 | .minor = XUARTPS_MINOR, | |
1162 | .nr = XUARTPS_NR_PORTS, | |
d3641f64 | 1163 | #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE |
e555a211 | 1164 | .cons = &xuartps_console, |
d3641f64 SB |
1165 | #endif |
1166 | }; | |
1167 | ||
4b47d9aa SB |
1168 | #ifdef CONFIG_PM_SLEEP |
1169 | /** | |
1170 | * xuartps_suspend - suspend event | |
1171 | * @device: Pointer to the device structure | |
1172 | * | |
489810a1 | 1173 | * Return: 0 |
4b47d9aa SB |
1174 | */ |
1175 | static int xuartps_suspend(struct device *device) | |
1176 | { | |
1177 | struct uart_port *port = dev_get_drvdata(device); | |
1178 | struct tty_struct *tty; | |
1179 | struct device *tty_dev; | |
1180 | int may_wake = 0; | |
1181 | ||
1182 | /* Get the tty which could be NULL so don't assume it's valid */ | |
1183 | tty = tty_port_tty_get(&port->state->port); | |
1184 | if (tty) { | |
1185 | tty_dev = tty->dev; | |
1186 | may_wake = device_may_wakeup(tty_dev); | |
1187 | tty_kref_put(tty); | |
1188 | } | |
1189 | ||
1190 | /* | |
1191 | * Call the API provided in serial_core.c file which handles | |
1192 | * the suspend. | |
1193 | */ | |
1194 | uart_suspend_port(&xuartps_uart_driver, port); | |
1195 | if (console_suspend_enabled && !may_wake) { | |
1196 | struct xuartps *xuartps = port->private_data; | |
1197 | ||
1198 | clk_disable(xuartps->refclk); | |
1199 | clk_disable(xuartps->aperclk); | |
1200 | } else { | |
1201 | unsigned long flags = 0; | |
1202 | ||
1203 | spin_lock_irqsave(&port->lock, flags); | |
1204 | /* Empty the receive FIFO 1st before making changes */ | |
1205 | while (!(xuartps_readl(XUARTPS_SR_OFFSET) & XUARTPS_SR_RXEMPTY)) | |
1206 | xuartps_readl(XUARTPS_FIFO_OFFSET); | |
1207 | /* set RX trigger level to 1 */ | |
1208 | xuartps_writel(1, XUARTPS_RXWM_OFFSET); | |
1209 | /* disable RX timeout interrups */ | |
1210 | xuartps_writel(XUARTPS_IXR_TOUT, XUARTPS_IDR_OFFSET); | |
1211 | spin_unlock_irqrestore(&port->lock, flags); | |
1212 | } | |
1213 | ||
1214 | return 0; | |
1215 | } | |
1216 | ||
1217 | /** | |
1218 | * xuartps_resume - Resume after a previous suspend | |
1219 | * @device: Pointer to the device structure | |
1220 | * | |
489810a1 | 1221 | * Return: 0 |
4b47d9aa SB |
1222 | */ |
1223 | static int xuartps_resume(struct device *device) | |
1224 | { | |
1225 | struct uart_port *port = dev_get_drvdata(device); | |
1226 | unsigned long flags = 0; | |
1227 | u32 ctrl_reg; | |
1228 | struct tty_struct *tty; | |
1229 | struct device *tty_dev; | |
1230 | int may_wake = 0; | |
1231 | ||
1232 | /* Get the tty which could be NULL so don't assume it's valid */ | |
1233 | tty = tty_port_tty_get(&port->state->port); | |
1234 | if (tty) { | |
1235 | tty_dev = tty->dev; | |
1236 | may_wake = device_may_wakeup(tty_dev); | |
1237 | tty_kref_put(tty); | |
1238 | } | |
1239 | ||
1240 | if (console_suspend_enabled && !may_wake) { | |
1241 | struct xuartps *xuartps = port->private_data; | |
1242 | ||
1243 | clk_enable(xuartps->aperclk); | |
1244 | clk_enable(xuartps->refclk); | |
1245 | ||
1246 | spin_lock_irqsave(&port->lock, flags); | |
1247 | ||
1248 | /* Set TX/RX Reset */ | |
1249 | xuartps_writel(xuartps_readl(XUARTPS_CR_OFFSET) | | |
1250 | (XUARTPS_CR_TXRST | XUARTPS_CR_RXRST), | |
1251 | XUARTPS_CR_OFFSET); | |
1252 | while (xuartps_readl(XUARTPS_CR_OFFSET) & | |
1253 | (XUARTPS_CR_TXRST | XUARTPS_CR_RXRST)) | |
1254 | cpu_relax(); | |
1255 | ||
1256 | /* restore rx timeout value */ | |
1257 | xuartps_writel(rx_timeout, XUARTPS_RXTOUT_OFFSET); | |
1258 | /* Enable Tx/Rx */ | |
1259 | ctrl_reg = xuartps_readl(XUARTPS_CR_OFFSET); | |
1260 | xuartps_writel( | |
1261 | (ctrl_reg & ~(XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS)) | | |
1262 | (XUARTPS_CR_TX_EN | XUARTPS_CR_RX_EN), | |
1263 | XUARTPS_CR_OFFSET); | |
1264 | ||
1265 | spin_unlock_irqrestore(&port->lock, flags); | |
1266 | } else { | |
1267 | spin_lock_irqsave(&port->lock, flags); | |
1268 | /* restore original rx trigger level */ | |
1269 | xuartps_writel(rx_trigger_level, XUARTPS_RXWM_OFFSET); | |
1270 | /* enable RX timeout interrupt */ | |
1271 | xuartps_writel(XUARTPS_IXR_TOUT, XUARTPS_IER_OFFSET); | |
1272 | spin_unlock_irqrestore(&port->lock, flags); | |
1273 | } | |
1274 | ||
1275 | return uart_resume_port(&xuartps_uart_driver, port); | |
1276 | } | |
1277 | #endif /* ! CONFIG_PM_SLEEP */ | |
1278 | ||
1279 | static SIMPLE_DEV_PM_OPS(xuartps_dev_pm_ops, xuartps_suspend, xuartps_resume); | |
1280 | ||
61ec9016 JL |
1281 | /** |
1282 | * xuartps_probe - Platform driver probe | |
1283 | * @pdev: Pointer to the platform device structure | |
1284 | * | |
e555a211 | 1285 | * Return: 0 on success, negative errno otherwise |
489810a1 | 1286 | */ |
9671f099 | 1287 | static int xuartps_probe(struct platform_device *pdev) |
61ec9016 | 1288 | { |
928e9263 | 1289 | int rc, id; |
61ec9016 JL |
1290 | struct uart_port *port; |
1291 | struct resource *res, *res2; | |
30e1e285 | 1292 | struct xuartps *xuartps_data; |
61ec9016 | 1293 | |
c03cae17 SB |
1294 | xuartps_data = devm_kzalloc(&pdev->dev, sizeof(*xuartps_data), |
1295 | GFP_KERNEL); | |
30e1e285 SB |
1296 | if (!xuartps_data) |
1297 | return -ENOMEM; | |
1298 | ||
991fc259 | 1299 | xuartps_data->aperclk = devm_clk_get(&pdev->dev, "aper_clk"); |
30e1e285 SB |
1300 | if (IS_ERR(xuartps_data->aperclk)) { |
1301 | dev_err(&pdev->dev, "aper_clk clock not found.\n"); | |
c03cae17 | 1302 | return PTR_ERR(xuartps_data->aperclk); |
30e1e285 | 1303 | } |
991fc259 | 1304 | xuartps_data->refclk = devm_clk_get(&pdev->dev, "ref_clk"); |
30e1e285 SB |
1305 | if (IS_ERR(xuartps_data->refclk)) { |
1306 | dev_err(&pdev->dev, "ref_clk clock not found.\n"); | |
c03cae17 | 1307 | return PTR_ERR(xuartps_data->refclk); |
2326669c JC |
1308 | } |
1309 | ||
30e1e285 SB |
1310 | rc = clk_prepare_enable(xuartps_data->aperclk); |
1311 | if (rc) { | |
1312 | dev_err(&pdev->dev, "Unable to enable APER clock.\n"); | |
c03cae17 | 1313 | return rc; |
30e1e285 SB |
1314 | } |
1315 | rc = clk_prepare_enable(xuartps_data->refclk); | |
2326669c | 1316 | if (rc) { |
30e1e285 SB |
1317 | dev_err(&pdev->dev, "Unable to enable device clock.\n"); |
1318 | goto err_out_clk_dis_aper; | |
61ec9016 JL |
1319 | } |
1320 | ||
1321 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
30e1e285 SB |
1322 | if (!res) { |
1323 | rc = -ENODEV; | |
1324 | goto err_out_clk_disable; | |
1325 | } | |
61ec9016 JL |
1326 | |
1327 | res2 = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
30e1e285 SB |
1328 | if (!res2) { |
1329 | rc = -ENODEV; | |
1330 | goto err_out_clk_disable; | |
1331 | } | |
61ec9016 | 1332 | |
7ac57347 | 1333 | #ifdef CONFIG_COMMON_CLK |
c4b0510c SB |
1334 | xuartps_data->clk_rate_change_nb.notifier_call = |
1335 | xuartps_clk_notifier_cb; | |
1336 | if (clk_notifier_register(xuartps_data->refclk, | |
1337 | &xuartps_data->clk_rate_change_nb)) | |
1338 | dev_warn(&pdev->dev, "Unable to register clock notifier.\n"); | |
7ac57347 | 1339 | #endif |
928e9263 MS |
1340 | /* Look for a serialN alias */ |
1341 | id = of_alias_get_id(pdev->dev.of_node, "serial"); | |
1342 | if (id < 0) | |
1343 | id = 0; | |
c4b0510c | 1344 | |
61ec9016 | 1345 | /* Initialize the port structure */ |
928e9263 | 1346 | port = xuartps_get_port(id); |
61ec9016 JL |
1347 | |
1348 | if (!port) { | |
1349 | dev_err(&pdev->dev, "Cannot get uart_port structure\n"); | |
30e1e285 | 1350 | rc = -ENODEV; |
c4b0510c | 1351 | goto err_out_notif_unreg; |
61ec9016 JL |
1352 | } else { |
1353 | /* Register the port. | |
1354 | * This function also registers this device with the tty layer | |
1355 | * and triggers invocation of the config_port() entry point. | |
1356 | */ | |
1357 | port->mapbase = res->start; | |
1358 | port->irq = res2->start; | |
1359 | port->dev = &pdev->dev; | |
30e1e285 SB |
1360 | port->uartclk = clk_get_rate(xuartps_data->refclk); |
1361 | port->private_data = xuartps_data; | |
c4b0510c | 1362 | xuartps_data->port = port; |
696faedd | 1363 | platform_set_drvdata(pdev, port); |
61ec9016 JL |
1364 | rc = uart_add_one_port(&xuartps_uart_driver, port); |
1365 | if (rc) { | |
1366 | dev_err(&pdev->dev, | |
1367 | "uart_add_one_port() failed; err=%i\n", rc); | |
c4b0510c | 1368 | goto err_out_notif_unreg; |
61ec9016 JL |
1369 | } |
1370 | return 0; | |
1371 | } | |
30e1e285 | 1372 | |
c4b0510c | 1373 | err_out_notif_unreg: |
7ac57347 | 1374 | #ifdef CONFIG_COMMON_CLK |
c4b0510c SB |
1375 | clk_notifier_unregister(xuartps_data->refclk, |
1376 | &xuartps_data->clk_rate_change_nb); | |
7ac57347 | 1377 | #endif |
30e1e285 SB |
1378 | err_out_clk_disable: |
1379 | clk_disable_unprepare(xuartps_data->refclk); | |
1380 | err_out_clk_dis_aper: | |
1381 | clk_disable_unprepare(xuartps_data->aperclk); | |
30e1e285 SB |
1382 | |
1383 | return rc; | |
61ec9016 JL |
1384 | } |
1385 | ||
1386 | /** | |
1387 | * xuartps_remove - called when the platform driver is unregistered | |
1388 | * @pdev: Pointer to the platform device structure | |
1389 | * | |
e555a211 | 1390 | * Return: 0 on success, negative errno otherwise |
489810a1 | 1391 | */ |
ae8d8a14 | 1392 | static int xuartps_remove(struct platform_device *pdev) |
61ec9016 | 1393 | { |
696faedd | 1394 | struct uart_port *port = platform_get_drvdata(pdev); |
30e1e285 | 1395 | struct xuartps *xuartps_data = port->private_data; |
2326669c | 1396 | int rc; |
61ec9016 JL |
1397 | |
1398 | /* Remove the xuartps port from the serial core */ | |
7ac57347 | 1399 | #ifdef CONFIG_COMMON_CLK |
c4b0510c SB |
1400 | clk_notifier_unregister(xuartps_data->refclk, |
1401 | &xuartps_data->clk_rate_change_nb); | |
7ac57347 | 1402 | #endif |
2326669c | 1403 | rc = uart_remove_one_port(&xuartps_uart_driver, port); |
2326669c | 1404 | port->mapbase = 0; |
30e1e285 SB |
1405 | clk_disable_unprepare(xuartps_data->refclk); |
1406 | clk_disable_unprepare(xuartps_data->aperclk); | |
61ec9016 JL |
1407 | return rc; |
1408 | } | |
1409 | ||
61ec9016 | 1410 | /* Match table for of_platform binding */ |
de88b340 | 1411 | static struct of_device_id xuartps_of_match[] = { |
61ec9016 JL |
1412 | { .compatible = "xlnx,xuartps", }, |
1413 | {} | |
1414 | }; | |
1415 | MODULE_DEVICE_TABLE(of, xuartps_of_match); | |
61ec9016 JL |
1416 | |
1417 | static struct platform_driver xuartps_platform_driver = { | |
e555a211 SB |
1418 | .probe = xuartps_probe, |
1419 | .remove = xuartps_remove, | |
61ec9016 JL |
1420 | .driver = { |
1421 | .owner = THIS_MODULE, | |
e555a211 | 1422 | .name = XUARTPS_NAME, |
61ec9016 | 1423 | .of_match_table = xuartps_of_match, |
4b47d9aa | 1424 | .pm = &xuartps_dev_pm_ops, |
61ec9016 JL |
1425 | }, |
1426 | }; | |
1427 | ||
61ec9016 JL |
1428 | static int __init xuartps_init(void) |
1429 | { | |
1430 | int retval = 0; | |
1431 | ||
1432 | /* Register the xuartps driver with the serial core */ | |
1433 | retval = uart_register_driver(&xuartps_uart_driver); | |
1434 | if (retval) | |
1435 | return retval; | |
1436 | ||
1437 | /* Register the platform driver */ | |
1438 | retval = platform_driver_register(&xuartps_platform_driver); | |
1439 | if (retval) | |
1440 | uart_unregister_driver(&xuartps_uart_driver); | |
1441 | ||
1442 | return retval; | |
1443 | } | |
1444 | ||
61ec9016 JL |
1445 | static void __exit xuartps_exit(void) |
1446 | { | |
61ec9016 JL |
1447 | /* Unregister the platform driver */ |
1448 | platform_driver_unregister(&xuartps_platform_driver); | |
1449 | ||
1450 | /* Unregister the xuartps driver */ | |
1451 | uart_unregister_driver(&xuartps_uart_driver); | |
1452 | } | |
1453 | ||
1454 | module_init(xuartps_init); | |
1455 | module_exit(xuartps_exit); | |
1456 | ||
1457 | MODULE_DESCRIPTION("Driver for PS UART"); | |
1458 | MODULE_AUTHOR("Xilinx Inc."); | |
1459 | MODULE_LICENSE("GPL"); |